diff --git a/.github/workflows/compile.yml b/.github/workflows/compile.yml new file mode 100644 index 00000000..e9228cb2 --- /dev/null +++ b/.github/workflows/compile.yml @@ -0,0 +1,49 @@ +name: CI + +on: [push] + +env: + doc_name: cheri-architecture + +jobs: + build: + # TODO: Run on Docker image that has latex pre-installed? + runs-on: [ubuntu-18.04] + steps: + - uses: actions/checkout@v1 + - name: Install latex + run: sudo apt-get install -y --no-install-recommends make texlive-plain-generic texlive-latex-base texlive-latex-recommended texlive-latex-extra texlive-science texlive-fonts-recommended texlive-fonts-extra texlive-bibtex-extra texlive-extra-utils biber latexmk + - name: Build document + run: make + - name: Upload artifact + + uses: actions/upload-artifact@master + with: + name: ${{ env.doc_name }}.pdf + path: ${{ env.doc_name }}.pdf + + - name: Get current date + id: date + run: echo "::set-output name=date::$(date +'%Y%m%d')" + - name: Create Release + id: create_release + uses: actions/create-release@v1 + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + with: + tag_name: draft-${{ steps.date.outputs.date }} + release_name: Draft release ${{ steps.date.outputs.date }} + body: Latest snapshot (${{ github.sha }}) + draft: true + prerelease: true + - name: Upload Release Asset + id: upload-release-asset + uses: actions/upload-release-asset@v1 + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + with: + upload_url: ${{ steps.create_release.outputs.upload_url }} # This pulls from the CREATE RELEASE step above, referencing it's ID to get its outputs object, which include a `upload_url`. See this blog post for more info: https://jasonet.co/posts/new-features-of-github-actions/#passing-data-to-future-steps + asset_path: ./${{ env.doc_name }}.pdf + asset_name: ${{ env.doc_name }}-snapshot-${{ github.sha }}.pdf + asset_content_type: application/pdf + diff --git a/.github/workflows/remove-old-artifacts.yml b/.github/workflows/remove-old-artifacts.yml new file mode 100644 index 00000000..ab04bac2 --- /dev/null +++ b/.github/workflows/remove-old-artifacts.yml @@ -0,0 +1,20 @@ +name: Remove old artifacts + +on: + workflow_dispatch: + schedule: + # Every day at 1am + - cron: '0 1 * * *' + +jobs: + remove-old-artifacts: + runs-on: ubuntu-latest + timeout-minutes: 10 + + steps: + - name: Remove old artifacts + uses: c-hive/gha-remove-artifacts@v1 + with: + age: '1 month' + skip-tags: true + skip-recent: 10 diff --git a/.gitignore b/.gitignore new file mode 100644 index 00000000..d0807001 --- /dev/null +++ b/.gitignore @@ -0,0 +1,21 @@ +/build +/cheri-architecture.aux +/cheri-architecture.bbl +/cheri-architecture.bcf +/cheri-architecture.blg +/cheri-architecture.fdb_latexmk +/cheri-architecture.fls +/cheri-architecture.glg +/cheri-architecture.glo +/cheri-architecture.gls +/cheri-architecture.ist +/cheri-architecture.log +/cheri-architecture.out +/cheri-architecture.pdf +/cheri-architecture.run.xml +/cheri-architecture.toc +/fig-*.fls +/fig-*.pdf + +/sail-cheri-riscv +/sail-cheri-mips diff --git a/20200816-cheri-timeline.pdf b/20200816-cheri-timeline.pdf new file mode 100644 index 00000000..49ee79ec Binary files /dev/null and b/20200816-cheri-timeline.pdf differ diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..dd316a2a --- /dev/null +++ b/Makefile @@ -0,0 +1,168 @@ +TARGET=cheri-architecture.pdf +PREVEOUS=../branches/20150624-cheri-architecture-1-13 + +SAIL_LATEX_MIPS_DIR=sail_latex_mips +SAIL_LATEX_RISCV_DIR=sail_latex_riscv + +SOURCES=$(wildcard *.tex insn-mips/*.tex insn-riscv/*.tex $(SAIL_LATEX_MIPS_DIR)/*.tex $(SAIL_LATEX_RISCV_DIR)/*.tex) cheri.bib +TEXSTYLES=$(wildcard *.sty) +DIFFDIR=diff +DIFFTEX=$(SOURCES:%=${DIFFDIR}/%) +DIFFPARAM=--type=UNDERLINE --packages=amsmath,hyperref --math-markup=1 + +TIKZFIGURES=fig-representable-regions.pdf fig-sentry-plt.pdf fig-type-token.pdf +FIGSOURCES= \ + fig-cheri-high-level.pdf \ + fig-pointer-provenance.pdf \ + fig-cheri-high-level.pdf \ + $(TIKZFIGURES) + +V?=0 +ifeq ($(V),0) +INTERACTION=batchmode +TEXLOGANALYSER_FLAGS=-w +else +INTERACTION=nonstopmode +# Also include page numbers to make it easier to find what caused the warning +TEXLOGANALYSER_FLAGS=-w -n +endif + +LATEXMK_COMMON_FLAGS=-bibtex -pdf +PDFLATEX_FLAGS=-file-line-error -halt-on-error -interaction=$(INTERACTION) + +.PHONY: all +all: ${TARGET} + +# The texloganalyser tool can be used to find all warning messages in the latex +# logfile which is useful when using interaction=batchmode. There is also +# a python package pydflatex that does the same thing (but with colours). +# Howver, texloganalyser is included by default in some TeX distributions so +# prefer that one. +# TODO: fix the broken sail hyperrefs so we don't have to filter the out. +${TARGET}: ${SOURCES} ${FIGSOURCES} + latexmk $(LATEXMK_COMMON_FLAGS) cheri-architecture.tex $(PDFLATEX_FLAGS); ret=$$?; \ + if command -v texloganalyser >/dev/null 2>/dev/null; then \ + texloganalyser $(TEXLOGANALYSER_FLAGS) build/cheri-architecture.log; \ + fi; exit $$ret + +$(TIKZFIGURES): %.pdf: %.tex Makefile + latexmk $(LATEXMK_COMMON_FLAGS) $(PDFLATEX_FLAGS) $< + +.PHONY: figures +figures: $(TIKZFIGURES) + +.PHONY: quick +quick: + pdflatex cheri-architecture.tex $(PDFLATEX_FLAGS) + @(echo "pdflatex only run once so build may be incomplete") + +.PHONY: diff +diff: ${PREVEOUS} diffdir ${DIFFDIR}/${TARGET} + +${PREVEOUS}: + @((echo "ERROR: the preveous version directory (" ${PREVEOUS} ") does not exist." ; echo "Set the PREVEOUS variable in the Makefile.") && false) + +.PHONY: diffdir +diffdir: + @(test -d ${DIFFDIR} || mkdir ${DIFFDIR}) + +${DIFFDIR}/$(TARGET): $(DIFFTEX) + cp Makefile ${DIFFDIR}/ + cp ${FIGSOURCES} ${DIFFDIR}/ + cp ${TEXSTYLES} ${DIFFDIR}/ + make -C ${DIFFDIR} + @(echo "diff of between "${PREVEOUS}" and this version is now in "${DIFFDIR}"/"${TARGET}) + +${DIFFDIR}/preamble.tex: preamble.tex + cp preamble.tex ${DIFFDIR} + +${DIFFDIR}/%.tex: %.tex + @(echo '\DIFaddbegin' > ${DIFFDIR}/diffbegin) + @(echo '\DIFaddend' > ${DIFFDIR}/diffend) + (if [ -f ${PREVEOUS}/$*.tex ]; then latexdiff ${DIFFPARAM} ${PREVEOUS}/$*.tex $*.tex > ${DIFFDIR}/$*.tex; else cat ${DIFFDIR}/diffbegin $*.tex ${DIFFDIR}/diffend > ${DIFFDIR}/$*.tex; fi) + +${DIFFDIR}/%.bib: %.bib + cp $*.bib ${DIFFDIR}/ + + +# The sed commands require GNU sed +ifeq ($(shell uname -s),Linux) +SED?=sed +else +SED?=gsed +endif + +# Work around `find: fts_read: Invalid argument` on macOS +ifeq ($(shell uname -s),Darwin) +FIND?=gfind +else +FIND?=find +endif + +$(SAIL_LATEX_MIPS_DIR) $(SAIL_LATEX_RISCV_DIR): %: + mkdir -p $@ + +sail-cheri-mips: + git clone https://github.com/CTSRD-CHERI/sail-cheri-mips + +SAIL_CHERI_MIPS_DIR?=sail-cheri-mips +sail-cheri-mips-latex: $(SAIL_CHERI_MIPS_DIR) | $(SAIL_LATEX_MIPS_DIR) + rm -rf $(SAIL_CHERI_MIPS_DIR)/cheri/$(SAIL_LATEX_MIPS_DIR) + $(MAKE) -C $(SAIL_CHERI_MIPS_DIR)/cheri latex_128 + chmod -R +w $(SAIL_LATEX_MIPS_DIR) + rm -rf $(SAIL_LATEX_MIPS_DIR) + cp -r $(SAIL_CHERI_MIPS_DIR)/cheri/$(SAIL_LATEX_MIPS_DIR) . + $(FIND) $(SAIL_LATEX_MIPS_DIR) -type f -name 'fcl*zexecute*.tex' -exec $(SED) -i -e '1d; 2{/^{$$/d}; $$d; s/^ //;' {} + + touch $(SAIL_LATEX_MIPS_DIR)/0GENERATED_FILES_DO_NOT_EDIT + touch $(SAIL_LATEX_MIPS_DIR)/zGENERATED_FILES_DO_NOT_EDIT + $(FIND) $(SAIL_LATEX_MIPS_DIR) -type f -exec chmod -w {} + + + +sail-cheri-riscv: + git clone --recurse-submodules https://github.com/CTSRD-CHERI/sail-cheri-riscv + +SAIL_CHERI_RISCV_DIR?=sail-cheri-riscv +sail-cheri-riscv-latex: $(SAIL_CHERI_RISCV_DIR) | $(SAIL_LATEX_RISCV_DIR) + rm -rf $(SAIL_CHERI_RISCV_DIR)/$(SAIL_LATEX_RISCV_DIR) + $(MAKE) -C $(SAIL_CHERI_RISCV_DIR) latex + chmod -R +w $(SAIL_LATEX_RISCV_DIR) + rm -rf $(SAIL_LATEX_RISCV_DIR) + cp -r $(SAIL_CHERI_RISCV_DIR)/$(SAIL_LATEX_RISCV_DIR) $(SAIL_LATEX_RISCV_DIR) + $(FIND) $(SAIL_LATEX_RISCV_DIR) -type f -name 'fcl*zexecute*.tex' -exec $(SED) -i -e '1d; 2{/^{$$/d}; $$d; s/^ //;' {} + + touch $(SAIL_LATEX_RISCV_DIR)/0GENERATED_FILES_DO_NOT_EDIT + touch $(SAIL_LATEX_RISCV_DIR)/zGENERATED_FILES_DO_NOT_EDIT + $(FIND) $(SAIL_LATEX_RISCV_DIR) -type f -exec chmod -w {} + + + +update-sail-defs-mips: $(SAIL_CHERI_MIPS_DIR) + git -C $(SAIL_CHERI_MIPS_DIR) pull --rebase + git -C $(SAIL_CHERI_MIPS_DIR) submodule update --init --recursive + $(MAKE) sail-cheri-mips-latex + +update-sail-defs-riscv: $(SAIL_CHERI_RISCV_DIR) + git -C $(SAIL_CHERI_RISCV_DIR) pull --rebase + git -C $(SAIL_CHERI_RISCV_DIR) submodule update --init --recursive + $(MAKE) sail-cheri-riscv-latex + +update-sail-defs: update-sail-defs-mips update-sail-defs-riscv + +.PHONY: clean update-sail-defs sail-cheri-riscv-latex sail-cheri-mips-latex update-sail-defs-riscv update-sail-defs-mips +clean: + latexmk -C $(LATEXMK_COMMON_FLAGS) cheri-architecture.tex + latexmk -C $(LATEXMK_COMMON_FLAGS) fig-*.tex + rm -f $(TARGET) $(TIKZFIGURES) + rm -rf $(DIFFDIR) + +cheri-sorted.bib: cheri.bib bib-sorting.conf + biber --tool $< --sortcase=false --strip-comments --sortdebug --isbn13 --isbn-normalise --fixinits \ + --output_indent=4 --output_fieldcase=lower --sortlocale=en_GB \ + --configfile=bib-sorting.conf --validate-config --output-file=$@ + + +.PHONY: check-bibliography check-bibliography-strict +check-bibliography: + # For more detailed output add --debug + biber --tool cheri.bib + +check-bibliography-strict: + biber --tool --validate-datamodel cheri.bib | grep -v "Missing mandatory field 'editor'" | grep -v "is not an integer" diff --git a/abstract.tex b/abstract.tex new file mode 100644 index 00000000..f625719c --- /dev/null +++ b/abstract.tex @@ -0,0 +1,63 @@ +\section*{Abstract} + +This technical report describes CHERI ISAv8, the eighth version of the +CHERI architecture +being developed by SRI International and the University of Cambridge. +This design captures ten years of research, development, experimentation, +refinement, formal analysis, and validation through hardware and software +implementation. + +CHERI introduces an architecture-neutral capability-based protection +model, which has been instantiated in various commodity base architectures +to give CHERI-MIPS, +CHERI-RISC-V, Arm's prototype Morello architecture, and (sketched) +CHERI-x86-64. +It enables software +to efficiently implement fine-grained memory protection and scalable software +compartmentalization, by providing strong, non-probabilistic, efficient +mechanisms to support the principles of least privilege and intentional use +in the execution of software at multiple levels of abstraction, preventing and +mitigating vulnerabilities. +Design goals include incremental adoptability from current ISAs and +software stacks, low performance overhead for memory protection, significant +performance improvements for software compartmentalization, formal grounding, +and programmer-friendly underpinnings. + +CHERI blends traditional paged virtual memory with an +in-address-space capability model that includes capability values in registers, +capability instructions, and tagged memory to enforce capability integrity. +This hybrid approach, inspired by the Capsicum security model, addresses the performance and robustness issues that arise +when trying to express more secure programming models, minimising +privilege, above conventional architectures that provide only +MMU-based protection. +CHERI builds on the C-language fat-pointer literature: its capabilities can +describe fine-grained regions of memory, and can be substituted for data or +code pointers in generated code, protecting data and improving +control-flow robustness. +Strong capability integrity and monotonicity properties allow CHERI +to express a variety of protection idioms, from enforcing valid C-language +pointer provenance and bounds checking to implementing the isolation and +controlled communication structures required for software +compartmentalization. + +CHERI's hybrid approach allows incremental adoption of capability-oriented design: +critical components can be ported and recompiled to use capabilities throughout, +providing fine-grain memory protection, or be largely unmodified but encapsulated in ways that permit +only controlled interaction. +Potential early deployment scenarios include low-level software Trusted Computing +Bases (TCBs) such as separation kernels, hypervisors, and operating-system +kernels, userspace TCBs such as language runtimes and web browsers, +and particularly high-risk +software libraries such as data compression, protocol parsing, and image +processing (which are concentrations of both complex and historically +vulnerability-prone code exposed to untrustworthy data sources). + +CHERI ISAv8 is a substantial enhancement to prior ISA versions. +Capability compression is now part of the abstract model. +Both 32-bit and 64-bit architectural address sizes are supported. +Various previously experimental features, such as sentry capabilities and +CHERI-RISC-V, are now considered mature. +We have defined a number of new temporal memory-safety acceleration features +including MMU assistance for a load-side-barrier revocation model. +We have added a chapter on practical CHERI microarchitecture. +CHERI ISAv8 is synchronized with Arm Morello. diff --git a/acknowledgments.tex b/acknowledgments.tex new file mode 100644 index 00000000..f12f51d7 --- /dev/null +++ b/acknowledgments.tex @@ -0,0 +1,143 @@ +\section*{Acknowledgments} + +\vspace{-0.2cm} + +The authors of this report thank members of the CTSRD, MRC2, ECATS, +CIFV, and REMS teams, our past and current research collaborators at SRI and +Cambridge, as well as colleagues at other institutions who have provided +invaluable feedback and continuing support throughout this work: + +\medskip + +\begin{small} +\noindent\begin{autogrid}{4} +Sam Ainsworth \\ +Ross J. Anderson \\ +Ruben Ayrapetyan \\ +Hadrien Barral \\ +Thomas Bauereiss \\ +Stuart Biles \\ +Andrew Bivin \\ +Peter Blandford-Baker \\ +Matthias Boettcher \\ +David Brazdil \\ +Reuben Broadfoot \\ +Kevin Brodsky \\ +Ruslan Bukin \\ +Brian Campbell \\ +Gregory Chadwick \\ +Serban Constantinescu \\ +Chris Dalton \\ +Nirav Dave \\ +Dominique Devriese \\ +Mike Dodson \\ +Lawrence Esswood \\ +Jonas Fiala \\ +Wedson Filho \\ +Anthony Fox \\ +Paul J. Fox \\ +Franz Fuchs \\ +Ivan Gomes Ribeiro \\ +Paul Gotch \\ +Tom Grocutt \\ +Khilan Gudka \\ +Brett Gutstein \\ +Jong Hun Han \\ +Andy Hopper \\ +Alex Horsman \\ +Timothy Jones \\ +Asif Khan \\ +Myron King \\ +Joe Kiniry \\ +Chris Kitching \\ +Wojciech Koszek \\ +Robert Kovacsics \\ +Karthik Muthusamy \\ +Patrick Lincoln \\ +Marno van der Maas \\ +Anil Madhavapeddy \\ +Ilias Marinos \\ +Tim Marsland \\ +Ed Maste \\ +Alfredo Mazzinghi \\ +Kayvan Memarian \\ +Dejan Milojicic \\ +Andrew W. Moore \\ +Will Morland \\ +Alan Mujumdar \\ +Prashanth Mundkur \\ +Edward Napierala \\ +Philip Paeps \\ +Lucian Paul-Trifu \\ +Austin Roach \\ +Colin Rothwell \\ +John Rushby \\ +Hassen Saidi \\ +Hans Petter Selasky \\ +Andrew Scull \\ +Muhammad Shahbaz \\ +Bradley Smith \\ +Lee Smith \\ +Ian Stark \\ +Ramy Tadros \\ +Andrew Turner \\ +Richard Uhler \\ +Munraj Vadera \\ +Jacques Vidrine \\ +Hugo Vincent \\ +Philip Withnall \\ +Bjoern A. Zeeb \\ +\end{autogrid} +\end{small} + +\medskip + +\noindent +The CTSRD team also thanks past and current members of its external oversight +group: + +\medskip + +\begin{small} +\noindent\begin{autogrid}{5} +Lee Badger \\ +Simon Cooper \\ +Rance DeLong \\ +Jeremy Epstein \\ +Virgil Gligor \\ +Li Gong \\ +Mike Gordon \\ +Steven Hand \\ +Andrew Herbert \\ +Warren A. Hunt Jr. \\ +Doug Maughan \\ +Greg Morrisett \\ +Brian Randell \\ +Kenneth F. Shotting \\ +Joe Stoy \\ +Tom Van Vleck \\ +Samuel M. Weber \\ +\end{autogrid} +\end{small} + +\medskip + +\noindent +We would also like to acknowledge the late David Wheeler and Paul Karger, +whose conversations with the authors about the CAP computer and capability +systems contributed to our thinking, and whose prior work provided +considerable inspiration. + +\medskip + +\noindent +Finally, we are grateful to Howie Shrobe, MIT professor and past DARPA CRASH +and MRC program manager, who offered both technical insight and support +throughout this work. We are also grateful to Robert Laddaga, Stu Wagner, and +Jonathan Smith, who succeeded Howie in overseeing the CRASH program, John +Launchbury (DARPA I2O office director), Dale Waters (DARPA AEO office +director), Linton Salmon (DARPA SSITH program manager), Keith Rebello (DARPA +SSITH program manager), Daniel Adams and +Laurisa Goergen (DARPA I2O SETAs supporting the CRASH and MRC programs), +Marnie Dunsmore and John Marsh (DARPA MTO SETAs supporting the SSITH +program), John Goodacre (UKRI), and Georgios Papadakis (UKRI). diff --git a/app-cheri-128.tex b/app-cheri-128.tex new file mode 100644 index 00000000..4a9f09d8 --- /dev/null +++ b/app-cheri-128.tex @@ -0,0 +1,498 @@ +\chapter{CHERI-128 Alternative Compression Formats (Deprecated)} +\label{app:cheri-128} +\label{sec:compressed-candidates} + +On the path to developing our current capability compression scheme, CHERI +Concentrate (see \cref{subsec:cheri-concentrate}), we developed three earlier +128-bit formats based on floating-point compression of bounds relative to the +virtual address in a capability. +We present those techniques here to explore potential tradeoffs in their +designs and potential alternative approaches. + +\section{CHERI-128 candidate 1} + +\begin{figure}[h] +\begin{center} +\begin{bytefield}[bitwidth=7pt]{64} +\bitheader[endianness=big]{0,63} \\ +\begin{rightwordgroup}{128\\bits} +\bitbox{23}{\cperms{}'23} & \bitbox{2}{\color{lightgray}\rule{\width}{\height}} & \bitbox{6}{\cexponent{}'6} & \bitbox{16}{\ctobase{}'16} & \bitbox{16}{\ctobound{}'16} & \bitbox{1}{\csealed{}} & \\ +\bitbox{16}{\cotype{}'16} & \bitbox{48}{\ccursor{}'48} +\end{rightwordgroup} +\end{bytefield} +\end{center} +\caption{CHERI-128 c1 memory representation of a capability} +\label{fig:cheri128c1-memory-representation-of-a-capability} +\end{figure} + +\paragraph{\csealed{}} + +The \csealed{} flag is set if the capability is sealed and is clear otherwise. +See the discussion of \cotype{} below. + +\paragraph{\cexponent{}} + +The 6-bit \cexponent{} field gives an exponent for the \ctobase{} and \ctobound{} fields. +The exponent is the number of bits that \ctobase{} and \ctobound{} should be shifted before being added to \ccursor{} when performing bounds checking. + +\paragraph{\ctobase{}} + +This 16-bit field contains a signed integer that is to be shifted by \cexponent{} and added to \ccursor{} (with the lower bits set to 0) to give the \cbase{} of the capability. +This field must be adjusted upon any update to \ccursor{} to preserve the \cbase{} of the capability. + +\newcommand{\mask}{{\bf mask}} +\begin{equation*} +\mask{} = -1 << \cexponent{} +\end{equation*} +\begin{equation*} +\cbase{} = (\ctobase{} << \cexponent{}) + \ccursor{} \& \mask{} +\end{equation*} + +\paragraph{\cperms} + +The 23-bit \cperms{} field contains precisely the same 15-bits of permissions as the 256-bit version. The \cperms{} field has 8-bits of software-defined permissions at the top, down from 16-bits in the 256-bit version. + +\paragraph{\ctobound{}} + +This 16-bit field contains a signed integer that is to be shifted by \cexponent{} and added to \ccursor{} (with the lower bits set to 0) to give the bound of the capability. +The \clength{} of the capability is reported by subtracting \cbase{} from the resulting bound. +This field must be adjusted upon any update to \ccursor{} to preserve the \clength{} of the capability. + +\begin{equation*} +\cbase{} + \clength{} = (\ctobound{} << \cexponent{}) + \ccursor{} \& \mask{} +\end{equation*} + +\paragraph{\cotype{}} + +The 16-bit \cotype{} field corresponds directly to the \cotype{} bit vector but is defined only when the capability is sealed. +If \csealed{} is cleared, the architectural \cotype{} is $2^{64}-1$ +but and the bits devoted to object type representation are instead an extension of \ccursor{}. + +\paragraph{\ccursor{}} + +The 64-bit \ccursor{} value holds a 48-bit absolute virtual address that is equal to the architectural \cbase{} + \coffset{}. +The address in \ccursor{} is the full 64-bit MIPS virtual address when the capability is unsealed, +and it holds a compressed virtual address when the capability is sealed. +The compression format places the 5 bits of the address segment in bits [47:42], replacing unused bits of the virtual address. +When the capability is unsealed, the segment bits are placed at the top of a 64-bit address and the rest are ``sign" extended. + +\begin{equation*} +\ccursor{} = \cbase{} + \coffset{} +\end{equation*} + +\paragraph{Compression Notes} +When \insnref{CSetBounds} is not supplied with a length that can be expressed with byte precision, the resulting capability has an \cexponent{} that is non-zero and \ctobase{} and \ctobound{} describe units of size $2^\cexponent{}$. +\cexponent{} is selected such that the pointer can wander outside of the bounds by at least the entire size of the capability both below the base and above the bound without becoming unrepresentable. +As a result, a 16-bit \ctobase{} and \ctobound{} require both a sign bit and a bit for additional range that cannot contribute to the size of representable objects. +The greatest length that can be represented with byte granularity for a 16-bit \ctobase{} and \ctobound{} is $2^{14}=16KiB$. +The resulting alignment in bytes required for an allocation can be derived from the length by rounding to the nearest power of two and dividing by this number. + +\begin{equation*} +alignment\_bits = \lceil log_2(X) \rceil - 14 +\end{equation*} + +\section{CHERI-128 candidate 2 (Low-fat pointer inspired)} + +\begin{figure}[h] +\begin{center} +\begin{bytefield}[bitwidth=7pt]{64} +\bitheader[endianness=big]{0,63} \\ +\begin{rightwordgroup}{128\\bits} +\bitbox{23}{\cperms{}'23} & \bitbox{6}{\cexponent{}'6} & \bitbox{2}{\color{lightgray}\rule{\width}{\height}} & \bitbox{16}{\cbasebits{}'16} & \bitbox{16}{\ctopbits{}'16} & \bitbox{1}{\csealed{}} & \\ +\bitbox{16}{\cotype{}'16} & \bitbox{48}{\ccursor{}'48} +\end{rightwordgroup} +\end{bytefield} +\end{center} +\caption{CHERI-128 c2 memory representation of a capability} +\label{fig:cheri-128c2-memory-representation-of-a-capability} +\end{figure} + + +\newcommand{\correction}{{\bf correction}} + +\paragraph{\cbasebits{}} +This 16-bit field gives bits to be inserted into \ccursor{}[\cexponent{}+15:\cexponent{}], with the lower bits set to 0, to produce the base of the capability. +\[\cbase{} = \{\ccursor{}[63:\cexponent{} + 16] + \correction, \cbasebits{}\}\ll \cexponent{}\] +The bits above $(\cexponent{} + 16)$ in \ccursor{} may differ from \cbase{} by at most 1, i.e. +\[\correction{} = f(\cbasebits{}, \ctopbits{}, \ccursor{}[\cexponent{}+15:\cexponent])= (1, 0, or -1)\] + +\begin{figure}[h] +\begin{center} +\begin{bytefield}[bitwidth=7pt]{64} +\bitheader[endianness=big]{0,63} \\ +\bitbox{34}{\ccursor{}[63:\cexponent{} + 16] + \correction~'(48-\cexponent)} & \bitbox{20}{\ctopbits{}~'16} & \bitbox{10}{0~'\cexponent} \\ +\end{bytefield} +\end{center} +\caption{CHERI-128 c2 base construction} +\label{fig:cheri-128c2-base-construction} +\end{figure} + + +\paragraph{\ctopbits{}} + +This 16-bit field gives bits to be inserted into the bits of \ccursor{} at \cexponent{} to produce the representable top of the capability equal to (top - 1024). +To compute the top, a circuit must insert \ctopbits{} at \cexponent{}, set the lower bits to 0, subtract 1024, and add a potential carry bit. +The carry bit is implied if \ctopbits{} is less than \cbasebits{}, as the top will never be less than the bottom of an object. +\[\cbound{} = \{\ccursor{}[63:\cexponent{} + 16] + \correction, \ctopbits{}, 0\}\] +The bits above $(\cexponent{} + 16)$ in \ccursor{} may differ from \cbound{} by at most 1: +\[\correction{} = f(\cbasebits{}, \ctopbits{}, \ccursor{}[\cexponent{}+15:\cexponent])= (1, 0, or -1)\] + +\begin{figure}[h] +\begin{center} +\begin{bytefield}[bitwidth=7pt]{64} +\bitheader[endianness=big]{0,63} \\ +\bitbox{34}{\ccursor{}[63:\cexponent{} + 16] + \correction~'(48-\cexponent)} & \bitbox{20}{\ctopbits{}~'16} & \bitbox{10}{0~'\cexponent} \\ +\end{bytefield} +\end{center} +\caption{CHERI-128 c2 top bound construction} +\label{fig:cheri-128c2-top-bound-construction} +\end{figure} + +\paragraph{Candidate 2 Notes} +Candidate 2 is inspired by ``Low-fat pointers"~\cite{kwon:lowfat}, +which insert selected bits into the pointer to produce the bounds. +The Low-fat pointer representation does not allow a pointer to go out of bounds, but we observe that \ccursor{} could wander out of bounds without causing \cbase{} and \cbound{} to become ambiguous as long as these three remain within the same $2^{(\cexponent{} + 16)}$-sized region. +Candidate 2 sets the edges of this range to a fixed $1024^\cexponent{}$ bytes beyond each bound, and encodes these in the top and bottom fields to allow high-speed access during pointer arithmetic. + +\section{CHERI-128 candidate 3} + +After substantial exploration, we developed a third compression model, +CHERI-128, which is somewhat similar to candidate 2 with two improvements: + +\begin{itemize} +%\item A smaller, 4 bit \cexponent{} with shift positions limited to multiples of 4 to reduce wiring requirements. +\item Condense hardware and software permissions, making room for larger \cbasebits{} and \ctopbits{} fields in the unsealed capability format. +\item A new sealed capability format, which reduces the size of \cbasebits{} and \ctopbits{} to make room for a larger \cotype{} and software-defined permissions. +\cotype{} no longer aliases bits of \ccursor{} but rather the bounds +metadata. +\end{itemize} + +Subsequent refinement of CHERI-128 gave rise to our current compression +scheme, CHERI Concentrate~\cite{Woodruff2019}, detailed in +\cref{subsec:cheri-concentrate}. + +\paragraph{Alternative exponents} +The CHERI-128 scheme treats the +exponent (\cexponent{}) as a $2^\cexponent{}$ multiplier, though we +note that in our current implementation the bottom two bits of +\cexponent{} are forced to be zero, so the exponent is actually +$16^{\cexponent[5:2]}$. Clearly we could chose different precision +for the exponent, trading precision for hardware cost and bits in the +capability format. + +\paragraph{Alternative precision for \cT{} and \cB{}} +Currently we use 20-bits to represent top and bottom bounds (\cT{} and +\cB{}). This gives us a great deal of precision; however, reducing these +bit widths may well be workable for a broad range of software. In +particular, we may wish to reduce the size of these fields in the +sealed capability format since sealed objects are a new concept and +introducing strong alignment requirements does not appear to have +significant penalty. Similarly, the bit widths could be increased for better +precision. + +\paragraph{Alternative \cotype{} size} +We may wish to adjust the field widths for the sealed capability +format to allow a larger \cotype{}, thereby allowing more sandboxes +without risk of \cotype{} reuse. + +\paragraph{Alternative \cperms{}} +We may wish to adjust field widths to increase the number of +permission bits. + +\subsection{Implementation} +\label{subsec:cheri-128-implementation} + +This section describes the compressed capability format known as +CHERI-128~\cite{UCAM-CL-TR-936}. +The compressed in-memory formats for CHERI-128 unsealed and sealed +capabilities are depicted in +Figures~\ref{fig:unsealed-cheri128-memory-representation-of-a-capability} +and~\ref{fig:sealed-cheri128-memory-representation-of-a-capability}. + +\begin{figure}[h] +\begin{center} +\begin{bytefield}[bitwidth=6pt]{64} +\bitheader[endianness=big]{0,63} \\ +\begin{rightwordgroup}{128 bits} +\bitbox{15}{\cmuperms{}'15} & \bitbox{2}{\color{lightgray}\rule{\width}{\height}} & \bitbox{6}{\cexponent{}'6} & \bitbox{1}{0} & \bitbox{20}{\cB{}'20} & \bitbox{20}{\cT{}'20} & \\ +\bitbox{64}{\caddr{}'64} +\end{rightwordgroup} +\end{bytefield} +\end{center} +\caption{Unsealed CHERI-128 memory representation of a capability} +\label{fig:unsealed-cheri128-memory-representation-of-a-capability} +\end{figure} + +\begin{figure}[h] +\begin{center} +\begin{bytefield}[bitwidth=6pt]{64} +\bitheader[endianness=big]{0,63} \\ +\begin{rightwordgroup}{128 bits} +\bitbox{15}{\cmuperms{}'15} & \bitbox{2}{\color{lightgray}\rule{\width}{\height}} & \bitbox{6}{\cexponent{}'6} & \bitbox{1}{1} & \bitbox{8}{\cB{}[19:12]} & \bitbox{12}{\cotype{}\_hi'12} & \bitbox{8}{\cT[19:12]{}} & \bitbox{12}{\cotype{}\_lo'12}& \\ +\bitbox{64}{\caddr{}'64} +\end{rightwordgroup} +\end{bytefield} +\end{center} +\caption{Sealed CHERI-128 memory representation of a capability} +\label{fig:sealed-cheri128-memory-representation-of-a-capability} +\end{figure} + +\begin{table}[b!] +\begin{center} +\begin{tabular}{lll} +\toprule +architectural bit\# & \cmuperms{} bit\#& Name \\ +\midrule +\cperms{}[0] & 0 & \cappermG \\ +\cperms{}[1] & 1 & \cappermX \\ +\cperms{}[2] & 2 & \cappermL \\ +\cperms{}[3] & 3 & \cappermS \\ +\cperms{}[4] & 4 & \cappermLC \\ +\cperms{}[5] & 5 & \cappermSC \\ +\cperms{}[6] & 6 & \cappermSLC \\ +\cperms{}[7] & 7 & \cappermSeal \\ +\cperms{}[8] & 8 & \cappermCInvoke \\ +\cperms{}[9] & 9 & \cappermUnseal \\ +\cperms{}[10] & 10 & \cappermASR \\ +\cuperms{}[15--18] & 11--14 & Software-defined permissions \\ +\bottomrule +\end{tabular} +\end{center} +\caption{Permission bit mapping} +\label{table:cheri128-perms-bits-mapping} +\end{table} + +\begin{description}[align=right, labelwidth=2em] +\item[\cmuperms{}] Hardware permissions for this format are trimmed from those listed in Table~\ref{table:capability-permission-bits} by consolidating system registers. The condensed format is listed in Table~\ref{table:cheri128-perms-bits-mapping} + +\item[\cexponent{}] Is an exponent for both the top (\cT{}) and bottom + (\cB{}) bits --- see calculations below. Currently the bottom two + bits of \cexponent{} are zero. + +\item[\csealed{}] Indicates if a capability is sealed or not, listed simply as 0 or 1 in Figures +\ref{fig:unsealed-cheri128-memory-representation-of-a-capability} and +\ref{fig:sealed-cheri128-memory-representation-of-a-capability} respectively +due to each format being specific to the state of the sealed bit. + +\item[\caddr{}] A 64-bit value holding a virtual address equal to the + architectural $\cbase{} + \coffset{}$. + +\item[\cB{}] +A 20-bit value used to reconstruct the architectural \cbase{}. +When deriving a capability with a requested \rbase{} and \rlength{}, we have: +\[\cB{} = \left\lfloor \frac{\rbase{}}{2^{\cexponent{}}} \right\rfloor +\mathbf{mod} \; 2^{20}\] +Which can be rewritten as a bit-manipulation: +\[\cB{} = \rbase{}[19+\cexponent{}:\cexponent{}]\hfill\] +For sealed capabilities, $\cB{}[11:0] = 0$ + +\item[\cT{}] +A 20-bit value used to reconstruct the architectural \ctop{} ($\cbase{}+\clength{}$). +When deriving a capability with a requested \rbase{} and \rlength{}, we have: +\[\cT = \left\lceil \frac{\rbase{} + \rlength{}}{2^{\cexponent{}}} \right\rceil \mathbf{mod} \; 2^{20}\] +Rewritten as bit manipulations: +\[ +\cT{} =\begin{cases} +(\rbase{} + \rlength{})[19+\cexponent{}:\cexponent{}],& \text{if } (\rbase{} + \rlength{})[\cexponent{}-1:0] = 0\\ +(\rbase{} + \rlength{})[19+\cexponent{}:\cexponent{}] + 1,& \text{otherwise} +\end{cases} +\] +\item[\cotype{}] +The 24-bit \cotype{} field (concatenation of the two \cotype{} fields of Figure~\ref{fig:sealed-cheri128-memory-representation-of-a-capability}) corresponds to the least-significant 24 bits of the architectural \cotype{} bit vector. These bits are not allocated in an unsealed capability, and the \cotype{} of an unsealed capability is $2^{64}-1$; the encoded value $2^{24}-1$ is reserved. + +\end{description} + +\noindent +The hardware computes \cexponent{} according to the following formula: +\[\cexponent{} = \left\lceil \mathbf{plog_2}\left(\frac{(\rlength{}) \cdot (1+2^{-6})}{2^{20}}\right) \right\rceil\hfill{}\text{where}\hfill{}\mathbf{plog_2}(x)=\begin{cases} +0, &\text{if }x<1\\ +\mathbf{log_2}(x), &\text{otherwise} +\end{cases}\] +which is equivalent to the following bit manipulation: +\[\cexponent{} = \mathbf{idxMSNZ}((\rlength{} + (\rlength{} \gg 6))\gg19)\]%XXX use an "algorithmic" evironment ? +where: +\begin{itemize} +% XXX-BD: idxMSNZ is a new function we made up. I wonder if it would make +% sense to define it in terms of clz() (count leading zeros) which is a +% standard function implemented by compilers. +\item $\mathbf{idxMSNZ}(x)$ returning the index of the most significant bit set in $x$ +\item $(\rlength{} + (\rlength{} \gg 6))$ being a 65-bit result +\end{itemize} +\pagebreak[2] +\noindent +Note that:\nopagebreak[4]% +\begin{itemize} +\item \cexponent{} is rounded up to the nearest representable value. + In the current implementation the bottom two bits of \cexponent{} + are zero. For example, the above \cexponent{} calculation returned + the value 1, then it would be rounded up to 4. +\item $\rlength{}$ is artificially inflated in the computation of + \cexponent{} in such a way that: + \[\rlength{} + 8 \text{KiB} \leq 2^{\cexponent{}+20}\] + to ensure that there is a representable region which is at least one + page above and below the base and bound. This allows pointers to + stray up to a page beyond the base and bound without causing an + exception, a feature which is necessary to run much legacy C-code. +\item \cexponent{} is computed in such a way that loss of precision + due to alignment requirements is minimized, i.e., \cexponent{} is + the smallest natural n satisfying: + \[\mathbf{maxLength}(n) \geq \rlength{}\hfill\text{where}\hfill + \mathbf{maxLength}(n)=\left\lfloor \frac{2^{n+20}}{1+2^{-6}} \right\rfloor\hfill\] +\end{itemize} + +\subsection{Representable Bounds Check} + +When \caddr{} is incremented (or decremented) we need to ascertain +whether the resulting capability is representable. We do not check to +see if the capability is within bounds at this point, which is done +only on dereference (load/store instructions). + +We first ascertain if we are \emph{inRange} and then if we are \emph{inLimits}. +The \emph{inRange} test determines whether an inspection of only the lower bits of +the pointer and increment can yield a definitive answer. +The \emph{inLimits} test assumes the success of the \emph{inRange} test, and determines +whether the update to $\caddr{}_{mid}$ could take it beyond the limits of the representable space. + +The increment $i$ is \emph{inRange} if its absolute value is less than $s$, the size of the +representable region: +\[ inRange = -s < i < s\] + +This reduces to a test that all the bits of $I_{top}$ ($i[63:\cexponent{}+20]$) are the same. +For \emph{inLimits}, we need only $\caddr{}_{mid}$ ($\caddr{}[19+\cexponent{}:\cexponent{}]$), +$I_{mid}$ ($i[\cexponent{}+19:\cexponent{}]$), and the sign of $i$ to ensure that we have not +crossed either $R$ ($\cB{} - 2^{12}$), the limits of the representable region: +\[ + inLimits=\begin{cases} + I_{mid} < (R - \caddr{}_{mid} - 1),& \text{if } i \geq 0 \\ + I_{mid} \geq (R - \caddr{}_{mid}) \land R \neq \caddr{}_{mid},& \text{if } i < 0 \\ + \end{cases} +\] + +When we are incrementing upwards, we must conservatively subtract one from the representable limit +to account for any carry that may propagate up from the lower +bits of the full pointer add. +When the increment is negative, we must conservatively disallow any operation where $\caddr{}_{mid}$ begins +at the representable limit as the standard test would spuriously allow any negative offset. + +One final test is required that ensures that, if $\cexponent{} \geq 44$, any increment is representable. +This handles a number of corner cases related to $T$, $B$, and $\caddr{}_{mid}$ describing +bits beyond the top of the pointer. +Our final fast \emph{representable} check composes these three tests: +\[ representable = (inRange \land inLimits) \lor (\cexponent{} \geq 44)\] + + +\subsection{Decompressing Capabilities} + +When producing the architectural \cbase{} of a capability, the value is computed by inserting \cB{} into \caddr{}[19+\cexponent{}:\cexponent{}], inserting zeros in \caddr{}[\cexponent-1:0], and adding a potential correction \cbasecorrection{} to \caddr{}[63:20+\cexponent{}] as defined in Table~\ref{table:address-correction}: +\begin{align*} +&\cbase{}[63:20+\cexponent{}] = \caddr{}[63:20+\cexponent{}]+\cbasecorrection{}\\ +&\cbase{}[19+\cexponent{}:\cexponent{}] = \cB{}\\ +&\cbase{}[\cexponent{}-1:0] = 0 +\end{align*} + +When producing the architectural \ctop{} ($=\cbase{}+\clength{}$) of a +capability, the value is computed by inserting \cT{} into +\caddr{}[19+\cexponent{}:\cexponent{}], inserting zeros in +\caddr{}[\cexponent-1:0], and adding a potential correction +\ctopcorrection{} to \caddr{}[63:20+\cexponent{}] as defined in Table +\ref{table:address-correction}: +\begin{align*} +&\ctop{}[64:20+\cexponent{}] = \caddr{}[63:20+\cexponent{}]+\ctopcorrection{}\\ +&\ctop{}[19+\cexponent{}:\cexponent{}] = \cT{}\\ +&\ctop{}[\cexponent{}-1:0] = 0 +\end{align*} +Note that \ctop{} is a 65-bit quantity to allow the upper bound to be +larger than the address space. For example, this is used at reset +to allow the default data capability to address all of the virtual +address space, because \ctop{} must be one byte more than the top +address. In this special case, $\cexponent{} \geq 45$. + +For sealed capabilities, $\cB{}[11:0] = 0$ and $\cT{}[11:0] = 0$. + +\begin{table}[h!] +\begin{minipage}{.15\textwidth} +\begin{align*} +&\text{We define}\\ +\caddr{}_{mid} &= \caddr{}[19+\cexponent{}:\cexponent{}]\\ +R &= \cB{} - 2^{12} +\end{align*} +\end{minipage} +%\vline +\hspace{.05\textwidth} +\begin{minipage}{.70\textwidth} +\begin{tabular}{ccrp{2em}ccr} +\cmidrule[\heavyrulewidth]{1-3}\cmidrule[\heavyrulewidth]{5-7} +$\caddr{}_{mid}= resetExp - 1, the bits we're looking at are coming directly from topBits and baseBits, are not being inferred, + // and therefore do not need correction. If we are below this range, check that the difference between the resulting top and + // bottom is less than one address space. If not, flip the msb of the top. + if (cap.bounds.exp<(resetExp-1) && (topTip - zeroExtend(botTip)) > 1) ret[msbp+1] = ~ret[msbp+1]; + return ret; +endfunction +\end{lstlisting} + +\section{CapInBounds} +\label{sec:cheri-128-listings-capinbounds} + +\emph{CapInBounds} detects if the current address of a capability is within its bounds. +This function does not decode the Top and Base of the capability, +but operates directly on compressed fields saving both time and logic. + +\begin{lstlisting}[language=bluespec] +function Bool capInBounds(CapFat cap, TempFields tf, Bool inclusive); + // Check that the pointer of a capability is currently within the bounds + // of the capability + Bool ptrVStop = (inclusive) ? (cap.addrBits<=cap.bounds.topBits) : (cap.addrBits= cap.bounds.baseBits) : tf.addrHi; + return topOk && baseOk; +endfunction +\end{lstlisting} + +\section{IncOffset} +\label{sec:cheri-128-listings-incoffset} + +The IncOffset function from cheri-cap-lib is shared between the IncOffset operation and the SetOffset operation as these two can be made to largely share logic. +The IncOffset function is almost entirely composed of the \emph{fast representable check}~\cite{Woodruff2019}, as the only change to the capability in a non-faulting case is to add the increment to the address. +This check determines if the resulting capability will decode as having the same bounds after the address modification, invalidating the capability if this might not be the case. +As this check is conservative, the boundary conditions are specified in the CHERI architecture in Section~\ref{sec:cheri-concentrate-fast-representable-limit-checking}. +This check is intended to run alongside the add of the address in execute unit. + + +\begin{lstlisting}[language=bluespec] +function VnD#(CapFat) incOffsetFat(CapFat cap, LCapAddress pointer, Bit#(CapAddressW) offset/*this is the increment in inc offset, and the offset in set offset*/, TempFields tf, Bool setOffset); +// NOTE: +// The 'offset' argument is the "increment" value when setOffset is false, +// and the actual "offset" value when setOffset is true. +// +// For this function to work correctly, we must have 'offset' = 'pointer'-'cap.address'. +// In the most critical case we have both available and picking one or the other +// is less efficient than passing both. If the 'setOffset' flag is set, this function will +// ignore the 'pointer' argument and use 'offset' to set the offset of 'cap' by adding it to +// the capability base. If the 'setOffset' flag is not set, this function will increment the +// offset of 'cap' by replacing the 'cap.address' field with the 'pointer' argument (with +// the assumption that the 'pointer' argument is indeed equal to 'cap.address'+'offset'. +// The 'cap.addrBits' field is also updated accordingly. + CapFat ret = cap; + Exp e = cap.bounds.exp; + // Updating the address of a capability requires checking that the new address + // is still within representable bounds. For capabilities with big representable + // regions (with exponents >= resetExp-2), there is no representability issue. + // For the other capabilities, the check consists of two steps: + // - A "inRange" test + // - A "inLimits" test + + // The inRange test + // ---------------- + // Conceptually, the inRange test checks the magnitude of 'offset' is less then + // the representable region's size S. This ensures that the inLimits test result + // is meaningful. The test succeeds if the absolute value of 'offset' is less than S, + // that is -S < 'offset' < S. This test reduces to a check that there are no + // significant bits in the high bits of 'offset', that is they are all ones or all + // zeros. + CapAddress offsetAddr = truncate(offset); + Bit#(TSub#(CapAddressW,MW)) signBits = signExtend(offset[valueOf(TSub#(CapAddressW,1))]); + Bit#(TSub#(CapAddressW,MW)) highOffsetBits = unpack(truncateLSB(offsetAddr)); + Bit#(TSub#(CapAddressW,MW)) highBitsfilter = -1 << e; + highOffsetBits = (highOffsetBits ^ signBits) & highBitsfilter; + Bool inRange = (highOffsetBits == 0); + + // The inLimits test + // ----------------- + // Conceptually, the inLimits test ensures that neither the of the edges of the + // representable region have been crossed with the new address. In essence, it + // compares the distance 'offsetBits' added (on MW bits) with the distance 'toBounds' + // to the edge of the representable space (on MW bits). + // - For a positive or null increment + // inLimits = offsetBits < toBounds - 1 + // - For a negative increment: + // inLimits = (offsetBits >= toBounds) and ('we were not already on the bottom edge') + // (when already on the bottom edge of the representable space, the relevant + // bits of the address and those of the representable edge are the same, leading + // to a false positive on the i >= toBounds comparison) + + // The sign of the increment + Bool posInc = offsetAddr[valueOf(CapAddressW)-1] == 1'b0; + + // The offsetBits value corresponds to the appropriate slice of the 'offsetAddr' argument + Bit#(MW) offsetBits = truncate(offsetAddr >> e); + + // The toBounds value is given by substracting the address of the capability from the + // address of the edge of the representable region (on MW bits) when the 'setOffset' + // flag is not set. When it is set, it is given by substracting the base address of + // the capability from the edge of the representable region (on MW bits). + // This value is both the distance to the representable top and the distance to the + // representable bottom (when appended to a one for negative sign), a convenience of + // the two's complement representation. + + // NOTE: When the setOffset flag is set, toBounds should be the distance from the base + // to the representable edge. This can be computed efficiently, and without relying on + // the temporary fields, as follows: + // equivalent to (repBoundBits - cap.bounds.baseBits): + Bit#(MW) toBounds_A = {3'b111,0} - {3'b000,truncate(cap.bounds.baseBits)}; + // equivalent to (repBoundBits - cap.bounds.baseBits - 1): + Bit#(MW) toBoundsM1_A = {3'b110,~truncate(cap.bounds.baseBits)}; + /* + XXX not sure if we still care about that + if (toBoundsM1_A != (toBounds_A-1)) $display("error %x", toBounds_A[15:13]); + */ + // When the setOffset flag is not set, we need to use the temporary fields with the + // upper bits of the representable bounds + Bit#(MW) repBoundBits = {tf.repBoundTopBits,0}; + Bit#(MW) toBounds_B = repBoundBits - cap.addrBits; + Bit#(MW) toBoundsM1_B = repBoundBits + ~cap.addrBits; + // Select the appropriate toBounds value + Bit#(MW) toBounds = (setOffset) ? toBounds_A : toBounds_B; + Bit#(MW) toBoundsM1 = (setOffset) ? toBoundsM1_A : toBoundsM1_B; + Bool addrAtRepBound = !setOffset && (repBoundBits == cap.addrBits); + + // Implement the inLimit test + Bool inLimits = False; + if (posInc) begin + // For a positive or null increment + // SetOffset is offsetting against base, which has 0 in the lower bits, so we don't need to be conservative. + inLimits = (setOffset) ? offsetBits <= toBoundsM1 : offsetBits < toBoundsM1; + end else begin + // For a negative increment + inLimits = (offsetBits >= toBounds) && !addrAtRepBound; + end + + // Complete representable bounds check + // ----------------------------------- + Bool inBounds = (inRange && inLimits) || (e >= (resetExp - 2)); + + // Updating the return capability + // ------------------------------ + if (setOffset) begin + // Get the base and add the offsetAddr. This could be slow, but seems to pass timing. + ret.address = getBotFat(cap,tf) + zeroExtend(offsetAddr); + // TODO write comments on this + Bit#(TAdd#(MW,2)) newAddrBits = zeroExtend(cap.bounds.baseBits) + zeroExtend(offsetBits); + ret.addrBits = (e == resetExp) ? {1'b0,truncate(newAddrBits)}:truncate(newAddrBits); + end else begin + // In the incOffset case, the 'pointer' argument already contains the new address + CapAddress tmpAddr = truncate(pointer); + ret.address = zeroExtend(tmpAddr); + ret.addrBits = truncate(pointer >> e); + end + // Nullify the capability if the representable bounds check has failed + if (!inBounds) ret.isCapability = False;//nullifyCap(ret); + + // return updated / invalid capability + return VnD {v: inBounds, d: ret}; +endfunction +\end{lstlisting} + +\section{SetAddress} +\label{sec:cheri-128-listings-setaddress} + +This \emph{SetAddress} function assigns a new address to the address field +of a capability. +It is almost entirely composed of a \emph{fast representable check} which asserts +that the bounds will continue to decode to the same value after the assignment +without actually decoding either of the bounds, which is slow. +If the bounds would change, the capability is invalidated. + +\begin{lstlisting}[language=bluespec] +function VnD#(CapFat) setAddress(CapFat cap, LCapAddress address, TempFields tf); + CapFat ret = setCapPointer(cap, address); + Exp e = cap.bounds.exp; + // Calculate what the upper bits of the new address must be if it is to be in representable bounds. + Bool newAddrHi = truncateLSB(ret.addrBits) < tf.repBoundTopBits; + // Shift amount needed to look at only the bits above the mantissa. + Exp toUpperBits = e + fromInteger(valueOf(MW)); + CapAddress mask = -1 << toUpperBits; + CapAddress newAddrDiff = (truncate(cap.address)&mask) - (truncate(address)&mask); + // Assert that the bits above the mantissa are all equal. + Bool inRepBounds = True; + // If the difference between the upper bits of the new address and the current + // address does not match the expected difference, call it outside of representable bounds. + // We construct the "actual" diff assuming that the inRepBounds check above succeeded. + Int#(2) diff = ?; + if (newAddrDiff == 0) diff = 0; + else if (newAddrDiff == mask) diff = -1; + else if (newAddrDiff == (mask^(mask<<1))) diff = 1; + else inRepBounds = False; + let t2 = tuple2; + Int#(2) expectedDiff = case (t2(tf.addrHi,newAddrHi)) + t2(True, True): return 0; + t2(True, False): return 1; + t2(False, True): return -1; + t2(False, False): return 0; + endcase; + if (diff != expectedDiff) inRepBounds = False; + if (e >= resetExp - 2) inRepBounds = True; + if (!inRepBounds) ret.isCapability = False; + return VnD {v: inRepBounds, d: ret}; +endfunction +\end{lstlisting} + +\section{SetBounds} +\label{sec:cheri-128-listings-setbounds} + +The \emph{SetBounds} function sets a new base and length of a capability, performing +and necessary rounding. +This function actually returns a data structure which includes not only the new capability, +but a flag indicating if rounding was necessary (to facilitate \emph{CSetBoundsExact}), +a mask that could be applied to a pointer to align it with the supplied length (to facilitate \emph{CRepresentableAlignmentMask}), +as well as the length that was actually achieved after rounding (to facilitate \emph{CRoundRepresentableLength}). + +\begin{lstlisting}[language=bluespec] +function SetBoundsReturn#(CapFat, CapAddressW) setBoundsFat(CapFat cap, Address lengthFull); + CapFat ret = cap; + // Find new exponent by finding the index of the most significant bit of the + // length, or counting leading zeros in the high bits of the length, and + // substracting them to the CapAddress width (taking away the bottom MW-1 bits: + // trim (MW-1) bits from the bottom of length since any length with a significance + // that small will yield an exponent of zero). + CapAddress length = truncate(lengthFull); + Bit#(TSub#(CapAddressW,TSub#(MW,1))) lengthMSBs = truncateLSB(length); + Exp zeros = zeroExtend(countZerosMSB(lengthMSBs)); + // Adjust resetExp by one since it's scale reaches 1-bit greater than a 64-bit length + // can express. + Bool maxZero = (zeros==(resetExp-1)); + Bool intExp = !(maxZero && length[fromInteger(valueOf(TSub#(MW,2)))]==1'b0); + // Do this without subtraction + //fromInteger(valueof(TSub#(SizeOf#(Address),TSub#(MW,1)))) - zeros; + Exp e = (resetExp-1) - zeros; + // Force otype to unsealed. + ret.otype = otype_unsealed; + // Derive new base bits by extracting MW bits from the capability + // address starting at the new exponent's position. + CapAddress tmpAddr = truncate(cap.address); + LCapAddress base = zeroExtend(tmpAddr); + Bit#(TAdd#(MW,1)) newBaseBits = truncate(base>>e); + + // Derive new top bits by extracting MW bits from the capability + // address + requested length, starting at the new exponent's position, + // and rounding up if significant bits are lost in the process. + LCapAddress len = zeroExtend(length); + LCapAddress top = base + len; + + // Create a mask with all bits set below the MSB of length and then masking all bits + // below the mantissa bits. + LCapAddress lmask = smearMSBRight(len); + // The shift amount required to put the most significant set bit of the + // len just above the bottom HalfExpW bits that are taken by the exp. + Integer shiftAmount = valueOf(TSub#(TSub#(MW,2),HalfExpW)); + + // Calculate all values associated with E=e (e not rounding up) + // Round up considering the stolen HalfExpW exponent bits if required + Bit#(TAdd#(MW,1)) newTopBits = truncate(top>>e); + // Check if non-zero bits were lost in the low bits of top, either in the 'e' + // shifted out bits or in the HalfExpW bits stolen for the exponent + // Shift by MW-1 to move MSB of mask just below the mantissa, then up HalfExpW + // more to take in the bits that will be lost for the exponent when it is non-zero. + LCapAddress lmaskLor = lmask>>fromInteger(shiftAmount+1); + LCapAddress lmaskLo = lmask>>fromInteger(shiftAmount); + // For the len, we're not actually losing significance since we're not storing it, + // we just want to know if any low bits are non-zero so that we will know if it will + // cause the total length to round up. + Bool lostSignificantLen = (len&lmaskLor)!=0 && intExp; + Bool lostSignificantTop = (top&lmaskLor)!=0 && intExp; + // Check if non-zero bits were lost in the low bits of base, either in the 'e' + // shifted out bits or in the HalfExpW bits stolen for the exponent + Bool lostSignificantBase = (base&lmaskLor)!=0 && intExp; + + // Calculate all values associated with E=e+1 (e rounding up due to msb of L increasing by 1) + // This value is just to avoid adding later. + Bit#(MW) newTopBitsHigher = truncateLSB(newTopBits); + // Check if non-zero bits were lost in the low bits of top, either in the 'e' + // shifted out bits or in the HalfExpW bits stolen for the exponent + // Shift by MW-1 to move MSB of mask just below the mantissa, then up HalfExpW + // more to take in the bits that will be lost for the exponent when it is non-zero. + Bool lostSignificantTopHigher = (top&lmaskLo)!=0 && intExp; + // Check if non-zero bits were lost in the low bits of base, either in the 'e' + // shifted out bits or in the HalfExpW bits stolen for the exponent + Bool lostSignificantBaseHigher = (base&lmaskLo)!=0 && intExp; + // If either base or top lost significant bits and we wanted an exact setBounds, + // void the return capability + + // We need to round up Exp if the msb of length will increase. + // We can check how much the length will increase without looking at the result of adding the + // length to the base. We do this by adding the lower bits of the length to the base and then + // comparing both halves (above and below the mask) to zero. Either side that is non-zero indicates + // an extra "1" that will be added to the "mantissa" bits of the length, potentially causing overflow. + // Finally check how close the requested length is to overflow, and test in relation to how much the + // length will increase. + LCapAddress topLo = (lmaskLor & len) + (lmaskLor & base); + LCapAddress mwLsbMask = lmaskLor ^ lmaskLo; + // If the first bit of the mantissa of the top is not the sum of the corrosponding bits of base and length, there was a carry in. + Bool lengthCarryIn = (mwLsbMask & top) != ((mwLsbMask & base)^(mwLsbMask & len)); + Bool lengthRoundUp = lostSignificantTop; + Bool lengthIsMax = (len & (~lmaskLor)) == (lmask ^ lmaskLor); + Bool lengthIsMaxLessOne = (len & (~lmaskLor)) == (lmask ^ lmaskLo); + + Bool lengthOverflow = False; + if (lengthIsMax && (lengthCarryIn || lengthRoundUp)) lengthOverflow = True; + if (lengthIsMaxLessOne && lengthCarryIn && lengthRoundUp) lengthOverflow = True; + + if(lengthOverflow && intExp) begin + e = e+1; + ret.bounds.topBits = (lostSignificantTopHigher) ? (newTopBitsHigher+'b1000):newTopBitsHigher; + ret.bounds.baseBits = truncateLSB(newBaseBits); + end else begin + ret.bounds.topBits = (lostSignificantTop) ? truncate(newTopBits+'b1000):truncate(newTopBits); + ret.bounds.baseBits = truncate(newBaseBits); + end + Bool exact = !(lostSignificantBase || lostSignificantTop); + + ret.bounds.exp = e; + // Update the addrBits fields + ret.addrBits = ret.bounds.baseBits; + // Derive new format from newly computed exponent value, and round top up if + // necessary + if (!intExp) begin // If we have an Exp of 0 and no implied MSB of L. + ret.format = Exp0; + end else begin + ret.format = EmbeddedExp; + Bit#(HalfExpW) botZeroes = 0; + ret.bounds.baseBits = {truncateLSB(ret.bounds.baseBits), botZeroes}; + ret.bounds.topBits = {truncateLSB(ret.bounds.topBits), botZeroes}; + end + + // Begin calculate newLength in case this is a request just for a representable length: + LCapAddress newLength = zeroExtend(length); + LCapAddress baseMask = -1; // Override the result from the previous line if we represent everything. + if (intExp) begin + LCapAddress oneInLsb = (lmask ^ (lmask>>1)) >> shiftAmount; + LCapAddress newLengthRounded = newLength + oneInLsb; + newLength = (newLength & (~lmaskLor)); + newLengthRounded = (newLengthRounded & (~lmaskLor)); + if (lostSignificantLen) newLength = newLengthRounded; + baseMask = (lengthIsMax && lostSignificantTop) ? ~lmaskLo:~lmaskLor; + end + + // Return derived capability + return SetBoundsReturn{cap: ret, exact: exact, length: truncate(newLength), mask: truncate(baseMask)}; +endfunction +\end{lstlisting} diff --git a/app-exp-peripherals.tex b/app-exp-peripherals.tex new file mode 100644 index 00000000..9b908c95 --- /dev/null +++ b/app-exp-peripherals.tex @@ -0,0 +1,110 @@ +CHERI's design focuses on the `main' CPU core(s), in which there is a single operating system, and capabilities are used within virtual address spaces, mediated via an MMU and a memory-coherency system. + +Many systems are composed of distributed compute elements that share memory. In various contexts these are termed `peripherals', `DMA engines', `accelerators' or `remote DMA network cards'. These may be on a single system-on-chip using fabrics such as AXI, or across interconnect such as PCI Express, Thunderbolt or Infiniband. + +When capabilities are used in such a system, there is a requirement to +protect them from inappropriate modification by cores that might be outside the purview of the primary operating system. Additionally, it would be advantageous for such cores to use capabilities for their own code and data, without having to mediate them from centralized authority. Furthermore, such systems frequently use multiple levels of address translation -- not just a virtual address space (as capabilities in this document primarily refer to), but a patchwork of multiple physical address spaces (including the guest physical address spaces used by hypervisors), as well as virtual address spaces used by accelerators and other cores. + +There are two challenges: first, preventing a core from modifying a +capability it does not own, and second, handling the case that capabilities +can alias if they refer to an incorrect address space. + +To achieve these goals, we propose several architectural features. + +\subsection{Scope and threat model} +This feature assumes that peripherals are capability-aware, in that they are able to load, store and manipulate capabilities and their tags. A number of scenarios with trustworthy hardware and software, untrustworthy software on trustworthy hardware, or untrustworthy hardware and software may be envisaged. Hardware that is not capability-aware and uses integers as pointers is out of scope for this extension, although it may be constrained or otherwise capability-wrapped by some other structure. + +\subsection{Address-space coloring} + +We deconstruct systems into regions of address-space colors (ASCs). A region with a common color has addresses with a single unambiguous meaning. Generalizing, a color could apply to an application's virtual address space, the system's hardware physical address space, the guest physical address space of a virtual machine, or a piece of memory on a peripheral. +A Processing Element (PE -- processor, DMA engine or other core) is assigned a color based on its physical location in the system topography. + +Colors also represent single regions of authority. Within a colored region, it is assumed that every device that can synthesize a capability has rights to do so. If a device is untrustworthy, it should be segmented into a different colored region. + +An address space may be connected to a different address space via an Address Translation and Protection Unit (ATPU). Examples of ATPUs might be MMUs, IOMMUs, and hypervisor page translation, but also more limited cases such as PCI BAR mapping or driving upper address bits from a page register. An ATPU may provide no translation between mutually distrusting hardware that happens to share an address space, but still apply protection between them. + +We generalize an ATPU as a bridge by which requests come in from one address space and are dispatched into another. The ATPU may itself make memory requests to determine the translation, such as when walking page tables. These would potentially occur in an address space of a third color. + +\subsection{Capability coloring} +Capabilities refer to addresses in particular address spaces, hence capabilities are given a color that is stored within the capability. It is now possible to disambiguate the address within a capability with the address space to which it refers. + +\subsubsection{Representation} +We describe architecturally the notion of address space color without specifying the specific representation. +However microarchitecturally we expect that the \cotype{} field in a capability would be reused, based on a tagging scheme to distinguish them from a software-defined \cotype{}. Given the limited number of bits available in the \cotype{} for the otype-color, it may be impossible to represent all the colors within these bits. It is not necessary for the otype-color field to be unique, only that it is possible to disambiguate which address space region is referred by a capability. For example, the upper bits of the address may be used to distinguish two regions with the same otype-color field which are each smaller than 64-bit addressing. Architecturally such regions would be thought of as having different colors. + +\paragraph{otype reuse} +\label{app:exp:otype-reuse} +Since 128-bit capabilities are constrained by size, we propose using the \cotype{} field to represent some or all of the ASC. To disambiguate from the softwaredefined \cotype{}, the data structure should be tagged. + +To avoid reducing the bits for the \cotype{}, we propose a variable-length tag. This also allows embedding one instance of a variety of other metadata in the \cotype{} field. For example: + +\begin{verbatim} +0x_xxxx_xxxx_xxxx_xxxx: Software-defined otype (17 bits) +10_xxxx_xxxx_xxxx_xxxx: Metadata type A (16 bits) +11_0xxx_xxxx_xxxx_xxxx: Metadata type B (15 bits) +... +11_1110_cccx_xxxx_xxxx: Metadata type E (8 alternatives of 9 bits each) +\end{verbatim} + + +\subsection{Operations on colored capabilities} +Colors are used to enforce policy by processing elements and ATPUs. A processing element has, in its hardware, an awareness of the color of its local address space. + +In this area exist a number of possibilities, subject to further research. + +Most conservatively, a PE could deal only with capabilities of its own color. A capability with another color is treated as if the tag is cleared. This would allow PEs to use capabilities internally, without sharing between them. A privileged process (boot loader, management processor, hypervisor, operating system on an application core) is used to generate initial colored capabilities for each PE, from where they are used internally. + +In this scenario, capability conversion between colors would be minimal or require a call to the privileged process. +Conversion would require translation between address spaces, with a chance that a capability could not be directly represented in the target address space (if it represents disparate physical pages, for instance). + +Other approaches are possible. For instance, colored capabilities could be treated as sealed. This would enable devices to be given `handles' to memory in another address space that they cannot access, but can pass around to other data structures. For instance, networking data structures might contain linked list pointers in network stack address space -- the NIC can build its own linked list, without the ability to access the data being pointed to. Much care would be required here to avoid confused deputy attacks. + +%We consider the following operations by PEs: + +%\begin{description} +%\item[Read of a capability, local color.] Allowed. A PE can make free use of capabilities of its local color. All the %regular operations on capabilities have their usual effect. +%\item[Write of a capability, local color.] Allowed. The capability is stored in memory with its color (potentially %transformed by ATPUs as described below). +%\item[Read/write of a capability, non-local color.] Non-local capabilities are treated as sealed. They can be stored in %memory and passed to other devices without modification. +%\item[Unseal capability, non-local color.] The unseal operation transforms a capability from a foreign address space into %the current address space, converting it to the local color. This may require a call-out to ATPU(s) to receive the %translation, potentially passing through several ATPUs. +%\item[Seal capability, local color.] Local use of sealing is still permitted, generating a sealed capability of a local %color. Given microarchitectural constraints, a smaller \cotype{} space may be available. +%\item[Seal capability, non-local color.] May change to the representation of a sealed capability with the target color. +%\item[Change color on capability.] A local capability may be converted to a capability of a different color by passing it %through ATPU(s), which return the appropriate non-local capability. The rights on the returned capability may be reduced %compared to the input. +%\end{description} + +\subsection{Enforcement} +Both PEs and system bridges are tasked with enforcing the capability model: + +\paragraph{Bridges} enforce operations on colored capabilities. For example, a bridge may disallow capabilities of other colors to pass through it. Bridges are viewed as more trustworthy than devices they connect, although a hierarchy exists -- bridges closer to DRAM are able to disallow capabilities that are accepted by bridges further away. Bridges have an awareness of whether hardware might be untrustworthy (for instance, plugged in to a motherboard slot or external port) and apply external enforcement of properties where the hardware might be untrustworthy. + +ATPUs could also transform capabilities that pass through them according to their address space remapping -- e.g., allowing a PE to store capabilities with its local address space, but remap them to physical addresses when storing to DRAM.\tmnote{Does this make sense? Reversibility? Representability? Need to consider what happens when something looks at the integer address of such a transformed cap.} + +%\paragraph{PEs} are tasked with enforcing sealing of non-local capabilities. +%\tmnote{What happens when malicious PE hardware violates the sealing of a non-local cap? Can the bridge efficiently enforce that?} +\paragraph{PEs} are tasked with enforcing the capability model within their local software. Bridges enforce colors, but PEs enforce the remainder of the capability model (monotonicity, tagging, etc). An untrustworthy PE may corrupt its own capabilities, but since the coloring is enforced by the bridge it will only have detrimental effects on its own software. + +\subsection{Implementation outline} +For a minimalist implementation, the following might be done: + +\begin{enumerate} +\item Choose a representation for the bits that indicate a color within a capability +\item Implement a CSR that configures the current color of a processor core. The +permissions on this register are up for debate but access control might be +similar to that of the IOMMU page table base register - potentially +set externally rather than internal to a PE +\item In user mode, loading or dereferencing capabilities checks the color +matches the current one, and causes an exception if mismatched +\item A privileged instruction takes two capabilities, an input capability +and an authorization capability. The output of the instruction is the input +capability with the color changed to match the authorization capability. +\tmnote{Is this something that should be restricted by a permission? Or by +a mode?} +\item Checks may be necessary to verify the input capability is a subset of the +authorization capability, bearing in mind they may be in different address +spaces without a contiguous mapping. +\item It may be necessary for a PE that wishes to change the color of its +capability to call out to a more trustworthy component, such as a bridge or +another processor with more authority. This could be modeled by the PE not +possessing a suitable authorization capability, and thus making an API call to +another PE or ATPU. ATPUs may implement such translation in hardware to +make it efficient. +\end{enumerate} diff --git a/app-experimental.tex b/app-experimental.tex new file mode 100644 index 00000000..10166ab0 --- /dev/null +++ b/app-experimental.tex @@ -0,0 +1,2459 @@ +\chapter{Experimental Features and Instructions} +\label{app:experimental} + +This appendix describes experimental features and instructions proposed for +possible inclusion in later versions of the CHERI ISA. +These items for consideration include optimizations, new permissions, new +compression formats, and overhauls of existing CHERI mechanisms. +Some are relatively mature, and we anticipate their achieving a +non-experimental status in the next version of the CHERI ISA specification +(e.g., capability flags and temporal memory safety). +Others arose as part of our more general design-space exploration, and we +document these alternative approaches (e.g., indirect capabilities) or +potential future avenues of investigation (e.g., linear capabilities). +We present them here in roughly increasing order of complexity. +The body of the appendix describes the rationale and approach for each +experimental feature; specific instruction encodings and semantics may be +found in Section~\ref{app:exp:insns}. +\pgnnote{roughly increasing order of complexity? + might they instead be grouped + more structurally as major sections, and then roughly increasing + order within those major sections?} + +% >>> +\section{Capability Reconstruction} % <<< +\label{section:capability-reconstruction} + +These additional experimental instructions can be used to efficiently +reconstruct capabilities (e.g., when a program has been paged out to disk +and then paged back in, and the operating system needs to reconstruct the +capabilities that were originally in its address space). +They also reduce the need for software to inspect the in-memory representation +of capabilities, making software more robust to format changes. + +Software should store or transit tags separately from the corresponding +capa\-bility-sized, capa\-bility-aligned memory via a trustworthy medium. +The ISA requires that tags be restored using a suitable authorizing capability +through which it should have been possible to derive the same resulting tagged +capability -- that is, without violating capability monotonicity. +A security review of these instructions is still in progress, and so they +should not yet be considered part of the ISA or safe to implement. +These instructions serve two purposes: + +\begin{enumerate} +\item They allow efficient internalization of capabilities that have been + stored or transferred via media that do not preserve tags. + This functionality might be utilized when tags must be restored by the + kernel's swap or compressed-memory pager, when migrating the memory of a + virtual machine, when restoring a process snapshot, or by an + in-address-space run-time linker. + +\item They allow tags to be restored on capabilities in a manner that + maintains architectural abstraction: software restoring tags need not encode + the specifics of the in-memory capability representation, making that + software less fragile in the presence of future use of reserved fields or + changed semantics. +\end{enumerate} + +Capabilities can also be reconstructed using the current +\insnref{CGetBase}, \insnref{CGetLen}, etc., instructions, examining +those fields and then recreating them utilizing the corresponding +\insnref{CSetBounds} instruction, and so on, but with reduced abstraction +and substantially less efficiency. + +Details of the proposed \insnref{CBuildCap}, \insnref{CCopyType}, +and \insnref{CCSeal} instructions are deferred to \cref{app:exp:insns}. + +\note{It has also been proposed that something much like capability +reconstruction be allowed to reconstruct an \emph{unsealed} capability from +a sealed one, again, guarded by needing a superset.}{nwf} + +% >>> +\section{Additional Architectural Assistance For Revocation} % <<< + +\subsection{Fast Capability Subset Testing} % <<< +\label{subsection:fast-capability-subset-testing} + +When implementing revocation or garbage collection requiring fast scanning +of memory for matching capabilities, significant numbers of instructions +would be used to check whether a tested capability is a subset of a reference +capability. We propose a new \insnref{CTestSubset} +instruction that reduces this instruction count substantially; see +\cref{app:exp:insns} for details. + +\subsection{CClearTags} % <<< + +Typically, allocators allow for the return of ``uninitialized'' memory +(e.g., \texttt{malloc} vs.\@ \texttt{calloc}). In the context of temporal +safety, this proves to be problematic unless the allocator is type- and +use-specicialized: data and pointers may unintentionally flow into the +possession of the holder of a new allocation, violating both confidentality +and, in a non-architectural sense, provenance integrity. Most treatments of +security-conscious allocators therefore always zero memory. CHERI can +directly probe at the difference between confidentality of data and +provenance integrity of pointers. Towards this end, we introduce a +\insnref{CClearTags} instruction, which permits bulk zeroing of +capabilities within a cacheline (i.e., at the same granularity as +\insnref{CLoadTags}). + +While \insnref{CClearTags} may be a useful alternative to +\texttt{bzero}-ing memory when confidentiality is not required, it has at +least one additional use in the context of revocation specifically. +\insnref{CClearTags} should accelerate sweeping by allowing allocators +to optimistically, even if not perfectly, remove capabilities within freed +regions, removing comparatively expensive look-aside checks of validity +during sweeps, at a lower cost than zeroing. + +\insnref{CClearTags} is intended to be \emph{non-allocating} in the caches, +as with its counterpart \insnref{CLoadTags}. If a cacheline is not present +in the cache fabric, the induced store should always transit to the tag cache +rather than pulling the line data into the caches. + +\nwfnote{We could also introduce a \insnnoref{CAndTags} instruction +that took a bitmask of which entries in the line to zero; this would make it +useful for small allocations, but it's not clear that that's actually +worthwhile. Small allocations seem like they might be likely to be in the +cache already.} + +% >>> +\subsection{Non-Temporal (Streaming) CLC} % <<< +\label{app:exp:clcnt} + +During revocation, whenever a capability is identified via +\insnref{CLoadTags}, it is fetched from memory for analysis. A large +fraction of these capabilities are expected to be valid, and so will not +cause additional activity within their cache line.% +% +\footnote{Those capabilities that are found to be revoked are then subjected +to a \insnref{CLLC}/\insnref{CSCC} sequence for atomic replacement +with their revoked image.} +% +Being able to hint to the cache that the revoker is \emph{streaming} through +memory, and so should not pave over the caches, seems like a worth-while +objective. We therefore introduce a non-temporal, streaming +\insnref{CLC} analogue, \insnref{CLCNT} with architectural semantics +exactly matching those of \insnref{CLC}, but as a separate opcode to +hint to the microarchitecture. To preserve encoding space, +\insnref{CLCNT} jettisons the immediate and assumes it to be zero. + +\nwfnote{It may make sense to unroll the revoker loop to some presumed +cacheline stride, in which case perhaps we should jettison the index +register rather than the immediate. But keeping the index register seems +the friendlier of the options.} + +While one implementation of such a streaming CLC would be to never promote +lines in the cache hierarchy (i.e., leave them in place, in DRAM or the LLC +when loading), analysis done as part of the Efficient Tagged Memory \cite[\S +VI.B]{joannou2017:tagged-memory} suggests that if a cacheline has one +capability, it is relatively likely to have another.% +% +\footnote{Specifically, the ratio of the probability of a capability being +found in memory with a ``grouping factor 8'' (corresponding to our FPGA's +caches for CHERI Concentrate capabilities) to an independent sampling of +eight ``grouping factor 1'' binomials (analysing on a word-by-word basis) is +between $0.97$ and $0.32$, implying clustering of capabilities.} +% +This suggests that \insnref{CLCNT} should be caching, but restrictedly +so. Na\"ively, we suggest that ensuring misses usually allocate below some +top $k$ lines of the MRU queue for the cache ``way'' activated will result +in it being evicted relatively soon and without introducing too much +contention with the application. When a \insnref{CLCNT} hits in the +cache, it should not trigger promotion to the front of the MRU queue. +Whether this policy is a good one, and, if so, what the correct values of +$k$ and ``usually'' are, remain open questions. + +% >>> + +\nwfnote{We may also be able to offer stronger guarantees to lock-free data +structures by adding a ``conditional CLC'' instruction which gates its operation +on the LL/SC link flag. In some toy examples, this seems to make full SMR +hazards unnecessary. Unclear that it is worth pursuing.} + +% >>> +\section{Recursive Mutable Load Permission} % <<< +\label{app:exp:recmutload} + +\makecapperm{RML}{Recursive\_Mutable\_Load} + +Several software capability systems have exploited the use of immutable data +structured to facilitate safe sharing (e.g., Joe-E~\cite{mettler:joee}). +CHERI capabilities can provide references through which stores are not +permitted; however, because they can be refined and distributed throughout the +system, simply holding a read-only reference is not sufficient to allow a +consumer to ensure that no simultaneous access can occur to the same memory +via another capability. +Further, passing a read-only reference to memory does not ensure that further +loads of capabilities from within that memory provide only read-only access to +`deep' data structures -- e.g., linked lists. + +Various software-level invariants could be used to improve confidence for both +callers and callees. +For example, the software runtime might make use of read-only MMU mappings for +immutable data, and provide capabilities that clearly provide an indication +that they refer to those read-only mappings -- e.g., via use of a +software-defined permission bit set only for such references, via use of +reserved portions of the address space, sealed via a certain type, or +checkable via a dynamic service operating in a trustworthy protection domain. +In addition, memory could be allocated as mutable and its MMU mapping later +modified to `freeze' the contents, or by performing a revocation-like sweep +to convert any extant store-enabled capabilities into load-only capabilities. + +However, providing strong architectural invariants to software offers +significant value. One idea we have considered is a new permission, +\cappermRML, which if not present, clears store +permissions and the recursive mutable load permission, on any capability +loaded via a capability with this permission present.% +% +\footnote{The concept of such \emph{transitively} read-only capabilities +appears to have been first developed in KeyKOS, where such capabilities were +termed `sensory keys'~\cite{hardy:keykos}. While sensory keys were +necessarily read-only, the descendent notion of the `weak' access modifier +in EROS could be applied to both read and write operations. When modifying +reads, it behaves as described so far; attempts to store some input +capability through a weak write-permitting capability resulted in a +weakened version of the input capability being stored~\cite{shapiro:eros}. +In the successor system Coyotos, `weak' was once again made to imply +read-only access~\cite{doerrie2015:confinement,shapiro:coyotosspec}.} +% +A module may clear the store permissions and also clear +\cappermRML on a capability before passing it to another +module. Having done so, the originator is guaranteed that this passed +capability could not then be used to mutate memory it directly describes +(lacking store permissions) or memory transitively referenced therefrom, even +if the latter capabilities, authorizing transitive access, bear some store +permissions. +% +This would not prevent temporal vulnerabilities +associated with reallocation of the memory; subject to other invariants +and safety properties, it might make it easier to construct safe references. +In particular, this mechanism is likely to be of great utility to systems +wishing to enforce the `*-property' (`no write down') of the model of +Bell and La Padula~\cite{B+LP76}.% +% +\footnote{Readers may be familiar with the infamous proof of +Boebert~\cite{boebert:inabilitystar} that ``an unmodified capability machine'' +is unable to enforce this property. As CHERI distinguishes between +capabilities and data, the proof is not directly +applicable~\cite{miller:capmyths}, and, indeed, one could imagine using trusted +intermediate software to emulate the effects of +\cappermRML, as proposed by +Miller~\cite{miller:paradigmregained}. Despite that, +\cappermRML is still of practical utility, as it is a +light-weight, architecturally enforceable mechanism that avoids indirection.} + +\paragraph{Interaction With Sealed Capabilities} +% +A question arises about loads of \emph{sealed} capabilities bearing (for +example) \cappermS through a capability lacking \cappermRML: in some sense, +this sealed capability is authorizing mutation; are we to clear its \cappermS, +despite the seal? We view the immutability of sealed capabilities as taking +precence, and so preserve \cappermS under seal even in this scenario. Beyond +aesthetics, we conjecture that this interpretation is convenient for software: +\cappermRML can be cleared to create read-only collections of sealed handles to +software objects.% +% +\footnote{By way of example, software can create an immutable collection $c$ of +\emph{arbitrary} unsealed capabilities by sealing each capability logically +held in $c$ to a type with an \emph{ambiently available} unsealing right and +referencing $c$ itself through \cappermRML-clear capabilities. A layer of +indirection suffices to permit arbitrary \emph{sealed} capabilities within $c$ +as well. Software can restrict this model by using compartmentalized unsealers +rather than ambient authority.} +% +Nevertheless, software must be aware that mutation authority under seal is not +stripped by \cappermRML. + +\let\cappermRML\undefined + +% >>> +\section{Hierarchical Revocation From Ephemeral Capabilities} % <<< +\label{app:exp:hierarchal-evocation} + +The ``revocation'' work atop CHERI to date has been about revoking all +(non-TCB) access to resources (usually, virtual address space). However, +``Capability Revocation'' more typically means the ability for any agent, +which has delegated access to some resource, to revoke some (or all) of its +delegations while retaining access and the ability to further delegate +access \cite{Redell74}. +% +Efforts to develop such capacity atop CHERI would likely rely upon sealed +capabilities or domain transitions (with or without exceptions) to mediate +delegation, as these are the most apparent mechanisms available to us to +prevent unchecked duplication of usable authority. However, these come with +somewhat large costs: domain transitions impose cycle overheads, and either +strategy would seem to require that the set of \emph{operations} on the +delegated resource be fixed by its constructor. For example, the original +source of a revokably delegated data resource would likely have to provide +specialized \texttt{memcpy} implementations for moving data out of or in to +the resource's memory. +In this section, we explore the implementation of directly-accessible +revokable delegation assuming the existence of \emph{ephemeral} +capabilities, which cannot be stored to memory once loaded into a register +file. + +\subsection{Ephemeral Capabilities} % <<< + +The basic primitive of an ephemeral capability is a degenerate +generalization of the \cappermG* / \cappermSLC* mechanism of CHERI (recall +\cref{sect:capability-permission-bits}) and the ``capability coloring'' +proposal of \cref{sec:compactcolors}. Ephemeral capabilities are +constructed via a new \emph{store} instruction, +\insnnoref{CStoreEphemeral} which, given a non-ephemeral capability +in a register, places an ephemeral version in memory, which may thereafter +be loaded with \insnref{CLC}.% +% +\footnote{We propose the use of a reserved \cotype{} value, rather than a new +permission bit, to designate capabilities of this form (but without +interpreting this value as \emph{sealed}). As we intend these non-storable +capabilities to be ephemeral, there will not be enough of them present in +the system at any moment to justify the use of a permission bit. Moreover, +while the use of an \cotype{} means that we cannot seal these non-storable +capabilities, even in registers, this does not seem to be a loss.} +% +If an attempt is made to store, via \insnref{CSC}, an ephemeral +capability to memory, an un-tagged version is stored instead. Thus, once +loaded, an ephemeral capability is confined to the register file and even a +context switch will destroy it. Similarly, a (transitive) callee's attempt +to spill such a capability to the stack will instead detag it, and so these +ephemeral capabilities must be considered lost across general procedure +calls. (While ephemeral capabilities can still be passed in registers as +arguments, in general, we suggest passing a non-ephemeral capability to the +ephemeral one instead.) + +Software consuming these ephemeral capabilities must be prepared to deal +with revocation and the \emph{appearance} of revocation, by attempting to +reload a tagged ephemeral capability from memory. Software must be careful +to preserve access to the memory locus of the ephemeral capability loaded to +the register file. Operations done against such revokably delegated +resources should be idempotent (which may just mean that they are precisely +resumable).% +% +\footnote{It is possible to imagine architectural assistance beyond trapping +on untagged capabilities, should the ``trap-and-reload'' approach sketched +here be unduely onerous.} + +% >>> +\subsection{Revocation} % <<< + +Armed with such a primitive capability form, resource revocation still needs +to remove (a hierarchy of) ephemeral capabilities from memory, but the +issuing authority has ensured that access to the delegated resource has not +spread unchecked in memory. Having removed all the targeted ephemeral +capabilities from memory, a single context switch on all cores suffices to +ensure that there is no retained access. These context switches may be +actively driven (with IPIs) or passively observed (as with epoch-revocation +schemes). We propose that a \emph{compartment} within the TCB oversee the +construction and (hierarchical) delegation of revokable delegate +intermediaries. + +In order to efficiently revoke a subtree of the delegation relationship, we +will need to construct that relationship explicitly in memory in a way that +its subtrees are easily enumerated. The design we propose herein makes +heavy use of sealed capabilities to small regions of memory, directly +storing the delegation relationship metadata with the delegated, ephemeral +capabilities themselves. These small regions of memory are used once and so +may be reclaimed by the existing \emph{global} revocation mechanisms after +their purpose has been served.% +% +\footnote{Users of this mechanism must therefore be prepared for faults +while using the ephemeral capability as well as when attempting to reload +it. Fortunately, this seems straightforward.} +% +Such a \emph{delegation box} contains: +% +\begin{itemize} +% + \item An ephemeral capability to the delegated resource +% + \item A capability to the progenitor delegation box, if any. +% + \item A pair of capabilities forming a doubly-linked list of this box's +delegation \emph{siblings}. +% + \item A capability to one of its child delegation boxes, if any. +% +\end{itemize} +% +Straightforward rose tree \cite{skillicorn:partreeskel} operations suffice +to maintain the hierarchical delegation structure using these boxes, and +sealing ensures that we can safely give out the rights to manipulate a box +(constructing a new child or revoking the subtree of which it is the root). +A separate grant of access directly to the ephemeral capability allows the +direct use of the delegated resource until the delegation box's revocation. + +% >>> +\section{Compressed Permission Representations} % <<< +\label{app:exp:compressperm} + +The model of Section~\ref{sect:capability-permission-bits} describes each +permission as a separate bit. This has certain advantages, including the +ability to describe {\em the} all-powerful capability, a uniform +presentation, wherein the monotonic non-increase of rights is directly +encoded by the monotonic operation of bitwise \emph{and}, and a fast operational +test for a given permission. However, in use and interpretation, the +permission bits are not orthogonal, so one could aim for a compressed +representation, freeing up bits for use as user permissions, or reserving +them for future expansion of the ISA. We do not fully develop this story; +instead, we merely indicate examples of redundancy in the abstract model, +which may be useful to architects wishing to squeeze every last bit out of +any particular representation. + +The \cappermG attribute, despite being enumerated as a permission, does not +describe permissions to the memory or objects designated by a capability. +Instead, it interacts with data storage permissions of other capabilities +(via \cappermSLC). As such, it truly is orthogonal to +the rest of the permission bits (though it remains `monotonic' in the +sense that clearing the \cappermG permission results in a capability capable of +participating in fewer operations). + +Broadly speaking, there are three spaces of identifiers described within the +CHERI capability system: virtual addresses, object types, and compartment +identifiers. Rights concerning executability, loads, and stores apply only +to capabilities describing virtual addresses, while the rights to (un)seal +an object apply only to capabilities describing object types. The +\cappermCid permission applies only to capabilities describing +compartment identifiers. This permits some reduction of encoding space. + +Similar reduction in encoding space may be realized if one mandates that +certain {\em user} permission bits are similarly applicable only to novel +non-architectural spaces of identifiers (e.g., UNIX file descriptors). +However, at +present we consider the sealing mechanism more useful and flexible +for the construction of such spaces of identifiers, as typically such +identifiers are ultimately given meaning by some bytes in virtual memory, to +which one may gain access by unsealing an object capability used as a +reference.% +% +\footnote{Sadly, while sealed capabilities are almost exactly what one wants +for file descriptors, because UNIX chose to type file descriptors as +\texttt{int}, the conversion to use sealed capabilities will be broadly +invasive, even if most of the changes will simply be to change the types.} +% +However, the notion of other spaces is not entirely out of the question; {\em +physical} addresses may prove to be a compelling example on some systems. + +While \cappermCInvoke* is {\em checked} only as part of \insnref{CInvoke}'s +operation on sealed (i.e., object) capabilities, it is inherited from these +sealed capabilities' precursors. That is, the present CHERI architecture +permits the creation of regions of virtual address space that can be +(subdivided and) sealed, but for which these derived object capabilities are +not useful with \insnref{CInvoke} (just with \insnref{CUnseal}). +The utility of such regions is perhaps not readily apparent, but any shift +to make \cappermCInvoke* apply only to object capabilities would require +modification of the \insnref{CSeal} instruction and would slightly +change the capability ontology. + +Within the virtual-address-specific permissions, one finds several +opportunities for compressing representations. First, many architectures +consider writable-and-executable to be too dangerous to permit; applying +this to CHERI's taxonomy would mean that the presence of \cappermX* implied +the absence of \cappermS*, \cappermSC*, and \cappermSLC* (see +\cref{app:exp:compressperm:wxorx}). Further, granting \cappermLC* +effectively implies granting \cappermL*: CLC and CLLC would trap without +the latter, but more substantially, a capability load of an un-tagged (in +memory or via the paging hardware) `should' result in a load of data +transferred in to a capability register, albeit with the tag cleared. On +the store side, \cappermSLC* implies \cappermSC*, which, in turn, implies +\cappermS*. Taking all of these implications into consideration, one finds +that there are $15$ consistent states of the six virtual-address-space +rights (\cappermX*, \cappermL*, \cappermLC*, \cappermS*, \cappermSC*, +\cappermSLC*) considered, enabling a four-bit compressed representation.% +% +\footnote{If one restricts consideration to just the five bits of +\cappermL*, \cappermLC*, \cappermS*, \cappermSC*, and \cappermSLC*, one finds 12 +valid states, requiring four bits. A straightforward reduced encoding then +leaves \cappermL* and \cappermLC* unaltered but can use two bits to indicate +which of $\emptyset$, \{\cappermS*{}\}, \{\cappermSC*, \cappermS*{}\}, or +\{\cappermSLC*, \cappermSC*, \cappermS*{}\} is present.} + +Consider the powerful \cappermASR permission. Because this +bit is meaningful only on capabilities used as a program counter, at the +very least its presence rather directly implies \cappermX. Moreover, +because this bit gates access to other architectural protection mechanisms, +including those, such as the paging hardware, involved in {\em interpreting} +(other) capabilities, it seems likely that this bit implies the ability to +at least read, and likely mutate (or cause the mutation of), any other +capability present in the system. (Admittedly, perhaps the ability to +synthesize new capabilities from whole cloth would remain beyond the reach +of code executing with \cappermASR*, but given the far-reaching +powers potentially conveyed, this hardly seems worth nitpicking.) As such, +one may be justified in considering \cappermASR* to be a single +value in one's encoding of capability permissions, rather than an orthogonal +bit. + +\subsection{A Worked Example of Type Segregation} % <<< + +Pushing a bit further on the `spaces of identifiers' concept above, we can +describe an alternative use of the 15 bits of {\cmuperms} available in the +128-bit encoding scheme of Section~\ref{subsec:cheri-128-implementation}. We +continue to leave the 18-bit \cotype{} field where it stands, and we claim no +new use of any reserved bits. Diagrams of the bit representations may be found +in Figure~\ref{fig:app:comprperm:typeseg}. + +In all capabilities, we reserve three bits for uninterpreted user +permissions, and four bits for the flow control detailed in +Section~\ref{sec:compactcolors}.% +% +\footnote{Absent the use of this experimental coloring scheme, these +reserved bits can instead be used to carry the \cappermG* and \cappermSLC* +bits, with two bits remaining reserved.} +% +One more bit distinguishes between virtual-address capabilities and all +other types. We have thus far consumed 8 of the 15 permission bits. + +For virtual-address capabilities +(subsequently to be abbreviated as `VA capabilities'), +the remaining seven bits correspond +one-to-one with memory-specific permissions. Specifically, they are: +\cappermX* (Ex), \cappermL* (L), \cappermS* (St), +\cappermLC* (LC), \cappermSC* (SC), \cappermCInvoke* (CC),% +% +\footnote{While any capability type can, in principle, be sealed and could be +unsealed at \insnref{CInvoke} time, \insnref{CInvoke} unseals only two +capabilities, installing them as PCC and IDC. As such, it seems sensible to +restrict \insnref{CInvoke} to operating only on VA capabilities, and so \cappermCInvoke is +defined only therein.} +% +and \cappermASR* (ASR). We have made no effort to +eliminate redundancy in this particular segment of the encoding, but all the +observations made above about these bits continue to hold. + +For non-virtual-address capabilities, we take one bit to distinguish +\emph{architectural control} capabilities from \emph{guarded-word} +capabilities. The latter are as might be expected: they are simply bounded (as +per usual with CHERI capabilities) \emph{integers}, protected by architectural +provenance, monotonicity, and nonforgeability. Guarded-word capabilities confer +no architectural authority, but may be of use to system software (e.g., for +describing file descriptors). The remaining six bits are all permission-like +(and are subject to manipulation via \insnref{CAndPerm}), but are +otherwise uninterpreted by the hardware.% +% +\footnote{It may seem odd to deliberately create architecturally `useless' +tagged integers; it may seem as though they could simply be VA capabilities +with all permission bits cleared. However, just because an agent has some +rights to memory address 0x1234 does not imply that they have rights to the +\emph{integer} 0x1234, but monotonic action on a capability authorizing the +former could result in one authorizing the latter in this hypothetical +`all-permission-bits-zero' encoding. The \emph{separate provenance tree} +of guarded-word capabilities distinguishes these: there is no monotonic +mechanism to transmute one into the other.} + +Architectural control capabilities include the ability to seal and unseal +particular object types, set the compartment identifier, and manipulate colors +(again, as detailed in Section~\ref{sec:compactcolors}). The remaining +six bits are, again, all permission-like. Three are reserved for future use +(not currently interpreted), while the other three correspond to the current +\cappermUnseal (U), \cappermSeal (Se), and \cappermCid (CID). No attempt +has been made to further refine the type space, so we continue to +architecturally conflate object types and compartment identifiers and rely on +system software to maintain proper partitioning. + +In this scheme, three primordial architectural roots should be created at +system reset: one for virtual addresses, one for architectural control, and +one for guarded words. All primordial capabilities should be unsealed, have +all defined and user permission bits asserted, and cover the full space of +their respective identifiers. + + +\begin{figure} +\small\centering\begin{tabular}{cl} + +\textbf{Type} & \textbf{Bit layout} \\ + +\raiseforbf{Virtual Address} & +{\begin{bytefield}[bitwidth=21pt]{15} + \bitbox{1}{1} & \bitbox{1}{ASR} & \bitbox{1}{CC} & \bitbox{1}{SC} & \bitbox{1}{LC} & \bitbox{1}{St} & \bitbox{1}{L} & \bitbox{1}{Ex} & \bitbox{3}{user perms'3} + \end{bytefield}} \\ + +\raiseforbf{Architectural Control} & +{\begin{bytefield}[bitwidth=21pt]{15} + \bitbox{1}{0} & \bitbox{1}{1} & \bitbox{3}{\color{lightgray}\rule{\width}{\height}} & \bitbox{1}{CID} & \bitbox{1}{Se} & \bitbox{1}{U} & \bitbox{3}{user perms'3} + \end{bytefield}} \\ + +\raiseforbf{Guarded word} & +{\begin{bytefield}[bitwidth=21pt]{15} + \bitbox{1}{0} & \bitbox{1}{0} & \bitbox{9}{user perms'9} + \end{bytefield}} \\ + +\end{tabular} + +\caption{Bit-level representations of a type-segregated metadata-bit-packing scheme.} +\label{fig:app:comprperm:typeseg} + +\end{figure} + +% >>> +\subsection{Type-segregation and Multiple Sealed Forms} % <<< + +\begin{figure} +\small\centering\begin{tabular}{cl} + +\textbf{Type} & \textbf{Bit layout} \\ + +\raiseforbf{Unsealed VA} & +{\begin{bytefield}[bitwidth=21pt]{15} + \bitbox{1}{1} & \bitbox{1}{0} & \bitbox{1}{0} & \bitbox{1}{ASR} & \bitbox{1}{CC} & \bitbox{1}{SC} & \bitbox{1}{LC} & \bitbox{1}{St} & \bitbox{1}{L} & \bitbox{1}{Ex} & \bitbox{3}{user perms'3} + \end{bytefield}} \\ + +\raiseforbf{Sealed VA} & +{\begin{bytefield}[bitwidth=21pt]{15} + \bitbox{1}{1} & \bitbox{1}{1} & \bitbox{1}{SV} & \bitbox{1}{ASR} & \bitbox{1}{CC} & \bitbox{1}{SC} & \bitbox{1}{LC} & \bitbox{1}{St} & \bitbox{1}{L} & \bitbox{1}{Ex} & \bitbox{3}{user perms'3} + \end{bytefield}} \\ + +\raiseforbf{Architectural Control} & +{\begin{bytefield}[bitwidth=21pt]{15} + \bitbox{1}{1} & \bitbox{1}{0} & \bitbox{1}{1} & \bitbox{4}{\color{lightgray}\rule{\width}{\height}} & \bitbox{1}{CID} & \bitbox{1}{Se} & \bitbox{1}{U} & \bitbox{3}{user perms'3} + \end{bytefield}} \\ + +\raiseforbf{Unsealed guarded word} & +{\begin{bytefield}[bitwidth=21pt]{15} + \bitbox{1}{0} & \bitbox{1}{0} & \bitbox{1}{0} & \bitbox{10}{user perms'10} + \end{bytefield}} \\ + +\raiseforbf{Sealed guarded word} & +{\begin{bytefield}[bitwidth=21pt]{15} + \bitbox{1}{0} & \bitbox{1}{1} & \bitbox{1}{0} & \bitbox{10}{user perms'10} + \end{bytefield}} \\ + +\raiseforbf{Reserved} & +{\begin{bytefield}[bitwidth=21pt]{15} + \bitbox{1}{0} & \bitbox{1}{\color{lightgray}\rule{\width}{\height}} & \bitbox{1}{1} & \bitbox{10}{\color{lightgray}\rule{\width}{\height}} + \end{bytefield}} \\ + +\end{tabular} + +\caption{A variant of packed metadata including multiple sealed forms.} +\label{fig:app:comprperm:typeseg2} + +\end{figure} + +\pgnnote{I would like to declare war on the gratuitous comma +`adjective, adjective noun' as in `small, sealed memory objects' -- + `small' can refer only to `memory objects', not to `sealed'} +Experiments with CheriOS have found that the increased alignment requirements +for sealed capabilities induced by the original 128-bit compressed format are +awkward (recall Section~\ref{subsec:cheri-128-implementation}). In particular, +there is a desire to pass small sealed memory objects, with size (and so, +ideal alignment) well below the requisite alignment size for sealing. +Subsequent work has defined a different CHERI Concentrate form with a dedicated +\cotype{} field, no need of a sealed bit, and no increased alignment +requirements to make room or the \cotype{} bits. And so, the remainder of this +subsection is largely mooted: all capabilities may be sealed in the new CHERI +Concentrate format. We retain it in this document for interest and its +possible applicability to implementers considering different capability +encoding options. + +The small objects passed by CheriOS are never sealed as interior pointers. +That is, the sealed forms are guaranteed to have offset zero (i.e., equal +cursor and base addresses). This permits 10 bits of the B field to be +transferred to the T field, offering much smaller alignment requirements. +(Byte alignment remains possible until objects approach 1 mibibyte in length. +Offsets need not be zero, but must be small, in the sense that they must be +below $2^{\mathbf{e}}$.) The experimental architectural encoding presently +requires stealing one of the two bits described in this document as reserved +within a capability representation. Given the possible utility of this +additional sealed form to the other provenance trees discussed above, it seems +worthwhile to present a possible unified story. + +For this example, we drop the ability to seal architectural control +capabilities, as we do not think these will be passed as tokens; instead, we +believe, should system programmers desire similar policies, they are free to +indirect, i.e., to place architectural control capabilities into small +regions of memory, seal the rights thereto, and pass that sealed capability +instead of a sealed architectural control capability. +This further removes concerns around the encoding of \cotype{}s and capability +color changing permissions (to be discussed). + +This illustrative +encoding uses 17 bits: 15 from the former \cmuperms{}, 1 from the +former sealed flag, and 1 formerly reserved. Bit-field representations are +shown in Figure~\ref{fig:app:comprperm:typeseg2}. For VA capabilities, the new +`Sealed Variant' (SV) flag, which is not a permission bit (and so not subject +to manipulation by \insnref{CAndPerm}), distinguishes between the form with +both T and B specified and the form with only T specified. We expect an +architecture using this form to have two \insnref{CSeal}-like instructions, +each generating one of the variants. For sealed guarded-word capabilities, we +permit only the latter form, as we believe sealed guarded words are more likely +to be used as tokens than as regions of integers. One-fourth of our type +encoding values are reserved for future expansion. + +% >>> +\subsection{\texttt{W\textasciicircum{}X} Saves A Bit} % <<< +\label{app:exp:compressperm:wxorx} + +\texttt{W\textasciicircum{}X} (`W xor X') is a shorthand for the notion +that no block of memory should be, at the same time, both writable and +executable. Most implementations in hardware work within the MMU, and rely +on the operating system to enforce the exclusivity of write and execute +permissions. From the view of application software, this means that a given +pointer value has additional hidden state beyond its being mapped or +unmapped. Applications on CHERI could, instead, structure the permissions +within capabilities to enforce exclusivity of write and execute permissions, +trading the stateful MMU protection for having multiple capabilities +representing the two different rights. + +Were we to push \texttt{W\textasciicircum{}X} on CHERI to an extreme, +it could become a property of the capability encoding itself and, thereby, +allow for more compact encoding of permissions. The existing eight-bit +architectural permission field, + +\begin{center} +% +{\begin{bytefield}[bitwidth=25pt]{8} + \bitbox{1}{ASR} & \bitbox{1}{CC} & \bitbox{1}{SLC} & \bitbox{1}{SC} & \bitbox{1}{LC} & \bitbox{1}{St} & \bitbox{1}{L} & \bitbox{1}{Ex} + \end{bytefield}} +% +\end{center} + +\noindent could instead be re-coded as a 7-bit field, making the +\texttt{W\textasciicircum{}X} explicit: + +\begin{center}\begin{tabular}{rl} +% +\raiseforbf{RX capability:} & +{\begin{bytefield}[bitwidth=25pt]{8} + \bitbox{1}{0} & \bitbox{1}{CC} & \bitbox{1}{\color{lightgray}\rule{\width}{\height}} & \bitbox{1}{ASR} & \bitbox{1}{LC} & \bitbox{1}{Ex} & \bitbox{1}{L} \\ + \end{bytefield}} \\ +% +\raiseforbf{RW capability:} & +{\begin{bytefield}[bitwidth=25pt]{8} + \bitbox{1}{1} & \bitbox{1}{CC} & \bitbox{1}{SLC} & \bitbox{1}{SC} & \bitbox{1}{LC} & \bitbox{1}{St} & \bitbox{1}{L} + \end{bytefield}} +% +\end{tabular}\end{center} + +As in the type-segregation proposals, this design creates yet another split +of architectural provenance roots: there must be two capabilities present at +system startup, granting separate read-write and read-execute regions. +Similarly, a single capability then could not express the total set of +permissions that may be granted by, e.g., the *nix \texttt{mmap()} call; the +API and consumers must be revised. (One hopes that relatively few consumers +initially request (or later transition, via \texttt{mprotect()}, to having) +both write and execute permissions.) It is not yet clear what additional +challenges this split imposes on our goal of C compatibility. + +There is some redundancy yet in this encoding, in that either RX or RW +capabilities can be monotonically turned into read-only capabilities. One +could imagine further segregation into a +\texttt{R\textasciicircum{}W\textasciicircum{}X} taxonomy, but this seems +especially likely to complicate C compatibility. Moreover, the obvious +utility of RW capabilities and popularity of data constants adjacent to +executable code (and thereby reachable using relative offsets from the +instruction pointer) argue for permitting read permissions in both write and +execute forms. + +When and if combined with the compact coloring proposal below, the +\cappermSLC (SLC) bit and its unused slot in the RX form +would vanish. + +% >>> +% >>> +\section{Memory-Capability Versioning} % <<< +\label{app:exp:versioning} + +Several existing architectures have responded to temporal safety issues in +software by proposing to `version' memory, embed versions into pointers, +and require that the versions of the pointer and target match on each +dereference. Two prominent examples are Oracle's SPARC's ADI/SSM +\cite{sparc-m7-adi} and Arm's MTE~\cite{arm-a64-v8-a-beta}. We conjecture +that the combination of these ideas with CHERI would enhance both and continue +to have reasonable performance overheads. Between these mechanisms, we can +offer an attractive secure mitigation of temporal safety violations in +untrusted code. + +Specifically, we propose to embed a four-bit version field% +% +\footnote{There is nothing special about the value four; even a one-bit +versioning scheme has practical utility, while more bits reduce likelihood of +collision in stochastic schemes and delay revocation in deterministic schemes +(see \cref{app:exp:versioning:syssoft}). Four simply seems to be a popularly +acceptable value.} +% +in every memory-authorizing capability, either using reserved bits or by +shrinking the address field from 64 to 60 bits.% +% +\footnote{Practically, most modern systems do not make use of their entire +64-bit virtual address space and require that all such addresses be +sign-extended values derived from (typically) 40-bit to 57-bit values, +depending on the architecture. We can therefore repurpose some of these bits +with only modest, localized changes to system software.} +% +Further, we pair the same number of bits of version with each `granule' of +physical memory, which we suggest to be roughly 64 bytes. (The proposed values +give a spatial overhead equivalent to CHERI's capability tags: one bit per 16 +bytes.) To ensure that untrusted code cannot inappropriately re-version memory +granules, we provide a simple model of authorization that does not require the +intervention of supervisor software. + +We divide memory-authorizing capabilities into two classes, versioned and +unversioned, and introduce an instruction that derives a versioned capability +from an unversioned one. The core of this protection mechanism is this: if a +versioned capability is used to access a granule, the access succeeds only if +(in addition to passing the existing CHERI permissions and bounds checks as +well as any MMU permissions checks) the granule and intra-capability versions +are equal. In the case of mismatch, an implementation must, at a minimum, +cause data fetches to return $0$, capability fetches to return untagged NULLs, +stores to fail silently, and instruction fetches to trap. To improve the +debugging experience, implementations may provide optional or mandatory traps +on these fetch and stores as well. + +Only unversioned capabilities can authorize the re-versioning of memory +granules. Additionally, unversioned capabilities authorize access regardless +of the version of the granule being accessed. We expect that these will become +closely held within subsystems that then exchange derived versioned +capabilities with other subsystems; the canonical example is, of course, memory +allocators, which will hold unversioned capabilities internally and give out +(and take back) versioned capabilities. + +Versions are `sticky,' in that any capability monotonically derived from a +versioned progenitor will have the same version. Dually, derivations from +unversioned capabilities are unversioned, unless the version is explicitly +branded into the progeny. + +\subsection{Legacy Memory Versioning Behaviors} % <<< + +When adding CHERI to an architecture that already has memory versioning support +(e.g., SPARC or Arm), it may be desirable to retain compatibility with existing +mechanism in hybrid or legacy code. That is, we may wish, assuming the system +has enabled memory versioning and has provided a non-NULL DDC, for legacy +(i.e., integer pointer using) load and store instructions to continue to +specify the intended memory version and legacy version manipulation +instructions to continue to function. (Recall that all such legacy +instructions have their integer addresses interposed by DDC.) + +We therefore propose that the interposed integer offsets arising from legacy +instructions be interpreted subject to existing architectural address handling +rules. Arm's MTE, for example, requires the use of Top Byte Ignore (TBI), +which partitions the 64-bit address into an 8-bit metadata field and a 56-bit +address; we propose that Arm processors with CHERI and MTE continue to claim +the top 8 bits of any integer offset within a capability as a metadata field.% +% +\footnote{Because integer offsets often come about through arithmetic, which +may not be aware of the 8+56 partition in the semantics of the bits being +manipulated, it may be useful to slightly tweak the encoding of versions. +Instead of directly taking the top 8 bits as the source of the version value, +it may be useful to XOR them with the top bit of the remaining 56-bit offset. +Thus, the 64-bit 2's-complement values of 1 and -1 would be interpreted as +56-bit 1 and -1, respectively, but both with a version field of zero.} +% +When combined with an \emph{unversioned} capability, the integer offset +specifies the memory version used for a memory transaction; a \emph{versioned} +capability instead overrides the requested version from the offset.% +% +\footnote{As memory transactions are already opportunities for traps in most +architectures, it may be worth trapping if the integer offset calls for a +non-zero version field in combination with a versioned capability. On the +other hand, it is likely acceptable from a security policy perspective if the +discrepancy is ignored.} +% +This policy may also be applicable to \emph{capability-authorized} instructions +with integer offset register operands, which may simplify capability-aware +supervisory software that must operate on versioned integer addresses. (It +seems unlikely that there is utility to permitting offset \emph{immediate} +operands to influence memory version fields.) + +% >>> +\subsection{Instructions} % <<< + +\begin{itemize} + + \item \insnnoref{CStoreVersion} sets the version bits of a memory +granule to the value given in a register operand; the authorizing capability +must be unversioned and must authorize stores of both data and capabilities +to the entire target granule. Setting the granule's version to $0$ will +cause it to be accessible only to unversioned capabilities. + + \item \insnnoref{CFetchVersion} fetches the version bits of a memory +granule; the authorizing capability must be unversioned, and must authorize +data fetches from the entire target granule. A return of $0$ indicates that +the granule is accessible only via unversioned capabilities. + + \item \insnnoref{CGetVersion} copies the version field of a +capability into a register. It is useful mostly for debugging and for +maintaining an abstract interface to capabilities despite the encoded form +bits' being accessible to software. + + \item \insnnoref{CSetVersion} derives a versioned capability from an +unversioned capability and a version value from a register operand. +Attempting to set the version to $0$ will trap. No other fields are +modified in the derived copy. Attempting to make a versioned capability +from a versioned one may succeed only if the desired and existing versions are +equal, otherwise the result will have its tag cleared.% +% +\footnote{It may be sensible to always clear the tag or always trap, as +well. We do not have a use case for the tagged result when-equal case.} + + \item \insnnoref{CLoadVersions} loads version fields for an +entire cache-line of memory granules into an integer register, akin to +\insnref{CLoadTags}. It is intended as an optimization for system software +paging virtual memory. + +\end{itemize} + +\subsubsection{Atomics} % <<< + +In addition to the above, we desire a means for \emph{atomic} update of the +version of a memory granule (as well as up to a capability-sized word within +it). Unfortunately, our desires brush up against (micro)architectural limits. +A version-manipulating, capability-sized (and -aligned) store-conditional +instruction, for example, should take four operands: +% +\begin{inenum} + + \item an unversioned capability authorizing access to the target, + + \item the data/capability to store to memory, + + \item the desired new version, and + + \item the destination register indicating success or failure of the store. + +\end{inenum} +% +However, it is challenging to fit so many register indices into a single +instruction and this may also exceed the port availability of the processor's +register file. (A general compare-and-swap instruction is even worse, adding +both the expected value of memory and the expected memory version.) +% +With these constraints in mind, we propose two possibly feasible subsets: +% +\begin{itemize} + + \item \insnnoref{CSCAndUnversion} takes an unversioned memory +capability authorizing the store, a capability register to store, and the +output register. (It is, therefore, rather like an ordinary +\insnref{CSC}.) It fixes the desired new version to the unversioned value. +Thus, on successful store, the memory version granule is inaccessible to any +versioned capability, and the same authority used with this instruction can be +used with \insnnoref{CStoreVersion} to subsequently update the target +granule's version. + + \item \insnnoref{CSCWithVersion} is similar, but reads the desired +version \emph{from the output register} before storing back the success +indication. This works around the encoding space problem, but may still +require an excess of access to the register file. +% +\nwfnote{Cross-reference the behavior of \insnnoref{SC.C.CAP} and +friends, which store back to one of their inputs. I didn't find a convenient +chunk of prose to point at.} + +\end{itemize} + +% >>> +% >>> +\subsection{Use With System Software} % <<< +\label{app:exp:versioning:syssoft} + +We envision that software will make use of memory versions +\emph{monotonically}. That is, versions of memory granules will be altered to +revoke \emph{all} access by any existing versioned capability inclusive of that +granule rather than to \emph{restore} access at some earlier version. Thus, we +believe that \insnnoref{CSCAndUnversion} is sufficiently atomic for +software's needs. Despite the observable transition of the granule to an +unversioned state before any subsequent transition to a version not yet held +anywhere in the system, the net authority in the system remains the same. + +Because there are only finitely many versions available, we further envision +that the \emph{system software} will provide a \emph{revocation} mechanism (in +the style of Cornucopia \cite{cornucopia}) to de-tag or otherwise remove +authority from all capabilities with mismatching versions. To minimize the +testing required by this facility, it will test only the granule containing the +\emph{base} of each versioned capability it encounters; software engaging in +version-based revocation should, nevertheless, re-version all (partially) +contained granules so that derived capabilities with offset bases are also +revoked. In a sense, granules exist because they are a sufficient and +straightforward mechanism to capture spans of version information, not because +we expect individual granules within a single segment authorized by a +capability to be changed. Dually, objects with different lifetimes should not +share granules; this results in much stronger alignment requirements for +allocators, but the practical impact remains to be measured. + +We do not specify the shape of the interface exposed for this facility; a +traditional system call to the (privileged) kernel is one possibility for +implementation, but more `autonomic' approaches are feasible as well. We +envision a global `epoch' counter maintained by the kernel, stepping after +every revocation pass. If software remembered the counter's value at the time +each allocation came to have its current version, that software would know when +all capabilities with their base in that allocation and of the wrong version +had necessarily been destroyed: in the second epoch after re-versioning. Such +a scheme would permit sharing work across many allocators desiring revocation +within the same address space. + +Because revocation may be done in the background, versions are intended to +be used once between revocations. That is, software should not assume that +it can restore an earlier version to re-authorize an existing capability, +because at any moment the mismatched capability may have become de-tagged. + +Whereas we conjecture that the minimum requirements given above for mismatched +versions for loads and stores are sufficient to eliminate temporal safety +issues, there remains the possibility of apparently \emph{inducing} bugs in +programs running under our new semantics. For example, if software attempts +to (re)initialize an object using a stale capability, the memory will not be +updated and may be reused in inconsistent state. Trapping on version +mismatch would better expose such issues. + +% >>> +\subsection{Microarchitectural Impact} % <<< + +The cache fabric must now store the version of each granule in each cache line +(which, in the proposal above, is one, given 64-byte cache lines). +Dereference operations must forward the capability's version field down to +the cache fabric as well. The minimum requirements for version mismatch +are, however, intended to remove the need to track store requests through +the memory hierarchy. While precise traps on stores would require +essentially a full read-modify-write cycle, the cache fabric may be able to +raise \emph{imprecise} traps well after accepting a store by tracking the +tentative version bits until they can be checked against the authoritative version +table. + +% >>> +% >>> +\section{Linear Capabilities} % <<< +\label{section:linear-capabilities} + +Linear capabilities are intended to support the implementation of +operating-system and language-level linearity features, which ensure that at +most one reference to an object is held at a time. +This feature might be used to help support efficient memory reuse -- e.g., by +requiring that a reference to stack memory be `returned' before a caller is +able to reuse the memory. +Architectural linearity does not prevent destruction of the reference, which +may require slow-path behavior such as garbage collection, but can support +strong invariants that would help avoid that behavior in the presence of +compliant software. +This architectural proposal has not yet been validated through +implementation in architecture, microarchitecture, or software. + +\subsection{Capability Linearity in Architecture} + +We propose to add a new bit to the capability format marking a capability as +\textit{linear}. +% +\note{Because the ISA permits overwrites of linear capabilities (in both +registers and memory), the more appropriate moniker +from substructural logic would be `affine', rather than `linear'. It +may be worth calling this out in the prose, but not worth renaming +everything.}{nwf} +% +It could be that this is a permission (e.g., Permit\_Non\_Linear). +However, as this +feature changes a number of other aspects of capability behavior, we recommend +not conflating this behavior with the permission mechanism, instead adding a +new field. + +Two new \textit{linear move} instructions would be added: + +\begin{description} +\item[Linear Load Capability Register (\insnnoref{LLCR})] +This instruction loads a capability from memory into a register, atomically +clearing the memory location [regardless of whether it loaded a linear +capability?]. +\note{Clear the whole word or just the tag?}{nwf} + +\item[Linear Store Capability Register (\insnnoref{LSCR})] +This instruction stores a capability from a register into memory, atomically +clearing the register when a successful store takes place (e.g., if it does +not trigger a page fault) [regardless of whether it stored a linear +capability?]. +\end{description} + +The reason to introduce an explicit +linear +load is to avoid taking the cost of an +atomic operation for every capability load dependent on whether the loaded +capability is linear. +% +\note{A non-linear load of a linear capability results in an untagged +register?}{nwf} +% +A separate linear store instruction is not motivated by this concern, but +would add +symmetry, avoiding the need for store instructions to vary their behavior +based on capability type. + +A new Permit\_Linear\_Override permission is added, which controls how +existing capability load and store instructions (e.g., \insnref{CLC} and +\insnref{CSC}) interact with linear capabilities. +If the permission is not present, then loaded linear capabilities will have +their tag cleared when written into a register, and stored linear +capabilities will have their tag cleared when written to memory. +This behavior maintains linearity without changing the register or memory +write-back behaviors of these instructions. + +If Permit\_Linear\_Override is present on the capability being used to load or +store non-linear capabilities, then linearity is violated, allowing both the +in-register and in-memory capabilities to continue to be valid and marked as +linear. +This permission allows for privileged system software to violate linearity +when, for example, implementing mechanisms such as Copy-on-Write (COW) in the +the OS virtual-memory subsystem or debugging features. + +To save instruction encoding space, we might limit these memory access +instructions to be R-type with only a register-specified offset. This +may be adequate if the instructions are infrequently used. + +For register-to-register instructions, there are several options -- in +particular, when implementing capability-manipulation instructions such as +\insnref{CIncOffset} and \insnref{CSetOffset}: + +\begin{itemize} +\item We might make existing instructions remove the tag in register write + back for linear capabilities, enforcing linearity by preventing duplication + of linear capabilities. + +\item We might require that, when existing instructions operate on linear + capabilities, they write back to their source register, enforcing linearity + by avoiding duplication to a second register. This might be + simplest microarchitecturally. + +\item We might add new explicitly linear variants of some existing + instructions, which would enforce linearity by clearing the source register, + preventing duplication. +\end{itemize} + +In general, ensuring write-back to the same register is easy and cheap to +check dynamically; it avoids the need to introduce a large number of new +instructions offering near-identical behavior. +It also avoids increasing the number of registers that must be written back +by instructions. + +Additional concerns exist around the implementation of \PCC{} as relates to +\insnref{CGetPCC}, which normally duplicates a capability. +Although undesirable, the natural design choice is to strip the tag when +writing to the target register, if \PCC{} is linear. + +\subsection{Capability Linearity in Software} + +The above architectural behavior means that, on the whole, software must +be aware when handling linear capabilities; code must be generated +specifically to use new linear load and store instructions, and to utilize +other register-to-register instructions in a manner consistent with linearity. +There are several specific implications that must be taken into account +when writing system software or compilers: + +\begin{itemize} +\item Linear capabilities must be explicitly identified via the source + language -- e.g., via types or qualifiers -- so as to guide code generation. + It might be desirable to utilize techniques such as symbol mangling to + prevent accidents. + +\item Linear values cannot be properly preserved by ordinary stack loads and + spills, so the compiler must take explicit action to prevent this from being + necessary. + This might also require static limitations on use of capabilities in the + language. + +\item When linear capabilities are used and manipulated as pointers, it may be + necessary to generate code quite differently, or to limit expressiveness. + For example, implied pointer arithmetic when iterating using a pointer + requires that the original pointer be destroyed, or that the pointer be + left unmodified but accessed using an integer-register index. + It is not yet clear to what extent this would interact with common C-language + idioms. + +\item Some systems code must be linearity-oblivious, such as context-switching + or VM code, and can employ Permit\_Linear\_Override to load and store + ordinary and linear capabilities using non-linear loads and stores. + However, it must assuredly not violate invariants of affected software, or + else linearity may not be enforced. + +\item Many current C-language OS and library APIs may be linearity-unfriendly, + as they frequently accept an existing pointer as an argument, but do not + `return' it to the caller. + It may be desirable to have a specific set of extended APIs that are + linearity-friendly -- e.g., variants of \ccode{memcpy} that copy data into + and out of linearly referenced memory. + It is unclear + whether this would extend to a broader suite of APIs, such as OS \ccode{read} + and \ccode{write} system calls -- and perhaps would imply polyinstantiation. + +\item Debugging tools would need to become aware of linearity so as to + accurately display information about linear capabilities found in registers + or memory. + They might use Permit\_Linear\_Override to gain access to the full contents + of the register with tag, but must still inspect capability fields suitably, + and avoid the need to spill values. + It is not clear how this would interact with current debugger internals. +\end{itemize} + +In general, when linearity is violated, it will lead to loss of tags, +preventing dereferences that violate invariants. +It is not clear to what extent this would be easily debuggable. +We can imagine having non-linear sequences generate an exception, +but in some cases this may be microarchitecturally awkward. + +Overall, it is not clear to what extent this proposal can interact well with +real-world software designs, or to what extent it usefully supports new +software behaviors. +Key use cases motivating this design typically involve garbage collection +avoidance: e.g., passing an stack pointer across protection-domain boundaries +and checking that it is `returned' before continuing, avoiding the need for +a GC to sweep the recipient domain. +But this does not necessarily alleviate the need to implement more complex +behaviors such as GC in the event that the invariant is violated. + +\subsection{Related Work in Linear Capabilities} + +Skorstengaard et al.~have concurrently developed ideas about linear +capabilities~\cite{Skorstengaard:2019:stktokens}, which focus on how to +produce a memory-safe execution substrate over a CHERI-derived abstract +capability instruction set. They are able to use linear capabilities to +construct a temporally safe stack calling convention against the model. +This allows formal proof of well-bracketed control flow and stack-frame +encapsulation. However, their approach also relies on two further +instructions not present in our current sketch: capability split and splice +instructions allowing linear capabilities for stack subsets to be separated, +delegated, returned, and rejoined. It is not yet clear to us whether these +additional instructions are microarchitecturally realistic, especially in +the presence of compressed capabilities. + +\nwfnote{The `splice' instruction of~\cite{Skorstengaard:2019:stktokens} has +potential interactions with sweeping revocation. The latter depends on a +strict hierarchical partitioning of memory, in which the allocator/revoker +can be certain that there are no capabilities that partially overlap the +regions it revokes. Permitting splicing of arbitrary linear capabilities +violates this assumption: splice a linear capability at the upper end of one +allocation +together with +one at the lower end of the adjacent, successive allocation. +Allocators +could prevent this by ensuring gaps between +allocations, +or the system can enforce restricted joins of linear capabilities via a +single architectural bit to indicate that a capability is the lowest result +of a series of splits. When splitting, if this bit is clear in the input, +then leave it clear only in the lower result; if it is set in the input, +leave it set in both outputs. When splicing, enforce that either both bits +are set (and leave it set in the result) or that the lower is clear and the +upper is set (and leave it clear in the result). When initially allocating +a segment, clear the bit. The effect is to enforce the tracking of the +lowermost capability arising from a series of splits and preventing it from +being spliced with a yet-lower linear capability, which will either be an +initial allocation (bit clear) or the upper result of a split (bit +set).} +\pgnnote{This seems REALLY PIGGY.} +\nwfnote{I am not sure what that means.} + +The creators of the SAFE architecture~\cite{chiricescu2013safe} also propose +that \textit{linear pointers} could contribute to reasoning about concurrent +memory use. + +% >>> +\section{Indirect Capabilities} % <<< +\label{section:indirect-capabilities} + +Indirect capabilities could support revocable or relocatable objects without +modification of application executables. +An indirect capability would be identified by the hardware as a pointer to the pointer +to the data. +That is, a load that takes as an address a capability that is marked as an +indirect capability would load a capability from the base address of the +indirect capability, and then would apply any offset to the loaded capability +before dereferencing and placing the returned data in the destination register. +Therefore, a single load that finds an indirect capability as its address would +perform two loads, a pointer access, and then a data access. + +\subsection{Indirect Capabilities in Architecture} + +We propose to add a new bit to the capability format, marking a capability as +\textit{indirect}. +We recommend +not conflating this behavior with the permission mechanism, instead adding a +new field. + +One new instruction would be added: + +\begin{description} +\item[Make Indirect (\insnnoref{CMI})] +This instruction makes an ordinary capability into an indirect capability +such that any future dereference will effectively dereference the capability +pointed to by this indirect capability. +The bounds of the capability must be at least the size of one capability, +and will be effectively truncated to this length by \insnnoref{CMI}, +though the original bounds will be preserved and applied to the +pointer on data access. + +\end{description} + +The \insnnoref{CMI} instruction makes a capability indirect, but no +instruction can make an indirect capability direct again. +As a result, delegating +an indirect capability does not +delegate access to the pointer that is dereferenced, but only to the data being +pointed to. + +Capability-manipulation instructions such as +\insnref{CIncOffset} and \insnref{CSetOffset} +would transform the offset of the indirect capability, +but this offset would be applied to the pointer on data access. +The pointer access will always use the base of the indirect capability. +In addition, \insnref{CSetBounds} will transform the bounds of the indirect +capability, but these bounds will be applied to the pointer on data access. +The final access must be both within the length of the indirect capability, +which may contain program-narrowed bounds, and the bounds of the object pointer. +The bounds of the indirect capability would be implicitly the size of one +capability, and would not need to be stored. +This behavior allows pointer arithmetic to work as expected on indirect +capabilities, to allow programs expecting standard capabilities to work +unmodified. + +\subsection{Indirect Capabilities in Software} + +The above architectural behavior means that, on the whole, that software need +not be aware when handling indirect capabilities, but only code that performs +allocation or delegation would construct indirect capabilities, maintaining +pointer tables. + +Indirect capabilities might be used for general revocation between compartments. +A buffer passed to another compartment could be passed as an indirect +capability, +with a word allocated by the caller to hold the pointer. +On return, this pointer capability will be invalidated, and no further use +of the indirect capability will succeed. + +Indirect capabilities might be used to achieve memory safety for the heap in C. +Every allocation could return an indirect capability, and generate a new entry +in a pointer table. +A call to free would invalidate the entry in the pointer table, and memory could +be reused immediately with a new allocation in the pointer table. +Sweeping revocation may eventually be necessary to free virtual memory space +consumed by freed segments of the pointer table. + +Indirect capabilities might be used for a copying garbage collector. +Relocation of allocated objects would be facilitated by all references being +indirected through a single pointer. +When an object is moved, a single pointer could be updated. +While an object is being moved, the pointer could be made invalid, with any +use causing a trap that could be caught and handled appropriately. + +% >>> +\section{Indirect Sentry Capabilities} % <<< +\label{app:exp:indsentry} + +While sentry capabilities facilitate the construction of capabilities +that grant the right to run code from a fixed entry point, if that code is +intended to run in a particular (register) context, software must use +trampolines (e.g., the PLT stubs) to ensure that this context is constructed +correctly. These trampolines must intermingle data and code, as the trampoline +has amplified access, relative to its caller, only to the region of its +instruction pointer. The trampolines must, as well, be \emph{per-context} +(e.g., library instance), which necessitates duplication of the trampoline code +sequence for each context. + +\subsection{Points-to-PCC} % <<< + +Herein, we propose yet another architecturally-understood form of sealed +capability, the \emph{indirect} sentry capability, which is a curious +hybrid of a sentry capability (of \cref{sec:arch-sentry}) and a special +case of an indirect capability (recall \cref{section:indirect-capabilities}). +Where sentry capabilities point directly at the code to be run (and +expose the entire region bounded by PCC to the callee), these indirect +capabilities point at a capability to be installed into PCC (which, in turn, +points to the code to be run). Upon invoking such a capability, it is unsealed +and installed into the IDC (capability) register and the pointed-to capability +is installed into PCC; thereby, the callee is granted access to both regions of +memory.% +% +\footnote{If this pointed-to capability is, itself, a sentry capability, +it should be unsealed as part of the load into PCC. We do not currently +believe that \emph{requiring} this capability to be a sentry capability +has any meaningful impact on the security properties of the system, and so we +do not.} +% +The unsealing and IDC register writeback is not separable from the load from +memory and change of PCC: either both registers are updated and the instruction +completes, or neither are updated and the instruction traps. We propose a +\insnref{CInvoke}-like, single-operand instruction for such invocations, +\insnnoref{CInvokeInd}; we intend this to be a separate instruction from +\insnref{CJR} so that there is no need for a conditional load in the +microarchitecture. We do not envision a version of \insnnoref{CInvokeInd} +that writes a link address, but see below for discussion of making function +calls and returns with \insnnoref{CInvokeInd}. + +Any capability authorizing capability load may be made into a sealed indirect +entry capability, for which we propose reserving the \cotype{} $2^{64} - 4$.% +% +\footnote{While we do not anticipate comingling code and data within the +authorized region, we do not see much benefit in enforcing a lack of +\cappermX on the original capability nor in shedding it as part of +sealing. +% +\nwfnote{If we get really tight on encoding space, we could use \cappermX +to distinguish between sentry and indirect sentry capabilities both with +\cotype{} $2^{64} - 2$.} +% +} +% +A new, two-operand instruction is required for this action, which we call +\insnnoref{CSealIndEntry}. + +It is straightforward to adapt the designs of \cref{sec:arch-sentry} to this +instruction so that, for example, the PLT stub \emph{code} can be relocated to +the common, read-only section, leaving a kind of data-only trampoline which +contains capabilities to the (also shared) code to be run and the per-instance +RW data. Each entrypoint requires one capability, rather than a full PLT stub. +This enables unifying the per-instance PLT stub and per-instance data regions +into a single per-instance region which continues to not need execute +permission. + +Additionally, this mechanism could be suitable for decreasing the information +exposure between caller and callee functions. If, rather than exposing a return +(sentry) capability to the callee, the caller were to spill its return +capability to the stack and expose a sealed indirect entry capability derived +from the stack, the callee can have its access to the caller's stack completely +removed. Upon return, the caller's original stack capability would be +available in IDC. Spilling the return address will involve storing a +capability derived from PCC but pointing past the \insnnoref{CInvokeInd} +instruction. All told, we expect this kind of function call to require ten +instructions on call rather than the one \insnref{CJALR}: +% +\begin{itemize} + + \item three (\insnref{CGetPCC}, \insnref{CIncOffsetImm}, + \insnref{CSC}) to compute and spill the return address, + + \item two to move the stack pointer + (\insnref{CRepresentableAlignmentMask}, + \insnref{CAndAddr}), + + \item four to bound the stack pointer (\insnref{CGetOffset}, + \insnref{CSetOffset} (to zero), \insnref{CSetBounds}, + \insnref{CSetOffset} (back)), + + \item one to seal indirect sentry capability into the link register + (\insnnoref{CSealIndEntry}), and + + \item one to transfer control (\insnref{CJR} or + \insnnoref{CInvokeInd}). + +\end{itemize} +% +There is likely opportunity for additional, specialized instructions here; +some plausible examples include: +% +\begin{itemize} +% + \item An instruction which set the \emph{limit} (i.e., $\cbase + + \clength$) of a capability to the cursor and left the base alone could + replace the four instruction sequence bounding the stack pointer. +% + \item \insnref{CRepresentableAlignmentMask} and \insnref{CAndAddr} + could be fused into a dedicated instruction for aligning the capability's + offset appropriately. +% +\end{itemize} + +% >>> +\subsection{Points to Pair} % <<< + +Another option, for architectures open to multi-word transactions in their +memory subsystems, is an indirect sentry capability which points to the pair of +PCC and IDC. Invocation of such a sentry performs two capability loads through +an ephemeral (architecturally invisible), unsealed copy of the given sentry and +then, with both capabilities in hand, installs both into the register file +atomically. There is no requirement that the two capabilities pointed at be +sealed. Because these capabilities reside in memory, the instruction +constructing these ``points to pair'' indirect sentries likely cannot perform +any validation on their contents. + +% >>> +% >>> +\section{Anti-tamper Seals} +\label{sec:anti-tamper} + +When implementing allocators such as the C language's malloc and free, +it is common to require that the caller only pass values to free that +were previously returned to malloc (according to ISO C, doing otherwise +is undefined behavior.) +As is typical of C, run-time programmers exploit this and do not perform +checks that the passed pointer is in fact an allocated pointer and the +implementation may not retain sufficent information to confirm this. +We could greatly reduce the number of check in the free path if we could +be certain that the passed capability was exactly the one we handed out. + +To address this need, we propose a new variant of sealing: anti-tamper seals. +A portion of the otype space would be reserved for anti-tamper seals +and capabilities sealed with an anti-tamper otype would have the following +properties: +\begin{itemize} + \item The capability can be dereferenced or jumped to as though it were + unsealed. +% + \item Address modifying instructions (e.g. CSetOffset) work as though + the capability where unsealed. +% + \item CAndPerm, CSetBounds, and CSetBoundsExact unseal the capability + (setting its otype to -1). + \bdnote{Other capability derrivation instructions require evaluation...} +\end{itemize} + +The justification for allowing address adjustments is similar to that +for allowing capabilities to stray out of bounds. +We want to allow for the case that a programmer alters the address +of a capability before restoring its address using some seperate state +(e.g. buffer length) and freeing it. +It's unclear how common such code is, but intuitively such patters +will be difficult to detect statically. + +% >>> +\section{Compact Capability Coloring} % <<< +\label{sec:compactcolors} + +\note{CInvoke presents an interesting challenge, generally, when we desire to +restrict capability flow: the colors of the sealed capabilities authorizing +CInvoke, the current PCC, and any argument capabilities to be passed must be +sensible to the calling domain (which holds them, of course, prior to the +CInvoke), but will become visible in the callee domain. This suggests that +callees must have some private, suitably colored region of memory whither to +spill whatever colors come their way. This further suggests, perhaps, that +the assignment of semantics to individual colors may not be as unconstrained +as desired, as the decisions are not confined to particular security +domains.}{nwf} + +As noted above, the \cappermG permission described in the model of +Section~\ref{sect:capability-permission-bits} is semantically not parallel +to the other permissions. It is a one-bit attribute of the capability +itself, a concept we term a \emph{color}, borrowing from the +information-flow +analysis community~\cite{Popek79}. Capabilities without the \cappermG +color (called Local) have their \emph{flow} constrained, in that they can +be stored only through a capability (of any color) bearing the +\cappermSLC permission (as well as +\cappermSC and \cappermS). These two bits, one color and +one permission, are leveraged by the existing runtime system to ensure that +pointers to the stack can be stored only to the stack (and not the heap). +That is, excepting capabilities within the TCB, all capabilities authorizing +access to stack memory are colored Local, and all capabilities bearing the +\cappermSLC permission authorize access only to stack +memory. While the model permits a capability to stack memory (which must, +per the above restriction, be Local) to be without the +\cappermSLC permission, such capabilities are not +deliberately constructed (unless they lack \cappermSC and/or +\cappermS as well, i.e., as part of a read-only view). + +To recapitulate, then, we have the following four states of being for +capabilities: + +\begin{center}\begin{tabular}{ccc} +{\bf Color} & {\bf \cappermSLC} & {\bf Use} \\ +\hline +Global & Yes & TCB only \\ +Global & No & Heap memory \\ +Local & Yes & Stack memory \\ +Local & No & Unused +\end{tabular}\end{center} + +The last configuration may be created (even outside its read-only utility) +by monotonic action from any of the other configurations. These colorings +and permissions capture the following intended flow policy: + +\begin{center}\begin{tabular}{ccc} +{\bf Capability type...} & {\bf Stored through type...} & {\bf Permitted} \\ +\hline +Stack & Stack & Yes \\ +Heap & Stack & Yes \\ +Stack & Heap & No \\ +Heap & Heap & Yes \\ +\end{tabular}\end{center} + +In this policy, stack-type capabilities are universal authorizers of +stores (`universal recipients', if you will) and heap-type capabilities +are universally authorized to be stored (`universal donors'). (The +TCB-only, Global capabilities with \cappermSLC may be +stored to and may authorize any capability store; the unused state can be +stored only to TCB- or stack-state capabilities, and may authorize storage +only of TCB- or heap-state capabilities.) + +Neglecting the TCB state for a moment, we see that a single bit should be +sufficient to encode our desired policy, using a material conditional: +\emph{if} the capability being stored is stack-type, then the capability +authorizing this store must also be stack-stated (or, equivalently, phrased +as the contrapositive, \emph{if} the capability authorizing the store is +heap-stated, the capability being stored must also be heap-stated). Similar +flow policies also exist for flows across permission rings (the kernel may +hold its own and user capabilities, but user programs may hold only user +capabilities) and for flows through garbage-collector-managed memory regions +(capabilities to managed memory may be stored only in managed memory, +so that the collector must be notified of roots escaping). This suggests that we are justified in +carving out several bits for orthogonal colorations; we suggest at least +three, for the cases just considered, and perhaps no more than six, for +reasons we will discuss below. + +To abstract over the several colors, we adopt the terms `positively colored' and +`negatively colored' to refer to the two possible states of a color. The flow +policy is the logical \emph{and} +of the conditional for each color: ``if the +capability being stored is positively colored, then the capability authorizing the +store must also be positively colored'' or, equivalently, ``if the capability +authorizing the store is negatively colored, the capability being stored must be +negatively colored.'' Positively colored capabilities are the `universal +recipients', and +negatively colored capabilities are the `universal donors'.% +% +\footnote{Another dimension of generalization would be to have +\emph{load}-side color checking. That is, we could imagine enforcing +policies of the form ``if the capability authorizing a load is positively colored, then +the capability loaded must also be positively colored (and if not, the result is not a +capability).'' We have no immediate use for such policies, but for somewhat +related considerations, see Section~\ref{app:exp:recmutload}.} + +The two-bit color-and-permission scheme described at the start of the +section has a simple answer to the `primordial' coloring of capabilities, +and to the recoloring of capabilities into target states: the +maximally permissive TCB state may be monotonically transformed with +\insnref{CAndPerm} into any other state. Subsequent (monotonic) +actions will never convert a heap-type capability into a stack-type one, or +vice-versa. Given only a single bit for our color, any primordial +capability must have \emph{some} color, not a dedicated TCB-only +`colorless' choice. Further, our one-bit scheme must not ambiently permit +conversion, in either direction, between the two states. We therefore +propose that color bits are separate from permissions, immune to the action +of the ambiently available \insnref{CAndPerm} instruction. We suggest +that, primordially, capabilities be positively colored in all colors, so that, having +explicitly changed the color of some memory capabilities, the software may +not accidentally store into these now negatively colored regions. + +What remains to be spelled out, then, is the \emph{selective} authority to +alter colors. Towards this end, we conceptually introduce yet another +`space' of identifiers guarded by capabilities and introduce a +`color-change authority' capability, which moves about the system as any +other (and itself bears colors). The primordial capability authorizes +any change to any color of any capability anywhere in memory. Such +authority may be monotonically shed, coming to authorize only some changes +(e.g., creating stacks from heap memory, but not the reverse) to some colors +(e.g., changing only the stack/heap color but not the kernel/user color).% +% +\footnote{In principle, one could also monotonically confine color changes +to capabilities located in particular parts of memory or, perhaps more +usefully, to memory capabilities \emph{referencing} particular parts of +memory. Encoding a restricted notion of change authority for non-memory +capabilities such as sealing, compartment, or color-change capabilities is +less obvious. We are not yet sure how to proceed in this dimension of +monotonicity, and do not so here. Our color-change capabilities will +always authorize changes to any capability anywhere, but, of course, the +would-be authorized agent needs access to the source capability in the first +place.} + +\paragraph{Variant 1} +% +We introduce a new instruction, \insnnoref{CChangeColor}, which takes a +capability register containing the source capability, another for the +destination, and a third for the authority capability. This instruction +carries out \emph{all authorized transitions} to produce a target that differs from the source only +in its colors. We might have preferred a four-parameter instruction, which +additionally specified \emph{which} color to change from the authorized set, +but this would likely require too many bits; in practice, we believe that +color-change-authorizing capabilities would be few and relatively static, so +the cost of tailoring to uses would be small. + +An initial encoding of such color-change authority capabilities, +backwards-compatible with the existing capability encoding described in this +document, is to use a capability that +% +\begin{itemize} +% + \item Bears no permissions other than a new Permit\_Change\_Color permission. +(Ideally, this would be encoded as the \emph{type} of the capability, and not +consume an entire permission bit.) +% + \item Has a base of zero and a limit of the top of the address space. +% + \item Stores in its offset a bitmask authorizing color changes as follows: +color $n$ may be transitioned from its current value $c_n$ to its negation +if bit $2n + c_n$ is set. +% +\end{itemize} +% +It is immaterial which of `0' or `1' one assigns to the different color +choices. However, the system must pick one; we suggest using `1', +commonly read as `true', for the `positively colored' choice, in keeping with the +presentation above. +In this encoding, the offset-adjusting instructions must be modified to +permit only bitwise \emph{and} operations on the offsets of these capabilities. +(If one is conflating capability types, as we do at present, the appropriate +guard is that \emph{only} Permit\_Change\_Color is set.) This is perhaps the +most awkward feature of this design, though we believe the checks can be +added without impacting timing. (In a world where capability types were +explicit and separate from permission bits, we could reuse the permission +bits, already subject to manipulation only by \insnref{CAndPerm} to +carry our permission bitmask, assuming there are at most half as many colors +as permission bits.) + +\paragraph{Variant 2} +% +Perhaps a more natural encoding +would instead have capabilities that enact +exactly one color change when cited (but may \emph{authorize} more than one). +Here, we propose that the space of integers from $0$ to $2C$, with $C$ being +the number of color bits available in the system, be another `identifier +space' for capabilities. A color-change capability holding value $2n+c_n$ +requests toggling color $n < C$ from $c_n$ to its negation when used as the +authorizing capability with the \insnnoref{CChangeColor} instruction. In +this scheme, there would be no need for any fiddly bit manipulations of +capability offsets, but at the cost of more capabilities held by agents +authorized to perform some, but not all, color changes. + +\paragraph{Variant 3} +% +In fact, there is no need to introduce an entirely new capability type, +permission bit, or instruction. Because sealing object types +(\cotype{}), in practice, are only at most 24 +bits wide, and there are very few colors, we could reuse invalid encoding space +for sealing capabilities to also authorize color changes: values $x$ in the +range of $2^{24}$ to $2^{24}+C$ could be defined as colors rather than invalid +\cotype{}s and the existing use of \cappermSeal and \cappermUnseal bits could +control setting the target capability's color number $x - 2^{24}$ to become +positively or negatively colored. The existing \insnref{CSeal} and +\insnref{CUnseal} +instructions could be used in lieu of any new +\insnnoref{CChangeColor}. This shares with variant 2 the need to have many capabilities +held by agents authorized to change multiple colors if they are not contiguous +or authorize different transition directions. + +\note{In light of the increased alignment requirements imposed on sealed +capabilities and to facilitate sealing of capabilities authorizing color +change, one may wish to shift the color index up by 12 bits, using $b$ to $b ++ 2^{12}C$ and ignoring the bits below 12. One might be tempted by $b = +2^{24}$, so as to be `just above' the \cotype{} space, as +it +was above, but +as sealing alignment requirements apply to them as well, perhaps $b = +2^{36}$ is a better choice.}{nwf} + +% >>> +\section{Sealing With In-Memory Tokens} % <<< +\label{app:exp:typetoken} + +Deciding on the number of \cotype{} bits within a sealed capability has +been challenging, because the bits come at the expense of bits for precision +of bounds, permissions, and colors. In this section, we propose that +\emph{virtual addresses} can play double-duty as \emph{type identifiers}, +either supplanting or reducing the need for in-capability \cotype{} +bits. The design of this section is a somewhat invasive change to CHERI, +but appears promising. + +\subsection{Mechanism Overview} % <<< + +We propose that sealed objects have their type not in the referring +capability, but rather in a tagged capability-sized structure at the +\emph{base} of the object in memory. This structure is termed a `type +token' and it contains a virtual address (and metadata) but does not confer +any permissions, to its contained address or otherwise, to its bearer; in +fact, as a defensive posture, we do not permit tagged type tokens to be +loaded into registers unless PCC has \cappermASR.% +% +\footnote{This means that a sealed object cannot simply be copied via +\texttt{memmove}; a copy or move constructor must be invoked to reconstruct +the type tag on the target memory. This does not seem to be an especially +high burden. In fact, even the \cappermASR caveat can +be removed if an alternative mechanism for tag reconstruction is made +available to the kernel; for example, capability reconstruction as per +\cref{section:capability-reconstruction} could gain the ability to +reconstruct tags given the sealing authority.} +% +In addition to creating a sealed reference capability, sealing an object +would \emph{store} a suitable type token to memory, derived from the +capability used to authorize the seal. Unsealing \emph{fetches} and +verifies this type token against the capability authorizing the unsealing. + +% >>> +\subsection{Shared VTables with Sentry Capabilities and Type Tokens} % <<< +\label{app:exp:typetoken:vt} + +\begin{figure}[htb] % fig:app:exp:typetoken:vt <<< + \centering + \includegraphics{fig-type-token.pdf} + + \caption{Schematic representation of a shared VTable design for a base class. + The user directly holds a sentry capability to the object constructor guard, + which uses the adjacent Permit\_Create\_Type\_Token-bearing capability to + stamp object instances. Each object instance is held by the user through a + \cappermLC-bearing capability and has a two-capability header, + consisting of a \cappermLC-bearing capability to the VTable and + a sealed capability bearing load and store permissions to the object instance + data. The VTable itself is an array of sentry capabilities pointing at + method guards, which in turn verify the object instance's type token against + their unsealing right before invoking the actual class method handler.} + % + \label{fig:app:exp:typetoken:vt} + +\end{figure} % >>> + +Sentry capabilities (recall \cref{sec:arch-sentry}) give software the ability +to ensure that control flow can enter a given region at a particular +address: the bearer of a sentry capability can jump to it but cannot adjust +its offset. However, unlike the existing +\insnref{CInvoke} mechanism, sentry capabilities when invoked transition only the PCC register. +To transition other registers as a function of the instance, we propose a +PLT-like scheme using dedicated trampolines to load \emph{unsealed} +capabilities that were nevertheless beyond the reach of the caller, due to +the sealed nature of the sentry capability held. + +In-memory type tokens allow software the ability to mimic the existing +CHERI sealing mechanism, trading one capability in memory to not need the +\cotype{} bits in referring capabilities. (This does come with the +additional cost that sealing a region of memory under multiple seals will +require the use of several tokens in memory with successively larger bounds +in the referring capabilities.) In \cref{fig:app:exp:typetoken:vt} we show a +schematic representation of using in-memory type tokens to guard method +invocation of a multiply instantiated (C++) object. + +Combined with sentry capabilities, an object's shared code can now securely +verify that its first argument is indeed a sealed capability to a data +region resulting from this object's constructor. The constructor is made +available as a sentery capability to a region containing a capability bearing +\cappermSeal. The non-constructor capabilities in the VTable are sentry +capabilities pointing within a region bearing corresponding \cappermUnseal +rights. These three regions (the constructor guard code, the method guard +code, and the VTable) are created once, when the object class is loaded, and +will never be written to thereafter. Conveniently, the object-class code +location can be used as its own type token value, there is no need for a +separate pool of virtual addresses for type token values. The separation of unsealing +rights is not essential and is another defense in depth: the non-constructor +methods will not necessarily come to hold, even transitively, a capability +bearing \cappermSeal for this object type. + +% >>> +\subsection{The Mechanism in More Detail} % <<< + +Type tokens are created directly into memory with a new \insnnoref{CSealTyT} +instruction, stored at the \emph{base address} of the capability +being sealed, which must be capability-aligned (and the to-be-sealed +capability must authorize an at-least-one-capability-sized segment of +memory). \insnnoref{CSealTyT} requires that the capability to be sealed +bear \cappermL and \cappermS and that the invocation reference an +in-bounds \cappermSeal-bearing% +% +\footnote{For compatibility with CHERI-MIPS, we exclude from +\insnnoref{CSealTyT}'s domain sealing capabilities referencing the +bottom of memory, from $0$ and to the maximum \cotype{} value, interpreted +as an unsigned integer, available to the implementation, inclusive. These are +reserved for use with the existing \insnref{CSeal} instruction.} +% +capability whose cursor will form the type tag.% +% +\footnote{It is not clear whether \insnnoref{CSealTyT} should permit the +clearing of \cappermL and/or \cappermS in the resulting sealed +capability, despite requiring them on input.} +% +Software must ensure that the store done as part of sealing is visible to +other processors before publishing the sealed capability anywhere it may be +read by another core. Immediate fencing is not always required, and so we +suggest it not be intrinsic to the \insnnoref{CSealTyT} instruction. +% +The sealed capability resulting from \insnnoref{CSealTyT} will have its +\cotype{} set to $2^{64} - 3$, truncated as required by the implementation. + +Attempting to load a type token via \insnref{CLC} will succeed, but will +strip the tag. The resulting register contents need not be particularly +well specified; in particular, we should no more expect sensible results +from the capability-observing instructions here than if we had loaded an +arbitrary untagged region of memory. + +Token-mediated unsealing is done by a new \insnnoref{CUnsealTyT} that +takes a sealed capability (with \cotype{} of $2^{64} - 3$) +and an in-bounds authorizing capability bearing +\cappermUnseal. If the cursor of the authorizing capability matches the +virtual address stored in the type token at the base of the sealed object,% +% +\footnote{This load is why \insnnoref{CSealTyT} required \cappermL of +its to-be-sealed capability.} +% +then \insnnoref{CUnsealTyT} produces an unsealed version of the sealed +capability. Microarchitecturally, \insnnoref{CUnsealTyT} is somewhat akin to a +compare-and-swap whose store-back is into the register file rather than +memory. + +It might be helpful to software to add a \insnnoref{CGetTypeTyT} +instruction that +somewhat mirrors the \insnref{CGetType} instruction. +\insnnoref{CGetTypeTyT} would fetch from the base address of a +sealed capability (of the right \cotype{}) and store +the virtual address from the type token back to a general-purpose +integer register. +We propose that, if an exception is not desirable, that the value $2^{64} - 1$ be +used if the memory at the base is not a type token. + +% >>> +\subsection{Unseal-Once Type Tokens} % <<< + +It is likely useful to have a version of unsealing that atomically prevents +any future attempts. Rather than merely \emph{fetch} the type token, this +instruction would carry out a CAS-like update of the type token in memory. + +% >>> +\subsection{User Permissions For Type-Sealed VA Capabilities} % <<< + +Because type tokens are capability-sized structures used only for their +contained virtual addresses, there are many spare bits in the structure (in +fact, a few type-tagging bits shy of an entire machine word's worth). One +especially attractive possibility, if it can be demonstrated to be +sufficiently secure, is to push the architecturally defined permission bits +within the sealed capability into the type token. This would permit the use +of the intra-capability permission bits as user permissions, subject to the +action of \texttt{CAndPerm} despite the sealed nature of the capability. +We would then be able to use capability permission bits to help arbitrate +permissions to methods within an object, as is typical of other capability +systems, rather than, as suggested by the design in +\cref{app:exp:typetoken:vt} above, having one sentry capability per procedure +and gating permission by possession of the procedure's guard's sentry +capability. \insnnoref{CUnsealTyT} would use the bits from the type token in +its output capability, and software would be able to inspect the permission +bits of the input object reference (i.e., there would be no need for a second +register storeback in \insnnoref{CUnsealTyT}). + +In this scheme, should an object wish to be able to grant sealed references +with one of several sets of architectural permissions, it suffices to place +an array of type tokens at the beginning of instance memory and adjust the +base of the (to be sealed) capability, while leaving the cursor to point at +the start of the object's data. Any type tokens within reach confer no +authority, even after we have moved architectural permission bits into them. +Further, because type tokens cannot be created in memory except by +\insnnoref{CSealTyT} or highly privileged software, aliasing of the +memory containing the type token cannot \emph{de novo} amplify architectural +access (but may be vulnerable to confusion within suitably authorized +control flow). + +% >>> +\subsection{Token-mediated CInvoke} % <<< + +\insnref{CInvoke} poses something of a challenge for in-memory type tags: a +single instruction must, seemingly, perform \emph{two} fetches from memory +and then do a comparison on the loaded values. However, because the +instruction cares only about the equality, it seems that we can turn this +into a fetch from one capability's base and then a CAS-style +\emph{comparison} against the other's. In fact, this combines nicely with +unseal-once type tokens: if \insnref{CInvoke} fetches from the sealed code +capability first, it is then in a position to issue the appropriate CAS +against the sealed data capability. In CHERI-MIPS, \insnref{CInvoke} is +already a two-cycle instruction, occupying two successive stages of the +pipeline, and so we conjecture that the changes requisite to support +token-mediation are small. + +% >>> +\subsection{Hybridization} % <<< + +This scheme uses one \cotype{} value for its sealed capabilities; the remaining +values are still available for the rest of the system's use. It is our hope +that most users of \cotype{} values can be rearchitected to use this in-memory +scheme and that the \cotype{} field can be reduced in size. However, the +\cotype{} field should not be entirely eliminated: its existence allows us avoid +some of the overhead of this design in the innermost ring of the system.% +% +\footnote{Because the innermost ring is presumably the kernel's TCB, a +hypervisor, or `nanokernel'-- effectively microcode -- the resulting system +has some similarities to the Intel 432 / BiiN / i960MX lineage, which had a +few architecturally understood special types of capabilities -- but relied on +software interpretation for the rest.} +% +Such \cotype{} bits would also let software create sealed objects other than +enter capabilities without memory footprint. + +% >>> +% >>> +\section{Windowed Short Capabilities} % <<< +\label{sec:windowedshortcaps} + +An frequent initial objection to CHERI is that even the 128-bit compressed +form of capabilities occupies too much space, especially for pointer-heavy +workloads. However, when discussing a 64-bit virtual address space, it +seems plausible that 128 bits is the best we can do: the metadata CHERI +requires vastly outstrips any `spare' bits in the address, and any size +that was not a power of two bits would be awkward, at best. One way out +would be to imagine that one could mix 128-bit and 64-bit capabilities +within an address space, with the caveat that the 64-bit capabilities could +address only a 32-bit address space (i.e., they would have a 4 GiB reach) +and would have a smaller set of permission bits, fewer flag bits, and fewer +bits for object types. While we could limit all 64-bit capabilities to +referencing a particular, fixed 4 GiB region of the larger addess space +(e.g., the first 4 GiB), a better design, if we could get it, would be to +allow the 4 GiB window to be chosen by a 128-bit capability. + +The design we detail here treats these 64-bit capabilities as specialized +representations of 128-bit capabilities. Importantly, this design does not +modify the representation or semantics of capabilities within the register +file: the bulk of the system's operation is not impacted. We introduce new, +purpose-made instructions for loading and storing these short +representations of capabilities; stores especially may fail if translation +is not possible. + +\subsection{Restricting Capabilities to 32-bit Windows} % <<< + +Because 64-bit capabilities operate only within a 4 GiB window of the +address space, when fetching a 64-bit capability from memory, we fill in the +implied upper 32 bits of the full 64-bit address from the \emph{cursor} of +the \emph{capability authorizing the fetch}. This straightforward operation +is provided by the \insnref{CLShC} instruction. + +When attempting to (encode and) store a capability to a short form in memory, +the store will fail% +% +\footnote{It would be sufficient to store a de-tagged word, but trapping is +more likely programmer friendly. While this is a data-dependent action, as it +requires a comparison between the (untranslated, virtual) target address and +the capability from the register file, this is not the only data dependence in +the short capability store instruction.} +% +unless all three of the following addresses agree on their top 32 bits: the +computed destination address of the store and the base and limit of the +capability being stored; the cursor of the capability to be stored is permitted +to be within either adjacent 4 GiB window (but must still be representable).% +% +\footnote{Alternatively, it would suffice to ensure that, on decoding, any +access beyond the limits of the 4-GiB-aligned region had been shed. Because +short capabilities are never used directly, there is some flexibility in +enforcement here.} +% +All of this is provided by the \insnref{CSShC} instruction. + +A consequence of this design is that short capabilities (transitively +reached through short capabilities) are always interpreted within the 4 GiB +window specified by the initial reference through a full capability. These +capabilities may be stored as short capabilities anywhere within this window +(or as full capabilities anywhere in the address space). Because +capabilities in registers always have their full 64-bit virtual address +cursor and bounds, it is impossible to use a short capability in one 4 GiB +window to derive a capability to any part of a different window: the +dereferencable region is always contained within the original window whence +the capability was loaded, and so attempted stores to another window will +fail.% +% +\footnote{If ever direct memory-to-memory capability copies become possible, +it would be necessary to explicitly check that copied short capabilities are +not being replicated in ways that would change their decoding.} + +\nwfnote{The proposed instruction encodings have quite sizable footprint in +the encoding space. Moreover, we probably want \insnnoref{CLLShC} +and \insnnoref{CSCShC} opcodes, too.} + +% >>> +\subsection{Restrictions Within Short Capabilities} % <<< + +In order to reduce the space required for metadata within short +capabilities, we suggest several restrictions. + +Within the permissions field, we suggest that short capabilities be limited +to expressing virtual address space, so that \cappermSeal, \cappermUnseal, +and \cappermCid are implicitly false for any short capability. This +seems reasonable, as these gate fundamentally new facilities offered by CHERI +and seem like they will be relatively rare even in fully CHERI-fied software +stacks, so the requirement to use a 128-bit capability should not be +onerous. +% +Further, because we intend short capabilities to be used mostly for +sandboxes within a larger ecosystem, we think it reasonable to imply that +\cappermASR is also false. +% +Similarly, we do not foresee the utility of the Local/Global distinction for +short capabilities, and so propose implying +\cappermSLC to be false.% +% +\footnote{We could also imply the Global permission bit to be \emph{true}, +but then we would need to fail attempts to encode local capabilities into short +forms. While we do not anticipate the use of capabilities bearing +\cappermSLC outside trusted +software, it nevertheless seems simpler to leave Global within the short +capability encoding.} +% +All told, these implications eliminate five existing permission bits from +short capabilities' representations. + +We suggest a reduced object type range for short capabilities, as well. +This will have implications in the software stack: `small' object types +will be somewhat precious, and so may need to have special handling in the +allocator(s) thereof. The utility of sealed short capabilities, and +especially of architecturally defined sealing object types to short +capabilities, remains an open question. + +Bound metadata may also be subject to pressure, and so short capabilities +may face stricter alignment requirements for large objects than full, +128-bit capabilities. While this would not be great, it may be that +references to large objects are relatively sparse, and so software may find +it easier to fall back to full capabilities rather than insist that all +capabilities should be short whenever possible. + +% >>> +\subsection{Tag Bits and Representation for Shared Memory} % <<< + +Short ``capabilities" could plausably be left untagged in the architecture +and used only as forgeable fat pointers which are lifted into the capability +space on coversion. +If we were to tag short capabilities, we require more bits for +distinguishing mixed capability widths from data. +In a 128-bit-sized and -aligned +region of memory, there are five possible options, assuming that 128-bit +capabilities must remain 128-bit-aligned: +% +\begin{inenum} +% + \item One 128-bit capability. +% + \item Two 64-bit capabilities. +% + \item One 64-bit capability, followed by data. +% + \item One 64-bit capability, preceded by data. +% + \item Only data. +% +\end{inenum} +% +There are several ways that we could arrange to distinguish these +possibilities, but two seem especially attractive. Perhaps the simplest +approach is to use three out-of-band tag bits rather than the one per +128-bit granule of memory that CHERI now imposes; this would leave us with +three values reserved for future expansion. One could slightly tamp down on +the need for tag bits by tagging entire \emph{cache lines} instead: eight +sets of 5-way discrimination, corresponding to 128-byte cache lines, requires +only 19 bits rather than the more straightforward 24, at the cost of more +complex decoding logic (likely in the LLC). + +However, we may be better served by the use of two out-of-band tags and one +bit in the capability encodings themselves, effectively giving us somewhere +between two and four bits of metadata, depending on the scenario. One +possible encoding is shown in \cref{tab:shorttags}. Forbidden states should +trigger machine check exceptions or something similarly indicative of +catastrophe. +% +This scheme is relatively straight foward to operate, but requires a little +awkward handling of the inherent asymmetry between the upper and lower 64 +bits within a 128-bit granule. A load of a full capability must verify that +both out of band tag bits and $t_\text{hi}$ are all asserted. A load of a +short capability from the upper position must verify that $T_\text{hi}$ is +asserted and $t_\text{hi}$ is clear. A load of a short capability from the +lower position must verify that $T_\text{low}$ is asserted, that +$t_\text{low}$ is clear, and that either $T_\text{hi}$ or $t_\text{hi}$ is +clear. Data stores always clear the corresponding out-of-band bit; stores +to the lower half of a capability granule must additionally access +$T_\text{hi}$ and, if $T_\text{hi}$ is asserted, then access $t_\text{hi}$ +to determine whether $T_\text{hi}$ should be cleared as well (to avoid the +forbidden states marked with $\dagger$). Fortunately, all of this state +machine logic is localized within a cache line and its tag bits. + +\begin{table} +\begin{center} +\begin{tabular}{cccc|l} + +$T_\text{hi}$ & $T_\text{low}$ & $t_\text{hi}$ & $t_\text{low}$ & Meaning \\ +\hline\hline + +0 & 0 & $X$ & $X$ & Two data words \\ +0 & 1 & $X$ & 0 & 64 bits of data above a 64-bit capability \\ +0 & 1 & $X$ & 1 & Forbidden \\ +1 & 0 & 0 & $X$ & A 64-bit capability above 64 bits of data \\ +1 & 0 & 1 & $X$ & Forbidden\textsuperscript{$\dagger$} \\ +1 & 1 & 0 & 0 & Two 64-bit capabilities \\ +1 & 1 & 0 & 1 & Forbidden \\ +1 & 1 & 1 & $X$ & A 128-bit capability \\ + +\end{tabular} +\end{center} + +\caption{A possible hybrid out-of-band and in-band tagging scheme for mixing +128-bit and 64-bit capabilities. $t_\text{hi}$ and $t_\text{low}$ are the +intra-capability tag bits for the upper and lower 64-bit regions, +respectively, while $T_\text{hi}$ and $T_\text{low}$ denote the +corresponding two out-of-band tag bits. $X$ indicates `don't care' and +stands for either bit value.} + +\label{tab:shorttags} +\end{table} + +Similar considerations hold should we wish to mix all of 64-, 128-, and +256-bit capability forms. In such a system, there are 26 states for every +256-bit granule of memory: each 128-bit granule may be in each of the 5 +states given above, or an adjacent pair may hold a 256-bit capability. + +\subsubsection{With Relaxed Alignment Requirements} % <<< + +It may be more natural to permit \emph{all} capabilities, both 64-bit and +128-bit, to be stored at 64-bit alignment. In such a case, within a +128-bit-sized and -aligned region, there are now these 10 possibilities: +% +\begin{inenum} +% + \item One 128-bit capability, spanning the whole region. +% + \item The tail of a 128-bit capability, followed by the head of a 128-bit capability. +% + \item The tail of a 128-bit capability, followed by a 64-bit capability. +% + \item The tail of a 128-bit capability, followed by data. +% + \item The head of a 128-bit capability, preceeded by a 64-bit capability. +% + \item The head of a 128-bit capability, preceeded by data. +% + \item Two 64-bit capabilities. +% + \item One 64-bit capability, followed by data. +% + \item One 64-bit capability, preceded by data. +% + \item Only data. +% +\end{inenum} + + +% >>> +% >>> +\subsection{SoCs With Mixed-Size Capabilities} % <<< + +It is frequently the case that Systems on Chip (SoCs) contain 64-bit +application cores and also 32-bit microcontrollers. +One potential further use for this approach is to allow bridging between those +two worlds: 64-bit cores with 128-bit capabilites that are able to load and +store 64-bit capabilities used by 32-bit cores connected to the same memory +fabric. +Care would be required to ensure that capabilities originating on one core +were derefenced only with a suitable address space on a second core able to +access them. + +\nwfnote{In such circumstances, one could imagine that the shared memory +block(s) have a capability granularity and then restrict larger cores to +using the short-cap operations and requiring that software preserve the +alignment requirements for these regions when they are virtually mapped.} + +% >>> +% >>> +\section{Capabilities For Physical Addresses} % <<< +\label{app:exp:physcap} + +\subsection{Motivation} + +CHERI capabilities that authorize access to memory are typically interpreted +in combination with an ambient virtual address translation configuration. +That is, the addresses authorized by a CHERI memory capability are taken to +be virtual addresses, which are then translated to physical addresses by the +core's MMU. The MMU configuration defines a virtual address space; it is, +ultimately, in all modern, mainstream architectures, described by +\emph{integers}.% +% +\footnote{In architectures with hardware page table walkers, such as Arm and +RISC-V, these integers are arranged in defined, tabular format. In +architectures without, such as MIPS, the analogous structures are defined +only in software, but the soft-loaded TLB is programmed using integer +values written to architecturally specified registers.} +% +The use of provenance-free integers to describe such configurations carries +risks, just as with pointers. Necessarily, the ability to configure the MMU +must be confined to privileged, and necessarily trusted, software; this +software must enforce its intended policies concerning permitted access to +the core's view of physical memory and it must do so with no architectural +safeguards. + +Moreover, a (software) system may, as part of timesharing the CPU core, +reprogram the MMU to achieve isolation (and, possibly, controlled +non-isolation) between different `process contexts'. Further, these +contexts may be dynamic, reshaping their associated MMU configurations +across time. CHERI capabilities are not explicitly associated with a +particular context and/or time. As a result, software must ensure that +capabilities are not transmissible improperly% +% +\footnote{The simplest and most restrictive policy is to entirely prevent +transmission of capabilities between contexts. However, if contexts have +common identically interpreted regions of their address spaces, one could +imagine utility in passing capabilities referencing only these spaces. Such +passing would, in CHERI's design, necessarily have to go via a software +intermediate rather than more direct passing through the shared region +itself.} +% +from one context to another, nor retained improperly as context mappings +evolve. Thus, the direct mechanisms available for capability passing within +a single context (including between CHERI compartments therein) are likely +not available for cross-context communication. + +A similar story plays out in hardware: `physical' addresses are meaningful +only when paired with a \emph{location}, as bus bridges may remap addresses +in transit from one port to another. When devices or cores wish to +communicate, they must model the action of the intermediate fabric and +generate (integer) addresses that may not be meaningful locally but will be +at the remote endpoint, across the bus fabric. Again, all the problems with +integer addresses resurface and are exacerbated by the relatively minimal +protection mechanisms available at the physical bus layer. + +For this section, we focus on two cases: software on a CHERI core seeking to +escalate its privilege, and peripheral devices wishing to attack the core +(possibly in cooperation with software). In both cases, the intended victim +of the attack(s) will be taken to be the CHERI core's trusted computing base +(e.g., a hypervisor). We restrict our attention to steady-state operation +rather than attacks against the initial bootstrap; that is, we assume that +any would-be attacker was not present during the load of said TCB and that +the \emph{core} itself is trusted to faithfully execute instructions. + +\subsection{Capability-Mediated CPU Physical Memory Protection} % <<< + +RISC-V has a notion of a Physical Memory Protection (PMP) unit that +validates every (post-virtual-address-translation) memory request issued by +a processor core. Roughly, for each request, an $n$-way associative lookup +against a table of (region, permissions) pairs is performed, and the request +is authorized only if the table contains a region containing the requested +address and the request is of a type permitted by that region. For details, +see the RISC-V Privileged Architecture specification~\cite[\S +3.6]{RISCV:Privileged:1.10}. + +The control interface to the PMP is, as might be imagined, based on +integers: coarsely speaking, machine-mode code is able to write arbitrary +bits to the PMP table through the core's CSR interface. Supervisor and user +mode code are not permitted access to the table. Thus, any code in machine +mode can alter restrictions imposed on supervisor or user memory access, and +so a confused deputy attack on the machine mode could result in privilege +escalation for the supervisor or user programs. We would prefer to have a +more `least authority'-friendly option. + +We propose a `capability-mediated PMP' (CPMP). Its control interface will +permit table entries to be populated only from valid (tagged) capabilities. +We imagine using a pair of a CSR and a special capability register to +provide row-by-row access to the augmented table. + +Because machine-mode code on RISC-V has explicit control over whether +address translation is enabled, a baseline capability-mediated PMP +implementation could repurpose the existing CHERI capability mechanisms and +rely on software to track the distinction between capabilities intended for +use as physical addresses and those intended for use as virtual addresses. +Such an approach runs slightly against the grain of our design principles, +and has limitations; for example, sealed forms must be used if these +capabilities are to be given to supervisor (or user) code. + +For these reasons, and to enable a wider series of uses, we envision creating +a new capability provenance \emph{root}. Capabilities derived from this +root are distinct from existing CHERI capabilities (by, say, having a bit +immutably set that the existing capabilities maintain cleared) and denote +ranges of physical addresses, even in the presence of paging. Accesses via +these capabilities bypass any paging mechanism and, dually, we can now make +accesses via the existing CHERI capabilities +that + \emph{always} go via address translation, even in machine mode.% +% +\footnote{This obviates the RISC-V \texttt{mstatus} MPRV mechanism for +toggling address translation.} +% +These capabilities may have their born authority decreased as with any other +CHERI capability, and may flow to non-machine-mode code to enable (for +example) light-weight partitioning of physical resources between multiple +supervisors. + +% >>> +\subsection{Capability-Mediated DMA Physical Memory Protection} % <<< + +Whereas RISC-V considers PMPs only in the context of a CPU core, nearly +identical hardware can be used to gate peripheral DMA requests. Here, the +PMP's control interface is exposed to the CPU, most likely as a +memory-mapped region, and the direction of requests is backwards, but the +operation of the device is fundamentally the same. When presented with a +memory request \emph{by the peripheral}, such a gate performs an associative +scan of the configured table and either permits the request to enter the bus +or rejects the request. We tentatively call such a gate an IOPMP. + +Whereas IOPMPs could be programmed using integers (as in the RISC-V PMPs), or +using existing CHERI capabilities transported over the memory bus, the story +is much more credible if they can require physical-address capabilities. So +equipped, we reduce the risk of confusion or misbehavior of machine-mode +code but, more excitingly, we gain the possibility of directly exposing +peripheral IOPMPs to non-machine-mode code for efficient device +pass-through. + +This story is fairly satisfying for the control of the IOPMP itself; +however, there remains a challenge of translating the authority carried by +the CHERI CPU core into an address suitable for comprehension by the +peripheral. That is, because the peripheral continues to speak in +\emph{integer} addresses in its control messages, software on the core could +easily treat the peripheral as a confused deputy, causing it to DMA to +regions authorized by, for example, other (software) compartments. It may +be necessary to limit sharing of peripherals this way, or more directly +involve the IOPMPs in device control. One could imagine, for example, that +the IOPMP could `back-translate' core-originated capabilities in control +messages into integers for the peripheral's consumption, perhaps with a tag. + +% >>> +\subsection{Capability-Based Page Tables} % <<< +\label{app:exp:physcap:ptw} + +Traditionally, hypervisors must deny the supervisors they oversee the +ability to directly control the memory translation tables. Towards the +`paravirtualization' end of the spectrum, the hypervisors require that the +guests make hypercalls to manipulate the page tables. Towards the +`hardware-assisted' end, the CPU's MMU will use `nested translation': +the `guest physical' addresses manipulated by the guest are subject to +re-translation, through tables controlled by the hypervisor, before becoming +`host physical' addresses and exiting the CPU core. Both approaches have +substantial costs. + +A more radical approach would have us change the traditional memory +management unit (MMU) page tables. Instead of mapping virtual +addresses to \emph{integer} physical addresses, the page tables would yield +a \emph{physical capability} for a virtual address. We envision repurposing +the capability permission bits for the PTE permission bits, and extending the +flags field of \cref{sec:model-flags} to encompass non-authority flags +of PTEs, notably including accessed, dirty, and global flags. + +To simplify the system, we may require that physical capabilities installed +in page tables have offset zero and length at least a full page (of the +appropriate level of the tree). This allows us to skip a capability bounds +check when translating a virtual address but retains proof of +\emph{provenance} of the authority to access a given region of physical +addresses. + +% >>> +\subsection{Capability-Based Page Tables in IOMMUs} % <<< + +As with the PMPs, this new facility also finds use in guarding peripherals. +Rather than the associative table scans of the IOPMPs above, we could have +capability-mediated IOMMUs whose page-table entires, again, contain +physical-address capabilities. Of course, there is no reason that an IOPMP +expose a 64-bit address space to the peripheral, nor that it use +hierarchical pages. For many peripherals, a \emph{single} page-sized +aperature (or even smaller) may suffice. The concern of integer addresses +in peripheral control messages continues to apply. + +% >>> +\subsection{Exposing Capabilities Directly To Peripherals} % <<< + +Both IOPMPs and IOMMUs, mediated by capabilities or not, continue to expose +an \emph{integer} address space to the peripheral. While the peripheral may +be using CHERI for its internal computations, its interface with the host +remains capability-less. In some cases of mutually distrusting peers, this +may suffice, and each side may have capability-mediating devices under its +control to guard the interconnect. + +However, in other cases the host may wish to extend the \emph{tagged} +memory bus all the way to the peripheral, and then grant capabilities +directly to the device as though it were a software process. In such cases, +we expect that an IOPMP- or IOMMU-like guarding device will still be useful, +to prevent a malicious or errant device from synthesizing or retaining (and +subsequently using) capabilities that the host does not intend. All +capabilities transiting the guard would be checked to be a \emph{subset} of +a capability in the guard's table. We note, in passing, that such guard +devices are also useful for the case of direct peripheral-to-peripheral +access, not merely the case of peripheral-to-memory as we have generally +focused upon here. The details of the control interface to such a device, +as well as its internal operation, are left to future work. + +% >>> +% >>> +\section{Distributed Capabilities For Peripherals And Accelerators} % <<< +%\tmnote{This section overlaps with the previous and is intentionally being kept separate for now. +%It will need merging in due course. Commented out until it's a bit more stable} +\input{app-exp-peripherals} + +% >>> +\section{Details of Proposed Instructions} % <<< +\label{app:exp:insns} + +The following instructions are described using the same syntax and approach as +those in Chapter~\ref{chap:isaref-mips}. + +\input{insn-mips/candaddr} +\input{insn-mips/cbuildcap} +\input{insn-mips/ccleartags} +\input{insn-mips/ccopytype} +\input{insn-mips/ccseal} +\input{insn-mips/cgetandaddr} +\input{insn-mips/clcnt} +\input{insn-mips/clshc} +\input{insn-mips/csshc} +\input{insn-mips/ctestsubset} + +% >>> + +% vim: foldmethod=marker:foldmarker=<<<,>>> diff --git a/app-isaquick-mips.tex b/app-isaquick-mips.tex new file mode 100644 index 00000000..5afdb997 --- /dev/null +++ b/app-isaquick-mips.tex @@ -0,0 +1,1027 @@ +\renewcommand{\asm}[1]{~\raiseforbf{\textsf{\footnotesize{#1}}}} +\newcommand{\optype}[1]{\subsection{#1 Instructions}} + +{ +\setlength{\parindent}{0cm} + +\newcommand{\loads}{ + \loadinst{\textit{x}}{\textit{s}}{\textit{t}}{1} + \loadinst{B}{1}{0}{0} + \loadinst{H}{1}{1}{0} + \loadinst{W}{1}{2}{0} + \loadinst{BU}{0}{0}{0} + \loadinst{HU}{0}{1}{0} + \loadinst{WU}{0}{2}{0} + \loadinst{D}{0}{3}{0} +} + +\newcommand{\stores}{ + \storeinst{\textit{x}}{\textit{t}}{1} + \storeinst{B}{0}{0} + \storeinst{H}{1}{0} + \storeinst{W}{2}{0} + \storeinst{D}{3}{0} +} + +\chapter{CHERI-MIPS ISA Quick Reference} +\label{app:isaquick-mips} + +This appendix provides a quick reference for CHERI-MIPS instruction encodings +excluding experimental instructions (see Appendix~\ref{app:experimental}). + +\section{Current Encodings} + + The following encodings are correct for implementations that exist at the time of this document's publication. + + \optype{Capability-Inspection} + + \cheritwoop[header]{0x0}{rd}{cb} + \asm{\insnmipsref{CGetPerm} rd, cb} + + \cheritwoop{0x1}{rd}{cb} + \asm{\insnmipsref{CGetType} rd, cb} + + \cheritwoop{0x2}{rd}{cb} + \asm{\insnmipsref{CGetBase} rd, cb} + + \cheritwoop{0x3}{rd}{cb} + \asm{\insnmipsref{CGetLen} rd, cb} + + \cheritwoop{0x4}{rd}{cb} + \asm{\insnmipsref{CGetTag} rd, cb} + + \cheritwoop{0x5}{rd}{cb} + \asm{\insnmipsref{CGetSealed} rd, cb} + + \cheritwoop{0x6}{rd}{cb} + \asm{\insnmipsref{CGetOffset} rd, cb} + + \cherioneop{0x0}{cd} + \asm{\insnmipsref{CGetPCC} cd} + + \cheritwoop{0xf}{rd}{cb} + \asm{\insnmipsref{CGetAddr} rd, cb} + + \cherithreeop{0x23}{rd}{cb}{rs} + \asm{\insnmipsref{CGetAndAddr} rd, cb, rs} + + \cheritwoop[header]{0x12}{rd}{cb} + \asm{\insnmipsref{CGetFlags} rd, cb} + + + \optype{Capability-Modification} + + \cherithreeop[header]{0xb}{cd}{cs}{ct} + \asm{\insnmipsref{CSeal} cd, cs, ct} + + \cherithreeop{0xc}{cd}{cs}{ct} + \asm{\insnmipsref{CUnseal} cd, cs, ct} + + \cherithreeop{0xd}{cd}{cs}{rt} + \asm{\insnmipsref{CAndPerm} cd, cs, rt} + + \cherithreeop{0xe}{cd}{cs}{rt} + \asm{\insnmipsref{CSetFlags} cd, cs, rt} + + \cherithreeop{0xf}{cd}{cs}{rt} + \asm{\insnmipsref{CSetOffset} cd, cs, rt} + + \cherithreeop{0x8}{cd}{cs}{rt} + \asm{\insnmipsref{CSetBounds} cd, cs, rt} + + \cherithreeop{0x9}{cd}{cs}{rt} + \asm{\insnmipsref{CSetBoundsExact} cd, cs, rt} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x14} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{11}{length} + \end{bytefield} + \asm{\insnmipsref{CSetBoundsImm} cd, cb, length} + + \cheritwoop{0xb}{cd}{cb} + \asm{\insnmipsref{CClearTag} cd, cb} + + \cherithreeop{0x11}{cd}{cb}{rt} + \asm{\insnmipsref{CIncOffset} cd, cb, rt} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x13} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{11}{increment} + \end{bytefield} + \asm{\insnmipsref{CIncOffsetImm} cd, cb, increment} + + \cherithreeop{0x1d}{cd}{cb}{ct} + \asm{\insnmipsref{CBuildCap} cd, cb, ct} + + \cherithreeop{0x1e}{cd}{cb}{ct} + \asm{\insnmipsref{CCopyType} cd, cb, ct} + + \cherithreeop{0x1f}{cd}{cs}{ct} + \asm{\insnmipsref{CCSeal} cd, cs, ct} + + \cherithreeop{0x22}{cd}{cs}{rs} + \asm{\insnmipsref{CSetAddr} cd, cs, rs} + + \cherithreeop{0x24}{cd}{cb}{rs} + \asm{\insnmipsref{CAndAddr} cd, cb, rs} + + \cheritwoop{0x7}{cd}{rs} + \asm{\insnmipsref{CGetPCCSetOffset} cd, rs} + + \cheritwoop{0x13}{cd}{rs} + \asm{\insnmipsref{CGetPCCIncOffset} cd, rs} + + \cheritwoop{0x14}{cd}{rs} + \asm{\insnmipsref{CGetPCCSetAddr} cd, rs} + + \cheritwoop{0x1d}{cd}{cs} + \asm{\insnmipsref{CSealEntry} cd, cs} + + \optype{Pointer-Arithmetic} + + \cherithreeop[header]{0x12}{rd}{cb}{cs} + \asm{\insnmipsref{CToPtr} rd, cb, cs} + + \cherithreeop{0x13}{cd}{cb}{rs} + \asm{\insnmipsref{CFromPtr} cd, cb, rs} + + \cherithreeop{0xa}{rt}{cb}{cs} + \asm{\insnmipsref{CSub} rt, cb, cs} + + \cheritwoop{0xa}{cd}{cs} + \asm{\insnmipsref{CMove} cd, cs} + + \cherithreeop{0x1b}{cd}{cs}{rs} + \asm{\insnmipsref{CMOVZ} cd, cs, rs} + + \cherithreeop{0x1c}{cd}{cs}{rs} + \asm{\insnmipsref{CMOVN} cd, cs, rs} + + \optype{Pointer-Comparison} + + \newcommand{\ptrcmp}[3][NOHEADER]{ + \cherithreeop[#1]{#3}{rd}{cb}{cs} + \asm{\insnmipsref[cptrcmp]{C#2} rd, cb, cs} + + } + + \ptrcmp[header]{EQ}{0x14} + \ptrcmp{NE}{0x15} + \ptrcmp{LT}{0x16} + \ptrcmp{LE}{0x17} + \ptrcmp{LTU}{0x18} + \ptrcmp{LEU}{0x19} + \ptrcmp{NEXEQ}{0x21} + \ptrcmp{EXEQ}{0x1a} + + \optype{Exception-Handling} + + \cherioneop[header]{0x1}{rd} + \asm{\insnmipsref{CGetCause} rd} + + \cherioneop{0x2}{rs} + \asm{\insnmipsref{CSetCause} rs} + + \optype{Control-Flow} + + \newcommand{\cheribranch}[3][NOHEADER]{ + \begin{bytefield}{32} + \ifthenelse{\equal{#1}{NOHEADER}}{} + {\bitheader[endianness=big]{0,15,16,25,20,21,25,26,31}}\\ + \bitbox{6}{0x12} + \bitbox{5}{#3} + \bitbox{5}{cd} + \bitbox{16}{offset} + \end{bytefield} + \asm{\insnmipsref{CB#2} cd, offset} + + } + \cheribranch[header]{TU}{0x9} + \cheribranch{TS}{0xa} + \cheribranch{EZ}{0x11} + \cheribranch{NZ}{0x12} + + \vspace{1.5ex} + + \cherioneop[header]{0x3}{cb} + \asm{\insnmipsref{CJR} cb} + + \cheritwoop{0xc}{cd}{cb} + \asm{\insnmipsref{CJALR} cd, cb}\\ + + \vspace{1.5ex} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,10,11,15,16,20,21,25,26,31}\\ + \bitbox{6}{0x12} + \bitbox{5}{0x05} + \bitbox{5}{cs} + \bitbox{5}{cb} + \bitbox{11}{0x001} + \end{bytefield} + \asm{\insnmipsref{CInvoke} cs, cb} + + \optype{Assertion} + + \cherioneop[header]{0x6}{cs} + \asm{\insnmipsref{CCheckTag} cs} + + \cherithreeop{0x20}{rd}{cb}{ct} + \asm{\insnmipsref{CTestSubset} rd, cb, ct} + + + \optype{Special-Purpose Register access} + + \cheritwoop[header]{0xd}{cd}{sel} + \asm{\insnmipsref{CReadHwr} cd, selector} + + \cheritwoop{0xe}{cb}{sel} + \asm{\insnmipsref{CWriteHwr} cb, selector} + + \optype{Fast Register-Clearing} + + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,15,16,20,21,25,26,31}\\ + \bitbox{6}{0x12} + \bitbox{5}{0xf} + \bitbox{5}{0x0} + \bitbox{16}{mask} + \end{bytefield} + \asm{\insnmipsref{ClearLo} mask} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0xf} + \bitbox{5}{0x1} + \bitbox{16}{mask} + \end{bytefield} + \asm{\insnmipsref{ClearHi} mask} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0xf} + \bitbox{5}{0x2} + \bitbox{16}{mask} + \end{bytefield} + \asm{\insnmipsref{CClearLo} mask} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0xf} + \bitbox{5}{0x3} + \bitbox{16}{mask} + \end{bytefield} + \asm{\insnmipsref{CClearHi} mask} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0xf} + \bitbox{5}{0x4} + \bitbox{16}{mask} + \end{bytefield} + \asm{\insnmipsref{FPClearLo} mask} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0xf} + \bitbox{5}{0x5} + \bitbox{16}{mask} + \end{bytefield} + \asm{\insnmipsref{FPClearHi} mask} + + \optype{Adjusting to Compressed Capability Precision} + \cheritwoop[header]{0x10}{rt}{rs} + \asm{\insnmipsref{CRoundRepresentableLength} rt, rs} + + \cheritwoop{0x11}{rt}{rs} + \asm{\insnmipsref{CRepresentableAlignmentMask} rt, rs} + + \optype{Memory-Access} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,10,11,15,16,20,21,25,26,31}\\ + \bitbox{6}{0x3e} + \bitbox{5}{cs} + \bitbox{5}{cb} + \bitbox{5}{rt} + \bitbox{11}{offset} + \end{bytefield} + \asm{\insnmipsref{CSC} cs, rt, offset(cb)} + + \begin{bytefield}{32} + \bitbox{6}{0x36} + \bitbox{5}{cs} + \bitbox{5}{cb} + \bitbox{5}{rt} + \bitbox{11}{offset} + \end{bytefield} + \asm{\insnmipsref{CLC} cd, rt, offset(cb)} + + \begin{bytefield}{32} + \bitbox{6}{0x1d} + \bitbox{5}{cs} + \bitbox{5}{cb} + \bitbox{16}{offset} + \end{bytefield} + \asm{\insnmipsref{CLCBI} cd, offset(cb)}\\ + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x00} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{5}{rt} + \bitbox{6}{0x38} + \end{bytefield} + \asm{\insnmipsref{CLCNT} cd, rt(cb)}\\ + + \vspace{1.5ex} + + \providecommand{\loadinst}[4]{ + \begin{bytefield}{32} + \ifthenelse{\equal{#4}{1}} + {\bitheader[endianness=big]{0,1,2,3,10,11,15,16,20,21,25,26,31}}{}\\ + \bitbox{6}{0x32} + \bitbox{5}{rd} + \bitbox{5}{cb} + \bitbox{5}{rt} + \bitbox{8}{offset} + \bitbox{1}{#2} + \bitbox{2}{#3} + \end{bytefield} + \asm{\insnmipsref[clbhwd]{CL#1} rd, rt, offset(cb)} + + } + + \loads{} + + \providecommand{\storeinst}[3]{ + \begin{bytefield}{32} + \bitbox{6}{0x3a} + \bitbox{5}{rs} + \bitbox{5}{cb} + \bitbox{5}{rt} + \bitbox{8}{offset} + \bitbox{1}{0} + \bitbox{2}{#2} + \end{bytefield} + \asm{\insnmipsref[csbhwd]{CS#1} rs, rt, offset(cb)} + + } + + \stores{} + + \optype{Atomic Memory-Access} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,1,2,3,6,10,11,15,16,20,21,25,26,31}\\ + \bitbox{6}{0x12} + \bitbox{5}{0x10} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{7}{\color{lightgray}\rule{\width}{\height}} + \bitbox{4}{0xf} + \end{bytefield} + \asm{\insnmipsref{CLLC} cd, cb} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x10} + \bitbox{5}{cs} + \bitbox{5}{cb} + \bitbox{5}{rd} + \bitbox{2}{\color{lightgray}\rule{\width}{\height}} + \bitbox{4}{0x7} + \end{bytefield} + \asm{\insnmipsref{CSCC} rd, cs, cb} + + \vspace{1.5ex} + + \renewcommand{\loadinst}[4]{ + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x10} + \bitbox{5}{rd} + \bitbox{5}{cb} + \bitbox{7}{\color{lightgray}\rule{\width}{\height}} + \bitbox{1}{1} + \bitbox{1}{#2} + \bitbox{2}{#3} + \end{bytefield} + \asm{\insnmipsref[cllbhwd]{CLL#1} rd, cb} + + } + + \loads{} + + \renewcommand{\storeinst}[3]{ + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x10} + \bitbox{5}{rs} + \bitbox{5}{cb} + \bitbox{5}{rd} + \bitbox{2}{\color{lightgray}\rule{\width}{\height}} + \bitbox{2}{0} + \bitbox{2}{#2} + \end{bytefield} + \asm{\insnmipsref[cscbhwd]{CSC#1} rd, cb} + + } + + \stores{} + + \optype{Tag-Memory Access} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x00} + \bitbox{5}{rd} + \bitbox{5}{cb} + \bitbox{5}{0x1E} + \bitbox{5}{0x3F} + \end{bytefield} + \asm{\insnmipsref{CLoadTags} rd, cb} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x00} + \bitbox{5}{cb} + \bitbox{5}{0x18} + \bitbox{5}{0x1F} + \bitbox{5}{0x3F} + \end{bytefield} + \asm{\insnmipsref{CClearTags} cb} + + \subsection{Encoding Summary} + + All three-register-operand, non-memory-accessing CHERI-MIPS instructions use the following encoding: + + \vspace{1em} + + \cherithreeop[header]{func}{r1}{r2}{r3} + + \vspace{1em} + + {\scriptsize + \begin{tabular}{r|cccccccc} + & 000 & 001 & 010 & 011 & 100 & 101 & 110 & 111 \\ \hline + 000 & CGetPerm* & CGetType* & CGetBase* & CGetLen* & CGetCause* & CGetTag* & CGetSealed* & CGetPCC* \\ + 001 & \insnmipsref*{CSetBounds} & \insnmipsref*{CSetBoundsExact} & \insnmipsref*{CSub} & \insnmipsref*{CSeal} & \insnmipsref*{CUnseal} & \insnmipsref*{CAndPerm} & \insnmipsref*{CSetFlags} & \insnmipsref*{CSetOffset} \\ + 010 & - & \insnmipsref*{CIncOffset} & \insnmipsref*{CToPtr} & \insnmipsref*{CFromPtr} & \insnmipsref*[cptrcmp]{CEQ} & \insnmipsref*[cptrcmp]{CNE} & \insnmipsref*[cptrcmp]{CLT} & \insnmipsref*[cptrcmp]{CLE} \\ + 011 & \insnmipsref*[cptrcmp]{CLTU} & \insnmipsref*[cptrcmp]{CLEU} & \insnmipsref*[cptrcmp]{CEXEQ} & \insnmipsref*{CMovN}** & \insnmipsref*{CMovZ}** & \insnmipsref*{CBuildCap} & \insnmipsref*{CCopyType} & \insnmipsref*{CCSeal} \\ + 100 & \insnmipsref*{CTestSubset} & \insnmipsref*[cptrcmp]{CNEXEQ} & \insnmipsref*{CSetAddr}** & \insnmipsref*{CGetAndAddr}** & \insnmipsref*{CAndAddr}** & - & - & - \\ + 101 & - & - & - & - & - & - & - & - \\ + 110 & - & - & - & - & - & - & - & - \\ + 111 & \insnmipsref*{CLCNT}$**$ & - & - & - & - & - & - & Two Op$\dagger$ \\ + \end{tabular} + + \begin{itemize} + \item[*] Deprecated encoding for instruction + \item[**] Reserved instruction slot for future opcode + \item[$\dagger$] This value is used for two-operand instructions. + \end{itemize} + } + + \vspace{1em} + +% This frees several minor opcodes free and allows us to allocate 35 more three-operand instructions immediately, and eight more once the deprecated encodings are removed, without having to allocate a new minor opcode. + + All two-operand instructions are of the following form: + + \vspace{1em} + + \cheritwoop[header]{func}{r1}{r2} + + \vspace{1em} + + {\scriptsize + \begin{tabular}{r|cccccccc} + & 000 & 001 & 010 & 011 & 100 & 101 & 110 & 111 \\ \hline + 00 & \insnmipsref*{CGetPerm} & \insnmipsref*{CGetType} & \insnmipsref*{CGetBase} & \insnmipsref*{CGetLen} & \insnmipsref*{CGetTag} & \insnmipsref*{CGetSealed} & \insnmipsref*{CGetOffset} & \insnmipsref*{CGetPCCSetOffset} \\ + 01 & -** & -** & \insnmipsref*{CMove} & \insnmipsref*{CClearTag} & \insnmipsref*{CJALR} & \insnmipsref*{CReadHwr} & \insnmipsref*{CWriteHwr} & \insnmipsref*{CGetAddr} \\ + 10 & \insnmipsref*{CRRL} & \insnmipsref*{CRAM} & \insnmipsref*{CGetFlags} & \insnmipsref*{CGetPCCIncOffset} & \insnmipsref*{CGetPCCSetAddr} & - & - & - \\ + 11 & - & - & - & - & \insnmipsref*{CSealEntry} & - & \insnmipsref*{CLoadTags}* & One Op$\dagger$ \\ + \end{tabular} + + \begin{itemize} + \item[*] This instruction accesses tag memory. + \item[**] This value was previously used by a removed instruction. + \item[$\dagger$] This value is used for one-operand instructions. + \end{itemize} + } + + \vspace{1em} + +% This allows us to allocate 21 new two-operand instructions without consuming a minor opcode. + + All one-operand instructions are of the following form: + + \vspace{1em} + + \cherioneop[header]{func}{r1} + + \vspace{1em} + + {\scriptsize + \begin{tabular}{r|cccccccc} + & 000 & 001 & 010 & 011 & 100 & 101 & 110 & 111 \\ \hline + 00 & \insnmipsref*{CGetPCC} & \insnmipsref*{CGetCause} & \insnmipsref*{CSetCause} & \insnmipsref*{CJR} & \insnmipsref*{CGetCID}$\dagger$ & \insnmipsref*{CSetCID}$\dagger$ & \insnmipsref*{CCheckTag} & - \\ + 01 & - & - & - & - & - & - & - & - \\ + 10 & - & - & - & - & - & - & - & - \\ + 11 & \insnmipsref*{CClearTags}$*\dagger$ & - & - & - & - & - & - & - \\ + \end{tabular} + + \begin{itemize} + \item[*] This instruction accesses tag memory. + \item[$\dagger$] Opcode may change + \end{itemize} + } + +\section{Deprecated/Removed Encodings} + + The following encodings were present in prior CHERI ISA versions, but have been deprecated or removed. + + \optype{Capability-Inspection} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,2,3,10,11,15,16,20,21,25,26,31}\\ + \bitbox{6}{0x12} + \bitbox{5}{0x0} + \bitbox{5}{rd} + \bitbox{5}{cb} + \bitbox{8}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x0} + \end{bytefield} + \asm{\insnmipsref{CGetPerm} rd, cb} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x0} + \bitbox{5}{rd} + \bitbox{5}{cb} + \bitbox{8}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x1} + \end{bytefield} + \asm{\insnmipsref{CGetType} rd, cb} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x0} + \bitbox{5}{rd} + \bitbox{5}{cb} + \bitbox{8}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x2} + \end{bytefield} + \asm{\insnmipsref{CGetBase} rd, cb} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x0} + \bitbox{5}{rd} + \bitbox{5}{cb} + \bitbox{8}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x3} + \end{bytefield} + \asm{\insnmipsref{CGetLen} rd, cb} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x0} + \bitbox{5}{rd} + \bitbox{5}{cb} + \bitbox{8}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x5} + \end{bytefield} + \asm{\insnmipsref{CGetTag} rd, cb} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x0} + \bitbox{5}{rd} + \bitbox{5}{cb} + \bitbox{8}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x6} + \end{bytefield} + \asm{\insnmipsref{CGetSealed} rd, cb} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x0d} + \bitbox{5}{rd} + \bitbox{5}{cb} + \bitbox{8}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x2} + \end{bytefield} + \asm{\insnmipsref{CGetOffset} rd, cb} + + \cherioneop{0x0}{cd} + \asm{\insnmipsref{CGetPCC} cd} + + \cheritwoop{0x7}{cd}{rs} + \asm{\insnmipsref{CGetPCCSetOffset} cd, rs} + + \optype{Capability-Modification} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ + \bitbox{6}{0x12} + \bitbox{5}{0x02} + \bitbox{5}{cd} + \bitbox{5}{cs} + \bitbox{5}{ct} + \bitbox{6}{\color{lightgray}\rule{\width}{\height}} + \end{bytefield} + \asm{\insnmipsref{CSeal} cd, cs, ct} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x03} + \bitbox{5}{cd} + \bitbox{5}{cs} + \bitbox{5}{ct} + \bitbox{6}{\color{lightgray}\rule{\width}{\height}} + \end{bytefield} + \asm{\insnmipsref{CUnseal} cd, cs, ct}\\ + + \vspace{1.5ex} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,2,3,5,6,10,11,15,16,20,21,25,26,31}\\ + \bitbox{6}{0x12} + \bitbox{5}{0x04} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{5}{rt} + \bitbox{3}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x0} + \end{bytefield} + \asm{\insnmipsref{CAndPerm} cd, cb, rt} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x04} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{8}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x5} + \end{bytefield} + \asm{\insnmipsref{CClearTag} cd, cb} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x0d} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{5}{rt} + \bitbox{3}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x0} + \end{bytefield} + \asm{\insnmipsref{CIncOffset} cd, cb, rt} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x13} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{11}{increment} + \end{bytefield} + \asm{\insnmipsref{CIncOffsetImm} cd, cb, increment} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x0d} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{5}{rt} + \bitbox{3}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x1} + \end{bytefield} + \asm{\insnmipsref{CSetOffset} cd, cb, rt} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x01} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{5}{rt} + \bitbox{6}{\color{lightgray}\rule{\width}{\height}} + \end{bytefield} + \asm{\insnmipsref{CSetBounds} cd, cb, rt} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x0} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{5}{rt} + \bitbox{6}{0x9} + \end{bytefield} + \asm{\insnmipsref{CSetBoundsExact} cd, cb, rt} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x14} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{11}{length} + \end{bytefield} + \asm{\insnmipsref{CSetBoundsImm} cd, cb, length} + + \optype{Pointer-Arithmetic} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ + \bitbox{6}{0x12} + \bitbox{5}{0x0c} + \bitbox{5}{rd} + \bitbox{5}{cb} + \bitbox{5}{ct} + \bitbox{6}{\color{lightgray}\rule{\width}{\height}} + \end{bytefield} + \asm{\insnmipsref{CToPtr} rd, cb, ct} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x04} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{5}{rt} + \bitbox{3}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x7} + \end{bytefield} + \asm{\insnmipsref{CFromPtr} cd, cb, rt} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x0} + \bitbox{5}{rt} + \bitbox{5}{cb} + \bitbox{5}{ct} + \bitbox{6}{0xa} + \end{bytefield} + \asm{\insnmipsref{CSub} rt, cb, ct} + + + \optype{Pointer-Comparison} + + \newcommand{\cptrcmp}[3]{ + \begin{bytefield}{32} + \ifthenelse{\equal{#3}{1}} + {\bitheader[endianness=big]{0,2,3,5,6,10,11,15,16,20,21,25,26,31}}{}\\ + \bitbox{6}{0x12} + \bitbox{5}{0x0e} + \bitbox{5}{rd} + \bitbox{5}{cb} + \bitbox{5}{ct} + \bitbox{3}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{#2} + \end{bytefield} + \asm{\insnmipsref[cptrcmp]{C#1} rd, cb, ct} + + } + + \cptrcmp{EQ}{0}{1} + \cptrcmp{NE}{1}{0} + \cptrcmp{LT}{2}{0} + \cptrcmp{LE}{3}{0} + \cptrcmp{LTU}{4}{0} + \cptrcmp{LEU}{5}{0} + \cptrcmp{EXEQ}{6}{0} + + \optype{Exception-Handling} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,2,3,5,6,10,11,15,16,20,21,25,26,31} \\ + \bitbox{6}{0x12} + \bitbox{5}{0x0} + \bitbox{5}{rd} + \bitbox{5}{0x0} + \bitbox{8}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x4} + \end{bytefield} + \asm{\insnmipsref{CGetCause} rd} + + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x04} + \bitbox{5}{0x0} + \bitbox{5}{0x0} + \bitbox{5}{rt} + \bitbox{3}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x4} + \end{bytefield} + \asm{\insnmipsref{CSetCause} rd} + + \optype{Control-Flow} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,15,16,25,20,21,25,26,31}\\ + \bitbox{6}{0x12} + \bitbox{5}{0x09} + \bitbox{5}{cd} + \bitbox{16}{offset} + \end{bytefield} + \asm{\insnmipsref{CBTU} cd, offset} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x0a} + \bitbox{5}{cd} + \bitbox{16}{offset} + \end{bytefield} + \asm{\insnmipsref{CBTS} cd, offset} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x11} + \bitbox{5}{cd} + \bitbox{16}{offset} + \end{bytefield} + \asm{\insnmipsref{CBEZ} cd, offset} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x12} + \bitbox{5}{cd} + \bitbox{16}{offset} + \end{bytefield} + \asm{\insnmipsref{CBNZ} cd, offset} + + \vspace{1.5ex} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ + \bitbox{6}{0x12} + \bitbox{5}{0x08} + \bitbox{5}{\color{lightgray}\rule{\width}{\height}} + \bitbox{5}{cb} + \bitbox{11}{\color{lightgray}\rule{\width}{\height}} + \end{bytefield} + \asm{\insnmipsref{CJR} cb} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x07} + \bitbox{5}{cd} + \bitbox{5}{cb} + \bitbox{11}{\color{lightgray}\rule{\width}{\height}} + \end{bytefield} + \asm{\insnmipsref{CJALR} cd, cb}\\ + + \vspace{1.5ex} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,10,11,15,16,20,21,25,26,31}\\ + \bitbox{6}{0x12} + \bitbox{5}{0x05} + \bitbox{5}{cs} + \bitbox{5}{cb} + \bitbox{11}{0x001} + \end{bytefield} + \asm{\insnmipsref{CInvoke} cs, cb} + + \optype{Assertion} + + \cheritwoop[header]{0x8}{cs}{rt} + \asm{\insnnoref{CCheckPerm} cs, rt} + + \cheritwoop{0x9}{cs}{cb} + \asm{\insnnoref{CCheckType} cs, cb} + + \vspace{1.5ex} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,2,3,5,6,10,11,15,16,20,21,25,26,31}\\ + \bitbox{6}{0x12} + \bitbox{5}{0x0b} + \bitbox{5}{cs} + \bitbox{5}{\color{lightgray}\rule{\width}{\height}} + \bitbox{5}{rt} + \bitbox{3}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x0} + \end{bytefield} + \asm{\insnnoref{CCheckPerm} cs, rt} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0x0b} + \bitbox{5}{cs} + \bitbox{5}{cb} + \bitbox{8}{\color{lightgray}\rule{\width}{\height}} + \bitbox{3}{0x1} + \end{bytefield} + \asm{\insnnoref{CCheckType} cs, cb} + + \optype{Fast Register-Clearing} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,15,16,20,21,25,26,31}\\ + \bitbox{6}{0x12} + \bitbox{5}{0xf} + \bitbox{5}{0x0} + \bitbox{16}{mask} + \end{bytefield} + \asm{\insnmipsref{ClearLo} mask} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0xf} + \bitbox{5}{0x1} + \bitbox{16}{mask} + \end{bytefield} + \asm{\insnmipsref{ClearHi} mask} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0xf} + \bitbox{5}{0x2} + \bitbox{16}{mask} + \end{bytefield} + \asm{\insnmipsref{CClearLo} mask} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0xf} + \bitbox{5}{0x3} + \bitbox{16}{mask} + \end{bytefield} + \asm{\insnmipsref{CClearHi} mask} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0xf} + \bitbox{5}{0x4} + \bitbox{16}{mask} + \end{bytefield} + \asm{\insnmipsref{FPClearLo} mask} + + \begin{bytefield}{32} + \bitbox{6}{0x12} + \bitbox{5}{0xf} + \bitbox{5}{0x5} + \bitbox{16}{mask} + \end{bytefield} + \asm{\insnmipsref{FPClearHi} mask} + + \optype{Deprecated and Removed} + +% \begin{bytefield}{32} +% \bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ +% \bitbox{6}{0x12} +% \bitbox{5}{0x04} +% \bitbox{5}{cd} +% \bitbox{5}{cb} +% \bitbox{5}{rt} +% \bitbox{3}{\color{lightgray}\rule{\width}{\height}} +% \bitbox{3}{0x3} +% \end{bytefield} +% \asm{\insnmipsref{CSetLen} cd, cb, rt} + +% \begin{bytefield}{32} +% \bitbox{6}{0x12} +% \bitbox{5}{0x04} +% \bitbox{5}{cd} +% \bitbox{5}{cb} +% \bitbox{5}{rt} +% \bitbox{3}{\color{lightgray}\rule{\width}{\height}} +% \bitbox{3}{0x2} +% \end{bytefield} +% \asm{\insnmipsref{CIncBase} cd, cb, rt} + +% \vspace{1.5ex} + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,15,16,25,20,21,25,26,31}\\ + \bitbox{6}{0x32} + \bitbox{5}{rd} + \bitbox{5}{cb} + \bitbox{5}{rt} + \bitbox{8}{offset} + \bitbox{1}{1} + \bitbox{2}{3} + \end{bytefield} + \asm{\insnmipsref[cllbhwd]{CLLD} rd, rt, offset(cb)} + + \begin{bytefield}{32} + \bitbox{6}{0x3a} + \bitbox{5}{rs} + \bitbox{5}{cb} + \bitbox{5}{rt} + \bitbox{8}{offset} + \bitbox{1}{1} + \bitbox{2}{3} + \end{bytefield} + \asm{\insnmipsref[cscbhwd]{CSCD} rs, rt, offset(cb)}\\ + +} + +\newpage diff --git a/app-isaquick-riscv-macros.tex b/app-isaquick-riscv-macros.tex new file mode 100644 index 00000000..8539f648 --- /dev/null +++ b/app-isaquick-riscv-macros.tex @@ -0,0 +1,32 @@ +\input{app-isaquick-table-macros} + +\makeatletter +\newcommand{\rvcherienctabletop}{\@cherienctable{@rvcheriencusetablestr}{top}{8}} +\newcommand{\rvcherienctablesrcsrcdest}{\@cherienctable{@rvcheriencusetablestr}{srcsrcdest}{128}} +\newcommand{\rvcherienctablesrcsrc}{\@cherienctable{@rvcheriencusetablestr}{srcsrc}{32}} +\newcommand{\rvcherienctablesrc}{\@cherienctable{@rvcheriencusetablestr}{src}{32}} +\newcommand{\rvcherienctablesrcdest}{\@cherienctable{@rvcheriencusetablestr}{srcdest}{32}} +\newcommand{\rvcherienctabledest}{\@cherienctable{@rvcheriencusetablestr}{dest}{32}} +\newcommand{\rvcherienctableexpload}{\@cherienctable{@rvcheriencusetablestr}{expload}{32}} +\newcommand{\rvcherienctableexpstore}{\@cherienctable{@rvcheriencusetablestr}{expstore}{32}} + +\let\rvcheriasminsnref\insnriscvref +\let\rvcheriasminsnnoref\insnnoref +\providecommand{\rvcheriasmfmt}{} +\renewcommand{\rvcheriasmfmt}[2][]{% + ~\raiseforbf{% + \textsf{\footnotesize{#2}}% + \ifthenelse{\equal{#1}{}}{% + }{% + ~{\textit{\scriptsize{(#1)}}}% + }% + }% +} + +\newcommand{\rvcheriisaquick}[1]{% + \rvcheribitbox{#1}~\rvcheriasm{#1}% +} + +\newcommand{\riscvbitboxaq}{\rotateinbitbox{\small aq}} +\newcommand{\riscvbitboxrl}{\rotateinbitbox{\small rl}} +\makeatother diff --git a/app-isaquick-riscv.tex b/app-isaquick-riscv.tex new file mode 100644 index 00000000..805d42f4 --- /dev/null +++ b/app-isaquick-riscv.tex @@ -0,0 +1,827 @@ +{ +\setlength{\parindent}{0cm} + +\input{def-riscv-insns} +\input{app-isaquick-riscv-macros} + +\chapter{CHERI-RISC-V ISA Quick Reference} +\label{app:isaquick-riscv} + + \section{Primary New Instructions} + + The RISC-V specification reserves 4 major opcodes for extensions: 11 (0xb / 0b0001011), 43 (0x2b / 0b0101011), 91 (0x5b / 0b1011011), and 123 (0x7b / 0b1111011). + The proposed CHERI encodings use major opcode 0x5b for all capability instructions. + + All register-register operations use the RISC-V R-type or I-type encoding formats. + \optype{Capability-Inspection} + + \mrnote{What is the RISC-V equivalent of CPtrCmp?} + \jwnote{Wouldn't the legacy comparisons do the trick? (described above)} + + \mrnote{We need to add \insnriscvref{CGetAddr}} + + \mrnote{Given that, unlike CHERI-MIPS, CHERI RISC-V does not yet + have a backwards-compatibility problem, we might take the opportunity + to rationalize the bit positions of permission bits.} + + \mmnote{I would prefer being able to click on the quick reference and jumping to the RISC-V specific Sail definitions.} + + \rvcheriheader + \rvcheriisaquick{CGetPerm} + + \rvcheriisaquick{CGetType} + + \rvcheriisaquick{CGetBase} + + \rvcheriisaquick{CGetLen} + + \rvcheriisaquick{CGetTag} + + \rvcheriisaquick{CGetSealed} + + \rvcheriisaquick{CGetOffset} + + \rvcheriisaquick{CGetFlags} + + \rvcheriisaquick{CGetAddr} + + \dcnote{CGetPCC is a Special} + + \dcnote{CGetPCCSetOffset is AIUPC} + + \optype{Capability-Modification} + + \rvcheriheader + \rvcheriisaquick{CSeal} + + \rvcheriisaquick{CUnseal} + + \rvcheriisaquick{CAndPerm} + + \rvcheriisaquick{CSetFlags} + + \rvcheriisaquick{CSetOffset} + + \rvcheriisaquick{CSetAddr} + + \rvcheriisaquick{CIncOffset} + + \rvcheriisaquick{CIncOffsetImm} + + \rvcheriisaquick{CSetBounds} + + \rvcheriisaquick{CSetBoundsExact} + + \rvcheriisaquick{CSetBoundsImm} + + \rvcheriisaquick{CClearTag} + + \rvcheriisaquick{CBuildCap} + + \rvcheriisaquick{CCopyType} + + \rvcheriisaquick{CCSeal} + + \rvcheriisaquick{CSealEntry} + + \optype{Pointer-Arithmetic} + + \dcnote{We might want a variant of these that works with DDC, because it's no longer a GPCR.} + + \mrnote{The CHERI-MIPS way to get NULL is CFromPtr of \$zero and \$DDC, which will be a pain if \$DDC is a special register. Do we have a NULL capability register in RISC-V? If \$DDC is a special register, is it more important to have CFromPtr?} + \arnote{In the merged register file model we would have a NULL capability register + zero, which we should also keep in a potential split implementation (and finally add + to CHERI-MIPS as well). In that case we don't need a cfromptr \$zero since we can + just do a CInc/SetOffset \$cOut, \$cNULL, \$gpr. + + To get a capability from DDC we should have a CFromDDC/CGetDDCSetOffset. + We also wouldn't need to use a new opcode for this since CToPtr raises an + exception on tag missing. Therefore, using it with the NULL register does not + make sense and we could use that encoding for CFromDDC. + If that complicates the decoder too much we can just keep that as an always + trapping instruction and add a separate CFromDDC opcode.} + + \rvcheriheader + \rvcheriisaquick{CToPtr} + + \rvcheriisaquick{CFromPtr} + + \jwnote{We do not need CSub, since a standard Sub will return the difference between two capabilities.} + + \jrtcnote{We do need a separate CSub with a split register file though, + so we define one that should be used even with a merged register file.} + + \rvcheriisaquick{CSub} + + \rvcheriisaquick{CMove} + + %\dcnote{We probably shouldn't have these, because RISC-V doesn't have equivalents for integer registers - or we should define these as working on all registers.} + + %\mrnote{If we have conditional moves, CMOVZ with a zero register + %can be used instead of CMove.} + + %\mrnote{I thought in the MIPS case, we added + %integer and capability conditional moves because they + %were important for performance. CHERI-MIPS was originally planned to + %be MIPS III compatible, and we upgraded to MIPS IV mainly to get + %the integer conditional moves. It seems likely the same performance + %argument will apply to RISC-V.} + + %\rvcheriisaquick{CMOVZ} + + %\rvcheriisaquick{CMOVN} + + %\optype{Pointer-Comparison} + % We inherit most of these from the RISC-V base specification. + % We should add EXEQ, NEXEQ and possibly EQ / NE which are omitted in the base spec + + %\ptrcmp[header]{EQ}{0x14} + %\ptrcmp{NE}{0x15} + %\ptrcmp{LT}{0x16} + %\ptrcmp{LE}{0x17} + %\ptrcmp{LTU}{0x18} + %\ptrcmp{LEU}{0x19} + %\ptrcmp{NEXEQ}{0x21} + %\ptrcmp{EXEQ}{0x1a} + + \optype{Pointer-Comparison} + + \rvcheriisaquick{CTestSubset} + + \rvcheriisaquick{CSetEqualExact} + + \optype{Control-Flow} + + \dcnote{RISC-V branch instructions all take two registers, so we end up with a lot of spare bits if we want to use one for CBTS / CBTU. It's probably better to fit them somewhere else in the opcode map. Given that they're not common (outside of fast path selection for dynamic languages, where they may be performance critical), I'm inclined to suggest that we should omit them for now and later decide if it's better to do fusion on the CGetTag + BEZ / BNZ sequence or add them as new branches.} + + \vspace{1.5ex} + + \dcnote{We probably don't need CJR to be a separate instruction, because we can use CJALR with the zero register as the link register} + + \rvcheriisaquick{CJALR} + + \vspace{1.5ex} + + \rvcheriisaquick{CInvoke} + + \optype{Special Capabilty Register Access} + + \rvcheriisaquick{CSpecialRW} + + \optype{Fast Register-Clearing} + + \jwnote{These require 4 instructions to clear a complete register file, + once for each quarter, with an 8-bit mask for each.} + + \rvcheriheader + \rvcheriisaquick{Clear} + + \rvcheriisaquick{CClear} + + \rvcheriisaquick{FPClear} + + \optype{Adjusting to Compressed Capability Precision} + + \rvcheriisaquick{CRoundRepresentableLength} + + \rvcheriisaquick{CRepresentableAlignmentMask} + +\optype{Tag-Memory Access} + +\rvcheriisaquick{CLoadTags} + +\rvcheriisaquick{CClearTags} + +\optype{Memory Loads with Explicit Address Type} + +These memory load instructions explicitly expect either capability addresses +or integer offsets to \DDC{}, with bounds coming either from cs1 or \DDC{} +respectively. For non-reserved loads, the encoding of bits 24 to 20 tries to +follow the standard RISC-V mapping for the width and signedness of the memory +access: +\begin{description} +\item [bit 24] 0 to indicate non-reserved load. +\item [bit 23] When 0, the load is DDC relative. Explicit capability is provided otherwise. +\item [bit 22] When 0, the result of the load is sign-extended, and zero-extended otherwise. +\item [bit 21-20] 00 loads a byte, 01 loads a half-word, 10 loads a word, 11 loads a double-word. +\end{description} + +For reserved loads (which require the A extension), the encoding of bits 24 to +20 tries to follow the standard RISC-V mapping for the width of the memory +access: +\begin{description} +\item [bit 24] 1 to indicate LR version of the load. +\item [bit 23] When 0, the load is DDC relative. Explicit capability is provided otherwise. +\item [bit 22-20] 000 loads a byte, 001 loads a half-word, 010 loads a word, 011 loads a double-word, 100 loads a quad-word/capability. +\end{description} + +Note that the RISC-V A extension (atomic) does not add unsigned versions of the +LR instruction.\\ +Note that the LQ.\{DDC, CAP\} instructions do not strictly follow this +pattern.\\ + +\vspace{1em} + +\rvcheriheader +\rvcheriisaquick{LB.DDC} + +\rvcheriisaquick{LH.DDC} + +\rvcheriisaquick{LW.DDC} + +\rvcheriisaquick{LC.DDC:RV32} + +\rvcheriisaquick{LD.DDC:RV64/128} + +\rvcheriisaquick{LC.DDC:RV64} + +\rvcheriisaquick{LQ.DDC:RV128} + +\rvcheriisaquick{LBU.DDC} + +\rvcheriisaquick{LHU.DDC} + +\rvcheriisaquick{LWU.DDC:RV64/128} + +\rvcheriisaquick{LDU.DDC:RV128} + +\rvcheriisaquick{LB.CAP} + +\rvcheriisaquick{LH.CAP} + +\rvcheriisaquick{LW.CAP} + +\rvcheriisaquick{LC.CAP:RV32} + +\rvcheriisaquick{LD.CAP:RV64/128} + +\rvcheriisaquick{LC.CAP:RV64} + +\rvcheriisaquick{LQ.CAP:RV128} + +\rvcheriisaquick{LBU.CAP} + +\rvcheriisaquick{LHU.CAP} + +\rvcheriisaquick{LWU.CAP:RV64/128} + +\rvcheriisaquick{LDU.CAP:RV128} + +\rvcheriisaquick{LR.B.DDC} + +\rvcheriisaquick{LR.H.DDC} + +\rvcheriisaquick{LR.W.DDC} + +\rvcheriisaquick{LR.C.DDC:RV32} + +\rvcheriisaquick{LR.D.DDC:RV64/128} + +\rvcheriisaquick{LR.C.DDC:RV64} + +\rvcheriisaquick{LR.Q.DDC:RV128} + +\rvcheriisaquick{LR.B.CAP} + +\rvcheriisaquick{LR.H.CAP} + +\rvcheriisaquick{LR.W.CAP} + +\rvcheriisaquick{LR.C.CAP:RV32} + +\rvcheriisaquick{LR.D.CAP:RV64/128} + +\rvcheriisaquick{LR.C.CAP:RV64} + +\rvcheriisaquick{LR.Q.CAP:RV128} + +\vspace{1em} + +\optype{Memory Stores with Explicit Address Type} + +These memory store instructions explicitly expect either capability addresses +or integer offsets to \DDC{}, with bounds coming either from cs1 or \DDC{} +respectively. The encoding of bits 11 to 7 tries to follow the standard RISC-V +mapping for the width of the memory access: +\begin{description} +\item [bit 11] When 1 with the A extension, SC version of the store. +\item [bit 10] When 0, the store is DDC relative. Explicit capability is provided otherwise. +\item [bit 9-7] 000 stores a byte, 001 stores a half-word, 010 stores a word, 011 stores a double-word, 100 stores a quad-word/capability. +\end{description} + +\vspace{1em} + +\rvcheriheader +\rvcheriisaquick{SB.DDC} + +\rvcheriisaquick{SH.DDC} + +\rvcheriisaquick{SW.DDC} + +\rvcheriisaquick{SC.DDC:RV32} + +\rvcheriisaquick{SD.DDC:RV64/128} + +\rvcheriisaquick{SC.DDC:RV64} + +\rvcheriisaquick{SQ.DDC:RV128} + +\rvcheriisaquick{SB.CAP} + +\rvcheriisaquick{SH.CAP} + +\rvcheriisaquick{SW.CAP} + +\rvcheriisaquick{SC.CAP:RV32} + +\rvcheriisaquick{SD.CAP:RV64/128} + +\rvcheriisaquick{SC.CAP:RV64} + +\rvcheriisaquick{SQ.CAP:RV128} + +\rvcheriisaquick{SC.B.DDC} + +\rvcheriisaquick{SC.H.DDC} + +\rvcheriisaquick{SC.W.DDC} + +\rvcheriisaquick{SC.C.DDC:RV32} + +\rvcheriisaquick{SC.D.DDC:RV64/128} + +\rvcheriisaquick{SC.C.DDC:RV64} + +\rvcheriisaquick{SC.Q.DDC:RV128} + +\rvcheriisaquick{SC.B.CAP} + +\rvcheriisaquick{SC.H.CAP} + +\rvcheriisaquick{SC.W.CAP} + +\rvcheriisaquick{SC.C.CAP:RV32} + +\rvcheriisaquick{SC.D.CAP:RV64/128} + +\rvcheriisaquick{SC.C.CAP:RV64} + +\rvcheriisaquick{SC.Q.CAP:RV128} + + \section{Memory-Access via Capability with Offset Instructions} + + \optype{Memory-Access} + + \dcnote{I'm not certain about operand order for these, because the RISC-V spec is too vague. LC/SC fit into the existing load / store encoding space, capability-base versions use the same layout for loads and stores currently, though there's no reason that we couldn't shuffle things around if it simplifies decoding.} + \vspace{1.5ex} + + \ajnote{Jon points out that if preserving the information of what kind of load loaded the pointer in the first place (which happens to be available early in decode, hence not introducing data dependent decoding later on), we can dereference it as a capability or a 64-bit pointer without relying on a new set of load/store instructions. I wonder whether this is a practical approach, or wether things like loading data via a 128-bit load and dereferencing a subset of that data as a 64-bit pointer is ever useful as this would no longer work (in context switches maybe that could be an issue?)} + +When using 64-bit capabilities in RV32, the RV64 instructions \texttt{LD} and \texttt{SD} are reused to behave as \texttt{LC} and \texttt{SC} respectively.\\ + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,6,7,11,12,14,15,19,20,24,25,31}\\ + \bitbox{12}{imm} + \bitbox{5}{rs1} + \bitbox{3}{0x3} + \bitbox{5}{cd} + \bitbox{7}{0x3} + \end{bytefield} + \rvcheriasmfmt[RV32]{\rvcheriasminsnref{LC} cd, rs1, imm} + + \begin{bytefield}{32} + \bitbox{7}{imm[11:5]} + \bitbox{5}{cs2} + \bitbox{5}{rs1} + \bitbox{3}{0x3} + \bitbox{5}{imm[0:4]} + \bitbox{7}{0x23} + \end{bytefield} + \rvcheriasmfmt[RV32]{\rvcheriasminsnref{SC} cs2, rs1, imm}\\ + +When using 128-bit capabilities in RV64, the RV128 instructions \texttt{LQ} and \texttt{SQ} \textit{(anticipated encoding)} are reused to behave as \texttt{LC} and \texttt{SC} respectively.\\ + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,6,7,11,12,14,15,19,20,24,25,31}\\ + \bitbox{12}{imm} + \bitbox{5}{rs1} + \bitbox{3}{0x2} + \bitbox{5}{cd} + \bitbox{7}{0xf} + \end{bytefield} + \rvcheriasmfmt[RV64]{\rvcheriasminsnref{LC} cd, rs1, imm} + + \begin{bytefield}{32} + \bitbox{7}{imm[11:5]} + \bitbox{5}{cs2} + \bitbox{5}{rs1} + \bitbox{3}{0x4} + \bitbox{5}{imm[0:4]} + \bitbox{7}{0x23} + \end{bytefield} + \rvcheriasmfmt[RV64]{\rvcheriasminsnref{SC} cs2, rs1, imm}\\ + + \optype{Atomic Memory-Access} + +When using 64-bit capabilities in RV32, the RV64A instructions \texttt{LR.D}, \texttt{SC.D} and \texttt{AMOSWAP.D} are reused to behave as \texttt{LR.C}, \texttt{SC.C} and \texttt{AMOSWAP.C} respectively.\\ + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,6,7,11,12,14,15,19,20,24,25,26,27,31}\\ + \bitbox{5}{0x2} + \bitbox{1}{\riscvbitboxaq} + \bitbox{1}{\riscvbitboxrl} + \bitbox{5}{0x0} + \bitbox{5}{rs1} + \bitbox{3}{0x3} + \bitbox{5}{cd} + \bitbox{7}{0x2f} + \end{bytefield} + \rvcheriasmfmt[RV32]{\rvcheriasminsnnoref{LR.C} cd, rs1} + + \begin{bytefield}{32} + \bitbox{5}{0x3} + \bitbox{1}{\riscvbitboxaq} + \bitbox{1}{\riscvbitboxrl} + \bitbox{5}{cs2} + \bitbox{5}{rs1} + \bitbox{3}{0x3} + \bitbox{5}{rd} + \bitbox{7}{0x2f} + \end{bytefield} + \rvcheriasmfmt[RV32]{\rvcheriasminsnnoref{SC.C} rd, cs2, rs1} + + \begin{bytefield}{32} + \bitbox{5}{0x1} + \bitbox{1}{\riscvbitboxaq} + \bitbox{1}{\riscvbitboxrl} + \bitbox{5}{cs2} + \bitbox{5}{rs1} + \bitbox{3}{0x3} + \bitbox{5}{cd} + \bitbox{7}{0x2f} + \end{bytefield} + \rvcheriasmfmt[RV32]{\rvcheriasminsnnoref{AMOSWAP.C} cd, cs2, rs1} + +When using 128-bit capabilities in RV64, the RV64A instructions \texttt{LR.Q}, \texttt{SC.Q} and \texttt{AMOSWAP.Q} \textit{(anticipated encoding)} are reused to behave as \texttt{LR.C}, \texttt{SC.C} and \texttt{AMOSWAP.C} respectively.\\ + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,6,7,11,12,14,15,19,20,24,25,26,27,31}\\ + \bitbox{5}{0x2} + \bitbox{1}{\riscvbitboxaq} + \bitbox{1}{\riscvbitboxrl} + \bitbox{5}{0x0} + \bitbox{5}{rs1} + \bitbox{3}{0x4} + \bitbox{5}{cd} + \bitbox{7}{0x2f} + \end{bytefield} + \rvcheriasmfmt[RV64]{\rvcheriasminsnnoref{LR.C} cd, rs1} + + \begin{bytefield}{32} + \bitbox{5}{0x3} + \bitbox{1}{\riscvbitboxaq} + \bitbox{1}{\riscvbitboxrl} + \bitbox{5}{cs2} + \bitbox{5}{rs1} + \bitbox{3}{0x4} + \bitbox{5}{rd} + \bitbox{7}{0x2f} + \end{bytefield} + \rvcheriasmfmt[RV64]{\rvcheriasminsnnoref{SC.C} rd, cs2, rs1} + + \begin{bytefield}{32} + \bitbox{5}{0x1} + \bitbox{1}{\riscvbitboxaq} + \bitbox{1}{\riscvbitboxrl} + \bitbox{5}{cs2} + \bitbox{5}{rs1} + \bitbox{3}{0x4} + \bitbox{5}{cd} + \bitbox{7}{0x2f} + \end{bytefield} + \rvcheriasmfmt[RV64]{\rvcheriasminsnnoref{AMOSWAP.C} cd, cs2, rs1} + +We do not provide any of the other AMOs at this point when operating on +capability values, as they generally make sense only when operating on integer +values. + +Since capabilities have precise bounds, sub-word atomics cannot be implemented +using word-sized atomics. To avoid unnecessary complexity compared with a +non-CHERI RISC-V implementation, we define only \texttt{LR.B}, \texttt{SC.B}, +\texttt{LR.H} and \texttt{SC.H}, without any of the corresponding AMOs. We also +only require these to be present in capability mode, but implementations may +choose to always provide them for simplicity. + + \begin{bytefield}{32} + \bitheader[endianness=big]{0,6,7,11,12,14,15,19,20,24,25,26,27,31}\\ + \bitbox{5}{0x2} + \bitbox{1}{\riscvbitboxaq} + \bitbox{1}{\riscvbitboxrl} + \bitbox{5}{0x0} + \bitbox{5}{rs1} + \bitbox{3}{0x0} + \bitbox{5}{rd} + \bitbox{7}{0x2f} + \end{bytefield} + \rvcheriasmfmt{\rvcheriasminsnnoref{LR.B} rd, rs1} + + \begin{bytefield}{32} + \bitbox{5}{0x3} + \bitbox{1}{\riscvbitboxaq} + \bitbox{1}{\riscvbitboxrl} + \bitbox{5}{rs2} + \bitbox{5}{rs1} + \bitbox{3}{0x0} + \bitbox{5}{rd} + \bitbox{7}{0x2f} + \end{bytefield} + \rvcheriasmfmt{\rvcheriasminsnnoref{SC.B} rd, rs2, rs1} + + \begin{bytefield}{32} + \bitbox{5}{0x2} + \bitbox{1}{\riscvbitboxaq} + \bitbox{1}{\riscvbitboxrl} + \bitbox{5}{0x0} + \bitbox{5}{rs1} + \bitbox{3}{0x1} + \bitbox{5}{rd} + \bitbox{7}{0x2f} + \end{bytefield} + \rvcheriasmfmt{\rvcheriasminsnnoref{LR.H} rd, rs1} + + \begin{bytefield}{32} + \bitbox{5}{0x3} + \bitbox{1}{\riscvbitboxaq} + \bitbox{1}{\riscvbitboxrl} + \bitbox{5}{rs2} + \bitbox{5}{rs1} + \bitbox{3}{0x1} + \bitbox{5}{rd} + \bitbox{7}{0x2f} + \end{bytefield} + \rvcheriasmfmt{\rvcheriasminsnnoref{SC.H} rd, rs2, rs1} + + \section{Assembly Programming} + + \subsection{Capability Register ABI Names} + + Table~\ref{table:riscv-register-names} lists the ABI names of + the capability registers. The ABI names follow from the ABI + names of the RISC-V \textbf{x} registers. All capability registers are + Caller-Save in the hybrid ABI. Capability registers follow + the same save requirements as \textbf{x} registers in the purecap ABI. + +\begin{table}[h] +\begin{center} +\begin{tabular}{lllll} +\toprule +Register & ABI Name & Description & Hybrid Saver & Purecap Saver \\ +\midrule +c0 & cnull & NULL pointer & - & - \\ +c1 & cra & Return address & Caller & Caller \\ +c2 & csp & Stack pointer & Caller & Callee \\ +c3 & cgp & Global pointer & - & - \\ +c4 & ctp & Thread pointer & - & - \\ +c5 & ct0 & Temporary/alternate link register & Caller & Caller \\ +c6-7 & ct1-2 & Temporaries & Caller & Caller \\ +c8 & cs0/cfp & Saved register/frame pointer & Caller & Callee \\ +c9 & cs1 & Saved register & Caller & Callee \\ +c10-11 & ca0-1 & Function arguments/return values & Caller & Caller \\ +c12-17 & ca2-7 & Function arguments & Caller & Caller \\ +c18-27 & cs2-11 & Saved registers & Caller & Callee \\ +c28-31 & ct3-6 & Temporaries & Caller & Caller \\ +\bottomrule +\end{tabular} +\end{center} +\caption{Assembler mnemonics for CHERI RISC-V capability registers} +\label{table:riscv-register-names} +\end{table} + + \subsection{Capability Encoding Mode Instructions} + + Table~\ref{table:riscv-capmode-instructions} lists instructions + which change semantics under capability mode. + +\begin{table} +\begin{center} +\begin{tabular}{ll} +\toprule +Integer Instruction & Capability Instruction \\ +\midrule +\texttt{l\{b|h|w|d|c\} rd, offset(rs)} & \texttt{cl\{b|h|w|d|c\} rd, offset(cs)} \\ +\texttt{l\{b|h|w|d\}u rd, offset(rs)} & \texttt{cl\{b|h|w|d\}u rd, offset(cs)} \\ +\texttt{s\{b|h|w|d|c\} rs, offset(rd)} & \texttt{cs\{b|h|w|d|c\} rs, offset(cd)} \\ +\texttt{fl\{w|d|q\} fd, offset(rs)} & \texttt{cfl\{w|d|q\} fd, offset(cs)} \\ +\texttt{fs\{w|d|q\} fs, offset(rd)} & \texttt{cfs\{w|d|q\} fs, offset(cd)} \\ +\texttt{lr.\{b|h|w|d|c\} rd, (rs)} & \texttt{clr.\{b|h|w|d|c\} rd, (cs)} \\ +\texttt{sc.\{b|h|w|d|c\} rd, rs, (rm)} & \texttt{csc.\{b|h|w|d|c\} rd, rs, (cm)} \\ +\texttt{amo.\{w|d\}[.order] rd, rs, (rm)} & \texttt{camo.\{w|d\}[.order] rd, rs, (cm)} \\ +\texttt{auipc rd, offset} & \texttt{auipcc rd, offset} \\ +\texttt{c.jr rs} & \texttt{c.cjr cs} \\ +\texttt{c.jalr rs} & \texttt{c.cjalr cs} \\ +\texttt{c.l\{w|d\} rd, offset(rs)} & \texttt{c.cl\{w|d\} rd, offset(cs)} \\ +\texttt{c.l\{w|d\}sp rd, offset(sp)} & \texttt{c.cl\{w|d\}sp rd, offset(csp)} \\ +\texttt{c.s\{w|d\} rs, offset(rd)} & \texttt{c.cs\{w|d\} rs, offset(cd)} \\ +\texttt{c.s\{w|d\}sp rs, offset(sp)} & \texttt{c.cs\{w|d\}sp rs, offset(csp)} \\ +\texttt{c.flw fd, offset(rs)} & \texttt{c.cflw fd, offset(cs)} \\ +\texttt{c.flwsp fd, offset(sp)} & \texttt{c.cflwsp fd, offset(csp)} \\ +\texttt{c.fsw fs, offset(rd)} & \texttt{c.cfsw fs, offset(cd)} \\ +\texttt{c.fswsp fs, offset(sp)} & \texttt{c.cfswsp fs, offset(csp)} \\ +\texttt{c.fld fd, offset(rs)} & \texttt{c.clc cd, offset(cs)} \\ +\texttt{c.fldsp fd, offset(sp)} & \texttt{c.clcsp cd, offset(csp)} \\ +\texttt{c.fsd fs, offset(rd)} & \texttt{c.csc cs, offset(cd)} \\ +\texttt{c.fsdsp fs, offset(sp)} & \texttt{c.cscsp cs, offset(csp)} \\ +\bottomrule +\end{tabular} +\end{center} +\caption{Instructions Dependent on Encoding Mode} +\label{table:riscv-capmode-instructions} +\end{table} + + Table~\ref{table:riscv-capmode-pseudo-remove} lists psuedoinstructions + removed in capability mode. + Table~\ref{table:riscv-capmode-pseudo-add} lists psuedoinstructions + added in capability mode. + +\begin{table} +\begin{center} +\begin{tabular}{ll} +\toprule +Pseudoinstruction & Meaning \\ +\midrule +\texttt{la rd, symbol} & Load address \\ +\texttt{lla rd, symbol} & Load local address \\ +\texttt{l\{b|h|w|d\} rd, symbol} & Load global \\ +\texttt{s\{b|h|w|d\} rd, symbol, rt} & Store global \\ +\texttt{fl\{w|d\} rd, symbol, rt} & Floating-point load global \\ +\texttt{fs\{w|d\} rd, symbol, rt} & Floating-point store global \\ +\midrule +\texttt{call symbol} & Call far-away subroutine \\ +\texttt{tail symbol} & Tail call far-away subroutine \\ +\bottomrule +\end{tabular} +\end{center} +\caption{Pseudoinstructions Removed in Capability Mode} +\label{table:riscv-capmode-pseudo-remove} +\end{table} + +\begin{sidewaystable} +\begin{center} +\begin{tabular}{lll} +\toprule +Pseudoinstruction & Base Instruction(s) & Meaning \\ +\midrule +\texttt{clgc cd, sym} & + \begin{tabular}{@{}l@{}} + \texttt{1: auipcc cd, \%captab\_pcrel\_hi(sym)} \\ \texttt{\ \ \ \ clc cd, \%pcrel\_lo(1b)(cd)} + \end{tabular} + & Load from capability table \\ +\texttt{cllc cd, sym} & + \begin{tabular}{@{}l@{}} + \texttt{1: auipcc cd, \%pcrel\_hi(sym)} \\ \texttt{\ \ \ \ cincoffset cd, cd, \%pcrel\_lo(1b)} + \end{tabular} + & Load PCC-relative capability \\ +\midrule +\texttt{cjr cs} & \texttt{cjalr cnull, cs} & Jump to capability \\ +\texttt{cjalr cs} & \texttt{cjalr cra, cs} & Jump to capability and link \\ +\texttt{cret} & \texttt{cjalr cnull, cra} & Return to capability \\ +\midrule +\texttt{cspecialr cd, scr} & \texttt{cspecialrw cd, scr, cnull} & Read special capability register \\ +\texttt{cspecialw scr, cs} & \texttt{cspecialrw cnull, scr, cs} & Write special capability register \\ +\bottomrule +\end{tabular} +\end{center} +\caption{Pseudoinstructions Added in Capability Mode} +\label{table:riscv-capmode-pseudo-add} +% TODO: should the hyperrefs for these pseudos link to CJALR instead? +\insnriscvlabel{cjr} +\insnriscvlabel{cret} +\insnriscvlabel{cspecialr} +\insnriscvlabel{cspecialw} +\insnriscvlabel{cllc} +\insnriscvlabel{clgc} +\end{sidewaystable} + + \section{Encoding Summary} + + CHERI-RISC-V general-purpose instructions use the 0x5b major opcode and use the RISC-V R-type or I-type encoding formats. + CHERI-RISC-V uses the funct3 field from bits 14-12 as a top-level opcode, and funct7 as a secondary + opcode for standard 3-register operand instructions. + Two-register operand instructions and single-register operand instructions are a subset + of the 3-register operand encodings. + + \subsection*{Top-level encoding allocation (funct3 field)} + {\scriptsize + \rvcherienctabletop + } + + \subsection*{Two Source \& Dest encoding allocation (funct7 field)} + All three-register-operand (two sources, one destination) CHERI-RISC-V instructions use the RISC-V R-type encoding format, with the same funct field stored in funct7 and a 0 value in funct3. + + \vspace{1em} + + \rvcherirawbitbox{srcsrcdest}{func}{cd}{cs1}{rs2/cs2} + + \vspace{1em} + + {\scriptsize + \rvcherienctablesrcsrcdest + } + + \subsection*{Stores encoding allocation (rd field)} + Store instructions are of the following form: + \vspace{1em} + + \rvcheriheader + \rvcherirawbitbox{expstore}{func}{rs2/cs2}{rs1/cs1} + + \vspace{1em} + + {\scriptsize + \def\rvcheriatomicfootnotemark{$\dagger$} + \rvcherienctableexpstore\\\\ + $\dagger$ The SC.\{B, H, W, D, Q\}.\{DDC, CAP\} instructions are available only when the RISC-V A extension (atomic) is present. + } + + \vspace{1em} + + \subsection*{Loads encoding allocation (rs2 field)} + Load instructions are of the following form: + \vspace{1em} + + \rvcheriheader + \rvcherirawbitbox{expload}{func}{rd/cd}{rs1/cs1} + + \vspace{1em} + + {\scriptsize + \def\rvcheriatomicfootnotemark{$\dagger$} + \def\rvcherildufootnotemark{$\ddagger$} + \rvcherienctableexpload\\\\ + $\dagger$ The LR.\{B, H, W, D, Q\}.\{DDC, CAP\} instructions are available only when the RISC-V A extension (atomic) is present.\\ + $\ddagger$ LDU.\{DDC, CAP\} instructions are available only in RV128. + } + + \vspace{1em} + + \subsection*{Two Source encoding allocation (rd field)} + Two Source instructions are of the following form: + \vspace{1em} + + \rvcheriheader + \rvcherirawbitbox{srcsrc}{func}{rs1/cs1}{rs2/cs2} + + \vspace{1em} + + {\scriptsize + \rvcherienctablesrcsrc + } + + \vspace{1em} + + \subsection*{One Source encoding allocation (rs2 field)} + One Source instructions are of the following form: + + \vspace{1em} + + \rvcheriheader + \rvcherirawbitbox{src}{func}{rs1/cs1} + + \vspace{1em} + + {\scriptsize + \rvcherienctablesrc + } + + \vspace{1em} + + \subsection*{Source \& Dest encoding allocation (rs2 field)} + Source \& Dest instructions are of the following form: + + \vspace{1em} + + \rvcheriheader + \rvcherirawbitbox{srcdest}{func}{rd/cd}{rs1/cs1} + + \vspace{1em} + + {\scriptsize + \rvcherienctablesrcdest + } + + \vspace{1em} + + \subsection*{Dest-Only encoding allocation (rs1 field)} + We do not currently have any one-register-operand instructions, but any + future dest-only instructions will be of the following form: + + \vspace{1em} + + \rvcheriheader + \rvcherirawbitbox{dest}{func}{rd} + + \vspace{1em} + + {\scriptsize + \rvcherienctabledest + } diff --git a/app-isaquick-table-macros.tex b/app-isaquick-table-macros.tex new file mode 100644 index 00000000..61150a05 --- /dev/null +++ b/app-isaquick-table-macros.tex @@ -0,0 +1,85 @@ +\ifcsname @app@isaquick@table@macros@tex\endcsname + \ea\endinput +\fi +\ea\gdef\csname @app@isaquick@table@macros@tex\endcsname{1} + +\makeatletter +\newcount\@cherienctable@col +\newcount\@cherienctable@cols +\newcount\@cherienctable@colbits +\newcount\@cherienctable@row +\newcount\@cherienctable@rows +\newcount\@cherienctable@rowbits +\newcount\@cherienctable@tmp +\def\@cherienctable@addtoformat#1{\ea\global\ea\def\ea\@cherienctable@format\ea{\@cherienctable@format #1}} +\def\@cherienctable@addtobody#1{\ea\global\ea\def\ea\@cherienctable@body\ea{\@cherienctable@body #1}} +% [cols] func2str class count +\newcommand{\@cherienctable}[4][8]{% + \@cherienctable@cols=\numexpr(#1)\relax% + \@cherienctable@rows=\numexpr(#4+\@cherienctable@cols-1)\relax% + \divide\@cherienctable@rows\@cherienctable@cols% + % + \let\@cherienctable@format\@empty% + \let\@cherienctable@body\@empty% + \ifnum\@cherienctable@rows>1% + \@cherienctable@addtoformat{r|}% + \@cherienctable@addtobody{ & }% + \fi% + % + \@cherienctable@colbits=1% + \@cherienctable@tmp=2% + \loop\ifnum\@cherienctable@tmp<\@cherienctable@cols% + \advance\@cherienctable@colbits 1% + \multiply\@cherienctable@tmp 2% + \repeat% + % + \@cherienctable@rowbits=1% + \@cherienctable@tmp=2% + \loop\ifnum\@cherienctable@tmp<\@cherienctable@rows% + \advance\@cherienctable@rowbits 1% + \multiply\@cherienctable@tmp 2% + \repeat% + % + \@cherienctable@col=0% + \loop\ifnum\@cherienctable@col<\@cherienctable@cols% + \@cherienctable@addtoformat{c}% + \ifnum\@cherienctable@col>0% + \@cherienctable@addtobody{ & }% + \fi% + \edef\@cherienctable@cell{\nbinary{\@cherienctable@colbits}{\the\@cherienctable@col}}% + \ea\@cherienctable@addtobody\ea{\@cherienctable@cell}% + \advance\@cherienctable@col 1% + \repeat% + \@cherienctable@addtobody{ \\ \hline}% + % + \@cherienctable@row=0% + \loop\ifnum\@cherienctable@row<\@cherienctable@rows% + \ifnum\@cherienctable@rows>1% + \edef\@cherienctable@cell{\nbinary{\@cherienctable@rowbits}{\the\@cherienctable@row}}% + \ea\@cherienctable@addtobody\ea{\@cherienctable@cell & }% + \fi% + \@cherienctable@col=0% + {% + \loop\ifnum\@cherienctable@col<\@cherienctable@cols% + \ifnum\@cherienctable@col>0% + \@cherienctable@addtobody{ & }% + \fi% + \edef\@cherienctable@cell{\csname #2\endcsname{#3}{\@cherienctable@row*\@cherienctable@cols + \@cherienctable@col}}% + \ifx\@cherienctable@cell\@empty% + \@cherienctable@addtobody{-}% + \else% + \ea\@cherienctable@addtobody\ea{\@cherienctable@cell}% + \fi% + \advance\@cherienctable@col 1% + \repeat% + }% + \@cherienctable@addtobody{ \\}% + \advance\@cherienctable@row 1% + \repeat% + % + \def\@cherienctable@begintabular{\begin{tabular}}% + \ea\@cherienctable@begintabular\ea{\@cherienctable@format}% + \@cherienctable@body% + \end{tabular}% +} +\makeatother diff --git a/app-versions-7-0-alpha1.tex b/app-versions-7-0-alpha1.tex new file mode 100644 index 00000000..521d2008 --- /dev/null +++ b/app-versions-7-0-alpha1.tex @@ -0,0 +1,250 @@ +This release of the \textit{CHERI Instruction-Set Architecture} is an +interim version intended for submission to DARPA/AFRL to meet the requirements +of CTSRD deliverable A001: + +\begin{itemize} +\item The CHERI ISA specification version numbering scheme has changed to +include the target major version in the draft version number. + +\item A significant refactoring of early chapters in the report has taken place: +there is now a more clear distinction between architecture-neutral aspects +of CHERI, and those that are architecture specific. +The CHERI-MIPS ISA is now its own chapter distinct from architecture-neutral +material. +We have aimed to maximize architecture-neutral content -- e.g., capability +semantics and contents, in-memory representation, compression, etc. -- using +the architecture-specific chapters to address only architecture-specific +aspects of the mapping of CHERI into the specific architecture -- e.g., as +relates to register-file integration, exception handling, and the Memory +Management Unit (MMU). +In some areas, content must be split between architecture-neutral and +architecture-specific chapters, such as behavior on reset, handling of the +\cappermASR permission and its role in controlling +architecture-specific behavior, and the integration of CHERI with virtual +memory, where the goals are largely architecture neutral but mechanism is +architecture specific. + +\item There are now dedicated chapters for each of our applications of CHERI +to each of three ISAs: 64-bit MIPS (Chapter~\ref{chap:cheri-mips}), 64-bit +RISC-V (Chapter~\ref{chap:cheri-riscv}), and x86-64 +(Chapter~\ref{chap:cheri-x86-64}). + +\item Our CHERI-RISC-V prototype has been substantially elaborated, and now +includes an experimental encoding in Appendix~\ref{app:isaquick-riscv}. +We have somewhat further elaborated our x86-64 model, including addressing +topics such as new page-table bits for CHERI, including a hardware-managed +capability dirty bit. +We also consider potential implications for RISC-V compressed instructions. + +\item We have completed an opcode renumbering for CHERI-MIPS. +The ``proposed new encoding'' from CHERI ISAv6 has now become the +established encodings; the prior encodings are now documented as +``deprecated encodings''. + +\item Substantial improvements have been made to descriptive text around memory +protection, with the concept of ``pointer protection'' -- i.e., as +implemented via tags -- more clearly differentiated from memory protection. + +\item We now more clearly describe how terms like ``lower bound'' and ``upper +bound'' relate to the base, offset, and length fields. + +\item We now more clearly differentiate language-level capability semantics +from capability use in code generation and the ABI, considering +pure-capability and hybrid C as distinct from pure-capability and hybrid code +generation. +We explain that different language-level integer interpretations of +capabilities are supportable by the architecture, depending on compiler +code-generation choices. + +\item Potential software policies for revocation, garbage collection, and +capability flow control based on CHERI primitives are described in greater +detail. + +\item Monotonicity is more clearly described, as are the explicit +opportunities for non-monotonicity around exception handling and +\insnnoref{CCall} Selector 1. +Handling of disallowed requests for non-monotonicity or bypass of guarded +manipulation by software is more explicitly discussed, including the +opportunities for both exception throwing and tag stripping to maintain +CHERI's invariants. + +\item Further notes have been added regarding the in-memory representation of +capabilities, including the storage of NULL capabilities, virtual addresses +for non-NULL capabilities, and how to store integer values in untagged +capability registers. +These values now appear in the bottom 64 bits of the in-memory +representation. +Topics such as endianness are also considered. + +\item NULL capabilities are now defined as having a base of 0x0, the maximum +length supported in a particular representation ($2^{64}$ for 128-bit +capabilities, and $2^{64} - 1$ for 256-bit capabilities), and no granted +permissions. +NULL capabilities continue to have an all zeros in-memory representation. +This allows integers to be stored in the offset of an untagged capability +without concern that they may hold values that are unrepresentable with +respect to capability bounds. + +\item New instructions \insnref{CReadHwr} and \insnref{CWriteHwr} have +been added. +These have allowed us to migrate special capability registers (SCRs) out of +the general-purpose capability register file, including \DDC{}, the new user +TLS register (\CULR{}), the new privileged TLS register (\CPLR{}), \KRC{}, +\KQC{}, \KCC{}, \KDC{}, and \EPCC{}. +Access to privileged special registers continues to be authorized by the +\cappermASR permission on \PCC{}. + +\item With this migration, \creg{0} is now available to use as a NULL +capability register, which is more consistent with the baseline MIPS ISA in +which \reg{0} is the zero register. +The only exception to this is in capability-relative load and store +instructions, and the \insnref{CTestSubset} instruction, in +which an operand of \creg{0} specifies that \DDC{} should be used. + +\item Various instruction pseudo-ops to access special registers, such as +\insnmipsref{CGetDefault}, now expand to special capability register access +instructions instead of capability move instructions. + +\item With consideration of merged rather than split integer and capability +register files for RISC-V and x86-64, and a separation between +general-purpose capability registers and special capability registers (SCRs) on 64-bit MIPS, we +avoid describing the integer register file as the ``general-purpose register +file''. +We describe a number of tradeoffs around ISA design relating to using a +split vs. merged register file; avoiding the use of specific capability +registers as special registers assists in supporting both register-file +approaches. + +\item The CPU reset state of various capability registers is now more clearly +defined. +Most capability registers are initialized to NULL on reset, with the +exception of \DDC{}, \PCC{}, \KCC{}, and \EPCC{}. +These defaults authorize initial access to memory for the boot process, and +are designed to allow CHERI-unaware code to operate oblivious to the +capability-system feature set. + +\item We more clearly describe design choices around failure-mode choices, +including throwing exceptions and clearing tag bits. +Here, concerns in conclude stylistic consistency with the host architecture, +potential use cases, and interactions with the compiler and operating +system. + +\item In general, we now refer to software-defined permissions rather than +user-defined permissions, as these permissions without an architectural +interpretation may be used in any ring. + +\item Permission numbering has been rationalized so that 128-bit and 256-bit +microarchitectural permission numbers consistently start at 15. + +\item The existing permission \cappermSeal, which authorized sealing and +explicit unsealing of sealed capabilities, has now been broken out into two +separate permissions: \cappermSeal, which authorizes sealing, and +\cappermUnseal, which authorizes explicit unsealing. +This will allow privilege to be reduced where unsealing is desirable (e.g., +within object implementations, or in C++ vtable use) by not requiring that +permission to seal for the object type is also granted. + +\item The ISA quick reference has been updated to reflect new instructions, as +well as to more correctly reflect endianness. + +\item We have added a reference to our recently released technical report, \textit{Capability +Hardware Enhanced RISC Instructions (CHERI): Notes on the Meltdown and +Spectre Attacks}~\cite{UCAM-CL-TR-916}, which considers the potential +interactions between CHERI and the recently announced Spectre and Meltdown +microarchitectural side-channel attacks. +CHERI offers substantial potential to assist in mitigating aspects of these +attacks, as long as the microarchitecture performs required capability +checks before performing any speculative memory accesses. + +\item We have added two new instructions, Get the architectural Compartment ID +(\insnref{CGetCID}) and Set the architectural Compartment ID +(\insnref{CSetCID}), which allow information on compartments to +be passed to via architecture to microarchitecture in order to support +mitigation of side-channel attacks. +This could be used to tag branch-predictor entries to control the +compartments in which they can be used, for example. +A new Permit\_Set\_CID permission allows capabilities to delegate use of +ranges of CIDs. + +\item Bugs have been fixed in the definitions of various capability-relative +load and store instructions, in which permission checks involving the +Permit\_Load, Permit\_Load\_Cap, Permit\_Store, and Permit\_Store\_Cap +permissions were not properly updated from our shift from an untagged +capability register file to a tagged register file. +All loads now require Permit\_Load. +If Permit\_Load\_Cap is also present, then tags will not be stripped when +loading into a capability register. +All stores now require Permit\_Store. +If Permit\_Store\_Cap is also present, then storing a tagged capability will +not generate an exception. + +\item New Capability Set Bounds From Immediate +(\insnref{CSetBoundsImm}) and Capability Increment Offset From Immediate +(\insnref{CIncOffsetImm}) instructions have been added. +These instructions optimize global-variable setup and stack allocations by +reducing the number of instructions and registers required to adjust pointer +values and set bounds. + +\item New Capability Branch if Not NULL (\insnref{CBNZ}) and +Capability Branch if NULL (\insnref{CBEZ}) instructions have +been added, which optimize pointer comparisons to NULL. + +\item A new Capability to Address (\insnref{CGetAddr}) +instruction allows the direct retrieval of a capability's virtual address, +rather than requiring the base and offset to be separately retrieved and added +together. +This facilitates efficient implementation of a CHERI C variant in which all +casts of capabilities to integers have virtual-address rather than offset +interpretation. +A capability's virtual address is now more directly defined when we specify +capability fields. + +\item We more clearly describe \insnnoref{CCall} Selector 1 as +``exception-free domain transition'' rather than ``userspace domain +transition'', as it is also intended to be used in more privileged rings. + +\item We have shifted to more consistently throwing an exception at jump +instructions (e.g., \insnref{CJR}) that go out of bounds, +rather than throwing the exception when fetching the first instruction at +the target address. +This provides more debugging information when using compressed +capabilities, as otherwise \EPCC{} might have unrepresentable bounds in the +event that the jump target is outside of the representable region. + +\item The exception vectors use during failures of Selector 0 and Selector 1 +\insnnoref{CCall} have been clarified. +The general-purpose exception vector is used for all failure modes with +\insnnoref{CCall} Selector 1. + +\item We have added a new experimental instruction, Test that Capability is a Subset of Another +(\insnref{CTestSubset}). +This instruction is intended to be used by garbage collectors that need to +rapidly test whether a capability points into the range of another +capability. + +\item A new experimental 64-bit capability format for 32-bit virtual addresses +has been added. + +\item A description of an experimental {\it linear capability} model has been +added (Section~\ref{section:linear-capabilities}). +This model introduces the concept that a capability may be linear -- i.e., +that it can only be moved rather copied in memory-to-register, +register-to-register, and register-to-memory operations. +This introduces two new instructions, Linear Load Capability Register +(\insnnoref{LLCR}) and Linear Store Capability Register +(\insnnoref{LSCR}). +This functionality has not yet been fully specified. + +\item An experimental appendix considers possible implementations of {\it +indirect capabilities}, in which a capability value points at an actual +capability to utilize, allowing table-based capability lookups +(Section~\ref{section:indirect-capabilities}). + +\item An experimental appendix considering potential forms of compression for +capability permissions has been added (Section~\ref{app:exp:compressperm}). + +\item We have added a reference to our ICCD 2017 paper, \textit{Efficient +Tagged Memory}, which describes how to efficiently implement tagged memory in +memory subsystems not supporting inline tags directly in + DRAM~\cite{joannou2017:tagged-memory}. +\end{itemize} diff --git a/app-versions-7-0-alpha2.tex b/app-versions-7-0-alpha2.tex new file mode 100644 index 00000000..1b4ad927 --- /dev/null +++ b/app-versions-7-0-alpha2.tex @@ -0,0 +1,88 @@ +This version of the \textit{CHERI Instruction-Set Architecture} is an interim +version distributed for review by DARPA and our collaborators: + +\begin{itemize} +\item We have removed the range check from the \insnref{CToPtr} + specification, as this has proven microarchitecturally challenging. + We anticipate that current consumers requiring this range check can use the + new \insnref{CTestSubset} instruction alongside \insnref{CToPtr}. + +\item Use of a branch-delay slot with \insnnoref{CCall} Selector + 1 has been removed. + +\item With the addition of \insnref{CReadHwr} and \insnref{CWriteHwr} + and shifting of special capability registers out of the + general-purpose capability register file, we have now removed the check for + the \cappermASR permission for all registers in the + general-purpose capability register file. + +\item A new \insnref{CCheckTag} instruction is added, which + throws an exception if the tag is not set on the operand capability. + This instruction could be used by a compiler to shift capability-related + exception behavior from invalid dereference to calculation of an invalid + capability via a non-exception-throwing manipulation. + +\item We have added a new \insnref{CLCBI} instruction that + allows capability-relative loads of capabilities to be performed using a + substantially larger immediate (but without a general-purpose + integer-register operand). + This substantially accelerates performance in the presence of CHERI-aware + linkage by avoiding multi-instruction sequences to load capabilities for + global variables. + +\item We have added new discussion relating to microarchitectural side + channels such as Spectre and Meltdown + (Section~\ref{section:microarchitectural-sidechannels}). + +\item We have added a reference to our ASPLOS 2019 paper, \textit{CheriABI: + Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the + POSIX C Run-time Environment}, which describes how to adapt a full MMU-based + OS design to support ubiquitous use of capabilities to implement C and C++ + pointers in userspace~\cite{davis2019:cheriabi}. + +\item We have added a reference to our POPL 2019 paper, \textit{ISA Semantics + for ARMv8-A, RISC-V, and CHERI-MIPS}, which describes a formal modeling + approach for instruction-set architectures, as well as a formal model of the + CHERI-MIPS ISA~\cite{sail-popl2019}. + +\item We have added a reference to our POPL 2019 paper, \textit{Exploring C + Semantics and Pointer Provenance}, which describes a formal model for C + pointer provenance, and is evaluated in part using pure-capability CHERI + code~\cite{cerberus-popl2019}. + +\item We have added a description of an experimental compact capability + coloring scheme, a possible candidate to replace our Local-Global capability + flow-control model (Section~\ref{sec:compactcolors}). + In the proposed scheme, a series of orthogonal ``colors'' can be set or + cleared on capabilities, authorized by a color space implemented in a + style similar to the sealed-capability object-type space using a single + permission. + For a single color implementing the Local-Global model, two bits are still + used. + However, for further colors, only a single bit is used. + This could make available further colors to use for kernel-user separation, + inter-process isolation, and so on. + +\item An experimental Permit\_Recursive\_Mutable\_Load permission is + described, which, if not present, causes further capabilities loaded via + that capability to be loaded without store permissions + (see Section~\ref{app:exp:recmutload}). + +\item We have added a new experimental \insnref{CLoadTags} + instruction that allows tags to be loaded for a cache line without pulling + data into the cache. + +\item A new experimental \textit{sealed entry capability} feature is + described, which permits entry via jump but otherwise do not allow + dereferencing (later editions considered these no longer experimental, and + so they are described in \cref{sec:arch-sentry}). + These are similar to enter capabilities from the + M-Machine~\cite{carter:mmachine94}, and could provide utility in providing + further constraints on capability use for the purposes of memory protection + -- e.g., in the implementation of C++ v-tables. + +\item A new experimental \textit{memory type token} feature is described, + which provides an alternative mechanism to object types within pairs of + sealed capabilities (Section~\ref{app:exp:typetoken}). + +\end{itemize} diff --git a/app-versions-7-0-alpha3.tex b/app-versions-7-0-alpha3.tex new file mode 100644 index 00000000..874b8d4e --- /dev/null +++ b/app-versions-7-0-alpha3.tex @@ -0,0 +1,72 @@ +This version of the \textit{CHERI Instruction-Set Architecture} is an interim +version distributed for review by DARPA and our collaborators: + +\begin{itemize} + +\item The CHERI Concentrate capability compression format is now documented, + with a more detailed rationale section than the prior CHERI-128 section. + +\item The \insnref{CLCBI} (Capability Load Capability with Big Immediate) + instruction, which accelerates position-independent access to global + variables, is no longer considered experimental. + +\item The architecture-neutral description of tagged memory has been + clarified. + +\item The maximum supported lengths for both compressed and uncompressed + capabilities has been updated: $2^{64}$ for 128-bit +capabilities, and + $2^{64} - 1$ for 256-bit capabilities. + +\item It is clarified that \insnref{CLoadTags} instruction must provide + cache coherency consistent with other load instructions. + We recommend ``non-temporal'' behavior, in which unnecessary cache-line + fills are avoided to limit cache pollution during revocation. + +\item We now define the object type for unsealed capabilities, returned by + the \insnref{CGetType} instruction, as $2^{64}-1$ rather than $0$. + +\item An experimental section has been added on how CHERI capabilities might + compose with memory-versioning schemes such as Sparc ADI and Arm MTE + (see Section~\ref{app:exp:versioning}). + +\item Pseudocode throughout the CHERI ISA specification is now generated from + our Sail formal model of the CHERI-MIPS ISA~\cite{sail-popl2019}. + +\item The \hyperref[glossary]{Glossary} has been updated for CHERI ISAv7 + changes including CHERI-RISC-V, split vs. merged register files, + capabilities for physical addresses, and special capability registers. + +\item Capability exception codes are now shared across architectures. + +\item CHERI-RISC-V now includes capability-relative floating-point load and + store instructions. + We have clarified that existing RISC-V floating-point load and store + instructions are constrained by \DDC{}. + +\item CHERI-RISC-V now throws exceptions, rather than clearing tags, when + non-mono\-tonic register-to-register capability operations are attempted. + +\item While a specific encoding-mode transition mechanism is not yet specified + for CHERI-RISC-V, candidate schemes are described and compared in greater + detail. + +\item CHERI-RISC-V's ``capability encoding mode'' now has different impacts + for uncompressed instructions vs. compressed instructions: In the compressed + ISA, jump instructions also become capability relative. + +\item CHERI-RISC-V page-table entries now contain a ``capability dirty bit'' + to assist with tracking the propagation of capabilities. + +\item Throwing an exception on an out-of-bounds capability-relative jump + rather than on the target fetch is now more clearly explained: This improves + debuggability by maintaining precise information about context state on + jump, whereas after the jump, bounds may not be representable due to + capability compression. + When an inappropriate \EPCC{} is installed, the exception will still be + thrown on instruction fetch. + +\item A new \ErrorEPCC{} special register has been defined, to assist with + exceptions thrown within exception handlers; its behavior is modeled on the + existing MIPS \ErrorEPC{} special register. + +\end{itemize} diff --git a/app-versions-7-0-alpha4.tex b/app-versions-7-0-alpha4.tex new file mode 100644 index 00000000..76b8e2a8 --- /dev/null +++ b/app-versions-7-0-alpha4.tex @@ -0,0 +1,105 @@ +This version of the \textit{CHERI Instruction-Set Architecture} is an interim +version distributed for review by DARPA and our collaborators: + +\begin{itemize} +\item We have added new instructions \insnref{CSetAddr} (Set capability + address to value from register), \insnref{CAndAddr} (Mask address of + capability -- experimental), and \insnref{CGetAndAddr} (Move capability + address to an integer register, with mask -- experimental), which optimize + common virtual-address-related operations in language runtimes such as + WebKit's Javascript engine. + These instructions cater better to a language mapping from C's + \ccode{intptr_t} type to the virtual address, rather than offset, of a + capability, which has been our focus previously. + These complement the previously added \insnref{CGetAddr} that allows + easier compiler access to a capability's virtual address. + +\item We have added two new experimental instructions, \insnref{CRAM} + (Retrieve Mask to Align Capabilities to Precisely Representable Address) and + \insnref{CRRL} (Round to Next Precisely Representable Value), which + allow software to retrieve alignment information for the base and length for + a proposed set of bounds. + +\item \insnref{CMove}, which was previously an assembler pseudo-operation + for \insnref{CIncOffset}, is now a stand-alone instruction. + This avoids the need to special case sealed capabilities when + \insnref{CIncOffset} is used solely to move, not to modify, a + capability. + +\item The names of the instructions \insnnoref{CSetBoundsImmediate} and + \insnnoref{CIncOffsetImmediate} have been shortened to + \insnref{CSetBoundsImm} and \insnref{CIncOffsetImm}. + +\item The instructions \insnnoref{CCheckType} and \insnnoref{CCheckPerm} + have been deprecated, as they have not proven to be particularly useful in + implementing multi-protection-domain systems. + +\item We have added a new pseudo-operation, \insnnoref{CAssertInBounds}, + described in \cref{\insnmipslabelname{cassertinbounds}}, allows an exception + to be thrown if the address of a capability is not within bounds. + +\item The instruction \insnref{CCheckTag} has now been assigned an opcode. + +\item We have revised the encodings of many instructions in our draft + CHERI-RISC-V specification in Appendix~\ref{app:isaquick-riscv}. + +\item We more clearly specify that when a special register write occurs to + \EPC{}, the result is similar to \insnref{CSetOffset} but with the tag + bit stripped, in the event of a failure, rather than an exception being + thrown. + +\item We have added a reference to our TaPP 2018 paper, \textit{Pointer + Provenance in a Capability Architecture}, which describes how architectural + traces of pointer behavior, visible through the CHERI instruction set, can + be analyzed to understand software and structure. + +\item We have added a reference to our ICCD 2018 paper, \textit{CheriRTOS: + A Capability Model for Embedded Devices}, which describes an embedded + variant of CHERI using 64-bit capabilities for 32-bit addresses, and how + embedded real-time operating systems might utilize CHERI features. + +\item We have revised our description of conventions for capability values, + including when used as pointers, to hold integers, and for NULL value, to + more clearly describe their use. + We more clearly describe the requirements for the in-memory + representation of capabilities, such as a zeroed NULL capability so that + BSS behaves as desired. + We provide more clear architecture-neutral explanations of pointer + dereferencing, capability + permissions and their composition, the namespaces protected by capability + permissions, exception handling, exception priorities, virtual memory, and + system reset. + These definitions appear in Chapter~\ref{chap:architecture}. + Chapter~\ref{chap:cheri-mips}, which describes CHERI-MIPS, has been + shortened as a variety of content has been made architectural neutral. + +\item More detailed rationale is provided for our composition of CHERI with + the MIPS exception-handling model. + +\item We are more careful to use the term ``pointer'' to refer to the + C-language type, verses integer or capability values that maybe used by the + compiler to implement pointers. + +\item With the advent of ISA variations utilizing a merged register file, we + are more careful to differentiate integer registers from general-purpose + registers, as general-purpose registers may also hold capabilities. + +\item We more clearly define the terms ``upper bound'' and ``lower bound''. + +\item We now more clearly describe the effects of our \textit{principle of + intentionality} on capa\-bility-aware instruction design in + Section~\ref{sec:capability-aware-instructions}. + +\item We better describe the rationale for tagged capabilities in registers + and memory, in contrast to cryptographic and probabilistic protections, in + Section~\ref{sec:probablistic_capability_protection}. + +\item We have made a number of improvements to the CHERI-x86-64 sketch, + described in Chapter~\ref{chap:cheri-x86-64}, to improve realism around trap + handling and instruction design. + +\item We have rewritten our description of the interaction between CHERI and + Direct Memory Access (DMA) in Section~\ref{sec:dma}. to more clearly + describe tag-stripping and capability-aware DMA options. + +\end{itemize} diff --git a/app-versions-7-0.tex b/app-versions-7-0.tex new file mode 100644 index 00000000..bb18164a --- /dev/null +++ b/app-versions-7-0.tex @@ -0,0 +1,56 @@ +This version of the \textit{CHERI Instruction-Set Architecture} is a full +release of the Version 7 specification: + +\begin{itemize} +\item We have now deprecated the CHERI-128 capability compression format, in + favor of CHERI Concentrate. + +\item The RISC-V \insnnoref{AUIPC} instruction now returns a + \PCC{}-relative capability in the capability encoding mode. + +\item Capabilities now contain a \cflags{} field (\cref{sec:model-flags}), + which will hold state that + can be changed without affecting privilege. + Corresponding experimental \insnref{CGetFlags} and + \insnref{CSetFlags} instructions have been added. + +\item The capability encoding-mode bit in CHERI-RISC-V is specified as a bit + in the \cflags{} field of a capability. + The current mode is defined as the flag bit in the currently installed + \PCC{}. + Design considerations and other potential options are described in + Chapter~\ref{chap:rationale}. + +\item We now more explicitly describe the reset states of special- and + general-purpose capability registers for CHERI-MIPS and CHERI-RISC-V. + +\item Compressed capabilities now contain a dedicated \cotype{} field that + always holds an object type (see + \cref{sec:model-object-types,section:object-type}), rather than stealing + bounds bits for object type when sealing. Now, any representable capability + may be sealed. Several object type values are reserved for architectural + experimentation (see \cref{tab:archotypes}). + +\item More detail is provided regarding the integration of CHERI Concentrate + with special registers, its alignment requirements, and so on. + +\item Initial discussion of a disjoint capability tree for physical + addresses and hardware facilities using these has been added to + the experimental appendix, in \cref{app:exp:physcap}. + +\item Initial discussion of a hybrid 64/128-bit capability design has been + added to the experimental appendix, in \cref{sec:windowedshortcaps}. + +\item We have added formal Sail instruction semantics for CHERI-RISC-V; this + is currently in Appendix~\ref{app:isaquick-riscv}. + +\item We have added a reference to our IEEE TC 2019 paper, \textit{CHERI + Concentrate: Practical Compressed Capabilities}, which describes our current + approach to capability compression. + +\item We have added a reference to Alexandre Joannou's PhD dissertation, + \textit{High-perform\-ance memory safety: optimizing the CHERI capability + machine}, which describes approaches to improving the efficiency of + capability compression and tagged memory. + +\end{itemize} diff --git a/app-versions-8-0.tex b/app-versions-8-0.tex new file mode 100644 index 00000000..42b21ef1 --- /dev/null +++ b/app-versions-8-0.tex @@ -0,0 +1,260 @@ +This version of the \textit{CHERI Instruction-Set Architecture} is a full +release of the Version 8 specification: + +\begin{itemize} +\item We have performed modest updates to discuss Arm's Morello processor, + System-on-Chip (SoC), and board. + The authoritative reference to Morello is Arm's Morello + specification~\cite{arm-morello}. + +\item We have added a new chapter, Chapter~\ref{chap:microarchitecture}, + describing the impact on CHERI on practical microarchitecture at a high + level. + It considers topics such as the impact of capabilities on the pipeline and + register file, efficient implementation of bounds compression and + decompression, fast bounds checking, tagged memory, and the potential + interaction with speculative execution. + This includes insights gained during the building of Arm's Morello + processor and SoC. + +\item Shift away from the idea that the fully precise 256-bit capabilities + are the essential model for CHERI. + Instead, describe capabilities as an architectural type made up of a set + of architectural fields, which may be constrained in terms of precision, and + that have an in-memory representation. + The microarchitecture may hold capabilities in another format internally + (e.g., when loaded in registers). + +\item The CHERI Concentrate description has been improved, including adding + information about the Fast Representability Check. + A number of constants have been updated. + +\item In several chapters, more care is taken when using the words + ``capability,'' ``pointer,'' and ``address,'' which are not interchangeable. + +\item Throughout, be more clear that CHERI applies to 32-bit architectures, + not just 64-bit architectures. + In Chapter~\ref{chap:architecture}, introduce \xlen{} and \clen{} + terminology previously only used for CHERI-RISC-V, to better abstract away + from specific address lengths. + +\item We are now more clear that capabilities may describe physical as well as + virtual addresses, and that virtual addressing may be implemented either + using software-managed TLBs (as on MIPS) or via architectural page tables + (as on RISC-V and ARMv8-A). + +\item The \insnnoref{CCall} instruction has been replaced with + \insnref{CInvoke}, which does not have a selector mechanism and supports + only exception-free domain transition. + The prior exception-based mechanism was introduced as scaffolding used + during domain-transition research, and the exception-free mechanism is our + preferred approach. + We have removed capability exception cause codes previously used + for that purpose, and will likely deprecate \insnref{CSetCause}, which was + used only for exception-based domain transition. + +\item The deprecated \insnnoref{CCheckPerm} and \insnnoref{CCheckType} + instructions have been removed as they were intended to be used with the + exception-based \insnnoref{CCall} mechanism. + +\item We have removed the experimental 64-bit capability format based on our + older CHERI-128 compression model. + We now document a 64-bit capability format as part of CHERI Concentrate in + Section~\ref{section:architectural-capabilities}. + +\item We now advocate for a policy of specifying a minimum capability bounds + precision, even with \insnref{CRRL} and \insnref{CRAM} instructions; see + Section~\ref{sec:the-value-of-architectural-minimum-precision}. + +\item We now more fully explore, and explain, exception throwing around + capability load and store permissions on capabilities and on page-table / + TLB entries. + MMU-originated exceptions are now distinct from CHERI exceptions. + Whereas a capability load through a capability without \cappermLC will always strip + the tag, a capability load via a page without load capability permission + will either strip the tag or throw an exception. + Similarly, a store via a page without permission to store a capability will + throw an exception if the tag bit is set on the capability being stored. + +\item We now discuss the use of per-page capability load barriers to + enable efficient capability revocation and garbage collection in + Section~\ref{section:capability-load-barriers}. Load + barriers use additional MMU permissions to selectively trap on + capability loads. + +\item \insnref{CPtrCmp} has been changed to compare only the addresses of + the two capabilities, and no longer consider the tag bit, for non-exact + comparisons. + The previous behavior could result in surprising run-time failures of C/C++ + programs. + +\item Sentry capabilities are no longer considered experimental. + +\item The instruction \insnref{CSealEntry} has been added to the ISA quick + references, from which it was missing. + +\item We now more completely elaborate how sentry capabilities interact with + exception handling, including automatic unsealing of sentries when installed + in exception program counters, not just when they are jumped to. + +\item Two new instructions (\insnmipsref{CGetPCCIncOffset} and + \insnmipsref{CGetPCCSetAddr}) have been added to improve code density when + generating code to create \PCC{}-derived capabilities for code or data + access. + This is of particular use when utilizing sentry capabilities. + +\item The \insnref{CRRL} and \insnref{CRAM} instructions, which assist with + capability bounds alignment and padding, are no longer considered + experimental. + +\item The \insnref{CLoadTags} instruction is no longer considered + experimental, and has now also been defined for CHERI-RISC-V. + +\item We have removed a note on \insnmipsref{CSeal} + regarding representable unsealed capabilities being unrepresentable as + sealed capabilities: all representable capabilities can now be sealed. + +\item We have a removed a note on \insnmipsref{CIncOffset} regarding a special + case in which offset of 0 is permitted to operate on sealed capabilities, + allowing \insnmipsref{CIncOffset} to be used to implement + \insnmipsref{CMove} as a pseudo-instruction. + This is no longer required, as \insnmipsref{CMove} is now its own + instruction to avoid this special casing. + +\item \insnmipsref{CIncOffset} is no longer specified to clear the base and + length if the bounds become unrepresentable, as we guarantee that the cursor + will hold the arithmetic result rather than the offset. + +\item \insnref{CSetFlags} no longer incorrectly notes that an exception + is thrown if the argument is untagged. + +\item We have added a new chapter, Chapter~\ref{chap:isaref-riscv}, listing the + semantics and encodings of CHERI-RISC-V instructions. + +\item Capability flags, and their associated instructions, + \insnref{CGetFlags} and \insnref{CSetFlags}, are no longer considered + experimental. + On CHERI-RISC-V, a capability flag is used to control what instruction + endcoding mode is active. + For details, see + \cref{sec:model-flags,sec:arch-flags,sec:cheri-riscv-encmodes}. + +\item Certain CHERI-RISC-V SCRs are now defined to exist only when their + corresponding extensions (e.g., the N extension) is present. + +\item In CHERI-RISC-V, when a special capability register is written using + \insnriscvref{CSpecialRW}, and some bits in the register are defined as WARL + (i.e., may be modified during the write), the tag bit will be cleared if the + capability value is sealed. + +\item A new Unaligned Base CHERI exception code has been defined, allowing + CHERI-RISC-V to throw an exception if the installed \PCC{} value has an + unaligned base. + +\item CHERI-RISC-V encodings are now defined for \insnriscvref{CRRL} and + \insnriscvref{CRAM}, and encoding space is reserved for a future implementation of + \insnriscvref{CClear} when using a split register file. + +\item CHERI-RISC-V encodings have been added for the + \insnriscvref{CSetEqualExact}, \insnriscvref{CLoadTags}, and + \insnriscvref{CClearTags} instructions. + +\item The CHERI-RISC-V exception cause code has changed from 0x20 to 0x1c + due to a collision with encoding space reserved for future use. + +\item We now define a set of CHERI-RISC-V atomic instructions corresponding to + the equivalent base RISC-V atomic instructions. + +\item We now document which RISC-V CSRs and FCSRs are white listed to not + require \cappermASR, such as the cycle counter. + +\item Capability exception cause codes are now properly architecture neutral, + but the mechanism for obtaining them is more accurately architecture + specific. + +\item CHERI-RISC-V now reports capability-related exception information via + the existing RISC-V Trap Value CSRs, \xtval{}, rather than through a new + capability cause register (a design inherited from CHERI-MIPS that is less + consistent with the baseline RISC-V design). + +\item We added two new exception codes for CHERI-related MMU faults to + CHERI-RISC-V. For these exceptions, \xtval{} holds the address of + the faulting memory reference as with existing MMU faults on RISC-V. + +\item We added additional PTE bits to CHERI-RISC-V to support + capability revocation. \texttt{CD} provides a capability dirty bit + to track pages holding capabilities. \texttt{CRM} and \texttt{CRG} + enable per-page capability load barriers. + +\item We document the CHERI-RISC-V \insnriscvref{CRET}, \insnriscvref{CJR}, and + \insnriscvref{CJALR} assembly aliases. + +\item We have added a CHERI-RISC-V assembly programming section to the + CHERI-RISC-V ISA quick reference. + +\item There have been numerous updates to our CHERI-x86-64 architectural + sketch. The page table permission bits have been adjusted to avoid + conflicting with the Protection Keys extension. Violations of the + CHERI page table permissions now raise a page fault rather than a + CHERI fault. The read capability permission now faults if violated + rather than stripping tags. We have removed an ambiguous suggestion + for handling RIP-relative addressing. + +\item The interaction of CHERI with existing memory versioning schemes + (e.g., Arm MTE) in \cref{app:exp:versioning} is now more fully articulated + and includes support for integer-pointer versioning instructions as well as + a new atomic instruction to manipulate version values in memory. + +\item A new experimental instruction, \insnref{CLCNT}, has been proposed to + perform a non-temporal (streaming) load of a capability via a capability. + This instruction may prove useful when scanning memory for capabilities in + order to implement revocation. + We have not yet validated this approach through a full-stack implementation. + +\item A new experimental instruction, \insnref{CClearTags}, has been proposed + to perform fast zeroing of multiple tags in memory, and will not allocate + cache lines if data is not already present in a cache. + This instruction may prove useful when rapidly clearing capabilities for + revocation purposes, in the absence of data confidentiality requirements. + We have not yet validated this approach through a full-stack implementation. + +\item A new experimental protection-domain transition mechanism, + \textit{sealed indirect enter capabilities}, has been proposed to allow + a sealed entry capability to carry not just a pointer to domain-specific + code, but also to domain-specific data, by adding an additional level of + indirection. + A new instruction, \insnnoref{CInvokeInd}, would be used to invoke a + sealed indirect enter capability. + We have not yet validated this approach through a full-stack implementation. + This is described in Section~\ref{app:exp:indsentry}. + +\item A new \emph{ephemeral capability} type is proposed. + Ephemeral capabilities can be held in registers but not stored to memory, + and we consider the implications for fast cross-domain calls, and an + explicitly maintained delegation tree to provide prompt revocation of + delegation sub-trees. + We have not yet validated this approach through a full-stack implementation. + This is described in Section~\ref{app:exp:hierarchal-evocation}. + +\item A new \emph{anti-tamper seal} mechanism is proposed, to allow + validation that a delegated capability that has been returned has not been + modified (other than its address) while in use. + The suggested use case is around memory allocators, to ensure that a pointer + passed to free is consistent with the pointer originally allocated. + We have not yet validated this approach through a full-stack implementation. + This is described in Section~\ref{sec:anti-tamper}. + +\item We now describe potential capability-related prefetch instructions in + Section~\ref{sec:caching-and-explicit-prefetch}, with specific + consideration of side-channel attacks. + We also explicitly specify \DDC{} bounds checking on the MIPS + \insnnoref{PREF} prefetch instruction in + Section~\ref{sec:mips-prefetch}. + +\item We now reference our papers \textit{CHERIvoke: Characterising Pointer + Revocation using CHERI Capabilities for Temporal Memory Safety} (IEEE MICRO + 2019), \textit{Rigorous engineering for hardware security: Formal modelling + and proof in the CHERI design and implementation process} (IEEE SSP 2020), + and \textit{Cornucopia: Temporal Safety for CHERI Heaps} (IEEE SSP 2020). + +\end{itemize} diff --git a/app-versions.tex b/app-versions.tex new file mode 100644 index 00000000..17f89bba --- /dev/null +++ b/app-versions.tex @@ -0,0 +1,1059 @@ +\chapter{CHERI ISA Version History} +\label{app:versions} + +This appendix contains both a high-level summary of prior CHERI ISA versions +(Section~\ref{sec:detailed-cheri-isa-version-change-history}), +and also a detailed change log for each version +(Section~\ref{sec:detailed-cheri-isa-version-change-history}). +This report was previously made available as the {\em CHERI Architecture +Document}, but is now the {\em CHERI Instruction-Set Architecture}. + +\section{CHERI ISA Specification Version Summary} +\label{sec:cheri-isa-specification-version-summary} + +A short summary of key ISA versions is presented here: + +\begin{description} +\item[CHERI ISAv1 - 1.0--1.4 - 2010--2012] + Early versions of the CHERI ISA explored the integration of capability + registers and tagged memory -- first in isolation from, and later in + composition with, MMU-based virtual memory. + CHERI-MIPS instructions were targeted only by an extended assembler, with an + initial microkernel (``Deimos'') able to create compartments on bare metal, + isolating small programs from one another. + Key early design choices included: + \begin{itemize} + \item to compose with the virtual-memory mechanism by being an + in-address-space protection feature, supporting complete MMU-based OSes, + \item to use capabilities to implement code and data pointers for C-language + TCBs, providing reference-oriented, fine-grained memory protection and + control-flow integrity, + \item to impose capability-oriented monotonic non-increase on pointers to + prevent privilege escalation, + \item to target capabilities with the compiler using explicit capability + instructions (including load, store, and jumping/branching), + \item to derive bounds on capabilities from existing code and data-structure + properties, OS policy, and the heap and stack allocators, + \item to have both in-register and in-memory capability storage, + \item to use a separate capability register file (to be consistent with the + MIPS coprocessor extension model), + \item to employ tagged memory to preserve capability integrity and + provenance outside of capability registers, + \item to enforce monotonicity through constrained manipulation instructions, + \item to provide software-defined (sealed) capabilities including a + ``sealed'' bit, user-defined permissions, and object types, + \item to support legacy integer pointers via a Default Data Capability + (\DDC{}), + \item to extend the program counter (\PC{}) to be the Program-Counter + Capability (\PCC{}), + \item to support not just fine-grained memory protection, but also + higher-level protection models such as software compartmentalization or + language-based encapsulation. + \end{itemize} + +\item[CHERI ISAv2 - 1.5 - August 2012] + This version of the CHERI ISA developed a number of aspects of capabilities + to better support C-language semantics, such as introducing tags on + capability registers to support capability-oblivious memory copying, as well + as improvements to support MMU-based operating systems. + +\item[UCAM-CL-TR-850 - 1.9 - June 2014] + This technical report accompanied publication of our ISCA 2014 paper on + CHERI memory protection. + Changes from CHERI ISAv2 were significant, supporting a complete + conventional OS (CheriBSD) and compiler suite (CHERI Clang/LLVM), a defined + \insnnoref{CCall}/\insnnoref{CReturn} mechanism + for software-defined + object capabilities, capability-based load-linked/store-conditional + instructions to support multi-threaded software, exception-handling + improvements such as a CP2 cause register, new instructions + \insnref{CToPtr} and \insnref{CFromPtr} to improve compiler + efficiency for hybrid compilation, and changes relating to object + capabilities, such as user-defined permission bits and instructions to check + permissions/types. + +\item[CHERI ISAv3 - 1.10 - September 2014] + CHERI ISAv3 further converges C-language pointers and capabilities, improves + exception-handling behavior, and continues to mature support for + object capabilities. + A key change is shifting from C-language pointers being represented by the + base of a capability to having an independent ``offset'' (implemented as a + ``cursor'') so that monotonicity is imposed only on bounds, and not on the + pointer itself. + Pointers are allowed to move outside of their defined bounds, but can be + dereferenced only within them. + There is also a new instruction for C-language pointer comparison + (\insnref{CPtrCmp}), and a NULL capability has been defined + as having + an in-memory representation of all zeroes without a tag, ensuring that BSS + (pre-zeroed memory) operates without change. + The offset behavior is also propagated into code capabilities, changing the + behavior of \PCC{}, \EPCC{}, \insnref{CJR}, \insnref{CJALR}, and + several aspects of exception handling. + The sealed bit was moved out of the permission mask to be a stand-alone bit + in the capability, and we went from independent \insnnoref{CSealCode} + and \insnnoref{CSealData} instructions to a single \insnref{CSeal} + instruction, and the \insnnoref{CSetType} instruction has been removed. + While the object type originates as a virtual address in an authorizing + capability, that interpretation is not mandatory due to use of a separate + hardware-defined permission for sealing. + +\item[UCAM-CL-TR-864 - 1.11 - January 2015] + This technical report refines CHERI ISAv3's convergence of C-language + pointers and capabilities; for example, it adds a \insnref{CIncOffset} + instruction that avoids read-modify-write accesses to adjust the offset + field, as well as exception-handling improvements. + TLB permission bits relating to capabilities now have modified semantics: + if the load-capability bit is not present, than capability tags are stripped + on capability loads from a page, whereas capability stores trigger an + exception, reflecting the practical semantics found most useful in our + CheriBSD prototype. + +\item[CHERI ISAv4 / UCAM-CL-TR-876 - 1.15 - November 2015] + This technical report describes \\ + CHERI ISAv4, introducing concepts required + to support 128-bit compressed capabilities. + A new \insnref{CSetBounds} instruction is added, allowing adjustments + to both lower and upper bounds to be simultaneously exposed to the hardware, + providing more information when making compression choices. + Various instruction definitions were updated for the potential for + imprecision in bounds. + New chapters were added on the protection model, and how CHERI features + compose to provide stronger overall protection for secure software. + Fast register-clearing instructions are added to accelerate domain switches. + A full set of capability-based load-linked, store-conditional instructions + are added, to better support multi-threaded pure-capability programs. + +\item[CHERI ISAv5 / UCAM-CL-TR-891 - 1.18 - June 2016] + CHERI ISAv5 primarily serves to introduce the CHERI-128 compressed + capability model, which supersedes prior candidate models. + A new instruction, \insnref{CGetPCCSetOffset}, allows jump targets to + be more efficiently calculated relative to the current \PCC{}. + The previous multiple privileged capability permissions authorizing access + to exception-handling state has been reduced down to a single system + privilege to reduce bit consumption in capabilities, but also to recognize + their effective non-independence. + In order to reduce code-generation overhead, immediates to + capability-relative loads and stores are now scaled. + +\item[CHERI ISAv6 / UCAM-CL-TR-907 - 1.20 - April 2017] + CHERI ISAv6 introduces support for kernel-mode compartmentalization, + jump-based rather than exception-based domain transition, + architecture-abstracted and efficient tag restoration, and more efficient + generated code. + A new chapter addresses potential applications of the CHERI protection model + to the RISC-V and x86-64 ISAs, previously described relative only to the + 64-bit MIPS ISA. + CHERI ISAv6 better explains our design rationale and research methodology. + +\item[CHERI ISAv7 / UCAM-CL-TR-927 - 7.0 - June 2019] + We more clearly differentiate an archi\-tecture-neutral CHERI protection + model vs. architecture-specific instantiations in 64-bit MIPS, 64-bit + RISC-V, and x86-64. + We have defined a new capability compression scheme, CHERI Concentrate, and + deprecated the previous CHERI-128 scheme. + CHERI-MIPS now supports special-purpose capability registers, which have + been moved out of the numbered general-purpose capability register space. + New special-purpose capability registers, including those for thread-local + storage, have been defined. + CHERI-RISC-V is more substantially elaborated. + A new compartment-ID register assists in resisting microarchitectural + side-channel attacks. + New optimized instructions with immediate fields improve the performance of + generated code. + Experimental 64-bit capabilities have been defined for 32-bit architectures, + as well as instructions to accelerate spatial and temporal memory safety. + The opcode reencoding begun in prior CHERI ISA specification versions has + now been completed. + +\item[CHERI ISAv8 / UCAM-CL-TR-951 - 8.0 - October 2020] + Capability compression is now part of the abstract model. + Both 32-bit and 64-bit architectural address sizes are supported. + Various previously experimental features, such as sentry capabilities and + CHERI-RISC-V, are now considered mature. We have defined a number of new + temporal memory-safety acceleration features including MMU assistance for a + load-side-barrier revocation model. + We have added a chapter on practical CHERI microarchitecture. + CHERI ISAv8 is synchronized with Arm Morello. + +\end{description} + +\section{Detailed CHERI ISA Version Change History} +\label{sec:detailed-cheri-isa-version-change-history} + +\begin{description} +\item[1.0] This first version of the CHERI architecture document was prepared + for a six-month deliverable to DARPA. + It included a high-level architectural description of CHERI, motivations + for our design choices, and an early version of the capability instruction + set. + +\item[1.1] The second version was prepared in preparation for a meeting of the + CTSRD External Oversight Group (EOG) in Cambridge during May 2011. + The update followed a week-long meeting in Cambridge, UK, in which many + aspects of the CHERI architecture were formalized, including + details of the capability instruction set. + +\item[1.2] The third version of the architecture document came as the first + annual reports from the CTSRD project were in preparation, including a + decision to break out formal-methods appendices into their own {\em CHERI + Formal Methods Report} for the first time. + With an in-progress prototype of the CHERI capability unit, we + significantly refined the CHERI ISA with respect to object capabilities, and + matured notions such as a trusted stack and the role of an + operating system supervisor. + The formal methods portions of the document was dramatically + expanded, with proofs of correctness for many basic security properties. + Satisfyingly, many `future work' items in earlier versions of the report + were becoming completed work in this version! + +\item[1.3] The fourth version of the architecture document was released + while + the first functional CHERI prototype was in testing. It reflects on + initial experiences adapting a microkernel to exploit CHERI capability + features. + This led to minor architectural refinements, such as improvements to + instruction opcode layout, some additional instructions (such as allowing + \insnref{CGetPerm} retrieve the unsealed bit), and automated + generation of opcode descriptions based on our work in creating a + CHERI-enhanced MIPS assembler. + +\item[1.4] This version updated and clarified a number of aspects of CHERI + following a prototype implementation used to demonstrate CHERI in November + 2011. + Changes include updates to the CHERI architecture diagram; replacement of + the \insnnoref{CDecLen} instruction with \insnnoref{CSetLen}, + addition of a \insnref{CMove} instruction; + improved descriptions of exception generation; clarification of the + in-memory representation of capabilities and byte order of permissions; + modified instruction encodings for \insnref{CGetLen}, + \insnref{CMove}, and \insnnoref{CSetLen}; + specification of reset state for capability registers; and clarification of + the \insnnoref{CIncBase} instruction. + +\item[1.5] This version of the document was produced almost two years + into the CTSRD project. It documented a significant revision (version 2) to + the CHERI ISA, which was motivated by our efforts to introduce + C-language extensions and compiler support for CHERI, with + improvements resulting from operating system-level work and + restructuring the BSV hardware specification to be more + amenable to formal analysis. The ISA, programming language, and + operating system sections were significantly updated. + +\item[1.6] This version made incremental refinements to version 2 of the + CHERI ISA, and also introduced early discussion of the CHERI2 prototype. + +\item[1.7] Roughly two and a half years into the project, this version + clarified and extended documentation of CHERI ISA features such as + \insnnoref{CCall}/\insnnoref{CReturn} and its software emulation, + Permit\_Set\_Type, the \insnref{CMove} + pseudo-op, new load-linked and instructions for store-conditional relative + to capabilities, and several bug fixes such as corrections to sign extension + for several instructions. + A new capability-coprocessor {\pathname cause} register, retrieved using a new + \insnref{CGetCause}, was added to allow querying information on the + most recent + CP2 exception (e.g., bounds-check vs type-check violations); priorities were + provided, and also clarified with respect to coprocessor exceptions vs. + other MIPS ISA exceptions (e.g., unaligned access). + This was the first version of the {\em CHERI Architecture Document} released + to early adopters. + +\item[1.8] Less than three and a half years into the project, this version + refined the CHERI ISA based on experience with compiler, OS, and userspace + development using the CHERI model. + To improve C-language compatibility, new instructions \insnref{CToPtr} + and \insnref{CFromPtr} were defined. + The capability permissions mask was extended to add user-defined permissions. + Clarifications were made to the behavior of jump/branch instructions relating + to branch-delay slots and the program counter. + \insnref{CClearTag} simply cleared a register's tag, not its value. + A software-defined capability-cause register range was made available, with a + new \insnref{CSetCause} instruction letting software set the cause for + testing or control-flow reasons. + New \insnnoref{CCheckPerm} and \insnnoref{CCheckType} instructions + were added, letting software + object methods explicitly test for permissions and the types of arguments. + TLB permission bits were added to authorize use of loading and storing + tagged values from pages. + New \insnmipsref{CGetDefault} and \insnmipsref{CSetDefault} pseudo-ops + have become the preferred way to control MIPS ISA memory access. + \insnnoref{CCall}/\insnnoref{CReturn} calling conventions were + clarified; \insnnoref{CCall} now pushes the + incremented version of the program counter, as well as stack pointer, to the + trusted stack. + +\item[1.9 - UCAM-CL-TR-850] + The document was renamed from the {\em CHERI Architecture Document} to the + {\em CHERI Instruction-Set Architecture}. + This version of the document was made available as a University of Cambridge + Technical Report. + The high-level ISA description and ISA reference were broken out into + separate chapters. + A new rationale chapter was added, along with more detailed explanations + throughout about design choices. + Notes were added in a number of places regarding non-MIPS adaptations of + CHERI and 128-bit variants. + Potential future directions, such as capability cursors, are discussed in + more detail. + Further descriptions of the memory-protection model and its use by operating + systems and compilers was added. + Throughout, content has been updated to reflect more recent work on compiler + and operating-system support for CHERI. + Bugs have been fixed in the specification of the \insnref{CJR} and + \insnref{CJALR} instructions. + Definitions and behavior for user-defined permission bits and OS exception + handling have been clarified. + +\item[1.10] + This version of the Instruction-Set Architecture is timed for delivery at + the end of the fourth year of the CTSRD Project. It reflects a significant + further revision to the ISA (version 3) focused on C-language compatibility, + better exception-handling semantics, and reworking of the object-capability + mechanism. + + The definition of the NULL capability has been revised such that the memory + representation is now all zeroes, and with a zeroed tag. This allows + zeroed memory (e.g., ELF BSS segments) to be interpreted as being filled + with NULL capabilities. To this end, the tag is now defined as unset, and + the Unsealed bit has now been inverted to be a Sealed bit; the + \insnnoref{CGetUnsealed} instruction has been renamed to + \insnmipsref{CGetSealed}. + + A new \coffset{} field has been added to the capability, which converts CHERI + from a simple base/length capability to blending capabilities and fat + pointers that associate a base and bounds with an offset. + This approach learns from the extensive fat-pointer research literature to + improve C-language compatibility. + The offset can take on any 64-bit value, and is added to the base on + dereference; if the resulting pointer does not fall within the base and + length, then an exception will be thrown. + New instructions are added to read (\insnref{CGetOffset}) and write + (\insnref{CSetOffset}) the + field, and the semantics of memory access and other CHERI instructions + (e.g., \insnnoref{CIncBase}) are updated for this new behavior. + + A new \insnref{CPtrCmp} instruction has been added, which provides + C-friendly + comparison of capabilities; the instruction encoding supports various types + of comparisons including `equal to', `not equal to', and both signed and + unsigned `less than' and `less than or equal to' operators. + + \insnref{CGetPCC} now returns \PC{} as the \coffset{} field of the + returned \PCC{} rather than storing it to a general-purpose integer register. + \insnref{CJR} and \insnref{CJALR} now accept target \PC{} values + via the offsets of their + jump-target capability arguments rather than via explicit general-purpose + integer registers. + \insnref{CJALR} now allows specification of the return-program-counter + capability register in a manner similar to return-address arguments to the + MIPS \insnnoref{JALR} instruction. + + \insnnoref{CCall} and \insnnoref{CReturn} are updated to save and + restore the saved \PC{} in the + \coffset{} field of the saved \EPCC{} rather than separately. + \EPCC{} now incorporates the saved exception \PC{} in its \coffset{} field. + The behavior of \EPCC{} and expectations about software-supervisor behavior + are described in greater detail. + The security implications of exception cause-code precedence as relates to + alignment and the emulation of unaligned loads and stores are clarified. + The behavior of \insnref{CSetCause} has been clarified to indicate + that the instruction should not raise an exception unless the check for + \capperm*{Access\_EPCC} fails. + When an exception is raised due to the state of an argument register for + an instruction, it is now defined which register will be named as the source + of the exception in the capability cause register. + + The object-capability type field is now 24-bit; while a relationship to + addresses is maintained in order to allow delegation of type allocation, + that relationship is deemphasized. + It is assumed that the software type manager will impose any required + semantics on the field, including any necessary uniqueness for the software + security model. + The \insnnoref{CSetType} instruction has been removed, and a single + \insnmipsref{CSeal} instruction + replaces the previous separate \insnnoref{CSealCode} and + \insnnoref{CSealData} instructions. + + The validity of capability fields accessed via the ISA is now defined for + untagged capabilities; the undefinedness of the in-memory representation of + capabilities is now explicit in order to permit `non-portable' + micro-architectural optimizations. + + There is now a structured description of the pseudocode language used in + defining instructions. + Format numbers have now been removed from instruction descriptions. + + Ephemeral capabilities are renamed to `local capabilities,' and + non-ephemeral capabilities are renamed to `global capabilities'; the + semantics are unchanged. + +\item[1.11 - UCAM-CL-TR-864] + This version of the CHERI ISA has been prepared for publication as a + University of Cambridge technical report. + It includes a number of refinements to CHERI ISA version 3 based on further + practical implementation experience with both C-language memory protection + and software compartmentalization. + + There are a number of updates to the specification reflecting introduction + of the \coffset{} field, including discussion of its semantics. + A new \insnref{CIncOffset} instruction has been added, which avoids the + need to read the offset into a general-purpose integer register for frequent + arithmetic operations on pointers. + + Interactions between \EPC{} and \EPCC{} are now better specified, including + that use of untagged capabilities has undefined behavior. + \insnref{CBTS} and \insnref{CBTU} are now defined to use + branch-delay slots, matching other MIPS-ISA branch instructions. + \insnref{CJALR} is defined as suitably incrementing the returned + program counter, along with branch-delay slot semantics. + Additional software-path pseudocode is present for \insnnoref{CCall} and + \insnnoref{CReturn}. + + \insnref{CAndPerm} and \insnref{CGetPerm} use of argument-register + or return-register permission bits has been clarified. + Exception priorities and cause-code register values have been defined, + clarified, or corrected for \insnref{CClearTag}, + \insnref{CGetPCC}, \insnref{CSC}, and \insnref{CSeal}. + Sign or zero extension for immediates and offsets are now defined + \insnmipsref[clbhwd]{CL}, \insnmipsref[clbhwd]{CS}, + and other instructions. + + Exceptions caused due to TLB bits controlling loading and storing of + capabilities are now CP2 rather than TLB exceptions, reducing code-path + changes for MIPS exception handlers. + These TLB bits now have modified semantics: {\bf LC} now discards tag bits + on the underlying line rather than throwing an exception; {\bf SC} will + throw an exception only if a tagged store would result, rather than + whenever a write occurs from a capability register. + These affect \insnref{CLC} and \insnref{CSC}. + + Pseudocode definitions now appear earlier in the chapter, and have now been + extended to describe \EPCC{} behavior. + The ISA reference has been sorted alphabetically by instruction name. + +\item[1.12] This is an interim release as we begin to grapple with 128-bit + capabilities. + This requires us to better document architectural assumptions, but also + start to propose changes to the instruction set to reflect differing + semantics (e.g., exposing more information to potential capability + compression). + A new \insnref{CSetBounds} instruction is proposed, which allows both + the base and length of a capability to be set in a single instruction, which + may allow the micro-architecture to reduce potential loss of precision. + Pseudocode is now provided for both the pure-exception version of the + \insnnoref{CCall} instruction, and also hardware-accelerated permission + checking. + +\item[1.13] This is an interim release as our 128-bit capability format (and + general awareness of imprecision) evolves; this release also makes early + infrastructural changes to support an optional converging of capability and + general-purpose integer register files. + + Named constants, rather than specific sizes (e.g., 256-bit vs. 128-bit) are + now used throughout the specification. + Reset state for permissions is now relative to available permissions. + Two variations on 128-bit capabilities are defined, employing two variations + on capability compression. + Throughout the specification, the notion of ``representable'' is now + explicitly defined, and non-representable values must now be handled. + + The definitions of \insnref{CIncOffset}, \insnref{CSetOffset}, and + \insnref{CSeal} have been modified to reflect the potential for + imprecision. + In the event of a loss of precision, the capability base, rather than + offset, will be preserved, allowing the underlying memory object to continue + to be accurately represented. + + Saturating behavior is now defined when a compressed capability's length + could represent a value greater than the maximum value for a 64-bit MIPS + integer register. + + EPCC behavior is now defined when a jump or branch target might push the + offset of PCC outside of the representable range for EPCC. + + \insnnoref{CIncBase} and \insnnoref{CSetLen} are deprecated in favor + of \insnref{CSetBounds}, which presents changes to base and bounds to + the hardware atomically. + The \insnref{CMove} pseudo-operation is now implemented using + \insnref{CIncOffset} rather than \insnnoref{CIncBase}. + \insnref{CFromPtr} has been modified to behave more like + \insnref{CSetOffset}: only the offset, not the base, is modified. + Bug fixes have been applied to the definitions of \insnref{CSetBounds} + and \insnref{CUnseal}. + + Several bugs in the specification of \insnref{CLC}, \insnref{CLLD}, + \insnref{CSC}, and \insnref[csbhwd]{CSD}, relating to omissions + during the update to capability offsets, have been fixed. + \insnref{CLC}'s description has been updated to properly reflect its + immediate argument. + + New instructions \insnref{CClearHi} and \insnref{CClearLo} have + been added to accelerate register clearing during protection-domain + switches. + + New pseudo-ops \insnref{CGetEPCC}, \insnref{CSetEPCC}, + \insnref{CGetKCC}, \insnref{CSetKCC}, \insnref{CGetKDC}, and + \insnref{CSetKDC} have been defined, in the interests of better + supporting a migration of `special' registers out of the capability register + file -- which facilitates a convergence of capability and general-purpose + integer register files. + +\item[1.14] + Two new chapters have been added, one describing the abstract CHERI + protection model in greater detail (and independent from concrete ISA + changes), and the second exploring the composition of CHERI's ISA-level + features in supporting higher-level software protection models. + + The value of the NULL capability is now centrally defined (all fields zero; + untagged). + + \insnref{ClearLo} and \insnref{ClearHi} instructions are now + defined for clearing general-purpose integer registers, supplementing + \insnref{CClearHi} and \insnref{CClearLo}. + All four instructions are described together under \insnref{CClearRegs}. + + A new \insnref{CSetBoundsExact} instruction is defined, allowing an + exception to be thrown if an attempt to narrow bounds cannot occur + precisely. + This is intended for use in memory allocators where it is a software + invariant that bounds are always exact. + A new exception code is defined for this case. + + A full range of data widths are now support for capability-relative + load-linked, store conditional: \insnref{CLLB}, \insnref{CLLH}, + \insnref{CLLW}, \insnref{CLLD}, \insnref{CSCB}, + \insnref{CSCH}, \insnref{CSCW}, and \insnref{CSCD} (as well as + unsigned load-linked variations). + Previously, only a doubleword variation was defined, but cannot be used to + emulate the narrower widths as fine-grained bounds around a narrow type + would throw a bounds-check exception. + Existing load-linked, store-conditional variations for capabilities + (\insnref{CLLC}, \insnref{CSCC}) have been updated, including with + respect to opcode assignments. + + A new `candidate three' variation on compressed capabilities has been + defined, which differentiates sealed and unsealed formats. + The unsealed variation invests greater numbers of bits in bounds accuracy, + and has a full 64-bit cursor, but does not contain a broader set of + software-defined permissions or an object-type field. + The sealed variation also has a full 64-bit cursor, but has reduced bounds + accuracy in return for a 20-bit object-type field and a set of + software-defined permissions. + + `Candidate two' of compressed capabilities has been updated to reflect + changes in the hardware prototype by reducing toBase and toBound precision + by one bit each. + + Explicit equations have been added explaining how bounds are calculated + from each of the 128-bit compressed capability candidates, as well as their + alignment requirements. + + Exception priorities have been documented (or clarified) for a number of + instructions including \insnref{CJALR}, \insnref{CLC}, + \insnref{CLLD}, \insnref{CSC}, \insnref{CSCC}, + \insnnoref{CSetLen}, \insnref{CSeal}, \insnref{CUnSeal}, and + \insnref{CSetBounds}. + + The behavior of \insnref{CPtrCmp} is now defined when an undefined + comparison type is used. + + It is clarified that capability store failures due to TLB-enforced + limitations on capability stores trigger a TLB, rather than a CP2, + exception. + + A new capability comparison instruction, \insnref{CEXEQ}, checks + whether all fields in the capability are equal; the previous + \insnref{CEQ} instruction checked only that their offsets pointed at the + same location. + + A new capability instruction, \insnref{CSUB}, allows the implementation + of C-language pointer subtraction semantics with the atomicity properties + required for garbage collection. + + The list of BERI- and CHERI-related publications, including peer-reviewed + conference publications and technical reports, has been updated. + +\item[1.15 - UCAM-CL-TR-876] + This version of the CHERI ISA, \textit{CHERI ISAv4}, has been prepared for + publication as a University of Cambridge technical report. + + The instructions \insnnoref{CIncBase} and \insnnoref{CSetLen} + (deprecated in version 1.13 of the CHERI ISA) have now been removed in favor + of \insnref{CSetBounds} (added in version 1.12 of the CHERI ISA). + The new instruction was introduced in order to atomically expose changes to + both upper and lower bounds of a capability, rather than requiring them to + be updated separately, required to implement compressed capabilities. + + The design rationale has been updated to better describe our ongoing + exploration of whether special registers (such as \KCC{}) should be in the + capability register file, and the potential implications of shifting to a + userspace exception handler for \insnnoref{CCall}/\insnnoref{CReturn}. + +\item[1.16] This is an interim update of the instruction-set specification in + which aspects of the 128-bit capability model are clarified and extended. + + The ``candidate 3'' unsealed 128-bit compressed capability representation + has been to increase the exponent field (\cexponent{}) to 6 bits from 4, and + the \cbasebits{} and \ctopbits{} fields have been reduced to 20 bits each + from the 22 bits. + \cperms{} has been increased from 11 to 15 to allow for a larger set of + software-defined permissions. +% XXX-BD: 2 - 4 + 4 != 0. Presumably we consumed two reserved bits? + The sealed representation has also been updated similarly, with a total of + 10 bits for \cotype{} (split over {\bf otypeLow} and {\bf otypeHigh}), 10 + bits each for \cbasebits{} and \ctopbits{}, and a 6-bit exponent. + The algorithm for decompressing a compressed capability has been changed to + better utilize the encoding space, and to more clearly differentiate + representable from in-bounds values. + A variety of improvements and clarifications have been made to the + compression model and its description. + + Differences between, and representations of, permissions for 128-bit and + 256-bit capability are now better described. + + Capability unrepresentable exceptions will now be thrown in various + situations where the result of a capability manipulation or operation cannot + be represented. + For manipulations such as \insnref{CSeal} and \insnref{CFromPtr}, + an exception will be thrown. + For operations such as \insnref{CBTU} and \insnref{CBTS}, the + exception will be thrown on the first instruction fetch following a branch + to an unrepresentable target, rather than on the branch instruction itself. + CHERI1 and CHERI2 no longer differ on how out-of-bounds exceptions are + thrown for capability branches: it uniformly occurs on fetching the target + instruction. + + The ISA specification makes it more clear that \insnmipsref{CEQ}, + \insnmipsref{CNE}, \insnmipsref[cptrcmp]{CL[TE]U}, and \insnmipsref{CEXEQ} are + forms of the \insnref{CPtrCmp} instruction. + + The ISA todo list has been updated to recommend a capability + conditional-move (\insnnoref{CCMove}) instruction. + + There is now more explicit discussion of the MIPS n64 ABI, Hybrid ABI, + and Pure-Capability ABI. + Conventions for capability-register have been updated and clarified -- + for example, register assignments for the stack capability, jump register, + and link register. + The definition that {\bf RCC}, the return code capability, is register + \creg{24} has been updated to reflect our use of \creg{17} in actual code + generation. + + Erroneous references to an undefined instruction \insnnoref{CSetBase}, + introduced during removal of the \insnnoref{CIncBase} instruction, have + been corrected to refer to \insnref{CSetBounds}. + +\item[1.17] This is an interim update of the instruction-set architecture + enhancing (and specifying in more detail) the CHERI-128 ``compressed'' + 128-bit capability format, better aligning the 128-bit and 256-bit models, + and adding capability-related instructions required for more efficient code + generation. + This is a draft release of what will be considered \textit{CHERI ISAv5}. + + The chapter on ISA design now includes a section describing ``deep'' versus + ``surface'' aspects of the CHERI model as mapped into the ISA. + For example, use of tagged capabilities is a core aspect of the model, but + the particular choice to have a separate capability register file, rather + than extending general-purpose integer registers to optionally hold capabilities, is + a surface design choice in that the operating system and compiler can target + the same software-visible protection model against both. + Likewise, although CHERI-128 specifies a concrete compression model, a range + of compression approaches are accepted by the CHERI model. + + A new chapter has been added describing some of our assumptions about how + capabilities will be used to build secure systems, for example, that + untrusted code will not be permitted to modify TLB state -- which permits + changing the interpretation of capabilities relative to virtual addresses. + + The rationale chapter has been updated to more thoroughly describe our + capability compression design space. + + A new CHERI ISA quick-reference appendix has been added to the + specification, documenting both current and proposed instruction + encodings. + + Sections of the introduction on historical context have been shifted to a + stand-alone chapter. + + Descriptions in the introduction have been updated relating to + our hardware and software prototypes. + + References to PhD dissertations on CHERI have been added to the publications + section of the introduction. + + A clarification has been added: the use of the term ``capability + coprocessor'' relates to CHERI's utilization of the MIPS ISA coprocessor + opcode space, and is not intended to suggest substantial decoupling of + capability-related processing from the processor design. + + Compressed capability ``candidate 3'' is now CHERI-128. The \cbasebits{}, + \ctopbits{} and + \ccursor{} fields have been renamed respectively \cB{}, \cT{} and \caddr{} + (following the terminology used in the micro paper). When sealed, only the + top 8 bits of the \cB{} and \cT{} fields are preserved, and the bottom 12 + bits are zeroes, which implies stronger alignment requirements for sealed + capabilities. The exponent \cexponent{} field remains a 6-bit field, but its + bottom 2 bits are ignored, as it is believed that coarser granularity is + acceptable, and making the hardware simpler. The \cotype{} field benefits + from the shorter \cB{} and \cT{} fields and is now 24 bits -- which is the same + as the \cotype{} for 256-bit CHERI. Finally, the representable region + associated with a capability has changed from being centred around the + described object to an asymmetric region with more space above the object + than below. The full description is available in Section~\ref{compression}. + + Alignment requirements for software allocators (such as stack and heap + allocators) in the presence of capability compression are now more + concisely described. + + The immediate operands to load and store instructions, including + \insnmipsref{CLC}, \insnmipsref{CSC}, \insnmipsref[clbhwd]{CL[BHWD][U]}, and + \insnmipsref[csbhwd]{CS[BHWD]} are now ``scaled'' by the width of the data being + stored (with the exception of capability stores, where scaling is by 16 + bytes regardless of in-memory capability size). + This extends the range of capability-relative loads and stores, permitting + a far greater proportion of stack spills to be expressed without additional + stack-pointer modification. + This is a binary-incompatible change to the ISA. + + The textual description of the \insnref{CSeal} instruction has been + updated to match the pseudocode in using $>=$ rather than $>$ in selecting + an exception code. + + A redundant check has been removed in the definition of the + \insnref{CUnseal} instruction, and an explanation added. + + Opcodes have now been specified for the \insnref{CSetBoundsExact} and + \insnref{CSub} instructions. + + To improve code generation when constructing a \PCC{}-relative capability as + a jump target, a new \insnref{CGetPCCSetOffset} instruction has been + added. + This instruction has the combined effects of performing sequential + \insnref{CGetPCC} and \insnref{CSetOffset} operations. + + A broader set of opcode rationalizations and cleanups have been applied + across the ISA, to facilitate efficient decoding and future use of the + opcode space. + This includes changes to \insnref{CGetPCC}. + + \creg{25} is no longer reserved for exception-handler use, as \creg{27} and + \creg{28} are already reserved for this purpose. + It is therefore available for ABI use. + + The 256-bit architectural capability model has been updated to use a single + system permission, \cappermASR, to control access to + exception-handling and privileged ISA state, rather than splitting it over + multiple permissions. + This brings the permission models in 128-bit and 256-bit representations + back into full alignment from a software perspective. + This also simplifies permission checking for instructions such as + \insnref{CClearRegs}. + The permission numbering space has been rationalized as part of this change. + Similarly, the set of exceptions has been updated to reflect a single system + permission. + The descriptions of various instructions (such as \insnref{CClearRegs} + have been updated with respect to revised protections for special registers + and exception handling. + + The descriptions of \insnnoref{CCall} and \insnnoref{CReturn} now + include an explanation of additional software-defined behavior such as + capability control-flow based on the local/global model. + + The common definition of privileged registers (included in the definitions + of instructions) has been updated to explicitly include \EPCC{}. + + Future ISA additions are proposed to add testing of branch instructions for + NULL and non-NULL capabilities. + +\item[1.18 - UCAM-CL-TR-891] This version of the CHERI ISA, + \textit{CHERI ISAv5}, has been prepared for publication as a University of + Cambridge technical report. + + The chapter on the CHERI protection model has been refined and extending, + including adding more information on sealed capabilities, the link between + memory allocation and the setting of bounds and permissions, more detailed + coverage of capability flow control, and interactions with MMU-based models. + + A new chapter has been added exploring assumptions that must be made when + building high-assurance software for CHERI. + + The detailed ISA version history has shifted from the introduction to a new + appendix; a summary of key versions is maintained in the introduction, along + with changes in the current document version. + + A glossary of key terms has been added. + + The term ``coprocessor'' is deemphasized, as, while it refers correctly to + CHERI's use of the MIPS opcode extension space, some readers found it + suggestive of an independent hardware unit rather than tight integration into + the processor pipeline and memory subsystem. + + A reference has been added to Robert Norton's PhD dissertation on optimized + CHERI domain switching. + + A reference has been added to our PLDI 2016 paper on C-language semantics and + their interaction with the CHERI model. + + The object-type field in both 128-bit and 256-bit capabilities is now 24 bits, + with Top and Bottom fields reduced to 8 bits for sealed capabilities. + This reflects a survey of current object-oriented software systems, suggesting + that 24 bits is a more reasonable upper bound than 20 bits. + + The assembly arguments to \insnref{CJALR} have been swapped for greater + consistency with jump-and-link register instructions in the MIPS ISA. + + We have reduced the number of privileged permissions in the 256-bit capability + model to a single privileged permission, \cappermASR, to match + 128-bit CHERI. + This is a binary-incompatible change. + + We have improved the description of the CHERI-128 model in a number of ways, + including a new section on the CHERI-128 representable bounds check. + + The architecture chapter contains a more detailed discussion of potential ways + to reduce the overhead of CHERI by reducing the number of capability + registers, converging the general-purpose integer and capability register files, + capability compression, and so on. + + We have extended our discussion of ``deep'' vs ``shallow'' aspects of the + CHERI model. + + New sections describe potential non-pointer uses of capabilities, as well as + possible uses as primitives supporting higher-level languages. + + Instructions that convert from integers to capabilities now share common + \ccode{int_to_cap} pseudocode. + + The notes on \insnref{CBTS} have been synchronized to those on + \insnref{CBTU}. + + Use of language has generally been improved to differentiate the + architectural 256-bit capability model (e.g., in which its fields are + 64-bit) from the 128-bit and 256-bit in-memory representations. + This includes consideration of differing representations of capability + permissions in the architectural interface (via instructions) and the + microarchitectural implementation. + + A number of descriptions of features of, and motivations for, the CHERI design + have been clarified, extended, or otherwise improved. + + It is clarified that when combining immediate and register operands with + the base and offset, 64-bit wrap-around is permitted in capability-relative + load and store instructions -- rather than throwing an exception. + This is required to support sound optimizations in frequent + compiler-generated load/store sequences for C-language programs. + +\item[1.19] This release of the \textit{CHERI Instruction-Set Architecture + (ISA) Specification} is an interim version intended for submission to + DARPA/AFRL to meet the requirements of CTSRD deliverable A015. + + The behavior of \insnref{CToPtr} in the event that the pointer of one + capability is to the base of the containing capability has been clarified. + + The \cappermASR permission is extended to cover non-CHERI ISA + privileges, such as use of MIPS TLB-management, interrupt-control, + exception-handling, and cache-control instructions available in the kernel + ring. + The aim of these in-progress changes is to allow the compartmentalization of + kernel code. + +\item[1.20 - UCAM-CL-TR-907] This version of the CHERI ISA, \textit{CHERI + ISAv6}, has been prepared for publication as University of Cambridge + technical report UCAM-CL-TR-907. + + Chapter~\ref{chap:introduction} has been substantially reformulated, + providing brief introductions to both the CHERI protection model and + CHERI-MIPS ISA, with much remaining content on our research methodology now + shifted to its own new chapter, Chapter~\ref{chap:research}. + Our architectural and application-level least-privilege motivations are now + more clearly described, as well as hybrid aspects of the CHERI approach. + Throughout, better distinction is made between the CHERI protection model and + the CHERI-MIPS ISA, which is a specific instantiation of the model with + respect to 64-bit MIPS. + The research methodology chapter now provides a discussion of our overall + approach, more detailed descriptions of various phases of our research and + development cycle, and describes major transitions in our approach as the + project proceeded. + + Chapter~\ref{chap:model} on the software-facing CHERI protection model has + been improved to provide more clear explanations of our approach as well as + additional illustrations. + The chapter now more clearly enunciates two guiding principles + underlying the CHERI ISA design: the \textit{principle of least privilege}, + and the \textit{principle of intentional use}. + The former has been widely considered in the security literature, and + motivates privilege reduction in the CHERI ISA. + The latter has not previously described, and is supports the use of explicitly + named rights, rather than implicitly selected ones, wherever possible in order + to avoid `confused deputy' problems. + Both contribute to vulnerability mitigation effects. + New sections have been added on revocation and garbage collection. + The role and implementation of monotonicity (and also non-monotonicity) in + the ISA are more clearly described. + + A chapter on architectural sketches has been added, describing how the CHERI + protection model might be introduced in the RISC-V and x86-64 ISAs. + In doing so, we identify a number of key aspects of the CHERI model that are + required regardless of the underlying ISA. + We argue that the CHERI protection model is a \textit{portable} model that can + be implemented consistently across a broad range of underlying ISAs and + concrete integrations with those ISAs. + One implication of this argument is that portable CHERI-aware software can be + implemented across underlying architectural implementations. + + Chapter~\ref{chap:architecture} now describes, at a high level, CHERI's + expectations for tagged memory. + + We in general now prefer the phrase ``control-flow robustness'' to + ``control-flow integrity'' when talking about capability protection for code + pointers, in order to avoid confusion with conventional CFI. + + The descriptions of software-defined aspects of the \insnnoref{CCall} and + \insnnoref{CReturn} instructions have been removed from the description and + pseudocode of each instruction. + They are instead part of an expanded set of notes on potential software use + for these instructions. + + A new \insnnoref{CCall} selector 1 has been added that provides a jump-like + domain transition without use of an architectural exception. + In this mode of operation, \insnnoref{CCall} unseals the sealed code and + data capabilities to enter the new domain, offering a different set of + hardware and software tradeoffs from the existing selector-0 semantics. + For example, complex exception-related mechanism is avoided in hardware for + domain switches, with the potential to substantially improve performance. + Software would most likely use this mechanism to branch into a trusted + intermediary capability of supporting safe and controlled switching to a new + object. + + To support the new \insnnoref{CCall} selector 1, a new permission, + \emph{Permit\_CCall} is defined authorizing use of the selector on sealed + capabilities. + The permission must be present on both sealed code and data capabilities. + + To support the new \insnnoref{CCall} selector 1, a new CP2 exception cause + code, Permit\_CCall Violation is defined to report a lack of the + \emph{Permit\_CCall} permission on sealed code or data capabilities passed to + \insnnoref{CCall}. + + New experimental instructions \insnref{CBuildCap} (import a capability), + \insnref{CCopyType} (import the \cotype{} field of a capability), and + \insnref{CCSeal} (conditionally seal a capability) have been added + to the ISA to be used when re-internalizing capabilities that have been + written to non-capability-aware memory or storage. + This instruction is intended to satisfy use cases such as swapping to + disk, migrating processes, migrating virtual machines, and run-time linking. + A suitable authorizing capability is required in order to restore the + tag. + As these instructions are considered experimental, they are documented in + Appendix~\ref{app:experimental} rather than the main specification. + + The \insnref{CGetType} instruction now returns $-1$ when used on an + unsealed capability, in order to allow it to be more easily used with + \insnref{CCSeal}. + + Two new conditional-move instructions are added to the CHERI-MIPS ISA: + \insnref{CMOVN} (conditionally move capability on non-zero), and + \insnref{CMOVZ} (conditionally move capability on zero). + These complement existing conditional-move instructions in the 64-bit MIPS + ISA, allowing more efficient generated code. + + The \insnref{CJR} (capability jump register) and \insnref{CJALR} + (capability jump and link register) have been changed to accept non-global + capability jump targets. + + The \insnref{CLC} (capability load capability) and \insnref{CLLC} + (capability load-linked conditional) instructions will now strip loaded tags, + rather than throwing an exception, if the Permit\_Load\_Capability permission + is not present. + + The \insnref{CToPtr} (capability to pointer) instruction now checks that + the source register is not sealed, and performs comparative range checks of + the two source capabilities. + More detailed rationale has been provided for the design of the + \insnref{CToPtr} instruction in Chapter~\ref{chap:rationale}. + + The pseudocode for the \insnnoref{CCheckType} (capability check + type) instruction has been corrected to test uperm as well as perm. + The pseudocode for \insnnoref{CCheckType} has been corrected to test the + sealed bit on both source capabilities. + An encoding error for \insnnoref{CCheckType} in the ISA quick reference has + been corrected. + + The pseudocode for the \insnref{CGetPerm} (capability get permissions) + instruction has been updated to match syntax used in the + \insnref{CGetType} and \insnref{CGetCause} instructions. + + The pseudocode for the \insnref{CUnseal} (capability unseal) instruction + has been corrected to avoid an aliasing problem when the source and + destination register are the same. + + The description of the \insnref{CSeal} (capability seal) instruction has + been clarified to explain that precision cannot be lost in the case where + bounds are no longer precisely representable, as an exception will be thrown. + + The description of the fast representability check for compressed capabilities + has been improved. + + CHERI-related exception handling behavior is now clarified with respect to the + MIPS EXL status bit, with the aim of ensuring consistent behavior. + Regardless of bounds set on \KCC{}, a suitable offset is selected so that the + standard MIPS exception vector will be executed via the exception \PCC{}. + + The section on CHERI control in Chapter~\ref{chap:cheri-mips} has been + clarified to more specifically identify 64-bit MIPS privileged instructions, + KSU bits, and general operation modified by the \cappermASR + permission. + The section now also more specifically described privileged behaviors not + controlled by the permission, such as use of specific exception vectors. + A corresponding rationale section has been added to + Chapter~\ref{chap:rationale}. + + A number of potential future instruction-set improvements relating to + capability compression, control flow, and instruction variants with immediates + have been added to the future ISA changes list in + Chapter~\ref{chap:architecture}. + + Opcode-space reservations for the previously removed \insnnoref{CIncBase} + and \insnnoref{CSetLen} instructions have also been removed. + + \creg{25}, which had its hard-coded ISA use removed in CHERI ISAv5, has now + been made a caller-save capability register in the ABI. + + Citations to further CHERI research publications have been added. + +\item[1.21] This release of the \textit{CHERI Instruction-Set Architecture} is + an interim version intended for submission to DARPA/AFRL to meet the + requirements of CTSRD deliverable A001, and contains the following changes + relative to CHERI ISAv6: + + The ISA encoding reference has been updated for new experimental + instructions. + + A new \insnref{CNExEq} instruction has been added, which provides a + more efficient implementation of a test for negative exact inequality than + utilizing \insnref{CExEq} and inverting the result. + + Specify that when a TLB exception results from attempting to store a + tagged capability via a TLB entry that does not authorize tagged store, the + MIPS EntryHi register will be set correspondingly. + +\item[7.0-ALPHA1] +\input{app-versions-7-0-alpha1} + +\item[7.0-ALPHA2] +\input{app-versions-7-0-alpha2} + +\item[7.0-ALPHA3] +\input{app-versions-7-0-alpha3} + +\item[7.0-ALPHA4] +\input{app-versions-7-0-alpha4} + +\item[7.0] +\input{app-versions-7-0} + +\item[8.0] +\input{app-versions-8-0} + +\end{description} diff --git a/bib-sorting.conf b/bib-sorting.conf new file mode 100644 index 00000000..aa1d456e --- /dev/null +++ b/bib-sorting.conf @@ -0,0 +1,15 @@ + + + + year + month + day + + + author + + + title + + + diff --git a/chap-architecture.tex b/chap-architecture.tex new file mode 100644 index 00000000..469d092e --- /dev/null +++ b/chap-architecture.tex @@ -0,0 +1,3433 @@ +\chapter{Mapping CHERI Protection into Architecture} +\label{chap:architecture} + +%\rwnote{This chapter has been largely rearranged, but requires substantial +% editing to tidy up the results, shift some contents to/from +% architecture-specific chapters, and to update the introduction and first few +% sections. It would be nice to add a section on ensuring that both the base +% ISA and our extensions consistently enforce CHERI's invariants/safety +% properties -- e.g., provenance validity, monotonicity, etc.} + +In this chapter, we explore architecture-neutral aspects of the mapping from +the abstract CHERI protection model into Instruction-Set Architectures (ISAs). +We consider the high-level architectural goals in mappings and the +implications of our specific capability-system model before turning to the +concrete definitions associated with CHERI's architectural capabilities, +register files, tagged memory, and its composition with various existing +architectural features such as exception handling and virtual memory. + +We conclude with a consideration of ``deep'' versus ``surface'' design +choices: where there is freedom to make different choices in instantiating +the CHERI model in a specific ISA, with an eye towards both the adaptation +design space and also applications to further non-MIPS ISAs, and where +divergence might lead to protection inconsistency across architectures. + +\section{Architectural Instantiations of CHERI Protection} + +Our current instantiations within concrete ISAs are: + +\begin{description} +\item[CHERI-MIPS] is our mature reference instantiation. + It is an instantiation of the CHERI protection model against the 64-bit + MIPS ISA (Chapter~\ref{chap:cheri-mips}). + + CHERI-MIPS has been validated with a complete end-to-end hardware-software + stack including a formal ISA model, ISA-level simulations, one FPGA + implementation, an adaptation of our CheriBSD operating system, + Clang/LLVM/LLD toolchain, GDB debugger, and application suite. + +\item[CHERI-RISC-V] is a draft experimental instantiation that is + seeing increasing use in our research, and will become our reference ISA in + the future. + It is an instantiation of the CHERI protection model against 32-bit and + 64-bit RISC-V (Chapter~\ref{chap:cheri-riscv}). + + CHERI-RISC-V has been validated with a complete end-to-end hardware-software + stack including a formal ISA model, ISA-level simulations, three FPGA + implementations, adaptations of our CheriBSD and CheriFreeRTOS operating + systems, Clang/LLVM/LLD toolchain, GDB debugger, and application suite. + + We expect continuing disruptive modification to this ISA mapping, including + reencoding of many key instructions, as it transitions to a more mature + status. + +\item[Arm Morello] is an experimental instantiation created by Arm + in collaboration with the CHERI team~\cite{arm-morello}. + It is an instantiation of the CHERI protection model against the 64-bit + ARMv8-A ISA. + % (Chapter~\ref{chap:morello}). + \rwnote{Need a Morello chapter.} + + Morello is the target of an in-progress CPU, SoC, and board design based on + Arm's Neoverse N1 system architecture, and has been validated for much of + the end-to-end- hardware-stack including a formal ISA model, ISA-level + simulations, an adaptation of our CheriBSD operating system, Clang/LLVM/LLD + toolchain, GDB debugger, and application suite. + +\item[CHERI-x86-64] is a sketch instantiation intended to describe + a potential approach to applying the CHERI protection model to the x86-64 + ISA -- the dominant non-RISC architecture (Chapter~\ref{chap:cheri-x86-64}). +\end{description} + +\section{High-Level Architectural Goals} + +In addition to the broad abstract goal of supporting pointer-centric +protection with strong compatibility and performance objectives, we have +pursued the following architectural goals in integrating CHERI into +contemporary instruction-set architectures: + +\begin{enumerate} + +\item When mapping the CHERI model into RISC architectures, CHERI's extensions + should subscribe to the RISC design philosophy: a load-store instruction set + intended to be targeted by compilers, with more complex instructions + motivated by quantitative analysis. + While current page-table structures (or in the case of MIPS, simply TLB + mechanisms) are retained for functionality and compatibility, new + table-oriented structures are avoided in describing new security primitives. + In general, instructions that do not access memory or trigger an exception + should be single-cycle register-to-register operations. + +\item New primitives, such as tagged memory and capabilities, are aligned + closely with current microarchitectural designs (e.g., as relates to + register files, pipelined and superscalar processors, memory subsystems, and + buses), offering minimal disruption necessary to offer substantial semantic + and performance improvements that would be difficult to support with + current architectures. + Where current de-facto approaches to microarchitecture must be changed to + support CHERI -- such as through the adoption of architectural tagged memory + -- there are efficient implementations. + +\item CHERI composes sensibly with MMU-based memory protection: current + MMU-based operating systems should run unmodified on CHERI designs, and as + CHERI support is introduced in an MMU-based operating system, it should + compose naturally while allowing both capability-aware and legacy programs + to run side-by-side. + This allows software designers to view the system as a set of more + conventional virtual address spaces within which CHERI offers protection -- + or as a single-address-space system environment as use of the MMU is + minimized. + +\item As protection pressure shifts from conventional MMU-based techniques to + reference-oriented protection using CHERI capabilities, page-table + efficiency increases as larger page sizes cease to penalize protection. + +\item Protection primitive use is common-case, not exceptional, and occurs + in performance-centric code paths such as stack and heap + allocation, on pointer arithmetic, and on pointer-relative load and store, + rather than being an infrequent higher-cost activity that can be amortized. + +\item The principles of least privilege and intentional use dictate a number + of aspects of CHERI ISA design, including requiring that no confusion arise + between the use of capabilities as pointers versus integers as pointers. + Load, store, and jump instructions will never automatically select + semantics based on presence of a tag -- for example, to avoid opportunities + accidental use of the wrong right (e.g., by virtue of a capability tag being + cleared due to an exploitable software vulnerability leading to its + interpretation as an integer virtual address). + Similarly, associative lookups of capabilities are entirely avoided. + + Trade-offs around this design goal inevitably exist. + For example, to run unmodified software, CHERI provides a Default Data + Capability that is transparently dereferenced when legacy + integer-pointer-based code accesses memory, which we deem necessary for + compatibility reasons. + Similarly, we do not currently choose to provide granular control over the + use of ring-based processor privilege, in order to avoid the complexity and + disruption of implementing entirely new interfaces for interrupt and MMU + management, using a single permission on code capabilities rather than a + broad set of possible capabilities representing different privileges. + A purer (non-hybridized) capability-system design would avoid these + design choices. + +\item Just as C-language pointers map cleanly and efficiently into integers + today, pointers must similarly map cleanly, efficiently, and vastly more + robustly, into capabilities. + This should apply both to language-visible data and code pointers, but also + pointers used in implementing language features, such as references to + C++ vtables, return addresses, etc. + +\item Flexibility exists to employ only legacy integer pointers or + capabilities as dictated by software design and code generation, trading off + compatibility, protection, and performance -- while ensuring that security + properties are consistently enforced and can be reasoned about cleanly. + +\item When used to implement isolation and controlled communication in support + of compartmentalization, CHERI's communication primitives scale with the + actual data footprint (i.e., the working set of the application). + Among other things, this implies that communication should not require + memory copying costs that grow with data size, nor trigger TLB aliasing + that increases costs as the degree of sharing increases. + Our performance goal is to support at least two orders of magnitude more + active protection domains per core than current MMU-based systems support + (going from tens or hundreds to at least tens of thousands of domains), and + similarly to reduce effective domain-crossing cost by at least two orders of + magnitude. + +\item When sharing memory or object references between protection domains, + programmers should see a unified namespace connoting efficient and + comprehensible delegation. + +\item When implementing efficient protection-domain switching, the + architecture supports a broad range of software-defined policies, calling + conventions, and memory models. + Where possible, software TCB paths should be avoided -- but where necessary + for semantic flexibility, they should be supported safely and efficiently. + As with MMU-based protection-domain representation and crossing, CHERI + supports both synchronous and asynchronous communication patterns. + +\item Where possible, we make use of provable, deterministic protection, + avoiding probabilistic techniques or the use of architectural or + microarchitectural secrets subject to leaking or side-channel attacks. + For example, we avoid the use of cryptographic hashes, random address-space + bits, and version numbers that must be truncated to small numbers of bits + within a pointer or capability, instead making use of tagging. + This offers resistance to attacks at stastical scale (e.g., millions of + devices), and also protects software structures that might otherwise reuse + secrets allowing multiple attempts (e.g., forked daemon or zygote + processes). + Tags allow strong non-reinjection properties: pointers leaked via network + communications or IPC cannot be reinjected, despite having previously been + valid. + This in turn allows stronger temporal safety properties to be enforced by + software, due to having stronger guarantees. + Provability is an essential aspect to our work: CHERI's architectural + safety properties must be formally expressible, deterministically true, and + mechanically provable from that expression. + +\item More generally, we seek to exploit hardware performance gains wherever + possible: in eliminating repeated software-generated checks by providing + richer semantics, in providing stronger underlying atomicity for pointer + integrity protection that would be very difficult to provide on current + architectures, and in providing more scalable models for memory sharing + between mutually distrusting software components. + By making these operations more efficient, we encourage their more extensive + use. + +\end{enumerate} + +These and other design goals permeate CHERI's abstract architecture-neutral +design as well as its architecture-specific instantiations. + +\section{Capability-System Model} + +In CHERI, capabilities are unforgeable tokens of authority through which +programs access all memory and services within an address space. +Capabilities are a fundamental hardware type that may be held in registers +(where they can be inspected, manipulated, and dereferenced using capability +instructions), or in memory (where their integrity is protected). +They include an integer virtual address, bounds, permissions, and other +protective metadata including an object type and one-bit tag. + +\textit{Capability permissions} determine what operations (if any) are +available via the architecture. +Commonly used permissions include those authorizing memory loads, memory +stores, and instruction fetches. +Where permissions authorize memory access, \textit{capability bounds} limit +the range of addresses that may be accessed; for other permissions, bounds +constrain other forms of access (e.g., use of the object-type space). +Memory capabilities (those authorizing memory access) may be used to load +other capabilities into registers for use. +Capabilities may also be sealed in order to make their fields immutable and +the capability non-dereferenceable. + +While motivated by the goal of representing pointers (protected virtual +addresses), they are also able to protect non-pointer values. +For example, \textit{sealed capabilities} without memory-access permissions +may be used to represent references to protection domains that can be +transitioned to via software-defined object invocation. + +\textit{Unforgeability} is implemented by two means: tag bits and guarded +manipulation. +Each capability register (and each capability-aligned physical memory +location) is associated with a tag bit indicating that a capability is valid. +Attempts to directly overwrite a capability in memory using data (rather than +capability) stores automatically clears the tag bit. +When data is loaded into a register, its tag bit is also loaded; while data +without a valid tag can be loaded into a register, attempts to dereference or +invoke such a register will trigger an exception. + +\textit{Guarded manipulation} is enforced by virtue of the ISA: instructions +that manipulate capability register fields (e.g., base, offset, length, +permissions, type) are not able to increase the rights associated with a +capability. +Similarly, sealed capabilities can be unsealed only via the invocation +mechanism, or via the unseal instruction subject to similar monotonicity +rules. +This enforces encapsulation, and prevents unauthorized access to the internal +state of objects. + +Collectively, unforgeability and guarded manipulation ensure that +dereferenceable capabilities (those with their tag set) have \textit{valid +provenance}: they are derived only from other valid capabilities, and only +through valid manipulations. +All other capabilities will not have their tag set, hence cannot be +dereferenced. + +\textit{Intentionality} avoids the automatic selection of a capability from +among a set in order to locate rights to authorize a requested operation. +It is always clear for every instruction what capability will authorize its +action, +e.g., +whether +for the executing code capability (to authorize privileged ISA +operations such as MMU management), explicit operand capabilities (to query, +modify, or dereference), or implicit use of the Default Data Capability (e.g., +when constraining legacy load and store instructions). +There are no associative lookups of capabilities to select from among several +options, and instructions are always clearly defined as expecting an integer +or a tagged capability as an operand, failing if that expectation is not met. + +We anticipate that many languages will expose capabilities to the programmer +via pointers or references -- e.g., as qualified pointers in C, or mapped from +object references in Java. +Similarly, capabilities may be used to bridge communication between different +languages more safely -- for example, by imposing Java memory-protection and +security properties on native code compiled against the Java Native Interface +(JNI). +In general, we expect that languages will not expose registers directly for +management by programmers, instead using them for instruction operands and as +a cache of active values, as is the case for integer pointers today. +On the other hand, we expect that there will be some programmers using the +equivalent of assembly-language operations, and the CHERI compartmentalization +model does not place trust in compiler correctness for non-TCB code. + +\section{Architectural Capabilities} +\label{section:architectural-capabilities} + +\textit{CHERI capabilities} are an architectural data type, directly +implemented by the CPU hardware in a manner similar to integers or +floating-point values. +Capabilities may be held in registers or in tagged memory. +On RISC (``load-store'') architectures, CHERI-aware code can use new +capability instructions to inspect, manipulate, and dereference capabilities +held in registers. +On CISC architectures, direct use of capabilities in memory may also be +possible. +In-register modification of capability values is subject to guarded +manipulation (e.g., to enforce monotonicity), and dereference is subject to +appropriate checks (e.g., for a valid tag, sealing, appropriate permissions, +and suitable bounds). +In-memory modification of capability values is protected by tagged memory. + +\subsection{Address Size and Capability Size} + +Architectural capabilities are sized with respect to the address size of the +architecture. +As we define CHERI capability variants for both 32-bit architectures and +64-bit architectures, we parameterize the definitions in this chapter as +follows: + +\begin{description} +\item[XLEN] is the architectural address size in bits. + For 32-bit architectures, \xlen{} is 32. + For 64-bit architectures, \xlen{} is 64. + +\item[CLEN] is the architectural capability size in bits, which is 2$\times$ + the architectural address size (and does not include the tag bit). + For 32-bit architectures, \clen{} is 64. + For 64-bit architectures, \clen{} is 128. +\end{description} + +\subsection{Capability Contents} + +Capabilities contain a number of software-accessible architectural fields, +which may differ in content and size from the microarchitectural +implementation or that is apparent from its in-memory representation: + +\begin{itemize} +\item +Tag bit (``\ctag{}'', 1 bit ``out of band'' from addressable memory) +\item +Permissions mask (``\cperms{}'', parameterizable size) +\item +Software-defined permissions mask (``\cuperms{}'', parameterizable size) +\item +Flags (``\cflags{}'', parameterizable size) +\item +Object type (``\cotype{}'', 4 bits for 64-bit capabilities or 18 bits for + 128-bit capabilities) +\item +Offset (``\coffset{}'', \xlen{}) +\item +Base virtual address (``\cbase{}'', \xlen{}) +\item +Length in bytes (``\clength{}'', \xlen{}) +\end{itemize} + +\subsubsection{Tag Bit} + +The \ctag{} bit indicates whether an in-register capability or a +capability-sized, capability-aligned location in physical memory contains a +valid capability. +If \ctag{} is set, the capability is valid and can be dereferenced (subject to +other checks). +If \ctag{} is clear, the capability is invalid, and cannot be dereferenced. +If capabilities are held in dedicated registers, rather than also being used +for general-purpose integer values and operations, +those registers must still +have tag bits in order to allow untagged data to move through those registers +-- e.g., to implement capability-oblivious memory-copy and sort operations. +Section~\ref{sec:tagged-memory} describes the behavior of tagged memory. + +% \subsubsection{Sealed Bit} +% +% The \csealed{} flag indicates whether a capability is usable for +% general-purpose capability operations. +% If this flag is set, the capability is sealed, causing it to become +% non-dereferenceable (i.e., cannot be used for load, store, or instruction +% fetch) and immutable (i.e., whose fields cannot be manipulated). +% Capabilities are sealed with an object type (see +% Section~\ref{section:object-type}); the sealed bit may be removed using only +% the \insnref{CUnseal} or \insnref{Cinvoke} instructions (see +% Section~\ref{section:protection-domain-transition-with-cinvoke}). +% One potential application of sealed capabilities is for use as +% object-capability references -- i.e., as references to software-defined +% objects with architecturally enforced encapsulation. +% However, they are available to software for more general use in constructing +% architecturally protected references. + +\subsubsection{Permission Bits} +\label{sect:capability-permission-bits} + +The \cperms{} bit vector governs the architecturally defined permissions of +the capability including read, write, and execute +permissions.\footnote{Although these values are used in CHERI-MIPS and +CHERI-RISC-V, the specific integer constants -- and in some cases the named +permissions -- differ in Arm's Morello.} +Bits 0--11 of this field, which control use and propagation of the +capability, and also limit access to privileged instructions, are defined in +Table~\ref{table:capability-permission-bits}. +Permissions grant access only subject to constraints imposed by the current +architectural ring -- that is, they always restrict relative to the existing +architectural security model. +Permissions are also contingent on the capability \ctag{} bit being set, and +specific permissions may depend on the capability being sealed (or unsealed), or +bounds checks against \cbase{} and \clength{}, when used: + +\begin{table} +\begin{center} +\begin{tabular}{llcll} +\toprule +Bit & Name & Tag? & Seal? & Bounds? \\ +\midrule +0 & \cappermG & \checkmark & - & - \\ +1 & \cappermX & \checkmark & Unsealed & Address\\ +2 & \cappermL & \checkmark & Unsealed & Address\\ +3 & \cappermS & \checkmark & Unsealed & Address\\ +4 & \cappermLC & \checkmark & Unsealed & - \\ +5 & \cappermSC & \checkmark & Unsealed & - \\ +6 & \cappermSLC & \checkmark & Unsealed & - \\ +7 & \cappermSeal & \checkmark & Unsealed & Object Type \\ +8 & \cappermCInvoke & \checkmark & Sealed & - \\ +9 & \cappermUnseal & \checkmark & Unsealed & Object Type \\ +10 & \cappermASR & \checkmark & Unsealed & - \\ +11 & \cappermCid & \checkmark & Unsealed & CID \\ +\bottomrule +\end{tabular} +\end{center} +\caption{Architectural permission bits for the \cperms{} capability field, + along with checks usually used alongside that permission: \textit{Tag?} + Require a valid tag; \textit{Seal?} Require the capability to be sealed or + unsealed; \textit{Bounds?} Perform a bounds check authorizing access to + the listed namespace. + See the instruction-set reference for detailed per-instruction + requirements.} +\label{table:capability-permission-bits} +\end{table} + +\begin{description} +\item[\cappermG] Allow this capability to be stored via capabilities that do not themselves have \\ \cappermSLC set. + +\item[\cappermX] Allow this capability to be used in the \PCC{} register as a capability for the program counter, constraining control flow. + +\item[\cappermL] Allow this capability to be used to load untagged data; also requires \\ \cappermLC to permit loading a tagged value. + +\item[\cappermS] Allow this capability to be used to store untagged data; also requires \\ \cappermSC to permit storing a tagged value. + +\item[\cappermLC] Allow this capability to be used to load capabilities with valid tags; \cappermL is also required. + +\item[\cappermSC] Allow this capability to be used to store capabilities with valid tags; the permission \cappermS is also required. + +\item[\cappermSLC] Allow this capability to be used to store non-global capabilities; also requires \cappermS and \cappermSC. + +\item[\cappermSeal] Allow this capability to authorize the sealing of another capability with a \cotype{} equal to this capability's \cbase{} $+$ \coffset{}. + +\item[\cappermCInvoke] Allow this sealed capability to be used with \insnref{CInvoke}. + +\item[\cappermUnseal] Allow this capability to be used to unseal another capability with a \cotype{} equal to this capability's \cbase{} $+$ \coffset{}. + +\item[\cappermCid] Allow the architectural compartment ID to be set to this capability's \cbase{} $+$ \coffset{} using \insnref{CSetCID}. +\end{description} + +In general, permissions on a capability relate to its implicit or explicit +use in authorizing an operation that uses the capability -- e.g., in fetching +an instruction via \PCC{}, branching to a code capability, loading or storing +data via a capability, loading or storing a capability via a capability, +performing sealing or unsealing operations, or controlling capability +propagation. +In addition, a further \textit{privileged permission} controls access to +privileged aspects of the instruction set such as exception-handling, which +are key to the security of the model and yet do not fit the ``capability as an +operand'' model: + +\begin{description} +\item[\cappermASR*] Allows access to privileged processor + permitted by the architecture (e.g., by virtue of being in supervisor mode), + with architecture-specific implications. + This bit limits access to features such as MMU manipulation, interrupt + management, processor reset, and so on. + The operating system can remove this permission to implement constrained + compartments within the kernel. +\end{description} + +A richer conversion to a capability architecture might replace existing +privileged instructions (e.g., to flush the TLB) with new instructions that +accept an authorizing capability as an operand, and adopt a more granular +model for authorizing architectural privileges using capabilities than this +all-or-nothing approach. + +The \cappermSLC permission bit is used to limit +capability propagation via software-defined policies: local capabilities +(i.e., those without the \cappermG permission set) can be stored only via +capabilities that have \cappermSLC set. +Normally, this permission will be set only on capabilities that, themselves, +have the \cappermG bit cleared. +This allows higher-level, software-defined policies, such as ``Disallow storing stack references to heap memory'' or ``Disallow passing local capabilities via cross-domain procedure calls,'' to be implemented. +We anticipate both generalizing and extending this model in the future in +order to support more complex policies -- e.g., relating to the propagation of +garbage-collected pointers, or pointers to volatile vs. non-volatile memory. + +\subsubsection{Software-Defined Permission Bits} + +The \cuperms{} bit vector may be used by the kernel or application programs +for software-defined permissions. +They can be masked and retrieved using the same \insnref{CAndPerm} and +\insnref{CGetPerm} instructions that operate on hardware-defined +permissions. +We define 0 software-defined permission bits for 64-bit capabilities, and 4 +software-defined permission bits for 128-bit capabilities. + +Software-defined permission bits can be used in combination with existing +hardware-defined permissions (e.g., to annotate code or data capabilities +with further software-defined rights), or in isolation of them (with all +hardware-defined permissions cleared, giving the capability only +software-defined functionality). +For example, software-defined permissions on code capabilities could be +employed by a userspace runtime to allow the kernel to determine whether a +particular piece of user code is authorized to perform system calls. +Similarly, user permissions on sealed data capabilities might authorize use of +specific methods (or sets of methods) on object capabilities, allowing +different references to objects to authorize different software-defined +behaviors. +Capabilities with all hardware-defined permission bits cleared have only +software-defined interpretations, making them suitable for potential use as +unforgeable tokens of authority authorizing use of in-application or kernel +services. + +\subsubsection{Flags} +\label{sec:arch-flags} + +The \cflags{} field can be read with the \insnref{CGetFlags} instruction +and written with the \insnref{CSetFlags} instruction. + +There are no architecture-neutral flags currently defined, therefore the size and +interpretation of this field are entirely architecture specific. + +\subsubsection{Object Type} +\label{section:object-type} + +\begin{table} +\begin{center}\begin{tabular}{r|l} + \cotype{} value & Interpretation \\ + \hline\hline + $2^{\xlen{}} - 1$ & Unsealed capability \\ + \hline + $2^{\xlen{}} - 2$ & Sealed entry (``sentry'') capabilities; see \cref{sec:arch-sentry} \\ + \hline + $2^{\xlen{}} - 3$ & Reserved (experimental ``memory type tokens''; see \cref{app:exp:typetoken}) \\ + \hline + $2^{\xlen{}} - 4$ & Reserved (experimental ``indirect enter capabilities''; see \cref{app:exp:indsentry}) \\ + \hline + $2^{\xlen{}} - 5$ & Reserved \\ + through & \\ + $2^{\xlen{}} - 16$ & \\ + \hline + other & Capability sealed by \insnref{CSeal} \\ +\end{tabular}\end{center} +% +\caption{Object types and their architecture-specified roles.} +\label{tab:archotypes} +% +\end{table} + +The \cotype{} field is 4 bits for 64-bit capabilities, and 18 bits for 128-bit +capabilities. +The field indicates whether a capability is sealed and, if so, +what ``type'' it has; see \cref{tab:archotypes} for defined values. +CHERI uses multiple object types to allow software to create unforgeable +associations between sealed capabilities. +The implementation values in \cotype{} fields are translated to the abstract +space as if by sign extension. Attempts to seal capabilities to types that +cannot be expressed by the implementation will fail in an +implementation-specified way, but generally similarly to any other +representability failure. +% +If a capability is sealed, it becomes non-dereferenceable (i.e., cannot be used +for load, store, or instruction fetch) and immutable (i.e., whose fields cannot +be manipulated). Capability unsealing is mediated either by capabilities (via +the \insnref{CUnseal} instruction) or by control transfers (via +the \insnref{CInvoke} instruction, as in +\cref{section:protection-domain-transition-with-cinvoke}, or +\insnref{CJALR} instructions, as in \cref{sec:arch-sentry}). +% +One potential application of sealed capabilities is for use as +object-capability references -- i.e., as references to software-defined objects +with architecturally enforced encapsulation. However, they are available to +software for more general use in constructing architecturally protected +references. + +\pmnote{There is inconsistency in various places where a 18-bit + \cotype{} is supposed to hold a 64-bit value like $2^{64}-1$. I've + marked the places I've found; there might be others.} + +\subsubsection{Base} + +The \xlen{}-bit \cbase{} field is the base address of the segment described +by a capability. +The \cbase{} field is the \textit{lower bound} of the capability: +dereferencing an effective virtual address below \cbase{} will throw an +exception. +In the presence of compressed capabilities, not all possible \xlen{}-bit +values of +\cbase{} will be representable (see Section~\ref{compression}). + +\subsubsection{Offset} + +The \xlen{}-bit \coffset{} field holds a free-floating pointer that will be +added to the base when dereferencing a capability. +The value can float outside of the range described by the capability -- e.g., +as a result of using \insnref{CSetOffset} to set the offset to a negative +value, or to a value greater than \clength{} -- but an exception will be +thrown if a requested dereference is out of range. +A non-zero offset may be used when a language-level pointer refers to a +location within a memory allocation or data structure; for example, to point +into the middle of a string, or at a non-zero index within an array. +A non-zero offset may also be used when the lower bound of a memory allocation +is insufficiently aligned to permit precise description with the \cbase{} +field of a compressed capability (see Section~\ref{compression}). + +\subsubsection{Address} + +The address, or \ccursor{}, of a capability is the sum of its +\cbase{} and \coffset{} fields. +The components of the virtual address may be accessed separately (e.g., via +\insnref{CGetOffset}), or as a single combined entity (e.g., via +\insnref{CGetAddr} and \insnref{CSetAddr}) depending on the software +use case. +For example, an integer cast of a C-language pointer might return either the +offset or the virtual address, depending on the C-language interpretation +being used. + +\note{As presently defined, CGetAddr and CGetOffset appear not to carry out +bounds checks, which means that software really should get the length (and +base) and do the math as well if the bound(s) matter(s). Could there be +utility to additional instructions for checked access when the intent is to +extract only in-bound offsets and addresses? Or, to dodge the question +about what such a checked accessor returns when the cursor is out of bounds, +a CBTS/CBTU-like pair of tests for the cursor being in-bounds? While a +CIncOffset by zero would clear the tag of an out of bounds capability, this +seems too fragile, too prone to optimization, to depend on from C.}{nwf} + +\subsubsection{Length} + +The \xlen{}-bit \clength{} field is the length of the segment described by a +capability. +The sum of \cbase{} and \clength{} is the \textit{upper bound} of the +capability: accessing at or above \cbase{} $+$ \clength{} will throw an +exception. +In the presence of compressed capabilities, not all possible \xlen{}-bit +values of \clength{} will be representable (see Section~\ref{compression}). + +\subsection{Capability Values} + +\subsubsection{Pointer Values in Capabilities} + +In general, C and C++-language pointers are suitable to be represented as +memory capabilities (i.e., those that are unsealed and have a memory +interpretation by virtue of memory-related permissions). +This includes both data pointers, which may have enabled permissions that +include \cappermL, \cappermS, \cappermLC, and +\cappermSC, and code pointers, which may have enabled +permissions that include \cappermL, \cappermX, and +\cappermLC. +Other permissions, such as \cappermG or \cappermCInvoke, may also be present. +The following architectural values will normally be used: + +\begin{itemize} +\item The \ctag{} is set. +\item The capability is unsealed (has \cotype{} of $2^{\xlen{}}-1$). +\item \cperms{} contains a suitable combination of load, store, and + execute permissions, as well as other possible permissions. +\item \cbase{} will point to the bottom of the memory allocation, allowing for + suitable alignment if bounds compression is used. +\item \coffset{} will point within the memory allocation (but may point + outside in some circumstances). +\item The address will be equal to the integer value of the pointer. +\item \clength{} will be the length of the memory allocation, allowing for + suitable alignment if bounds compression is used. +\end{itemize} + +Code pointers will normally include \cappermL and \cappermLC +so that constant islands and global variables can be accessed via the code +segment. +Due to bounds compression, the memory allocation may require stronger than +word alignment or padding so as to ensure non-overlapping bounds with other +allocations. +Implied pointers in the run-time environment, originating in +compiler-generated code or the run-time linker, such as Program Linkage Table +(PLT) entries, Global Offset Table (GOT) entries, the Thread-Local Storage +(TLS) pointer, C++ v-table pointers, and return addresses, will typically have +similar values. +Note that the \cflags{} field may have an architecture-specific default value. + +\subsubsection{The NULL Capability} + +When representing C-language pointers as capabilities, it is important to have +a definition of NULL with as close-as-possible semantics to today's +definition that NULL has an integer value of 0. +We choose to define a NULL capability that has the following architecture +values set: + +\begin{itemize} +\item \ctag{} is cleared. +\item The capability is unsealed (has \cotype{} of $2^{\xlen{}}-1$). +\item \cperms{} is 0x0. +\item \cflags{} is 0x0. +\item \cbase{} is 0x0. +\item \coffset{} is 0x0. +\item By implication, the virtual address of the capability is 0x0. +\item \clength{} is the largest permitted length ($2^{\xlen{}}$). +\end{itemize} + +The NULL capability is used in several places in the architecture, including +being the value returned when \creg{0} is used as an operand to many (but not +all) instructions, when a 0 integer value is passed to \insnref{CToPTR}, +and when comparisons with NULL are performed by the \insnref{CBEZ} and +\insnref{CBNZ} instructions. + +\subsection{Integer Values in Capabilities} +\label{subsection:integer_values_in_capabilities} + +In the C language, the \ccode{intptr_t} type is intended to be an integer +type large enough to hold a pointer, and sees two common uses: an opaque field +that can hold either an integer or pointer type; or an integer type permitting +arithmetic and other integer operations on pointer values. +We find it convenient to store an integer value in a capability using the +following conventions: + +\begin{itemize} +\item \ctag{} is cleared. +\item The capability is unsealed (has \cotype{} of $2^{\xlen{}}-1$). +\item \cperms{} is 0x0. +\item \cflags{} is 0x0. +\item \cbase{} is 0x0. +\item \coffset{} is the integer value to be stored. +\item By implication, the virtual address of the capability is the integer + value to be stored. +\item \clength{} is the largest permitted length ($2^{\xlen{}}-1$). +\end{itemize} + +\subsection{General-Purpose Capability Registers} + +General-purpose capability registers are registers that are able to load, +store, inspect, +manipulate, and dereference capabilities while preserving their 1-bit tag and +full set of structured fields. +New capability-aware instructions (see +Section~\ref{sec:capability-aware-instructions}) allow use of new registers or +new fields added to existing registers, and via guarded manipulation must +implement properties such as tag preservation, monotonic transformation, and +so on. +Capability registers are tagged so that capability-oblivious operations -- +such as tag-preserving memory copies of regions containing both data and +capabilities -- can be performed, preserving both set and unset tag bits. +This means that all capability-aware instructions dereferencing a capability +must check for a valid tag, as capability registers may contain data values +that are not permitted to be dereferenced. + +Architectures may be extended with capability registers in two ways: first, by +introducing new architectural registers that supplement existing registers, or +second, by extending existing registers with new capability-register fields +that can be accessed through new instructions. +These two approaches may be combined in the same architecture, as +in CHERI-MIPS (see Chapter~\ref{chap:cheri-mips}), where we introduce +both a new capability register file supplementing the integer register file, +and also extend certain special registers, as described in +Section~\ref{section:special-capability-registers}, to become capability +registers -- such as the Program Counter (\PC{}) becoming the Program-Counter +Capability +(\PCC{}). + +An alternative approach would extend the existing general-purpose integer +register file to allow it to hold \xlen{}-sized integers and also capabilities, with +instructions selecting the desired semantics when utilizing a register. +We refer to this design as a \textit{merged register file}. +This is similar to extension of 32-bit registers to 64-bit registers, in which +32-bit load, store, and manipulation can take place despite the full register +size being large enough to hold a 64-bit value. +A similar set of constraints applies: when an integer is loaded into a +capability-width register, the tag bit and remainder of the non-integer data +bits in the register must be zeroed, in similar manner to the use of zero or +sign extension when loading a smaller integer into a larger integer register. +When a register containing a tagged capability is used as an input to an +integer arithmetic operation, we recommend that the virtual address of a +capability be used as the integer value used for input. + +When integer and capability instructions share a common underlying register +file, it is essential that intentionality be maintained: instructions +must not select between integer and capability interpretations based on the +tag value. +Instead, instructions must specifically interpret input and output registers +as integers or as capabilities. +If a capability dereference is expected, an exception must be thrown if the +input register does not contain a valid tag. +If an integer dereference is to be performed, only the integer portion of the +capability register will be used (per above, the virtual address of the +capability), and it will be indirected through an appropriate implied +capability such as the Program-Counter Capability (\PCC{}) or Default Data +Capability (\DDC{}). + +When utilizing a merged register file, not all +integer registers may be extended to hold capabilities. +A tradeoff exists around the extension of existing well-supported ABIs, such +as the calling convention, vs. the impact of register-file growth and opcode +utilization. +Larger numbers of capability registers will increase the memory footprint of +context switching and the cost of stack spillage (where a callee cannot know +whether a register requires saving as a full capability or whether integer +width would be sufficient). +Similarly, larger numbers of available capability registers increase the +opcode footprint of capability-relative instructions. +While this opcode space is no greater than for integer-relative instructions, +in some architectures (e.g., ARMv8-A), opcode space is at a substantial premium, +and adding new capability variants of all load/store/jump instructions will +over-consume or exhaust the space. +Reducing the number of capability registers comes at other costs, such as +potentially disrupting current ABI design choices, and increasing register +pressure for pointer-intensive workloads. +Here, a variety of design points are available, but one option would be to +limit capabilities to a subset of the full register file, allowing a smaller +number of bits to name the available capability registers. +This pressure is especially acute in variable-size instruction sets (e.g., +with the RISC-V compressed instruction set). +Other options to avoid this pressure include the introduction of new opcode +modes in which existing opcodes can be reused to refer to capabilities instead +of integers, at a cost to binary compatibility. +The most straightforward choice, where opcode space is plentiful with respect +to the vocabulary of load-store instructions, is to allow all existing +general-purpose integer registers to hold capabilities. + +Microarchitectural and in-memory representations of capabilities may differ +substantially from the architectural representation in terms of size and +contents, but these differences will not be exposed via instructions operating +on capability-register fields. +See Section~\ref{compression} for a discussion of capability compression, +used to avoid storing a minimum of 3$\times$ \xlen{} bits in each capability. + +\subsubsection{Register-File Implications for Integer Values in Capabilities} + +The convention for storing integers in capabilities, described in +Section~\ref{subsection:integer_values_in_capabilities}, is not currently +defined in architecture when using a split register file. +However, it is convenient that: + +\begin{itemize} +\item Adding an integer value to the offset of a NULL capability (e.g., using + \insnref{CIncOffset}) gives a capability that follows these + conventions. +\item Maximal bounds allow the virtual address to take on any value without + risking a bounds representability failure during arithmetic -- in contrast + to using a maximum length of 0, which might otherwise seem intuitive. +\end{itemize} + +With a merged register file, this is instead an architectural definition, and +is used when an integer value is moved or loaded into a capability register. +This might occur during an ordinary data load into a register, or as a result +of (for example) an integer arithmetic operation writing back to a register. +Sign extension will occur as normal for the architecture to fill the offset +field, with remaining fields being set to the above values. + +\subsection{Special Capability Registers} +\label{section:special-capability-registers} + +In addition to the general-purpose capability registers available for use via +capability load, store, jump, query, and manipulation instructions, there are +also a set of \textit{Special Capability Registers} (SCRs). +These capability registers are accessed via special get and set instructions +(and, in some architectures, swap or direct manipulation), and serve specific +architectural functions. +Access to special capability registers is controlled on a case-by-case basis +(\insnref{CReadHwr} and \insnref{CWriteHwr}), but +may include universal read and write access, read and write access only when +holding \cappermASR, or based on execution ring or +exception-handling state. +The specific registers vary by underlying architecture, but will include the +following (or natural variations of them): + +\begin{description} +\item[Program Counter Capability (\PCC{})] extends the existing Program + Counter (\PC{}) to be a full capability, imposing validity, permission, + bounds, and other checks on instruction fetch. + +\item[Default Data Capability (\DDC{})] indirects legacy non-capability loads + and stores, controlling and relocating data accesses to memory. + +\item[Exception Program Counter Capability (\EPCC{})] Just as conventional + architectures save the \PC{} in \EPC{} following an exception, and restore + \EPC{} into \PC{} on exception return, \EPCC{} extends \EPC{} to hold a + copy of the full saved \PCC{}. + +\item[Kernel Code Capability (\KCC{})] When an exception is taken, the value + in \PCC{} is replaced with the value in \KCC{}, installing a suitable + execution and security context for the exception handler. + Note: A better name for this capability might be the Exception Code + Capability. + +\item[Kernel Data Capability (\KDC{})] When an exception is taken, \KDC{} + holds a suitable data capability for use by the exception handler. + Note: A better name for this capability might be the Exception Data + Capability. + +\item[User Thread-Local Storage (\CULR{})] A capability extended + version of a Thread-Local Storage (TLS) register, available to any executing + code. + +\item[Privileged Thread-Local Storage (\CPLR{})] A capability register + intended to be used only by privileged code within a ring to implement + Thread-Local Storage (TLS). +\end{description} + +Although these capability special registers may be viewed as extensions to +existing special registers (e.g., \EPC{}), CHERI introduces new +capability-based instructions to get and set their values, rather than +conflating them with existing integer-based special-register instructions in +the architecture ISA, in order to ensure intentional use in the presence of a +merged register file. + +Where existing special registers, such as the Program Counter (\PC{}) or +Exception Program Counter (\EPC{}), are extended to become capabilities, the +semantics of accessing the integer interpretation must be determined with +care. +Unlike with the general-purpose integer register file, it may be desirable for +reasons of compatibility to modify the capability while retaining its tag +and other metadata (such as bounds and permissions) without modification -- +subject to maintaining monotonicity. +For example, when modifying \PC{}, it is desirable to leave other fields (such +as bounds of \PCC{}) unmodified, and further to have integer accesses be +performed on \coffset{} rather than on the capability virtual address, so that +capability-unaware code can jump within its code segment without experiencing +a tag violation or being exposed to absolute virtual addresses. +%%%% SUCH AS BOUNDS was ambiguous, in a sentence with TOO MANY COMMAS, +%%%% and I may have miscorrected it. PLEASE VET MY SECOND TRY. +A similar argument applies to \EPC{}, where capability-unaware +exception-handling code may be able to continue to operate. +These design choices allow accesses to be relocated relative to each of +these capabilities.\footnote{This is a design point on which we have had +considerable discussion, and for which other approaches would also be +reasonable. +For example, a virtual-address interpretation of \PC{} or \EPC{} would also be +meaningful, but would place greater constraints on how capabilities were +used to constrain access by unmodified software.} +In the case of \EPC{}, it is desirable that attempted writes be considered +equivalent to \insnref{CSetOffset}, but with failures -- such as might +occur if a sealed capability has been placed in \EPCC{} -- leading to the tag +being cleared rather than an exception being through in what is likely to +already be an exception-handling context. + +\section{Capabilities in Memory} + +Maintaining the integrity and provenance validity of capabilities stored to, +and later read from, memory, is an essential feature of the CHERI +architecture. +Capabilities may be stored to memory in a broad variety of circumstances, +including, when language-level pointers are implemented using capabilities, +operating-system context switching, stack spills of capability registers, +stack storage for local pointer variables, pushing return capabilities to the +stack on function call, the capabilities held in Global Offset Table (GOT) +structures to reach global variables, global variables themselves holding +types implemented via capabilities, Procedure Linkage Table (PLT) entries +holding code capabilities that can be jumped to, and so on. +As tagged memory maintains tag bits at capability-sized, capability-aligned +intervals, stores of capabilities to memory will retain their tags only if +at suitable alignment. +This allows capabilities to be held at any suitably aligned memory location, +interleaved arbitrarily with other data -- such as is commonly the case with +pointers and other data today. + +\subsection{In-Memory Representation} + +As implemented in CHERI-MIPS and CHERI-RISC-V, all in-memory capability bits +are directly addressable via ordinary data accesses (e.g., byte loads) except +for the tag bit, which is stored ``out-of-band'' as a 65th or 129th bit. +The in-memory capability representation will typically not be a direct mapping +of architectural capability fields into memory, as fields may be stored as +partially computed values to improve performance (e.g., storing a virtual +address rather than base and offset), to reduce size (e.g., through bounds +compression), or to utilize multiple formats (e.g., for unsealed vs.\@ sealed +capabilities). +Given the prior definitions, we impose several constraints on the in-memory +representation: + +\begin{description} +\item[NULL has an all zeroes in-memory representation, with cleared tag.] + This definition allows zero-filled memory to be interpreted as NULL-filled + memory when loaded as a capability, providing greater consistency with the + C-language expectations for NULL pointers. + +\item[The bottom \xlen{} bits of a capability hold its address value.] + Supporting casts between a capability and an ordinary integer type sized to + correspond to the size of a virtual address has significant utility in + practical C code. +\end{description} + +The CHERI Concentrate compression format used for both 64-bit and 128-bit +capabilities is described in Section~\ref{compression}. +These formats vary in terms of the number of permission bits they offer, and +also bounds precision effects stemming from capability compression. Concrete +architectures may additionally allocate bits for the \cflags{} field. +\pdrnote{Do we want to somehow specify the in-memory representation of \cflags{}? +It seems hard to do this in an arch-neutral manner.} + +Software authors are discouraged from directly interpreting the in-memory +capability representation to improve the chances of software portability +(e.g., across architectures) and forward compatibility (e.g., with respect to +newly added permissions or other changes in field behavior). +This also allows multi-endian architectures or heterogeneous designs to utilize +a single endianness for in-memory capability storage (e.g., little endian) to +avoid ambiguities in which the same in-memory bit pattern might otherwise +describe two different sets of rights depending on where it is loaded and +interpreted. +This is also important given the desire to be able to retrieve the virtual +address or integer value of an in-memory capability by loading from the bottom +\xlen{} bits of the capability. + +Despite the software benefits from avoiding encoding the in-memory capability +representation, it is important that the in-memory representation be +considered architectural (i.e., having a defined and externally consistent +representation) to better support systems software functions such as swap, +core dumps, debuggers, virtual-machine migration, and efficient run-time +linking, which may embed that representation within file formats or network +protocols. + +\subsection{Tagged Memory} +\label{sec:tagged-memory} + +CHERI relies on tagged physical memory: the association of a 1-bit {\em tag} +with each capability-sized, capability-aligned location in physical memory. +Associating tags with physical memory ensures that if memory is mapped at +multiple virtual addresses, the same tags will be loaded and stored regardless +of the virtual address through which it is accessed. +Tags must be atomically bound to the data they protect. +As a result, it is expected that tags will be cached with the memory they describe within the cache hierarchy. + +When a capability-sized value in a capability register is written to a +capability-aligned area of memory using a capability store instruction, and +the capability via which the store takes place has suitable permissions, the +tag bit on the capability register will be stored atomically in memory with +the capability value. +Other stores of untagged capability values or other types (e.g., bytes, half +words, words, floats, doubles, and double words) across one or more +capability-aligned locations in memory will atomically clear the corresponding +tag bits for that memory. + +When a capability-sized value is loaded into a capability register from a +capability-aligned location in memory using a capability load instruction, and +the capability via which the load takes place has suitable permissions, the +tag associated with that memory is loaded atomically into the register along +with the capability value. +Otherwise, loads will clear the capability register tag bit. + +Strong atomicity properties are required such that it is not possible to +partially overwrite a capability value in memory while retaining the tag, or +partially load a capability and have the tag bit set. +These strong atomicity properties ensure that tag bits are set only on +capability values that have valid provenance -- i.e., that have not been +corrupted due to data stores into their contents, or undergone non-monotonic +transformations. +Our use of atomicity, in this context, has primarily to do with the visibility +of partial or interleaved results (which must not occur for capability stores +or tag clearing during data overwrite, or there is a risk that corrupted +capabilities might be dereferenceable), rather than ordering or visibility +progress guarantees (where we accept the memory model of the host +architecture). +This provides a set of properties that falls out naturally from current +microarchitectures and coherent memory-subsystem designs: atomicity is with +respect only to lines in the local cache, and not global state. + +\subsection{Compressed Capabilities} +\label{compression} + +In the abstract, full precision capabilities (i.e., those containing all of +the architectural capability fields at full width in their in-memory +representation) offer higher levels of software compatibility, but at a cost: +quadrupling the memory size of pointers implemented using capabilities. +This has significant software and micro-architectural costs to cache +footprint, memory bandwidth, and also in terms of the widths of memory paths +in the design. +However, CHERI is designed to be largely agnostic to the in-memory +representation, permitting alternative ``compressed'' representations while +retaining largely compatible software behavior. +Compression is possible because the base, length, and pointer values in +capabilities are frequently redundant. For example the pointer is often +within bounds and the length small, so the most significant bits of the pointer, +base and upper bound are likely to be the same. +This can be exploited by increasing +the alignment requirements on bounds associated with a pointer (while +retaining full precision for the pointer itself) and encoding the bounds relative +to the pointer with limited precision. +Space can further be recovered by reducing the number of permission and reserved bits. + +Using this approach, it is possible to usefully represent capabilities via a +compressed 128-bit in-memory representation, while retaining a 64-bit +architectural view of their fields. +Compression results in a loss of precision, exposed as a requirement for stronger +bounds alignment, for larger memory allocations. +Because of the representation, we are able to vary the +requirement for alignment based on the size of the allocation, and for small +allocations ($< 4$ KiB), impose no additional alignment requirements. +The design retains full monotonicity: no setting of bounds or adjustment of +the pointer value can cause bounds to increase, granting further rights -- but +care must be taken to ensure that intended reductions in rights occur where +desired. +Some manipulations of pointers could lead to unrepresentable bounds (as the +bounds are no longer redundant to content in the pointer): in this case, which +occurs when pointers are moved substantially out of bounds, the tag will be +cleared preventing further dereferencing. + +For bounds imposed by memory allocators, this is not a substantial cost: +heap, stack, and OS allocators already impose alignment in order to achieve +natural word, pointer, page, or superpage alignment in order to allow fields +to be accessed and efficient utilization of virtual-memory features in the +architecture. +For software authors wishing to impose narrower bounds on arbitrary subsets of +larger structures, the precision effects can become visible: it is no longer +possible to arbitrarily subset objects over the $4$ KiB threshold without +alignment adjustments to bounds. +This might occur, for example, if a programmer explicitly requested small and +unaligned bounds within a much larger aligned allocation -- such as might be +the case for video frame data within a $1$ GiB memory mapping. +In such cases, care must be taken to ensure that this cannot lead to buffer +overflows with potential security consequences. Alignment +requirements are further explored in \cref{sec:ccalignment} and \cref{sec:cheri-128-alignment}. + +Different representations might be used for unsealed data capabilities versus +sealed capabilities used for object-capability invocation. +Data capabilities experience very high levels of precision intended to support +string subsetting operations on the stack, in-memory protocol parsing, and +image processing. +Sealed capabilities require additional fields, such as the object type and +further permissions, but because they are unused by current software, and +represent coarser-grained uses of memory, greater alignment can be enforced in +order to recover space for these fields. +Even stronger alignment requirements could be enforced for the default data +capability in order to avoid further arithmetic addition in the ordinary RISC +load and store paths, where a bitwise or, rather than addition, is possible +due to zeroed lower bits in strongly aligned bounds. + +CHERI ISAv8 specifies a single compression scheme for capabilities, +CHERI Concentrate.\footnote{CHERI-128 (\cref{app:cheri-128}), our previous +compression format, is now deprecated.} + +\subsection{CHERI Concentrate Compression} +\label{subsec:cheri-concentrate} + +In this section, we describe how CHERI Concentrate compresses the bounds used +in 128-bit capabilities with 64-bit architectural addresses.\footnote{A +variant of CHERI Concentrate is used in Arm Morello, but with different +precision constants and a slightly different encoding format.} + +\begin{figure} + +\begin{bytefield}[bitwidth=\linewidth/64]{64} +\bitheader[endianness=big]{0,63} \\ +\bitbox{16}{$p$'16} & \bitbox{3}{\color{lightgray}\rule{\width}{\height}} & \bitbox{15}{otype'18} + & \bitbox{2}{$I_E$} & + \bitbox{9}{$T[11:3]$} & \bitbox{4}{$T_\text{E}$'3} + \bitbox{11}{$B[13:3]$} & \bitbox{4}{$B_\text{E}$'3} \\ +\bitbox[lrb]{64}{$a$'64} +\end{bytefield} + +\begin{minipage}{\linewidth} +\begin{center} +\begin{tabular}{ccc} +\\ +$p$: permissions & otype: object type & $a$: pointer address\\ +\end{tabular} +\end{center} +\end{minipage} + +\vspace{1em} + +\begin{center} +\begin{tabular}{r c l | r c l} +If $I_E=0$: & & & If $I_E=1$: & & \\ +$E$ &=& $0$ & $E$ &=& $\{T_\text{E},B_\text{E}\}$ \\ +$T[2:0]$ &=& $T_\text{E}$ & $T[2:0]$ &=& $0$ \\ +$B[2:0]$ &=& $B_\text{E}$ & $B[2:0]$ &=& $0$ \\ +$L_\text{carry\_out}$ &=& $ \begin{cases} + 1,& \text{if } T[11:0] < B[11:0] \\ + 0,& \text{otherwise} +\end{cases} $ & + +$L_\text{carry\_out}$ &=& $ \begin{cases} + 1,& \text{if } T[11:3] < B[11:3] \\ + 0,& \text{otherwise} + \end{cases} $ \\ + +$L_\text{msb}$ &=& $0$ & $L_\text{msb}$ &=& $1$ \\ +\end{tabular} +\end{center} + +Reconstituting the top two bits of T: +\begin{center} +$T[13:12] $=$ B[13:12] + L_\text{carry\_out} + L_\text{msb}$ +\end{center} + +Decoding the bounds: +\begin{center} +% spread out the table a bit otherwise it is too tight for maths +{ +\renewcommand{\arraystretch}{1.5} +\begin{tabular}{r|c|c|c|} +\cline{2-4} +address, $a =$ & $a_\text{top} = a[63:E+14]$ & $a_\text{mid} = a[E+13:E]$ & $a_\text{low} = a[E-1:0]$ \\ \cline{2-4} +top, $t =$ & $a_\text{top}+c_\text{t}$ & $T[13:0]$ & $0$'$E$ \\ \cline{2-4} +base, $b =$ & $a_\text{top}+c_\text{b}$ & $B[13:0]$ & $0$'$E$ \\ \cline{2-4} +\end{tabular} +} +\end{center} + +To calculate corrections $c_\text{t}$ and $c_\text{b}$: + +\begin{center} +\begin{tabular}{r c l} + $A_3$ &=& $a[E+13:E+11]$ \\ + $B_3$ &=& $B[13:11]$ \\ + $T_3$ &=& $T[13:11]$ \\ + $R$ &=& $B_3 - 1$ \\ +\end{tabular} +\end{center} + +\begin{center} +\begin{tabular}{@{}ccr@{}p{1em}@{}ccr@{}} +\cmidrule[\heavyrulewidth]{1-3}\cmidrule[\heavyrulewidth]{5-7} +$A_3 1))\ \algorithmicthen\ t[64] = !t[64]\] +That is, if the decoded length of the capability is larger than $E$ allows, invert the most significant bit of $t$. + +\subsubsection{CHERI Concentrate Encoding (Set Bounds)} +\label{sec:cheri-concentrate-encoding-set-bounds} + +To encode a capability with requested base, $b$, length, $l$, and top, $t = b + l$, using this encoding we must first determine $E$ by finding the most significant set bit of $l$. We select an $E$ that aligns $T[12]$ with the most significant set bit of $l$ as required for the top two bits of $T$ to be inferred correctly when decoded: +\[ +E = 52 - \text{CountLeadingZeros}(l[64:13]) +\] +Note that $l$ is a 65-bit value allowing the maximum possible length of $2^{64}$ to be encoded with $E=52$, $T=2^{12}$ and $B=0$. We exclude the lower 12 bits of $l$ because lengths less than this are encoded with $E = 0$ and $I_E$ set depending on the value of $l[12]$ ($L_{msb}$): +\[ +I_E = +\begin{cases} +0,\text{ if }E=0\text{ and }l[12] = 0 \\ +1,\text{ otherwise} +\end{cases} +\] +The values of $B$ and $T$ are formed by extracting the relevant bits from $b$ and $t$. For $I_E = 0$ this means: +\[ +B = b[13:0] \\ +T = t[11:0] +\] +With $I_E = 1$, we discard the lower bits and also lose three bits of each to store the exponent: +\[ +B = b[E+13:E+3] \\ +T = t[E+11:E+3] +\] +If in truncating $t$ we have rounded it down (i.e., if there were any set bits in $t[E+2:0]$) then we must increment $T$ by one to ensures that the encoded region includes the requested top as required by \insnref{CSetBounds}. +Rounding up $t$ to a $2^{E+3}$ aligned value may increase the length, and therefore might cause $L_{msb}$ to increase by one, therefore mandating that the $E$ of the resulting capability also increase so that $L_{msb}$ lands at exactly $E+12$ to ensure correct decoding. +Selecting a new $E$ forces a fresh selection of $T$ and $B$, but is certain not to overflow again. + +\subsubsection{CHERI Concentrate Alignment Requirements} +\label{sec:ccalignment} +For a requested base and top to be exactly representable the CHERI concentrate format may require additional alignment requirements: +\begin{itemize} +\item + For allocations with $I_E = 0$ (i.e. lengths less than $4$ kiB for $MW = 14$) there is no specific alignment requirement. +\item + For larger allocations the base and top must be aligned to $2^{E+3}$ byte boundaries (i.e. the $E + 3$ least significant bits are zero) where $E$ is determined from the length, $l$, by $E = 52 - \text{CountLeadingZeros}(l[64:13])$ +\item + No additional alignment requirements are currently placed on sealed capabilities or on \DDC{}. +\end{itemize} +Note that there is a jump in required alignment from 1-byte to 8-bytes at the transition between $I_E = 0$ and $I_E = 1$ caused by using the lower 3 bits of $T$ and $B$ to store the exponent. + +\subsubsection{CHERI Concentrate Fast Representable Limit Checking} +\label{sec:cheri-concentrate-fast-representable-limit-checking} +% +% This text pulled from the CHERI Concentrate paper, section 6.3, but 8/9-bit +% values converted to 13/14-bit values. +% + +Pointer arithmetic is typically performed using addition, and does not raise an exception. +If we wish to preserve these semantics for capabilities, capability pointer addition +must fit comfortably within the delay of simple arithmetic in the pipeline, and should not introduce the possibility of an exception. +For CC, as with Low-fat, typical pointer addition requires adding only an offset to the pointer address, leaving the rest of the capability fields unchanged. +However, it is possible that the address could pass either the upper or the lower limits of the representable space, beyond which the original bounds can no longer be reconstituted. +In this case, CHERI Concentrate clears the tag of the resulting capability to maintain memory safety, preventing an illegal reference to memory from being forged. +This check against the representable limit, $R$, has been designed to be much faster than a precise bounds check, thereby eliminating the costly measures the Low-fat design required to achieve reasonable performance. +%While we could push the check to the exception path, exceptions +%on arithmetic instructions prevent certain reorderings in a complex pipeline +%and are avoided in modern RISC architectures. + +To ensure that the critical path is not unduly lengthened, CHERI Concentrate verifies that an increment $i$ will not compromise the encoding by inspecting only $i$ and the original +address field. We first ascertain if +$i$ is \emph{inRange}, and then if it is \emph{inLimit}. +The \emph{inRange} test determines whether the magnitude of $i$ is greater than that of the size of the representable space, $s$, +which would certainly take the address out of representable limits: +\[ inRange = -s < i < s\] +The \emph{inLimit} test assumes the success of the \emph{inRange} test, and determines +whether the update to $A_\text{mid}$ could take it beyond the representable limit, outside the representable space: +\[ + inLimit=\begin{cases} + I_\text{mid} < (R - A_\text{mid} - 1),& \text{if } i \geqslant 0 \\ + I_\text{mid} \geqslant (R - A_\text{mid}) \text{~and~} R \neq A_\text{mid},& \text{if } i < 0 + \end{cases} +\] +The \emph{inRange} test reduces to a test that all the bits of $I_\text{top}$ ($i[63:E+14]$) are the same. +The \emph{inLimit} test needs only 14-bit fields ($I_\text{mid}=i[E+13,E]$) and the sign of $i$. + +The $I_\text{mid}$ and $A_\text{mid}$ used in the \emph{inLimit} test do not include the lower bits +of $i$ and $a$, potentially ignoring a carry in from the lower bits, presenting an \emph{imprecision hazard}. +We solve this by conservatively subtracting one from the representable limit +when we are incrementing upwards, and by not allowing any subtraction when $A_\text{mid}$ is equal to $R$. +%These are simplified to a single comparison and two equivalence checks in our +%implementation. +%\begin{align*} +% &inLimit=\begin{cases} +% \neg{GT} \text{~and~} I_\text{mid} \neq (R - 1),& \text{if } i \geqslant 0 \\ +% GT \text{~and~} R \neq A_\text{mid},& \text{if } i < 0 \\ +% \end{cases}\\ +% &\text{where } GT = I_\text{mid} \geqslant (R - A_\text{mid}) +%\end{align*} + +One final test is required to ensure that if $E \geqslant 50$, any increment is representable. +(If $E = 50$, the representable space, $s$, encompases the entire address space.) +This handles a number of corner cases related to $T$, $B$, and $A_\text{mid}$ describing +bits beyond the top of a virtual address. +Our final fast \emph{representability} check composes these three tests: +\[ representable = (inRange \text{~and~} inLimit) \text{~or~} (E \geqslant 50)\] + +To summarize, the representability check depends only on four 14-bit fields, $T$, $B$, $A_\text{mid}$, +and $I_\text{mid}$, and the sign of $i$. +Only $I_\text{mid}$ must be extracted during execute, as $A_\text{mid}$ is cached +in our register file. +%This operation is simpler than reconstructing even one full bound, as +%demonstrated in Section~\ref{sec:eval:microarch}. +This fast representability check allows us to perform pointer arithmetic on compressed capabilities directly, avoiding decompressing capabilities in the register file that introduces both a dramatically enlarged register file and substantial load-to-use delay. + +\subsection{Capability Address and Length Rounding Instructions} +\label{sec:capability-address-and-length-rounding} + +Capability compression requires stronger alignment as allocation sizes +increase. +For infrequent allocations of large memory mappings, the software cost of +calculating suitable alignment is small. +However, stack allocations occur frequently and have less tolerance for +arithmetic overheads. +Further, it may be desirable for an architecture to support a range of +compression parameters -- for example, the bits invested in exponents, top, +and bottom fields. +In this case, having the architecture calculate requirements based on its +specific parametrization would be beneficial. +We propose two new instructions that allow the architecture to provide +information to memory allocators regarding precision effects: + +\begin{description} +\item[CRepresentableAlignmentMask (CRAM)] \insnref{CRAM} accepts a proposed + bounds length, and returns a mask suitable for use in aligning down the + address of an allocation. + +\item[CRoundRepresentableLength (CRRL)] \insnref{CRRL} accepts a proposed + bounds length, and returns a rounded-up size that will be accepted by + \insnref{CSetBoundsExact} without throwing an exception. +\end{description} + +Collectively, these instructions can be used to efficiently calculate +suitable base and length alignment, to permit exception-free bounds setting +using \insnref{CSetBoundsExact}. +They are intended to be well suited for use with dynamic stack allocation -- +e.g., using \ccode{alloca}, but also other types of allocation. + +\subsection{32-bit Modes on 64-bit Architectures} + +We currently consider 32-bit execution modes on 64-bit processors to be legacy +compatibility modes, and hence do not define capability instruction-set +extensions for those modes. +The essential design goal is therefore to maintain CHERI's security properties +while enabling the execution of 32-bit capability-unaware code. + +Our recommendation is that capability-aware instructions be inaccessible in +32-bit modes, and that it be impossible for executing code to introduce +capability values that violate provenance validity and monotonicity +properties. +Any writes of non-capability values into capability-extended general-purpose +registers be treated in a similar manner to integer stores into those +registers in the capability-aware execution environment: they should clear the +remainder of the register including the tag bit. +Writes of integer values into capability-extended special-purpose registers +will need similar handling to 64-bit writes: in some cases they should clear +the tag, and in other cases they should modify the offset being accessed, in +a manner similar to changes to \PC{}, and so on. + +While this appear to be a coherent design direction, we have not validated +this approach in architecture. + +\section{Capability State on CPU Reset} +\label{sec:capability-state-on-cpu-reset} + +Although the architecture-neutral description of CHERI does not define a +specific set of capability registers (or capability extensions to existing +registers), there are architecture-neutral invariants that must be maintained +from the time of processor reset. +An initial set of strong \textit{root capabilities} must be available from +inception for use by software. +Most critically, the \textit{program-counter capability} must authorize the +execution of code following reset, and will typically cover the entire virtual +address space. +Similarly, at least one suitable root \textit{data capability} is necessary to +authorize access for data loads and stores; this will typically also cover the +entire virtual address space. + +An important design question is whether multiple roots are present, and if so, +whether they define disjoint trees of potential capabilities. +For example, the initial program-counter capability might grant load and +execute permissions but not store permission; similarly, an initial data +capability might grant load and store permissions but not execute permissions. +Due to monotonicity rules, this would prevent the later creation of any +capability holding both store and execute permissions (``W\^{}X''). +Similarly, it is easy to imagine using additional independent capability roots +for orthogonal architectural rights, such as sealing and unsealing permission +vs.\@ memory access, which utilize independent namespaces (object types vs.\@ +virtual addresses). Additional discussion may be found in +\cref{app:exp:compressperm}. + +In general, we have taken the view that initial architectural root +capabilities should hold all permissions, both architecture-defined and +software-defined, allowing software the flexibility to implement any suitable +models. +This impacts higher-level software behavior substantially: for example, +certain current POSIX APIs (e.g., \ccode{mmap()} combined with +\ccode{mprotect()}) assume that decisions about load, store, and execute +combinations can be made dynamically, and that it is possible to have pointers +that hold all three permissions. + +Depending on compatibility and security goals, software might choose to expose +independent roots in its own structure -- e.g., by not granting sealing +permission to user code using code or data capabilities, instead returning +a specific sealing root capability via a separate system call, allowing only +certain object types to be used directly by userspace. +The main downsides to this view are that the architecture itself does not +directly embody invariants such as W\^{}X, and that this also prevents use of +different formats for disjoint provenance trees of capabilities with orthogonal +functions -- e.g., the use of different formats for memory-access vs.\@ sealing +capabilities. +We choose to accept these costs in return for a more flexible software model +in which all root capabilities at processor reset hold all permissions. + +\subsection{Capability Registers on Reset} + +When the CPU is hard reset, all capability registers intended to act as roots +will be initialized to the following values: + +\begin{itemize} +\item +The \ctag{} bit is set. +\item +\coffset{} = 0, except for the program-counter capability, which will have its +\coffset{} initialized to an appropriate boot vector address. +Other architecture-specific capability registers may have other initial values +-- e.g., as relates to exception vectors. +\item +\cbase{} = 0 +\item +\clength{} = $2^{\xlen{}}$. +\item +\cotype{} = $2^{\xlen{}}-1$ (truncated as required by the implementation's encoding). +\item +All available permission bits are set; other bits will be returned as zero +architecturally. +% \nwfnote{Bits 8 and 9 are now taken, no longer reserved, yes?} +% Permission bits 8 and 9 are currently reserved for future use; these are +% included in the the 31 (or 15) permission bits that are set on reset). +\item +Concrete architectures specify the reset value of \cflags{} for root capabilities. +\item +All unused bits are cleared. +\end{itemize} + +\noindent +If the architecture-specific approach is to extend existing integer registers +to also hold tagged capabilities, then those registers may instead be +initialized to hold untagged values: + +\begin{itemize} +\item +The \ctag{} bit is unset. +\item +\coffset{} = 0 (or some other value appropriate to the register). +\item +\cbase{} = 0. +\item +\clength{} = $2^{\xlen{}}$. +\item +\cotype{} = $2^{\xlen{}}-1$ (truncated as required by the implementation's encoding). +\item +All available permission bits are unset. +\item +\cflags{} = 0x0. +\item +All unused bits are cleared. +\end{itemize} + +\subsection{Tagged Memory on Reset} + +In an ideal world, all tags in memory are cleared on CPU reset, as this avoids +the unpredictable introduction of additional capability roots. +However, this is not straightforward to offer architecturally or +microarchitecturally. +We instead rely on firmware or software supervisors to ensure that pages +placed into use, especially with untrustworthy code, have been properly +cleared. +While this property is often already enforced by real-world hardware and +systems -- whether due to Error-Correcting Codes +(ECC),\footnote{To avoid any potential confusion, we note that ECC is also widely used for Elliptic-Curve Cryptography.} or because of page zeroing by the OS. +However, the criticality of this behavior becomes quite high given the risks +associated with errant tagged values. + +\section{Capability-Aware Instructions} +\label{sec:capability-aware-instructions} + +A key design choice in the CHERI protection model is \textit{intentionality}: +the use of explicit instructions that accept (and require) capability +operands rather than overloading existing instructions, allowing selection of +integer-relative or capability-relative semantics. +In particular, it is essential that selection of integer or capability +semantics never be conditional on the value of the operand's tag. +This requires not just the introduction of instructions to inspect, +manipulate, load, and store capabilities, as a new CPU data type, but also a +set of explicit load, store, and control-flow instructions accepting capability +operands as the base address or jump target where the baseline ISA would +accept explicit integer operands. + +We have generally attempted to minimize the number of new instructions. +However, in some cases multiple variants are required to optimize important +code paths -- for example, capability bounds can be set using both an integer register +operand (\insnref{CSetBounds}), where there is a dynamically defined +size, such as when using \ccode{malloc}, and an immediate operand +(\insnref{CSetBoundsImm}), where there is a compilation-time size +available, such as for most stack-allocated buffers. + +Where possible, the structure and semantics of capability instructions have been +aligned with similar core MIPS instructions, similar calling conventions, and so on. +CHERI depends on introducing several new classes of instructions to the +baseline ISA. +In some cases these are congruent to similar instructions relating to +general-purpose integer registers, control-flow manipulation, and memory +accesses, in the form of capability-register manipulation, jumps to +capabilities, and capability-relative memory accesses. +Others have functions specific to CHERI, such as those manipulating capability +fields, and those relating to protection-domain transition. +The semantics of these instructions implements many aspects of the protection +model; for example, constraints on permission and bounds manipulation in +capability field manipulation instructions contribute to enforcing CHERI's +capability monotonicity properties. +These instructions are described in detail in Chapter~\ref{chap:isaref-mips}: + +\begin{description} +\item[Retrieve capability fields] +These instructions extract specific capability-register fields and move their +values into general-purpose (integer) registers: +\insnref{CGetAddr}, \insnref{CGetAndAddr}, +\insnref{CGetBase}, \insnref{CGetFlags}, \insnref{CGetLen}, +\insnref{CGetOffset}, \insnref{CGetPerm}, \insnref{CGetSealed}, +\insnref{CGetTag}, and \insnref{CGetType}. + +\item[Capability move] +This instruction moves a capability from one register to another without +change: \insnref{CMove}. + +\item[Conditional capability move] +These instructions conditionally move a value based on whether a capability +is NULL or non-NULL: \insnref{CMOVN} and \insnref{CMOVZ}. + +\item[Manipulate capability fields] +These instructions modify capability-register fields, setting them to values +moved from integer registers, subject to constraints such as monotonicity and +representability: \insnref{CAndAddr}, \insnref{CAndPerm}, +\insnref{CClearTag}, +\insnref{CIncOffset}, \insnref{CIncOffsetImm}, +\insnref{CSetAddr}, \insnref{CSetBounds}, +\insnref{CSetBoundsExact}, \insnref{CSetBoundsImm}, +\insnref{CSetFlags}, and +\insnref{CSetOffset}. + +\item[Derive integer pointers from capabilities, or capabilities from integer +pointers] +The \insnref{CToPtr} and \insnref{CFromPtr} instructions efficiently +convert between integer pointers and capabilities, performing suitable bounds +checks against contextual capabilities. +These support efficient hybrid code, in which use of integer pointers and +capabilities are intermixed. + +\item[Capability pointer comparison and arithmetic] +These instructions provide C-language pointer comparison and +subtraction behavior: \insnref{CPtrCmp} and \insnref{CSub}. + +\item[Load or store via a capability] +These instructions access memory indirected via an explicitly named capability +register, and will ideally correspond to a full range of contemporary +indexing modes present in the baseline ISA -- for example, allowing aligned or +unaligned access to zero-extended and sign-extended integers of varying +widths, as well as loading and storing of capabilities themselves. +Further, software stacks dependent on atomic operations on pointers will +require a suitable suite of atomic operations loading, modifying, and storing +capabilities -- e.g., load-linked, store-conditional instructions, or atomic +test-and-set instructions, depending on the underlying architecture. +These instructions include: \insnref[clbhwd]{CL[BHWD][U]}, \insnref{CLCBI}, +\insnref[cllbhwd]{CLL[BHWD][U]}, \insnref{CLLC}, \insnref{CSC}, +\insnref[csbhwd]{CS[BHWD]}, \insnref[cscbhwd]{CSC[BHWD]}, and \insnref{CSCC}. + +These correspond in semantics to the similar baseline ISA instructions, but +are constrained by the properties of the named capability including tag check, +permissions, bounds, seal check, and so on; if capability protections would be +violated, then an exception will be thrown. +Capability restrictions can be used to implement spatial safety via +permissions and bounds. + +Additionally, the \insnref{CLoadTags} instruction provides direct, +\emph{read-only} access to capability tags; see +\cref{sec:rationale:cloadtags}. + +\item[Program-Counter Capability] +Generated code makes frequent reference to \PCC{} in common position-independent +code structures, such as references to the Global Offset Table (GOT) or +Program Linkage Table (PLT). +These instructions allow \PCC{} to be retrieved and used as a base for +further pointer manipulation and accesses: +\insnref{CGetPCC}, \insnref{CGetPCCIncOffset} and \insnref{CGetPCCSetAddr}. + +\item[Capability jumps] +Capability-based code pointers allow the implementation of control-flow +robustness by limiting the permissions and bounds on jump targets (e.g., +preventing store, and limiting fetchable instructions). +Depending on the underlying ISA, different jump variations may be required -- +for example, adding capability variants of jump-and-link register, jump +register, and so on, including: \insnref{CJALR} and \insnref{CJR}. + +\item[Branch on capability fields] +These instructions branch within the current program-counter capability +(i.e., to an immediate relative to the current program counter) dependent on +capability tags or the capability holding a NULL value. +These include: \insnref{CBEZ}, \insnref{CBNZ}, \insnref{CBTS}, +and \insnref{CBTU}. + +\item[Capability checks] +The \insnref{CCheckTag} instruction throws an exception if the capability tag +is not set. +This is usd for compiler-inserted tag assertions. + +\item[Capability sealing] +The \insnref{CSeal} and \insnref{CUnseal} instructions seal or +unseal capabilities given a suitable authorizing capability (i.e., one with +the \cappermSeal or \cappermUnseal permission as appropriate). +Sealed capabilities allow software to implement encapsulation, such as is +required for software compartmentalization. The \insnref{CSealEntry} +instruction constructs \emph{hardware-interpreted} sealed entry (`sentry') +capabilities; see \cref{sec:arch-sentry}. + +\item[Protection-domain switching] +The \insnref{CInvoke} instruction is a +primitive upon which protection-domain switching can be implemented. +\insnref{CInvoke} has a jump-based semantic that +unseals its sealed code and data capability-register operands. +This allows software-controlled non-monotonicity by granting +access to additional state via unsealing. + +\item[Fast register clear] +The \insnref{CClearRegs} instruction clears a range of capability, +integer, or floating-point registers to support fast protection-domain +transition. + +\item[Special capability registers] +Special capability registers are read and written via special +\insnref{CReadHwr} and \insnref{CWriteHwr}. + +\item[Tag loading and rederivation] +Certain system operations, such as process or virtual-machine checkpointing +and memory compression, require that tagged memory have its tags saved and +then restored. +Memory locations can be iteratively loaded into capability registers to check +for tags; tags can then be later restored by manually rederived manually using +instructions such as \insnref{CAndPerm} and \insnref{CSetBounds}. +However, these instruction sequence is complex and can incur substantial +overhead when used during bulk restoration. +The \insnref{CLoadTags} instruction allows tags to be loaded for a cache +line of memory (non-temporally), and the \insnref{CBuildCap}, +\insnref{CCopyType}, and \insnref{CCSeal} instructions allow tags to +be efficiently restored. + +\item[Compartment identifiers] +CHERI protection domains, when constructed purely of graphs of capabilities, +do not allow the microarchitecture to explicitly identify one domain from +another. +In order to allow tagging of microarchitectural state, such as +branch-predictor entries, to avoid side channels, instructions are present to +allow software to explicitly identify compartment boundaries where +confidentiality requirements preclude more extensive microarchitectural +sharing: \insnref{CGetCID} and \insnref{CSetCID}. +\end{description} + +In addition, architectures may require additional capability-related +instructions related to conditional moves and exception delivery. + +\section{Sealed Entry Capabilities} +\label{sec:arch-sentry} + +CHERI borrows from earlier capability architectures a notion of immutable +capabilities that are usable solely as jump targets, most notably the +M-machine \cite{carter:mmachine94}, where these are called ``\emph{enter} +capabilities.'' +% +These reside somewhere between CHERI's unsealed and sealed +\cappermX-bearing capabilities. Because they act in tandem with +CHERI's sealing mechanism and describe function entry points, we use the +name `sealed entry' capability or just `sentry,' for short. +% +Similar to sealed capabilities, sentry capabilities are immutable by their +bearer and do not authorize memory loads or stores. Like unsealed +capabilities, the bearer may directly jump to the sentry to begin executing +the instructions it references. The jump instruction atomically unseals the +sentry and installs it to the program counter capability register. In our +implementations, we use the same instruction (e.g., \insnref{CJR} or +\insnref{CJALR}) to vector control through either unsealed or sentry +capabilities, so that code can be oblivious to whether it is jumping through +an ordinary code capability or a sentry. One could, of course, imagine +instructions that enforced the type of their operand. + +Since userspace function pointers are often passed to kernels for use in +callbacks, such as signal handlers, performing an exception return +(\insnnoref{ERET} on MIPS and ARMv8-A, \xRET{} on RISC-V and +\insnnoref{IRET} on x86) also atomically unseals the implicit jump target +when installing it to \PCC{} just like a normal capability jump instruction, +rather than forcing the kernel to re-derive an unsealed capability for the same +function. However, due to the need for kernels to perform actions such as +emulating unaligned accesses or unimplemented instructions, and thus manually +increment the application's \PCC{}, exceptions install the original unsealed +\PCC{} in \EPCC{} rather than creating a sentry and similarly forcing the +kernel to re-derive the unsealed capability. In addition to eliminating +unnecessary work, reducing the need for kernels to unseal or re-derive sentry +capabilities in software provides a security benefit by reducing the authority +present in userspace-facing code paths. +\jrtcnote{If anyone has a better way to phrase this that is more x86 stack +friendly I'm all ears.} + +Creating sentry capabilities is taken to be an ambient monotonic action, +requiring no additional permission than to have a capability bearing +\cappermX. +% +The \insnref{CSealEntry} instruction derives a sentry capability from any +\cappermX-bearing capability, otherwise preserving permissions, bounds, +and cursor. +% +Sentry capabilities have \cotype{} of $2^{\xlen{}}-2$ (truncated as required by the +implementation; recall \cref{tab:archotypes}) but are not intended to be +unsealable within general system software% +% +\footnote{While it would be ideal if the permission to unseal \cotype{} +$2^{\xlen{}}-2$ (and $2^{\xlen{}}-1$) were excluded from the primordial capability set, +instead, early boot code can enforce this when it partitions its boot +capabilities into the provenance roots it uses in the steady state.} +% +except by entry of control flow.% +% +\footnote{Of course, one could create a `self-unsealing enter capability' that +transferred PCC to the return value (capability) register and then returned +control to the caller. While this particular gadget is unlikely to be more +than a niche party trick, it demonstrates the need to manage, and (in +particular) clear, capabilities derived from the unsealed PCC before yielding +control.} + +We have altered CHERI-MIPS to create sentry capabilities +whenever it stores the PCC to a link register, as in \insnref{CJALR}. +We speculate that this is a lightweight change that furthers our adherence +to the principle of least privilege and reduces the number of ``gadgets'' +available to adversarial code. +\jrtcnote{This is a bit dated now; maybe we just remove the first sentence and +glue the second one to another paragraph?} + +Because the full, unsealed sentry is installed as the program counter, +PCC-relative addressing then permits the invoked instructions to use authority +beyond \cappermX. We exhibit some examples of such usage below. + +\nwfnote{Alex noted that the earlier encoding might also have required +\cappermX in \cperms{}. For the current proposal as well, we could +repurpose $\cotype{} = 2^{\xlen{}} - 2$ capabilities lacking \cappermX for some other +use of not-executable capabilities. Dually, we could say that $\cotype{} = 2^{\xlen{}} - 2$ +implies \cappermX and repurpose the bit in the encoding for something +else, should the need arise.} + +% +% For ease of research and experimentation, we propose using one of the two +% reserved bits in the 128-bit CHERI-MIPS implementation. If this and the +% existing ``sealed'' bit are both set, then the capability is an enter +% capability. Capability encodings with this new bit set and the extant +% sealed bit clear remain reserved. Eventually we should reconsider +% introducing multiple architectural capability roots and repacking bits +% appropriately, as per \cref{app:exp:compressperm}. +% +% This effectively widens the sealed flag to two bits and currently uses three +% of the possible four states: +% +% \begin{enumerate} +% \item[0b00\textbf{}] Unsealed capability (unchanged) +% \item[0b01\textbf{}] Sealed capability with \cotype{} (unchanged) +% \item[0b10\textbf{}] Reserved for future use +% \item[0b11\textbf{}] Enter capabilities +% \end{enumerate} +% +% \note{Since enter capabilities require PERMIT\_EXECUTE, we could also use +% \texttt{sealed = 0b11 \&\& !PERMIT\_EXECUTE} for a version of +% sealed data capabilities without an otype which can be unsealed using +% an unsealed capability that is a superset.}{Alex} + +\subsection{Per-Library Globals Pointers} + +Sentry capabilities are useful for multiply instantiated objects (e.g., shared +libraries), as schematically shown in \cref{fig:arch:sentry:plt}. In this +scenario, we wish to guarantee that any transfer of control into the read-only +region is guaranteed to have a capability to some instance's read-write section +in a register. In the case of a shared library, this may be a capability to +the library instance's global \texttt{.data} and \texttt{.bss} segments, and so +one sometimes hears the name `globals register' for this register use. More +generally, the capability may be likened to C++'s \texttt{this}. + +In order to achieve the desired effect, the loader should, at instantiation +time, create a Procedure Linkage Table (PLT) per instance; the PLT contains +dedicated trampoline code, together with capabilities to the read-only and +per-instance read-write regions. For efficiency, we would like the caller to +affect as direct a transfer of control as possible, yet we wish to guard +against frame-shifted entry to the trampoline code. Moreover, the trampoline +must arrange for the invoked code to have the correct state capability (e.g., +to a library's global variables), and yet the caller of the library must not +directly hold this capability. The atomic unseal-and-jump behavior of sentry +capabilities is ideal: the PLT may contain the capability to the state, and the +sentry can authorize its (PCC-relative) load once it has been entered, +yet the user can neither fetch or manipulate capabilities through the sentry +capability nor enter the instruction stream at an incorrect offset. + +\begin{figure} % fig:arch:sentry:plt <<< +\centering +\includegraphics{fig-sentry-plt.pdf} + +\caption{PLT-style multiple instantiation showing capability reachability. +The RO region is referenced with a subset of execute and load (data and +capability) permissions by the PLT. The PLT references its corresponding RW +region with any desired set of permissions. The PLT is referenced using +sentry capabilities by the outside world. The RW instance region may also +hold references to the corresponding PLT with additional permissions (dotted +lines); such references are required when the object's methods are not leafs +of the control graph.} +% +\label{fig:arch:sentry:plt} + +\end{figure} % >>> + +In order to continue to ensure that the code runs with the correct +capability in the globals register after return from a transfer of control +outside the library, re-entry must also be gated by similar PLT stubs. That +is, the return addresses must themselves be given PLT entries and direct +control transfers must not be used to call out from the library. Instead, +return addresses (in addition to the usual function entry points) should be +given appropriate PLT stubs and sentry capabilities to those stubs must be +used as the return address given to the callee. + +The contents of the stack and register file are otherwise shared with the +callee; the stack may still be visible to the caller, as well. This +mechanism is therefore not suitable for distrusting inter-domain calls, but +we believe it affords a reasonable amount of control flow integrity +assurance within a domain, acting as a defense against return- or +jump-oriented techniques. + +This technique relies very little on architectural mechanism beyond sentry +capabilities, namely, just PCC-relative loads of capabilities. Moreover, it is +likely simple to explain to a traditional dynamic linker. However, it requires +dedicated trampolines per instance of the object (library) under study, and +does not completely guarantee control flow: for example, code called by our +sentry-guarded library instance may engage in non-stack-discipline control flow +and skip its return. + +\subsection{Environment Calls via Sentry Capabilities} + +Sentry capabilities are also useful for sandboxing. While sandboxed code can +be made to look like a library to the caller, a more +interesting observation is that the reverse is also possible and that sentry +capabilities are also viable for calls \emph{from} the sandbox back to a +single-threaded supervisor environment. On sandbox construction, the +supervisor allocates space for its state closure (a \texttt{longjmp} buffer +and other state) and builds a set of PLT-like stubs for this +new sandbox that will ensure that a capability to this closure is passed to +the functions invoked, just as the PLT stubs above ensured that the global +pointer is passed. Whenever the environment calls into the sandbox, it must +update its state closure as part of preparing the register file for entry to +the sandbox. The return address given to the sandbox should, as discussed +above, also be a sentry capability pointing to one of the constructed +PLT-like stubs. + +In the case of multiple threads calling into the sandbox, the environment must +demultiplex its closure pointers, as it cannot necessarily depend on the +sandbox to not use the return sentry capability from one thread within another +thread's execution. The trampoline code for invoking or returning to the +supervisor environment will, ultimately, involve asking the \emph{supervisor environment's +supervisor} for the notion of `current thread' and using that information to +retrieve the appropriate closure state. In the case that the environment is +running under a kernel, demultiplexing may avail itself of a system call or +fetch from VDSO to retrieve the current thread identifier or thread local +storage capability. In the case that the environment \emph{is} the kernel, it +must use privileged architectural state (e.g., a saved stack pointer) to +distinguish threads (and so the sentry capability itself must bear +\cappermASR or have access to another capability that does). + +% >>> + + +\section{Handling Failures} + +Instruction-set architectures have various resources in the event that a +``failure'' occurs, with common choices being to set special status bits (on +ISAs that have status registers), to write back a special value to a +general-purpose integer register, or to throw an exception. +CHERI introduces several new potential failure modes: + +\begin{description} +\item[Instruction-fetch failures] Because the program counter is extended to + be a capability, it is possible for CHERI to deny access for instruction + fetch. + For example, the program counter may move out of bounds, software may + jump to an untagged or otherwise insufficiently authorized capability, or an + exception handler may install an untagged or insufficiently authorized + capability on return. + + We explored two variations on failure reporting: to report the + failure via an exception at the time that the new program-counter capability + is installed (e.g., on the jump instruction), or at the time that the + instruction fetch is requested (i.e., when execution of the new instruction + is requested). + Throwing an exception on fetch leads to the most consistent general + behavior, and also better handles installation of an invalid exception + program-counter capability by avoiding an exception within the kernel when + the exception program-counter capability is written to. +%%%% PGN COMMENT: capabilities are not written to. REGISTERS are... + Throwing an exception prior to writing the new value to \PC{}, on the other + hand, provides more complete debugging information: the errant jump \PC{} is + available to the exception handler. + With compressed capabilities, this also provides access to the target virtual + address and fully precise bounds; in the event of a substantially + out-of-bounds target address, either the target virtual address or the + bounds would have to be discarded to ensure a representable capability. + + Ultimately, both approaches are consistent with our security goals. + We therefore err on the side of improved debuggability, throwing exceptions + on jump where possible. + We also require checking of capability properties on instruction fetch to + catch cases such as exception return to an invalid or out-of-bounds + capability. + +\item[Load and store failures] When dereferencing a capability for data + access occurs, ISAs generally report this failure via an exception at the + time of the attempted access, which CHERI in general does as well. + These exceptions fit existing patterns of exception delivery in MMU-based + architectures and operating systems, which are designed to handle faults on + memory access. + + There are two cases in which an alternative approach is taken: when the + \cappermL capability permission or equivalent page-table or TLB + permission is not present, any tag on the loaded capability is instead + stripped. + This avoids an exception that depends on the loaded data value, which is + awkward in some architectures (e.g., ARMv8-A), but also facilitates writing + code for tag-stripping memory copies, which arise frequently around + protection-domain boundaries. + +\item[Guarded manipulation failures] + A new class of register-to-register instructions in CHERI can experience + failures when attempts are made to violate rules imposed via guarded + manipulation -- for example, attempts to perform non-monotonic operations, or + transformations that lead to non-representable bounds with compressed + capabilities. + In our initial CHERI-MIPS design, we took the perspective that reporting + failures early allowed the greatest access to debugging information, and + favored throwing an exception at the earliest possible point: the + instruction attempting to violate guarded manipulation. + + Another potential design choice is to instead strip the tag from the value + being written back to a target capability register, which maintains our + security safety properties, but defers exception delivery until an attempted + dereference -- e.g., an instruction load via the resulting invalid + capability. + There are two arguments for this latter behavior: first, that some + architectures by design limit the set of instructions that throw exceptions + to facilitate superscalar scheduling (e.g., ARMv8-A); and second, that + exception delivery means that failures that could otherwise be easily + detected and handled by a compiler or language run time via an explicit tag + check are now complex to handle. +%%%% STRANGE USAGE. more difficult to handle? more complex? + + When using tag stripping in ISAs with status registers (e.g., ARMv8-A), the + cost of checking results for frequent operations can be amortized via a + single status check. + For ISAs without status registers, checking results can come at a + significant cost, and a deferred exception delivery at time of dereference + will be the best choice for performance-critical code. + + We therefore make design choices about exception delivery for violations of + guarded manipulation in a case-by-case basis, taking into account more + general architectural design philosophies, and also specific use cases where + software may benefit from tag clearing rather than exception delivery. +\end{description} + +%\subsection{Object-Capability Invocation} +% +%\rwnote{A fair amount of this text relates to the software model and not the +% architectural model -- this should be moved somewhere more appropriate.} +% +%\rwnote{.. But it would be a good idea to have a high-level architectural +% consideration of non-monotonicity here. And mention our new thoughts on the +% CID concept.} +% +%{\em Object invocation} is a central operation in the CHERI ISA, as it +%implements protected subsystem domain transitions that atomically update the +%set of rights (capabilities) held by an architectural thread, and that provide a +%trustworthy return path for later use. +%When an object capability is invoked, its data and code capabilities are +%{\em unsealed} to allow access to per-object instance data and code +%execution. +%Rights may be both acquired and dropped on invocation, allowing non-hierarchical +%security models to be implemented. +%Strong typing and type checking of objects +%in hardware, +%(a notion first introduced in PSOS's {\em type +%enforcement,}~\cite{PSOS,NeumannFeiertag03}) +%serves functions both at the ISA level -- providing object +%atomicity despite the use of +%multiple +%independent capabilities to describe an +%object -- and support for language-level type features. +%For example, types can be used to check whether additional object arguments +%passed to a method are as they should be. +%As indicated earlier, the architectural capability type may be used to support +%language-level types, but should not be confused with language-level types. + +\section{Composing Architectural Capabilities with ISAs}\label{CAP-ISAs} + +In applying CHERI to an architecture, the aim is to impose the key properties +of the abstract CHERI model in a manner keeping with the design philosophy and +approach of each architecture: strong compatibility with MMU-based, C-language +TCBs; strong fine-grained memory protection supporting language properties; +and incrementally deployable, scalable, fine-grained compartmentalization. +This should allow the construction of portable, CHERI-aware software stacks +that have consistent protection properties across a range of underlying +architectures and architectural integration strategies. + +ISAs vary substantially in their representation and semantics, but have +certain common aspects: + +\begin{itemize} +\item One or more operation encoding (opcode) spaces representing specific + instructions as fetched from memory; +\item A set of architectural registers managed by a compiler or hand-crafted + assembly code, which hold intermediate values during computations; +\item Addressable memory, reached via a variety of segmentation and paging + mechanisms that allow [optional] implementation of virtual addressing; +\item An instruction set allowing memory values to be loaded and stored, + values to be computed upon, control flow to be manipulated, and so on, + with respect to both general-purpose integer and floating-point values -- and + vectors of values for an increasing number of ISAs; +\item An exception mechanism allowing both synchronous exceptions (e.g., + originating from instructions such as divide-by-zero, system calls, + unimplemented instructions, and page-table misses) and asynchronous events + from outside of the instruction flow (timers, inter-processor interrupts, + and external I/O interrupts) that cause a controlled transition to a + supervisor; +\item A set of control instructions or other (perhaps memory-mapped) + interfaces permitting interaction with the boot environment, management of + interrupt mechanisms, privileged state, virtual addressing features, timers, + debugging features, energy management features, and performance-profiling + features. + + Depending on the architecture, these might be strictly part of the ISA + (e.g., implemented explicit instructions to flush the TLB, mask + interrupts, or reset the register state), or they may be part of a broader + platform definition with precise architectural behavior dependent on the + specific processor vendor (e.g., having firmware interfaces that flush TLBs + or control interrupt state, or register values at the start of OS boot + rather than CPU reset). +\end{itemize} + +Implementations of these concepts in different ISAs differ markedly: opcodes +may be of fixed or variable lengths; instructions might strictly separate or +combine memory access and computation; page tables may be a purely software +or architectural constructs; and so on. Despite these differences in +underlying software representation, a large software corpus (implemented in +both low-level languages (e.g., C, C++) and higher-level managed languages +-- e.g., Java) can be written and maintained in a portable manner across +multiple mainstream architectures. + +The CHERI protection model is primarily a transformation of memory access +mechanisms in the instruction set, substituting a richer capability mechanism +for integer pointers used with load and store instructions (as well as +instruction fetch). +However, it has broad impact across all of the above ISA aspects, as it is by +design explicitly integrated with register use (to ensure intentionality of +access) rather than implicit in existing memory access (as is the case with +virtual memory). +CHERI must also integrate with the exception mechanism, as handling an +exception implies a change in effective protection domain, control of +privileged operations such as management of virtual memory, and so on. + +CHERI-MIPS is an application of the CHERI protection model to the 64-bit MIPS +ISA. +CHERI-MIPS is grounded in MIPS's load-storage architecture (instructions +either load/store data with respect to memory, or compute on register values, +but never both), the software-managed TLB (page tables are a purely software +construct), and the MIPS ISA ``coprocessor'' opcode space reserved for ISA +extensions. +As a result, a number of concrete design choices are made that are in many +ways specific to MIPS: a decision to separate general-purpose integer files and +capability register files; occupation of the coprocessor opcode space; and TLB +rather than page-table additions to control the use of capabilities. +These low-level design choices will apply to only a limited degree in other +ISAs -- but the objectives achieved through these choices must also appear in +other ISAs implementing the CHERI model: explicit use of capabilities for +addressing relative to virtual-address spaces, monotonicity enforcement via +guarded manipulation, tagged memory protecting valid pointer provenance in +memory, suitable support in the exception mechanism to allow current OS +approaches combining user and kernel virtual-address spaces, and so on. + +In the following chapters we present high-level sketches of applications of +the CHERI protection model to three ISAs: 64-bit MIPS (in which our ideas were +first developed and prototyped), RISC-V (a contemporary load-store instruction +set -- which in many ways is a descendant of the MIPS ISA); and the x86-64 ISA +(which has largely independent lineage of Complex Instruction Set (CISC) +architectures). +The CHERI model applies relatively cleanly to all three, with many options +available in how specifically to apply its approach, and yet with a consistent +overall set of implications for software-facing design choices. +Wherever possible, we aim to support the same operating-system, language, +compiler, run-time, and application protection and security benefits, which +will be represented differently in machine code and low-level software +support, but be largely indistinguishable from a higher-level programming +perspective. +These instantiations should retain the highly compatible strong protection and +compartmentalization scalability properties seen with +CHERI extensions for MIPS. + +It is possible to imagine less tight integration of CHERI's features with the +instruction set. +Microcontrollers, for example, are subject to tighter constraints on area and +power, and yet might benefit from the use of capabilities when sharing memory +with software running on a fully CHERI-integrated application processor. +For example, a microcontroller might perform DMA on behalf of a CHERI-compiled +application, and therefore desire to constrain its access to those possible +through capabilities provided by the application. +In this scenario, a less complete integration might serve the purposes of that +environment, such as by providing a small number of special capability +registers sufficient to perform capability-based loads and stores, or to +perform tag-preserving memory copies, but not intended to be used for the +majority of general-purpose operations in a small, fixed-purpose program for +which strong static checking or proof of correctness may be possible. + +\subsection{Architectural Privilege} + +In operating-system design, {\em privileges} are a special set of rights +exempting a component from the normal protection and access-control models -- +perhaps for the purposes of system bootstrapping, system management, or +low-level functionality such as direct hardware access. +In CHERI, three notions of privilege are defined, complementing current +notions of architectural privilege: + +\begin{description} + +\item[Ring-based privilege] derives from the widely used architectural notion + that code executes within a \textit{ring}, typically indicated by the state + of a privileged status register, authorizing access to architectural protection + features such as MMU configuration or interrupt management. + Code executing in lower rings, such as a microkernel, hypervisor, or full + operating-system kernel, has the ability to manage state giving it control + over state in higher, but not lower, rings. + When a privileged operation is attempted in a higher ring, an architectural + exception will typically be thrown, allowing a supervisor to emulate the + operation, or handle this as an error by delivering a signal or terminating + a process. + More recent hardware architectures allow privileged operations to be + virtualized, improving the performance of full-system virtualization in + which code that would historically have run in the lowest ring (i.e., the OS + kernel) now runs over a hypervisor. + + CHERI retains and extends this notion of privilege into the capability + model: when an unauthorized operation is performed (such as attempting to + expand the rights associated with a capability), the processor will throw an + exception and transition control to a lower ring. + The exception mechanism itself is modified in CHERI, in order to save and + restore the capability register state required within the execution of each + ring -- to authorize appropriate access for the exception handler. + The lower ring may hold the privilege to perform the operation, and emulate + the unauthorized operation, or perform exception-handling operations such + as delivering a signal to (or terminating) the user process. + +\item[Capability control of ring-related privileges] refers to limitations + that can be placed on ring-related privileges using the capability model. + Normally, code executing in lower protection rings (e.g., the supervisor) has + access to privileged functions, such as MMU, cache, and interrupt + management, by virtue of ambient authority. + CHERI permits that ambient authority to be constrained via capability + permissions on the \textit{program-counter capability}, preventing less + privileged code (still executing within a low ring) from exercising + virtual-memory features that might allow bypassing of in-kernel sandboxing. + More generally, this allows vulnerability mitigation by requiring + explicit (rather than implicit) exercise of privilege, as individual + functions can be marked as able to exercise those features, with other + kernel code unable to do so. +\end{description} + +These models can be composed in a variety of ways. +For example, if a compartmentalization model is implemented in userspace over +a hybrid kernel, the kernel might choose to accept system calls from only +suitably privileged compartments within userspace -- such as by requiring +those compartments to have a specific software-defined permission set on their +program-counter capability. + +\subsubsection{Layering Software Privilege over Capability Privilege} + +In addition to these purely architectural views of privilege, privileged +software (e.g., the OS kernel running in supervisor mode) is able to +selectively proxy access to architectural privilege via system calls. +This facility is used extensively in contemporary designs. +For example, requests to memory +map files or anonymous memory, after processing by many levels of abstraction, +lead to page-table updates, TLB flushes, and so on. +Similarly, requests to configure in-process signal timers or time out I/O +events, many levels of abstraction lower, are translated into operations to +manage hardware timers and interrupts. + +Similar structures can be implemented using the CHERI capability model. +\textbf{Privilege through capability context} is a new, and more general, +notion of privilege arising solely from the capability model, based on a set of +rights held by an execution context connoting privilege within an address +space. +When code begins executing within a new address space, it will frequently be +granted full control over that address space, with initial capabilities that +allow it to derive any required code, data, and object capabilities it might +require. +This notion of privilege is fully captured by the capability model, and no +recourse is required to a lower ring as part of privilege management in this +sense. +This approach follows the spirit of Paul Karger's paper on limiting the +damage potential of discretionary Trojan horses~\cite{Karger87}, and extends +it further. +Certain operations, such as domain transition, do employ the ring mechanism, +in order to represent controlled privilege escalation -- e.g., via the +object-capability call and return instructions. + +\subsection{Traps, Interrupts, and Exception Handling} +\label{sec:traps_interrupts_exception_handling} + +CHERI retains and extends existing architectural exception support, as +triggered by traps, system calls, and interrupts. +CHERI affects the situations in which exceptions are triggered, and changes +aspects of exception delivery, state management within exceptions, and also +exception return. +Exception handling is also one of the means by which non-monotonic state +transition takes place: as exception handlers are entered, they gain access to +capabilities unavailable to general execution, allowing them to implement +mechanisms such as domain transition to more privileged compartments. +As exception support varies substantially by architecture -- how exception +handlers are registered, what context is saved and restored, and so on -- +CHERI integration necessarily varies substantially. +However, certain general principles apply regardless of the specific +architecture. + +\subsubsection{New Exceptions for Existing and New Instructions} + +New exception opportunities are introduced for both existing and new +instructions, which may trap if insufficient rights are held, or an invalid +operation is requested. +For example: + +\begin{itemize} +\item Instruction fetch may trap if it attempts to fetch an instruction in a + manner not authorized by the installed Program-Counter Capability (\PCC{}). + +\item Existing integer-relative load and store instructions will trap if they + attempt to access memory locations in a manner not authorized by the + installed Default Data Capability (\DDC{}). + +\item New capability-relative load and store instructions will trap if they + attempt to access memory locations in a manner not authorized by the + explicitly presented capability. + +\item New capability-manipulation instructions may trap if they violate + guarded-manipulation rules, such as by attempting to increase the bounds on + a capability. +\end{itemize} + +\noindent +In general, CHERI attempts to provide useful cause information when exceptions +fire, including to identify whether an exception was triggered by using an +invalid capability, dereferencing a sealed capability, or an access request +not being authorized by capability permissions or bounds (see +Section~\ref{sec:capability_exception_causes} for details). + +\subsubsection{Exception Delivery} + +The details of exception delivery vary substantially by architecture; however, +CHERI adaptations are in general fairly consistent across architectures: + +\paragraph{Interrupt state} +Interrupts will typically be disabled on exception entry. +System software will typically leave interrupts disabled during low-level +processing, but re-enable interrupts so as to allow preemption during normal +kernel operation. +CHERI does not change this behavior. + +\paragraph{Control-flow state} +The Program Counter (\PC{}) will be saved to an Exception Program Counter +(\EPC{}). +System status state, such as the ring in which the interrupted code was +executing, as well as possibly other state such as interrupt masks, will be +saved in a special status register. +System software will typically save this and any other register state +associated with the preempted code, allowing to to establish a full execution +context for the exception handler, or to switch to another thread. +CHERI extends \PC{} to become a Program-Counter Capability +(\PCC{}) and \EPC{} to become an Exception Program-Counter Capability +(\EPCC{}). +Depending on the architecture, status registers may be extended to also +contain CHERI-related information, such as whether opcode interpretation for +loads and stores is integer relative or capability relative (as in +CHERI-RISC-V), allowing that state to differ between interrupted code and the +exception handler. + +\paragraph{Other architectural state} +In addition to general-purpose registers, architectures may provide access to +a set of special registers, such as for Thread-Local Storage (TLS). +Additional context banking or saving may also occur, to facilitate fast +exception delivery. +For example, in ARMv8-A, the stack pointer register is banked, allowing +exception handlers to use their own stack pointer to save remaining registers. +In x86-64, the stack pointer register is potentially replaced and the original +stack pointer is saved on the exception stack. +CHERI extensions are also required to these additional pieces of +architectural context management; for example, TLS integer registers must be +extended to become TLS capabilities. +The banked ARMv8-A stack pointer and x86-64 exception stack pointers +would need to be widened to full capabilities. + +\paragraph{Exception-handler entry} +In order to execute an exception handler, the architecture will switch to an +appropriate ring (often the supervisor ring), and set \PC{} to the address of +the desired exception vector. +Exception delivery may also change other aspects of execution, such 32-bit +vs. 64-bit execution, so as to enter the exception handler in the execution +mode that is expected. +CHERI introduces two new capabilities: the Kernel Code Capability (\KCC{}) and +the Kernel Data Capability (\KDC{}), which provide additional rights to the +exception handler authorizing its execution. +\KCC{} will automatically be combined with exception vector address and +installed in \PCC{} to execute the vector. +\KDC{} becomes available by virtue of \PCC{} having the +\cappermASR* permission, and can be used to reach +exception-handler data such as global variables. + +\subsubsection{Safe exception state handling} + +In some architectures, partial register banking or reserved exception-only +registers mean that exception handlers must utilize only a subset of +registers unless they explicitly save them. +With CHERI, it is essential that capability register values not just be saved +and restored, to ensure correct functionality, but that capability register +values are also not leaked, as this may undesirably grant privilege. +For example, even if the ABI does not require that a system call or trap +maintain the values of certain registers over exception handling, the +exception handler must restore or clear those values to ensure that +capabilities used by the exception handler or another context are not leaked. + +\subsubsection{Exception Return} + +Exception return unwinds the effects described in the previous section, +restoring \PC{} from \EPCC{}, restoring the saved ring and interrupt-enable +state, swapping banked registers, and so on. +The changes made to support CHERI exception entry must also be made to +exception return, such as restoring the full \EPCC{} to \PCC{}. + +\subsubsection{Capability Exception Causes} +\label{sec:capability_exception_causes} + +In each of the target ISAs (MIPS, RISC-V, and x86-64), we introduce a new +exception to report capability violations. +Since this exception covers a variety of error cases, each CHERI ISA +must provide a capability exception code in an architecture-specific +manner which indicates the specific violation. +While the capability exception code delivery is architecture-specific, +the capability exception codes are shared across all architectures. +The possible capability exception codes are shown in Table~\ref{table:capability-cause}. + +\begin{table} +\begin{center} +\begin{threeparttable} +\begin{tabular}{ll} +\toprule +Value & Description \\ +\midrule +0x00 & None \\ +0x01 & Length Violation \\ +0x02 & Tag Violation \\ +0x03 & Seal Violation \\ +0x04 & Type Violation \\ +0x05 & \emph{reserved} \\ +0x06 & \emph{reserved} \\ +0x07 & \emph{reserved} \\ +0x08 & Software-defined Permission Violation \\ +0x09 & MMU prohibits store capability \tnote{1} \\ +0x0a & Representability Violation \\ +0x0b & Unaligned Base \tnote{2} \\ +0x0c & \emph{reserved} \\ +0x0d & \emph{reserved} \\ +0x0e & \emph{reserved} \\ +0x0f & \emph{reserved} \\ +0x10 & \cappermG Violation \\ +0x11 & \cappermX Violation \\ +0x12 & \cappermL Violation \\ +0x13 & \cappermS Violation \\ +0x14 & \cappermLC Violation \\ +0x15 & \cappermSC Violation \\ +0x16 & \cappermSLC Violation \\ +0x17 & \cappermSeal Violation \\ +0x18 & \cappermASR Violation \\ +0x19 & \cappermCInvoke Violation \\ +0x1a & \capperm{Access\_CInvoke\_IDC} Violation \\ +0x1b & \cappermUnseal Violation \\ +0x1c & \cappermCid Violation \\ +0x1d & \emph{reserved} \\ +0x1e & \emph{reserved} \\ +0x1f & \emph{reserved} \\ +\bottomrule +\end{tabular} +\begin{tablenotes} +\item [1] Deprecated, only used on CHERI-MIPS. +\item [2] Only used on CHERI-RISC-V. +\end{tablenotes} +\end{threeparttable} +\end{center} +\caption{Capability Exception Codes} +\label{table:capability-cause} +\end{table} + +\subsubsection{Capability Exception Priority} +\label{sec:capability_exception_priority} + +Exception handling in most architectures involves an architectural cause code +that describes the type of event that triggered the exception -- for example, +indicating that a trap has been caused by a read or write page fault. +Exception types are prioritized so that if more than one exception code could +be delivered -- e.g., there is the potential for both an alignment fault and +also a page fault triggered by a particular load or store -- a single cause is +consistently reported. + +Capability-triggered exceptions in general have a high priority, above that +for either alignment faults or MMU-related faults (such as page-table or TLB +misses), as capability processing logically occurs ``before'' a virtual +address is interpreted. +This also prevents undesirable (or potentially insecure) behaviors, such as +the ability to trigger a page fault on a virtual address outside the bounds of +a capability being dereferenced: instead, the bounds error should be reported. +Similarly, if an operating system implements emulation of unaligned loads and +stores by catching unaligned-access exceptions, having capability checks occur +in preference to alignment exceptions avoids having alignment emulation also +perform capability checks -- e.g., of its length or permissions. +Other priority rules are less security critical, but are defined by this +specification so that exception processing is deterministic. +Each architecture defines its own exception priority, and +architecture-specific instantiations of CHERI must define an +architecture-specific prioritization for capability-related exceptions +relative to other exception types. + +If an instruction could potentially throw more than one capability exception, +the capability exception code is set to the highest priority exception (numerically lowest +priority value) as shown in Table~\ref{table:exception-priority}. + +\begin{table} +\begin{center} +\begin{tabular}{ll} +\toprule +Priority & Description \\ +\midrule +1 & \cappermASR Violation \\ +2 & Tag Violation \\ +3 & Seal Violation \\ +4 & Type Violation \\ +5 & \cappermSeal Violation \\ + & \cappermCInvoke Violation \\ + & \capperm{Access\_CInvoke\_IDC} Violation \\ + & \cappermUnseal Violation \\ + & \cappermCid Violation \\ +6 & \cappermX Violation \\ +7 & \cappermL Violation \\ + & \cappermS Violation \\ +8 & \cappermLC Violation \\ + & \cappermSC Violation \\ +9 & \cappermSLC Violation \\ +10 & \cappermG Violation \\ +11 & Length Violation \\ +12 & Requested bounds cannot be represented exactly \\ +13 & Software-defined Permission Violation \\ +14 & MMU prohibits store capability \\ +\bottomrule +\end{tabular} +\end{center} +\caption{Exception Priority} +\label{table:exception-priority} +\end{table} + +\subsection{Virtual Memory} +\label{sec:virtual_memory} + +Where virtual memory is present and enabled, CHERI capabilities are +interpreted with respect to the current virtual address space. +In CHERI-MIPS, this means that the embedded address in a capability is always +a virtual address, as the virtual-address translation cannot be disabled. +In others, such as CHERI-RISC-V, where virtual-address translation can be +enabled or disabled dynamically, the embedded address will be interpreted as a +physical address when translation is disabled, and a virtual address when +virtual addressing is enabled. + +Capabilities do not embed Address-Space IDentifiers (ASIDs), and so will be +interpreted relative to the current virtual address space; this means that, +as with virtual addresses themselves, the interpretation of a specific +capability value depends on the address space that they are used in. +The operating system or other TCBs may wish to limit the flow of capabilities +between address spaces for this reason. + +Processing of capabilities is therefore ``before'' virtual-address +translation, with the result of each memory access via a capability being an +access control decision (allow or reject the access) and a virtual address and +length for the authorized operation. +The operation then proceeds through the normal memory access paths for +instruction fetch, load, or store. +The capability mechanism therefore never enables new operations not already +supported by existing MMU-based checks. + +\subsubsection{Authorizing MMU Control} + +Memory Management Units (MMUs) typically come in two flavors: those supporting +architectural (hardware) page-table walking; and those supporting software TLB +management. +In the former category, a series of instructions or control registers +configures parameters such as the page-table format being used, the current +page-table root, and can selectively or fully flush the Translation +Look-aside Buffer (TLB). +The page table has an architecturally defined format, consisting of a +multi-level tree of Page-Table Directory Entries (PTDEs) and leaf-node +Page-Table Entries (PTEs), and may not only be read but also written to if +dirty bits are supported. +The architecture will perform a series of memory reads to locate the correct +page-table entry to satisfy a lookup, filling a largely microarchitectural +TLB. +In the latter category, instructions directly manipulate architectural TLB +entries as a result of TLB miss (or other) exceptions. +In both cases, exceptions may fire if operations are rejected as a result of +page permission checks (e.g., and attempt to store to a read-only page). +CHERI composes with these mechanisms in several ways: + +\begin{itemize} +\item CHERI controls use of privileged instructions and control registers that + configure the MMU, including enabling and disabling translation, configuring + a page-table root if supported, and flushing the TLB. + The \cappermASR* permission must be present on \PCC{} to perform these + operations. + +\item On systems with a software-managed TLB, such as CHERI-MIPS, retrieving + and inserting TLB entries also depends on \cappermASR* being + present on \PCC{}. + The TLB exception handler will use \KCC{} and \KDC{}, available in the + exception context, to authorize access to the software-managed page table. + +\item On systems with a hardware page-table walker, CHERI currently + \textit{does not} control memory accesses performed by the walker via + physical addresses. + In a more ideal future world, the page-table walker would be given an + initial, likely physical, capability to use as the root, and have further + access authorized by capabilities embedded in page-table directory entries. +\end{itemize} + +\subsubsection{MMU Capability Permissions} + +Virtual-address translation is itself unmodified, but permission checking is +extended with new page permissions in the MMU mappings (i.e., TLB entries or +PTEs, depending on the architecture): + +\begin{description} +\item[MMU Load Capability Permission] +If this permission is present, as well as the existing page-table read +permission, then loading tagged capabilities is permitted. +If this permission is not present, architectures may either trap or +clear the tag bit of the loaded capability. + +If the \cappermLC permission is not present on the authorizing capability for +the memory read, then the tag is cleared from the loaded capability, and this +page permission is ignored. + +If an exception is raised, the exception should resemble other MMU +exceptions for the architecture. In particular, the virtual address +of the attempted memory access should be provided by the exception in +a similar manner to other MMU exceptions. + +\item[MMU Store Capability Permission] +If this permission is present, as well as the existing page-table write +permission, then storing tagged capabilities is permitted. +Otherwise, if a capability store operation occurs with a capability value that +has the tag bit set, an exception will be thrown. + +If an exception is raised, the exception should resemble other MMU +exceptions for the architecture. In particular, the virtual address +of the attempted memory access should be provided by the exception in +a similar manner to other MMU exceptions. + +With the page-table store-capability permission, it is also imaginable that +the architecture might choose to strip the tag bit before performing the +store, rather than throw an exception, if the permission is required but not +present. +This would avoid a data-dependent exception, which may simplify the +microarchitecture. +However, this would disallow the dynamic tracking of possible capability +locations using this permission bit, in a manner similar to emulated dirty +page support. +As this support may be important in improving performance for revocation and +garbage collection, it would be desirable to provide some other mechanism in +that case. +\end{description} + +\subsubsection{Capability Dirty Bit} + +In architectures that support tracking dirty pages in the page table, by +performing updates to page-table entries when a page has been dirtied, it is +imaginable that a new \textit{capability dirty bit} might provide a suitable +substitute for trapping on a failed capability store. +This bit would be set atomically if a new tagged capability value is stored +via the page. +In as much as the architecture supported false positives for the page dirty +bit -- i.e., that the dirty bit could be set even though there wasn't a +committed data write -- that would also be permissible for the capability +dirty bit. +However, false negatives -- in which the dirty bit is not set despite the +page becoming dirty -- would not be permissible for the capability dirty bit. +Otherwise, there is a risk that revocation or garbage collection might +``miss'' a capability, violating a temporal security or safety policy. + +\subsubsection{Per-Page Capability Load Barriers} +\label{section:capability-load-barriers} + +Garbage collectors and capability revocation, in addition to lazily tracking +capability flow through stores, would like to be able to catch (attempted) +capability transfers on loads from memory. Such software could avail itself of +a different interpretation of the page-table load capability permission, in +which loading a (tagged) capability \emph{trapped}. As both behaviors might be +useful in different circumstances, we expect that architectures offering this +feature will have a separate bit in the MMU mapping to indicate which is +requested. +% +(It is possible to emulate the tag-clearing semantics given only the trapping +semantics, at the cost of efficiency; if only one is possible, we suggest +providing only the trapping behavior.) +% +While, ideally, an implementation would ensure that such a capability-load trap +were raised only if a \emph{set} tag were returned from memory, this would be a +\emph{data-dependent trap}, a potentially uncomfortable proposition for +high-performance microarchitectures. Instead, we believe it permissible for a +(micro)architecture to always trap on capability load instructions fetching +through MMU mappings so configured; the loss of precision is unlikely to have +huge repercussions as, in general, capability-bearing pages will be visited by +the collector or revoker eventually, and so any significant difference will +come from timing or imprecision in tracking which pages bear capabilities. + +Across an application's lifetime, its address space may need to be repeatedly +scanned. That is, its capability-bearing pages may need to transition in +tandem between permitting capability loads and trapping thereupon to cue the +collector or revoker's inspection of the source page before restoring that page +to permitting capability loads. While it is certainly possible to update all +MMU mappings to toggle between the two, this operation would take linear time +and touch linear memory, likely with all application threads paused. We +instead envision a parallel constant-time operation for the bulk update, +achieved by equipping each \emph{CPU core} and all MMU mappings with one-bit +``generation counters'' delimiting per-address-space ``epochs.'' Prior to the +start of an epoch, all generation counters within the address space's page +tables and actively associated cores are equal. The beginning of an epoch is +signaled by all cores incrementing their generation (synchronously, from the +perspective of the application), and the epoch comes to an end when all MMU +mappings' generation counters once again equal this incremented value. + +\nwfnote{fwref experimental appendix on CLGs, once that's ready} + +\subsubsection{Memory Compression, Memory Encryption, Swapping, and Migration} + +When memory pages are stored to a non-tag-bearing medium, such as by virtue +of being compressed in DRAM, encrypted, swapped, or perhaps migrated to +another system by virtue of process or virtual-machine migration, tags must +also be saved and restored. +Architecturally, this can be performed by reading through the page of memory, +checking for tags, and preserving them out-of-band -- e.g., in a swap +meta-data structure. +They can then be restored by rederiving the capability value from some +suitably privileged authorizing capability. +We offer specific instructions to support efficiently restoring tags without +software inspecting the in-memory format: \insnref{CBuildCap} and +\insnref{CCSeal}. +The \insnref{CLoadTags} allows efficient gathering of tag data from full +cache lines, and will have non-temporal behavior -- i.e., will not perform +cache allocation, despite being coherent, to avoid sweeping passes pulling +all the corresponding data into the cache. +It is imaginable that a \insnnoref{CStoreTags} instruction might be +desirable to set tags bulk, but this would require some care with privilege to +avoid an arbitrary \insnnoref{CSetTag} implementation rather than +controlled rederivation. + +\subsection{Direct Memory Access (DMA)} +\label{sec:dma} + +As described in this chapter, the CHERI capability model is a property of the +instruction-set architecture of the CPU, and imposed on code executing on that +CPU. +However, in most computer systems, Direct Memory Access (DMA) is used by +non-application cores, accelerators, and peripheral devices to transfer data +into and out of system memory without explicit instruction execution for each +byte transferred: device drivers configure and start DMA using device or +DMA-engine control registers, and then await completion notification through +an interrupt or by polling. +Used in isolation, nothing about the CHERI ISA implies that device memory +access would be constrained by capabilities. + +\subsubsection{DMA Stores with Tag Stripping} + +Our first recommendation is that, in the absence of additional support, DMA +access to memory be unable to write tagged values, and that it implicitly +strip tags associated with stored memory locations as all writes will be data +and not capabilities. +This implements a conservative model in which only the CPU is able to +introduce capabilities into the system, and DMA stores do not risk errantly +(or maliciously) introducing capabilities without valid provenance, or +corrupt CPU-originated capabilities-- as all such writes will involve data and +not capabilities. + +\subsubsection{Capability-Aware DMA and IOMMUs} + +Our second recommendation is that ``capability-aware DMA'' -- i.e., DMA that +can load and store tagged values -- be the remit of only trustworthy DMA +engines that will preserve valid provenance, ensure monotonicity, and so on. +As with capabilities on general-purpose CPUs, capabilities must be evaluated +with respect to an address space. +In the event that no IOMMU is present, this will be a (possibly ``the'') +physical address space. +With an IOMMU, this will be one of potentially many I/O virtual address +spaces. +As with multiple virtual address spaces on an MMU-enabled general-purpose CPU, +care will need to be taken to ensure that capabilities can be used only in +address spaces where they have appropriate meaning. + +There is a more general question about the \textit{reachability} of all +capabilities: a general-purpose OS can reasonably be expected to find all +available capabilities through awareness of architectural registers and +tag-enabled memory, for the purposes of revocation or garbage collection. +Capabilities held by devices will require additional work to locate or +revoke, and will likely require awareness of the specific device. +This is an area for further research. + +\subsection{Caching and Explicit Prefetch} +\label{sec:caching-and-explicit-prefetch} + +Some architectures (including MIPS, from MIPS-IV onwards) have an explicit +prefetch instruction that gives a hint to the CPU that data at a particular +virtual address might be used in the near future. For performance reasons, +the MIPS prefetch instruction does not raise TLB exceptions. This allows a highly +parallel CPU implementation to start executing the next instruction in the program +without waiting for the TLB check to complete. (Imagine, for example, that +a prefetch is followed by a store to a different address). For similar performance +reasons, with CHERI a \DDC{}-relative prefetch instruction may fail without raising +an exception if the address is outside the range of \DDC{}. On the other hand, +there is a potential covert timing channel if programs are allowed to prefetch +memory addresses to which they do not have access. If a prefetch to the out of +bounds address changed the contents of the memory caches, then another subprogram +(one that did have a capability granting access to the memory address) could +test whether or not the prefetch had happened by doing a load and timing how +long it took. The compromise between performance and security is that prefetch +of an out of bounds address does not raise an exception, but also does not +change the memory caches or (in multicore CPUs) affect the behavior of other cores; +it acts like a no-op. + +Prefetch will typically fetch an entire cache line, not just the address that +has been explicitly prefetched. The question then arises as to what happens +if \DDC{} grants access to the address that is explicitly prefetched, but not +all of the cache line. As prefetch does not raise an exception on failure, it +can silently fail in this case without affecting program correctness (though +there will be a performance penalty). If covert +channels via memory caches are a concern, subsystems that are intended to be +isolated should not share cache lines: ordinary loads, and load-linked/store conditional +also provide opportunities for covert channels via caches. Rounding up a protected subsystem's +memory region to a cache line boundary will mean that the reduced performance case +where part of the cache line is outside the range of \DDC{} will not be encountered. + +To allow explicit prefetch in pure capability mode, a prefetch via capability +instruction may also be added. The security and performance trade-offs are +the same as for prefetch relative to \DDC{}: an out of bounds prefetch can fail +silently without raising an exception, as long as it does not perturb the +memory caches. + +\section{Implications for Software Models and Code Generation} + +\subsection{C and C++ Language and Code Generation Models} + +CHERI capabilities are an architectural primitive that can be used in a +variety of ways to support different aspects of software robustness. +This is especially true because of CHERI's hybrid approach, which supports +incremental deployment within both source languages and code generation. +We have explored three different C and C++ language models: + +\begin{description} +\item[Pure Integer Pointers] In this C-language variant, all pointers are + assumed to be implemented as integer virtual addresses. + +\item[Hybrid Pointers] In this C-language variant, pointers may be implemented + as integer virtual addresses or as capabilities depending on language-level + types or other annotations. + While we have primarily explored the use of a simple qualifier, + \ccode{__capability}, which indicates that a pointer type should be + implemented as a capability, a variety of other mechanisms can or could be + used. + For example, policy for the use of capabilities might be dictated by binary + compatibility constraints: public APIs and ABIs for a library might utilize + integer pointers, but all internal implementation might use capabilities. + +\item[Pure-Capability Pointers] In this C-language variant, all pointers are + implemented as capabilities. +\end{description} + +Alongside these language-level models, we have also developed a set of binary +code-generation and binary interface conventions regarding software-managed +capabilities. +These are similar to those used in non-capability designs, including features +such as caller-save and callee-save registers, a stack pointer, etc. +We have explored three different Application Binary Interfaces (ABIs) that +utilize capabilities to varying degrees: + +\begin{description} +\item[Native ABI] The native ABI(s) for the architecture: capability registers + and capability instructions are unused. + Generated code relies on CHERI compatibility features to interpret integer + pointers with respect to the program-counter and default-data capabilities. + +\item[Hybrid ABI] Capability-aware code makes selective use of capability + registers and instructions, but can transparently interoperate with MIPS-ABI + code when capability arguments or return values are unused. + The programmer may annotate pointers or types to indicate that data pointers + should be implemented in terms of capabilities; the compiler and linker may + be able utilize capabilities in further circumstances, such as for pointers + that do not escape a scope, or are known to pass to other hybrid code. + They may also use capabilities for other addresses or values used in + generated code, such as to protect return addresses or for on-stack + canaries. + The goal of this ABI is binary compatibility with, where requested by the + programmer, additional protection. + This is used within hybrid applications or libraries to provide selective + protection for key allocations or memory types, as well as interoperability + with pure-capability compartments. + +\item[Pure-Capability ABI] Capabilities are used for all language-level + pointers, but also underlying addresses in the run-time environment, such as + return addresses. + The goal of this ABI is strong protection at significant cost to binary + interoperability. + This is used for both compartmentalized code, and also pure-capability + (``CheriABI'') applications. +\end{description} + +\subsection{Object Capabilities} + +\rwnote{This section is a bit out-of-place here, and relates more to the + software model -- but we do need to talk about this somewhere after the + basic architecture is defined. This text is also a bit out-of-date given + our exception-free CCall.} + +As noted above, the CHERI design calls for two forms of capabilities: +capabilities that describe regions of memory and offer bounded-buffer +``segment'' semantics, and object capabilities that permit the +implementation of protected subsystems. +In our model, object capabilities are represented by a pair of sealed +code and data capabilities, which provide the necessary information to implement +a protected subsystem domain transition. +Object capabilities are ``invoked'' using the \insnref{CInvoke} instruction. + +In traditional capability designs, invocation of an object capability triggered microcode +responsible for state management. +Initially, we implemented a pair of \insnnoref{CCall} and +\insnnoref{CReturn} instructions via software exception +handlers in the kernel, but have since refined this model to a single \insnref{CInvoke} which +performs a jump-like operation to minimize overhead. +In the longer term, we hope to investigate the congruence of object-capability invocation with message-passing primitives between architectural threads: if each register +context represents a security domain, and one domain invokes a service offered by +another domain, passing a small number of general-purpose integer and capability +registers, then message passing may offer a way to provide significantly enhanced +performance.\footnote{This appears to be another instance of the isomorphism +between explicit message passing and shared memory design. If we introduce +hardware message passing, then it will in fact blend aspects of both models and +use the explicit message-passing primitive to cleanly isolate the two contexts, +while still allowing shared arguments using pointers to common storage, or +delegation using explicit capabilities. This approach would allow application +developers additional flexibility for optimization.} +In this view, architectural thread contexts, or register files, are simply caches of thread +state to be managed by the processor. + +Significant questions then arise regarding rendezvous: how can messages be +constrained so that they are delivered only as required, and what are the interactions +regarding scheduling? +While this structure +might appear more efficient than a TLB (by virtue of +not requiring objects with multiple names to appear multiple times), it still requires an +efficient lookup structure (such as a TCAM). +\nwfnote{What for?} + +In either instantiation, a number of design challenges arise. +How can we ensure safe invocation and return behavior? +How can callers safely delegate arguments by reference for the duration of the +call to bound the period of retention of a capability by a callee (which is +particularly important if arguments from the call stack are passed by reference)? + +How should stacks themselves be handled in this light, since a single +logical stack will arguably be reused by many different security +domains, and it is undesirable that one domain in execution might +`pop' rights from another domain off of the stack, or reuse a +capability to access memory previously used as a call-by-reference +argument. + +These concerns argue for at least three features: a logical stack spanning many +stack fragments bound to individual security domains, a fresh source of ephemeral +stacks ready for reuse, and some notion of a do-not-transfer facility in order to +prevent the further propagation of a capability (perhaps implemented via a +revocation mechanism, but other options are readily apparent). PSOS explored +similar notions of propagation-limited capabilities with similar motivations. + +\section{Deep Versus Surface Design Choices} +\label{sec:deep-vs-surface} + +\rwnote{Some things to add here: A few more details on compression formats + and variance within the ones we've defined; a bit more on domain + transition; temporal-safety mechanisms; example instruction list; global/ + local capabilities; composition with privilege/rings; other things?} + +In adapting an ISA to implement the CHERI protection model, we find it useful +to contrast between two types of changes: + +\begin{description} +\item[Deep design choices] include the decision to expose capability use and + management for explicit use by the compiler, employing tagged memory to + protect capability values, enforcing monotonicity using limitations on the + instruction set, preventing capability use if its valid provenance has been + violated, and introducing (or extending) registers (including control + registers such as the Program Counter) to hold capability values. + +\item[Surface design choices] reflect to the specific possible integrations + with the target ISA, including the specific blend of instructions and their + encodings, whether the address embedded in a capability is physical or + virtual, whether entirely new registers are used to hold capability values + rather than extending existing registers, the specific number (or mix) of + capability registers, and whether violations of capability provenance or + monotonicity are prevented by an exception being thrown or the tag on the + target of an operation being cleared. +\end{description} + +Further, applications to an ISA are necessarily sensitive to existing choices +in the ISA -- for example, whether and how page tables are represented in the +instruction set, and the means by which exception delivery takes place. +In general, the following aspects of CHERI are fundamental design decisions +that it is desirable to retain in applying CHERI concepts in any ISA: + +\begin{itemize} +\item Capabilities can be used to implement pointers into virtual address + spaces (or physical address spaces for processors without MMUs); +\item Tags on registers or in memory determine whether they are valid + capabilities for loading, fetching, or jumping to; +\item Tagged registers can contain both data + and capabilities, allowing (for example) capability-oblivious memory copies; +\item Tags on capability-sized, capability-aligned units of memory preserve + validity (or invalidity) across loads and stores to memory; +\item Tags are associated with physical memory locations -- i.e., if + the same physical memory is mapped at two different virtual addresses, the + same tags will be used; +\item Attempts to store data (rather than a valid capability) into memory that + has one or more valid tags will atomically clear the tags on any affected + memory; +\item Capability loads and stores to memory offer strong atomicity with + respect to capability values and tags preventing race +conditions + that might yield + combinations of different capability values, or the tag remaining set when + a corrupted capability is reloaded; +\item Capabilities contain bounds and permissions; a capability's address is + able to float freely within (and to varying extents, beyond) the bounds; +\item Permissions control both data and control-flow operations; +\item Guarded manipulation implements monotonicity: rights can be reduced but + not increased through valid manipulations of capabilities; +\item Invalid manipulations of capabilities violating guarded-manipulation rules + lead to an exception or clearing of the valid tag, whether in a register or + in memory, with suitable atomicity; +\item Loads via, stores via, and jumps to capabilities are constrained by their + permissions and bounds, throwing exceptions on a violation; +\item Capability exceptions, in general, are delivered with greater priority + than MMU exceptions; +\item Permissions on capabilities include the ability to not just control + loading and storing of data, but also loading and storing of capabilities; +\item Capability-unaware loads, stores, and jump operations via integer + pointers are constrained by implied capabilities such as the Default Data + Capability and Program Counter Capability, ensuring that legacy code is + constrained; +\item If present, the Memory Management Unit (MMU), whether through extensions + to the software-managed Translation Look-aside Buffers (TLBs), or via + extensions to the page-table entries for hardware-managed TLBs, contains + additional permissions controlling the loading and storing of capabilities; +\item That MMU-enforced permissions may clear tags or throw exceptions if + violated (possibly as configurable option); +\item Strong C-language compatibility is maintained through definitions of + NULL to be untagged, zero-filled memory, instructions to convert between + capabilities and integer pointers, and instructions providing C-compatible + equality operators; +\item Reserved capabilities, whether +in +special registers or within a capability + register file, allow a software supervisor to operate with greater rights + than non-supervisor code, recovering those rights on exception delivery; +\item A simple capability flow-control model to allow the propagation of + capabilities to be constrained; +\item Sealed capabilities allow a non-monotonic escalation of privilege + associated with a constrained control-flow transition to a defined address. + Subject to the use of suitable instructions, and appropriate permissions, a + pair of sealed capabilities with identical object types allow access to + unsealed versions of the capabilities, with code beginning execution at one + of them. + This enables software-enabled behaviors such as software + compartmentalization. +\item Sealed entry capabilities likewise allow non-monotonic escalation of + privilege associated with a constrained control-flow transition to a + defined address. + Subject to use of suitable instructions, and appropriate permissions, a + single sealed entry (sentry) capability allows code to begin execution via + an unsealed version of the same capability. +\item By clearing architecture-defined permissions, and utilizing software-defined + permissions, capabilities can be used to represent spaces other than the + virtual address space; +\item For compressed capabilities, addresses can stray well out-of-bounds + without becoming unrepresentable; +\item For compressed capabilities, alignment requirements do not + restrict common object sizes and do not overly restrict large objects beyond + common limitations of allocators and virtual memory mapping; and +\item That through inductive properties of the instruction set, from the + point of CPU reset, via guarded manipulation, and suitable firmware and + software management, it is not possible to ``forge'' capabilities or + otherwise escalate privilege other than as described by this model and + explicit exercise of privilege (e.g., via saved exception-handler + capabilities, unsealing, etc). +\end{itemize} + +The following design choices are associated with our specific integrations of +the CHERI model into the 64-bit MIPS and 32/64-bit RISC-V ISAs, and might be +revisited in various forms in integrating CHERI support into these or other +ISAs: + +\begin{itemize} +\item Whether capability registers are in their own register file, or + extended versions of existing general-purpose integer registers, as long as tags are + used to control dereferencing capabilities; +\item The number of capability registers present; +\item How capability-related permissions on MMU pages are indicated; +\item How capabilities representing escalated privilege for exception + handlers are stored; +\item Whether specific capability-related failures (in particular, operations + violating guarded manipulation) lead to an immediate exception, or simply + clearing of the tag and a later exception on use; +\item How tags are stored in the memory subsystem -- e.g., whether close to + the DRAM they protect or in a partition of memory -- as long as they are + presented with suitable protections and atomicity up the memory hierarchy; +\item How the instruction-set opcode space is utilized -- e.g., via + coprocessor reservations in the opcode space, reuse of existing instructions + controlled by a mode, etc; +\item What addressing modes are supported by instructions -- e.g., whether + instructions accept only a capability operand as the base address, perhaps + with immediates, or whether they also accept integer operands via + non-capability (or untagged) registers; and +\item The specific parameter choices in capability values, including the + number of dereferenceable bits in the address, the investment of bits in + bounds-related fields (such as the exponent size), the size of the + object-type field, the number of software-defined permissions, and also the + specific in-memory layout. +\item How capabilities are represented microarchitecturally -- e.g., + compressed or decompressed if compression is used; if the base and offset + are stored pre-computed as a cursor rather than requiring additional + arithmetic on dereference; or whether an object-type field is present for + non-sealed in-memory representations. +\end{itemize}\pdrnote{Is it worth adding: Size and interpretation of the \cflags{} field?} + +\section{Potential Future Changes to the CHERI Architecture} + +The following changes have been discussed and are targeted for short-term +implementation in the CHERI architecture: + +\begin{itemize} +\item + Define the values of base, length, and offset for compressed + capabilities with $\cexponent{} > 43$, where the formulas for + decompressing base and top do not make sense due to bit indexes + being out of bounds. This is possible for the default capability + (defined to have $length = 2^{64}$, although $\cexponent{}$ is + unspecified) and untagged data loaded from memory. One proposed + behavior is to treat all untagged compressed capabilities as though + they have $base=0$ and $length=2^{64}$ for the purposes of the + instructions where this matters, namely \insnref{CGetBase}, + \insnref{CGetOffset}, \insnref{CIncOffset}, + \insnref{CGetLen}, \insnref{CPtrCmp} and \insnref{CSub}. + However, there is also a desire that \insnref{CSetOffset} should preserve + the values of $T$ and $B$ for debugging purposes, where possible. + +\item + Consider re-writing pseudocode in terms of absolute addresses rather + than offsets, without changing the semantics. This would eliminate + repeated use of \cbase{} $+$ \coffset{} to mean the address field of the + capability; it would also potentially reduce ambiguity such as where + \cbase{} is not well defined due to $\cexponent{} > 43$ as above. + +\item + Provide a separate instruction for clearing the \emph{global} bit on a + capability. \cappermG is currently treated as a permission, but it is + really an information flow label rather than a permission. We may want to + allow clearing the \cappermG bit on a sealed capability, which would + be easiest to implement with a separate instruction, as permissions cannot + be changed on sealed capabilities. + +\item + Provide multiple orthogonal capability ``colors'', expanding the + local-global features to allow multiple consumers. + We have considered in particular the use of colors to: (1) prevent kernel + pointers from errantly wandering into userspace memory; (2) prevent user + pointers from improperly moving between processes sharing some or all of + their virtual address spaces; (3) prevent pointers from improperly flowing + between intra-process protection domains; and (4) to prevent stack pointers + from being improperly shared between threads. + Section~\ref{sec:compactcolors} elaborates a more efficient representation + for this coloring model, requiring one rather than two bits per color, by + virtue of utilizing a new capability type to authorize color management. + +\item + Allow clearing of software-defined permission bits for sealed + capabilities rather than requiring a domain switch or call to a privileged + supervisor to do this. + One way to do this would be to provide a separate instruction for clearing + the software-defined permission bits + on a sealed capability. The other permission bits on a sealed capability + can be regarded as the permissions to access memory that the called protected + subsystem will gain when \insnref{CInvoke} is invoked on the sealed + capability; these should not be modifiable by the caller. On the other hand, + the software-defined capability bits can be regarded as application-specific + permissions that the caller has for the object that the sealed capability + represents, and the caller might want to restrict these permissions before + passing the sealed capability to another subsystem. + +\item + Provide a \insnnoref{CFromInt} instruction that copies a + general-purpose integer register into the \coffset{} field of a capability register, +clearing all the other fields of the capability -- including the \ctag{} bit. + This is an architecturally cleaner way to implement casting an + \emph{int} to an \emph{intcap\_t} than the current approach of + \insnref{CFromPtr} of the NULL pointer followed by + \insnref{CSetOffset}. + +\item + Provide a variant of \insnref{CSetBounds} that sets imprecise bounds + suitable for sealing with \insnref{CSeal}. In the 128-bit + representation, the bounds of sealed capabilities have stronger alignment + requirements than for unsealed capabilities. + +\item Introduce a \insnref{CTestSubset} instruction, which would allow + efficient testing of whether one capability describes rights that are a + subset of another, directly exposing the partial order implied by subset + tests in \insnref{CToPtr}, the proposed \insnref{CBuildCap}, etc. + This is described in more detail in \cref{\insnlabelname{ctestsubset}}. + +\item + Add versions of \insnref{CSetOffset} and \insnref{CIncOffset} + that raise an exception, rather than clearing the tag bit, when the result + is not representable. This would assist in debugging, by causing an + exception to be raised at the point in the program when the capability + became unrepresentable, rather than later on when the capability is + dereferenced. + + An alternative implementation (rather than having separate trapping and + non-trapping instructions) would be to add a status register that enables + the trapping behavior. This is similar to floating point, where the + FCSR controls whether a floating point overflow results in an IEEE + infinity value or an exception being thrown. + + A cheap tag assertion instruction that can trigger a trap when a tag is lost + would allow special compilation modes to improve debuggability by detecting + unexpected tag loss sooner. + + If MIPS had a user status register, a tag-loss bit could be set implicitly + on tag clear, allowing intermittent conditional-branch instructions to detect + and handle loss. + +\item + Add a version of \insnref{CUnseal} that returns NULL, rather than + raising an exception, if the security checks fail. A common use case + for \insnref{CUnseal} is that a protected subsystem is passed a sealed + capability by an untrusted (possibly malicious) caller, and the callee uses + \insnref{CUnseal} to unseal it. It would be quicker for the callee + to use a non-trapping \insnref{CUnseal} and then check that the result + is not NULL, rather than either (a) catching the exception in the case that + the untrusted caller has passed a bad capability; or (b) checking that + the capability is suitable for unsealing before attempting to unseal it. + +%\item +% Add a \insnnoref{CGetPCCIncOffset} instruction that is similar to +% \insnref{CGetPCCSetOffset}, except that it increments the offset +% instead of setting it. This instruction could be useful (for example) when +% using \insnref{CInvoke}; \insnnoref{CGetPCCIncOffset} would provide +% a convenient way to construct a capability for the return address. +% \arnote{This is included in ISAv8} + +\item + Add instructions for copying non-capability data from a capability register + into a general-purpose integer register. A use case is when a function is called + with a parameter whose type is the union of a pointer and a non-pointer type, + such as an int. This parameter must be passed in a capability register, because + the tag needs to be preserved when it holds a capability. If the body of + the function accesses the non-capability branch of the union, it needs to + get the non-capability bits out of the capability register and into a general + purpose register. This can be done by spilling the capability register to the + stack and then reading it back into a general-purpose integer register, but a register + to register copy would be faster. (We need to investigate whether this happens + often enough for the optimization to be worthwhile). + + With compressed 128-bit capabilities, two instructions are needed (to get + the upper and lower 64 bits of the capability register). + +\item + Add an instruction that is like \insnref{CSetBounds} except that it + sets \cbase{} to the current \cbase{} $+$ \coffset{} and the new length + is the old \clength{} $-$ \coffset{} (i.e., the upper bound is unchanged). + A question that needs to be resolved: what if the requested bounds cannot + be represented exactly? The use case for this instruction is when its + desired to move up the \cbase{} of the capability, without needing to + extra instructions to explicitly calculate the new \clength{}. + +\item + Add an instruction that returns the alignment requirement for memory regions + of a particular size. Having an instruction for this would avoid the + need for memory allocators to know the details of the compression scheme. + +\item Swapping and virtual-machine migration require that tags be stripped + from capabilities as memory is serialized, and that tags be reattached to + capabilities as memory is restored. + Section~\ref{section:capability-reconstruction} describes a set of + experimental instructions that improve the efficiency of these operations, + but also avoid the need for software to directly inspect and interact with + the in-memory representation of capabilities. +\end{itemize} + +The following changes have been discussed for longer-term consideration: + +\begin{itemize} +%\item Investigate a three-capability variation on object capabilities for the +% 128-bit version of CHERI. +% This would provide more bits to be used in describing classes and objects, +% and avoid requiring storing the object type in pointer bits. + +\item Introduce finer-grained permissions (or new capability types) to express + CPU privileges in a more granular way. + For example, to allow management of interrupt-related CPU features without + authorizing manipulation of the MMU. + +\item Introduce a control-flow-focused ``immutable'' (or, more accurately, + ``non-manipulable'') permission bit, which would prevent explicit changes to + the bounds or offset, while still allowing the offset to be implicitly + changed if the capability is placed in execution (i.e., is installed in + \PCC{}. + This would limit the ability of attackers, in the presence of a memory + re-use bug, to manipulate the offset of a control-flow capability in order + to attempt a code re-use exploit. + Some care would be required -- e.g., to ensure that it was easy and + efficient to update the value in the offset during OS exception handling, + where it is common to adjust the value of the \PC{} forward after emulating + an instruction. + +\item Introduce further hardware permissions, such as physical-address load + and store permissions, which would allow non-virtual-address interpretations + of capabilities, bypassing the MMU. + These might be appropriate for use by kernels, accelerators, and DMA engines + there physical addresses (or perhaps hypervisor-virtualised physical + addresses) offer great efficiency or improved semantics. + +\item Consider whether any further instructions require variants that accept + immediate values rather than register operands. + Some already exist (e.g., when setting bounds or offsets, to avoid setting + up integer register operands) but it may also be worth adding others. + For example, if it transpires that permission-masking is a common operation + in some workloads, a new \insnnoref{CAndPermImm} could be added. + +\item Capability linearity, in which the architecture prevents duplication of + a capability, might offer stronger invariants around protection-domain + crossing. + Section~\ref{section:linear-capabilities} describes an experimental proposal + for how this might be implemented. + +\item Today, a uniform set of capability roots are provided: \PCC{}, \DDC{}, + \KCC{}, and possibly other special capability registers, are all + preinitialised to grant all permissions across the full address space. + This is a simple model that is easy to understand, but implies that certain + efficiencies cannot be realized in the in-memory capability representation -- + for example, although sealing, CIDs, and memory access refer to different + namespaces, we cannot efficiently encode +the + lack of overlap to reduce the number of bits in capability representation. +%%%??? + + Moving to multiple independent roots originating in different special + registers would allow these efficiencies to be realized. + For example, by having three different capability roots -- memory + capabilities (with only virtual-address permissions), sealing capabilities + (with only sealing and unsealing permissions), and compartment capabilities + (with only CID permissions). + + A further root could be achieved by introducing a distinction between \PCC{} + authorizing use of the privileged ISA (e.g., MMU configuration) and a special + register used for this purpose. + If a new ``system authorization special register'' were to be added, then a + further System\_Access\_Registers-only root could be introduced, and derived + capabilities could be installed into the special register when those + privileges are required; a NULL capability could be installed when not in + order to prevent use. + +\item Introduce capability-extended versions of virtually indexed + cache-management instructions. + This is important in order to allow compartmentalized DMA-enabled device + drivers to force write-back. + Support for invalidate, however, remains challenging, as invalidate + instructions could cause memory to ``rewind'', for example rolling back + memory zeroing. + This may require some changes around device drivers to avoid the need for + direct use of invalidation instructions by unprivileged device drivers, and + is a topic for further research. +\end{itemize} diff --git a/chap-assurance.tex b/chap-assurance.tex new file mode 100644 index 00000000..2f9d3ca8 --- /dev/null +++ b/chap-assurance.tex @@ -0,0 +1,412 @@ +\chapter{CHERI in High-Assurance Systems} +\label{chap:assurance} + +This chapter considers the roles of formal methods relating to the assurance +of CHERI-MIPS hardware and software. It gives an informal explanation of some +features of the CHERI mechanism that may of interest to developers of +high-assurance hardware, secure microkernels, and formal models of CHERI, +including an initial security argument for a reference monitor. Further +work on proofs of properties of the CHERI ISA and were published in our +IEEE Symposium on Security and Privacy in 2020~\cite{cheri-formal-SP2020}. + +\section{Unpredictable Behavior} + +In the semantics for the CHERI instructions in Chapter \ref{chap:isaref-mips}, +we try +to avoid defining behavior as ``unpredictable''. There were several reasons +for avoiding unpredictable behavior, including the difficulty it creates for +formal verification. +Although CHERI is based on the MIPS ISA, +the MIPS ISA specification (e.g., for the +R4000) makes extensive use of ``unpredictable''. If ``unpredictable'' is +modeled as ``anything could happen'', then clearly the system is not secure. +As a +concrete example, imagine a hypothetical CHERI implementation that contains +a Trojan horse such that when a sandboxed program executes an arithmetic +instruction whose result is ``unpredictable'', it also changes the capability +registers so that a capability granting access to the entire virtual address +space is placed in a capability register. If ``unpredictable'' means that +anything could happen, then this is compliant with the MIPS ISA; it is also +obviously insecure. Later versions of the MIPS ISA (e.g., MIPS64 volume I) make +it clear that ``unpredictable'' is more restrictive than this, saying that +``\emph{unpredictable} operations must not read, write, or modify the contents of +memory or internal state that is inaccessible in the current processor mode''. +However, that is clearly not strong enough. + +For the CHERI mechanism to be secure, we require that programs whose behavior +is ``unpredictable'' according to the MIPS ISA do not modify memory or +capability registers in a way that allows the capability mechanism to be bypassed. +One easy way to achieve this is that the ``unpredictable'' case requires that +neither memory nor capability registers are modified. + +The test suite for our CHERI1 FPGA implementation checks that the CPU follows +known CHERI1-specific behavior in the ``unpredictable'' cases. + +\section{Bypassing the Capability Mechanism Using the TLB} + +If a program can modify the TLB (the status register has CU0 set, KSU not +equal to 2, EXL set or IRL set), then it can bypass the capability mechanism +by modifying the TLB. Although composition with the Memory Management Unit and +virtual-addressing mechanism in this manner is a critical and intentional part +of our design, it is worth considering the implications from the perspective +of high-assurance design. +The ``attack'' is as follows: Consider a location in memory +whose virtual address is not accessible using the capability mechanism; take +its physical address and change the TLB so that its new virtual address is one +to which you have a capability, and then access the data through the new virtual +address. There are several ways to prevent this attack: + +\begin{itemize} +\item +In CheriBSD, user-space programs are unable to modify the TLB (except through +system calls such as \ccode{mmap}), and thus cannot carry out this attack. +This security argument makes it explicit that the security of the capability +mechanism depends on the correctness of the underlying operating system. +However, this may not be adequate for high-assurance systems. +\item +Similarly, a high-assurance microkernel could run untrusted code in user +space, with KSU=2, CU0 false, EXL false, and IRL false. A security proof +for the combined hardware-software system could verify that untrusted code +cannot cause this condition to become false except by reentering the microkernel +via a system call or exception. +\item +A single-address-space microkernel that has no need for the TLB could run on +a CHERI-enabled CPU without a TLB. Our CHERI1 FPGA prototype can be +synthesized in a version without a TLB, and our formal model in the L3 +specification language includes a TLB-less variant. Removing the TLB for +applications that don't need it saves chip area, and removes the risk that the +TLB could be used as part of an attack. +\item +We are considering future extensions to CHERI that would allow the capability +mechanism to be used for sandboxing in kernel mode; these would allow more control +over access to the TLB when in kernel mode. As well as enabling sandboxing of +device drivers in monolithic kernels such as that of CheriBSD, the same mechanism +could also be used by microkernels. +\end{itemize} + +\section{Malformed Capabilities} + +The encoding formats for capabilities can represent values that can never be +created using the capability instructions while taking the initial contents of +the capability registers as a starting point. For example, with compressed +128-bit capabilities, there are bit patterns corresponding to \cbase{} $+$ +\clength{} $> 2^{64}$. +The capability registers are initialized on reset, so there will +never be malformed capabilities in the initial register contents, and +a CHERI instruction will never create malformed capabilities from +well-formed ones. However, DRAM is not cleared on system reset, so that it is +possible that the initial memory might contain malformed capabilities with the +tag bit set. + +Operating systems or microkernels are expected to initialize memory before +passing references to it to untrusted code. (If you give untrusted code a capability that +has the \emph{Load\_Capability} permission and refers to uninitialized memory, +you don't know what rights you are delegating to it.) +This means that untrusted +code should not be in a position to make use of malformed capabilities. + +There are (at least) two implementation choices. An implementation of the CHERI +instructions could perform access-control checks in a way that would +work on both well-formed and malformed capabilities. +Alternatively, the hardware could be +slightly simplified by performing the checks in a way that might behave +unexpectedly on malformed capabilities, and then rely on the capability +mechanism (plus the operating system initializing memory) to guarantee that +they will never become available to untrusted code. + +If the hardware is designed to guard against malformed capabilities, this +presents special difficulties in testing. No program whose behavior +is defined by the ISA specification will ever trigger the case of encountering +a malformed capability. (Programs whose behavior is ``unpredictable'', because +they access uninitialized memory, may encounter them). +However, some approaches to +automatic test generation may have difficulty constructing such tests. + +More generally, however, uninitialized memory might also contain highly +privileged and yet entirely well-formed capabilities, and hence references to +that memory should be given to less trustworthy code only after suitable +clearing. +This requirement is present today for current hardware, as uncleared memory on +boot might contain sensitive data from prior boots, but this requirement is +reinforced in a capability-oriented environment. + +\section{Constants in the Formal Model} + +The L3 language that we used to specify CHERI does not have a notion of +a named constant as distinct from a mutable variable. Fully machine-checked +security proofs may need to prove that some of these constants are in fact +constant. (For example, that it is not possible to bypass the capability +mechanism by changing the CPU's endianness and hence the effect of a capability +dereference, because there is no way to change the endianness). + +\section{Outline of Security Argument for a Reference Monitor} + +The CHERI ISA can be used to provide several different security properties (for +example, control-flow integrity or sandboxing). This section provides the +outline of a security argument for how the CHERI instructions can be used +to implement a reference monitor. + +The Trusted Computer System Evaluation Criteria (``Orange Book'')~\cite{TCSEC} +expressed the requirement for a reference monitor as ``The TCB shall maintain +a domain for its own execution that protects it from external interference or +tampering''. + +The Common Criteria~\cite{CC2012-3} contain a similar requirement: + +\begin{quote} +``ADV\_ARC.1.1D The developer shall design and implement the [target of +evaluation] so that the security features of the [target of evaluation +security functionality] cannot be bypassed.'' + +``ADV\_ARC.1.2D The developer shall design and implement the [target of +evaluation security functionality] so that it is able to protect itself from +tampering by untrusted active entities.'' +\end{quote} + +In this section, we we explain how the CHERI mechanism can be used +to provide this requirement(s), and provides a semi-formal outline of a +proof of its correctness. + +We are assuming that the system operates in an environment where +the attacker does not have physical access to the hardware, so that +hardware-level attacks such as introducing memory errors~\cite{Govinda+03} +are not applicable. +%%%% WE MIGHT ALSO MENTION the A2 best paper from IEEE SS&P 2016 on +%%%% injecting analog circuit malware into the hardware. + +In this section, we do not consider covert channels. There are many +applications where protection against covert channels is not a requirement. +The CHERI1 FPGA implementation has memory caches, which probably could be +exploited as a covert channel. + +The architecture we use to meet this requirement consists of +(a) some trusted code that initializes the CPU and then calls the untrusted + code; and (b) some untrusted code. The CHERI capability mechanism is +used to restrict which memory locations can be accessed by the untrusted +code. +Here, ``trusted'' means +that, for the purpose of security analysis, we know what the code does. The +``untrusted'' code, on the other hand, might do anything. + +The reference monitor consists of the trusted code and the CHERI hardware; and +the ``security domain'' provided for the reference monitor consists of a set of +memory addresses ($S_K$) for the data, code, and stack segments of the trusted +code, together with the CHERI reserved registers. + +Our security requirement of the hardware is that the untrusted code will run +for a while, eventually returning control to the trusted code; and when the +trusted code is re-entered, (a) it will be reentered at one of a small number +of known entry points; (b) its code, data and stack will not have been modified +by the untrusted code; and (c) the reserved capability registers will not have +been modified by the untrusted code. + +This security property provided by the hardware allows us to reason that the +trusted code is still trusted when it is reentered. If its code and data have +not been modified. we can still know what it will do +(to the extent that it is actually trustworthy -- not just ``trusted''), + +The ``cannot be bypassed'' and ``tamperproof'' requirements are here +interpreted as meaning that there is no way within the ISA to modify the +reference monitor's reserved memory or the reserved registers. That is, all +memory accesses are checked against a capability register, and do not succeed +unless the capability permits them. The untrusted code can access memory without +returning control to the trusted code; +however, all of its memory access are mediated +by the capability hardware, which is considered to be part of the reference +monitor. Tampering with the reference monitor by making physical modifications +to the hardware is considered to be out of scope; the attacker is assumed +not to have physical access. + +The proof of this security property proceeds by induction on states. Let the +predicate \emph{SecureState} refer to the following set of conditions: + +\begin{itemize} +\item +CP0.Status.KSU $\neq$ 0 +\item +CP0.Status.CU0 = \algorithmicfalse{} +\item +CP0.Status.EXL = \algorithmicfalse{} +\item +CP0.Status.ERL = \algorithmicfalse{} +\item +The TLB is initialized such that every entry has been initialized; every entry has +a valid page mask; and there is no (ASID, virtual address) pair that matches multiple +entries. +\item +Let $S_U$ be a set of (virtual) memory addresses allocated for use by the untrusted code, +and $T_U$ a set of \cotype{} values allocated for use by the untrusted code. +\item +The set of virtual addresses $S_U$ does not contain an address that maps (under the +TLB state mentioned above) into any of the memory addresses reserved for use +by the trusted code's code, stack or data segments. +\item +The set of virtual addresses $S_U$ does not contain an address that maps (under the +TLB state mentioned above) into the physical address used by a memory-mapped I/O +device. (If this property is weakened to allow some I/O devices to be memory-mapped +by untrusted code, then the security proof has to show that the I/O device can't +be used to break the security property, e.g. by causing the I/O device to DMA +into a region of memory outside of $S_U$). +\item +The set of virtual addresses $S_U$ are all mapped to cached memory. (A load-linked +operation on uncached memory is defined as unpredictable in the MIPS ISA. While +this probably can't be used to attack a real system, any unpredictable behavior +has to prevent for provable security). +\item +All capability registers have \cbase{} $+$ \clength{} $\leq 2^{64}$ +\algorithmicor{} \ctag{} $=$ \algorithmicfalse{}. +\item +The above is also true of all capabilities contained within the set of memory +addresses $S_U$. +\item +All capability registers are either (a) reserved registers; (b) have \ctag{} = +\algorithmicfalse{}; (c) are sealed with an \cotype{} not in $T_U$; or do not +grant \emph{Access\_System\_Registers} permission. +\item +The above is also true of all capabilities contained within the set of memory +addresses $S_U$. +\item +All capability registers are either (a) reserved registers; (b) have \ctag{} = +\algorithmicfalse{}; (c) are sealed with an \cotype{} not in $T_U$; or do not +grant access to a region of virtual addresses outside of $S_U$. +\item +The above is also true of all capabilities contained within the set of memory +addresses $S_U$. +\item +All capability registers are either (a) reserved registers; (b) have \ctag{} = +\algorithmicfalse{}; (c) are sealed with an \cotype{} not in $T_U$; or do not +grant access to a region of the \cotype{} space outside of $T_U$. +\item +The above is also true of all capabilities contained within the set of memory +addresses $S_U$. +\item +If the current instruction is in a branch delay slot, then the above restrictions +on capability registers also apply to the \PCC{} value that is the target of the +branch. That is, \emph{SecureState} is not true if the trusted code does a +\insnref{CJR} that grants privilege and then runs the first instruction of +the untrusted code in the branch delay slot. +\end{itemize} + +Let the predicate \emph{TCBEntryState} refer to a state in which the trusted code +has been reentered at one of a small number of known entry points. + +We assume that \emph{SecureState} is true initially (i.e., +a requirement of +the trusted code is that it puts the CPU into this state before calling the +untrusted code). +We then wish to show that \emph{SecureState} $\Rightarrow$ \textbf{X} + (\emph{SecureState} \algorithmicor{} \emph{TCBEntryState}) (where \textbf{X} is +the next operator in linear temporal logic). By induction on states, +\emph{SecureState} $\Rightarrow$ \emph{TCBEntryState} \textbf{R} \emph{SecureState} +(where \textbf{R} is the release operator in linear temporal logic). + +The argument that \emph{SecureState} $\Rightarrow$ \textbf{X} (\emph{SecureState} +\algorithmicor{} \emph{TCBEntryState}) can be summarized as: + +\begin{itemize} +\item +Given that CP0.Status.KSU $\neq$ 0, CP0.Status.CU0 = \algorithmicfalse{}, +CP0.Status.EXL = \algorithmicfalse{} and CP0.Status.ERL = \algorithmicfalse{}, +all instructions will either raise an exception (\textbf{X} +\emph{TCBEntryState}) or leave CP0 registers unchanged, leaving this +part of the \emph{SecureState} invariant unchanged. +\item +Given that CP0.Status.KSU $\neq$ 0 (etc.), all instructions will +either raise an exception or leave the TLB unchanged, preserving the parts of +\emph{SecureState} relating to the TLB. +\item +Given that the TLB is in the state given by \emph{SecureState}, load and store +operations will not result in ``undefined'' or ``unpredictable'' behavior due +to multiple matches in the TLB. +\item +Given that CP0.Status.KSU $\neq$ 0 (etc.), and the TLB is in the state +described above, no instruction can result in +behavior that is ``undefined'' according to the MIPS ISA. (The MIPS ISA +specification makes a distinction between ``undefined'' and ``unpredictable'', +but our model in the L3 language combines the two). +\item +However, instructions can still result in behavior that is ``unpredictable'' +according to the MIPS ISA. These cases can be dealt with by providing a +CHERI-specific refinement of the MIPS ISA (i.e. describing what CHERI does in +these cases). +\item +The capability instructions preserve the part of \emph{SecureState} that +relates to the capability registers and to capabilities within $S_U$. +\item +Given that the capability registers (apart from reserved registers) do not grant +access to any memory addresses outside of $S_U$, store instructions might raise +an exception (\textbf{X} \emph{TCBEntryState}), but they will not modify locations +outside of $S_U$; thus, the trusted code's data, code and stack segments + will be unmodified. +\item +Given that the capability registers (apart from the reserved registers) do +not grant \emph{Access\_System\_Registers} permission, the reserved +registers will not be modified. +\end{itemize} + +The theorem \emph{SecureState} $\Rightarrow$ \emph{TCBEntryState} \textbf{R} +\emph{SecureState} uses the \textbf{R} operator, which is a weak form of +``until'': the system might continue in \emph{SecureState} indefinitely. +Sometimes it is desirable to have the stronger property that +\emph{TCBEntryState} is guaranteed to be reached eventually. This can be +ensured by having the trusted code enable timer interrupts, and use a +timer interrupt to force return to \emph{TCBEntryState} if the untrusted +code takes too long. + +More formally, the following properties are added to \emph{SecureState} +to make a new predicate, \emph{SecureStateTimer}: + +\begin{itemize} +\item +CP0.Status.IE = \algorithmictrue{} +\item +CP0.Status.IM(7) = \algorithmictrue{} +\end{itemize} + +Given that CP0.Status.KSU $\neq$ 0 (etc.), it follows that these properties +are also preserved, i.e. +\emph{SecureStateTimer} $\Rightarrow$ \emph{TCBEntryState} \textbf{R} +\emph{SecureStateTimer}. + +As CP0.Count increases by at least one for every instruction, a timer interrupt +will eventually be triggered. (If Compare is 2, for example, and Count +increments from 1 to 3 without ever going through the intervening value of 2, +a timer interrupt is still triggered). As CP0.KSU $\neq$ 0, CP0.Status.EXL += \algorithmicfalse{}, CP0.Status.ERL = \algorithmicfalse{}, CP0.Status.IE = +\algorithmictrue{} and CP0.Status.IM(7) = \algorithmictrue{}, the interrupt +will be enabled and return to \emph{TCBEntryState} will occur: + +\emph{SecureStateTimer} $\Rightarrow$ \textbf{F} \emph{TCBEntryState} + +It then follows that \emph{SecureStateTimer} $\Rightarrow$ +\emph{SecureStateTimer} \textbf{U} \emph{TCBEntryState}, where +\textbf{U} is the until operator in linear temporal logic. + +\section*{Illicit Information Flows} + +Using an argument similar to the one in the preceding section, it ought +to be possible to formally prove confidentiality properties of the CHERI ISA. +However, proofs of confidentiality suffer from the ``refinement paradox'': +confidentiality properties are not preserved by refinement. If there is +any non-determinism in a specification, a refinement of it might leak +secret information via values that were originally left unspecified. + +In more concrete terms, an implementation of the CHERI ISA might leak secret +information due to security problems at the microarchitectural level. + +The Common Criteria~\cite{CC2017-1} uses the term ``covert channel'' (alternatively, +``illicit information flow'') for cases where it is possible to use +features of the implementation to signal information in a way that is +prohibited by the security policy. + +The most obvious potential source of a covert channel in CHERI is using the +memory caches as a timing channel. Meltdown~\cite{Lipp2018meltdown} and +Spectre~\cite{Kocher2018spectre} are examples of realistic attacks against +a CPU's memory protection using the cache as a timing channel. +Subsequently, the related Foreshadow attacks have been reported~\cite{Foreshadow,Foreshadow-NG}. + +To reduce the risk of an attack similar to Meltdown, implementations of CHERI +should perform MMU and capability permissions checks before a store or load, +rather than speculatively executing the load and store before all capability +checks have completed: tag violation, bounds check, permissions check, seal +check, and so on. diff --git a/chap-cheri-mips.tex b/chap-cheri-mips.tex new file mode 100644 index 00000000..ee9a06ea --- /dev/null +++ b/chap-cheri-mips.tex @@ -0,0 +1,847 @@ +\chapter{The CHERI-MIPS Instruction-Set Architecture} +\label{chap:cheri-mips} + +Having considered the software-facing semantics and architecture-neutral +aspects of the CHERI protection model in previous chapters, we now turn to +elaborating CHERI capabilities within a specific RISC architecture: 64-bit +MIPS. +Wherever possible, CHERI-MIPS implements the architecture-neutral concepts +described in Chapter~\ref{chap:architecture}. +In addition to the mechanics of defining specific instructions and choices +about whether a new register file is used (vs. extending the existing integer +register file), MIPS differs substantially from other RISC ISAs in several +key areas -- especially in its use of a software-managed Translation Look-aside +Buffer (TLB), and in the details of its exception mechanism. +In those cases, we necessarily take a MIPS-oriented perspective. +This chapter specifies the following aspects of CHERI-MIPS: + +\begin{itemize} +\item Coprocessor 2 instructions +\item Architectural capabilities +\item Special capability registers +\item The capability register file +\item Capability-aware instructions +\item Capability state on CPU reset +\item Exception handling and capability-related exceptions +\item Changes to MIPS ISA processing +\item Changes to the Translation Look-aside Buffer (TLB) +\item Protection-domain transition with \insnmipsref{CInvoke} +\item Capability register conventions and the Application Binary Interface (ABI) +\end{itemize} + +\noindent +The chapter finishes with a discussion of potential future directions for +the CHERI-MIPS ISA. +Detailed descriptions of specific capability-aware instructions can be found +in Chapter~\ref{chap:isaref-mips}. + +\section{The CHERI-MIPS ISA Extension} + +CHERI-MIPS extends 64-bit MIPS with a new \textit{tagged capability register +file} able to hold both valid capabilities and data, and \textit{tagged + memory} +to distinguish and protect capabilities. It +adds new \textit{capability instructions} that inspect, manipulate, and +use \textit{capability registers}. +CHERI-MIPS also modifies certain existing MIPS architectural behaviors, such +as relating to existing MIPS memory accesses, the program counter, exception +delivery, and the software-managed TLB. +New instructions are added using the coprocessor-2 portion of the MIPS opcode +space, which is intended for local vendor extensions. +Despite this MIPS-originated nomenclature, microarchitectural implementations +of CHERI will be tightly integrated with the main pipeline, rather than as a +separate ``coprocessor''. +Wherever possible, CHERI-MIPS inherits its behavior from the +architecture-neutral specification found in Chapter~\ref{chap:architecture}; +however, in some cases must extend it -- e.g., by defining MIPS-specific aspects of +architectural privilege. + +\section{Architectural Capabilities} + +In CHERI-MIPS, capabilities may be held in a dedicated capability register +file, where they can be manipulated or dereferenced using capability +coprocessor instructions, in a set of special capability registers, and in +tagged memory. +Capabilities in the capability register file may be used as operands to +capability instructions that retrieve or modify capability contents, namely, +load and store instructions, and control-flow instructions. +Capability addresses used for load, store, and instruction fetch are always +interpreted as virtual addresses. +Special capability registers are accessed via new read- and write-register +instructions. +Guarded manipulation and tagged memory enforce capability unforgeability, +capability monotonicity, provenance validity, and capability integrity. + +\subsection{Capability Permissions} + +Architecture-neutral capability permission bits are described in +Section~\ref{sect:capability-permission-bits}; the following permissions +have CHERI-MIPS-specific interpretations: + +\begin{description} +\item[\cappermASR{}] Allow access to \EPCC{}, \ErrorEPCC{}, \KDC{}, \KCC{}, +\KRC{}, \KQC{} and \capcausereg{} when this permission is set in \PCC{}. +Also authorize access to kernel features such as the TLB, CP0 registers, and +system-call return (see Section~\ref{changes-to-MIPS-ISA}). +\end{description} + +\subsection{Capability Flags} + +In CHERI-MIPS, the \cflags{} field has size 0. + +\section{Capability Registers} + +CHERI supplements the 32 general-purpose per-hardware-thread integer registers +provided by the MIPS ISA with 32 additional general-purpose capability +registers. +Where general-purpose integer registers describe data values operated on by a +software thread, capability registers describe its instantaneous rights within +an address space. +A thread's capabilities potentially imply a larger set of rights (loadable via +held capabilities) which may notionally be considered as the protection domain +of a thread. + +Unlike general-purpose integer registers, capability registers are structured, +consisting of a 1-bit tag and a 128-bit set of architectural fields +with defined semantics and constrained values. +Capability instructions retrieve and set these fields by moving values in and +out of general-purpose integer registers, enforcing constraints on field manipulation. + +\section{Special Capability Registers} + +There are also several special capability registers associated with each +architectural thread, including a memory capability that corresponds to the +instruction pointer, and capabilities used during exception handling. +This is structurally congruent to implied registers and system control +coprocessor (CP0) registers found in the base MIPS ISA. +Special instructions are used to move special capabilities in and out of +general-purpose capability registers. + +\section{The Capability Register File} + +\rwnote{This section, lifted from an earlier ISA chapter, has some material + that is redundant with respect to the prior section, and requires merging.} + +\begin{table} +\begin{center} +\begin{tabular}{lp{11cm}} +\toprule +Register(s) & Description \\ +\midrule + \creg{NULL} (\creg{0}) & A capability register that returns the NULL value when +read. Writes to \creg{NULL} are ignored. \\ + \creg{1}...\creg{25} & General-purpose capability registers referenced + explicitly by capability-aware instructions\\ + \IDC{} (\creg{26}) & Invoked data capability: the capability that was unsealed + at the last protected procedure call \nwfnote{Can we think of boot as a + primordial CInvoke?}\ajnote{given that we moved everything else to special + registers, I was wondering whether moving this as well would make sense, or + if one CReadHwr on protection domain entry is not a good idea. It's a bit + awkward to have this random register in the middle be overwritten on + ccall...}\\ + \creg{27}...\creg{31} & General-purpose capability registers referenced + explicitly by capability-aware instructions\\ +\bottomrule +\toprule + Special Register(s) & Description \\ +\midrule + \PCC{} & Program counter capability (\PCC): the capability through which \PC{} + is indirected by the processor when fetching instructions.\\ + \DDC{} & Capability register through which all non-capability load and store + instructions are indirected. This allows legacy MIPS code to be controlled + using the capability coprocessor. \\ + \KRC{} & A capability reserved for use during kernel exception + handling. \\ + \KQC{} & A capability reserved for use during kernel exception + handling. \\ + \KCC{} & Kernel code capability: the code capability moved to \PCC{} when + entering the kernel for exception handling.\\ + \KDC{} & Kernel data capability: the data capability containing the security + domain for the kernel exception handler. \\ + \EPCC{} & Capability register associated with the exception program counter + (\EPC{}) required by exception handlers to save, interpret, and store the + value of \PCC{} at the time the exception fired.\\ + \ErrorEPCC{} & Capability register associated with the error exception program counter + (\ErrorEPC{}) that is used on exception return if CP0.Status.ERL is set. The CHERI prototype + does not actually support any exception types (e.g. cache error) that require \ErrorEPC{} but + it is supported for consistency with MIPS. \\ +\bottomrule +\end{tabular} +\end{center} +\label{table:capability-registers} +\caption{Capability registers defined by the capability coprocessor. See +\insnmipsref{CReadHwr}~(\ref{\insnmipslabelname{creadhwr}}) and +\insnmipsref{CWriteHwr}~(\ref{\insnmipslabelname{cwritehwr}}) for details +on special capability registers.} +\end{table} + +In CHERI-MIPS, the general-purpose capability register file is distinct from +the general-purpose integer register file. +Table~\ref{table:capability-registers} illustrates capability registers +defined by the capability coprocessor. +CHERI-MIPS defines 31 general-purpose capability registers, which may be named using +most capability register instructions. +These registers are intended to hold the working set of rights required by in-execution +code, intermediate values used in constructing new capabilities, and copies of capabilities +retrieved from \EPCC{} and \PCC{} as part of the normal flow of code execution, which is congruent with current MIPS-ISA exception handling via coprocessor 0. +In addition to the 31 general-purpose capability registers, \creg{0} is a constant NULL capability\footnote{For some instructions, specifying a register operand of 0 will utilize \DDC{} rather than \creg{0}. This can reduce the instruction count for certain sequences such as capability loads and stores in a hybrid compiler mode.}. +The special capability registers (other than \PCC) can be read using the \insnmipsref{CReadHwr} instruction and set using the \insnmipsref{CWriteHwr} instruction, subject to suitable permission. + +Each capability register also has an associated tag indicating whether it +currently contains a valid capability. Any load, store, or instruction +fetch via an invalid capability will trap. + +\section{Capability-Aware Instructions} + +Per Section~\ref{sec:capability-aware-instructions}, CHERI-MIPS introduces a +number of new capability-related instructions. +Many are ``portable'' CHERI instructions, but others are MIPS-specific either +in terms of augmenting the existing instruction set (congruent +capability-based jump, load, and store instructions), or to address +MIPS-specific interactions with CHERI (e.g., as relates to exception +handling). +CHERI-MIPS introduces the following control-flow and memory-access instruction +classes: + +\begin{description} +\item[Load or store via a capability] +These instructions access memory indirected via an explicitly named capability +register, and include a full range of access sizes (byte, half word, word, +double word, capability), optional sign extension for loads, and +load-linked/store-conditional variations to implement atomic operations: +\insnmipsref[clbhwd]{CL[BHWD][U]}, \insnmipsref{CLC}, +\insnmipsref[csbhwd]{CS[BHWD]}, \insnmipsref{CSC}, +\insnmipsref[cllbhwd]{CLL[BHWDC][U]}, \insnmipsref{CLLC}, +\insnmipsref[cscbhwd]{CSC[BHWD]}, and \insnmipsref{CSCC}. + +\item[Capability jumps] +These instructions jump to an explicitly named capability register, setting +the program-counter capability to the value of the capability operand: +\insnmipsref{CJR} and \insnmipsref{CJALR}. +These correspond in semantics to the MIPS \insnnoref{JR} jump, used for +function returns, and \insnnoref{JALR}, used for function calls, but +constrained by the properties of the named capability including permissions, +bounds, validity, and so on. +\end{description} + +\noindent +CHERI-MIPS introduces the following capability-aware instructions to +cater to architecture-specific aspects of the MIPS ISA: + +\begin{description} +\item[Conditional move] +The \insnmipsref{CMovN} and \insnmipsref{CMovZ} instructions conditionally +move a capability from one register to another, permitting conditional +behavior without the use of branches. +These support efficient hybrid code, in which use of integer pointers and +capabilities are intermixed. + +\item[Retrieve program-counter capability] +These instructions retrieve the architectural program-counter capability, +and optionally modify its offset for the purposes of \PCC{}-relative +addressing: \insnmipsref{CGetPCC}, \insnmipsref{CGetPCCSetAddr}, \insnmipsref{CGetPCCIncOffset} and \insnmipsref{CGetPCCSetOffset}. + +\item[Exception handling] +The \insnmipsref{CGetCause} and \insnmipsref{CSetCause} instructions get and +set capability-related exception state, such as the cause of the current +exception. + +\item[Get and set special capability registers] +The \insnmipsref{CReadHWR} and \insnmipsref{CWriteHWR} instructions get and set +special capability registers such as \DDC{}, \EPCC{}, \KDC{}, and \KCC{}. +\end{description} + +\section{Capability State on CPU Reset} + +Section~\ref{sec:capability-state-on-cpu-reset} requires that capability root +registers be initialized to offer full capability rights; all other registers +are initialized to NULL. +The capability roots in CHERI-MIPS are \PCC{}, \KCC{}, \EPCC{}, \ErrorEPCC{}. +These values allow capability-unaware code to load and store data with respect +to the full virtual address space, and for exception handling to operate with +full rights. +All other general-purpose and special capability registers should contain the +NULL value. + +In our CHERI-MIPS hardware prototype, all tags in physical memory are +initialized to 0, ensuring that there are no valid capabilities in memory on +reset. +This is not strictly required: the firmware, hypervisor, or operating system +can in principle ensure that tags are cleared on memory before it is exposed +to untrustworthy software, in much the same way that they will normally ensure +that memory is cleared to prevent data leaks before memory reuse. + +\section{Exception Handling} + +As described in Section~\ref{sec:traps_interrupts_exception_handling}, CHERI +adopts and extends the existing exception model of its host architecture. +CHERI-MIPS retains the same general model found in MIPS, with modest +extensions to provide exception handlers with both code and data capabilities, +as well as allow the interrupted capability-extended context to be saved and +restored. + +\subsection{Exception-Related Capabilities} + +MIPS exception handling saves interrupted state, transfers control to an +exception vector, and also grants supervision privilege in the ring model. +CHERI-MIPS extends this model so that the exception handler also gains access +to additional code and data capabilities (\KCC{} and \KDC{}) to authorize its +execution. + +In order to preserve the full interrupted \PCC{}, \EPC{} has been extended +from a special integer register to a special capability register, \EPCC{}. +Accessing the existing MIPS CP0 \EPC{} special register in effect accesses the +\coffset{} field of \EPCC{}. + +When an exception occurs, the victim \PCC{} is copied to \EPCC{} so that the +exception may return to the correct address, and \KCC{}, leaving aside its +\coffset{} field, which will be set to the appropriate MIPS exception-vector +address, is moved to \PCC{} to grant execution rights for kernel code. + +Access to \KDC{}, the Kernel Data Capability, is authorized by +System\_Access\_Registers, and can be used to reach exception-handler data. +\KCC{} will normally be configured to grant this access, if \KDC{} is used. +Exception handlers making use of legacy loads and stores will most likely +install \KDC{} in \DDC{}. +\DDC{}, as with other special registers, will need to be saved and restored to +implement full context switching. + +When an exception handler returns with \insnnoref{ERET}, \EPCC{} (or \ErrorEPCC{} if CP0.Status.ERL is set), possibly after +having been updated by the software exception handler, is moved into \PCC{}. + +\subsection{Exception Temporary Special Registers} + +In the MIPS ABI, two general-purpose integer registers are reserved for use +by exception handlers: \regname{k0} and \regname{k1}. +In earlier CHERI-MIPS revisions, we made a similar design choice for the +capability register file, reserving two general-purpose capability registers for exception-handling +use. +In more recent revisions, we have defined two special capability +registers, \KRC{} and \KQC{}, which are accessible only when +Access\_System\_Registers is present on \PCC{}, and can be used to hold values +during exception handling -- for example, to temporarily save the value of a +general-purpose capability register so that it can be used to hold \KDC{} +during context save. + +\subsection{Capability-Related Exceptions and the Capability Cause Register} + +CHERI-MIPS implements a \capcausereg{} register that gives additional +information about the causes of capability-related exceptions. +The register is formatted as shown in Figure~\ref{fig:cap-cause}. +The \emph{ExcCode} field holds the capability exception code +as described in Section~\ref{sec:capability_exception_causes}. +If the last instruction to throw an exception did not throw a capability +exception, then the \emph{ExcCode} field of \capcausereg{} will be \emph{None}. +\emph{ExcCode} values from 128 to 255 are reserved for use by application +programs. +\jhbnote{Do we still want to reserve 128 to 255 in this way? Or + should we deprecate that along with CSetCause now that CCall 0 is gone?} + +\begin{figure} +\begin{center} + \begin{bytefield}{16} + \bitheader[endianness=big]{0,7,8,15}\\ + \bitbox{8}{ExcCode} + \bitbox{8}{RegNum} + \end{bytefield} +\end{center} +\caption{Capability Cause Register} +\label{fig:cap-cause} +\end{figure} + +The \emph{RegNum} field of \capcausereg{} will hold the number of the capability +register whose permission was violated in the last exception, if this +register was not the unnumbered register \PCC{}. If the capability exception +was raised because \PCC{} did not grant access to a numbered reserved register, +then \capcausereg{} will contain the number of the reserved register to which +access was denied. If the exception was raised because \PCC{} did not +grant some other permission (e.g., permission to read \capcausereg{} was +required, but not granted) then \emph{RegNum} will hold 0xff. + +The \insnmipsref{CGetCause} instruction can be used by an exception handler to +read the \capcausereg{} register. +Software can use \insnmipsref{CSetCause} to set \emph{ExcCode} to either an +architectural or software-defined value. +\insnmipsref{CGetCause} and \insnmipsref{CSetCause} will raise an exception +if \PCC{}.\cperms{}.\emph{Access\_System\_Registers} is not set, allowing +control over whether unprivileged code can access \capcausereg{}. + +When an attempted operation, prohibited by the capability mechanism, triggers +an exception, the \textit{ExcCode} field within the \causereg{} +register of coprocessor 0 are set to 18 (\textit{C2E}, coprocessor 2 +exception), and the \textit{ExcCode} field within the \capcausereg{} will be set to a constant from +Table~\ref{table:capability-cause}. +The \emph{RegNum} field of \capcausereg{} is set to the register which caused +the reported exception. + +If an instruction throws more than one capability exception with the +same priority (e.g., both the source and destination register are +reserved registers), then the register that is furthest to the left in +the assembly language opcode has priority for setting the \emph{RegNum} field. + +\subsection{Exceptions and Indirect Addressing} + +If an exception is caused by the combination of the values of a capability +register and a general-purpose integer register (e.g., if an expression such as +\texttt{clb t1, t0(c0)} raises an exception because the offset \texttt{t0} is +trying to read beyond \texttt{c0}'s length), the number of the capability register +(not of the general-purpose integer register) will be stored in \capcausereg{}.\emph{RegNum}. + +\subsection{Capability-Related Exception Priority} + +In CHERI-MIPS, capability exceptions have a lower priority than Reset, Soft +Reset, and Non-Maskable Interrupt (NMI) but higher priority than all other +exception types. +In particular, they have a priority higher than address errors (e.g., +alignment exceptions, reported by \texttt{AdEL} and \texttt{AdES}) and TLB +exceptions, as capability processing for addresses occurs logically ``before'' +dereference of a virtual address. +With respect to the capability cause register provided via \capcausereg{}, +CHERI-MIPS implements the exception priority scheme described in +Section~\ref{sec:capability_exception_priority}. + +\subsection{Implications for Pipelining} + +MIPS is unusual as an architecture in that the privileged supervisor mode can +explicitly see the effects of pipeline hazards. +System software must issue suitable NOPs and barriers to ensure that +potentially confusing (and even insecure) implications of pipelining are not +visible to application software. +For example, MIPS normally requires a specific number of NOP instructions +follow any writes to TLB-related registers before the effects of those writes +are visible to software. +In general, CHERI does not change this behavior: general-purpose capability +registers experience no visible pipelining effects in normal use; and where +existing pipelining effects exist, such as in accessing \EPC{}, similar +assumptions should be made about capability-extended registers, such as +\EPCC{}. + +\section{Changes to MIPS ISA Processing} +\label{changes-to-MIPS-ISA} + +\rwnote{There is a blend of MIPS-specific and architecture-neutral content + here.} + +The following changes are made to the behavior of instructions from the +standard MIPS ISA when a capability coprocessor is present: + +\paragraph{Instruction fetch} +The MIPS-ISA program counter (\PC{}) is extended to a full program-counter +capability (\PCC{}), which incorporates the historic \PC{} as +\PCC{}.\coffset{}. +Instruction fetch is controlled by the \emph{Permit\_Execute} permission, as +well as bounds checks, tag checks, and a requirement that the capability not +be sealed. +Failures will cause a coprocessor 2 exception (\textit{C2E}) to be thrown. +In general, instructions that set \PCC{} (such as \insnmipsref{CJR}) prohibit +setting invalid values with the notable exception of \insnnoref{ERET}. +This is because \insnnoref{ERET} will typically be used in the kernel's +exception return routine where triggering an exception could be difficult +to recover from. +If an \insnnoref{ERET} occurs with an invalid \EPCC{} the relevant exception is raised +on the following instruction fetch, just as returning to an invalid \PC{} would +trigger a TLB fault on the next instruction fetch in MIPS. +Note that \EPCC{} for the resulting exception will not have changed. This is particularly +important if \EPCC{} was sealed. + +If an address exception occurs during instruction fetch (e.g., AdEL, or a TLB miss) +then \emph{BadVAddr} is set equal to \PCC{}.\cbase{} + \PCC{}.\coffset{}, +providing the absolute virtual address rather than a \PCC{}-relative virtual +address to the supervisor, avoiding the need for capability awareness in TLB +fault handling. + +\paragraph{Load and Store instructions} +Standard MIPS load and store instructions are interposed on by the {\em +default data capability}, \DDC{}. +Addresses provided for load and store will be transformed and bounds checked by +\DDC{}.\cbase{}, \DDC{}.\coffset{}, and \DDC{}.\clength{}. +\DDC{} must have the appropriate permission (\textit{Permit\_Store} or +\textit{Permit\_Load}) set, the full range of addresses covered by the load or +store must be in range, \DDC{}.\ctag{} must be set, and \DDC{} must not be sealed +(i.e., \DDC{}.\cotype{} must be $2^{64}-1$). +Failures will cause a coprocessor 2 exception (\textit{C2E}) to be thrown. +As with instruction fetch, \emph{BadVAddr} values provided to the supervisor +will be absolute virtual addresses, avoiding the need for capability awareness +in TLB fault handling. + +Standard MIPS load and store instructions will raise an exception if the +value loaded or stored is larger than a byte, and the virtual address is +not appropriately aligned. With the capability coprocessor present, this +alignment check is performed after adding \DDC{}.\cbase{}. (\DDC{}.\cbase{} +will typically be aligned, so the order in which the check is performed will +often not be visible. In addition, CHERI1 can be built with an option to +allow unaligned loads or stores as long as they do not cross a cache line +boundary). + +\paragraph{Floating-point Load and Store instructions} +If the CPU is configured with a floating-point unit, all loads and stores +between the floating-point unit and memory are also relative to +\DDC{}.\cbase{} and \DDC{}.\coffset{}, and are checked against the +permissions, bounds, tag, and sealed state of \DDC{}. + +\paragraph{Jump and branch instructions} +If the target is out-of-bounds in relation to \emph{\PCC{}}, a coprocessor 2 +exception (\textit{C2E}) will be thrown. +The \emph{RegNum} field of \capcausereg{} will indicate a \PCC{} exception, and +\emph{ExcCode} will indicate a Length Violation. +\EPC{} and \EPCC{} will point to the branch instruction and not the branch +target (as in previous CHERI revisions). This is better for debugging +and removes the need for a special case for handling the situation where EPCC +is not representable due to capability compression. \note{rmn30}{TODO check we are consistent about this everywhere.} + +\paragraph{Jump and link register} +After a \insnnoref{JALR} instruction, the return address is relative +to \emph{\PCC{}.\cbase}. + +\paragraph{Exceptions} +The MIPS exception program counter (\EPC{}) is extended to a full exception +program-counter capability (\EPCC{}), which incorporates the historic \EPC{} +as \EPCC{}.\coffset{}. +If an exception occurs while CP0.Status.EXL is false, \PCC{} will be +saved in \EPCC{} and the program counter will be saved in \EPCC{}.\coffset{} +(also visible as \EPC{}). If CP0.Status.EXL is true, then \EPCC{} and \EPC{} are unchanged. +(In the MIPS ISA, exceptions leave \EPC{} unchanged if CP0.Status.EXL is true). +After saving the old \PCC{} the contents of the {\em kernel code +capability} (\KCC{}), excluding \KCC{}.\coffset{}, are moved into \PCC{}. +\PC{} (and \PCC.\coffset{}) will be set so that \PCC{}.\cbase{} $+$ +\PC{} is the exception vector address normally used by MIPS. +This allows the exception handler to run with the permissions granted by +\KCC{}, which may be greater than the permissions granted by \PCC{} before +the exception occurred. + +On return from an exception (\insnnoref{ERET{}}), \PCC{} is restored from +\EPCC{} (or \ErrorEPCC{} if Status.ERL is set in CP0). +The program counter is restored +from the \coffset{} field. +This allows exception handlers that are not aware of capabilities to continue +to work on a CPU with the CHERI-MIPS extensions. +If \EPCC{} is not appropriate for execution, the target will +throw the relevant exception in response to an unusable \PCC{}. +Similarly, the result of an exception or interrupt is \textbf{UNDEFINED} if +\KCC{}.\ctag{} is not set, \KCC{} is sealed, or \KCC{} does not have the +execute permission. + +The legacy MIPS instructions \insnnoref{DMFC0} and +\insnnoref{DMTC0} can +be used to read or write the \coffset{} of \EPCC{} and \ErrorEPCC{} +as \EPC{} and \ErrorEPC{} respectively. Note +that we must prohibit modification of sealed capabilities and, if +capability compression is being used (see Section~\ref{compression}), cope +with the possibility of an unrepresentable result. +An attempt to modify a sealed \EPCC{} or \ErrorEPCC{} using +\insnnoref{DMTC0} +results in the tag being cleared. +If \EPC{} is set so far outside the bounds of \EPCC{} that the bounds would no longer +be representable, then the tag is cleared and other fields are set as per \insnmipsref{CSetOffset}. +An unrepresentable \EPCC{} cannot occur as a result of an exception because the \PC{} +should always be within the bounds of \PCC{} or nearly in bounds: +branches outside \PCC{} bounds should throw an exception on the branch instruction, +and if execution runs off the end of +\PCC{} then the resulting \EPCC{} will have an offset just 4 more than +the top of \PCC{} so is guaranteed to be representable. + +\paragraph{CP0, TLB, CACHE, and ERET privileges} +The set of MIPS privileges normally reserved for use only in kernel mode, +including the ability to read and write CP0 control registers (using +\insnnoref{MFC0}, \insnnoref{MTC0}, \insnnoref{DMFC0}, and +\insnnoref{DMTC0}), manage the TLB (using \insnnoref{TLBR}, +\insnnoref{TLBWI}, \insnnoref{TLBWR}, and \insnnoref{TLBP}), perform +\insnnoref{CACHE} operations that could lead to data loss or rollback of +stores, and use the \insnnoref{ERET} exception-return instruction, is +available only if \PCC{} contains the Access\_System\_Registers permission AND +the CPU is running in kernel mode. This permits capability sandboxes to be used +in kernel mode by preventing them from being subverted using the TLB. + +\paragraph{Other KSU-controlled mechanisms} +Despite the Access\_System\_Registers permission controlling use of privileged +ISA features, absence of the bit does not change the behavior of the MIPS ISA +with respect to other KSU/EXL-related mechanisms. +For example, the value present in the bit does not affect any of the +following: selection of the +TLB miss handler to use; the KSU bits used to select the kernel, supervisor, +or user virtual address space used in TLB lookup; the KSU bits reported in the +\textit{XContext} register; or the automatic setting and clearing of the EXL +flag on exception entry and return. +Memory capabilities are used to constrain the use of memory within kernel or +supervisor compartments, rather than the ring-based MIPS segmentation +mechanism, which is unaffected by the Access\_System\_Registers permission. + +\paragraph{Prefetch} +\label{sec:mips-prefetch} + +The MIPS-IV prefetch instruction (\insnnoref{PREF}) checks the prefetched +address against \DDC. If the prefetched address is outside the bounds of +\DDC{}, the prefetch fails silently, without raising an exception but also +without prefetching the data into the cache. If \DDC{} does not grant +Load permission, then the prefetch will also silently fail. + +\section{Changes to the Translation Look-aside Buffer (TLB)} + +CHERI-MIPS implements CHERI adaptations to virtual-memory support following +the model described in Section~\ref{sec:virtual_memory}. +As MIPS provides a software-managed TLB, CHERI-related changes are primarily +with respect to TLB management instructions (which now require the +Access\_System\_Registers permission on \PCC{}) and TLB-entry contents. + +\begin{table} +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,31}\\ +\bitbox{1}{\rotateinbitbox{\small SCI}} +\bitbox{1}{\rotateinbitbox{\small LCI}} +\bitbox{30}{0} \\ +\bitbox{2}{0} +\bitbox{24}{PFN} +\bitbox{3}{C} +\bitbox{1}{D} +\bitbox{1}{V} +\bitbox{1}{G} +\end{bytefield} +\end{center} +\caption{EntryLo Register} +\label{table:entrylo} +\end{table} + +%\begin{table} +%\begin{center} +%\begin{tabular}{lll} +%\toprule +%EntryLo bit & Name & Description \\ +%\midrule +%62 & \texttt{LCI} & Strip the tag from any value loaded via this TLB entry \\ +%63 & \texttt{SCI} & Throw an exception if a tagged value is stored via this TLB entry \\ +%\bottomrule +%\end{tabular} +%\end{center} +%\caption{New permission bits added to the MIPS EntryLo portion of a TLB entry} +%\label{table:cheri-mips-tlb-entries} +%\end{table} + +Two new permission bits have been added to the MIPS EntryLo portion of each +TLB entry to indicate whether a given memory page is configured to have +capabilities loaded or stored (see Figure~\ref{table:entrylo}). +This functionality can be used in a variety of ways to control and track +capability use within a virtual address space. +For example, mapping pages with \texttt{SCI} and/or \texttt{LCI} can be used to +prevent sharing of tagged capability values between address spaces where +capabilities might have different interpretations. +\texttt{SCI} could also be used to implement a ``capability dirty bit'' in the TLB +handler, tracking which pages have been used to store capabilities, perhaps +for the purposes of efficient garbage collection or revocation. + +\begin{description} +\item[Load Capability Inhibit (\texttt{LCI})] If this bit is set then capability + loads are disabled for the page. + If the \insnmipsref{CLC} instruction is used on a page with the \texttt{LCI} + bit set, and the load succeeds, the value loaded into the destination + register will have its tag bit cleared, even if the tag bit was set in + memory. + +\item[Store Capability Inhibit (\texttt{SCI})] If this bit is set, capability + stores are disabled for the page. + If the \insnmipsref{CSC} instruction is used on a page with the \texttt{SCI} + bit set, and the capability register to be stored has the tag bit set, then + a CP2 exception will be raised, with \capcausereg{} set to 0x9 (MMU + prohibits store capability). + If the capability register to be stored does not have the tag bit set (i.e., + it contains non-capability data), then this exception will not be raised, + and the store will proceed. +\end{description} + +\noindent +% +As with other TLB-related exceptions, \texttt{BadVAddr} will be set to the +absolute virtual address that has triggered the fault, and \texttt{EntryHi} +will also be set accordingly.% +% +\footnote{CHERI-MIPS is a bit of an architectural outlier, updating both +\capcausereg{} (nominally, a CP2 register) and \texttt{BadVAddr} (CP0) on its +capability-related MMU faults. System software generally cares only about the +faulting virtual address (i.e., \texttt{BadVAddr}) except for diagnostic +reporting, and so we anticipate that most other CHERI instantiations will +report only this value.} +% +This new fault is raised \emph{after} checking +the existing \texttt{V} and \texttt{D} bits in the TLB entry; that is, existing +``TLB Refill'' and ``TLB Modify'' exceptions arising from the store destination +page take precedence. (This choice slightly simplifies system software, which +may assume that a ``MMU prohibits store capability'' fault necessarily points +\texttt{BadVAddr} at a mapped, dirty page.) + +\section{Protection-Domain Transition with CInvoke} +\label{section:protection-domain-transition-with-cinvoke} + +\rwnote{Much of the content here is architecture neutral, but some parts are + MIPS specific.} + +Cross-domain procedure calls are implemented using the \insnmipsref{CInvoke} +instruction, which provides access to controlled non-monotonicity for the +purposes of a privileged capability register-file transformation and memory +access. +The instruction accepts two capability-register operands, which represent the +sealed code and data capability describing a target protection domain. +\insnmipsref{CInvoke} checks that the two capabilities are valid, that both are +sealed, that the code capability is executable, that the data capability is +non-executable, and that they have a matching object type. + +\insnmipsref{CInvoke} unseals the sealed code and data capabilities +and places them in \PCC{} and \IDC{}, with control transferred +directly to the target code capability. +A programming-language or concurrent programming-framework runtime might +arrange that all sealed code capabilities point to a message-passing +implementation that proceeds to check argument registers or clear other +registers, switching directly to the target domain via a further +\insnmipsref{CJR}, or returning to the caller if the message will be delivered +asynchronously. + +Voluntary protection-domain crossing -- i.e., not triggered by an interrupt -- +will typically be modeled as a form of function invocation or message passing +by the operating system. +In either case, it is important that function callers/callees, message +senders/recipients, and the operating system itself, be constructed to protect +themselves from potential confidentiality or integrity problems arising from +leaked or improperly consumed general-purpose integer registers or +capabilities passed across domain transition. +On invocation, callers will wish to ensure that non-argument registers, as +well as unused argument registers, are cleared. +Callees will wish to receive only expected argument registers. +Similarly, on return, callees will wish to ensure that non-return registers, +as well as unused return registers, are cleared. +Likewise, callers will wish to receive back only expected return values. +In practice, responsibility for this clearing lies with multiple of the +parties: for example, only the compiler may be aware of which argument +registers are unused for a particular function, whereas the operating system +or message-passing routine may be able to clear other registers. +Work performed by the operating system as a trusted intermediary in a +reliable way may be usefully depended on by either party in order to prevent +duplication of effort. +For example, if the OS the clears non-argument +registers on call, and non-return registers on return, caller and +callee can avoid clearing those registers allowing that clearing +to occur exactly once. +\jhbnote{I'm tempted to replace OS in this paragraph with something + like ``domain-transfer supervisor'' since the intermediary may well + live in user space (like the runtime linker).} +Efficient register clearing instructions (e.g., \insnmipsref{CClearRegs}) can +also be used to substantially accelerate this process. + +In CHERI, the semantics of secure message passing or invocation are software defined, and we anticipate that different operating-system and programming-language security models might handle these, and other behaviors, in different ways. +For example, in our prototype CheriBSD implementation, a userspace supervisor maintains a ``trusted stack'' onto which values are pushed during invocation, and from which values are popped on return. +Over time, we anticipate providing multiple sets of semantics, perhaps corresponding to less synchronous domain-transition models, and allowing different userspace runtimes to select (or implement) the specific semantics their programming model requires. +This is particularly important in order to provide flexible error handling: if a sandbox suffers a fault, or exceeds its execution-time budget, it is the OS and programming language that will define how recovery takes place, rather than the ISA definition. + +\section{Capability Register Conventions / Application Binary Interface + (ABI)} + +All ABIs implement the following capability register reservations for calls +within a protection domain (i.e., ordinary jump-and-link-register / return +instructions): + +\begin{itemize} + \item \creg{1}--\creg{2} are caller-save. During a cross-domain call, these are used to pass the \PCC{} and \IDC{} values, respectively. In the invoked context, they are always available as temporaries, irrespective of whether the function was invoked as the result of a cross-domain call. + \item \creg{3}--\creg{10} are used to pass arguments and are not preserved across calls. + \item \creg{11}--\creg{16} and \creg{25} are caller-save registers. + \nwfnote{Maybe add a note that \creg{25} was once reserved, thus its odd place in this list?} + \item \creg{17}--\creg{24} are callee-save registers. +\end{itemize} + +\noindent +In all ABIs, the following convention also applies: + +\begin{itemize} +\item \creg{3} optionally contains a capability returned to a caller + (congruent to MIPS \mreg{v0}, \mreg{v1}). +\end{itemize} + +\noindent +The pure-capability ABI, used within compartments or for pure-capability +(``CheriABI``) applications, implements the following further conventions for +capability use: + +\begin{itemize} +\item \creg{11}, in the pure-capability ABI, contains the stack capability + (congruent to MIPS \mreg{sp}). +\item \creg{12}, in the pure-capability ABI, contains the jump register + (congruent to MIPS \mreg{t9}). +\item \creg{17}, in the pure-capability ABI, contains the link register + (congruent to MIPS \mreg{ra}). +\end{itemize} + +When calling (or being called) across protection domains, there is no +guarantee that a non-malicious caller or callee will abide by these +conventions. +Thus, all registers should be regarded as caller-save, and callees cannot +depend on caller-set capabilities for the stack and jump registers. +Additionally, all capability registers that are not part of the explicit +argument or return-value sets should be cleared via explicit assignment or +via the \insnmipsref{CClearHi} and \insnmipsref{CClearLo} instructions. +This will prevent leakage of rights to untrustworthy callers or callees, as +well as accidental use (e.g., due to a compiler bug). +Where rights are explicitly passed between domains, it may be desirable to +clear the global bit that will (in a suitably configured runtime) limit +further propagation of the capability. +Similar concerns apply to general-purpose integer registers, or capability registers +holding data, which should be preserved by the caller if their correct +preservation is important, and cleared by the caller or callee if they might +leak sensitive data. +Optimized clearing instructions \insnmipsref{ClearHi} and \insnmipsref{ClearLo} are +available to efficiently clear general-purpose integer registers. + +\mrnote{Is \IDC{} a caller-save or callee-save register?} + +\section{Potential Future Changes to the CHERI-MIPS ISA} + +The following changes have been discussed and are targeted for short-term +implementation in the CHERI-MIPS architecture: + +\begin{itemize} +\item Develop (modest) changes to \insnmipsref{CInvoke} so as to + ensure that the two sealed capabilities are in expected registers for the + callee. + In the original \insnnoref{CCall}, our extensions to MIPS CP0 allowed the exception handler to + check the trapping instruction's encoding to ensure \creg{1} and \creg{2} + were passed (or other ABI choices), ensuring reliable access to sealed + versions of the caller's operands -- giving access to the object type, for + example. + In userspace, we do not have access to MIPS CP0, and it would be preferable + to find some other way to reliably pass not just the unsealed versions, but + also caller sealed versions, to the callee. + + One way to accomplish this would be to complete our shift of reserved + capability registers away from the main capability register file into a bank + of named system registers, allowing allowing the two input registers and two + output sealed registers to be placed in well-known locations for access by + the callee. + This would also avoid encoding use of \IDC{} in the instruction definition, + which is similarly undesirable. + + \jhbnote{We've done the first part of this (shifting reserved cap + registers into a separate bank), so this needs to be revised to + just say the second half, but perhaps more explicitly? (E.g. + reserving C27/C28 for outputs?)} + +\item + Another feature consideration for \insnmipsref{CInvoke} is the + need for the caller to construct its own return \PCC{} value. + In more conventional \insnmipsref{CJALR} jump-and-link-register + instructions, the call instruction itself saves the current \PCC{}. + While placing yet more obligation on the architecture to write to registers, + this would avoid substantial caller work (typically materialization of a + return address provided by the linker, \insnmipsref{CGetPCC}, and + \insnmipsref{CSetOffset} to construct a suitable return capability). + +\item Add instructions for loading/storing floating point registers via a + capability. This is not just a performance optimization, but also simplifies + register allocation in a compiler: storing a float by moving it to an + integer register and then storing the integer register to memory needs an + integer register that isn't being used for something else. +\end{itemize} + +The following changes have been discussed for longer-term consideration: + +\begin{itemize} +\item + Consider further the effects of combining general-purpose integer and capability + register files, which would avoid adding a new register file, but make some + forms of ABI compatibility more challenging. +\end{itemize} diff --git a/chap-cheri-riscv.tex b/chap-cheri-riscv.tex new file mode 100644 index 00000000..5da3a80d --- /dev/null +++ b/chap-cheri-riscv.tex @@ -0,0 +1,1578 @@ +\chapter{The CHERI-RISC-V Instruction-Set Architecture} +\label{chap:cheri-riscv} + + +\newcommand{\riscvloadcappagefault}{0x1A} +\newcommand{\riscvstorecappagefault}{0x1B} +\newcommand{\riscvcheriexception}{0x1C} + +In this chapter we propose a draft application of the CHERI protection model +to the RISC-V ISA. +We build on our experience designing CHERI-MIPS, revisiting key design choices +and also adapting the model anew to a similar but distinct instruction set +with a more contemporary set of architectural features. +We choose to design CHERI-RISC-V as a parameterizable instruction set that +includes several key design points that allow us to evaluate both +microarchitectural and architectural implications via side-by-side +experiments. +This specification is a draft in that it remains a work-in-progress and has +not yet been fully elaborated or realized in microarchitecture. +In particular, we are aware that our compiler-targeted instruction set is +likely to be largely usable, but the privileged aspects, including exception +handling and page-table walking, will likely require further iteration. +We anticipate substantial changes in future CHERI ISA revisions as the +CHERI-RISC-V ISA matures. + +\section{The RISC-V Instruction-Set Architecture} + +RISC-V is a contemporary open-source architecture developed at the University +of California at Berkeley. +RISC-V is intended to be used with a range of microprocessors spanning small +32-bit microcontrollers intended for embedded applications to larger 64-bit +superscalar processors intended for use in datacenter computing. +The RISC-V ISA is reminiscent of MIPS, with some important differences: a more +modular design allows the ISA to be more easily subsetted and extended; a +variable-length instruction encoding improves code density; the MMU has a +hardware page-table walker rather than relying on software TLB management; +the ISA avoids exposing pipelining behaviors to software (e.g., there is no +branch-delay slot); and it has a more contemporary approach to atomic memory +instructions. +Various drafts and standardized extensions add other more contemporary +features such as hypervisor support. There is also ongoing work to define +broader platform behaviors beyond the architecture, including platform +self-description and peripheral-device enumeration. +At the time of writing, the RISC-V userspace ISA has been standardized +(v2.2)~\cite{RISCV:User:2.2}, but the privileged ISA remains under +development (v1.10)~\cite{RISCV:Privileged:1.10}\footnote{As v1.11 of the +privileged specification remains a work-in-progress, we define CHERI-RISC-V +relative to v1.10.}. \mmnote{1.11 is ratified now, so we should rewrite this chapter with v1.11 changes.} + +%\textbf{XXXRW: It would be nice to propose an extension name; unfortunately, +%the `C' extension is already used for compressed instructions. +%`S' is taken for the supervisor extensions, and `P' for SIMD. +%Perhaps we should be `W' for Weally Secure, Doc?} + +\section{CHERI-RISC-V Approach} + +Our application of CHERI to the RISC-V architecture is motivated by several +opportunities: + +\begin{itemize} +\item To gain access to a maturing open-source ISA, hardware, and software + ecosystem, for the purposes of a stronger experimental baseline and + methodology (such as more mature core variants). + At the time of writing, the MIPS software ecosystem remains richer, but we + see a substantial community effort at filling gaps for RISC-V. + +\item To demonstrate the portability of the CHERI approach across multiple + architectures, and in particular to illustrate how portable CHERI software + stacks can be designed and maintained despite underlying architectural + differences. + +\item To apply lessons learned from CHERI-MIPS in an entirely fresh + application of the protection model to a new architecture. + Many of our MIPS design choices reflect pragmatic design choices made prior + to the development of full compiler and operating-system stacks, and are + difficult to change within those stacks. + +\item To revisit and scientifically explore a design space around CHERI + integration into a target architecture -- for example, around the use of + register files and exceptions. + +\item To support new CHERI experimentation in the space of microcontrollers, + heterogenous cores and accelerators, and DMA, as well as in relation to + microarchitectural side channels. + +\item To lay groundwork for possible open-source transition of the CHERI + protection model into the RISC-V architecture. +\end{itemize} + +In the following subsections, we describe our high-level approach before +providing a more detailed specification of CHERI-RISC-V. + +\subsection{Target RISC-V ISA Variants} + +The RISC-V ISA defines both 32-bit (\texttt{XLEN}=32) and 64-bit +(\texttt{XLEN}=64) base integer instruction +sets (RV32I, RV64I). \mmnote{Maybe mention that we don't support RV128I, +because it has not been ratified yet.} +Our current proposal would support either mode with few differences beyond +capability width, although safe support for both modes in a single processor +is not specified at this time. +\pgnnote{This may be understated. It may also be misinterpreted, + as to whether what exists is not safe, or not done at all. + That seems ambiguous. The RISC-V privileged spec itself + is mostly parameterized for XLEN (Prashanth), and I would presume + perhaps the CHERI-RISC-V might also, as it seems is described below.} +\pdrnote{I think adding the word dynamically clears up this confusion?} +Our definition of CHERI-RISC-V should work with either 32-register or +16-register (RV32E) variants of RISC-V. +We specify CHERI as applied to RVG, which consists of the general-purpose +elements of the RISC-V ISA: integer, multiplication and division, +atomic, floating-point, and double floating-point instructions. +We also describe extensions to RVS, the supervisor extension defined in the +privileged portion of the ISA. + +\subsection{CHERI-RISC-V is an ISA Design Space} + +A key aim in CHERI-RISC-V is to allow experiments to be run comparing various +CHERI-related parameters: Are the general-purpose integer and capability +register files separate or merged? Are capabilities with respect to 32-bit or +64-bit virtual addresses? What are the impacts of various instruction-set +variations or microarchitectural optimizations? How does greater investment +of opcode space affect performance -- and what techniques, such as instruction +compression or different capability-aware modes, may impact this? How can +CHERI interact with other architectural specializations such as DMA and +heterogenous compute? +To answer these and other questions, we have designed CHERI-RISC-V as an ISA +design space, in which several key design dimensions are parameterized: + +\begin{itemize} +\item Both 32-bit and 64-bit RISC-V are extended, with 64-bit and 128-bit + capabilities respectively. + +\item Both split and merged general-purpose integer and capability register + files are supported. + +% XXXRW: We now think that we are not doing this in CHERI-RISC-V. +% +%\item Both exception-throwing and tag-clearing variants of monotonic +% capability manipulation instructions are supported. +% \arnote{I thought we had concluded that we should not be throwing exceptions unless absolutely required.} + +\item Optional instruction variations and an optional ``capability encoding + mode'' that + invest opcode space differently to reduce instruction count for common + instruction sequences -- especially with respect to load/store instructions + that occupy substantial quantities of opcode space. +\end{itemize} + +With respect to all of these design dimensions, we intend that specific +instantiated microarchitectures, compiler targets, compiled operating systems, +and compiled software stacks support only one point in the space. +However, we hope that carefully parameterized hardware and software designs +will be able to target more than one point to allow side-by-side comparison +from the perspectives of hardware resource utilization, performance, security, +and compatibility. + +\subsection{CHERI-RISC-V Strategy} + +Our baseline strategy transliterates non-load/store CHERI-specific +instruction definitions ``as is'' to the greatest extent possible, and retains +the fundamental CHERI design choices including the use of capabilities in +tagged capability registers (protected by guarded manipulation) and tagged +memory. +As with MIPS, legacy RISC-V integer-relative load/store instructions similarly +indirect via \DDC{}, and instruction fetch via \PCC{}. +We utilize the same in-memory capability representation, architectural +constants, and compression model in both CHERI-MIPS and CHERI-RISC-V. + +Certain necessary divergences arise around RISC-V-specific aspects of the ISA, +in particular around privileged features such as exception handling and +hardware page-table support. +Greater variation also arises around memory load/store instructions, where we +attempt to conform to the RISC-V philosophy (supporting only relatively simple +addressing modes due to the assumption of micro-op fusion), and for branch +instructions (where no branch-delay slot is used). + +A key area where CHERI-RISC-V differs from CHERI-MIPS is in allowing the +general-purpose integer and capability register files to be ``merged'', in the +style of 64-bit extensions to 32-bit architectures, rather than introducing a +new capability register file. +This approach offers the potential for reduced microarchitectural overhead due +to reduced control logic, as well as reduced disruption to software context +management. +Both ``split'' and ``merged'' register files are supported in CHERI-RISC-V to +allow explicit evaluation of their respective compatibility, security, and +performance tradeoffs. + +% XXXRW: We now think we are not doing this in CHERI-RISC-V. +% +%Another area of specific intentional divergence is in shifting from delivering +%exceptions on non-monotonic register-to-register operations to instead +%clearing the tag during register write back, which may offer more +%conventional compiler-driven error handling, as well as simplifying +%superscalar designs by allowing the possibility of an exception being thrown +%to be identified during instruction decode for register-to-register +%instructions.\pmnote{``Intentional divergence'' is perhaps too strong, since the goal is to explore/support both options?} + +Wherever possible, we attempt to conform to the specific aesthetic of RISC-V, +such as with respect to opcode layout choices and aligning the semantics of +new Special Capability Register access instructions with existing RISC-V CSRs. + +\pgnnote{This begs the question of whether we will remain fully compliant + with the RISC-V privileged spec, or must necessarily deviate.} + +\subsection{Architectural Features Shared with CHERI-MIPS} + +The following CHERI-MIPS features have been transliterated into CHERI-RISC-V: + +\begin{itemize} +\item Tagged memory with capability-width tag granularity and alignment. +\item An identical architectural capability format (i.e., fields accessed via + explicit instructions). +\item An identical in-memory capability format, including compression model(s) + -- except that the format is little endian. + We anticipate transitioning CHERI-MIPS to a little-endian in-memory format + in due course. +\item Registers able to hold capabilities are tagged. +\item \PCC{} transforms and controls program-counter-relative fetches. +\item \DDC{} transforms and controls legacy RISC-V load-store instructions, + including relocating access addresses using the capability base and offset. +\item Requests for non-monotonic capability transformations, + capability-related violations (such as loads/stores/fetches via untagged + capabilities, out-of-bound accesses, and so on) trigger immediate precise + exceptions. +\item It is never left ambiguous as to whether a register index operand to a + load or store instruction, or the register target of a jump instruction, + is a capability and therefore must have a tag set. + This both ensures that a split register file can be used (as it is always + clear what register file the operand reads from) and also reinforces + intentionality. +\item The Access\_System\_Registers permission bit limits privileged ISA + operations when within privileged rings. + While RISC-V's specific privileged operations differ, the intent remains the + same: to allow code compartmentalization within the privileged ring. +\end{itemize} + +\subsection{Architectural Features that Differ from CHERI-MIPS} + +The following important differences arise between CHERI-MIPS and CHERI-RISC-V: + +\begin{itemize} +\item CHERI-RISC-V supports a ``merged'' register-file variant. +\item RISC-V exception handling -- including register banking, scratch + registers, and cause mechanism -- is used. +\item A new exception code, \riscvloadcappagefault{}, will be + reported in the RISC-V \xcause{} CSRs when a load attempts to fetch a + capability through a valid page table entry granting read permission but + forbidding loads of capabilities. This fault otherwise behaves like a RISC-V + load page fault. +\item A new exception code, \riscvstorecappagefault{}, will be + reported in the RISC-V \xcause{} CSRs when a store attempts to write a + capability through a valid page table entry granting write permission but + forbidding stores of capabilities. This fault otherwise behaves like a + RISC-V store/AMO page fault. +\item A new exception code, \riscvcheriexception{}, will be + reported in the RISC-V \xcause{} CSRs when other + capability-related exceptions (such as tag violations) occur. + % + Additional capability-specific exception cause information, such + as more specific cause information and the identity of the faulting + register is reported in the existing \xtval{} CSRs (see + Section~\ref{subsubsec-cheri-tval}). +\item New per-mode capability CSRs are added as \xccsr{} (see + Section~\ref{subsubsec-ccsrs}). +\item CHERI-related page permissions are added to RISC-V architectural + page-table formats rather than MIPS TLB entries. +\item In CHERI-MIPS, memory capabilities (i.e., those with \cappermL, + \cappermS, ... permissions) always have a virtual-address interpretation. + This still allows describing physical addresses due to MIPS's architectural + physically mapped segments, which directly map portions of the physical + address space into the virtual address space. + + In CHERI-RISC-V, the interpretation of addresses in memory capabilities + depends on whether virtual addressing is enabled via the RISC-V + \texttt{satp} CSR\footnote{This is not a substantially different design + choice than in CHERI-MIPS or with MMU addressing enabled: memory + capabilities are interpreted relative to the active address space, and + control of that address space is delegated to suitably privileged code, + whether configuring a simple direct map between virtual and physical memory, + or managing multiple more complex address spaces. + In all cases, care is required as physical-memory access authorized by a + capability is determined by the addressing mode and current translation + table contents.}. + When \texttt{satp} is set to \texttt{Bare}, capabilities have a + physical-address interpretation. + When \texttt{satp} enables page-table translation, capabilities have a + virtual-address interpretation. +\item Both XLEN=32 and XLEN=64 will be supported (albeit not dynamically). + In the future, it may be desirable to also support XLEN=128. +\item A richer set of atomic instructions is extended with capability + support. +\item There is support only for compressed capabilities (128 bit for XLEN=64; + 64 bit for XLEN=32). +\item Floating point is fully supported, including capability-relative + floating-point load and store instructions. +\item The \cflags{} field contains a single bit indicating the ``capability + encoding mode'' to use when the capability is installed as \PCC{}. +\item In the non-compressed RISC-V encoding, the capability encoding mode + allows existing opcodes, e.g.\ for loads, stores, \insnnoref{auipc}, + to be interpreted as expecting capability rather than integer operands + (reducing opcode footprint while maintaining intentionality). +\item In the compressed RISC-V encoding, the capability encoding mode allows + existing load, store, and jump opcodes to be interpreted as expecting + capability rather than integer operands. + +% XXXRW: We are no longer doing this in CHERI-RISC-V: +% +%\item Instructions performing operations that would violate monotonicity or +% otherwise lead to an undereferenceable (e.g., unrepresentable) capability +% clear the tag when writing the register back, rather than immediately +% throwing an exception. +% Later attempts to dereference those capabilities will throw a tag +% violation exception. +% \jrtcnote{In CHERI-RISC-V is an ISA Design Space we say both +% exception-throwing and tag-clearing variants are supported} +\end{itemize} + +\section{CHERI-RISC-V Specification} + +In this section, we describe in greater detail the integration of CHERI into +the RISC-V instruction set, drawing attention to both similarities and +differences from CHERI-MIPS. +Draft instruction opcode encodings can be found in +Appendix~\ref{app:isaquick-riscv}; these are expected to change as our approach +evolves. + +\pmnote{Perhaps mention something like this: + +\subsection{CHERI as a non-standard RISC-V extension} + +CHERI is integrated into the RISC-V ISA as a non-standard extension +named Xcheri, and follows the idioms for RISC-V extensions to the +extent possible. In the extension terminology of the RISC-V +specification, CHERI is a \emph{greenfield} extension since it adds +new instructions by populating a new instruction encoding space. The +prefix used for the encoding is currently ``1011011'', placing it in +the \emph{custom-2/rv128} opcode space that the specification allows +for use for custom instruction set extensions on RV64; this makes it a +standard-compatible global encoding. (See however the discussion in +Section~\ref{section:cheri-risc-v-rv128-lq-sq}.) + +A CHERI-RISC-V processor has the X bit of the \texttt{misa} register +hardwired to 1 on boot to indicate the presence of a non-standard +extension. Information tying this set X bit to the Xcheri extension +would be communicated to system software in a platform-specific manner. +} +\pdrnote{Agreed: this would be great, although pedantically, our adding of +load cap and store cap in non-extension space must make us brownfield?} + +\subsection{Tagged Capabilities and Memory} + +In CHERI-MIPS, we allow both registers and memory to hold tagged capabilities, +allowing capabilities and data to be intermingled. +This allows capabilities to be embedded within in-memory data structures, and +supports the implementation of capability-oblivious memory copy operations. +We recommend that the same approach be taken in CHERI-RISC-V, as this will +maintain strong C-language pointer compatibility for capabilities. +This implies the use of tagged memory as in CHERI-MIPS, consisting of 1-bit +tags protecting capability-aligned, capability-sized words of memory in +CHERI-RISC-V, implemented with suitable protection and atomicity properties. + +While we currently do not define CHERI-RISC-V support for RV128, we anticipate +that we will wish to support RV128 in the future. +It seems plausible that 256-bit capabilities might incorporate 128-bit +addresses along with compressed bounds in a similar manner to our 128-bit +capabilities for 64-bit addresses. + +\subsection{Capability Register File} + +In 64-bit MIPS, we introduce an additional capability register file to hold +tagged capability registers, rather than extending the +general-purpose integer register file. +In RISC-V, we are presented with a choice: introduce a new (``split'') +register file (e.g., as occurs with the RISC-V F extension for floating +point), or extend the existing (``merged'') general-purpose integer registers in the +base instruction set. + +Both options can be effectively targeted by a CHERI-aware compiler, but offer +quite different performance tradeoffs for both the microarchitecture and +software code generation. +For example, an additional register file may require additional control logic, +especially in simpler pipelined designs, and additional registers may impose an +additional data-cache footprint due to additional callee/caller register saving and context switching. + +In CHERI-RISC-V, we choose to specify the instruction set such that the +register-file choice is parameterized, allowing the design space to be +evaluated experimentally. +Particular CPUs and compiled software stacks will target only one of these two +approaches. + +\subsubsection{Split Register File} + +In CHERI-RISC-V, the split register file works much as in CHERI-MIPS: CHERI +instructions with capability register operands access the capability register +file, and integer operands specify access to the integer register file. + +\pmnote{The increased cost of context switching due to the larger + register context can be alleviated in some cases using the support + in \texttt{mstatus.XS} for optimizing context saves and restores.} + +\subsubsection{Merged Register File} + +In CHERI-RISC-V, we alternatively allow use of a \textit{merged +register file} in which general-purpose integer registers optionally hold +full +capabilities, along with a tag, reducing the amount of control logic otherwise +required (by avoiding an additional register file). +This also reduces the size of register context growth, but does require us to +avoid a design choice made in earlier version of the CHERI-MIPS ISA in which +certain general capability registers had reserved functions, such as \DDC{} +and \EPCC{}. +These must instead be accessed via Special Capability Registers accessed via +dedicated instructions similar to those accessing conventional RISC-V Control +and Status Registers (CSRs), which offer +two further advantages: the number of capability +registers can more easily be varied (e.g., in RV32E), and the special behavior +of those registers with respect to legacy memory access and exception handling +is disentangled from the register file's control logic. +Clean separation of general-purpose vs.\ control capability registers is also a +design choice present in the CHERI-MIPS ISA as of CHERI ISAv7 for these +reasons. + +Merging the general-purpose integer and capability register files raises the +question of whether and how non-capability-aware instructions should +interact with capability values in registers -- a concern not dissimilar to +the behavior of instructions on 64-bit architectures offering legacy 32-bit +support. +We specify that individual instructions reading from, or writing to, a +register in the register file have fixed integer or capability interpretations +based on the opcode encoding -- i.e., that new instructions be introduced that +explicitly specify whether capability semantics are required for an input or +output register, or that the current architectural mode unambiguously specify +integer or capability operand interpretation. + +A further design choice relates to the specific subset of general-purpose +integer registers that are extended to capability width, as it need not be the +case that all are. +In our baseline specification, we extend all registers, but allow software +ABIs to limit specific numbered registers to only integer use. +We hope to evaluate different points in this design space to determine whether +performance tradeoffs favour a complete set of capability registers, or simply +a partial set (which might reduce microarchitectural overhead). + +The bottom \texttt{XLEN} bits of the register will contain the integer +interpretation (which, for a capability, will be its address\pdrnote{Does this also +cover capabilities which authorise type space rather than address space?}), and the +top \texttt{XLEN} bits (plus additional tag bit) will contain any capability +metadata. +When a register is read as an integer (i.e., using an opcode that dictates an +integer interpretation), +the register's bottom \texttt{XLEN} bits will be utilized, and any other bits ignored. +When a register is written as an integer, its bottom \texttt{XLEN} bits will +hold the new +integer value, and the top \texttt{XLEN} bits and tag bit will be cleared to match +those of the NULL capability. This both prevents in-register corruption of tagged +capabilities by implicitly clearing the tag, and also provides reasonable semantics +for integer access to capability values. + +\subsubsection{Capability Length Architectural Constant (CLEN)} + +One challenge in introducing CHERI support is that the architectural constant, +\texttt{XLEN}, the number of bits in a register, is used to define numerous +behaviors throughout the ISA, such as the size of CSRs, the operation of +integer operations, the size of addresses, and so on. +We choose to leave \texttt{XLEN} as constant as the majority of these operations +are intended to be of the natural integer size (e.g., for addition). +However, this does mean that in some cases we need to introduce new +instructions intended to operate on full capability-wide values. +We introduce a new architectural constant, \texttt{CLEN}, which we define as +$2\times$\texttt{XLEN}, which excludes the tag bit. +Operations such as capability-width CSR access, capability load, and capability +store will operate on \texttt{CLEN}$+1$ bits including the tag bit. + +Specifically, for 32-bit CHERI-RISC-V, \texttt{CLEN} will be 64 bits, and for +64-bit CHERI-RISC-V, \texttt{CLEN} will be 128 bits, affecting a variety of +functions including the stride of tag bits in physical memory. +Opcode space is reserved in the RISC-V ISA for 64-bit load and store +instructions even when \texttt{XLEN} is 32, and we can reuse these opcode +reservations and encodings to load 64-bit \texttt{CLEN} words as well as +their tag bit. +Similarly, when \texttt{XLEN} is 64, we can use 128-bit \texttt{CLEN} load +and store opcodes. + +We do not currently define support for 32-bit compatibility (with or without +capability support) when operating in a 64-bit RISC-V processor, but +anticipate that adding non-capability-aware 32-bit support would be +straightforward. +We also do not yet define an architecture supporting multiple capability +widths concurrently, but recognize that there are certain use cases -- such as +when interoperating between a 64-bit application core and a 32-bit +microcontroller within a single System-on-Chip (SoC) -- where this would be +valuable. + +\subsection{Capability-Aware Instructions} + +In CHERI-MIPS, two general categories of instructions are added: those that +query or manipulate capability fields within registers, and those that +utilize registers for the purposes of load, store, or jump operations. + +Register-to-register instructions querying and manipulating fields can remain +roughly as defined in CHERI-MIPS, allowing integer values to be moved in and +out of portions of an in-register capability, subject to guarded manipulation. +As such, they are simply new instructions defined in CHERI-RISC-V and added to +the opcode space. +When using a split register file, those instructions operate as in CHERI-MIPS, +accessing the integer or capability register files as specified. +With the merged register file, integer and capability values are instead read +from, and written back to, the same register file. + +In CHERI-RISC-V, assuming that capabilities are stored in the general-purpose +integer register file, it is possible to imagine having memory-access and +control-flow instructions condition their behavior based on the presence of a +tag, selecting a compatible integer behavior if the tag is not set, and a +capability behavior if it is set. +However, this would violate the principle of intentional use: not only should +privilege be minimized, but it should not be unintentionally, implicitly, or +ambiguously exercised. +Allowing a corrupted capability (i.e., one with its tag stripped due to an +overlapping data write) to dereference \DDC{} implicitly would violate this +design goal. +We therefore specify strong \textit{type safety} for all capability-aware +instructions: all instructions explicitly encode whether an integer or +capability operand is being used, and attempts to use untagged values where +tagged ones are expected will lead to an exception. + +\subsection{Control and Status Registers (CSRs)} +\label{subsection:cheri-riscv-csrs} + +CHERI-RISC-V extends the behavior of the baseline RISC-V integer CSR set, +allowing capability control over access to some CSRs for compartmentalization +purposes, as well as adding several new CSRs to control capability-related +functionality. +These are accessed via existing RISC-V CSR instructions, and their encodings +are given in Table~\ref{tab:risc-v-control-and-status-registers}. +New Special Capability Registers (SCRs), accessed via new CSR-like +instructions, are described in Section~\ref{subsection:cheri-riscv-scrs}. + +\begin{table}[h] +\centering +\begin{tabular}{c>{\raggedright\arraybackslash}p{2.7in}>{\raggedright\arraybackslash}p{2.5in}} +\toprule +\textbf{Encoding} & \textbf{Register} & Privilege notes \\ +\midrule +\textbf{0x8C0} & User capability control and status register (\uccsr{}) & \PCC{}.\cperms{}.\emph{Access\_System\_Registers} \\ +\textbf{0x9C0} & Supervisor capability control and status register (\sccsr{}) & \{S,M\}-mode \& \PCC{}.\cperms{}.\emph{Access\_System\_Registers} \\ +\textbf{0xBC0} & Machine capability control and status register (\mccsr{}) & M-mode \& \PCC{}.\cperms{}.\emph{Access\_System\_Registers} \\ +\bottomrule +\end{tabular} +\caption{Control and Status Registers (CSRs)} +\label{tab:risc-v-control-and-status-registers} +\end{table} + +\subsubsection{Controlling Access to CSRs} + +Accessing some RISC-V CSRs also requires the PCC{}.\cperms{}.\emph{Access\_System\_Registers} +permission to be set for the currently executing code. +This allows privileged-level code to be constrained from interfering with key +system management functionality (such as exception handling). +We adopt a whitelist approach: reading or writing any CSR requires the permission, with the exceptions listed in Table~\ref{tab:risc-v-access-system-registers-whitelist}. + +\pdrnote{Text describing current makeshift whitelist, pending updates. TODO we want three separate permissions: UASR, SASR, MASR, permitting access only to the +corresponding privilege mode's CSRs. Debate still open over whether these are encoded as 3 bits, or as a 2-bit counter that monotonicity can only decrease +(make less privileged). This could either be a separate instruction or implicitly enforced on CAndPerms. We likely still want some kind of whitelist after this change} +\ajnote{I am not sure I am fully happy with that, but probably just need to be convinced by someone that this is the way to go... It feels weird that a user task which used to just access, say, the instret or time csr suddenly needs Access\_System\_Registers on its PCC.} +\pmnote{User access to the instret and time csrs are already constrained by scounteren.{IR,TM}; i.e. the user task will suffer an exception if these are not enabled by the supervisor. Access\_System\_Registers on its PCC would be similar.} + +\begin{table}[h!] +\centering +\begin{tabular}{cc} +\toprule +\textbf{CSR} & \textbf{Read/Write} \\ +\texttt{cycle(h)} & Read-Only \\ +\texttt{time(h)} & Read-Only \\ +\texttt{instret(h)} & Read-Only \\ +\texttt{hmpcounter(h)} & Read-Only \\ +[1.5em] +\texttt{fflags} & Read-Write \\ +\texttt{frm} & Read-Write \\ +\texttt{fcsr} & Read-Write \\ +\bottomrule +\end{tabular} +\caption{CSR Whitelist. The accesses shown are the only CSR accesses that are permitted when the installed PCC does not have the \emph{Access\_System\_Registers} permission bit set.} +\label{tab:risc-v-access-system-registers-whitelist} +\end{table} + +\subsubsection{Capability Exception Reporting} +\label{subsubsec-cheri-tval} + +CHERI-RISC-V extends the definition of the Trap Value CSRs, \xtval{}, to +report capability exception details as described in +Figure~\ref{fig-cheri-tval} (shown for XLEN=32): + +\begin{figure}[!h] +\begin{center} +\begin{bytefield}[bitwidth=\textwidth/34]{32} + \bitheader[endianness=big]{0,4,5,10,31} \\ + \bitbox{21}{\textbf{WPRI}} + \bitbox{6}{\texttt{cap idx}} + \bitbox{5}{\texttt{cause}} +\end{bytefield} +\caption{\xtval{} register format for Capability Exception} +\label{fig-cheri-tval} +\end{center} +\end{figure} + +\begin{description} +\item [cause] The \texttt{cause} field reports the capability exception code as described in Section~\ref{sec:capability_exception_causes}. +\item [cap idx] The \texttt{cap idx} field reports the index of the capability register that caused the last exception. When +the most significant bit is set, the 5 least significant bits are used to index +the special purpose capability register file described in +Table~\ref{tab:risc-v-special-capability-registers}, otherwise, they index the +general-purpose capability register file. +\end{description} + +\subsubsection{Capability Control and Status Registers (CCSRs)} +\label{subsubsec-ccsrs} +New per HART \xccsr{} \texttt{XLEN}-bit RISC-V CSRs are defined as per +Figure~\ref{fig-ccsr} (shown for XLEN=32): + +\begin{figure}[!h] +\begin{center} +\begin{bytefield}[bitwidth=\textwidth/34]{32} + \bitheader[endianness=big]{0,1,2,4,5,9,10,15,16,31} \\ + \bitbox{16}{\textbf{WIRI}} + \bitbox{6}{\texttt{cap idx}} + \bitbox{5}{\texttt{cause}} +% \bitbox{1}{\texttt{m}} + \bitbox{3}{\textbf{WIRI}} + \bitbox{1}{\texttt{d}} + \bitbox{1}{\texttt{e}} +\end{bytefield} +\caption{\xccsr{} register format; WIRI bits are Write Ignore Read Ignore.} +\label{fig-ccsr} +\end{center} +\end{figure} + +\pmnote{WIRI has been removed from the RISC-V specification. The spec + now typically uses WPRI (Write-Preserve, Read-Ignore) for such + undefined bits (e.g. in \texttt{mstatus}). Both WARL (Write-Any, + Read-Legal) and WLRL (Write-Legal, Read-Legal) seem unsuitable here. + The RISC-V spec unsatisfyingly does not specify what happens if + software doesn't preserve values for WPRI, but then this spec + doesn't need to either.} + +\begin{description} +\item [e] The \texttt{e} ``enable'' bit \ajnote{read only? / only wriFable in u-mode? only writable with a specific permission in pcc?} tells whether capability extensions are enabled or disabled. +\item [d] The \texttt{d} ``dirty'' bit tells whether a capability register has been written. This is intended to help with memory requirements when implementing context switching. \arnote{Is this still useful if we have hybrid and purecap co-process communication?} +\hmnote{If the user-mode apps are purecap, and the kernel is hybrid (or does not do any cap ops at all), this bit might be useful +to do lazy CHERI-context save/restore similar fo floating point.} +%\item [m] The \texttt{m} ``mode'' bit controls the current capability encoding +%mode (i.e. the behavior of memory instructions). +\item [cause] The \texttt{cause} field reports the cause of the last capability exception, following the encoding described in Table~\ref{table:capability-cause}. +\item [cap idx] The \texttt{cap idx} field reports the index of the capability register that caused the last exception. +\end{description} + +The \texttt{cause} and \texttt{cap idx} fields of this register are deprecated +and will be replaced by \xtval{}. + +\subsection{Special Capability Registers (SCRs)} +\label{subsection:cheri-riscv-scrs} + +Special Capability Registers (SCRs) are similar to CSRs in that they affect +special functions such as exception delivery, rather than being +general-purpose registers, but have capability rather than integer types. +SCRs are therefore accessed via new capability-aware instructions. + +The new \asm{CSpecialRW} instruction allows reading and writing special +capability registers. When the destination register is 0, the instruction shall +not read the special capability register and shall not cause any of the +side-effects that might occur on a special capability register read, similar to +the standard \asm{csrrw} RISC-V instruction. When the source register is 0, the +instruction will not write to the special capability register at all, and so +shall not cause any of the side effects that might otherwise occur on a special +capability register write, similarly to the standard \asm{csrrs/c} RISC-V +instruction. + +Table~\ref{tab:risc-v-special-capability-registers} lists the SCRs +available via that instruction, as well as their values at CPU reset, which +will be set in a manner consistent with the description in +Section~\ref{sec:capability-state-on-cpu-reset}. +Whether a register is initialized to NULL or the omnipotent capability, its +flags field will be initialized to zero (specifying integer encoding mode). + +\pdrnote{I have added MTDC, UTDC, STDC to match exception handling section. +Might be worth further discussion to decide if we need/want them.} + +\begin{table}[h!] +\centering +\begin{tabular}{cllcccc@{}} +\toprule +& \textbf{Register} & \textbf{Modes} & \textbf{Access} & \textbf{Reset} & \textbf{Extends} \\ \midrule +\textbf{0} & Program counter capability (\PCC{}) & U, S, M & RO & $\infty$ & \PC{} \\ +\textbf{1} & Default data capability (\DDC{}) & U, S, M & - & $\infty$ & - \\ +[1.5em] +\textbf{4} & User trap code capability (\UTCC{}) & U, S, M & ASR & $\infty$ & \utvec{} \\ +\textbf{5} & User trap data capability (\UTDC{}) & U, S, M & ASR & $\emptyset$ & - \\ +\textbf{6} & User scratch capability (\UScratchC{}) & U, S, M & ASR & $\emptyset$ & - \\ +\textbf{7} & User exception PC capability (\UEPCC{}) & U, S, M & ASR & $\infty$ & \uepc{} \\ +[1.5em] + +\textbf{12} & Supervisor trap code capability (\STCC{}) & S, M & ASR & $\infty$ & \stvec{} \\ +\textbf{13} & Supervisor trap data capability (\STDC{}) & S, M & ASR & $\emptyset$ & - \\ +\textbf{14} & Supervisor scratch capability (\SScratchC{}) & S, M & ASR & $\emptyset$ & - \\ +\textbf{15} & Supervisor exception PC capability (\SEPCC{}) & S, M & ASR & $\infty$ & \sepc{} \\ +[1.5em] + +\textbf{28} & Machine trap code capability (\MTCC{}) & M & ASR & $\infty$ & \mtvec{} \\ +\textbf{29} & Machine trap data capability (\MTDC{}) & M & ASR & $\emptyset$ & - \\ +\textbf{30} & Machine scratch capability (\MScratchC{}) & M & ASR & $\emptyset$ & - \\ +\textbf{31} & Machine exception PC capability (\MEPCC{}) & M & ASR & $\infty$ & \mepc{} \\ +\bottomrule +\end{tabular} +\caption{Special Capability Registers (SCRs). +SCRs 4-7 are available only with the N extension, and 12-15 only with the S +extension. +\textbf{Modes} shows which RISC-V privilege modes are allowed to access the +registers. +\textbf{Access} indicates additional restrictions on accessing the registers: +\PCC{} is read-only via \insnriscvref{CSpecialRW}, but is set by +\insnriscvref{CJALR} and during exceptions; \textit{ASR} indicates +\PCC{}.\cperms{} must grant \cappermASR{} to permit access (in addition to +being in a permitted mode). +\textbf{Reset} indicates whether the register should be initialised to the +default root capability ($\infty$) or NULL capability ($\emptyset$). +Some special capabilities registers are extensions of existing RISC-V +registers, with the capability offset being equal to the original register. +\note{We should describe this in more detail including behavior if they are +sealed or become unrepresentable and what to do about PC alignment. Note this +table shares quite a lot with \cref{subsection:riscv:exceptionhandling}}{rmn30} +} +\label{tab:risc-v-special-capability-registers} +\end{table} + +Where an SCR extends a RISC-V CSR, e.g.\ \MTCC{} extending \mtvec{}, +any read to the CSR shall return the offset of the corresponding SCR. +Similarly, any write to the CSR shall set the offset of the SCR to the value +written. +This shall be equivalent to a \insnriscvref{CSetOffset} instruction, but with +any exception condition instead just clearing the tag of the SCR. +This allows sealed capabilities to be held in SCRs without allowing them to +be modified in a tag-preserving way, while also preventing exceptions when +installing trap vectors: something that can be problematic where the task +is delegated to a higher privilege level. +Some RISC-V CSRs have write ignore bits, or otherwise implicitly modify +the written value to restrict the CSR to legal values. +These modifications must be applied to the SCR's new offset when writing a CSR +extended by an SCR, or to the offset of the newly written capability when +using \insnriscvref{CSpecialRW}. +\insnriscvref{CSpecialRW} of a sealed capability to an SCR which extends a CSR +with any non-preserved bits clears the tag on the capability, even if the +offset would not be changed. +As per the rest of the RISC-V specification, should the SCR become +unrepresentable as a result of the offset being set, the resulting address is +preserved, and the rest of the capability is cleared to match the null +capability. +Note that this means a read of the CSR (where the SCR has restricted bounds) +may not be consistent with the preceding write, but this approach is +consistent with the invalidating of other RISC-V capabilities, and allows a +meaningful address to be reported should the SCR be dereferenced. + +\arnote{what about an unprivileged register for TLS?} \hmnote{Unlike ARM, RISC-V uses a general-purpose integer register \textit{tp} +for TLS in user-level. In the kernel, the thread's kernel's context pointer +is saved in the scratch register. We try to follow RISC-V design where possible.} + +\subsection{Efficiently Encoding Capability-Relative Operations} +\label{subsec-encoding-cap-ops} + +The RISC-V instructions that interpret arguments or results as addresses +(e.g.\ loads, stores, jumps, \insnnoref{auipc}) can either act on integer pointers +relative to \DDC{} or \PCC{}, or on explicit capabilities. +For example, capability-relative load and store instructions accept (and expect) capability +operands that relocate and constrain data accesses, performing tag, bounds, +permission, and other checks as required. +However, load and store instructions occupy large amounts of instruction +encoding space due to having multiple register operands and large immediate +values. +One consideration in adding CHERI support to RISC-V is the degree to which we +are willing to occupy large chunks of remaining encoding space by simply +supplementing each address-manipulating instruction with a +corresponding capability-relative version, as we did in CHERI-MIPS. +Other options that conserve opcode space include utilizing a more limited set +of addressing modes or using smaller immediate sizes for capability-relative +instructions -- with a potentially significant negative impact on performance +due to an increase in resulting code size. +We therefore consider several points in this design space: + +\begin{itemize} +\item Introduce a full set of new load and store instructions occupying + substantial opcode space, but providing more efficient capability-intensive + generated code. + +\item Introduce only a limited set of new load and store instructions, + reducing new opcode utilization, and supportingly less efficient + capability-intensive generated code. + +\item Introduce a new \textit{capability encoding mode} in which + existing RISC-V load-store opcode space is reused for capability-relative + accesses, allowing a rich set of load-store instructions without + substantially occupying available RISC-V opcode space. + + In the conventional (legacy) \textit{integer encoding mode}, a small set of + capability-relative loads and stores are added, tuned to limit opcode + space utilization -- e.g., by having small or no immediates -- at the cost + of increased code footprint. + + To maintain intentionality, this approach is never ambiguous in either mode + as to whether load and store opcodes are intended to access relative to + integer or capability operand: address operands are always integer relative + in integer encoding mode, and always capability relative in capability + encoding mode. + + Pure-capability and hybrid code can be generated against either encoding, + but will be most efficient (in terms of instruction footprint) when + generated against the corresponding mode. + We have specified that the encoding mode will change as a result of jumping + to a \PCC{} with a different encoding-mode flag. + Section~\ref{section:capability-encoding-mode} considers other options for + encoding-mode switches. +\end{itemize} + +\noindent +In the interest of experimentation, we plan to pursue all three approaches +in stages, considering tradeoffs around efficiency and instruction-set design +across a range of workloads: + +\begin{enumerate} +\item Begin by adding a conservative set of capability-relative load and store +instructions without immediate offsets, which will consume a small amount of +opcode space, and be sufficient to allow initial compiler engineering to take +place. + +\item Introduce an architectural ``encoding mode bit'' in which RISC-V +instruction encodings used for integer-relative \DDC{}-constrained loads and +stores are instead used for CHERI-RISC-V capability-relative loads and stores. +To continue to allow hybrid code when in capability mode, we would introduce a +further simple set of \DDC{}-indirected integer-relative loads and stores with +no immediate, similar to the capability-relative set described above. + +\item Introduce a full set of capability-relative loads and stores +with immediate offsets to enable full flexibility without switching modes. +While this may not be acceptable to the upstream community without increasing +the size of instructions, we should understand how much performance is being +lost by reducing the flexibility of code generation. +\end{enumerate} + +As register-relative jump instructions have relatively light opcode +utilization, and because there are many easy-to-imagine uses for protecting +control flow using capabilities even in hybrid code, we do not apply semantic +changes to those baseline non-compressed RISC-V instructions when in +capability encoding mode. +The implications for compressed instructions are described in +Section~\ref{subsection:compressed-instructions}. + +\subsubsection{Encoding Modes} +\label{sec:cheri-riscv-encmodes} + +%We define two encoding modes selected using the \texttt{m} bit of \xccsr{} (see +%Section~\ref{subsubsec-ccsrs}): + +We define two encoding modes, selected using the CHERI-RISC-V-specific +encoding-mode flag in the capability \cflags{} field of \PCC{}: + +\begin{description} +\item[Integer encoding mode (0)] Conventional RISC-V execution mode, in which + address operands to existing RISC-V load and store opcodes contain + \textit{integer addresses}. + If using a merged register file, the upper \texttt{XLEN} bits and tag bit of + the operand register will be ignored. + The dereference will implicitly occur relative to \DDC{}. + The tag bit on \DDC{} must indicate that a valid capability is present, and + all capability-related checks (such as bounds checks) must be performed in + order for a successful load or store to take place. + +\item[Capability encoding mode (1)] CHERI capability encoding mode, in which address operands to + existing RISC-V load and store opcodes contain \textit{capabilities}. + The tag bit must indicate a valid capability is present, and all + capability-related checks (such as bounds checks) must be performed in order + for a successful load or store to take place. +\end{description} + +The operating system will automatically save and restore \PCC{} on context +switches, preserving an execution context's encoding mode. +It is essential that changes in encoding mode be properly observed when an +exception is processed, as the exception handler must execute with expected +semantics or risk insecure behavior. +When \xTCC{} is set by the operating system, it should contain an appropriate +encoding-mode flag to ensure that exception handlers utilize the correct +instruction encoding. + +%\rwnote{Should we say something about architectural visibility of an +% encoding-mode change -- i.e., that it's visible only after an exception is +% fired, when an exception returns, or on a jump?} + +% +%\rwnote{Or is there a status CSR being restored during exception entry...?}\ajnote{\mccsr{} would be the one implicitly used to decide on instruction decoding when entering an m-mode exception, \sccsr{} for s-mode, and \uccsr{} for u-mode exceptions.} +%\pmnote{There is space in mstatus[30:23] that could be used to store the per-ring mode bits. +% There is also a reserved but unused trap-mode bit in mtvec.mode[1] that could be used to determine instruction decoding of the exception handler.} + +\subsubsection{Non-Compressed Instructions Affected by Capability Encoding + Mode} + +The following non-compressed RISC-V load and store instructions would be +affected by the capability encoding-mode bit (see the following section for +further details on compressed instructions): + +\medskip + +\begin{savenotes} +\begin{tabular}{llllll} +\textit{Integer load} & LB & LH & LW & LD & LQ \\ +\textit{Integer load (unsigned)} & LBU & LHU & LWU & LDU & \\ +\textit{Integer store} & SB & SH & SW & SD & SQ \\ +\textit{Floating-point load} & FLW & FLD & FLQ & & \\ +\textit{Floating-point store} & FSW & FSD & FSQ & & \\ +\textit{Atomic} & LR & SC & AMOSWAP & AMOADD & AMOAND \\ +\textit{Atomic (cont)} & AMOOR & AMOXOR & AMOMAX & AMOMIN & \\ +\textit{Address calculation} & AUIPC\footnote{See Section~\ref{section:cheri-risc-v-auipc}.} & & & & \\ +\end{tabular} +\end{savenotes} + +\subsection{Compressed Instructions} +\label{subsection:compressed-instructions} + +\rwnote{Ensure that this text is up-to-date after our revisions to the + encoding-mode mechanism.} + +The compressed instruction extension (extension \texttt{C}) is now +routinely used by the RISC-V gcc compiler to improve code density. It seems +likely that the \texttt{C}ompressed extension will become mandatory for +the \texttt{G}eneral configuration (which is currently +\texttt{IMAFD}). +Two problems arise in adding compressed instruction support for capabilities: +the need for additional opcode space for load, store, and jump instructions; +and the need to add new instructions to load and store capabilities. + +Given the tight encoding space for compressed instructions, some +registers (e.g.~the stack pointer - \texttt{sp}) are implicit for some +instructions. Since there appears to be no free encoding space to +differentiate between a capability-\texttt{sp} and an +integer-\texttt{sp}, one potential design choice is to use our capability +encoding mode to also control the interpretation of compressed instructions. +Similarly, for compressed loads and +stores that can use only registers \texttt{x8}--\texttt{x15} as the +base address, the encoding mode would allow us to reuse opcode space. +As with the baseline compressed instruction set, this imposes ABI-related +constraints on the architecture, and would require the compiler to conform to +those constraints in order to accomplish the best code density. + +In his thesis~\cite{WatermanThesis2016}, Waterman gives the following +function prologue and epilogue examples to illustrate how compressed +instructions improve code density: + +\begin{small} +\begin{verbatim} + prologue_legacy: epilogue_legacy: + c.addi sp, -16 c.ldsp ra, 8(sp) + c.sdsp ra, 8(sp) c.ldsp s0, 0(sp) + c.sdsp s0, 0(sp) c.addi sp, 16 + c.jr t0 c.jr ra +\end{verbatim} +\end{small} + +For capability-aware code, saving and restoring the return address +(\texttt{ra}) requires capability store and load instructions. +Given the frequency of capability use for the pure-capability code targeted by +our capability encoding mode (all pointer loads and stores), one option might +be to relieve pressure on the compressed opcode space by removing the less +frequently used floating-point double load and store instructions. +For RV64, we could replace the compressed load floating-point double +(\texttt{C.FLD}) with compressed load capability (\texttt{C.LC}) with +the same encoding as compressed load quad (\texttt{C.LQ}) used in +RV128. Similarly, replace: \texttt{C.FSD} with \texttt{C.SC} +(compressed store capability). For stack-relative memory access, +replace floating-point double operations with capability operations: +\texttt{C.FLDSP} with \texttt{C.LCSP} and \texttt{C.FSDSP} with +\texttt{C.SCSP}. + +In the RISC-V I base instruction set (non-compressed instructions), we chose to make +capability jump instructions available in both integer and capability encoding +modes, as they use relatively little encoding space compared to the amount of +free space available. +In the RISC-V C extension (compressed instructions), the amount of free space is +far smaller, leading us to select a different design choice: when in capability +encoding mode, as with load-store instructions, we interpret existing compressed +instructions \insnnoref{C.J}, \insnnoref{C.JAL}, \insnnoref{C.JR}, and +\insnnoref{C.JALR} as the capability instructions \insnriscvref{CJAL}, +\insnriscvref{CJR}, and \insnriscvref{CJALR}, accepting capability rather than +integer register operands for jump target registers and link registers. + +There is one large gap in the compressed instruction encoding at +\verb#100X_XXXX_XXXX_XX00# (where \verb#X#$=$ don't care) that could +be used to support a \insnriscvref{CIncOffsetImm} (\texttt{c.cincoff}) +instruction to allow the stack pointer to be adjusted. + +This would result in capability-aware prologue and epilogues: + +\begin{small} +\begin{verbatim} + prologue_cap_aware: epilogue_cap_aware: + c.cincoff csp, -16 c.lcsp cra, 8(csp) + c.scsp cra, 8(csp) c.lcsp s0, 0(csp) + c.scsp cs0, 0(csp) c.cincoff csp, 16 + c.cjr ct0 c.cjr cra +\end{verbatim} +\end{small} + +A further interaction relates to encoding-mode selection. +If we pursue a design choice using the lowest bit of a target jump address to +set the encoding used following a jump, then no additional opcode pressure is +introduced. +If we instead choose to use new instructions, such as to get or set the mode +explicitly, then additional space might be required. +The amount of space required would be modest, but this additional usage might +be a further consideration in the encoding-mode management strategy. + +If the approach of using a mode bit for compressed instructions is +adopted, then it follows that the uncompressed versions of the +instructions should follow suit to preserve the design intent that +all compressed instructions can be expanded out to uncompressed +instructions by the processor's decoder, and that the assembler should +be permitted to optimize uncompressed instructions into their +compressed form where possible. +\pdrnote{These last two paragraphs do seem a bit stale, and do we need to +add a note about the prologue assuming it's been called in the correct +mode? (or doing a check)} + +\subsubsection{Compressed Instructions Affected by Capability Encoding Mode} + +The following compressed instructions are affected by capability encoding +mode: + +\medskip + +\begin{tabular}{llllll} +\textit{Control flow} & C.JALR & C.JR & & \\ +\textit{Compressed integer load} & C.LW & C.LD & C.LWSP & C.LDSP & \\ +\textit{Compressed integer store} & C.SW & C.SD & C.SWSP & C.SDSP & \\ +\textit{Compressed floating-point load} & C.FLW & C.FLD & C.FLWSP & C.FLDSP & \\ +\textit{Compressed floating-point store} & C.FSW & C.FSD & C.FSWSP & C.FSDSP & \\ +\end{tabular} + +\subsection{Floating Point} + +The vast majority of floating-point instructions are not impacted by the +presence of CHERI-RISC-V. +In CHERI-MIPS, we did not define capability-relative load and store +instructions for floats and doubles, requiring that they loaded via +general-purpose integer registers and then be moved into floating-point registers, +leading to reduced code density. +Existing RISC-V floating-point load and store instructions, in the +integer encoding mode, are relocated and constrained by \DDC{}. +In CHERI-RISC-V, we define a new set of simple capability-relative load and +store instructions, as well as a more rich set via capability encoding mode. + +In CHERI-MIPS, the floating point status and control register is part of the floating +point coprocessor, not co-processor 0, and so can be accessed without needing +\emph{Access\_System\_Registers} permission. In CHERI-RISC-V, the floating point control +registers (FCSR, FRM, and FFlags) are whitelisted in Table \ref{tab:risc-v-access-system-registers-whitelist} +so they can be accessed without needing \emph{Access\_System\_Registers permission}. + +\subsection{Exception Handling} +\label{subsection:riscv:exceptionhandling} +RISC-V defines several privilege modes, including machine mode, user mode, and +supervisor mode, with exceptions allowing controlled transition between those modes. +CHERI-RISC-V introduces several new exception-related Special Capability Registers +to supplement existing RISC-V exception CSRs with new capability-related functionality. +In addition, when a capability exception is raised, \xtval{} will provide +details about the exception as described in Section~\ref{subsubsec-cheri-tval}. + +\subsubsection{Exceptions to Machine Mode} +We define the following new special capability registers that can be read and +written only from machine mode: + +\begin{itemize} +\item \MEPCC{} - Machine Mode Exception Program Counter Capability (extends + \mepc{}) +\item \MTDC{} - Machine Mode Data Capability +\item \MTCC{} - Machine Mode Trap Code Capability (extends \mtvec{}) +\item \MScratchC{} - Machine Mode Scratch Capability +\end{itemize} + +\subsubsection{Exceptions to Supervisor Mode} + +We define the following new special capability registers that can be read and +written only from supervisor mode and above: + +\begin{itemize} +\item \SEPCC{} - Supervisor Mode Exception Program Counter Capability (extends + \sepc{}) +\item \STDC{} - Supervisor Mode Data Capability +\item \STCC{} - Supervisor Mode Trap Code Capability (extends + \stvec{}) +\item \SScratchC{} - Supervisor Mode Scratch Capability +\end{itemize} + +\subsubsection{Exceptions to User Mode} + +We employ the ``N'' extension (for ``User-Level Interrupts'') being developed in +the newer versions of the RISC-V specifications, and extend it with the following +new special capability registers that can be read and written from any mode: + +\begin{itemize} +\item \UEPCC{} - User Mode Exception Program Counter Capability (extends + \uepc{}) +\item \UTDC{} - User Mode Data Capability +\item \UTCC{} - User Mode Trap Code Capability (extends \utvec{}) +\item \UScratchC{} - User Mode Scratch Capability +\end{itemize} + +The extension could be leveraged for user-space-only implementations +of \insnriscvref{CInvoke}, as well as routing specific interrupts from +suitable devices to user-level compartments for handling by sandboxed +device drivers. + +Explicit vector and data capabilities replace our definitions of the \KCC{} +and \KDC{} Special Capability Registers in CHERI-MIPS, giving each ring its +own code and data capabilities to utilize during exception handling. +We define ``scratch capabilities'' to allow the exception handler to stash a +capability register for the purposes of having a working register that +corresponding data capabilities can be loaded to in order to begin a full +context save. +This is consistent with RISC-V's use of scratch registers in various modes to +avoid committing general-purpose integer registers to exception handling, as happens +in the MIPS ABI with \regname{k0} and \regname{k1}. +We are therefore able to similarly avoid the need for CHERI-MIPS's \KRC{} and +\KQC{}. + +When exception behavior, e.g.\ a trapping instruction, \insnnoref{ecall}, +or \xRET{}, causes \PCC{} to take a value stored in an SCR, it is possible that +the SCR contains a capability that would not be a valid \PCC{} (untagged, +sealed, not executable, or improperly aligned). +In these cases, the value is still installed in \PCC{}, and a check on the next +instruction fetch will trigger a further exception. + +% XXXRW: We are no longer doing this in CHERI-RISC-V: +% +%\subsection{Exceptions vs. Tag Clearing on Capability Manipulation Failure} +% +%In CHERI-MIPS, in keeping with the MIPS ISA design, many instructions are able +%to throw exceptions -- not only the load/store/jump variants, but also +%operations to manipulate capability fields. +%In more complex microarchitectures, it may be desirable to limit the set of +%instructions that can throw exceptions. +%If that is desirable for CHERI-RISC-V, then this could be accomplished by +%shifting manipulation instructions from throwing exceptions on non-permitted +%access to clearing the tag bit in the target register. +%This maintains the security invariant that monotonicity (and other aspects) +%is enforced, but shifts the point of exception delivery from manipulation to +%dereference. +% +%One risk in adopting this approach is that debugging non-derefenceable +%pointers may become more difficult, due to greater asynchrony. +%An additional architectural status bit that can be checked to detect loss of a +%tag by an instruction would allow compiler-inserted instrumentation to check +%for tag loss at suitable moments (e.g., after potentially tag-stripping +%operations such as pointer manipulation). + +\subsection{Virtual Memory and Page Tables} +\label{subsection:riscv:pagetables} + +In CHERI-RISC-V, capability addresses are interpreted with respect to the +privilege level of the processor in line with RISC-V's handling of integer +addresses. +% +In Machine Mode, capability addresses are generally interpreted as physical +addresses; if the \texttt{mstatus} \texttt{MPRV} flag is asserted, then data +accesses (but not instruction accesses) will be interpreted as if performed by +lower-privileged modes. +% +In Supervisor and User Modes, capability addresses are interpreted as dictated +by the current \texttt{satp} configuration: addresses are virtual if paging is +enabled and physical if not. +% +% \hmnote{It is more accurate to say that addresses are interpreted as virtual +% addresses IIF SATP.mode != Bare. There could exist M/U processors with no +% virtual addresses, or even SW that, theoretically but not practically runs on +% M/S/U processors that still work with SATP.mode = Bare across all rings.} + +Unlike in CHERI-MIPS, the page-table walker is implemented by the architecture +and not the software stack, and in the absence of further extensions to the +page-table format, continues to contain physical addresses loaded and stored +on behalf of executing software. +In CHERI-RISC-V, we require the Access\_System\_Registers permission to change +the page-table root (\texttt{satp}) and other virtual-memory parameters. +(In the future, it may be desirable to extend the page-table walking mechanism +to itself utilize capabilities, allowing the walker to be constrained; +see \cref{app:exp:physcap:ptw}.) + +As with CHERI-MIPS, it is desirable to extend the Memory Management Unit +to constrain the loading and storing of valid capabilities via specific page +mappings. +In CHERI-MIPS, this is expressed via two new Translation Look-aside Buffer +(TLB) permissions that, if not granted, cause loads to strip tags and stores to +trigger an exception when storing a capability with an asserted tag bit. +% +The natural translation of this idea to RISC-V, which includes architectural +support for page tables, rather than software TLB management, would be to add +two effectively identical permission bits to the current Page Table Entry +(PTE) format. +% +Unfortunately, there are no remaining spare bits in the RISC-V Sv32 (32-bit) +PTE format for additional hardware permissions. +(For the purposes of prototyping, we could utilize the two +available software-defined PTE permission bits -- but these are likely to be +used in current operating systems, requiring a longer-term solution.) +% +The Sv39 (39-bit) and Sv48 (48-bit) PTE formats include several reserved bits, +some of which we allocate for use by CHERI-RISC-V; see \cref{fig:riscv:sv39}. +% +We go beyond the CHERI-MIPS permission taxonomy and offer more nuanced control +over and observation of capability flow through pages. + +\subsubsection{Capability Stores} + +Capability stores are mediated with two bits per PTE, called CW and CD. Their +effect on capability flow parallels the existing W and D bits and is described +by the following table: + +\begin{center} +% +\begin{tabular}{ccl} + +\textbf{CW} & \textbf{CD} & \textbf{Behavior} \\ +0 & X & Trap on capability stores (exception code \riscvstorecappagefault{}) \\ +1 & 0 & Capability stores atomically raise CD or fault (as above) \\ +1 & 1 & Capability stores permitted +\end{tabular} +% +\end{center} + +\noindent Currently, implementations must apply these behaviors to all +instructions which would store an asserted capability tag; that is, they are +dependent on the tag bit. This may be relaxed in future versions of this +specification to all instructions which \emph{could} store an asserted +capability tag, removing the dependence on the tag bit. Instructions which are +able to move only data (and so necessarily clear tags) will not interact with +these PTE flags. CHERI-aware Sv32 implementations, lacking room in their PTEs, +will act as though CW and CD are \emph{set}. + +As with the existing D bit, there are two permitted approaches for hardware to +take in response to an attempted store with an asserted CHERI tag and through a +PTE with clear CD: +% +\begin{inenum} +% + \item raise a store capability page fault (exception code + \riscvstorecappagefault{}), or +% + \item atomically update the PTE to set CD. In this case, the existing rules + regarding atomicity continue to apply: the PTW must check, atomically, that + the PTE is valid and has W and CW both set, and the PTE update must become + visible no later than the causal store. +% +\end{inenum} +% +Capability-store instructions are still stores and so are expected to check the +W permission, in addition to CW, and to set the existing D bit (or fault if it +is clear, using the existing RISC-V \xcause{} code) in addition to the CD bit +(or fault, using the new capability store/AMO page fault \xcause{} code). +% +The ordering of checks of, and updates to, the PTE follows the scheme of RISC-V +but interdigitates capability mediation: V, U, and W must be checked first, +followed by CW, before any of D and/or CD (and/or A) are atomically asserted or +are used as grounds for faulting. In the latter case, D and/or A take +precedence over CD. + +The PTE bits CW and CD have no necessary relationship to any of the CHERI tag +bits on the corresponding physical page. In particular, CD does not reflect +the presence of capabilities on the page, much as D does not reflect anything +about the particular values of data on a page. Software-enforced temporal +safety mechanisms, for example, are anticipated to regularly clear CD (and +even, occasionally, CW) on PTEs referencing pages that nevertheless contain +capabilities. + +\subsubsection{Capability Loads} + +Aside from experimental behavior,\nwfnote{to be fwd ref'd} there are three +behaviors we would like to elicit upon attempted load of a capability: succeed, +strip loaded tags, or raise a fault. To leave sufficient room for +experimentation, we reserve three bits for mediation of capability loads, CR, +CRM, and CRG, but we reserve most configurations (which will raise page faults +by virtue of being invalid settings in PTEs). These bits interact with +capability flow as follows: + +\begin{center} +% +\begin{tabular}{cccl} + +\textbf{CR} & \textbf{CRM} & \textbf{CRG} & \textbf{Behavior} \\ +0 & 0 & 0 & Capability loads strip tags on loaded result \\ +0 & 1 & 0 & Capability loads fault (exception code \riscvloadcappagefault) \\ +0 & X & 1 & \textit{Reserved for future use} \\ +1 & 0 & 0 & Capability loads are unaltered \\ +1 & 0 & 1 & \textit{Reserved for future use} \\ +1 & 1 & X & \textit{Reserved for generational load barriers} +\end{tabular} +% +\end{center} + +\noindent As with CW/CD, implementations are required to take a data-dependent +disposition when a PTE is configured to fault on a capability load, raising +faults only when the resulting tag is set. Future versions of this +specification may, similarly, relax this to any instruction which \emph{could} +load a capability with a set tag. CHERI-aware Sv32 implementations will act as +though CR is \emph{set} and both CRM and CRG are clear. + +\nwfnote{Asking as an almost entirely software person... might it be +possible to use Sv39 PTE layouts on an otherwise standard RV32 machine? +Rather than using a 3-level translation table, one could maintain a 2-level +scheme by requiring the use of aligned, consecutive pairs of physical pages +for PDs and PTs, or even a kind of gross hybrid in which the PDs retain +their Sv32 structure and only the leaf PTs become increasingly aligned and +full of 64-bit structures. Atomic operations in software against the page +structures would be impossible without some treachery, but these are +unlikely to be required by software. This may also not be very attractive, +as it fundamentally makes CHERI-RISC-V an odd duck, but existing RISC-V code +is likely relatively easily adopted to such a Sv39-on-32 scheme.} + +\begin{figure} + +\begin{center} +\begin{bytefield}[endianness=big,bitwidth=2.4em]{16} +\bitheader[lsb=48]{48,53,54,58,59,60,61,62,63}\\ +\bitbox{1}{CW} +\bitbox{1}{CR} +\bitbox{1}{CD} +\bitbox{1}{CRM} +\bitbox{1}{CRG} +\bitbox{5}{\textit{Reserved}} +\bitbox{6}{PPN[2] \dots}\\ + +\bitheader[lsb=32]{32,47}\\ +\bitbox{16}{\dots PPN[2] \dots} \\ + +\bitheader[lsb=16]{16,18,19,27,28,31}\\ +\bitbox{4}{\dots PPN[2]} +\bitbox{9}{PPN[1]} +\bitbox{3}{PPN[0] \dots}\\ + +\bitheader{0,1,2,3,4,5,6,7,8,9,10,15}\\ +\bitbox{6}{\dots PPN[0]} +\bitbox{2}{RSW} +\bitbox{1}{D} +\bitbox{1}{A} +\bitbox{1}{G} +\bitbox{1}{U} +\bitbox{1}{X} +\bitbox{1}{W} +\bitbox{1}{R} +\bitbox{1}{V} +\end{bytefield} +\end{center} + +\caption{A Sv39 PTE showing CHERI extensions in bits 59 through 63.} +\label{fig:riscv:sv39} +\end{figure} + +\subsection{The RV128 LQ, SQ, and Atomic Instructions} +\label{section:cheri-risc-v-rv128-lq-sq} + +The putative 128-bit RISC-V ISA (RV128) reserves additional quadword load and +store instructions, \insnnoref{LQ} and \insnnoref{SQ}, to be +used to load and store 128-bit quantities, as well as quad-word atomics. +In CHERI-RISC-V for RV64, we reuse these hypothesised opcode encodings for our +129-bit capability load and store instructions, \insnriscvref{LC} and +\insnriscvref{SC}, to avoid additional opcode commitment. +We also introduce corresponding atomics on capabilities reusing the +quad-word atomic opcodes. + +Should the future RV128 standard utilize 128-bit addresses, then the most +natural course of action would be to utilize compressed 256-bit capabilities, +and add new capability load and store opcodes for the broader capability +width. +However, should an RV128 be defined that instead uses 64-bit virtual +addresses (i.e., one with 128-bit data registers but not a 128-bit address +space), our current opcode-space reuse would not be appropriate for a +corresponding CHERI-RISC-V variant. +Overloaded opcodes might reduce intentionality and in the split register-file +configuration we would be unable to distinguish operations intended for the +integer register file vs. the capability register file. +With respect to intentionality, it remains to be seen how essential this +concern is with respect to security: tag-free copies could still be +implemented efficiently by stripping Permit\_Load\_Capability from a source +capability during a memory copy. +However, the alignment requirements imposed by our capability load, store, +and atomic instructions can be beneficial in debugging what is otherwise +potential tag loss. +Should RV128 be more fully specified in the future, we will need to revisit +whether capability load instructions can be combined with the +\insnnoref{LQ}, \insnnoref{SQ}, and atomic instructions. + +\subsection{The AUIPC Instruction} +\label{section:cheri-risc-v-auipc} + +The RISC-V \insnnoref{AUIPC} instruction generates an address derived +from \PC{} and a 20-bit immediate, typically intended to be used in generating +addresses for global variables. +Because this instruction occupies a significant amount of opcode space, we +choose to implement a capability-based version of the instruction only in the +capability encoding mode, where the instruction returns a capability derived +from \PCC{} rather than an integer virtual address. +When using \insnnoref{AUIPC} to generate an integer in the capability +encoding mode, or a capability in the integer encoding mode, an additional, +less efficient, instruction sequence must be used instead. +Depending on the code linkage model, it might also be desirable to have a +further version of the instruction, \insnnoref{AUICGP}, which returns +a capability derived from a global capability table register. + +\subsection{\PCC{} alignment} +\label{section:cheri-risc-v-pcc-align} + +Matching the RISC-V specification, we specify that installation of an +insufficiently aligned \PC{} triggers exception at the jump rather than at +the jump target. +However, CHERI-RISC-V poses additional potential alignment issues. +In particular, an unaligned base in \PCC{} would force either its address +or its offset to be similarly unaligned. +Since the architecturally visible \PC{} is the offset of \PCC{}, allowing +this to be unaligned would break assumptions made by RISC-V software, while +allowing the address to be unaligned may break assumptions made in +RISC-V SoCs. +We instead specify that the \PCC{} base must be 4-byte aligned when compressed +instructions are disabled. +This is enforced on the capability-based jump instruction, throwing an +Unaligned Base exception. +Whenever compressed instructions are enabled, the \PCC{} base may be aligned to +only 2 bytes, however writes to the WARL field of \texttt{misa} to re-enable +compressed instructions are ignored while the \PCC{} base is not 4-byte +aligned, as is the case if the \PC{} would be unaligned. +The following edge-case behaviors relating to CSRs/SCRs are also specified: +\begin{itemize} +\item \insnriscvref{CSpecialRW} instructions that attempt to write a capability + into \xTCC{} with a base that is not 4-byte aligned (regardless of whether + compressed instructions are enabled) shall leave \xTCC{} unmodified. + This simplifies the treatment of the lowest two bits of \xtvec{}, + which are used in the RISC-V specification to determine the vectoring + mode of an exception. +\item \xEPCC{} can be written with an arbitrarily aligned base. + Reads of \xEPCC{} (via \xRET{}, \insnriscvref{CSpecialRW}, or CSR read + from \xepc{}) implicitly mask the offset as per \xepc{} in the RISC-V + specification, triggering a Representability Violation if the resulting + capability is unrepresentable. + An \xRET{} to a capability with an insufficiently aligned base causes an + Unaligned Base exception on the following instruction fetch. +\end{itemize} + +\pmnote{Perhaps add a sub-section on PCC alignment: The RISC-V + architecture has the property that with the RVC compressed + instruction-set extension, the processor cannot generate + fetch-misaligned faults. However, if PCC is improperly set, then + CHERI-RISC-V could generate such faults. Since compiler-generated + code would normally use aligned offsets, we could just ensure that + explicit assignments to PCC result in an aligned base. One way to + ensure this would be to zero the lowest bits needed for alignment: + lowest bit for RVC, and lowest 2-bits for non-RVC systems. It might + be simplest to always zero the lowest 2-bits, even for RVC.} + +% \subsection{Capability Encoding Mode} +% \label{subsec-cap-mode} +% +% \rwnote{This section not yet edited after planning session, relocation from +% the CHERI-RISC-V appendix.} + +% \newcommand{\capmode}{\textbf{capability encoding mode}} + +% When the \texttt{e} ``enable'' field is set, the use of capability registers and +% instructions is enabled. +% The \texttt{d} ``dirty'' field is set by hardware when the capability registers +% are written to\footnote{The dirty bit is only useful to accelerate context +% switch for an architecture with a dedicated capability register file. If the +% architecture is using a merged register file for capability and integer +% registers, the dirty field should be removed}. +% When the \texttt{m} ``mode'' field is set, the processor operates in +% ``\capmode{}''. Running in \capmode{} affects the behavior of certain +% instructions as defined below. + +% Instructions that alter the control flow and cause memory accesses for +% instruction fetches, such as branches and jumps, consider their target address +% as an offset in \PCC{}. + +% In general, data memory accesses are checked against \DDC{} when not in +% \capmode{}, and are checked against specific capability operands otherwise. +% Instruction memory accesses are always checked against \PCC{}. On exception, +% depending on the current privilege mode, the appropriate trap code capability +% \UTCC{}, \STCC{} or \MTCC{} is loaded in \PCC{}, and \PCC{} is saved in the +% appropriate \UEPCC{}, \SEPCC{} or \MEPCC{}. If the exception is a capability +% exception, the appropriate RISC-V \ucause{}, \scause{} or \mcause{} is set to a +% new ``capability exception'' cause, and the \texttt{cap idx} and \texttt{cause} +% fields of the \xccsr{} are also updated. + +% The following instruction produces a \PCC{}-derived capability when in +% \capmode{}, and an offset into \PCC{} otherwise: +% \asm{AUIPC} +% This allows the expected behavior both for integer-pointer code operating +% relative to \PCC{} or \DDC{}, and for capability-pointer code that expects to +% dereference a capability with its own bounds. + +% When in \capmode{}, the following instructions (which perform ordered +% comparisons) read their operands as capabilities and must order tagged +% capabilities after \arnote{consider tagged capabilitie greater than?} untagged capabilities. These instructions are: +% \asm{BGEU}, +% \asm{BGE}, +% \asm{BLTU}, +% \asm{BLT}, +% \asm{SLTIU}, +% \asm{SLTI}, +% \asm{SLTU}, +% \asm{SLT}. + +% When in \capmode{}, the following instructions (which perform unordered +% comparisons) read their operands as capabilities and compare all of the bits in +% the register. These instructions are: +% \asm{BNE} +% \asm{BEQ} + +% Shifts are not defined on capabilities because most shifts will quickly take an +% address out of the representable range. + +% 64-bit instructions that are specifically designed to operate on only the low 32 +% bits, similarly, do not make sense when applied to capabilities. + +% With a merged register file, the following instructions will ignore the +% capability bits on source operands and clear them on the destination register: +% \asm{ADD}, +% \asm{ADDI}, +% \asm{ADDIW}, +% \asm{ADDW}, +% \asm{ANDI}, +% \asm{AND}, +% \asm{ORI}, +% \asm{OR}, +% \asm{SLLIW}, +% \asm{SLLI}, +% \asm{SLLI}, +% \asm{SLLW}, +% \asm{SLL}, +% \asm{SRAIW}, +% \asm{SRAI}, +% \asm{SRAI}, +% \asm{SRAW}, +% \asm{SRA}, +% \asm{SRLIW}, +% \asm{SRLI}, +% \asm{SRLI}, +% \asm{SRLW}, +% \asm{SRL}, +% \asm{SUB}, +% \asm{SUBW}, +% \asm{XORI}, +% \asm{XOR}. + +% With a merged register file, the \asm{LUI} instruction clears all of the +% capablity bits in the destination register. + +% When in \capmode{}, \asm{JALR} and \asm{JAL} write the capability link register +% with \PCC{} + 4. \asm{JALR} also uses a capability operand for the target of +% the jump. +% \dcnote{It would be nice if they could set a thing that's both a capability and a valid address, but that's possible only if we don't do PCC-offsetting.} +% +% When not in \capmode{}, all existing load and store instructions treat the +% memory address as a \DDC{}-relative address. With a merged register file, when +% not in \capmode{}, load instructions will zero all of the capability bits in +% their target register. When in \capmode{}, the address operand is a capability +% register. +% \asm{LBU}, +% \asm{LB}, +% \asm{LD}, +% \asm{LHU}, +% \asm{LH}, +% \asm{LWU}, +% \asm{LW}, +% \asm{SB}, +% \asm{SD}, +% \asm{SH}, +% \asm{SW}. + +\pmnote{Need a section on capability state on reset.} diff --git a/chap-cheri-x86-64.tex b/chap-cheri-x86-64.tex new file mode 100644 index 00000000..f1eaf35c --- /dev/null +++ b/chap-cheri-x86-64.tex @@ -0,0 +1,639 @@ +\chapter{The CHERI-x86-64 Instruction-Set Architecture (Sketch)} +\label{chap:cheri-x86-64} + +\rwnote{New introduction is required, and some change of pitch.} + +In this chapter, we explore models for applying CHERI protection to the x86 +architecture. +The x86 architecture is a widely deployed CPU architecture used in a +variety of applications ranging from mobile to high-performance computing. +The architecture has evolved over time from 16-bit processors without +MMUs to present-day systems with 64-bit processors supporting virtual +memory via a combination of segmentation and paging. + +The x86 architecture has spanned three register sizes (16, 32, and +64 bits) and multiple memory management models. We choose to define +CHERI solely for the 64-bit x86 architecture for a variety of reasons +including its more mature virtual-memory model, as well as its larger +general-purpose integer register file. + +\section{Capability Registers versus Segments} + +The x86 architecture first added virtual memory support via +relocatable and variable-sized segments. Each segment was assigned a +mask of permissions. Memory references were resolved with respect to a +specific segment including relocation to a base address, bounds +checking, and access checks. Special segment types permitted transitions +to and from different protection domains. + +These features are similar to features in CHERI capabilities. +However, there are also some key differences. + +First, x86 addresses are stored as a combination of an offset and a +segment spanning two different registers. General-purpose registers +are used to hold offsets, and dedicated segment selector registers are +used to hold information about a single segment. The x86 architecture +provides six segment selector registers -- three of which are reserved +for code, stack, and general data accesses. A fourth register is +typically used to define the location of thread-local storage (TLS). +This leaves two segment registers to use for fine-grained segments +such as separate segments for individual stack variables. These +registers do not load a segment descriptor from arbitrary locations in +memory. Instead, each register selects a segment descriptor from a +descriptor table with a limited number of entries. One could treat +the segment descriptor tables (or portions of these tables) as a cache +of active segments. + +Second, more fine-grained segments are not derived from existing +segments. Instead, each entry in a descriptor table is independent. +Write access to a descriptor table permits construction of arbitrary +segments (including special segments that permit privilege +transitions). Restricting descriptor-table write access to kernel +mode does not protect against construction of arbitrary segments in +kernel mode due to bugs or vulnerabilities. As a result, segment +descriptors are not able to provide the same provenance guarantees as +tagged capabilities. + +Third, existing segment descriptors do not have available bits for +storing types or permissions more expressive than the existing +read, write, and execute. + +Finally, x86 segmentation is typically not used in modern operating +systems. On the 32-bit x86 architecture, systems generally create +segments with infinite bounds and use a non-zero base address only +for a single segment that provides TLS. The 64-bit x86 architecture +codifies this by removing segment bounds entirely and supporting non-zero-base +addresses only for two segment registers. +Software for x86 systems stores only the offset portion of virtual +addresses in pointer variables. Segment registers are set to fixed +values at program startup, never change, and are largely ignored. + +One approach for providing a similar set of features to CHERI +capabilities on x86 would be to extend the existing segment primitives +to accommodate some of these differences. For example, descriptor-table +entries could be tagged, whereby loading an untagged segment would trigger +an exception. However, some other potential changes are broader in +scope (e.g., whether segment selectors should contain an index into a +table, versus a logical address of a segment descriptor). Extending +segments would also result in a very different model compared to CHERI +capabilities on other architectures, limiting the ability to share code +and algorithms. Instead, we propose to add CHERI capabilities to 64-bit +x86 by extending existing general-purpose integer registers. + +\section{Tagged Capabilities and Memory} + +As with CHERI-MIPS and CHERI-RISC-V, we recommend that both memory and +registers contain tagged capabilities. Similar to CHERI-RISC-V, we also +recommend a single, 128-bit format for CHERI-x86-64 capabilities. + +\section{Extending Existing Registers} + +The x86 architecture has expanded its general-purpose integer registers multiple +times. Thus, the 16-bit \AX{} register has been extended to 32-bit \EAX{} +and 64-bit \RAX{}. +We propose extending each general-purpose integer register to a tagged, 128-bit register +able to contain a single capability. +The capability-sized registers would be named with a `C' prefix in place +of the `R' prefix used for 64-bit registers +(\CAX{}, \CBX{}, etc.). +As with CHERI-RISC-V, +we recommend that reads of the general-purpose registers as integers return +the cursor value (virtual address). +Writes to general-purpose registers using non-capability-aware instructions +should clear the tag and upper 64 bits of capability metadata, storing the +desired integer value in the register's cursor. + +The \RIP{} register (which contains the address of the current instruction) +would also be extended into a \CIP{} capability. This would function as +the equivalent of \PCC{} for CHERI-MIPS and CHERI-RISC-V. As with +those architectures, the +value of \RIP{} should be the current offset of \CIP{} rather than the +cursor value (virtual address). + +\section{Additional Capability Registers} + +Additional capability registers beyond those present in the general-purpose +integer +register set will also be required. + +A new register will be required to hold \DDC{} for controlling +non-capability-aware memory accesses. + +The x86 architecture currently uses the \FS{} and \GS{} segment selector registers +to provide thread-local storage (TLS). In the 64-bit x86 architecture, +these selectors are mostly reduced to holding an alternate base address +that is added as an offset to the virtual address of existing instructions. +For CHERI-x86-64 we recommend replacing these segment registers with two +new capability registers: \CFS{} and \CGS{}. + +In addition, new capability registers may be required to manage user +to kernel transitions as detailed below. + +\section{Using Capabilities with Memory Address Operands} + +As with other CHERI architectures, CHERI-x86-64 should support running existing +x86-64 code, capability-aware code, and hybrid code. This +requires the architecture to support multiple addressing modes. +The x86 architecture has implemented this in the past when it was +extended to support 32-bit operation. We propose to reuse some of the +same infrastructure to support a new capability-based addressing +mode. + +When x86 was extended from 16 bits to 32 bits, the architecture +included the ability to run existing 16-bit code without modification +as well as execute individual 16-bit or 32-bit instructions within a +32-bit or 16-bit codebase. The support for 16-bit versus 32-bit +operation was +split into two categories: operand size and addressing modes. The +code segment descriptor contains a single-bit `D' flag, which sets the +default operand size and addressing mode. These attributes can then +be toggled to the non-default setting via opcode prefixes. The 0x66 +prefix is used to toggle the operand size, and the 0x67 prefix is used +to toggle the addressing mode. + +In 64-bit (``long'') mode, the `D' flag is currently always set to +0 to indicate 32-bit operands and 64-bit addressing. A value of +1 for `D' is reserved. The 0x67 opcode prefix is used to toggle +between 32-bit and 64-bit addresses, but a few other single-byte opcodes +are invalid in 64-bit mode and could be repurposed as a prefix. + +We propose a new capability-aware addressing mode that can be +toggled via the `D' flag of the current code segment and a new 0x62 +opcode prefix. (In 32-bit x86, the 0x62 opcode is the +\insnnoref{BOUND} instruction, which is invalid in 64-bit mode.) +If the `D' flag of a 64-bit code segment is set to 1, +then the CPU would execute in ``capability mode'' -- which would include +using the capability-aware addressing mode by default. Individual +instructions could toggle between capability-aware and ``plain'' +64-bit addressing via the 0x62 opcode prefix. Addresses using the +``plain'' 32-bit or 64-bit addressing would always be treated as offsets +relative to \DDC{}. Instructions using capability-aware addressing +would always use 64-bit virtual addresses and ignore any 0x67 opcode +prefix. + +Note that one can change the value of \CS{} in user mode (for example, +a user process in FreeBSD/amd64 can switch between 32 and 64-bit by +using a far call that loads a different value of \CS{}). This would mean +that user code could swap into pure-capability mode without requiring +a system call. However, this would not alter the contents of +capability registers or their enforcement, merely the decoding of +instructions. If \DDC{} is invalid, then sandboxed code that switched to +a non-capability \CS{} would still require valid capability registers to +access memory. + +\subsection{Capability-Aware Addressing} + +For instructions with register-based memory operands, capability-aware +addressing would use the capability version of the register rather +than the virtual address relative to \DDC{}. + +For example: + +\begin{verbatim} +mov 0x8(%cbp),%rax +\end{verbatim} + +would read the 64-bit value at offset 8 from the capability described +by the \CBP{} register. + +On the other hand, + +\begin{verbatim} +mov 0x8(%rbp),%rax +\end{verbatim} + +would read the 64-bit value at an offset of RBP+8 from the \DDC{} capability. +Both instructions would use the same opcode aside from the addition of +an 0x62 opcode prefix. In a code segment with `D' set to 1, the second +instruction would require the prefix. In a code segment with `D' set to 0, +the first instruction would require the prefix. + +\subsection{Scaled-Index Base Addressing} + +x86 also supports an addressing mode that combines the values of two +registers to construct a virtual address known as scaled-index base +addressing. These addresses use one register, the \emph{base}, and a +second register, the \emph{index}, multiplied by a scaling factor of 1, 2, +4, or 8. For these addresses, capability-aware addresses would select +a capability for the base register, but the index register would use +the integer value of the register. For example: + +\begin{verbatim} +mov (%rax,%rbx,4),%rcx +\end{verbatim} + +This computes an effective address of \RAX{} + \RBX{} * 4 and loads the value +at that address into \RCX{}, The capability-aware version would be: + +\begin{verbatim} +mov (%cax,%rbx,4),%rcx +\end{verbatim} + +That is, starting with the \CAX{} capability, \RBX{} * 4 would be added to the +offset, and the resulting address validated against the \CAX{} capability. + +\subsection{RIP-Relative Addressing} + +The 64-bit x86 architecture added a new addressing mode to support more +efficient Position-Independent Code (PIC) performance. +This addressing mode uses an immediate offset +relative to the current value of the instruction +pointer. These addresses are known as \RIP{}-relative addresses. + +To support existing code, \RIP{}-relative addresses should be resolved +relative to \DDC{} when using ``plain'' 64-bit addressing. +Specifically, the value of \RIP{} (offset of \CIP{}) would be added to +the immediate offset. The resulting value would then be used as an +offset relative to \DDC{} for the load or store. + +When capability-aware addressing is used, \RIP{}-relative addresses +should be resolved relative to \CIP{}. +The immediate offset is applied to \CIP{} and the load +or store is constrained by the bounds and permissions of \CIP{}. + +\subsection{Using Additional Capability Registers} + +The proposed capability-aware addressing mode proposed above allows +for the capability versions of existing general-purpose integer registers such +as \CAX{} or \CBP{} to be encoded in existing register instructions. +However, it does not permit the direct use of the additional +capability registers \DDC{}, \CFS{}, or \CGS{}. \DDC{} is not expected to be +used as an explicit base address, but \CFS{} and \CGS{} must be usable in this +manner to support TLS with capability-aware addresses. + +One option would be to repurpose the existing \FS{} and \GS{} segment +prefixes when used with instructions using capability-aware addresses +to select an implicit base register of \CFS{} or \CGS{}, respectively. +However, this approach is potentially confusing. Would an instruction +using an existing address of ``(\%cax)'' and an instruction prefix of +``GS:'' simply use the cursor of \CAX{} (value of \RAX{}) as an offset +relative to \CGS{}? In addition, instructions that manipulate +capabilities need a way to specify an additional capability register +as an operand. + +To handle both of these cases, we propose to reuse the existing \FS{} and +\GS{} segment prefixes to extend the capability register selector field +in opcodes. This is similar to the use of bits in \REX{} prefixes to +extend the general-purpose integer register selector fields in other +instructions. Instructions with memory addresses will use at most one +capability-register, and the \FS{} prefix could be used to select +capability registers with an index of 32 or higher. For instructions +operating on two capability registers, the \FS{} prefix would affect the +register selected for the first capability register operand, and the +\GS{} prefix would affect the register selected for the second capability +register operand. Additional capability registers such as \DDC{}, \CFS{}, +and \CGS{} would be assigned register indices starting at 32 and require +a suitable prefix. + +\subsection{Instructions with Implicit Memory Operands} + +Some x86 instructions have implicit memory operands addressed by a +register. These instructions should support addressing memory with +capabilities. + +The ``string'' +instructions use \RSI{} as source address and \RDI{} as a destination address. +For example, the +\insnnoref{STOS} instruction stores the value in \AL{}/\AX{}/\EAX{}/\RAX{} to the address in +\RDI{}, and then either increments or decrements the destination +index register (depending on the Direction Flag). When capability +addressing mode is enabled, +these string instructions should use \CSI{} instead of \RSI{} and \CDI{} instead of +\RDI{}. + +Instructions that work with the stack such as \insnnoref{PUSH} +or \insnnoref{CALL} use the stack pointer as an implicit +operand. In plain 64-bit mode, \RSP{} would be treated as an offset +into \DDC{} to compute the stack pointer. In ``capability mode'', +these instructions would use \CSP{} as the stack pointer. Hybrid code +executing in plain 64-bit mode that uses \CSP{} as the stack pointer +would simulate these instructions using \insnnoref{MOV} +instructions and adjusting the offset of \CSP{}. Similarly, +``capability mode'' instructions using \RSP{} as the stack pointer +would use \insnnoref{MOV} combined with adjustments to \RSP{}. + +\section{Capability-Aware Instructions} + +\subsection{Control-Flow Instructions} + +Existing control-flow operations such as \insnnoref{JMP}, +\insnnoref{CALL}, and \insnnoref{RET} would modify the offset of the +\CIP{} capability as well as verify that the new offset is valid. + +New instructions would be required when performing a control-flow +operation that loads a full \CIP{} capability. For example, a new +\insnnoref{CJMP} instruction would accept either a capability register +or an in-memory capability as its sole argument and load the new capability +into \CIP{} similar to the CHERI-RISC-V \insnriscvref{CJR} instruction. +New \insnnoref{CCALL} and \insnnoref{CRET} instructions would be +used for function calls that push the full \CIP{} capability onto the stack +as the return address. + +One option for these new instructions may be to use an opcode prefix +to toggle between loading a \RIP{} offset versus a full \CIP{} +capability. In that case, the default mode of an instruction may be +governed by the `D' flag of the current code segment to permit compact +instruction encoding for capability-aware software. Note that since +\insnnoref{CALL} and \insnnoref{JMP} may accept a memory +operand, this opcode prefix would need to be a different prefix than +the 0x62 used to toggle addressing modes. + +Another option that avoids the use of a new opcode prefix would be to +offer new instructions that always operate on \CIP{} and choose a +subset of comonly-used but shorter opcodes that default to loading a +full \CIP{} instead of \RIP{} in ``capability mode''. + +The implicit stack pointer operand in \insnnoref{CALL} and +\insnnoref{RET} also bears consideration. To avoid an +explosion of new opcodes while also providing compact enoding for +common uses, these instructions would use \CSP{} as the stack pointer +in ``capability mode'' and \RSP{} as the stack pointer in plain 64-bit +mode. Code that needed to use an alternate stack pointer would use +explicit stack manipulation along with \insnnoref{JMP}. + +\subsection{Manipulating Capabilities} + +New instructions will need to be defined to support capability +manipulations similar to other CHERI architectures. + +New \insnnoref{MOV} variants could handle loading and storing of +capabilities similar to \insnref{CLC} and \insnref{CSC}. + +NULL-derived capabilities with constant values can be loaded into +registers using existing \insnnoref{MOV} instructions which +write into general purpose registers since those instructions will +clear the upper 64-bits of metadata as a side effect. Arbitrary +null-derived capabilities can be stored to memory as a two instruction +sequence where the first instruction uses an existing +\insnnoref{MOV} of an immediate value into a general purpose +register and the second stores the aliased capability register value +into the destination. + +However, storing NULL pointers into memory is a frequent operation +which might warrant optimization. A few alternatives include: + +\begin{enumerate} + \item Use a two instruction sequence where the first instruction is + a well-known instruction for generating a zero value. Modern + x86 CPUs complete such instructions during decoding so only the + second instruction would use execution pipeline resources. + However, this requires using a general purpose register to hold + the temporary zero value. + + \item Add a read-only \CNULL register in the additional bank of + capability registers which can be used as the source of a + capability-sized \insnnoref{MOV}. + + \item Add a new \insnnoref{MOVNULL} instruction which stores + a NULL capability to the destination. +\end{enumerate} + +A new variant of \insnnoref{CMPXCHG} will be required to support +atomic operations on capabilities. (Note that \insnnoref{CMPXCHG16B}'s +existing semantics are not suitable for capabilities +as it divides the values into register pairs.) It may also be +desirable to define a capability variant of \insnnoref{XADD}. + +Variants of \insnnoref{PUSH}/\insnnoref{POP} could be used to +save and restore capability registers on the stack -- if those operations +are common enough to warrant new instructions rather than using +capability \insnnoref{MOV} instructions paired with adjustments to +\CSP{}. + +For other capability operations such as \insnref{CIncOffset}, we +propose adding new CHERI-specific instructions rather than +repurposing existing instructions such as \insnnoref{ADD}. +Existing general-purpose x86 instructions support two operands rather +than three operands. To avoid introducing a new operand encoding +format, we propose to use two-operand variants of CHERI +instructions when adapting instructions to x86. + +The \insnnoref{LEA} instruction warrants additional consideration. +When capability mode addressing is enabled for this instruction, the +effective address should be a capability stored in a capability +destination register. This would permit the use of \insnnoref{LEA} +to perform some operations such as \insnref{CIncOffset}, without +overwriting the source capability register. + +Some x86 instructions such as \insnnoref{MOV} have variants +which accept operands of differing sizes. Assemblers and +disassemblers can use suffixes such as \texttt{b}, \texttt{w}, +\texttt{l}, and \texttt{q} to explicitly state the operand size. We +recommand that the \texttt{c} suffix be used to explicitly state +operands which are capability-sized. + +\subsection{Inspecting Tags} + +CHERI-MIPS provides dedicated \insnref{CBTU} and +\insnref{CBTS} instructions for conditional branches. For x86, a +more natural model may be to add a new ``tagged'' flag to the +\RFLAGS{} register. Any instruction that stored a capability such as +capability-aware variants of \insnnoref{MOV} would set this +flag to the tag bit of the stored capability. New conditional jump +instructions would be added that tested this flag. + +\section{Capability Violation Faults} + +For reporting capability violations, we propose reserving a new +exception vector. This new exception would report an error code +pushed as part of the exception frame similar to GP\# and PF\# faults. +This error code would contain the capability exception code as +described in Section~\ref{sec:capability_exception_causes} to indicate +the specific violation. + +CHERI-MIPS and CHERI-RISC-V include the name of the register which +triggers a capability violation. It is not feasible to provide a +direct analog of this on x86. Indirect jumps and calls may raise an +exception while loading a capability from memory that is not present +in any register at the start of the instruction. However, unlike page +faults, capability violation faults are not generally restartable and +the register name's primary use is for debugging convenience rather than +correctness. There are a few possible options for providing similar +information: + +\begin{enumerate} +\item Provide a copy of the faulting capability via one of the + currently-unused but reserved control registers, such as \CRFIVE{} + or \CRTWELVE{} -- similar to the PF\# virtual address stored in + \CRTWO{}. This faulting capability would include the result of any + offset adjustments from immediates or scaled indices. If the result + of offset adjustments made the capability unrepresentable, the + faulting capability would be a null capability holding the computed + virtual address. +\item Similar to the above, but ignore offset adjustments and only + provide the base capability value. +\item Provide the virtual address from the faulting capability in + \CRTWO{} similar to PF\#. A debugger could examine the faulting + instruction's operands to determine which capability triggered the fault. +\item Do nothing as the prior approaches may be too expensive to + implement. +\end{enumerate} + +\section{Interrupt and Exception Handling} + +For interrupt and exception handling, we propose a new overall CPU +mode that enables the use of capabilities. The availability of this +mode would be indicated by a new \insnnoref{CPUID} flag. The +mode would be enabled by setting a new bit in \CRFOUR{}. When this mode +is enabled, exceptions would push a new type of interrupt frame that +would replace \RIP{} with the full \CIP{} capability, and \RSP{} with the full +\CSP{} capability. \insnnoref{IRET} would be modified to unwind this expanded stack +frame. + +Interrupt and exception handlers require new capabilities for the +program counter (\CIP{}) and stack pointer (\CSP{}) registers. We consider +two possible approaches. + +\subsection{Kernel Code and Stack Capabilities} + +The first approach would add two new control registers: the Kernel +Code Capability (\KCC{}) and Kernel Stack Capability (\KSC{}). Access to +these registers would be restricted to supervisor mode. These new registers +could be named as instruction operands, using the same approach decribed +earlier for \CFS{} and \CGS{}. + +Transitions into +supervisor mode would load new offsets relative to \KCC{} and \KSC{} from +existing data structures and tables to construct the new \CIP{} and \CSP{} +register values. For example, the current virtual address stored in +each Interrupt Descriptor Table (\IDT{}) entry would be used as an offset +relative to \KCC{} to build \CIP{}, and the address stored in the Interrupt +Stack Table (\IST{}) entry in the current Task-State Segment (\TSS{}) would +be used as an offset relative to \KSC{} to build \CSP{}. Transitions via +the \insnnoref{SYSCALL} instruction would use the offset from \LSTAR{} to +construct the new \CIP{}. + +This approach does require broad capabilities +for \KCC{} and \KSC{} that can accommodate any desired entry point or stack +location. However, it will require minimal changes to existing systems +code such as operating-system kernels. + +\subsection{Capabilities in Entry Points} + +The second approach would be to replace virtual addresses stored in +existing entry points with complete capabilities. This is a more +invasive change, requiring larger changes to existing systems code, but +it enables the use of more fine-grained capabilities for each entry +point. + +Setting the desired kernel stack pointers \CSP{} would require a new +\TSS{} layout that expanded the existing \RSP{} and \IST{} entries to +capabilities. + +For \insnnoref{SYSCALL}, a new control register \CSTAR{} could be +added to hold the target instruction pointer. As with \KCC{}, +this register would be a privileged register in the same bank as +\CFS{} and \CGS{}. + +Entries in the \IDT{} would be expanded to 32-bytes, appending a capability +code pointer in the last 16 bytes. This would double the size of the +\IDT{}, and most of the bytes would be unused. However, it would +ensure that all of the information currently stored in an \IDT{} entry +(such as the segment selector, \IST{} index, and descriptor type) would +be configurable. + +\subsection{\insnnoref{SWAPGS} and Capabilities} + +The \insnnoref{SWAPGS} instruction is used in user-to-kernel +transitions for the 64-bit x86 architecture to permit separate TLS +pointers for user and kernel mode. One option would be to provide a +capability version of \insnnoref{SWAPGS}, either by extending the +\KGSBASE{} MSR to a capability, or adding a new MSR. However, this +instruction can be difficult to use. Interrupt and exception handlers +must be careful not to invoke \insnnoref{SWAPGS} if the interrupt +or exception is taken while executing the kernel mode \GS{}. We +recommend avoiding the use of \insnnoref{SWAPGS}, and instead defining +a new privileged control register \KGS{}. Operating systems could +either choose to use \KGS{} to initialize \CGS{} in interrupt and +exception handlers, or else use \KGS{} directly as the kernel mode TLS +pointer. + +\section{Page Tables} + +Similar to CHERI on other architectures, additional page-table +permission bits governing loads and stores of capabilities are +desirable. In addition, it may be beneficial to have a ``capability +dirty'' bit. At present the 64-bit x86 architecture has reserved bits +in a range from bit 52 (\texttt{MAXPHYADDR}) to bit 62. The Protection Keys +extension uses bits 59-62 from that range. To avoid conflicting with +Protection Keys, CHERI-x86-64 could use bits starting at bit 58 as described in Table~\ref{table:x86:pte}. Higher bits are +preferred, to permit maximal room for growth of the physical address +field that currently ends at bit 51. + +\begin{table} +\begin{center} +\begin{tabular}{lll} +\toprule +Bit & Name & Description \\ +\midrule +58 & CW & Permits writes of tagged capabilities \\ +57 & CR & Permits reads of tagged capabilities \\ +56 & CD & Set when a tagged capability is written to this page \\ +\bottomrule +\end{tabular} +\end{center} +\caption{CHERI-x86-64 Page Table Bits} +\label{table:x86:pte} +\end{table} + +If an instruction performs a memory access which violates a CHERI page +permission (such as a store of a tagged capability to a page where the +\texttt{CW} bit is clear), a page-fault (PF\#) exception should be +raised. Bit 6 (currently reserved) should be set in the page-fault +error code provided by the processor indicating that the fault was +caused by a capabilty permission violation. Other bits in the page +fault error code such as \texttt{P}, \texttt{W/R}, \texttt{U/S}, and +\texttt{I/D} should be set to indicate the type of memory access. In +addition, the virtual address of the memory access should be provided +in the \CRTWO{} register similar to other page-fault exceptions. + +Note that the \texttt{CR} and \texttt{CW} bits only fault if the +capability being read or written is tagged. Untagged capability +values can be read from or written to memory regardless of the +\texttt{CR} and \texttt{CW} permissions. In addition, if the +authorizing capability for a capability read does not hold \cappermLC, +then reading a tagged capability will always return a capability with +the tag cleared instead of faulting. + +Instruction fetches always ignore tags and will never raise a +capability page-fault exception. + +\section{Capabilities and Integer Instructions} + +Throughout this chapter, we have proposed that CHERI-x86-64 should +assume that existing integer instructions writing to a capaiblity +register should always strip the tag with the exception of +\insnnoref{LEA} in capability mode. This approach offers the +following benefits: + +\begin{itemize} +\item +It avoids ``implicit'' operations on capabilities. +\item +It is consistent with 32-bit instructions zero-extending results when +stored in 64-bit registers in long mode. +\item +Micro-architecturally it permits integer instructions to always assume +an untagged output. +\end{itemize} + +However, an alternative approach would be for integer instructions to +instead perform the requested integer operation against the virtual +address, and strip the tag only if the new virtual address results in +unrepresentable bounds. In this model, existing instructions such as +\insnnoref{ADD} or \insnnoref{SUB} could be used in +place of \insnref{CIncOffset}. This would offer the following +benefits: + +\begin{itemize} +\item +Pointer manipulations may be able to use shorter instructions, because +new capability-specific instructions will all likely be using 2- +and 3-byte opcodes. +\item +Fewer new opcodes may be required, because some capability instructions +might be fully implemented via existing instructions. +\item +Compilers may be able to reuse existing code sequences for function +prologues and epilogues. +\end{itemize} diff --git a/chap-conclusion.tex b/chap-conclusion.tex new file mode 100644 index 00000000..62540908 --- /dev/null +++ b/chap-conclusion.tex @@ -0,0 +1,163 @@ +\chapter{Conclusion} +\label{chap:conclusion} +The CHERI project is in its tenth year -- an evolution described in detail in +Chapter~\ref{chap:research}. +Throughout the project, we have utilized hardware-software co-design, with an +increasing focus on also co-designing with formal models. +For the last several years, we have increased our focus on transition, +including through a close collaboration with Arm in the development of their +Morello architecture and hardware prototype~\cite{arm-morello}. +Our contributions include: + +\begin{enumerate} +\item We developed the CHERI protection model and reference CHERI-MIPS and + CHERI-RISC-V Instruction-Set Architectures, which offer low-overhead + fine-grained memory protection and support scalable software + compartmentalization based on a hybrid capability model. + Over several generations of the ISA, we refined integration with + conventional + RISCs ISA, composed the capability-system model with the MMU, pursued strong + C-language compatibility, developed compartmentalization features based on + an object-capability model, refined the architecture to improve performance + and adoptability through features such as compressed 128-bit capabilities, + introduced support for temporal memory safety, + and developed the notion of a portable protection model that can be applied + to further ISAs. + We also explored the implications of CHERI on 32-bit microcontroller + architectures + that do not have MMUs, giving capabilities a physical interpretation, and + also taking into account common microcontroller microarchitectural choices. + +\item Employed increasingly complete formal models of the protection model and + ISA semantics. + We began by using PVS/SAL formal models of the ISA to analyze + expressivity and security. + Subsequently, and in close collaboration with the University of Cambridge's + EPSRC-funded Rigorous Engineering of Mainstream Systems (REMS) Project and + DARPA-funded CHERI Instruction-set Formal Verification (CIFV), we + developed L3 and SAIL formal models suitable to act as a gold model for + testing, to use in automated test generation, and as inputs to formal + verification tools to prove ISA-level security properties. + We have also used formal modeling to explore how CHERI interacts with + C-language semantics. + In the future, we hope to employ these models in support of hardware and + software verification. + +\item Elaborated the ISA feature set in CHERI to support real-world operating + systems -- primarily this has consisted of developing mature compositions of + CHERI's concepts with system features such as the MMU and exception model, + but also programmable interrupt controllers (PICs). + We have also spent considerable time refining successive versions of + the ISA intended to better support high levels of MMU-based operating-system + and C-language compatibility, as well as automatic use by compilers. + This work has incorporated ideas from, but also gone substantially beyond, + the C-language fat-pointer and software compartmentalization research + literature. + +\item Created our CheriBSD and CheriFreeRTOS operating-system prototypes. + These reference designs explore how CHERI integration with the OS can + improve both OS and application security. + We created prototype memory protection and software compartmentalization + environments including CheriBSD's CheriABI process environment, and multiple + approaches to sandboxing. + We have applied CHERI to protection of key system libraries, but also the + operating system kernel itself. + This has included substantial baseline OS infrastructure work, including + porting FreeBSD to the budding RISC-V architecture. + +\item Prototyped, tested, and refined CHERI ISA extensions across multiple CPU + architectures. + We have open sourced reference MIPS and RISC-V processor designs, and the + QEMU ISA-level emulator, on order to allow reproducible experimentation with + our approach, as well as to act as an open-source platform for other future + hardware-software research projects. + +\item Adapted the Clang/LLVM compiler suite to be able to generate CHERI ISA + instructions as directed by C-language annotations, exploring a variety of + language models, code-generation models, and ABIs. + We have explored two new C-language models and associated code generation: + a hybrid in which explicitly annotated or automatically inferred pointers + are compiled as capabilities; and a pure-capability model in which all + pointers and implied virtual addresses are compiled as capabilities. + Similarly, we have begun an exploration of how CHERI affects program + linkage, with early prototype integration with the compile-time and run-time + linkers. + These collectively provide strong spatial and pointer protection for both + data and code pointers. + We have upstreamed substantial improvements to Clang/LLVM MIPS support, as + well as changes making it easier to support ISA features such as extra-wide + pointers utilized in the CHERI ISA. + We have also begun to explore how CHERI can support higher-level language + protection, such as by using it to reinforce memory safety and security for + native code running under the Java Native Interface (JNI). + +\item Began to develop semi-automated techniques to assist software + developers in compartmentalizing applications using Capsicum and CHERI + features. + This is a subproject known as Security-Oriented Analysis of Application + Programs (SOAAP), and performed in collaboration with Google. + +\item Collaborated with Arm on the creation of Morello~\cite{arm-morello}, a + tight integration of CHERI into the ARMv8-A architecture as well as a + reference industrial quality microarchitecture. + Morello boards will ship for experimental use in late 2021 along with our + complete CHERI software stack. +\end{enumerate} + +Collectively, these accomplishments have validated our research hypotheses: +that a hybrid capability-system architecture and viable supporting +microarchitecture can support low-overhead memory protection and fine-grained +software compartmentalization while maintaining strong compatibility with +current RISC, MMU-based, and C/C++-language software stacks, as well as an +incremental software adoption path to additional trustworthiness. +Further, the resulting protection model, co-designed around a specific ISA and +concrete extensions, is in fact a generalizable and portable protection model +that has been applied to other ISAs; it is suitable for a multitude of +implementations in architecture and microarchitecture. +Formal methodology deployed judiciously throughout the design and +implementation process has increased our confidence that the resulting design +can support robust and resilient software designs. + +\section{Future Work} +We have made a strong beginning, but clearly there is still much to do in our +remaining CHERI efforts. +Our ongoing key areas of research include: + +\begin{itemize} +\item +Continuing to refine performance with respect to both the architecture (e.g., +models for capability compression) and microarchitecture (e.g., as relates to +efficient implementations of compression and tagged memory). + +\item +Exploring how CHERI's features might be scaled up (e.g., to superscalar +processor designs), down (e.g., to 32-bit microcontrollers without MMUs), and +to other compute types (e.g., DMA engines, GPUs, and so on). +Also, looking at how CHERI interacts with other emerging hardware technologies +such as non-volatile memory, where CHERI may support more rapid, robust, and +secure adoption. + +\item +Continuing to elaborate how CHERI should affect the design of operating +systems (whether hybrid systems such as CheriBSD, or clean-slate designs), +languages (e.g., C, C++, Java, and so on), and runtimes (e.g., system +libraries, run-time linking, and higher-level language runtimes). + +\item +Continuing to explore how CHERI affects software tracing and debugging; for +example, through capability-aware software debuggers. + +\item +Continuing to explore potential models for software compartmentalization, such +as clean-slate microkernel-style message passing grounded in CHERI's +object-capability features, but not hybridized with conventional OS designs. +In addition, continuing to investigate potential approaches to semi- or +fully automated software compartmentalization. + +\item +Continuing our efforts to develop and utilize formal models of the +microarchitecture, architecture, operating system, linkage model, language +properties, compilation, and higher-level applications. +This will help us understand (and ensure) the protection benefits of CHERI up +and down the hardware-software stack. +\end{itemize} diff --git a/chap-historical.tex b/chap-historical.tex new file mode 100644 index 00000000..19583e9c --- /dev/null +++ b/chap-historical.tex @@ -0,0 +1,803 @@ +\chapter{Historical Context and Related Work} +\label{chap:historical} + +\nwfnote{There's a great deal more to say here. Suggestions include +Cambridge's CAP (esp. S-CAP), MIT's M-Machine, Intel iAPX 432, Rekursiv, IBM +System/38, Plessey System 250, RSRE Malvern Flex machine. Possibly CMU's C.mmp +(and Hydra), and Multics' descriptors as well.} + +% Intro prose <<< + +As with many aspects of contemporary computer and operating-system design, +many of the origins +of operating-system security can be found at the world's leading research +universities -- +especially the Massachusetts Institute of Technology (MIT), the University of Cambridge, +and Carnegie Mellon University. +MIT's Project MAC, which began with MIT's Compatible Time +Sharing System (CTSS)~\cite{corbato:timesharing}, +and continued over the next decade with MIT's Multics +project (joint with Honeywell, and originally Bell Labs), +described many central tenets of computer security~\cite{corbato:multics,Graham68}. +Dennis and Van Horn's 1965 {\em Programming Semantics for Multiprogrammed +Computations}~\cite{dennis:semantics} laid out principled hardware +and software approaches +to concurrency, object naming, and security for multi-programmed computer systems -- +or, as they are known today, multi-tasking and multi-user computer systems. +Multics implemented a coherent, unified architecture for processes, virtual memory, and protection, +integrating new ideas such as {\em capabilities}, unforgeable tokens of authority, and +{\em principals}, the end users with whom authentication takes place and to whom resources +are accounted~\cite{Saltzer74}. + +In 1975, Saltzer and Schroeder surveyed the rapidly expanding vocabulary of computer +security in {\em The Protection of Information in Computer Systems}~\cite{SaltzerSchroeder75}. +They enumerated design principles such as the {\em principle of least privilege} +(which demands that computations run with only the privileges they require) and +the core security goals of +protecting {\em confidentiality}, {\em integrity}, and {\em availability}. +The tension between fault tolerance and security (a recurring debate in +systems literature) saw its initial analysis in Lampson's 1974 +{\em Redundancy and Robustness in Memory Protection}~\cite{LampsonRedund}, which +considered ways in which hardware memory protection addressed accidental and +intentional types of failure: e.g., if it is not reliable, it will not be secure, +and if it is not secure, it will not be reliable! Intriguingly, recent work +by Nancy Leveson and William Young has unified security and human safety +as overarching emergent system properties~\cite{LevesonYoung14}, and allows +the threat model to fall out of the top-down analysis, rather than driving +it. This work in some sense +unifies a long thread of work that considers trustworthiness as a property +encompassing security, integrity, reliability, survivability, human safety, +and so on (e.g.,~\cite{Neumann06holistic,PSOS}, among others). + +The Security Research community also blossomed outside of MIT: +Wulf's HYDRA operating system at Carnegie Mellon University (CMU)~\cite{wulf:hydra,CohenJefferson75}, +Needham and Wilkes' CAP Computer at +Cambridge~\cite{WilkesNeedham79}, SRI's Provably Secure Operating +System (PSOS)~\cite{PSOSreport,PSOS} hardware-software co-design that included +strongly typed object capabilities, +Rushby's security kernels supported by formal +methods at Newcastle~\cite{Rushby81}, and Lampson's work on +formal models of security +protection at the Berkeley Computer +Corporation all explored the structure of operating-system access control, and +especially the application of capabilities to the protection +problem~\cite{lampson:dynamicprotection,lampson:protection}. +Another critical offshoot from the Multics project was Ritchie and Thompson's UNIX +operating system at Bell Labs, which simplified concepts +from Multics, and became the basis for countless directly and indirectly derived +products such as today's Solaris, FreeBSD, Mac OS X, and Linux operating +systems~\cite{ritchie:unix}. + +The creation of secure software went hand in hand with analysis of security flaws: +Anderson's 1972 US Air Force {\em Computer Security Technology Planning +Study} not +only defined new security structures, such as the {\em reference monitor}, but +also analyzed potential attack methodologies such as Trojan horses and +inference attacks~\cite{anderson72}. +Karger and Schell's 1974 report on a security analysis of the Multics system +similarly demonstrated a variety of attacks that bypass hardware and OS +protection~\cite{KargerSchell74}. +In 1978, Bisbey and Hollingworth's {\em Protection Analysis: Project final report} at ISI +identified common patterns of security vulnerability in operating +system design, such as race conditions and incorrectly validated arguments at security +boundaries~\cite{Bisbey78}. +Adversarial analysis of system security remains as critical to the success of security +research as principled engineering and formal methods. + +Almost fifty years of research have explored these and other +concepts in great detail, bringing new contributions in hardware, software, language +design, and formal methods, as well as networking and cryptography technologies that +transform the context of operating system security. +However, the themes identified in those early years remain topical and highly influential, +structuring current thinking about systems design. + +Over the next few sections, we consider three closely related ideas that directly influence +our thinking for CTSRD: capability security, microkernel OS design, and +language-based constraints. +These apparently disparate areas of research are linked by a duality, +observed by Jim Morris +in 1973, between the enforcement of data types and safety goals in programming languages on one hand, +and the hardware and software protection techniques explored in operating +systems~\cite{morris:protectionprogramming} on the other hand. +Each of these approaches blends a combination of limits defined by static analysis +(perhaps at compile-time), limits on expression on the execution substrate (such as what +programming constructs can even be represented), and dynamically enforced policy that generates +runtime exceptions (often driven by the need for configurable policy and labeling not known +until the moment of access). +Different systems make different uses of these techniques, affecting expressibility, +performance, and assurance. + +% >>> +\section{Capability Systems} % <<< + +Throughout the 1970s and 1980s, high-assurance systems were expected +to employ a capability-oriented design that would map program +structure and security policy into hardware enforcement; for example, +Lampson's BCC design exploited this linkage to approximate least +privilege~\cite{lampson:dynamicprotection,lampson:protection}. + +Systems such as the CAP Computer at Cambridge~\cite{WilkesNeedham79} and + +Ackerman's DEC PDP-1 architecture at MIT~\cite{ackerman:multiprocessing} +attempted to realize this vision through embedding notions of capabilities in +the memory management unit of the CPU, an approach described by Dennis and Van +Horn~\cite{dennis:semantics}. Levy provides a detailed exploration of segment- +and capability-oriented computer system design through the mid-1980s in {\em +Capability-Based Computer Systems}~\cite{levy:capabilities}. + +\subsection{Objects of Authorization} + +Dennis and Van Horn's seminal text on capability +systems~\cite{dennis:semantics} defines a capability as a structure that +locates by means of [a unique code or effective name] some computing object, +and indicates the actions that the computation may perform with respect to that +object.'' One may then ask what exactly constitutes a ``computing object,'' +and one should not be surprised to learn that there have been several answers +to that question. + +\paragraph{Memory Capability Systems} + +One answer, and perhaps the simplest, identifies a ``computing object'' with a +mere span of memory. Such systems closely resemble traditional segmented memory +architectures. + +% In their simplest form, there is no direct support for encapsulation +% of private state + +\paragraph{Software Object Capability Systems} + +In so-called ``object capability'' (``ocap'') systems, ``computing objects'' +are identified with pairs of code and private data, as in ``object-oriented +programming.'' These systems may treat objects as entirely opaque, exposing +only one or a series of ``entry'' capabilities, corresponding to object +methods, or may, additionally, optionally offer more direct access to object +data. + +Perhaps the most common object capability systems are those built +\emph{without} dedicated hardware support. Therein, existing abstractions, +such as a privileged supervisory program, are repurposed to provide the +capability substrate. + +Entry capability invocation ranges from fully synchronous, in which threads of +control more or less directly transition from within one object to another, +gaining and losing rights as required, to fully asynchronous, in which all +invocations are done my means of message passing between other threads. In +practice, systems tend to support both options, though they may take one or the +other as their sole ``primitive'' operation. + +Ackerman's architecture~\cite{ackerman:multiprocessing} seems to have been +the first to realize the importance of allowing subsystems to construct +multiple, differentiated entry capabilities, to correspond to different +permitted requests (e.g., invoking different methods on different logical +targets within the same subsystem). A six-bit field, the ``transmitted +word,'' was provided within the entry capability, immune from influence of +the bearer but made available to the subsystem itself on entry. Similar +facilities have been found in almost all subsequent object capability +systems.% +% +\footnote{CHERI lacks such a field within its capabilities; however, the +\insnref{CInvoke} mechanism can be used to similar effect (recall +Section~\ref{sec:model-sealed-capability-invocation}).} + +\paragraph{Hardware Object Capability Systems} + +Some systems, including the ill-fated Intel iAPX 432 lineage (including +the BiiN family of systems and the Intel i960MX), have attempted to move +core aspects of the software object capability model into hardware. Exactly +which features and object types are manifest in hardware depends on the +particular system, but generally one should expect to see a rich notion of +``context'' or ``domain'' of execution and primitives for secure transition +from one to another. + +% \paragraph{Hybrid Schemes} iAPX 432 / BiiN. CHERI. + +% \subsection{Interpretation of Capabilities} + +% >>> +\section{Bounds Checking and Fat Pointers} % <<< + +In contrast to prior capability systems, a key design goal for CHERI was to support mapping C-language pointers into capabilities. +In earlier prototypes, we did this solely through base and bounds fields within capabilities, which worked well but required substantial changes to existing C software that often contained programming idioms that violated monotonic rights decrease for pointers. +In later versions of the ISA, we adopt ideas from the C fat-pointer literature, which differentiate the idea of a delegated region from a current pointer: while the base and bounds are subject to guarded manipulation rules, we allow the offset to float within and beyond the delegated region. +Only on dereference are protections enforced, allowing a variety of imaginative pointer operations to be supported. +Many of these ideas originate with the type-safe C dialect Cyclone~\cite{trevor:cyclone}, and see increasing adaptation to off-the-shelf C programs with work such as Softbound~\cite{Nagarakatte:2009:SHC:1542476.1542504}, Hardbound~\cite{Devietti:2008:HAS:1353536.1346295}, and CCured~\cite{Necula:2002:CTR:503272.503286}. +This flexibility permits a much broader range of common C idiom to be mapped into the capability-based memory-protection model. + +% >>> +\section{Realizing Capability Systems} % <<< + +When a capability systems is encoded, as software or in hardware or with a +mixture of the two, several decisions must be made about how the abstract +objects and actions are to be made manifest. We highlight two of the major +decisions which must be made. + +\subsection{Memory Layout} % <<< + +A reified capability system must have some mechanism to distinguish +capabilities from non-capability data or, equivalently, for determining the +semantic type assigned to bits being accessed by the instruction stream. +Broadly speaking, two approaches have emerged: making the type distinction +\emph{intrinsically associated} with the bits in question or associating the +type with the \emph{access path} taken to those bits. + +Systems choosing the former option are generally said to be ``tagged +architectures'' or to have ``tagged memory:'' at least one bit is associated +with a granule of memory no larger than a capability, which indicates +whether the associated granule contains capability-typed bits or data-typed +bits. CHERI is such a design, with one bit per capability-sized and +suitably-aligned piece of memory. The IBM System/38 uses four bits per +capability-sized piece of memory and requires that they all be set when +attempting to decode a suitably-aligned bit pattern as a capability. + +The second variety of systems seem to lack a similarly punchy moniker, but we +may, at the risk of further overloading an already burdened term, call them +``segmented architectures.'' In these systems, it is usually the +(memory-referencing) capabilities themselves that describe the type of the bits +to be found therein; integrity of the capability representations is ensured by +software's careful avoidance of overlapping capabilities. In simplest +manifestation, a capability to memory designates, in addition to bounds and +permissions, the type of all bits found therein. Such capabilities are often +described with terms such as ``C-type'' or ``D-type'' (as in the Cambridge CAP +family~\cite{WilkesNeedham79}), emphasising the homogeneous nature of the +segment of memory referenced. Some other segmented architectures (notably +including the HYDRA microkernel~\cite{CohenJefferson75,Wulf81}) have bifurcated +segments, wherein each contiguous memory segment is effectively two: one +containing capabilities and one containing data; in these systems, capabilities +typically point at the boundary between the two regions and specify length of +each. Naturally, such segments could carry exclusively capabilities or +exclusively data. + +One occasionally sees designs that straddle the distinction between segmented +and tagged architectures. Therein, capabilities may authorize access to both +data and other capabilities, but there is no requirement that data and +capabilities be separated and contiguous within the authorized memory segment. +For example, in the Coyotos microkernel~\cite{shapiro:2004}, capabilities are +stored in pages of memory accessible only to the capability kernel, but these +``cap pages'' are freely miscible with data pages (either accessible by the +user program or solely by the kernel). This compromise allows Coyotos to run +on commodity hardware and without a specialized language runtime, but requires +indirection to capabilities in memory: data structures contain pointers to +addresses that will fault if dereferenced in the user program, but these +pointers may be passed to the capability kernel during system calls. + +% >>> +\subsection{Indirection of Reference to Capabilities} % <<< + +Capability systems also differ in how they name and manipulate capabilities. +In a traditional von Neumann architecture, the primitive indirection mechanism +is the interpretation of an integer as an index into memory. Virtualization of +this architecture is most often accomplished by inserting a mapping function +from integer ``virtual addresses'' to integer ``physical addresses'' before the +latter are given to the hardware's memory subsystem. Dennis and Van Horn built +upon this primitive in their initial design of capability +systems~\cite{dennis:semantics}, and so many implementations of capability +systems refer to capabilities by \emph{integers}: the capabilities available to +the current process are, at least logically, enumerated in a translation table +(the ``C-list'' of the process) and the process uses integers to index into +this table. Data fetch operations through capabilities in such systems specify +the integer \emph{index} (within this table) of the authorizing capability and +the integer \emph{offset} within that capability of the data desired, and the +result is placed into an (integer) register. Capability fetch, on the other +hand, takes a source index, an offset, and a \emph{target index}: the loaded +capability is placed at the target index within the translation table. Dually, +while data stores transfer integers from registers to memory, capability stores +transfer a capability from the translation table to memory. + +This style of manipulation is especially popular in software capability +systems, as integers abound and a plethora of key-value mapping data structures +are well-understood. Adding another domain of interpretation to integers is +even something of a time-honored tradition; the manipulation of ``file +descriptors'' may be so habitual to UNIX programmers, for example, that pausing +to reflect that they arise from \emph{design decisions} may be seen as unusual. +Software capability kernels can readily implement this design on behalf of +their (user) programs, even on commodity hardware, by moving all capability +interpretation into the kernel. As discussed earlier, Coyotos repurposes +virtual addresses (with backing pages beyond the reach of user programs) as +references to capabilities, conflating its capability translation with the +translation structures used for address virtualization. One often sees small +extensions added in the interest of amortizing the cost of transitions to and +from the supervisor; for example, capability fetch and store operations may be +willing to traverse \emph{paths} (represented by \emph{sequences} of integers), +or multiple capability manipulations may be packaged together, possibly with +other operations, into ``channel programs'' in domain-specific languages +interpreted by the capability kernel. + +Even in hardware, such designs are attractive, as they can be ``drop-in +compatible'' with existing MMU-style translation systems, requiring no changes +to the design of the CPU core. Indeed, the CAP family of +computers~\cite{WilkesNeedham79} divides addresses, as generated by the CPU, +into capability index and offset fields, much as other systems divide (virtual) +addresses into virtual page number and intra-page offset. In systems where +safe table manipulation operations are directly exposed to the user program, +manipulation of the capability address space can be cheaper than in traditional +MMU-style designs, where the MMU mapping structures are highly guarded and +manipulated solely by the supervisor. +% +\nwfnote{Check, but I think the iAPX432 does as well, yes?} + +However, such indirection comes with costs. While the process as a whole may +satisfy the principle of least authority, the use of integer indices still +presents a challenge to the principle of intensional use. In the CAP systems, +for example, indexing past the end of a maximally-sized segment, or, indeed, +sufficiently past the end of any segment, will not result in a processor trap, +but will, instead, be interpreted as an access within \emph{a different +capability}. Even when indices and offsets are maintained separately, there is +nothing, architecturally, that ensures the \emph{provenance} of the index as +such: to confuse a program into acting using an unintended subset of its +authority, it would suffice to corrupt the bits of an integer used as an index. + +The use of integer indexes interpreted within a process may also complicate +sharing between processes. When sending capabilities to another process, the +sender must marshal those capabilities into a (to be) shared segment, as the +indices by which the sender refers to these capabilities are useless to the +recipient. (The situation is analogous to the passing of integer virtual +addresses in shared memory segments: because the segments may be mapped at +different offsets by participating processes, even if the addresses reference +within the segment in one process, they may be meaningless to another.) + +CHERI takes a subtly different approach, in which capabilities are loaded into +CPU registers. The instruction stream combines in-register capabilities with +offsets to make memory accesses. As with the systems employing separated index +and offset fields, it is impossible for an out-of-bounds offset to shift the +capability against which the offset is interpreted. Moreover, CHERI ensures +the architectural validity of the derivation of the capability being used to +authorize the access.% +% +\footnote{That is not to say that it is impossible for a CHERI program to have +bugs or to otherwise give an attacker control over which capability is used in +a given access. It does, however, rule out a large class of historically +powerful attack vectors in which adversarial data is \emph{directly} +interpreted as an integer address.} + +% >>> +% >>> +\section{Capabilities In Hardware} % <<< + +\subsection{Tagged-Memory Architectures} % <<< + +Perhaps the most well-known tagged machine design these days is that of the +Burroughs Large systems, starting with the B5000, designed in 1961. Both +contemporaneous \cite{Creech69,Burroughs-B6700,Organick73} and retrospective +\cite{Mayer82,Barton87} material about this family of machines is available +for the curious reader, as is an interesting report of a concerted +penetration test against Burroughs' operating system \cite{Wilkinson}. For +present purposes, however, we focus on its memory model and, in particular, +its use of tags and descriptors. In the B5000, each word was equipped with +a bit distinguishing its intended use as either data or instructions. The +later B6500 moved to a three-bit tag; we may (very) roughly summarize this +latter taxonomy as differentiating between data words, program instructions, +and pointers of various sorts. In several cases, the tags were used to +convey \emph{type} information to the CPU, so that, for example, the unique +addition instruction would operate on single-precision words or +double-precision word pairs depending on the data tag of its operands +\cite[p. 97]{Organick73}, or the processor's ``step and branch'' instruction +can manipulate a ``step index word'' containing all of the current value, +increment, and limit of iteration \cite[p. 7-5]{Burroughs-B6700}. More +naturally (to a CHERI-minded reader, at least), loads and stores and +indirect transfers of control required their operands to be properly tagged, +and subroutine entry generates tagged return addresses on the stack +\cite[ch. 7]{Burroughs-B6700}. + +While concerned mostly with detection of software bugs, rather than any +consideration of system security, Gumpertz's \emph{Error Detection with +Memory Tags} \cite{Gumpertz81} deserves mention. The tags in this work are +not used to determine operations (as they might have been in the Burroughs +B5000) but rather as additional checks on tag-independent operations. +Gumpertz's design focuses on light-weight checks, performed in parallel with +CPU operations and makes it ``possible to check an arbitrary number of +assertions using only a small tag of fixed size'' \cite[p. i]{Gumpertz81}, +which is similar to CHERI's imbuing of an arbitrary number of bits (i.e., +the width of a capability) with architectural semantics using a single, +external tag bit. + +% >>> +\subsection{Segmented Architectures} % <<< + +\subsubsection{Cambridge CAP Computer} % <<< + +The family of Cambridge CAP computer designs% +% +\footnote{The CAP experiment seems to have produced one physical, heavily +microprogrammed CPU design and at least three different microcode programs.} +% +\cite{WilkesNeedham79} +% +are, at their core, capability-based refinements of earlier, +base-and-length memory segmentation schemes. In these earlier schemes, the +CPU computes offsets within a segment and then dereferences memory as a pair +of an offset and an \emph{index} into a segment table; on dereference, the +offset is checked to be in bounds, and the indirection between segment and +memory---usually just an addition operation---is performed to yield the +``linear'' (or ``physical'') address used to communicate with the memory +subsystem. Programs running on the CAP computer similarly have a virtual +address space consisting of pairs of indices into a \emph{capability table} +and offsets within those capabilities. While the exact interpretation and +mechanisms of the capabilities of each CAP design differed, there are +commonalities across the family. + +The CAP computers interpreted virtual addresses, held in arithmetic +registers, as pairs of a capability specifier and a 16-bit index to a word +within that capability. On the CAP computers, capabilities are interpreted +only after a virtual address has been dispatched from the CPU. This +separation of construction and interpretation violates our principle of +intensional use and enables certain kinds of confusion. To wit, overflowing +the offset results in a potentially in-bound offset \emph{within a different +capability}. This is in stark contrast to a pure-capability CHERI design, +wherein capabilities \emph{supplant} virtual addresses and are directly +manipulated while in registers, making it impossible for operations on a +capability's offset to change to \emph{which} capability the offset is +relative.% +% +\footnote{Though CHERI does have its IDC mechanism for compatibility with +non-capability programs. Similar confusion is possible in hybrid +applications if an offset intended to be relative to one capability is +instead used with another, for example, due to improper management of IDC. +Historically, similar confusion can arise in the more common segmentation +models, as seen in, for example, Intel's X86 CPUs, in which segment table +indices (``segment selectors'') are held in dedicated registers and only +combined with offsets (held in arithmetic registers) by the instruction +stream.} + +% \subsubsection{CAP-1} + +% \subsubsection{CAP-3} + +% >>> +% >>> +% >>> +\section{Microkernels} % <<< + +Denning has argued that the failures of capability hardware projects were classic failures of +large systems projects, an underestimation of the complexity and cost of reworking an entire system +design, rather than fundamental failures of the capability model~\cite{denning:faulttolerance}. +However, the benefit of hindsight suggests that the earlier demise of hardware capability systems +was a result of three related developments in systems research: microkernel OS design, a +related interest from the security research community in security kernel design, and +Patterson and Sequin's Reduced Instruction-Set Computers (RISC)~\cite{patterson:risc}. + +With a transition from complex instruction set computers (CISC) to reduced instruction +set computers (RISC), and a shift away from microcode toward operating system implementation +of complex CPU functionality, the attention of security researchers turned to microkernels. + +Carnegie Mellon's HYDRA~\cite{CohenJefferson75,Wulf81} embodied this approach, in which microkernel +message passing between separate tasks stood in for hardware-assisted security domain crossings +at capability invocation. +HYDRA developed a number of ideas, including the relationship between +capabilities and object references, refined the {\em object-capability} paradigm, +and +further pursued the separation of policy and mechanism.\footnote{Miller has expanded on the +object-capability philosophy in considerable depth in his 2006 PhD dissertation, +{\em Robust composition: towards a unified approach to access control and concurrency +control}~\cite{miller:robustcomposition}} +Jones and Wulf argue through the HYDRA design that the capability model allows the +representation of a broad range of +system policies as a result of integration with the OS object model, which in turn facilitates +interposition as a means of imposing policies on object access~\cite{Jones74}. + +Successors to HYDRA at CMU include Accent and Mach~\cite{Accent,accetta:mach}, +both microkernel systems intended to +explore the decomposition of a large and decidedly un-robust operating system kernel. +In microkernel designs, traditional OS services, such as the file system, are +migrated out of ring 0 and into user processes, improving debuggability and +independence of failure modes. +They are also based on mapping of capabilities as object references into IPC pipes +({\em ports}), in which messages on ports represent methods on objects. +This shift in operating system design went hand in hand with a related analysis in the +security community: Lampson's model for capability security was, in fact, based on pure +message passing between isolated processes~\cite{lampson:protection}. +This further aligned with proposals by Andrews~\cite{andrews:partitions} and +Rushby~\cite{Rushby81} for a {\em security kernel}, whose responsibility lies +solely in maintaining isolation, rather than the provision of higher-level services such as file +systems. +Unfortunately, the shift to message passing also invalidated Fabry's semantic argument for +capability systems, namely, that by offering a single namespace shared by all protection domains, +the distributed system programming problem could be avoided~\cite{fabry:caseforcapabilities}. + +A panel at the 1974 National Computer Conference and Exposition (AFIPS) chaired by Lipner +brought the design goals and choices for microkernels and security kernels clearly into +focus: microkernel developers sought to provide flexible platforms for OS research with an +eye towards protection, while security kernel developers aimed for a high assurance platform +for separation, supported by hardware, software, and formal +methods~\cite{lipner:securitykernels}. + +The notion that the microkernel, rather than the hardware, is responsible for implementing +the protection semantics of capabilities also aligned well with the simultaneous research (and +successful technology transfer) of RISC designs, which eschewed microcode by shifting complexity +to the compiler and operating system. +Without microcode, the complex C-list peregrinations of CAP's capability unit, and protection domain +transitions found in other capability-based systems, +become less feasible in hardware. +Virtual memory designs based on fixed-size pages and simple semantics +have since been standardized throughout the industry. + +Security kernel designs, which combine a minimal kernel focused entirely on correctly +implementing protection, and rigorous application of formal methods, formed the foundation +for several secure OS projects during the 1970s. +Schiller's security kernel for the PDP-11/45~\cite{Schiller75} and Neumann's Provably +Secure Operating System~\cite{PSOS} design study were ground-up operating system designs +based soundly in formal methodology.\footnote{PSOS's ground-up design included ground-up hardware, +whereas Schiller's design revised only the software stack.} +In contrast, Schroeder's MLS kernel design for Multics~\cite{schroeder:multicssecuritykernel}, +the DoD Kernelized Secure Operating System (KSOS)~\cite{McCauley}, and Bruce Walker's UCLA UNIX +Security Kernel ~\cite{walker:uclasecureunix} attempted to slide MLS kernels underneath existing +Multics and UNIX system designs. +Steve Walker's 1980 survey of the state of the art in trusted operating systems provides a summary +of the goals and designs of these high-assurance security kernel +designs~\cite{walker:adventtrusted}. + +The advent of CMU's Mach microkernel triggered a wave of new research into security kernels. +TIS's Trusted Mach (TMach) project extended Mach to include mandatory access +control, relying on enforcement in the microkernel and a small number of +security-related servers to implement the TCB to accomplish sufficient +assurance for a TCSEC B3 evaluation~\cite{BranstadLandauer89}. +Secure Computing Corporation (SCC) and the National Security Agency (NSA) adapted PSOS's +type enforcement from LoCK (LOgical Coprocessor Kernel) +for use in a new Distributed +Trusted Mach (DTMach) prototype, which built on the TMach approach while adding +new flexibility~\cite{sebes:dtmach}. +DTMach, adopting ideas from HYDRA, separates mechanism (in the microkernel) from +policy (implemented in a userspace security server) via a new reference monitor +framework, FLASK~\cite{spencer:flask}. +A significant focus of the FLASK work was performance: an access vector cache is +responsible for caching access control decisions throughout +the OS to avoid costly up-calls and message passing (with associated context switches) to the +security server. +NSA and SCC eventually migrated FLASK to the FLUX microkernel developed by the University of +Utah in the search for improved performance. +Invigorated by the rise of +microkernels and their congruence with security kernels, +this flurry of operating system security research also faced the limitations +(and eventual rejection) of the microkernel approach by the computer industry -- +which perceived the performance overheads as too great. + +Microkernels and mandatory access control have seen another experimental +composition in the form of Decentralized Information Flow Control (DIFC). +This model, proposed by Myers, allows applications to assign information flow labels +to OS-provided objects, such as communication channels, which are propagated and +enforced by a blend of static analysis and runtime OS enforcement, implementing +policies such as taint tracking~\cite{myers:difc} -- effectively, a composition of mandatory +access control and capabilities in service to application security. +This approach is embodied by Efstathopoulos et al.'s Asbestos~\cite{efstathopoulos:asbestos} +and Zeldovich et al.'s Histar~\cite{zeldovich:histar} research operating systems. + +Despite the decline of both hardware-oriented and microkernel +capability system design, capability models continue to interest both +research and industry. Inspired by the proprietary KeyKOS +system~\cite{hardy:keykos}, Shapiro's EROS~\cite{shapiro:eros} (now +CapROS) and Coyotos~\cite{shapiro:2004} continued the investigation of higher-assurance software +capability designs, and +seL4~\cite{klein:sel4}, a formally verified, capability-oriented +microkernel, has also continued along this avenue. +General-purpose systems also have adopted elements of the microkernel capability design +philosophy, such as Apple's Mac OS X~\cite{apple:macosx} +(which uses Mach interprocess communication (IPC) +objects as capabilities) and +Cambridge's Capsicum~\cite{Watson10} research project +(which attempts to blend capability-oriented design with UNIX). + +More influentially, Morris's suggestion of capabilities at the programming language +level has seen widespread deployment. +Gosling and Gong's Java security model blends language-level type safety with a capability-based +virtual machine~\cite{gosling:javalanguage,Gong+97}. +Java maps language-level constructs (such as object member and method protections) into +execution constraints enforced by a combination of a pre-execution bytecode verification +and expression constraints in the bytecode itself. +Java has seen extensive deployment in containing potentially (and actually) malicious +code in the web browser environment. +Miller's development of a capability-oriented E language~\cite{miller:robustcomposition}, +Wagner's Joe-E capability-safe +subset of Java~\cite{mettler:joee}, and Miller's Caja capability-safe subset of JavaScript continue a +language-level exploration of capability security~\cite{miller:caja}. + +% >>> +\section{Language and Runtime Approaches} % <<< + +Direct reliance on hardware for enforcement (which is central to both historic +and current systems) is not the only approach to isolation enforcement. +The notion that limits on expressibility in a programming language can be used to +enforce security properties is frequently deployed in contemporary systems to +supplement coarse and high-overhead operating-system process models. +Two techniques are widely used: virtual-machine instruction sets (or perhaps physical +machine instruction subsets) with limited expressibility, and more expressive languages +or instruction sets combined with type systems and formal verification techniques. + +The Berkeley Packet Filter (BPF) is one of the most frequently cited +examples of the virtual machine approach: user processes upload pattern matching programs +to the kernel to avoid data copying and context switching when sniffing network packet +data~\cite{mccanne:bpf}. +These programs are expressed in a limited packet-filtering virtual-machine instruction +set capable of expressing common constructs, such as accumulators, conditional forward +jumps, and comparisons, but are incapable of expressing arbitrary pointer arithmetic that +could allow escape from confinement, or control structures such as loops that might lead +to unbounded execution time. +Similar approaches have been used via the type-safe Modula 3 programming language in +SPIN~\cite{bershad:spin}, and the DTrace instrumentation tool that, like BPF, uses a narrow +virtual instruction set to implement the D language~\cite{cantrill:dtrace}. + +Google's Native Client (NaCl) model edges towards a verification-oriented approach, in which +programs must be implemented using a `safe' (and easily verified) subset of the x86 or ARM +instruction sets, which would allow confinement properties to be validated~\cite{yee:nativeclient}. +NaCl is closely related to Software Fault Isolation (SFI)~\cite{wahbe:sfi}, in which safety +properties of machine code are enforced through instrumentation to ensure no unsafe access, +and Proof-Carrying Code (PCC), in which the safe properties of code are demonstrated through +attached and easily verifiable proofs~\cite{necula:pcc}. +As mentioned in the previous section, the +Java Virtual Machine (JVM) model is similar; +it combines runtime execution constraints of a +restricted, capability-oriented bytecode with a static verifier run over +Java classes before they can be loaded into the execution environment; this + ensures that only safe accesses have been expressed. +C subsets, such as Cyclone~\cite{trevor:cyclone}, and type-safe languages such as +Ruby~\cite{ruby}, offer similar safety guarantees, which can be leveraged to provide +security confinement of potentially malicious code without hardware support. + +These techniques offer a variety of trade-offs relative to CPU enforcement +of the process model. For example, some (BPF, D) limit expressibility that +may prevent potentially useful constructs from being used, such as loops +bounded by invariants rather than instruction limits; in doing so, +this can typically impose potentially significant performance overhead. +Systems such as FreeBSD often support just-in-time compilers (JITs) that +convert less efficient virtual-machine bytecode into native code subject to +similar constraints, addressing performance but not expressibility +concerns~\cite{mckusick:freebsd}. + +Systems like PCC that rely on proof techniques have had limited impact in +industry, and often align poorly with widely deployed programming languages (such as C) +that make formal reasoning difficult. +Type-safe languages have gained significant ground over the last decade, with widespread use +of JavaScript and increasing use of functional languages such as OCaML~\cite{remy:ocaml}; they offer +many of the performance benefits with improved expressibility, yet have had little impact on +operating system implementations. +However, an interesting twist on this view is described by Wong in Gazelle, in +which the observation is made that a web browser is effectively an operating system by virtue of +hosting significant applications and enforcing confinement between different +applications~\cite{wang:gazelle}. +Web browsers frequently incorporate many of these techniques including Java Virtual Machines and +a JavaScript interpreter. + +% >>> +\section{Influences of Our Own Past Projects} % <<< + +Our CHERI capability hardware design responds to all these design trends -- and their problems. +Reliance on traditional paged virtual memory for strong address-space separation, as used in Mach, +EROS, and UNIX, comes at significant cost: attempts to compartmentalize system software and +applications sacrifice the programmability benefits of a language-based capability design (a point made +convincingly by Fabry~\cite{fabry:caseforcapabilities}), and introduce significant performance +overhead to cross-domain security boundaries. +However, running these existing software designs is critical to improve the odds of technology +transfer, and to allow us to incrementally apply ideas in CHERI to large-scale contemporary applications +such as office suites. +CHERI's hybrid approach allows a gradual transition from virtual address separation to capability-based +separation within a single address space, +thus +restoring programmability and performance so as to facilitate +fine-grained compartmentalization throughout the system and its applications. + +We consider some of our own past system designs in greater detail, +especially as they relate to CTSRD: + +\paragraph{Multics} % <<< +The Multics system incorporated many new concepts in hardware, software, +and programming~\cite{Organick,DaleyNeumann}. +The Multics hardware provided independent virtual +memory segments, paging, interprocess and intra-process separation, +and cleanly separated address spaces. +The Multics software provided +symbolically named files that were dynamically linked for efficient +execution, rings of protection providing layers of security and system +integrity, hierarchical directories, and access-control lists. +Input-output was also symbolically named and dynamically linked, with +separation of policy and mechanism, and separation of device +independence and device dependence. +A subsequent redevelopment of the two +inner-most rings enabled Multics to support multilevel security in the +commercial product~\cite{schroeder:multicssecuritykernel}. +Multics was implemented in a stark subset (EPL) of +PL/I that considerably diminished the likelihood of many common +programming errors. +In addition, the stack discipline inherently +avoided buffer overflows. + +% >>> +\paragraph{PSOS} % <<< +SRI's Provably Secure Operating System hardware-software design was formally +specified in a single language (SPECIAL), +with encapsulated modular abstraction, interlayer state mappings, +and abstract programs relating each layer to those on which it +depended~\cite{PSOS,NeumannFeiertag03}. +The hardware design provided tagged, typed, unforgeable +capabilities required for every operation, with identifiers that were unique +for the lifetime of the system. In addition to a +few primitive types, application-specific object types could be defined and +their properties enforced with the hardware assistance provided by the +capability-based access controls. The design allowed application layers to +efficiently execute instructions, with object-oriented +capability-based addressing directly to the hardware -- despite appearing at +a much higher layer of abstraction in the design specifications. + +%{\em Newcastle Distributed Secure System}~\cite{Rushby+Randell83c} +% +%{\em Separation Kernels}~\cite{Rushby81,Rushby82,Rushby04:separation} + +% >>> +\paragraph{MAC Framework} % <<< +The MAC Framework is an OS reference-monitor framework used in FreeBSD, also +adopted in Mac OS X and iOS, as well as other FreeBSD-descended operating +systems such as Juniper Junos and McAfee Sidewinder~\cite{watson13}. +Developed in the DARPA CHATS program, the MAC Framework allows static and +dynamic extension of the kernel's access-control model, supporting +implementation of {\em security localization} -- +that is, + %%% IS THIS CORRECT? IT WAS UNGRAMMATICAL AND AMBIGUOUS +the adaptation of the OS +security to product and deployment-specific requirements. +The MAC Framework (although originally targeted at classical mandatory access +control models) found significant use in application sandboxing, especially in +Junos, Mac OS X, and iOS. +One key lesson from this work is the importance of longer-term thinking about +security-interface design, +including +interface stability and +support for multiple policy models; these are especially important in +instruction-set design. +Another important lesson is the increasing criticality of extensibility of not +just the access-control model, but also the means by which remote principals +are identified and execute within local systems: +not only is consideration of classical UNIX users inadequate, +but also there is a need to allow widely varying policies and +notions of remote users executing local code across systems. +These lessons are taken to heart in capability systems, which carefully +separate policy and enforcement, but also support extensible policy through +executable code. + +% >>> +\paragraph{Capsicum} % <<< +Capsicum is a lightweight OS capability and sandbox framework included in +FreeBSD 9.x and later~\cite{Watson10,Watson10a}. +Capsicum extends (rather than replaces) UNIX APIs, and +provides new kernel primitives +(sandboxed capability mode and capabilities) and a userspace sandbox +API. +These tools support compartmentalization of monolithic UNIX applications +into logical applications, an increasingly common goal supported poorly by +discretionary and mandatory access controls. +This approach was demonstrated by adapting core FreeBSD utilities and +Google's Chromium web browser to use Capsicum primitives; it showed +significant simplicity and robustness benefits to Capsicum over other +confinement techniques. +Capsicum provides both inspiration and motivation for CHERI: its hybrid +capability-system model is transposed into the ISA to provide +compatibility with current software designs, and its demand for finer-grained +compartmentalization motivates CHERI's exploration of more scalable +approaches. + +% >>> +% >>> +\section{A Fresh Opportunity for Capabilities} % <<< + +Despite an extensive research literature exploring the potential of +capability-system approaches, and limited transition to date, we believe +that the current decade has been the time to revisit these +ideas, albeit through the lens of contemporary problems and with insight gained through decades of research into security and systems design. +As described in Chapter~\ref{chap:introduction}, a transformed threat +environment deriving from ubiquitous computing and networking, and the +practical reality of widespread exploitation of software vulnerabilities, +both +provide a strong motivation to investigate improved processor foundations for +software security. +This change in environment has coincided with improved +and more rapid +hardware prototyping +techniques and higher-level hardware-definition languages that facilitate +academic hardware-software system research at larger scales; without them we +would have been unable to explore the CHERI approach in such detail. +Simultaneously, our understanding of operating-system and programming-language +security has been vastly enhanced by several decades of research; +in particular, recent +development of the hybrid capability-system Capsicum model suggests a strong alignment between +capability-based techniques and successful mitigation approaches that can be +translated into processor design choices. + +% >>> + +% vim: foldmethod=marker:foldmarker=<<<,>>> diff --git a/chap-intro.tex b/chap-intro.tex new file mode 100644 index 00000000..207bf948 --- /dev/null +++ b/chap-intro.tex @@ -0,0 +1,1211 @@ +\chapter{Introduction} +\label{chap:introduction} + +CHERI (Capability Hardware Enhanced RISC Instructions) extends +Instruction-Set Architectures (ISAs) with new capability-based primitives that +improve software robustness to security vulnerabilities. +The CHERI model is motivated by the \textit{principle of least privilege}, +which argues that greater security can be obtained by minimizing the +privileges accessible to running software. +A second guiding principle is the \textit{principle of intentional use}, which +argues that, where many privileges are available to a piece of software, the +privilege to use should be explicitly named rather than implicitly selected. +While CHERI does not prevent the expression of vulnerable software designs, it +provides strong \textit{vulnerability mitigation}: attackers have a more +limited vocabulary for attacks, and should a vulnerability be successfully +exploited, they gain fewer rights, and have reduced access to further attack +surfaces. +CHERI allows software privilege to be minimized at two granularities: + +\begin{description} +\item[Fine-grained code protection] +CHERI enables \textit{fine-grain protection} and \textit{intentional +use} by introducing in-address-space \textit{memory capabilities}, which +replace integer virtual-address representations of code and data pointers. +The aim here is to minimize the rights available to be exercised on an +instruction-by-instruction basis, limiting the scope of damage from inevitable +software bugs. + +CHERI capabilities protect the integrity and valid provenance of pointers +themselves, as well as allowing fine-grained protection of the in-memory data +and code that pointers refer to. +These protection +% +policies +% properties +can, to a large extent, be based on information +already present in program descriptions -- e.g., from C- and C++-language types, memory +allocators, and run-time linking. + +This application of least privilege and intentional use provides strong, +non-probabilistic +protection against a broad range of memory- and pointer-based vulnerabilities +and exploit techniques -- buffer overflows, format-string attacks, pointer +injection, data-pointer-corruption attacks, control-flow attacks, and so on. +Many of these goals can be achieved through code recompilation on CHERI. + +\item[Secure encapsulation] +At a coarser granularity, CHERI also supports +\textit{secure encapsulation} and \textit{intentional use} +through the robust and efficient implementation of highly scalable +in-address-space \textit{software compartmentalization} -- for example, +implementing \textit{object capabilities}. + +The aim here is to minimize the set of rights available to +larger isolated software components, building on efficient architectural +support for strong software encapsulation. +These protections are grounded in explicit descriptions of isolation and +communication provided by software authors, such as through explicit software +sandboxing. +There is also the potential to direct compartmentalization through +language- or linker-level structures and annotations, such as class or module +definitions. + +This application of least privilege and intentional use mitigates +application-level vulnerabilities, such as logical errors, +downloaded malicious code, or software Trojans inserted in the software supply +chain. + +Effective software compartmentalization depends on explicit software +structure, and can require significant code change. +Where compartmentalization already exists in software, CHERI can be used to +significantly improve compartmentalization performance and granularity. +Where that structure is not yet present, CHERI can improve the adoption path +for compartmantalization due to supporting in-address-space +compartmentalization models. +\end{description} + +CHERI is designed to support incremental adoption within current +security-critical, C- and C++-language \textit{Trusted Computing Bases (TCBs)}: +operating-system (OS) kernels, key system libraries and services, language +runtimes supporting higher-level type-safe languages, and applications such as +web browsers and office suites. +While CHERI builds on many historic ideas about capability systems (see +Chapter~\ref{chap:historical}), one of the key contributions of this work is +CHERI's \textit{hybrid capability-system architecture}. +In this context, \textit{hybrid} refers to combining aspects from conventional +architectures, system software, and language/compiler choices with +capability-oriented design. +Key forms of hybridization in the CHERI design include: + +\begin{description} +\item[A RISC capability system] A capability-system model is blended with a + conventional RISC user-mode architecture without disrupting the majority of + key RISC design choices. + +\item[An MMU-enabled capability system] A capability-system model is cleanly + and usefully composed with conventional ring-based privilege and + virtual memory implemented by processor MMUs (Memory Management Units). + +\item[A C-language capability system] CHERI can be targeted by a + C/C++-language compiler with strong compatibility, performance, and + protection properties. + +\item[Hybrid system software] CHERI supports a range of OS models including + conventional MMU-based virtual-memory designs, hybridized designs that + host capability-based software within multiple virtual address spaces, and + pure single-address-space capability systems. + +\item[Incremental adoptability] Within pieces of software, capability-aware + design can be disregarded, partially adopted, or fully adopted with useful + and predictable semantics. + This allows incremental adoption within large software bases, from OS + kernels to application programs. +\end{description} + +We hope that these hybrid aspects of the design will support gradual +deployment of CHERI features in existing software, rather than obliging a +clean-slate software design, thereby offering a more gentle hardware-software +adoption path. + +In the remainder of this chapter, we describe our high-level design goals +for CHERI, the notion that CHERI is an architecture-neutral protection model +with architecture-specific mappings (such as CHERI-MIPS and CHERI-RISC-V)% +\psnote{(the CHERI-MIPS and CHERI-RISC-V mappings detailed here, Arm's experimental Morello architecture~\cite{arm-morello}, and the sketch mapping for x86 described in Chapter~\ref{chap:cheri-x86-64})}, an +introduction to the CHERI-MIPS concrete instantiation, a brief version +history, an outline of the remainder of this report, and our publications to +date on CHERI. +A more detailed discussion of our research methodology, including motivations, +threat model, and evolving approach from ISA-centered prototyping to a broader +architecture-neutral protection model may be found in +Chapter~\ref{chap:research}. +Historical context and related work for CHERI may be found in +Chapter~\ref{chap:historical}. +The \hyperref[glossary]{Glossary} at the end of the report contains +stand-alone definitions of many key ideas and terms, and may be useful +reference material when reading the report. + +\section{CHERI Design Goals} + +CHERI has three central design goals aimed at dramatically improving the +security of contemporary C-language TCBs, through processor support for +fine-grained memory protection and scalable software compartmentalization, +whose (at times) conflicting requirements have required careful negotiation in +our design: + +\begin{description} +\item[Fine-grained memory protection] +improves software resilience to escalation paths +that allow low-level software bugs involving individual data +structures and data-structure manipulations to be coerced into more powerful +software vulnerabilities; +e.g., through remote code injection via buffer overflows, control-flow and +data-pointer corruption, and other memory-based techniques. +Unlike MMU-based memory protection, CHERI memory protection is intended to +be driven by the compiler in protecting programmer-described data structures +and references, rather than via coarse page-granularity protections. +When C and C++ pointers are implemented using capabilities, capability +protections constrain the the ranges of memory (via bounds) and operations +that can be performed (via permissions). +They also protect the integrity, provenance, and monotonicity of pointers in +order to prevent inadvertent or inappropriate manipulation +that might otherwise lead to privilege escalation. + +Capabilities can be used to implement a variety of language-level pointer +types including heap, stack, global, thread-local, and function pointers. +These protect against application-level mismanipulation and misuse of +source-visible pointers, including out-of-range accesses to explicit or +implied memory allocations, and corruption of pointers within those +allocations. +Capability can also be used to implement sub-language pointers created and +maintained by the compiler, runtime, and operating system, such as the stack +pointer, control-flow pointers such as return addresses, and the pointers to +internal linkage structures such as Procedure Linkage Tables (PLTs) and the +Global Offset Table (GOT). +Collectively, strong pointer integrity, pointer provenance validity, bounds, +permissions, monotonicity, and encapsulation prevent corrupted pointers from +allowing a range of vulnerable behaviors (e.g., buffer overflows) and also +directly impede common exploit techniques (e.g., pointer injection). + +Fine-grained protection also provides the foundation for expressing +compartmentalization within application instances. +We draw on, and extend, ideas from recent work in C-language {\em software +bounds checking} by combining {\em fat pointers} with capabilities, allowing +capabilities to be substituted for C pointers with only limited changes to +program semantics. + +CHERI permits efficient implementation of dialects of C and C++ in +which various invalid accesses, deemed to be undefined behavior in +those languages, and potentially giving arbitrary behavior in +their implementations, are instead guaranteed to throw an exception. +While CHERI has not been specifically designed with other languages in mind, +there appear to be many potential applications of CHERI within the language +runtimes for higher-level and managed languages. + +\item[Software compartmentalization] +involves the decomposition of software (at present, primarily +application software) +into isolated components to +mitigate the effects of security vulnerabilities by applying +sound principles of security, such as abstraction, encapsulation, +type safety, and especially least privilege and the minimization of +what must be trustworthy (and therefore sensibly trusted!). + +Previously, it seems that the +adoption of compartmentalization has been limited by a conflation of hardware +primitives for virtual addressing and separation, leading to inherent performance and +programmability problems when implementing fine-grained separation. +With CHERI, we seek to decouple the virtualization from separation to avoid +scalability problems imposed by MMUs based on translation look-aside buffers +(TLBs), which impose a very high performance penalty as the number of +protection domains increases, as well as complicating the writing of compartmentalized software. + +As with an MMU, CHERI enables a variety of \textit{software operational +models} for compartmentalization. +Taking advantage of CHERI's strong in-address-space protection, we have +explored both intra-process sandboxing models, providing robust encapsulation +for dynamic libraries, and also acceleration of the traditional process model +(\textit{co-processes}) by colocating multiple separated processes within the +same virtual address space. + +\item[Formal modeling and verification] +We draw on {\it formal methodologies} wherever feasible, to improve our confidence in the design and implementation of CHERI. +This use is necessarily subject to real-world constraints of timeline, budget, design process, +and prototyping, but it has helped increase our confidence that CHERI meets our +functional and security requirements. +Formal methods can also help to avoid many of +the characteristic design flaws that are common in both hardware and software. +This desire requires us not only to perform research into CPU and software design, but also to +develop new formal methodologies, and adaptations and extensions of existing ones. +To this end, we have produced formal models of our instruction-set extensions +for multiple architectures, and used both pragmatic SMT-based validation and +formal proof to validate that the models satisfy essential security +properties such as provenance validity and monotonicity. + +\item[A viable transition path] must be applicable to current software and +hardware designs. +CHERI hardware must be able to run most current software without significant +modification, and allow incremental deployment of security +improvements starting with the most critical software components: the TCB +foundations on which the remainder of the system rests, and software with the +greatest exposure to risk. +CHERI's features must significantly improve security, to create demand for +upstream processor manufacturers from their downstream mobile and embedded +device vendors. +These CHERI features must at the same time conform to vendor expectations +for performance, energy use, and compatibility in order to compete with less +secure alternatives. + +CHERI is therefore necessarily disruptive, but its architectural, +microarchitectural, and software interventions are bounded in scope, and +constrained in their implications. +Introducing architectural capabilities and tagged memory has significant +implications for instruction-set design and maintainability, as well as +microarchitectural implications for the processor design and memory subsystem. +On the other hand, the general computational, operating-system, and software +compilation models are largely retained, and most existing architectural, +microarchitectural, and software implementation choices are preserved. + +For example, although tagged capabilities are used instead of unadorned +integers in the instruction-level descriptions of loads and stores, once +checks are performed capabilities are largely reduced to integer addresses +for processing by the MMU and memory subsystem. +Compilers must use capability-relative loads and stores for capability-aware +code, but the structure (and often format) of those instructions remain the +same, and although code is generated to use capabilities rather than integers +for pointers, the vast majority of source code remains the same. +Running native capability-unaware binary code is specifically designed for and +supported, allowing conventional OS compatibility ABI techniques (such as used +in the 32-bit to 64-bit transition) to be used. + +\end{description} + +We are concerned with satisfying the need for +trustworthy systems and networks, where {\it +trustworthiness} is a multidimensional measure of how well a system or +other entity satisfies its various requirements -- such as those for +security, system integrity, and reliability, as well as human safety, +and total-system survivability, +robustness, and resilience, notably in the presence of a wide range of +adversities such as hardware failures, software flaws, malware, +accidental and intentional misuse, and so on. Our approach to +trustworthiness encompasses hardware and software architecture, +dynamic and static evaluation, formal and non-formal analyses, good +software-engineering practices, and much more. + +\section{Architecture Neutrality and Architectural Instantiations} +\label{sec:archneut} + +CHERI consists of an architectural-neutral protection model, and a set of +instantiations of that model across multiple ISAs. +Our initial mapping into the 64-bit MIPS ISA has allowed us to develop the +CHERI approach. +We have now expanded to include a more elaborated mapping into +the 64-bit RISC-V ISA, and a sketch mapping into the x86-64 ISA. +We have collaborated with Arm as they have developed the experimental Morello +architecture, an application of CHERI to the ARMv8-A +architecture~\cite{arm-morello}. + +Over the course of this evolution, we have attempted to maximize the degree to +which specification is architecture neutral, and minimize the degree to which +it is architecture specific. +Even within a single ISA, there are multiple potential instantiations of the +CHERI protection model, which offer different design tradeoffs -- for example, +decisions about whether to have separate integer and capability register files +or to merge them into a single register file. + +The successful mapping into multiple ISAs has led us to believe that the CHERI +protection model is a portable protection model, that supports portable +software stacks in much the same way that portable virtual-memory-based +operating systems can be implemented across a variety of architectural MMUs. +Unlike MMUs, whose software interactions are primarily with the operating +system, CHERI interacts directly with compiler-generated code, key system +libraries, compartmentalization libraries, and applications; across all of +these, we have found that an architecture-neutral approach can be highly +effective, offering portability to the vast majority of CHERI-aware C/C++ +code. +In this report, we first consider the architecture-neutral model, and then +applications of our approach in specific ISAs. + +\subsection{The Architecture-Neutral CHERI Protection Model} +\label{sec:cheri-protection-model} + +The aim of the CHERI protection model, as embodied in both the software stack +(see Chapter~\ref{chap:model}) and architecture (see +Chapter~\ref{chap:architecture}), is to support two vulnerability mitigation +objectives: first, +fine-grained pointer and memory protection within address spaces, and second, +primitives to support both scalable and programmer-friendly +compartmentalization within address spaces. +The CHERI model is designed to support low-level TCBs, typically implemented +in C or a C-like language, in workstations, servers, mobile devices, and +embedded devices. +In contrast to MMU-based protection, this is done by protecting +\textit{references to code and data} (pointers), rather than the +\textit{location of code and data} (virtual addresses). +This is accomplished via an \textit{in-address-space capability-system model}: +the architecture provides a new primitive, the \textit{capability}, that +software components (such as the OS, compiler, run-time linker, +compartmentalization runtime, heap allocator, etc.) can use to implement +strongly protected pointers within virtual address spaces. + +%Simultaneously, it will provide reasonable assurance of correctness and a +%realistic technology transition path from existing hardware and software +%platforms. + +In the security literature, capabilities are tokens of authority that are +unforgeable and delegatable. +\textit{CHERI capabilities} are integer virtual addresses that have been +extended with metadata to protect their integrity, limit how they are +manipulated, and control their use. +This metadata includes a \textit{tag} implementing strong integrity +protection (differentiating valid and invalid capabilities), \textit{bounds} +limiting the range of addresses that may be +dereferenced, \textit{permissions} controlling the specific operations that +may be performed, and also +\textit{sealing}, used to support higher-level software encapsulation. +Protection properties for capabilities include the ISA ensuring that +capabilities are always derived via valid manipulations of other capabilities +(\textit{provenance}), that corrupted in-memory capabilities cannot be +dereferenced (\textit{integrity}), and that rights associated with +capabilities are non-increasing (\textit{monotonicity}). + +CHERI capabilities may be held in registers or in memories, and are loaded, +stored, and dereferenced using CHERI-aware instructions that expect +capability operands rather than integer virtual addresses. +On hardware reset, initial capabilities are made available to software via +special and general-purpose capability registers. +All other capabilities will be derived from these initial valid capabilities +through valid capability transformations. + +In order to continue to support non-CHERI-aware code, dereference of integer +virtual addresses via legacy instruction is transparently indirected via a +\textit{default data capability} (\DDC{}) for loads and stores, or a +\textit{program-counter capability} (\PCC{}) for instruction fetch. + +A variety of programming-language and code-generation models can be used with +a CHERI-extended ISA. +As integer virtual addresses continue to be supported, C or C++ compilers +might choose to always implement pointers via integers, selectively implement +certain pointers as capabilities based on annotations or type information +(i.e., a \text{hybrid C} interpretation), or +alternatively +always implement pointers as +capabilities except where explicitly annotated (i.e., a +\textit{pure-capability} interpretation). +Programming languages may also employ capabilities internal to their +implementation: for example, to protect return addresses, vtable pointers, and +other virtual addresses for which capability protection can provide enhanced +vulnerability mitigation. + +When capabilities are being used to implement pointers (e.g., to code or data) +or internal addresses (e.g., for return addresses), they must be +constructed with suitably restricted rights, to accomplish effective protection. +This is a run-time operation performed using explicit instructions (e.g., to +set bounds, mask permissions, or seal capabilities) by the operating system, +run-time linker, language runtime and libraries, and application code itself: + +\begin{description} +\item[The operating-system kernel] may narrow bounds and permissions on + pointers provided as part of the start-up environment when executing a + program binary (e.g., to arguments or environmental variables), or when + returning pointers from system calls (e.g., to new memory mappings). + +\item[The run-time linker] may narrow bounds and permissions when setting up + code pointers or pointers to global variables. + +\item[The system library] may narrow bounds and permissions when returning a + pointer to newly allocated heap memory. + +\item[The compartmentalization runtime] may narrow bounds and permissions, + as well as seal capabilities, enforcing compartment isolation (e.g., to act + as sandboxes). + +\item[The compiler] may insert instructions to narrow bounds and permissions + when generating code to take a pointer to a stack allocation, or when taking + a pointer to a field of a larger structure allocated as a global, on the + stack, or on the heap. + +\item[The language runtime] may narrow bounds and permissions when returning + pointers to newly allocated objects, or when setting up internal linkage, as + well as seal capabilities to non-dereferenceable types. + +\item[The application] may request changes to permissions, bounds, and other + properties on pointers, in order to further subset memory allocations and + control their use. +\end{description} + +The CHERI model can also be used to implement other higher-level protection +properties. +For example, tags on capabilities in memory can be used to support accurate +C/C++-language temporal safety via revocation or garbage collection, and +sealed capabilities can be used to enforce language-level encapsulation and +type-checking features. +The CHERI protection model and its implications for software security are +described in detail in Chapter~\ref{chap:model}. + +\psnote{this is the third time (at least) that we've talked about arch-neutral. Suggest merging the following into the intro to Section~\ref{sec:archneut}.} +CHERI is an \textit{architecture-neutral protection model} in that, like +virtual memory, it can be deployed within multiple ISAs. +In developing CHERI, we initially considered it as a concrete extension to the +64-bit MIPS ISA; using it, we could explore the implications downwards into +the microarchitecture, and upwards into the software stack. +Having developed a mature hardware-software protection model, we used this as +the baseline in deriving an architecture-neutral CHERI protection model. +This architecture-neutral model is discussed in detail in +Chapter~\ref{chap:architecture}. +We have demonstrated the possibility of adding CHERI protection to more than +one base ISA by providing a detailed concrete +instantiation for the 64-bit MIPS ISA (Chapter~\ref{chap:cheri-mips}), a +draft instantiation in the RISC-V ISA (Chapter~\ref{chap:cheri-riscv}), and a +lightweight +architectural sketch for the x86-64 ISA (Chapter~\ref{chap:cheri-x86-64}). + +\subsection{An Architecture-Specific Mapping into 64-bit MIPS} +\label{sec:cheri-isa-design} + +\psnote{much of the following, eg tagged memory and the notion of capability instructions, seems arch-neutral to me. I'd move all that into the previous section, and then present the four architectures more symmetrically} + +The CHERI-MIPS ISA (see Chapter~\ref{chap:cheri-mips}) is an instantiation of +the CHERI protection model as an +extension to the 64-bit MIPS ISA~\cite{Heinrich:1993:MRU:154056}. +CHERI adds the following features to the MIPS ISA\footnote{Formally, +CHERI instructions are added to MIPS as a \textit{MIPS coprocessor} -- a reservation +of opcode space intended for third-party use. +Despite the suggestive term ``coprocessor'', CHERI support will typically be +integrated tightly into the processor pipeline, memory subsystem, and so on. +We therefore eschew use of the term.} to support granular memory protection +and compartmentalization within address spaces: + + +\begin{description} +\item[Capability registers] describe the rights ({\em protection domain}) of +the executing thread to +access memory, and to invoke object references +to transition between protection domains. +We model these registers as a separate {\em capability register file}, +supplementing the general-purpose integer register file. + +Capability registers contain a tag, object type, permission mask, base, length, and offset (allowing the description of not just a bounded region, but also a pointer into that region, improving C-language compatibility). +Capability registers are suitable for describing both data and code, and can hence protect both data integrity/confidentiality and control flow. +Certain registers are reserved for use in exception handling; all others are available to be managed by the compiler using the same techniques used with conventional registers. +Over time, we imagine that software will increasingly use capabilities rather +than integers to describe data and object references. + +Another potential integration into the ISA (which would maintain the same +CHERI protection semantics) would be to extend the existing general-purpose +integer registers so that they could also hold capabilities. +This might reduce the hardware resources required to implement CHERI support. +However, we selected our current approach to maintain consistency with the +MIPS ISA extension model (in which coprocessors have independent register +files), and to minimize \textit{Application Binary Interface (ABI)} disruption +on boundaries between legacy and CHERI-aware code for the purposes of rapid +architectural and software iteration. +We explore the potential space of mappings from the CHERI model into the ISA +in greater detail in Section~\ref{sec:deep-vs-surface}, as well as in +Chapters~\ref{chap:cheri-riscv} and~\ref{chap:cheri-x86-64} where we consider +alternative mappings into non-MIPS ISAs. + +\item[Capability instructions] allow executing code to create, constrain (e.g., by reducing bounds or permissions), manage, and inspect capability register values. Both unsealed (memory) and sealed (object) capabilities can be loaded and stored via memory capability registers (i.e., dereferencing). +Object capabilities can be invoked, via special instructions, allowing a transition between protection domains, but are {\em immutable} and {\em non-dereferenceable}, providing encapsulation of the code or data that they refer to. + Capability instructions implement {\em guarded manipulation}: invalid capability manipulations (e.g., to increase rights or length) and invalid capability dereferences (e.g., to access outside of a bounds-checked region) result in an exception that can be handled by the supervisor or language runtime. +A key aspect of the instruction-set design is \textit{intentional use of + capabilities}: explicit capability registers, rather than ambient +authority, are used to indicate exactly which rights should be exercised, to +limit the damage that can be caused by exploiting bugs. +Tradeoffs exist around intentional use, and in some cases compatibility or +opcode utilization may dictate implicit capability selection; for example, +legacy MIPS load and store instructions implicitly dereference a Default +Data Capability as they are unable to explicitly name a capability register. +Most capability instructions are part of the user-mode ISA, rather than the privileged ISA, and will be generated by the compiler to describe application data structures and protection properties. + +\item[Tagged memory] associates a 1-bit tag with each capability-aligned and capability-sized word in physical memory, which allows capabilities to be safely loaded and stored in memory without loss of integrity. + Writes to capability values in memory that do not originate from a valid capability in the capability register file will clear the tag bit associated with that memory, preventing accidental (or malicious) dereferencing + of invalid capabilities. + +This functionality expands a thread's effective protection domain to include the transitive closure of capability values that can be loaded via capabilities via those present in its register file. For example, a capability register representing a C pointer to a data structure can be used to load further capabilities from that structure, referring to further data structures, which could not be accessed without suitable capabilities. + +Non-bypassable tagging of unforgeable capabilities enables not only reliable +and secure enforcement of capability properties, but also reliable and secure +identification of capabilities in memory for the purposes of implementing +other higher-level protection properties such as temporal safety. +\end{description} + +\psnote{The first sentence is a bit arch -- does anyone in the last couple of decades really think x86 instructions are intended for use directly by the programmer? Probably better to de-RISC the discussion.} +In keeping with the RISC philosophy, CHERI instructions are intended for use +primarily +by the operating system and compiler rather than directly by the programmer, and consist of relatively simple instructions that avoid (for example) combining memory access and register value manipulation in a single instruction. +In our current software prototypes, there are direct mappings from programmer-visible C-language pointers to capabilities in much the same way that conventional code generation translates pointers into general-purpose integer register values; this allows CHERI to continuously enforce bounds checking, pointer integrity, and so on. +There is likewise a strong synergy between the capability-system +model, which espouses a separation of policy and mechanism\psnote{does + it really? that's not very clear to me, for CHERI, esp. for the + fine-grain-protection case (it seems more true for the sealed + capability stuff)}, and RISC: CHERI's features make possible +the implementation of a wide variety of OS, compiler, and application-originated policies on a common protection substrate that optimizes fast paths through hardware support. + +% +% Comment out this text in order to de-emphasize a coprocessor interpretation +% of CHERI. However, we might want to lift some ideas from this paragraph and +% weave them back into the overall text here at some point. +% +%The capability coprocessor is a coprocessor in two senses. +%First, the capability coprocessor occupies a portion of the existing ISA +%encoding dedicated to extensions (typically referred to as coprocessor +%instructions). +%Second, the capability coprocessor supplements the general-purpose integer register +%file with its own ISA-managed registers, as well as performing (and +%transforming) memory access, and delivering exceptions to the main pipeline, +%requiring hardware resources that interact with the primary processor +%pipeline. This behavior is comparable in many ways to system, +%floating-point, vector, or cryptographic coprocessors that will similarly +%supplement the base ISA and processor features. + + +%\psnote{rephrasing, as we've already introduced the fact that we're +%prototyping on MIPS} +%In order to prototype this approach, we have instantiated our ideas about CHERI +%capability access to a specific instruction set: the 64-bit MIPS ISA. +%This +Our prototype of this approach, instantiating our ideas about CHERI +capability access to a specific instruction set (the 64-bit MIPS ISA) +has necessarily led to a set of congruent implementation decisions about +register-file size, selection of specific instructions, exception handling, +memory alignment requirements, and so on, that reflect that starting-point +ISA. +These decisions might be made differently with another starting-point ISA as +they are simply surface features of the underlying approach; we anticipate that +adaptations to ISAs such as ARM, RISC-V, and x86-64 would adopt +instruction-encoding conventions, and so on, more in keeping with their +specific flavor and design (see Chapters~\ref{chap:cheri-riscv} +and~\ref{chap:cheri-x86-64}). + +Other design decisions reflect the goal of creating a platform for prototyping +and exploring the design space itself. +In our initial work on CHERI, we utilized an uncompressed capability format +in which each capability was 256 bits in size. +This gave us significant flexibility to experiment with capability contents +and semantics for bounds checking and capability behaviors. +As our protection and software models matured, we turned our attention to the +performance implications of large capability sizes, including potentially +substantial data-cache overhead for pointer-intensive applications. +We adapted an approach explored in fat-pointer research -- bounds compression +exploiting redundancy between a pointer value and its bounds -- to implement +128-bit compressed capabilities. +As of CHERI ISAv8, capabilities are assumed to use compressed bounds whether +based on a 32-bit or 64-bit base address size. + +\psnote{This is getting very MIPS-implementation-specific -- it's ok, + but possibly gives the wrong emphasis for people now reading the + document from the top?} +In our CHERI-MIPS prototype implementation of the CHERI model, capability +support is tightly coupled with the existing processor pipeline: instructions +propagate values between general-purpose integer registers and capability registers; capabilities +transform interpretation of virtual addresses generated by capability-unaware +instructions including by transforming the program counter; capability +instructions perform direct memory stores and loads both to and from +general-purpose integer registers and capability registers; and capability-related behaviors +deliver exceptions to the main pipeline. +By virtue of having selected the MIPS-centric design choice of exposing +capabilities as a separate set of registers, we maintain a separate capability +register file as an independent hardware unit -- in a manner comparable to +vector or floating-point units in current processor designs. +The impacts of this integration include additional control logic due to +maintaining a separate register file, and a potentially greater occupation of +opcode space, whereas +combining register files might permit existing instructions +to be reused (with care) across integer and capability operations. +%In many ways, these are surface design choices that do not affect the majority +%of programmer-visible protection semantics (aside from small quantities of OS, +%runtime, and compiler-visible code generation and assembly). + +Wherever possible, CHERI systems make use of existing hardware designs: processor pipelines and register files, cache memory, +system buses, commodity DRAM, and commodity peripheral devices such as +NICs and display cards. +We are currently focusing on enforcement of CHERI security properties on applications +running on a general-purpose processor; in future work, we hope to consider the effects of +implementing CHERI in peripheral processors, such as those found in Network Interface Cards (NICs) or Graphical Processing Units (GPUs). + +\subsection{CHERI-RISC-V, CHERI-x86-64, and Arm Morello} + +The abstract CHERI memory protection and security models described above have +been applied to three other architectures: + +\begin{description} +\item[CHERI-RISC-V] is an increasingly mature application of CHERI to the + 32-bit and 64-bit variants of the open-source RISC-V architecture + (Chapter~\ref{chap:cheri-riscv}). + RISC-V is a more contemporary architecture than MIPS, and includes features + such as a hardware page-table walker. + We have fully elaborated these ISA extensions, implemented multiple + microarchitectures on FPGA, and ported our complete CHERI software stack to + CHERI-RISC-V. + +\item[CHERI-x86-64] is a sketch application of CHERI to the Intel x86-64 + architecture (Chapter~\ref{chap:cheri-x86-64}). + It is not fully elaborated, and has not been implemented, but serves to + demonstrate how CHERI could be applied to a CISC architecture. + +\item[Arm Morello] is an experimental application of CHERI to the ARMv8-A + architecture~\cite{arm-morello}. Developed by Arm, Morello is a complete + integration into + a rich commercially used load-store architecture that includes features + such as vector instructions and virtualization support. + We have ported our complete CHERI software stack to Morello. +\end{description} + +Even when targeting a specific architecture, there are multiple ways to +express CHERI's higher-level memory-protection and security-model goals. +For example, the CHERI model can be implemented using a \textit{split +capability register file}, similar to floating point, in which capability +values are stored in a separate register file, or using a \textit{merged +register file}, in which capabilities extend existing integer registers. +CHERI provenance validity and monotonicity properties can be maintained by +throwing an exception on attempted violation (e.g., an attempt to broaden +bounds), or by clearing the tag and allowing a future attempted dereference +to throw an exception. + +These three architectural adaptations reflect substantially improved +understanding of the CHERI model and its potential architecture application +and microarchitectural implementation. +For example, all architectures now use a merged register files rather than +a split register file as was the case in CHERI-MIPS.\footnote{CHERI-RISC-V can + in fact be parameterized to use a split register file, for experimental + purposes, but this is not fully supported by our hardware and software + implementations at the time of writing.} + +There is a high degree of source-level compatibility between software across +these architectures. +Compilers and low-level operating-system components necessarily have modest +amounts of architecture-specific code generation, assembly code, and status +or control registers. +However, high-level CHERI-aware systems C/C++ code is entirely portable across +the multiple architectures. +This is comparable to the portability of architecture-neutral virtual-memory +abstractions and APIs despite architecture-specific interfaces to MMUs and +TLB management. + +\section{Deterministic Protection} + +CHERI has been designed to provide strong, non-probabilistic protection rather +than depending on short random numbers or truncated cryptographic hashes that +can be leaked and reinjected, or that could be brute forced. +Essential to this approach is using out-of-band memory tags that prevent +confusion between data and capabilities. +Software stacks can use these features to construct higher-level protection +properties, such as preventing the transmission of pointers via Inter-Process +Communication (IPC) or network communications. +They are also an essential foundation to strong compartmentalization, which +assumes a local adversary. + +\section{Formal Modeling and Provable Protection} + +The design process for CHERI has used formal semantic models as an +important tool in +various ways. +% +Our +goal here has been to understand how we can support the CHERI design +and engineering process with judicious use of mathematically rigorous +methods, both in lightweight ways (providing engineering and assurance +benefits without the costs of full formal verification), and using +machine-checked proof to establish high confidence that the +architecture design provides specific security properties. + +The basis for all this has been use of formal specifications of the +ISA instruction behavior as a fundamental design tool, initially for +CHERI-MIPS in L3~\cite{Fox2015}, and now for CHERI-MIPS and +CHERI-RISC-V in Sail~\cite{sail-popl2019}. L3 and Sail are +domain-specific languages specifically designed for expressing +instruction behavior, encoding data, etc. +Simply moving from the informal pseudocode commonly used to describe +instruction behavior to parsed and type-checked +artifacts already helps maintain clear specifications. +The CHERI-MIPS instruction descriptions in Chapter~\ref{chap:isaref-mips} +are automatically included from the Sail model, keeping documentation +and model in sync. +\psnote{Robert: do we want to include pointers to the model repos somewhere?} + +Both L3 and Sail support automatic generation of executable models +(variously in SML, OCaml, or C) from these specifications. These +executable models have been invaluable, both as golden models for +testing our hardware prototypes, and as emulators for testing CHERI +software above. The fact that they are automatically generated from +the specifications again helps keep things in sync, enabling +regression testing on any change to the specification, and makes for +easy experimentation with design alternatives. +The generated emulators run fast enough to boot FreeBSD in a few minutes (booting +cheribsd +%128-bit cheri-mips model and it +%80e6 instructions +currently takes around 250s, roughly 320kips). + +We have also used the models to automatically generate ISA test cases, +both via simple random instruction generation, and using +theorem-prover and SMT approaches~\cite{DBLP:journals/scp/CampbellS16}. + + +Finally, the models support formal verification, with mechanised +proof, of key architectural security properties. +L3 and Sail support automatic generation of versions of the models in +the definition languages of (variously) the +HOL4, Isabelle, and Coq theorem provers, which we have used as a basis +for proofs. +Key architectural verification goals including proving not just low-level +properties, such as the monotonicity of each individual instruction +and properties of the CHERI Concentrate compression scheme, but also +higher-level goals such as compartment monotonicity, in which arbitrary code +sequences isolated within a compartment are unable to construct additional +rights beyond those reachable either directly via the register file or +indirectly via loadable capabilities. +We have proven a number of such properties about the CHERI-MIPS ISA~\cite{cheri-formal-SP2020,UCAM-CL-TR-940}. + +The CHERI design process has also benefitted from an interplay with +our work on rigorous semantics for C~\cite{Cerberus-PLDI16,cerberus-popl2019}. + + +\section{CHERI ISA Version History} + +\psnote{the following describes the history in \emph{four} different ways. Surely at least one of those can go?} + +\begin{table}[th!] +\begin{center} +\caption{CHERI ISA revisions and major development phases} +\input{cheri-version-table} +\end{center} +\label{table:intro-cheri-isa-versions} +\end{table} + +This is the eighth version of the CHERI ISA specification. +A high-level summary of CHERI ISA versions and their corresponding +contributions can be found in Table~\ref{table:intro-cheri-isa-versions}. +A much more detailed version summary and complete change log can be found in +Appendix~\ref{app:versions}. +A more narrative exploration of the research and development cycle leading to +our current specification can be found in Chapter~\ref{chap:research}. + +\subsection{Changes in CHERI ISA 8.0} + +This release of the \textit{CHERI Instruction-Set Architecture (ISA) +Specification} is an interim draft release, and contains the following +changes relative to CHERI ISAv7: + +\input{app-versions-8-0} + +\section{Experimental Features} +\label{sec:intro:experimental} + +\rwnote{Ensure this is updated for ISAv8} + +Appendix~\ref{app:experimental} describes a number of experimental features +that extend CHERI with new functionality. +These include several architectural features: + +\begin{itemize} +\item Efficient tag rederivation for use with swapping, memory compression, + memory encryption, and virtual-machine migration +\item A number of architectural features to accelerate temporal memory safety + and capability revocation: fast capability subset testing, non-temporal + tag loading, and non-temporal capability loading. +\item A recursive mutable load permission that limits the store rights + via future capability loads +\item More efficient capability permission representations +\item Memory versioning for use with capabilities +\item Linear capabilities +\item Indirect capabilities +\item Indirect sealed entry capabilities +\item Capability coloring for capability flow control +\item Sealing with large object type fields in memory +\item A system for mixing 64-bit and 128-bit capabilities +\item Capabilities referencing physical addresses +\item Use of capabilities across a system for peripherals and accelerators +\end{itemize} + +We believe that these represent interesting, and in some cases promising, +portions of the design space beyond the baseline CHERI. +However, they appear in an appendix because: (1) we do not yet recommend their +use; (2) they have not been thoroughly evaluated across architecture, +hardware, and software with respect to utility, security, compatibility, +microarchitectural realism, nor performance; and/or (3) their preservation of +essential CHERI security properties has not been formally proven. +They are therefore included to provide insight into potential future +directions or interesting potential alternative points in the overall design +space. + +\section{Document Structure} + +This document is an introduction to, and a reference manual for, the CHERI +protection model and instruction-set architecture. + +\medskip +\noindent +Chapter~\ref{chap:introduction} introduces the CHERI protection model, our +architecture-neutral approach, and specific CHERI-MIPS and CHERI-RISC-V ISAs. + +\medskip +\noindent +Chapter~\ref{chap:model} describes the high-level model for the CHERI approach +in terms of architectural features, software protection objectives, and +software mechanism. + +\medskip +\noindent +Chapter~\ref{chap:architecture} provides a detailed description of +architecture-neutral aspects of the CHERI protection model, including +capability and tagged-memory models, categories of new instructions, etc. + +\medskip +\noindent +Chapter~\ref{chap:cheri-mips} describes an architecture-specific mapping of +the CHERI protection model into the 64-bit MIPS architecture. +This includes specification of the CHERI-MIPS capability coprocessor, register +file, Translation Look-aside Buffer (TLB), privilege model, and other +ISA-specific semantics. + +\medskip +\noindent +Chapter~\ref{chap:cheri-riscv} describes \psnote{do we really still want to regard and label this as a ``draft''?} a draft architecture-specific mapping +of the CHERI protection model into the 64-bit RISC-V architecture. +This includes specification of the CHERI-RISC-V architecture extension, +register file, Memory Management Unit (MMU), privilege models, and other +ISA-specific semantics. + +\medskip +\noindent +Chapter~\ref{chap:cheri-x86-64} provides an ``architectural sketch'' of how +the CHERI protection model might be mapped into the x86-64 ISA, a decidedly +non-RISC instruction set. + +\medskip +\noindent +Chapter~\ref{chap:isaref-mips} provides a detailed description of each +CHERI-MIPS instruction, and also how compilers should handle floating-point +loads and stores via capabilities. + +\medskip +\noindent +Chapter~\ref{chap:isaref-riscv} provides a detailed description of each +CHERI-RISC-V instruction. + +\medskip +\noindent +Chapter~\ref{chap:rationale} discusses the design rationale for many aspects +of the CHERI-MIPS ISA, as well as our thoughts on future refinements based on +lessons learned to date. +\psnote{The following doesn't belong with this chapter description, so + I'd just delete it. And that draft + seems never to have made it to an actual UCAM technical report, so + we shouldn't cite it as such in any case. We mention the early PVS + work in Chapter~\ref{chap:research}. +``A broader document on our use of formal methods +relating to the CHERI total-system architecture is in draft +form~\cite{CHERI-FM15}.''} + +\medskip +\noindent +Chapter~\ref{chap:assurance} outlines a detailed (but not formally +proved) argument for +why a reference monitor above CHERI provides certain security +properties, and touches on some issues in the specification that +formal proof has to deal with. +\psnote{I've rewritten this, because that chapter is no longer ``how we have used formal +methodology to ensure correctness of aspects of the CHERI ISA.''} + +\medskip +\noindent +Chapter~\ref{chap:microarchitecture} provides a high-level summary of how +CHERI can be integrated into RISC pipelines and the memory subsystem. + +\medskip +\noindent +Chapter~\ref{chap:research} describes the motivations and hardware-software +co-design research approach taken in developing CHERI, including major phases of +the research. +\psnote{TODO: do we want to include the hardware-software co-design to hardware-software-formal + co-design narrative, in brief, in the intro chapter? And/or in + detail in Chapter~\ref{chap:research}?} + +\medskip +\noindent +Chapter~\ref{chap:historical} describes the historical context for this work, +including past systems that have influenced our approach. + +\medskip +\noindent +Chapter~\ref{chap:conclusion} discusses our short- and long-term plans for the +CHERI protection model and CHERI-MIPS ISA, considering both our specific plans +and open research questions that must be answered as we proceed. + +\medskip +\noindent +Appendix~\ref{app:versions} provides a more detailed version history of the +CHERI protection model and CHERI-MIPS ISA. + +\medskip +\noindent +Appendix~\ref{app:isaquick-mips} is a quick reference for CHERI-MIPS +instructions and encodings. + +\medskip +\noindent +Appendix~\ref{app:isaquick-riscv} is a quick reference for CHERI-RISC-V +instructions and encodings. + +\medskip +\noindent +Appendix~\ref{app:experimental} specifies a number of CHERI-MIPS instructions +that we still consider experimental, and hence are not included in the main +specification. + +\medskip +\noindent +Appended~\ref{app:cheri-128} describes our prior (now deprecated) CHERI-128 +compression scheme, which has been superseded by CHERI Concentrate. + +\medskip +\noindent +The report also includes a \hyperref[glossary]{Glossary} defining many key +CHERI-related terms. + +\medskip + +Future versions of this document will continue to expand our +consideration of the CHERI model and CHERI-MIPS instruction-set architecture, +its impact on software, and evaluation strategies and results. +Additional information on our prototype CHERI hardware and software +implementations, as well as formal methods work, can be found in accompanying +reports. + +\section{Publications} +\label{sec:publications} + +As our approach has evolved, and project developed, we have published a number +of papers and reports describing aspects of the work. +Our conference papers contain greater detail on the rationale for various +aspects of our hardware-software approach, along with evaluations of +micro-architectural impact, software performance, compatibility, and security: +\psnote{It'd be useful to add links here to the pdfs of these} + +\begin{itemize} +\item In the International Symposium on Computer Architecture (ISCA 2014), we + published \citetitleit{woodruff:cheriisca2014}~\cite{woodruff:cheriisca2014}. + This paper describes our architectural and micro-architectural approaches + with respect to capability registers and tagged memory, hybridization with a + conventional Memory Management Unit (MMU), and our high-level software + compatibility strategy with respect to operating systems. + +\item In the International Conference on Architectural Support for Programming + Languages and Operating Systems (ASPLOS 2015), we published + \citetitleit{ChisnallCPDP11}~\cite{ChisnallCPDP11}, which extends our architectural approach to + better support convergence of pointers and capabilities, as well as to + further explore the C-language compatibility and performance impacts of + CHERI in larger software corpora. + +\item In the IEEE Symposium on Security and Privacy (IEEE S\&P, or + ``Oakland'', 2015), we + published \citetitleit{watson15:cheri}~\cite{watson15:cheri}, which + describes a hardware-software architecture for mapping compartmentalized + software into the CHERI capability model, as well as extends our explanation + of hybrid operating-system support for CHERI. + +\item In the ACM Conference on Computer and Communications Security (CCS + 2015), we published \citetitleit{gudka15:soaap}~\cite{gudka15:soaap}, + which describes our higher-level design + approach to software compartmentalization as a a form of vulnerability + mitigation, including static and dynamic analysis techniques to validate the + performance and effectiveness of compartmentalization. + +\item In the ACM SIGPLAN Conference on Programming Language Design and + Implementation (PLDI 2016), we published + \citetitleit{Cerberus-PLDI16}~\cite{Cerberus-PLDI16}, which develops a + formal semantics for the C programming language. + As part of that investigation, we explore the effect of CHERI on C + semantics, which led us to refine a number of aspects of CHERI code + generation, as well as refine the CHERI ISA. In the other + direction, understanding the changes needed to port existing + software to CHERI has informed our views on what C semantics should be. + +\item In the September-October 2017 issue of IEEE Micro, we published + \citetitleit{watson2016:microjournal}~\cite{watson2016:microjournal}, + expanding on architectural + and microarchitectural aspects of the CHERI object-capability + compartmentalization model described in our Oakland 2015 paper. + +\item In the International Conference on Architectural Support for Programming + Languages and Operating Systems (ASPLOS 2017), we published + \citetitleit{chisnall2017:cherijni}~\cite{chisnall2017:cherijni}. + This paper describes how to use CHERI memory safety and compartmentalization + to isolate Java Native Interface (JNI) code from the Java Virtual Machine, + imposing the Java memory and security model on native code. + +\item In the MIT Press book, \textit{New Solutions for Cybersecurity}, we + published two chapters on CHERI. \citetitleit{watson2017:cheri-deployability} + discusses our research and development approach, and how + CHERI hybridizes conventional architecture, microarchitecture, operating + systems, programming languages, and general-purpose software designs with + a capability-system model~\cite{watson2017:cheri-deployability}. + \textit{Fundamental Trustworthiness Principles in CHERI} discusses how CHERI + fulfills a number of critical trustworthiness + principles~\cite{neumann2017:cheri-principles}. + +\item In the International Conference on Computer Design (ICCD 2017), we + published \citetitleit{joannou2017:tagged-memory}~\cite{joannou2017:tagged-memory}. + This paper describes how awareness of the architectural semantics of tagged + pointers can be used to improve performance and reduce DRAM access overheads + for tagging implemented over DRAM without innate tag storage. + +\item In the International Conference on Computer Design (ICCD 2018), we + published \citetitleit{xia:cherirtos}~\cite{xia:cherirtos}. + This paper describes an embedded variant on CHERI using 64-bit capabilities + for 32-bit addresses, and how embedded real-time operating systems might + utilize CHERI features. + +\item In the ACM SIGPLAN Symposium on Principles of Programming Languages + (POPL 2019), we published \citetitleit{sail-popl2019}, which describes + a formal modeling approach and formal models + for several instruction sets including CHERI-MIPS~\cite{sail-popl2019}. + +\item In the ACM SIGPLAN Symposium on Principles of Programming Languages + (POPL 2019), we published \citetitleit{cerberus-popl2019}, describing a + formal model for C pointer provenance and its + practical evaluation, including via pure-capability C code on the CHERI + architecture~\cite{cerberus-popl2019}. + +\item In the International Conference on Architectural Support for + Programming Languages and Operating Systems (ASPLOS 2019), we published + \citetitleit{davis2019:cheriabi}~\cite{davis2019:cheriabi}. + This paper describes how to adapt a full MMU-based OS design to support + ubiquitous use of capabilities to implement C and C++ pointers in userspace. + +\item In IEEE Transactions on Computers, we published \citetitleit{Woodruff2019}~\cite{Woodruff2019}. + This paper describes our compressed 128-bit and 64-bit capability formats, + evaluating the effects of precision loss in bounds, and the potential + performance impact of the approach. + +\item In the IEEE/ACM International Symposium on Microarchitecture (IEEE + MICRO 2019), we published \citetitleit{Xia_CHERIvokeCharacterisingPointer_2019}~\cite{Xia_CHERIvokeCharacterisingPointer_2019}. + This paper performs a simulation study of a potential approach to temporal + memory safety using CHERI. + +\item In the IEEE Symposium on Security and Privacy (Oakland 2020), we + published \citetitleit{cheri-formal-SP2020}~\cite{cheri-formal-SP2020}. + This paper describes formal modeling and proof of isolation properties for + the CHERI-MIPS ISA. + +\item In the IEEE Symposium on Security and Privacy (Oakland 2020), we + published \citetitleit{cornucopia}~\cite{cornucopia}. + This paper describes a full hardware-software implementation of temporal + memory safety for CHERI, including architectural accelerations. +\end{itemize} + +We have additionally released several technical reports, including this +document, describing our approach and prototypes. +Each has had multiple versions reflecting evolution of our approach: + +\begin{itemize} +\item This report, the \citetitleit{UCAM-CL-TR-951}~\cite{UCAM-CL-TR-850, UCAM-CL-TR-864, + UCAM-CL-TR-876, UCAM-CL-TR-891, UCAM-CL-TR-907, UCAM-CL-TR-927, + UCAM-CL-TR-951}, + describes the CHERI ISA, both as a high-level, software-facing + model and the specific mapping into the 64-bit MIPS instruction set. + Successive versions have introduced improved C-language support, support for + scalable compartmentalization, and compressed capabilities. + +\item The \citetitleit{UCAM-CL-TR-877}~\cite{UCAM-CL-TR-877} describes in greater detail our + mapping of software into instruction-set primitives in both the compiler and + operating system; earlier versions of the document were released as the + \textit{Capability Hardware Enhanced RISC Instructions: CHERI User's + Guide}~\cite{UCAM-CL-TR-851}. + +\item The \citetitleit{UCAM-CL-TR-852}~\cite{UCAM-CL-TR-852, UCAM-CL-TR-868} describes hardware aspects + of our prototyping platform, including physical platform and practical user + concerns. + +\item The \citetitleit{UCAM-CL-TR-853}~\cite{UCAM-CL-TR-853, UCAM-CL-TR-869} describes + non-CHERI-specific software aspects of our prototyping platform, including + software build and practical user concerns. + +\item The technical report, \citetitleit{UCAM-CL-TR-873}~\cite{UCAM-CL-TR-873}, provides a more + detailed accounting of the impact of software compartmentalization on + software structure and security using conventional designs, with potential + applicability to CHERI-based designs as well. + +\item The technical report, \citetitleit{UCAM-CL-TR-916}~\cite{UCAM-CL-TR-916}, + explores the potential interactions between + CHERI, a fundamentally architectural protection technique, and the recently + announced Spectre and Meltdown microarchitectural side-channel attacks. + The report describes a modest architecture extension identifying CHERI + compartment identifiers to the microarchitecture, and also explores + opportunities for Spectre mitigation arising from performing capability + checks in speculation. + +\item The technical report, \citetitleit{UCAM-CL-TR-940}~\cite{UCAM-CL-TR-940}, + is a preprint version of our similarly named + paper published at Oakland 2020~\cite{cheri-formal-SP2020}. + +\item \citetitleit{UCAM-CL-TR-941}~\cite{UCAM-CL-TR-941} provides a + high-level introduction to CHERI: the abstract protection model, + architectural instantiations, formal modeling, microarchitectural + implementation, and software stack. + It was released alongside the announcement of the Arm Morello + board~\cite{arm-morello}. + +\item The \citetitleit{UCAM-CL-TR-947}~\cite{UCAM-CL-TR-947} is an + introduction to pure-capability C/C++, variants of the C and C++ programming + languages targeting implementation of all pointers using CHERI architectural + capabilities. +\end{itemize} + +The following technical reports are PhD dissertations that describe both CHERI +and our path to our current design: + +\begin{itemize} +\item Robert Watson's PhD dissertation, \citetitleit{UCAM-CL-TR-818}, + describes the operating-system + access-control and compartmentalization approaches, including FreeBSD's + MAC Framework and Capsicum, + which motivated our work on CHERI~\cite{Watson10a,UCAM-CL-TR-818}. + +\item Jonathan Woodruff's PhD dissertation, \textit{CHERI: A RISC capability + machine for practical memory safety}, describes our CHERI1 prototype + implementation~\cite{UCAM-CL-TR-858}. + +\item Robert Norton's PhD dissertation, \citetitleit{UCAM-CL-TR-887}, + describes how hardware support is provided for + optimized domain transition using the CHERI2 prototype + implementation~\cite{UCAM-CL-TR-887}. + +\item Alexandre Joannou's PhD dissertation, \citetitleit{UCAM-CL-TR-936}, + describes hardware + optimizations for efficient implementation of CHERI capabilities such as + capability compression for a 128-bit capability format and a hierarchical tag + cache for efficient tagged memory~\cite{UCAM-CL-TR-936}. + +\item Alexander Richardson's PhD dissertation, \citetitleit{UCAM-CL-TR-949}, + describes the implementation + of C/C++ compilation and linkage using CHERI capabilities for spatial memory + safety~\cite{UCAM-CL-TR-949}. +\end{itemize} + +As our research proceeded, and prior to our conference and journal articles, +we published a number of workshop papers laying out early aspects of our +approach: + +\begin{itemize} +\item Our philosophy in revisiting of capability-based approaches is described + in {\em Capabilities Revisited: A Holistic Approach to Bottom-to-Top + Assurance of Trustworthy Systems}, published at the Layered Assurance + Workshop (LAW 2010)~\cite{NeumannWatson10LAW}, shortly after the inception + of the project. + +\item Mid-way through creation of both the BERI prototyping platform, and + CHERI protection model and CHERI-MIPS ISA, we published {\em CHERI: A + Research Platform Deconflating Hardware Virtualization and Protection} at + the Workshop on Runtime Environments, Systems, Layering and Virtualized + Environments (RESoLVE 2012)~\cite{watson:cheriresolve2012}. + +\item Jonathan Woodruff, whose PhD dissertation describes our initial CHERI + prototype, published a workshop paper on this work at the CEUR Workshop's + Doctoral Symposium on Engineering Secure Software and Systems (ESSoS 2013): + \textit{Memory Segmentation to Support Secure + Applications}~\cite{NeumannWatson10LAW}. + +\item In the USENIX Workshop on the Theory and Practice of Provenance (TaPP), + we published {\em Pointer Provenance in a Capability + Architecture}~\cite{mazzinghi:pointer-provenance}. + This paper describes how architectural traces of pointer behavior, visible + through the CHERI instruction set, can be analyzed to understand software + structure and security. +\end{itemize} + +\noindent +Further research publications and technical reports will be forthcoming. diff --git a/chap-isaref-mips.tex b/chap-isaref-mips.tex new file mode 100644 index 00000000..ba3aa96c --- /dev/null +++ b/chap-isaref-mips.tex @@ -0,0 +1,687 @@ +\chapter{The CHERI-MIPS Instruction-Set Reference} +\label{chap:isaref-mips} + +CHERI-MIPS's instructions express a variety of operations affecting capability +and integer registers as well as memory access and control flow. +A key design concern is {\em guarded manipulation}, which provides +a set of constraints +across all instructions that ensure monotonic non-increase in rights through +capability manipulations. +These instructions also assume, and specify, the presence of {\em tagged +memory}, described in the previous chapter, which protects in-memory +representations of capability values. +Many further behaviors, such as reset state and exception handling (taken for +granted in these instruction descriptions), are also described in the previous +chapter. +A small number of more recently specified experimental instructions are +specified in Appendix~\ref{app:experimental} rather than in this chapter. + +The instructions fall into a number of categories: instructions to copy +fields from capability registers into integer registers so that they +can be computed on, instructions for refining fields within capabilities, instructions for memory access via +capabilities, instructions for jumps via capabilities, instructions for sealing capabilities, and instructions for capability invocation. +In this chapter, we specify each instruction via both informal descriptions +and code in the Sail language. +To allow for more succinct code descriptions, we rely on a number of +common function definitions also described in this chapter. + +%TODO: Insert this section +%\section{Capability Exceptions} + +\newcommand{\cchecktag}{\emph{cb}.\ctag{} is not set.} + +\section{Sail language used in instruction descriptions} +\label{sec:sail-language-description} + +\newcommand{\isail}[1]{\lstinline[language=sail]{#1}} + +The instruction descriptions contained in this chapter are accompanied +by code in the Sail language~\cite{sail-popl2019,sail-url} taken from the Sail CHERI-MIPS implementation~\cite{sail-cheri-mips}. Sail is +a domain specific imperative language designed for describing +processor architectures. It has a compiler that can output executable +code in OCaml or C for building executable models, and can also +translate to various theorem prover languages for automated reasoning +about the ISA. + +The following is a brief description of the Sail language features +used in this document. For a full description see the Sail +language documentation. + +Types used in Sail: + +\label{sailMIPSzbits} +\label{sailRISCVzbits} +\begin{itemize} +\item \isail{int} Sail integers are of arbitrary precision (therefore there are no overflows) but can be constrained using simple first-order constraints. As a common case integer range types can be defined using \isail{range(a,b)} to indicate an integer in the range $a$ to $b$ inclusive. Operations on integers repsect the constraints on their operands so, for example, if \isail{x} and \isail{y} have type \isail{range(a, b)} then \isail{x + y} has type \isail{range(a + a, b + b)}. Integer literals are written in decimal. +\item \isail{bits(n)} \label{zbits} is a bit vector of length \isail{n}. Vectors are indexed using square bracket notation with index 0 being the least significant bit. Aritmetic and logical operations on vectors are defined on two vectors of equal length producing a result of the same length and truncating on overflow. Where signedness is significant it is indicated in the operator name, for example \isail{<_s} performs signed comparison of bit vectors . Bit vector literals are written in hexadecimal for multiples of four bits or in binary with \isail{0x} or \isail{0b} prefixes, e.g. \isail{0x3} means `0011' and \isail{0b11} means `11'. The at symbol, \isail{@}, indicates concatenation of vectors. +\item \isail{structs} are similar to C structs with named, typed fields acessed with a dot as in \isail{struct_val.field_name}. Struct copying with field updates is also supported as in \isail{\{struct_val with field_name=new_val\}}. +\item Registers in Sail contain the architectural state that is modified by instruction execution. By convention register names in the CHERI specification start with a capital letter to distinguish them from local variables. Sail also supports a form of `assignment' to function calls as in \isail{wGPR(rd) = result}. This is just syntactic sugar for an extra argument to the function call. This syntax is used by functions that write registers or memory and have special behavior such as \isail{wGPR}, \isail{writeCapReg} and \isail{MEMw}. +\end{itemize} + +The following operators and expression syntax are used in the Sail code: + +\begin{itemize} +\item \label{sailRISCVznot}\label{sailMIPSznot}Boolean operators: +\isail{not}, \isail{|} (logical OR), \isail{&} (logical AND), \isail{^} (exclusive OR) + +\item Integer operators: +\isail{+} (addition), \isail{-} (subtraction), \isail{*} (multiplication), \isail{\%} (modulo) + +Sail operations on integers are the usual mathematical operators. Note \isail{a \% b} is the modulo operator that, for $b > 0$ returns a value in the range $0$ to $b-1$ regardless of the sign of $a$. Although Sail integers are notionally infinite in range, CHERI instructions can be implemented with finite arithmetic. + +\item Bit vector operators: +\isail{&} (bitwise AND), \isail{<_s} (signed less than), \isail{@} (bit vector concatenation) + +\item Equality: +\isail{==} (equal), \isail{!=} (not equal) + +\item Vector slice: + + \isail{v[a..b]} + +Creates a sub-range of a vector from index $a$ down to $b$ inclusive. + +\item Local variables: + + \isail{mutable_var = exp;} \\ + \isail{let immutable_var = exp;} + +Mutable variables are introduced by simply assigning to them. An explicit type may be given following a colon, but types can usually be inferred. Sail supports mutable or immutable variables where immutable ones are introduced by \isail{let} and assigned only once when created. + +\item Functional if: + +\isail{if cond then exp1 else exp2} + +May return a value similar to C ternary operator. + + +\item Foreach loop: + +% XXX: for som reason sail generates a link to "to" for ccleartags/cloadtags +\begin{lstlisting}[language=sail,label=sailMIPSzto] +foreach(i from start_exp to end_exp) { + body +}; +\end{lstlisting} + +\item Function invocation: + +\isail{func_id (arg1, arg2)} + +\item Field selection from struct: + + \isail{struct\_val.field} + +Returns the value of the given field from structure. + +\item Functional update of structure: + +\isail{\{struct\_val with field=exp\}} + +A copy of the structure with the named field replaced with another value. + +\end{itemize} + +% rmn30: removing these sections for now. Might be nice to update them for Sail. +%The precedence of the operators used in the pseudocode is shown in +%Table~\ref{table:operator-precedence}. +% +%\begin{figure} +%\begin{center} +%\begin{tabular}{l} +%\algorithmicor{} \\ +%\algorithmicand{} \\ +%\algorithmicnot{} \\ +%$=$, $\ne$, $<$, $\le$, $>$, $\ge$ \\ +%\algorithmicwith{} \\ +%$+$, $-$ \\ +%$*$, $/$, $\bmod$ \\ +%$a^{b}$ +%\end{tabular} +%\end{center} +%\caption{Operator precedence in pseudocode} +%\label{table:operator-precedence} +%\end{figure} + +\section{Common Constant Definitions} + +The constants used in the Sail are show in \cref{table:pseudocode-constants}. +% ; their value depends on the capability format in use and architecture specific features such as the RISC-V capability mode flag. + +\begin{figure} +\begin{center} +\begin{tabular}{lrl} +\toprule + & 128-bit & Description \\ +\midrule +\verb+cap_size+ & 16 & Number of bytes used to store a capability. \\ +%\verb+caps_per_cacheline+ & - & Number of capabilities in a cacheline (uArch detail) \\ +\verb+max_otype+ & $2^{18}-1$ & Maximum \cotype{} allowed by capability format. \\ +\verb+last_hperm+ & 11 & Last hardware-defined permission bit. \\ +\verb+first_uperm+ & 15 & First software-defined permission bit. \\ +\verb+last_uperm+ & 18 & Last software-defined permission bit. \\ +\verb+num_flags+ & 0 & Number of capability flags. \\ +\bottomrule +\end{tabular} +\end{center} + +\caption{Constants in Sail code} +\label{table:pseudocode-constants} +\end{figure} + +%The null capability is defined as follows: +% +%null\_capability = int\_to\_cap(0) +% +%\textbf{TO DO}: We should have a table defining the values of the capability +%exception codes. + +%\section{Common Variable Definitions} +% +%The following variables are used in the pseudocode: +% +%\begin{tabular}{lll} +%cb & : & Capability \\ +%cd & : & Capability \\ +%cs & : & Capability \\ +%ct & : & Capability \\ +%rd & : & Unsigned64 \\ +%rs & : & Unsigned64 \\ +%rt & : & Unsigned64 \\ +%mask & : & Unsigned16 \\ +%offset & : & Signed16 \\ +%\end{tabular} +% +%\textbf{TO DO: The notation for types should be explained as well. \emph{mem} +%and \emph{tags} are also used as variables.} + +\section{Common Function Definitions} + +This section contains descriptions of convenience functions used by the Sail code featured in this chapter. + +\subsection*{Functions for integer and bit vector manipulation} +\label{sec:sail-int-and-bitvector-functions} + +The following functions convert between bit vectors and integers and manipulate bit vectors: + +\medskip +\sailMIPSval{unsigned} +\sailMIPSval{signed} +\sailMIPSval{to\_bits} +\sailMIPSval{truncate} +\sailMIPSval{pow2} + +% The following are overloads so we can't easily use the generated latex +% Hacky hspace to get rid of unwanted hangindent + +\phantomsection +\label{sailMIPSzzzerozyextend} +\saildocval{Adds zeros in most significant bits of vector to obtain a vector of desired length.}{\hspace{-\parindent}\isail{zero_extend}} + +\label{sailMIPSzsignzyextend} +\saildocval{Extends the most significant bits of vector preserving the sign bit.}{\hspace{-\parindent}\isail{sign_extend}} + +\label{sailMIPSzzzeros} +\saildocval{Produces a bit vector of all zeros}{\hspace{-\parindent}\isail{zeros}} + +\label{sailMIPSzzones} +\saildocval{Produces a bit vector of all ones}{\hspace{-\parindent}\isail{ones}} + +\subsection*{Functions for ISA exception behavior} + +\sailMIPSval{SignalException} +\sailMIPSval{SignalExceptionBadAddr} +\sailMIPSval{raise\_c2\_exception} +\sailMIPSval{raise\_c2\_exception\_noreg} +\sailMIPSval{raise\_c2\_exception\_badaddr} +\sailMIPSval{checkCP2usable} +\sailMIPSval{pcc\_access\_system\_regs} + +\subsection*{Functions for control flow} + +\sailMIPSvalexecuteBranch{} +\sailMIPSvalexecuteBranchPcc{} +\sailMIPSvalsetNextPcc{} +\sailMIPSvalexecute{} + +\subsection*{Functions for reading and writing register and memory} + +\sailMIPSval{rGPR} +\sailMIPSval{wGPR} +\sailMIPSval{readCapReg} +\sailMIPSval{readCapRegDDC} +\sailMIPSval{writeCapReg} +\sailMIPSval{memBitsToCapability} +\sailMIPSval{capToMemBits} +\sailMIPSval{MEMr\_wrapper}\note{rmn30}{TODO rename horrible memory functions} +\sailMIPSval{MEMr\_reserve\_wrapper} +\sailMIPSval{MEMr\_tagged} +\sailMIPSval{MEMr\_tagged\_reserve} +\sailMIPSval{MEMr\_tag} +\sailMIPSval{MEMw\_wrapper} +\sailMIPSval{MEMw\_conditional\_wrapper} +\sailMIPSval{MEMw\_tagged} +\sailMIPSval{MEMw\_tagged\_conditional} +\sailMIPSval{TLBTranslate} +\sailMIPSval{TLBTranslateC} +\sailMIPSval{wordWidthBytes} +\sailMIPSval{isAddressAligned} +\sailMIPSval{extendLoad} +\sailMIPSval{getAccessLevel} +\sailMIPSval{grantsAccess} + +\subsection*{Functions for manipulating capabilities} + +The Sail code abstracts the capability representation using the following functions for getting and setting fields in the capability. +% XXXRW: OK change? +% The functions have different implementations for 256-bit and 128-bit capability formats. + +The base of the capability is the address of the first byte of memory to which it grants access and the top is one greater than the last byte, so the set of dereferenceable addresses is: +\[ +\{ a \in \mathbb{N} \mid \mathit{base} \leq a < \mathit{top}\} +\] +Note that for 128-bit capabilities $\mathit{top}$ can be up to $2^{64}$, meaning the entire 64-bit address space can be addressed. +% XXXRW: OK change? +%, but that the 256-bit capability format has a maximum length of $2^{64} - 1$ so the last byte of the address space is inaccessible. Capability length is defined by the relationship $\mathit{base} + \mathit{length} = \mathit{top}$. +\note{rmn30}{XXX For CHERI 256 $top$ is actually derived using $base + length$ but for 128-bit we derive $length$ using $top - base$. For valid (tagged) capabilities we have (we hope) the invariant $0 \leq base \leq top \leq 2^{64}$, so the length is always positive and in the range $0 .. 2^{64}$ but for untagged 256-capabilities we may have $base + length \geq 2^{64}$ so we have to be careful about overflow. For most instructions this is OK because we check the tag before using getCapTop but this is not true of CBuildCap and CTestSubset so sail code may not have correct semantics there -- need to test. For 128-bit more thought is required... } + +\medskip +\sailMIPSval{getCapBase} +\sailMIPSval{getCapTop} +\sailMIPSval{getCapLength} + +\noindent The capability's address (also known as cursor) and offset (relative to base) are related by: +\[ +\mathit{base} + \mathit{offset}\ \mathbf{mod}\ 2^{64} = \mathit{cursor} +\] +The following functions return the cursor and offset of a capability respectively: +\note{rmn30}{Re-name cursor to address here?} + +\medskip +\sailMIPSval{getCapCursor} +\sailMIPSval{getCapOffset} +\note{rmn30}{explain what happens when offset is negative? In fact it is computed modulo $2^{64}$ and always converted straight to a 64-bit vector so not important. Should maybe just return vector.} + +\noindent The following functions adjust the bounds and offset of capabilities. When using compressed capabilities not all combinations of bounds and offset are representable, so these functions return a boolean value indicating whether the requested operation was successful. Even in the case of failure a capability is still returned, although it may not preserve the bounds of the original capability. \note{rmn30}{Need more detail here?} + +\medskip +\sailMIPSval{setCapBounds} +\sailMIPSval{setCapAddr} +\sailMIPSval{setCapOffset} +\sailMIPSval{incCapOffset} + +\medskip +\sailMIPSval{getRepresentableAlignmentMask} +\sailMIPSval{getRepresentableLength} + +\medskip +\sailMIPSval{hasReservedOType} +\sailMIPSval{isSentryCap} +\sailMIPSval{sealCap} +\sailMIPSval{unsealCap} +\sailMIPSval{unrepCap} + +\mrnote{We should explain the is\_representable function. What properties is +it required to have? All offsets between 0 and length (inclusive) must +be representable for C semantics. Is a length of zero (for any base) required +to be representable? There is also the fast representability check -- there +are in fact several different representability functions depending on where +its called.} + +Capability permissions are accessed using the following functions: + +\medskip +\sailMIPSval{getCapPerms} +\sailMIPSval{setCapPerms} +\note{rmn30}{could separate user and hw permissions as per existing pseudocode} +\sailMIPSval{getCapFlags} +\sailMIPSval{setCapFlags} + +%\sailMIPSval{CapStruct} +%\sailMIPSval{wordWidthBytes} +%\sailMIPSval{getAccessLevel} +%\sailMIPSval{grantsAccess} +%\sailMIPSval{nullcap} +%\sailMIPSval{uintsixfour} +%\sailMIPSval{CapLen} +%\note{rmn30}{CapLen should really be $0 .. 2^{64}$ but that fails to compile -- will need to tweak sail code a bit.} + +\section{Table of CHERI-MIPS Instructions} + +\begin{table} +\begin{center} +\begin{tabular}{p{1.3in}p{4.6in}} +\toprule +Mnemonic & Description \\ +\midrule + CGetAddr & \insnmipsref*[cgetaddr]{Move capability address to an integer register} \\ + CGetAndAddr & \insnmipsref*[cgetandaddr]{Move capability address to an integer register, with mask} \textit{(experimental)} \\ + CGetBase & \insnmipsref*[cgetbase]{Move base to an integer register} + \\ + CGetFlags & \insnmipsref*[cgetflags]{Move flags to an integer register} \\ + CGetLen & \insnmipsref*[cgetlen]{Move length to an integer register} + \\ + CGetOffset & \insnmipsref*[cgetoffset]{Move offset to an integer register} \\ + CGetPerm & \insnmipsref*[cgetperm]{Move permissions to an integer + register} \\ + CGetSealed & \insnmipsref*[cgetsealed]{Test if a capability is sealed} \\ + CGetTag & \insnmipsref*[cgettag]{Move tag bit to an integer register} \\ + CGetType & \insnmipsref*[cgettype]{Move object type to an integer + register} \\ + CPtrCmp & \insnmipsref*[cptrcmp]{Capability pointer compare} \\ + CToPtr & \insnmipsref*[ctoptr]{Capability to integer pointer} \\ +\midrule + CAndAddr & \insnmipsref*[candaddr]{Mask address of capability} + \textit{(experimental)} \\ + CAndPerm & \insnmipsref*[candperm]{Restrict permissions} \\ + CBuildCap & \insnmipsref*[cbuildcap]{Import a capability} + \textit{(experimental)} \\ + CClearRegs & \insnmipsref*[cclearregs]{Clear multiple registers} \\ + CClearTag & \insnmipsref*[ccleartag]{Clear the tag bit} \\ + CCopyType & \insnmipsref*[ccopytype]{Import a capability's \cotype{}} + \textit{(experimental)} \\ + CFromPtr & \insnmipsref*[cfromptr]{Create capability from pointer} \\ + CGetPCC & \insnmipsref*[cgetpcc]{Move PCC to capability register} \\ + CGetPCCSetOffset & \insnmipsref*[cgetpccsetoffset]{Move PCC to capability + register with new offset} \\ + CGetPCCIncOffset & \insnmipsref*[cgetpccincoffset]{Move PCC to capability + register and increment offset} \\ + CGetPCCSetAddr & \insnmipsref*[cgetpccsetaddr]{Move PCC to capability + register with new address} \\ + CIncOffset & \insnmipsref*[cincoffset]{Increment offset} \\ + CIncOffsetImm & \insnmipsref*[cincoffsetimm]{Increment Offset by + Immediate} \\ + CMove & \insnmipsref*[cmove]{Move capability} \\ + CMOVN & \insnmipsref*[cmovn]{Conditionally move capability on non-zero} \\ + CMOVZ & \insnmipsref*[cmovz]{Conditionally move capability on zero} \\ + CReadHwr & \insnmipsref*[creadhwr]{Read a special-purpose capability register} \\ + CSetAddr & \insnmipsref*[csetaddr]{Set capability address to value from register} \\ + CSetBounds & \insnmipsref*[csetbounds]{Set bounds} \\ + CSetBoundsExact & \insnmipsref*[csetboundsexact]{Set bounds exactly} \\ + CSetBoundsImm & \insnmipsref*[csetboundsimm]{Set bounds (immediate)} \\ + CSetFlags & \insnmipsref*[csetflags]{Set flags} + \textit{(experimental)} \\ + CSetOffset & \insnmipsref*[csetoffset]{Set cursor to an offset from base} \\ + CSub & \insnmipsref*[csub]{Subtract capabilities} \\ + CWriteHwr & \insnmipsref*[cwritehwr]{Write a special-purpose capability register} \\ +\bottomrule +\end{tabular} +\end{center} +\caption{Capability coprocessor instruction summary} +\label{table:capability-instruction-summary} +\end{table} + +\begin{table} +\begin{center} +\begin{tabular}{p{1.3in}p{4.6in}} +\toprule +Mnemonic & Description \\ +\midrule + CL[BHWD][U] & \insnmipsref*[clbhwd]{Load integer via capability} \\ + CLC & \insnmipsref*[clc]{Load capability via capability} \\ + CLCBI & \insnmipsref*[clcbi]{Load capability via capability (big + immediate)} \\ + CLL[BHWD][U] & \insnmipsref*[cllbhwd]{Load linked integer via capability} \\ + CLLC & \insnmipsref*[cllc]{Load linked capability via capability} \\ + CSC & \insnmipsref*[csc]{Store capability via capability} \\ + CS[BHWD] & \insnmipsref*[csbhwd]{Store integer via capability} \\ + CSC[BHWD] & \insnmipsref*[cscbhwd]{Store conditional integer via capability} \\ + CSCC & \insnmipsref*[cscc]{Store conditional capability via capability} \\ +\midrule + CBEZ & \insnmipsref*[cbez]{Branch if capability is NULL} \\ + CBNZ & \insnmipsref*[cbnz]{Branch if capability is not NULL} \\ + CBTS & \insnmipsref*[cbts]{Branch if capability tag is set} \\ + CBTU & \insnmipsref*[cbtu]{Branch if capability tag is unset} \\ + CJALR & \insnmipsref*[cjalr]{Jump and link capability register} \\ + CJR & \insnmipsref*[cjr]{Jump capability register} \\ +\midrule + CCheckTag & \insnmipsref*[cchecktag]{Raise exception if capability tag is + unset} \\ +\midrule + CSeal & \insnmipsref*[cseal]{Seal a capability} \\ + CCSeal & \insnmipsref*[ccseal]{Conditionally seal a capability} + \textit{(experimental)} \\ + CUnseal & \insnmipsref*[cunseal]{Unseal a sealed capability} \\ +\midrule + CInvoke & \insnmipsref*[cinvoke]{Call into another security domain} \\ +\midrule + CGetCause & \insnmipsref*[cgetcause]{Move the capability exception cause + register to an integer register} \\ + CGetCID & \insnmipsref*[cgetcid]{Move the architectural Compartment ID + (CID) to an integer register} \\ + CSetCause & \insnmipsref*[csetcause]{Set the capability exception cause + register} \\ + CSetCID & \insnmipsref*[csetcid]{Set the architectural Compartment ID + (CID)} \\ +\bottomrule +\end{tabular} +\end{center} +\caption{Capability coprocessor instruction summary, continued} +\label{table:capability-instruction-summary-2} +\end{table} + +Tables~\ref{table:capability-instruction-summary} +and~\ref{table:capability-instruction-summary-2} list available capability +coprocessor instructions. + +% rmn30: personally i think this section is pointless. +%\section{Details of Individual Instructions} +% +%The following sections provide a detailed description of each CHERI ISA +%instructions. +%Each instruction description includes the following information: +% +%\begin{itemize} +%\item Instruction opcode format number +%\item Assembly language syntax +%\item Bitwise figure of the instruction layout +%\item Text description of the instruction +%\item Sail code for the instruction +%\item Enumeration of any exceptions that the instruction can trigger +%\end{itemize} + +\input{insn-mips/candperm} +\input{insn-mips/cbez} +\input{insn-mips/cbts} +%\input{insn-mips/cbuildcap} +\input{insn-mips/cchecktag} +\input{insn-mips/cclearregs} +\input{insn-mips/ccleartag} +%\input{insn-mips/ccopytype} +%\input{insn-mips/ccseal} +\input{insn-mips/cfromptr} +\input{insn-mips/cgetaddr} +\input{insn-mips/cgetbase} +\input{insn-mips/cgetcid} +\input{insn-mips/cgetcause} +\input{insn-mips/cgetflags} +\input{insn-mips/cgetlen} +\input{insn-mips/cgetoffset} +\input{insn-mips/cgetpcc} +\input{insn-mips/cgetpccsetoffset} +\input{insn-mips/cgetpccincoffset} +\input{insn-mips/cgetpccsetaddr} +\input{insn-mips/cgetperm} +\input{insn-mips/cgetsealed} +\input{insn-mips/cgettag} +\input{insn-mips/cgettype} +\input{insn-mips/cincoffset} +\input{insn-mips/cincoffsetimm} +\input{insn-mips/cinvoke} +\input{insn-mips/cjalr} +\input{insn-mips/cl} +\input{insn-mips/clc} +\input{insn-mips/clcbi} +\input{insn-mips/cllbhwd} +\input{insn-mips/cllc} +\input{insn-mips/cloadtags} +\input{insn-mips/cmove} +\input{insn-mips/cmovn} +\input{insn-mips/cptrcmp} +\input{insn-mips/cram} +\input{insn-mips/creadhwr} +\input{insn-mips/crrl} +\input{insn-mips/cs} +\input{insn-mips/csc} +\input{insn-mips/cscbhwd} +\input{insn-mips/cscc} +\input{insn-mips/cseal} +\input{insn-mips/csealentry} +\input{insn-mips/csetaddr} +\input{insn-mips/csetbounds} +\input{insn-mips/csetboundsexact} +\input{insn-mips/csetboundsimm} +\input{insn-mips/csetcause} +\input{insn-mips/csetcid} +\input{insn-mips/csetflags} +\input{insn-mips/csetoffset} +\input{insn-mips/csub} +\input{insn-mips/ctoptr} +\input{insn-mips/cunseal} +\input{insn-mips/cwritehwr} + +\clearpage +\section{Assembler Pseudo-Instructions} + +For convenience, several pseudo-instructions are accepted by the assembler. +These expand to either single instructions or short sequences of instructions. + +\subsection{CGetDefault, CSetDefault} +\insnmipslabel{cgetdefault} +\insnmipslabel{csetdefault} +\subsubsection*{Get/Set Default Capability} + +\asm{CGetDefault} and \asm{CSetDefault} get and set the capability register that +is implicitly employed by the legacy MIPS load and store instructions. +In the current version of the ISA, this register is special-purpose capability +register 0. + +In previous versions of the ISA, \DDC{} was register \creg{0} in the main +capability register file. In these versions of the architecture, using +\insnnoref{CSetDefault} rather than an capability operation with destination +\creg{0} allowd the Clang/LLVM compiler to know that the semantics of subsequent +MIPS loads and stores will be affected by the change to \DDC{}. + +\begin{asmcode} +# The following are equivalent: + CGetDDC $c1 + CGetDefault $c1 + CReadHWR $c1, $0 +\end{asmcode} + +\begin{asmcode} +# The following are equivalent: + CSetDDC $c1 + CSetDefault $c1 + CWriteHWR $c1, $0 +\end{asmcode} + +\subsection{CGetEPCC, CSetEPCC} +\insnmipslabel{cgetepcc} +\insnmipslabel{csetepcc} +\subsubsection*{Get/Set Exception Program Counter Capability} + +Pseudo-operations are provided for getting and setting \EPCC{}. In the current +ISA, EPCC is special-purpose capability register 31. + +\begin{asmcode} +# The following are equivalent: + CGetEPCC $c1 + CReadHWR $c1, $31 +\end{asmcode} + +\begin{asmcode} +# The following are equivalent: + CSetEPCC $c1 + CWriteHWR $c1, $31 +\end{asmcode} + +\subsection{CGetKDC, CSetKDC} +\insnmipslabel{cgetkdc} +\insnmipslabel{csetkdc} +\subsubsection*{Get/Set Kernel Data Capability} + +\begin{asmcode} +# The following are equivalent: + CGetKDC $c1 + CReadHWR $30 +\end{asmcode} + +\begin{asmcode} +# The following are equivalent: + CSetKDC $c1 + CWriteHWR $30 +\end{asmcode} + +\subsection{GGetKCC, CSetKCC} +\insnmipslabel{cgetkcc} +\insnmipslabel{csetkcc} +\subsubsection*{Get/Set Kernel Code Capability} + +\begin{asmcode} +# The following are equivalent: + CGetKCC $c1 + CReadHWR $29 +\end{asmcode} + +\begin{asmcode} +# The following are equivalent: + CSetKCC $c1 + CWriteHWR $29 +\end{asmcode} + +\subsection{CAssertInBounds} +\insnmipslabel{cassertinbounds} +\subsubsection*{Assert that a capability in bounds} +This pseudo operation can be used to assert that a capability grants access to a given number of bytes (if the size argument is omitted, one byte is assumed). +This instruction only checks the bounds of the capability and ignores permissions. Therefore, an access might still be prohibited even if \insnnoref{CAssertInBounds} did not raise an exception. +\begin{asmcode} +# The following are equivalent (check that at least one byte is accessible): + CAssertInBounds $c1 + CSetBoundsImm $cnull, $c1, 1 +\end{asmcode} + +\begin{asmcode} +# The following are equivalent (check that at least 10 bytes are accessible): + CAssertInBounds $c1, 10 + CSetBoundsImm $cnull, $c1, 10 +\end{asmcode} + + +\subsection{Capability Loads and Stores of Floating-Point Values} + +The current revision of the CHERI ISA does not have CHERI-MIPS instructions for loading floating point values directly via capabilities. +MIPS does provide instructions for moving values between integer and floating point registers, so +a load or store of a floating point value via a capability +can be implemented in two instructions. + +Four pseudo-instructions are defined to implement these patterns. +These are \asm{clwc1} and \asm{cldc1} for loading 32-bit and 64-bit floating point values, and \asm{cswc1} and \asm{csdc1} as the equivalent store operations. +The load operations expand as follows: +\begin{asmcode} + cldc1 $f7, $zero, 0($c2) + # Expands to: + cld $1, $zero, 0($c2) + dmtc1 $1, $f7 +\end{asmcode} + +Note that integer register \regname{1} (\regname{at}) is used; +this pseudo-op is unavailable if the \asm{noat} directive is used. +The 32-bit variant (\asm{clwc1}) has a similar expansion, using \asm{clwu} and \asm{mtc1}. + +The store operations are similar: + +\begin{asmcode} + csdc1 $f7, $zero, 0($c2) + # Expands to: + dmfc1 $1, $f7 + csd $1, $zero, 0($c2) +\end{asmcode} + +The specified floating point value is moved from the floating point register to \regname{at} and then stored using the correct-sized capability instruction. + +\mrnote{If the floating point loads and stores were real instructions rather than +pseudo-ops, we would have to deal with the problem of what happens if a +capability exception or TLB exception is raised in the floating point pipeline. +The floating point and integer pipelines would need to be synchronized so that +the exception occurs at the correct point in program order.} diff --git a/chap-isaref-riscv.tex b/chap-isaref-riscv.tex new file mode 100644 index 00000000..7389ddda --- /dev/null +++ b/chap-isaref-riscv.tex @@ -0,0 +1,297 @@ +\chapter{The CHERI-RISC-V Instruction-Set Reference} +\label{chap:isaref-riscv} + +\input{def-riscv-insns} +\def\rvcheriasminsnref#1{#1} +\def\rvcheriasminsnnoref#1{#1} +\providecommand{\rvcheriasmfmt}{} +\renewcommand{\rvcheriasmfmt}[2][]{% + #2% + \ifthenelse{\equal{#1}{}}{% + }{% + ~{\textit{\footnotesize{(#1)}}}% + }% +} + +In this chapter, we specify each instruction via both informal descriptions +and code in the Sail language. +To allow for more succinct code descriptions, we rely on a number of +common function definitions and constants also described in this chapter. + +\section{Sail language used in instruction descriptions} +The instruction descriptions contained in this chapter are accompanied +by code in the Sail language~\cite{sail-popl2019,sail-url} taken from the Sail +CHERI-RISC-V implementation~\cite{sail-cheri-riscv}. +Sail is a domain specific imperative language designed for describing +processor architectures. It has a compiler that can output executable +code in OCaml or C for building executable models, and can also +translate to various theorem prover languages for automated reasoning +about the ISA. +A brief description of the Sail language features used in this chapter can be +found in \cref{sec:sail-language-description}. +For a full description see the Sail language documentation~\cite{sail-url}. + +\section{Constant Definitions} +The following constants are used in various type and function definitions throughout the specification. +The concrete values listed here apply to the CHERI-RISC-V ISA with +128-bit capabilities that extends the base 64-bit RISC-V ISA. +The constants for with 64-bit CHERI capabilities (extending the 32-bit RISC-V ISA) +can be found in the CHERI-RISC-V Sail model~\cite{sail-cheri-riscv}. +\arnote{and are not listed here as they may change in the near future?} + +\medskip +% Note: we can use \sailRISCVtype{foo\_bar} instead after rems-project/sail#100 +\phantomsection\label{sailRISCVzxlen} +\sailRISCVtype{xlen} +\sailRISCVtypecapAddrWidth{} +\sailRISCVtypecapLenWidth{} +\sailRISCVtypecapSizze{} +\sailRISCVtypecapMantissaWidth{} + +% FIXME: These extra labels are required to allow markdown saildoc references such as [cap_uperms_width] to work correctly. +\phantomsection\label{sailRISCVzcapzyhpermszywidth} +\sailRISCVtypecapHpermsWidth{} +\phantomsection\label{sailRISCVzcapzyupermszywidth} +\sailRISCVtypecapUpermsWidth{} +\phantomsection\label{sailRISCVzcapzyupermszyshift} +\sailRISCVtypecapUpermsShift{} +\phantomsection\label{sailRISCVzcapzyflagszywidth} +\sailRISCVtypecapFlagsWidth{} +\phantomsection\label{sailRISCVzcapzyotypezywidth} +\sailRISCVtypecapOtypeWidth{} + +% Work around https://github.com/rems-project/sail/issues/101 +\begin{lstlisting}[language=sail,label=sailRISCVzmaxzyotype] +let max_otype = MAX(cap_otype_width) - reserved_otypes +\end{lstlisting} + +\section{Function Definitions} + +This section contains descriptions of convenience functions used by the Sail code featured in this chapter. + +\subsection*{Functions for integer and bit vector manipulation} + +The following functions convert between bit vectors and integers and manipulate bit vectors: + +\medskip +\sailRISCVval{unsigned} +\sailRISCVval{signed} +\sailRISCVval{to\_bits} +% Technically this is not a vector, but it seems appropriate to put these together +\sailRISCVval{bool\_to\_bit} +\sailRISCVval{bool\_to\_bits} +\sailRISCVval{truncate} +\sailRISCVval{pow2} + +% The following are overloads so we can't easily use the generated latex +% Hacky hspace to get rid of unwanted hangindent + +\phantomsection +\label{sailRISCVzEXTZ} +\saildocval{Adds zeros in most significant bits of vector to obtain a vector of desired length.}{\hspace{-\parindent}\isail{EXTZ}} + +\label{sailRISCVzEXTS} +\saildocval{Extends the most significant bits of vector preserving the sign bit.}{\hspace{-\parindent}\isail{EXTS}} + +\label{sailRISCVzzzeros} +\saildocval{Produces a bit vector of all zeros}{\hspace{-\parindent}\isail{zeros}} + +\label{sailRISCVzzones} +\saildocval{Produces a bit vector of all ones}{\hspace{-\parindent}\isail{ones}} + +\subsection*{Types used in function definitions} + +\sailRISCVtype{CapBits} +\sailRISCVtype{CapAddrBits} +\sailRISCVtype{CapLenBits} +\sailRISCVtype{CapPermsBits} + +% Expanding this looks very ugly \sailRISCVtype{Capability} +\medskip +\noindent +Many functions also use \isail{struct Capability}, a structure holding a +partially-decompressed representation of CHERI capabilities. +% +The following functions can be used to convert between the structure +representation and the raw capability bits: + +\medskip% +\sailRISCVval{capBitsToCapability} +\sailRISCVval{capToBits} + +\subsection*{Functions for reading and writing register and memory} + +\arnote{TODO: document X() and C()} +%\label{sailRISCVzC} +\begin{lstlisting}[language=sail,label=sailRISCVzC] +C(n) : regno -> Capability +C(n) : (regno, Capability) -> unit +\end{lstlisting} +The overloaded function \isail{C(n)} is used to read or write capability register \isail{n}. + +\begin{lstlisting}[language=sail,label=sailRISCVzX] +X(n) : regno -> xlenbits +X(n) : (regno, xlenbits) -> unit +\end{lstlisting} +The overloaded function \isail{X(n)} is used to read or write integer register \isail{n}. + +\begin{lstlisting}[language=sail,label=sailRISCVzF] +F(n) : regno -> xlenbits +F(n) : (regno, xlenbits) -> unit +\end{lstlisting} +The overloaded function \isail{F(n)} is used to read or write floating-point register \isail{n}. + +\medskip +\sailRISCVval{memBitsToCapability} +\sailRISCVval{capToMemBits} +\sailRISCVval{int\_to\_cap} + +\medskip +\sailRISCVval{get\_cheri\_mode\_cap\_addr} +\sailRISCVval{handle\_load\_cap\_via\_cap} +\sailRISCVval{handle\_load\_data\_via\_cap} +\sailRISCVval{handle\_store\_cap\_via\_cap} +\sailRISCVval{handle\_store\_data\_via\_cap} + + + +\subsection*{Functions for ISA exception behavior} +\sailRISCVval{handle\_exception} +\sailRISCVval{handle\_illegal} +\sailRISCVval{handle\_mem\_exception} +\sailRISCVval{handle\_cheri\_cap\_exception} +\sailRISCVval{handle\_cheri\_reg\_exception} +\sailRISCVval{handle\_cheri\_pcc\_exception} + +\medskip +\sailRISCVval{pcc\_access\_system\_regs} +\sailRISCVval{privLevel\_to\_bits} +\sailRISCVval{min\_instruction\_bytes} + +\medskip +\sailRISCVval{legalize\_epcc} +\sailRISCVval{legalize\_tcc} + +% TODO: \subsection*{Functions for control flow} + + +\subsection*{Functions for manipulating capabilities} + +The Sail code abstracts the capability representation using the following functions for getting and setting fields in the capability. +The base of the capability is the address of the first byte of memory to which it grants access and the top is one greater than the last byte, so the set of dereferenceable addresses is: +\[ +\{ a \in \mathbb{N} \mid \mathit{base} \leq a < \mathit{top}\} +\] +Note that for 128-bit capabilities $\mathit{top}$ can be up to $2^{64}$, meaning the entire 64-bit address space can be addressed. + +\medskip +\sailRISCVval{getCapBounds} +\sailRISCVval{getCapBaseBits} +\sailRISCVval{getCapTop} +\sailRISCVval{getCapLength} +\sailRISCVval{inCapBounds} + +\noindent The capability's address (also known as cursor) and offset (relative to base) are related by: +\[ +\mathit{base} + \mathit{offset}\ \mathbf{mod}\ 2^{64} = \mathit{cursor} +\] +The following functions return the cursor and offset of a capability respectively: +\note{rmn30}{Re-name cursor to address here?} + +\medskip +\sailRISCVval{getCapCursor} +\sailRISCVval{getCapOffsetBits} +\note{rmn30}{explain what happens when offset is negative? In fact it is computed modulo $2^{64}$ and always converted straight to a 64-bit vector so not important. Should maybe just return vector.} + +\noindent The following functions adjust the bounds and offset of capabilities. +Not all combinations of bounds and offset are representable, so these functions return a boolean value indicating whether the requested operation was successful. +Even in the case of failure a capability is still returned, although it may not preserve the bounds of the original capability. + +\medskip +\sailRISCVval{setCapBounds} +\sailRISCVval{setCapAddr} +\sailRISCVval{setCapOffset} +\sailRISCVval{incCapOffset} + +\medskip +\sailRISCVval{getRepresentableAlignmentMask} +\sailRISCVval{getRepresentableLength} + +\medskip +\arnote{TODO: short description of sealing and unsealing} +\sailRISCVval{sealCap} +\sailRISCVval{unsealCap} +\sailRISCVval{isCapSealed} +\sailRISCVval{hasReservedOType} +\sailRISCVval{invalidateCap} + +\noindent +Capability permissions and flags are accessed using the following functions: + +\medskip +\sailRISCVval{getCapPerms} +\sailRISCVval{setCapPerms} +\sailRISCVval{getCapFlags} +\sailRISCVval{setCapFlags} + +\subsection*{Checking for availability of ISA features} +\sailRISCVval{haveRVC} +\sailRISCVval{haveFExt} +\sailRISCVval{haveNExt} +\sailRISCVval{haveSupMode} + + +\section{CHERI-RISC-V Instructions} + +\input{insn-riscv/auipcc} +\input{insn-riscv/candperm} +\input{insn-riscv/cbuildcap} +\input{insn-riscv/cclear} +\input{insn-riscv/ccleartag} +%\input{insn-riscv/ccleartags} % missing sail +\input{insn-riscv/ccopytype} +\input{insn-riscv/ccseal} +\input{insn-riscv/cfromptr} +\input{insn-riscv/cgetaddr} +\input{insn-riscv/cgetbase} +\input{insn-riscv/cgetflags} +\input{insn-riscv/cgetlen} +\input{insn-riscv/cgetoffset} +\input{insn-riscv/cgetperm} +\input{insn-riscv/cgetsealed} +\input{insn-riscv/cgettag} +\input{insn-riscv/cgettype} +\input{insn-riscv/cincoffset} +\input{insn-riscv/cincoffsetimm} +\input{insn-riscv/cinvoke} +\input{insn-riscv/cjalr} +\input{insn-riscv/lc} % [c]lc +\input{insn-riscv/clear} +\input{insn-riscv/cloadtags} +\input{insn-riscv/cmove} +\input{insn-riscv/crepresentablealignmentmask} +\input{insn-riscv/croundrepresentablelength} +\input{insn-riscv/sc} % [c]sc +\input{insn-riscv/cseal} +\input{insn-riscv/csealentry} +\input{insn-riscv/csetaddr} +\input{insn-riscv/csetbounds} +\input{insn-riscv/csetboundsexact} +\input{insn-riscv/csetboundsimm} +\input{insn-riscv/csetequalexact} +\input{insn-riscv/csetflags} +\input{insn-riscv/csetoffset} +\input{insn-riscv/cspecialrw} +\input{insn-riscv/csub} +\input{insn-riscv/ctestsubset} +\input{insn-riscv/ctoptr} +\input{insn-riscv/cunseal} +\input{insn-riscv/fpclear} +\input{insn-riscv/loaddatacap} % l[bhwd][u].cap +\input{insn-riscv/loaddataddc} % l[bhwd][u].ddc +\input{insn-riscv/loadcapcap} % lc.cap +\input{insn-riscv/loadcapddc} % lc.ddc +\input{insn-riscv/storedatacap} % s[bhwd].cap +\input{insn-riscv/storedataddc} % s[bhwd].ddc +\input{insn-riscv/storecapcap} % sc.cap +\input{insn-riscv/storecapddc} % sc.ddc diff --git a/chap-microarchitecture.tex b/chap-microarchitecture.tex new file mode 100644 index 00000000..f62c22b8 --- /dev/null +++ b/chap-microarchitecture.tex @@ -0,0 +1,319 @@ +\chapter{Microarchitectural Techniques for CHERI} +\label{chap:microarchitecture} + +The CHERI architecture has been designed to fit into modern RISC pipelines without disturbing existing control-flow or data paths. +As a result, microarchitectural concerns are simpler than they could otherwise be, but there are nevertheless several innovations that have been developed for prototype implementations that should be considered in any microarchitecture that supports the CHERI model. + +The following repositories hold open-source CHERI implementations or libraries, and are referenced in the sections below. +\begin{description} + \item[CHERI-MIPS~\cite{CHERI-cheri-cpu}] Original reference implementation of the CHERI-MIPS instruction set + \item[cheri-cap-lib~\cite{CHERI-cheri-cap-lib}] A library of reference capability algorithms developed for CHERI-MIPS and adapted for CHERI-RISC-V implementations + \item[TagController~\cite{CHERI-TagController}] Tag controller for emulating a tagged memory using an hierarchical in-memory table developed for CHERI-MIPS and adapted for CHERI-RISC-V implementations + \item[Piccolo~\cite{CHERI-Piccolo}] CHERI-RISC-V CPU with a simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT) + \item[Flute~\cite{CHERI-Flute}] CHERI-RISC-V CPU with a simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance + \item[Toooba~\cite{CHERI-Toooba}] CHERI-RISC-V CPU with a superscalar, out-of-order pipeline and multi-core capable; based on RISCY-OOO from MIT +\end{description} + +\section{Capabilities in the Pipeline} +Capability instructions in the CHERI architecture are modeled after integer operations and are almost entirely single-cycle in the open-source implementations. +This makes it possible for a CHERI architecture to unify integer and capability registers and execution paths. + +\subsubsection{Register File} +Capabilities may be stored in an extended, integer register file, or may use a separate, dedicated register file. + +The CHERI-MIPS architecture and microarchitecture use a separate capability register file, enabling instructions to access capability operands in addition to two integer operands. +CHERI-MIPS uses a dedicated module to perform CHERI operations, but this runs in lock-step with the main pipeline as many capability instructions have integer operands or results, and all legacy memory operations implicitly have \DDC{} as a capability operand. +This microarchitecture is described in ~\cite{woodruff:cheriisca2014}. +A superscalar and out-of-order implementation in this style would dedicate execution units to capability operations with ports into the capability register file which would not be necessary in integer execution units, similar to specializations used for floating point execution units. + +Our CHERI-RISC-V architecture and microarchitectures use a unified register file for both integers and capabilities. +All integer execution units are extended to implement capability manipulation operations. + +It should also be possible to implement a unified register-file architecture with a microarchitecturally split register file. +One such option would split the physical register file between the lower half, which is used by integer operations, and the upper half which is consumed (and produced) exclusively by capability operations. +This division could enable specialization of execution units to reduce the cost of capabilities to integer paths. +This would also reduce total register file storage, as all integer operands and results would not require an entry in the capability register file, while complicating renaming due to operands being split between two renamed register files. + +\subsection{Capability Decoding} + +CHERI capabilities are compressed (see Section~\ref{comp-cap}) and various microarchitectures may choose to decode +capabilities in stages when there is opportunity in the pipeline. +The open-source CHERI implementations, including CHERI-MIPS, Piccolo, Flute, and Toooba, +use 3 stages of decompression. +The first is the fully-compressed, architectural \textbf{in-memory} format. +The second is a lightly-decoded \textbf{in-register} format that is produced on load from memory. +The third is a \textbf{pipeline} format that is consumed by high-performance functions in the pipeline and is decoded on read from the register file. + +The open-source cheri-cap-lib library (summarised in Appendix~\ref{app:cheri-128-listings}) used in our open-source CHERI implementations expresses these three levels of compression using a typeclass; a microarchitectural ``API'' to capabilities +which includes capability manipulation operations for each level of decompression. +The in-register view extracts $E$ (the exponent) into a dedicated field, reconstitutes the top two bits of the $T$ field, and also extracts $a_\text{mid}$ from the address into a dedicated field. +This decompression is fast enough to be performed parallel to the byte-select in the general-purpose loads in the CHERI-MIPS pipeline~\cite{Woodruff2019}. +In turn, this format is further decoded into the in-pipeline format by adding a few booleans and 2-bit offsets that locate the top and base with respect to the address. +These fields are used to perform capability operations such as computing a full top or base, or fast +representability checks. + +While many variations of the capability typeclass could be useful for +a CHERI implementation, these +three design points provided in the library have enabled sufficient flexibility to +implement an array of optimised hardware microarchitectures. + +\subsection{Program Counter Capability (\PCC{})} +CHERI extends the program counter (PC) with bounds and permissions, which are together called \PCC{}. +PC is very performance sensitive and is predicted in most microarchitectures. + +A processor requires the address of \PCC{} at the earliest stage of the pipeline to initiate instruction fetch, but the bounds and permissions of \PCC{} are needed only to decide exception conditions and can therefore be checked at any point in the pipeline. +The CHERI-MIPS microarchitecture takes advantage of this distinction to speculate on only the address of \PCC{} (\textit{i.e.}\ the address of the instruction to be fetched) using the branch predictor, but forwards updates to \PCC{} bounds to the execute stage of the pipeline. +This microarchitecture is described in ~\cite{woodruff:cheriisca2014}. +The in-order Piccolo and Flute microarchitectures share this design. + +Forwarding in superscalar and out-of-order pipelines is more complex so we chose to predict the entirety of \PCC{} in the Toooba microarchitecture. +The BTB delivers both bounds and address, allowing the bounds to be checked early in the pipeline, with a branch misprediction resulting from a mismatch in either the address bits or the bounds and permissions. +The Arm implementers of the Morello prototype observe that predicting the bounds, as is done in Toooba, is the optimal performance solution, though it is expensive microarchitecturally. +In order to optimise prediction state, a microarchitecture may choose to predict the bounds separately from the address to take advantage of shared bounds and permissions between branch targets. + +The Arm Morello design chose to predict the PC address but forward the bounds in the context of the superscalar, out-of-order Ares microarchitecture. +In its base Ares design, any readers of the PC track which PC register file (PCrf) entry has their base address. +For Morello, the PCrf also has a pointer to which \PCC{} register file (PCCrf) entry has its bounds and permissions information. +For commit-time bounds checking, Morello walks and broadcasts the PCrf entries that have a “resolved” (known) PCCrf entry so that we can resolve any \PCC{} bounds exceptions. +The issue queues can also use this broadcast PCrf to release any \PCC{} readers who have dependencies without having to rename the PC or track any extra information. + +Another way of handling the PC/\PCC{} interlock would be to rename PC/\PCC{} and do physical tag tracking for dependencies, as is done with any other renamed register. + +\subsection{Default Data Capability (\DDC{})} +CHERI defines a \DDC{} register which provides both an offset and bounds for non-capability-aware loads and stores such that the capability mechanism can constrain legacy executables. +Both the offset and the bounds for integer addresses require special handling in the microarchitecture. + +The CHERI-MIPS architecture added register-offset addressing to the base MIPS instruction set such that a capability-address store has two integer register operands (data and offset) as well as a capability register address operand. +This path in the CHERI-MIPS microarchitecture was used to implement standard MIPS loads and stores which also offset through \DDC{}. + +The CHERI-RISC-V architecture does not introduce a new addressing mode and therefore does not require an additional register operand for addressing in any common case. +Our CHERI-RISC-V microarchitectures implement \DDC{} as a special, non-forwarded capability register. +That is, CSpecialRW modifications of \DDC{} traverse the back end of the pipeline alone to avoid consistency issues. +\DDC{} is then read directly in any place in the pipeline where it is needed directly from the register without forwarding. + +In many implementations it may be desirable to optimise the address offset of \DDC{}, as an extra add on the address-generation path may be problematic. + +For memory operations with an immediate offset, microarchitectures without \DDC{} forwarding can add the \DDC{} offset to the immediate operand before the Execute stage so that we preserve two-operand address calculation on the critical path. +As RISC-V and MIPS exclusively provide immediate-offset addressing, this optimization resolves the issue for these architectures where \DDC{} forwarding is not implemented. + +For register-offset addressing or for microarchitectures that forward \DDC{}, the \DDC{}-offset performance might be optimised by an architectural change that limits allowed alignments and possibly sizes of \DDC{}. +For example, if \DDC{} were constrained to be aligned and sized to the same power of two, we may simply OR the \DDC{} offset with the resulting address. +If the access is in-bounds, the OR will be exactly equivalent to an ADD, and if not the instruction will be cancelled due to the exception. +One could also imagine implementations that perform this optimization microarchitecturally such that power-of-two aligned-and-sized \DDC{}s operate at full speed and other values of \DDC{} fall back to a lower performance mode. + +\subsection{Capability Mode Bit} +A CHERI ISA may choose to implement a capability \emph{mode} bit in order to reuse legacy load and store encodings for capability-based loads and stores. +This mode bit affects the decoding of instructions, determining the source of bounds for memory access and may also determine alternate decodings of other repurposed instructions. + +CHERI-RISC-V specifies a mode bit that is defined in \PCC{}. +Our in-order open-source implementations, Piccolo and Flute, forward the mode bit along with the bounds to the Execute stage such that mode-bit-dependant decoding does not take place before Execute, which surprisingly fits well into these microarchitectures. + +Our Toooba implementation predicts the mode bit with the entirety of \PCC{} so that the mode bit is available anywhere in the pipeline including Decode. + +If the mode bit is specified in a special register rather than being attached to \PCC{}, the same design options should be available. +The mode bit might cause a pipeline flush on modification so that the current mode might be accessed anywhere in the pipeline, might be forwarded to allow rapid mode switching, or might be predicted along with \PCC{} to optimise repeated mode switches. + +\subsection{Bounds Checking} +Many CHERI instructions must check bounds, including all memory-access instructions and many capability-manipulation instructions. +The CHERI-MIPS microarchitecture implements all instructions with a single general-purpose bounds-check unit in the pipeline which is never used more than once by any instruction. +In addition to this general-purpose bounds-check, there is a bounds-check on \PCC{}. + +The general-purpose bounds check generally produces exceptions and does not affect destination register values, so the bounds-check in CHERI-MIPS is set up in the Execute stage but is performed during Memory Access. + +The general-purpose bounds-check unit must support not only less-than comparison for the top (the common case), but also less-than-or-equal-to for \insnref{CSetBounds}. +\insnref{CSetBounds} also requires extended precision for the upper bound rather than wrap-around arithmetic used by addresses. +The bounds check unit supports separate upper and lower address comparisons against the upper and lower bounds respectively in order to validate the highest and lowest byte accessed by a memory transaction, and also to support the TestSubset operation. +This shared-bounds-check strategy is also used in the Piccolo and Flute microarchitectures, and the Toooba superscalar microarchitecture has one set of bounds-check logic per integer pipe and memory access pipe with some specialization to the two cases. + +The \PCC{} bounds check can be optimised in a number of ways. + +The CHERI-MIPS and CHERI-RISC-V architectures are designed to remove the need to ever perform a \emph{representable check} on \PCC{} modification. +While any legacy branch or jump to an integer register could be considered an add to the address of \PCC{}, potentially requiring a representability check, the MIPS and RISC-V CHERI architectures avoid this condition by throwing an out-of-bounds exception on the branch using the general-purpose bounds-check for control flow instructions. + +All of our open-source CHERI microarchitectures bounds check \PCC{} for every instruction executed. +As branch targets are guaranteed to be in-bounds, it should be possible for the bounds check on \PCC{} to be elided for the majority of instructions, possibly checking \PCC{} bounds in batches. +Alternatively, we might calculate the number of instructions to the bound on each jump and assert that the distance-to-the-bound counter does not reach zero. + +\subsection{Special Capability Registers} +The set of \emph{Special Capability Registers} (SCRs) contain registers with special pipeline implications (such as \DDC{} and \PCC{}) and also registers to allow simplified privilege escalation which are gated by privilege ring. +These registers are accessible only through explicit move-from and move-to GPR instructions. + +The CHERI-MIPS implementation implements all SCRs besides \PCC{}, \KCC{}, and \EPCC{} as forwarded general-purpose capability registers. +\PCC{} is predicted, and \KCC{} and \EPCC{} are used for swapping with \PCC{} on exception and are broken out into dedicated registers without forwarding to enable single-cycle exceptions without the need to access the forwarded register file. + +Piccolo, Flute, and Toooba implement all SCRs as non-forwarded registers, blocking the pipeline for the duration of the execution of any SCR modification. + +\section{Compressed Capability Optimizations} +\label{comp-cap} + +The compression scheme used in CHERI-128 and CHERI-64 is partially described in ~\cite{Woodruff2019} and its key algorithms are implemented in the \emph{cheri-cap-lib} repository. +The key algorithms are reproduced in the Appendix~\ref{app:cheri-128-listings}. +These algorithms are a significant contributions to the community as they enable reasonably efficient microarchitectural implementations of CHERI. + +\subsection{Decompressing Bounds} +Decompressing the bounds of capabilities is highly optimised. +Bounds decompression requires detecting the relative positioning between the top and bottom with respect to the address, as described in ~\cite{Woodruff2019}. + +The \emph{GetTop} function is more complex than the \emph{GetBase} function, as described in Section~\ref{sec:cheri-128-listings-gettop}, due to the requirement to discern between top being $0$ or $2^{64}$. +This algorithm is a noted contribution as it is non-trivial to develop a correct algorithm that is fast enough for common use in pipelines. + +\subsection{Bounds Checking} +There are two types of bounds check in CHERI microarchitectures: precise and representable. +Precise bounds checks assert that an address is between the bounds of the capability, +but a representable check asserts that a transformation on the address of a compressed capability +does not change its bounds due to the limitations of compression. +\subsubsection{Precise Bounds Check} +Cheri-cap-lib provides \emph{CapInBounds} (listed in Section~\ref{sec:cheri-128-listings-capinbounds}) which is an algorithm to check that an encoded capability is within bounds without +decompressing the bounds of the capability. + +We have not required an optimised bounds check which integrates an offset to the address (\textit{e.g.} for offset addressing) as these +bounds checks are not on the critical path in our designs, but generally produce exceptions. +Precise bounds checks with an offset are usually checked against fully decoded bounds (usually in the next pipeline stage), +but could use the \emph{IncOffset} function discussed below followed by \emph{CapInBounds}. + +\subsubsection{Fast Representability Checks} +When the address of a capability is being modified, the algorithm must assert that the resulting capability will still decode the same bounds as the original capability. +Custom \emph{fast representability checks} that operate directly on the compressed fields of the encoding are required for each single-cycle operation that modifies the address to avoid dependance on decompressed values which generally require the majority of a cycle to calculate. + +The \emph{IncOffset} and \emph{SetOffset} operations are supported by a single function listed in Section~\ref{sec:cheri-128-listings-incoffset} and implement the function described in Section~\ref{sec:cheri-concentrate-fast-representable-limit-checking}. +This shared function allows a single circuit to support both operations. + +The \emph{SetAddress} operation must detect if an arbitrary new address is within the representable limits of the capability, and has a distinct implementation listed in Section~\ref{sec:cheri-128-listings-setaddress}. + +\subsection{Setting Bounds} +The \emph{SetBounds} function listed in Section~\ref{sec:cheri-128-listings-setbounds} and described in Section~\ref{sec:cheri-concentrate-encoding-set-bounds} provides a single, shared, high-speed function that returns a single data structure containing a capability with the new bounds (to implement \insnref{CSetBounds}), +a flag indicating if rounding was necessary (to facilitate \insnref{CSetBoundsExact}), +a mask that could be applied to a pointer to align it with the supplied length (to facilitate \insnref{CRepresentableAlignmentMask}), +as well as the length that was actually achieved after rounding (to facilitate \insnref{CRoundRepresentableLength}). + +It is a challenge to implement a \emph{SetBounds} circuit that rounds only when precisely necessary while achieving single-cycle execution. +The example algorithm is described in detail in the comments of the listing, and includes pre-computing all fields for both the rounded and unrounded cases while simultaneously detecting if rounding will occur, followed by a select of the correct return values. +The rounding detection logic is sophisticated and uses a \emph{smear-right} technique to generate a mask to select bits in the address and length relative to the most significant set bit of the length without waiting for the result of \emph{CountLeadingZeros}. +A case matrix is then constructed to detect carry ins to an arbitrary region of the new top based on masked values rather than waiting for the result of full adds. + +\section{Loading and Storing Capabilities} +CHERI requires atomic memory access to capability-wide words (\textit{e.g.} 129-bit words). + +\subsection{Capability Width} +All open-source CHERI implementations have widened the memory interface between the core and the caches to the capability width. +The CHERI-MIPS microarchitecture required that all memory paths were at least capability-width at least to the TagController. +For Flute and Piccolo we allow memory paths past the L1 to be half the width of a capability, but never split a capability between bursts. +These implementations duplicate the tag bit on the two flits of the capability. +The \emph{tag} bit is added to the USER fields of the data channels of AXI (RDATA/WDATA) in these implementations, so it was not possible to transfer less than one tag bit with each flit. + +In addition to the cache interfaces, the Toooba microarchitecture enlarged all load and store buffers to at least 129 bits along with all other memory forwarding paths. + +The Arm Morello architecture defines store capability pair instructions (\emph{ST\{L\}XP}) which perform a 32-byte store. +Morello implements this in a 16-byte store buffer design which required cracking the operation into two store $\mu$ops. +This adds complexity to handle correct success or failure for two $\mu$ops instead of one to ensure that the result is atomic such that both succeed or both fail. +New logic was required to handle one tag/address for both stores, to handle translation atomically, and to handle writing data from both or none at all. +Morello associates adjacent pairs of merge buffer entries so that they atomically retire and write together or fail together. + +Alternative solutions to store pairs of capabilities may be preferable in other microarchitectures. +To simplify, a design could make the entire store data path 32 bytes wide within the processor including the store buffers and writes to the cache or memory subsystem. +Other solutions are highly dependent on individual microarchitectures including how and where they track pass or fail of exclusive instructions, how they write to the data cache and memory subsystem, or how they preserve store order for release semantics. + +\subsection{Capability Permission Complexity} +The CHERI architecture requires data-dependent faults such that the address and data must be available for inspection before a store can be issued. +Specifically, the architecture defines a \cappermSLC bit on an address that may trigger a fault if the \cappermG bit is not set on capability data that is being stored. + +The open-source CHERI implementations are based on microarchitectures that do not issue stores unless both operands are available, and so are able to trivially inspect both operands and mark a store for exception if necessary. +Most high performance processors will separate address and data issue to release the store address as soon as possible, but might need to delay the store address issue until store data is available in order to capture both the tag and global bit for fault detection. +A few other options could be considered if the \cappermSLC is no longer required in the architecture. + +\section{Tagged Memory} +The CHERI capability model requires one extra bit per capability word, \textit{e.g.} CHERI-128 requires 129-bit memory words. +This requires changes to the microarchitecture of the memory subsystem to widen structures where possible, or emulate wider memory where it is not. + +\subsection{Tagging Data Caches} +Data banks and interfaces of caches can simply be widened to accommodate tagged words. +The capability tags can either be stored in the data banks, or the capability tags for a line might be aggregated and stored separately, \textit{e.g} into the record for that line in the cache-tag bank. +We have used both approaches in open-source implementations, with the second facilitating \insnref{CLoadTags}. + +Alternatively, tags could be stored in a separate cache structure that could reduce on-chip storage using compression. +This design point would need to solve problems with coherency and would need to integrate into the pipeline such that tag and data pairs are always accessed atomically. + +Efficient Tagged Memory~\cite{joannou2017:tagged-memory} discusses each of the above design points in detail. + +\subsection{Tagging Memory} + +External memory has become a commodity, so there are strong pressures to build systems that support industry-standard interfaces. + +\subsubsection{Tag Controller with Cache} +Our primary approach, described in ~\cite{joannou2017:tagged-memory}, is a tag controller that allows an external memory controller to emulate a memory holding tagged words. +This tag controller maintains a tag table in the external memory and provides the tag bits for each line requested from the remainder of external memory. +The tag controller contains a cache of lines from the tag table to reduce tag table accesses. +Furthermore, the tag table can be hierarchical such that each bit of a root level indicates whether any bits are set in a block of the leaf table. +This structure significantly reduces cache pressure, as a single line of the root table can potentially replace many lines of the leaf (or flat) table. + +We have implemented this approach in the open-source TagController project which is used in all of our open-source implementations. +This tag controller is parametrisable for arbitrary hierarchy depths and arbitrary block sizes at each level of the hierarchy. + +\subsubsection{Wide Memory} +Commodity external memory may hold memory words wider than its processor word size (\textit{e.g.} ECC memory). +A capability system may choose such a memory type and use these bits to hold capability tags alongside data in external memory. +As ECC bits typically provide more storage than necessary to hold capability tags, a CHERI system using ECC memory should be able to support in-word capability tags and as well as error detection and correction at a some level. + +\subsubsection{Dedicated Memory} +It is also possible to design a system with a dedicated memory channel for tags. +For example, a system with a 1024-bit memory interface (\textit{e.g.} HBM) might add an 8-bit memory interface for accessing tags. + +\subsection{Loading Tags} +The CHERI architecture includes a \insnref{CLoadTags} instruction to load the tags for a cache line into a register. +\insnref{CLoadTags} is expected to be cache coherent, so it is not possible to bypass data caches completely, and it is complex to allow greater-than-cache-line granularity. + +The CHERI-MIPS implementation will opportunistically return tags from the cache if the line is present, but will not trigger a cache fill based on a miss due to \insnref{CLoadTags}, but will forward the request to the next level of cache hierarchy, ultimately hitting the TagController if all caches miss. If the request hits the TagController, it will respond to the request directly, performing an ordinary tag table lookup and caching any results. + +The Arm Morello project found that the implementation of \insnref{CLoadTags} (\emph{LDCT}) that triggers a cache fill requires special care to wait for all the data to return before responding. +This is of concern if the tag bits are stored in the same banks as the data they are associated with and if the data returned is sent in multiple beats (\textit{e.g.} 2). +One way to do this is to force the access to be in the middle of the cache line, forcing the load operation to wait until the entire cache line is returned. + +Performance for the Arm design would be more ideal if tag loading were tracked separately from data lines to avoid special handling. +An alternative, simpler design of LDCT would be to crack the instruction into one microarchitectural tag load for each capability word (\textit{e.g.} 4 tag load $\mu$ops) and merge their results. + +\section{Speculative Side-channel Precautions} +We recommend that CHERI implementations take reasonable precautions to prevent data access through speculative side channels. +Many of these observations are explored in~\cite{UCAM-CL-TR-916}. +CHERI microarchitectures should reasonably be expected to constrain memory access in speculation to capabilities that are architecturally available to the program. +That is, no capability should exist in registers and forwarding paths beyond capabilities in the latest committed architectural state of the register file, those transitively reachable through them, and less-powerful capabilities derived from these. +This property, which we may call Speculative Capability Constraint (\emph{SCC}), requires a few microarchitectural features. + +\subsection{Capability-Guarded Cache Access} +Permissions and bounds of a memory access should be verified before any cache access is initiated. +This is generally reasonable, as these checks are simpler than TLB translation which must also occur before the cache can take action on behalf of a memory access. +This property is necessary to support \emph{SCC} by preventing unreachable capabilities from being introduced into the pipeline from memory. +All of our open-source implementations have this behavior. + +\subsection{\PCC{} Bounds Forwarding (Not Prediction)} +\emph{SCC} may be violated by a design that predicts the bounds of \PCC{}. +For example, the Toooba implementation predicts the bounds of \PCC{}, storing the entire \PCC{} in the branch target buffer. +On any jump, it is possible for a powerful \PCC{} to be predicted, introducing read rights to new addresses that were not implied by the latest-committed state of the register file. +The Morello implementation chooses to forward the bounds of \PCC{} rather than predict them, so the \PCC{} capability cannot be used in a data memory access unless it is legally sourced form another register in the pipeline. +CHERI-MIPS, Piccolo, and Flute share this design choice, though they are of less note as their simple pipelines do not allow speculative read gadgets. + +\subsection{Speculative Forgery Prevention} +\emph{SCC} may also be violated if capabilities can be forged in speculation. +CHERI capability manipulation instructions should not speculatively produce capabilities with privilege greater than their operands provide. +For example, \insnref{CBuildCap} should not forward tagged bits to its consumers while waiting for the result of its bounds check. +\insnref{CSetBounds} and \insnref{CUnseal} share similar concerns. +It is believed that all open-source CHERI implementations may currently forward unsafe values for these instructions, and the Toooba microarchitecture is likely vulnerable to speculative execution attacks through this vector. +This concern might be more Systematically alleviated by an architecture that clears tags rather than throws exceptions for operations that manipulate the privilege of a capability. The ARM Morello architecture generally clears tags rather than throws exceptions for capability manipulation instructions, and we expect the Morello microarchitecture to be immune to this class of attacks for this reason. + +In addition, any speculation in a microarchitecture that could synthesise a value rather than deriving it from architecturally-defined bits (\textit{e.g.} value speculation) should not produce valid capability values. +This could include not only a capability predicted to be loaded from a memory location, but also a predicted integer value that is used to bound a capability. + +If these restrictions become performance-limiting, one could imagine deploying Speculative Taint Tracking~\cite{yu2019speculative} to ensure that speculatively-forged capabilities do not affect cache state. + +\subsection{Compartment ID (\emph{CID}) Enforcement} +Even if \emph{SCC} is enforced, we may have code paths that manipulate powerful capabilities that must be protected from speculative execution attacks. +The CID is described in Section~\ref{section:microarchitectural-sidechannels} to provide an architectural means to convey trust boundaries to the microarchitecture. +The CID should be used to tag microarchitectural state to prevent instructions in disparate compartments influencing each other's execution in much the same way as we might hope a modern microarchitecture might prevent user space speculative state influencing kernel execution. +For example, the branch target buffer should tag entries with the CID such that targets learned in one compartment would not be used when speculating in another compartment, allowing an attacker to redirect branches that expose powerful capabilities to side-channel gadgets. +The branch history table may also be tagged, as well as prefetchers and any other structure that holds state that influences prediction. + +The CID itself may be large and require compression in the microarchitecture. +For example, a microarchitecture may introduce a table that holds several active CIDs while attaching table indices to all state used for speculation. +Such a microarchitecture requires a means to flush state belonging to old table values before installing a new value at an index. + +If domain crossing is to be highly optimised, the application of the CID may be imprecise (\textit{e.g.} allowing use of old CID state until the new CID install commits) or the CID itself may be predicted. +Either of these may be very difficult to allow without introducing speculative-side-channel vulnerabilities. diff --git a/chap-model.tex b/chap-model.tex new file mode 100644 index 00000000..011c2be3 --- /dev/null +++ b/chap-model.tex @@ -0,0 +1,1878 @@ +\chapter{The CHERI Protection Model} +\label{chap:model} + +This chapter describes the portable \textit{CHERI protection model}, its use +in software, and its impact on potential software vulnerabilities; concrete +mappings into computer architecture are left to later chapters. +We consider a number of topics from a more abstract, software-facing +perspectives: the principles underlying the model, our goals for capabilities, +hybridization with conventional architectural designs, implications for +operating-system and language support and compatibility, and concerns around +microarchitectural side channels. + +There are many potential concrete mappings of this abstract software-facing +protection model into specific Instruction-Set Architectures (ISAs), but most +key aspects of the model can be shared across target architectures, including +the capability protection model, composition with virtual memory, and tagged +memory. +Whether used for memory protection or compartmentalization, CHERI's properties +hold with considerable uniformity across underlying architectural +implementations (e.g., regardless of capability size, whether capabilities are +stored in their own register file or as extensions to general-purpose integer +registers, etc.), and support common (and portable) programming +models and approaches. + +We describe the cross-architecture aspects of CHERI in +Chapter~\ref{chap:architecture}. +Collectively, our instantiations of the CHERI protection model in the 64-bit +MIPS (Chapter~\ref{chap:cheri-mips}), 32- and 64-bit RISC-V +(Chapter~\ref{chap:cheri-riscv}), and 64-bit ARMv8-A +(Morello~\cite{arm-morello}) ISAs +demonstrate the portability of the model despite diverse underlying +architectural implementations. + +\section{Underlying Principles} + +The design of CHERI is influenced by two broad underlying principles that are +as much philosophical as architectural, but are key to all aspects of the +design: + +\begin{description} +\item[\textit{The principle of least privilege}] It should be possible to + express and enforce a software design in which each program component can execute + with only the privileges it requires to perform its function. + This is expressed in terms of architectural privileges (e.g., by allowing + restrictions to be imposed in terms of bounds, permissions, etc., + encapsulating a software-selected but hardware-defined set of rights) and at + higher levels of abstraction in software (e.g., by allowing sealed + capabilities to refer to encapsulated code and data incorporating both a + software-selected and software-defined set of rights). +\psnote{the ``architectural privileges'' vs ``higher levels of + abstraction'' conceptualization works a bit better here than on p.1, + but it still seems iffy if I try to nail it down: the sealed caps + are just as much in the ISA architecture as the first set} + This principle has a long history in the research literature, and has been + explored (with varying degrees of granularity) both in terms of the expression + of reduced privilege (i.e., through isolation and compartmentalization) and + the selection of those privileges (e.g., through hand separation, automated + analysis, and so on). + +\item[\textit{The principle of intentional use}] When multiple rights + are available to a program, the selection of rights used to authorize work + on behalf of the program should be explicit, rather than implicit in the + architecture or another layer of software abstraction. + The effect of this principle is to avoid the accidental or unintended + exercise of rights that could lead to a violation of the intended policy. + It helps counter what are classically known as + `confused deputy' problems, in which a program will unintentionally exercise + a privilege that it holds legitimately, but on behalf of another program + that does not (and should not) exercise that privilege~\cite{Hardy1988}. + This principle, common to many capability systems but usually not explicitly + stated, has been applied throughout the CHERI design, from architectural + privileges (e.g., the requirement to explicitly identify capability + registers used for load or store) through to the sealed capability mechanism + that can be used to support object-capability models such as found in + CheriBSD. +\end{description} + +\noindent +These principles, which offer +substantial mitigations against + software vulnerabilities or malicious code, guide the integration +of a capability-system model with the general-purpose instruction set -- and +its exposure in the software model. +A more detailed exploration of the design principles embodied in and supported +by CHERI can be found in \textit{Fundamental Trustworthiness Principles in +CHERI}~\cite{neumann2017:cheri-principles}. + +\section{CHERI Capabilities: Strong Protection for Pointers} + +A key purpose of the CHERI protection model is to provide architectural +primitives to support strong protection for C and C++-language pointers. +Typically, language-level pointer types are implemented using architectural +integers in registers and in memory. +CHERI provides a new architectural data type, the \textit{capability}, which +software (such as a compiler) can use use instead when implementing pointers. +CHERI protections complementing existing architectural protection mechanisms +such as virtual memory implemented by a Memory Management Unit (MMU) or +non-virtualized protection implemented by a Memory Protection Unit (MPU). +CHERI protections apply to the storage and manipulation of pointers, and also +accesses performed via pointers. +The rationale for this approach is two-fold: + +\begin{enumerate} +\item A large number of vulnerabilities in Trusted Computing Bases (TCBs), and + many of the application exploit techniques, arise out of bugs involving + pointer manipulation, corruption, and use. + These occur in several ways, with bugs such as those permitting attackers to + coerce arbitrary integer values into dereferenced pointers, or leading to + undesirable arithmetic manipulation of pointers or buffer bounds. + These can have a broad variety of impacts -- including overwriting or leaking + sensitive data or program metadata, injection of malicious code, and attacks + on program control flow, which in turn allow attacker privilege escalation. + + Virtual memory fails to address these problems as (a) it is concerned with + protecting data mapped at virtual addresses rather than being sensitive to + the context in which a pointer is used to reference the address -- and hence + fails to assist with misuse of pointers; and (b) it fails to provide + adequate \textit{granularity}, being limited to page granularity -- or even + more coarse-grained ``large pages'' as physical memory sizes grow. + +\item Strong integrity protection, fine-grained bounds checking, + encapsulation, and monotonicity for pointers can be used to construct + efficient \textit{isolation} and \textit{controlled communication}, + foundations on which we can build scalable and programmer-friendly + compartmentalization within address spaces. + This facilitates deploying scalable application sandboxing with greater + ubiquity, in turn mitigating a broad range of logical programming errors + higher in the software stack, as well as resisting future undiscovered + vulnerability classes and exploit techniques. + + Virtual memory also fails to address these problems, as (a) it scales + poorly, paying a high performance penalty as the degree of + compartmentalization grows; and (b) it offers poor programmability, + as the medium for sharing is the virtual-memory page rather than the + pointer-based programming model used for code and data sharing within + processes. +\end{enumerate} + +Consequently, \textit{CHERI capabilities} are designed to represent +language-level pointers with additional metadata to protect their integrity +and provenance, enforce bounds checks and permissions (and their +monotonicity), and hold additional fields supporting undereferenceable +(i.e., sealed) software-defined +pointers suitable to implement higher-level protection models such as +separation and efficient compartmentalization. +Unlike virtual memory, whose functions are intended to be managed only by +low-level operating-system components such as kernels, hypervisors, and system +libraries, CHERI capabilities are also targeted more broadly at compiler and +language-runtime use, allowing program structure and dynamic memory allocation +to direct their use. +%We anticipate CHERI being used within operating-system kernels, and also in +%userspace libraries and applications, for the purposes of both memory +%protection and compartmentalization. + +Significant attention has gone into providing strong compatibility with the C +and C++ programming languages, widely used in off-the-shelf TCBs such as +OS kernels and language runtimes, and also with conventional MMUs and +virtual-memory models -- which see wide use today and continue to operate on +CHERI-enabled systems. +This is possible by virtue of CHERI having a \textit{hybrid capability model} +that +securely +composes a capability-system model with conventional architectural +features and programming-language pointer interpretation. +CHERI is designed to support incremental migration via selective recompilation +(e.g., transforming pointers into capabilities, as discussed below). +It provides several possible strategies for selectively deploying changes +into larger code bases -- constructively trading off source-code +compatibility, binary compatibility, performance, and protection. + +Most source code can be recompiled to employ CHERI capabilities transparently +by virtue of existing pointer syntax and semantics, which the compiler can map +into capability use just as it currently maps that functionality into integer +address use -- while providing additional metadata to the architecture +allowing the implementation of stronger memory safety. +Code in which all pointers (and implied addresses) are implemented +solely using capabilities is referred to as \textit{pure-capability code}. +Capability use can also be driven selectively, albeit less transparently, +through annotation of C pointers and types to indicate that hybrid capability +code generation should be used when operating on those pointers -- referred to +as \textit{hybrid-capability code}. +It is also possible to imagine compilers making automatic policy-based +decisions about capability use on a case-by-case basis, based on trading off +compatibility, performance, and protection with only limited programmer +intervention. +It is further worth observing that, although the primary focus of CHERI has +been protecting pointers using capabilities, capabilities are a more +generalizable hardware data type that can be used to protect other types from +corruption and mis-manipulation. + + +\section{Architectural Capabilities} +\label{sec:architecturalcapabilities} + +\psnote{Note to be associated with Figure~\ref{fig:fig-pointer-provenance}: + Suggest we explain here what the boxes and arrows are, and how they + illustrate those properties. Are the horizontal bars all + representations of the global (typically virtual) address space, with the + coloured regions capabilities? But then if the arrows are pointers + (occurrences of capabilities), I don't understand why multiple + arrows come from the same source? Do Load/Store and Execute refer + to the top-level bars, or are they just identifying the colours?} + +\psnote{Also prompted by Figure~\ref{fig:fig-pointer-provenance}, but + more generally: the + text doesn't explain the terms used in its caption (provenance + validity etc.), and they're a + bit mysterious right now. The Glossary does, and has a lot of other + carefully considered good stuff besides, but it's 400 pages away and I guess few readers + are going to spontaneously consult it. We could (though I realise this might + need an unachievable level of editing) in-line Glossary entries + throughout the text where appropriate, while still (using latex + macros to avoid forking) accumulating them in the Glossary at the end?} + +\begin{figure}[t] +\centering +\includegraphics[width=\columnwidth]{fig-pointer-provenance.pdf} +\caption{CHERI enforces strict \textit{integrity}, \textit{provenance +validity}, \textit{monotonicity}, \textit{bounds}, \textit{permissions}, and +\textit{encapsulation} on pointers, mitigating common vulnerabilities and +exploit techniques.} +\label{fig:fig-pointer-provenance} +\end{figure} + +In current systems, software typically implements pointers as integer values +stored in two architectural forms: in integer registers, and in memory. +\textit{Architectural capabilities} are a new architectural data type likewise +stored in register and memory, and containing an integer value that will most +frequently be interpreted as an address. +Capabilities also contain a number of other fields that contain additional +metadata associated with the address, such as bounds and permissions, as well +as a tag protecting their integrity. +Compilers, toolchain, and runtimes implementing pointers in terms of +architectural capabilities can imbue pointers with those protections, enforced +in hardware, subject to appropriately managing that metadata. +Capabilities are 2$\times$ (plus 1 bit) the size of the architecture's +natural address size, with the metadata compressed to fit in the additional +space. +On 32-bit architectures, capabilities are 64 bits ($+$1 tag bit), and on +64-bit architectures, capabilities are 128 bits ($+$1 tag bit). +In many senses, architectural capabilities used to implement pointers act like +the integers they replace, being loaded or stored, loaded or stored via, +jumped to, and so on. +The operating system, compiler, linker, and language runtimes are able to use +them to implement fine-grained memory safety for C and C++, as well as for +other purposes such as in-address-space software compartmentalization. + +The majority of the capability is stored in a register or in +addressable memory, as is the case +for current integer pointers, with additional metadata stored adjacent to the +integer address it protects. +However, there is also a 1-bit tag that may be +inspected via the instruction set, but is not visible via byte-wise loads and +stores. +This tag is used to record whether the capability is valid; it is +preserved by legal capability operations but cleared by other architectural +operations on that memory. +% +Some of CHERI's protections are for pointers themselves (e.g., their integrity +and provenance validity), whereas others are for the pointee data or code +referenced by pointers (e.g., bounds and permissions). +CHERI's sealing feature protects both a pointer (via immutability) and the +pointee (via non-dereferenceability). + +Extending architectures with capability registers and suitable memory storage +naturally aligns with many current architectural and microarchitectural design +choices, as well as software-facing considerations such as compiler code +generation, stack layout, operating-system behavior, and so on. +However, the generalized CHERI protection model can be mapped into +architectures in many different forms. +For example, an early design choice might be between holding capabilities in +a dedicated \textit{capability register file} or extending existing 64-bit +registers to hold 128-bit capabilities, known as a a \textit{merged +register file}. +While this and many other choices will affect a variety of factors in the +architecture and microarchitecture, the resulting protection model can be +considered \textit{portable} in that common protection properties and usage +patterns can be mapped into various architectural instantiations. +These topics are considered further in Chapter~\ref{chap:architecture}. + +In the remainder of this section, we describe the high-level protection +properties and other functionality that capabilities grant to pointers and +the execution environment (see Figure~\ref{fig:fig-pointer-provenance}): + +\begin{itemize} +\item Capability tags for pointer integrity and provenance + (Section~\ref{sec:model-tags}) +\item Capability bounds to limit the dereferenceable range of a pointer + (Section~\ref{sec:model-bounds}) +\item Capability permissions to limit the use of a pointer + (Section~\ref{sec:model-permissions}) +\item Capability monotonicity and guarded manipulation to prevent privilege + escalation (Section~\ref{sec:model-monotonicity}) +\item Capability sealing to implement software encapsulation + (Section~\ref{sec:model-sealedcapabilities}) +\item Capability object types to enable a software object-capability model + (Section~\ref{sec:model-object-types}) +\item Sealed capability invocation to implement non-monotonic domain + transition (Section~\ref{sec:model-sealed-capability-invocation}) +\item Capability control flow to limit pointer propagation + (Section~\ref{sec:model-capability-control-flow}) +\item Capability compression to reduce the in-memory overhead of pointer + metadata (Section~\ref{sec:model-compression}) +\item Hybridization with integer pointers + (Section~\ref{sec:model-hybridization-integer-pointers}) +\item Hybridization with MMU-based virtual memory + (Section~\ref{sec:model-hybridization-virtual-addressing}) +\item Hybridization with ring-based privilege + (Section~\ref{sec:model-hybridization-architectural-privilege}) +\item Failure modes and exception delivery + (Section~\ref{sec:failuremodesandexceptions}) +\item Capability revocation (Section~\ref{sec:model-capability-revocation}) +\end{itemize} + +\noindent +These features allow capabilities to be architectural primitives upon which +higher-level software protection and security models can be constructed (see +Section~\ref{sec:software-protection-using-cheri}). + +\psnote{ perhaps the following subsections should be restructured to + partition the description of what a capability comprises -- currently + \ref{sec:model-tags}--\ref{sec:model-permissions} are basically doing + that, though object types come later -- from the description of + properties, which currently \ref{sec:model-monotonicity} onwards + mostly are? Or, if not, at least have a short bit here that briefly + says what the data of a capability is. Perhaps also with an + \emph{illustrative} bit layout, emphasising that different arch + instantiations will do things differently. Could be a bit more + specific about the permissions data, too.} + +\subsection{Tags for Pointer Integrity and Provenance} +\label{sec:model-tags} + +Each location that can hold a capability -- whether a capability register or a +capability-sized, capability-aligned word of memory -- has an associated 1-bit +tag that consistently and atomically tracks capability validity for the value +stored at that location: + +\begin{description} +\item[Capability registers] each have a 1-bit tag tracking whether the + in-register value is a valid capability. + This bit will be set or cleared only as permitted by guarded manipulation. + +\item[Capability-sized, capability-aligned words of memory] each have a 1-bit + tag associated with the location, which is not directly addressable via data + loads or stores: \textit{tagged memory}. + Depending on the ISA variant, this may be at 64-bit or 128-bit granularity. + The capability's address, as well as its other metadata such as + bounds and permissions, are stored within the capability in addressable + memory; these fields are protected by the corresponding unaddressable tag + bit. + If untagged memory exists in the system, the tags of capability values + stored to those locations are discarded, and all loaded capability values + will have the tag bit unset. +\end{description} + +\noindent +Tags atomically follow capabilities into and out of capability registers when +their values are loaded from, or stored to, tagged memory. +Stores of other non-capability types -- e.g., of bytes or half words -- +automatically and atomically clear the tag in the destination memory location. +This allows in-memory pointer corruption by data stores to be detected on next +attempted dereference -- for example, this prevents arbitrary data received +over the network from being directly dereferenced as a pointer. + +The capability tag controls which operations can be performed using a +capability. +Attempting controlled operations on an untagged capability will cause an +precise exception. + +Regardless of the value of the tag bit, capability register fields can be +accessed: they can be extracted and, subject to guarded manipulation, +modified. +Similarly, addressable portions of the capability can be read from memory +using ordinary data load and store instructions. +Capability values can also be loaded and stored via other valid capabilities +regardless of the validity of the loaded or stored capability. +An untagged capability value is simply data: allowing capability registers to +hold untagged values allows them to be used for capability-oblivious +operations. +For example, a region of memory can be copied via capability registers, including pointers within data structures, preserving the value of the +tag bit for each copied location. + +However, other operations that \textit{dereference} or otherwise use a +capability require that the capability have its tag set -- i.e., be a +\textit{valid capability}. +Dereferencing refers to using the capability to load or store data or other +capabilities, or to fetch instructions. +This includes the implied dereference associated with the Default Data +Capability controlling legacy integer-relative loads and stores. +A valid tag is also required to use a capability to seal or unseal another +capability, to jump to that capability, to use it to set the architectural +compartment ID, or to call it for the purposes of domain transition. +Detailed information on which instructions require capabilities to have valid +tags, or operate on untagged capability values, may be found in the +instruction reference. + +Valid capabilities can be constructed only by deriving them from existing +valid capabilities, which ensures \textit{pointer provenance} +(Figure~\ref{fig:fig-pointer-provenance}). +In almost all cases, a new capability value will be derived from a single +capability value -- e.g., as a result of reducing bounds or permissions. +In a few cases, a capability may derive from multiple other capability +values. +For example, a sealed capability is derived from both the authorizing sealing +capability and an original data capability. +Similarly, an explicitly unsealed capability is derived from both the sealed +capability and the capability that authorizes its unsealing. + +Implementing C pointers as tagged capabilities allows them to be reliably +identified in the address space, which can help support techniques +such as garbage collection. +The CHERI model has been designed to avoid leakage of dereferenceable addresses out of +tagged capabilities (e.g., into general-purpose integer registers) during normal +memory allocation, comparison, manipulation, and dereference, to facilitate +reliable detection of pointers in both registers and memory. +Virtual addresses can be extracted from capabilities -- e.g., for debugging +purposes -- but avoiding doing so in code generation supports potential use +of techniques such as copying garbage collection. + +Our CHERI +prototypes implement tagged memory using partitioned memory, with tags and +associated capability-sized units linked close to the memory controller, and +propagated by the cache hierarchy in order to provide strong atomicity with +the data it protects. +However, it is also possible to imagine implementations in which DRAM -- +e.g., alongside ECC metadata -- or +non-volatile memory is extended to store tags with capability-sized units as +well. +We similarly assume that DMA will clear tags when writing to memory, although +it is possible to imagine future DMA implementations that are able to +propagate tags (e.g., to maintain tags on capabilities in descriptor rings). + +\subsection{Bounds on Capabilities} +\label{sec:model-bounds} + +Capabilities contain lower and upper bounds for the memory they authorize +access to +While a capability's address may move out of bounds (and perhaps back in +again), attempts to dereference (e.g., via a load, store, or instruction +fetch) an out-of-bounds capability will throw a hardware exception. +This prevents exploitation of buffer overflows on global variables, the heap, +and the stack, as well as out-of-bounds execution. +Allowing addresses to sometimes be out-of-bounds with respect to their +bounds -- without faulting -- is important for de-facto C-language +compatibility. +In an ideal world, addresses could be arbitrarily out of bounds. +However, our +bounds-compression scheme places restrictions on this property, as bounds +compression depends on redundancy between the address and bounds, which is +reduced when addresses are substantially outside of their bounds (see +Section~\ref{compression} for details). + +Bounds originate in allocation and linking events. +The operating system is able to place bounds on pointers to initial +address-space +allocations during process startup (e.g., via the initial register file, and +ELF auxiliary arguments in memory), and on an ongoing basis as new address-space +mappings are made available (e.g., via \ccode{mmap} system calls). +In practice, most bounds originate in the userspace language runtime or +compiler-generated +code, including the run-time linker for function pointers and global data, +the heap allocator for pointers to heap allocations, and generated code for +pointers taken to stack allocations. + Programming languages may also offer explicit subsetting support to allow +software to impose its own expectations on suitable bounds for memory accesses +to complex objects (such as in-memory video streams) or in their own memory +allocators. + +\subsection{Permissions on Capabilities} +\label{sec:model-permissions} +Capabilities additionally extend addresses with a permissions mask controlling how the +capability may be used. +For example, the run-time linker or compiler may set a capability's +permissions so that pointers to data cannot be reused for instruction fetch, +or so that pointers to code cannot be used to store data. +Further permissions control the ability to load and store capabilities +themselves, allowing the compiler to implement policies such as +\textit{dereferenceable code and data pointers cannot be loaded from character +strings.} +Permissions can also be made accessible to higher-level aspects of the +run-time and programmer model, offering dynamic enforcement of concepts +similar to \ccode{const}.\footnote{The C-language \ccode{const} qualifier +conflates several orthogonal properties and thus can not be enforced +automatically. +Our language extensions include more constrained \ccode{\_\_input} and +\ccode{\_\_output} qualifiers.} +Languages may provide further facilities to allow programmer-directed +refinement of permissions -- for example, for use in Just-in-Time (JIT) +compilers. + +Permissions changes, as with bounds setting, are often linked to allocation +events. +Permissions on capabilities for initial memory memory mappings can be +introduced by the kernel during process startup; further capabilities returned +for new mappings will also have their permissions restricted based on intended +use. +Executable capabilities representing function pointers and return addresses +will be refined by the run-time linker. +Read-only and read-write capabilities referring to data will be refined by the +run-time linker, heap allocator, and stack allocator. + +Permissions also control access to the sealing facility used for encapsulation +(see Section~\ref{sec:model-sealedcapabilities}). +While sealing permission could be granted with all data and code capabilities, +best practice in privilege minimization suggests that a separate hierarchy +of sealing pointers should be maintained instead. +Returning independent sealing capabilities via a dedicated system-call +interface reduces opportunities for arbitrary code and data capabilities being +used improperly for this purpose. + +\subsection{Capability Monotonicity via Guarded Manipulation} +\label{sec:model-monotonicity} + +\textit{Capability monotonicity} is a property of the CHERI protection model +ensuring that new capabilities must be derived +from existing capabilities only via valid manipulations that may narrow (but +never broaden) rights ascribed to the original capability. +This property prevents broadening the bounds on pointers, increasing the +permissions on pointers, and so on, eliminating many manipulation attacks and +inappropriate pointer reuses. +Monotonicity also underlies effective isolation for software +compartmentalization by ensuring that delegated capabilities cannot be used to +reach other resources despite further manipulation. +CHERI enforces capability monotonicity via four mechanisms: + +%across the vast majority of its +%instructions\psnote{what does ``vast majority'' mean here? that it +% doesn't enforce c.m. for some instructions, or that for some it +% isn't by g.m., or what?} +%\knnote{The sealedness of a capability is not monotonic, but the +% bounds and permissions of a capability are monotonic. To avoid +% defining what ``vast majority'' means, \textit{capability +% monotonicity} could also be replaced by \textit{capability bounds +% monotonicity} and \textit{capability permission monotonicity}.} +%by +%\psnote{think we can just delete this: ``virtue of \textit{guarded manipulation}: they cannot +%represent non-monotonic transformations. +%This is accomplished via''. I don't see a need to introduce the +%``guarded manipulation'' concept, esp. if we're immediately +%eliminating it, and I don't know exactly what it means.} +% four mechanisms: + +\begin{description} +\item[Limited expressivity] Some instructions are prevented, by design, from + expressing an increase of rights due to the expression of their operands and + implementation. + For example, permissions on capabilities are modified using a bitwise `and' + operation, and hence cannot express an increase in permissions. + +\item[Exceptions on monotonicity violation] Some instructions are able to + represent non-monotonic operations, but attempts to use them + non-monotonically will lead to an exception being delivered. + For example, an attempt to broaden bounds on a capability might throw an + exception without writing back the non-monotonically modified capability. + Throwing an exception at the point of violation may ease debugging close to + the point of violation. + +\item[Stripping the tag in register write-back] As an alternative to throwing + an exception, a non-monotonic operation might succeed in writing back a new + capability -- but with the tag bit cleared, preventing future dereference. + Clearing the tag allows the failure to be discovered by an explicit + software check, or on the next attempt to dereference. + This may make debugging more expensive (if additional checks are introduced, + perhaps with help from the compiler) or more tricky (if loss of the tag is + only discovered substantially later). + +\item[Stripping the tag in memory store] Tagged memory ensures that direct + modification of capabilities stored in memory using data store instructions + (whether non-monotonically or otherwise) will clear the tag on affected + in-memory capabilities. + This causes later attempts to dereference the capability to fail. + This ensures that attempts to modify capabilities cannot bypass guarded + manipulation. +\psnote{Add an analogous comment about debugging in this situation? +Are all such tag-clears indicative of bugs? (not necessarily, given +strong updates, but perhaps). Further to the +CHERI-as-perfect-sanitizer pitch, could we get eager detection here too, +by some combination of h/w and compiler support?} +\rwnote{No -- we frequently overwrite tagged values when storing a NULL, + initialising memory, writing via another type in a union, doing a COW onto + a page, etc. There are surely cases where clearing the tag is a bug, but + I suspect most cases are not.} + +\end{description} + +Selecting which enforcement mechanism to use will reflect the specific +operation being implemented, concerns about about ease of debugging, as well +as the context of the surrounding architecture. For example, in some +architectures, exceptions can be thrown on any instruction (e.g., MIPS), while +in others it is preferable for exceptions to be thrown only on memory +accesses (e.g., ARMv8-A). +As a result of these combined architectural features, guarded manipulation +implements \textit{non-bypassable capability monotonicity}. +\knnote{I don't know what ``non-bypassable'' means here: if the + sentence would read ``\ldots implements capability monotonicity'' + would that already be enough? I also wonder whether this sentence + should repeat that capabilities are not always monotonic.} + +Monotonicity allows reasoning about the set of reachable rights for executing +code, as they are limited to the rights in any capability registers, and +inductively, the set of any rights reachable from those capabilities -- but no +other rights, which would require a violation of monotonicity. +\knnote{But CHERI does violate monotonicity. Perhaps it would help to + introduce the exceptions to monotonicity first, and then discuss in + this paragraph why these exceptions are not a problem for + compartmentalization.} +Monotonicity is a key foundation for fine-grained compartmentalization, as it +prevents delegated rights from being used to gain access to other undelegated +areas of memory. +More broadly, monotonicity contributes to the implementation of the principle +of intentional use, in that capabilities not only cannot be used for +operations beyond those for which they are authorized, but also cannot +inadvertently be converted into capabilities describing more broad rights. + +The two notable exceptions to strict monotonicity +\psnote{are these really exceptions to c.m. in the specific sense + defined above, about the construction of new capabilities? They + have more to do with the lack of monotonicity of the permissions of + the current hardware thread...} + are invocation of sealed +capabilities (see Section~\ref{sec:model-sealed-capability-invocation}) and +exception delivery (see Section~\ref{sec:failuremodesandexceptions}). +\knnote{Is unsealing capabilities with \textit{CUnseal} an exception to monotonicity?} +Where non-monotonicity is present, control is transferred to code trusted to +utilize a gain in rights appropriately -- for example, a trusted +message-passing routine in the userspace runtime, or an OS-provided exception +handler. +This non-monotonicity is required to support protection-domain transition from +one domain holding a limited set of rights to destination domain that holds +rights unavailable to the originating domain -- and is therefore also +a requirement for fine-grained compartmentalization (see +Section~\ref{sec:model-isolation-controlled-communication-compartmentalization}). + + +\subsection{Capability Flags} +\label{sec:model-flags} +Capabilities include a flags field that can be manipulated freely. +Unlike the permissions field, it does not determine privilege, i.e., the state +of this field is orthogonal to capability monotonicity. +% +That is, these flags are intended to affect the \emph{semantics} of access, +rather than impose access control. +% +Currently, there are only architecture-specific interpretations for this +field: CHERI-RISC-V uses it to control opcode interpretation on instruction +fetch. +In the future, other non-security behavioral flags relating to capabilities may +be placed here, such +as to hint as to cache interactions for shared-memory rings, or to control +the behavior of operations such as capability equality testing. + +\subsection{Sealed Capabilities} +\label{sec:model-sealedcapabilities} + +Capability \textit{sealing} allows capabilities to be marked as +\textit{immutable} and \textit{non-deref\-erenceable}, causing hardware +exceptions to be thrown if attempts are made to modify, dereference, or jump +to them. +This enables capabilities to be used as unforgeable tokens of authority for +higher-level software constructs grounded in \textit{encapsulation}, while +still allowing them to fit within the pointer-centric framework offered by CHERI +capabilities. +There are two forms of capability sealing: pairs of capabilities sealed +using a common \textit{object type}, and stand-alone \textit{sealed entry +capabilities} (sentry capabilities). + +Sealed pairs are primarily designed to support the linking of a pair of code +and data capabilities for use together during domain transition. +A jump-like instruction, \insnref{CInvoke}, allows the two sealed +capabilities to be atomically unsealed as control flow transfers to the code +pointed to by the code capability, if their object types match. +This can be used to implement controlled privilege escalation for the purposes +of domain transition. +Sealed capabilities sharing a common object type are the foundation for +building the CheriBSD \textit{object-capability model} supporting +in-address-space compartmentalization, where pairs of sealed code and data +capabilities are object references whose invocation triggers a +protection-domain switch. + +Sealed entry capabilities simply seal a single code capability, which likewise +can be jumped to leading to an atomic unsealing and control-flow transfer. +This can also be used to implement domain transition with privilege +escalation, but to date has primarily been used to strength control-flow +robustness within a single protection domain by preventing the undesired +manipulation and use of code pointers. +Jump-and-link instructions acting on sealed entry capabilities also generate +a sealed return capability. + +Sealed capabilities can also be used to support other operating-system or +language robustness features, such as representing other sorts of delegated +(non-hardware-defined) rights, or ensuring that pointers are dereferenced only +by suitable code (e.g., in support of language-level memory or type safety). + +\rwnote{The next few subsections feel a bit redundant, and could be + condensed.} + +\subsection{Capability Object Types} +\label{sec:model-object-types} + +Capabilities contain an additional piece of metadata, an \textit{object +type}\psnote{that sounds as if \emph{all} capabilities contain an + object type...}% +\nwfnote{They do, at least implicitly! \insnref{CGetType} returns +something, specifically $2^{64}-1$, for unsealed capabilities. I've tried +to make the ISA speak in terms of \emph{encoding} the architectural +\cotype{} into the bit patterns of a capability, rather than being exactly +those bits, so that we can uniformly treat CC's separate \cotype{} field +and C-128's \csealed{} flag and shared \cotype{} bits.}% +, updated when a capability undergoes (un)sealing. +Object types allow multiple sealed capabilities to be indelibly (and +indivisibly) linked, so that the kernel or language runtime can avoid +expensive checks (e.g., via table lookups) to confirm that they are intended +to be used together. +% +\nwfnote{I am not sure I like ``indivisibly'' or maybe ``linked'' above; the indivisibility is +only up to ${\sim}/\cotype{}$, but it almost sounds like it's specifically a +pair of capabilities that are linked. Perhaps ``associated''?} +% +For example, for object-oriented compartmentalization models (such as the +CheriBSD object-capability model), pairs of sealed capabilities can represent +objects: one is the code capability for a class, and the other is a data +capability representing the data associated with a particular instance of an +object. +In the CheriBSD model, these two sealed capabilities have the same value in +their object-type field, and two candidate capabilities passed to object +invocation will not be accepted together if their object types do not match. + +The object-type field is set when a capability is sealed based on a second +input capability authorizing use of the type space -- itself simply a +capability permission authorizing sealing within a range of values specified +by the capability's bounds. +A similar model authorizes \textit{unsealing}, which permits a sealed +capability to be restored to a mutable and dereferenceable state -- if a +suitable capability to have sealed it is held. +This is used in the CheriBSD model during object invocation to grant the +callee access to its internal state. + +A similar model could be achieved without using an unsealing mechanism: a +suitably privileged component could inspect a sealed capability and rederive +its unsealed contents. +However, authorizing both sealing and unsealing based on type capabilities +allows the right to construct encapsulated pointers to be delegated, without +requiring recourse to a privileged software supervisor at the cost of +additional domain transitions -- or exercise of unnecessary privilege. + +\subsection{Sealed Capability Invocation} +\label{sec:model-sealed-capability-invocation} + +CHERI supports two forms of non-monotonicity\psnote{someone should + revisit this phrasing after the glossary for monotonicity is sorted + out: either that is only up to domain transitions, in which case + these aren't non-..., or not, in which case these are}: jump-like capability invocation, +and exception handling (see Section~\ref{sec:failuremodesandexceptions}). +In CHERI-MIPS, the \insnref{CInvoke} instruction accepts a pair of sealed +capability operands on which various checks are performed (for example, that +they are valid, sealed, and have matching object types). +If all tests are passed, then additional capabilities become available to the +executing CPU context by virtue of unsealing of the operand +registers. + +The destination execution environment has well-defined and +reliable properties, such as a controlled target program-counter capability +and additional data capability that can be used to authorize domain +transition. +\insnref{CInvoke} behaves much like a conventional jump to register, permitting an +in-address-space domain switch without changing rings. + +The newly executing code has the ability to further manipulate +execution state, and impose semantics such as call-return secure function +invocation (CheriBSD) or secure asynchronous message passing (microkernel), +which will likely be followed by a privilege de-escalation as a target domain +is entered (see +Section~\ref{sec:model-isolation-controlled-communication-compartmentalization}). + +\subsubsection{Object-Capability Policies in CHERI} + +Consider an execution environment having access to several capabilities +sealed with the same \texttt{otype}. The tests required by the +\insnref{CInvoke} mechanism describe a \emph{Cartesian product} of method +rights (indicated by the sealed code capability) and object rights (sealed data +capability) to this environment. Regardless of how the environment +came to have these sealed capabilities, it is free to pair any sealed code +capability with any sealed data capability and have the \insnref{CInvoke} +tests pass. + +Non-Cartesian and/or stateful policies can be encoded by +indirection, using memory to store additional data to be checked by the +invoked subsystem on entry. The sealed data pointers given out by the +invoked subsystem now no longer directly reference objects; instead, they +reference ``data trampolines'' describing the pairing of object(s) \emph{and +remote agent(s)} with associated access rights information. Attenuation of +access rights is no longer necessarily an ambiently available action and +requires either the explicit construction of membranes (i.e., proxy objects) +or active cooperation of the invoked subsystem (or an agent acting on its +behalf) to create new data trampoline(s). + +\subsection{Capability Protection for Non-Pointer Types} + +While the design of CHERI capabilities is primarily focused on the protection +of pointers, the pointer interpretation of capabilities depends entirely on +a capability's permissions mask. +If the mask authorizes load, store, and fetch instructions, then the +capability has a pointer interpretation. +\psnote{recent discussion in WG14/21 makes me sensitive to this: + there's important code out there that relies on equality comparison + of pointers to objects after lifetime-end of those objects, and the + analogue of that in CHERI (with some temporal safety scheme) could + be capabilities with tags or permissions cleared -- in which case + they'd still have \emph{a} pointer interpretation, albeit a limited one} +Capabilities are not required to have those permissions set, however, allowing +capabilities to be used for other purposes -- for example, to protect other +critical data types from in-memory corruption (such as implementing UNIX file +descriptors or stack canaries), or to authorize access to system services +(such as authorizing use of specific system calls identified by the +capability). +Sealed capabilities and a set of software-defined permissions bits facilitate +these use cases by permitting non-architecture-defined capability +interpretations while retaining capability-based protections. + +\subsection{Capability Flow Control} +\label{sec:model-capability-control-flow} + +The CHERI capability model is designed to support the implementation of +language-level pointers: tagged memory allows capabilities to be stored in +memory, and in particular, embedded within software-managed data structures +such as objects or the stack. +CHERI is therefore particularly subject to a historic criticism of +capability-system models -- namely, +that capability propagation makes it difficult to track +down and revoke rights (or to garbage collect them). +To address this concern, CHERI has three mechanisms by which the flow of +capabilities can be constrained: + +\begin{description} + +\item[Capability PTE or TLB bits] extend the existing load and store + permissions on TLB entries (or, in architectures with hardware page-table walkers, + page-table entries) with new permissions to authorize loading and storing + of capabilities. + This allows the operating system to maintain pages from which tagged + capabilities cannot be loaded (tags will be transparently stripped on load), + and to which capabilities cannot be stored (a hardware exception will be + thrown). + This can be used, for example, to prevent tagged capabilities from being + stored in memory-mapped file pages (as the underlying object might not + support tag storage), or to create regions of shared memory through which + capabilities cannot flow. + +\item[Capability load and store permission bits] extend the load and store + permissions on capabilities themselves, similarly allowing a capability to + be used only for data access -- if suitably configured. + This can be used to create regions of shared memory within an address + space through which capabilities cannot flow. + For example, it can +prevent + two separated compartments from + delegating access to one another's memory regions, instead limiting + communication to data traffic via the single shared region. +%%%% THE ORIGINAL SENTENCE WAS CONVOLUTED, ALLOWING SOMETHING NOT TO HAPPEN +%%%% DID NOT MAKE ANY SENSE. ON THE OTHER HAND, I MAY HAVE GOTTEN THE FIX +%%%% BACKWARDS! + +\item[Capability control-flow permissions] ``color'' capabilities to limit + propagation of specific types of capabilities via other capabilities. + This feature marks capabilities as \textit{global} or \textit{local} to + indicate how they can be propagated. + Global capabilities can be stored via any capability authorized for + capability store. + Local capabilities can be stored only via a capability specifically + authorized as \textit{store local}. + This can be used, for example, to prevent propagation of temporally + sensitive stack memory between compartments, while still allowing + garbage-collected heap memory references to be shared. + + This feature remains under development, as we hope to generalize it to + further uses such as limiting the propagation of ephemeral DRAM references + in persistent-memory systems. +However, it + is used successfully in the CheriBSD + compartmentalization model to improve memory safety and limit obligations of + garbage collection. + +\end{description} + +The decision to strip tags on load, but throw an exception on +store\psnote{this might be rather opaque to readers -- did it refer to + text that isn't there any more? maybe expand to +explain?}, reflects +pragmatic software utilization goals: language runtimes and system libraries +often need to implement \textit{capability-oblivious memory copying}, as the +programmer may not wish to specify whether a region of memory must (or must +not) contain capabilities. +By stripping tags rather than throwing an exception on load, a +capability-oblivious memory copy is safe to use against arbitrary +addresses and source capabilities -- without risk of throwing an exception. +Software that wishes to copy only data from a source capability (excluding tag +bits due to a non-propagation goal) can simply remove the load-capability +permission from the source capability before beginning a memory copy. +%%%% THIS only SEEMS TO BE IN THE RIGHT PLACE: only specific data, +%%%% RATHER THAN data only from a source capability!!! + +On the other hand, it is often desirable to detect stripping of a capability on +store\psnote{this may also appear cryptic} via a hardware exception, to ease debugging. +For example, it is typically desirable to catch storing a tagged capability to +a file as early as possible in order to avoid debugging a later failed +dereference due to loss of a tag. +Similarly, storing a tagged capability to a virtual-memory page might be an +indicator to a garbage collector that it may now be necessary to scan that +page in search of capabilities. + +This design point conserves PTE/TLB and permission bits; there is some argument +that completing the space (i.e., shifting to three or four bits +each\psnote{each what?}) would +offer functional improvements -- for example, the ability to avoid exceptions on +a capability-oblivious memory copy via a capability that does not authorize +capability store, or the ability to transparently strip tags on store to a +shared memory page. +However, we have not yet found these particular combinations valuable in our software experimentation, + +\subsection{Capability Compression} +\label{sec:model-compression} + +\psnote{confusing contrast between ``in-memory representation'' and + ``implementation'' -- I suspect better to position these as + architectural alternates, rather than the latter as an + ``implementation'' of the former} +\psnote{I suspect there needs to be some clarification across the + whole document about whether ``128-bit'' refers to the old 128-bit + scheme, or CHERI concentrate, or both? (and some particular version + of concentrate?)} + +Architecturally, capability fields are exposed via a set of accessor +instructions that get or set field values, such as the address, upper bound, +lower bound, and permissions. +The in-register and in-memory formats for capability contents may differ +substantially, permitting a more efficient representation using compressed +capability bounds. +CHERI utilizes a floating-point-like \textit{fat-pointer compression +technique} that relies on redundancy between the address, lower bound, and +upper bound. +The compressed representation exchanges stronger alignment requirements +(proportional to object size) for a more compact representation. + +The CHERI Concentrate compression model (see Section~\ref{compression}) maintains the monotonicity: +no ISA manipulation of a +capability can grant increased rights, and when unrepresentable cases are +generated +(e.g., a pointer substantially out of bounds, or a very unaligned object), +the pointer becomes un-dereferenceable. +Memory allocators already implement alignment requirements for heap and stack +allocations (word, pointer, page, and superpage alignments), and these +algorithms require only minor extension to ensure fully accurate bounds for +large memory allocations. Small allocations require no additional +alignment, where the definition of `small' depends on the compression format used and might be from 4 kiB to 1 MiB. +Relative to a 64-bit pointer, the 128-bit design reduces per-pointer memory +overhead (with a strong influence on cache footprint for some software +designs) by roughly two thirds, compared to, for example, a 256-bit +representation as found in earlier CHERI versions. + +\subsection{Hybridization with Integer Pointers} +\label{sec:model-hybridization-integer-pointers} + +Processors implementing CHERI capabilities also support existing programs +compiled to use conventional integer pointers, rather than capability +pointers, using two special capability registers: + +\begin{description} +\item[Default Data Capability (DDC)] DDC indirects and controls legacy + instructions that load and store relative to integer addresses rather than + capabilities. + +\item[Program Counter Capability (PCC)] PCC extends the conventional program + counter with capability metadata, indirecting and controlling instruction + fetches. +\end{description} + +Programs compiled to use capabilities to represent pointers (whether +implicitly or via explicit program annotations) will not use the default data +capability, instead employing capability registers and capability-based +instructions for pointer operations and indirection. +The program-counter capability will be used regardless of the code model +employed, although capability-aware code generation will employ constrained +program-counter bounds and permissions to implement control-flow robustness +rather than using a single large code segment. +Support for legacy loads and stores can be disabled by installing a +sufficiently constrained (e.g., untagged) default data capability. + +Different compilation modes and ABIs provide differing levels of compatibility +with existing code -- but include the ability to run entirely unmodified +non-CHERI binaries, to execute non-CHERI code in sandboxes within CHERI-aware +applications, and CHERI-aware code in sandboxes within CHERI-unaware +applications. + +\subsection{Hybridization with Virtual Addressing} +\label{sec:model-hybridization-virtual-addressing} + +\begin{figure}[t] +\centering +\includegraphics[width=\columnwidth]{fig-cheri-high-level.pdf} +\caption{CHERI supports a wide range of operational software models including: +unmodified MMU-based RISC operating systems; hybrid operating systems +utilizing the MMU to support a process model and/or virtualization while +using CHERI within virtual address spaces; and pure single-address-space +CHERI-based operating systems.} +\label{fig:fig-os-models} +\end{figure} + +The above features\psnote{which? just those in the preceding + subsection, or all in this chapter?} compose naturally with, and complement, the Virtual-Memory (VM) +models commonly implemented using commodity Memory Management Units (MMUs) in +current OS designs (Figure~\ref{fig:fig-os-models}). +Capabilities are \textit{within} rather than \textit{between} address spaces; +they protect programmer references to data (pointers), and are intended to be +driven primarily by the compiler rather than by the operating system. +In-address-space compartmentalization complements process isolation by +providing fine-grained memory sharing and highly efficient domain switching +for use between compartments in the same application, rather than between +independent programs via the process model. +Operating-system kernels will also be able to use capabilities to improve the +safety of their access to user memory, as user pointers cannot be accidentally +used to reference kernel memory, or accidentally access memory outside of +user-provided buffers. +Finally, the operating system might choose to employ capabilities internally, +and even in its interactions with userspace, in referencing kernel data +structures and objects. + +\subsection{Hybridization with Architectural Privilege} +\label{sec:model-hybridization-architectural-privilege} + +Conventional architectures employ ring-based mechanisms to control use of +architectural privilege: only code executing in ``supervisor'' or ``kernel'' +mode is permitted to access the virtual address space with supervisor rights, +but also to control the MMU, certain cache management operations, +interrupt-related features, system-call return, and so on. +The ring model prevents unprivileged code from manipulating the virtual +address space (and other processor features) in such a way as to bypass memory +protection and isolation configured by the operating system. +Contemporary instantiations may also permit virtualization of those features, +allowing unmodified operating systems to execute efficiently over microkernels +or hypervisors. +CHERI retains support for these models with one substantial modification: use +of privileged features within privileged rings, other than in accessing +virtual memory as the supervisor, depends on the program-counter capability +having a suitable hardware permission set. + +This feature similarly allows code \emph{within} kernels, microkernels, and +hypervisors to be compartmentalized, preventing bypass of the capability model +within the kernel virtual address space through control of virtual memory +features. +The feature also allows vulnerability mitigation by allowing only explicit +use of privileged features: kernel code can be compiled and linked so that +most code executes with a program-counter capability that does not authorize +use of privilege, and only by jumping to selected program-counter capabilities +can that privilege be exercised, preventing accidental use. +Finally, this feature paves the way for process and object models in which the +capability model is used without recourse to rings. + +\subsection{Failure Modes and Exceptions} +\label{sec:failuremodesandexceptions} + +Bounds checks, permissions, monotonicity, and other properties of the CHERI +protection model inevitably introduce the possibility of new ISA-visible +failure modes when software violates rules imposed through capabilities +(whether due to accident or malicious intent). +In general, in our prototyping, we have selected to deliver \textit{hardware +exceptions} as early as possible when such events occur; for example, on +attempts to perform disallowed load and store operations, to broaden bounds, +and so on. +This allows the operating system (which in turn may delegate to the userspace +language runtime or application) the ability to catch and handle failures in +various ways -- such as by emulating disallowed accesses, converting to a +language-visible exception, or performing some diagnostic or mitigation +activity. + +Different architectures express differing design philosophies for when +exceptions may be delivered, and there is flexibility in the CHERI model in +when exceptions might be delivered. +For example, while an attempt to broaden (rather than narrow) bounds could +generate an immediate exception (our prototyping choice), the operation could +instead generate a non-dereferenceable pointer as its output, in effect +deferring an exception until the time of an attempted load, store, or +instruction fetch. +The former offers slightly improved debuggability (by exposing the error +earlier), whereas the latter can offer microarchitectural benefits by +reducing the set of instructions that can throw exceptions. +Both of these implementations ensure monotonicity by preventing derived +pointers from improperly allowing increased access following guarded +manipulation, and are consistent with the model. + +\subsection{Capability Revocation, Garbage Collection, and Flow Control} +\label{sec:model-capability-revocation} + +Revocation is a key design concern in capability systems, as revocation is +normally implemented via table indirection -- an approach in tension with the +CHERI design goal of avoiding table-based lookups or indirection on pointer +operations. +As described in Section~\ref{sec:model-capability-control-flow}, CHERI provides +explicit ISA-level features to constrain the flow of capabilities in order to +reduce the potential overhead in walking through memory to find outstanding +capabilities to resources (e.g., to implement garbage collection or sweeping +revocation). +There are also explicit features in the instruction-set architecture that +directly support the implementation of both pointer and object-capability +revocation: + +\begin{description} +\item[MMU-based virtual-address revocation] + As CHERI capabilities are evaluated prior to virtual addressing (i.e., they + are pointers within address spaces), the MMU can be used not only to + maintain virtual address spaces, but also to explicitly prevent the + dereferencing of pointers to virtual address ranges -- regardless of the + capability mechanism. + Combined with a policy of either non-reuse of virtual address space (as + distinct from non-reuse of physical address space), sweeping revocation, or + garbage collection, this + allows all outstanding capabilities (and any further capabilities derived + from them) to be revoked without the need to search for those capabilities + in the register file or memory. + This revocation is subject to the granularity and scalability limitations + of MMUs: for example, it is not possible to revoke portions of the virtual + address space smaller than one page. + + This low-level hardware mechanism must be combined with suitable software + management of the virtual address space in order for it to be effective. + For example, a policy of non-reuse of the virtual address space at + allocation time will prevent stale capabilities from referring to a new + allocation after an old one has been freed. + A further policy of revoking MMU mappings for the region of virtual address + space will prevent use of the freed memory as a communications channel from + the point of free. + Asynchronous and batched revocations will improve performance, subject to + windows of opportunity in which use after free (but not use after + re-allocation) might still be possible. + It is also worth observing explicitly that non-reuse of the virtual address + space in no way implies non-reuse of physical memory, as memory underlying + revoked virtual addresses can be safely reused. + An alternative to virtual address-space non-reuse is garbage collection, in + which outstanding references to freed (and perhaps revoked) virtual address + space are sought and explicitly invalidated. + + Use of the MMU for virtual address-space revocation is subject to a number + of limits depending on the non-reuse and garbage-collection policies + adopted. + For example, if small, sub-page-size, tightly packed memory allocations + are freed in a manner that leads to fragmentation (i.e., both allocated and + freed memory within the same virtual page), then revocation will not be + possible -- as it would prevent access to valid allocations (which could be + emulated only at great expense). + Similarly, fragmentation of the virtual address space may lead to greater + overhead in the OS's virtual-memory subsystem, due to the need to maintain + many individual small mappings, as well as the possibility of reduced + opportunity to use superpages should revocations occur that are expressed + in terms of smaller page sizes. + + However, overall, the MMU provides a non-bypassable means of preventing use + of all outstanding capabilities to a portion of the virtual address space, + permitting strong revocation to be used where appropriate. + +\item[Accurate garbage collection] + Traditional implementations of C are not amenable to accurate garbage + collection because unions and types such as \ccode{intptr_t} allow a register + or memory location to contain either an integer value or a pointer. + CHERI-C does not have this limitation: The tag bit makes it possible to + accurately identify all memory locations that contain data that can be + interpreted as a pointer. + In addition, the value of the pointer (encoded in the offset) is distinct from + the base and length; thus, code that stores other data in low bits of the + pointer will not affect the collector. + Garbage collection is the logical dual of revocation: garbage collection + extends the lifetime of objects as long as they have valid references, whereas + revocation curtails the lifetime of references once the objects to which they + refer are no longer valid. + A simple stop-the-world mark-and-sweep collector for C can perform both tasks, + scanning all reachable memory, invalidating all references to revoked objects, and recycling unreachable memory. + + More complex garbage collectors typically rely on read or write barriers + (i.e., mechanisms for notifying the collector that a reference has been read or + written). + These are typically inserted by the compiler; however, in the context of revocation + the compiler-generated code must be treated as untrusted. + It may be possible to use the permission bits -- either in capabilities + themselves or in page-table entries -- to introduce traps that can be used as + barriers. + +\item[Capability tags for sweeping revocation] + In addition to supporting garbage collection, capability tags in registers + and memory also allow the reliable identification of capabilities for the + purposes of explicit revocation. + Subject to safety in the presence of concurrency (e.g., by suspending + software execution in the address space, or temporarily limiting + access to portions of the address space), software can reliably + sweep through registers and memory, clearing the tags (or otherwise + replacing) +for + capabilities that are to be revoked. + This comes at potentially significant cost, which can be mitigated through + use of the MMU -- e.g., to prevent capabilities from being used in certain + pages intended only to store data, or to track where capabilities have been + stored via a capability dirty bit in virtual-memory metadata. + +\item[Revocation of sealed capabilities] + When the interpretation of sealed capabilities is performed by a trustworthy + software handler, there is the opportunity for that + handler to implement revocation semantics explicitly. + For example, the object invocation handler of a trusted userspace + supervisor entered by \insnref{CInvoke} + could interpret the + address of a sealed capability as pointing to a table entry + within its domain, + rather than directly encapsulating a pointer to the target object's data. + The address could be split into two parts: a table index, and a generation + counter. + The table entry could then itself contain a generation counter. + Sealed object-capability references to the table entry would incorporate + the value of the counter at the time of sealing, and the invocation handler + would check the generation count, rejecting invocation on a mismatch. + When object-capability revocation is desired, the table generation counter + could be bumped, preventing any further use of outstanding references. + This approach would be subject to limits on table-entry reuse and the size + of the table; for example, a reasonable design might employ a 24-bit table + index (permitting up to $2^{24}$ objects in the system at a time) and a + 40-bit generation counter. + Use of the 24-bit object-type could further increase the number of objects + permissible in the system concurrently. + Many other similar schemes incorporating explicit checks for revocation + based on software interposition employing counters, tables, etc., can be + imagined. +\end{description} + +CHERI includes several architectural features to facilitate techniques such +as garbage collection and sweeping revocation. +Tags allow capabilities to be accurately identified in both registers and +memory. +In addition, CHERI can limit the flow of capabilities via various mechanisms, +limiting the memory areas that must be swept for the two techniques: MMU +permissions controlling capability load and store via specific pages; +capability permissions controlling capability load and store via specific +capabilities; and the local-global feature that controls the propagation of +subsets of capabilities. +These primitives may be combined to support higher-level software policies +such as: + +\begin{itemize} +\item ``capabilities may not be shared between address spaces'' +\item ``local stack capabilities may be stored only to the local stack'' +\item ``this shared-memory buffer can be used only for data sharing, not + capability sharing'' +\item ``capabilities can flow only one way through this shared buffer'' +\item ``only the TCB can introduce capabilities to shared memory between + compartments'' +\item ``supervisor involvement is required to share sealed capabilities + between compartments'' +\item ``first store of a capability to any page will deliver an exception to + the supervisor'' +\end{itemize} + +\noindent +As a result, garbage collection and sweeping revocation can rely on strong +invariants about capability propagation that limit the areas of memory that +must be swept for garbage collection or revocation. + +\section{Software Protection and Security Using CHERI} +\label{sec:software-protection-using-cheri} + +The remainder of the chapter explores these ideas\psnote{which? just 2.3.16 +\emph{Capability Revocation, Garbage Collection, and Flow Control}, or +everything in 2, or the section title?} in greater detail, +describing the high-level semantics + offered +by the ISA and how they are mapped +into programmer-visible constructs such as C-language features. +The description in this chapter is intended to be agnostic to the specific +Instruction-Set Architecture (ISA) in which CHERI is implemented. +Whereas the +implementation described in later chapters maps into the 64-bit MIPS ISA, the +overall CHERI strategy is intended to support a variety of ISA backends, and +could be implemented in the 64-bit ARMv8, SPARCv9, or RISC-V ISAs with only +modest localization. +In particular, it is important that programmers be able to rely on the +properties described in this chapter -- regardless of the ISA-level +implementation -- +and that software abstractions built over these properties have +consistent behavior that can be depended upon to mitigate vulnerabilities. + +\subsection{Abstract Capabilities} + +The CHERI architecture imposes tight constraints on capability manipulation and +use including provenance validity and monotonicity. +While these rules generally permit the execution of current C and C++ code +without significant modification, there are occasions on which the +programmer model of pointer properties (for example) may violate rules for +capabilities. +For example, the architecture maintains provenance validity of capabilities +from reset, permitting them to remain valid only if they are held in tagged +memory or registers. +In practice, operating systems may swap memory pages from DRAM to disk and +back, violating architectural provenance validity. +The OS kernel is able to maintain the appearance of provenance validity for +swapped pages by saving tags when swapping out, and re-deriving capabilities +from valid architectural capabilities when swapped back in -- maintaining the +\textit{abstract capabilities} that compiler-generated code works with. +Our ASPLOS 2019 paper on CheriABI explores this issue in +detail~\cite{davis2019:cheriabi}, covering topics such as context switching, +the C-language runtime, virtual-memory behavior, and debugging. + +\subsection{C/C++ Language Support} + +CHERI has been designed so that there are clean mappings from the C and C++ +programming language into these protection properties. Unlike +conventional virtual memory, the compiler (and not just the operating system) +is intended to play a significant role in managing these protections. +Protection is within address spaces, whether in a conventional user +process, or within the operating-system kernel itself in implementing its own +services or in accessing user memory: + +\begin{description} +\item[Spatial safety] +CHERI protections are intended to directly protect the \textit{spatial safety} +of userspace types and data structures. This protection includes +the integrity of pointers to code and +data, as well as implied code pointers in the form of return addresses and +vtable entries; bounds on heap and stack allocations; the prevention +of executable data, and modification of executable code via permission. + +\item[Temporal safety] +CHERI provides instruction-set foundations for higher-level \textit{temporal +safety} properties, such as non-reuse of heap allocations via garbage +collection and revocation, and compiler clearing of return addresses on the +stack. +In particular, the capability tags on registers and in memory allows pointers +to be reliably located and atomically replaced with a different value +(including an invalid capability). +Acceleration features allow capabilities to be located more efficiently than +simply sweeping all of physical memory. + +\item[Software compartmentalization] +CHERI provides hardware foundations for highly efficient +\textit{software compartmentalization}, the fine-grained decomposition of +larger software packages into +smaller isolated components that are +granted access +only to the memory (and also software-defined) resources they actually require. + +\item[Enforcing language-level properties] +CHERI's software-defined permission bits and sealing features can also be used +to enforce other language-level protection objectives (e.g., opacity of +pointers exposed outside of their originating modules) or to implement +hardware-assisted type checking for language-level objects (e.g., to more +robustly link C++ objects with their corresponding vtables). + +\end{description} + +\noindent +CHERI protections are implemented by a blend of +functionality: + +\begin{description} + +\item[Compiler and linker] responsible for generating code that manipulates + and dereferences code and data pointers, compile-time linkage, and + stack allocation. + +\item[Language runtime] responsible for ensuring that program run-time + linkage, memory allocation, and exceptions implement suitable policies in + their refinement and distribution of capabilities to the application and its + libraries. + +\item[Operating-system kernel] responsible for interactions with conventional + virtual memory, maintaining capability state across context switches, + reporting protection failures via signals or exceptions, and implementing + domain-transition features used with compartmentalization. + +\item[Application program and libraries] responsible for distributing and + using pointers, allocating and freeing memory, and employing higher-level + capability-based protection features such as compartmentalization during + software execution. + +\end{description} + +\subsubsection{Data-Pointer Protection} + +Depending on +the desired +compilation mode, some or all data pointers will be implemented +using capabilities. +We anticipate that memory allocation (whether from the stack or heap, or via +kernel memory mapping) will return capabilities whose bounds and permissions +are suitable for the allocation, which will then be maintained for any derived +pointers, unless explicitly narrowed by software. +This will provide the following general classes of protections: + +\begin{description} +\item[Pointer integrity protection] Overwriting a pointer in memory with data + (e.g., received over a socket) will not be able to construct a + dereferenceable pointer. + +\item[Pointer provenance checking and monotonicity] Pointers must be derived + from prior pointers via manipulations that cannot increase the range or + permissions of the pointer.\psnote{TODO: check consistency with + glossary for provenance after that's updated} + +\item[Bounds checking] Pointers cannot be moved outside of their allocated + range and then be dereferenced for load, store, or instruction fetch. + +\item[Permissions checking] Pointers cannot be used for a purpose not granted + by its permissions. + In as much as the kernel, compiler, and run-time linker restrict + permissions, this will (for example) prevent data pointers from being used + for code execution. + +\item[Bounds or permissions subsetting] Programmers can explicitly reduce the + rights associated with a capability -- e.g., by further limiting its valid + range, or by reducing permissions to perform operations such as store. + This might be used to narrow ranges to specific elements in a data structure + or array, such as a string within a larger structure. + +\item[Flow control on pointers] Capability (and hence pointer) flow + propagation can be limited using CHERI's capability flow-control + mechanism, and used to enforce higher-level policies such as that +\textit{stack capabilities cannot be written to global data structures}, or + that \textit{non-garbage-collectable capabilities cannot be passed across + domain transitions}. +\end{description} + +\subsubsection{Code-Pointer Protection} + +Again with support of the compiler and linker, CHERI capabilities can be used +to implement control-flow robustness that prevents code pointers from being +corrupted or misused. +This can limit various forms of control-flow attacks, such as overwriting +of return addresses on the stack, as well as pointer re-use attacks such as +\textit{Return-Oriented Programming (ROP)} and \textit{Jump-Oriented +Programming (JOP)}. +Potential applications include: + +\begin{description} +\item[Return-address protection] Capabilities can be used in place of pointers + for on-stack return addresses, preventing their corruption. + +\item[Function-pointer protection] Function pointers can also be implemented + as capabilities, preventing corruption. + +\item[Exception-state protection] On-stack exception state and signal + frame information also contain pointers whose protection will limit + malicious control-flow attacks. + +\item[C++ vtable protection] A variety of control-flow attacks rely on either + corrupting C++ vtables, or improper use of vtables, which can be detected + and prevented using CHERI capabilities to implement both pointers to, and + pointers in, vtables. +\end{description} + +\subsection{Protecting Non-Pointer Types} + +One key property of CHERI capabilities is that although they are designed to +represent pointers, they can also be used to protect other types -- whether +those visible directly to programmers through APIs or languages, or those used +only in lower-level aspects of the implementation to improve robustness. +A capability can be stripped of its hardware interpretation by masking all +hardware-defined permission bits (e.g., those authorizing load, store, and so +on). +A set of purely software-defined permission bits can be retrieved, masked, and +checked using suitable instructions. +Sealed capabilities further impose immutability on capability fields. +These non-pointer capabilities benefit from tag-based integrity and provenance +protections, monotonicity, etc. +There are many possible use cases, including: + +\begin{itemize} +\item Using CHERI capabilities to represent hardware resources such as + physical addresses, interrupt numbers, and so on, where software will + provide implementation (e.g., allocation, mapping, masking), but +where capabilities + can be stored and delegated. + +\item Using CHERI capabilities as canaries in address spaces: while stripping + any hardware-defined interpretation, tagged capabilities can be used to + detect undesired memory writes where bounds may not be suitable. + +\item Using CHERI capabilities to represent language-level type information, + where there is not a hardware interpretation, but unforgeable tokens are + required -- for example, to authorize use of vtables by suitable C++ + objects. +\end{itemize} + +\subsection{Isolation, Controlled Communication, and Compartmentalization} +\label{sec:model-isolation-controlled-communication-compartmentalization} + +In \textit{software compartmentalization}, larger complex bodies of software +(such as operating-system kernels, language runtimes, web browsers, and office +suites) are decomposed into multiple components that run in isolation from one +another, having only selectively delegated rights to the broader application +and system, and limited further attack surfaces. +This allows the impact of exploited vulnerabilities or faults to be +constrained, subject to software being suitably structured -- i.e., that its +privileges and functionality have been suitable decomposed and safely +represented. +Software sandboxing is one example of compartmentalization, in which +particularly high-risk software is tightly isolated due to the risks it poses +-- for example, in rendering HTML\psnote{can be ambiguously read -- isolation of the + HTML(!), or the rendering engine?} downloaded from a web site, or in processing +images attached to e-mail. +Compartmentalization is a more general technique, of which sandboxing is just +one design pattern, in which privileges are delimited and minimized to improve +software +robustness~\cite{Karger87,provos:preventingprivesc,Watson10,gudka15:soaap}. +Software compartmentalization is one of the few known techniques able to +mitigate future unknown classes of software vulnerability and exploitation, as +its protective properties do not depend on the specific vulnerability or +exploit class being used by an attacker. + +Software compartmentalization is build on two primitives: \textit{software +isolation} and \textit{controlled communication}. +CHERI hybridizes two orthogonal mechanisms exist to construct isolation and +controlled communication: the conventional MMU (using multiple virtual address +spaces as occurs in widely used sandboxed process models), and CHERI's +in-address-space capability mechanism (by constructing +closures\psnote{not sure what that ``closures'' is supposed to mean -- closures in + the PL sense? probably not. boundaries?} in the graph +of reachable capabilities). +These mechanisms can be combined to construct fine-grained software +compartmentalization within virtual address spaces, which may complement (or +even replace) a virtual-address-based process model. + +To constrain software execution using CHERI, a more privileged software +runtime must arrange that only suitable capabilities are delegated to software +that must run in isolation. +For example, the runtime might grant software access to its own code, a stack, +global variables, and heap storage, but not to the private privileged state of +the runtime, nor to the internal state of other isolated software components. +This is accomplished by suitably initializing the thread register file of the +software (and hence CPU register file when it begins execution) to point into +an initial set of delegated code and allocation capabilities, and then +exercising discretion in storing capabilities into any further memory that it +can reach. +Capability nonforgeability, monotonicity, and provenance validity ensure +that new rights cannot be created by constrained software, and that existing +rights cannot be escalated. +As isolation refers not just to the initial state, but also the continuing +condition of software, discretion in delegating capabilities must be continued +throughout execution, in much the same way that software isolation using the +MMU depends not just on safe initial configuration, but safe continuing +configuration as code executes. + +In order to achieve compartmentalization, and not simply isolation, CHERI's +selective non-monotonic\psnote{again: should check consistency of use + of ``monotonicity'' following glossary fix} mechanisms can be used: exception handling, and +jump-based invocation. +If the software supervisor arranges that additional rights will be acquired by +the exception handler (using more privileged kernel code and data +capabilities), then the exception handler will be able to perform +non-monotonic transformations on the set of capabilities in the register file, +accessing memory (and other resources) unavailable to the isolated code. +Sealed capabilities allow encapsulated handles to resources to be delegated to +isolated code in such a manner that the sealed capabilities and resources they +describe can be protected from interference. +CHERI's jump-based invocation mechanism allows those resources to be unsealed +in a controlled manner, with control flow transferred to appropriate receiving +code in a way that protects both the caller and callee. +This source of non-monotonicity can also be used to implement domain +transition by having the caller discard rights prior to performing the jump, +and the callee acquire any necessary rights via unsealing of its capabilities. +It is essential to CHERI's design that exercise of non-monotonicity support +reliable transfer of control to code trusted with newly acquired rights. + +Efficient controlled communication can persist across domain transitions +through the appropriate delegation of capabilities to shared memory, as well +as the delegation of sealed capabilities allowing selected domain switching. +CHERI's permissions allow uses of shared memory to be constrained in a +variety of ways. +The software configuring compartmentalization might choose to delegate +load-only or load-execute access to shared code or read-only data segments. +Other permissions constrain the propagation of capabilities; for example, the +software supervisor might allow communication only using data and not +capabilities via a communication ring between two mutually distrusting phases +in a processing pipeline. +Similarly, CHERI's local-global protections might be utilized to prevent +capabilities for non-garbage-collectable memory from being shared between +mutually distrusting components, while still allowing garbage-collectable heap +allocations to be delegated. + +Collectively, these mechanisms allow a variety of software-defined +compartmentalization models to be constructed. +We have experimented with several, including the CheriBSD in-process +compartmentalization mechanism, which models domain transition on a secure +function call with trusted stack maintained by the operating-system kernel +via exception-based invocation~\cite{watson15:cheri,watson2016:microjournal}, +and microkernel-based systems that utilize jump-based domain transition within +a single-address-space operating system, which model domain transition on +asynchronous or synchronous message passing. +Effective software compartmentalization relies not only on limiting access to +memory, but also a variety of other properties such as appropriate (perhaps +fair or prioritized) scheduling, resource allocation, and non-leakage of data +or rights via newly allocated or freshly reused memory, which are higher-level +properties that must be ensured by the software supervisor. +While many of these concerns exist in MMU-based software compartmentalization, +they can take on markedly different forms or implications. +For example, the zeroing of memory before reuse prevents the leakage of +rights, and not just data, in the capability model. +As with MMU-based isolation and compartmentalization, CHERI provides strong +architectural primitives, and is not intended to directly address +microarchitectural concerns such as cache side channels or information leakage +through branch predictors, performance counters, or other state. + +Substantially different architectural underpinnings for capability-based, +rather than MMU-based, compartmentalization give it quite different practical +properties. +For example, two protection domains sharing access to a region of memory will +not experience increased page-table and TLB footprint by virtue of sharing a +virtual address space. +Similarly, the model for delegating shared memory is substantially different: +simple pointer delegation, rather than page-table construction, has far lower +overhead. +On the other hand, revoking access to shared memory via the capability model +requires either non-reuse of portions of the virtual address space, sweeping +capability revocation, or garbage collection (see +Section~\ref{sec:model-capability-revocation}). +We have found that the two approaches complement one another well: virtual +memory continues to provide a highly useful underpinning for conventional +coarse-grained virtual-machine and process models, whereas CHERI +compartmentalization works extremely well within applications as it caters to +rapid domain switching and large amounts of sharing between fine-grained and +tightly coupled components. + +\subsection{Source-Code and Binary Compatibility} + +CHERI supports Application Programming Interfaces (APIs) and +Application Binary Interfaces (ABIs) with compatibility properties intended +to facilitate incremental deployment of its features within current software +environments. +For example, an OS kernel can be extended to support CHERI capabilities in +selected userspace processes with only minor extensions to context switching +and process setup, allowing both conventional and CHERI-extended programs to +execute -- without implying that the kernel itself needs to be implemented +using capabilities. +Further, given suitable care with ABI design, CHERI-extended libraries can +exist within otherwise unmodified programs, allowing fine-grained memory +protection and compartmentalization to be deployed selectively to the most +trusted software (i.e., key system libraries) or least trustworthy (e.g., +video CODECs), without disrupting the larger ecosystem. +CHERI has been tested with a large range of system software, and efficiently +supports a broad variety of C programming idioms poorly supported by the state +of the art in software memory protection. +It provides strong and reliable hardware-assisted protection in eliminating +common exploit paths that today can be mitigated only by using probabilistically +correct mechanisms (e.g., grounded in address-space randomization) that often +yield to determined attackers. + +\subsection{Code Generation and ABIs} + +Compilers, static and dynamic linkers, debuggers, and operating systems will +require extension to support CHERI capabilities. +We anticipate multiple conventions for code generation and binary interfaces, +including: + +\begin{description} +\item[Conventional code generation] Unmodified operating systems, user + programs, and user libraries will work without modification on CHERI + processors. + This code will not receive the benefits of CHERI memory protection -- + although it may execute encapsulated within sandboxes maintained by + CHERI-aware code, and thus can participate in a larger compartmentalized + application. + It will also be able to call hybrid code. + +\item[Hybrid code generation] Conventional code generation, calling + conventions, and binary interfaces can be extended to support (relatively) + transparent use of capabilities for selected pointers -- whether hand + annotated (e.g., with a source-code annotation) or statically determined at + compile time (e.g., return addresses pushed onto the stack). + Hybrid code will generally interoperate with conventional code with + relative ease -- although conventional code will be unable to directly + dereference capability-based types. + CHERI memory-protection benefits will be seen only for pointers implemented + via capabilities -- which can be adapted incrementally based on tolerance + for software and binary-interface modification. + +\item[Pure-capability code generation] Software can also be compiled to use + solely capability-based instructions for memory access, providing extremely + strong memory protection. + Direct calling in and out of pure-capability code from or to conventional + code or hybrid code requires ABI wrappers, due to differing calling + conventions. + Extremely strong memory protection is experienced in the handling of both + code and data pointers. + +\item[Compartmentalized code] is accessed and can call out via + object-capability invocation and return, rather than by more traditional + function calls and returns. + This allows strong isolation between mutually distrusting software + components, and makes use of a new calling convention that ensures, among + other properties, non-leakage of data and capabilities in unused argument + and return-value registers. + Compartmentalized code might be generated using any of the above models; + although it will experience greatest efficiency when sharing data with other + compartments if a capability-aware code model is used, as this will allow + direct loading and storing from and to memory shared between compartments. + Containment of compartmentalized components does not depend on the + trustworthiness of the compiler used to generate code for those components. +\end{description} + +Entire software systems need not utilize only one code-generation or +calling-convention model. For example, a kernel compiled with conventional +code, and a small amount of CHERI-aware assembly, can host both hybrid +and pure-capability userspace programs. +A kernel compiled to use pure-capability or hybrid code generation could +similarly host userspace processes using only conventional code. +Within the kernel or user processes, some components might be compiled to be +capability-aware, while others use only conventional code. +Both capability-aware and conventional code can execute within +compartments, where they are sandboxed with limited rights in the broader +software system. +This flexibility is critical to CHERI's incremental adoption model, and +depends on CHERI's hybridization of the conventional MMU, OS models, and C +programming-language model with a capability-system model. + +\subsection{Operating-System Support} + +Operating systems may be modified in a number of forms to support CHERI, +depending on whether the goal is additional protection in userspace, in the +kernel itself, or some combination of both. +Typical kernel deployment patterns, some of which are orthogonal and may be +used in combination, might be: + +\begin{description} +\item[Minimally modified kernel] The kernel enables CHERI support in the + processor, initializes register state during context creation, and + saves/restores capability state during context switches, with the goal of + supporting use of capabilities in userspace. + Virtual memory is extended to maintain tag +integrity + across swapping, and to prevent + tags from being used with objects that cannot support them persistently + -- such as memory-mapped files. + Other features, such as signal delivery and debugging support require minor + extensions to handle additional context. + The kernel can be compiled with a capability-unaware compiler and limited + use of CHERI-aware assembly. + No additional protection is afforded to the kernel in this model; instead, + the focus is on supporting fine-grained memory protection within user + programs. + +\item[Capability domain switching in userspace] Similar + to the minimally modified kernel model, + only modest changes are made to the kernel itself. + However, some additional extensions are made to the process model in order + to support multiple mutually distrusting security domains within user + processes. + Access to system calls is limited to authorized userspace domains. + +\item[Fine-grained capability protection in the kernel] In addition to + capability context switching, the kernel is extended to support fine-grained + memory protection throughout its design, replacing all kernel pointers with + capabilities. + This allows the kernel to benefit from pointer tagging, bounds checking, and + permission checking, mitigating a broad range of pointer-based attacks such + as buffer overflows and return-oriented programming. + +\item[Capability domain switching in the kernel] Support for a + capability-aware kernel is extended to include support for fine-grained, + capability-based compartmentalization within the kernel itself. + This in effect implements a microkernel-like model in which components of +the kernel, such as filesystems, network processing, etc., have only limited + access to the overall kernel environment delegated using capabilities. + This model protects against complex threats such as software supply-chain + attacks against portions of the kernel source code or compiled kernel + modules. + +\item[Capability-aware system-call interface] Regardless of the kernel code + generation model, it is possible to add a new system-call Application Binary + Interface (ABI) + that replaces conventional pointers with capabilities. + This has dual benefits for both userspace and kernel safety. + For userspace, the benefit is that system calls operating on its behalf will + conform to memory-protection policies associated with capabilities passed to + the kernel. + For example, the \ccode{read} system call will not be able to overflow a + buffer on the userspace stack as a result of an arithmetic error. + For the kernel, referring to userspace memory only through capabilities + prevents a variety of \textit{confused deputy problems} in which kernel bugs + in validating userspace arguments could permit the kernel to access kernel + memory when userspace access is intended, perhaps reading or overwriting + security-critical data. + The capability-aware ABI would affect a variety of user-kernel interactions + beyond system calls, including ELF auxiliary arguments during program + startup, signal handling, and so on, and resemble other +pointer-compatibility ABIs -- such as 32-bit compatibility for 64-bit kernels. +\end{description} + +\noindent +These points in the design space revolve around hybrid use of CHERI +primitives, with a continued strong role for the MMU implementing a +conventional process model. +It is also possible to imagine operating systems created without taking this +view: + +\begin{description} + +\item[Pure-capability operating system] A clean-slate operating-system design + might choose to minimize or eliminate MMU use in favor of using the CHERI + capability model for all protection and separation. + Such a design might reasonably be considered a \textit{single address-space + system} in which capabilities are interpreted with respect to a single + virtual address space (or the physical address space in MMU-free designs). + All separation would be implemented in terms of the object-capability + mechanism, and all memory sharing in terms of memory capability delegation. + If the MMU is retained, it might be used simply for full-system + virtualization (a task for which it is well suited), or also support + mechanisms such as paging and revocation within the shared address space. +%\pgnnote{This alternative would be particularly relevant to dedicated +% special-purpose CHERI processor systems, perhaps for input-output +% microprocessors or Internet of Things device controllers.} + +\end{description} + +\section{Protection Against Microarchitectural Side-Channels} +\label{section:microarchitectural-sidechannels} + +While CHERI has been designed as an architectural security mechanism -- i.e., +one concerned with explicit access to memory contents or control of system +functions -- recent publication of highly effective attacks against +microarchitectural side channels has caused us to reconsider CHERI's potential +role~\cite{Kocher2018spectre}. +Several of these attacks (e.g., Spectre variants) rely on overly optimistic +speculative execution of paths that violate invariants embedded in the +executing code. +For example, code may contain explicit bounds checks, but by suitably training +a branch predictor, an attacker can cause the code to bypass those checks in +speculative execution, which then leaves behind a measurable result in the +instruction or data cache. +CHERI offers new opportunities to bound speculative execution such that it +observes security properties otherwise not explicitly available to the +microarchitecture. +Possible bounds on speculative execution grounded in CHERI features include: + +\begin{itemize} +\item Enforcing capability tag checks in speculation, preventing code or data + pointers without valid provenance from being used. +\item Enforcing capability bounds checks in speculation, preventing any + out-of-bounds memory accesses for data load/store or instruction fetch. +\item Enforcing capability permission checks in speculation, preventing + inappropriate loads or stores or instruction fetch. +\item Enforcing other capability protections, such as being sealed, to ensure + encapsulation is implemented in speculation. +\item Limiting data-value speculation for capability values, or for values + that will be combined with capabilities (e.g., integer values that are added + to a capability offset to calculate a new capability). +\item Limiting speculation across protection-domain boundary transitions. +\end{itemize} + +In addition, we have extended CHERI with new instructions to get and set a +software-defined \textit{compartment ID} (CID). +Unlike with conventional MMU-based virtual address spaces that have specific +address-space identifiers or page-table roots identifying protection domains, +CHERI protection domains are emergent from the dynamic delegation of +capabilities. +The CID might be used by microarchitectures to limit speculation of sharing +of microarchitectural state. +For example, branch-predictor entries may be tagged with a CID to prevent them +from being used with the wrong compartment. +This would necessarily need to be combined with an address-space identifier +(ASID), as addresses (and hence corresponding capabilities) may have different +interpretations in different address spaces. + +As with other CHERI features, CID management is authorized using a capability, +allowing regions of CIDs to be delegated to domains or switchers for their +own selective use. +Where strong side-channel-free confidentiality is not required between a set +of domains, the CID may be left as-is. +Otherwise, a suitably authorized software domain switcher will be able to set +the CID to a new value. + +Protective effects rely, of course, on appropriate implementation in the +microarchitecture. +Further notes on our thoughts on CHERI and microarchitectural side channels +may be found in our technical report, \textit{Capability Hardware Enhanced +RISC Instructions (CHERI): Notes on the Meltdown and Spectre Attacks}~\cite{UCAM-CL-TR-916}. diff --git a/chap-rationale.tex b/chap-rationale.tex new file mode 100644 index 00000000..8eb89af5 --- /dev/null +++ b/chap-rationale.tex @@ -0,0 +1,1516 @@ +\chapter{Detailed Design Rationale} +\label{chap:rationale} + +During the design of CHERI, we considered many different capability +architectures and design approaches. This chapter describes the various +design choices; it briefly outlines some possible alternatives, and provides +rationales for the selected choices. + +\section{High-Level Design Approach: Capabilities as Pointers} + +Our goals of providing fine-grained memory protection and compartmentalization +led to an early design choice to allow capabilities to be used as C- and +C++-language pointers. +This rapidly led to a number of conclusions: + +\begin{itemize} +\item Capabilities exist within virtual address spaces, imposing an ordering in + which capability protections are evaluated before virtual-memory + protections; this in turn had implications for the hardware composition of + the capability coprocessor and conventional interactions with the MMU. + +\item Capability pointers can be treated by the compiler in much the same way + as integer pointers, meaning that they will be loaded, manipulated, + dereferenced, and stored via registers and to/from general-purpose memory + only by explicit instructions. + These instructions were modeled on similar conventional RISC instructions. + +\item Incremental deployment within programs meant that not all pointers would + immediately be converted from integers to capabilities, implying that both + forms might coexist in the same virtual memory; + also, there was a strong desire to embed capabilities + within data structures, rather than store them in separate segments, + which in turn required fine-granularity tagging. + +\item Incremental deployment and compatibility with the UNIX model implied + the need to retain + the general-purpose memory management unit (MMU) more or less as + it then existed, including support for variable page sizes, TLB layout, + and so on. + The MIPS ISA describes a software-managed TLB rather than hardware + page-table walking -- as is present in most other ISAs. + However, this is not fundamental + to our approach, and either model would work. +\end{itemize} + +\section{Tagged Memory for Non-Probablistic Protection} +\label{sec:probablistic_capability_protection} + +Introducing tagged memory has the potential to impose a substantial adoption +cost for CHERI, due to greater microarchitectural disruption. +We have demonstrated that there are efficient implementations of memory +tagging, even without integrated tag support within +DRAM~\cite{joannou2017:tagged-memory, UCAM-CL-TR-936}, but even so there is a significant +concern as to whether potential adopters will perceive the hurdle of adopting +tagged memory as outweighing the benefits that tagged memory brings. +In this section, we consider the benefits of tagging, as well as how +cryptographic non-tagged approaches might be used. +Tagging offers a number of significant potential benefits: + +\begin{itemize} +\item Tags are a deterministic (non-probabilistic) means of protecting the + integrity and provenance validity of pointers in memory. + Probabilistic schemes, such as cryptographic hashes, are exposed both to + direct brute forcing (especially due to limited bit investment within + pointers) and also reinjection if leaked to attackers. + +\item Tags offer strong atomicity properties that are also well-aligned with + current microarchitecture (e.g., in caches), avoiding the need for + substantial disruption close to the processor. + +\item Tags have highly efficient microarchitectural implementations, including + being directly embedded in tagged DRAM (an option likely to become increasingly + available due to the widespread adoption of +error-correcting codes, and also via tag + controllers and tag caches that are affine to the DRAM controller. + These may be substantially more performance- and energy-efficient than + cryptographic techniques that would require hashes to be calculated or checked. + +\item Tags offer strong C-language compatibility, which has been demonstrated + with significant software corpuses including operating-system kernels + (FreeBSD), the complete UNIX userspace (FreeBSD), and significant C and + C++-language applications (the Postgres database, OpenSSH client and server, + and WebKit web-rendering framework). + + Key areas of incompatibility include the need to explicitly preserve tags + during memory copies via capability-sized, capability-aligned loads and + stores, and stronger alignment requirements for pointers. + The operating system must also support maintaining tags in virtual memory, + including across operations such as swapping, memory compression, and + virtual-machine migration. + In general, we have found that the modifications are modestly sized, + although some impacts (such as the cost of tag preservation and + restoration) are not yet fully quantified -- e.g., for memory compression. + +\item Tags allow pointers to be deterministically identified in memory, a + foundation for strong temporal memory-safety techniques such as revocation + and garbage collection. + +\item The choice between tag-preserving and tag-stripping memory copying + allows software to impose policies on when it is appropriate and safe for + pointers to move between protection domains. + For example, a kernel can selectively preserve tags in system-call + arguments, + preventing data copied into the kernel from an untrustworthy process from + being interpreted as a pointer within the kernel, or when received by + another process. +\end{itemize} + +As an alternative to tagging, one could imagine making use of probabilistic +cryptographic hashing techniques that protect capabilities from corruption, +not unlike Cryptographic Control-Flow Integrity +(CCFI)~\cite{Mashtizadeh_CCFICryptographicallyEnforced_2015} or Arm's ARM v8.3 Pointer +Authentication Codes (PAC). +Some number of bits would be co-opted from either the virtual address (as is +the case in CCFI or PAC), or from the metadata portion of a CHERI capability to +hold a keyed hash, protecting the contents from corruption in memory or due to +mis-manipulation in a register, rather than a tag. +With additional capability metadata bits available, consumption of +virtual-address bits could be reduced. + +Wherever the CHERI architecture requires a tag check, a cryptographic hash +check could instead be required architecturally. +Wherever the CHERI architecture maintains a tag during pointer manipulation, +the cryptographic hash could be updated. +While architectural behavior might appear to require frequent checks of, and +updates to, the hash (e.g., during loop iteration as a register is +successively incremented and then used for loads or stores), it is conceivable +that microarchitectural techniques (such as speculation) might both reduce the +delay associated with those updates, and perhaps also elide them entirely, +updating the hash only during write back. +Tags appear to offer the following essential advantages over cryptographic +approaches: + +\begin{itemize} +\item Tags offer deterministic rather than probabilistic protection, + and require neither secrecy of a cryptographic key, nor brute-forcing resistance given a + bounded number of hash bits. + Depending on the OS model, cryptographic keys might also be shared by more + than one address space -- e.g., if \ccode{fork()} is frequently used to + generate multiple processes, or if there is a shared memory segment that + includes linked pointers. + +\item Tags do not rely on cryptographic hash generation during capability + updates, nor checking during dereference. + These could otherwise lead to a performance overhead (e.g., as a result of + load-to-use or check-to-use delays), or energy-use overheads (due to + frequent cryptographic hash operations). + +\item Tags prevent reinjection of leaked pointer values, even though the + bitwise pattern of the addressable memory contents remain identical. + Potential vulnerabilities with hash-based protection include leaking a valid + pointer value to a local or remote attacker via socket communications. + The attacker could later reinject that value -- potentially into a different + process if they share keying material (e.g., if they are forked from the + same parent). + +\item Tags ensure provenance validity of capabilities, such that the TCB can + deterministically ensure that a pointer value is no longer in memory. + As with the previous item, this protects against reinjection, but has the + stronger inductive property that the TCB can reliably perform revocation or + garbage collection. + This is also essential to compartmentalization strength. +\end{itemize} + +However, a hash-based approach also has several appealing properties when +compared to tags: + +\begin{itemize} +\item Cryptographic hashes do not require the implementation of tagged memory, + which could reduce memory-subsystem complexity and DRAM-traffic impact. + +\item Cryptographic hashes do not impose alignment requirements on + capabilities, which may improve compatibility. + +\item Cryptographically protected capabilities can be copied in memory, + swapped to disk, or migrated in virtual-machine images, without special + support for tags. + + This could entirely avoid the need for special capability load and store + instructions, although retaining them might assist with microarchitectural + optimization of hash use. +\end{itemize} + +If hashed-based protection were viewed as a stepping stone to a full CHERI +implementation, substituting hashing for tags in an initial implementation, +there are several steps that could be taken to reduce the further disruption +associated with later tag adoption: + +\begin{itemize} +\item Explicit capability load and store instructions would be maintained and + used in future capability-aware memory copying, etc. + +\item Capability load and store instructions would require strong alignment + for values that would later be used for load and store, even though this is + not required with hashing. + +\item Other non-tag-related capability properties, such as monotonicity, would + continue to be enforced via guarded manipulation. +\end{itemize} + +However, substantially smaller benefit would arise prior to the introduction +of tags: capabilities would be able to provide capability-like spatial memory +protection, and probabilistic pointer integrity protection, but not the +non-probabilistic protection or enforcement of provenance validity required +for stronger policies such as preventing pointer reinjection, supporting +temporal memory safety through deterministic pointer identification in memory, +or enabling in-address-space compartmentalization that depends on those +properties. + +\section{Capability Register File} + +The decision to separate the capability-register file from the general-purpose +integer +register file is somewhat arbitrary from a software-facing perspective: we +envision capabilities gradually displacing general-purpose integer registers as +pointers, but where management of the two register files will remain largely +the same, with stack spilling behaving the same way, and so on, as is already +the case for disjoint integer and floating-point register files. +We selected the separate representation for a few pragmatic reasons: + +\begin{itemize} +\item Coprocessor interfaces frequently make the assumption of additional + register files (a la floating-point registers). +\item Capability registers are quite large, and by giving the capability + coprocessor its own pipeline for manipulations, we could avoid enforcing a + 128-bit-wide path through the main pipeline. +\item It is more obvious, given a coprocessor-based interface, how to provide + compatibility support in which the capability coprocessor is ``disabled,'' + the default configuration in order to support unmodified MIPS compilers and + operating systems. +\end{itemize} + +\noindent +However, it is entirely possible to imagine a variation on the CHERI design in +which (more similar to the manner in which the 32-bit x86 ISA was extended to +support 64-bit registers) the two files are \textit{merged} and able to hold +both general-purpose integer registers and capability registers. +This becomes a more appealing choice in the presence of 128-bit compressed +capabilities, as register size doubles rather than quadruples. + +Early in our design cycle, capability registers were able to hold only true +capabilities (i.e., with tags); later, we weakened this requirement by adding +an explicit tag bit to each register, in order to improve support for +capability-oblivious code such as memory-copy routines able to copy data +structures consisting of both capabilities and ordinary data. +This shifts our approach somewhat more towards a merged approach; our view +is that efficiency of implementation and compatibility (rather than +maintaining a negligible +effect on the software model) would be the primary reasons to select one +approach or another for a particular starting-point ISA. + +Another design variation might have specific capability registers +more tightly coupled with general-purpose integer registers -- an approach we discussed +extensively, especially when comparing with the bounds-checking literature, +which has explored techniques based on {\em sidecar registers} or associative +look-aside buffers. +Many of these approaches did not adopt tags as a means of strong integrity +protection (which we require for the compartmentalization model), which +would make associative techniques less suitable. +Further, we felt that the working-set properties of the two register files +might be quite different; effectively pinning the two to one another would +reduce the efficiency of both. + +In CHERI-RISC-V (Chapter~\ref{chap:cheri-riscv}), we parameterize the +instruction set to support both split and merged registers files. +This will allow us to explore in greater detail the performance and +compatibility implications of this design choice. + +\section{The Compiler is Not Part of the TCB for Isolated Code} + +CHERI is designed to support the isolation of arbitrary untrustworthy code, +including code compiled with an incorrect or compromised compiler. +The security argument outlined in +Chapter~\ref{chap:assurance} starts with the premise that the attacker is able to +run arbitrary machine-code. This approach has advantages for high-assurance systems: +compilers are often large and complex programs, and proving correctness of their +security mechanisms is easier if it does not depend on also proving the correctness +of the compiler. This approach also has the advantage that users are not restricted +by the security design to programming in just one programming language, and can use +any language for which a compiler has been written. In particular, it is a design +goal of CHERI that it be able to run legacy code written in C. + +Some earlier capability machines, such as the Burroughs B5000, made the compiler +a privileged program. We have followed the approach taken in capability machines +such as CAP, in which the compiler was not privileged. + +\mrnote{We could expand on this, perhaps in the high-assurance section. We do depend +on the compiler being correct, in the sense that if the attacker has complete +control of the compiler, he can make the programs you've compiled with it do +whatever you want. The property we're looking for is more like: assuming the TCB +has been compiled with a correct compiler, we can allow untrusted users to compile +their code using whatever compiler they want, without fear that this will let them +break out of the sandbox. We probably do depend on the \emph{dynamic linker} being +correct -- this depends on how we load code into a sandbox.} + +\section{Base and Length Versus Lower and Upper Bounds} + +The CHERI architecture permits two different interpretations of capabilities: +as a virtual address paired with lower and upper bounds; and as a base, +length, and current offset. +These different interpretations support differing C-language models for +pointers. +The former, in which pointer casts to integers return their virtual addresses, is more compatible with current software, but risks leaking those virtual +addresses (or their implications) out of tagged values where they cannot be +found for the purposes of pointer-transformation techniques such as copying +garbage collection. +The latter, in which pointer casts to integers return their offsets, is less +compatible (as comparisons between pointers into different buffers may give +surprising equality results), but avoids leakage of virtual address out of +tagged values, enabling techniques such as copying garbage collection. + +Over time, our thinking on these two approaches has shifted from aiming to +support copying garbage collection in C to one focused on revocation and +greater compatibility. +While some C source code naturally is extremely careful to avoid integer +interpretations of pointers, significant amounts of historic code, especially +systems code, cannot avoid this idiomatic use. +For example, run-time linkers and memory allocators both naturally consider +integer virtual addresses as part of their operation. +More subtly, techniques such as ordering locks for objects based on object +address, or sorting trees based on object address, makes copying garbage +collection a difficult prospect. +Compressed capabilities further complicate this story, as a precise lower +bound may not be possible without padding; this is easy to arrange within +memory allocators for new allocations, but when subsetting an existing +allocation (e.g., to describe the bounds of an array embedded within another +structure), the 0 offset from the bottom of the embedded structure may not +carry over to being a 0 offset relative to the base address of a capability. + +In recent versions of the CHERI C compiler, we have shifted to preferring a +virtual-address interpretation of pointers in all cases except those where +specific built-in functions are used to query the offset. +We retain an optional compiler mode utilizing an offset interpretation, which +will be suitable for future experimentation with copying garbage collection. + +\section{Signed and Unsigned Offsets} + +In the CHERI instructions that take both a register offset and an immediate +offset, the register offset is treated as unsigned integer, whereas the +immediate offset is treated as a signed integer. + +Register offsets are treated as unsigned so that given a capability to +the entire address space (except for the very last byte, as +explained above), a register offset can be used to access any byte within it. +Signed register offsets would have the disadvantage that negative offsets +would fail the capability bounds check, and memory at offsets within the +capability greater than $2^{63}$ would not be accessible. + +Immediate offsets, on the other hand, are signed, because the C compiler +often refers to items on the stack using the stack pointer as register +offset plus a negative immediate offset. +We have already encountered observable difficulty due to a reduced number of +bits available for immediate offsets in capability-relative memory operations +when dealing with larger stack-frame sizes; it is unclear what real +performance cost this might have (if any), but it does reemphasize the +importance of careful investment of how instruction bits are encoded. + +\section{Address Computation Can Wrap Around} + +If the target address of a load or store (base $+$ offset $+$ register offset +$+$ scaled immediate offset) is greater than \emph{max\_addr} or less than +zero, it wraps around modulo $2^{64}$. The load or store succeeds if this +modulo arithmetic address is within the bounds of the capability (and other +checks, such as for permissions, also succeed). + +An alternative choice would have been for an overflow in the address computation +to cause the load or store to fail with a length-violation exception. + +The approach of allowing the address to wrap around does not allow malicious +code to break out of a sandbox, because a bounds check is still performed on +the wrapped-around address. + +However, there is a potential problem if a program uses an array offset that +comes from a potentially malicious source. For example, suppose that code for +parsing packet headers uses an offset within the packet to determine the +position of the next header. The threat is that an attacker can put in a +very large value for the offset, which will cause wrap-around, and result +in the program accessing memory that it is permitted to access, but was not +intended to be accessed at this point in the packet processing. This attack +is similar to the confused deputy attack. It can be defended against by +appropriate use of \insnref{CSetBounds}, or by using some explicit +range checks in application code in addition to the bounds checks that are +performed by the capability hardware. +\nwfnote{Maybe "Using \insnref{CSetBounds} to derive a capability +to just the array, and using this capability for offsetting, supplants any +explicit range checks in application code." This might also be a good place +to say something about Meltdown and Spectre (variant 1)? "By informing the +architecture of the intended bounds of access, even speculative use of a +capability can be precisely confined."} + +The advantage of the approach that we have taken is that it fits more naturally +with C language semantics, and with optimizations that can occur inside compilers. +The following are equivalent in C: + +\begin{itemize} +\item +a[x + y] +\item +*(a + x + y) +\item +(a + x)[y] +\item +(a + y)[x] +\end{itemize} + +They would not be equivalent if they had different behavior on overflow, and +the C compiler would not be able to perform optimizations that relied on +this kind of reordering. + +\section{Overwriting Capabilities in Memory} + +In CHERI, if a valid in-memory capability is partly overwritten via an +untagged data store, then the tag associated with the in-memory capability +is cleared, making it an invalid capability that cannot be dereferenced. + +Alternative designs would have been for the capability to be zeroed first +before being overwritten; or for the write to raise an exception (with +an explicit ``clear tag in memory'' operation for the case when a +program really intends to overwrite a capability with non-capability data). + +The chosen approach is simpler to +implement in hardware. If store instructions needed to check the tag bit +of the memory location that was being written, then they would need a +read-modify-write cycle to memory, rather than just a write; in general, +the MIPS architecture carefully avoids the need for a read-modify-write cycle +within a single instruction. (However, once the memory system needs +to deal with cache coherence, a write is not that much simpler than a +read-modify-write.) + +The CHERI behavior also has the advantage that programs can write to a +memory location (e.g., when spilling a register onto the stack) without +needing to worry about whether that location previously contained a +capability or non-capability data. + +A potential disadvantage is that the contents of capabilities cannot be +kept secret from a program that uses them. A program can always discover +the contents of a capability by overwriting part of it, then reading the +result as non-capability data. In CHERI, there are +intentionally +other, more direct, ways +for a program to discover the contents of a capability it owns, and this +does not present a security vulnerability. + +However, there are ABI concerns: we have tried to design the ISA in such a +way that software does not need to be aware of the in-memory layout of +capabilities. As it is necessarily exposed, there is a risk that software +might become dependent on a specific layout. +One noteworthy case is in the operating-system paging code, which must +save and restore capabilities and their tags separately; this can be +accomplished by using instructions such as \insnref{CGetBase} on untagged +values loaded from disk and then refining an in-hand capability using +\insnref{CSetBounds} -- an important reason not to limit capability field +retrieval instructions to tagged values. +We have proposed a new instruction, \insnref{CBuildCap}, which would add a +tag to an untagged value in a capability-register operand, authorized by a +second operand holding a suitably authorized capability, to avoid software +awareness of the in-memory layout, as well as to accelerate tag restoration +when implementing system services such as swap. +This instruction in effect implements rederivation, which is also possible +using a sequence of individual instructions refining the authorizing +capabilities bounds, permissions, object type, and so on. +\insnref{CBuildCap} is not intended to change the set of reachable +capabilities. + +\section{Reading Capabilities as Bytes} + +In CHERI, if a data load instruction such as \insnref[clbhwd]{CLB} is used +on a memory location containing a capability, the internal representation +of the capability is read. An alternative architecture would have +such loads return zero, or raise an exception. + +As noted above, +because the contents of capabilities are not secret, allowing them to be +read as raw data is not a security vulnerability. + +\section{OTypes Are Not Secret} + +Another consequence of the decision not to make the contents of capabilities secret +is that the \cotype{} field is not secret. It is possible to determine the +\cotype{} of a capability by reading it with \insnref{CGetType}, or by +reading the capability as bytes. If a program has two pairs of code and data +capabilities, ($c_1$, $d_1$) and ($c_2$, $d_2$) it can check if $c_1$ and $c_2$ +have the same \cotype{} by invoking \insnref{CInvoke} on ($c_1$, $d_2$). +\jrtcnote{This is a weird thing to say; yes you implicitly check by not +trapping, but, uh, don't use it that way?} + +As a result, a program can tell whether it has been passed an object of +\cotype{} O or an interposing object of \cotype{} I that forwards the +\insnref{CInvoke} on to an object of \cotype{} O (e.g. after having performed +some additional access control checks or auditing first). +\section{Capability Registers are Dynamically Tagged} + +In CHERI, capability registers and memory locations have a tag bit +that indicates whether they hold a capability or non-capability data. +(An alternative architecture would give memory locations a tag bit, +where capability registers could contain only capabilities -- with +an exception raised if an attempt were made to load non-capability data into a +capability register with \insnref{CLC}.) + +Giving capability registers and memory locations a tag bit +simplifies the implementation of \ccode{cmemcpy()}. +\ccode{cmemcpy()} is a variant of \ccode{memcpy()} that copies +the tag bit as well as the data, and so can be used to copy structures +containing capabilities. As capability registers are dynamically tagged, +\ccode{cmemcpy()} can copy a structure by loading +its constituent words into capability +registers and storing them to memory, without needing to know at compile time +whether it is copying a capability or non-capability data. + +Tag bits on capability registers may also be useful for dynamically typed +languages in which a parameter to a function can be (at run time) either a +capability or an integer. \ccode{cmemcpy()} can be regarded as +a function whose parameter (technically a \ccode{void *}) is +dynamically typed. + +\section{Separate Permissions for Storing Capabilities and Data} + +CHERI has separate permission bits for storing a capability versus storing +non-capability data (and similarly, for loading a capability versus loading +non-capability data). + +(An alternative design would be just one Permit\_Load and just one +Permit\_Store permission that were used for both capabilities and non-capability data.) + +The advantage of separate permission bits for capabilities is that +that there can be two protected subsystems that communicate via a memory +buffer to which they have Permit\_Load and Permit\_Store permissions, but +do not have Permit\_Load\_Capability or Permit\_Store\_Capability. Such +communicating subsystems cannot pass capabilities via the shared buffer, even +if they collude. (We realized that this was potentially a requirement when +trying to formally model the security guarantees provided by CHERI.) + +\section{Capabilities Contain a Cursor} + +In the C language, pointers can be both incremented and decremented. +C pointers are sometimes used as a cursor that points to the current working +element of an array, and is moved up and down as the computation progresses. + +CHERI capabilities include an offset field, which gives the difference between +the base of the capability and the memory address that is currently of +interest. The offset can be both incremented and decremented without changing +\cbase{}, so that it can be used to implement C pointers. + +In the ANSI C standard, the behavior is undefined if a pointer is incremented +more than {\it one} beyond the end of the object to which it points. However, we have found +that many existing C programs rely on being able to increment a pointer beyond +the end of an array, decrement it back within range, and then deference it. +In particular, network packet processing software often does this. +In order to support programs that do this, CHERI offsets are allowed to take +on any value.% +% +\footnote{CHERI Concentrate (\cref{subsec:cheri-concentrate}) exploits the +observation that, in practice, pointers do not wander ``far'' from their base +to reduce the number of bits used to store the base, cursor, and limit +addresses. Attempts to move the cursor far out of bounds will, instead, yield +an un-tagged result.} +% +A range check is performed when the capability is +dereferenced, so buffer overflows are prevented; thus, the offset can take +on intermediate out-of-range values as long as it is not dereferenced. + +An alternative architecture would have not included an offset within the +capability. This could have been supported by two different capability types +in C, one that could not be decremented (but was represented by just a +capability) and one that supported decrementing (but was represented by a pair of +a capability and a separate integer for the offset). Programming languages +that did not have pointer arithmetic could have their pointers compiled as +just a capability. + +The disadvantage of including offsets within capabilities is that it wastes +64 bits in each capability in cases where offsets are not needed (e.g., +when compiling languages that don't have pointer arithmetic, or when +compiling C pointers that are statically known to never be decremented). + +The alternative (no offset) architecture could have used those 64 bits +of the capability for other purposes, and stored an extra offset outside +the capability when it was known to be needed. The disadvantage of the +no-offset architecture is that C pointers become either unable to support +decrementing or enlarging: because capabilities need to be aligned, a pair of a +capability and an integer will usually end up +being padded to the size of two capabilities, doubling the size of a C pointer, +and this is a serious performance consideration. + +Another disadvantage of the no-offset alternative is that it makes the +seal/unseal mechanism considerably more complicated and hard to explain. +A program that has a capability for a range of types has to somehow select +which type within its permitted range of types it wishes to use when sealing a +particular data capability. The CHERI architecture uses the offset for this +purpose; not having an offset field leads to more complex encodings when +creating sealed capabilities. + +By comparison, the CCured language includes both \ccode{FSEQ} and +\ccode{SEQ} pointers. CHERI capabilities are analogous to CCured's +\ccode{SEQ} pointers. The alternative (no offset) architecture +would have capabilities that acted like CCured's FSEQ, and used an extra +offset when implementing SEQ semantics. + +\section{NULL Does Not Have the Tag Bit Set} + +In some programming languages, pointer variables must always point to +a valid object. In C, pointers can either point to an object or be NULL; +by convention, NULL is the integer value zero cast to a pointer type. + +If hardware capabilities are used to implement a language that has NULL +pointers, how is the NULL pointer represented? CHERI capabilities have +a \ctag{} bit; if the \ctag{} bit is set, a valid capability follows, otherwise +the remaining data can be interpreted as (for example) bytes or integers. +The representation we have chosen for NULL is that the \ctag{} bit is not set +and the \cbase{} and \clength{} fields are zero; effectively, NULL is the +integer zero stored as a non-capability value in a capability register. + +An alternative representation we have could have chosen for NULL would +have been with the \ctag{} bit set, and zero in the \cbase{} field and +\clength{} fields. Effectively, NULL would have been a capability for +an array of length zero. + +Many CHERI instructions are agnostic as to which of these two +conventions for NULL is employed, but the \insnref{CFromPtr}, +\insnref{CToPtr} and \insnref{CPtrCmp} operations are aware of the +convention. + +The advantages of NULL's \ctag{} bit being unset are: + +\begin{itemize} +\item +Initializing a region of memory by writing zero bytes to it will initialize +all capability variables within the region to the NULL capability. Initializing +memory by writing zeros is, for example, done by the C \ccode{calloc()} +function, and by some operating systems. +\item +It is possible for code to conditionally branch on a capability being NULL by +using the \insnref{CBTS} or \insnref{CBTU} instruction. +\end{itemize} + +\section{The length of NULL is MAXINT} + +Given that we have chosen NULL to have its tag bit unset, it isn't semantically +meaningful to talk about its length, as NULL is not a reference to a region +of memory. But programs can still attempt to query the length of NULL, and +the questions arises as to which value is returned. + +We have chosen the length of NULL to be $2^{64}-1$, as this simplifies the +implementation of compressed capabilities. To support the semantics of the +C language, the capability compression scheme must be able to represent +all $2^{64}$ possible values of \coffset{} when \ctag{} is set and \clength{} +is MAXINT. If we make the length of NULL be MAXINT, the compressed capability +format can use the same encoding regardless of whether \ctag{} is set or +not: NULL becomes a value whose \coffset{} is currently zero, but that can +be changed (with \insnref{CIncOffset}) to any integer value without +becoming unrepresentable. + +Alternative design choices included: + +\begin{itemize} +\item +Use a capability compression algorithm that also has the property that all +values of \coffset{} are representable when \clength{} is zero, and make +the length of NULL be zero. Versions of the CHERI ISA prior to V7 allowed the +length of NULL to be implementation-defined, and used a compression algorithm +that had this property, so the length of NULL could be zero. To enable the +use of compression algorithms that don't have this property, the V7 ISA +defines the length of NULL to be MAXINT. +\item +Use a different compression algorithm depending on whether \ctag{} is set +or not. This might make the hardware more complex, but there is no reason in +principle why valid capabilities (\ctag{} set) and integers packed into +capability registers (\ctag{} unset) should have to use the same compression +algorithm. +\end{itemize} + +\section{Permission Bits Determine the Type of a Capability} + +In CHERI, a capability's permission bits together with the \cotype{} field +determine what kind of capability it is. A capability for a region of memory +has is unsealed (a \cotype{} of $2^{64}-1$) and \emph{Permit\_Load} and/or \emph{Permit\_Store} set; +a capability for an object is sealed and has \emph{Permit\_Execute} +unset; a capability to call a protected subsystem (a ``call gate'') is +sealed and has \emph{Permit\_Execute} set; a capability that allows +the owner to create objects whose type identifier (\cotype{}) falls within +a range is unsealed and \emph{Permit\_Seal} set. + +An alternative architecture would have included a separate +\emph{capability type} field, as well as the \cperms{} field, within each +capability; the meaning of the rest of the bits in the capability would have +been dependent on the value of the \emph{capability type} field. + +A potential disadvantage of not having a \emph{capability type} field is that +different kinds of capability cannot use the remaining bits of the capability +in different ways. + +A consequence of the architecture we have chosen is that it is possible for +software receiving the primordial, omnipotent capability to create capabilities +with arbitrary permissions. Some of these sets of permissions do not have a +clear use case; they just exist as a consequence of the representation chosen +for capabilities' permissions. (Other choices are possible; see +\cref{app:exp:compressperm} for a less-orthogonal representation.) + +\mrnote{TO DO: Explain that capabilities with the Permit\_Seal capability +are really a different type of capability from memory capabilities, and +could in principle have used a different encoding to save bits. We don't +have a use case for a capability with both Permit\_Seal and read/write +permissions. If they were different types, you would need some mechanism to +obtain the initial sealing capability.} + +\section{Object Types Are Not Addresses} + +In CHERI, we make a distinction between the unique identifier for an +object type (the \cotype{} field) and the address of the executable code +that implements a method on the type (the \cbase{} $+$ \coffset{} fields +in a sealed executable capability). + +An alternative architecture would have been to use the same fields for +both, and take the entry address of an object's methods as a convenient +unique identifier for the type itself. + +The architecture we have chosen is conceptually simpler and easier to +explain. It has the disadvantage that the type field is only 24 bits, +as there is insufficient space inside the capability for more. + +The alternative of treating the set of object type identifiers as being the +same as the set of memory addresses enables the saving of some bits within +a capability by using the same field for both. +It also simplifies +assigning type identifiers to protected subsystems: each subsystem can +use its start address as the unique identifier for the type it implements. +Subsystems that need to implement multiple types, or create new types +dynamically can be given a capability with the permission +\emph{Permit\_Set\_Type} set for a +range of memory addresses, and they are then able to use types within that +range. (The current CHERI ISA does not include the +\emph{Permit\_Set\_Type} permission; +it would be needed only for this alternative approach). This avoids the need +for some sort of privileged type manager that +creates new type identifiers; such a type manager is potentially a source +of covert channels. (Suppose that the type manager and allocated +type identifiers in numerically ascending order. A subsystem that asks the +type manager twice for a new type id and gets back $n$ and $n+1$ knows that no +other subsystem has asked for a new type id in between the two calls; this +could in principle be used for covert communication between two subsystems +that were supposed to be kept isolated by the capability mechanism.) + +\section{Unseal is an Explicit Operation} + +In CHERI, it would require an explicit operation to +convert an undereferenceable pointer to an object into a pointer that +allows the object's contents to be inspected or modified directly. +This can be done directly with the \insnref{CUnseal} operation, +or by using \insnref{CInvoke} to run the result of unsealing the first +argument on the result of unsealing the second argument. + +An alternative architecture would have been one with ``implicit'' unsealing, +where a sealed capability could be dereferenced without +explicitly unsealing it first, provided that the subsystem attempting the +dereference had some kind of ambient authority that permitted it to deference +sealed capabilities of that type. This ambient authority could have taken +the form of a protection ring or the \cotype{} field of \PCC{}. + +A disadvantage of an implicit unseal approach such as the one outlined above +is that it is potentially vulnerable to the ``confused deputy'' +problem~\cite{Hardy1988}: the attacker calls a protected subsystem, passing +a sealed capability in a parameter that the called subsystem expects to be +unsealed. If unsealing is implicit, the protected subsystem can be tricked +by the attacker into using its privileges to read or write to memory to +which the attacker does not have access. + +The disadvantage of the architecture we have chosen is that protected subsystems +need to be careful not to leak capabilities that they have unsealed, for example +by leaving them on the stack when they return to their caller. In an +architecture with ``implicit unseal'', protected subsystems would just need +to delete their ambient authority for the type before returning, and would +not need to explicitly clean up all the unsealed capabilities that they +had created. + +\section{CMove is not Implemented as CIncOffset} + +\insnref{CMove} is an independent instruction to move a capability value +from one register to another. +In conventional instruction-set design, integer \insnnoref{Move} is +frequently an assembler pseudo-operation that expands to an arithmetic +operation that does not modify the value (e.g., an add instruction with the +zero register as one operand). +In an earlier CHERI design, we similarly implemented \insnref{CMove} is an +assembler pseudo-operation that expanded to \insnref{CIncOffset} with an +offset of zero. +This required that the \insnref{CIncOffset} instruction treat a zero +offset as a special case, allowing it to be used to move sealed capabilities +and values with the tag bit unset. +Using a separate opcode for \insnref{CMove} has the disadvantage of +consuming another opcode, but avoids this special case in the definition of +\insnref{CIncOffset} in which an exception will not be thrown if a zero +operand is used. +We have therefore changed to specifying an explicit \insnref{CMove} +instruction, and removed special casing in \insnref{CIncOffset}. + +\section{Instruction-Set Randomization} + +CHERI does not include features for instruction set +randomization~\cite{Keromytis2003}; +the unforgeability of capabilities in CHERI can be used as an alternative +method of providing control flow integrity. + +However, instruction set randomization would be easy to add, as long as +there are enough spare bits available inside a capability (the 128 bit +representation of capabilities does not have many spare bits). Code +capabilities could contain a key to be used for instruction set +randomization, and capability branches such as \insnref{CJR} could +change the current ISR key to the value given in the capability that is +branched to. + +\section{System Privilege Permission} + +In the current version of the CHERI, one of the capability permission bits +authorizes access to privileged processor features that would allow +bypass of the capability model, if present on \PCC{}. +This is intended to be used by hybrid operating-system kernels to manage +virtual address spaces, exception handling, interrupts, and other necessary +architectural features that do not map cleanly into memory-oriented +capabilities. +It can also be used by stand-alone CHERI-based microkernels to control use +of the exception-handling and cache-management mechanisms, and of the MMU on +MMU-enabled hardware. +Although the permission limits use of features to control the virtual address +space (e.g., TLB manipulation), it does not prevent access to kernel-only +portions of the virtual address space. +This allows kernel code to operate without privileged permission using the +capability mechanism to limit which portions of kernel address space are +available for use in constrained compartments. + +We employ a single permission bit to conserve space (especially in 128-bit +capabilities), but also because it offers a coherent view on architectural +privilege: many of the privileged architectural instructions allow bypass of +in-address-space memory protection in different ways, and using subsets of +those operations safely would be quite difficult. +In earlier versions of the CHERI ISA, we employed multiple privileged bits, +but did not find the differentiation useful in practical software design. +In more feature-rich privileged instruction sets (e.g., those with +virtualization features), a more fine-grained decomposition might be of +greater utility, and could motivate a new capability format intended to +authorize use of privilege. + +In earlier versions, the privileged permission(s) controlled use of only CP2 +privilege (i.e., exception-handling capabilities); in the current version, the +bit also controls MIPS privileges available only in kernel mode: TLB, CP0, +selected uses of the \insnnoref{CACHE} instruction, and +\insnnoref{ERET} use. +This allows compartmentalization within the kernel address space (e.g., to +sandbox untrustworthy components), as well as more general mitigation by +limiting use of privileged features to only selected code components, jumped +to via code pointers carrying the privileged permission. +If virtual-memory and exception-handling features were not controlled by this +permission bit, use of those ISA features would allow bypass of in-kernel +compartmentalization. +Regardless of this bit, extreme care is required to safely compartmentalize +within an operating-system kernel. + +In our design, absence of the privileged permission denies use of privileged +ISA features, but presence does not grant that right unless it is also +authorized by kernel mode. +Other compositions of the capability permission bit and existing MIPS KSU +(kernel/supervisor/user-mode) authorization are imaginable. +For example, the permission bit could grant privileged ISA use in userspace +regardless of KSU state. +While this composition might allow potentially interesting delegation of +privilege to user components, the lack of granularity of control appears to +offer little benefit when a similar effective delegation can be implemented +via the exception model and implied ring transition. +In a ring-free design (e.g., one without an MMU or kernel/supervisor/user +modes), however, the privileged permission would be the sole means of +authorizing privilege. + +Another design choice is that we have not extended MIPS with new +capability-based privilege instructions; instead, we chose to limit use of +existing instructions (such as those used in TLB management). +This fails to extend the principle of intentional use to these privileged +features; in return we achieve reduced disruption to current software +stacks, and avoid introducing new instructions in the opcode space. +Despite that slight apparent shortcoming, +we observe that fine-grained privilege can still be accomplished -- +due to use of a permission bit +%%%% NO buts, please +on \PCC{}: even within a highly privileged +kernel, most functions might operate without the ability to employ privileged +instructions, with an explicit use of \insnref{CJALR} to jump to a code +pointer with the Access\_System\_Registers permission enabled -- which +executes +only the necessary instructions and reduces the window of opportunity for +privilege misuse. + +An alternative design would extend the MIPS privileged instruction set to +include versions that accept explicit capability operands authorizing use of +those instructions, in a manner similar to our extensions to our +capability-extended load and store instructions. +Another variation on this scheme would authorize setting of a privilege status +register, enabling specific instructions (or classes of instructions) based on +an offered capability, combining these two approaches to authorize selected +(but unmodified) privileged instructions. + +Finally, it is conceivable that capabilities could be used to authorize +delegation of the right to use privileged instructions to userspace code, +rather than simply restricting the right to use privileged instructions in +kernel code. +We have opted to limit our approach to using capabilities to restrict features +in the MIPS model, with a simple and deterministic composition of features. + +\section{Composing CHERI with MIPS Exception Handling} + +Exception handling is inevitably architecture specific, with the approach +taken in MIPS being particularly RISC-esque and quirky. +In MIPS, an exception interrupts the instruction flow, sets the \EXL{} status +flag to transition to kernel mode, disable interrupts, updates the +exception cause register to provide information about the exception, saves the +current \PC{} in \EPC{}, and sets \PC{} to the appropriate interrupt vector +address. +Later versions of MIPS allow that address to be configured. +Special handling is also provided if an exception fires while \EXL{} is set, +making use of \ErrorEPC{} instead of \EPC{}. +As only one register is saved by the architecture (\PC{}), this makes it +difficult to perform a software-based context switch. +Other more recent RISC architectures will bank a second register, typically +the stack pointer, to allow that to take place. +In MIPS, the ABI instead reserves two general-purpose integer registers, \regname{k0} +and \regname{k1}, for use by exception handlers. + +\subsection{MIPS-centric Exception Handling} + +A primary goal of our work is to avoid disrupting MIPS exception handling. +This has two implications: first, that when a capability-unaware OS is booted +and operating, it should work as it did previously; and second, that when a +capability-aware OS is used, CHERI extensions to exception handling preserve +the existing structure and approach of exception handling. + +\subsection{Capability Extensions to MIPS Special Registers} + +The most natural extension to MIPS exception handling simply extends the +existing \EPC{} to be an Exception Program Counter Capability (\EPCC{}), and +\ErrorEPC{} to be an Error Exception Program Counter Capability +(\ErrorEPCC{}), which can save and restore the full \PCC{} rather than just +\PC{}. +However, this is insufficient to authorize or safely protect execution of the +exception vector, which the interrupted code may not have access to, and +should not be able to influence. +As with later MIPS versions, we therefore allow the exception vector to be +defined using a special capability register, the Kernel Code Capability +(\KCC{}), which will be installed in \PCC{} when the exception is taken, both +authorizing access for the exception handler, and preventing the interrupted +code from improperly affecting the exception handler. +In the interests of a more object-centered design, in which capabilities for +code and data are not unnecessarily, we also provide a special capability +register, the Kernel Data Capability (\KDC{}), which is readable in kernel +mode. + +\subsection{Kernel-Reserved Special Capability Registers} + +MIPS reserves two general-purpose integer registers for exception-handler +bootstrapping, \regname{k0} and \regname{k1}. +In earlier versions of the CHERI ISA, we similarly reserved two +general-purpose capability registers, \KRC{} and \KQC{}, for kernel use. +We have since shifted these to the Special Capability Register File, accessed +via \insnref{CReadHwr} and \insnref{CWriteHwr}. +We anticipate that they will be used to temporarily save general-purpose +capability registers in a similar manner, letting the general-purpose +registers be used by the exception handler itself -- e.g., to hold a copy of +\KDC{} for the purposes of memory access to save capability registers for the +preempted context. +This design choice is especially important when contemplating a +merged register file, in which case avoiding further reservations in that file +would limit ABI disruption. +Avoiding special interpretations of general-purpose capability registers also +avoids special access-control rules (e.g., to limit access to those +registers), simplifying the ISAs. +Finally: these registers are used only very infrequently, and as such take up +valuable space that could be available to the compiler, meaning that using up +encoding and register-file space is a poorer use of micro-architectural +resources. + +\section{CInvoke: Jump-Based Domain Transition} +\label{sec:jump-based-domain-transition} + +Earlier versions of the CHERI-MIPS ISA included an exception-based +mechanism for domain transition via a pair of \insnnoref{CCall} +and \insnnoref{CReturn} instructions. The use of exceptions +introduced both runtime overhead and implementation complexity in the +kernel. We have replaced this mechanism with \insnref{CInvoke} +which provides jump-like semantics. +Non-monotonicity is accomplished by virtue of unsealing the sealed +operand capabilities to \insnref{CInvoke}. +%In both cases, destination code is controlled by the trusted computing base. +% What does this mean? CCalls1 jumps into an arbitrary sealed domain. +% Will it always be controlled by the trusted computing base? +% Maybe we're saying that it often is? Anyway, commented out for now. + +While a standard MIPS pipeline allows a branch delay slot before diverting +control flow after a branch, \insnref{CInvoke} does not have +a branch-delay slot -- +as the remaining branch-delay instruction in the calling domain would +otherwise +have access to data registers written by the branch. +Removing the delay slot for this case disturbs the +normal control flow of the pipeline, causing a pipeline bubble in our case, +and also prevents an important optimization for safe +domain crossing -- which uses the delay slot to clear the last registers in the +calling domain that were needed as operands for the \insnref{CInvoke} +itself. +Nevertheless, significant software complexity was necessary to ensure a safe +branch-delay slot for \insnref{CInvoke}. +Rather than removing the delay slot after \insnref{CInvoke}, we +could have thrown an exception on any instruction that reads or writes \IDC{} +in the branch-delay slot. +The result would be that the newly unsealed \IDC{} is available only to code +executing at +the newly unsealed \PCC{}, avoiding premature exposure of \IDC{} to the caller +before callee code begins executing. +However an exception in the branch delay slot would still expose \IDC{} to the +exception handler, and a creative use of signals could expose \IDC{} to the +calling domain. +Rather than mandate a more complex set of invariants in software, we chose +to eliminate the branch delay slot of \insnref{CInvoke}. + +It is possible to imagine more comprehensive jump-based instructions +including: +\begin{itemize} +\item A variation that has link-register semantics, saving the caller \PCC{} + in a manner similar to \insnref{CJALR}. + We choose not to implement this to avoid writing two general-purpose registers + in one instruction, and because the + caller can itself perform a move to a link destination based on + \insnref{CGetPCC}. + +\item A variation that seals caller \PCC{} and \IDC{} to construct a + return-capability pair. + We choose not to implement this to multiple register writes in one instruction, + because the + caller can itself perform any necessary sealing of its own return state, if + required. + Further, to provide strict call-return semantics, additional more complex + behavior is required, which is not well captured by a single RISC + instruction. +\end{itemize} + +In general, we anticipate that \insnref{CInvoke} will be used +to invoke trusted software routines. For situations involving +mutual distrust, \insnref{CInvoke} can be used to invoke +a trusted supervisor responsible for mediating messages and +requests between distrusting parties. The supervisor would be +responsible for clearing non-argument capability and general-purpose +integer resgisters and performing any additional checks. +The \insnref{CInvoke} trusted +routine can jump out of trusted code without +any special handling in the ISA, as it will conform to monotonic +semantics -- i.e., the clearing of registers that should not be passed to the +callee, followed by a \insnref{CJR} to transfer control to the callee. + +\section{Compressed Capabilities} +\label{sec:rational:comressed} +In prior CHERI ISA versions, we specified a 256-bit capability +representation able to fully represent byte-granularity protection. +This allowed arbitrary subsets of the address space to be described, as well as +providing substantial +space for object types, software-defined permissions, and so on. +However, they come at a significant performance overhead: the size of 64-bit +pointers is quadrupled, increasing cache footprint and utilization of memory +bandwidth. +Fat-pointer compression techniques exploit information redundancy between the +base, pointer, and bounds to reduce the in-memory footprint of fat pointers, +reducing the precision of bounds -- with substantial space savings. +We now specify only compressed capabilities, whether 64-bit capabilities for +32-bit architectural addresses, or 128-bit capabilities for 64-bit +achitectural addresses. +Prior versions of our compression approaches, the CHERI-128 candidates, are +described in \cref{app:cheri-128}. + +\subsection{Semantic Goals for Compressed Capabilities} + +Our target for compressed capabilities was 128 bits: the next natural +power-of-two pointer size above 64-bit pointers, with an expected one-third of +the overhead of the full 256-bit scheme. +A key design goal was to allow both 128-bit and 256-bit capabilities to be +used with the same instruction set, permitting us to maintain and evaluate +both approaches side-by-side. +To this end, and in keeping with previously published schemes, the CHERI ISA +continues to access fields such as permissions, pointer, base, and bounds via +64-bit general-purpose integer registers. +The only visible semantic changes between 256-bit and 128-bit operation should +be these: +the in-memory footprint when a capability register is loaded or stored, +the density of tags (doubled when the size of a capability is halved), +potential imprecision effects when adjusting bounds, potential loss of tag if +a pointer goes (substantially) out of bounds, a reduced number of permission +bits, a reduced object type space, and (should software inspect it) a change +in the in-memory format. + +The scheme described in our specification is the result of substantial +iteration through designs attempting to find a set of semantics that support +both off-the-shelf C-language use, as well as providing strong protection. +Existing pointer-compression schemes generally provided suitable monotonicity +(pointer manipulation cannot lead to an expansion of bounds) and a completely +accurate underlying pointer, allowing base and bounds to experience +imprecision only during bounds adjustment. +However, they did not, for example, allow pointers to go ``out of bounds'' -- +a key C-language compatibility requirement identified in our analysis of +widely used C programs. +The described model is based on a floating-point representation of distances +between the pointer and base/bounds, and places a particular focus on fully +precise representation bounds for small memory allocations % ($<\frac{3}{4}MiB$) +-- e.g., as occur on the stack, or when performing string or image processing. + +\subsection{Precision Effects for Compressed Capabilities} + +Precision effects are primarily visible during the narrowing of bounds on an +existing capability. +In order to provide the implementation with maximum flexibility in selecting a +compression strategy for a particular set of bounds, we have removed the +\insnnoref{CIncBase} and \insnnoref{CSetLen} instructions in favor of +a single \insnref{CSetBounds} instruction that exposes adjustments to +both atomically. +This allows the implementation to select the best possible parameters with +full information about the required bounds, maximizing precision. +Precision effects occur in the form of increased alignment requirements for +base and bounds: if requested bounds are highly unaligned, then the resulting +capability returned by \insnref{CSetBounds} may have broader rights than +requested, following stronger alignment rules. +\insnref{CSetBounds} maintains full monotonicity; however, bounds on a +returned capability will never be broader than those of the capability passed in. +Further, narrowing bounds is itself monotonic: as allocations become smaller, +the potential for precision increases due to the narrower range described. +Precision effects will generally be visible in two software circumstances: +memory allocation and arbitrary subsetting, which have different +requirements. + +Memory allocation subdivides larger chunks of memory into smaller ones, which +are then delegated to consumers -- which most frequently are heap and stack +allocation, but this +can also occur when the operating system inserts new memory +mappings into an address space, returning a pointer (now a capability) to that +memory. +Memory allocators already impose alignment requirements: certainly for word or +pointer alignment so that allocated data structures can be stored at natural +alignment, but also (for larger allocations) for page or superpage alignment to +encourage effective use of virtual memory. +Compressed capabilities strengthen these alignment requirements for large +allocations, which requires modest changes to heap, stack, and OS memory +allocators in order to avoid exposing undesired precision effects. +Bounds on memory allocations will be set using \insnref{CSetBoundsExact}, +which will throw an exception if precise bounds are not possible due to +precision effects. + +Arbitrary subsetting occurs when programmers explicitly request that a +capability to an existing allocation be narrowed, in order to enforce bounds +checks linked to software invariants. +For example, an MPEG decoder might subset a larger memory buffer containing +many frames into individual frames when processing them, in order to catch +misbehavior without permitting (for example) corruption of adjacent frames. +Similarly, packet-processing systems frequently embed packet data within other +data structures; bugs in protocol parsing or packet construction could affect +packet metadata, with security consequences. +128-bit CHERI can provide precise subsetting for smaller subsets, % ($<1MiB$), +but may experience precision effects for larger subsets. +These are accepted in our programmer model, and could permit buffer overflows +between subsets, which would be prevented in the 256-bit model. +Unless specifically annotated to require full precision, arbitrary subsetting +will utilize \insnref{CSetBounds}, which can return monotonically +non-increasing -- but with potentially imprecise bounds. + +Two further cases required careful consideration: object capabilities, and the +default data capability, for quite different reasons. +Object capabilities require additional capability fields (software-defined +permission bits, and the fairly wide object type field). +The default data capability is an ordinary 128-bit capability, but has the +property that use of a full cursor (base plus offset) introduces a further +arithmetic addition in a critical path of MIPS loads and stores. +In both cases, we have turned to reduced precision (i.e., increased alignment +requirements) to eliminate these problems, looking to minimum page-granularity +alignment of bounds while retaining fully precise pointers. +By requiring strong alignment for default data capabilities, the extra +addition becomes a \texttt{logical or} when constructing the final virtual address, +assisting with the critical path. +As object capabilities are used only by newly implemented software, and +provide coarser-grained protection, we accepted the stronger alignment +requirement for sealed capabilities, and have not encountered significant +problems as a result. + +The final way in which imprecision may be visible to software is if the +pointer (offset) in a capability goes substantially out of bounds. +In this case, the compression scheme may not be able to represent the +distances from the pointer to its original bounds accurately. +In this scenario, the tag will be cleared on the capability to prevent +dereference, and then one of the resulting pointer value or bounds must be +cleared due to the unrepresentability of the resulting value. +To discourage this from happening in the more common software case of allowing +small divergence from the bounds, \insnref{CSetBounds} over-provisions +bits required to represent the distances during compression; however, that +over-provisioning comes at a slight cost to precision: i.e., we accept slightly +stronger alignment requirements in return for the ability to allow pointers to +be somewhat out of bounds. + +\subsection{The Value of Architectural Minimum Precision} +\label{sec:the-value-of-architectural-minimum-precision} + +The \insnref{CRepresentableAlignmentMask} and +\insnref{CRoundRepresentableLength} instructions avoid encoding the details of +the capability compression scheme into programs. +This is in turn allows different microarchitectures to choose different +tradeoffs in the precision of compressed capabilities. +With no constraints on implementations, this may lead to unnecessary work +when performing operations like loading programs into memory. +For example, if linkers allow the generation of static binary load addresses +which are insufficiently aligned to be representable, then program loaders +must potentially pad the beginning of the mapped region, and enter a loop +that adjusts the base and length of the region until they match. +This could be avoided if an architectural minimum precision as specified so +that an OS ABI could forbid under-aligned load addresses and thus +image activators could simply refuse to load such programs rather than having +to handle every edge case. +Microarchitectures could still implement more precision if they choose and +that should be handled by \insnref{CRepresentableAlignmentMask} and +\insnref{CRoundRepresentableLength}. + +\section{Capability Encoding Mode} +\label{section:capability-encoding-mode} + +As implemented in CHERI-MIPS, CHERI duplicates the full load-store encoding +space to provide capability-relative variations on load and store +instructions. +This approach ensures intentionality: the architecture is always able to +perform a \DDC{}-relative access with legacy integer-relative load and store +instructions, and is always able to assert that the tag bit is set for +capability-relative load and store instructions. +However, this makes heavy use of remaining unused opcode space in many +instruction sets, and so finding alternative encoding models to make less +copious use of opcode space is desirable. + +One scheme we are deploying in CHERI-RISC-V is the use of legacy vs. +capability encoding modes: in the legacy encoding mode, load and store opcodes +have their current interpretations, and a small selection of +capability-relative loads and stores are added. +To get access to the full range of load and store variations, the encoding +mode can be switched to one in which existing load and store opcodes are +instead interpreted as requiring capability operands, and \DDC{}-relative +integer-based access is disabled. + +There are a variety of mechanisms that could be used to switch between +encoding modes, but information on the mode must be available at the time +of instruction decode. +There are several essential considerations: + +\begin{description} +\item[How frequently will mode switches take place?] + There are a range of possibilities, from whole programs or systems operating + within a single encoding, to inter-function or sub-function changes in mode + depending on ABI and optimization requirements. + Given our overall goal in CHERI of avoiding the need for additional + exceptions to a privileged supervisor for capability manipulation, we + similarly believe that a non-exception-based encoding transition mechanism + is desirable to support more tight integrations of integer-relative and + capability-relative generated code. + As such, the mechanisms we consider will generally support granular + transition, at least at library boundaries or individual function call and + return. + +\item[How will encoding mode be selected and preserved across function calls?] + Assuming that a more granular approach to encoding is desired -- e.g., that + there are direct calls between code generated in differing modes -- then it + will be necessary to switch to the callee encoding during function entry, + and restore the caller encoding on function return. + This might be supported implicitly through contextual information, such as + using page-table properties, or explicitly such as through extended or + entirely new compiler- or linker-managed instructions saving and setting + encoding modes. + +\item[How will encoding mode be preserved across context switches?] + As with function-call boundaries, this might be implicit (e.g., based on the + address or metadata held in \PCC{}, or via page-table metadata for the + target that \PCC{} points to) or explicit + (e.g., the saving and restoring of a bit in \xccsr{} when an exception is taken). + +\item[What will the performance implications be for microarchitectural + optimizations?] + For example, will the target encoding be accurately predicted alongside the + target \PCC{,} so that speculative execution can utilize the correct + encoding? + +\item[How should encoding-mode selection work around protection-domain + boundary crossings?] + When control is transferred across a protection-domain boundary (e.g., + by virtue of an exception being thrown, or use of \insnref{CInvoke}), the + destination code must be able to ensure that it is being safely executed + with its intended interpretation. + This might be implied by the mechanism (e.g., by virtue of properties of the + virtual page holding the executing code) or explicit (e.g., using + dedicated instructions in the callee to switch modes, or assert the mode, + before any affected instructions are executed). + +\item[Should encoding-mode switches require privilege?] + One potential fear is that an additional encoding mode increases the gadget + space available to control-flow attackers. + As long as the effect is only for the current execution context, + we currently take the view that changing encoding modes + does not require privilege: the set of available capabilities remains the + same; the increase in gadget space is small; and attacks on control flow to + use gadgets rely on having bypassed control-flow robustness arising from + fine-grained code capabilities. + See Section~\ref{section-capability-encoding-mode-unprivileged} for further + considerations. +\end{description} + +\subsubsection{Potential encoding mode-switch mechanisms} + +We are considering the following mechanisms: +\rwnote{Must add notes on the safety concern to each of these.} + +\begin{description} +\item[New jump instruction sets mode flag in \xccsr{}] + An architecture mode bit, held in \xccsr{}, would select between the two + different instruction encodings. + A new jump instruction would allow the target mode to be selected via an + immediate operand (``enter integer encoding mode'' or ``enter capability + encoding mode''). + This is a simple mechanism allowing dynamic selection of encoding at a fine + granularity -- e.g., per function. It utilizes existing context + switching, as \xccsr{} will already be saved and restored. + + This approach has a number of complications from a software perspective: + on function call, the caller must be aware of the callee encoding; on + function return, the callee must likewise be aware of the caller encoding, + so as to ensure that the correct encoding is used when control flow moves + between functions. + In some usage scenarios, such as dynamically linked libraries, this might + require the introduction of thin stubs -- already present thanks to PLTs + during call, but not presently implemented in current software stacks. + Certain more complex control flows, such as those relating to exception + delivery, might similarly present obstacles. + +\item[Flag in jump-target addresses, maintained in \xccsr{}] + Because of a minimum code alignment of 16 bits in RISC-V, the lowest bit in + a jump target address is ignored (and cleared when installed in \PC{}), + leaving it available as a potential flag to instructions such as + \insnnoref{JALR} and \insnref{CJALR}\footnote{The \insnnoref{JAL} instruction shifts its immediate + operand, and could not be used to change mode.}. + This bit could be used to select the target ISA encoding, in the style of + ARMv7's instruction-set trigger to switch between 32-bit instructions and + 16-bit Thumb instructions. + \xccsr{} would contain an architectural mode bit to select between the two + instruction codings. + A lowest bit of 0 in the target virtual address would select integer + encoding mode; a + lowest bit of 1 in the target virtual address would select capability + encoding mode. + JALR and CJALR would similarly adjust the virtual address of a generated + return address or capability, so as to restore the correct encoding on + function return or exception delivery. + This approach would avoid the need for any new instructions being + introduced, and would associate the encoding with the callee rather than + caller. + Branch-predictor targets could also reliably predict encoding to allow + speculative fetch and decode. + + Software would be relatively easily modified to set the bit as needed + during compile-time or run-time linking. + However, there may already be software consumers making use of the same + bit. + +\item[Flag in jump-target addresses, maintained in \PCC{}] + As with the prior option, the lowest bit in the target virtual address for + JALR or CJALR would select the target encoding. + However, rather than extending \xccsr{}, the lowest bit would persist in + \PCC{} and be ignored as an address for fetching instructions, allowing it + to continue to indicate the target encoding. + This would require a modest change to the baseline RISC-V ISA to preserve + but ignore the bit in \PC{}. + This approach avoids the need for a new \xccsr{} bit, and differently + addresses the goal of allowing encoding to track executing code, and be + saved, set, and restored around function calls and returns. + + As the bit would not be cleared, debuggers and other address-aware code, + such as code implementing PC-relative GOT access in hybrid mode, would have + to be suitably adapted to ignore the bit. + It might be desirable to have the bit also ignored for the purposes of + \insnnoref{AUIPC} used for GOT access. + +\item[New capability flag to select the target encoding of a jump] + A new capability flag could be introduced to select the target encoding for + capability-relative jump targets (i.e., capabilities authorizing instruction + fetch). + Changing the flag would not change the rights associated with a capability, + allowing us to avoid a new permission bit to authorize changing the flag, + and sealing would prevent modification. + Target encodings could be saved with corresponding branch-predictor entries + to allow speculative fetch and decode. + The encoding state would be preserved with \PCC{} on call, return, and in + exception handling. + +\item[Explicit unprivileged instruction to switch modes] + New instructions could be added to switch explicitly between the two opcode + instructions, to be placed either in function prologues/epilogues, or in + trampolines inserted by static or dynamic linkage. + Standard RISC-V \insnnoref{RWI}, \insnnoref{RSI}, and \insnnoref{RCI} + CSR manipulation instructions could be used. + Dynamic changes of encoding might necessitate invalidating speculative + decoding and execution, however. + +\item[Page-table flag specifying encoding for executable code] + On MMU-enabled systems, page-table mappings for pages could themselves + contain information on the encoding of instructions stored in the page. + As binary pages are typically mapped by a run-time linker that is aware of + code properties, this would avoid changes to code generation itself, use of + new instructions, flags, etc. + However, this would be dependent on having an MMU present, software authors + using the MMU, as well as code having page alignment by encoding type. + When running without virtual addressing enabled, it would not be possible to + switch modes, which would be undesirable for small embedded-class systems. +\end{description} + +%Of these potential schemes, requesting a target encoding based on address +%lower bits, and using \xccsr{} to hold the current encoding state, seems the +%most appealing, as it minimizes disruption to the ISA, and allows +%encoding-mode switches to be directed by the compile-time or run-time linker, +%which will already be aware of code requirements. +%If sub-function control of encoding is required, then direct manipulation of +%the \xccsr{} bits would also be possible. + +Of these potential schemes, requesting a target encoding based on a PCC flag +seems the most appealing. + +\pdrnote{We changed the concluding paragraph to match the conclusion we made +but may need to justify why the advantages of this approach won out.} + +\section{Capability Encoding Mode Switching Can Be Unprivileged} +\label{section-capability-encoding-mode-unprivileged} + +In CHERI-RISC-V, we introduce the concept that existing integer-relative load +and store opcodes could be reused in a richer ``capability encoding mode'', +conserving opcode space. +We argue +above +\pgnnote{DUPLICATED TEXT COVERED ABOVE. Check back whether duped. + search on `fear' and `gadget space'} +that switching between encodings is a safe operation to be performed +without privilege -- i.e., by arbitrary untrustworthy code -- as long as safe +mechanisms exist to switch to a predetermined encoding state when +transitioning across trust boundaries. +For example, it must be the case that exception handlers can operate reliably +in their intended encoding regardless of the encoding mode being used by +unprivileged user code triggering an exception. +Similarly, a reliable encoding switch must be achieved when using +\insnref{CInvoke}. + +Our argument for safe unprivileged use is grounded in the belief that the +primary concern is one of potential code-reuse attacks, as switching encodings +does not change the set of capabilities available to executing code. +Instead, the fear is that an attacker able to manipulate control flow now has +access to an increased number of gadgets, as executable memory may now be used +with multiple interpretations. +We agree that the gadget space does modestly increase, and consider the +problem from two perspectives: + +\begin{description} +\item[When the attack is against hybrid code:] The attacker may have the + ability to influence an integer-based \PC{} value, and will gain access to + additional gadgets (possibly doubling the gadget space). + However, in hybrid code making only limited use of capabilities, CHERI is + not intended to provide additional control-flow robustness. + +\item[When the attack is against pure-capability code:] The attacker must + first gain influence over a capability-based \PCC{} value, which will not + only be protected against a number of common attacks (e.g., by virtue of + tagged memory detecting data overwrites), but also will have narrowed + bounds significantly limiting available gadget space. + + Further, a successful mode switch will have the sole impact of converting + capability-relative loads and stores to integer-relative loads and stores + against \DDC{}, which will hopefully be set to NULL when executing in a + pure-capability code environment -- meaning that while the interpretation of + instructions has changed, the impact of the newly accessible instructions + will, by default, be an exception being thrown. + + Neither of these arguments precludes potentially effective manipulations of + the run-time environment by the attacker, but many tools currently available + to attackers that might benefit from a mode switch are entirely eliminated + or significantly mitigated. +\end{description} + +Overall, this leads us to the conclusion that unprivileged transition between +encodings is permissible. +However, significant care must be taken to ensure that when a privilege change +does occur, there is a safe mechanism by which exception handlers or +domain-transition mechanisms can execute only in the desired mode. + +\pgnnote{ [LOTS OF DUP????] } + +\section{Loading Multiple Tags Without Corresponding Data} % <<< +\label{sec:rationale:cloadtags} + +Occasionally, one may wish to have access to tags without, or before, +loading capabilities to registers. This would be potentially useful when +paging to disk, for example, where one may wish to use DMA to transfer +memory contents to the disk, but yet one must separately store the +corresponding tags. In the absence of direct (i.e., read) access to the +tags, the only alternative would be to involve the CPU in the bulk data copy +and \insnref{CLC} all of the memory to be paged. Separately, when +sweeping memory for revocation or garbage collection, being able to skip +contiguous spans of non-capabilities in memory could dramatically reduce the +DRAM traffic involved in sweeping. + +Towards these ends, we have introduced the \insnref{CLoadTags} +instruction, which takes a capability to memory and loads several tag bits +into a target register. The least-significant bit corresponds to the tag +for the memory at the capability cursor; more significant bits correspond to +tags of memory at larger addresses. The design of our cache fabric allows +us to instantiate this instruction with an efficient load of the tag bits +from one cache-line worth of memory, or, for CHERI Concentrate, 8 tags at +once. + +Full details of the \insnref{CLoadTags} instruction may be found +on \cpageref{\insnlabelname{cloadtags}}. + +% >>> diff --git a/chap-research.tex b/chap-research.tex new file mode 100644 index 00000000..4062b6a8 --- /dev/null +++ b/chap-research.tex @@ -0,0 +1,999 @@ +\chapter{Research Approach} +\label{chap:research} + +In this chapter, we describe the research approach and methodology, grounded +initially in hardware-software co-design and now in +hardware-software-formal co-design, used to develop the CHERI protection model and its ISA instantiations in MIPS, RISC-V, and ARMv8-A. + +\section{Motivation} + +The CHERI protection model provides a sound and formally based architectural +foundation for the principled development of highly +trustworthy systems. +The CHERI approach builds on and extends decades of research into hardware and +operating-system security.\footnote{Levy's {\em Capability-Based Computer Systems}~\cite{levy:capabilities} provides a +detailed history of segment- and capability-based designs through the early +1990s~\cite{levy:capabilities}. +However, it leaves off just as the transition to microkernel-based capability systems such as +Mach~\cite{accetta:mach}, L4~\cite{liedtke:l4}, and, later, seL4~\cite{klein:sel4}, as +well as capability-influenced virtual machines such as the Java Virtual Machine~\cite{Gong99}, +begins. +Chapter~\ref{chap:historical} discuss historical influences on our work in greater detail.} +However, some of the historic approaches that CHERI incorporates (especially capability architectures) +have not been adopted in commodity hardware designs. +In light of these past transition failures, a reasonable question +is ``Why now?'' +What has changed that could allow CHERI to succeed where +so many previous efforts have failed? +Several factors have motivated our decision to begin and carry out this project: + +\begin{itemize} +\item Dramatic changes in threat models, resulting from ubiquitous +connectivity and pervasive uses of computer technology in many +diverse and widely used applications such as wireless mobile +devices, automobiles, and critical infrastructure. +In addition, cloud computing and storage, robotics, software-defined +networking. safety of autonomous systems, and the Internet of Things have +significantly widened the range of vulnerabilities that can be exploited. + +\item An extended ``arms race'' of inevitable vulnerabilities and novel new +attack mechanisms has led to a cycle of ``patch and pray'': systems will be +found vulnerable, and have little underlying robustness to attackers should +even a single vulnerability be found. +Defenders must race to patch systems as vulnerabilities are announced -- and +vulnerabilities may have long half-lives in the field, especially unpublicized ones. +There is a strong need for underlying architectures that offer stronger +inherent immunity to attacks; when successful attacks occur, robust +architectures should yield fewer rights to attackers, minimize gained attack +surfaces, and increase the work factor for attackers. + +\item New opportunities for research into (and possible revisions of) +hardware-software interfaces, brought about by programmable hardware +(especially FPGA soft cores) +and complete open-source software stacks such as +FreeBSD~\cite{mckusick:freebsd} and LLVM~\cite{LA04}. + +\item An increasing trend towards exposing inherent hardware parallelism +through virtual machines and explicit software +multi-programming, and an increasing awareness of information flow +for reasons of power and performance that may align well with the +requirements of security. + +\item Emerging advances in programming languages, such as the ability +to map language structures into protection parameters to +more easily express and implement various policies. + +\item Reaching the tail end of a ``compatibility at all costs'' trend in +CPU design, due to +proximity to physical limits on clock rates and +trends towards heterogeneous and distributed computing. +While ``Wintel'' remains entrenched on desktops, mobile systems -- such as +phones and tablet PCs, as well as appliances and embedded devices -- are +much more diverse, running on a wide variety of instruction set architectures +(especially ARM and MIPS). + +\item Similarly, +new diversity in operating systems has arisen, in which commercial +products such as Apple's iOS and Google's Android extend open-source systems +such as FreeBSD, Mach~\cite{accetta:mach}, and Linux. +These new platforms abandon many traditional constraints, requiring +that rewritten +applications conform to new security models, programming languages, +hardware architectures, and user-input modalities. + +\item Development of {\em hybrid capability-system models} (notably Capsicum~\cite{Watson10}) that integrate capability-system design tenets into current operating-system and language designs. +With CHERI, we are transposing this design philosophy into the instruction-set architecture. +Hybrid design is a key differentiator from prior capability-system processor designs that have typically required ground-up software-architecture redesign and reimplementation. + +\item Significant changes in the combination of hardware, software, +and formal methods to enhance assurance (such as those noted above) +now make possible the development of trustworthy system +architectures that previously were simply too far ahead of their times. +\end{itemize} + +\subsection{C-Language Trusted Computing Bases (TCBs)} + +Contemporary client-server and cloud computing are based on highly distributed +applications, with end-user components executing in rich execution substrates such +as POSIX applications on UNIX, or AJAX in web browsers. +However, even thin clients are not thin in most practical senses: as with client-server +computer systems, they are built from commodity operating-system kernels, hundreds +of user-space libraries, window servers, language runtime environments, and web +browsers, which themselves include scripting language interpreters, virtual machines, +and rendering engines. +Both server and embedded systems likewise depend on complex (and quite +similar) software stacks. +All require confluence of competing interests, representing multiple sites, tasks, and end users in unified computing environments. + +Whereas higher-layer applications are able to run on top of type-safe or constrained +execution environments, such as JavaScript interpreters, lower layers of the system +must provide the link to actual execution on hardware. +As a result, almost all such systems are written in the C programming language; +collectively, this Trusted Computing Base (TCB) consists of many tens of millions of +lines of trusted (but not trustworthy) C and C++ code. +Coarse hardware, OS, and language security models mean that much of this code is +security-sensitive: a single flaw, such as an errant NULL pointer dereference in the kernel, +can expose all rights held by users of a system to an attacker or to malware. + +The consequences of compromise are serious, and include loss of data, release of +personal or confidential information, damage to system and data integrity, and even total +subversion of a user's online presence and experience by the attacker (or even +accidentally without any attacker presence!). +These problems are compounded by the observation that the end-user systems are also an +epicenter for multi-party security composition, where a single web browser or office suite +(which manages state, user interface, and code execution for countless different security domains) +must simultaneously provide strong isolation and appropriate sharing. +The results present not only significant risks of compromise that lead to financial loss or +disruption of critical infrastructure, but also frequent occurrences of such events. + +Software vulnerabilities appear inevitable; +indeed, an arms race has arisen in new +(often probabilistic) software-based mitigation techniques and exploit +techniques that bypass them. +Even if low-level escalation techniques (such as arbitrary code injection and +code reuse attacks) could be prevented, logical errors and supply-chain +attacks will necessarily persist. +Past research has shown that compartmentalizing applications into components executed +in isolated sandboxes can mitigate exploited vulnerabilities (sometimes referred to as privilege +separation). +Only the rights held by a compromised component are accessible to a successful attacker. +This technique is effectively applied in Google's Chromium web browser, placing HTML +rendering and JavaScript interpretation into sandboxes isolated from the global file system. +Compartmentalization exploits the principle of least privilege: if each software element executes with +only the rights required to perform its task, then attackers lose access to most all-or-nothing +toeholds; vulnerabilities may be significantly or entirely mitigated, and attackers must identify +many more vulnerabilities to accomplish their goals. + +\subsection{The Software Compartmentalization Problem} + +The {\em compartmentalization problem} arises from attempts to decompose +security-critical software into components running in different security +domains: the practical application of the principle of least privilege to +software. +Historically, compartmentalization of TCB components such as operating system kernels +and central system services has caused significant +difficulty for software developers -- which limits its applicability for large-scale, +real-world applications, and leads to the abandonment of promising research +such as 1990s {\em microkernel} projects. +A recent resurgence of compartmentalization, applied in userspace to system software and applications +such as OpenSSH~\cite{provos:preventingprivesc} and Chromium~\cite{reis:chromium}, +and more recently in our own Capsicum project~\cite{Watson10}, has been motivated by a +critical security need; however it has seen success only at very coarse separation granularity due to +the challenges involved. +A more detailed history of work in this area can be found in +Chapter~\ref{chap:historical}. + +On current conventional hardware, native applications must be converted to employ message +passing between address spaces (or processes) rather than using a unified address space +for communication, sacrificing programmability and performance by transforming a local +programming problem into a distributed systems problem. +As a result, large-scale compartmentalized programs are difficult to design, write, debug, +maintain, and extend; this raises serious questions about correctness, performance, and most +critically, security. + +These problems occur because current hardware provides strong separation +only at coarse granularity via rings and virtual address spaces, making +the isolation of complete applications (or even multiple operating systems) +a simple task, but complicates +efficient and easily expressed separation between tightly coupled software +components. +Three closely related problems arise: + +\paragraph{Performance is sacrificed.} +Creating and switching between process-based security domains is expensive due +to reliance on software and hardware address-space infrastructure -- such as a +quickly overflowed Translation Look-aside Buffer (TLB) and large page-table +sizes that can lead to massive performance degradation. +Also, above an extremely low threshold, performance overhead from context +switching between security domains tends to go from simply expensive to +intolerable: each TLB entry is an access-control list, with each object (page) +requiring multiple TLB entries, one for each authorized security domain. + +High-end server CPUs typically have TLB entries in the low hundreds, and +even recent network embedded devices reach +the low thousands; the TLB +footprint of fine-grained, compartmentalized software increases with the product of +in-flight security domains and objects due to TLB aliasing, which may easily require +tens or hundreds of thousands of spheres of protection. +The transition to CPU multi-threading has not only failed to relieve this burden, +but actively made it worse: TLBs are implemented using ternary content-addressable +memory (TCAMs) or +other expensive hardware lookup functions, and are often shared between hardware +threads in a single core due to their expense. + +Similar scalability critiques apply to page tables, the tree-oriented +in-memory lookup tables used to fill TLB entries. +As physical memory sizes increase, and reliance on independent virtual address +spaces for separation grows, these tables also grow -- competing for cache +and memory space. + +In comparison, physically indexed general-purpose CPU caches are several orders +of magnitude larger than TLBs, scaling instead with the working set of code paths +explored or the memory footprint of data actively being used. +If the same data is accessed by multiple security domains, it shares data or code +cache (but not TLB entries) with current CPU designs. + +\paragraph{Programmability is sacrificed.} +Within a single address space, programmers +can easily and efficiently share memory between program elements using pointers +from a common namespace. +The move to multiple processes frequently requires the adoption of a distributed +programming model based on explicit message passing, making development, +debugging, and testing more difficult. +RPC systems and higher-level languages are able to mask some (although usually +not all) of these limitations, but are poorly suited for use in TCBs -- RPC systems and +programming language +runtimes are non-trivial, security-critical, and implemented using weaker +lower-level facilities.\footnote{Through extreme +discipline, a programming model can be constructed that maintains synchronized +mappings of multiple address spaces, while granting different rights on memory +between different processes. This leads to even greater TLB pressure +and expensive context switch operations, as +the layouts of address spaces must be managed using cross-address-space +communication. +Bittau has implemented this model via {\em sthread}s, an OS primitive that +tightly couples UNIX processes via shared memory associated with data types +-- a promising separation approach constrained by the realities of current +CPU design~\cite{bittau:wedge}.} + +\paragraph{Security is sacrificed.} +Current hardware is intended to provide robust +shared memory communication only between mutually trusting parties, or at +significant additional expense; granularity of delegation is limited and its +primitives expensive, leading to programmer error and extremely limited use +of granular separation. +Poor programmability contributes directly to poor security properties. + +\section{Methodology} + +Despite half a century of research into computer systems and software design, +it is clear that security remains a challenging problem -- and an increasingly +critical problem as computer-based technologies find ever expanding deployment +in all aspects of contemporary life, from mobile communications devices to +self-driving cars and medical equipment. +There are many contributing factors to this problem, including the asymmetric +advantage held by attackers over defenders (which cause minor engineering +mistakes to lead to undue vulnerability), the difficulties in assessing -- and +comparing -- the security of systems, and market pressures to deliver products +sooner rather than in a well-engineered state. +Perhaps most influential is the pressure for backward compatibility, required +to allow current software stacks to run undisturbed on new generations of +systems, as well as to move seamlessly across devices (and vendors), locking +in least-common-denominator design choices, and preventing the deployment of +more disruptive improvements that serve security. + +Both the current state, and worse, the current direction, support a view that +today's computer architectures (which underlie phenomenal growth of +computer-based systems) are fundamentally ``unfit for purpose'': Rather than +providing a firm foundation on which higher-level technologies can rest, they +undermine attempts to build secure systems that depend on them. +To address this problem, we require designs that mitigate, rather than +emphasize, inevitable bugs, and offer strong and well-understood protections +on which larger-scale systems can be built. +Such technologies can be successful only if transparently adoptable by end +users -- and, ideally, also many software developers. +On the other hand, the resulting improvement must be dramatic to justify +adopting substantive architectural change, and while catering to short-term +problems, must also offer a longer-term architectural vision able to support +further benefit as greater investment is made. + +\subsection{Technical Objectives and Implementation} + +From a purely technical perspective, the aim of the CHERI project is to +introduce architectural support for the principle of least privilege in order +to encourage its direct utilization at all levels of the software stack. +Current computer architectures make this extremely difficult as they impose +substantial performance, robustness, compatibility, and complexity penalties +in doing so -- strongly disincentivizing adoption of such approaches in +off-the-shelf system designs despite the potential to mitigate broad classes +of known (and also as-yet unknown) vulnerability classes. + +Low-level Trusted Computing Bases (TCBs) are typically written in +memory-unsafe languages such as C and C++, which do not offer compatible or +performant protection against pointer corruption, buffer overflows, or other +vulnerabilities arising from that lack of safety not offered directly by the +architecture. +Similarly, software compartmentalization, which mitigates both low-level +vulnerabilities grounded in program representation and high-level application +vulnerabilities grounded in logical bugs, is poorly supported by current MMUs, +leading to substantial (crippling) loss of programmability and performance as +the technique is deployed. + +CHERI also seeks to minimize disruption of current designs, in order to +support incremental adoption with significant +transparency: Ideally, CHERI could be ``slid under'' current software stacks +(such as Apple's iOS ecosystem, or Google's Android ecosystem), allowing +non-disruptive introduction, yet providing an immediate reward for adoption. +This requires supporting current low-level languages such as C and C++ more +safely, but also cleanly supplementing MMU-based programming models required +to support current operating systems and virtualization techniques. +These goals have directed many key design choices in the CHERI-MIPS ISA. + +\subsection{Hardware-Software-Formal Co-Design Methodology} + +Changes to the hardware-software interface are necessarily disruptive. +The ISA is a ``narrow waist'' abstraction that allows hardware designers to +pursue sophisticated optimization strategies (e.g., to exploit parallelism), +while software developers can simultaneously depend on a (largely unchanging) +interface to build successively larger and more complex artifacts. +Stable ISAs have allowed the development of operating systems and application +suites that can operate successfully on a range of systems, and that outlast +the specific platforms on which they were developed. + +This structure is inherently predisposed to non-disruption, as platforms that +incur lower adoption costs will be preferred to those that have higher costs. +However, substantive changes in underlying program representation, such as to +support greater memory safety or fine-grained compartmentalization required to +dramatically improve security, require changes to the ISA. +We therefore aimed to: + +\begin{itemize} +\item Iteratively explore disruptions to the ISA, projecting changes both up + into the software stack including operating systems, compilers, and + applications (to assess impact on compatibility and security), as well as + down into microarchitecture (assessing impact on performance and viability). + +\item Start with a conventional and well-established 64-bit RISC ISA, rather + than re-invent the wheel for general-purpose computation, to benefit from + existing mature software stacks that could then be used for validation. + + For the first few years of the project, we worked with 64-bit MIPS, but we + have more recently worked with RISC-V and ARMv8-A. + These latter two ISAs have offered the opportunity to revisit our + integration with the architecture ``from scratch,'' allowing us to + substantially refine our approach -- e.g., by employing a merged register + file. + +\item Employ realistic open-source software artifacts, including the FreeBSD + operating system, Clang/LLVM compiler suite, and an open-source application + corpus, to ensure that experiments were run with suitable scale, complexity, + performance footprint, and idiomatic use. + +\item Employ realistic hardware artifacts, developing multiple FPGA + soft-core based processor prototypes able to validate key questions about + integration with components such as the pipeline and memory hierarchy, as + well as support performance validation for the full stack including + software. + + In our 64-bit MIPS work, we utilized a single pipelined processor design. + For RISC-V, we have employed three microarchitectures spanning a broad + spectrum: 3-stage and 5-stage pipelined designs, and a superscalar design. + +\item Employ formal models of the ISA, to provide an executable gold model for + testing, from which tests can be automatically generated, and against which + theorem proving can be deployed to ensure that key properties relied on for + software security actually hold. + +\item Pursue the hypothesis that historic capability-system models, designed + to support implementation of the principle of least privilege, can be + hybridized with current software approaches to support compatible and + efficient fine-grained memory protection and compartmentalization. + +\item Take an initially purist capability-system view, incrementally adapting + that model towards one able to efficiently yet safely support the majority + of current software use. + This approach allowed us to retain well-understood monotonicity and + encapsulation properties, as well as pursue capturing notions of explicit + valid provenance enforcement and intentional use not well characterized in + prior capability-system work. + Appropriately but uncompromisingly represented, these properties have proven + to align remarkably well with current OS and language designs. + +\item Aim specifically to cleanly compose with conventional MMUs and MMU-based + software designs by providing an in-address-space protection model, as well + as be able to represent C-language pointers as capabilities. + +\item Support incremental adoption, allowing significant benefit to be gained + through modest efforts (such as re-compiling) for selected software, while + not disrupting binary-compatible execution of legacy applications. + Likewise, support incremental deployment of more disruptive + compartmentalization into key software through greater (but selective) + investment. + +\item Provide primitives that offer immediate short-term benefit (e.g., + invulnerability to common pointer-based exploit techniques, scalable + sandboxing of libraries in key software packages), while also offering a + longer-term vision for future software structure grounded in strong memory + safety and fine-grained compartmentalization. +\end{itemize} + +\section{Research and Development} +\label{sec:development} + +\begin{table}[th] +\begin{center} +\caption{CHERI ISA revisions and major development phases} +\input{cheri-version-table} +\end{center} +\label{table:cheri-isa-versions} +\end{table} + +Between 2010 and 2020, eight major versions of the CHERI model and its +architectural instantiations -- initially MIPS, and later also RISC-V and +ARMv8-A -- developed a +mature hybridization of conventional RISC architecture with a strong (but +software-compatible) capability-system model. +Key research and development milestones can be found in +Figure~\ref{fig:cheri-r-and-d} including major publications. +The major ISA versions, with their development focuses, are described in +Table~\ref{table:cheri-isa-versions}. +This work occurred in several major overlapping phases as aspects of the +approach were proposed, refined, and stabilized through a blend of ISA design, +integrated hardware and software prototyping, and validation of the combined +stack. + +\begin{sidewaysfigure} +\begin{center} +\includegraphics[width=\columnwidth]{20200816-cheri-timeline.pdf} +\caption{CHERI research and development timeline, 2010--2021} +\label{fig:cheri-r-and-d} +\end{center} +\end{sidewaysfigure} + +\medskip +\noindent +\textbf{2010--2015: Composing the MMU with a capability-system model} + +\nopagebreak +\smallskip +\noindent +A key early design choice was that the capability-system model would be +largely orthogonal to the current MMU-based virtual-memory model, yet also +compose with it cleanly~\cite{woodruff:cheriisca2014}. +We chose to place the capability-system model ``before'' the MMU, causing +capabilities to be interpreted with respect to the virtual, rather than +physical, address space. +This reflected the goal of providing fine-grained memory protection and +compartmentalization within address spaces -- i.e., with respect to the +application-programmer model of memory. + +Capabilities therefore protect and implement virtual addresses dereferenced in +much the same way that integer pointers are interpreted in conventional +architectures. +Exceptions allow controlled escape from the capability model by providing +access to privileged capability registers, and execution in privileged rings +grants the ability to manipulate the virtual address space, controlling the +interpretation of virtual addresses embedded in capabilities. + +This approach tightly integrates the capability-system model with the pipeline +and register file, requiring that capabilities be first-class primitives +managed by the compiler, held in registers, and so on. +In order to protect capabilities in the virtual address space, we chose to +physically tag them, distinguishing strongly protected pointers from ordinary +data, in turn extending the implementation of physical memory, but also making +that protection entirely independent from (and non-bypassable by) the MMU +mechanism. + +\medskip +\noindent +\textbf{2012--2014: Composing C pointers with the capability-system mode} + +\smallskip +\noindent +Another key early design choice was the goal of using capabilities to +implement C-language pointers -- initially discretionarily (i.e., as annotated +in the language), and later ubiquitously (i.e., for all virtual addresses in a +more-secure program). +This required an inevitable negotiation between C-language semantics and the +capability-system model, in order to ensure strong compatibility with current +software~\cite{ChisnallCPDP11,Cerberus-PLDI16}. + +For example, C embeds a strong notion that pointers point within buffers. +This requires that CHERI capabilities distinguish the notion of current virtual +address from the bounds of the containing buffer -- while also still providing +strong integrity protection to the virtual address. +This led us to compose +fat-pointer~\cite{trevor:cyclone,Nagarakatte:2009:SHC:1542476.1542504,Necula:2002:CTR:503272.503286} and capability +semantics as the capability-system model evolved. + +Similarly, we wished to allow all pointers to be represented as capabilities +-- including those embedded within other data structures -- leading naturally +to a choice to mandatorily tag pointers in memory. +A less obvious implication of this approach is that operations such as memory +copying must be capability-oblivious, maintaining the tag across +pointer-propagating memory operations, requiring that data and capabilities +not only be intermingled in memory, but also in register representation. +Capability registers are therefore also tagged, allowing them to hold data or +capabilities, preserving provenance transparently. + +As part of this work, we also assisted with the development of new formal +semantics for the C programming language, ensuring that we met the practical +requirements of C programs, but also assisting in formalizing the protection +properties we offer (e.g., strong protection of provenance validity grounded +in an implied pointer provenance model in C). + +CHERI should be viewed as providing primitives to support strong C-language +pointer protection, rather than as directly implementing that protection: it +is the responsibility of the compiler (and also operating system and +runtime) to employ capabilities to enforce protections where desired -- +whether by specific memory type, based on language annotations, or more +universally. +The compiler can also perform analyses to trade off source-code and binary +compatibility, enforcing protection opportunistically in responding to various +potential policies on tolerance to disruption. + +\medskip +\noindent +\textbf{2014--2015: Fine-grained compartmentalization} + +\smallskip +\noindent +A key goal of our approach was to differentiate virtualization (requiring +table-based lookups, and already implemented by the MMU) from protection +(now implemented as a constant-time extension to the pointer primitive), which +would avoid table-oriented overheads being imposed on protection. +This applies to C-language protection, but also to the implementation of +higher-level security constructs such as +compartmentalization~\cite{watson15:cheri,watson2016:microjournal}. + +Compartmentalization depends on two underlying elements: strong isolation and +controlled communication bridging that isolation. +Underlying monotonicity in capabilities -- i.e., that a delegated reference +to a set of rights cannot be broadened to include additional rights -- +directly supports the construction of confined components within address +spaces. +Using this approach, we can place code in execution with only limited +access to virtual memory, constructing ``sandboxes'' (and other more complex +structures) within conventional processes. +The CHERI exception model permits transition to a more privileged component +-- e.g., the operating-system kernel or language runtime -- allowing the +second foundation, controlled communication, to be implemented. + +Compartmentalization is facilitated by further extensions to the capability +model, including a notion of ``sealed'' (or encapsulated capabilities). +In CHERI, this is implemented as a software-defined capability: one that has +no hardware interpretation (i.e., cannot be dereferenced), and also strong +encapsulation (i.e., whose fields are immutable). +Other aspects of the model include a type mechanism allowing sealed code and +data capabilities to be inextricably linked; pairs of sealed code +capabilities and data +capabilities can then be used to efficiently describe protection domains via +an object-capability model. +We provide some hardware assistance for protection-domain switching, +providing straightforward parallel implementation of key checks, but leave +the implementation of higher-level aspects of switching to the software +implementation. + +Here, as with C-language integration, it is critical that CHERI provide a +general-purpose mechanism rather than enforce a specific policy: the sealed +capability primitive can be used in a broad variety of ways to implement +various compartmentalization models with a range of implied communication +and event models for software. +We have experimented with several such models, including a protection-domain +crossing primitive modeled on a simple (but now strongly protected) function +call, and also on asynchronous message passing. +Our key performance goal was fixed (low) overhead similar to a function call, +avoiding overheads that scale with quantity of memory shared (e.g., as is the +case with table-oriented memory sharing configured using the MMU). + +\medskip +\noindent +\textbf{2015--2017: Architectural and microarchitectural efficiency} + +\smallskip +\noindent +Side-by-side with development of a mature capability-based architectural +model, we also explored the implications on performance. +This led to iterative refinement of the ISA to improve generated code, but +also substantive efforts to ensure that there was an efficient in-memory +representation of capabilities, as well as microarchitectural implementations +of key instructions. + +A key goal was to maintain the principle of a load-store architecture by +avoiding combining computations with memory accesses -- already embodied by +both historic and contemporary RISC architectures. +While pointers are no longer conflated with integer values, a natural +composition of the capability model and ISA maintains that structural goal +without difficulty. + +One important effort lay in the reduction from a 256-bit capability (capturing +the requirements of software for 64-bit pointer, 64-bit upper bound, and +64-bit lower bound, as well as additional metadata such as permissions) to a +128-bit compressed representation. +We took substantial inspiration from published work in pointer +compression~\cite{kwon:lowfat}, but found that our C-language compatibility +requirements imposed a quite different underlying model and representation. +For example, it is strictly necessary to support the common C-language idiom +of permitting out-of-bounds pointers (but not dereference), which had been +precluded by many proposed +schemes~\cite{ChisnallCPDP11,Cerberus-PLDI16,davis2019:cheriabi}. +Similarly, the need to support sealed capabilities led to efforts to +characterize the tradeoff between the type space (the number of unique classes +that can be in execution in a CHERI address space) and bounds precision (the +alignment requirements imposed on sealed references). + +Another significant effort lay in providing in-memory tags, which are not +directly supported by current DRAM layouts~\cite{joannou2017:tagged-memory, UCAM-CL-TR-936}. +In our initial implementation, we relied on a flat tag table (supported by a +dedicated tag cache). +This imposed a uniform (and quite high) overhead in additional DRAM accesses +across all memory of roughly $10\%$. +We have developed new microarchitectural techniques to improve emulated tag +performance, based on a hierarchical table exploiting sparse use of pointers +in memory, to reduce this overhead to $<2\%$ even with very high pointer +density (e.g., in language runtimes). + +\medskip +\noindent +\textbf{2016--2017: Kernel Compartmentalization} + +\smallskip +\noindent +Our initial design focus was on supporting fine-grained memory protection +within the user virtual address space, and implicitly, also +compartmentalization. +Beyond an initial microkernel brought up to validate early capability model +variants, kernel prototypes through much of our project have eschewed use of +capability-aware code in the kernel due to limitations of the compiler, but +also because of a focus on large userspace TCBs such as compression libraries, +language runtimes, web browsers, and so on, which are key attack surfaces. + +We have more recently returned to in-kernel memory protection and +compartmentalization, where the CHERI model in general carries through without +change -- code executing in the kernel is not fundamentally different from +code executing in userspace. +The key exception is a set of management instructions available to the kernel, +able to manipulate the MMU (and hence the interpretation of capabilities), as +well as control features such as interrupt delivery and exception handling. +We are now extending CHERI to allow the capability mechanism to control access +to these features so that code can be compartmentalized within the kernel. +We are also pursuing changes to the exception-based domain-transition +mechanism used in earlier ISA revisions that shift towards a jump-based model, +which will avoid exception-related overheads in the microarchitecture. + +\medskip +\noindent +\textbf{2018--2020: Temporal Memory Safety} + +The potential to support strong and deterministic temporal memory safety was +an aim of the CHERI architecture from inception, facilitated by several +architectural features: tagged capabilities allowing accurate identification +of pointers in memory; composition with an MMU to allow invalidation of +portions of the virtual address space; and capability flow control via MMU +and capability permission bits limiting where capabilities could be stored in +memory. +However, we had envisioned this primarily from the perspective of software +compartmentalization, and hence a relatively low overall throughput of +revoked or invalidated capabilities. + +With an increased focus on supporting C and C++ memory safety by implementing +all language-level pointers using architectural capabilities, we began to +explore whether heap temporal memory safety could perform adequately using +these techniques. +While for some workloads, they were sufficient, we have expanded the set of +architectural tools to support capability revocation through instructions to +efficiently access tags across regions of memory, and MMU features to allow +tracking of versioned capabilities permitting implementation of load-side +barrier techniques similar to those found in garbage collection appearing in +CHERI ISAv8. +This remains an area of active ongoing research. + +\medskip +\noindent +\textbf{2014--2020: Architectural Neutrality} + +In our earlier research, CHERI was in all senses an extension to the 64-bit +MIPS ISA. +We took a ``ground up'' view on developing the model, prototyping in a tight +hardware-software co-design loop around the architecture, microarchitecture, +and software, as we brought together ideas about capability-system design and +the baseline ISA. +However, it became apparent that the evolving CHERI protection model in +software related to ideas entirely portable across ISAs: C pointer +implementation, fine-grained memory protection, and software encapsulation. + +In 2014, we began a long-running and still ongoing collaboration with Arm +Limited to explore generalizing the model across ISAs, and specifically to +integrate it into the 64-bit ARMv8-A architecture. +This led to the development of a portable architectural model: concept such as +tagged capabilities are essential to CHERI, but not specific to MIPS, ARMv8-A, +or other architectures. +In 2017, in CHERI ISAv6, we sketched integrations of CHERI with the commercial +x86-64 ISA and developing open-source RISC-V ISA. +In CHERI ISAv7, we fully elaborated CHERI-RISC-V, and in CHERI ISAv8 we +polished many aspects of this design based on the experience of implementing a +full hardware-software stack, including three microarchitectures. +In 2019, Arm announced Morello~\cite{arm-morello}, both the integration of +CHERI into ARMv8-A, and also an experimental board implementing the ISA in a +high-end contemporary superscalar processor design. + +\section{A Hybrid Capability-System Architecture} + +Unlike past research into capability systems, CHERI allows traditional address-space separation, implemented using a memory management unit (MMU), to +coexist with granular decomposition of software within each address space. +Similarly, we have aimed to model CHERI capability behavior not only on strong +capability semantics (e.g., monotonicity), but also to be compatible with +C-language pointer semantics. +As a result, fine-grained memory protection and compartmentalization can be applied selectively throughout existing software +stacks to provide an incremental software migration path. +We envision early deployment of CHERI extensions in selected components of the +TCB's software stack: separation kernels, operating system kernels, programming +language runtimes, sensitive libraries such as those involved in data compression or encryption, and network applications such as web browsers and web +servers. + +CHERI addresses current limitations on memory protection and compartmentalization by extending virtual +memory-based separation with hardware-enforced, fine-grained protection within address spaces. +Granular memory protection mitigates a broad range of previously exploitable bugs by coercing common memory-related failures into exceptions that can be handled by the application or operating system, rather than yielding control to the attacker. +The CHERI approach also restores a single address-space programming model for +compartmentalized (sandboxed) software, facilitating efficient, programmable, and robust +separation through the capability model. + +We have selected this specific composition of traditional virtual memory with an +in-address-space security model to facilitate technology transition: in CHERI, +existing C-based software can continue to run within processes, and even +integrate with capability-enhanced software within a single process, to provide +improved robustness for selected software components -- and perhaps over time, all +software components. +For example, a sensitive library (perhaps used for image processing) might employ +capability features while executing as part of a CHERI-unaware web browser. +Likewise, a CHERI-enabled application can sandbox and instantiate multiple copies of +unmodified libraries, to efficiently and easily gate access to the rest of application +memory of the host execution environment. + +\section{A Long-Term Capability-System Vision} + +While we have modeled CHERI as a hybrid capability-system architecture, and in +particular described a well-defined and practical composition with MMU-based +designs, CHERI can also support more ``pure'' capability-oriented hardware and +software designs. +At one extreme in this spectrum, we have begun early experimentation with an +MMU-free processor design offering solely CHERI-based protection for software +use. +We are able to layer a CHERI-specific microkernel over this design, which +executes all programs within a single address-space object-capability model. +This approach might be appropriate to microcontroller-scale systems, to avoid +the cost of an MMU, and in which conventional operating systems might be +inappropriate. +The approach might also be appropriate to very large-scale systems, in which +an MMU is unable to provide granular protection and isolation due to TLB +pressure requiring a shift to very large page sizes. + +However, in retaining our primary focus on a hybridization between MMU- and +capability-based approaches, software designs can live at a variety of points +in a spectrum between pure MMU-based and solely CHERI-based models. +A CHERI-based microkernel might be used, for example, within a conventional +operating-system kernel to compartmentalize the kernel -- while retaining an +MMU-based process model. +A CHERI-based microkernel might similarly be used within an MMU-based process +to compartmentalize a large application. +Finally, the CHERI-based microkernel might be used to host solely CHERI-based +software, much as in an MMU-less processor design, leaving the MMU dormant, +or restricted to specific uses such as full-system virtualization -- a task +for which the MMU is particularly well suited. + +\section{Threat Model} + +%\pgnnote{Model, singular? Might we have multiple models? For example, +% embedded microprocessors might have a different threat model than +% general-purpose hardware for mobile devices.} +% +%\rwnote{I think I'd take the view that they are the same threat model, as we +% are concerned with threats originating in locally executing software, +% whether due to external manipulation (e.g., via network data) or simple +% local malice. I'm not sure I perceive a large structural difference for +% the embedded case -- we are not concerned with physical attacks, etc, +% where different packaging might affect the story? + +CHERI protections constrain code ``in execution'' and allow fine-grained management +of privilege within a framework for controlled separation and communication. +Code in execution can represent the focus of many potentially malicious parties: +subversion of legitimate code in violation of security policies, injection of malicious +code via back doors, Trojan horses, and malware, and also +denial-of-service attacks. +CHERI's fine-grained memory protection mitigates +many common attack techniques by implementing bounds and permission checks, +reducing opportunities for the conflation of code and data, corruption of +control flow, and also catches many common exploitable programmer bugs; +compartmentalization constrains successful attacks via pervasive observance of +the principle of least privilege. + +Physical attacks on CHERI-based systems are explicitly excluded from our threat model, +although CHERI CPUs might easily be used in the context of tamper-evident or +tamper-resistant systems. +Similarly, no special steps have been taken in our design to counter undesired +leakage of electromagnetic emanations and certain other side channels such as acoustic inferences: +we take for granted the presence of an +electronic foundation on which CHERI can run. +CHERI will provide a supportive framework for a broad variety of security-sensitive +activities; while not itself a distributed system, CHERI could form a sound foundation for various forms of distributed trustworthiness. + +CHERI is an ISA-level protection model that does not address increasingly +important CPU- or bus-level covert and side-channel attacks, relying on the +micro-architecture to limit implicit data flows. +In some sense, CHERI in fact increases exposure: the greater the offers of +protection within a system, the greater the potential impact of unauthorized +communication channels. +As such, we hope side-channel attacks are a topic that we will be able to +explore in future work. +Overall, we believe that our threat model is realistic and will +lead to systems that can be substantially more trustworthy than +today's commodity systems -- while recognizing that ISA-level protections must +be used in concert with other protections suitable to different threat models. + +\section{Formal Methodology} + +Throughout this project, we apply formal semantics and reasoning techniques to help avoid +system vulnerabilities. +We are (judiciously) applying formal methodology in +five areas: + +\begin{enumerate} +\item Early in the project, we developed a formal semantics for the CHERI-MIPS ISA described in + SRI's Prototype Verification System (PVS) -- an automated theorem-proving + and model-checking toolchain -- which can be used to verify the + expressibility of the ISA, but also to prove properties of critical code. + For example, we are interested in proving the correctness of software-based + address-space management and domain transitions. + We are likewise able to automatically generate ISA-level test suites from + formal descriptions of instructions, which are applied directly to our + hardware implementation. + +\item We developed extensions to the BSV compiler to export + an HDL description to SRI's PVS and SAL model checker. + We also developed a new tool (Smten) +for efficient SMT (Satisfiability Modulo Theories) modeling of designs + (using SRI's Yices), and another tool for + automated extraction of key properties from larger designs in the + BSV language, both + of which greatly simplify formal analysis. +%PS +% These tools will allow us to verify low-level properties of the hardware design +% and use the power of model checking and satisfiability solvers to analyze +% related properties. +% Ideally they will also help link ISA-level specifications with the CPU implementation. + + +\item We then developed more complete CHERI-MIPS ISA models, + incorporating both + MIPS and CHERI instructions, first using the L3 and then the Sail instruction-set description + languages (both of which support automatic generation of executable + emulators from formal definitions). + We have used these as the ``golden model'' of instruction + behavior, against which our test suite is validated, software implementations can + be tested in order to generate traces of correct processor execution, and so + on. + We have used the L3 and Sail models to identify a number of bugs in multiple hardware + implementations of CHERI-MIPS, as well as to discover software dependences + on undefined instruction-set behavior. + +\item We have used these L3 and Sail models also as a basis for + mechanised proof of key architectural security properties. +% PS: this is pasted from new intro text +L3 and Sail support automatic generation of versions of the models in +the definition languages of (variously) the +HOL4, Isabelle, and Coq theorem provers. +Key architectural verification goals including proving not just low-level +properties, such as the monotonicity of each individual instruction +and properties of the CHERI capability compression schemes, but also +higher-level goals such as compartment monotonicity, in which arbitrary code +sequences isolated within a compartment are unable to construct additional +rights beyond those reachable either directly via the register file or +indirectly via loadable capabilities. +We have proven a number of such properties about the CHERI-MIPS ISA, to be +documented in future papers and reports. + +% this is now subsumed by the previous bullet +%\item We have proven a number of properties about our ``compressed'' 128-bit +% capability implementation to ensure that the protection and security +% properties present in the 256-bit reference semantics (e.g., capability +% monotonicity) hold of the compressed version -- and that the compression +% and decompression algorithms are correct. + +\item From Sail, we also automatically generate SMT problems, which we + have used to check properties of our capability compression + schemes. + + +\item We have explored how CHERI impacts a formal specification of C-language + semantics, improving a number of aspects of our C-language compatibility + (e.g., as relates to conformant handling of the \ccode{intptr_t} type). +\end{enumerate} + +\psnote{Taken out the following, as that draft isn't available (as far + as I can see). Presumably it described the earlier PVS work -- do + we need a pointer to something that does describe that? +``A detailed description of formal methods efforts relating to CHERI may +be found in the emerging draft {\em CHERI Formal Methods +Report}~\cite{CHERI-FM15}.'' +} + +\section{Protection Model and Architecture} + +As our work on CHERI has proceeded, we have transitioned from a view in which +CHERI is an ISA extension to 64-bit MIPS to one in which CHERI is a general +protection model that can be expressed through a variety of approaches +and mappings into multiple underlying ISAs. +This report describes a software-facing protection model +(Chapter~\ref{chap:model}) focused on operating systems and compilers, +specific mapping into the 64-bit MIPS ISA for the purposes of experimentation +and evaluation (Chapters~\ref{chap:architecture}, ~\ref{chap:cheri-mips} +and~\ref{chap:isaref-mips}), and architectural sketches for potential integration +into other ISAs (Chapters~\ref{chap:cheri-riscv} on CHERI-RISC-V, +Chapter~\ref{chap:cheri-x86-64} on CHERI-x86-64, and Arm +Morello~\cite{arm-morello}). +However, we have taken a ``ground-up'' approach utilizing hardware-software +co-design to ensure that concrete mapping exist that +satisfies the practical engineering requirements of architecture, +microarchitecture, compiler, operating system, and applications. +At the time CHERI ISAv8 is published, we are in the throes of transitioning +the bulk of our research from CHERI-MIPS to CHERI-RISC-V and Morello, which +have learned substantially from our initial experiences implementing CHERI. + +Our selection of RISC as a foundation for the CHERI capability extensions +is motivated by two factors. +First, simple instruction set architectures are easier to reason about, extend, and implement. +Second, RISC architectures (such as ARM and MIPS) are widely used in network embedded +and mobile device systems such as firewalls, routers, smart phones, and tablets -- markets +with the perceived +flexibility to adopt new CPU facilities, and also an immediate and pressing +need for improved security. +CHERI's new security primitives would also be useful in workstation and server environments, +which face similar security challenges. + +CHERI-RISC-V and Arm Morello demonstrate that the abstract CHERI protection +model, as well as our architectural approach, applies to a range of RISC +architectures. +The design principles would also apply to other non-RISC ISAs, such as 32-bit and +64-bit Intel and AMD, but require significantly more adaptation work, as well as careful +consideration of the implications of the diverse set of CPU features found in more CISC-like +architectures. + +It is not impossible to imagine pure-software implementations of the CHERI +protection model -- not least, because we use these daily in our work through +both cycle-accurate processor simulations, and a higher-performance but less +microarchitecturally realistic Qemu implementation. +Further, compiler-oriented approaches employing a blend of static checking and +dynamic enforcement could also approximate or implement CHERI protection +semantics (e.g., along the lines of software fault isolation +techniques~\cite{wahbe:sfi} or Google Native Client (NaCl)~\cite{yee:nacl}). +We do, however, hypothesize that these implementations would be difficult to +accomplish without hardware assistance: for example, continuous checking of +program-counter and default data capability bounds, as well as atomic clearing +of tags for in-memory pointers during arbitrary memory writes might come at +substantial expense in software, yet being ``free'' in supporting hardware. + +\section{Hardware and Software Prototypes} + +As a central part of this research, we have developed reference prototypes of +the CHERI ISA via several CHERI processor designs. +These prototypes allow us to explore, +validate, evaluate, and demonstrate the CHERI approach through realistic +hardware properties and real-world software stacks. +A detailed description of the current prototypes, both from architectural and +practical use perspectives, may be found in our companion papers and technical +reports, described in Section~\ref{sec:publications}. + +In our CHERI-MIPS work, we developed two pipelined processor variations that +incorporated our evolving CHERI-MIPS ISA. +These prototypes allowed us to explore ISA design tradeoffs with moderate +microarchitectural realism. +We implement our prototypes in Bluespec SystemVerilog +(BSV)~\cite{Bluespec:TFRG}, allowing us to create highly parameterizable +designs, as well as perform rapid design-space exploration. +Wherever possible, we open source our designs to allow reproduction and reuse +by other researchers. + +In addition to our BSV implementations, we have also implemented executable +models using first the L3 ISA modeling language~\cite{Fox2015}, and later +SAIL~\cite{sail-popl2019}. +The SAIL descriptions of CHERI-MIPS and CHERI-RISC-V are used for formal +proof, SMT checking, and also directly incorporated into our CHERI ISA +specification. +We also use an adaptation of the QEMU fast ISA accelerator. + +As the CHERI security model is necessarily a hardware-software model, we have +also performed substantial experimentation with software stacks targeting all +of our ISA instantiations of CHERI. +We have an adaptation of the open-source Clang/LLVM compiler suite, LLD +linker, and GDB debugger, which are able to generate code using CHERI +capabilities. +We have adaptations of the FreeRTOS and FreeBSD operating systems to CHERI, +known as CheriFreeRTOS and CheriBSD. +CheriBSD is portable across all of our CHERI-extended architectures: +CHERI-MIPS, CHERI-RISC-V, and Morello. +We use CheriFreeRTOS and CheriBSD on our ISA simulations and also on FGPA. + +Throughout, we consider metrics such as microarchitectural disruption, Power +Area and Performance (PPA) on FPGA, dynamic benchmark performance, software +language and source-code disruption, and security as part of our evaluation +cycle. diff --git a/cheri-architecture.tex b/cheri-architecture.tex new file mode 100644 index 00000000..18b69069 --- /dev/null +++ b/cheri-architecture.tex @@ -0,0 +1,156 @@ +%%%% University of Cambridge tech-report formatting; enable when producing +%%%% tech-report versions of these documents; otherwise, disable. +\documentclass[12pt,twoside,openright,a4paper]{report} +\setlength{\oddsidemargin}{-0.4mm} % 25 mm left margin +\setlength{\evensidemargin}{\oddsidemargin} +\setlength{\textwidth}{160mm} % 25 mm right margin +\setlength{\topmargin}{-5.4mm} % 20 mm top margin +\setlength{\headheight}{5mm} +\setlength{\headsep}{5mm} +\setlength{\footskip}{10mm} +\setlength{\textheight}{237mm} % 20 mm bottom margin +%%%% .. or regular document +%\documentclass[12pt,letterpaper,twoside,openright,fleqn]{report} +%\usepackage{etex} +%%%% End of tech-report vs. regular +%%%% + +\input{preamble} + +\begin{document} +\title{Capability Hardware Enhanced RISC Instructions: \\ + \smallskip CHERI Instruction-Set Architecture \\ + {\large Version 8}} +\author{ + \parbox{\linewidth}{\centering% + Robert~N.~M.~Watson, + Peter~G.~Neumann, + Jonathan~Woodruff, + Michael~Roe, + Hesham~Almatary, + Jonathan~Anderson, + John~Baldwin, + Graeme~Barnes, + David~Chisnall, + Jessica~Clarke, + Brooks~Davis, + Lee~Eisen, + Nathaniel~Wesley~Filardo, + Richard~Grisenthwaite, + Alexandre~Joannou, + Ben~Laurie, + A.~Theodore~Markettos, + Simon~W.~Moore, + Steven~J.~Murdoch, + Kyndylan~Nienhuis, + Robert~Norton, + Alexander~Richardson, + Peter~Rugg, + Peter~Sewell, + Stacey~Son, and + Hongyan~Xia + }% + \\ + \\ + SRI International, University of Cambridge, and Arm Limited +} + +%% CL tech-report format provides its own cover page +%\begin{minipage}[h]{\textwidth} +% %\vspace{-.2cm} +% \maketitle +% +% %\vspace{-0.2cm} +% {\footnotesize +% Approved for public release; distribution is unlimited. +% Sponsored by the Defense Advanced Research Projects Agency (DARPA) and the +% Air Force Research Laboratory (AFRL), under contract FA8750-10-C-0237 +% (``CTSRD''), with additional support from FA8750-11-C-0249 (``MRC2''), +% HR0011-18-C-0016 (``ECATS''), and FA8650-18-C-7809 (``CIFV'') as part of +% the DARPA CRASH, MRC, and SSITH research programs. +% The views, opinions, and/or findings contained in this report are those of +% the authors and should not be interpreted as representing the official +% views or policies, either expressed or implied, of the Department of +% Defense or the U.S. Government. +% +% \smallskip +% This work was supported in part by the Innovate UK project Digital +% Security by Design (DSbD) Technology Platform Prototype, 105694. +% +% \smallskip +% Additional support was received from St John's College Cambridge, +% the Google SOAAP Focused Research Award, a Google Chrome University +% Research Program Award, the RCUK's Horizon Digital Economy Research Hub +% Grant (EP/G065802/1), the EPSRC REMS Programme Grant (EP/K008528/1), the +% EPSRC Impact Acceleration Account (EP/K503757/1), the EPSRC IOSEC grant +% (EP/EP/R012458/1), the ERC Advanced Grant ELVER (789108), the Isaac Newton +% Trust, the UK Higher Education Innovation Fund (HEIF), Thales E-Security, +% Microsoft Research Cambridge, Arm Limited, Google DeepMind, HP Enterprise, +% and a Gates Cambridge Scholarship. +% +%} +%\end{minipage} +%% + +\normalsize + +%% CL tech-report format requires page numbering to start at 3 +\setcounter{page}{3} +%% + +%% For revisions sent for editing, prefer double spacing. +%\doublespacing +%% + +\clearpage + +\input{abstract} + +\clearpage + +\input{acknowledgments} + +\clearpage + +\tableofcontents + +\clearpage + +\input{chap-intro} +\input{chap-model} +\input{chap-architecture} +\input{chap-cheri-mips} +\input{chap-cheri-riscv} +\input{chap-cheri-x86-64} +\input{chap-isaref-mips} +\input{chap-isaref-riscv} +\input{chap-rationale} +\input{chap-assurance} +\input{chap-microarchitecture} +\input{chap-research} +\input{chap-historical} +\input{chap-conclusion} + +\appendix + +\input{app-versions} + +\input{app-isaquick-mips} +\input{app-isaquick-riscv} + +\input{app-experimental} + +\input{app-cheri-concentrate-listings.tex} +\input{app-cheri-128.tex} + +\glsaddall +\printglossaries + +\cleardoublepage +\phantomsection +\addcontentsline{toc}{chapter}{Bibliography} +\printbibliography + +%\chapter*{Index} + +\end{document} diff --git a/cheri-version-table.tex b/cheri-version-table.tex new file mode 100644 index 00000000..deb1b127 --- /dev/null +++ b/cheri-version-table.tex @@ -0,0 +1,40 @@ +\begin{tabular}{llp{3.25in}} +\toprule + Year(s) & Version & Description \\ +\midrule + 2010- & ISAv1 & RISC capability-system model w/64-bit MIPS \\ + 2012 & & Capability registers and tagged memory \\ + & & Guarded manipulation of registers \smallskip \\ + 2012 & ISAv2 & Extended tagging to capability registers \\ + & & Capability-aware exception handling \\ + & & MMU-based OS with CHERI support \smallskip \\ + 2014 & ISAv3~\cite{UCAM-CL-TR-864} & Fat pointers $+$ capabilities, compiler \\ + & & Instructions to optimize hybrid code \\ + & & Sealed capabilities, \insnnoref{CCall}/\insnnoref{CReturn} \smallskip \\ + 2015 & ISAv4~\cite{UCAM-CL-TR-876} & MMU-CHERI integration (TLB permissions) \\ + & & ISA support for compressed capabilities \\ + & & Hardware-accelerated domain switching \\ + & & Multicore instructions: \insnnoref{LL}/\insnnoref{SC} variants \smallskip \\ + 2016 & ISAv5~\cite{UCAM-CL-TR-891} & CHERI-128 compressed capability model \\ + & & Improved generated code efficiency \\ + & & Initial in-kernel privilege limitations \smallskip \\ + 2017 & ISAv6~\cite{UCAM-CL-TR-907} & Mature kernel privilege limitations \\ + & & Further generated code efficiency \\ + & & CHERI-x86 and CHERI-RISC-V sketches \\ + & & Jump-based protection-domain transition \smallskip \\ + 2019 & ISAv7~\cite{UCAM-CL-TR-927} & Architecture-neutral protection model \\ + & & A more complete CHERI-RISC-V elaboration \\ + & & Compartment IDs for side-channel resistance \\ + & & 64-bit capabilities for 32-bit architectures \\ + & & Architectural temporal memory safety \\ + & & CHERI Concentrate compressed capabilities \smallskip \\ + 2020 & ISAv8~\cite{UCAM-CL-TR-951} & Compressed capabilities in abstract + model \\ + & & 32- and 64-bit address sizes \\ + & & Deployed sentry capabilities \\ + & & Fully elaborated CHERI-RISC-V \\ + & & MMU-assisted load-side-barrier revocation \\ + & & Richer microarchitectural exploration \\ + & & Synchronized with Arm Morello architecture~\cite{arm-morello} \\ +\bottomrule +\end{tabular} diff --git a/cheri.bib b/cheri.bib new file mode 100644 index 00000000..bf3875f4 --- /dev/null +++ b/cheri.bib @@ -0,0 +1,16511 @@ + +@techreport{CHERI-FM15, + author = {Peter G. Neumann and Robert N. M. Watson and Nirav Dave and Alexandre Joannou and Matthew Naylor and Michael Roe and Anthony Fox and Jonathan Woodruff}, + title = {{CHERI Formal Methods, interim version 3.0}}, + year = {2015}, + source = {}, + institution = {SRI International and the University of Cambridge}, + address = {}, +} + + +@article{karger:performance, + author = {Karger, Paul A.}, + title = {Using registers to optimize cross-domain call performance}, + journal = {SIGARCH Computer Architecture News}, + volume = {17}, + number = {2}, + year = {1989}, + issn = {0163-5964}, + pages = {194--204}, + doi = {10.1145/68182.68201}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + + +@inproceedings{demoura-etal07:VSTTE, + AUTHOR = {Leonardo de Moura and Sam Owre and Harald Rue{\ss} and + John Rushby and Natarajan Shankar}, + TITLE = {Integrating Verification Components}, + CROSSREF = {VSTTE07} +} + +@proceedings{VSTTE07, + TITLE = {Verified Software: + Theories, Tools, and Experiments}, + BOOKTITLE = {Verified Software: + Theories, Tools, and Experiments}, + EDITOR = {Bertrand Meyer and Jim Woodcock}, + NUMBER = 4171, + SERIES = {LNCS}, + YEAR = 2008 +} +@comment{ PUBLISHER = {Springer Verlag}, } + +@techreport{andrews:partitions, + author = {Andrews, Gregory R.}, + title = {Partitions and Principles for Secure Operating Systems}, + year = {1975}, + source = {http://www.ncstrl.org:8900/ncstrl/servlet/search?formname=detail\&id=oai%3Ancstrlh%3Acornellcs%3ACORNELLCS%3ATR75-228}, + institution = {Cornell University}, + address = {Ithaca, NY, USA}, +} + +@article{wulf:hydra, + author = {Wulf, W. and Cohen, E. and Corwin, W. and Jones, A. and Levin, R. and Pierson, C. and Pollack, F.}, + title = {{HYDRA: the kernel of a multiprocessor operating system}}, + journal = {Communications of the ACM}, + volume = {17}, + number = {6}, + year = {1974}, + issn = {0001-0782}, + pages = {337--345}, + doi = {10.1145/355616.364017}, + publisher = {ACM}, + address = {New York, NY, USA}, + } + +@article{walker:uclasecureunix, + author = {Walker, Bruce J. and Kemmerer, Richard A. and Popek, Gerald J.}, + title = {{Specification and verification of the UCLA Unix security kernel}}, + journal = {Communications of the ACM}, + volume = {23}, + number = {2}, + year = {1980}, + issn = {0001-0782}, + pages = {118--131}, + doi = {10.1145/358818.358825}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@inproceedings{schroeder:multicssecuritykernel, + author = {Schroeder, Michael D.}, + title = {{Engineering a security kernel for Multics}}, + booktitle = {SOSP '75: Proceedings of the Fifth ACM Symposium on Operating Systems Principles}, + year = {1975}, + pages = {25--32}, + location = {Austin, Texas, United States}, + doi = {10.1145/800213.806518}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@inproceedings{walker:adventtrusted, + author = {Walker, Stephen T.}, + title = {The advent of trusted computer operating systems}, + booktitle = {AFIPS '80: Proceedings of the May 19-22, 1980, national computer conference}, + year = {1980}, + pages = {655--665}, + location = {Anaheim, California}, + doi = {10.1145/1500518.1500626}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@inproceedings{sebes:dtmach, +author = {E. J. Sebes}, +booktitle = {{Proceedings of the USENIX Mach Symposium}}, +title = {{Overview of the architecture of Distributed Trusted Mach}}, +pages = {20--22}, +month = nov, +year = {1991}, +pmid = {286502042582210013related:3VWJ-xbc-QMJ}, + publisher = {USENIX Association}, +} + +@InProceedings{spencer:flask, + author = "Ray Spencer and Stephen Smalley and Peter Loscocco and + Mike Hibler and David Andersen and Jay Lepreau", + title = "The {Flask} Security Architecture: System Support for + Diverse Security Policies", + annote = "Separate policy and mechanisms derived from DTOS and + somewhat consistant with GFAC. Not so suitable: + Capability systems (difficulty to control propagation) + and interception systesm (e.g., L4 Clan/Chief, problem + of exposure of all abstractions). Fluke (\& flask) + homepage: + \url{http://www.cs.utah.edu/flux/fluke/html/flask.html}", + pages = "123--139", + booktitle = "{Proceedings of the 8th {USENIX} Security Symposium}", + year = "1999", + publisher = {USENIX Association}, + month = aug, + address = "Washington, D.C., USA", +} + +@inproceedings{wang:gazelle, + author = {Wang, Helen J. and Grier, Chris and Moshchuk, Alexander and King, Samuel T. and Choudhury, Piali and Venter, Herman}, + title = {{The multi-principal OS construction of the Gazelle web browser}}, + booktitle = {Proceedings of the 18th USENIX Security Symposium}, + year = {2009}, + pages = {417--432}, + location = {Montreal, Canada}, + publisher = {USENIX Association}, + address = {Berkeley, CA, USA}, +} + +@inproceedings{remy:ocaml, + author = {R\'{e}my, Didier and Vouillon, J\'{e}r\^{o}me}, + title = {{Objective ML: a simple object-oriented extension of ML}}, + booktitle = {{POPL '97: Proceedings of the 24th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages}}, + year = {1997}, + isbn = {0-89791-853-3}, + pages = {40--53}, + location = {Paris, France}, + doi = {10.1145/263699.263707}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@book{mckusick:freebsd, + author = {McKusick, Marshall Kirk and Neville-Neil, George V. and Watson, + Robert N. M.}, + title = {{The Design and Implementation of the FreeBSD Operating System, + Second Edition}}, + year = {2014}, + publisher = {Pearson Education}, +} + +@misc{ruby, + title = {{Ruby Programming Language}}, + howpublished = {\url{http://www.ruby-lang.org/}}, + author = {{Ruby Users Group}}, + year = 2010, + month = oct, +} + +@inproceedings{trevor:cyclone, + author = {Jim, Trevor and Morrisett, J. Greg and Grossman, Dan and Hicks, Michael W. and Cheney, James and Wang, Yanling}, + title = {Cyclone: A Safe Dialect of~{C}}, + booktitle = {{ATEC '02: Proceedings of the USENIX Annual Technical Conference}}, + year = {2002}, + isbn = {1-880446-00-6}, + pages = {275--288}, + publisher = {USENIX Association}, + address = {Berkeley, CA, USA}, +} + +@inproceedings{cantrill:dtrace, + author = {Cantrill, Bryan M. and Shapiro, Michael W. and Leventhal, Adam H.}, + title = {Dynamic instrumentation of production systems}, + booktitle = {ATEC '04: Proceedings of the USENIX Annual Technical Conference}, + year = {2004}, + location = {Boston, MA}, + publisher = {{USENIX Association}}, + address = {Berkeley, CA, USA}, +} + +@inproceedings{necula:pcc, + author = {Necula, George C. and Lee, Peter}, + title = {Safe kernel extensions without run-time checking}, + booktitle = {OSDI '96: Proceedings of the Second USENIX symposium on Operating Systems Design and Implementation}, + year = {1996}, + isbn = {1-880446-82-0}, + pages = {229--243}, + location = {Seattle, Washington, United States}, + doi = {10.1145/238721.238781}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@inproceedings{yee:nativeclient, + author = {Yee, Bennet and Sehr, David and Dardyk, Gregory and Chen, J. Bradley and Muth, Robert and Ormandy, Tavis and Okasaka, Shiki and Narula, Neha and Fullagar, Nicholas}, + title = {Native Client: A Sandbox for Portable, Untrusted x86 Native Code}, + booktitle = {SP '09: Proceedings of the 2009 30th IEEE Symposium on Security and Privacy}, + year = {2009}, + isbn = {978-0-7695-3633-0}, + pages = {79--93}, + doi = {10.1109/SP.2009.25}, + publisher = {IEEE Computer Society}, + address = {Washington, DC, USA}, +} + +@inproceedings{mccanne:bpf, + author = {McCanne, Steven and Jacobson, Van}, + title = {{The BSD packet filter: a new architecture for user-level packet capture}}, + booktitle = {{USENIX'93: Proceedings of the USENIX Winter 1993 Conference}}, + year = {1993}, + location = {San Diego, California}, + publisher = {USENIX Association}, + address = {Berkeley, CA, USA}, +} + +@inproceedings{bershad:spin, + author = {Bershad, B. N. and Savage, S. and Pardyak, P. and Sirer, E. G. and Fiuczynski, M. E. and Becker, D. and Chambers, C. and Eggers, S.}, + title = {{Extensibility safety and performance in the SPIN operating system}}, + booktitle = {{SOSP '95: Proceedings of the Fifteenth ACM Symposium on Operating Systems Principles}}, + year = {1995}, + isbn = {0-89791-715-4}, + pages = {267--283}, + location = {Copper Mountain, Colorado, United States}, + doi = {10.1145/224056.224077}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@article{myers:difc, + author = {Myers, Andrew C. and Liskov, Barbara}, + title = {A decentralized model for information flow control}, + journal = {SIGOPS Oper. Syst. Rev.}, + volume = {31}, + issue = {5}, + month = oct, + year = {1997}, + issn = {0163-5980}, + pages = {129--142}, + numpages = {14}, + doi = {10.1145/269005.266669}, + acmid = {266669}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@article{efstathopoulos:asbestos, + author = {Efstathopoulos, Petros and Krohn, Maxwell and VanDeBogart, Steve and Frey, Cliff and Ziegler, David and Kohler, Eddie and Mazi\`{e}res, David and Kaashoek, Frans and Morris, Robert}, + title = {Labels and event processes in the asbestos operating system}, + journal = {SIGOPS Oper. Syst. Rev.}, + volume = {39}, + issue = {5}, + month = oct, + year = {2005}, + issn = {0163-5980}, + pages = {17--30}, + numpages = {14}, + doi = {10.1145/1095809.1095813}, + acmid = {1095813}, + publisher = {ACM}, + address = {New York, NY, USA}, + keywords = {event processes, information flow, labels, mandatory access control, secure web servers}, +} + +@inproceedings{zeldovich:histar, + author = {Zeldovich, Nickolai and Boyd-Wickizer, Silas and Kohler, Eddie and Mazi\`{e}res, David}, + title = {Making information flow explicit in {HiStar}}, + booktitle = {Proceedings of the 7th symposium on Operating systems design and implementation}, + series = {OSDI '06}, + year = {2006}, + isbn = {1-931971-47-1}, + location = {Seattle, Washington}, + pages = {263--278}, + numpages = {16}, + url = {http://portal.acm.org/citation.cfm?id=1298455.1298481}, + acmid = {1298481}, + publisher = {USENIX Association}, + address = {Berkeley, CA, USA}, +} + +@inproceedings{boebert:inabilitystar, + title = {On the Inability of an Unmodified Capability Machine to Enforce the *-Property}, + booktitle = {Proc. 7th {{DoD}}/{{NBS Computer Security Conference}}}, + author = {Boebert, William Earl}, + date = {1984-09}, + pages = {291--293}, + url = {https://csrc.nist.gov/CSRC/media/Publications/conference-paper/1984/09/24/7th-dod-nbs-computer-security-conference/documents/1984-7th-conference-proceedings.pdf}, + eventtitle = {{{DoD}}/{{NBS Computer Security Conference}}} +} + + +@article{hardy:keykos, + author = {Hardy, Norman}, + title = {{KeyKOS architecture}}, + journal = {SIGOPS Operating Systems Review}, + volume = {19}, + number = {4}, + year = {1985}, + issn = {0163-5980}, + pages = {8--25}, + doi = {10.1145/858336.858337}, + publisher = {ACM}, + address = {New York, NY, USA}, + note = {Also available at \url{http://cap-lore.com/CapTheory/upenn/OSRpaper.html}} +} + +@inproceedings{shapiro:eros, +author = {Jonathan Shapiro and Jonathan Smith and David Farber}, +booktitle = {{SOSP '99: Proceedings of the seventeenth ACM Symposium on Operating Systems Principles}}, +title = {{EROS: a fast capability system}}, +abstract = {EROS is a capability-based operating system for commodity processors which uses a single level storage model. The single level store's persistence is transparent to applications. The performance consequences of support for transparent persistence and ...}, +year = {1999}, +month = dec, +pmid = {319151.319163}, +url = {http://portal.acm.org/citation.cfm?id=319151.319163}, +howpublished = {\url{http://portal.acm.org/citation.cfm?id=319151.319163}}, +} + +@misc{shapiro:coyotosspec, + author={Jonathan S. Shapiro and Jonathan W. Adams}, + title={Coyotos Microkernel Specification}, + subtitle={Version 0.6+}, + date={2007-09-10}, + url={https://web.archive.org/web/20160904092954/http://www.coyotos.org:80/docs/ukernel/spec.html} +} + +@inproceedings{mettler:joee, + author = {Mettler, Adrian and Wagner, David}, + title = {{Class properties for security review in an object-capability subset of Java}}, + booktitle = {PLAS '10: Proceedings of the 5th ACM SIGPLAN Workshop on Programming Languages and Analysis for Security}, + year = {2010}, + isbn = {978-1-60558-827-8}, + pages = {1--7}, + location = {Toronto, Canada}, + doi = {10.1145/1814217.1814224}, + publisher = {ACM}, + address = {New York, NY, USA}, + } + +@misc{miller:elang, + author = {Mark S. Miller}, + title = {The E Language}, + note = "\url{http://www.erights.org/}", +} + +@misc{miller:caja, + author = {Mark S. Miller and Mike Samuel and Ben Laurie and Ihab Awad and Mike Stay}, + title = {Caja: Safe active content in Sanitized JavaScript}, + month = may, + year = {2008}, + institution = {Google}, + url = {http://google-caja.googlecode.com/files/caja-spec-2008-06-07.pdf}, + note = "\url{http://google-caja.googlecode.com/files/caja-spec-2008-06-07.pdf}", +} + +@article{miller:capmyths, + title = {Capability {Myths} {Demolished}}, + abstract = {We address three common misconceptions about capability-based systems: the Equivalence Myth (access control list systems and capability systems are formally equivalent), the Confinement Myth (capability systems cannot enforce confinement), and the Irrevocability Myth (capability-based access cannot be revoked). The Equivalence Myth obscures the benefits of capabilities as compared to access control lists, while the Confinement Myth and the Irrevocability Myth lead people to see problems with capabilities that do not actually exist.}, + language = {en}, + author = {Miller, Mark S and Yee, Ka-Ping and Shapiro, Jonathan}, + pages = {15}, + url = {http://srl.cs.jhu.edu/pubs/SRL2003-02.pdf} +} + +@article{miller:paradigmregained, + address = {Berlin, Heidelberg}, + title = {Paradigm {Regained}: {Abstraction} {Mechanisms} for {Access} {Control}}, + isbn = {978-3-540-40965-6}, + abstract = {Access control systems must be evaluated in part on how well they enable one to distribute the access rights needed for cooperation, while simultaneously limiting the propagation of rights which would create vulnerabilities. Analysis to date implicitly assumes access is controlled only by manipulating a system's protection state – the arrangement of the access graph. Because of the limitations of this analysis, capability systems have been ”proven” unable to enforce some basic policies: revocation, confinement, and the *-properties (explained in the text).}, + booktitle = {Advances in {Computing} {Science} – {ASIAN} 2003. {Progamming} {Languages} and {Distributed} {Computation} {Programming} {Languages} and {Distributed} {Computation}}, + publisher = {Springer Berlin Heidelberg}, + author = {Miller, Mark S. and Shapiro, Jonathan S.}, + editor = {Saraswat, Vijay A.}, + year = {2003}, + pages = {224--242}, + url = {http://www.erights.org/talks/asian03/} +} + +@phdthesis{miller:robustcomposition, + author = {Miller, Mark Samuel}, + title = {Robust composition: towards a unified approach to access control and concurrency control}, + year = {2006}, + order_no = {AAI3245526}, + school = {Johns Hopkins University}, + address = {Baltimore, MD, USA}, +} + +@book{gosling:javalanguage, + author = {Gosling, James and Joy, Bill and Steele, Guy L.}, + title = {The Java Language Specification}, + year = {1996}, + isbn = {0201634511}, + publisher = {Addison-Wesley Longman Publishing Co., Inc.}, + address = {Boston, MA, USA}, +} + +@inproceedings{lipner:securitykernels, + author = {Lipner, Steven B. and Wulf, William A. and Schell, Roger R. and Popek, Gerald J. and Neumann, Peter G. and Weissman, Clark and Linden, Theodore A.}, + title = {Security kernels}, + booktitle = {AFIPS '74: Proceedings of the May 6-10, 1974, National Computer Conference and Exposition}, + year = {1974}, + pages = {973--980}, + location = {Chicago, Illinois}, + doi = {10.1145/1500175.1500361}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@inproceedings{ackerman:multiprocessing, + author = {Ackerman, William B. and Plummer, William W.}, + title = {An implementation of a multiprocessing computer system}, + booktitle = {SOSP '67: Proceedings of the First ACM Symposium on Operating System Principles}, + year = {1967}, + pages = {5.1--5.10}, + doi = {10.1145/800001.811666}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@article{ritchie:unix, + author = {Ritchie, Dennis M. and Thompson, Ken}, + title = {{The UNIX time-sharing system}}, + journal = {Communications of the ACM}, + volume = {17}, + number = {7}, + year = {1974}, + issn = {0001-0782}, + pages = {365--375}, + doi = {10.1145/361011.361061}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@article{denning:faulttolerance, + author = {Denning, Peter J.}, + title = {Fault Tolerant Operating Systems}, + journal = {ACM Computing Surveys}, + volume = {8}, + number = {4}, + year = {1976}, + issn = {0360-0300}, + pages = {359--389}, + doi = {10.1145/356678.356680}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@inproceedings{patterson:risc, + author = {Patterson, David A. and Sequin, Carlo H.}, + title = {{RISC I: A Reduced Instruction Set VLSI Computer}}, + booktitle = {ISCA '81: Proceedings of the 8th Annual Symposium on Computer Architecture}, + year = {1981}, + pages = {443--457}, + location = {Minneapolis, Minnesota, United States}, + publisher = {IEEE Computer Society Press}, + address = {Los Alamitos, CA, USA}, + } + +@inproceedings{corbato:multics, + author = {Corbat\'{o}, F. J. and Vyssotsky, V. A.}, + title = {{Introduction and overview of the Multics system}}, + booktitle = {AFIPS '65 (Fall, part I): Proceedings of the November 30--December 1, 1965, Fall Joint Computer Conference, part I}, + year = {1965}, + pages = {185--196}, + location = {Las Vegas, Nevada}, + doi = {10.1145/1463891.1463912}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@inproceedings{corbato:timesharing, + author = {Corbat\'{o}, Fernando J. and Merwin-Daggett, Marjorie and Daley, Robert C.}, + title = {An experimental time-sharing system}, + booktitle = {AIEE-IRE '62 (Spring): Proceedings of the May 1--3, 1962, Spring Joint Computer Conference}, + year = {1962}, + pages = {335--344}, + location = {San Francisco, California}, + doi = {10.1145/1460833.1460871}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@article{dennis:semantics, + author = {Dennis, Jack B. and Van Horn, Earl C.}, + title = {Programming semantics for multiprogrammed computations}, + journal = {Communications of the ACM}, + volume = {9}, + number = {3}, + year = {1966}, + issn = {0001-0782}, + pages = {143--155}, + doi = {10.1145/365230.365252}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@inproceedings{reis:chromium, + author = {Reis, Charles and Gribble, Steven D.}, + title = {Isolating web programs in modern browser architectures}, + booktitle = {EuroSys '09: Proceedings of the 4th ACM European Conference on Computer Systems}, + year = {2009}, + isbn = {978-1-60558-482-9}, + pages = {219--232}, + location = {Nuremberg, Germany}, + doi = {10.1145/1519065.1519090}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@inproceedings{provos:preventingprivesc, +author = {Neils Provos and Markus Friedl and Peter Honeyman}, +booktitle = {{Proceedings of the 12th USENIX Security Symposium}}, +title = {{Preventing Privilege Escalation}}, +year = {2003}, + publisher = {USENIX Association}, +} + +@inproceedings{bittau:wedge, +author = {Andrea Bittau and Petr Marchenko and Mark Handley and Brad Karp}, +booktitle = {{Proceedings of the 5th USENIX Symposium on Networked Systems Design and Implementation}}, +title = {{Wedge: Splitting Applications into Reduced-Privilege Compartments}}, +school = {University College London}, +pages = {309--322},year = {2008}, +url = {http://www.cs.ucl.ac.uk/staff/m.handley/papers/wedge.pdf}, +howpublished = {\url{http://www.cs.ucl.ac.uk/staff/m.handley/papers/wedge.pdf}}, + publisher = {USENIX Association}, +} + +@techreport{accetta:mach, + author = "M. Accetta and R. Baron and D. Golub and R. Rashid and A. + Tevanian and M. Young", + institution = "{Computer Science Department, Carnegie Mellon + University}", + title = "{Mach: A New Kernel Foundation for UNIX Development}", + year = "1986", + month = aug, +} + +@InProceedings{liedtke:l4, + author = {Jochen Liedtke}, + title = {On Microkernel Construction}, + booktitle = {SOSP'95: Proceedings of the + 15th ACM Symposium on Operating System Principles}, + address = {Copper Mountain Resort, CO}, + month = dec, + year = 1995, + url = {http://l4ka.org/publications/} +} + +@book{levy:capabilities, + author = {Levy, Henry M.}, + title = {Capability-Based Computer Systems}, + year = {1984}, + isbn = {0932376223}, + publisher = {Butterworth-Heinemann}, + address = {Newton, MA, USA}, + } + +@inproceedings{yee:nacl, + author = {Yee, Bennet and Sehr, David and Dardyk, Gregory and Chen, J. Bradley and Muth, Robert and Ormandy, Tavis and Okasaka, Shiki and Narula, Neha and Fullagar, Nicholas}, + title = {Native Client: A Sandbox for Portable, Untrusted x86 Native Code}, + booktitle = {Proceedings of the 2009 30th IEEE Symposium on Security and Privacy}, + year = {2009}, + isbn = {978-0-7695-3633-0}, + pages = {79--93}, + numpages = {15}, + url = {http://portal.acm.org/citation.cfm?id=1607723.1608126}, + doi = {10.1109/SP.2009.25}, + acmid = {1608126}, + publisher = {IEEE Computer Society}, + address = {Washington, DC, USA}, + keywords = {Security, World Wide Web}, +} + +@inproceedings{wahbe:sfi, + author = {Wahbe, Robert and Lucco, Steven and Anderson, Thomas E. and Graham, S +usan L.}, + title = {Efficient software-based fault isolation}, + booktitle = {SOSP '93: Proceedings of the Fourteenth ACM Symposium on Operating + Systems Principles}, + year = {1993}, + isbn = {0-89791-632-8}, + pages = {203--216}, + location = {Asheville, North Carolina, United States}, doi = {10.1145/168619.168635}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@article{richards:bluespecreasoning, + author = {Richards, Dominic and Lester, David}, + affiliation = {School of Computer Science, The University of Manchester, Manchester, UK}, + title = {{A monadic approach to automated reasoning for Bluespec SystemVerilog}}, + journal = {Innovations in Systems and Software Engineering}, + publisher = {Springer London}, + issn = {1614-5046}, + keyword = {Computer Science}, + pages = {1-11}, + note = {10.1007/s11334-011-0149-0}, + year = {2011} +} + +@InProceedings{NeumannWatson10LAW, +Author={Peter G. Neumann and Robert N.~M. Watson}, +Title={Capabilities Revisited: A Holistic Approach to + Bottom-to-Top Assurance of Trustworthy Systems}, +BookTitle={Fourth Layered Assurance Workshop}, +Organization={U.S. Air Force Cryptographic Modernization Office and AFRL}, +Address={Austin, Texas}, +Year={2010}, Month=dec, pages={}, Note = + {http://www.csl.sri.com/neumann/law10.pdf}} + +@InProceedings{Watson07, +Author={Robert N.~M. Watson}, +Title={Exploiting Concurrency Vulnerabilities in System Call Wrappers}, +BookTitle={WOOT Workshop}, +Organization={USENIX Security}, Address={Gaithersburg, Maryland}, +Year={2007}, Month={}, pages={}, Note = { + http://www.watson.org/~robert/2007woot/20070806-woot-concurrency.pdf}} + +@PhdThesis{Drimer10, + author = {Saar Drimer}, + title = {Security for Volatile FPGAs}, + school = {University of Cambridge}, + year = {2010} } + +@inproceedings{Cadar:2008:KUA:1855741.1855756, + author = {Cadar, Cristian and Dunbar, Daniel and Engler, Dawson}, + title = {{KLEE}: unassisted and automatic generation of high-coverage tests for complex systems programs}, + booktitle = {Proceedings of the 8th USENIX conference on operating systems design and implementation}, + series = {OSDI'08}, + year = {2008}, + location = {San Diego, California}, + pages = {209--224}, + numpages = {16}, + url = {http://portal.acm.org/citation.cfm?id=1855741.1855756}, + acmid = {1855756}, + publisher = {USENIX Association}, + address = {Berkeley, CA, USA}, +} + +@inproceedings{Yanagisawa:2006:DAS:1173706.1173717, + author = {Yanagisawa, Yoshisato and Kourai, Kenichi and Chiba, Shigeru}, + title = {A dynamic aspect-oriented system for {OS} kernels}, + booktitle = {Proceedings of the 5th international conference on Generative programming and component engineering}, + series = {GPCE '06}, + year = {2006}, + isbn = {1-59593-237-2}, + location = {Portland, Oregon, USA}, + pages = {69--78}, + numpages = {10}, + doi = {10.1145/1173706.1173717}, + acmid = {1173717}, + publisher = {ACM}, + address = {New York, NY, USA}, + keywords = {Linux, aspect-oriented programming, dynamic AOP, operating system, profiling and debugging}, +} + +@article{Nethercote:2007:VFH:1273442.1250746, + author = {Nethercote, Nicholas and Seward, Julian}, + title = {Valgrind: a framework for heavyweight dynamic binary instrumentation}, + journal = {SIGPLAN Not.}, + volume = {42}, + issue = {6}, + month = jun, + year = {2007}, + issn = {0362-1340}, + pages = {89--100}, + numpages = {12}, + doi = {10.1145/1273442.1250746}, + acmid = {1250746}, + publisher = {ACM}, + address = {New York, NY, USA}, + keywords = {Memcheck, Valgrind, dynamic binary analysis, dynamic binary instrumentation, shadow values}, +} + +@INPROCEEDINGS{Weimer05miningtemporal, + author = {Westley Weimer and George C. Necula}, + title = {Mining Temporal Specifications for Error Detection}, + booktitle = {In TACAS}, + year = {2005}, + pages = {461--476} +} + + +@inproceedings{muvi:sosp2007, + author = "Shan Lu and Soyeon Park and Chongfeng Hu and Xiao Ma and Weihang Jiang and Zhenmin Li and Raluca A. Popa and Yuanyuan Zhou", + title = "MUVI: Automatically Inferring Multi-Variable Access Correlations and Detecting Related Semantic and Concurrency Bugs", + booktitle = "Proceedings of the 21st ACM Symposium on Operating Systems Principles (SOSP07)", + month = oct, + year = "2007", +} + + +@misc{rfc4252, + author="T. Ylonen and C. Lonvick", + title="{The Secure Shell (SSH) Authentication Protocol}", + series="Request for Comments", + number="4252", + howpublished="RFC 4252 (Proposed Standard)", + publisher="IETF", + organisation="Internet Engineering Task Force", + year=2006, + month=jan, + url="http://www.ietf.org/rfc/rfc4252.txt", +} + +@article{Bishop:2005:RSC:1090191.1080123, + author = {Bishop, Steve and Fairbairn, Matthew and Norrish, Michael and Sewell, Peter and Smith, Michael and Wansbrough, Keith}, + title = {Rigorous specification and conformance testing techniques for network protocols, as applied to {TCP}, {UDP}, and sockets}, + journal = {SIGCOMM Comput. Commun. Rev.}, + issue_date = {October 2005}, + volume = {35}, + issue = {4}, + month = aug, + year = {2005}, + issn = {0146-4833}, + pages = {265--276}, + numpages = {12}, + doi = {10.1145/1090191.1080123}, + acmid = {1080123}, + publisher = {ACM}, + address = {New York, NY, USA}, + keywords = {API, HOL, TCP/IP, conformance testing, higher-order logic, network protocols, operational semantics, sockets, specification}, +} + +@inproceedings{Madhavapeddy:2009:CSM:1695271.1695302, + author = {Madhavapeddy, Anil}, + title = {Combining Static Model Checking with Dynamic Enforcement Using the Statecall Policy Language}, + booktitle = {Proceedings of the 11th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering}, + series = {ICFEM '09}, + year = {2009}, + isbn = {978-3-642-10372-8}, + location = {Rio de Janeiro, Brazil}, + pages = {446--465}, + numpages = {20}, + doi = {10.1007/978-3-642-10373-5_23}, + acmid = {1695302}, + publisher = {Springer-Verlag}, + address = {Berlin, Heidelberg}, +} + +@inproceedings{Baldwin:2002:LMF:1250894.1250898, + author = {Baldwin, John H.}, + title = {Locking in the multithreaded {FreeBSD} kernel}, + booktitle = {Proceedings of the BSD Conference 2002}, + series = {BSDC'02}, + year = {2002}, + location = {San Francisco, California}, + pages = {4--4}, + numpages = {1}, + url = {http://portal.acm.org/citation.cfm?id=1250894.1250898}, + acmid = {1250898}, + publisher = {USENIX Association}, + address = {Berkeley, CA, USA}, +} + +@inproceedings{LA04, + title = {{{LLVM}}: {{A Compilation Framework}} for {{Lifelong Program Analysis}} \& {{Transformation}}}, + shorttitle = {{{LLVM}}}, + booktitle = {Proceedings of the {{International Symposium}} on {{Code Generation}} and {{Optimization}}: {{Feedback}}-Directed and {{Runtime Optimization}}}, + author = {Lattner, Chris and Adve, Vikram}, + date = {2004-03}, + pages = {75--86}, + publisher = {{IEEE Computer Society}}, + location = {{Washington, DC, USA}}, + doi = {10.1109/CGO.2004.1281665}, + url = {http://dl.acm.org/citation.cfm?id=977395.977673}, + abstract = {This paper describes LLVM (Low Level Virtual Machine),a compiler framework designed to support transparent, lifelongprogram analysis and transformation for arbitrary programs,by providing high-level information to compilertransformations at compile-time, link-time, run-time, and inidle time between runs.LLVM defines a common, low-levelcode representation in Static Single Assignment (SSA) form,with several novel features: a simple, language-independenttype-system that exposes the primitives commonly used toimplement high-level language features; an instruction fortyped address arithmetic; and a simple mechanism that canbe used to implement the exception handling features ofhigh-level languages (and setjmp/longjmp in C) uniformlyand efficiently.The LLVM compiler framework and coderepresentation together provide a combination of key capabilitiesthat are important for practical, lifelong analysis andtransformation of programs.To our knowledge, no existingcompilation approach provides all these capabilities.We describethe design of the LLVM representation and compilerframework, and evaluate the design in three ways: (a) thesize and effectiveness of the representation, including thetype information it provides; (b) compiler performance forseveral interprocedural problems; and (c) illustrative examplesof the benefits LLVM provides for several challengingcompiler problems.}, + isbn = {978-0-7695-2102-2}, + series = {{{CGO}} '04}, + venue = {Palo Alto, California} +} + +@misc{rfc793, + author="J. Postel", + title="{Transmission Control Protocol}", + series="Request for Comments", + number="793", + howpublished="RFC 793 (Standard)", + publisher="IETF", + organisation="Internet Engineering Task Force", + year=1981, + month=sep, + day="1", + note="Updated by RFC 3168", + url="http://www.ietf.org/rfc/rfc793.txt", +} + +@inproceedings{BR02, + author = {Ball, Thomas and Rajamani, Sriram K.}, + title = {The {SLAM} project: debugging system software via static analysis}, + booktitle = {Proceedings of the 29th ACM SIGPLAN-SIGACT symposium on Principles of programming languages}, + series = {POPL '02}, + year = {2002}, + isbn = {1-58113-450-9}, + location = {Portland, Oregon}, + pages = {1--3}, + numpages = {3}, + doi = {10.1145/503272.503274}, + acmid = {503274}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@inproceedings{CS04, + author = {Cantrill, Bryan M. and Shapiro, Michael W. and Leventhal, Adam H.}, + title = {Dynamic instrumentation of production systems}, + booktitle = {Proceedings of the USENIX Annual Technical Conference}, + series = {ATEC '04}, + year = {2004}, + location = {Boston, MA}, + pages = {2--2}, + numpages = {1}, + url = {http://portal.acm.org/citation.cfm?id=1247415.1247417}, + acmid = {1247417}, + publisher = {USENIX Association}, + address = {Berkeley, CA, USA}, +} + +@inproceedings{HJ02, +Address = {London, UK}, +Author = {Thomas A. Henzinger and Ranjit Jhala and Rupak Majumdar and George C. Necula and Gr\&\#233;goire Sutre and Westley Weimer}, +Booktitle = {Proceedings of the 14th International Conference on Computer Aided Verification (CAV)}, +Date-Added = {2005-11-09 11:43:39 +0000}, +Date-Modified = {2005-11-09 11:44:40 +0000}, +Isbn = {3-540-43997-8}, +Keywords = {security,systems}, +Pages = {526--538}, +Publisher = {Springer-Verlag}, +Title = {Temporal-Safety Proofs for Systems Code}, +Year = {2002}} + +@TechReport{BP81, +author={K.H. Britton and D.L. Parnas}, +Title={A-7E Software Module Guide}, +institution= {NRL Memorandum Report 4702, Naval Research Laboratory}, +address={Washington, D.C.}, month =dec, Year=1981 } + +@InProceedings{CCMT93, +Author = "G. Canfora and A. Cimitile and M. Munro and C. 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Snelting}, +TITLE = {Reengineering of Configurations based on Mathematical Concept Analysis}, +JOURNAL = {IEEE Transactions on Software Engineering and Methodology}, +YEAR = {1996}, VOLUME = {5}, +NUMBER = {2}, PAGES = {146--189}, MONTH = {} } + +@InProceedings{ST98, +Author = "G. Snelting and F. Tip", +Title = "Reengineering Class Hierarchies Using Concept Analysis", +Booktitle = "Proceedings of the International Symposium on Foundations of + Software Engineering", +Organization = "", Address = "", Year = "1998", +Pages="", Month = "" } + +@InProceedings{SH89, +Author = "G. Snider and J. Hays", +Title = "The Modix Kernel", +Booktitle = "1989 Winter USENIX Conference Proceedings", +Organization = "", Address = "San Diego, California", Year = "1989", +Pages="377--392", Month = feb } + +@ARTICLE{T01, +Author={P. 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Neumann}, +School={Department of Applied Mathematics, Harvard University}, +Title={Efficient Error-Limiting Variable-Length Codes}, +Year={1961}, Month=may, +Note ={Published as report BL-28, + Theory of Switching, The Computation Laboratory, Harvard University.}} + +@Book{Neumann60, +Author={P.G. Neumann}, +Publisher={Thesis for Dr rerum naturum degree, + Department of Mathematics and Physics, Technische Hochschule, + Darmstadt, Germany}, +Title={Funktionale Prefixcodes als Grundlage der praktischen + Verschul\"{u}sselung}, +Year={1960}, Month=jun} + +@ARTICLE{NeumannRao75, +Author={P.G. Neumann and T.R.N. Rao}, +TITLE = {Error Correction Codes for Byte-Organized Arithmetic Processors}, +JOURNAL = {IEEE Transactions on Computers}, YEAR = {1975}, VOLUME = {C-24}, +NUMBER = {3}, PAGES = {226-232}, MONTH = mar } + +@ARTICLE{Neumann62a, +Author={P.G. Neumann}, +TITLE = {Efficient Error-Limiting Variable-Length Codes}, +JOURNAL = {IRE Transactions on Information Theory}, +YEAR = {1962}, VOLUME = {IT-8}, +NUMBER = {}, PAGES = {292-304}, MONTH = jul } + +@ARTICLE{Neumann62b, +Author={P.G. Neumann}, +TITLE = {On a Class of Efficient Error-Limiting Variable-Length Codes}, +JOURNAL = {IRE Transactions on Information Theory}, YEAR = {1962}, +VOLUME = {IT-8}, +NUMBER = {}, PAGES = {S260-266}, MONTH = sep } + +@ARTICLE{Neumann63, +Author={P.G. Neumann}, TITLE = {On Error-Limiting Variable-Length Codes}, +JOURNAL = {IEEE Transactions on Information Theory}, YEAR = {1963}, +VOLUME = {IT-9}, NUMBER = {}, PAGES = {209}, MONTH = jul } + +@ARTICLE{Neumann64, +Author={P.G. Neumann}, +TITLE = {Error-Limiting Coding Using Information-Lossless Sequential Machines}, +JOURNAL = {IEEE Transactions on Information Theory}, +YEAR = {1964}, VOLUME = {IT-10}, +NUMBER = {}, PAGES = {108-115}, MONTH = apr } + +@ARTICLE{Neumann65, +Author={P.G. Neumann}, +TITLE = {A Note on {Gilbert} Burst-Correcting Codes}, +JOURNAL = {IEEE Transactions on Information Theory}, +YEAR = {1965}, VOLUME = {IT-11}, +NUMBER = {}, PAGES = {377-384}, MONTH = jul } + +@article{Mealy55, +Key = {Mealy}, Author = {G.H. Mealy}, +Title = {A method for synthesizing sequential circuits}, +journal = {Bell System Technical Journal}, year = {1955}, volume = {34}, +number = {}, pages = {1045--79}, month = sep } + +@TechReport{Baron+87, +Key={Baron}, Author={R. {Baron et al.}}, Title={Mach Kernel Interface Manual}, +Institution={Computer Science Department, Carnegie-Mellon University, +Pittsburgh, Pennsylvania}, Month=apr, Year=1987 } + +@InProceedings{BranstadTMachDesign87, Author={M.A. Branstad and P.S. Cochrane +and H. Orman and J. Landauer and T. Parenty and T. Haley and D. Dalva and D. +Baggett}, Title={Trusted {M}ach Design Issues}, Booktitle={Proceedings of +the Third Aerospace Computer Security Applications Conference}, +Month=dec, Year=1987 } + +@InProceedings{Branstad+87, Author={M.A. Branstad and P.S. Cochrane and H. +Orman and J. Landauer and T. Parenty and T. Haley and D. Dalva and D. Baggett}, +Title={Trusted {M}ach Design Issues}, Booktitle={Proceedings of the Third +Aerospace Computer Security Applications Conference}, Month=dec, +Year=1987 } + +@inproceedings{Branstad+89, +author={M.A. Branstad and H. Tajalli and F. Mayer and +D. Dalva}, title={Access Mediation in a Message Passing Kernel}, +booktitle={Proceedings of the IEEE Symposium on Security and Privacy}, +address={Oakland, California}, pages={66--72}, month=may, year=1989 } + +@InProceedings{BranstadSecurityTMach88, +Author={M.A. Branstad and H. Tajalli and F. Mayer}, +Title={Security Issues of the {T}rusted {M}ach System}, +Booktitle={Proceedings of the Fourth Aerospace Computer Security Applications Conference}, +Month=dec, +Year=1988 } + +@InProceedings{xBranstadAccessMed88, +Author={M.A. Branstad and F.L. Mayer}, +Title={Access Mediation in Server-Oriented Systems: An Examination of Two Systems}, +Booktitle={Proceedings of the Eleventh National Computer Security Conference}, +Month=oct, +Year=1988 } + +@InProceedings{BranstadMayer88Server, +Author={M.A. Branstad and F.L. Mayer}, +Title={Access Mediation in Server-Oriented Systems: An Examination of Two +Systems}, Booktitle={Proceedings of the Eleventh National Computer Security +Conference}, Month=oct, Year=1988 } + +@TechReport{xBranstadMayer88ServerReport, +Author={M.A. Branstad and F.L. Mayer}, key ={Branstad}, +title={Access Mediation in Server-Oriented Systems: An Examination of Two Systems}, +institution={Trusted Information Systems, Inc., Glenwood, Maryland}, +number={Report 159}, +month=feb, year={1988} } + +@TechReport{Branstad88Extensions, +Author={M.A. {Branstad et al.}}, key ={Branstad}, +title={Trust Extensions to the {M}ach Message Passing System}, +institution={Trusted Information Systems, Inc., Glenwood, Maryland}, number={}, +year={1988} } + +@TechReport{TMachKernel89, +Author={D.I. Dalva}, +title={Mach Kernel Modifications for the Implementation of the Security Policy}, +institution={Trusted Information Systems, Inc., Glenwood, Maryland}, number={}, +year={1988}, day={19}, month=sep } + +@TechReport{TMachName89, +Author={H. Tajalli and J. Graham}, +title={Trusted {Mach} Name Server Interface Document}, +institution={Trusted Information Systems, Inc., Glenwood, Maryland}, number={}, +year={1988}, day={15}, month=sep } + +@TechReport{TMachFile89, +Author={J. Graham}, +title={Trusted {Mach} File Server Interface Document}, +institution={Trusted Information Systems, Inc., Glenwood, Maryland}, number={}, +year={1988}, day={15}, month=sep } + +@TechReport{TMachAudit89, +Author={J. Graham}, +title={Trusted {Mach} Audit Server Interface Document}, +institution={Trusted Information Systems, Inc., Glenwood, Maryland}, number={}, +year={1988}, day={19}, month=sep } + +@TechReport{TMachVerif89, +Author={K.D. Hendriksen and J. Graham}, +title={Trusted {Mach} Verification Server Interface Document}, +institution={Trusted Information Systems, Inc., Glenwood, Maryland}, number={}, +year={1988}, day={15}, month=sep } + +@TechReport{TMachShell89, +Author={D. Baggett and J. Graham}, +title={Trusted {Mach} Trusted Shell and Trusted Administrator Shell +Administrator's Guide}, +institution={Trusted Information Systems, Inc., Glenwood, Maryland}, number={}, +year={1988}, day={30}, month={August} } + +@inproceedings{BranstadLandauer89, +author={M.A. Branstad and J. Landauer}, +title={Assurance for the {Trusted Mach} Operating System}, +BookTitle={Proceedings of the Fourth Annual Conference on Computer +Assurance COMPASS '89}, Organization={IEEE}, Month=jun, year={1989}, +Pages={9--13}} + +@TechReport{RomulusIntegrity91, +Author={}, key ={Rome Laboratory}, +title={Romulus Theories of Integrity}, +institution={Rome Laboratory}, +number={}, +year={1991}, month=oct } + +@TechReport{Feiertag90DTMach, +Author={E.J. Sebes and R.J. Feiertag}, key ={Sebes}, +title={Distributed {Trusted Mach} Concept Exploration}, +institution={Rome Laboratory}, +number={RL-TR-91-246}, +year={1991}, month=sep, NOTE={Final Technical Report.} } + +@InProceedings{Cronus86, +Author={R. Schantz and R. Thomas and G. Bono}, +Title={The Architecture of the {C}ronus Distributed Operating System}, +Booktitle={Proceedings of the {IEEE} Sixth International Conference on +Distributed Computing Systems}, Month=may, Year={1986}, pages={250--259} } + +@TechReport{Cronus88, +Author={BBN}, Title={Cronus System/Subsystem Specification}, +Institution={5884 Revision 1.7, BBN Communications Corp.}, +Month=jan, Year={1989}} + +@Book{Firschein, +Author="O. Firschein and M.P. Georgeff and W. Park and P. +Cheeseman and J. Goldberg and P.G. Neumann and W.H. Kautz and K.N. Levitt and +R.J. Rom and A.A. Poggio", Title="Artificial Intelligence for {S}pace {S}tation +Automation: Crew Safety, Productivity, Autonomy, Augmented Capability", +Publisher= "Noyes, Park Ridge NJ", Key="Firschein", Year="1986", Note="(This +book is a verbatim copy of an SRI report, ``NASA Space Station Automation: +AI-Based Technology Review'', May 1985.)" } + +@InProceedings{Barton63, +Author={R.S. Barton}, +Title={A Critical Review of the State of the Programming Art}, +Booktitle={Proceedings of the Spring Joint Computer Conference}, +volume=23, +publisher={AFIPS Press}, +address={Montvale, New Jersey}, +Month =may, +Year=1963, +pages = {169--177} } + +@inProceedings{DaleyNeumann, +key="Daley", Author="Robert C. Daley and Peter G. Neumann", +Title="A General-Purpose File System for Secondary Storage", +Booktitle="{AFIPS} Conference Proceedings, Fall Joint Computer Conference", +Publisher="Spartan Books", Year="1965", Month=nov, Pages="213--229"} + +@InProceedings{Neumann69, +Key = {}, Author = {P.G. Neumann}, +Title = {The Role of Motherhood in the Pop Art of System Programming}, +Booktitle = {Proceedings of the {ACM} Second Symposium on Operating Systems +Principles, Princeton, New Jersey}, +Organization = {ACM}, Address = {}, Year = {1969}, +Pages={13--18}, Month = oct, +Note = {http://www.multicians.org/pgn-motherhood.html} +} + +@inProceedings{Neumann71, +key="Neumann",Author="P.G. Neumann", Title="System +Design for Computer Networks", Booktitle="Computer-Communication Networks +(Chapter 2)", Note ="N. Abramson and F.F. Kuo (editors)", Publisher = +"Prentice-Hall",Year="1971",Pages="29--81"} + +@Book{AbramsonKuo, +Author="N. Abramson and F.F. Kuo (editors.)", +Title="Computer-Communication Networks", +Publisher = "Prentice-Hall",Year="1971"} + +@TechReport{ARPA73, +Key="Neumann", Author="P.G. Neumann and J. Goldberg and +K.N. Levitt and J.H. Wensley", Title="A Study of Fault-Tolerant Computing", +Institution="Stanford Research Institute, Menlo Park, California", +Year="1973", Month=jul, +Type="Final Report for {ARPA}, {AD} 766 974"} + +@InProceedings{CAPRI, +Author="P.G. Neumann", +Title="Experiences with Formality in Software Development", +Booktitle="Theory and Practice of Software Technology", +Note ="D. Ferrari, M. Bolognani, and J. Goguen (editors)", +Publisher = "North-Holland",Year="1983",Pages="203--219", +Note="Reprinted in Rein Turn, editor, {\it Advances in Computer Security}, +Volume 2, Artech House, 1984."} + +@inProceedings{ZEN, +Author="P.G. Neumann", +Title="Psychosocial Implications of Computer Software Development and +Use: Zen and the Art of Computing", +Booktitle="Theory and Practice of Software Technology", +Note ="D. Ferrari, M. Bolognani, and J. Goguen (editors).", +Publisher = "North-Holland", +Year="1983", Pages="221--232"} + +@book{LeeTiger, +Author={M. Lee and E. Lee and J. Johnstone}, +Title={Ride the Tiger to the Mountain}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={1989} } + +@BOOK{LeeTigerx, +Note={ISBN 0-201-18077-4.} } + +@TechReport{RADC81, +Key="Lamport", Author="L. Lamport and W.H. Kautz and P.G. +Neumann and R.L. Schwartz and P.M. Melliar-Smith", Title="Formal Techniques for +Fault Tolerance in Distributed Data Processing", +Institution="Computer Science Laboratory, SRI International, Menlo Park, +California", Year="1981", Month=apr, +Note="For Rome Air Development Center"} + +@TechReport{NeumannLamport83, +Key="Neumann", Author="P.G. Neumann and L. Lamport", +Title="Highly Dependable Distributed Systems", +Institution="Computer Science Laboratory, SRI International, Menlo Park, +California", Year="1983", Month=jun, +Note="Final Report, Contract No. DAEA18-81-G-0062, for U.S. Army CECOM."} + +@TechReport{Neumann+lamportXXX, + Key={Neumann}, + Author={P.G. Neumann and L. Lamport}, + Institution={Computer Science Laboratory, SRI International}, + Title={Highly Dependable Distributed Systems}, + Year={1983}, + Month=jun, + Type={Final Report, Contract No. DAEA18-81-G-0062} + } + +@Article{Neumann86, +Title="On Hierarchical Design of Computer Systems for Critical Applications", +Author="P.G. Neumann", +Journal="{IEEE} Transactions on Software Engineering", +Year="1986", Volume="SE-12", Number="9", Month=sep, +Page="905--920",Key="Neumann", +Note="Reprinted in Rein Turn, editor, {\it Advances in +Computer System Security}, Vol. 3, Artech House, Dedham, Massachusetts, 1988" } + +@InProceedings{Neely, + Key="Neely", Author="R.B. Neely and J.W. Freeman", + BookTitle="Proc. 1985 Symposium on Security and Privacy", + Organization="IEEE Computer Society", + Title="Structuring Systems for Formal Verification", + Address="Oakland, California", Year="1985", Month=apr, pages=""} + +@article{Ames83, +Key="Ames", +author = "S.R. {Ames Jr.} and M. Gasser and R.R. Schell", +title = "Security Kernel Design and Implementation: An Introduction", +Month=jul, Year="1983", Journal="IEEE Computer", Volume="16", Number="7", +Pages="14-22"} + +@article{Schell83, +Key="Schell", author = "R. Schell", +title = "A Security Kernel for a Multiprocessor Microcomputer", +Month=jul, Year="1983", Journal="IEEE Computer", Volume="16", Number="7", +Pages="47-53"} + +@InProceedings{Arbo89, + Key = "Arbo", + Author = "R.S. Arbo and E.M. Johnson and R.L. Sharp", + Title = "Extending Mandatory Access + Controls to a Networked MLS Environment", + Booktitle = "Proc. 12th National Computer Security Conference", + Organization = "NCSC/NIST", Address = "Baltimore", Year = "1989", + Pages="286-295", month=oct } + +@book{Kane89, +author={P. Kane}, title={{V.I.R.U.S.}, Protection of {V}ital +{I}nformation {R}esources {U}nder {S}iege}, publisher={Bantam Software +Library, New York}, year=1989 } + +@article{parnasmay, +Title="A Technique for Software Module Specification with Examples", +Author="D.L. Parnas", +Journal="Communications of the ACM", Volume="15", Number="5", +Month=may, Year="1972", Page="330--336"} + +@Article{parnas72, +Title="On the Criteria to be Used in Decomposing Systems +into Modules", Journal="Communications of the ACM", Year="1972", +Month=dec, Page="1053--1058",Author="D.L. Parnas", Volume="15", +Number="12"} + +@ARTICLE{Courtois71, +Author={P.J. Courtois and F. Heymans and D.L. Parnas}, +TITLE = {Concurrent Control with Readers and Writers}, +JOURNAL = {Communications of the ACM}, YEAR = {1971}, VOLUME = {14}, +NUMBER = {10}, PAGES = {667-668}, MONTH = oct } + +@InProceedings{ParnasPrice73, +Author = {D.L. Parnas and W.R. Price}, +Title = {The Design of the Virtual Memory Aspects of a Virtual Machine}, +Booktitle = {Proceedings of the ACM SIGARCH-SIGOPS Workshop on Virtual +Computer Systems}, +Organization = {ACM}, Address = {}, +Year = {1973}, +Pages={}, Month = mar } + +@InProceedings{ParnasPrice74, +Author={D.L. Parnas and W.R. Price}, +TITLE = {Design of a Non-Random Access Virtual Memory Machine}, +Booktitle = {Proceedings of the International Workshop On Protection in + Operating Systems}, +YEAR = {1974}, Location = {IRIA, Rocquencourt, France}, +VOLUME = {}, +NUMBER = {}, PAGES = {177--181}, MONTH = aug } + +@ARTICLE{ParnasSiewiorek75, +Author={D.L. Parnas and D.L. Siewiorek}, +TITLE = {Use of the Concept of Transparency in the + Design of Hierarchically Structured Systems}, +JOURNAL = {Communications of the ACM}, YEAR = {1975}, VOLUME = {18}, +NUMBER = {7}, PAGES = {401-408}, MONTH = jul } + +@InProceedings{Parnas75ICRS, +Author={D.L. Parnas}, +TITLE = {The Influence of Software Structure on Reliability}, +Booktitle = {Proceedings of the International Conference on Reliable Software}, +YEAR = {1975}, Location = {Los Angeles, California}, +PAGES = {358--362}, MONTH = apr, +NOTE = {Reprinted with improvements in R. Yeh, +{\it Current Trends in Programming Methodology I}, Prentice-Hall, 1977, +111--119.} } + +@TechReport{ParnasHandzel75, +author={D.L. Parnas and G. Handzel}, +Title={More on Specification Techniques for Software Modules}, +institution= {Fachbereich Informatik, Technische Hochschule Darmstadt, +Research Report BS I 75/1}, +address={Germany}, month =apr, Year=1975 } + +@ARTICLE{Parnas76, +Author={D.L. Parnas}, +TITLE = {On the Design and Development of Program Families}, +JOURNAL = {IEEE Transactions on Software Engineering}, +YEAR = {1976}, VOLUME = {SE-2}, +NUMBER = {1}, PAGES = {1--9}, MONTH = mar } + +@ARTICLE{Parnas+85, +Author={D.L. Parnas and P.C. Clements and D.M. Weiss}, +TITLE = {The Modular Structure of Complex Systems}, +JOURNAL = {IEEE Transactions on Software Engineering}, YEAR = {1985}, +VOLUME = {SE-11}, NUMBER = {3}, PAGES = {259--266}, MONTH = mar } + +@inproceedings{Neumann74GI, +author={P.G. Neumann}, title={Toward a Methodology for Designing Large Systems +and Verifying Their Properties},month=oct,year={1974}, +booktitle={{GI} -- 4. Jahrestagung}, pages={52--66}, +publisher={Springer-Verlag, Berlin, +Lecture Notes in Computer Science, Vol. 26}, +editors={G. Goos and J. Hartmanis} } + +@InProceedings{buzzword, +Author = "D.L. Parnas", Title="On a ``Buzzword'': +Hierarchical Structure", key="Parnas", BookTitle = "Information Processing 74 +(Proceedings of the {IFIP} Congress 1974)", Publisher = "North-Holland, +Amsterdam", Volume = "Software", Pages="336--339", Year = "1974"} + +@InProceedings{ProctorRAP, +Key={Proctor}, Author={N.E. Proctor}, BookTitle={Proceedings of the 1985 +Symposium on Security and Privacy}, Organization={IEEE Computer Society}, +Title={The Restricted Access Processor: An Example of Formal Verification}, +Address="Oakland, California", Year={1985}, Month=apr, pages={49--55}} + +@InProceedings{Fray+86, +Author={J.-M. Fray and Y. Deswarte and D. Powell}, +BookTitle={Proceedings of the 1986 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, +Title={Intrusion Tolerance Using Fine-Grain Fragmentation-Scattering}, +Address="Oakland, California", Year={1986}, Month=apr, pages={194--201}} + +@InProceedings{Deswarte91, +Author={Y. Deswarte and L. Blain and J.-C. Fabre}, +BookTitle={Proceedings of the 1991 Symposium on Research in + Security and Privacy}, +Organization={IEEE Computer Society}, +Title={Intrusion Tolerance in Distributed Computing Systems}, +Address="Oakland, California", Year={1991}, Month=apr, pages={110--121}} + +@inproceedings{ProctorWong89, +author={N.E. Proctor and R. Wong}, title={The +Security Policy of the {S}ecure {D}istributed {O}perating {S}ystem Prototype}, +booktitle={Proceedings of the Fifth Aerospace Computer Security Applications +Conference}, address={Tucson AZ}, month=dec, year=1989 } + +@article{RochlisEichin89, +author={J.A. Rochlis and M.W. Eichin}, title={With +Microscope and Tweezers: {T}he {W}orm from {MIT's} perspective}, +journal={{Communications of the ACM}}, volume={32}, number={6}, pages={689--698}, month=jun, +year=1989 } + +@article{Seeley89, +author={D. Seeley}, title={Password Cracking: A Game of +Wits}, journal={{Communications of the ACM}}, volume={32}, number={6}, pages={700--703}, +month=jun, year=1989 } + +@article{Spafford89, +author={E.H. Spafford}, title={The {I}nternet {W}orm: +{Crisis} and aftermath}, journal={{Communications of the ACM}}, volume={32}, number={6}, +pages={678--687}, month=jun, year=1989 } + +@article{Stoll88, +author={C. Stoll}, title={Stalking the {W}ily +{H}acker}, journal={{Communications of the ACM}}, volume={31}, number={5}, pages={484--497}, +month=may, year=1988 } + +@book{Stoll89, +author={C. Stoll}, title={The Cuckoo's Egg: Tracking a Spy +Through the Maze of Computer Espionage}, publisher={Doubleday, +New York}, year=1989 } + +@manual{TCSEC, + title = {Department of {{Defense Trusted Computer System Evaluation Criteria}} ({{TCSEC}})}, + date = {1985-12-26}, + note = {\url{https://csrc.nist.gov/CSRC/media/Publications/white-paper/1985/12/26/dod-rainbow-series/final/documents/std001.txt} or \url{https://csrc.nist.gov/csrc/media/publications/conference-paper/1998/10/08/proceedings-of-the-21st-nissc-1998/documents/early-cs-papers/dod85.pdf}}, + number = {DoD 5200.28-STD, Orange Book}, +} + +@Manual{TCSEC-Glossary, +Key="NCSC", Author={NCSC}, Title ="Glossary of Computer Security Terms", +Year ="21 October 1988", Organization ="National Computer +Security Center", Note ="NCSC-TG-004 Version-1" } + +@Manual{TCSEC-TNIold, +Key="NCSC", Author={NCSC}, Title ="Trusted Network +Interpretation (TNI)", Year ="31 July 1987", Organization ="National Computer +Security Center", Note ="NCSC-TG-005 Version-1" } + +@Manual{TCSEC-TNI, +Key="NCSC", Author={NCSC}, Title ="Trusted Network +Interpretation (TNI)", +Year ="31 July 1987", Organization ="National Computer +Security Center", Note ="NCSC-TG-005 Version-1, Red Book" } + +@Manual{TCSEC-Guide, +Key="NCSC", Author={NCSC}, Title="Guidance for +Applying the Trusted Computer System Evaluation Criteria in Specific +Environments", date={1985-06}, +Organization="National Computer Security Center", Note="CSC-STD-003-85, +Yellow Book" } + +@Manual{TCSEC-TNI-guide, +Key="NCSC", Author={NCSC}, +Title ="Trusted Network Interpretation Environments Guideline", +Year ="1 August 1990", Organization ="National Computer +Security Center", Note ="NCSC-TG-011 Version-1" } + +@Manual{TCSEC-TDI, +Key="NCSC", Author={NCSC}, Title="Trusted Database +Management System Interpretation of the Trusted Computer System Evaluation +Criteria (TDI)", Year="April 1991", Organization="National Computer +Security Center", Note="NCSC-TG-021, Version-2, Lavender Book" } + +@Manual{TCSEC-TVI, +Key="Trusted", Author={Trusted Information Systems}, Title="A Proposed +Interpretation of the {TCSEC} for Virtual Machine Monitor Architectures +{(TVI)}, Volume 1: Strict Separation", Year="draft, 1 May 1990", +Organization="Trusted Information Systems, Inc., Glenwood, Maryland, TIS Report 325" +} + +@Manual{TCSEC-CSSI, +Key="NCSC", Author={NCSC}, Title="Computer System +Subsystem Interpretation of the Trusted Computer System Evaluation Criteria", +Year="16 September 1988", Organization="National Computer Security Center", +Note="NCSC-TG-009, Version-1." } + +@Manual{NCSC-79-91-Integrity, +Key="NCSC", Author={NCSC}, Title="Integrity in Automated Information Systems", +Year="1991", Month=sep, +Organization="National Computer Security Center", +Note="C Technical Report 79-91" } + +@Manual{ITSEC, +Author={{European Communities Commission}}, +Title="Information Technology Security Evaluation Criteria (ITSEC), Provisional +Harmonised Criteria (of France, Germany, the +Netherlands, and the United Kingdom)", Year="1991", month=jun, +Note="Version 1.2. Available from the Office for +Official Publications of the European Communities, L-2985 Luxembourg, +item CD-71-91-502-EN-C. Also available from U.K. CLEF, CESG Room 2/0805, +Fiddlers Green Lane, Cheltenham U.K. +GLOS GL52 5AJ, or GSA/GISA, Am Nippenkreuz 19, D 5300 Bonn 2, Germany", +Organization={} } + +@MANUAL{ITSECx, +NOTE = {ISBN 92-826-3004-8} } + +@Manual{ITSEC90, +Author={{European Communities Commission}}, +Title="Information Technology Security +Evaluation Criteria (ITSEC), Harmonised Criteria of France, Germany, the +Netherlands, and the United Kingdom", Year="2 May 1990", +Note="Draft, Version 1, Available from the U.K. CLEF, CESG Room 2/0805, +Fiddlers Green Lane, Cheltenham U.K. GLOS GL52 5AJ, or GSI/GISA, Am Nippenkreuz +19, D 5300 Bonn 2, Germany", +Organization={} +} + +@Manual{CC2000, +key ="International", +Author="{International Standards Organization}", +Title="The Common Criteria for Information Technology Security Evaluation, + Version 2.1, ISO 15408", +Month ="19 September", YEAR = "2000", +Organization={ISO/NIST/CCIB}, +NOTE = "(\xlink{http://csrc.nist.gov/cc}{http://csrc.nist.gov/cc})" +} + +@TechReport{UKSP01, +author={U.K.-CESG/DTI}, +Title={{U.K. IT} Security Evaluation and Certification Scheme: Description of +the Scheme (Publication No. 1, Issue 1.0)}, +institution= {Communications Electronics Security Group (Cheltenham) +and the Department of Trade and Industry}, +address={}, month ={1 March}, +Year=1991 } + +@TechReport{UKSP06, +author={U.K.-CESG/DTI}, +Title={{U.K. IT} Security Evaluation and Certification Scheme: {U.K.} +Certified Product List (Publication No. 6)}, +institution= {Communications Electronics Security Group (Cheltenham) +and the Department of Trade and Industry}, +address={}, month ={1 October}, +Year=1991 } + +@Manual{CTCPEC, +Key="Canada", Author={}, Title={Canadian Trusted Computer Product Evaluation +Criteria}, Month=dec, Year="1990", Note="Final Draft, version 2.0", +Organization={Canadian Systems Security Centre, Communications Security +Establishment, Government of Canada.} } + +@Manual{CTCPEC93, Key="Canada", +Author={{Canadian Systems Security Centre, + Communications Security Establishment, Government of Canada}}, +Title={Canadian Trusted Computer Product Evaluation Criteria, Version 3.0e}, +Month=jan, Year="1993" } + +@Manual{MoD89-55, +Author={U.K. Ministry of Defence}, +Title={Draft Interim Defence Standard 00-55, +Requirements for the procurement of safety critical software in defence +equipment}, +Year="1989", Note="({DefStan} 00-55)", Organization={U.K. Ministry of Defence} } + +@Manual{MoD89-56, +Author={U.K. Ministry of Defence}, +Title={Draft Interim Defence Standard 00-56, +Requirements for the analysis of safety-critical hazards}, +Year="1989", Note="({DefStan} 00-56)", Organization={U.K. Ministry of Defence} } + +@Manual{MoD91-55, +Key="MoD", Author={U.K.-MoD}, Title={Interim Defence Standard 00-55, +The Procurement of Safety-Critical Software in Defence Equipment}, Month="5 April", +Year="1991", Note="DefStan 00-55; Part 1, Issue 1: Requirements; +Part 2, Issue 1: Guidance", +Organization={U.K. Ministry of Defence} } + +@Manual{MoD91-56, +Key="MoD", Author={U.K.-MoD}, Title={Interim Defence Standard 00-56, +Hazard Analysis and Safety Classification of the Computer +and Programmable Electronic System Elements of Defence Equipment}, Month="5 April", +Year="1991", Note="DefStan 00-56", Organization={U.K. Ministry of Defence} } + +@Manual{FedCritI, +author={}, key={Federal01}, +Title={Federal Criteria for Information Technology Security, {Volume I}, +Protection Profile Development, +Version 1.0}, institution= {National Institute of Standards and Technology +and National Security Agency}, +address={}, month =dec, Year=1992 } + +@Manual{FedCritII, +author={}, key={Federal02}, +Title={Federal Criteria for Information Technology Security, {Volume II}, +Registry of Protection Profiles, Version 1.0}, +institution= {National Institute of Standards and Technology +and National Security Agency}, +address={}, month =dec, Year=1992 } + +@InProceedings{Tierney91, +Author = {M. Tierney}, +Title = {The Evolution of {DefStan} 00-55 and 00-56: an intensification +of the `formal methods debate' in the {U.K.}}, +Booktitle = {Software Workshop on Policy Issues in Systems and Software +Development}, Organization = {SPRU}, Address = {Brighton, U.K.}, +Year = {1991}, Pages={}, Month = {18-19 July}, +Note={Available from RCSS, Edinburgh University, 56 George Square, +Edinburgh EH8 9JU} } + +@Manual{TCCSEC, +Key={USAirForce}, Author={USAF}, Title={Air Force Trusted Critical Computer +System Evaluation Criteria (TCCSEC)}, day={25}, month={June}, Year={1990}, +Note={Draft}, Organization={U.S. Air Force HQ Electronic Security Command, +AFCSC/SRVC, San Antonio, TX 78243-5000} } + +@Manual{TECSECI, +Key={USAirForce}, Author={USAF}, Title={Air Force Trusted Embedded Computer +System Evaluation Criteria Interpretation (TECSECI)}, day={25}, month={June}, +Year={1990}, +Note={Draft}, Organization={U.S. Air Force HQ Electronic Security Command, +AFCSC/SRVC, San Antonio, TX 78243-5000} } + +@InProceedings{Arbo+89, +Key = "Arbo", Author = "R.S. Arbo and E.M. Johnson and +R.L. Sharp", Title = "Extending Mandatory Access Controls to a Networked {MLS} +Environment", Booktitle = {Proceedings of the Twelfth National Computer Security Conference}, +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1989", +Pages="286--295", month=oct } + +@InProceedings{Boeing-LAN89, +Author={Gary R. Stoneburner and Dean A. Snow}, +Booktitle = {Proceedings of the Twelfth National Computer Security Conference}, +Title={The {Boeing MLS LAN:} Headed Towards an {INFOSEC} Security Solution}, +Organization = {NIST/NCSC}, Address = {Baltimore, Maryland}, +Pages = {254--266}, Year = {1989}, Month = {10--13 October} } + +@InProceedings{Cohen, +Key="Cohen", Author = "F. Cohen", Title = "Computer Viruses", +BookTitle="Seventh DoD/NBS Computer Security Initiative Conference", +Organization = "National Bureau of Standards, Gaithersburg, Maryland", +Year="1984", Month="24--26 September", +Pages="240--263", +Note="Reprinted in Rein Turn, editor, +{\it Advances in Computer System Security}, +Vol. 3, Artech House, Dedham, Massachusetts, 1988" } + +@inProceedings{Neumann78, +key="Neumann3", Author="P.G. Neumann", +Title="Computer Security Evaluation", Booktitle="AFIPS Conference Proceedings, +NCC", Publisher="AFIPS Press", Year="1978", Month=jan, Pages="1087--1095", +Note="Reprinted in Rein Turn, editor, +{\it Advances in Computer Security}, Artech +House, Dedham, Massachusetts, 1981"} + +@InProceedings{Neumann+74, +Author={P.G. Neumann and R.S. Fabry and K.N. Levitt and L. Robinson + and J.H. Wensley}, +TITLE = {On the Design of a Provably Secure Operating System}, +Booktitle = {Proceedings of the International Workshop On Protection in + Operating Systems}, +YEAR = {1974}, Location = {IRIA, Rocquencourt, France}, +VOLUME = {}, +NUMBER = {}, PAGES = {161--175}, MONTH = aug } + +@InProceedings{Robinson+77, +Author={L. Robinson and K.N. Levitt and P.G. Neumann and A.R. Saxena}, +TITLE = {A Formal Methodology for the Design of Operating System Software}, +Booktitle = {R. Yeh (editors), {\it Current Trends in Programming Methodology +I}, Prentice-Hall, 61--110}, year = {1977} } + +@Inproceedings{BoyerElspas75, +Author="R.S. Boyer and B. Elspas and K.N. Levitt", +Title="{SELECT:} {A} formal system for testing and debugging +programs by symbolic execution", Booktitle="Proc. Int. Conf. Reliable +Software", Organization="IEEE", Publisher="IEEE", Pages="234-244", +Year="1975", Month=apr} + +@Techreport{PSOS75, +Author={P.G. Neumann and L. Robinson and K.N. Levitt and R.S. Boyer + and A.R. Saxena}, Title={A Provably Secure Operating System}, +Institution={Computer Science Laboratory +SRI International, Menlo Park, California}, Year={1975}, day={13}, month={June} } + +@Techreport{PSOS77, +Author={P.G. Neumann and R.S. Boyer and R.J. Feiertag and +K.N. Levitt and L. Robinson}, Title={A Provably Secure Operating System: The + System, Its Applications, and Proofs}, +Institution={Computer Science Laboratory +SRI International, Menlo Park, California}, Year={1977}, day={11}, month={February} } + +@Techreport{PSOS, Author={P. G. Neumann and R.S. Boyer and R.J. Feiertag and +K.N. Levitt and L. Robinson}, Title={{A Provably Secure Operating System}: +The System, Its Applications, and Proofs}, Institution={Computer Science +Laboratory, SRI International, Menlo Park, California}, Year={1980}, +Month=may, Note={2nd edition, Report CSL-116} } + +@InProceedings(PSOSreport, +Key="Feiertag", Author="R. J. Feiertag and P. G. Neumann", +Title="The Foundations of a {Provably Secure Operating System} ({PSOS})", +Publisher="AFIPS Press", +Booktitle="Proceedings of the National Computer Conference", +Year="1979", Pages = "329--334", +NOTE = "\url{http://www.csl.sri.com/neumann/psos.pdf}" +) + +@InProceedings{NeumannFeiertag03, +Author="P. G. Neumann and R. J. Feiertag", +Title="{PSOS} Revisited", +BookTitle="Proceedings of the 19th Annual Computer Security Applications +Conference (ACSAC 2003), Classic Papers section", +Organization="IEEE Computer Society", +Address="Las Vegas, Nevada", Year="2003", Month=dec, pages="208--216", +NOTE="http://www.acsac.org/ and http://www.csl.sri.com/neumann/psos03.pdf." +} + +@techreport(Feiertag79b, +Author="R.J. Feiertag and K.N. Levitt and P.M. +Melliar-Smith", Title="Tactical {E}xecutive ({TACEXEC}): A Real-Time Secure +Operating System for Tactical Applications", Year="1979", Month=jul, +Institution="Computer Science Laboratory, SRI International", +Note="Final Report, Project 5545", Key="Feiertag79b") + +@Article{proof, +Key="Robinson", Author="L. Robinson and K.N. Levitt", Title="Proof Techniques +for Hierarchically Structured Programs", Journal={Communications of the ACM}, +Year="1977", Volume="20", Number="4", Pages="271--283", Month=apr} + +@ARTICLE{Robinson+Levitt..., +AUTHOR = {Lawrence Robinson and Karl N. Levitt}, +TITLE = {Proof Techniques for Hierarchically Structured Programs}, +JOURNAL = {Communications of the ACM}, YEAR = {1977}, VOLUME = {20}, +NUMBER = {4}, PAGES = {271--283}, MONTH = apr } + +@Article{RobinsonLevitt77..., +Author={L. Robinson and K.N. Levitt}, +Title={Proof Techniques for Hierarchically Structured Programs}, +Journal={Communications of the ACM}, +volume=20, +number=4, +month=apr, +year=1977 } + +@article{Linden76, +author={T.A. Linden}, +title={Operating System Structures to Support Security and Reliable + Software}, +journal={ACM Computing Surveys}, +volume={5}, number={1}, month=mar, year={1973}, pages={}} + +@InProceedings{KargerHerbert84, +Key="Karger", Author="P.A. Karger and A.J. Herbert", +Title="An Augmented Capability Architecture to Support Lattice Security + and Traceability of Access", +BookTitle="Proceedings of the 1984 +Symposium on Security and Privacy", Organization="IEEE Computer Society", +Address="Oakland, California", Year="1984", Month=apr, pages="95--100"} + +@InProceedings{Karger87, +Key="Karger", Author="P.A. Karger", Title="Limiting the +Damage Potential of Discretionary {T}rojan Horses", +BookTitle="Proceedings of the 1987 Symposium on Security and Privacy", +Organization="IEEE Computer Society", +Address="Oakland, California", Year="1987", Month=apr, pages="32--37"} + +@InProceedings{Karger88, +Key="Karger", Author="P.A. Karger", Title="Implementing Commercial +Data Integrity with Secure Capabilities", BookTitle="Proceedings of the 1988 +Symposium on Security and Privacy", Organization="IEEE Computer Society", +Address="Oakland, California", Year="1988", Month=apr, pages="130--139"} + +@InProceedings{Karger78, +Author={P.A. Karger}, +Title={The lattice model in a public computing network}, +Booktitle={Proceedings of the ACM Annual Conference}, +volume=1, +month=dec, +year=1978 } + +@PhDThesis{KargerThesis, + Key={Karger}, Author={P.A. Karger}, + Title={Improving Security and Performance for Capability Systems}, + School={Computer Laboratory, University of Cambridge, + Cambridge, England}, + Year={1988}, Month=oct, Note={Technical Report No. 149} +} + +@InProceedings{KargerSchell74, +Author="P.A. Karger and R.R. Schell", +Title="Multics Security Evaluation: Vulnerability Analysis", +BookTitle="Proceedings of the 18th Annual Computer Security Applications +Conference (ACSAC), Classic Papers section", +Organization="", +Address="Las Vegas, Nevada", Year="2002", Month=dec, pages="", +NOTE="Originally available as U.S. Air Force report +ESD-TR-74-193, Vol. II, Hanscomb Air Force Base, Massachusetts." +} + +@InProceedings{KargerSchell02, +Author="P.A. Karger and R.R. Schell", +Title="Thirty Years Later: Lessons from the {Multics} Security Evaluation", +BookTitle="Proceedings of the 18th Annual Computer Security Applications +Conference (ACSAC), Classic Papers section", +Organization="", +Address="Las Vegas, Nevada", Year="2002", Month=dec, pages="", +NOTE="http://www.acsac.org/ ." +} + +@InProceedings{Lee88, +Key="Lee", Author="T.M.P. Lee", Title="Using Mandatory +Integrity", BookTitle="Proceedings of the 1988 +Symposium on Security and Privacy", Organization="IEEE Computer Society", +Address="Oakland, California", Year="1988", Month=apr, pages="140--146"} + +@article{Shoch82, +Title={The {``Worm''} Programs -- Early Experience with a Distributed +Computation}, Author={J.F. Shoch and J.A. Hupp}, Key="", Month=mar, +Year=1982, Journal= {Communications of the ACM}, Volume=25, Number=3, Pages="172--180", +NOTE={Reprinted in Denning (ed.), {\it Computers Under Attack}} } + +@book{Ford82, +Author={D. Ford}, +Title={Three Mile Island: Thirty Minutes to Meltdown}, +Publisher={Viking Press}, +Year={1982}, +NOTE="Sensor-related quote reproduced in {\it ACM SIGSOFT Software Engineering + Notes, 11,} 3, 9--10, July 1986."} + +@techreport{Shockley88, +author={W.R. Shockley}, Title="Implementing the {C}lark/{W}ilson Integrity +Policy Using Current Technology", institution="Gemini Computers, P.O. Box +222417, Carmel California", Year=1988, Note="GCI-88-6-01." } + +@article{MorrisThompson, +Title="Password Security: A Case History", +Author="R. Morris and K. Thompson", Key="Morris", Month=nov, +Year=1979, Journal= {Communications of the ACM}, Volume=22, Number=11, Pages="594--597"} + +@Article{Thompson84, + Key={Thompson}, Author={K.L. Thompson}, Journal={Communications of the ACM}, + Title={Reflections on Trusting Trust}, Year={1984}, + Month=aug, Pages={761--763}, Volume={27}, Number={8} } + +@TechReport{RTMorris85, +author={R.T. Morris}, +Title={Computer Science Technical Report 117}, +institution= {AT\&T Bell Laboratories}, +address={Murray Hill, New Jersey}, month ={25 February}, Year=1985} + +@book{Salus, +Author={P. Salus}, +Title={A Quarter-Century of Unix}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={1994} } + +@article(Rosen81, +Key="Rosen", Author="E. Rosen", Title="Vulnerabilities of +Network Control Protocols", Journal="ACM SIGSOFT Software Engineering Notes", +Year="1981", Volume="6", Number="1", Pages="6--8", Month=jan) + +@article{Garman, +Key="Garman", Author="J. Garman", Title="The Bug Heard 'Round the World", +Journal="ACM SIGSOFT Software Engineering Notes", Year="1981", +Month =oct, Volume="6", Number="5", Pages="3--10"} + +@article{Jaffe89, +Key="Jaffe", Author="M. {Jaffe, as reported by P.G. Neumann}", +Title="Aegis, {Vincennes,} and the {Iranian} {Airbus}", +Journal="ACM SIGSOFT Software Engineering Notes", +Year="1989", Volume="14", Number="5", Pages="20--21", Month=jul} + +@InProceedings{YoungMcHugh, +Key="Young", Author="W.D. Young and J. McHugh", +Title="Coding for a Believable Specification to Implementation Mapping", +BookTitle="Proceedings of the 1987 Symposium on Security and Privacy", Organization="IEEE +Computer Society", Address="Oakland, California", Year="1987", Month=apr, +pages="140--148"} + +@InProceedings{ClarkWilson87, +Author="D.D. {Clark and D.R. Wilson}", +Title="A Comparison of Commercial and Military Computer Security Policies", +BookTitle="Proceedings of the 1987 Symposium on Security and Privacy", Organization="IEEE +Computer Society", Address="Oakland, California", Year="1987", Month=apr, +pages="184--194"} + +@InProceedings{ClarkWilson87x, +NOTE = {IEEE 87CH2416-6, ISBN 0-8186-0771-8.}} + +@InProceedings{Lipner82, +Key="Lipner", Author = "S.B. Lipner", +Title="Non-Discretionary Controls for Commercial Applications", Year="1982", +Pages="2--10", Booktitle="Proceedings of the 1982 Symposium on Security and +Privacy", Publisher="IEEE", Note="Oakland, California, 26--28 April 1982" } + +@InProceedings(Sebe88, +Author="M.M. Sebring and E. Shellhouse and M.E. Hanna and R.A. Whitehurst", +Title="Expert System in Intrusion Detection: A Case Study", +BookTitle="Eleventh National Computer Security Conference", +Address = "Baltimore, Maryland", Year="1988", Month=oct) + +@InProceedings{GarveyLunt90, +Author={T.D. Garvey and T.F. Lunt}, +Title={Multilevel Security for Knowledge-based Systems}, +Booktitle={Proceedings of the EISS Workshop on Database Security}, +address={European Institute for System Security, Karlsruhe, Germany}, +month=apr, +Year=1990 } + +@TechReport{GarveyLuntReport90, +author={T.D. Garvey and T.F. Lunt}, +Title="Multilevel Security for Knowledge Based Systems", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, +Year=1990 } + +@InProceedings(Lunt88, +Key="Lunt", Author="T.F. Lunt", +Title="Automated Audit Trail Analysis and Intrusion Detection: A Survey", +BookTitle="Eleventh National Computer Security Conference", +Address = "Baltimore, Maryland", Year="1988", Month=oct) + +@InProceedings{LuntJagannathan88, +Key="Lunt", Author="T.F. Lunt and R. Jagannathan", +Title="A Prototype Real-Time Intrusion-Detection Expert System", +BookTitle="Proceedings of the 1988 Symposium on Security and Privacy", Organization="IEEE +Computer Society", Address="Oakland, California", Year="1988", Month=apr, +pages="59--66"} + +@book{Johnson94, +Author={D. Johnson}, +Title={Computer Ethics (2nd ed.)}, +Publisher={Prentice-Hall, Englewood Cliffs, New Jersey}, +Year={1994} } + +@book{Johnson+95, +Author={D. Johnson and H. Nissenbaum}, +Title={Computer Ethics and Social Values}, +Publisher={Prentice-Hall, Englewood Cliffs, New Jersey}, +Year={1995} } + +@book{ParkerEthics, +Author={D.B. Parker}, Title={Ethical Conflicts in Information and Computer +Science, Technology, and Business}, +Publisher={QED Information Sciences, Wellesley, Massachusetts}, Year={1990} } + +@book{Parker83, +Author={D.B. Parker}, Title={Fighting Computer Crime}, Publisher={Scribner, +New York}, Year={1983} } + +@book{Parker76, +Author={D.B. Parker}, Title={Crime by Computer}, Publisher={Scribner, +New York}, Year={1976} } + +@book{Parker98, +Author={D.B. Parker}, Title={Fighting Computer Crime}, Publisher={John Wiley +\& Sons, New York}, Year={1998} } + +@InProceedings{NeumannParker89, +Key = "Neumann1", Author = "P. G. Neumann and +D.B. Parker", Title = "A Summary of Computer Misuse Techniques", Booktitle = +"Proceedings of the Twelfth National Computer Security Conference", Organization = "NIST/NCSC", +Address = "Baltimore, Maryland", Year = "1989", Pages="396--407", month=oct} + +@Manual{Washcloth1, +title = {A Study of Computer Abuse -- Volume One: Computer Abuse Techniques}, +author = {P.G. Neumann and D.B. Parker}, key={Neumannaa2}, +organization = {SRI International, Menlo Park, California}, +month = {Revised, 2 March}, +year = {1990}, note={Final report for SRI Project 6812, U.S. Government} } + +@Manual{Washcloth2, +title = {A Study of Computer Abuse -- Volume Two: +Information Exploitation Database}, +author = {P.G. Neumann and D.B. Parker}, key={Neumannbb3}, +organization = {SRI International, Menlo Park, California}, +month = {31 July}, +year = {1989}, note={Final report for SRI Project 6812, U.S. Government} } + +@InProceedings{Gasser+89, +Key = "Gasser", +Author = "M. Gasser and A. Goldstein and C. Kaufman and B. Lampson", +Title = "The {Digital} Distributed System Security Architecture", +Booktitle = "Proceedings of the Twelfth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1989", +Pages="305--319", month=oct } + +@InProceedings{RussellSchaefer89, +Key = "Russell", Author = "T.T. Russell and +M. Schaefer", Title = "Toward a High {B} +Level Security Architecture for the {IBM} +{ES/3090} Processor Resource/Systems Manager {(PR/SM)}", +Booktitle = "Proceedings of the Twelfth +National Computer Security Conference", Organization = "NIST/NCSC", Address = +"Baltimore, Maryland", Year = "1989", Pages="184--196", month=oct } + +@InProceedings{Smid+89, +Key = "Smid", Author = "M. Smid and J. Dray and R.B.J. +Warnar", Title = "A Token Based Access Control System for Computer Networks", +Booktitle = "Proceedings of the Twelfth National Computer Security Conference", Organization = +"NIST/NCSC", Address = "Baltimore, Maryland", Year = "1989", Pages="232--253", Month = +"10--13 October" } + +@article{Fenton74, +Author={J.S. Fenton}, Title={Memoryless Subsystems}, +Key={Fenton}, Month=may, Year=1974, Journal={Computer Journal}, +Volume=17, Number=2, Pages={143--147}} + +@InProceedings{Denning74, +Key={Denning}, Author={D.E. Denning and P.J. Denning and G.S. Graham}, +BookTitle={Protection in Operating Systems, +Proceedings of the International Workshop on Protection in Operating Systems}, +Organization={IRIA, Rocquencourt, Le Chesnay, France}, +Title={Selectively Confining Subsystems}, Year={1974}, +Month=aug } + +@InProceedings{Jones74, +Key = {Jones}, Author = {A.K. Jones and W.A. Wulf}, +Title = {Towards the Design of Secure Systems}, +Booktitle = {Protection in Operating Systems, +Proceedings of the International Workshop on Protection in Operating Systems}, +Organization = {Institut de Recherche d'Informatique}, Address = {Rocquencourt, +Le Chesnay, France}, +Pages={121--135}, date={1974-08-13/1974-08-14}} + +@article{Jones_DesignSecureSystems_1975, + title = {Towards the Design of Secure Systems}, + author = {Jones, Anita K. and Wulf, William A.}, + date = {1975-10}, + journaltitle = {Software: Practice and Experience}, + volume = {5}, + pages = {321--336}, + doi = {10.1002/spe.4380050403}, + abstract = {Within a programmed system, we may distinguish between different kinds of information in order to control the use of each kind by separate security policies, where each policy is tailored to the sensitivity and desired dissemination of that one kind of information. This paper analyses the implications of implementing security policies and describes mechanisms which can be used as the basis for constructing operating systems with the desired security attributes.}, + langid = {english}, + number = {4} +} + +@InProceedings{CohenJefferson75, + title = {Protection in the {{Hydra Operating System}}}, + booktitle = {Proceedings of the Fifth {{ACM}} Symposium on {{Operating}} Systems Principles}, + author = {Cohen, Ellis and Jefferson, David}, + date = {1975-11-01}, + pages = {141--160}, + publisher = {{Association for Computing Machinery}}, + location = {{New York, NY, USA}}, + doi = {10.1145/800213.806532}, + abstract = {This paper describes the capability based protection mechanisms provided by the Hydra Operating System Kernel. These mechanisms support the construction of user-defined protected subsystems, including file and directory subsystems, which do not therefore need to be supplied directly by Hydra. In addition, we discuss a number of well known protection problems, including Mutual Suspicion, Confinement and Revocation, and we present the mechanisms that Hydra supplies in order to solve them.}, + isbn = {978-1-4503-7863-5}, + keywords = {Capability,Confinement,Mutual suspicion,Operating system,Protected subsystem,Protection,Protection problem,Revocation,Type}, + series = {{{SOSP}} '75} +} + +@book{Wulf81, + Title={Hydra/{C.mmp}: An Experimental Computer System}, + Author={W.A. Wulf and R. Levin and S.P. Harbison}, + Year={1981}, + publisher={McGraw-Hill, New York}, + } + +@InProceedings{Denning83, +Key={Denning}, Author={D.E. Denning}, BookTitle={Proceedings of CRYPTO '83}, +Organization={UCSB}, Title={Field Encryption and Authentication}, Year={1983}, +Month=aug } + +@TechReport{Kramer81, Key={Kramer}, Author={S.M. Kramer}, Institution={Mitre +Corporation}, Title={The {Ina} {Jo} Flow Table Generator}, Year={1981}, +Month=feb, Number={WP23103}, Address={Bedford, Massachusetts}, Type={Working +Paper} } + +@inproceedings{Rushby81, +key={Rushby}, author={J.M. Rushby} +,title={The Design and Verification of Secure Systems} +,booktitle={Proceedings of the Eighth ACM Symposium on Operating System Principles} ,address={Asilomar, California} +,month=dec ,year={1981} ,pages={12--21} , +note={(ACM Operating Systems Review, 15(5)).}, +url ="http://www.csl.sri.com/~{}rushby/abstracts/sosp81" +} + +@inproceedings{Rushby82, +key={Rushby} ,author={J.M. Rushby} ,title={{Proof of Separability}--a +Verification Technique for a Class of Security Kernels} ,month=apr +,year={1982} ,booktitle={Proceedings of the Fifth International Symposium on Programming} +,address={Turin, Italy} ,pages={352--367} , +publisher={M. Dezani-Cianaglini and U. Montanari, eds., Springer-Verlag, +Berlin, Lecture Notes in Computer Science, Vol. 137} } + +@article{HorningRandell73, +author={J. Horning and B. Randell}, +title={Process Structuring}, journal={ACM Computing Surveys}, +volume={5}, number={1}, month=mar, year={1973}, pages={}} + +@InCollection{Horning+74, +Publisher = "Springer-Verlag", +Author = "J.J. Horning and H.C. Lauer and P.M. Melliar-Smith and +B. Randell", +Title = "A Program Structure for Error Detection and Recovery", +Year = "1974", Pages = "171-187", Address = "Berlin", +Booktitle = "Operating Systems, Proceedings of an International Symposium, +Notes in Computer Science 16", +Editors = "E. Gelenbe and C. Kaiser" } + +@Article{Anderson+Knight, + Key={Anderson}, + Author={T. Anderson and J.C. Knight}, + Journal={IEEE Transactions on Software Engineering}, + Title={A Framework for Software Fault Tolerance in Real-Time Systems}, + Year={1983}, + Month=may, + Pages={355--364}, + Volume={SE-9}, + Number={3} + } + +@Book{Anderson+Lee, + Key={Anderson}, + Author={T. Anderson and P.A. Lee}, + Publisher={Prentice-Hall International, Englewood Cliffs, New Jersey}, + Title={Fault-Tolerance: Principles and Practice}, + Year={1981} + } + +@TechReport{Rushby+Randell83b, + Key={Rushby}, + Author={J.M. Rushby and B. Randell}, + Institution={Computing Laboratory, University of Newcastle upon Tyne}, + Title={A Distributed Secure System}, + Year={1983}, + Month=may, + Number={182} + } + +@InProceedings{Rushby+Randell83c, + Key={Rushby}, + Author={J.M. Rushby and B. Randell}, + BookTitle={Proceedings of the 1983 IEEE Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={A Distributed Secure System (Extended Abstract)}, + Pages={127--135}, + Month=apr, + Year={1983} + } + +@Article{Rushby83, +Key={Rushby}, Author={J.M. Rushby and B. Randell}, Journal={IEEE Computer}, +Title={A Distributed Secure System}, Year={1983}, Month=jul, Pages={55--67}, +Volume={16}, Number={7} } + +@TechReport{Feiertag80, +Author={R.J. Feiertag}, Title={A Technique for Proving Specifications are +Multilevel Secure}, number={CSL-109}, +Institution={Computer Science Laboratory, SRI International}, +Address={Menlo Park, California}, month=jan, Year=1980 } + +@Manual{HDM:Handbook, +Key={Robinson}, +Author={L. Robinson and K.N. Levitt and B.A. Silverberg}, +Title={The {HDM} Handbook}, Year={1979}, Month=jun, +Organization={Computer Science Laboratory, SRI International}, +Note={Three Volumes}, Address={Menlo Park, California} } + +@InProceedings{L+N78, +Key={L+N78}, Author={H.C. Lauer and R.M. Needham}, BookTitle={Proceedings of the Second +International Symposium on Operating Systems}, Organization={IRIA, France}, +Title={On the Duality of Operating System Structures}, Year={1978}, +Month=oct, Note={(Reprinted in ACM Operating Systems Review, Vol 13, No +2, April 1979, pp.3--19)} } + +@book{WilkesNeedham79, +Author={M.V. Wilkes and R.M. Needham}, +Title={The {Cambridge} {CAP} Computer and Its Operating System}, +Publisher={Elsevier North Holland, New York}, +Year={1979} } + +@InProceedings{Boebert+Kain, + Key={Boebert}, + Author={W.E. Boebert and R.Y. Kain}, + BookTitle={Proceedings of the Eighth DoD/NBS Computer Security Initiative Conference}, + Title={A Practical Alternative to Hierarchical Integrity Policies}, + Address={Gaithersburg, Maryland}, + Year={1985}, + Month={1--3 October} } + +@Article{YBK85, + author = {W.D. Young and W.E. Boebert and R.Y. Kain}, + title = {Proving a Computer System Secure}, + journal = {Scientific Honeyweller}, + year = 1985, + volume = 6, + number = 2, + month = jul, + pages = {18--27}, + note = {Reprinted in Tutorial: Computer and Network Security, + M.D. Abrams and H.J. Podell, editors, IEEE Computer Society Press, 1987, + pp. 142--157.} +} + +@InProceedings{FLR77, Key={Feiertag}, Author={R.J. +Feiertag and K.N. Levitt and L. Robinson}, BookTitle={Proceedings of the Sixth ACM Symposium +on Operating System Principles}, Title={Proving Multilevel Security of a System +Design}, Year={1977}, Month=nov, Pages={57--65} } + +@techreport{B+LP76, +key={Bell76}, author={D.E. Bell and L.J. La Padula}, title={Secure Computer +System: Unified Exposition and {Multics} Interpretation}, +number={ESD-TR-75-306}, institution={The Mitre Corporation}, address={Bedford, +Massachusetts}, month=mar, year={1976}} + +@techreport{B+LP73, key={Bell73}, author={D.E. +Bell and L.J. La Padula}, title={Secure Computer Systems : Volume {I} -- +Mathematical Foundations; Volume {II} -- A Mathematical Model; Volume {III} -- +A Refinement of the Mathematical Model}, number={MTR-2547 (three volumes)}, +institution={The Mitre Corporation}, address={Bedford, Massachusetts}, +month={March--December}, year={1973}} + +@techreport{B+L73a, key={Bell73a}, +author={D.E. Bell and L.J. La Padula}, title={Secure Computer Systems : +Mathematical Foundations}, number={MTR-2547 Vol. I}, institution={Mitre +Corporation}, address={Bedford, Massachusetts}, month=mar, year={1973}} + +@techreport{B+L73b, key={Bell73b}, author={D.E. Bell and L.J. La Padula}, +title={Secure Computer Systems : A Mathematical Model}, number={MTR-2547 Vol. +{II}}, institution={Mitre Corporation}, address={Bedford, Massachusetts}, month=may, +year={1973}} + +@techreport{B+L73c, key={Bell73c}, author={D.E. Bell and L.J. La +Padula}, title={Secure Computer Systems : A Refinement of the Mathematical +Model}, number={MTR-2547 Vol. {III}}, institution={Mitre Corporation}, +address={Bedford, Massachusetts}, month=dec, year={1973}} + +@TechReport{Bell73, +Author={D.E. Bell and L.J. La Padula}, +Title={Secure Computer Systems: Mathematical Foundations and Model}, +Institution={The Mitre Corporation}, +Address={Bedford, Massachusetts}, +number={M74-244}, +Month=may, +Year=1973 } + +@InProceedings{Lampson69, +Author = "B.W. Lampson", +Title = "On reliable and extendible operating systems", +Booktitle = "Proceedings of the Second NATO Conference on + Techniques in Software Engineering", +Organization = "NATO", Address = "Rome, Italy", Year = "1969", +Pages="", Month = "" } + +@article{LampsonSturgis76, +author={B.W. Lampson and H. Sturgis}, +title={Reflections on an operating system design}, +journal={Communications of the ACM}, +volume={19}, number={5}, month=may, year={1976}, pages={251--265} } + +@article{lampson73, +key={Lampson}, author={B.W. Lampson}, title={A Note on the Confinement +Problem}, journal={Communications of the ACM}, volume={16}, number={10}, month=oct +,year={1973}, pages={613--615}} + +@InProceedings{LampsonRedund, +author={B.W. Lampson}, +title={Redundancy and Robustness in Memory Protection}, +Booktitle={Information {P}rocessing 74 ({Proceedings of the IFIP Congress} 1974)}, +Publisher={North-Holland, Amsterdam}, +year={1974}, volume = {Hardware II}, pages={128--132}} + +@Article{Fraim, +Key={Fraim}, Author={L.J. +Fraim}, Journal={Computer}, Title={{SCOMP}: A Solution to the Multilevel +Security Problem}, Year={1983}, Month=jul, Pages={26--34}, Volume={16}, +Number={7} } + +@InProceedings{Silverman, +Key={Silverman}, Author={J.M. +Silverman}, BookTitle={Proceedings of the Ninth ACM Symposium on Operating System Principles}, +Title={Reflections on the Verification of the Security of an Operating System}, +Year={1983}, Month=oct, Pages={143--154} } + +@InProceedings{Lipner, +Key={Lipner}, Author={S.B. Lipner}, BookTitle={Proceedings of the Fifth ACM Symposium on +Operating System Principles}, Organization={ACM}, Title={A Comment on the +Confinement Problem}, Year={1975}, Pages={192--196} } + +@TechReport{Denning:Derivation, +Key={Denning}, Author={D.E. Denning}, +Institution={Purdue University}, Title={On the Derivation of Lattice Structured +Information Flow Policies}, Year={1976}, Month=mar, Number={CSD TR 180} } + +@Article{Denning:Lattice, +Key={Denning}, Author={D.E. Denning}, Journal={Communications of the ACM}, +Title={A Lattice Model of Secure Information Flow}, Year={1976}, Month=may, +Pages={236--243}, Volume={19}, Number={5} } + +@misc{Goguen:Database, +title = {Secure Database Concepts}, author = {J.A. Goguen}, year = 1982, month = +jun, howpublished = {Working paper prepared for National Academy of Science, +AFSB Summer Study on Multilevel Database Security}, key = {Goguen}} + +@InProceedings{G+M82, +Key={Goguen}, Author={J.A. Goguen and J. +Meseguer}, Title={Security Policies and Security Models}, BookTitle={Proceedings of the 1982 +Symposium on Security and Privacy}, Organization={IEEE Computer Society}, +Address={Oakland, California}, Year={1982}, Month=apr, Pages={11--20} } + +@InProceedings{G+M84, + Key={Goguen}, + Author={J.A. Goguen and J. Meseguer}, + BookTitle={Proceedings of the 1984 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={Unwinding and Inference Control}, + Year={1984}, + Pages={75--86}, + Month=apr + } + +@misc{G+M:Unwinding, +author = {J.A. Goguen and J. Meseguer}, +title = {Unwinding of Noninterference Assertions}, +year = 1983, +howpublished= {Draft appears in \cite{psos83}}, +key = {Goguen + Meseguer}} + +@techreport{psos83, +author = {P.G. {Neumann et al.}}, +title = {Technology for Provably Secure Systems}, +institution = {Computer Science Laboratory, SRI International}, +Address={Menlo Park, California}, +year = 1983, +month = aug, +key = {Neumann} } + +@misc{Goguen:MMS, +title = {Formalization of {Landwehr}-{Heitmeyer} {SMMS} Model}, +author = {J.A. Goguen}, +year = 1982, month = jun, +howpublished = {Working paper prepared for National Academy of Science, AFSB + Summer Study on Multilevel Database Security}, +key = {Goguen}} + +@Book{Denning:Book, + Key={Denning}, + Author={D.E. Denning}, + Publisher={Addison-Wesley, Reading, Massachusetts}, + Title={Cryptography and Data Security}, + Year={1982} + } + +@Article{Fenton, + Key={Fenton}, + Author={J.S. Fenton}, + Journal={Computer Journal}, + Title={Memoryless Subsystems}, + Year={1974}, + Month=may, + Pages={143--147}, + Volume={17}, + Number={2} + } + +@TechReport{Rushby:Basis, + Key={Rushby}, + Author={J.M. Rushby}, + Institution={Computer Science Laboratory, SRI International}, + Title={Mathematical Foundations of the {MLS} Tool for Revised Special}, + Year={1986}, + Address={Menlo Park, California}, + Type={Forthcoming} + } + +@TechReport{Rushby:SRI, + Key={Rushby}, + Author={J.M. Rushby}, + Institution={Computer Science Laboratory, SRI International}, + Address={Menlo Park, California}, + Title={The {SRI} Security Model}, + Year={Forthcoming} + } + +@TechReport{Rushby:BLP, + Key={Rushby}, + Author={J.M. Rushby}, + Institution={Computer Science Laboratory, SRI International}, + Address={Menlo Park, California}, + Title={The {Bell} and {La Padula} Security Model}, + Year={1986}, + Month=jun, + Type={Draft Report} + } + +@TechReport{Rushby:Models, + Key={Rushby}, + Author={J.M. Rushby}, + Institution={Computer Science Laboratory, SRI International}, + Address={Menlo Park, California}, + Title={Computer Security Models}, + Year={1984}, + Type={Draft Internal note}, + Month=apr + } + +@TechReport{Rushby:Comparison, + Key={Rushby}, + Author={J.M. Rushby}, + Institution={Computer Science Laboratory, SRI International}, + Address={Menlo Park, California}, + Title={Comparison between the {Bell} and {La Padula} and the {SRI} Security Models}, + Year={1986}, + Type={Forthcoming} + } + +@Book{H+U69, + Key={Hopcroft}, + Author={J.E. Hopcroft and J.D. Ullman}, + Publisher={Addison-Wesley, Reading, Massachusetts}, + Title={Formal Languages and their Relation to Automata}, + Year={1969} + } + +@InCollection{Mesarovic, + Key={Mesarovic}, + Author={M.D. Mesarovi\'{c}}, + Booktitle={Trends in General Systems Theory}, + Publisher={John Wiley and Sons}, + Title={A Mathematical Theory of General Systems}, + Year={1972}, + Editor={G.J. Klir} + } + +@TechReport{Millen:Models, + Key={Millen}, + Author={J.K. Millen and C.M. Cerniglia}, + Institution={Mitre Corporation}, + Title={Computer Security Models}, + Year={1983}, + Month=sep, + Number={WP25068}, + Address={Bedford, Massachusetts}, + Type={Working Paper} + } + +@TechReport{McLean, + Key={Mclean}, + Author={J. McLean}, + Institution={Naval Research Laboratory}, + Title={A Comment on the ``Basic Security Theorem'' of {Bell} and {La Padula}}, + Year={1983}, + Type={Informal Note} + } + +@InProceedings{Lipner:Panel, + Key={Lipner}, + Author={S.B. Lipner (Moderator)}, + BookTitle={Proceedings of the 1983 IEEE Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={Panel Session: {Bell/La Padula} and Alternative Models of Security}, + Month=apr, + Year={1983} + } + +@Manual{Revised:Special, + Author={SRI-CSL}, + Key={HDM}, + Title={{HDM} Verification Environment Enhancements, Interim Report on +Language Definition}, + Year={1983}, + note={SRI Project No. 5727, Contract No. MDA904-83-C-0461}, + Organization={Computer Science Laboratory, SRI International}, + Address={Menlo Park, California} + } + +@InProceedings{Bell:Retrospective, + Key={Bell}, + Author={D.E. Bell}, + BookTitle={Proceedings of the 1983 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={Secure Computer Systems: a Retrospective}, + Year={1983}, + Month=apr, + Pages={161--162} + } + +@InProceedings{hinke83, + Key={Hinke}, + Author={T. Hinke and J. Althouse and R.A. Kemmerer}, + BookTitle={Proceedings of the 1983 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={{SDC} Secure Release Terminal Project}, + Year={1983}, + Month=apr, + Pages={113--119} + } + +@InProceedings{Hartman84, + Key={Hartman}, + Author={B.A. Hartman}, + BookTitle={Proceedings of the 1984 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={A {Gypsy}-Based Kernel}, + Year={1984}, + Month=apr, + Pages={219--225} + } + +@InProceedings{Taylor84, + Key={Taylor}, + Author={T. Taylor}, + BookTitle={Proceedings of the 1984 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={Comparison Paper between the {Bell} and {La Padula} Model and + the {SRI} Model}, Year={1984}, Month=apr, pages={195--202} } + +@techreport{landwehr82 + ,key={Landwehr} + ,author={C.E. Landwehr and C.L. Heitmeyer} + ,title={Military Message Systems: Requirements and Security Model} + ,number={{NRL} Memorandum Report 4925} + ,institution={Naval Research Laboratory} + ,address={Washington, D.C.} + ,month=sep + ,year={1982}} + +@article{landwehr81 + ,key={Landwehr} + ,author={C.E. Landwehr} + ,title={A Survey of Formal Models for Computer Security} + ,journal={Computing Surveys} + ,volume={13} + ,number={3} + ,month=sep + ,year={1981} + ,pages={247--278}} + +@InProceedings{Graubart, + Key={Graubart}, + Title={A Preliminary Naval Surveillance {DBMS} Security Model}, + Author={R.D. Graubart and J.P.L. Woodward}, + BookTitle={Proceedings of the 1982 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Year={1982}, + Month=apr, + Pages={21--37} + } + +@inproceedings{ames80 + ,key={Ames80} + ,author={S.R. {Ames, Jr.} and J.G. Keeton-Williams} + ,title={Demonstrating Security for Trusted Applications on a Security Kernel Base} + ,booktitle={Proceedings of the 1980 Symposium on Security and Privacy} + ,organization={IEEE Computer Society} + ,address={Oakland, California} + ,month=apr + ,year={1980} + ,pages={145--156}} + +@techreport{anderson72 + ,key={Anderson} + ,author={J.P. Anderson} + ,title={Computer Security Technology Planning Study} + ,institution={U.S. Air Force Electronic Systems Division} + ,number={ESD-TR-73-51} + ,month=oct + ,year={1972} + ,note={(Two volumes)}} + +@inproceedings{barnes80 + ,key={Barnes} + ,author={D.H. Barnes} + ,title={Computer Security in the {RSRE PPSN}} + ,booktitle={Networks '80} + ,pages={605--620} + ,organization={Online Conferences} + ,month=jun + ,year={1980}} + +@inproceedings{barnes81 + ,key={Barnes} + ,author={D.H. Barnes} + ,title={The Provision of End To End Security for User Data on an Experimental Packet Switched Network} + ,booktitle={Proceedings of the Fourth International Conference on Software Engineering for Telecommunications Switching Systems} + ,organization={IEE} + ,address={Warwick, England} + ,pages={144--148} + ,month=jul + ,year={1981}} + +@inproceedings{Woodward + ,key={Woodward} + ,author={J.P.L. Woodward} + ,title={Applications for Multilevel Secure Operating Systems} + ,BookTitle={National Computer Conference} + ,Organization={AFIPS Conference Proceedings} + ,Note={Vol. 48} + ,year=1979 + ,pages={319--328}} + +@inproceedings{stotz + ,key={Stotz} + ,author={R. Stotz and R. Tugender and D. Wilczynski} + ,title={{SIGMA}--An interactive message service for the Military +Message Experiment} + ,BookTitle={National Computer Conference} + ,Organization={AFIPS Conference Proceedings} + ,Note={Vol. 48} + ,year=1979 + ,pages={839--846}} + +@InProceedings{Barnes83, + Key={Barnes}, + Author={D.H. Barnes}, + BookTitle={Proceedings of the 1983 IEEE Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Month=apr, + Year={1983}, + Title={The Provision of Security for User Data on Packet Switched Networks}, + Pages={121--126} + } + +@Article{Sift, + Key={Melliarsmith}, + Author={P.M. Melliar-Smith and R.L. Schwartz}, + Journal={IEEE Transactions on Computers}, + Title={Formal Specification and Verification of {SIFT}: A +Fault-Tolerant Flight Control System}, + Year={1982}, + Month=jul, + Pages={616--630}, + Volume={C-31}, + Number={7} + } + +@Article{Cheheyl, + Key={Cheheyl}, + Author={M. {Cheheyl et al.}}, + Journal={Computing Surveys}, + Title={Verifying Security}, + Year={1981}, + Month=sep, + Pages={279--339}, + Volume={13}, + Number={3} + } + +@Article{Hebbard, + Key={Hebbard}, + Author={B. {Hebbard et al.}}, + Journal={ACM Operating Systems Review}, + Title={A Penetration Analysis of the Michigan Terminal System}, + Year={1980}, + Month=jan, + Pages={7--20}, + Volume={14}, + Number={1} + } + +@Article{Attanasio, + Key={Attanasio}, + Author={C.R. Attanasio and P.W. Markstein and R.J. Phillips}, + Journal={IBM Systems Journal}, + Title={Penetrating an Operating System: a Study of {VM}/370 Integrity}, + Year={1976}, + Pages={102--116}, + Volume={15}, + Number={1} + } + +@Article{Wilkinson, + Key={Wilkinson}, + Author={A.L. {Wilkinson et al.}}, + Journal={ACM Operating Systems Review}, + Title={A Penetration Study of a {Burroughs} Large System}, + Year={1981}, + Month=jan, + Pages={14--25}, + Volume={15}, + Number={1} + } + +@InProceedings{Linde, + Key={Linde}, + Author={R.R. Linde}, + BookTitle={National Computer Conference}, + Organization={AFIPS Conference Proceedings}, + Title={Operating System Penetration}, + Year={1975}, + Note={Vol. 44}, + Pages={361--368} + } + +@TechReport{Abbott, + Key={Abbott}, + Author={R.P. {Abbott et al.}}, + Institution={National Bureau of Standards}, + Title={Security Analysis and Enhancements of Computer Operating Systems}, + Year={1974}, + Note={Order No. S-413558-74} + } + +@InProceedings{Berson79, + Key={Berson}, + Author={T.A. Berson and G.L. {Barksdale Jr.}}, + BookTitle={National Computer Conference}, + Organization={AFIPS Conference Proceedings}, + Note={Vol. 48}, + Title={{KSOS}: Development Methodology for a Secure Operating System}, + Year={1979}, + Pages={365--371} + } + +@InProceedings{McCauley, + Key={Mccauley}, + Author={E.J. McCauley and P.J. Drongowski}, + BookTitle={National Computer Conference}, + Organization={AFIPS Conference Proceedings}, + Note={Vol. 48}, + Title={{KSOS}: The Design of a Secure Operating System}, + Year={1979}, + Pages={345--353} + } + +@TechReport{Craigen:Guard, + Key={Craigen}, + Author={D. Craigen}, + Institution={I.P. Sharp Associates}, + Title={A Formal Specification of the {LSI Guard}}, + Year={1982}, + Month=aug, + Number={TR-5031-82-2}, + Address={Ottawa} + } + +@TechReport{Stahl, + Key={Stahl}, + Author={S. Stahl}, + Institution={Mitre Corporation}, + Title={{LSI Guard} Security Specification}, + Year={1981}, + Month=sep, + Number={MTR 8451}, + Address={Bedford, Massachusetts} + } + +@TechReport{Good:MFM, + Key={Good}, + Author={D.I. Good and A.E. Siebert and L.M. Smith}, + Institution={Institute for Computing Science and Computer Applications, +The University of Texas}, + Title={The Message Flow Modulator, Final Report}, + Year={1982}, + Month=dec, + Number={34}, + Address={Austin, TX} + } + +@InProceedings{Berson83, + Key={Berson}, + Author={T.A. Berson and R.J. Feiertag and R.K. Bauer}, + BookTitle={Proceedings of the 1983 IEEE Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={Processor-per-Domain Guard Architecture}, + Month=apr, + Year={1983}, + Pages={120}, + Note={(Abstract only)} + } + +@Article{Bic, + Key={Bic}, + Author={L. Bic}, + Journal={Communications of the ACM}, + Title={A Protection Model and its Implementation in a Dataflow System}, + Year={1982}, + Month=sep, + Pages={650--658}, + Volume={25}, + Number={9} + } + +@Article{Voydock, + Key={Voydock}, + Author={V.L. Voydock and S.T. Kent}, + Journal={ACM Computing Surveys}, + Title={Security Mechanisms in High-Level Network Protocols}, + Year={1983}, + Month=jun, + Pages={135--171}, + Volume={15}, + Number={2} + } + +@InProceedings{Denning84, + Key={Denning}, + Author={D.E. Denning}, + BookTitle={Proceedings of the 1984 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={Cryptographic Checksums for Multilevel Database Security}, + Year={1984}, + Month=apr, + pages={52--61} + } + +@InProceedings{Gold84, + Key={Gold}, + Author={B.D. Gold and R.R. Linde and P.F. Cudney}, + BookTitle={Proceedings of the 1984 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={{KVM/370} in Retrospect}, + Year={1984}, + Month=apr, + pages={13--23} + } + +@TechReport{Rushby:Scomp, + Key={Rushby}, + Author={J.M. {Rushby et al.}}, + Institution={Computer Science Laboratory, SRI International}, + Title={{SCOMP}-{CYBER} Security}, + Year={1984}, + Month=feb, + Address={Menlo Park, California}, + Note={(Client Confidential)}, + Type={Final Report, SRI Project 6121} + } + +@TechReport{Ashcroft, + Key={Ashcroft}, + Author={E.A Ashcroft}, + Institution={Computer Science Laboratory, SRI International}, + Title={An Eduction Engine}, + Year={1984}, + Month=apr, + Address={Menlo Park, California}, + Type={Draft Report} + } + +@TechReport{Feiertag:ICN, + Key={Feiertag}, + Author={R.J. Feiertag}, + Institution={Sytek Inc.}, + Title={A Model of Security Policy for the Integrated Computer Network}, + Year={1981}, + Month=apr, + Number={SYTEK-TR-81001}, + Address={Mountain View, California} + } + +@TechReport{Rushby81b, + Key={Rushby}, + Author={J.M. Rushby}, + Institution={Computing Laboratory, University of Newcastle upon Tyne}, + Title={Verification of Secure Systems}, + Year={1981}, + Month=aug, + Number={166} + } + +@TechReport{SMSV, + Key={Schwartz}, + Author={R.L. Schwartz, P.M. Melliar-Smith and F.H. Vogt}, + Institution={Computer Science Laboratory, SRI International}, + Title={An Interval Logic for Higher-Level Temporal Reasoning}, + Year={1983}, + Month=feb, + Number={CSL-138}, + Address={Menlo Park, California} + } + +@InProceedings{Pnueli, + Key={Pnueli}, + Author={A. Pnueli}, + BookTitle={Proceedings of the Eighteenth Symposium on Foundations of Computer Science}, + Organization={ACM}, + Title={The Temporal Logic of Programs}, + Year={1977}, + Address={Providence, RI}, + Month=nov, + Pages={46--57} + } + +@InProceedings{Lamport83, + Key={Lamport}, + Author={L. Lamport}, + BookTitle={Information Processing 83}, + Organization={North-Holland}, + Title={What Good is Temporal Logic?}, + Year={1983}, + Address={Paris}, + Editor={R.E.A. Mason}, + Pages={657--668} + } + +@Book{tunis, + Key={Holt}, + Author={R.C. Holt}, Publisher={Addison-Wesley, Reading, Massachusetts}, + Title={Concurrent {Euclid}, the {UNIX} System, and {TUNIS}}, Year={1983} } + +@Book{Thoth, + Key={Cheriton}, + Author={D.R. Cheriton}, + Publisher={North-Holland}, + Title={The {Thoth} System: Multi-Process Structuring and Portability}, + Year={1982}, + Series={Operating and Programming Systems Series} + } + +@inproceedings{Ames81, + key={Ames}, + author={S.R. {Ames Jr.}}, + title={Security Kernels: a Solution or a Problem?}, + booktitle={Proceedings of the 1981 Symposium on Security and Privacy}, + month=apr, + year={1981}, + address={Oakland, California}, + organization={IEEE Computer Society}, + pages={141--150}} + +@TechReport{Plan9-91, +author={R. Pike and D. Resotto and K. Thompson and H. Trickey and +T. Duff and G. Holzmann}, +Title={Plan 9: The Early Papers}, +institution= {AT\&T Bell Laboratories}, +address={Murray Hill, New Jersey}, month =jul, +Year=1991, Note={(Computing Science Technical Report 158. +This report contains seven conference papers presented during 1990 and 1991.) } } + +@TechReport{IX-92, +author={J.A. Reeds and M.D. McIlroy}, +Title={The {IX} Multilevel-Secure {UNIX} System}, +institution= {AT\&T Bell Laboratories}, +address={Murray Hill, New Jersey}, month =jan, +Year=1992, Note={Computing Science Technical Report No. 162. +This report contains 5 papers on IX. } } + +@ARTICLE{McIlroy90, +Author={M.D. McIlroy}, TITLE = {Green Light for Bad Software}, +JOURNAL = {Communications of the ACM}, YEAR = {1990}, VOLUME = {33}, +NUMBER = {5}, PAGES = {479}, MONTH = may } + +@BOOK{Holzmann91, +author={G.J. Holzmann}, +title={Design and Validation of Computer Protocols}, +publisher={Prentice-Hall, Englewood Cliffs, New Jersey}, Year={1991}} + +@MastersThesis{Fisher, + Key={Fisher}, Author={P.F. Fisher}, + School={Computing Laboratory, University of Newcastle upon Tyne, England}, + Title={An Operating System Security Kernel}, Year={1982}, Month=sep + } + +@Article{Wegner84, + Key={Wegner}, + Author={P. Wegner}, + Journal={IEEE Software}, + Title={Capital-Intensive Software Technology}, + Year={1984}, + Month=jul, + Volume={1}, + Number={3}, + Pages={7--45} + } + +@Article{Andrews83, + Key={Andrews}, + Author={G.R. Andrews and F.B. Schneider}, + Journal={ACM Computing Surveys}, + Title={Concepts and Notations for Concurrent Programming}, + Year={1983}, + Month=mar, + Pages={3--43}, + Volume={15}, + Number={1} + } + +@article{Alpern+Schneider, +AUTHOR = {B. Alpern and F.B. Schneider}, +TITLE = {Defining Liveness}, +JOURNAL = {Information Processing Letters}, +YEAR = {1985}, +VOLUME = {21}, +NUMBER = {4}, +PAGES = {181--185}, +MONTH = oct +} + +@book{Schneider97, +Author={F.B. Schneider}, +Title={On Concurrent Programming}, +Publisher={Springer Verlag, New York}, +Year={1997} } + +@Article{Nil:Language, + Key={Parr}, + Author={F.N. Parr and R.E. Strom}, + Journal={IBM Systems Journal}, + Title={{NIL}: A High-Level Language for Distributed Systems Programming}, + Year={1983}, + Pages={111--127}, + Volume={22}, + Number={1/2} + } + +@InProceedings{Nil:Security, + Key={Strom}, + Author={R.E. Strom}, + BookTitle={Proceedings of the 10th Symposium on Principles of Programming Languages}, + Title={Mechanisms for Compile-Time Enforcement of Security}, + Year={1983}, + Address={Austin, TX}, + Month=jan, + Pages={276--284} + } + +@InProceedings{Nil:System, + Key={Strom}, + Author={R.E. Strom and S. Yemini}, + BookTitle={Proceedings of the SIGPLAN '83 Symposium on Programming Language +Issues in Software Systems}, + Title={{NIL}: An Integrated Language and System for Distributed Programming}, + Year={1983}, + Address={San Francisco, California}, + Month=jun, + Note={(in SIGPLAN Notices Vol 18, No. 6, June 1983)}, + Pages={73--82} + } + +@Article{Gehani, + Key={Gehani}, + Author={N.H. Gehani and T.A. Cargill}, + Journal={Software--Practice and Experience}, + Title={Concurrent Programming in the {Ada} Language: the Polling Bias}, + Year={1984}, + Month=may, + Pages={413--427}, + Volume={14}, + Number={5} + } + +@InProceedings{Perrine, + Key={Perrine}, + Author={T. Perrine and J. Codd and B. Hardy}, + BookTitle={Proceedings of the Seventh DoD/NBS Computer Security Initiative Conference}, + Title={An Overview of the {Kernelized Secure Operating System ({KSOS})}}, + Address={Gaithersburg, Maryland}, + Pages={146--160}, + Year={1984}, + Month=sep + } + +@InProceedings{Barnes84, + Key={Barnes}, + Author={D.H. Barnes}, + BookTitle={Proceedings of the Seventh DoD/NBS Computer Security Initiative Conference}, + Title={Secure Communications Processor Research}, + Address={Gaithersburg, Maryland}, + Pages={312--317}, + Year={1984}, + Month=sep + } + +@InProceedings{Rushby:TCB, + Key={Rushby}, + Author={J.M. Rushby}, + BookTitle={Proceedings of the Seventh DoD/NBS Computer Security Initiative Conference}, + Title={A Trusted Computing Base for Embedded Systems}, + Address={Gaithersburg, Maryland}, + Pages={294--311}, + Year={1984}, + Month=sep + } + +@InProceedings{Rushby:HDM, +Key={Rushby}, Author={J.M. Rushby}, +BookTitle={Proceedings of the Seventh DoD/NBS Computer Security Initiative Conference}, +Title={The Security Model of {Enhanced HDM}}, Address={Gaithersburg, Maryland}, +Pages={120--136}, Year={1984}, Month=sep } + +@TechReport{Froscher+Carroll, + Key={Froscher}, + Author={J.N. Froscher and J.M. Carroll}, + Institution={Naval Research Laboratory}, + Title={Security Requirements for Navy Embedded Computers}, + Year={1984}, + Month=sep, + Number={5425}, + Type={{NRL} Memorandum Report} + } + +@Article{Leveson84, + Key={Leveson}, + Author={N.G. Leveson}, + Journal={Computer}, + Title={Software Safety in Computer Controlled Systems}, + Year={1984}, + Month=feb, + Pages={48--55}, + Volume={17}, + Number={2} + } + +@InProceedings{Leveson:Kernels, + Key={Leveson}, + Author={N.G. {Leveson et al.}}, + BookTitle={Proceedings of the AIAA Twenty-first Aerospace Sciences Meeting}, + Organization={American Institute of Aeronautics and Astronautics}, + Title={Design for Safe Software}, + Address={Reno, NV}, + Year={1983}, + Month=jan + } + +@Article{LevesonYoung14, + Author={Nancy G. Leveson and William Young}, + Journal={Communications of the ACM}, + Title={An Integrated Approach to Safety and Security Based on System Theory}, + Year={2014}, + Month=feb, + Pages={31--35}, + Volume={57}, + Number={2}, + note = {\url{http://www.csl.sri.com/neumann/insiderisks.html}} + } + +@Article{Landwehr:MMM, + Key={Landwehr}, + Author={C.E. Landwehr and C.L. Heitmeyer and J. McLean}, + Journal={ACM Transactions on Computer Systems}, + Title={A Security Model for Military Message Systems}, + Year={1984}, Month=aug, Pages={198--222}, Volume={2}, Number={3} } + +@inproceedings{Accent + ,key={Rashid} + ,author={R. Rashid and G. Robertson} + ,title={{Accent}: A Communications Oriented Network Operating System Kernel} + ,booktitle={Proceedings of the Eighth ACM Symposium on Operating System Principles} + ,address={Asilomar, California} + ,month=dec + ,year={1981} + ,pages={64--75} + ,note={(ACM Operating Systems Review, Vol. 15, No. 5)}} + +@TechReport{Carlstedt75, +author={J. Carlstedt and R. {Bisbey II} and G. Popek}, +Title={{Pattern-Directed Protection Evaluation}}, +institution= {USC Information Sciences Institute (ISI)}, +number={ISI/SR-75-31}, +address={Marina Del Rey, California}, month =jun, Year=1975} + +@TechReport{Bisbey75, +author={R. {Bisbey II} and G. Popek and J. Carlstedt}, +Title={{Protection Errors in Operating Systems: Inconsistency of a +single data value over time}}, +institution= {USC Information Sciences Institute (ISI)}, +number={ISI/SR-75-4}, +address={Marina Del Rey, California}, month =dec, Year=1975} + +@TechReport{Bisbey76, +author={R. {Bisbey II} and J. Carlstedt and D. Chase}, +Title={{Data Dependency Analysis}}, +institution= {USC Information Sciences Institute (ISI)}, +number={ISI/SR-76-45}, +address={Marina Del Rey, California}, month =feb, Year=1976} + +@TechReport{Carlstedt76, +author={J. Carlstedt}, +Title={{Protection Errors in Operating Systems: Validation of +critical conditions}}, +institution= {USC Information Sciences Institute (ISI)}, +number={ISI/SR-76-5}, +address={Marina Del Rey, California}, month =may, Year=1976} + +@TechReport{Hollingworth76, +author={D. Hollingworth and R. {Bisbey II}}, +Title={Protection Errors in Operating Systems: Allocation/Deallocation +Residuals}, +institution= {USC Information Sciences Institute (ISI)}, +address={Marina Del Rey, California}, month =jun, Year=1976} + +@TechReport{Bisbey78, +author={R. {Bisbey II} and D. Hollingworth}, +Title={{Protection Analysis: Project final report}}, +institution= {USC Information Sciences Institute (ISI)}, +address={Marina Del Rey, California}, month ={}, Year=1978} + +@book{LocusBook, +Author={G.J. Popek and B.J. Walker}, +Title={The Locus Distributed System Architecture}, +Publisher={MIT Press, Cambridge, Massachusetts}, +Year={1985} } + +@inproceedings{Locus + ,key={Popek} + ,author={G. Popek et al.} + ,title={{Locus}: A Network Transparent, High Reliability, Distributed +System} + ,booktitle={Proceedings of the Eighth ACM Symposium on Operating System Principles} + ,address={Asilomar, California} + ,month=dec + ,year={1981} + ,pages={169--177} + ,note={(ACM Operating Systems Review, Vol. 15, No. 5)}} + +@Article{Brownbridge, + Key={Brownbridge}, + Author={D.R. Brownbridge, L.F. Marshall and B. Randell}, + Journal={Software--Practice and Experience}, + Title={The {Newcastle Connection}, or {UNIXes} of the World Unite!}, + Year={1982}, + Month=dec, + Pages={1147--1162}, + Volume={12}, + Number={12} + } + +@InProceedings{cornwell84, + Key={Cornwell}, + Author={M. Cornwell and R. Jacob}, + BookTitle={Proceedings of the Seventh DoD/NBS Computer Security Initiative Conference}, + Title={Structure of a Rapid Prototype Secure Military Message System}, + Address={Gaithersburg, Maryland}, + Pages={48--57}, + Year={1984}, + Month=sep + } + +@InProceedings{verdix, + Key={Donaldson}, + Author={A.L. Donaldson}, + BookTitle={Proceedings of the Seventh DoD/NBS Computer Security Initiative Conference}, + Title={A Multi-Level Secure Local Area Network}, + Address={Gaithersburg, Maryland}, + Pages={341--350}, + Year={1984}, + Month=sep + } + +@InProceedings{Macewan84, + Key={Macewan}, + Author={G.H. MacEwan and B. Burwell and Z-J. Lu}, + BookTitle={Proceedings of the 1984 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={Multi-Level Security Based on Physical Distribution}, + Year={1984}, + Pages={167--177}, + Month=apr + } + +@article{Heitmeyer+Wilson, + Key={Heitmeyer}, + Author={C.L. Heitmeyer and S.L. Wilson}, + Journal={IEEE Transactions on Communications}, + Title={Military Message Systems: Current Status and Future Directions}, + Year={1980}, + Month=sep, + Pages={1645--1654}, + Volume={COM-28}, + Number={9} + } + +@Article{end-to-end, + Key={Saltzer}, + Author={J.H. Saltzer and D.P. Reed and D.D. Clark}, + Journal={ACM Transactions on Computer Systems}, + Title={End-To-End Arguments in System Design}, + Year={1984}, + Month=nov, + Pages={277--288}, + Volume={2}, + Number={4} + } + +@manual{Views:Proposal, + Key={Denning}, + Author={D.E. Denning and P.G. Neumann}, + Title={Secure Data Views}, + Year={1985}, + Month=mar, + Organization={SRI International}, + Note={Proposal for Research No. ECU 85-203} + } + +@manual{Ocrea:Proposal, + Key={Rushby}, + Author={J.M. Rushby}, + Title={Security Modeling for Complex Systems}, + Year={1984}, + Month=oct, + Organization={Computer Science Laboratory, SRI International}, + Number={Proposal for Research No. ECU 84-034R} + } + +@manual{Demonstrator:Proposal, + Key={Rushby}, + Author={J.M. Rushby}, + Title={A Verified Secure ``Demonstrator'' System}, + Year={1984}, + Month=dec, + FullOrganization={Computer Science Laboratory, SRI International}, + Number={Proposal for Research No. ECU 84-103} + } + +@article(VERKI, +Key="Neumann", Author="P.G. {Neumann, editor}", +Title={{VERkshop I}: {V}erification {W}orkshop}, +Journal="ACM SIGSOFT Software Engineering Notes", Year="1980", Volume="5", +Number="3", Pages="4-47", +Month=jul) + +@article{VERKII, +Key="Neumann", Author="P.G. {Neumann, editor}", +Title={{VERkshop II}: {V}erification {W}orkshop}, +Journal="ACM SIGSOFT Software Engineering Notes", Year="1981", Volume="6", +Number="3", Pages="1-63", +Month=jul} + +@article(VERKIII, +Author="K.N. Levitt and S. Crocker and D. {Craigen, editors}", +Title={{VERkshop III}: Verification Workshop}, +Journal="ACM SIGSOFT Software Engineering Notes", Year="1985", Volume="10", +Number="4", Pages="1-136", Month=aug) + +@InProceedings{Macdonald85, + Key={Macdonald}, + Author={R. Macdonald}, + BookTitle={Proceedings of the {VERkshop III}}, + Address={Watsonville, California}, + Title={Verifying a Real System Design: Some of the Problems}, + Year={1985}, + Pages={126--129}, + Month=feb, + Note={Published as ACM Software Engineering Notes, Vol. 10, No. 4, Aug. 85} + } + +@article{Clark85, +author={D.D. Clark}, +title={The Structuring of Systems Using Upcalls}, +journal={Operating Systems Review}, +month={}, +vol = {19}, +no = {5}, +pages = {171--180}, +year=1985} + +@Article{Atkins88, + Author={M.S. Atkins}, + Journal={ACM Transactions on Computer Systems}, + Title={Experiments in {SR} with Different Upcall Program Structures}, + Year={1988}, Month=nov, Pages={365--392}, Volume={6}, Number={4} } + +@Book{Modula2, + Key={Wirth}, + Author={N. Wirth}, + Publisher={Springer-Verlag, Berlin}, + Title={Programming in {MODULA}-2}, + Year={1982}, + note={second edition}, + Series={Texts and Monographs in Computer Science} + } + +@InProceedings{Anderson:TCB, + Key={Anderson}, Author={E.R. Anderson}, + BookTitle={Proceedings of the 1985 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Title={{Ada}'s Suitability for Trusted Computer Systems}, + Year={1985}, Address={Oakland, California}, Month=apr, Pages={184--189} + } + +@manual{Fletcher, + Key={Fletcher}, + Author={J.C. Fletcher}, + Organization={Department of Defense}, + Title={Report of the Study on Eliminating the Threat Posed by Nuclear Ballistic Missiles, Volume {V}: Battle Management, Communications, and Data Processing}, + Year={1984}, + Month=feb + } + +@Manual{Eastport, + Key={Eastport}, + Author={Eastport Study Group}, + Title={Report to the Director, {SDIO}}, + Year={December, 1985} + } + +@Article{Lamport:Clocks, + Key={Lamport}, + Author={L.Lamport}, + Journal={Communications of the ACM}, + Title={Time, Clocks, and the Ordering of Events in a Distributed System}, + Year={1978}, + Month=jul, + Pages={558--565}, + Volume={21}, + Number={7} + } + +@Article{Lamport:Specifying, + Key={Lamport}, + Author={L.Lamport}, + Journal={ACM Transactions on Programming Languages and Systems}, + Title={Specifying Concurrent Program Modules}, + Year={1983}, + Month=apr, + Pages={190--222}, + Volume={5}, + Number={2} + } + +@Article{Lamport:Specifying89, + Key={Lamport}, + Author={L. Lamport}, + Journal={Communications of the ACM}, + Title={A Simple Approach to Specifying Concurrent Program Systems}, + Year={1989}, + Month=jan, + Pages={32--45}, + Volume={32}, + Number={1} + } + +@Article{Lamport:Timeout, + Key={Lamport}, + Author={L.Lamport}, + Journal={ACM Transactions on Programming Languages and Systems}, + Title={Using Time Instead of Timeout for Fault-Tolerant Distributed Systems}, + Year={1984}, + Month=apr, + Pages={254--280}, + Volume={6}, + Number={2} + } + +@TechReport{Lamport:Interprocess, + Key={Lamport}, + Author={L. Lamport}, + Institution={Computer Science Laboratory, SRI International}, + Title={On Interprocess Communication}, + Year={1985} + } + +@InProceedings{Lamport:Sometime, + Key={Lamport}, + Author={L. Lamport}, + BookTitle={Proceedings of the 10th Symposium on Principles of Programming Languages}, + Title={Sometime is Sometimes Not Never}, + Year={1980}, + Month=jan, + Pages={174--185} + } + +@InProceedings{Lamport:Priority, + Key={Lamport}, + Author={L. Lamport}, + BookTitle={Proceedings of the 10th Symposium on Principles of Programming Languages}, + Title={What it Means for a Concurrent Program to Satisfy a +Specification: Why No One Has Specified Priority}, + Year={1985}, + Month=jan + } + +@Article{Bernstein+Goodman, + Key={Bernstein}, + Author={P.A. Bernstein and N. Goodman}, + Journal={ACM Computing Surveys}, + Title={Concurrency Control in Distributed Database Systems}, + Year={1981}, + Month=jun, + Pages={185--221}, + Volume={13}, + Number={2} + } + +@TechReport{Panzieri:Rajdoot-techrep, + Key={Panzieri}, + Author={F. Panzieri and S.K. Shrivastava}, + Institution={Computing Laboratory, University of Newcastle upon Tyne}, + Title={{Rajdoot}: a remote procedure call mechanism supporting orphan +detection and killing}, + Year={1985}, + Month=may, + Number={200} + } + +@Article{Traiger, + Key={Traiger}, + Author={I.L. Traiger and J. Gray and C.A. Galtieri and B.G. Lindsay}, + Journal={ACM TODS}, + Title={Transactions and Consistency in Distributed Database Systems}, + Year={1982}, + Month=sep, + Pages={323--342}, + Volume={7}, + Number={3} + } + +@Article{Lamport:Reliable, + Key={Lamport}, + Author={L. Lamport}, + Journal={Computer Networks}, + Title={The Implementation of Reliable Distributed Multiprocess Systems}, + Year={1978}, + Pages={95--114}, + Volume={2} + } + +@Article{Shrivastava, + Key={Shrivastava}, + Author={S.K. Shrivastava and F. Panzieri}, + Journal={IEEE Transactions on Computers}, + Title={The Design of a Reliable Remote Procedure Call Mechanism}, + Year={1982}, + Month=jul, + Pages={692--687}, + Volume={C-31}, + Number={7} + } + +@Article{Lamport:Byzantine, + Key={Lamport}, + Author={L. Lamport and R. Shostak and M. Pease}, + Journal={ACM Transactions on Programming Languages and Systems}, + Title={The {Byzantine} Generals Problem}, + Year={1982}, + Month=jul, + Pages={382--401}, + Volume={4}, + Number={3} + } + +@Article{Pease, + Key={Pease}, + Author={M. Pease and R. Shostak and L. Lamport}, + Journal={Journal of the ACM}, + Title={Reaching Agreement in the Presence of Faults}, + Year={1980}, + Month=apr, + Pages={228--234}, + Volume={27}, + Number={2} + } + +@Article{Lamport:Synchronizing, + Key={Lamport}, + Author={L. Lamport and P.M. Melliar-Smith}, + Journal={Journal of the ACM}, + Title={Synchronizing Clocks in the Presence of Faults}, + Year={1985}, + Month=jan, + Pages={52--78}, + Volume={32}, + Number={1} + } + +@InProceedings{Dobson+Randell, + Key={Dobson}, + Author={J.E. Dobson and B. Randell}, + BookTitle={Proceedings of the 1986 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Title={Building reliable Secure Computing Systems out of Unreliable +Unsecure Components}, + Year={1986}, + Address={Oakland, California}, + Month=apr, + Pages={187--193} + } + +@InProceedings{RandellDobson, + Key="Randell", Author="B. Randell and J.E. Dobson", + BookTitle="Proceedings of the Fifth Symposium on Reliability in + Distributed Software and Database Systems", + Organization="", + Title="Reliability and Security Issues in Distributed Computing Systems", + Address="Los Angeles, California", Year="1986", Month=jan, pages=""} + +@InProceedings{Haigh+Young, + Key={Haigh}, + Author={J.T. Haigh and W.D. Young}, + BookTitle={Proceedings of the 1986 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Title={Extending the Non-Interference Model of {MLS} for {SAT}}, + Year={1986}, + Address={Oakland, California}, + Month=apr, + Pages={232--239} + } + +@Article{Haigh+Young87, +author={J.T. Haigh and W.D. Young}, +Title={Extending the Non-Interference Model of {MLS} for {SAT}}, +Journal={IEEE Transactions on Software Engineering}, +volume={SE-13}, number=2, pages={141-150}, month=feb, year=1987 } + +@InProceedings{LOCK87, +Key={Saydjari}, Author={O.S. Saydjari and J.M. Beckman +and J.R. Leaman}, Title={{LOCKing} Computers Securely}, + BookTitle={10th National Computer Security Conference, Baltimore, Maryland}, +Year={1987}, Month={21-24 September}, +pages={129-141}, Note={Reprinted in Rein Turn, +editor, {\it Advances in Computer +System Security}, Vol. 3, Artech House, Dedham, Massachusetts, 1988 }} + +@InProceedings{LOCK87-, +Key={Saydjari}, Author={O.S. Saydjari and J.M. Beckman +and J.R. Leaman}, Title={{LOCKing} Computers Securely}, + BookTitle={10th National Computer Security Conference, Baltimore, Maryland}, +Year={1987}, Month={21-24 September}, +pages={129-141} } + +@TechReport{Fine+, +Author={T. Fine and J.T. Haigh and R.C. O'Brien and +D.L. Toups}, Title={An Overview of the {LOCK} {FTLS}}, +Institution={Honeywell}, Month={}, Year=1988 } + +@TechReport{HaighFTLS, +Author={J.T. Haigh}, Title={Top Level Security +Properties for the {LOCK} System}, Institution={Honeywell}, Month={}, Year=1988 } + +@TechReport{SCTC-B10, +Author={{Secure Computing Technology Center}}, +Title={{LOCK} Formal Top Level Specification, Volumes 1-6}, +Institution={SCTC}, Month={}, Year=1988 } + +@TechReport{SCTC-007, +Author={J.T. {Haigh et al.}}, Title={Assured Service Concepts and Models, +Final Technical Report, Volume 1: Summary}, +Institution={Secure Computing Technology Corporation}, Month=jul, Year=1991 } + +@TechReport{SCTC-B11, +Author={{Secure Computing Technology Center}}, +Title={{LOCK} Software {B}-Specification, Vol. 2}, +Institution={SCTC}, Month={}, Year=1988 } + +@TechReport{SCTC-005, +Author={J.T. {Haigh et al.}}, Title={Assured Service Concepts and Models, +Final Technical Report, Vol. 3: Security in Distributed Systems}, +Institution={Secure Computing Technology Corporation}, Month=jul, Year=1991 } + +@TechReport{SCTC-004, +Author={J.T. {Haigh et al.}}, Title={Assured Service Concepts and Models, +Final Technical Report, Vol. 4: Availability in Distributed {MLS} Systems}, +Institution={Secure Computing Technology Corporation}, Month=jul, Year=1991 } + +@TechReport{OBrien90, +Author={R.C. {O'Brien} and J.T. Haigh and D.J. Thomsen}, +Title={Trusted Database Consistency Policy}, +Institution={Rome Air Development Center}, +Address={Griffiss Air Force Base, NY}, +number={RADC-TR-90-387}, +Month=dec, Year={1990} } + +@TechReport{MoitraSchneider90, +Author={A. Moitra and E.A. Schneider}, +Title={Basic Technology for {SDI} Computer Security: {SDI} Real Time +Trusted Computer Based Requirements}, +Institution={Rome Air Development Center}, +Address={Griffiss Air Force Base, NY}, +number={RADC-TR-90-435, vol. III}, +Month=dec, Year={1990} } + +@manual{Net:Criteria, + Key={DoDCSC}, + Organization={Department of Defense Computer Security Center}, + Title={Proceedings of the Department of Defense Computer Security Center Invitational Workshop on Network Security}, + Month=mar, + Year={1985}, + Address={New Orleans, LA} + } + +@InProceedings{Rushby85a, + Key={Rushby}, + Author={J.M. Rushby}, + Booktitle={Proceedings of the Department of Defense Computer Security Center Invitational Workshop on Network Security}, + Organization={Publ. by Department of Defense Computer Security Center}, + Title={Report of the Working Group on Verification and Covert Channels}, + Month=mar, + Year={1985}, + Address={New Orleans, LA}, + Pages={7--5 to 7--12} + } + +@InProceedings{Rushby85, + Key={Rushby}, + Author={J.M. Rushby}, + Booktitle={Proceedings of the Department of Defense Computer Security Center Invitational Workshop on Network Security}, + Organization={publ. by Department of Defense Computer Security Center}, + Title={Networks are Systems}, + Month=mar, + Year={1985}, + Address={New Orleans, Louisiana}, + Pages={7--24 to 7--37} + } + +@TechReport{Ezhilchelvan, + Key={Ezhilchelvan}, + Author={P.D. Ezhilchelvan and S.K. Shrivastava}, + Institution={Computing Laboratory, University of Newcastle upon Tyne}, + Title={A Characterisation of Faults in Systems}, + Year={1985}, + Month=sep, + Number={206} + } + +@InProceedings{Schell84, + Key={Schell}, + Author={R.R. Schell and T.F. Tao}, + BookTitle={Proceedings of the Seventh DoD/NBS Computer Security Initiative Conference}, + Title={Microcomputer-Based Trusted Systems for Communications and +Workstation Applications}, + Address={Gaithersburg, Maryland}, + Pages={277--290}, + Year={1984}, + Month=sep + } + +@TechReport{Gordon:Why, + Key={Gordon}, + Author={M. Gordon}, + Institution={University of Cambridge Computer Laboratory}, + Title={Why Higher-Order Logic is a Good Formalism for Specifying and +Verifying Hardware}, + Year={1985}, + Month=sep, + Number={77} + } + +@TechReport{Gordon:HOL85, + Key={Gordon}, + Author={M. Gordon}, + Institution={University of Cambridge Computer Laboratory}, + Title={{HOL:} A Machine Oriented Formulation of Higher Order Logic}, + Address = {Cambridge, England}, + Year={1985}, + Month=jul, + Number={68} + } + +@Book{Barringer:Book, + Key={Barringer}, + Author={H. Barringer}, + Publisher={Springer-Verlag, Berlin, + Lecture Notes in Computer Science, Vol. 191}, + Title={A Survey of Verification Techniques for Parallel Programs}, + Year={1985} + } + +@Book{LCF, + Key={Gordon}, + Author={M. Gordon and R. Milner and C. Wadsworth}, + Publisher={Springer-Verlag, Berlin, + Lecture Notes in Computer Science, Vol. 78}, + Title={Edinburgh {LCF}: A Mechanized Logic of Computation}, + Year={1979} + } + +@InProceedings{Barringer:Compose, + Key={Barringer}, + Author={H. Barringer and R. Kuiper and A. Pnueli}, + BookTitle={Proceedings of the Sixteenth ACM Symposium on Theory of Computing}, + Title={Now you May Compose Temporal Logic Specifications}, + Year={1984}, + Address={Washington, D.C.}, + Month=may + } + +@Article{Joseph+Birman, + Key={Joseph}, + Author={T.A. Joseph and K.P. Birman}, + Journal={ACM TOCS}, + Title={Low Cost Management of Replicated Data in Fault-Tolerant +Distributed Systems}, + Year={1986}, + Month=feb, + Pages={54--70}, + Volume={4}, + Number={1} + } + +@Article{Bernstein84, + Key={Bernstein}, + Author={P.A. Bernstein and N. Goodman}, + Journal={ACM TODS}, + Title={An Algorithm for Concurrency Control and Recovery in +Replicated Distributed Databases}, + Year={1984}, + Month=dec, + Pages={596--615}, + Volume={9}, + Number={4} + } + +@InProceedings{Melliar-Smith+Rushby, + Key={Melliar-Smith}, + Author={P.M. Melliar-Smith and J.M. Rushby}, + BookTitle={Proceedings of the {VERkshop III}}, + Address={Watsonville, California}, + Title={The {Enhanced HDM} System for Specification and Verification}, + Year={1985}, + Pages={41--43}, + Month=feb, + Note={Published as ACM Software Engineering Notes, Vol. 10, No. 4, Aug. 85} + } + +@InProceedings{Musser85, + Author={D.R. Musser}, + BookTitle={Proceedings of the {VERkshop III}}, + Address={Watsonville, California}, + Title={Aids to Hierarchical Specification Structuring and Reusing Theorems in +{AFFIRM-85}}, + Year={1985}, + Pages={2--4}, + Month=feb, + Note={Published as ACM Software Engineering Notes, Vol. 10, No. 4, Aug. 85} + } + +@InProceedings{Guttman, + Key={Guttman}, + Author={Joshua Guttman}, + BookTitle={Proceedings of the 1987 IEEE Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={Information Flow and Invariance}, + Pages={67--73}, + Month=apr, + Year={1987} + } + +@manual{EHDM:Userguide, +Author={SRI-CSL}, +Key = {EHDM}, Title= +{E{\sc HDM} Specification and Verification System -- Version 6.1: User's Guide}, +Organization={Computer Science Laboratory, SRI International}, +Year={1992}, Month={March 27,}, Address={Menlo Park, California} } + +@manual{EHDM:Language, +Author={SRI-CSL}, +Key = {EHDM}, +Organization={Computer Science Laboratory, SRI International}, Title={{\sc +Ehdm} Specification and Verification System Version 4.1: Preliminary +Definition of the {EHDM} Specification Language}, Year={1988}, +day={6}, month=sep, Address={Menlo Park, California} } + +@manual{EHDM:Tutorial, AUTHOR = {F. von Henke and J.M. Rushby}, +Key = {EHDM}, +Organization={Computer Science Laboratory, SRI International}, +Title={Introduction to {E\sc HDM}}, Year={1988}, Month=sep, +Address={Menlo Park, California} } + +@manual{EHDM:semantics, AUTHOR = {F. von Henke and N. Shankar and J.M. Rushby}, +Key = {EHDM}, +Organization={Computer Science Laboratory, SRI International}, +Title={Formal Semantics of EHDM}, +Year={1988}, Month={September 28,}, Address={Menlo Park, California} } + +@TechReport{EHDM:intro, AUTHOR = {J.M. Rushby and F. von Henke and S. Owre}, +Key = {Rushby}, +Organization={Computer Science Laboratory, SRI International}, +Title={An Introduction to Formal Specification and Verification +Using {EHDM}}, +Number = {SRI-CSL-91-02}, +Year={1991}, Month=feb, Address={Menlo Park, California} } + +@PhDThesis{Rushby77, Key={Rushby}, Author={J.M. Rushby}, School={Computing +Laboratory, University of Newcastle upon Tyne}, Title={{LR}(k) Sparse-Parsers +and their Optimisation}, Year={1977}, Month=sep } + +@InProceedings{CarlsonLunt86, Key="Carlson", + Author="R.A. Carlson and T.F. Lunt", + Title="The Trusted Domain Machine: A Secure Communication Device +for Security Guard Applications", + BookTitle="Proceedings of the 1986 Symposium on Security and Privacy", + Organization="IEEE Computer Society", + Address="Oakland, California", Year="1986", Month=apr, pages="182-186"} + +@InProceedings{Carlson+Lunt86, Key={Carlson}, Author={R.A. Carlson and T.F. +Lunt}, BookTitle={Proceedings of the 1986 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Title={The {Trusted Domain Machine}: a +Secure Communication Device for Security Guard Applications}, Year={1986}, +Address={Oakland, California}, Month=apr, Pages={182--186} } + +@Article{Huguet, Key={Huguet}, Author={M. Huguet}, Journal={ACM Computer +Architecture News}, Title={The Protection of the Processor Status Word of the +{PDP}-11/60}, Year={1982}, Month=jun, Pages={27--30}, Volume={10}, +Number={4} } + +@Article{Popek+Goldberg, +Key={Popek}, Author={G.J. Popek and R.P. +Goldberg}, Journal={Communications of the ACM}, Title={Formal Requirements for Virtualizable Third +Generation Architectures}, Year={1974}, Month=jul, Pages={412--421}, +Volume={17}, Number={7} } + +@Article{Saltzer74, +Key={Saltzer}, Author={J.H. Saltzer}, Journal={Communications of the ACM}, +Title={Protection and the Control of Information Sharing in {Multics}}, +Year={1974}, Month=jul, Pages={388--402}, Volume={17}, Number={7} } + +@InProceedings{RedellFabry74, +Author={D.D. Redell and R.S. Fabry}, +TITLE = {Selective Revocation of Capabilities}, +Booktitle = {Proceedings of the International Workshop on Protection in + Operating Systems}, +YEAR = {1974}, Location = {IRIA, Rocquencourt, France}, +VOLUME = {}, +NUMBER = {}, PAGES = {197--209}, MONTH = aug } + +@PhDThesis{Redell74, +Author={D.D. Redell}, School={University of California at Berkeley}, +Title={Naming and Protection in Extendible Operating Systems}, +Note = {Also MIT Project MAC TR-104.}, +Year={1974}, Month={} } + +@Article{Fabry74, +Key={Fabry}, Author={R.S. Fabry}, Journal={Communications of the ACM}, +Title={Capability-Based Addressing}, +Year={1974}, Month=jul, Pages={403--412}, Volume={17}, Number={7} } + +@TechReport{Schiller75, Key={Schiller}, Author={W.L. +Schiller}, Institution={Mitre Corporation}, Title={The Design and Specification +of a Security Kernel for the {PDP}-11/45}, Year={1975}, Month=mar, +Number={MTR-2934}, Address={Bedford, Massachusetts} } + +@TechReport{Smith75, Key={Smith}, +Author={L. Smith}, Institution={Mitre Corporation}, Title={Architectures for +Secure Computer Systems}, Year={1975}, Month=apr, Number={ESD-TR-75-51}, +Address={Bedford, Massachusetts} } + +@Article{Hoare72, Key={Hoare}, Author={C.A.R. Hoare}, +Journal={Acta Informatica}, Title={Proof of Correctness of Data +Representations}, Year={1972}, Pages={271--281}, Volume={1} } + +@Article{Harrison:Protection, Key={Harrison}, Author={M.A. Harrison and W.L. +Ruzzo and J.D. Ullman}, Journal={Communications of the ACM}, Title={Protection in Operating +Systems}, Year={1976}, Month=aug, Pages={461--471}, Volume={19}, +Number={8} } + +@Article{Harrison76x, +Author={M.A. Harrison and W.L. Ruzzo and J.D. Ullman}, +Title={Protection in Operating Systems}, +Journal={Communications of the ACM}, +volume=19, +number=8, +month=aug, +year=1976 } + +@inproceedings{Anderson:Evaluation, Key={Anderson}, Author={T. +Anderson and P.A. Barrett and D.N. Halliwell and M.R. Moulding}, Title={An +Evaluation of Software Fault Tolerance in a Practical System}, +Booktitle={Digest of Papers, Fault Tolerant Computing Symposium 15}, +Address={Ann Arbor, Michigan}, +Organization={IEEE Computer Society}, Month=jun, Year={1985}, +Pages={140--145} } + +@Article{Alford85, Key={Alford}, Author={M.W. Alford}, +Journal={Computer}, Title={{SREM} at the Age of Eight; The +Distributed Computing Design System}, Year={1985}, Month=apr, +Pages={36--46}, Volume={18}, Number={4} } + +@Article{Roman85, Key={Roman}, +Author={G--C. Roman}, Journal={Computer}, Title={A Taxonomy of Current +Issues in Requirements Engineering}, Year={1985}, Month=apr, +Pages={14--21}, Volume={18}, Number={4} } + +@Article{Scheffer85, Key={Scheffer}, +Author={P.A. Scheffer and A.H. {Stone III} and W.E. Rzepka}, Journal={IEEE +Computer}, Title={A Case Study of {SREM}}, Year={1985}, Month=apr, +Pages={47--54}, Volume={18}, Number={4} } + +@InProceedings{Silverman83, + Key={Silverman}, + Author={J.M. Silverman}, + Title={Reflections on the Verification of the Security of an Operating System Kernel}, + BookTitle={Proceedings of the Ninth ACM Symposium on Operating Systems Principles}, + Year={1983}, + Address={Bretton Woods, NH}, + Month=oct, + Note={(ACM Operating Systems Review, Vol 17, No. 5)} + } + +@Article{Celko83, + Key={Celko}, + Author={J. Celko and J.S. Davis and J. Mitchell}, + Journal={SIGPLAN Notices }, + Title={A Demonstration of Three Requirements Language Systems}, + Year={1983}, + Month=jan, + Pages={9--14}, + Volume={18}, + Number={1} + } + +@Article{Bell77, + Key={Bell}, + Author={T.E. Bell and D.C. Bixler and M.E. Dyer}, + Journal={IEEE Transactions on Software Engineering}, + Title={An Extendable Approach to Computer--Aided Software Requirements Engineering}, + Year={1977}, + Month=jan, + Pages={49--59}, + Volume={SE--3}, + Number={1} + } + +@Article{Alford77, + Key={Alford}, + Author={M.W. Alford}, + Journal={IEEE Transactions on Software Engineering}, + Title={A Requirements Engineering Methodology for Real--Time Processing Requirements}, + Year={1977}, + Month=jan, + Pages={60--69}, + Volume={SE--3}, + Number={1} + } + +@Article{Davis77, + Key={Davis}, + Author={C.G. Davis and C.R. Vick}, + Journal={IEEE Transactions on Software Engineering}, + Title={The Software Development System}, + Year={1977}, + Month=jan, + Pages={69--84}, + Volume={SE--3}, + Number={1} + } + +@Article{Basili84, + Key={Basili}, + Author={V.R. Basili and B.T. Perricone}, + Journal={Communications of the ACM}, + Title={Software Errors and Complexity: {An} Empirical Investigation}, + Year={1984}, + Month=jan, + Pages={42--52}, + Volume={27}, + Number={1} + } + +@Article{Moriconi85, + Key={Moriconi}, + Author={M. Moriconi and D.F. Hare}, + Journal={Computer}, + Title={Visualizing Program Designs through {PegaSys}}, + Year={1985}, + Month=aug, + Volume={18}, + Number={8}, + Pages={72--85} + } + +@Article{Moriconi86a, + Key={Moriconi}, + Author={M. Moriconi and D.F. Hare}, + Journal={ACM Transactions on Programming Languages and Systems}, + Title={The {PegaSys} System: {Pictures} as Formal Documentation of Large Programs}, + Year={1986}, + Month=oct, + Pages={524--546}, + Volume={8}, + Number={4} + } + +@InProceedings{Moriconi86b, + Key={Moriconi}, + Author={M. Moriconi}, + Publisher={Springer-Verlag, Berlin, Lecture Notes in Computer Science}, + Title={{PegaSys} and the Role of Logic in Programming Environments}, + Year={1986}, + Month=jun, + Address={Trondheim, Norway}, + booktitle={Proceedings of the International Workshop on Advanced Programming Environments} + } + +@Article{Stevens74, + Key={Stevens}, + Author={W.P. Stevens and G.F. Myers and L.C. Constantine}, + Journal={IBM Systems Journal}, + Title={Structured Design}, + Year={1974}, + Volume={13}, + Number={2}, + Pages={115--139} + } + +@Article{Leveson86, + Author={N.G. Leveson}, Journal={ACM Computing Surveys}, + Title={Software Safety: {Why}, What, and How}, + Year={1986}, Volume={18}, Number={2}, Month=jun, Pages={125--163} +} + +@TechReport{IITRI, +Key={IITRI}, + Author={Anonymous}, + Title={{Ada} Verification System ({AVS}) Studies}, + Institution={IIT Research Institute}, + Year=1987, + Address={4550 Forbes Blvd., Suite 300, Lanham, Maryland 20706}, + Type={Draft Final Report}, + Month=feb, + Note={Prepared for: Defense Communications Engineering Center, 1860 +Wiehle Avenue, Reston, VA 22090-5500} +} + +@INPROCEEDINGS{MusserStepanov, + AUTHOR = {D.R. Musser and A.A. Stepanov}, + TITLE = {Generic Algorithms + Generic Data Structures = Reusable Software}, + BOOKTITLE = {Tenth Minnowbrook Workshop}, + YEAR = {1987} +} + +@BOOK{Booch, + AUTHOR = {G. Booch}, + TITLE = {Software Components in {Ada}}, + PUBLISHER = {Benjamin/Cummings}, + YEAR = {1987} +} + +@INPROCEEDINGS{Musser802, + AUTHOR = {D.R. Musser}, + TITLE = {On Proving Inductive Properties of Abstract Data Types}, + BOOKTITLE = {Seventh ACM Symposium on Principles of Programming Languages}, + YEAR = {1980}, + ADDRESS = {Las Vegas, NV}, + MONTH = Jan +} + +@INPROCEEDINGS{MOK87, +Author={Al Mok}, +Key={Mok}, +Year=1987, +Month=jul, +Title={Annotating {Ada} for Real Time Program Synthesis}, +BookTitle={Proceedings of the COMPASS 87}, +Organization={IEEE}, +Pages={63--66}} + +@Unpublished{MCHUGHMS, + Key={McHugh}, + Author={J. McHugh}, + Title={Structured Development and Constructive Proof of a Real Time +Data Acquisition System}, + Institution={University of Maryland at College Park}, + Year={1975}, + Location={University of Maryland, Computer Science Center Library}, + Note={M.S. Scholarly Paper, University of Maryland}} + +@TECHREPORT{Kemmerer:assess, + AUTHOR = {R.A. Kemmerer}, + TITLE = {Verification Assessment Study Final Report}, + INSTITUTION = {National Computer Security Center}, + YEAR = {1986}, + NUMBER = {C3-CR01-86}, + ADDRESS = {Ft. Meade, Maryland}, + NOTE = {5 Volumes. US distribution only} +} + +@manual{gypsy-methodology, + Author={ M.K. Smith and D.I. Good and B.L. DiVito}, + Key={Good}, + Title={Using the {Gypsy} Methodology: {DRAFT}, nov 1987}, + Year={1987}, + Organization={Computational Logic Inc.}} + +@manual{gypsy21, + Author={D.I. Good}, + Key={Good}, + Title={Revised Report on {Gypsy} 2.1: {DRAFT}, jul 1984}, + Year={1984}, + Organization={Institute for Computing Science, +The University of Texas at Austin}} + +@manual{gypsy205, + Author={D.I. Good and R.L. Akers and L.M. Smith}, + Key={Good}, + Title={Report on {Gypsy} 2.05: oct 1986}, + Year={1986}, + Organization={Computational Logic Inc.}} + +@TechReport{Bevier87, + AUTHOR = {W.R. Bevier}, + TITLE = {A Verified Operating System Kernel}, + Institution = {Ph.D. thesis, +Department of Computer Science, The University of Texas at Austin}, + YEAR = {1987} +} + +@MANUAL{KapurZhang, + TITLE = {{RRL}: A User's Manual}, + AUTHOR = {D. Kapur and H. Zhang}, + ORGANIZATION = {General Electric Corporate Research and Development}, + ADDRESS = {Schenectady, NY}, + MONTH = mar, + YEAR = {1986}, + NOTE = {Unpublished Manuscript} +} + +@ARTICLE{IOTA, + AUTHOR = {T. Yuasa and R. Nakajima}, + TITLE = {{IOTA}: A Modular Programming System}, + JOURNAL = {IEEE Transactions on Software Engineering}, + YEAR = {1985}, + VOLUME = {SE-11}, + NUMBER = {2}, + PAGES = {179--187}, + MONTH = feb +} + +@BOOK{ANNA, + AUTHOR = {David C. Luckham and Friedrich W. von Henke and Bernd Krieg-Br\"{u}ckner and Olaf Owe}, + TITLE = {{ANNA} A Language for Annotating {Ada} Programs}, + PUBLISHER = {Springer-Verlag, Berlin, + Lecture Notes in Computer Science, Vol 260}, + YEAR = {1987} } + +@BOOK{IOTA-book, + EDITOR = {R. Nakajima and T. Yuasa}, + TITLE = {The {IOTA} Programming System}, + PUBLISHER = {Springer-Verlag, Berlin, + Lecture Notes in Computer Science, Vol 160}, + YEAR = {1982} } + +@TECHREPORT{Gerhart:overview, + AUTHOR = {Susan L. Gerhart}, + TITLE = {Design Technology Assessment: Overview}, + INSTITUTION = {MCC}, + YEAR = {1986}, + NUMBER = {STP-078-86}, + ADDRESS = {Austin, TX}, + MONTH = feb +} + +@TECHREPORT{Harel:statecharts, + AUTHOR = {David Harel}, + TITLE = {Statecharts: a Visual Approach to Complex Systems}, + INSTITUTION = {MCC}, + YEAR = {1986}, + ADDRESS = {Austin, TX}, + MONTH = feb +} + + +@TECHREPORT{statecharts, + AUTHOR = {G.R. Burns and S.L. Gerhart and I. Forman and M. Graf}, + TITLE = {Design Technology Assessment: The Statecharts Approach}, + INSTITUTION = {MCC}, + YEAR = {1986}, + NUMBER = {STP-107-86}, + ADDRESS = {Austin, TX}, + MONTH = mar +} + +@ARTICLE{Clarke86, + AUTHOR = {E.M. Clarke and E.A. Emerson and A.P. Sistla}, + TITLE = {Automatic Verification of Finite-State Concurrent Systems using Temporal Logic Specifications}, + JOURNAL = {ACM Transactions on Programming Languages and Systems}, + YEAR = {1986}, + VOLUME = {8}, + NUMBER = {2}, + PAGES = {244--263}, + MONTH = apr +} + +@TECHREPORT{siftproof, + AUTHOR = {L. Moser and P.M. Melliar-Smith and R. Schwartz}, + TITLE = {Design Verification of {SIFT}}, + MONTH = sep, + YEAR = {1987}, + INSTITUTION = {NASA Langley Research Center}, + TYPE = {Contractor Report}, + NUMBER = 4097, + ADDRESS = {Hampton, Virginia} +} + +@ARTICLE{Church:types, + AUTHOR = {A. Church}, + TITLE = {A Formulation of the Simple Theory of Types}, + JOURNAL = {Journal of Symbolic Logic}, + YEAR = {1940}, + VOLUME = {5} } + +@inproceedings{metavcg, +author = {M. Moriconi and R.L. Schwartz}, +title = {Automatic Construction of Verification Condition + Generators from {Hoare} Logics}, +booktitle = {Proceedings of the Eighth International Colloquium on + Automata, Languages, and Programming}, +address = {Acre (Akko), Israel}, +pages = {363--377}, +month = jul, +publisher = {Springer-Verlag, Berlin, + Lecture Notes in Computer Science, No. 115}, +year = 1981 } + +@article{moriconi:dva, +author = {M. Moriconi}, +title = {A designer/verifier's assistant}, +journal = {ieeese}, +volume = {SE-5}, +number = 4, +month = jul, +year = {1979}, +pages = {387--401}, +note = {Reprinted in {\it Artificial Intelligence and Software +Engineering}, edited by C.\ Rich and R.\ Waters, Morgan Kaufmann +Publishers, Inc., 1986. Also reprinted in {\it Tutorial on +Software Maintenance}, edited by G.\ Parikh and N.\ Zvegintzov, +IEEE Computer Society Press, 1983.} } + +@phdthesis{moriconi:thesis, +author = {M. Moriconi}, +title = {A system for incrementally designing and verifying programs}, +school = {Computer Science Department, + The University of Texas at Austin}, +month = dec, +year = 1977, +note = {Also Technical Report CSL--73 and CSL--74, + Computer Science Laboratory, SRI International, + and Technical Reports ISI/RR--77--64 and + ISI/RR--77--66, USC/Information Sciences Institute} } + +@ARTICLE{MoriconiWinkler90, +Author={M. Moriconi and T.C. Winkler}, +TITLE = {Approximate Reasoning About the Semantic Effects of Program Changes}, +JOURNAL = {IEEE Transactions on Software Engineering}, YEAR = {1990}, VOLUME = {16}, +NUMBER = {9}, PAGES = {990-1004}, MONTH = sep } + +@manual{Ada83, + key={DoD}, + title={Reference Manual for the {Ada} Programming Language}, + month=jan, + year=1983, + organization={United States Department of Defense}, + note={ANSI/MIL-STD-1815 A}} + +@ARTICLE{Barringer+Mearns, + AUTHOR = {H. Barringer and I. Mearns}, + TITLE = {Axioms and Proof Rules for {Ada} Tasks}, + JOURNAL = {IEE Proceedings}, + YEAR = {1982}, + VOLUME = {129}, + NUMBER = {Part E, Number 2}, + MONTH = Mar +} + +@MASTERSTHESIS{Mearns, + AUTHOR = {I. Mearns}, + TITLE = {A Message-Based Run-Time System and proof Rules for {Ada} Tasks}, + SCHOOL = {Department of Computer Science, University of Manchester}, + YEAR = {1981}, + MONTH = Oct +} + +@TECHREPORT{Ada:libraries, + AUTHOR = {J.A. Goguen and K.N. Levitt}, + TITLE = {Report on {Ada} Program Libraries Workshop}, + INSTITUTION={Computer Science Laboratory, SRI International}, + YEAR = {1983}, + TYPE = {Report for SRI Project 6186}, + ADDRESS = {Menlo Park, California}, + MONTH = nov +} + +@ARTICLE{Goguen:LIL, + AUTHOR = {J.A. Goguen}, + TITLE = {Reusing and Interconnecting Software Components}, + JOURNAL = {Computer}, + YEAR = {1986}, + VOLUME = {19}, + NUMBER = {2}, + PAGES = {16--28}, + MONTH = feb +} + +@InProceedings{McCullough87, + Author={D. McCullough}, + BookTitle={Proceedings of the 1987 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Title={Specifications for Multi-Level Security and a Hook-Up Property}, + Year={1987}, + Address={Oakland, California}, + Month=apr, + Pages={161--166} +} + +@InProceedings{McCullough88, + Author={D. McCullough}, + BookTitle={Proceedings of the 1988 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Title={Noninterference and Composability of Security Properties}, + Year={1988}, Address={Oakland, California}, Month=apr, Pages={177--186} } + +@TechReport{McCullough88b, +author = {D. McCullough}, key = {McCullough}, +title = {Ulysses Security Properties Modeling Environment: The Theory of Security}, +institution = {Odyssey Research Associates}, +year = {1988}, address = {Ithaca, New York}, MONTH = jul } + +@inproceedings{Wong+89, +author={R. Wong and M. Chacko and E. Ding and B. Kahn +and N.E. Proctor and J. Sebes and R. Varadarajan}, title={The {SDOS} System: {A} +{S}ecure {D}istributed {O}perating {S}ystem Prototype}, +booktitle={Proceedings of the Twelfth National Computer Security Conference}, +address={Baltimore, Maryland}, +month=oct, pages={172-183}, year=1989 } + +@TechReport{SDOS89-SDD, +author = {{ORA Corp.}}, key = {ORA}, +title = {Software Design Document for the (THETA) Experimental Secure Distributed +Operating System Development (8 volumes)}, +institution = {Odyssey Research Associates}, +year = {1989}, address = {Ithaca, New York}, MONTH = {30 December} } + +@TechReport{SDOS89-FSM, +author = {{ORA Corp.}}, key = {ORA}, +title = {Formal Security Model +for the Experimental Secure Distributed Operating System Development}, +institution = {Odyssey Research Associates}, +year = {1989}, address = {Ithaca, New York}, MONTH = {7 October} } + +@TechReport{THETA91-SRS, +author = {{ORA Corp.}}, key = {ORA08}, +title = {Software Requirements Specification +for the {(THETA)} {E}xperimental {S}ecure {D}istributed {O}perating {S}ystem +Development}, institution = {ORA Corporation},year = {1991},address = {Ithaca, New York}, +day={15}, month=jul, Note ={Rome Laboratory Contract F30602-88-C-0146, +CDRL A008.} } + +@TechReport{THETA91-FSM, +author = {{ORA Corp.}}, key = {ORA09}, +title = {Formal security model specification +for the {(THETA)} {E}xperimental {S}ecure {D}istributed {O}perating {S}ystem +Development}, institution = {ORA Corporation},year = {1991},address = {Ithaca, New York}, +day={15}, month=jul, Note ={Rome Laboratory Contract F30602-88-C-0146, +CDRL A009.} } + +@TechReport{THETA91-SPM, +author = {{ORA Corp.}}, key = {ORA10}, +title = {Software programmer's manual +for the {(THETA)} {E}xperimental {S}ecure {D}istributed {O}perating {S}ystem +Development}, institution = {ORA Corporation},year = {1991},address = {Ithaca, New York}, +day={15}, month=jul, Note ={Rome Laboratory Contract F30602-88-C-0146, +CDRL A010.} } + +@TechReport{THETA91-SDD, +author = {{ORA Corp.}}, key = {ORA11}, +title = {Software Design Document for the +{(THETA)} {E}xperimental {S}ecure {D}istributed {O}perating {S}ystem Development}, +institution = {ORA Corporation}, +year = {1991}, address = {Ithaca, New York}, day={15}, month=jul, +Note ={Rome Laboratory Contract F30602-88-C-0146, +CDRL A011: Volume I, Part I, Volume II, Parts II-VIII.} } + +@TechReport{THETA91-SDDI, +author = {{ORA Corp.}}, key = {ORA11a}, +title = {Software Design Document for the +{(THETA)} {E}xperimental {S}ecure {D}istributed {O}perating {S}ystem Development}, +institution = {ORA Corporation}, +year = {1991}, address = {Ithaca, New York}, day={15}, month=jul, +Note ={Rome Laboratory Contract F30602-88-C-0146, +CDRL A011: Volume I, Part I.} } + +@TechReport{THETA91-SDDII, +author = {{ORA Corp.}}, key = {ORA11b}, +title = {Software Design Document for the +{(THETA)} {E}xperimental {S}ecure {D}istributed {O}perating {S}ystem Development}, +institution = {ORA Corporation}, +year = {1991}, address = {Ithaca, New York}, day={15}, month=jul, +Note ={Rome Laboratory Contract F30602-88-C-0146, +CDRL A011: Volume II, Parts II-VIII.} } + +@TechReport{THETA91-DP, +author = {{ORA Corp.}}, key = {ORA16}, +title = {Demonstration Plan +for the {(THETA)} {E}xperimental {S}ecure {D}istributed {O}perating {S}ystem +Development}, institution = {ORA Corporation},year = {1991},address = {Ithaca, New York}, +day={15}, month=jul, Note ={Rome Laboratory Contract F30602-88-C-0146, +CDRL A016.} } + +@TechReport{THETA91-SUM, +author = {{ORA Corp.}}, key = {ORA17}, +title = {Software user's manual +for the {(THETA)} {E}xperimental {S}ecure {D}istributed {O}perating {S}ystem +Development}, institution = {ORA Corporation},year = {1991},address = {Ithaca, New York}, +day={15}, month=jul, Note ={Rome Laboratory Contract F30602-88-C-0146, +CDRL A017.} } + +@TechReport{THETA91-FIN, +author = {{ORA Corp.}}, key = {ORA21}, +title = {Final Report for the +{(THETA)} {E}xperimental {S}ecure {D}istributed {O}perating {S}ystem +Development}, institution = {ORA Corporation},year = {1991}, +address = {Ithaca, New York}, day={15}, month=jul, +Note ={Rome Laboratory Contract F30602-88-C-0146, CDRL A021.} } + +@inproceedings{McEnerney90, +author={J.R. McEnerney and D.G. Weber and R. Brown}, +title={Automated Extensibility in {THETA}}, +booktitle={Proceedings of the Thirteenth National Computer Security Conference}, +address={Washington, D.C.}, +month=oct, pages={144--153}, year=1990 } + +@InProceedings{Jacob88, + Author={Jeremy Jacob}, + BookTitle={Proceedings of the 1988 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Title={Security Specifications}, + Year={1988}, + Address={Oakland, California}, + Month=apr, + Pages={14--23} +} + +@InProceedings{Gligor83, + Key={Gligor}, Author={V.D. Gligor}, + BookTitle={Proceedings of the 1983 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Title={A Note on the Denial-of-Service Problem}, + Address="Oakland, California", Year={1983}, Month=apr, pages={139-149} } + +@InProceedings{Yu88, +Key={Yu}, Author={C.-F. Yu and V.D. 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MacEwan}, + TITLE = {The Development and Proof of a Formal Specification for a Multi-Level Secure System}, + JOURNAL = {tocs}, + YEAR = {1987}, + VOLUME = {5}, + NUMBER = {2}, + PAGES = {151--184}, + MONTH = may +} + +@TECHREPORT{Rushby:Calculus, + AUTHOR = {J.M. Rushby}, + TITLE = {Security Policies for Distributed Systems: A Model and Calculus}, + INSTITUTION = {Computer Science Laboratory, SRI International}, + YEAR = {1987}, + ADDRESS = {Menlo Park, California}, + MONTH = may, + NOTE = {(Draft)} +} + +@INPROCEEDINGS{Rushby:safety-original, + AUTHOR = {J.M. Rushby}, + TITLE = {Kernels for Safety?}, + BOOKTITLE = {Proceedings of the Safety and Security Symposium}, + YEAR = {1986}, + ORGANIZATION = {Centre for Software Reliability}, + ADDRESS = {Glasgow, Scotland}, + MONTH = oct +} + + +@INCOLLECTION{Rushby:safety, + AUTHOR = {J.M. Rushby}, + TITLE = {Kernels for Safety?}, + BOOKTITLE = {Safe and Secure Computing Systems}, + PUBLISHER = {Blackwell Scientific Publications}, + YEAR = {1989}, + EDITOR = {T. Anderson}, + CHAPTER = {13}, + PAGES = {210--220}, + NOTE = {Proceedings of a Symposium held in Glasgow, October 1986} +} + +@INCOLLECTION{Rushby:networks, + AUTHOR = {J.M. Rushby}, + TITLE = {Networks are Systems}, + BOOKTITLE = {Tutorial: Computer and Network Security}, + PUBLISHER = {IEEE Computer Society Press}, + YEAR = {1986}, + EDITOR = {Marshall D. Abrams and Harold J. Podell}, + PAGES = {300--316} +} + +@MANUAL{DRC:SDI, + TITLE = {Distributed Systems Technology Assessment for {SDI}}, + ORGANIZATION = {Dynamics Research Corporation}, + ADDRESS = {Wilmington, Massachusetts}, + MONTH = sep, + YEAR = {1986}, + NOTE = {Final Report to Rome Air Development Center, TEMS Task 0029, Contract F19628-84-D-0016} +} + +@ARTICLE{Schlichting+Schneider, + AUTHOR = {R.D. Schlichting and F.B. Schneider}, + TITLE = {Fail-Stop Processors: an approach to designing fault-tolerant computing systems}, + JOURNAL = {tocs}, + YEAR = {1983}, + VOLUME = {1}, + NUMBER = {3}, + PAGES = {222--238}, + MONTH = apr +} + +@INPROCEEDINGS{Butler:FTCS, + AUTHOR = {R.W. Butler and D.L. Palumbo and S.C. Johnson}, + TITLE = {Application of a Clock Synchronization Validation +Methodology to the {SIFT} Computer System}, + BOOKTITLE={Digest of Papers, FTCS 15}, + ADDRESS={Ann Arbor, Michigan}, + ORGANIZATION={IEEE Computer Society}, + PAGES = {194--199}, + MONTH=jun, + YEAR={1985}} + +@TECHREPORT{Butler:clock-survey, + AUTHOR = {R.W. Butler}, + TITLE = {A Survey of Provably Correct Fault-Tolerant Clock +Synchronization Techniques}, + YEAR = {1988}, + INSTITUTION = {NASA Langley Research Center}, + NUMBER ={TM-100553}, + MONTH = feb +} + +@INPROCEEDINGS{Dolev:possible, + AUTHOR = {D. Dolev and J.Y. Halpern and H.R. Strong}, + TITLE = {On the Possibility and Impossibility of Achieving Clock Synchronization}, + BOOKTITLE = {Proceedings of the Sixteenth Annual {ACM} Symposium on Theory of Computing}, + YEAR = {1984}, + PAGES = {504--511}, + ADDRESS = {Washington, D.C.}, + MONTH = apr +} + +@ARTICLE{Panzieri:Rajdoot, + AUTHOR = {F. Panzieri and S.K. Shrivastava}, + TITLE = {{Rajdoot}: a remote procedure call mechanism supporting orphan +detection and killing}, + JOURNAL = {IEEE Transactions on Software Engineering}, + YEAR = {1988}, + VOLUME = {SE-14}, + NUMBER = {1}, + PAGES = {30--37}, + MONTH = jan +} + +@MISC{OSCAR, + AUTHOR = {A.R. Downing and I.B. Greenberg and J.M. Peha}, + TITLE = {A Log-Based Replication and Consistency Scheme}, + HOWPUBLISHED = {Submitted for publication}, + MONTH = may, + YEAR = {1988} +} + +@INPROCEEDINGS{Cristian:delta, + AUTHOR = {Flaviu Cristian and Houtan Aghili and Ray Strong and Danny Dolev}, + TITLE = {Atomic Broadcast: from simple Message Diffusion to {Byzantine} Agreement}, + BOOKTITLE={Digest of Papers, FTCS 15}, + ADDRESS={Ann Arbor, Michigan}, + ORGANIZATION={IEEE Computer Society}, + PAGES = {200--206}, + MONTH=jun, + YEAR={1985}} + +@TECHREPORT{Cristian:membership, + AUTHOR = {Flaviu Cristian}, + TITLE = {Reaching Agreement on Processor Group Membership in Synchronous Distributed Systems}, + INSTITUTION = {IBM Almaden Research Center}, + YEAR = {1988}, + TYPE = {Research Report}, + NUMBER = {RJ 5964}, + ADDRESS = {San Jose, California}, + MONTH = mar +} + +@TECHREPORT{Cristian:issues, + AUTHOR = {Flaviu Cristian}, + TITLE = {Issues in the Design of Highly Available Computing Systems}, + INSTITUTION = {IBM Almaden Research Center}, + YEAR = {1987}, + TYPE = {Research Report}, + NUMBER = {RJ 5856}, + ADDRESS = {San Jose, California}, + MONTH = oct +} + +@INPROCEEDINGS{Cristian:presence, + AUTHOR = {Flaviu Cristian}, + TITLE = {Agreeing on who is Present and who is Absent in a Synchronous Distributed System}, + BOOKTITLE = {Digest of Papers, FTCS 18}, + YEAR = {1988}, + PAGES = {206--211}, + ORGANIZATION = {IEEE Computer Society}, + ADDRESS = {Tokyo, Japan}, + MONTH = jun +} + +@INPROCEEDINGS{Strom:volatile, + AUTHOR = {Robert E. Strom and David F. Bacon and Shaula A. Yemini}, + TITLE = {Volatile Logging in N-Fault-Tolerant Distributed Systems}, + BOOKTITLE = {Digest of Papers, FTCS 18}, + YEAR = {1988}, + PAGES = {44--49}, + ORGANIZATION = {IEEE Computer Society}, + ADDRESS = {Tokyo, Japan}, + MONTH = jun +} + +@ARTICLE{Birman:comms, + AUTHOR = {K.P. Birman and T.A. Joseph}, + TITLE = {Reliable Communication in the Presence of Failures}, + JOURNAL = {tocs}, + YEAR = {1987}, + VOLUME = {5}, + NUMBER = {1}, + PAGES = {47--76}, + MONTH = feb +} + +@ARTICLE{Strom:optimistic, + AUTHOR = {Robert E. Strom and Shaula Yemini}, + TITLE = {Optimistic Recovery in Distributed Systems}, + JOURNAL = {tocs}, + YEAR = {1988}, + VOLUME = {3}, + NUMBER = {3}, + PAGES = {204--226}, + MONTH = aug +} + +@TECHREPORT{Randell:duality, + AUTHOR = {S.K. Shrivastava and L.V. Mancini and B. Randell}, + TITLE = {On the Duality of Fault Tolerant System Structures}, + INSTITUTION = {Computing Laboratory, University of Newcastle upon Tyne}, + YEAR = {1987}, + NUMBER = {248}, + ADDRESS = {Newcastle upon Tyne, U.K.}, + MONTH = nov +} + +@ARTICLE{Randell:structure, + AUTHOR = {B. Randell}, + TITLE = {System Design and Structuring}, + JOURNAL = {Computer Journal}, + YEAR = {1986}, + VOLUME = {29}, + NUMBER = {4}, + PAGES = {300--306} +} + +@INPROCEEDINGS{Laprie:dependability, + AUTHOR = {J.-C. Laprie}, + TITLE = {Dependable Computing and Fault Tolerance: Concepts and Terminology}, + BOOKTITLE={Digest of Papers, FTCS 15}, + ADDRESS={Ann Arbor, Michigan}, + ORGANIZATION={IEEE Computer Society}, + PAGES = {2--11}, + MONTH=jun, + YEAR={1985}} + +@ARTICLE{Leveson+Knight86, +Author={J.C. Knight and N.G. Leveson}, +TITLE = {An Experimental Evaluation of the Assumption +of Independence in Multi-Version Programming}, +JOURNAL = {IEEE Transactions on Software Engineering}, +YEAR = {1986}, VOLUME = {SE-12}, +NUMBER = {1}, PAGES = {96-109}, MONTH = jan } + +@INPROCEEDINGS{Knight+Leveson:Vienna, + AUTHOR = {J.C. Knight and N.G. Leveson}, + TITLE = {An Empirical Study of Failure Probabilities in Multi-Version Software}, + BOOKTITLE={Digest of Papers, FTCS 16}, + ADDRESS={Vienna, Austria}, + ORGANIZATION={IEEE Computer Society}, + PAGES = {165--170}, + MONTH=jul, + YEAR={1986}} + +@ARTICLE{Brilliant89, +Author={S. Brilliant and J.C. Knight and N.G. Leveson}, +TITLE = {The Consistent Comparison Problem in N-Version Programming}, +JOURNAL = {IEEE Transactions on Software Engineering}, YEAR = {1989}, +VOLUME = {SE-15}, NUMBER = {11}, PAGES = {}, MONTH = nov } + +@ARTICLE{Brilliant90, +Author={S.S. Brilliant and J.C. Knight and N.G. Leveson}, +TITLE = {Analysis of Faults in an N-Version Software Experiment}, +JOURNAL = {IEEE Transactions on Software Engineering}, YEAR = {1990}, +VOLUME = {16}, NUMBER = {2}, PAGES = {238-247}, MONTH = feb } + +@ARTICLE{ShimeallLeveson91, +Author={T.J. Shimeall and N.G. Leveson}, +TITLE = {An Empirical Comparison of Software Fault +Tolerance and Fault Elimination}, +JOURNAL = {IEEE Transactions on Software Engineering}, YEAR = {1991}, +VOLUME = {SE-17}, NUMBER = {2}, PAGES = {173-183}, MONTH = feb } + +@ARTICLE{Leveson+90, +Author={N.G. Leveson and S.S. Cha and J.C. Knight and T.J. Shimeall}, +TITLE = {The Use of Self Checks and Voting in Software Error Detections: +An Empirical Study}, JOURNAL = {IEEE Transactions on Software Engineering}, +YEAR = {1990}, VOLUME = {SE-16}, +NUMBER = {4}, PAGES = {}, MONTH = apr } + +@ARTICLE{Leveson91Safety, +Author={N.G. Leveson}, +TITLE = {Software Safety in Embedded Computer Systems}, +JOURNAL = {Communications of the ACM}, +YEAR = {1991}, VOLUME = {34}, +NUMBER = {2}, PAGES = {}, MONTH = feb } + +@ARTICLE{Therac92, +author={N.G. Leveson and C. Turner}, +Title={An Investigation of the {Therac-25} Accidents}, +Journal={Computer}, pages ={18--41}, month =jul, Year=1993 } + +@ARTICLE{Leveson91Ada, +Author={N.G. Leveson and S.S. Cha and T.J. Shimeall}, +TITLE = {Safety Verification of {Ada} Programs using Software Fault Trees}, +JOURNAL = {IEEE Software}, YEAR = {1991}, VOLUME = {8}, +NUMBER = {7}, PAGES = {}, MONTH = jul } + +@book{Leveson95, +Author={N.G. Leveson}, +Title={Safeware: System Safety and Computers}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={1995} } + +@InProceedings{Leveson00, +Author = "N.G. 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Stickel}, + TITLE = {A {Prolog} Technology Theorem Prover}, + BOOKTITLE = {Proceedings of the Eighth International Conference on Automated Deduction}, + YEAR = {1986}, + PAGES = {573--587}, + ADDRESS = {Oxford, England}, + MONTH = jul +} + +@BOOK{Manna+Waldinger85, + AUTHOR = {Zohar Manna and Richard Waldinger}, + TITLE = {The Logical Basis for Computer Programming}, + PUBLISHER = {Addison-Wesley, Reading, Massachusetts}, + YEAR = {1985}, + VOLUME = {1} +} + +@BOOK{Manna+Waldinger88, + AUTHOR = {Zohar Manna and Richard Waldinger}, + TITLE = {The Logical Basis for Computer Programming}, + PUBLISHER = {Addison-Wesley, Reading, Massachusetts}, + YEAR = {1988}, + VOLUME = {2} +} + + +@book{Shoenfield, + Author={Jospeh R. Shoenfield}, + Title={Mathematical Logic}, + Publisher={Addison-Wesley}, + Address={Reading, Massachusetts}, + Year={1967}} + +@BOOK{Andrews:book, + AUTHOR = {Peter B. Andrews}, + TITLE = {An Introduction to Logic and Type Theory: To Truth through Proof}, + PUBLISHER = {Academic Press, New York}, + YEAR = {1986} +} + +@MANUAL{Gnu, + TITLE = {{GNU Emacs} Manual}, + AUTHOR = {Richard Stallman}, + ORGANIZATION = {Free Software Foundation}, + ADDRESS = {1000 Massachusetts Ave., Cambridge, Massachusetts}, + EDITION = {Fourth}, + MONTH = feb, + YEAR = {1986} +} + +@MANUAL{Rushby:sqa:part1, + TITLE = {Measures and Techniques for Software Quality Assurance}, + AUTHOR = {J.M. Rushby}, + ORGANIZATION = {Computer Science Laboratory, SRI International}, + ADDRESS = {333 Ravenswood Ave., Menlo Park, California}, + MONTH = sep, + YEAR = {1988} +} + +@Article{Hoare:69, + Author = {C.A.R. Hoare}, + Title = {An axiomatic basis of computer programming}, + Journal = {Communications of the ACM}, + Year = {1969}, + Volume = {12}, + Number = {10}, + Pages = {576--580}, + Month = oct } + +@ARTICLE{Yadav88, + AUTHOR = {Surya B. Yadav and Ralph R. Bravocco and Akemi T. Chatfield and T.M. Rajkumar}, + TITLE = {Comparison of Analysis Techniques for Information Requirement Determination}, + JOURNAL = {Communications of the ACM}, + YEAR = {1988}, + VOLUME = {31}, + NUMBER = {9}, + PAGES = {1090--1097}, + MONTH = sep +} + +@ARTICLE{Davis88, + AUTHOR = {Alan M. Davis}, + TITLE = {A Comparison of Techniques for the Specification of External System Behavior}, + JOURNAL = {Communications of the ACM}, + YEAR = {1988}, + VOLUME = {31}, + NUMBER = {9}, + PAGES = {1098--1115}, + MONTH = sep +} + +@ARTICLE{Johnson+Thayer88, + AUTHOR = {Dale M. Johnson and F. Javier Thayer}, + TITLE = {Stating Security Requirements with Tolerable Sets}, + JOURNAL = {tocs}, + YEAR = {1988}, + VOLUME = {6}, + NUMBER = {3}, + PAGES = {284--295}, + MONTH = aug +} + +@InProceedings{Millen84, + Author={Jonathan K. Millen}, + BookTitle={Proceedings of the 1984 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={The {Interrogator}: A Tool for Cryptographic Protocol Security}, + Year={1984}, + Pages={134--141}, + Month=apr + } + +@INPROCEEDINGS{Lu+Sundareshan86, + AUTHOR = {W.P. Lu and M.K. Sundareshan}, + TITLE = {A Hierarchical Key Management Scheme for End-to-End Encryption in {Internet} Environments}, + BOOKTITLE={Proceedings of the 1986 Symposium on Security and Privacy}, + YEAR = {1986}, + PAGES = {138--147}, + ORGANIZATION = {IEEE Computer Society} +} + +@ARTICLE{Kasami82, + AUTHOR = {Tadao Kasami and Saburo Yamamura and Kenichi Mori}, + TITLE = {A Key Management Scheme for End-to-End Encryption and a Formal Verification of its Security}, + JOURNAL = {Systems Computers Controls}, + YEAR = {1982}, + VOLUME = {13}, + NUMBER = {3}, + PAGES = {59--69} +} + +@INPROCEEDINGS{Sidhu+Leung, + AUTHOR = {Deepinder Sidhu and Ting-kau Leung}, + TITLE = {Experience with Test Generation for Real Protocols}, + BOOKTITLE = {SIGCOMM '88 Symposium}, + YEAR = {1988}, + PAGES = {257--261}, + ORGANIZATION = {ACM SIGCOMM}, + ADDRESS = {Stanford, California}, + MONTH = aug, + NOTE = {(Computer Communication Review, vol. 18, No. 4, August 88)} +} + +@TECHREPORT{Schneider:understanding, + AUTHOR = {F.B. Schneider}, + TITLE = {Understanding Protocols for {Byzantine} Clock Synchronization}, + INSTITUTION = {Department of Computer Science, Cornell University}, + YEAR = {1987}, + NUMBER = {87-859}, + ADDRESS = {Ithaca, New York}, + MONTH = aug +} + +@TECHREPORT{Lamport:servers, + AUTHOR = {Leslie Lamport}, + TITLE = {Synchronizing Time Servers}, + INSTITUTION = {DEC Systems Research Center}, + YEAR = {1987}, + NUMBER = {18}, + ADDRESS = {Palo Alto, California}, + MONTH = jun +} + +@Article{Lampson+91, +Author = {B. Lampson and M. Abadi and M. Burrows and E. Wobber}, +Title = {Authentication in Distributed Systems: Theory and Practice}, +Journal = {ACM Operating Systems Review}, +Note = {Proceedings of the Thirteenth ACM Symposium on Operating Systems Principles}, +Organization = {ACM}, +Year = {1991}, volume = {25}, number = {5}, +Pages={165-182}, Month = oct } + +@Article{Lampson+92, +Author = {B. Lampson and M. Abadi and M. Burrows and E. Wobber}, +Title = {Authentication in Distributed Systems: Theory and Practice}, +Journal = {ACM Transactions on Computer Systems}, +Year = {1992}, volume = {10}, number = {4}, +Pages={265-310}, Month = nov } + +@Article{Wobber+93, +Author = {E. Wobber and M. Abadi and M. Burrows and B. Lampson}, +Title = {Authentication in the {Taos} Operating System}, +Journal = {ACM Operating Systems Review}, +Note = {Proceedings of the Fourteenth ACM Symposium on Operating Systems + Principles}, Organization = {ACM}, +Year = {1993}, volume = {27}, number = {5}, +Pages={256-269}, Month = dec } + +@TECHREPORT{Abadi+91, + AUTHOR = {M. Abadi and M. Burrows and B. Lampson and G. Plotkin}, + TITLE = {A Calculus for Access Control in Distributed Systems}, + INSTITUTION = {DEC Systems Research Center}, + MONTH = {28 February}, + YEAR = {1991}, + NUMBER = {70}, + ADDRESS = {Palo Alto, California} +} + +@Article{Mitchell:1988:ATE, + author = "J.C. Mitchell and G.D. Plotkin", + title = "Abstract Types Have Existential Type", + journal = "ACM Transactions on Programming Languages and Systems", + volume = "10", + number = "3", + pages = "470--502", + month = jul, + year = "1988" +} + +@Article{BAN90, + Key={Burrows}, + Author={M. Burrows and M. Abadi and R. Needham}, + Journal={ACM Transactions on Computer Systems}, + Title={A Logic of Authentication}, + Year={1990}, Month=feb, Pages={18-36}, Volume={8}, Number={1} } + +@TechReport{AbadiNeedham94, + Author={M. Abadi and R. Needham}, + Institution={Digital Equipment Corporation, SRC Research Report}, + Title={Prudent Engineering Practice for Cryptographic Protocols}, + Address = {Palo Alto, California}, + Year={1994}, Month=jun } + +@TechReport{AbadiGordon98, + Author={M. Abadi and A.D. Gordon}, + Institution={Digital Equipment Corporation, SRC Research Report 149}, + Title={A Calculus for Cryptographic Protocols: The {Spi} Calculus}, + Address = {Palo Alto, California}, + Year={1998}, Month=jan } + +@InProceedings{Abadi+99, + Author={M. Abadi and A. Banerjee and N. Heintze and J.G. Riecke}, + BookTitle={POPL '99, Proceedings of the 26th SIGPLAN-SIGACT Symposium + on Principles of Programming Languages}, + Title={A Core Calculus of Dependency}, + Year={1999}, + Address={San Antonio, Texas}, + Month={January 20-22}, + Pages={147--160} + } + +@TechReport{AbadiLeino98, + Author={M. Abadi and K.R.M. Leino}, + Institution={Compaq Systems Research Center, SRC Research Report 161}, + Title={A Logic of Object-Oriented Programs}, + Address = {Palo Alto, California}, + Year={1998}, Month=sep } + +@InProceedings{Abadi94 + ,Author={M. Abadi and R.M. Needham} + ,BookTitle={Proceedings of the IEEE Symposium on Research in Security and Privacy} + ,Address={Oakland, California} + ,Title={Prudent Engineering Practice for Cryptographic Protocols} + ,Year={1994} + ,Month=may + ,Pages={122--136} + } + +@Article{AbadiNeedham96, + Author={M. Abadi and R. Needham}, + Journal={IEEE Transactions on Software Engineering}, + Title={Prudent Engineering Practice for Cryptographic Protocols}, + Year={1996}, Month=jan, Pages={6--15}, Volume={22}, Number={1} } + +@InProceedings{Simmons85, + Key={Simmons}, Author={G.E. Simmons}, + BookTitle={Proceedings of the 1985 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Title={How to (Selectively) Broadcast a Secret}, + Year={1985}, Address={Oakland, California}, Month=apr, Pages={108-113} + } + +@TECHREPORT{Cristian:probabilistic, + AUTHOR = {F. Cristian}, + TITLE = {Probabilistic Clock Synchronization}, + INSTITUTION = {IBM Almaden Research Center}, + YEAR = {1988}, + NUMBER = {RJ 6432}, + ADDRESS = {San Jose, California}, + MONTH = sep +} + +@INPROCEEDINGS{Cristian:prob, + AUTHOR = {F. Cristian}, + TITLE = {A probabilistic approach to distributed clock synchronization}, + BOOKTITLE={Proceedings of the Ninth International Conference on +Distributed Computing Systems}, + YEAR = {1989}, + PAGES = {288-296}, + ORGANIZATION = {IEEE Computer Society} +} + +@ARTICLE{Cristian:servers, +Author={F. Cristian}, TITLE={Understanding fault-tolerant distributed systems}, +JOURNAL = {Communications of the ACM}, YEAR = {1991}, VOLUME = {34}, +NUMBER = {2}, PAGES = {56-78}, MONTH = feb } + +@BOOK{Lakatos, + AUTHOR = {Imre Lakatos}, + TITLE = {Proofs and Refutations}, + PUBLISHER = {Cambridge University Press}, + YEAR = {1976}, + ADDRESS = {Cambridge, England} +} + +@Article{Fetzer, + Author = {James H. Fetzer}, + Title = {Program Verification: the Very Idea}, + Journal = {Communications of the ACM}, + Year = {1988}, + Volume = {31}, + Number = {9}, + Pages = {1048--1063}, + Month = sep } + +@ARTICLE{Maes+vanDijk, + AUTHOR = {R. Maes and J.E.M. van Dijk}, + TITLE = {On the Role of Ambiguity and Incompleteness in the Design of Decision Tables and Rule-Based Systems}, + JOURNAL = {Computer Journal}, + YEAR = {1988}, + VOLUME = {31}, + NUMBER = {6}, + PAGES = {481--489} +} + +@TECHREPORT{Gordon88:programs, + AUTHOR = {M.J.C. Gordon}, + TITLE = {Mechanizing Programming Logics in Higher Order Logic}, + INSTITUTION = {Cambridge Computer Science Research Centre, +SRI International}, + YEAR = {1988}, + NUMBER = {CCSRC-006}, + ADDRESS = {Suite 23, Millers Yard, Mill Lane, Cambridge CB2 1RQ, England}, + MONTH = sep +} + +@ARTICLE{Stickel:PTTP, + AUTHOR = {Mark E. Stickel}, + TITLE = {A {Prolog} Technology Theorem Prover: Implementation by an Extended {Prolog} Compiler}, + JOURNAL = {Journal of Automated Reasoning}, + YEAR = {1988}, + VOLUME = {4}, + NUMBER = {4}, + PAGES = {353--380}, + MONTH = dec +} + +@BOOK{F16, + AUTHOR = {Carl S. Droste and James E. Walker}, + TITLE = {The {General Dynamics} Case Study on the {F16} Fly-by-Wire Flight Control System}, + PUBLISHER = {American Institute of Aeronautics and Astronautics}, + YEAR = {Undated}, + SERIES = {AIAA Professional Study Series} +} + +@ARTICLE{Shostak:combination, + AUTHOR = {Robert E. Shostak}, + TITLE = {Deciding Combinations of Theories}, + Journal={Journal of the ACM}, + YEAR = {1984}, + VOLUME = {31}, + NUMBER = {1}, + PAGES = {1--12}, + MONTH = jan +} + +@ARTICLE{Shostak:arithmetic, + AUTHOR = {Robert E. Shostak}, + TITLE = {A Practical Decision Procedure for Arithmetic with Function Symbols}, + Journal={Journal of the ACM}, + YEAR = {1979}, + VOLUME = {26}, + NUMBER = {2}, + PAGES = {351--360}, + MONTH = apr +} + +@ARTICLE{Shostak:sup-inf, + AUTHOR = {Robert E. Shostak}, + TITLE = {On the {SUP-INF} Method for Proving {Presburger} Formulas}, + Journal={Journal of the ACM}, + YEAR = {1977}, + VOLUME = {24}, + NUMBER = {4}, + PAGES = {529--543}, + MONTH = oct +} + +@ARTICLE{Shostak:equality, + AUTHOR = {Robert E. Shostak}, + TITLE = {An Algorithm for Reasoning about Equality}, + JOURNAL = {Communications of the ACM}, + YEAR = {1978}, + VOLUME = {21}, + NUMBER = {7}, + PAGES = {583--585}, + MONTH = jul +} + +@INPROCEEDINGS{STP, + AUTHOR = {R.E. Shostak and R. Schwartz and P.M. Melliar-Smith}, + TITLE = {{STP}: A Mechanized Logic for Specification and Verification}, + BOOKTITLE = {Sixth International Conference on Automated Deduction ({CADE}-6)}, + PUBLISHER={Springer-Verlag, Berlin, + Lecture Notes in Computer Science, Vol. 138}, + YEAR = {1982} +} + +@INCOLLECTION{Shostak:circuits, + AUTHOR = {Robert E. Shostak}, + TITLE = {Formal Verification of Circuit Designs}, + BOOKTITLE = {Computer Hardware Description Languages}, + PUBLISHER = {North-Holland}, + YEAR = {1983}, + EDITOR = {T. Uehara and M. Barbacci}, + PAGES = {13--29} +} + +@INPROCEEDINGS{Avizienis:search, + AUTHOR = {Algirdas Avi\v{z}ienis and Michael R. Lyu and +Werner Sch\"{u}tz}, + TITLE = {In Search of Effective Diversity: {A} Six-Language +Study of Fault Tolerant Flight Control Software}, + BOOKTITLE = {Digest of Papers, FTCS 18}, + YEAR = {1988}, + PAGES = {15--22}, + ORGANIZATION = {IEEE Computer Society}, + ADDRESS = {Tokyo, Japan}, + MONTH = jun +} + +@INPROCEEDINGS{Kelly88, + AUTHOR = {John P.J. Kelly and others}, + TITLE = {A Large Scale Second Generation Experiment in +Multi-Version Software: Description and Early Results}, + BOOKTITLE = {Digest of Papers, FTCS 18}, + YEAR = {1988}, + PAGES = {9--14}, + ORGANIZATION = {IEEE Computer Society}, + ADDRESS = {Tokyo, Japan}, + MONTH = jun +} + +@INPROCEEDINGS{Brunelle, + AUTHOR = {J.E. Brunelle and D.E. {Eckhardt, Jr.}}, + TITLE = {Fault-Tolerant Software: An Experiment with the +{SIFT} Operating System}, + PAGES = {355--360}, + BOOKTITLE = {Proceedings of the Fifth AIAA Computers in Aerospace Conference}, + MONTH = oct, YEAR = {1985} } + +@ARTICLE{Eckhardt+Lee, +AUTHOR = {Dave E. {Eckhardt, Jr.} and Larry D. Lee}, +TITLE = {A Theoretical Basis for the Analysis of Multiversion +Software Subject to Coincident Errors}, +JOURNAL = {IEEE Transactions on Software Engineering}, YEAR = {1985}, +VOLUME = {SE-11}, NUMBER = {12}, PAGES = {1511--1517}, MONTH = dec } + +@ARTICLE{Eckhardt+91, +AUTHOR = {D.E. Eckhardt and A.K. Caglayan and J.C. Knight and L.D. Lee +and D.F. McAllister and M.A. Vouk and J.P.J. Kelly}, +TITLE = {An Experimental Evaluation of Software Redundancy as a Strategy +for Improving Reliability}, +JOURNAL = {IEEE Transactions on Software Engineering}, YEAR = {1991}, +VOLUME = {SE-11}, NUMBER = {12}, PAGES = {692-702}, MONTH = jul } + +@TECHREPORT{Rushby89:ica, + AUTHOR = {J.M. Rushby and F. von Henke}, + TITLE = {Formal Verification of the Interactive Convergence Clock Synchronization Algorithm using {EHDM}}, + INSTITUTION = {Computer Science Laboratory, SRI International}, + YEAR = {1989}, + NUMBER = {SRI-CSL-89-3}, + ADDRESS = {Menlo Park, California}, + MONTH = feb, + NOTE = {Also available as NASA Contractor Report 4239} +} +@comment{(Final Report for SRI Project 4616, Task 4, NASA Contract NSA1 17067), also forthcoming NASA Contractor Report} + +@inproceedings{Rushby94:icah, + AUTHOR = {J.M. Rushby}, + TITLE = {A Formally Verified Algorithm for Clock + Synchronization Under a Hybrid Fault Model}, + BOOKTITLE = {Proceedings of the Thirteenth Conference on + Principles of Distributed Computing}, + PAGES = {304--313}, + ORGANIZATION = {ACM}, + ADDRESS = {Los Angeles, California}, + MONTH = aug, + YEAR = 1994 +} + +@techreport{Lincoln+Rushby92:OMH, + AUTHOR = {Patrick Lincoln and John Rushby}, + TITLE = {Formal Verification of an Algorithm for Interactive + Consistency under a Hybrid Fault Model}, + NUMBER = {SRI-CSL-93-2}, + INSTITUTION = {Computer Science Laboratory, SRI International}, + YEAR = 1993, + ADDRESS = "Menlo Park, California", + MONTH = mar, + NOTE = {Also available as NASA Contractor Report 4527, July 1993}, +} + +@inproceedings{Lincoln+Rushby93:FTCS, + AUTHOR = {P.D. Lincoln and J.M. Rushby}, + TITLE = {A Formally Verified Algorithm for Interactive Consistency + under a Hybrid Fault Model}, + BOOKTITLE = {Fault Tolerant Computing Symposium 23}, + PAGES = {402--411}, + YEAR = {1993} +} + +@inproceedings{Lincoln95NASA, + AUTHOR = {P.D. Lincoln and J.M. Rushby and N. Suri and C. Walter}, + TITLE = {Hybrid Fault Algorithms}, +BookTitle={Proceedings of the Third NASA Langley Formal Methods Workshop, + May 10-12, 1995}, + MONTH = jun, + YEAR = {1995}, +ORGANIZATION={NASA Langley Research Center}, +Pages={193--209}} + +@inproceedings{Rushby95NASA, + AUTHOR = {J.M. Rushby}, + TITLE = {Fault-Tolerant Algorithms and the Design of {PVS}}, +BookTitle={Proceedings of the Third NASA Langley Formal Methods Workshop, + May 10-12, 1995}, + MONTH = jun, + YEAR = {1995}, +ORGANIZATION={NASA Langley Research Center}, +Pages={93--104}} + +@techreport{Lincoln+Rushby95, + AUTHOR = {P.D. Lincoln and J.M. Rushby}, + TITLE = {Formally Verified Algorithms for Diagnosis + of Manifest, Symmetric, Link, and {Byzantine} Faults}, + NUMBER = {SRI-CSL-95-14}, + INSTITUTION = {Computer Science Laboratory, SRI International}, + YEAR = "1995", + ADDRESS = "Menlo Park, California", + MONTH = oct, +} + +@techreport{LincolnRushby95, + AUTHOR = {P.D. Lincoln and J.M. Rushby}, + TITLE = {Formally Verified Algorithms for Diagnosis + of Manifest, Symmetric, Link, and {Byzantine} Faults}, + NUMBER = {SRI-CSL-95-14}, + INSTITUTION = {Computer Science Laboratory, SRI International}, + YEAR = "1995", + ADDRESS = "Menlo Park, California", + MONTH = oct, +} + +@techreport{DiVitoRoberts96, + AUTHOR = {B.L. DiVito and L.W. Roberts}, + TITLE = {Using Formal Methods to Assist in the Requirements Analysis + of the Space Shuttle {GPS} Change Request}, + NUMBER = {NASA Contractor Report 4652}, + INSTITUTION = {NASA Langley Research Center}, + YEAR = 1996, + ADDRESS = "Hampton, Virginia", + MONTH = aug, +} + +@inproceedings{Dill95NASA, + AUTHOR = {D.L. Dill}, + TITLE = {Model Checking}, +BookTitle={Proceedings of the Third NASA Langley Formal Methods Workshop, + May 10-12, 1995}, + MONTH = jun, + YEAR = {1995}, +ORGANIZATION={NASA Langley Research Center}, +Pages={211--216}} + +@BOOK{McMillan:SMV, + AUTHOR = {K.L. McMillan}, + TITLE = {Symbolic Model Checking}, + PUBLISHER = {Kluwer Academic Publishers}, + ADDRESS = {Boston, Massachusetts}, + YEAR = 1993 +} + +@ARTICLE{Burch-etal94, + AUTHOR = {J.R. Burch and E.M. Clarke and D.E. Long and + K.L. McMillan and D.L. Dill}, + TITLE = {Symbolic Model Checking for Sequential Circuit Verification}, + JOURNAL = {IEEE Transactions on Computer-Aided Design}, + YEAR = 1994, + VOLUME = 13, + NUMBER = 4, + PAGES = {401--424}, + MONTH = apr +} + +@article{Atlee+Gannon93, + AUTHOR = {J.M. Atlee and J. Gannon}, + TITLE = {State-Based Model Checking of Event-Driven System Requirements}, + JOURNAL = {IEEE Transactions on Software Engineering}, + YEAR = 1993, + VOLUME = 19, + NUMBER = 1, + PAGES = {24--40}, + MONTH = jan +} + +@ARTICLE{Clarke-etal94, + AUTHOR = {E.M. Clarke and O. Grumberg and D.E. Long}, + TITLE = {Model Checking and Abstraction}, + JOURNAL = {ACM Transactions on Programming Languages and Systems}, + YEAR = 1994, + VOLUME = 16, + NUMBER = 5, + PAGES = {1512--1542}, + MONTH = sep +} + +@TECHREPORT{Rushby88:SQA, + AUTHOR = {J.M. Rushby}, + TITLE = {Quality measures and Assurance for {AI} Software}, + INSTITUTION = {Computer Science Laboratory, SRI International}, + YEAR = {1988}, + NUMBER = {SRI-CSL-88-7R}, + ADDRESS = {Menlo Park, California}, + MONTH = sep, + NOTE = {Also available as NASA Contractor Report 4187} +} +@comment{(Final Report for SRI Project 4616, Task 5, NASA Contract NSA1 17067), also available as NASA Contractor Report 4187} + +@ARTICLE{Cohn83, + AUTHOR = {Avra Cohn}, + TITLE = {The Equivalence of Two Semantic Definitions: A Case Study in {LCF}}, + JOURNAL = {sicomp}, + YEAR = {1983}, + VOLUME = {12}, + NUMBER = {2}, + PAGES = {267--285}, + MONTH = may +} + +@BOOK{Boyer-Moore79, + AUTHOR = {R.S. Boyer and J S. Moore}, + TITLE = {A Computational Logic}, + PUBLISHER = {Academic Press}, + YEAR = {1979}, + ADDRESS = {New York} +} + +@BOOK{Kaufmann-Moore00, + AUTHOR = {M Kaufmann and J S. Moore and P. Manolios}, + TITLE = {Computer-Aided Reasoning: An Approach}, + PUBLISHER = {Kluwer Academic Publishing}, + YEAR = {2000}, + ADDRESS = {Norwell, Massachusetts} +} + +@INPROCEEDINGS{Littlewood+Miller, + AUTHOR = {B. Littlewood and D.R. Miller}, + TITLE = {A Conceptual Model of Multi-Version Software}, + BOOKTITLE={Digest of Papers, FTCS 17}, + ADDRESS={Pittsburgh, Pennsylvania}, + ORGANIZATION={IEEE Computer Society}, + PAGES = {150--155}, + MONTH=jul, + YEAR={1987}} + +@ARTICLE{Dunham86, + AUTHOR = {Janet R. Dunham}, + TITLE = {Experiments in Software Reliability: Life Critical Applications}, + JOURNAL = {IEEE Transactions on Software Engineering}, + YEAR = {1986}, + VOLUME = {SE-12}, + NUMBER = {1}, + PAGES = {110--123}, + MONTH = jan +} + +@TECHREPORT{Moore:piton-short, + AUTHOR = {J Strother Moore}, + TITLE = {A Mechanically Verified Language Implementation}, + INSTITUTION = {Computational Logic Incorporated}, + YEAR = {1988}, + NUMBER = {30}, + ADDRESS = {Austin, TX}, + MONTH = sep +} + +@TECHREPORT{Moore:piton-long, + AUTHOR = {J Strother Moore}, + TITLE = {Piton: A Verified Assembly Level Language}, + INSTITUTION = {Computational Logic Incorporated}, + YEAR = {1988}, + NUMBER = {22}, + ADDRESS = {Austin, TX}, + MONTH = sep +} + +@TECHREPORT{Young88, + AUTHOR = {W.D. Young}, + TITLE = {A Verified Code Generator for a Subset of {Gypsy}}, + INSTITUTION = {Computational Logic Incorporated}, + YEAR = {1988}, + NUMBER = {33}, + ADDRESS = {Austin, TX}, + MONTH = oct +} + +@ARTICLE{Scarl87, + AUTHOR = {E.A. Scarl and J.R. Jamieson and C.I. Delaune}, + TITLE = {Diagnosis and Sensor Validation through Knowledge of Structure and Function}, + JOURNAL = {IEEE Transactions on Systems, Man, and Cybernetics}, + YEAR = {1987}, + VOLUME = {SMC-17}, + NUMBER = {3}, + PAGES = {360--368}, + MONTH = {May/June} +} + +@INPROCEEDINGS{Chand87, + AUTHOR = {B. Chandraskeran and W.F. {Punch III}}, + TITLE = {Data Validation During Diagnosis, A Step Beyond Traditional Sensor Validation}, + BOOKTITLE = {Proceedings of the AAAI 87 (Vol. 2)}, + YEAR = {1987}, + PAGES = {778--782}, + ADDRESS = {Seattle, WA}, + MONTH = jul +} + +@TECHREPORT{MacEwan:realtime, + AUTHOR = {Glenn H. MacEwan}, + TITLE = {Using Higher-Order Logic for Modular Specification of Real-Time Distributed Systems}, + INSTITUTION = {Computer Science Laboratory, SRI International}, + YEAR = {1988}, + ADDRESS = {Menlo Park, California}, + Type = {Draft report} + +} + +@ARTICLE{Avizienis85, + AUTHOR = {Algirdas Avi\v{z}ienis}, + TITLE = {The {{\em N\/}-Version} Approach to Fault-Tolerant Software}, + JOURNAL = {IEEE Transactions on Software Engineering}, + YEAR = {1985}, + VOLUME = {SE-11}, + NUMBER = {12}, + PAGES = {1491--1501}, + MONTH = dec +} + +@INPROCEEDINGS{Barrow83, + AUTHOR = {Harry G. Barrow}, + TITLE = {Proving the Correctness of Digital Hardware Designs}, + BOOKTITLE = {Proceedings of the AAAI 83}, + YEAR = {1983}, + PAGES = {17--21}, + ADDRESS = {Washington, D.C.}, + MONTH = aug +} + +@ARTICLE{Infis+Moore88, + AUTHOR = {A.H. Infis and W.R. Moore}, + TITLE = {Economic Approach to Fault-Tolerant Synchronization}, + JOURNAL = {IEE Proceedings, Part E}, + YEAR = {1988}, + VOLUME = {135}, + NUMBER = {2}, + PAGES = {82--86}, + MONTH = mar +} + +@TECHREPORT{SIFT-report, + AUTHOR = {J.H. {Wensley et al.}}, + TITLE = {Design Study of Software-Implemented Fault-Tolerance {(SIFT)} Computer}, + INSTITUTION = {Computer Science Laboratory, SRI International}, + YEAR = {1982}, + ADDRESS = {Menlo Park, California}, + TYPE = {{NASA} Contractor Report 3011}, + MONTH = jun +} + +@TECHREPORT{Hunt:FM8501-short, + AUTHOR = {Warren A. {Hunt, Jr.}}, + TITLE = {The Mechanical Verification of a Microprocessor Design}, + INSTITUTION = {Computational Logic Incorporated}, + YEAR = {1987}, + NUMBER = {6}, + ADDRESS = {Austin, TX} +} + +@TECHREPORT{Bevier:kit-short, + AUTHOR = {W.R. Bevier}, + TITLE = {Kit: A Study in Operating System Verification}, + INSTITUTION = {Computational Logic Incorporated}, + YEAR = {1988}, + NUMBER = {28}, + ADDRESS = {Austin, TX}, + MONTH = aug +} + +@TECHREPORT{Bevier:kit-long, + AUTHOR = {W.R. Bevier}, + TITLE = {A Verified Operating System Kernel}, + INSTITUTION = {Computational Logic Incorporated}, + YEAR = {1987}, + NUMBER = {11}, + ADDRESS = {Austin, TX}, + MONTH = oct +} + +@article{Moore+JAR89, +author={J S. {Moore, editor}}, title = {System Verification}, +journal = {Journal of Automated Reasoning}, year = {1989}, volume = {5}, +number = {4}, pages = {409-530}, month = dec, +NOTE = {Includes five papers by Moore, W.R. Bevier, W.A. Hunt, Jr, +and W.D. Young.} +} + +@article{MooreJAR89, +author={J S. Moore}, title = {System Verification}, +journal = {Journal of Automated Reasoning}, year = {1989}, volume = {5}, +number = {4}, pages = {409-410}, month = dec } + +@article{Bevier+JAR89, +author={W.R. Bevier and W.A. {Hunt, Jr.} and J S. Moore and W.D. Young}, +title = {An Approach to Systems Verification}, +journal = {Journal of Automated Reasoning}, year = {1989}, volume = {5}, +number = {4}, pages = {411-428}, month = dec } + +@article{HuntJAR89, +author={W.A. {Hunt Jr.}}, title = {Microprocessor Design Verification}, +journal = {Journal of Automated Reasoning}, year = {1989}, volume = {5}, +number = {4}, pages = {429-460}, month = dec } + +@article{MooreJAR89a, +author={J S. Moore}, title = {A Mechanically Verified Language Implementation}, +journal = {Journal of Automated Reasoning}, year = {1989}, volume = {5}, +number = {4}, pages = {461-492}, month = dec } + +@article{YoungJAR89, +author={W.D. Young}, title = {A Mechanically Verified Code Generator}, +journal = {Journal of Automated Reasoning}, year = {1989}, volume = {5}, +number = {4}, pages = {493-518}, month = dec } + +@article{BevierJAR89, +author={W.R. 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Luckham}, + TITLE = {Automatic Program Verification {I}: A Logical Basis and its Implementation}, + JOURNAL = {acta}, + YEAR = {1975}, + VOLUME = {4}, + PAGES = {145--182} +} + +@Article(DaleyDennis68, +key="Daley", Author="R.C. Daley and J.B. Dennis", +Title={Virtual Memory, Processes, and Sharing in {Multics}}, +Journal="Communications of the ACM", +Year="1968", Month=may, Page="306--312", Volume="11", Number="5",) + +@Article(Graham68, +key="Graham", Author="R.M. Graham", +Title={Protection in an Information Processing Utility}, +Journal="Communications of the ACM", +Year="1968", Month=may, Page="365--369", Volume="11", Number="5",) + +@Article(dijkstra68, +Author="E.W. Dijkstra", Key="Dijkstra", +Title={The Structure of the {THE} Multiprogramming System}, +Journal="Communications of the ACM", +Year="1968", Month=may, Page="341--346", Volume="11", Number="5",) + +@InProceedings{Dijkstra68CSP, +Author={E.W. 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Gordon}, + TITLE = {Mechanizing Programming Logics in Higher Order Logic}, + INSTITUTION = {Cambridge Computer Science Research Center, SRI International}, + YEAR = {1988}, + NUMBER = {CCSRC-006}, + ADDRESS = {Cambridge, England}, + MONTH = sep +} + +@TECHREPORT{Cohn:parser, + AUTHOR = {Avra Cohn and Robin Milner}, + TITLE = {On using {Edinburgh LCF} to Prove the Correctness of a Parsing Algorithm}, + INSTITUTION = {Edinburgh University Computer Science Department}, + YEAR = {1982}, + NUMBER = {CSR-113-82}, + NOTE = {Also Cambridge University Computer Laboratory Technical Report 20.} +} + +@MANUAL{Stanford-verifier, + TITLE = {Stanford {Pascal} Verifier User's Manual}, + AUTHOR = {D. Luckham and others}, + ORGANIZATION = {Stanford University}, + ADDRESS = {Stanford, California}, + YEAR = {1979}, + NOTE = {AI memo CS-79-731} +} + +@BOOK{Polak:book, + AUTHOR = {W. Polak}, + TITLE = {Compiler Specification and Verification}, + PUBLISHER = {Springer-Verlag, Berlin}, + YEAR = {1981}, +} + +@TECHREPORT{OBJ:intro, + AUTHOR = {J.A. Goguen and T. Winkler}, + TITLE = {Introducing {OBJ3}}, + INSTITUTION = {Computer Science Laboratory, SRI International}, + YEAR = {1988}, + NUMBER = {SRI-CSL-88-9}, + ADDRESS = {Menlo Park, California}, + MONTH = aug +} + + +@Unpublished{ACohn:Notion, + Author = {A. Cohn}, + Title = {The Notion of Proof in Hardware Verification}, + Note = {Draft, Cambridge University Computer Laboratory}, + Address = {Cambridge, England}, + Year = {1988} } + + +@TechReport{NODEN, + Author = {C. H. Pygott}, + Title = {{NODEN}: An engineering approach to hardware verification}, + Institution = {RSRE}, + Number = {415-88}, + Year = {1988} } + +@ARTICLE{Johnson+Malek88, + AUTHOR = {Allen M. {Johnson, Jr.} and Miroslaw Malek}, + TITLE = {Survey of Software Tools for Evaluating Reliability, Availability and Serviceability}, + JOURNAL = {Computing Surveys}, + YEAR = {1988}, + VOLUME = {20}, + NUMBER = {4}, + PAGES = {227--269}, + MONTH = dec +} + +@ARTICLE{Flannagan86, + AUTHOR = {Im Flannagan}, + TITLE = {The Consistency of Negation as Failure}, + JOURNAL = {The Journal of Logic Programming}, + YEAR = {1986}, + VOLUME = {3}, + NUMBER = {2}, + PAGES = {93--114}, + MONTH = jul +} + +@PROCEEDINGS{SIFT:review, + AUTHOR = {NASA}, + TITLE = {Peer Review of a Formal Verification/Design Proof Methodology}, + YEAR = {1983}, + ORGANIZATION = {NASA Conference Publication 2377}, + MONTH = jul +} + +@TECHREPORT{RSRE:methodology, + AUTHOR = {W.J. Cullyer and C.H. Pygott}, + TITLE = {Hardware Proofs using {LCF-LSM} and {ELLA}}, + INSTITUTION = {Royal Signals and Radar Establishment}, + YEAR = {1985}, + TYPE = {Memorandum}, + NUMBER = {3832}, + MONTH = sep +} + +@TECHREPORT{Joyce:asynch, + AUTHOR = {Jeffrey J. Joyce}, + TITLE = {Formal Specification and Verification of Asynchronous Processes in Higher Order Logic}, + Institution={University of Cambridge Computer Laboratory}, + YEAR = {1988}, + NUMBER = {136}, + MONTH = jun +} + +@ARTICLE{Kopetz89:mars, + AUTHOR = {Hermann Kopetz and others}, + TITLE = {Distributed Fault-Tolerant Real-Time Systems: The {Mars} Approach}, + JOURNAL = {IEEE Micro}, + YEAR = {1989}, + VOLUME = {9}, + NUMBER = {1}, + PAGES = {25--40}, + MONTH = feb +} + +@InProceedings{Crocker88, + Author = {S.D. Crocker and E. Cohen and S. Landauer and H. Orman}, + Title = {Reverification of a Microprocessor}, + BookTitle={Proceedings of the 1988 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Year={1988}, + Pages={166-176}, + Month=apr + } + +@TECHREPORT{Rushby+Whitehurst89, + AUTHOR = {J.M. Rushby and R. Alan Whitehurst}, + TITLE = {Formal Verification of {AI} Software}, + INSTITUTION = {Computer Science Laboratory, SRI International}, + YEAR = {1989}, + TYPE = {Final Report, NASA Contract 18226 (Task5)}, + ADDRESS = {Menlo Park, California}, + MONTH = feb +} + +@MANUAL{CLIPS, + TITLE = {{CLIPS} User's Guide}, + AUTHOR = {Joseph C. Giarratano}, + ORGANIZATION = {Artificial Intelligence Center, Lyndon B. Johnson Space Center}, + MONTH = jun, + YEAR = {1988} +} + +@INPROCEEDINGS{Kapuretal, + AUTHOR = {D. Kapur and H. Zhang and G. Sivakumar}, + TITLE = {{RRL}: A Rewrite Rule Laboratory}, + BOOKTITLE = {Eighth International Conference on Automated Deduction +(CADE-8)}, + YEAR = {1986}, + PUBLISHER = {Springer-Verlag, Berlin, + Lecture Notes in Computer Science, Vol. 230}, + ADDRESS = {Oxford, England} +} + +@InProceedings{Benzel+Tavilla85, + Author={T.C. Vickers Benzel and D.A. Tavilla}, + BookTitle={Proceedings of the 1985 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Title={Trusted Software Verification: A Case Study}, + Year={1985}, + Address={Oakland, California}, + Month=apr, + Pages={14--31} + } + +@InProceedings{McHugh+Good85, + Author={J. McHugh and D.I. Good}, + BookTitle={Proceedings of the 1985 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Title={An Information Flow Tool for {Gypsy}}, + Year={1985}, + Address={Oakland, California}, + Month=apr, + Pages={46--48} + } + +@ARTICLE{Denning:views, + AUTHOR = {Dorothy E. Denning and others}, + TITLE = {Views for Multilevel Database Security}, + JOURNAL = {IEEE Transactions on Software Engineering}, + YEAR = {1987}, + VOLUME = {SE-13}, + NUMBER = {2}, + PAGES = {129--140}, + MONTH = feb +} + +@ARTICLE{Haigh+Young85, + AUTHOR = {J.T. Haigh and W.D. Young}, + TITLE = {Extending the Noninterference Version of {MLS} for {SAT}}, + JOURNAL = {IEEE Transactions on Software Engineering}, + YEAR = {1987}, + VOLUME = {SE-13}, + NUMBER = {2}, + PAGES = {141--150}, + MONTH = feb +} + +@ARTICLE{Haigh+others85, + AUTHOR = {J.T. Haigh and R.A. Kemmerer and J. McHugh and W.D. Young}, + TITLE = {An Experience Using Two Covert Channel Analysis Techniques on a Real System Design}, + JOURNAL = {IEEE Transactions on Software Engineering}, + YEAR = {1987}, + VOLUME = {SE-13}, + NUMBER = {2}, + PAGES = {157--168}, + MONTH = feb +} + +@book{GasserBook, +Author={M. Gasser}, +Title={Building a Secure Computer System}, +Publisher={Van Nostrand Reinhold Company, New York}, +Year={1988}, +URL = "http://www.acsac.org/secshelf/secshelf/book002.html" } + + @ARTICLE{Gasser89, + AUTHOR = {M. Gasser}, + TITLE = {An Optimization for Automated Information Flow Analysis}, + JOURNAL = {Cipher (Newsletter of the {IEEE} Technical Committee on Security and Privacy)}, + YEAR = {1989}, + MONTH = jan, + PAGES = {32--36} +} + +@ARTICLE{Fine+others89, + AUTHOR = {T.E. Fine and J.T. Haigh and R.C. O'Brien}, + TITLE = {A General Non-Interference Unwinding Theorem}, + JOURNAL = {Cipher (Newsletter of the {IEEE} Technical Committee on Security and Privacy)}, + YEAR = {1989}, + MONTH = apr, + PAGES = {38--40} +} + +@ARTICLE{Gasser+others80, + AUTHOR = {M. Gasser and J.K. Millen and W.F. Wilson}, + TITLE = {A Note on Information Flow into Arrays}, + JOURNAL = {ACM Software Engineering Notes}, + YEAR = {1980}, + VOLUME = {5}, + NUMBER = {1}, + PAGES = {28--29}, + MONTH = jan +} + +@ARTICLE{Denning80, + AUTHOR = {Dorothy E. Denning}, + TITLE = {Embellishments to the Note on Information Flow into Arrays}, + JOURNAL = {ACM Software Engineering Notes}, + YEAR = {1980}, + VOLUME = {5}, + NUMBER = {2}, + PAGES = {15--16}, + MONTH = apr +} + +@TECHREPORT{Platek+Sutherland84, + AUTHOR = {Richard Platek and David Sutherland}, + TITLE = {The Semantics of the {Feiertag MLS} Information Flow Tool and its Impact on Design Verification: Some {SCOMP} Examples}, + INSTITUTION = {Odyssey Research Associates}, + YEAR = {1984}, + ADDRESS = {Ithaca, New York}, + MONTH = jan } + +@InProceedings{Sutherland86, +Author={D.I. Sutherland}, +Title={A Model of Information Flow}, pages={175-183}, +Booktitle={Proceedings of the Ninth National Computer Security Conference}, +Year=1986, Month =sep } + +@TECHREPORT{Rushby:mls, + AUTHOR = {J.M. Rushby}, + TITLE = {Verifying Noninterference Security Policies}, + INSTITUTION = {Computer Science Laboratory, SRI International}, + YEAR = {1989}, + ADDRESS = {Menlo Park, California}, + MONTH = jun +} + +@ARTICLE{Kemmerer:protocols89, + AUTHOR = {R.A. Kemmerer}, + TITLE = {Analyzing Encryption Protocols Using Formal Verification Techniques}, + JOURNAL = {IEEE Journal on Selected Areas in Communications}, + YEAR = {1989}, + VOLUME = {7}, + NUMBER = {4}, + PAGES = {448--457}, + MONTH = may +} + +@ARTICLE{Moore:protocols88, + AUTHOR = {Judy H. Moore}, + TITLE = {Protocol Failures in Cryptosystems}, + JOURNAL = {Proceedings of the IEEE}, + YEAR = {1988}, + VOLUME = {76}, + NUMBER = {5}, + PAGES = {594--602}, + MONTH = may +} + +@TECHREPORT{Seaview:specs, + AUTHOR = {T.F. Lunt and R.A. Whitehurst}, + TITLE = {The {SeaView} Formal Top Level Specifications and Proofs}, + TYPE = {Final Report}, + INSTITUTION = {Computer Science Laboratory, SRI International}, + YEAR = {1989}, + NOTE = {Volumes 3A and 3B of ``Secure Distributed Data Views,'' SRI Project 1143}, + ADDRESS = {Menlo Park, California}, + MONTH = {January/February} +} + +@Unpublished{Gordon89:cells, + AUTHOR = {Mike Gordon and Paul Lowenstein and Moshe Shahaf}, + TITLE = {Formal Verification of A Cell Library--a case study in technology transfer}, + YEAR = {1989}, + NOTE = {Submitted for publication} + +} + +@BOOK{Gordon:book2, + AUTHOR = {Michael J.C. Gordon}, + TITLE = {Programming Language Theory and its Implementation}, + PUBLISHER = {Prentice-Hall International (U.K.) Ltd.}, + YEAR = {1988}, + ADDRESS = {Hemel Hempstead, U.K.} +} + +@BOOK{Jones:VDM, + AUTHOR = {Cliff B. Jones}, + TITLE = {Systematic Software Development Using {VDM}}, + PUBLISHER = {Prentice-Hall International (U.K.) Ltd.}, + YEAR = {1986}, + ADDRESS = {Hemel Hempstead, U.K.} +} + +@INPROCEEDINGS{Schaefer:harmful, + AUTHOR = {M. Schaefer}, + TITLE = {Symbol Security Condition Considered Harmful}, +BOOKTITLE = {Proceedings of the 1989 Symposium on Security and Privacy}, + YEAR = {1989}, + PAGES = {20--46}, + ORGANIZATION = {IEEE Computer Society}, + ADDRESS = {Oakland, California}, + MONTH = may +} + +@BOOK{Misra+Chandy:book, + AUTHOR = {K. Mani Chandy and Jayadev Misra}, + TITLE = {Parallel Program Design: A Foundation}, + PUBLISHER = {Addison-Wesley}, + YEAR = {1988}, + ADDRESS = {Reading, Massachusetts} +} + + + +@INPROCEEDINGS{Rushby88:AAAI, + AUTHOR = {J.M. Rushby}, + TITLE = {Validation and Testing of Knowledge-Based Systems: How Bad can it get?}, + BOOKTITLE = {Proceedings of the AAAI 88 Workshop on Validation and Testing Knowledge-Based Systems}, + YEAR = {1988}, + ADDRESS = {Saint Paul, MN}, + MONTH = aug +} + +@InProceedings{Benson89, + Author={G. Benson and W. Appelbe and I. Akyildiz}, + BookTitle={Proceedings of the 1989 Symposium on Security and Privacy}, + Organization={IEEE Computer Society}, + Address={Oakland, California}, + Title={The Hierarchical Model of Distributed System Security}, + Year={1989}, + Pages={194--203}, + Month=may + } + +@ARTICLE{Wood89, + AUTHOR = {Kem Wood and others}, + TITLE = {Shuttle Failure Detection}, + JOURNAL = {Aerospace America}, + YEAR = {1989}, + VOLUME = {27}, + NUMBER = {7}, + PAGES = {34--36}, + MONTH = jul +} + +@ARTICLE{Smith89, + AUTHOR = {David M. Smith}, + TITLE = {Expert System's Role Broadens}, + JOURNAL = {Aerospace America}, + YEAR = {1989}, + VOLUME = {27}, + NUMBER = {7}, + PAGES = {26--28}, + MONTH = jul +} + +@ARTICLE{Corrigan89, + AUTHOR = {J.D. Corrigan and K.J. Keller and S.A. Meyer}, + TITLE = {Promise of Decision Aiding}, + JOURNAL = {Aerospace America}, + YEAR = {1989}, + VOLUME = {27}, + NUMBER = {7}, + PAGES = {30--31}, + MONTH = jul +} + +@ARTICLE{Hosmer89, + AUTHOR = {Douglas M. Hosmer}, + TITLE = {A Pilot's View of Intelligent Systems}, + JOURNAL = {Aerospace America}, + YEAR = {1989}, + VOLUME = {27}, + NUMBER = {7}, + PAGES = {32--33}, + MONTH = jul +} + +@Article{GY1, +Author = {S.L. Gerhart and L. Yelowitz}, +Title = {Observations of Fallibility in Modern Programming Methodologies}, +Journal = {IEEE Transactions on Software Engineering}, +Year = {1976}, +Volume = {SE-2}, +Number = {3}, +pages = {195--207}, +Month = sep +} + +@ARTICLE{Avizienis+Laprie, + AUTHOR = {A. Avi\v{z}ienis and J-C. Laprie}, + TITLE = {Dependable Computing: {F}rom Concepts to Design Diversity}, + JOURNAL = {Proceedings of the IEEE}, + YEAR = {1986}, + VOLUME = {74}, + NUMBER = {5}, + PAGES = {629--638}, + MONTH = may +} + +@ARTICLE{Avizienis+04, + AUTHOR = {A. Avi\v{z}ienis and J.-C. Laprie and + B. Randell and C. Landwehr}, + TITLE = {Basic Concepts and Taxonomy of Dependable + and Secure Computing}, + JOURNAL = {IEEE Transactions on Dependable and Secure Computing}, + YEAR = {2004}, + VOLUME = {1}, + NUMBER = {1}, + PAGES = {11--33}, + MONTH = "January-March" +} + +@proceedings{DCCA1, + TITLE = {Dependable Computing for Critical Applications}, + BOOKTITLE = {Dependable Computing for Critical Applications}, + MONTH = aug, + YEAR = 1989, + VOLUME = 4, + ADDRESS = {Santa Barbara, California}, + EDITOR = {A. Avi\v{z}ienis and J. C. Laprie}, + PUBLISHER = {Springer-Verlag, Vienna, Austria}, + SERIES = {Dependable Computing and Fault-Tolerant Systems} +} + +@BOOK{PDCS95, + EDITOR = {B. Randell and J.-C. Laprie and + H. Kopetz and B. Littlewood}, + TITLE = {Predictably Dependable Computing Systems}, + PUBLISHER = {Springer-Verlag, Berlin}, + YEAR = 1995, + SERIES = {Basic Research Series} +} + +@book{Laprie90, +Author={J.C. {Laprie, editor}}, +Title={Dependability: {A} Unifying Concept + for Reliable Computing and Fault Tolerance}, +Publisher={Springer-Verlag}, +Year={1990} } + +@InProceedings{Kopetz00, +Author={H. Kopetz}, +Title={Composability in the Time-Triggered Architecture}, +BookTitle={Proceedings of the SAE World Congress}, +Organization={SAE Press}, Address={Detroit, Michigan}, +Year={2000}, Month={}, pages={1--8}} + +@INPROCEEDINGS{Santel:pacemaker, +AUTHOR = {D. Santel and C. Trautmann and W. Liu}, + TITLE = {The Integration of a Formal Safety Analysis into the Software Engineering Process: An Example from the Pacemaker Industry}, + BOOKTITLE = {Proceedings of the Symposium on the Engineering of Computer-Based Medical Systems}, + YEAR = {1988}, + PAGES = {152--154}, + ORGANIZATION = {IEEE Computer Society}, + ADDRESS = {Minneapolis, Minnesota}, + MONTH = jun +} + +@ARTICLE{lu89, + AUTHOR = {Meiliu Lu and Du Zhang and Tadai Murata}, + TITLE = {A Design Approach for Self-Diagnosis of Fault-Tolerant Clock Synchronization}, + JOURNAL = {IEEE Transactions on Computers}, + YEAR = {1989}, + VOLUME = {C-38}, + NUMBER = {9}, + PAGES = {1337--1341}, + MONTH = sep +} + +@ARTICLE{Jacky89, + AUTHOR = {Jonathan Jacky}, + TITLE = {Programmed for Disaster: Software Errors that Imperil Lives}, + JOURNAL = {The Sciences}, + YEAR = {1989}, + PAGES = {22--27}, + MONTH = {September/October} +} + +@ARTICLE{Cohn89, + AUTHOR = {Avra Cohn}, + TITLE = {The Notion of Proof in Hardware Verification}, + JOURNAL = {Journal of Automated Reasoning}, + YEAR = {1989}, + VOLUME = {5}, + NUMBER = {2}, + PAGES = {127--139}, + MONTH = jun +} + +@ARTICLE{Barwise89, + AUTHOR = {Jon Barwise}, + TITLE = {Mathematical proofs of computer system correctness}, + JOURNAL = {Notices of the AMS}, + YEAR = {1989}, + NOTE = {To appear} +} + +@MISC{00-55, +key={MoD}, + TITLE = {{U.K.} Draft Interim Defence Standards 00-55 and 00-56}, + YEAR = {1989} +} + +@BOOK{Scharbach, + EDITOR = {P.N. Scharbach}, + TITLE = {Formal Methods: Theory and Practice}, + PUBLISHER = {CRC Press}, + YEAR = {1989}, + ADDRESS = {Boca Raton, Florida} +} + +@PROCEEDINGS{CHDL89, + TITLE = {Ninth International Symposium on Computer Hardware Description Languages and their Applications}, + Year = {1989}, + EDITOR = {J.A. Darringer and F.J. Rammig}, + ORGANIZATION = {1FIP}, + ADDRESS = {Washington, D.C.}, + MONTH = jun +} + +@TECHREPORT{MMU:FDIR, + AUTHOR = {D.G. Lawler and L.J.F. Williams}, + TITLE = {{MMU FDIR} Automation Task}, + INSTITUTION = {McDonnell Douglas Astronautics Company}, + YEAR = {1988}, + TYPE = {Final Report}, + ADDRESS = {16055 Space Center Blvd., Houston, TX 77062}, + MONTH = feb +} + +@BOOK{GiarratanoRiley89, + AUTHOR = {Joseph Giarratano and Gary Riley}, + TITLE = {Expert Systems: Principles and Programming}, + PUBLISHER = {PWS-Kent Publishing Company}, + YEAR = {1989}, + ADDRESS = {Boston, Massachusetts} +} + +@BOOK{BFKM85, + AUTHOR = {L. Brownston and R. Farrell and E. Kant and N. Martin}, + TITLE = {Programming Expert Systems in OPS5}, + PUBLISHER = {Addison-Wesley, Reading, Massachusetts}, + ADDRESS = {Reading, Massachusetts}, + YEAR = {1985} +} + +@BOOK{Ll84, + AUTHOR = {J. Lloyd}, + TITLE = {Foundations of Logic Programming}, + PUBLISHER = {Springer-Verlag, Berlin}, + YEAR = {1984} +} + +@INPROCEEDINGS{Mo89, + AUTHOR = {C.K. Mohan}, + TITLE = {Priority rewriting: semantics, confluence, and conditionals}, + BOOKTITLE = {Proceedings of the Third International Conference +on Rewriting Techniques and Applications}, + YEAR = {1989}, + PAGES = {278--291}, + ADDRESS = {Chapel Hill, NC} +} + +@ARTICLE{Ve77, + AUTHOR = {S.A. Vere}, + TITLE = {Relational production systems}, + JOURNAL = {Artificial Intelligence}, + YEAR = {1977}, + VOLUME = {8}, + NUMBER = {1}, + PAGES = {47--68}, + MONTH = feb +} + +@inProceedings{SDOS, +author={R. {Wong et al.}}, +title={The {SDOS} System: {A} {S}ecure {D}istributed {O}perating {S}ystem Prototype}, +Booktitle={Proceedings of the Twelfth National Computer Security Conference}, +month=oct, +year=1989, note="USE Wong+89 instead."} + +@Article{McCullough90, +Author={D. McCullough}, Title={A Hookup Theorem for Multilevel Security}, +Journal={IEEE Transactions on Software Engineering}, Volume=16, Number=6, +month=jun, year=1990, pages={563-568} } + +@Article{S5, +Author={M. Akey and K. Dunkelberger and R. C. Erdman}, +Title={Case Studies in Tactical Decision Support Systems}, +Journal={Signal}, +Volume={XL(10)}, +Pages={73+}, +Month=jun, +Year=1986 } + +@InProceedings{DenningAkl87, +Author={S.G. Akl and D.E. Denning}, +Title={Checking Classification Constraints for Consistency and Completeness}, +Book@title={Proceedings of the 1987 IEEE Symposium on Security and Privacy}, +Month=apr, +Year=1987 } + +@TechReport{ANDE72, +Author={J.P. Anderson}, +Title={Computer Security Technology Planning Study}, +Institution={ESD/AFSC, Hanscom AFB}, +number={ESD-TR-73-51}, +Address={Bedford, Massachusetts}, +Month=oct, +Year=1972 } + +@TechReport{Anderson80, +Author={J.P. Anderson}, +Title={Computer Security Threat Monitoring and Surveillance}, +Institution={James P. Anderson Company}, +Address={Fort Washington, Pennsylvania}, +Month=apr, +Year=1980 } + +@InProceedings{GajnakRADC88, +Author={G.E. Gajnak}, +Title={Some Results from the Entity Relationship Multilevel Secure DBMS Project}, +Booktitle={Research Directions in Database Security (T.F. Lunt, ed.)}, +Year={forthcoming} } + +@TechReport{Gajnak87, +Author={AOG Systems and Gemini Computers}, +Title={Multilevel Secure Entity-Relationship Database Management System: + Security Policy and Interpretation}, +Institution={AOG Systems and Gemini Computers}, +type={Draft Report}, +Month=aug, +Year=1987 } + +@TechReport{AOG88, +author={AOG Systems Corporation and Gemini Systems Inc.}, +title={Multilevel Secure Entity-Relationship DBMS}, +type={Draft}, +institution={AOG Systems Corporation}, +month={May 19}, +year=1988 } + +@Article{SystemR, +Author={M.M. Astrahan and others}, +Title={System {R}: A Relational Database Management System}, +Journal={Computer}, +Volume=12, +number=5, +Year=1979 } + +@Article{BANE87, +author={J. Banerjee and H.-T. Chou and J. F. Garza and W. Kim and D. Woelk and N. Ballou and H.-J. Kim}, +title={Data Model Issues for Object-Oriented Applications}, +Journal={ACM Transactions on Office Information Systems}, +volume=5, +number=1, +month=jan, +year=1987 } + +@misc{AW6, +Title={Rome Air Development Center Focuses on Expert Systems Applications for C3, Natural Speech Technology}, +Journal={Aviation Week}, +Volume={CXXII(16)}, +pages=84, +month={April 22}, +year=1985 } + +@misc{AW7, +Title={{DARPA}'s Pilot's Associate Program Provides Development Challenges}, +Journal={Aviation Week}, +Volume={CXXIV(7)}, +pages=45, +month={February 17}, +year=1988 } + +@misc{AW8, +Title={{AFIT} Seeks Tactical Aid based on {AI}}, +Journal={Aviation Week}, +Volume={CXXIV(7)}, +pages={61+}, +month={February 17}, +year=1986 } + +@misc{AW5, +Title={Navy Looks Toward Operational Applications}, +Journal={Aviation Week}, +Volume={CXXII(16)}, +pages=67, +month={April 22}, +year=1985 } + +@misc{AW9, +Title={Boeing Accelerates Research, Dissemination of Technology}, +Journal={Aviation Week}, +Volume={CXXIV(7)}, +pages={71+}, +month={February 17}, +year=1986 } + +@misc{Beck80, +Author={L.L. Beck}, +Title={A security mechanism for statistical databases}, +Journal={ACM Transactions on Database Systems}, +Volume=5, +Number=3, +month=sep, +year=1980 } + +@InProceedings{BersonLuntIEEE87, +Author={T.A. Berson and T.F. Lunt}, +Title={Multilevel Security for Knowledge-Based Systems}, +Booktitle={Proceedings of the 1987 IEEE Symposium on Security and Privacy}, +Month=apr, +Year=1987 } + +@InProceedings{BersonLuntClassi87, +Author={T.F. Lunt and T.A. Berson}, +Title={An Expert System to Classify and Sanitize Text}, +Booktitle={Proceedings of the Third Aerospace Computer Security Conference}, +Month=dec, +Year=1987 } + +@TechReport{Biba, +Key="Biba", Author="K.J. Biba", Institution="The Mitre Corporation", +Title="Integrity Considerations for Secure Computer Systems", +Year="1975", Month=jun, Number="MTR 3153", Address="Bedford, Massachusetts" , +Note = {Also available from USAF Electronic Systems Division, Bedford, Massachusetts, +as ESD-TR-76-372, April 1977.} } + +@TechReport{Biba77, +Author={K.J. Biba}, +Title={Integrity Considerations for Secure Computer Systems}, +Institution={USAF Electronic Systems Division}, +Address={Bedford, Massachusetts}, +number={ESD-TR-76-372}, +Month=apr, +Year=1977 } + +@InProceedings{BlakleyDatabase85, +Author={G.R. Blakley and C. Meadows}, +Title={A Database Encryption Scheme which allows the Computation of Statistics using Encrypted Data}, +Booktitle={Proceedings of the 1985 IEEE Symposium on Security and Privacy}, +Month=apr, +Year=1985 } + +@InProceedings{BarkerCryptTMach88, +Author={W.C. Barker and P.S. Cochrane and M.A. Branstad}, +Title={Embedding Cryptography into a {T}rusted {M}ach System}, +Booktitle={Proceedings of the Fourth Aerospace Computer Security Applications Conference}, +Month=dec, +Year=1988 } + +@InProceedings{Burns86, +Author={R. Burns}, +Title={Towards practical {MLS} database management systems using the integrity lock technology}, +Booktitle={Proceedings of the Ninth National Computer Security Conference}, +Year=1986, Month=sep } + +@InProceedings{Casey88, +Author={T.A. {Casey, Jr.} and S.T. Vinter and D.G. Weber and R. Varadarajan and D. Rosenthal}, key={Casey}, +Title={A Secure Distributed Operating System}, +Booktitle={Proceedings of the 1988 IEEE Symposium on Security and Privacy}, +Month=apr, +Year=1988 } + +@InProceedings{Varadarajan89, +author= {R. {Varadarajan et al.}}, key={Varadarajan}, +title={The {S}ecure {D}istributed {O}perating {S}ystem: An Overview}, +Booktitle={1989 Workshop on Operating Systems for Mission Critical Computing, +University of Maryland}, Month=sep, Year={1989} } + +@TechReport{SDOS88, +Author={T.R. {Vinter et al.}}, key={Vinter}, +Title={The {S}ecure {D}istributed {O}perating {S}ystem Design Project}, +Institution={Rome Air Development Center}, +Address={Griffiss Air Force Base, NY}, +number={RADC-TR-88-127}, +Month=jun, Year={1988} } + +@TechReport{Schneider+90, +Author={E.A. Schneider and S. Perlo and D. Rosenthal}, +Title={Discretionary Access Control Mechanisms for Distributed Systems}, +Institution={Rome Air Development Center}, +Address={Griffiss Air Force Base, NY}, +number={RADC-TR-90-275}, +Month=nov, Year={1990} } + +@InProceedings{Chau87, +Author={R. Chau and J.I. Glasgow and M.A. Jenkins}, +Title={A Framework for Knowledge-Based Systems in {N}ial}, +Booktitle={Proceedings of the IEEE Phoenix Conference on Computers and Communications}, +Year=1987 } + +@InProceedings{Chen81, +Author={P.P. Chen}, +chapter={A Preliminary Framework for Entity-Relationship Models}, +Booktitle={Entity-Relationship Approach to Information Modeling and Analysis}, +publisher={ER Institute}, +Year=1981 } + +@Article{Chin82, +Author={F.Y. Chin and G. Ozsoyoglu}, +Title={Auditing and inference control in statistical databases}, +Journal={IEEE Transactions on Software Engineering}, +Volume=8, +Number=6, +month=nov, +year=1982 } + +@InProceedings{Chin79, +Author={F.Y. Chin and G. Ozsoyoglu}, +Title={Security in partitioned dynamic statistical databases}, +Booktitle={Proceedings of the IEEE COMPSAC Conference}, +Year=1979 } + +@Article{Chin81, +Author={F.Y. Chin and G. Ozsoyoglu}, +Title={Statistical database design}, +Journal={ACM Transactions on Database Systems}, +month=mar, +year=1981 } + +@InProceedings{Claybrook83, +Author={B.G. Claybrook}, +Title={Using Views in a Multilevel Secure Database Management System}, +Booktitle={Proceedings of the 1983 IEEE Symposium on Security and Privacy}, +Year=1983 } + +@InProceedings{ClydeInsider87, +Author={A.R. Clyde}, +Title={Insider Threat Identification Systems}, +Booktitle={Proceedings of the 10th National Computer Security Conference}, +month=sep, +Year=1987 } + +@Article{Codd70, +Author={E.F. Codd}, +Title={A Relational Model for Large Shared Data Banks}, +Journal={Communications of the ACM}, +volume=13, +number=6, +month=jun, +year=1970 } + +@Article{Codd79, +Author={E.F. Codd}, +Title={Extending the Database Relational Model to Capture More Meaning}, +Journal={ACM Transactions on Database Systems}, +volume=4, +number=6, +month=dec, +year=1979 } + +@Article{Conway72, +Author={R.W. Conway and W.L. Maxwell and H.L. Morgan}, +Title={On the implementation of security measures in information systems}, +Journal={Communications of the ACM}, +volume=15, +number=4, +month=apr, +year=1972 } + +@TechReport{Cox78, +Author={L.H. Cox}, +Title={Suppression Methodology and Statistical Disclosure Control}, +type={Technical Report~Confidentiality in Surveys}, +number=26, +Institution={Department of Statistics, University of Stockholm}, +Address={Stockholm, Sweden}, +Month=jan, +Year=1978 } + +@Article{Cox80, +Author={L.H. Cox}, +Title={Suppression methodology and statistical disclosure control}, +Journal={J. Amer. Stat. Assoc.}, +volume=75, +number=370, +month=jun, +year=1980 } + +@TechReport{Cox81, +Author={L.H. Cox and L.R. Ernst}, +Title={Controlled Rounding}, +type={Technical Report}, +Institution={U.S. Bureau of the Census}, +Address={Washington, D.C.}, +Month=jan, +Year=1981 } + +@TechReport{EHDMUserguide, +Author={J.S. Crow and S.T. Jefferson and R. Lee and P.M. Melliar-Smith and J.M. Rushby and R.L. Schwartz and R.E. Shostak and F.W. von Henke}, +Title={SRI Specification and Verification System Version 3.1 - User's Guide}, +Institution={Computer Science Laboratory, SRI International}, +Address={Menlo Park, California}, +Month=oct, +Year=1986 } + +@TechReport{EHDMLanguage, +Author={J.S. Crow and S.T. Jefferson and R. Lee and P.M. Melliar-Smith and J.M. Rushby and R.L. Schwartz and R.E. Shostak and F.W. von Henke}, +Title={SRI Specification and Verification System Version 3.0 - Preliminary Definition of the Revised SPECIAL Specification Language}, +Institution={Computer Science Laboratory, SRI International}, +Address={Menlo Park, California}, Month=may, +year=1986 } + +@misc{IEEEComputer86, +title={Special Issue on Expert System Applications}, +Journal={Computer}, +month=jul, +year=1986 } + +@TechReport{CCA85, +Author={CCA}, +Title={Robust Distributed Database Update System}, +type={Interim Technical Report}, +Institution={CCA}, +Month=feb, +year=1985 } + +@article{DSL7, +title={Silicon {V}alley Group Holds Second Meeting}, +journal={Data Security Letter}, +editor={T.F. Lunt}, +volume=1, +number=7, +month=jan, +year=1989 } + +@InProceedings{DaleniusReiss79, +Author={T. Dalenius and S.P. Reiss}, +Title={Data-swapping -- a technique for disclosure control}, +Booktitle={Proceedings of the Section on Survey Research Methods}, +organization={American Statistics Association}, +address={Washington, D.C.}, +Year=1979 } + +@Book{Date83, +Author={C.J. Date}, +Title={An Introduction to Database Systems}, +volume={II}, +publisher={Addison-Wesley, Reading, Massachusetts}, +year=1983 } + +@Book{Date86, +Author={C.J. Date}, +Title={An Introduction to Database Systems}, +volume={I}, +edition={Fourth}, +publisher={Addison-Wesley}, +address={Reading, Massachusetts}, +year=1986 } + +@Article{Davida81, +Author={G.I. Davida and D.L. Wells and J.B. Kam}, +Title={A Database Encryption System with Subkeys}, +Journal={ACM Transactions on Database Systems}, +volume=6, +number=2, +month=jun, +year=1981 } + +@Article{DAVID84, +Author={S.B. Davidson}, +Title={Optimism and Consistency in Partitioned Distributed Database Systems}, +Journal={ACM Transactions on Database Systems}, +volume=9, +number=3, +month=sep, +year=1984 } + +@Article{DAVID85, +Author={S.B. Davidson and H. Garcia-Molina and D. Skeen}, +Title={Consistency in Partitioned Networks}, +Journal={ACM Computing Surveys}, +volume=17, +number=3, +month=sep, +year=1985 } + +@misc{Davison88, +Author={J.W. Davison}, +title={Implementation Design for a Kernelized Trusted DBMS}, +booktitle={Research Directions in Database Security}, +editor={T.F. Lunt}, +note={to appear} } + +@InProceedings{Delisle86, +Author={N. Delisle and M. Schwartz}, +Title={Neptune: A Hypertext System for {CAD} Applications}, +Booktitle={ACM SIGMOD Conference Proceedings}, +Year=1986 } + +@Article{DenningTracker79, +Author={D.E. Denning and P.J. Denning and M.D. Schwartz}, +Title={The {T}racker: a Threat to Statistical Database Security}, +Journal={ACM Transactions on Database Systems}, +volume=4, +number=1, +month=mar, +year=1979 } + +@Article{DenningFast80, +Author={D.E. Denning and J. Schlorer}, +Title={A fast procedure for finding a tracker in a statistical database}, +Journal={ACM Transactions on Database Systems}, +volume=5, +number=1, +month=mar, +year=1980 } + +@Article{DenningRSQ80, +Author={D.E. Denning}, +Title={Secure Statistical Databases under Random Sample Queries}, +Journal={ACM Transactions on Database Systems}, +volume=5, +number=3, +month=sep, +year=1980 } + +@Article{DenningMemoryless82, +Author={D.E. Denning and J. Schlorer and E. Wehrle}, +Title={Memoryless inference controls for statistical databases}, +Journal={ACM Transactions on Database Systems}, +year=1982 } + +@misc{DenningWorking82, +Author={D.E. Denning}, +title={Multilevel Secure Database Systems: Requirements and Model}, +type={Working Paper}, +organization={NAS/AFSB Summer Study on Multilevel Databases}, +year=1982 } + +@Book{DenningBook82, +Author={D.E. Denning}, +Title={Cryptography and Data Security}, +publisher={Addison-Wesley}, +address={Reading, Massachusetts}, +year=1982 } + +@Article{DenningInference83, +Author={D.E. Denning and J. Schlorer}, +Title={Inference controls for statistical database security}, +Journal={Computer}, +volume=16, +number=7, +month=jul, +year=1983 } + +@InProceedings{DenningField83, +Author={D.E. Denning}, +Title={Field Encryption and Authentication}, +Booktitle={Proceedings of CRYPTO '83}, +publisher={Plenum Press}, +Year=1983 } + +@InProceedings{DenningModel83, +Author={D.E. Denning}, +Title={A Security Model for Statistical Databases}, +Booktitle={Proceedings of the Second International + Workshop on Statistical Database Management}, +organization={Lawrence Berkeley Laboratory}, +month=sep, +Year=1983 } + +@InProceedings{DenningChecksums84, +Author={D.E. Denning}, +Title={Cryptographic Checksums for Multilevel Data Security}, +Booktitle={Proceedings of the 1984 IEEE Symposium on Security and Privacy}, +Year=1984 } + +@InProceedings{DenningCommutative85, +Author={D.E. Denning}, +Title={Commutative Filters for Reducing Inference Threats in Multilevel + Database Systems}, +Booktitle={Proceedings of the 1985 IEEE Symposium on Security and Privacy}, +Year=1985 } + +@InProceedings{DenningSafety86, +Author={D.E. Denning}, +Title={Secure Databases and Safety: Some Unexpected Conflicts}, +Booktitle={Proceedings of the Safety and Security Symposium}, +organization={Centre for Software Reliability}, +month=oct, +Year=1986 } + +@InProceedings{DenningInfer86, +Author={D.E. Denning}, +Title={The Inference Problem in Multilevel Database Systems}, +Booktitle={Proceedings of the National Computer Security Center +Invitational Workshop on Database Management Security}, +month=jun, +Year=1986 } + +@TechReport{DenningCECOM86, +Author={D.E. Denning and M. Morgenstern}, +Title={Military Database Technology Study: AI Techniques for + Security and Reliability}, +Institution={Computer Science Laboratory, SRI International}, +Address={Menlo Park, California}, +Year=1986 } + +@TechReport{IDESFinal87, +Author={D.E. Denning and D.L. Edwards and R. Jagannathan and T.F. Lunt and P.G. +Neumann}, Title={A Prototype {IDES}: A Real-Time Intrusion-Detection Expert +System}, Institution={Computer Science Laboratory, SRI International}, +Address={Menlo Park, California}, Year=1987 } + +@Article{IDES87, +Author={D.E. Denning}, +Title={An Intrusion-Detection Model}, +Journal={IEEE Transactions on Software Engineering}, +volume=13, +number=2, +month=feb, +year=1987 } + +@InProceedings{DenningSocial87, +Author={D.E. Denning and P.G. Neumann and Donn B. Parker}, +Title={Social Aspects of Computer Security}, +Booktitle={Proceedings of the 10th National Computer Security Conference}, +month=sep, +Year=1987 } + +@Article{DenningViews87, +Author={D.E. Denning and S.G. Akl and M. Heckman and T.F. Lunt and M. Morgenstern and P.G. Neumann and R.R. Schell}, +Title={Views for Multilevel Database Security}, +Journal={IEEE Transactions on Software Engineering}, +volume=13, +number=2, +month=feb, +year=1987 } + +@InProceedings{DenningDataModel87, +Author={D.E. Denning and T.F. Lunt and R.R. Schell and M. Heckman and W.R. Shockley}, +Title={A Multilevel Relational Data Model}, +Booktitle={Proceedings of the 1987 IEEE Symposium on Security and Privacy}, +month=apr, +Year=1987 } + +@misc{DenningLessons87, +author={D.E. Denning}, +title={Lessons Learned from Modeling a Secure Multilevel Relational Database System}, +type={draft report}, +Institution={Computer Science Laboratory, SRI International}, +Address={Menlo Park, California}, +Year=1987 } + +@InProceedings{DenningModel88, +Author={D.E. Denning and T.F. Lunt and R.R. Schell and W.R. Shockley and M. Heckman}, +Title={The {SeaView} Security Model}, +Booktitle={Proceedings of the 1988 IEEE Symposium on Security and Privacy}, +month=apr, +Year=1988 } + +@Article{DeKleer86, +Author={J. de Kleer}, +Title={An Assumption-Based {TMS}}, +Journal={Artificial Intelligence Journal}, +volume=28, +number=2, +month=mar, +year=1986 } + +@InProceedings{Dillaway86, +Author={B.B. Dillaway and J.T. Haigh}, +Title={A Practical Design for a Multilevel Secure Database Management System}, +Booktitle={Proceedings of the Second Aerospace Computer Security Conference}, +month=dec, +Year=1986 } + +@Article{Dobkin79, +Author={D. Dobkin and A.K. Jones and R.J. Lipton}, +Title={Secure databases: protection against user inference}, +Journal={ACM Transactions on Database Systems}, +volume=4, +number=1, +month=mar, +year=1979 } + +@InProceedings{Downs77, +Author={D.Downs and G.J. Popek}, +Title={A Kernel Design for a Secure Data Base Management System}, +Booktitle={Proceedings of the Third Conference on Very Large Data Bases}, +Year=1977 } + +@TechReport{Duffy85, +Author={K.J. Duffy and J. Sullivan}, +Title={Integrity Lock Prototype}, +type={Technical Report}, +Institution={The Mitre Corporation}, +Address={Bedford, Massachusetts}, +month=dec, +Year=1985 } + +@TechReport{HoneywellPolicy87, +author={B.B. Dillaway and others}, +Title="Security Policy Extensions for a Database Management System", +type={Interim Report A002}, +institution="Honeywell Systems Research Center and + Corporate Systems Development Division", +Month=apr, +Year=1987 } + +@InProceedings{Dittrich88, +Author={K.R. Dittrich and M. Hartig and H. Pfefferle}, +Title={Discretionary Access Control in Structurally Object-Oriented Database Systems}, +Booktitle={Proceedings of the Second IFIP WG11.3 Workshop on Database Security}, +month=oct, +Year=1988 } + +@TechReport{Dwyer88, +author={P. Dwyer and E. Onuegbe and B.M. Thuraisingham}, +Title="Design of a Query Processor for a Multilevel Secure Relational Database Management System", +type={Technical Report}, +institution="Honeywell Systems Research Center and + Corporate Systems Development Division", +Year=1988 } + +@Article{Dwyer87, +Author={P.A. Dwyer and G.D. Jelatis and B.M. Thuraisingham}, +Title={Multilevel Security in Database Management Systems}, +Journal={Computers and Security}, +volume=6, +number=3, +month=jun, +year=1987 } + +@TechReport{HoneywellSpec88, +author={P.Dwyer and E. Onuegbe and P. Stachour and B. Thuraisingham}, +Title="Secure Distributed Data Views: Implementation Specifications", +type={Interim Report A005}, +institution="Honeywell Systems Research Center and + Corporate Systems Development Division", +Month=may, +Year=1988 } + +@Article{Erman80, +Author={L.D. Erman and F. Hayes-Roth and V.R. Lesser and D.R. Reddy}, +Title={The {H}earsay-{II} Speech Understanding System: Integrating Knowledge to Resolve Uncertainty}, +Journal={Computing Surveys}, +volume=12, +month=jun, +year=1980 } + +@InProceedings{Erman86, +Author={L.D. Erman and J.S. Lark and F. Hayes-Roth}, +Title={Engineering Intelligent Systems: Progress Report on {ABE}}, +Booktitle={Proceedings of the DARPA Expert Systems Workshop}, +month=apr, +Year=1986 } + +@TechReport{ECMA85, +author={European Computer Manufacturers' Assocation, Technical Committee 29}, +Title="Office Document Architecture", +type={Standard ECMA-101}, +address={Geneva}, +Month=sep, +Year=1985 } + +@Article{Fagin78, +Author={R. Fagin}, +Title={On an authorization mechanism}, +Journal={ACM Transactions on Database Systems}, +volume=3, +number=3, +month=sep, +year=1978 } + +@Book{Fernandez81, +Author={E.B. Fernandez and R.C. Summers and C. Wood}, +Title={Database Security and Integrity}, +publisher={Addison-Wesley}, +address={Reading, Massachusetts}, +year=1981 } + +@InProceedings{FISCH82, +Author={M.J. Fischer and A. Michael}, +Title={Sacrificing Serializability to Attain High Availability of Data + in an Unreliable Network}, +Booktitle={Proceedings of the ACM SIGACT-SIGMOD Symposium on + Principles of Database Systems}, +Year=1982 } + +@Book{Fodor, +Author={Fodor's Travel Guides}, +Title={FODOR's Germany West and East 1986}, +publisher={Fodor}, +year=1986, +note={page 443} } + +@Article{S4, +Author={J.P. Flynn and T.E. Senator}, +Title={DARPA Naval Battle Management Applications}, +Journal={Signal}, +volume={XL(10)}, +pages={59+}, +month=jun, +year=1986 } + +@InProceedings{Froscher88, +Author={J.N. Froscher and C. Meadows}, +Title={Achieving a Trusted Database Management System Using Parallelism}, +Booktitle={Proceedings of the 1988 IFIP WG 11.3 Workshop on Database Security}, +month=oct, +Year=1988 } + +@InProceedings{Gajnak88, +Author={G.E. Gajnak}, +Title={Some Results from the Entity/Relationship Multilevel Secure {DBMS} Project}, +Booktitle={Proceedings of the Fourth Aerospace Computer Security + Applications Conference}, +month=dec, +Year=1988 } + +@InProceedings{GARCI83, +Author={H. Garcia-Molina and others}, +Title={Data-{P}atch: Integrating Inconsistent Copies of a Database After a Partition}, +Booktitle={Proceedings of the Third IEEE Symposium on Reliability +in Distributed Software and Database Systems}, +Year=1983 } + +@InProceedings{GARV88, +Author={C. Garvey and N. Jenson and J. Wilson}, +Title={The Advanced Secure {DBMS}: Making Secure {DBMS}s Usable}, +Booktitle={Proceedings of the IFIP Working Group 11.3 Workshop on Database Security}, +month=oct, +Year=1988 } + +@TechReport{Garvey86, +author={C. Garvey}, +Title="Multilevel Data Store Design ({MLDS})", +type={Technical Report}, +institution="TRW Defense Systems Group", +Year=1986 } + +@InProceedings{Garvey88, +Author={C. Garvey}, +Title={{ASD} Views}, +Booktitle={Proceedings of the 1988 IEEE Symposium on Security and + Privacy}, +month=apr, +Year=1988 } + +@InProceedings{Ginsberg87, +Author={A. Ginsberg}, +Title={A New Approach to Checking Knowledge Bases for Inconsistency and Redundancy}, +Booktitle={Proceedings of the Third Expert Systems in Government Conference}, +Year=1987 } + +@InProceedings{Ginsberg88, +Author={A. Ginsberg}, +Title={Knowledge-Base Reduction: A New Approach to Checking Knowledge-Bases for +Inconsistency and Redundancy}, +Booktitle={Proceedings of the AAAI 88}, +volume=2, +Year=1988 } + +@InProceedings{Goguen84, +Author={J.A. Goguen and J. Meseguer}, +Title={Unwinding and Inference Control}, +Booktitle={Proceedings of the 1984 IEEE Symposium on Security and Privacy}, +Year=1984 } + +@InProceedings{Graham72, +Author={G.S. Graham and P.J. Denning}, +Title={Protection: Principles and Practice}, +Booktitle={Proceedings of the Spring Joint Computer Conference}, +volume=40, +publisher={AFIPS Press}, +address={Montvale, New Jersey}, +Year=1972 } + +@InProceedings{Graubart82, +Author={R.D. Graubart and J.P.L. Woodward}, +Title={A Preliminary Naval Surveillance {DBMS} Security Model}, +Booktitle={Proceedings of the 1982 IEEE Symposium on Security and Privacy}, +month=apr, +Year=1982 } + +@InProceedings{Graubart84, +Author={R.D. Graubart}, +Title={The integrity-lock approach to secure database management}, +Booktitle={Proceedings of the 1984 IEEE Symposium on Security and Privacy}, +Year=1984 } + +@Article{Griffiths76, +Author={P.P. Griffiths and B.W. Wade}, +Title={An Authorization Mechanism for a Relational Database System}, +Journal={ACM Transactions on Database Systems}, +volume=1, +number=3, +pages={59+}, +month=sep, +year=1976 } + +@TechReport{Grohn76, +author={M.J. Grohn}, +Title="A Model of a Protected Data Management System", +type={Technical Report}, +number={ESD-TR-76-289}, +institution="I.P. Sharp Associates Ltd.", +month=jun, +Year=1976 } + +@Book{LifeBerlin, +Author={Fredric V. Grunfeld and the Editors of Time-Life Books}, +Title={Berlin}, +publisher={Time-Life Books}, +year=1977 } + +@TechReport{Gusfield84, +author={D. Gusfield}, +Title="A Graph Theoretic Approach to Statistical Data Security", +type={Technical Report}, +number={327}, +institution="Computer Science Department, Yale University", +month=aug, +Year=1984 } + +@Article{DR87, +Author={D.W. Haskin}, +Title={Keeping Watch on a {VAX}}, +Journal={Digital Review}, +month={December 16}, +year=1987 } + +@Book{Hayes-RothBook, +editor={F. Hayes-Roth and D.A. Waterman and D.B. Lenat}, +Title={Building Expert Systems}, +publisher={Addison-Wesley}, +address={Reading, Massachusetts}, +year=1983 } + +@TechReport{Heitmeyer85, +Author={C.L. Heitmeyer and M. Cornwell}, +Title={Specifications for Three Members of the Military Message System {(MMS)} + Family}, Institution={Naval Research Laboratory}, +type={{NRL} Memorandum Report 5645}, +day={9}, month=sep, +Year=1985 } + +@TechReport{Heitmeyer86, +Author={C.L. Heitmeyer}, +Title={Requirements for the Military Message System Family: Data Types and User Commands}, +Institution={Naval Research Laboratory}, +type={{NRL} Memorandum Report 5670}, +day={11}, month=apr, +Year=1986 } + +@TechReport{HinkeSchaefer, +Author="T.H. Hinke and M. Schaefer", +Title="Secure Data Management System", Note = "RADC-TR-266 (NTIS AD A019201)", +Institution="Rome Air Development Center", Month=nov, Year="1975"} + +@InProceedings{Hinke86, +Author={T.H. Hinke}, +Title={Secure database management system architectural analysis}, +Booktitle={Proceedings of the National Computer Security Center Invitational + Workshop on Database Management Security}, +month=jun, +Year=1986 } + +@InProceedings{HINK88b, +Author={T.H. Hinke and C. Garvey and N. Jensen and J. Wilson and A. Wu}, +Title={A1 Secure {DBMS} Design}, +Booktitle={Proceedings of the Eleventh National Computer Security Conference - Appendix}, +month=oct, +Year=1988 } + +@InProceedings{HINK88c, +Author={T.H. Hinke}, +Title={Database Inference Engine Design Approach}, +Booktitle={Proceedings of the IFIP Working Group 11.3 Workshop on Database Security}, +month=oct, +Year=1988 } + +@InProceedings{Hinke88, +Author={T.H. Hinke}, +Title={Inference Aggregation Detection in Database Management Systems}, +Booktitle={Proceedings of the 1988 IEEE Symposium on Security and Privacy}, +month=apr, +Year=1988 } + +@InProceedings{Hinke88b, +Author={T.H. Hinke and C. Garvey and A. Wu}, +Title={A1 Secure {DBMS} Architecture}, +Booktitle={Research Directions in Database Security}, +editor={T.F. Lunt}, +year={forthcoming} } + +@Article{Hoffman70, +Author={L.J. Hoffman and W.F. Miller}, +Title={Getting a personal dossier from a statistical data bank}, +Journal={Datamation}, +volume=16, +number=5, +month=may, +year=1970 } + +@book{InvitationalWorkshop, +title={Proceedings of the National Computer Security Center Invitational Workshop on Database Security}, +address={Baltimore, Maryland}, +month=jun, +year=1986 } + +@Article{IrvingMonitoring86, +Author={R.H. Irving and C.A. Higgins and F.R. Safayeni}, +Title={Computerized Performance Monitoring Systems: Use and Abuse}, +Journal={Communications of the ACM}, +volume=29, +number=8, +year=1986 } + +@TechReport{Javitz86, +author={H.S. Javitz and A. Valdes and D.E. Denning and P.G. Neumann}, +Title="Analytical Techniques Development for a Statistical Intrusion-Detection System ({SIDS}) based on Accounting Records", +institution="SRI International", +address={Menlo Park, California}, +month=jul, +Year=1986 +} + +@InProceedings{JENS88, +Author={N. Jensen}, +Title={System Security Officer Functions in the A1 Secure DBMS}, +Booktitle={Proceedings of the IFIP Working Group 11.3 Workshop on Database Security}, +month=oct, +Year=1988 } + +@Article{DE1, +Author={J.F. Judge}, +Title={{SCP} Gets High Marks at Midterm}, +Journal={Defense Electronics}, +volume={XVII(5)}, +pages={65+}, +month=may, +year=1986 } + +@TechReport{Kao86, +author={M. Kao}, +Title="Systematic Protection of Precise Information on Two-Dimensional + Cross Tabulated Tables", +type={Technical Report}, +institution="Computer Science Department, Yale University", +Year=1986 } + +@Article{Kohonen88, +Author={T. Kohonen}, +Title={The ``Neural'' Phonetic Typewriter}, +Journal={Computer}, +month=mar, +year=1988 } + +@Article{Kung81, +Author={H.T. Kung and J.T. Robinson}, +Title={On Optimistic Methods for Concurrency Control}, +Journal={ACM Transactions on Database Systems}, +volume=6, +number=2, +month=jun, +year=1981 } + +@InProceedings{Lampson71, +Author={B.W. Lampson}, +Title={Protection}, +Booktitle={Proceedings of the + Fifth Princeton Symposium on Info. Sci. and Systems}, +month=mar, +Year=1971, +note={Reprinted in ACM Operating Systems Review, Vol. 8 (1), January 1974} } + + +@Book{LaurieBook, +editor={P. Laurie}, +Title={Beneath City Streets}, +publisher={Penguin Books}, +address={Reading, Massachusetts}, +year={circa 1970}, +note={This book's fascinating contents apparently offer an example of what security types call an ``aggregation problem.'' It is out of print} } + +@book{Lehner, +author={P.E. Lehner and T.M. Mullin and M.S. Cohen}, +title={When Should a Decision Maker Ignore the Advise of a Decision Aid?}, +year={to appear} } + +@Article{S9, +Author={L.B. Lenat and A. Clarkson}, +Title={Artificial Intelligence and {C3I}}, +Journal={Signal}, +volume={XL(10)}, +pages={115-119}, +month=jun, +year=1986 } + +@InProceedings{Linde75, +Author={R.R. Linde}, +Title={Operating System Penetration}, +Booktitle={Proceedings of the National Computer Conference}, +Year=1975 } + +@InProceedings{Lochovsky, +author={F.H. Lochovsky and C.C. Woo}, +title={Role-Based Security in Data Base Management Systems}, +booktitle={Database Security: Status and Prospects}, +editor={C.E. Landwehr}, +publisher={North-Holland}, +year=1988 } + +@article{DSL4TDI, +title={A First Glimpse at the {TDI}}, +journal={Data Security Letter}, +editor={T.F. Lunt}, +Volume=1, +number=4, +month=aug, +year=1988 } + +@InProceedings{LuntIDES89a, +Author={T.F. Lunt and R. Jagannathan and R. Lee and A. Whitehurst and S. Listgarten}, +Title={Knowledge-Based Intrusion Detection}, +Booktitle={Proceedings of the 1989 AI Systems in Government Conference}, +month=mar, +Year=1989 } + +@InProceedings{LuntIDES89b, +Author={T.F. Lunt}, +Title={Real-Time Intrusion Detection}, +Booktitle={Proceedings of the COMPCON Spring '89}, +month=mar, +Year=1989 } + +@TechReport{IDESFinal88, +author={T.F. Lunt and R. Jagannathan and R. Lee and S. Listgarten and D.L. Edwards and P.G. Neumann and H.S. Javitz and A. Valdes}, +Title="Development and Application of {IDES}: A Real-Time Intrusion-Detection + Expert System", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, +Year=1988 } + +@TechReport{IDESFinal92, +author={T.F. Lunt and A. Tamaru and F. Gilham and R. Jagannathan +and C. Jalali and P.G. Neumann and H.S. Javitz and A. Valdes}, +Title="{A Real-Time Intrusion-Detection Expert System} {(IDES)}", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, day={28}, month={February}, Year=1992 } + +@TechReport{NIDES-SDD93, +author={R. Jagannathan and T.F. Lunt and D. Anderson and C. Dodd and +F. Gilham and C. Jalali and H.S. Javitz and P.G. Neumann and +A. Tamaru and A. Valdes}, +Title="System {Design} {Document}: {Next-generation Intrusion-Detection +Expert System} {(NIDES)}", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, day={9}, month={March}, Year=1993 } + +@TechReport{Safeguard93, +author={D. Anderson and T. Lunt and H. Javitz and A. Tamaru and A. Valdes}, +Title={Safeguard Final Report: Detecting Unusual Program Behavior Using +the {NIDES} Statistical Component}, +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, day={2}, month=dec, Year=1993 } + +@TechReport{Javi94, +author={H.S. Javitz and A. Valdes}, +Title={The {NIDES} Statistical Component Description and Justification}, +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, Month=mar, Year=1994 } + +@TechReport{CalderaraKo, +author={A.B. Calderara and Hai-Ping Ko}, +Title={Intrusion Detection with {NIDES} in a Simulated Environment}, +institution="GTE Government Systems Corporation", +address={Needham, Massachusetts}, Month={}, Year=1995 } + +@TechReport{NIDES-SOUI93, +author={D. Anderson and C. Dodd and +F. Gilham and C. Jalali and A. Tamaru and M. Tyson}, +Title="Next-generation Intrusion-Detection Expert System {(NIDES)}: +User Manual for Security Officer User Interface {(SOUI)}", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, day={26}, month={March}, Year=1993 } + +@TechReport{NIDES-SOUI94, +author={D. Anderson and T. Frivold and A. Tamaru and A. Valdes}, +Title="{Next-generation Intrusion-Detection Expert System} {(NIDES)}: +User Manual for Security Officer User Interface {(SOUI)}", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, day={19}, month={May}, Year=1994 } + +@TechReport{NIDES-final94, +author={D. Anderson and T. Frivold and A. Valdes}, +Title="{Next-generation Intrusion-Detection Expert System} {(NIDES)}: +Final Technical Report", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, day={16}, month=nov, Year=1994 } + +@TechReport{NIDES95, +author={D. Anderson and T. Frivold and A. Valdes}, +Title="{Next-generation Intrusion-Detection Expert System} {(NIDES)}", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California, SRI-CSL-95-07}, Month=may, Year=1995 } + +@TechReport{EMERALD1xxx, +author={P.A. Porras and P.G. Neumann}, +Title={{EMERALD: Event Monitoring Enabling Responses to Anomalous Live + Disturbances}}, +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, Month=feb, Year=1997, +Note = {Submitted for publication.} } + +@TechReport{EMERALD2, +author={P.A. Porras and P.G. Neumann}, +Title={{EMERALD Message System Requirements Statement}}, +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, Month=feb, Year=1997} + +@InProceedings{PorrasNeumann97, +Author = "P.A. Porras and P.G. Neumann", +Title = "{{EMERALD: Event Monitoring Enabling Responses to Anomalous + Live Disturbances}}", +Booktitle= + "Proceedings of the Nineteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1997", +Pages="353--365", Month = "22-25 October" } + +@InProceedings{PorrasValdes97, +Author = "P.A. Porras and A. Valdes", +Title = "Live Traffic Analysis of {TCP/IP} Gateways", +Booktitle= "Proceedings of the Symposium on Network and + Distributed System Security", +Organization = "Internet Society", Year = "1998", +Pages="", Month = mar } + +@InProceedings{NeumannPorras99, +Author={P.G. Neumann and P.A. Porras}, +Title={Experience with {EMERALD} to Date}, +BookTitle={Proceedings of the First USENIX Workshop on +Intrusion Detection and Network Monitoring}, +Organization={USENIX}, Address={Santa Clara, California}, +Year={1999}, Month=apr, pages={73--80}, +Note = {Best paper}, +url = "http://www.csl.sri.com/neumann/det99.html"} + +@InProceedings{LindqvistPorras99, +Author={U. Lindqvist and P.A. Porras}, +Title={Detecting Computer and Network Misuse through the {Production-Based + Expert System Toolset (P-BEST)}}, +BookTitle={Proceedings of the 1999 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1999}, Month=may, pages={}} + +@InProceedings{Lindqvist:2001:EXPERTBSM, + Author={U. Lindqvist and P.A. Porras}, + title = "{eXpert-BSM}: A Host-based Intrusion-Detection + Solution for {Sun Solaris}", + booktitle = "Proceedings of the 17th Annual Computer Security + Applications Conference ({ACSAC} 2001)", + month = "10--14 December", + year = 2001, + address = "New Orleans, Louisiana", +} + +@InProceedings{Almgren:2001:AIDCFSM, + author = "M. Almgren and U. Lindqvist", + title = "Application-Integrated Data Collection for + Security Monitoring", + booktitle = "Recent Advances in Intrusion Detection + ({RAID~2001})", + month = "10--12 October", + year = 2001, + address = "Davis, California", +} + +@PhDThesis{Lindqvist99, +Author={U. Lindqvist}, +School={Department of Computer Engineering, Chalmers University of Technology}, +Title={On the Fundamentals of Analysis and Detection of Computer Misuse}, +Year={1999}, Month={}, Note = "ISBN 91-7197-832-1" } + +@TechReport{PorrasNitz03, +Author = "P.A. Porras and K. Nitz and U. Lindqvist and M. Fong and + P.G. Neumann", +Title = "Discerning Attacker Intent", +Institution={Computer Science Laboratory, SRI International, Project 10779}, +Year={2003}, Month=apr, Address={Menlo Park, California} } + +@TechReport{CIDF, +author={P.A. Porras}, +Title={Common Intrusion Detection Framework}, +institution= {Computer Science Lab, SRI International}, +address={Menlo Park, California}, month =apr, Year=1998 } + +@InProceedings{Jagan89GLU, +Author = {R. Jagannathan}, +Title = {Transparent Multiprocessing in the Presence of Fail-Stop Faults}, +Booktitle = {Proceedings of the 3rd Workshop on Large-Grain Parallelism}, +Organization = {}, Address = {Pittsburgh, Pennsylvania}, +Year = {1989}, +Pages={}, Month = oct } + +@TechReport{JaganGLU, +Author={R. Jagannathan and A.A. Faustini}, Key={Jagannathan}, +Institution={Computer Science Laboratory, SRI International}, +Title={The {GLU} Programming Language}, Note={CSL Technical Report CSL-90-11}, +Year={1990}, Month=nov, Address={Menlo Park, California} } + +@TechReport{Jagan94GLU, +Author={R. Jagannathan and C. Dodd}, Key={Jagannathan}, +Institution={Computer Science Laboratory, SRI International}, +Title={{GLU} Programmer's Guide v0.9}, Note={CSL Technical Report CSL-94-06}, +Year={1994}, Month=nov, Address={Menlo Park, California} } + +@InProceedings{Jagan95Coarse, +Author = {R. Jagannathan}, +Title = {Coarse-Grain Dataflow Programming of Conventional Parallel Computers}, +Booktitle = {{\it Advanced Topics in Dataflow Computing and Multithreading} + (edited by L. Bic, J-L. Gaudiot, and G. Gao)}, +Organization = {IEEE Computer Society}, Address = {}, Year = {1995}, +Pages={}, Month = apr } +% ISBN 0-8186-6542-4. + +@InProceedings{LuntSurvey88, +Author={T.F. Lunt}, +Title={Automated Audit-Trail Analysis and Intrusion Detection: A Survey}, +Booktitle={Proceedings of the Eleventh National Computer Security Conference}, +month=oct, pages={188-193}, Year=1988 } + +@InProceedings{LuntAudit86, +Author={T.F. Lunt and J. van Horne and L. Halme}, +Title={Automated Analysis of Computer System Audit Trails}, +Booktitle={Proceedings of the Ninth DOE Computer Security Group Conference}, +month=may, +Year=1986 } + +@TechReport{LuntSytek1, +author={T.F. Lunt and J. van Horne and L. Halme}, +Title="Analysis of Computer System Audit Trails: Initial Data Analysis", +type={Technical Report}, +number={TR-85009}, +institution="Sytek", +address={Mountain View, California}, +month=sep, +Year=1985 } + +@TechReport{LuntSytek2, +author={T.F. Lunt and J. van Horne and L. Halme}, +Title="Analysis of Computer System Audit Trails: Intrusion Characterization", +type={Technical Report}, +number={TR-85012}, +institution="Sytek", +address={Mountain View, California}, +month=oct, +Year=1985 } + +@TechReport{LuntSytek3, +author={T.F. Lunt and J. van Horne and L. Halme}, +Title="Analysis of Computer System Audit Trails: Feature Identification and + Selection", +type={Technical Report}, +number={TR-85018}, +institution="Sytek", +address={Mountain View, California}, +month=dec, +Year=1985 } + +@TechReport{LuntSytek4, +author={T.F. Lunt and J. van Horne and L. Halme}, +Title="Analysis of Computer System Audit Trails: Design and Program Classifier", +type={Technical Report}, +number={TR-86005}, +institution="Sytek", +address={Mountain View, California}, +month=mar, +Year=1986 } + +@InProceedings{LuntBerson87, +Author={T.F. Lunt and T.A. Berson}, +Title={Security Considerations for Knowledge-Based Systems}, +Booktitle={Proceedings of the Third Expert Systems in Government Conference}, +month=oct, +Year=1987 } + +@Article{LuntAssurance87, +Author={T.F. Lunt and D.E. Denning and R.R. Schell and M. Heckman and W.R. Shockley}, +Title={Element-Level Classification with {A}1 Assurance}, +Journal={Computers and Security}, +month=feb, +year=1988 } + +@MASTERSTHESIS{Porras92, +AUTHOR = {P.A. Porras}, +TITLE = {{STAT}: A {S}tate {T}ransition {A}nalysis {T}ool for Intrusion + Detection}, +SCHOOL={Computer Science Department, University of California, Santa Barbara}, +YEAR = {1992}, MONTH = jul } + +@TechReport{DenningPolicy86, +author={T.F. Lunt and D.E. Denning and P.G. Neumann and R.R. Schell and M. Heckman and W.R. Shockley}, +Title="Final Report Vol.\ 1: Security Policy and Policy Interpretation for a + Class A1 Multilevel Secure Relational Database System", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, +Year=1988 } + +@Article{LuntQuestions88, +Author={T.F. Lunt}, +Title={Access Control Policies: Some Unanswered Questions}, +Journal={Computers and Security}, +month=feb, +year=1989 } + + +@InProceedings{LuntIFIP88, +Author={T.F. Lunt}, +Title={Access Control Policies for Database Systems}, +Booktitle={Proceedings of the Second IFIP WG11.3 Workshop on Database Security}, +month=oct, +Year=1988 } + +@TechReport{MillenLuntReport89, +author={J.K. Millen and T.F. Lunt}, +title={Secure Knowledge-Based Systems}, +institution={Computer Science Laboratory, SRI International}, +type={Technical Report}, +number={SRI-CSL-90-04}, +address={Menlo Park, California}, +month=aug, +year = 1989 } + +@TechReport{LuntDAC90, +Author={T.F. Lunt}, +Title={Discretionary Security for Object-Oriented Database Systems}, +type={Technical Report}, +number={RADC-TR-91-17}, +institution="Rome Air Development Center", +month=mar, Year=1991 } + +@inproceedings{issues89, author={A. Downing and I. Greenberg and T. Lunt}, +title={Issues in Distributed System Security}, booktitle={Proceedings of the Fifth +Aerospace Computer Security Conference}, month=dec, year=1989 } + +@InProceedings{LuntDistributed89xxx, +Author={T.F. Lunt and A. Downing and I. Greenberg}, +Title={Issues in Distributed Database Security}, +Booktitle={Proceedings of the Twelfth National Computer Security Conference}, +Year={submitted for publication, not accepted} } + +@InProceedings{LuntObject89, +Author={T.F. Lunt}, +Title={Multilevel Security for Object-Oriented Database Systems}, +Booktitle={Proceedings of the Third IFIP Database Security Workshop}, +month=sep, +Year=1989 } + +@InProceedings{VonHenke88, +author={J.S. Crow and R. Lee and J.M. Rushby and F.W. von Henke and R.A. Whitehurst}, +title={{EHDM} Verification Environment: An Overview}, +booktitle={Proceedings of the Eleventh National Computer Security Conference}, +month=oct, +year=1988 } + + +@TechReport{LuntSpec88, +author={T.F. Lunt and R.A. Whitehurst}, +Title={Final Report Vol.\ 3A: The {SeaView} Formal Top Level Specifications}, +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, +Year=1989 } + + +@TechReport{LuntDef89, +Author={T.F. Lunt}, +Title={Final Report Vol.\ 4: Secure Distributed Data Views: Identification of Deficiencies and Directions for Future Research}, +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, +Year=1989 } + + +@InProceedings{Shockley87, +Author={W.R. Shockley and R.R. Schell}, +Title={{TCB} Subsetting for Incremental Evaluation}, +Booktitle={Proceedings of the Second AIAA Conference on Computer Security}, +month=dec, +Year=1987 } + +@TechReport{vonGlahn83, +Author={P.G. {von Glahn}}, key={vonGlahn}, +Title={An Annotated Computer Network Security Bibliography}, +Institution={Rome Air Development Center}, +Address={Griffiss Air Force Base, NY 13441}, +number={RADC-TR-83-251}, +Month=nov, Year={1983} } + +@Article{Reed79, +Author={D.P. Reed and R.K. Kanodia}, +Title={Synchronization with Eventcounts and Sequencers}, +Journal={Communications of the ACM}, +volume=22, number=2, month=feb, year=1979 } + +@InProceedings{LuntA188, +Author={T.F. Lunt}, +Title={Multilevel Database Systems: Meeting Class {A}1}, +Booktitle={Proceedings of the Second IFIP WG11.3 Workshop on Database Security}, +month=oct, +Year=1988 } + +@TechReport{Greenberg90 + ,Key={} + ,Author={I.B. Greenberg and A.R. Downing and M. Morgenstern} + ,Institution={SRI International} + ,Title={{Distributed database integrity}} + ,Year={1990} + ,Month=apr + ,Number={} + ,Address={Menlo Park, California} + ,Type={Interim Report} + ,Note={For RADC Contract No. F30602-89-C-0055} + ,Read={y} + ,File={} + } + +@TechReport{Greenberg91a + ,Key={} + ,Author={I.B. Greenberg and P.K. Rathmann} + ,Institution={SRI International} + ,Title={{Distributed database integrity}} + ,Year={1990} + ,Month=nov + ,Number={} + ,Address={Menlo Park, California} + ,Type={Final Report} + ,Note={For RADC Contract No. F30602-89-C-0055} + ,Read={y} + ,File={} + } + +@TechReport{Greenberg91b + ,Key={} + ,Author={I.B. Greenberg and P.K. Rathmann} + ,Institution={SRI International} + ,Title={{Feasibility Implementation Plan}} + ,Year={1990} + ,Month=nov + ,Number={} + ,Address={Menlo Park, California} + ,Type={Interim Report} + ,Note={For RADC Contract No. F30602-89-C-0055} + ,Read={y} + ,File={} + } + +@InProceedings{LuntLargeAI88, +Author={T.F. Lunt and B.M. Thuraisingham}, +Title={Security for Large {AI} Systems}, +Booktitle={Proceedings of the AAAI-88 Workshop on Databases in Large AI Systems}, +month=aug, +Year=1988 } + +@InProceedings{LuntMSQL88, +Author={T.F. Lunt and R.R. Schell and W.R. Shockley and M. Heckman and D. Warren}, +Title={Toward a Multilevel Relational Data Language}, +Booktitle={Proceedings of the Fourth Aerospace Computer Security Applications + Conference, Orlando FL}, +month=dec, +Year=1988 } + + +@InProceedings{LuntInfer89, +Author={T.F. Lunt}, +Title={Aggregation and Inference: Facts and Fallacies}, +Booktitle={Proceedings of the 1989 IEEE Symposium on Research in Security and + Privacy}, +month=may, +Year=1989 } + +@InProceedings{MaimoneGreenberg90, +Author={W.T. Maimone and I.B. Greenberg}, +Title={Single-Level Multiversion Schedulers for Multilevel Secure + Database Systems}, +Booktitle={Proceedings of the Sixth Annual Computer Security Applications + Conference}, +Month=dec, +Year=1990 } + +@InProceedings{McHugh85, +Author={J. McHugh}, +Title={An {EMACS}-Based Downgrader for {SAT}}, +Booktitle={Proceedings of the Eighth National Computer Security Conference}, +month=oct, +Year=1985 } + +@InProceedings{McLean87, +Author={J. McLean}, +Title={Reasoning about Security Models}, +Booktitle={Proceedings of the 1987 IEEE Symposium on Security and + Privacy}, +month=apr, +Year=1987 } + +@InProceedings{Maier86, +Author={D. Maier and J. Stein and A. Otis and A. Purdy}, +Title={Development of an Object-Oriented {DBMS}}, +Booktitle={OOPSLA 86 Proceedings}, +Year=1986 } + +@InProceedings{Matloff86, +Author={N.S. Matloff}, +Title={Another look at the use of noise addition for database security}, +Booktitle={Proceedings of the IEEE 1986 Symposium on Security and Privacy}, +month=apr, +Year=1986 } + +@InProceedings{MayerInterp88, +Author={F.L. Mayer}, +Title={An Interpretation of a Refined {B}ell - {L}a {P}adula Model For the {TM}ach Kernel}, +Booktitle={Proceedings of the Fourth Aerospace Computer Security Applications Conference, Orlando FL}, +month=dec, +Year=1988 } + +@misc{Meadows88, +author={C. Meadows and C. Landwehr}, +title={Designing a Trusted Application Using an Object-Oriented Data Model}, +booktitle={Research Directions in Database Security}, +editor={T.F. Lunt}, +note={forthcoming} } + +@TechReport{Medlock88, +author={R.J. Medlock}, +Title="Secure Distributed Database Management System ({SD-DBMS}), Volume {II} (Draft): {SDI} {BM}/{C3} Application", +institution="Unisys +System Development Group", +month=sep, +Year=1988 } + +@Article{AW1, +Author={J.T. Merrifield}, +Title={{AI} System for Satellite Repair}, +Journal={Aviation Week}, +volume={CXXIV(19)}, +pages={89+}, +month={May 12}, +year=1986 } + +@Article{AW2, +Author={J.T. Merrifield}, +Title={Ames Readies Initial {AI} Demonstration for Space Station}, +Journal={Aviation Week}, +volume={CXXIV(21)}, +pages={129+}, +month={May 26}, +year=1986 } + +@Article{AW3, +Author={J.T. Merrifield}, +Title={{AI} Research at Ames Focuses on Increased Crew Effectiveness}, +Journal={Aviation Week}, +volume={CXXIV(22)}, +pages={73-75}, +month={June 2}, +year=1986 } + +@Article{AW4, +Author={J.T. Merrifield}, +Title={Ames Seeks {AI} Applications in Aeronautics, Space Programs}, +Journal={Aviation Week}, +volume={CXXIV(23)}, +pages={153+}, +month={June 9}, +year=1986 } + +@InProceedings{MOHAN84, +Author={C. Mohan}, +Title={Recent and Future Trends in Distributed Database Management}, +Booktitle={Proceedings of the NYU Symposium on New Directions in Database + Systems}, +Year=1984 } + +@InProceedings{Morgenstern84, +Author={M. Morgenstern}, +Title={Constraint equations: declarative expression of constraints with + automatic enforcement}, +Booktitle={Proceedings of the 10th International Conference on Very Large Databases}, +month=aug, +Year=1984 } + +@InProceedings{Morgenstern86, +Author={M. Morgenstern}, +title={The role of constraints in databases, expert systems, and knowledge + representation}, +Booktitle={Expert Database Systems, Proceedings of the +First International Workshop on Expert Database Systems}, +editor={L. Kerschberg}, +publisher={Benjamin Cummings Publishers}, +year=1986 } + +@InProceedings{Morgenstern87, +Author={M. Morgenstern}, +Title={Security and Inference in Multilevel Database and Knowledge-Base Systems}, +Booktitle={Proceedings of the ACM International Conference on Management of + Data (SIGMOD-87)}, +month=may, +Year=1987 } + +@InProceedings{Morgenstern88, +Author={M. Morgenstern}, +Title={Controlling Logical Inference in Multilevel Database Systems}, +Booktitle={Proceedings of the 1988 IEEE Symposium on Security and Privacy}, +month=apr, +Year=1988 } + +@InProceedings{Murray88, +Author={W.H. Murray}, +Title={Data Integrity in a Business Data Processing System}, +Booktitle={Report of the Invitational Workshop on Integrity Policy in Computer Information Systems (Appendix 6)}, +month=oct, +Year=1987 } + +@TechReport{Neumann80, +author={P. G. Neumann and R.S. Boyer and R.J. Feiertag and K.N. Levitt and L. Robinson}, +Title="A {Provably Secure Operating System}: The System, Its Applications, and Proofs", +institution="Computer Science Laboratory, SRI International", +number={CSL-116, Second edition}, +address={Menlo Park, California}, +month=may, +Year=1980 } + +@TechReport{Neumann85, +author={P.G. Neumann}, +Title="Audit Trail Analysis and Usage Data Collection and Processing, Part One", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, +month=jan, +Year=1985 } + +@TechReport{Neumann87, +author={P.G. Neumann and F. Ostapik}, +Title="Audit Trail Analysis and Usage Data Collection and Processing, Part Two", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, +month=may, +Year=1987 } + +@Article{Nguyen87, +Author={T. Nguyen and W. Perkins and T.J. Laffey and D. Pecora}, +Title={Knowledge Base Verification}, +Journal={AI Magazine}, +volume=8, +number=2, +year=1987 } + +@TechReport{OConnor88, +author={J.P. O'Connor and J.W. Gray and C. Jensen and D.T. Westby-Gibson}, +Title="Secure Distributed Database Management System ({SD-DBMS}), +Volume {I}: Architecture Definition, Tradeoff Analysis", +institution="Unisys +System Development Group", +month=aug, +Year=1988 } + +@TechReport{Olsson75, +author={L. Olsson}, +Title="Protection of Output and Stored Data in Statistical Databases", +institution="Statistika Centralbyran", +type={Technical Report~ADB-Information, 4}, +address={Stockholm, Sweden}, +Year=1975 } + +@InProceedings{Omar83, +Author={K.A. Omar and D.L. Wells}, +Title={Modified architecture for the subkeys model}, +Booktitle={Proceedings of the 1983 IEEE Symposium on Security and Privacy}, +month=apr, +Year=1983 } + +@InProceedings{Ozsoyoglu81, +Author={G. Ozsoyoglu and M. Ozsoyoglu}, +Title={Update handling techniques in statistical databases}, +Booktitle={Proceedings of the First LBL Workshop on Statistical Database Management}, +address={Lawrence Berkeley Lab, Berkeley, California}, +month=dec, +Year=1981 } + +@Article{S7, +Author={G.M. Powell and G. Loberg and H.H. Black and M.L. Gronberg}, +Title={{ARES}: Artificial Intelligence Research Project}, +Journal={Signal}, +volume={XL(10)}, +pages={106-109}, +month=jun, +year=1986 } + +@InProceedings{Rabitti88, +Author={F. Rabitti and D. Woeld and W. Kim}, +Title={A Model of Authorization for Object-Oriented and Semantic Databases}, +Booktitle={Proceedings of the International Conference on Extending Database +Technology}, +Year=1988 } + +@TechReport{Rapaport75, +author={E. Rapaport and B. Sundgren}, +Title="Output Protection in Statistical Databases", +institution="Nat. Central Bur. Stat.", +type={Technical Report~S/SYS-E04}, +address={Stockholm, Sweden}, +Year=1975 } + +@Article{RA86, +Author={R.F. Rashid}, +Title={Threads of a New System}, +Journal={UNIX Review}, +volume={4}, +number={8}, +month=aug, +year=1986 } + +@InProceedings{Reiss80, +Author={S.P. Reiss}, +Title={Practical data-swapping: the first steps}, +Booktitle={Proceedings of the 1980 IEEE Symposium on Security and Privacy}, +month=apr, +Year=1980 } + +@Article{S6, +Author={J.P. Retelle, Jr. and M. Kaul}, +Title={The Pilot's Associate -- Aerospace Application of Artificial Intelligence}, +Journal={Signal}, +volume={XL(10)}, +pages={100-105}, +month=jun, +year=1986 } + +@Book{RichBook, +author={E. Rich}, +Title={Artificial Intelligence}, +publisher={McGraw Hill, New York}, +year=1982 } + +@TechReport{HDM1, +author={L. Robinson}, +Title="{HDM} Handbook, Vol. 1: The Foundations of {HDM}", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, +month=jun, +Year=1979 } + +@Article{Rosenkrantz84, +Author={D.J. Rosenkrantz and R.E. Stearns and P.M. Lewis}, +Title={Consistency and Serializability in Concurrent Database Systems}, +Journal={SIAM Journal on Computing}, +volume=13, +number=2, +month=aug, +year=1984 } + +@InProceedings{Sybase87, +Author={P.A. Rougeau and E.D. Sturms}, +Title={ Sybase Secure Dataserver: A Solution to the Multilevel Secure DBMS Problem}, +Booktitle={Proceedings of the 10th National Computer Security Conference}, +month=sep, +Year=1987 } + +@InProceedings{Rowe87, +author={L.A. Rowe}, +title={A Shared Object Hierarchy}, +booktitle={The POSTGRES Papers, Memorandum No. UCB/ERL M86/85}, +editor={M. Stonebraker and L.A. Rowe}, +publisher={Electronics Research Laboratory, College of Engineering, University +of California, Berkeley}, +year=1987 } + +@misc{Rowe86, +Author={N.C. Rowe}, +title={Security problems with inferences from the results of rule-based + expert systems}, +note={unpublished paper} } + +@TechReport{Rushby88, +author={J.M. Rushby}, +Title="Quality Measures and Assurance for AI Software", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, +Year=1988 } + +@Article{SARIN85, +Author={S.K. Sarin and B. Blaustein and C. Kaufman}, +Title={System Architecture for Partition-Tolerant Distributed Databases}, +Journal={IEEE Transactions on Computers}, +volume={C-34}, +number=122, +month=dec, +year=1985 } + +@InProceedings{SARIN86b, +Author={S.K. Sarin}, +Title={Robust Application Design in Highly Available Distributed Databases}, +Booktitle={Proceedings of the Fifth IEEE Symposium on Reliability in Distributed + Software and Database Systems}, +month=jan, +Year=1986 } + +@InProceedings{SARIN86a, +Author={S.K. Sarin and C. Kaufman and J.E. Somers}, +Title={Using History Information To Process Delayed Database Updates}, +Booktitle={Proceedings of the Twelfth International Conference on + Very Large Data Bases}, +month=aug, +Year=1986 } + +@InProceedings{SchaeferSchell84, +Author={M. Schaefer and R.R. Schell}, +Title={Toward an Understanding of Extensible Architectures for + Evaluated Trusted Computer System Products}, +Booktitle={Proceedings of the 1984 IEEE Symposium on Security and Privacy}, +month=apr, +Year=1984 } + +@InProceedings{Schell85, +Author={R.R. Schell and T.F. Tao and M. Heckman}, +Title={Designing the {GEMSOS} Security Kernel for Security and Performance}, +Booktitle={Proceedings of the Eighth National Computer Security Conference}, +Year=1985 } + +@InProceedings{SchellIntegrity86, +Author={R.R. Schell and D.E. Denning}, +Title={Integrity in Trusted Database Systems}, +Booktitle={Proceedings of the Ninth National Computer Security Conference}, +Year=1986, Month =sep } + +@Article{Schlorer76, +Author={J. Schlorer}, +Title={Confidentiality of statistical records: a threat monitoring scheme + for on line dialogue}, +Journal={Methods Inf. Med.}, +volume=15, +number=1, +year=1976 } + +@Article{SchlorerQuantitative80, +Author={J. Schlorer}, +Title={Disclosure from statistical databases: quantitative aspects of + trackers}, +Journal={ACM Transactions on Database Systems}, +volume=5, +number=4, +month=dec, +year=1980 } + +@TechReport{SchlorerLoss83, +author={J. Schlorer}, +Title="Information Loss in Partitioned Statistical Databases", +type={Technical Report, Klinische Dokumentation}, +institution="Universit{\"a}t Ulm", +address={Ulm, Germany}, +Year=1983 } + +@TechReport{SchlorerOutput82, +author={J. Schlorer}, +Title="Query Based Output Perturbations to Protect Statistical + Databases", +type={Technical Report, Klinische Dokumentation}, +institution="Universit{\"a}t Ulm", +address={Ulm, Germany}, +month=oct, +Year=1982 } + +@Article{SchlorerMultidimensional81, +Author={J. Schlorer}, +Title={Security of statistical databases: multidimensional transformation}, +Journal={ACM Transactions on Database Systems}, +volume=6, +number=1, +month=mar, +year=1981 } + +@TechReport{Schroeder72, +author={M.D. Schroeder}, +Title="Cooperation of Mutually Suspicious Subsystems in a Computer Utility", +institution="Ph.D. Thesis, M.I.T., Cambridge, Massachusetts", +month=sep, +Year=1972 } + +@article{SchroederSaltzer72, +author={M.D. Schroeder and J.H. Saltzer}, title = {A Hardware +Architecture for Implementing Protection Rings}, +journal = {Communications of the ACM}, volume = {15}, number = {3}, +pages = {}, month = mar, year = {1972}} + +@article{SaltzerSchroeder75, + title = {The Protection of Information in Computer Systems}, + author = {Saltzer, Jerome H. and Schroeder, Michael D.}, + date = {1975-09}, + journaltitle = {Proceedings of the IEEE}, + volume = {63}, + pages = {1278--1308}, + doi = {10.1109/PROC.1975.9939}, + url = {http://cap-lore.com/CapTheory/ProtInf/}, + number = {9} +} + +@book{SaltzerKaashoek09, +Author={J.H. Saltzer and F. Kaashoek}, +Title={Principles of Computer System Design}, +Publisher={Morgan Kaufmann}, +Year={2009}, +NOTE = {Chapters 1-6 only. Chapters 7-11 are online:\\ + http://ocw.mit.edu/Saltzer-Kaashoek} +} + +@book{Organick, +Author={E.I. Organick}, +Title={The {Multics} System: An Examination of Its Structure}, +Publisher={MIT Press, Cambridge, Massachusetts}, +Year={1972} } + +@InProceedings{Schroeder77, +Author={M.D. Schroeder and D.D. Clark and J.H. Saltzer}, +Title={The {Multics} Kernel Design Project}, +Booktitle={Proceedings of the Sixth Symposium on Operating System Principles}, +Note={ACM Operating Systems Review 11(5)}, +month=nov, Year=1977 } + +@article{NeedhamSchroeder78, +author={R.M. Needham and M.D. Schroeder}, key={needham}, title = {Using +Encryption for Authentication and Authorization Systems}, +journal = {Communications of the ACM}, volume = {21}, number = {12}, +pages = {993-999}, month = dec, year = {1978}} + +@article{NeedhamSchroeder87, +author={R.M. Needham and M.D. Schroeder}, key={needham}, title = +{Authentication Revisited}, +journal = {Operating Systems Review}, volume = {21}, number = {1}, +pages = {7}, month = {}, year = {1987}} + +@article{OtwayRees87, +author={D. Otway and O. Rees}, title = {Efficient and Timely Mutual +Authentication}, +journal = {Operating Systems Review}, volume = {21}, number = {1}, +pages = {8--10}, month = {}, year = {1987}} + +@ARTICLE{SchroederGrape, +Author={M.D. Schroeder and A.D. Birrell and R.M. Needham}, +TITLE = {Experience with {Grapevine}: The Growth of a Distributed System}, +JOURNAL = {TOCS}, YEAR = {1984}, VOLUME = {2}, +NUMBER = {1}, PAGES = {3-23}, MONTH = feb } + +@article{DiffieHellman76, +author={W. Diffie and M.E. Hellman}, key={Diffie}, title = {New Directions +in Cryptography}, journal = {IEEE Transactions on Information Theory}, volume= {22}, +number = {5}, pages = {}, month = nov, year = {1976}} + +@article{Rivest+78, +author={R. Rivest and A. Shamir and L. Adleman}, key={Rivest}, +title = {A Method for Obtaining Digital Signatures and Public-Key +Cryptosystems}, journal = {Communications of the ACM}, volume = {21}, number = {2}, +pages = {120-126}, month = feb, year = {1978}} + +@TechReport{Rivest90, +author={R. Rivest}, +Title={The {MD4} message digest algorithm}, +institution={MIT Laboratory for Computer Science}, +address={}, month =oct, note={TM 434}, +Year= {1990} } + +@TechReport{RivestLampson96, +author={R. Rivest and B. Lampson}, +Title={{SDSI} -- A Simple Distributed Security Infrastructure}, +institution={MIT Laboratory for Computer Science}, +address={}, month ={}, note={Version 2.0 is +available online +(\xlink{http://theory.lcs.mit.edu/\~{}cis/sdsi.html}{http://theory.lcs.mit.edu/\~{}cis/sdsi.html}) +along with other documentation and source code}, +Year= {2000} } + +@TechReport{Ellison+99, +author={C.M. {Ellison et al.}}, +Title={{SPKI} Certificate Theory}, +institution={Internet Engineering Task Force}, +address={}, month =sep, +Year= {1999}, Note={\xlink{http://www.ietf.org/rfc/rfc2693.txt}{http://www.ietf.org/rfc/rfc2693.txt}) +}} + +@InProceedings{Abadi97, +Author={M. Abadi}, +Title={On {SDSI's} Linked Local Name Spaces}, +BookTitle={Proceedings of the 10th IEEE Computer Security Foundations + Workshop}, Address={Rockport, Massachusetts}, +Year={1997},Month=jun,Pages={98--108} } + +@TechReport{DES, +Author={NIST}, Institution={National Institute of Standards and Technology +(formerly NBS)}, Title={Data Encryption Standard}, Year={1977} } + +@InProceedings{ElGamal84, +Author = {T. ElGamal}, +Title = {A public key cryptosystem and a signature scheme +based on discrete logarithms}, +Booktitle = {Advances in Cryptology: Proceedings of CRYPTO '84}, +Organization = {G.R. Blakley and David Chaum, eds., Springer-Verlag, Berlin}, +Year = {1985}, Pages={10--18}, Month = {} } + +@article{ElGamal85, +author={T. ElGamal}, title = {A public key cryptosystem and a signature scheme +based on discrete logarithms}, journal = {IEEE Transactions on Information Theory}, +volume = {31}, number = {}, pages = {469--472}, month = {}, year = {1985}} + +@InProceedings{Schnorr89, +Author = {C.P. Schnorr}, +Title = {Efficient identification and signatures for smart cards}, +Booktitle = {Advances in Cryptology: Proceedings of CRYPTO '89}, +Organization = {G. Brassard, ed., Springer-Verlag, Berlin, LCNS 435}, +Year = {1990}, Pages={239-251}, Month = {} } + +@InProceedings{LaMacchiaOdlyzko91, +Author={B.A. LaMacchia and A.M. Odlyzko}, +Title={Computation of Discrete Logarithms in Prime Fields}, +Booktitle={Designs, Codes, and Cryptography 1}, pages={47-62}, +Year=1991, Publisher={Kluwer} } + +@ARTICLE{Kaliski+88, +Author={B.S. {Kaliski Jr.} and R.L. Rivest and A.T. Sherman}, +TITLE = {Is the {Data} {Encryption} {Standard} a Group? +(Results of Cycling Experiments on {DES})}, +JOURNAL = {Journal of Cryptology}, YEAR = {1988}, VOLUME = {1}, +NUMBER = {1}, PAGES = {3--36}, MONTH = {} } + +@InProceedings{Kaliski94, +Author={B.S. {Kaliski Jr.}}, +TITLE = {Public-Key Cryptography in Smart Cards}, +Booktitle = {CardTech/SecurTech '94}, YEAR = {1994}, +MONTH = {10--13 April}, +Organization = {}, Address = {Arlington, Virginia} } + +@ARTICLE{Merkle90, +Author={R.C. Merkle}, TITLE = {A fast software one-way hash function}, +JOURNAL = {Journal of Cryptology}, YEAR = {1990}, VOLUME = {3}, +NUMBER = {1}, PAGES = {43--58}, MONTH = {} } + +@ARTICLE{Schnorr91, +Author={C.P. Schnorr}, TITLE = {Efficient signature generation by smart cards}, +JOURNAL = {Journal of Cryptology}, YEAR = {1991}, VOLUME = {4}, +NUMBER = {3}, PAGES = {161--174}, MONTH = {} } + +@InProceedings{CampbellWiener92, +Author = {K.W. Campbell and M.J. Wiener}, +Title = {{DES} is not a Group}, +Booktitle = {Advances in Cryptology: Proceedings of CRYPTO '92 (E.F. Brickell, +editor)}, Organization = {Springer-Verlag, Berlin, LCNS 740}, +Year = {1992}, Pages={512-517}, Month = {} } + +@InProceedings{Micali92, +Author={S. Micali}, TITLE = {Fair Public-Key Cryptosystems}, +Booktitle = {Advances in Cryptology: Proceedings of CRYPTO '92 (E.F. Brickell, +editor)}, Organization = {Springer-Verlag, Berlin, LCNS 740}, +Year = {1992}, Pages={512-517}, Month = {} } + +@InProceedings{Blundo+94, +Author={C. Blundo and A. {De Santis} and G. {Di Crescenzo} and +A.G. Gaggia and U. Vaccaro}, +TITLE = {Multi-Secret Sharing Schemes}, +Booktitle = {Advances in Cryptology: Proceedings of CRYPTO '94 (Y.G. Desmedt, +editor)}, Organization = {Springer-Verlag, Berlin, LCNS 839}, +Year = {1994}, Pages={150--163}, Month = {} } + +@book{Schneier94, +Author={B. Schneier}, +Title={Applied Cryptography}, +Publisher={John Wiley and Sons, New York}, +Year={1994} } + +@book{Schneier96, +Author={B. Schneier}, +Title={Applied Cryptography: Protocols, Algorithms, and Source Code in C: + Second Edition}, +Publisher={John Wiley and Sons, New York}, +Year={1996} } + +@book{Schneier00, +Author={B. Schneier}, +Title={Secrets and Lies: Digital Security in a Networked World}, +Publisher={John Wiley and Sons, New York}, +Year={2000} } + +@book{Schneier95, +Author={B. Schneier}, +Title={E-Mail Security with {PGP} and {PEM}}, +Publisher={John Wiley and Sons, New York}, +Year={1995} } + +@book{Zimmermann95, +Author={P.R. Zimmermann}, +Title={The Official {PGP} User's Guide}, +Publisher={MIT Press, Cambridge, Massachusetts}, +Year={1995} } + +@article{Goldberg85, +author={A. Goldberg}, title = {Reliability of Computer Systems and +Risks to the Public}, journal = {Communications of the ACM}, year = {1985}, +volume = {28}, number = {2}, pages = {131-133}, month = feb } + +@ARTICLE{Bidzos91Risks, +Author={J. Bidzos}, TITLE = {Letter to {C}ongressman {T}im {V}alentine on +{NIST's} {DSS}}, JOURNAL = {RISKS FORUM +(comp.risks, online newsgroup)}, YEAR = {1991}, VOLUME = {12}, NUMBER = {37}, +PAGES = {}, MONTH = {20 September} } + +@ARTICLE{Bidzos91SENxxxxx, +Author={J. Bidzos}, TITLE = {Letter to {C}ongressman {T}im {V}alentine on +{NIST's} {DSS}}, +JOURNAL = {ACM Software Engineering Notes}, YEAR = {1991}, VOLUME = {16}, +NUMBER = {4}, PAGES = {}, MONTH = oct } + +@article{CommBib, +author={C. Partridge}, +title = {Bibliography of Recent Publications on Computer Communication}, +journal = {ACM SIGCOMM Computer Communication Review}, +year = {1991}, volume = {21}, number = {1}, pages = {132-145}, +month = jan } + +@article{ISOstatus, +author={L. Chapin}, title = {Status of {OSI} (and related) Standards}, +journal = {ACM SIGCOMM Computer Communication Review}, +year = {1991}, volume = {21}, number = {1}, pages = {111-131}, +month = jan } + +@TechReport{ISO7498-1, + Key={International}, Author={ISO}, Institution={International Standards + Organization}, Title={Open Systems Interconnection Architecture Basic + Reference Model}, Year={1984}, day={15}, month={October} } + +@TechReport{ISO7498-1C, + Key={International}, Author={ISO}, Institution={International Standards + Organization}, Title={Open Systems Interconnection Architecture Basic + Reference Model, Technical Corrigendum}, Year={1988}, day={15}, month=dec } + +@TechReport{ISO7498-2, + Key={International}, Author={ISO}, Institution={International Standards + Organization}, Title={Open Systems Interconnection Architecture Security + Architecture}, Year={1988}, day={19}, month={August} } + +@TechReport{ISO7498-3, + Key={International}, Author={ISO}, Institution={International Standards + Organization}, Title={Open Systems Interconnection Architecture Naming + and Addressing}, Year={1989}, day={1}, month={March} } + +@TechReport{ISO7498-4, + Key={International}, Author={ISO}, Institution={International Standards + Organization}, Title={Open Systems Interconnection Architecture + Management Framework}, Year={1989}, day={15}, month=nov } + +@TechReport{ISO7498-1Add1, + Key={International}, Author={ISO}, Institution={International Standards + Organization}, Title={Open Systems Interconnection Architecture, + Addendum 1: Connectionless Data}, Year={1987}, day={15}, month={August} } + +@TechReport{ISO7498-X, + Key={International}, Author={ISO}, Institution={International Standards + Organization}, Title={Open Systems Interconnection Architecture Basic + Reference Model}, Year={198}, Month={} } + +@InProceedings{Vissers90, +Key = {}, Author = {C.A. Vissers}, +Title = {Protocol specification: The first ten years, the next ten years}, +Booktitle = {Proceedings of the 10th International IFIP Symposium on Protocol Specification, +Testing, and Verification}, +Organization = {IFIP}, Address = {Ottawa, Canada}, +Year = {1990}, +Pages={}, Month = jun } + +@InProceedings{Miller90, +Key = {}, Author = {R.E. Miller}, +Title = {Protocol verification: The first ten years, the next ten years; +some personal observations}, +Booktitle = {Proceedings of the 10th International IFIP Symposium on Protocol Specification, +Testing, and Verification}, +Organization = {IFIP}, Address = {Ottawa, Canada}, +Year = {1990}, +Pages={}, Month = jun } + +@InProceedings{Sidhu90, +Key = {}, Author = {D. Sidhu}, +Title = {Protocol testing: The first ten years, the next ten years}, +Booktitle = {Proceedings of the 10th International IFIP Symposium on Protocol Specification, +Testing, and Verification}, +Organization = {IFIP}, Address = {Ottawa, Canada}, +Year = {1990}, +Pages={}, Month = jun } + +@article{Sidhu+91, +author={D. Sidhu and A. Chung and T.P. Blumer}, +title = {Experience with Formal Methods in Protocol Development}, +journal = {ACM SIGCOMM Computer Communication Review}, +year = {1991}, volume = {21}, number = {2}, pages = {81-101}, +month = apr } + +@ARTICLE{SidhuBlumer90, +Author={D. Sidhu and T.P. Blumer}, TITLE = {Semi-automatic implementation +of {OSI} protocols}, +JOURNAL = {Computer Networks \& ISDN System}, YEAR = {1990}, VOLUME = {18}, +NUMBER = {}, PAGES = {}, MONTH = {} } + +@TechReport{RFC1113, + Key={Kent}, Author={S. Kent}, Institution={Internet Activities Board Privacy + Task Force}, Month=aug, Year={1989}, + Title={Privacy Enhancement for {Internet} Electronic Mail: Part {I}. {RFC 1113}} } + +@TechReport{RFC1114, + Key={Kent}, Author={S. Kent and J. Linn}, + Institution={Internet Activities Board Privacy Task Force}, + Month=aug, Year={1989}, + Title={Privacy Enhancement for {Internet} Electronic Mail: Part {II}: + Certificate Based Key Management. {RFC 1114}} } + +@TechReport{RFC1115, + Key={Linn}, Author={J. Linn}, Institution={Internet Activities Board Privacy + Task Force}, Month=aug, Year={1989}, + Title={Privacy Enhancement for {Internet} Electronic Mail: Part {III}: + Algorithms, Models and Identifiers. {RFC 1115}} } + +@InProceedings{Linn90, +Key={Linn}, Author={J. Linn}, Title={Practical Authentication for +Distributed Computing}, BookTitle={Proceedings of the 1990 Symposium on Research in +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1990}, Month=may, pages={31--40}} + +@InProceedings{GongNeedhamYahalom90, +Author={L. Gong and R. Needham and R. Yahalom}, +Title={Reasoning about Belief in Cryptographic Protocols}, +BookTitle={Proceedings of the 1990 Symposium on Research in +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1990}, Month=may, pages={234-248}} + +@InProceedings{Yaholom+93, +Author={R. Yahalom and B. Klein and Th. Beth}, +Title={Trust Relationships in Secure Systems: A Distributed +Authentication Procedure}, +BookTitle={Proceedings of the 1993 Symposium on Research in +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1993}, Month=may, pages={150-164}} + +@Article{RavindranChanson89, +Key = {Ravindran}, Author = {K. Ravindran and S.T. Chanson}, +Title = {Failure Transparency in Remote Procedure Calls}, +Journal = {IEEE Transactions on Computers}, +Year = {1989}, volume ={32}, number = {8}, +Pages={1173-1187}, Month = aug } + +@Article{Birman85, +Key = {Birman}, Author = {K.P. Birman}, +Title = {Implementing Remote Procedure Calls}, +Journal = {ACM Transactions on Computer Systems}, +Year = {1985}, volume = {SE-11}, number = {6}, +Pages={502-8}, Month = jun } + +@InProceedings{PowellPresotto83, +Key = {Powell}, Author = {M.L. Powell and D.L. Presotto}, +Title = {{PUBLISHING}: A reliable broadcast communication mechanism}, +Booktitle = {Proceedings of the Ninth Symp. on Operating Systems Principles}, +Organization = {ACM SIGOPS}, Address = {}, +Year = {1983}, +Pages={100--109}, Month = jun } + +@Article{LiskovScheifler83, +Key = {Liskov}, Author = {B. Liskov and R. Scheifler}, +Title = {Guardians and Actions: Linguistic support for robust distributed programs}, +Journal = {ACM Transactions on Programming Language Systems}, +Year = {1983}, volume = {5}, Pages={381--404}, Month = jul } + +@article{Birrell85, +author={A.D. Birrell}, key={Birrell}, +title = {Secure Communication Using Remote Procedure Calls}, +journal = {ACM Transactions on Computer Systems}, +volume = {3}, number = {1}, pages = {1-14}, month = feb, year = {1985}} + +@TechReport{Kerberos87, + Key={Miller}, Author={S. Miller and B. Neuman and J. Schiller and +J. Saltzer}, + Institution={MIT Project Athena Technical Plan Section E.2.1}, + day={21}, month=dec, Year={1987}, + Title={Kerberos Authentication and Authorization System} } + +@Article{shamir79, +Author={A. Shamir},Journal={Communications of the ACM}, +Title={How to Share a Secret},Year={1979},Month=nov,Pages={612--613} +,Volume={22},Number={11} } + +@InProceedings{steiner88 + ,Author={J.G. Steiner and C. Neuman and J.I. Schiller} + ,BookTitle={Proceedings of the USENIX Winter Conference} + ,Title={Kerberos: An Authentication Service for Open Network Systems} + ,Year={1988},Month=feb,Pages={191--202} } + +@TechReport{Kohl+90, + Author={J. Kohl and B.C. Neuman and J. Steiner}, + Institution={MIT Project Athena}, + day={8}, month={October}, Year={1990}, + Title={The {Kerberos} Network Authentication Service (Version 5, draft 3) } } + +@TechReport{DavisSwick90, + Key={Davis}, Author={D. Davis and R. Swick}, + Institution={MIT Laboratory for Computer Science Tech. Mem. 424}, + Month=feb, Year={1990}, + Title={Workstation Services and {Kerberos} Authentication at {P}roject {A}thena} } + +@InProceedings{BellovinMerritt91, +author={S.M. Bellovin and M. Merritt}, +title = {Limitations of the {Kerberos} Authentication System}, +booktitle = {{USENIX} Conference Proceedings, Winter '91}, +volume = {}, number = {}, pages = {}, month = jan, year = {1991}, +note = {A version of this paper + appeared in {\it Computer Communications Review,} October 1990} } + +@article{Gong89, +author={L. Gong}, key={gong}, title = {Using One-Way Functions +for Authentication}, journal = {ACM Communications Review}, volume = {19}, +number = {5}, pages = {8-11}, month = oct, year = {1989}} + +@InProceedings{KailarGligor91, +author={R. Kailar and V.D. Gligor}, +Title={On the Evolution of Beliefs in Authentication Protocols}, +BookTitle={Proceedings of the IEEE Computer Security Foundations Workshop IV}, +Address={Franconia, New Hampshire}, +Year={1991}, Month=jun } + +@InProceedings{Gligor+91 + ,Author={V.D. Gligor and R. Kailar and S. Stubblebine and L. Gong} + ,BookTitle={Proceedings of the 4th IEEE Computer Security Foundations Workshop} + ,Address={Franconia, New Hampshire} + ,Title={Logics for Cryptographic Protocols -- Virtues and Limitations} + ,Year={1991} + ,Month=jun + ,Pages={219--226} + } + +@InProceedings{Millen94hookup, +author={J.K. Millen}, +Title={Hookup security for synchronous machines}, +BookTitle={Proceedings of the IEEE Computer Security Foundations Workshop VII}, +Organization = {IEEE Computer Society}, +Address={Franconia, New Hampshire}, pages = {2-10}, +Year={1994}, Month=jun } + +@InProceedings{StubblebineGligor92, +Author={S.G. Stubblebine and V.D. Gligor}, +Title={On Message Integrity in Cryptographic Protocols}, +BookTitle ={Proceedings of the 1992 Symposium on Research in Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1992}, Month=may, pages={85--104} } + +@InProceedings{ReiterBirmanGong92, +Author={M. Reiter and K. Birman and L. Gong}, +Title={Integrating Security in a Group Oriented Distributed System}, +BookTitle ={Proceedings of the 1992 Symposium on Research in Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1992}, Month=may, pages={18--32} } + +@ARTICLE{Gong93, +Author={L. Gong and T.M.A. Lomas and R.M. Needham and J.H. Saltzer}, +TITLE = {Protecting poorly chosen secrets from guessing attacks}, +JOURNAL = {IEEE Journal of Selected Areas in Communications}, +YEAR = {1993}, VOLUME = {11}, NUMBER = {5}, PAGES = {648-656}, MONTH = jun } + +@TechReport{Berson+93, +Author={T. Berson and L. Gong and T.M.A. Lomas}, +TITLE = {Secure, Keyed, and Collisionful Hash Functions}, +Institution = {SRI International, included in SRI-CSL-94-08}, +YEAR = {1993} } + +@Article{ReiterBirman94, +Author={M. Reiter and K. Birman}, +Journal={ACM Transactions on Programming Languages and Systems}, +Title={How to Securely Replicate Services}, +Year={1994},Month=may,Pages={986--1009},Volume={16},Number={3} } + +@Article{Neuman+94, +Author={B.C. Neuman and T. Ts'o}, Journal={IEEE Communications}, +Title={Kerberos: An Authentication Service for Computer Networks}, +Year={1994},Month=sep,Pages={33--38},Volume={32},Number={9} } + +@InProceedings{DesmedtFrankelYung92, +Author={Y. Desmedt and Y. Frankel and M. Yung}, +Title={Multi-receiver/multi-sender network security: Efficient +authenticated multicast/feedback}, +BookTitle={Proceedings of IEEE INFOCOM}, Organization={IEEE}, +Address={}, Year={1992}, Month={}, pages={}} + +@InProceedings{Kailar+94, +Author={R. Kailar and V.D. Gligor and L. Gong}, +Title={On the Security Effectiveness of Cryptographic Protocols}, +BookTitle ={Proceedings of the 1994 Conference on Dependable Computing for +Critical Applications}, +Organization={}, Address={San Diego, California}, +Year={1994}, Month=jan, pages={90--101} } + +@misc{ShockleyWorkshop88, +author={W.R. Shockley}, +title={Fundamental Limitations on View-Based Access Controls}, +booktitle={Research Directions in Database Security}, +editor={T.F. Lunt}, +note={to appear} } + +@TechReport{ShockleySpec89, +author={W.R. Shockley and R.R. Schell and T.F. Lunt and D. Warren and +M. Heckman}, Title="Final Report Vol.\ 5: The {S}ea{V}iew Implementation +Specifications (draft)", institution="Gemini Computers", Year=1989 } + +@InProceedings{Shirley81, +Author={L.J. Shirley and R.R. Schell}, +Title={Mechanism Sufficiency Validation by Assignment}, +Booktitle={Proceedings of the 1981 IEEE Symposium on Security and Privacy}, +month=apr, Year=1981 } + +@MastersThesis{Shirley81T, + Key={Shirley}, Author={L.J. Shirley}, + Title={Non-Discretionary Security Validation by Assignment}, Year={1981}, + School={Department of Computer Science, + Naval Postgraduate School, Monterey, California}, Month=jun } + +@misc{S1, +Title={Artificial Intelligence for {B}1-{B}}, +Journal={Signal}, +volume={XL(10)}, +pages=130, +month=jun, +year=1986 } + +@Article{S2, +Author={R.P. Shumaker and J. Franklin}, +Title={Artificial Intelligence in Military Applications}, +Journal={Signal}, +volume={XL(10)}, +pages={29+}, +month=jun, +year=1986 } + +@InProceedings{Smaha88, +Author={S.E. Smaha}, +Title={Haystack: An Intrusion Detection System}, +Booktitle={Proceedings of the Fourth Aerospace Computer Security Applications + Conference, Orlando FL}, +month=dec, +Year=1988 } + +@InProceedings{Smith88, +Author={G.W. Smith}, +Title={Identifying and Representing the Security Semantics of an Application}, +Booktitle={Proceedings of the Fourth Aerospace Computer Security Applications + Conference, Orlando FL}, +month=dec, +Year=1988 } + +@Article{Stefik86, +author={M. Stefik and D.G. Bobrow}, +title={Object-Oriented Programming: Themes and Variations}, +Journal={The AI Magazine}, +month={Winter}, +year=1986 } + +@Article{Stefik82, +Author={M. Stefik and J. Aikens and R. Balzer and J. Benoit and L. Birnbaum and F. Hayes-Roth and E.D. Sacerdoti}, +Title={The Organization of Expert Systems}, +Journal={Artificial Intelligence}, +volume=18, +pages={29+}, +year=1982 } + +@InProceedings{Stonebraker87, +author={M. Stonebraker and L.A. Rowe}, +title={The Design of {POSTGRES}}, +booktitle={The POSTGRES Papers, M86/85}, +editor={M. Stonebraker and L.A. Rowe}, +publisher={Electronics Research Laboratory, College of Engineering, University +of California, Berkeley}, +year=1987 } + +@InProceedings{Stonebraker74, +Author={M. Stonebraker and E. Wong}, +Title={Access Control in a Relational Data Base Management System by Query + Modification}, +Booktitle={Proceedings of the 1974 ACM Annual Conference}, +Year=1974 } + +@InProceedings{SuOz87, +Author={T. Su and G. Ozsoyoglu}, +Title={Data Dependencies and Inference Control in Multilevel Relational Database +Systems}, +Booktitle={Proceedings of the 1987 IEEE Symposium on Security and Privacy}, +month=apr, +Year=1987 } + +@Article{Suwa82, +Author={M. Suwa and A. Carlisle Scott and E.H. Shortliffe}, +Title={An Approach to Verifying Completeness and Consistency in a Rule-Based Expert +System}, +Journal={AI Magazine}, +volume=3, +number=4, +year=1982 } + +@Article{S8, +Author={A.J. Tachmindji and E.L. Lafferty}, +Title={Artificial Intelligence for Air Force Tactical Planning}, +Journal={Signal}, +volume={XL(10)}, +pages={110-114}, +month=jun, +year=1986 } + +@InProceedings{Tener86, +Author={W.T. Tener}, +Title={Discovery: An Expert System in the Commercial Data Security Environment}, +Booktitle={Proceedings of the IFIP Security Conference}, +address={Monte Carlo}, +Year=1986 } + +@Article{Thuraisingham87, +Author={M.B. Thuraisingham}, +Title={Security Checking in Relational Database Management Systems Augmented + with Inference Engines}, +Journal={Computers and Security}, +volume=6, +number=6, +year=1987 } + +@InProceedings{Thuraisingham88, +Author={T.F. Keefe and W.T. Tsai and M.B. Thuraisingham}, +Title={A Multilevel Security Model for Object-Oriented Systems}, +Booktitle={Proceedings of the Eleventh National Computer Security Conference}, +month=oct, +Year=1988 } + +@InProceedings{Keef90b, +Author={T.F. Keefe and W.T. Tsai}, +BookTitle={Proceedings of the 1990 Symposium on Research in Security and Privacy}, +Address={Oakland, California}, +Title={Multiversion Concurrency Control for Multilevel Secure Database Systems}, +Organization={IEEE Computer Society}, +Year={1990},Month=may,Pages={369-383} } + +@Article{VaradharajanBlack91, +Author={V. Varadharajan and S. Black}, +Title={Multilevel Security in a Distributed Object-Oriented System}, +Journal={Computers and Security}, +volume=10, number=1, year=1991, pages={51-68} } + +@Article{Traub84, +Author={J.F. Traub and H. Wozniakowski and Y. Yemini}, +Title={Statistical security of a statistical data base}, +Journal={ACM Transactions on Database Systems}, +volume=9, +number=4, +month=dec, +year=1984 } + +@Article{Trueblood83, +Author={R.P. Trueblood and H.R. Hartson and J.J. Martin}, +Title={{MULTISAFE}: {A} modular multiprocessing approach to secure database + management}, +Journal={ACM Transactions on Database Systems}, +volume=8, +number=3, +month=sep, +year=1983 } + +@TechReport{TRW86, +author={TRW Defense Systems Group}, +Title="Intrusion-Detection Expert System Feasiblity Study", +type={Final Report}, +institution="TRW", +number={46761}, +Year=1986 } + +@Book{Ullman88, +Author={J.D. Ullman}, +Title={Principles of Database and Knowledge-Base Systems}, +volume={1}, +publisher={Computer Science Press}, +address={Rockville, Maryland}, +year=1988 } + +@Book{Ullman82, +Author={J.D. Ullman}, +Title={Principles of Database Systems}, +publisher={Computer Science Press}, +address={Rockville, Maryland}, +year=1982 } + +@inproceedings{VaccaroLiepins89, +author={H.S. Vaccaro and G.E. Liepins}, +title={Detection of Anomalous Computer Session Activity}, +Booktitle={Proceedings of the 1989 IEEE Symposium on Research in Security and Privacy}, +pages={280-289}, month=may, Year=1989 } + +@TechReport{VanHorneSytek5, +author={J. van Horne and L.Halme}, +Title="Analysis of Computer System Audit Trails: Training and Experimentation + with Classifier", +institution="Sytek", +address={Mountain View, California}, +number={TR-85006}, +month=mar, +Year=1986 } + +@TechReport{VanHorneSytek6, +author={J. van Horne and L. Halme}, +Title="Analysis of Computer System Audit Trails: Final Report", +institution="Sytek", +address={Mountain View, California}, +number={TR-85007}, +month=may, +Year=1986 } + +@InProceedings{Vinter88, +author={S.T. Vinter}, +title={Extended Discretionary Access Controls}, +booktitle={Proceedings of the 1988 IEEE Symposium on Security and Privacy}, +month=apr, +year=1988 } + +@InProceedings{Watson81, +Author={R.W. Watson}, +title={Distributed Systems Architecture Model}, +Booktitle={Distributed Systems -- Architecture and Implementation: An +Advanced Course, volume 105 of Lecture Notes in Computer Science, +B.W. Lampson (ed.)}, +publisher={Springer-Verlag, Berlin}, pages={10-43}, Year=1981 } + +@inproceedings{Watson10, + title = {Capsicum: {{Practical Capabilities}} for {{UNIX}}}, + shorttitle = {Capsicum}, + booktitle = {Proceedings of the 19th {{USENIX Conference}} on {{Security}}}, + author = {Watson, Robert N. M. and Anderson, Jonathan and Laurie, Ben and Kennaway, Kris}, + date = {2010-08-11}, + publisher = {{USENIX Association}}, + location = {{Berkeley, CA, USA}}, + url = {https://www.cl.cam.ac.uk/research/security/capsicum/papers/2010usenix-security-capsicum-website.pdf}, + abstract = {Capsicum is a lightweight operating system capability and sandbox framework planned for inclusion in FreeBSD 9. Capsicum extends, rather than replaces, UNIX APIs, providing new kernel primitives (sandboxed capability mode and capabilities) and a userspace sandbox API. These tools support compartmentalisation of monolithic UNIX applications into logical applications, an increasingly common goal supported poorly by discretionary and mandatory access control. We demonstrate our approach by adapting core FreeBSD utilities and Google's Chromium web browser to use Capsicum primitives, and compare the complexity and robustness of Capsicum with other sandboxing techniques.}, + series = {{{USENIX Security}}'10} +} + + + +@TechReport{Watson10a, +author={Robert N.~M. Watson}, +Title="{New Approaches to Operating System Security Extensibility}", +institution="Ph.D. Thesis, University of Cambridge, Cambridge, UK", +month=oct, +Year=2010 +} + +@TechReport{UCAM-CL-TR-818, + author = {Watson, Robert N. M.}, + title = {{New approaches to operating system security extensibility}}, + year = 2012, + month = apr, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-818.pdf}, + institution = {University of Cambridge, Computer Laboratory}, + number = {UCAM-CL-TR-818} +} + +@Book{Lampson81, +Author={B.W. {Lampson (ed.)}}, +Title={Distributed Systems -- Architecture and Implementation: An +Advanced Course}, +publisher={Springer-Verlag, Berlin, +Lecture Notes in Computer Science, Vol. 105}, +Year=1981 } + +@InProceedings{Lampson03, +author = {B.W. Lampson}, +Title = {Software Components: Only The Giants Survive}, +Booktitle = {Computer Systems: papers for Roger Needham, K. Spark-Jones and A. Herbert (editors)}, +publisher = {Microsoft Research, Cambridge, U.K.}, +month = feb, +year = {2003}, +pages = {113-120} } + +@book{McKBKQ96, +Author = {M.K. McKusick and K. Bostic and M.J. Karels and J.S. Quarterman}, +Title = {The Design and Implementation of the 4.4~BSD Operating System}, +Publisher = {Addison-Wesley, Reading, Massachusetts}, +Year ={1996} } + +@TechReport{WhitehurstProofs89, +author={R. Alan Whitehurst and T.F. Lunt}, +Title="Final Report Vol.\ 3B: The {SeaView} Formal Verification: Proofs", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, +Year=1989 } + +@InProceedings{Wilson88, +Author={J. Wilson}, +Title={Views as the Security Objects in a Multilevel Secure Relational + Database Management System}, +Booktitle={Proceedings of the 1988 IEEE Symposium on Security and + Privacy}, +month=apr, +Year=1988 } + +@InProceedings{Woodward87, +Author={J. Woodward}, +Title={Exploiting the Dual Nature of Sensitivity Labels}, +Booktitle={Proceedings of the 1987 IEEE Symposium on Security and + Privacy}, +month=apr, +Year=1987 } + +@Article{S3, +Author={M. Youngers and J. Franklin and C. Lackey Carmody and A. Meyrowitz}, +Title={Improving {C}3: The Potential of Artificial Intelligence}, +Journal={Signal}, +volume={XL(10)}, +pages={51+}, +month=jun, +year=1986 } + +@InProceedings{Wagner86, +Author={N.R. Wagner and P.S. Putter and M.R. Cain}, +Title={Encrypted database design: specialized approaches}, +Booktitle={Proceedings of the 1986 IEEE Symposium on Security and + Privacy}, +month=apr, +Year=1986 } + +@Article{Waltz83, +Author={D.L. Waltz}, +Title={Helping Computers Understand Natural Languages}, +Journal={IEEE Spectrum}, +month=nov, +year=1983 } + +@TechReport{Wehrle83, +author={E. Wehrle and J. Schlorer}, +Title="The Partner Algorithm for Protecting Statistical Databases", +type={Technical Report, Klinische Dokumentation}, +institution="Universit{\"a}t Ulm", +address={Ulm, Germany}, +month=mar, +Year=1983 } + +@TechReport{Whitehurst87, +author={R. Alan Whitehurst}, +Title="Expert Systems in Intrusion-Detection: A Case Study", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, +month=nov, +Year=1987 } + +@InProceedings{Whitehurst89, +Author={R. Alan Whitehurst and T.F. Lunt}, +Title={The {SeaView} Verification}, +Booktitle={Proceedings of the Second Workshop on the Foundations of Computer Security}, +month=jun, +Year=1989 } + +@InProceedings{Woelk86, +Author={D. Woelk and W. Kim and W. Luther}, +Title={An Object-Oriented Approach to Multimedia Databases}, +Booktitle={ACM SIGMOD Conference Proceedings}, +Year=1986 } + +@Article{Yankelovich88, +Author={N. Yankelovich and B. Haan and N. Meyrowitz and S. Drucker}, +Title={Intermedia: The Concept and the Construction of a Seamless Information + Environment}, +Journal={Computer}, +month=jan, +year=1988 } + +@TechReport{DoD87, +author={National Computer Security Center}, +title={A guide to Understanding Discretionary Access Controls in Trusted Systems}, +number={NCSC-TG-003}, +institution={National Computer Security Center}, +month=sep, +year=1987 } + +@TechReport{2167A, +author={Department of Defense}, +title={Defense System Software Development}, +number={DoD-STD-2167A}, +institution={Department of Defense}, +month=feb, +year=1988 } + +@TechReport{JDN88031, +Author={J.D. Northcutt and R.K. Clark and S.E. Shipman and D.P. +Maynard and D. C. Lindsay and E.D. Jensen and J.M. Smith and R.B. +Kegley and P.J. Keleher and B.A. Zimmerman}, +Title={{A}lpha Preview: A Briefing and Technology Demonstration for +{DoD}}, +Institution={Department of Computer Science}, +Type={Archons Project Technical Report 88031}, +Address={Carnegie-Mellon University, Pittsburgh, Pennsylvania}, +Month=mar, +Year=1988} + +@TechReport{EDJ88121, +Author={E.D. Jensen and J.D. Northcutt and R.K. Clark and S.E. +Shipman and D.P. Maynard and D.C. Lindsay}, +Title={The {A}lpha Operating System: An Overview}, +Type={Archons Project Technical Report 88121}, +Institution={Department of Computer Science}, +Address={Carnegie-Mellon University, Pittsburgh, Pennsylvania}, +Month=dec, +Year=1980 } + +@TechReport{JDN88011, +Author={J.D. Northcutt}, +Title={The {A}lpha Operating System: Requirements and Rationale}, +Type={Archons Project, technical report 88011}, +Institution={Department of Computer Science}, +Address={Carnegie-Mellon University, Pittsburgh, Pennsylvania}, +Month=jan, +Year=1988 } + +@TechReport{JDN88011a, +Author={J.D. Northcutt and R.K. Clark}, +Title={The {A}lpha Operating System: Programming Model}, +Type={Archons Project Technical Report 88021}, +Institution={Department of Computer Science}, +Address={Carnegie-Mellon University, Pittsburgh, Pennsylvania}, +Month=feb, +Year=1988 } + +@TechReport{JDN88122, +Author={J.D. Northcutt and R.K. Clark and S.E. Shipman and D.C. +Lindsay}, +Title={The {Alpha} Operating System: System/Subsystem Specification}, +Type={Archons Project Technical Report 88122}, +Institution={Department of Computer Science}, +Address={Carnegie-Mellon University, Pittsburgh, Pennsylvania}, +Month=dec, +Year=1988 } + +@TechReport{JDN88111, +Author={J.D. Northcutt}, +Title={The {A}lpha Operating System: Kernel Programmer's Interface +Manual}, +Type={Archons Project Technical Report 88111}, +Institution={Department of Computer Science}, +Address={Carnegie-Mellon University, Pittsburgh, Pennsylvania}, +Month=nov, +Year=1988 } + +@TechReport{JET88123, +Author={J.E. Trull and J.D. Northcutt and R.K. Clark and S.E. +Shipman}, +Title={An Evaluation of {A}lpha Real-Time Scheduling Policies}, +Type={Archons Project Technical Report 88123}, +Institution={Department of Computer Science}, +Address={Carnegie-Mellon University, Pittsburgh, Pennsylvania}, +Month=dec, +Year=1988 } + +@TechReport{RKC88032, +Author={R.K. Clark and R.B. Kegley and P.J. Keleher and D.P. +Maynard and J.D. Northcutt and S.E. Shipman and B.A. Zimmerman}, +Title={An Example Real-Time Command and Control Application on {A}lpha}, +Type={Archons Project Technical Report 88032}, +Institution={Department of Computer Science}, +Address={Carnegie-Mellon University, Pittsburgh, Pennsylvania}, +Month=mar, +Year=1988} + +@TechReport{JDN88123, +Author={J.D. Northcutt and S.E. Shipman}, +Title={The {A}lpha Operating System: Program Maintenance Manual}, +Type={Archons Project Technical Report 88123}, +Institution={Department of Computer Science}, +Address={Carnegie-Mellon University}, +Month=dec, +Year=1988} + +@TechReport{JDN88041, +Author={J.D. Northcutt and S.E. Shipman}, +Title={The {A}lpha Operating System: Programming Utilities}, +Type={Archons Project Technical Report 88041}, +Institution={Department of Computer Science}, +Address={Carnegie-Mellon University, Pittsburgh, Pennsylvania}, +Month=apr, +Year=1988} + +@TechReport{JDN88033, +Author={J.D. Northcutt}, +Title={The {A}lpha Distributed Computer System Testbed}, +Type={Archons Project Technical Report 88033}, +Institution={Department of Computer Science}, +Address={Carnegie-Mellon University, Pittsburgh, Pennsylvania}, +Month=mar, +Year=1988 } + +@book{JDN87, +Author={J.D. Northcutt}, +Title={Mechanisms for Reliable, Distributed Real-Time Operating Systems: The +{A}lpha Kernel}, +Publisher={Academic Press, New York}, +Year=1987} + +@TechReport{EDJ88120, +Author={E.D. Jensen and J.A. Test and R.D. Reynolds and E. Burke +and J.G. Hanko}, +Title={Alpha Release 2 Design Summary Report}, +Type={Technical Report 88120}, +Institution={Kendall Square Research Corporation, Cambridge, Massachusetts}, +Month=sep, +Year=1988} + +@TechReport{FDR88121, +Author={F.D. Reynolds and J.G. Hanko and J.A. Test and E. Burke +and E.D. Jensen}, +Title={Alpha Release 2 Kernel Interface Specification}, +Type={Technical Report 88121}, +Institution={Concurrent Computer Corporation, Cambridge, Massachusetts}, +Month=dec, +year=1988} + +@TechReport{RDR88122, +Author={F.D. Reynolds and J.G. Hanko and E.D. Jensen}, +Title={Alpha Release 2 Preliminary System/Subsystem Description}, +Type={Technical Report 88122}, +Institution={Concurrent Computer Corporation}, +Month=dec, +year=1988} + +@manual{Clark90, + Organization={Ph.D. Thesis, School of Computer + Science, Carnegie-Mellon University}, + Title={Scheduling Dependent Real-Time Activities}, + Author={R.K. {Clark}}, Year={1990}, Address={Pittsburgh, Pennsylvania}, + } + +@TechReport{DenningSecurityModel87, +author={T.F. Lunt and D.E. Denning and R.R. Schell +and M. Heckman and W.R. Shockley}, Title="Secure Distributed Data Views: +Formal Security Policy Model", +type={Technical Report}, number={RADC-TR-89-313, vol. II (of five)}, +institution="Rome Air Development Center", Year=1989 } + +@Article{LuntSeaViewModel90, +author={T.F. Lunt and D.E. Denning and R.R. Schell and M. Heckman and +W.R. Shockley}, Title="The {SeaView} Security Model", +Journal={IEEE Transactions on Software Engineering}, +volume=16, +number=6, +pages={593-607}, +month=jun, +year=1990 } + +@TechReport{Denning86Policy, +Author={D.E. Denning and T. Lunt and P.G. Neumann +and R.R. Schell and M. Heckman and W. Shockley}, Institution={Computer Science +Laboratory, SRI International}, Title={Security Policy and Interpretation for a +Class A1 Multilevel Secure Relational Database System}, Year={1986}, +Month=nov, Address={Menlo Park, California}} + +@InProceedings{KeyKOS, +Author={S.A. Rajunas and N. Hardy and A.C. Bomberger and W.S. Frantz and C.R. Landau}, +Title={Security in {K}ey{KOS}}, +Booktitle={Proceedings of the 1986 IEEE Sympsium on Security and Privacy}, +Month=apr, +Year=1986 } + +@Article{ShapiroHardy02, + Author={J.S. Shapiro and N. Hardy}, + Journal={IEEE Software}, + Title={{EROS:} A Principle-Driven Operating System from the Ground Up}, + Year={2002}, + Month={January/February}, + Volume={19}, + Number={1}, + Pages={26--33} + } + +@inproceedings{Kain86, +author = "R.Y. Kain and C.E. Landwehr", +title = "On Access Checking in Capability-Based Systems", +booktitle = {Proceedings of the 1986 IEEE Symposium on Security and Privacy}, +month = apr, +year = 1986 } + +@book{KainArch, +Author={R.Y. Kain}, +Title={Computer Architecture: Software and Hardware}, +Publisher={Prentice-Hall}, +Year={1988} } + +@InProceedings{Gong89c, +Author={L. Gong}, Title={A Secure Identity-Based Capability System}, +BookTitle ={Proceedings of the 1989 Symposium on Research in Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1989}, Month=may, pages={56--63} } + +@book{Soltis-400, +Author={F.G. Soltis}, +Title={Inside the AS/400}, +Publisher={29th Street Press, Loveland, Colorado, second edition}, +Year={1997} } + +@book{Soltis-i, +Author={F.G. Soltis}, +Title={Fortress Rochester: The Inside Story of the IBM iSeries}, +Publisher={29th Street Press, Loveland, Colorado}, +Year={2001} } + +@InProceedings{LuntDesign88, +Key={Lunt}, Author={T.F. Lunt and R.R. Schell and W.R. +Shockley and M. Heckman and D. Warren}, Title={A Near-Term Design for the +\mbox{{SeaView}} Multilevel Database System}, +BookTitle={Proceedings of the 1988 Symposium on +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1988}, Month=apr, pages={234-244}} + +@InProceedings{LuntDonovan90, +Author={T.F. Lunt and D. Hsieh}, +Title={The {SeaView} Secure Database System: A Progress Report}, +BookTitle={Proceedings of the European Symposium on Research in Computer Security +(ESORICS 90)}, Organization={IEEE Computer Society}, Address={Toulouse, +France}, Year={1990}, Month=oct, pages={}} + +@TechReport{DenningNeumann85, +Author={D.E. Denning and P.G. Neumann}, +Institution={Computer Science Laboratory, SRI International}, +Title={Requirements and Model for {IDES}: {A} Real-Time Intrusion-Detection +Expert System}, Year={1985}, Month=aug, Address={Menlo Park, California} } + +@TechReport{NCIC89, +Author={J.J. Horning and P.G. Neumann and D.D. Redell and J. Goldman and D.R. Gordon}, +Institution={Computer Professionals for Social Responsibility}, +Title={A Review of NCIC 2000 (report to the Subcommittee on Civil and +Constitutional Rights of the Committee on the Judiciary, United States House of +Representatives)}, Year={1989}, Month=feb, Address={Palo Alto, California} } + +@TechReport{NCIC90, +Author={P.G. Neumann}, +Institution={Computer Science Laboratory, SRI International}, +Title={Security Controls for NCIC Computer System Use: Federal, State, and Local}, +Year={1990}, day={29}, month={June}, Address= {Menlo Park, California} } + +@TechReport{TECSSecReq, +Author={T.F. Lunt and P.G. Neumann and J. Rushby and M. Moriconi}, +Institution={Computer Science Laboratory, SRI International}, +Title={{FBI-Customs Trusted Guard}: Security Policy and Security Requirements}, +Year={1990}, day={12}, month=nov, Address= {Menlo Park, California}, +NOTE= {Prepared for Roger Woods, FBI, Washington, D.C., under +Contract No.~N00174-89-C-0188. } } + +@InProceedings{Neumann90Halifax, +Author={P.G. Neumann}, Title={Whither Formal Methods?}, Booktitle={Formal +Methods for Trustworthy Computer Systems (FM'89), A Workshop on the Assessment +of Formal Methods for Trustworthy Computer Systems}, Note={23-27 July 1989, +Nova Scotia, Canada, D. Craigen and K. Summerskill (eds.)}, Year=1990, +isbn={3-540-19635-8}, +Publisher={Springer-Verlag, Berlin} } + +@Book{Craigen90, +Author={D. Craigen and K. {Summerskill (eds.)}}, Title={Formal +Methods for Trustworthy Computer Systems (FM'89), A Workshop on the Assessment +of Formal Methods for Trustworthy Computer Systems}, Note={23-27 July 1989, +Nova Scotia, Canada}, Year=1990, +isbn={3-540-19635-8}, +Publisher={Springer-Verlag, Berlin} } + +@Book{Srivas+96, +Author={M. Srivas and A. {Camilleri, editors}}, +Title={Formal Methods in Computer-Aided Design}, +publisher={Springer-Verlag, Berlin, +Lecture Notes in Computer Science, Vol. 1166}, +Year=1996 } + +@INPROCEEDINGS{Neumann87COMPASS, +Author={P.G. Neumann}, Key={Neumann}, +Year=1987, Month="Jun-Jul", Title={The {N} Best (or Worst) +Computer-Related Risk Cases}, +BookTitle={Proceedings of the Second Annual Conference on Computer +Assurance COMPASS '87, IEEE 87TH0196-6}, Organization={IEEE}, Pages={xi-xiii}} + +@INPROCEEDINGS{Neumann88COMPASS, +Author={P.G. Neumann}, Key={Neumann}, +Year=1988, Month=Jun, Title={The Computer-Related Risk of the Year: Computer +Abuse}, BookTitle={Proceedings of the Third Annual Conference on Computer +Assurance COMPASS '88, IEEE 88CH2628-6}, Organization={IEEE}, Pages={8-12}} + +@INPROCEEDINGS{Neumann89COMPASS, +Author={P.G. Neumann}, Key={Neumann}, +Year=1989, Month=Jun, Title={The Computer-Related Risk of the Year: +Misplaced Trust in Computer Systems}, +BookTitle={Proceedings of the Fourth Annual Conference on Computer +Assurance, COMPASS '89}, Organization={IEEE}, Pages={9-13}} + +@INPROCEEDINGS{Neumann90COMPASSa, +Author={P.G. Neumann}, Key={Neumann}, +Year=1990, Month=Jun, Title={The Computer-Related Risk of the Year: Distributed +Control}, BookTitle={Proceedings of the Fifth Annual Conference on Computer +Assurance, COMPASS '90, IEEE 90CH2830}, Organization={IEEE}, Pages={173-177}} + +@INPROCEEDINGS{Neumann90COMPASSb, +Author={P.G. Neumann}, Key={Neumann}, +Year=1990, Month=Jun, Title={Towards Standards and Criteria for Critical +Computer Systems}, BookTitle={Proceedings of the Fifth Annual Conference on +Computer Assurance, COMPASS '90}, Organization={IEEE}, Pages={186-188}} + +@INPROCEEDINGS{Neumann91COMPASS, +Author={P.G. Neumann}, Key={Neumann}, +Year=1991, Month=Jun, Title={The Computer-Related Risk of the Year: +Weak Links and Correlated Events}, +BookTitle={Proceedings of the Sixth Annual Conference on Computer +Assurance, COMPASS 91}, Organization={NIST, IEEE 91CH3033-8}, Pages={5-8}} + +@INPROCEEDINGS{Neumann93COMPASS, +Author={P.G. Neumann}, Key={Neumann}, +Year=1993, Month=Jun, Title={Myths of Dependable Computing: +Shooting the Straw Herrings in Midstream}, +BookTitle={Proceedings of the Eighth Annual Conference on Computer +Assurance, COMPASS 93}, Organization={NIST}, Pages={1--4}} + +@InProceedings{Neumann90EWD, +Key={Neumann}, Author={P.G. Neumann}, +title={Beauty and the Beast of Software Complexity -- Elegance versus Elephants}, +organization={Springer-Verlag, Berlin, New York}, +pages={346-351 (Chapter 39)}, +Year="11 May 1990", +booktitle= "Beauty Is Our Business, A Birthday Salute to Edsger W. Dijkstra", +note = {W.H.J. Feijen, A.J.M. van Gasteren, D. Gries, J. Misra, eds.} } + +@book{DijkstraBeauty, +Author={W.H.J. Feijen and A.J.M. van Gasteren and D. Gries and J. {Misra, editors}}, +Title={Beauty is our Business, A Birthday Salute to Edsger W. Dijkstra}, +Publisher={Springer-Verlag, Berlin}, +isbn={0-387-97299-4}, +Year={11 May 1990} } + +@InProceedings{Neumann90NCS, +Key = "Neumann", Author = "P.G. Neumann", +Title="Rainbows and Arrows: How the Security Criteria Address Computer Misuse", +Booktitle="Proceedings of the Thirteenth National Computer Security + Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1990", +Pages="414-422", month=oct } + +@InProceedings{Ware95NCS, +Key = "Ware", Author = "W.H. Ware", +Title="A Retrospective of the Criteria Movement", +Booktitle = "Proceedings of the Eighteenth +National Information Systems Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1995", +Pages="582-588", month=oct } + +@TechReport{Ware70, +author={W.H. Ware}, +Title={Security Controls for Computer Systems}, +institution= {RAND report for the Defense Science Board}, +address={}, month ={}, Year=1970, +note = {http://cryptome.org/sccs.htm} } + +@InProceedings{Neumann90Complexity, +Key = "Neumann", Author = "P.G. Neumann", +Title = "Managing Complexity in Critical Systems", +Booktitle = "Managing Complexity and Modeling Reality: Strategic Issues +and an Action Agenda", +Note="In a report edited by D. Frailey, based on an ACM +Conference on Critical Issues, Arlington, Virginia, +6-7 November 1990. This paper +includes a discussion of papers by David Parnas, Edward +S. Cheevers and R. Leddy in the conference track on Managing Complexity", +Address = "ACM, New York", Year = "1991", +ISBN={0-89791-458-9}, Pages="2-36 -- 2-42" } + +@TechReport{Neumann90NSF, +Author={P.G. Neumann}, Key={Neumann}, +Institution={Computer Science Laboratory, SRI International}, +Title={On the Design of Dependable Computer Systems for +Critical Applications}, Note={CSL Technical Report CSL-90-10}, +Year={1990}, Month=oct, Address={Menlo Park, California} } + +@TechReport{Neumann90RADC, +Author={P.G. Neumann and N.E. Proctor and T.F. Lunt}, Key={Neumann}, +Title={Secure Distributed Systems: Vulnerabilities, Defenses, and Analyses}, +Institution={Computer Science Laboratory, SRI International}, +Note={Project 1021, Interim Report}, +Year={1990}, Month=nov, Address={Menlo Park, California} } + +@TechReport{Neumann91RADC1, +Author={P.G. Neumann and N.E. Proctor and T.F. Lunt}, Key={Neumann}, +Title={A Designer's Handbook for Secure Distributed Systems -- Preventing +System Misuse: Analysis and Synthesis}, +Institution={Computer Science Laboratory, SRI International}, +Note={Project 1021, Interim Report}, +Year={1991}, Month=apr, Address={Menlo Park, California} } + +@TechReport{NeumannProctor91Handbook, +Author={P.G. Neumann and N.E. Proctor and T.F. Lunt}, +Title={Preventing Security Misuse in Distributed Systems}, +Institution={Computer Science Laboratory, SRI International}, +Note={Project 1021, Final Report}, +Year={1992}, day={20}, month={March}, Address={Menlo Park, California} } + +@TechReport{Neumann92RL, +Author={P.G. Neumann and N.E. Proctor and T.F. Lunt}, +Title={Preventing Security Misuse in Distributed Systems}, +Institution={Rome Laboratory Air Force Systems Command, +Griffiss Air Force Base, N.Y., 13441-5700}, +Note={RL-TR-92-152. For Official Use Only: +US Government Agencies and their +Contractors -- Critical Technology.}, +Year={1992}, Month=jun, Address={} } + +@TechReport{NeumannProctorLunt92, +Author={P.G. Neumann and N.E. Proctor and T.F. Lunt}, Key={Neumann}, +Title={Preventing Security Misuse in Distributed Systems}, +Institution={Computer Science Laboratory, SRI International}, +Note={Issued as Rome Laboratory report RL-TR-92-152, +Rome Laboratory C3AB, Griffiss AFB NY 13441-5700. +For Official Use Only.}, +Year={1992}, Month=jun, Address={Menlo Park, California} } + +@TechReport{LABCOM92, +Author={A. Barnes and A. Hollway and P.G. Neumann}, +Title={Survivable Computer-Communication Systems: The Problem and + Preliminary Recommendations}, +Institution={U.S. Army Vulnerability Assessment Laboratory}, +Note={For Official Use Only.}, +Year={1992}, Month=nov, Address={U.S. Army Vulnerability +Assessment Laboratory, SLCVA-D, White Sands Missile Range, NM 88002-5513} } + +@TechReport{LABCOM93, +Author={A. Barnes and A. Hollway and P.G. Neumann}, +Title={Survivable Computer-Communication Systems: The Problem and + Working Group Recommendations. {VAL-CE-TR-92-22} (revision 1)}, +Note={For Official Use Only.}, +Year={1993}, Month=may, Institution={U.S. Army Research +Laboratory, AMSRL-SL-E, White Sands Missile Range, NM 88002-5513} } + +@TechReport{Greenberg93, +Author={I. Greenberg and P. Boucher and R. Clark and E.D. Jensen and +T.F. Lunt and P.G. Neumann and D. Wells}, +Title={The Multilevel Secure Real-Time Distributed Operating System Study}, +Institution={Computer Science Laboratory, SRI International}, +Note={Issued as Rome Laboratory report RL-TR-93-101, +Rome Laboratory C3AB, Griffiss AFB NY 13441-5700. Contact Emilie Siarkiewicz, +Internet: SiarkiewiczE@CS.RL.AF.MIL, phone 315-330-3241. +For Official Use Only.}, +Year={1992}, Month=jun, Address={Menlo Park, California} } + +@TechReport{Proctor91RADC, +Author={N.E. Proctor}, Key={Proctor}, +Title={{SeaView} formal specifications}, +Institution={Computer Science Laboratory, SRI International}, +Year={1991}, Month=apr, Address={Menlo Park, California} } + +@TechReport{Gree91 + ,Author={I.B. Greenberg}, Institution={SRI International} + ,Title={Distributed Database Security}, Year={1991} + ,Month=apr, Address={Menlo Park, California}, Type={Final Report} + ,Note={For Contract No. MDA904-90-C-7708} } + +@InProceedings{Gree91b, +Author={I.B. Greenberg}, +BookTitle={Proceedings of the Fourth RADC Multilevel Database Security Works +hop},Organization={},Address={Little Compton, RI}, +Title={Should Serializability be Enforced in Multilevel Database Systems}, +Year={1991},Month=apr,Pages={} } + +@ARTICLE{NeumannRISKSindex91, +Author={P.G. Neumann}, TITLE = {Illustrative Risks to the Public in the +Use of Computer Systems and Related Technology, Index to {RISKS} cases +as of 23 {D}ecember 1991}, +JOURNAL = {ACM Software Engineering Notes}, YEAR = {1992}, VOLUME = {17}, +NUMBER = {1}, PAGES = {23-32}, MONTH = jan , NOTE = {(Cumulative +updates are available on request.)}} + +@ARTICLE{NeumannRISKSindex94, +Author={P.G. Neumann}, TITLE = {Illustrative Risks to the Public in the +Use of Computer Systems and Related Technology, Index to {RISKS} cases, +as of 7 {O}ctober 1993}, +JOURNAL = {ACM Software Engineering Notes}, YEAR = {1994}, VOLUME = {19}, +NUMBER = {1}, PAGES = {16--29}, MONTH = jan, +NOTE = {(At-least quarterly cumulative updates to this index are available +on request.)}} + +@ARTICLE{NeumannRISKSindex96, +Author={P.G. Neumann}, TITLE = {Illustrative Risks to the Public in the +Use of Computer Systems and Related Technology, Index to {RISKS} cases +as of 27 {N}ovember 1995}, +JOURNAL = {ACM Software Engineering Notes}, YEAR = {1996}, VOLUME = {21}, +NUMBER = {1}, PAGES = {16--30}, MONTH = jan, +NOTE = {(This refers to the most recent published version. +Cumulative updates to this index are available online +at \verb+ftp://ftp.csl.sri.com/pub/users/neumann/illustrative.ps+ +and \verb+.pdf+ .)}} + +@TechReport{NeumannRISKSindex, +Author={P.G. Neumann}, TITLE = {Illustrative Risks to the Public in the +Use of Computer Systems and Related Technology, Index to {RISKS} cases}, +Institution = {Computer Science Laboratory, SRI International}, +Address = {Menlo Park, California}, +YEAR = {2010}, +NOTE = {Updated now and then: http://www.csl.sri.com/neumann/illustrative.html; +also in .ps and .pdf form for printing in a denser format.} +} + +@TechReport{NeumannRISKSindexVot, +Author={P.G. Neumann}, TITLE = {Illustrative Risks to the Public in the +Use of Computer Systems and Related Technology, Index to {RISKS} cases}, +Institution = {Computer Science Laboratory, SRI International}, +Address = {Menlo Park, California}, +YEAR = {2004}, +NOTE = {The most recent version is available online +in html form for browsing at \xlink{http://www.csl.sri.com/neumann/illustrative.html}{http://www.csl.sri.com/neumann/illustrative.html}. +Click on ``Election Problems''.}} + +@article{InsideRISKS, +author={P.G. Neumann}, key={neumann}, title = {Inside +RISKS}, journal = {Communications of the ACM}, year = {1990-}, volume = {33-}, number = {}, +pages = {inside back cover}, month = {}, year = {}, Note = {monthly column +since Jul 1990} } + +@InProceedings{Neumann91NCCV, +Key = {Neumann}, Author = {P.G. Neumann}, +Title = {Computer Security and Human Values}, +Booktitle = {Proceedings of the National Conference on Computing and Values}, +Organization = {Southern Connecticut State University, New Haven, +Connecticut}, Year = {1991}, Pages={}, Month = {12-16 August} } + +@InProceedings{Neumann92GI, +author={P.G. Neumann}, +Title={Developing Complex Software for Critical Systems}, +BookTitle={22. Jahrestagung der Gesellschaft f\"{u}r Informatik}, +Year="1992", Month="30 Sept -- 2 October", pages="117-131" } + +@InProceedings{ProctorNeumann92, +author={N.E. Proctor and P.G. Neumann}, +Title={Architectural Implications of Covert Channels}, +BookTitle="Proceedings of the Fifteenth National Computer Security Conference", +Address = "Baltimore, Maryland", Year="1992", Month="13--16 October", +pages="28--43", +url="http://www.csl.sri.com/neumann/ncs92.html" } + +@TechReport{NeumannGong94, +author={P.G. Neumann and L. Gong}, +Title={Minimizing Trust in Multilevel-Secure Systems}, +Institution = "SRI International, Menlo Park, California", +Year="1994", Month="15 March" } + +@InProceedings{Gong94, +Author={L. Gong}, TITLE = {New Protocols for Third-Party-Based +Authentication and Secure Broadcast}, +Booktitle = {Second ACM Conference on Computer and Communications Security}, +Organization = {ACM SIGSAC}, Address = {Fairfax, Virginia}, +Year = {1994}, +Pages={176--163}, Month = nov } + +@TechReport{Gong94CSL, +author={L. Gong}, +Title={Authentication, Key Distribution, and Secure Broadcast in +Computer Networks Using No Encryption or Decryption}, +Institution = "SRI International, Menlo Park, California, SRI-CSL-94-08", +Year="1994", Month=may, Note = {This report contains two earlier related +papers on hash functions.} } + +@TechReport{gong96f + ,Author={S. Keung and L. Gong} + ,Title={{Enclaves in Java: APIs and Implementations}} + ,Institution={SRI International, Computer Science Laboratory} + ,Address={333 Ravenswood Avenue, Menlo Park, California 94025} + ,Year={1996} + ,Month=jul + ,Number={SRI-CSL-96-07} + } + +@TechReport{Gong96, +author={L. Gong}, +Title={An Overview of {Enclaves} 1.0}, +Institution = "SRI International, Menlo Park, California, SRI-CSL-96-01", +Year="1996", Month=jan, +Note = "(\xlink{http://www.csl.sri.com/papers/346/}{http://www.csl.sri.com/papers/346/})" } + +@ARTICLE{Dugger88, +Author={R. Dugger}, TITLE = {Annals of Democracy (Voting by Computer)}, +JOURNAL = {New Yorker}, YEAR = {1988}, VOLUME = {}, +NUMBER = {}, PAGES = {}, MONTH = {November 7,} } + +@TechReport{Saltman88, +author={R.G. Saltman}, +Title={Accuracy, Integrity, and Security in Computerized Vote-Tallying}, +institution= {National Bureau of Standards (now NIST) special publication}, +address={Gaithersburg, Maryland}, month ={}, Year=1988} + +@InProceedings{Shamos93, +Author={M. Shamos}, TITLE = {Electronic Voting: Evaluating the Threat}, +Booktitle = {Computers, Freedom and Privacy '93}, YEAR = {1993}, +PAGES = {3.18--3.25}, MONTH = mar } + +@InProceedings{Saltman93, +Author={R.G. Saltman}, TITLE = {Assuring Accuracy, Integrity and Security +in National Elections: The Role of the {U.S.} {Congress}}, +Booktitle = {Computers, Freedom and Privacy '93}, YEAR = {1993}, +PAGES = {3.8--3.17}, MONTH = mar } + +@InProceedings{Saltman93b, +Author={R.G. Saltman}, TITLE = {An integrity model is needed for +computerized voting and similar systems}, +BookTitle="Proceedings of the Sixteenth National Computer Security Conference", +Address = "Baltimore, Maryland", Year="1993", Month=sep, +pages="471--473" } + +@InProceedings{Neumann93NCS, +author={P.G. Neumann}, +Title={Security Criteria for Electronic Voting}, +BookTitle="Proceedings of the Sixteenth National Computer Security Conference", +Address = "Baltimore, Maryland", Year="1993", Month=sep, +pages="478--482" } + +@InProceedings{Greenhalgh93, +Author = "G.L. Greenhalgh", +Title = "Security and Auditability of Electronic Vote +Tabulation Systems: One Vendor's Perspective", +Booktitle = "Proceedings of the Sixteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1993", +Pages="483--489", month=sep} + +@InProceedings{Mercuri92, +Author = "R.T. Mercuri", +Title = "Physical Verifiability of Computer Systems", +Booktitle = "5th International Computer Virus and Security Conference", +Year = "1992", Month = mar} + +@InProceedings{Mercuri93, +Author = "R. Mercuri", +Title = "Threats to Suffrage Security", +Booktitle = "Proceedings of the Sixteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1993", +Pages="474--477", month=sep } + +@InProceedings{NRM, +Key="Fellows", Author="J. Fellows and J. Hemenway and N. Kelem", +Title="The Architecture of a Distributed Trusted Computing Base", +BookTitle="10th National Computer Security Conference", +Address = "Baltimore, Maryland", Year="1987", Month="21-24 September", pages="68-77", +Note="Reprinted in Rein Turn, editor, +{\it Advances in Computer System Security}, +Vol. 3, Artech House, Dedham, Massachusetts, 1988" } + +@InProceedings{Weissman88, +Author={C. Weissman}, Title={Blacker: Security for the {DDN}. {E}xamples of +{A1} Security Engineering Trades}, +BookTitle ={Proceedings of the 1992 Symposium on Research in Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1992}, Month=may, pages={286-292}, +Note={This paper was originally presented at the April 1988 Symposium, +but not published for four years because of a release problem.}} + +@InProceedings{Weissman88N, +Author={C. Weissman}, Title={Blacker: Security for the {DDN}. {E}xamples of +{A1} Security Engineering Trades}, +BookTitle ={Proceedings of the 1992 Symposium on Research in Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1992}, Month=may, pages={286-292}, +Note = {This paper was the recipient of the 1988 SSP Best Paper award, but +was not published until 1992.} } + +@article{Weissman91, +author={C. Weissman}, title = {A National Debate on Encryption Exportation}, +journal = {Communications of the ACM}, year = {1991}, volume = {34}, number = {10}, +pages = {162}, month = oct, Note = {Guest contribution to P.G. Neumann's +{\it Inside Risks} column} } + +@article{Neumann90CACM, +author={P.G. Neumann}, title = {Risks in Computerized Elections}, +journal = {Communications of the ACM}, year = {1990}, volume = {33}, +number = {11}, pages = {170}, month = nov, +Note= {{\it Inside Risks} column.} } + +@article{NeumannCACM94-4, +author={P.G. Neumann}, title = {Risks of Passwords}, +journal = {Communications of the ACM}, year = {1994}, volume = {37}, +number = {4}, pages = {126}, month = apr, +Note= {{\it Inside Risks} column.} } + +@article{NeumannCACM94-5, +author={P.G. Neumann}, title = {Alternative Passwords}, +journal = {Communications of the ACM}, year = {1994}, volume = {37}, +number = {5}, pages = {146}, month = may, +Note= {{\it Inside Risks} column.} } + +@article{MercuriNeumannCACM01-1, +author={R. Mercuri and P.G. Neumann}, title = {System Integrity Revisited}, +journal = {Communications of the ACM}, year = {2001}, volume = {44}, +number = {1}, pages = {}, month = jan, +Note= {{\it Inside Risks} column.} } + +@article{MercuriCACM92-11, +author={R. Mercuri}, title = {Voting-Machine Risks}, +journal = {Communications of the ACM}, year = {1992}, volume = {35}, +number = {11}, pages = {}, month = nov, +Note= {{\it Inside Risks} column.} } + +@article{MercuriCACM93-11, +author={R. Mercuri}, title = {Corrupted Polling}, +journal = {Communications of the ACM}, year = {1993}, volume = {36}, +number = {11}, pages = {}, month = nov, +Note= {{\it Inside Risks} column.} } + +@article{MercuriCACM02-1, +author={R. Mercuri}, title = {Uncommon Criteria}, +journal = {Communications of the ACM}, year = {2002}, volume = {45}, +number = {1}, pages = {}, month = jan, +Note= {{\it Inside Risks} column.} } + +@article{MercuriCACM02-11, +author={R. Mercuri}, +title = {Florida 2002: Sluggish Systems, Vanishing Votes}, +journal = {Communications of the ACM}, year = {2002}, volume = {45}, +number = {11}, pages = {}, month = nov, +Note= {{\it Inside Risks} column.} } + +@article{MercuriCACM03-1, +author={R. Mercuri}, +title = {On Auditing Audit Trails}, +journal = {Communications of the ACM}, year = {2003}, volume = {46}, +number = {1}, pages = {}, month = jan, +Note= {{\it Security Watch} column.} } + +@ARTICLE{NeumannMercuriWeinstein01, +Author={P.G. Neumann and R. Mercuri and L. Weinstein}, +TITLE = {Internet and Electronic Voting}, +JOURNAL = {ACM Software Engineering Notes}, YEAR = {2001}, VOLUME = {26}, +NUMBER = {2}, PAGES = {8}, MONTH = mar, +NOTE ={Earlier version in the Risks Forum, volume 21 number 14.} } + +@InCollection{MercuriNeumann02, +Publisher = "Kluwer Academic Publishers", +Author = "R. Mercuri and P.G. Neumann", +Title = "Verification for Electronic Balloting Systems", +Year = "2002", Pages = "", Address = "Boston, Massachusetts", +Booktitle = "Secure Electronic Voting, Advances in Information + Security, Volume 7", +Editors = "D. Grizalis" } + +@inProceedings{MercuriNeumann02x, +Author="R. Mercuri and P.G. Neumann", +Title="Verification for Electronic Balloting Systems", +Booktitle="Secure Electronic Voting", +Note ="D. Gritzalis (editor)", Publisher = +"Kluwer Academic Publishers, Boston",Year="2002",Pages=""} + +@book{Boehm89, +Author={B. Boehm}, +Title={Tutorial: Software Risk Management}, +Publisher={IEEE Computer Society Press, Piscataway, New Jersey}, +Year={1989} } + +@book{Charette89, +Author={R.N. Charette}, +Title={Software Engineering Risk Analysis and Management}, +Publisher={McGraw-Hill, New York}, +Year={1989} } + +@book{Charette90, +Author={R.N. Charette}, +Title={Application Strategies for Risk Analysis}, +Publisher={McGraw-Hill, New York}, +Year={1990} } + +@book{Charette93, +Author={R.N. Charette and F. Scarff and A. Carty}, +Title={Introduction to the Management of Risk}, +Publisher={HMSO (Her Majesty's Stationary Office)}, +NOTE = {ISBN 0 11 330648 2}, +Year={1993} } + +@InProceedings{Charette97, +Author={R.N. Charette}, +TITLE = {Managing the Risks in Information Systems and Technology}, +Booktitle = {Advances in Computers}, YEAR = {1997}, VOLUME = {44}, +Publisher = {Academic Press}, +PAGES = {1--58} } + +@proceedings{LSSI, +Title={SEI/NSIA Conference on Risks in the Acquisition and Development of +Large-Scale Software Intensive (LSSI) Systems}, +ORGANIZATION={SEI/NSIA}, +Address ={Pittsburgh, Pennsylvania}, +Month={October 8-10}, +Year={1991} } + +@book{Jones94, +Author={C. Jones}, +Title={Assessment and Control of Software Risks}, +Publisher={Yourdon Press}, +Year={1994} } + +@InProceedings{BrunnsteinTrust, +Key = {Brunnstein}, Author = {Klaus Brunnstein, Simone Fischer-Huebner}, +Title = {Risk Analysis of "Trusted Computer Systems"}, +Booktitle = {Sixth International Conference on Information Security: SEC'90}, +Organization = {IFIP TC-11}, Address = {Helsinki-Espoo}, Year = {1990}, +Pages={}, Month = {23-25 May} } + +@Manual{DTI, +KEY={GreatBritain}, TITLE = {Dark Green Books}, +ORGANIZATION={Commercial Computer Security Centre, Department of Trade and Industry}, +AUTHOR={U.K.-DTI}, +NOTE = {Volumes V01 (Overview Manual), V02 (Glossary), V03 (Index), V11 (Users' +Code of Practice), V21 (Security Functionality Manual), V22 (Evaluation +Levels Manual), V23 (Evaluation and Certification Manual), V31 (Vendors' +Code of Practice), Version 3.0}, +MONTH = feb, +YEAR={1989}} + +@Manual{GISA, +TITLE = {IT-Security Criteria, Criteria for the Evaluation of +Trustworthiness of Information Technology (IT) Systems}, +ORGANIZATION = {German Information Security Agency (ZSI), +Am Nippenkreuz 19, D 5300 Bonn 2}, AUTHOR={GISA}, +NOTE = {Translation of Kriterien +f\"{u}r die Bewertung der Sicherheit von Systemen der Informationstechnik (IT), +Zentralstelle f\"{u}r Sicherheit in der Informationstechnik (formerly +ZSI, now CSI), +first edition, Bundesanzeiger, K\"{o}ln, Postfach +108006, 5000 Germany}, +MONTH = {11 January}, YEAR= {1989} } + +@article{TanenbaumVanRenesse, +key={tanenbaum}, Author={A.S. Tanenbaum and R. van Renesse}, +TITLE = {Distributed Operating Systems}, JOURNAL = {ACM Computing Surveys}, +YEAR={1985}, VOLUME = {17}, NUMBER = {4}, PAGES = {419-470}, MONTH = dec } + +@book{Mullender89, +Author={S.J. {Mullender (ed.)}}, key={Mullender}, +Title={Distributed Systems}, Publisher={ACM Press, New York, +and Addison-Wesley, Reading, Massachusetts}, Year={1989} } + +@book{Tanenbaum92, +Author={A.S. Tanenbaum}, +Title={Modern Operating Systems}, +Publisher={Prentice-Hall, Englewood Cliffs, New Jersey}, +Year={1992} } + +@article{Amoeba90, +Author={S.J. Mullender and G. van Rossum and A.S. Tanenbaum and R. van Renesse +and H. van Staveren}, TITLE = {Amoeba, A distributed operating system for the +1990s}, JOURNAL = {Computer}, YEAR = {1990}, VOLUME = {33}, NUMBER = {5}, +PAGES = {44-53}, MONTH = may } + +@article{Amoeba90a, +key={tanenbaum}, Author={A.S. Tanenbaum and R. van Renesse and H. van Staveren +and G.J. Sharp and S.J. Mullender and G. van Rossum}, TITLE = {Experiences with +the {A}moeba distributed operating system}, +JOURNAL = {Communications of the ACM}, +YEAR = {1990}, VOLUME = {33}, NUMBER = {12}, PAGES = {46-63}, MONTH = dec } + +@book{Schach, +Author={S.R. Schach}, +Title={Software Engineering, 2nd ed.}, +Publisher={Aksen Associates, Homewood, Illinois}, +Year={1993} } + +@TechReport{Bull+90, +Author={C.E. Landwehr and A.R. Bull and J.P. McDermott and W.S. Choi}, +Institution={Center for Secure Information Technology, +Information Technology Division, Naval Research Laboratory}, +Title={A Taxonomy of Computer Program Security Flaws, with Examples}, +Year={1993}, Month=nov, Address={Washington, D.C.} } + +@book{Hoffman90, +Author={L.J. {Hoffman (ed.)}}, key={Hoffman}, +Title={Rogue Programs: Viruses, Worms, and Trojan Horses}, +Publisher={Van Nostrand Reinhold, New York}, +isbn={0-442-00454-0}, +Year={1990}} + +@book{DenningACM90, +Author={P.J. {Denning (ed.)}}, key={Denning}, +Title={Computers Under Attack: Intruders, Worms, and Viruses}, +Publisher={ACM Press, New York, and Addison-Wesley, Reading, Massachusetts}, +Year={1990}, Note={ACM order number 706900} } + +@book{DenningDenning97, +Author={P.J. Denning and D.D. Denning}, +Title={Internet Besieged}, +Publisher={ACM Press, New York, and Addison-Wesley, Reading, Massachusetts}, +Year={1997} } + +@InProceedings{NeumannACM90, +Author = {P.G. Neumann}, Title = {A Perspective from the Risks Forum}, +Booktitle = {Computers Under Attack: Intruders, Worms, and Viruses}, +Organization = {ACM Press, New York}, +Year = {1990}, Pages={Article 39, 535-543}, Month = {}, NOTE={} } + +@InProceedings{NeumannAAAS93, +Author = {P.G. Neumann}, +Title = {Limitations of Computer-Communication Technology}, +Booktitle = {Proceedings of an Invitational Conference on Legal, Ethical, +and Technological Aspects of Computer and Network Use and Abuse}, +Organization = {AAAS}, Address = {}, +Year = {1993}, Pages={}, Month = dec } + +@TechReport{Paul90, +author={J. Paul}, +Title={Bugs in the Program}, +institution= {Report by the Subcommittee on Investigations and Oversight +of the Committee on Science, Space and Technology}, +address={U.S. House of Representatives}, month ={}, Year=1990} + +@book{NeumannRisksBook, +Author={P.G. Neumann}, +Title={Computer-Related Risks}, +Publisher={ACM Press, New York, and Addison-Wesley, Reading, Massachusetts}, +Year={1995} } + +@book{NeumannRisksBookISBN, +Author={P.G. Neumann}, +Title={Computer-Related Risks}, +Note = {ISBN 0-201-55805-X.}, +Publisher={ACM Press, New York, and Addison-Wesley, Reading, Massachusetts}, +Year={1995} } + +@book{Bernstein96, +Author={P.L. Bernstein}, +Title={Against the Gods: The Remarkable Story of Risk}, +Publisher={John Wiley \& Sons, New York}, +Year={1996} } + +@TechReport{Neumann94crypto, +author={P.G. Neumann}, +Title={Can Systems Be Trustworthy with Software-Implemented Crypto?}, +institution= {Final Report, Project 6402, SRI International}, +Note={For Official Use Only, NOFORN.}, +address={Menlo Park, California}, month =oct, Year={1994}} + +@TechReport{Neumann95Arch, +author={P.G. Neumann}, +Title={Architectures and Formal Representations for Secure Systems}, +institution= {Final Report, Project 6401, SRI International}, +Note={CSL report 96-05.}, +address={Menlo Park, California}, month =oct, Year={1995} } + +@TechReport{Neumann99ARL, +author={P.G. Neumann}, +Title={Practical Architectures for Survivable Systems and Networks}, +institution= {Final Report, Phase One, Project 1688, SRI International}, +address={Menlo Park, California}, +month =jan, Year={1999}, +URL="http://www.csl.sri.com/neumann/arl-one.html", +NOTE = {also available in .ps and .pdf form} } + +@TechReport{Neumann00ARL, +author={P.G. Neumann}, +Title={Practical Architectures for Survivable Systems and Networks}, +institution= {Final Report, Phase Two, Project 1688, SRI International}, +address={Menlo Park, California}, +month =jun, Year={2000}, +NOTE = "http://www.csl.sri.com/neumann/survivability.html" +} + +@TechReport{NeumannCHATS01a, +author={Peter G. Neumann}, +Title={Composability Revisited}, +institution= {Computer Science Laboratory, SRI International}, +Note = {Interim report, SRI Project 11459, updated occasionally as noted, at +\xlink{http://www.csl.sri.com/neumann/chats1.html}{http://www.csl.sri.com/neumann/chats1.html}; also chats1.ps and chats1.pdf.}, +address={Menlo Park, California}, month ={28 September}, Year=2001 } + +@TechReport{NeumannCHATS01b, +author={Peter G. Neumann}, +Title={{CHATS} Principles}, +institution= {Computer Science Laboratory, SRI International}, +Note = {Interim report, SRI Project 11459, updated occasionally as noted, at +\xlink{http://www.csl.sri.com/neumann/chats2.html}{http://www.csl.sri.com/neumann/chats2.html}; also chats2.ps and chats2.pdf.}, +address={Menlo Park, California}, day=29, month=dec, Year=2001 } + +@TechReport{NeumannCHATS02a, +author={P. G. Neumann}, +Title={Principled Composable Trustworthy Architectures}, +institution= {Computer Science Laboratory, SRI International}, +Note = {Interim report, SRI Project 11459, updated occasionally as noted, at +\xlink{http://www.csl.sri.com/neumann/chats3.html}{http://www.csl.sri.com/neumann/chats3.html}; also chats3.ps and chats3.pdf.}, +address={Menlo Park, California}, day=29, month=mar, Year=2002 } + +@TechReport{NeumannCHATS02b, +author={P.G. Neumann}, +Title={Principled Assuredly Trustworthy Composable Architectures}, +institution= {Computer Science Laboratory, SRI International}, +Note = {First-year final report, SRI Project 11459, +\xlink{http://www.csl.sri.com/neumann/chats4.html}{http://www.csl.sri.com/neumann/chats4.html}; also chats4.ps and chats4.pdf.}, +address={Menlo Park, California}, day=29, month=jun, Year=2002 } + +@TechReport{NeumannCHATS04, +author={Peter G. Neumann}, +Title={Principled Assuredly Trustworthy Composable Architectures}, +institution= {Computer Science Laboratory, SRI International}, +address={Menlo Park, California}, month=dec, Year=2004, +NOTE = "http://www.csl.sri.com/neumann/chats4.html, .pdf, and .ps, Final report, SRI Project 11459" + } + +@InProceedings{Neumann03DISCEX3, +Author={P.G. Neumann}, +Title={Achieving Principled Assuredly Trustworthy Composable Systems + and Networks}, +BookTitle={Proceedings of the DARPA Information Survivability Conference + and Exhibition, DISCEX3, volume 2}, +Organization={DARPA and IEEE Computer Society}, Address={}, +Year={2003}, Month=apr, pages={182--187}} + +@TechReport{Lee+92, +author={E.S. Lee and P.I.P. Boulton and B.W. Thomson and R.E. Soper}, +Title={Composable Trusted Systems}, +institution= {Computer Systems Research Institute}, +Note = {CSRI-272}, +address={University of Toronto, Ontario}, month ={31 May}, Year=1992 } + +@TechReport{Dinolt94, +author={L.A. Benzinger and G.W. Dinolt and M.G. Yatabe}, +Title={Final Report: A distributed system multiple security policy model}, +institution= {Loral Western Development Laboratories, report WDL-TR00777}, +address={San Jose, California}, month =oct, Year={1994} } + +@InProceedings{Dinolt94b, +author={L.A. Benzinger and G.W. Dinolt and M.G. Yatabe}, +Title={Combining components and policies}, +Booktitle={Proceedings of the Computer Security Foundations + Workshop VII, J. Guttman, editor}, +institution= {IEEE Computer Society Press}, +month =jun, Year={1994} } + +@InProceedings{DinoltWilliams87, + author = "G.W. Dinolt and J.C. Williams", + title = "{A Graph-Theoretic Formulation of Multilevel Secure + Distributed Systems: An overview}", + booktitle = "1987 IEEE Symposium on Security and Privacy", + year = "1987", + pages = "99-103", + organization = "The Computer Society of the IEEE", + publisher = "IEEE Computer Society Press", + address = "1730 Massachusetts Avenue, N.W., Washington, D.C. 20036-1903", + month = Apr} + +@book{BurnhamRise, +Author={D. Burnham}, +Title={The Rise of the Computer State}, +Publisher={Random House, New York}, +Year={1982} } + +@book{BurnhamIRS, +Author={D. Burnham}, +Title={A Law Unto Itself: The {IRS} and the Abuse of Power}, +Publisher={Vintage Books, Random House, New York}, +Year={1989} } + +@book{GarfinkelSpafford91, +Author={S. Garfinkel and E. Spafford}, key={Garfinkel}, +Title={Practical {UNIX} Security}, +Publisher={O'Reilly \& Associates, Sebastopol, California}, +Year={1991} } + +@book{GarfinkelSpafford03, +Author={S. Garfinkel and E. Spafford and A. Schwartz}, key={Garfinkel}, +Title={Practical {UNIX} and Internet Security, 3rd Edition}, +Publisher={O'Reilly \& Associates, Sebastopol, California}, +Year={2003} } + +@book{Garfinkel95, +Author={S. Garfinkel}, +Title={PGP: Pretty Good Privacy}, +Publisher={O'Reilly \& Associates, Sebastopol, California 95472}, +Year={1995} } + +@book{Ferbrache92, +Author={D. Ferbrache}, +Title={A Pathology of Computer Viruses}, +Publisher={Springer-Verlag, Berlin}, +Year={1992} } + +@InProceedings{Bonyun, +Author = "D. Bonyun", +Title = "Rules as the Basis of Access Control in Database Management Systems", +BookTitle="7th DoD/NBS Computer Security Initiative Conf., +NBS, Gaithersburg, Maryland", Year="1984", Month="24-26 September", Pages="38-47"} + +@Manual{AFSB83, +Author={M. {Schaefer et al.}}, key={Schaefer}, +Title={Multilevel Data Management Security}, +organization={Air Force Studies Board, National Research Council, +National Academies Press}, Year=1983, +Note={Final report of the 1982 Multilevel Data Management Security + Committee.} } + +@Book{NAS, +Key="Schaefer", Author = {M. {Schaefer (editor)}}, +Title ="Multilevel Data Management Security", Note = "Report of the 1982 +Summer Study, National Academy of Sciences, +Air Force Studies Board, Marvin Schaefer, Chairman, For Official Use Only)", +Publisher ="National Academies Press, Air Force Studies Board, National +Research Council", Address = "Washington, D.C.", Year= "1983"} + +@Book{NASdb, Key="Schaefer", Author = {M. {Schaefer (editor)}}, Title +="Multilevel Data Management Security", Note = "Report of the 1982 +Summer Study, National Academy of Sciences, +Air Force Studies Board, Marvin Schaefer, Chairman; published in 1983). +In particular, see Chapter 3 +-- General Security Policy, D.E. Denning and P.G. Neumann (eds)", +Publisher ="National Academies Press, Air Force Studies Board, National +Research Council", Address = "Washington, D.C.", Year= "1983"} + +@InProceedings{NASsdb, +Author = {D.E. Denning and P.G. {Neumann, editors}}, +title ={General Security Policy}, +Booktitle ={Multilevel Data Management Security}, +Note={Chapter 3 of the Report of the 1982 Summer Study, + National Academy of Sciences, + Air Force Studies Board, Marvin Schaefer, Chairman}, +Address = "Washington, D.C.", Year= "1983"} + +@manual{NAS90, +author = {D.D. {Clark et al.}}, title = {Computers at Risk: Safe +Computing in the Information Age}, organization = {National Research Council, +National Academies Press, 2101 Constitution Ave., Washington, +D.C.}, month = {5 December}, year = {1990}, note={Final report of the +System Security Study Committee.} } + +@book{NRC96, +author = {K.W. Dam and H.S. {Lin, editors}}, +title = {Cryptography's Role In Securing the Information Society}, +publisher = {National Research Council, National Academies Press, +2101 Constitution Ave., Washington, D.C.}, +year = {1996}, note={Final report of the Cryptographic Policy Study +Committee, ISBN 0-309-05475-3.} } + +@book{NRC98trust, +author = {F.B. Schneider and M. {Blumenthal, editor}}, +title = {Trust in Cyberspace}, +publisher = {National Research Council, National Academies Press, +2101 Constitution Ave., Washington, D.C.}, +year = {1998}, note={Final report of the National Research +Council Committee on Information Trustworthiness.} } + +@book{NRC00, +author = {S.H. Fuller and D.G. {Messerschmitt, editors}}, +title = {Making It Better: Expanding Information Technology + Research To Meet Society's Needs}, +publisher = {National Research Council, National Academies Press, +2101 Constitution Ave., Washington, D.C.}, +month = may, year = {2000}, note={Final report of the National Research +Council Committee.} } + +@article{SchneiderCACM98-11, +author={F.B. Schneider}, title = {Toward Trustworthy Networked Information + Systems}, +journal = {Communications of the ACM}, year = {1998}, volume = {41}, +number = {11}, pages = {}, month = nov, +Note= {{\it Inside Risks} column.} } + +@TechReport{Schneider02, +Author={F.B. {Schneider, editor}}, +Title={Research to Support Robust Cyber Defense}, +Institution={Study Committee for J. Lala, DARPA}, +Month =may, Year={2000}, Note={Slides only.} } + +@BOOK{NAS90x, +NOTE = {ISBN 0-309-04388-3} } + +@article{Loepere85, +author={K. P. Loepere}, +title={Resolving Covert Channels within a {B}2 Class Secure System}, +journal={Operating Systems Review}, +month=jul, +year=1985} + +@InProceedings{LuntReal90, +Key = "Loepere", Author = "K.P. Loepere and F.D. Reynolds and E.D. Jensen and +T.F. Lunt", Title = "Security for real-time systems", +Booktitle = "Proceedings of the Thirteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1990", +Pages="318-332", month=oct } + +@book{LeviAgrawala90, +Author={S.-T. Levi and A.K. Agrawala}, +Title={Real-Time System Design}, +Publisher={McGraw-Hill, New York}, +Year={1990} } + +@InProceedings{SandhuJajodia90, +Key = "Sandhu", Author = "R.S. Sandhu and S. Jajodia", +Title = "Integrity mechanisms in database management systems", +Booktitle = "Proceedings of the Thirteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1990", +Pages="526-540", month=oct } + +@InProceedings{SandhuJajodia91, +Key = "Sandhu", Author = "R.S. Sandhu and S. Jajodia", +Title = "Honest Databases That Can Keep Secrets", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="267-282", month=oct } + +@TechReport{Gray89, +author={J. Gray}, Title={Transparency in Its Place}, +institution={TR89.1, Tandem Computers}, +address={Cupertino, California}, month ={}, +Year= 1989 } + +@TechReport{GrayTandem, Key={Gray}, Author={J. Gray}, +Title={Why Do Computers Stop, and What Can Be Done About It?}, +Institution={TR85.7, Tandem Computers, Inc.}, Year={1985}, +Month ={}, Address={Cupertino, California}, } + +@article{OszuValduriez91a, +author={M.T. \"{O}szu and P. Valduriez}, title = {Distributed Database Systems: +Where Are We Now?}, +journal = {Computer}, year = {1991}, volume = {24}, +number = {8}, pages = {68-78}, month = aug } + +@book{OszuValduriez91b, +Author={M.T. \"{O}szu and P. Valduriez}, +Title={Principles of Distributed Database Systems}, +Publisher={Prentice-Hall, Englewood Cliffs, New Jersey}, +Year={1991} } + +@TechReport{Wallace+91a, +author={D.R. Wallace and D.R. Kuhn and J.C. Cherniavsky}, +Title={Proceedings of the Workshop on High Integrity Software}, +institution= {National Institute of Standards and Technology}, +address={Gaithersburg, Maryland}, month ={22-23 January }, +Year=1991, Note = {NIST Special Publication 500-190} } + +@TechReport{Wallace+91b, +author={D.R. Wallace and M. Brown and A. {McKinlay VI}}, +Title={Proceedings of the Forum on Standards for High Integrity Software +({DoD, Goverment, Industry})}, +institution= {National Institute of Standards and Technology}, +address={Gaithersburg, Maryland}, month ={22-23 January }, +Year=1991, Note = {NISTIR 4656} } + +@InProceedings{Roskos90, +Key = "Roskos", Author = "J.E. Roskos and S.R. Welke and J.M. Boone +and T. Mayfield", Title = "A taxonomy of integrity models, implementations +and mechanisms", Booktitle = "Proceedings of the Thirteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1990", +Pages="541-551", month=oct } + +@InProceedings{Levin90, +Key = "Levin", Author = "T.E. Levin and A. Tao and S.J. Padilla", +Title = "Covert storage channel analysis: a worked example", +Booktitle = "Proceedings of the Thirteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1990", +Pages="10-19", month=oct } + +@InProceedings{Thompson90, +Author = "M.F. Thompson and R.R. Schell and A. Tao and T.E. Levin", +Title = "Introduction to the Gemini Trusted Network Processor", +Booktitle = "Proceedings of the Thirteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1990", +Pages="211-217", month=oct } + +@TechReport{GEMSOS91, +author={Gemini}, +Title={Programmer's Guide to the GEMSOS Security Kernel Interface}, +institution= {Gemini Computers, Inc.}, +address={Carmel, California}, month =jul, +Year=1991 } + +@InProceedings{King90, +Key = "", Author = "G. King", +Title = "Considerations for {VSLAN} Integrators and {DAAs}", +Booktitle = "Proceedings of the Thirteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1990", +Pages="201-210", month=oct } + +@InProceedings{Bell90, +Key = "", Author = "D.E. Bell", +Title = "Trusted {Xenix} Interpretation: Phase 1", +Booktitle = "Proceedings of the Thirteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1990", +Pages="333-339", month=oct } + +@InProceedings{WinklerJ90, +Key = "", Author = "J.R. Winkler", +Title = "A {Unix} Prototype for Intrusion and Anomaly Detection in +Secure Networks", +Booktitle = "Proceedings of the Thirteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1990", +Pages="115-124", month=oct } + +@InProceedings{Winkler90, +Key = "", Author = "H.B. Winkler-Parenty", +Title = "Trusted System Interoperability", +Booktitle = "Proceedings of the Thirteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1990", +Pages="567-569", month=oct } + +@InProceedings{Vetter90, +Key = "", Author = "L.L. Vetter", +Title = "Oracle Secure Systems: 1989-1990 A `Year in Review", +Booktitle = "Proceedings of the Thirteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1990", +Pages="570-571", month=oct } + +@InProceedings{Alstad+90, +Author = "J.P Alstad and C.M. Brophy and T.C. Vickers Benzel and M.M. Bernstein +and R.J. Feiertag", +Title = "The Role of {``System Build''} in Trusted Embedded Systems", +Booktitle = "Proceedings of the Thirteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1990", +Pages="172-181", month=oct } + +@article{Ramanathan90, +author={P. Ramanathan and K.G. Shin and R.W. Butler}, key= {Ramanathan}, +title = {Fault-Tolerant Clock Synchronization in Distributed Systems}, +journal = {Computer}, year = {1990}, volume = {23}, +number = {10}, pages = {33-42}, month = oct } + +@article{Manber90, +author={U. Manber}, key={Manber}, +title = {Chain Reactions in Networks}, +journal = {Computer}, year = {1990}, volume = {23}, +number = {10}, pages = {57-63}, month = oct } + +@InProceedings{Meadows90, +Key={Meadows}, Author={C. Meadows}, Title={Extending the Brewer-Nash + Model to a Multilevel Context}, +BookTitle={Proceedings of the 1990 Symposium on Research in +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1990}, Month=may, pages={95--102}} + +@InProceedings{Wray91, +Key={Wray}, Author={J.C. Wray}, Title={An Analysis of Covert Timing Channels}, +BookTitle={Proceedings of the 1991 Symposium on Research in +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1991}, Month=may, pages={2-7}} + +@InProceedings{Hu91, +Key={Hu}, Author={W.-M. Hu}, Title={Reducing Timing Channels with Fuzzy Time}, +BookTitle={Proceedings of the 1991 Symposium on Research in +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1991}, Month=may, pages={8-20}} + +@InProceedings{Gray91, +Key={Gray}, Author={J.W. {Gray III}}, Title={Toward a Mathematical +Foundation for Information Flow Security}, +BookTitle={Proceedings of the 1991 Symposium on Research in +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1991}, Month=may, pages={21-34}} + +@InProceedings{PorrasKemmerer91, +Key={Porras}, Author={P.A. Porras and R.A. Kemmerer}, Title={Analyzing +Covert Storage Channels}, BookTitle={Proceedings of the 1991 Symposium on Research in +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1991}, Month=may, pages={36-51}} + +@InProceedings{KargerWray91, +Key={Karger}, Author={P.A. Karger and J.C. Wray}, Title={Storage Channels +in Disk Arm Optimization}, BookTitle={Proceedings of the 1991 Symposium on Research in +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1991}, Month=may, pages={52-61}} + +@InProceedings{KargerKurth04, +Key={Karger}, Author={P.A. Karger and H. Kurth }, Title={Increased + Information Flow Needs for High-Assurance Composite Evaluations}, + BookTitle={Proceedings of the Second International Information Assurance + Workshop (IWIA 2004)}, + Organization={IEEE Computer Society}, Address={Charlotte, + North Carolina}, Year={2004}, Month=may, pages={129--140}} + +@InProceedings{Meadows91, +Key={Meadows}, Author={C. Meadows}, Title={A System for the Specification +and Analysis of Key Management Protocols}, +BookTitle={Proceedings of the 1991 Symposium on Research in +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1991}, Month=may, pages={}} + +@InProceedings{Tardo+91, +Key={Tardo}, Author={J.J. Tardo and K. Alagappan}, Title={{SPX}: Global +Authentication Using Public Key Certificates}, +BookTitle={Proceedings of the 1991 Symposium on Research in +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1991}, Month=may, pages={232-244}} + +@Manual{CCITT509, +Key="CCITT", Author={CCITT}, Title="{CCITT} Draft Recommendation {X.509}: +The Directory-Authentication Framework, version 7", +Year="November 1987", +Organization="{CCITT}, Gloucester" } + +@TECHREPORT{Abadi+Lamport:refinement, + AUTHOR = {M. Abadi and L. Lamport}, + TITLE = {The Existence of Refinement Mappings}, + INSTITUTION = {DEC Systems Research Center}, + YEAR = {1988}, NUMBER = {29}, ADDRESS = {Palo Alto, California}, + MONTH = aug } + +@INPROCEEDINGS{Lamport+Abadi89, + AUTHOR = {M. Abadi and L. Lamport}, + TITLE = {Composing Specifications}, + BOOKTITLE = {Stepwise Refinement of Distributed Systems: Models, Formalisms, Correctness}, + YEAR = {1989}, + EDITOR = {J.W. de Bakker and W.-P. de Roever and G. Rozenberg}, + PAGES = {1--41}, + PUBLISHER = {Springer-Verlag, Berlin, + Lecture Notes in Computer Science, vol.~230}, + ADDRESS = {REX Workshop, Mook, The Netherlands}, + MONTH = {May-June} +} + +@TechReport{Rushby91Composing, +author={J.M. Rushby}, +Title="Composing Trustworthy Systems", +institution="Computer Science Laboratory, SRI International", +address={Menlo Park, California}, month =jul, +Year=1991 } + +@techreport{Rushby92:intransitive-noninterference, +AUTHOR = {J.M. Rushby}, +TITLE = {Noninterference, Transitivity, and Channel-Control Security Policies}, +INSTITUTION = {Computer Science Laboratory, SRI International}, +NUMBER = {SRI-CSL-92-2}, +YEAR = {1992}, +ADDRESS = {Menlo Park, California}, MONTH = dec } + +@techreport{Rushby91:intransitive-verification, +AUTHOR = {J.M. Rushby}, +TITLE = {Formal Verification of the Unwinding Theorem for Intransitive +Noninterference Security Policies}, +INSTITUTION = {SRI Computer Science Laboratory}, YEAR = {1991}, +ADDRESS = {Menlo Park, California}, MONTH = mar } + +@InProceedings{McLean94, +Author={J. McLean}, +Title={A General Theory of Composition for Trace Sets Closed under Selective + Interleaving Functions}, +BookTitle={Proceedings of the 1994 Symposium on Research in +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1994}, Month=may, pages={79--93}} + +@InProceedings{Seagar+95, +Author={M. Seagar and D. Guaspari and M. Stillerman and C. Marceau}, +Title={Formal Methods in the Theta Kernel}, +BookTitle={Proceedings of the 1995 Symposium on +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1993}, Month=may, pages={88--100}} + +@InProceedings{Badger+95, +Author={L. Badger and D.F. Sterne and D.L. Sherman and K.M. Walker +and S.A. Haghighat}, +Title={Practical Domain and Type Enforcement for {Unix}}, +BookTitle={Proceedings of the 1995 Symposium on +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1993}, Month=may, pages={66--77}} + +@article{Spafford92, +author={E. Spafford}, title = {Are Computer Hacker Break-ins Ethical?}, +journal = {Journal of Systems and Software}, year = {1992}, volume = {}, +number = {}, pages = {}, month = jan, +note = {Purdue Report CSD-TR-994, March 1991} } + +@book{Petroski, +Author={H. Petroski}, +Title={To Engineer Is Human: The Role of Failure in Successful Design}, +Publisher={St.~Martin's Press, New York}, +Year={1985} } + +@book{Petroski94, +Author={H. Petroski}, +Title={Design Paradigms: Case Histories of Error and Judgment in Engineering}, +Publisher={Cambridge University Press, Cambridge, England}, +Year={1994} } + +@book{HoareCSP, +Author={C.A.R. Hoare}, +Title={Communicating Sequential Processes}, +Publisher={Prentice-Hall, Englewood Cliffs, New Jersey}, +Year={1985} } + +@article{Sinha91, +author={P.K. {Sinha et al.}}, title = {The {Galaxy} Distributed Operating +System}, journal = {Computer}, year = {1991}, volume = {24}, +number = {8}, pages = {34-41}, month = aug } + +@article{NitzbergLo91, +author={B. Nitzberg and V. Lo}, title = {Distributed Shared Memory: +A Survey of Issues and Algorithms}, +journal = {Computer}, year = {1991}, volume = {24}, +number = {8}, pages = {52-60}, month = aug } + +@article{Ousterhout88, +author={J.K. {Ousterhout et al.}}, +title = {The {Sprite} Network Operating System}, +journal = {Computer}, year = {1988}, volume = {21}, +number = {2}, pages = {23-36}, month = feb } + +@article{BakerOusterhout91, +author={M. Baker and J.K. Ousterhout}, +title = {Availability in the {Sprite} Distributed File System}, +journal = {ACM SIGOPS Operating Systems Review}, year = {1991}, volume = {25}, +number = {2}, pages = {95-98}, month = apr } + +@article{Yokote+91, +author={Y. Yokote and F. Teraoka and A. Mitsuzawa and N. Fujinami and M. Tokoro}, +title = {The {Muse} Object Architecture: a New Operating System +Structuring Concept}, +journal = {ACM SIGOPS Operating Systems Review}, year = {1991}, volume = {25}, +number = {2}, pages = {22-46}, month = apr } + +@article{KaashoekTanenbaum91, +author={M.F. Kaashoek and A.S. Tanenbaum}, +title = {Fault Tolerance Using Group Communication}, +journal = {ACM SIGOPS Operating Systems Review}, year = {1991}, volume = {25}, +number = {2}, pages = {71-74}, month = apr } + +@TechReport{Engler98, +author={D.R. Engler}, +Title="{The Exokernel Operating System Architecture}", +institution="Ph.D. Thesis, M.I.T., Cambridge, Massachusetts", +month=oct, +Year=1998 } + +@Article{Engler+95, +author={D.R. Engler and M.F. Kaashoek and J. {O'Toole Jr.}}, +title = {Exokernel: An Operating System Architecture for + Application-Level Resource Management}, +Journal = {Operating Systems Review}, year = {1995}, +Organization = {ACM}, +Note = {Proceedings of the Fifteenth Symposium on Operating + Systems Principles (SOSP '95)}, +volume = {29}, +number = {}, pages = {251--266}, month = dec } + +@ARTICLE{LubaCourtois98, +Author={M. Lubaszewski and B. Courtois}, +TITLE = {A Reliable Fail-Safe System}, +JOURNAL = {IEEE Transactions on Computers}, YEAR = {1998}, VOLUME = {C-47}, +NUMBER = {2}, PAGES = {236-241}, MONTH = feb } + +@ARTICLE{Blaum+98, +Author={M. Blaum and J. Bruck and K. Rubin and W. Lenth}, +TITLE = {A Coding Approach for Detection of Tampering in Write-Once +Optical Disks}, +JOURNAL = {IEEE Transactions on Computers}, YEAR = {1998}, VOLUME = {C-47}, +NUMBER = {1}, PAGES = {120--125}, MONTH = jan } + +@article{StephensonBirman91, +author={P. Stephenson and K. Birman}, +title = {Fast Causal Multicast}, +journal = {ACM SIGOPS Operating Systems Review}, year = {1991}, volume = {25}, +number = {2}, pages = {75-79}, month = apr } + +@article{CheritonV, +Author={D.R. Cheriton}, TITLE = {The {V} Distributed System}, +JOURNAL = {Communications of the ACM}, +YEAR = {1988}, VOLUME = {31}, NUMBER = {3}, PAGES = {314-333}, +MONTH = mar } + +@PhDThesis{RussoThesis, + Key={}, Author={V.F. Russo}, + Title={An Object-Oriented Operating System}, + School={Univ. of Illinois, Computer Science Dept}, + Year={1991}, Month=jan, Note={UIUCDCS-R-919-1640} +} + +@TechReport{Dykstra91, +author={D.W. Dykstra}, +Title={Hardware Enforced Protection for Object-Oriented Operating Systems}, +institution= {Univ. of Illinois, Computer Science Dept}, +address={Urbana-Champaign, IL}, month =mar, Year=1991, +Note={UIUCDCS-R-91-1666} } + +@TechReport{DykstraCampbell91, +author={D.W. Dykstra and R.H. Campbell}, +Title={Object-Oriented Hierarchies Across Protection Boundaries}, +institution= {Univ. of Illinois, Computer Science Dept}, +address={Urbana-Champaign, IL}, month =mar, Year=1991, +Note={UIUCDCS-R-919-1667} } + +@TechReport{CampbellMadany91, +author={R.H. Campbell and P.W. Madany}, +Title={Considerations of Persistence and Security in Choices, an +Object-Oriented Operating System}, +institution= {Univ. of Illinois, Computer Science Dept}, +address={Urbana-Champaign, IL}, month =mar, Year=1991, +note={UIUCDCS-R-91-1670} } + +@TechReport{JensenReed91, +author={D.W. Jensen and D.A. Reed}, +Title={File Archive Activity in a Supercomputer Environment}, +institution= {Univ. of Illinois, Computer Science Dept}, +address={Urbana-Champaign, IL}, month =apr, Year=1991, +note={UIUCDCS-R-91-1672} } + +@TechReport{Lu91, +author={S. Lu}, +Title={A Distributed Concurrency Control Protocol Considering + Read-Only Transactions}, +institution= {Univ. of Illinois, Computer Science Dept}, +address={Urbana-Champaign, IL}, month =apr, Year=1991, +note={UIUCDCS-R-91-1678} } + +@TechReport{Shi91, +author={S.-B. Shi}, +Title={Building Reliable Programs Through Active Replication}, +institution= {Univ. of Illinois, Computer Science Dept}, +address={Urbana-Champaign, IL}, month ={}, Year=1991, +note={UIUCDCS-R-91-1679} } + +@TechReport{Enc86, +author={Encore}, key={Encore}, +Title={{UMAX} 4.2 Programmer's Reference Manual}, +institution= {Encore Computer Corp.}, +address={Marlboro, Massachusetts}, month ={}, Year=1986 } + +@TechReport{Enc89, +author={Encore}, key={Encore}, +Title={Multimax Technical Summary}, +institution= {Encore Computer Corp.}, +address={Marlboro, Massachusetts}, month ={}, Year=1989 } + +@TechReport{DCICThreat89, +Author={DCIC}, +Title={Threat to Intelligence Community Automated +Information Systems and Networks}, +institution= {DCIC 10002-89}, +Month = {19 January}, Year = {1989}, Note={SECRET/NOFORN/WNINTEL.} } + +@TechReport{Hollway92, +Author={A. Hollway}, +Title={Worldwide Threat to Computers and Automated Control Systems}, +institution= {U.S. Army VAL FIO}, +Month = oct, Year = {1992}, Note={SECRET/NOFORN/WNINTEL.} } + +@TechReport{NIST92, +Author={D. Steinauer and M. Swanson}, +Title={Matrix Questions Answered at a National Level}, +institution= {NIST}, Month = {3 April}, Year = {1989}, +NOTE={Produced for the Survivability-Vulnerability Working Group.} } + +@InProceedings{Neumann97surv, +Author={P.G. Neumann and P.A. Porras}, +Title={A Global View of Information Survivability}, +BookTitle={Proceedings of the 1997 Workshop on Survivability}, +Organization={IEEE Computer Society}, Address={San Diego, California}, +Year={1997}, Month=feb, pages={}} + +@PhDThesis{Mounji97, +Author={A. Mounji}, +School={Notre-Dame de la Paix, Namur, Belgium}, +Title={Languages and Tools for Rule-Based Distributed Intrusion Detection}, +Year={1997}, Month=sep } + +@TechReport{DISA92, +Author={DISA}, +Title ={Security Analysis (Draft), Background Security Description and +Defense Message System Security Documentation Instructions}, +Institution = {Defense Information Systems Agency}, +Month=mar, Year={1992} } + +@TechReport{FriedmanOlson92, +Author={A.R. Friedman and I.M. Olson}, +Title={Introduction to Certification and Accreditation Concepts (Draft)}, +Institution={Mitre Corporation, under contract to the National Security Agency}, +Month=jun, Year={1992} } + +@Article{Munro92, +Author={N. Munro}, +Title={DoD Planners Prepare New Security Stategy}, +Journal={Defense News}, +Volume=7, Number=18, Month={4-10 May}, Year={1992} } + +@InProceedings{Corbato+72, +Author={F.J. Corbat\'{o} and J. Saltzer and C.T. Clingen}, +Title={Multics: {The} first seven years}, +Booktitle={Proceedings of the Spring Joint Computer Conference}, +volume=40, +publisher={AFIPS Press}, +address={Montvale, New Jersey}, +Year=1972 } + +@article{Corbato91, +Title="On Building Systems That Will Fail (1990 {T}uring {A}ward {L}ecture, +with a following interview by {Karen Frenkel})", +Author="F.J. Corbat\'{o}", Key="", Month=sep, +Year=1991, Journal= {Communications of the ACM}, Volume=34, Number=9, Pages="72-90" } + +@InProceedings{Bell91, +Author = "D.E. Bell", +Title = "Putting Policy Commonalities to Work", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="456-471 (Volume II)", month=oct } + +@InProceedings{Branstad+91, +Author="M.A. Branstad and C.P. Pfleeger and D. Brewer and C. Jahl and H. Kurth", +Title = "Apparent Differences Between the {U.S.} {TCSEC} and the {E}uropean +{ITSEC}", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="45-58 (Volume I)", month=oct } + +@InProceedings{FaganStraw91, +Author = "P. Fagan and J. Straw", +Title = "Experience of Commercial Security Evaluation", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="195-204", month=oct } + +@InProceedings{EpsteinPicciotto91, +Author = "J. Epstein and J. Picciotto", +Title = {Trusting {X}: Issues in Building Trusted {X} {Window} {Systems}}, +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="619-629", month=oct } + +@InProceedings{Faden91, +Author = "G. Faden", +Title = {Reconciling {CMW} Requirements with those of {X11} Applications}, +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="472-479", month=oct } + +@InProceedings{SandhuSuri91, +Author = "R.S. Sandhu and G.S. Suri", +Title = "A Distributed Impementation of the Transform Model", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="177-187", month=oct } + +@TechReport{Binns91, +author={L.J. Binns}, +Title={Inference Through Polyinstantiation}, +institution= {Office of INFOSEC Computer Science}, +address={U.S. Department of Defense, Ft. George G. Meade, Maryland}, month ={}, +Year=1991 } + +@InProceedings{SebesFeiertag91, +Author = "E.J. Sebes and R.J. Feiertag", +Title = "Trusted Distributed Computing: Using Untrusted Network Software", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="608-618", month=oct } + +@InProceedings{Parker91, +Author = "T.A. Parker", +Title = "A Secure {E}uropean System for Applications in a Multi-vendor +Environment ({T}he {SESAME} {P}roject)", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="505--513", month=oct } + +@InProceedings{GarveyLunt91, +Author = "T.D. Garvey and T.F. Lunt", +Title = "Model-Based Intrusion Detection", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="372--385", month=oct } + +@Article{Lunt93CS, +Author={T.F. Lunt}, Title={A survey of intrusion detection techniques}, +Journal={Computers and Security}, pages={405--418}, +volume=12, number={4}, year=1993 } + +@InProceedings{DIDS91, +Author = "S.R. Snapp and J. Brentano and G.V. Dias and T.L Goan and +L.T. Heberlein and C.-L. Ho and K.N. Levitt and B. Mukherjee and +S. Smaha and T. Grance and D.M. Teal and D. Mansur", +Title = "{DIDS (Distributed Intrusion Detection System)} -- +Motivation, Architecture, and an Early Prototype", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="167--176", month=oct } + +@InProceedings{Heberlein+91, +Author = "L.T. Heberlein and K.N. Levitt and B. Mukherjee", +Title = "A Method to Detect Intrusive Activity in a Networked Environment", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="362--371", month=oct } + +@InProceedings{Banning+91, +Author = "D. Banning and G. Ellingwood and C. Franklin and C. Muckenhirn and +D. Price", +Title = "Auditing of Distributed Systems", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="59--68", month=oct } + +@InProceedings{Jackson+91, +Author = "K.A. Jackson and D.H. DuBois and C.A. Stallings", +Title = "An Expert System Application for Network Intrusion Detection", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="215--225", month=oct } + +@InProceedings{King91, +Author = "M.M. King", +Title = "Identifying and Controlling Undesirable Program Behaviors", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="283--294", month=oct } + +@InProceedings{ParkerDB91, +Author = "D.B. Parker", +Title = "Restating the Foundations of Information Security", +Booktitle = "Proceedings of the Fourteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Washington, D.C.", Year = "1991", +Pages="", month=oct } + +@TechReport{Irvine+91, +author={C.E. Irvine and R.R. Schell and M.F. Thompson}, +Title={Using {TNI} Concepts for the Near Term Use of High Assurance +Database Management Systems}, +institution= {Gemini Computers, Inc.}, +address={Carmel California}, month ={}, +Year=1991, Note={Presented at the 1991 Rome Laboratory Database Security Workshop} } + +@ARTICLE{DeTreville, +Author={J. DeTreville}, TITLE = {A Cautionary Tale}, +JOURNAL = {ACM Software Engineering Notes}, YEAR = {1991}, VOLUME = {16}, +NUMBER = {2}, PAGES = {19--22}, MONTH = apr } + +@ARTICLE{XuParnas91, +Author={J. Xu and D. Parnas}, TITLE = {On Satisfying Timing Constraints in +Hard-Real-Time Systems}, +JOURNAL = {ACM Software Engineering Notes}, YEAR = {1991}, VOLUME = {16}, +NUMBER = {5}, PAGES = {132--146}, MONTH = dec } + +@InProceedings{Parnas94, +Author = {D.L. Parnas}, +Title = {Mathematical Descriptions and Specification of Software}, +Booktitle = {Proceedings of the IFIP World Congress 1994, Volume I}, +Organization = {IFIP}, Address = {}, +Year = {1994}, +Pages={354--359}, Month = aug } + +@InProceedings{ParnasRespons94, +Author = {D.L. Parnas}, +Title = {Professional Responsibilities of Software Engineers}, +Booktitle = {Proc. of IFIP World Congress 1994, Volume II}, +Organization = {IFIP}, Address = {}, +Year = {1994}, +Pages={332--339}, Month = aug } + +@ARTICLE{Parnas+94, +Author={D.L. Parnas and J. Madey and M. Iglewski}, +TITLE = {Precise Documentation of Well-Structured Programs}, +JOURNAL = {IEEE Transactions on Software Engineering}, YEAR = {1994}, +VOLUME = {20}, +NUMBER = {12}, PAGES = {948--976}, MONTH = dec } + +@article{Parnas+94b, +author={D.L. Parnas and A.J. {van Schouwen} and S.P. Kwan}, +title = {Evaluation of Safety-Critical Software}, +journal = {Communications of the ACM}, volume = {33}, number = {6}, +pages = {636--648}, month = jun, year = {1990} } + +@article{ParnasWang94, +Author = {D.L. Parnas and Y. Wang}, +Title={Simulating the Behaviour of Software Modules by + Trace Rewriting Systems}, +Journal = {IEEE Transactions of Software Engineering}, +VOLUME = {19}, NUMBER = {10}, +Month = oct, Year = {1994}, PAGES = {750--759} } + +@article{Parnas97SE, +author={D.L. Parnas}, +title = {Software Engineering: An Unconsummated Marriage}, +journal = {Communications of the ACM}, year = {1997}, volume = {40}, +number = {9}, pages = {128}, month = sep, +Note= {{\it Inside Risks} column.} } + +@article{DenningDivorce, +author={D.L. Parnas}, +title = {Computer Science and Software Engineering: Filing for Divorce?}, +journal = {Communications of the ACM}, year = {1998}, volume = {41}, +number = {8}, pages = {}, month = aug, +Note= {{\it Inside Risks} column.} } + +@ARTICLE{RushbyvonHenke91, +Author={J.M. Rushby and F. {von Henke}}, TITLE = {Formal Verification of +Algorithms for Critical Systems}, +JOURNAL = {ACM Software Engineering Notes}, YEAR = {1991}, VOLUME = {16}, +NUMBER = {5}, PAGES = {1--15}, MONTH = dec } + +@TechReport{Rushby+95PVS, +author={J.M. Rushby and D.W.J. Stringer-Calvert}, +Title={A less elementary tutorial for the {PVS} specification and + verification system}, +institution= {SRI International, Menlo Park, California, CSL-95-10}, +address={}, month =oct, Year=1995 } + +@TechReport{Rushby95FMAir, +author={J.M. Rushby}, +Title={Formal Methods and Their Role in Digital Systems Validation +for Airborne Systems}, +institution= {SRI International, Menlo Park, California, CSL-95-01}, +address={}, month =mar, Year=1995 } + +@TechReport{Rushby95KerVer, +author={J.M. Rushby}, +Title={A Foundation for Security Kernel Verification}, +institution= {SRI International, Menlo Park, California}, +address={}, month =oct, Year=1995 } + +@TECHREPORT{Rushby99:partitioning, + AUTHOR = {J. Rushby}, + TITLE = {Partitioning for Avionics Architectures: + Requirements, Mechanisms, and Assurance}, + INSTITUTION={NASA Langley Research Center}, + NOTE = {Contractor Report CR-1999-209347; also issued as + FAA DOT/FAA/AR-99/58.}, + MONTH = jun, + YEAR = "1999", + url ="http://www.csl.sri.com/~{}rushby/abstracts/partitioning"} + +@TECHREPORT{Rushby01:modcert, + AUTHOR = {J. Rushby}, + TITLE = {Modular Certification}, + INSTITUTION="Computer Science Laboratory, SRI International, Menlo Park, + California", + MONTH = jun, + YEAR = 2002, + url ="http://www.csl.sri.com/~{}rushby/abstracts/modcert"} + +@TECHREPORT{Rushby04:separation, + AUTHOR = {J. Rushby}, + TITLE = {A separation kernel formal security policy in PVS}, + INSTITUTION="Computer Science Laboratory, SRI International, Menlo Park, + California", + MONTH = mar, + YEAR = 2004, + url ="http://www.csl.sri.com/~{}rushby/abstracts/"} + +@TechReport{Butler93, +author={R.W. Butler}, +Title={An elementary tutorial on formal specification and verification + using {PVS}}, +institution= {NASA Langley Research Center}, +address={Hampton, Virginia}, month =jun, Year=1993 } + +@InProceedings{Butler+95, +Author={R.W. Butler and J.L. Caldwell and V.A. {Carre\~{n}o} and +C.M. Holloway and P.S. Miner and B.L. DiVito}, +TITLE = {{NASA} {Langley's} Research and Technology-Transfer Program + in Formal Methods}, +BookTitle={Proceedings of the Tenth Annual Conference on Computer +Assurance, COMPASS 95}, Organization={IEEE}, Year=1995, Month=jun, +Pages={135--149}, + NOTE = {(A longer version is available in {\it Proceedings of +the Third NASA Langley Formal Methods Workshop,} May 1995, 247--268.)} +} + +@InProceedings{Butler+95o, +Author={R.W. Butler and J.L. Caldwell and V.A. {Carre\~{n}o} and +C.M. Holloway and P.S. Miner and B.L. DiVito}, +TITLE = {{NASA} {Langley's} Research and Technology-Transfer Program + in Formal Methods}, +BookTitle={Proceedings of the Third NASA {Langley} Formal Methods Workshop, +May 10-12, 1995}, +ORGANIZATION={NASA Langley Research Center}, +Year=1995, Month= jun, +Note = {This is a longer but earlier version of~\cite{Butler+95}, +and includes 28 more references.}, +Pages={247--268}} + +@Proceedings{NASALaRC95, +Editor={C.M. Holloway}, +Title={Third {NASA} {Langley} Formal Methods Workshop}, +ORGANIZATION={NASA Langley Research Center}, +Address ={Hampton, Virginia}, +Month={May 10-12}, +Note ={NASA Conference Publication 10176, June 1995.}, +Year={1995} } + +@book{NASA95-1, +Author={{NASA Langley Research Center}}, +Title={Formal Methods Specification and Verification, Volume I}, +Publisher={NASA}, +Month =jun, Year={1995} } + +@book{NASA95-2, +Author={{NASA Langley Research Center}}, +Title={Formal Methods Specification and Verification, Volume II}, +Publisher={NASA}, +Month ={Fall}, Year={1995} } + +@ARTICLE{ButlerFinelli91, +Author={R.W. Butler and G.B. Finelli}, TITLE = {The Infeasibility of +Experimental Quantification of Life-Critical Software Reliability}, +JOURNAL = {ACM Software Engineering Notes}, YEAR = {1991}, VOLUME = {16}, +NUMBER = {5}, PAGES = {66--76}, MONTH = dec } + +@book{Spivey88, +Author={J.M. Spivey}, +Title={Understanding Z: a specification language and its formal semantics}, +Publisher={Cambridge University Press, Cambridge, England}, +Year={1988} } + +@book{Potter91, +Author={B. Potter and J. Sinclair and D. Till}, +Title={An Introduction to Formal Specification and Z}, +Publisher={Prentice-Hall International, Hemel Hempstead, Great Britain}, +Year={1991} } + +@book{Turner93, +Author={K. J. {Turner, ed.}}, +Title={Using Formal Description Languages}, +Publisher={John Wiley, Chichester}, +Year={1993} } + +@InProceedings{Jirach95, +Author={A. Jirachiefpattana and R. Lai}, +TITLE = {An {Estelle-NPN} based system for protocol verification}, +BookTitle={Proceedings of the Tenth Annual Conference on Computer +Assurance, COMPASS 95}, Organization={IEEE}, Year=1995, Month=jun, +Pages={245--259}} + +@Article{HarelKurshan90, +Author = {Z. {Har'El} and R.P. Kurshan}, +TITLE = {Software for Analytic Development of Communications Protocols}, +JOURNAL = {AT\&T Technical Journal}, +YEAR = {1990}, VOLUME = {69}, MONTH = {January-February}, NUMBER = {1}, +PAGES = {45--59} } + +@TechReport{Craigen+93, +Author={D. Craigen and S. Gerhart and T. Ralston}, +TITLE = {An International Survey of Industrial Applications of Formal Methods}, +institution= {U.S. National Institute of Standards and Technology}, +Note = {Also available from U.S. Naval Research Laboratory and the Atomic +Energy Board of Canada.}, +address={Gaithersburg, Maryland}, month =mar, Year=1993 } + +@ARTICLE{Boswell95, +Author={A. Boswell}, +TITLE = {Specification and Validation of a Security Policy Model}, +JOURNAL = {IEEE Transactions on Software Engineering}, +NOTE = {Special section on Formal Methods Europe '93.}, +YEAR = {1995}, VOLUME = {21}, MONTH = feb, NUMBER = {2}, +PAGES = {63--69} } + +@ARTICLE{Barrett95, +Author={G. Barrett}, +TITLE = {Model Checking in Practice: The T9000 Virtual Channel Processor}, +JOURNAL = {IEEE Transactions on Software Engineering}, +NOTE = {Special section on Formal Methods Europe '93.}, +YEAR = {1995}, VOLUME = {21}, MONTH = feb, NUMBER = {2}, +PAGES = {69--78} } + +@ARTICLE{BicarreguiRitchie95, +Author={J. Bicarregui and B. Ritchie}, +TITLE = {Invariants, Frames, and Postconditions: +A Comparison of the {VDM} and {B} Notations}, +JOURNAL = {IEEE Transactions on Software Engineering}, +NOTE = {Special section on Formal Methods Europe '93.}, +YEAR = {1995}, VOLUME = {21}, MONTH = feb, NUMBER = {2}, +PAGES = {79--89} } + +@ARTICLE{Craigen+95, +Author={D. Craigen and S. Gerhart and T. Ralston}, +TITLE = {Formal Methods Reality Check: Industrial Usage}, +JOURNAL = {IEEE Transactions on Software Engineering}, +NOTE = {Special section on Formal Methods Europe '93.}, +YEAR = {1995}, VOLUME = {21}, MONTH = feb, NUMBER = {2}, +PAGES = {90--98} } + +@ARTICLE{Jacky95, +Author={J. Jacky}, +TITLE = {Specifying a Safety-Critical Control System in {Z}}, +JOURNAL = {IEEE Transactions on Software Engineering}, +NOTE = {Special section on Formal Methods Europe '93.}, +YEAR = {1995}, VOLUME = {21}, MONTH = feb, NUMBER = {2}, +PAGES = {99-106} } + +@ARTICLE{Owre+95, +Author={S. Owre and J. Rushby and N. Shankar and F. {von Henke}}, +TITLE = {Formal Verification for Fault-Tolerant Architectures: + Prolegomena to the Design of {PVS}}, +JOURNAL = {IEEE Transactions on Software Engineering}, +NOTE = {Special section on Formal Methods Europe '93.}, +YEAR = {1995}, VOLUME = {21}, MONTH = feb, NUMBER = {2}, +PAGES = {107-125} } + +@techreport{PVS:Interpretations, + Author= {S. Owre and N. Shankar}, + Title= {Theory Interpretations in {PVS}}, + Number= {SRI-CSL-01-01}, + Institution= {Computer Science Laboratory, SRI International}, + Address= {Menlo Park, CA}, + Month= apr, + Year= {2001}, +NOTE="\xlink{http://www.csl.sri.com/\~{}owre}{http://www.csl.sri.com/\~{}owre}" + } + +@ARTICLE{MoriconiQian94, +Author={M. Moriconi and X. Qian}, +TITLE = {Correctness and Composition of Software Architectures}, +JOURNAL = {ACM Software Engineering Notes}, YEAR = {1994}, VOLUME = {19}, +NUMBER = {5}, PAGES = {164--174}, MONTH = dec, +NOTE = {Proceedings of the Second ACM SIGSOFT Symposium on Foundations +of Software Engineering} } + +@ARTICLE{Moriconi+95, +Author={M. Moriconi and X. Qian and R.A. Riemenschneider}, +TITLE = {Correct Architecture Refinement}, +JOURNAL = {IEEE Transactions on Software Engineering}, +YEAR = {1995}, VOLUME = {21}, MONTH = apr, NUMBER = {4}, +PAGES = {356--372} } + +@TechReport{IntegrityWG91, +author={M.D. Abrams and E. Amoroso and L.J. LaPadula and T.F. Lunt and +J.N. Williams}, +Title={Report of an Integrity Working Group}, +institution= {Mitre Corp. (Abrams)}, +address={McLean, Virginia}, month =nov, +Year=1991 } + +@TechReport{JonesKluepfel92, +author={A. Jones and H.M. Kluepfel}, +Title={A Systems Engineering Approach to Security Baselines for {SS7}: +A contribution in support of {Network Operations Forum, Issue} 138 -- +{SS7} Network Integrity-Security}, institution= {Pac$\star$Bell and Bellcore}, +address={}, month ={}, Year=1992 } + +@TechReport{DISSP91, +author={DISSPO}, key = {DISSP}, +Title={Defense-Wide Information Systems Security Program {(DISSP)}, Action Plan}, +institution= {Defense-Wide Information Systems Security Program Office}, +note= {6 volumes, Prepared for the Assistant Secretary of Defense for Command, +Control, Communications, and Intelligence.}, +address={}, month ={15 August}, Year=1991 } + +@book{Golde76, +Author={R.A. Golde}, +Title={{Muddling Through}: The Art of Properly Unbusinesslike Management}, +Publisher={AMACOM (a division of the American Management Associations), +New York}, +note={ISBN 0-8144-5411-9, 0-8144-7523-X paperback}, +Year={1976} } + +@book{Mander78, +Author={J. Mander}, +Title={Four Arguments for the Elimination of Television}, +Publisher={William Morrow/Quill, New York}, +Year={1978} } + +@book{Mander92, +Author={J. Mander}, +Title={In the Absence of the Sacred: The Failure of Technology \& +the Survival of the {Indian} {Nations}}, +Publisher={Sierra Club Books, San Francisco, California}, +isbn={0-87156-509-9.}, +Year={1991, paperback 1992}} + +@book{Perrow, +Author={C. Perrow}, +Title={Normal Accidents}, +Publisher={Basic Books, New York}, +Year={1984} } + +@book{Norman88, +Author={D.A. Norman}, +Title={The Psychology of Everyday Things}, +Publisher={Basic Books, New York}, +Year={1988} } + +@article{Norman90, +Title= {Human error and the design of computer systems}, +Author={D.A. Norman}, Month=jan, +Year=1990, Journal= {Communications of the ACM}, Volume=33, Number=1, Pages="4--5,7" } + +@article{Denning90, +Title= {Human error and the search for blame}, +Author={P.J. Denning}, Month=jan, +Year=1990, Journal= {Communications of the ACM}, Volume=33, Number=1, Pages="6--7" } + +@article{Denning93Sense, +Title= {Designing new principles to sustain research in our universities}, +Author={P.J. Denning}, Month=jul, +Year=1993, Journal= {Communications of the ACM}, Volume=36, Number=7, Pages="98-104" } + +@InProceedings{Denning91NCCV, +Author={D.E. Denning}, TITLE = {Responsibility and blame in computer security}, +Booktitle = {Proceedings of the National Conference on Computing and Values}, +Organization = {Southern Connecticut State University, New Haven, +Connecticut}, Year = {1991}, Pages={}, Month = {12--16 August} } + +@Article{Denning93AmSci, +Author={D.E. Denning}, +Title={The {Clipper} Encryption System}, Journal={American Scientist}, +volume=81, number=4, month={July-August}, pages={319-323}, year=1993 } + +@article{Kent93, +Title= {Internet Privacy Enhanced Mail}, +Author={S.T. Kent}, Month=aug, +Year=1993, Journal= {Communications of the ACM}, Volume=36, Number=8, Pages="48--60" } + +@TechReport{Synergy93, +author={O.S. Saydjari and S.J. Turner and D.E. Peele and J.F. Farrell +and P.A. Loscocco and W. Kutz and G.L. Bock}, +Title={Synergy: A distributed, microkernel-based security architecture}, +institution= {NSA INFOSEC Research and Technology}, +address={}, month ={November 22}, Year=1993 } + +@article{Rotenberg93, +Title= {Communications Privacy: Implications for Network Design}, +Author={M. Rotenberg}, Month=aug, +Year=1993, Journal= {Communications of the ACM}, Volume=36, Number=8, Pages="61--68" } + +@article{Tuerkheimer93, +Title= {The Underpinnings of Privacy Protection}, +Author={Tuerkheimer}, Month=aug, +Year=1993, Journal= {Communications of the ACM}, Volume=36, Number=8, Pages="69--73" } + +@book{Pfleeger89, +Author={C.P. Pfleeger}, Title={Security in Computing}, +Publisher={Prentice-Hall, Englewood Cliffs, New Jersey}, Year={1989} } + +@book{Pfleeger96, +Author={C.P. Pfleeger}, Title={Security in Computing}, +Publisher={Prentice-Hall, Englewood Cliffs, New Jersey}, Year={1996}, +Note ={Second edition} +} + +@book{SLPfleeger98x, +Author={S.L. Pfleeger}, +Title={Software Engineering: The Production of Quality Software}, +Publisher={Prentice-Hall, Englewood Cliffs, New Jersey}, Year={1998} } + +@book{SLPfleeger98, +Author={S.L. Pfleeger}, +Title={Software Engineering: Theory and Practice}, +Publisher={Prentice-Hall, Englewood Cliffs, New Jersey}, Year={1998} } + +@book{BloomBecker, +Author={B. BloomBecker}, +Title={Spectacular Computer Crimes: What They Are and How They Cost American +Business Half a Billion Dollars a Year}, +Publisher={Dow Jones--Irwin, New York}, Year={1990} } + +@book{Wiener93, +Author={L. Wiener}, +Title={Digital Woes: Why We Should Not Depend on Software}, +Publisher={Addison--Wesley, Reading, Massachusetts}, +Year={1993} } + +@book{Casey93, +Author={S.M. Casey}, +Title={Set Phasers on Stun, and Other True Tales +of Design Technology and Human Error}, +Publisher={Aegean Publishing Company, Santa Barbara, California}, +Year={1993} } + +@book{Talbott94, +Author={S. Talbott}, +Title={The Future Does Not Compute}, +Publisher={O'Reilly \& Associates, Sebastopol, California 95472}, +Year={1994} } + +@book{Neuromancer, +Author={W. Gibson}, +Title={Neuromancer}, +Publisher={Ace Books}, +note = {ISBN 0-441-56959-5, reprinted as ISBN 0-932096-41-7}, +Year={1948}, Note={Reprinted by Phantasia Press, 1986.} } + +@ARTICLE{AsimovRobots, +Author={I. Asimov}, TITLE = {Runaround}, +JOURNAL = {Astounding Science Fiction}, YEAR = {1941}, VOLUME = {}, +NUMBER = {}, PAGES = {}, MONTH = apr, +NOTE={Also anthologized in {\it I, Robot} and {\it The Complete Robot.} } } + +@book{AsimovRobots0, +Author={I. Asimov}, +Title={Forward the Foundation}, +Publisher={Doubleday, New York}, +isbn={0-553-56507-9}, +Year={1993}, Note={Also Bantam paperback, 1994.} } + +@book{Sterling92, +Author={B. Sterling}, +Title={The Hacker Crackdown: Law and Disorder on the Electronic Frontier}, +Publisher={Bantam, New York}, +isbn={0-553-56370-X}, +Year={1992 (paperback 1993)} } + +@book{Borenstein91, +Author={N.S. Borenstein}, +Title={Programming As If People Mattered: Friendly Programs, Software +Engineering, and Other Noble Delusions}, +Publisher = {Princeton University Press, Princeton, New Jersey}, +Year={1991} } + +@book{Gall75, +Author={J. Gall}, +Title={Systemantics: How Systems Work and Especially How They Fail}, +Publisher={Quadrangle/New York Times Book Co., New York}, Year={1977}, +Note = {Also, Pocket Books, New York, 1975} } + +@book{Gall86, +Author={J. Gall}, +Title={Systemantics : The Underground Text of Systems Lore : How Systems + Really Work and Especially How They Fail}, +Publisher={General Systemantics Press, 3200 W. Liberty, Ann Arbor 48103}, +Year={1986} } + +@book{Illuminatus, +Author={R.J. Shea and R.A. Wilson}, +Title={The Illuminatus! Trilogy}, +Publisher={Dell, New York}, +Year={1975} } + +@book{PirsigZen, +Author={R.M. Pirsig}, +Title={Zen and the Art of Motorcycle Maintenance}, +Publisher={William Morrow and Bantam Books, New York}, +Year={1974} } + +@book{PirsigLila, +Author={R.M. Pirsig}, +Title={Lila, An Inquiry into Morals}, +Publisher={Bantam Books, New York}, +Year={1991} } + +@book{Papert93, +Author={S. Papert}, +Title={The Children's Machine: Rethinking School in the Age of the Computer}, +Publisher={Basic Books, New York}, Year={1993} } + +@book{Swasy93, +Author={A. Swasy}, +Title={Soap Opera: The Inside Story of Proctor \& Gamble}, +Publisher={Times Books, New York}, +Year={1993} } + +@book{Formaini90, +Author={R. Formaini}, +Title={The Myth of Scientific Public Policy}, +Publisher={Transaction Publishers (Social Philosophy \& Policy Center), +New Brunswick, New Jersey}, +isbn={0-88738-852-3}, +Year={1990} } + +@book{Beck92, +Author={U. Beck}, Title={Risk Society: Towards a New Modernity}, +Publisher={Sage Publications, Beverly Hills, California}, Year={1992}, +isbn={0-8039-8346-8}} + +@book{Unger94, +Author={S.H. Unger}, +Title={Controlling Technology: Ethics and the Responsible Engineer}, +Publisher={John Wiley and Sons, New York, 2nd ed.}, +Year={1994}, isbn={0-471-59181-5.} } + +@book{Asseline, +Author={M. Asseline}, +Title={Le pilote --- est-il coupable? (The Pilot: Is He To Blame?)}, +Publisher={Edition \#1 (4, rue Galleria, 75116 Paris)}, +Year={1992}, isbn={2-86-39-1517-7.} } + +@article{Weingarten94, +Title= {Public Interest and the {NII}}, +Author={F.W. Weingarten}, Month=mar, Year=1994, +Journal= {Communications of the ACM}, Volume=37, Number=3, Pages="17--19" } + +@book{Kling95, +Author={R. {Kling (ed.)}}, +Title={Computerization and Controversy: Value Conflicts and Social Choices}, +Publisher={Academic Press, New York}, +Year={1995} } + +@book{Firewalls94, +Author={W.R. Cheswick and S.M. Bellovin}, +Title={Firewalls and Internet Security: Repelling the Wily Hacker}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={1994} } + +@book{Firewalls03, +Author={W.R. Cheswick and S.M. Bellovin and A.D. Rubin}, +Title={Firewalls and Internet Security: Repelling the Wily Hacker, + Second Edition}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={2003} } + +@InProceedings{Blaze93, +Author={M. Blaze}, TITLE = {A Cryptographic File System for {UNIX}}, +Booktitle = {First ACM Conference on Computer and Communications Security}, +Organization = {ACM SIGSAC}, Address = {Fairfax, Virginia}, +Year = {1993}, +Pages={9--16}, Month = nov } + +@InProceedings{Blaze94, +Author={M. Blaze}, TITLE = {Protocol failure in the escrowed encryption +standard}, +Booktitle = {Second ACM Conference on Computer and Communications Security}, +Organization = {ACM SIGSAC}, Address = {Fairfax, Virginia}, +Year = {1994}, +Pages={59-67}, Month = nov } + +@InProceedings{Reiter94, +Author={M.K. Reiter}, TITLE = {Reliable and Atomic Group Multicast +in {Rampart}}, +Booktitle = {Second ACM Conference on Computer and Communications Security}, +Organization = {ACM SIGSAC}, Address = {Fairfax, Virginia}, +Year = {1994}, +Pages={68--80}, Month = nov } + +@TechReport{Landau94, +Author={S. Landau and S. Kent and C. Brooks and S. Charney and D. Denning +and W. Diffie and A. Lauck and D. Miller and P. Neumann and D. Sobel}, +TITLE = {Codes, Keys, and Conflicts: Issues in {U.S.} Crypto Policy}, +INSTITUTION = {ACM}, YEAR = {1994}, MONTH = jun } + +@ARTICLE{Landau94s, +Author={S. Landau and S. Kent and C. Brooks and S. Charney and D. Denning +and W. Diffie and A. Lauck and D. Miller and P. Neumann and D. Sobel}, +TITLE = {Crypto Policy Perspectives}, +JOURNAL = {Communications of the ACM}, YEAR = {1994}, VOLUME = {37}, +NUMBER = {8}, PAGES = {115-121}, MONTH = aug } + +@TechReport{Landau94x, +Author={S. Landau and S. Kent and C. Brooks and S. Charney and D. Denning +and W. Diffie and A. Lauck and D. Miller and P. Neumann and D. Sobel}, +TITLE = {Codes, Keys, and Conflicts: Issues in {U.S.} Crypto Policy}, +INSTITUTION = {ACM}, YEAR = {1994}, MONTH = jun, NOTE = +{A summary of this report by the same authors is available as ``Crypto Policy +Perspectives'' in the {\it Communications of the ACM, 37,} 8, 115-121, +August 1994.} } + +@InProceedings{Anderson94, +Author={R. Anderson}, Title={A Note on Correlation Attacks}, +BookTitle={Proceedings of the 1994 Leuven conference}, +Organization={}, Address={Leuven}, +Year={1994}, Month=dec, pages={}} + +@InProceedings{AndersonKuhn96, +Author={R. Anderson and M. Kuhn}, +Title={Tamper Resistance --- a Cautionary Note}, +BookTitle={Proceedings of the Second Usenix Workshop on Electronic Commerce}, +Organization={USENIX}, Address={}, +url={http://www.cl.cam.ac.uk/users/rja14/tamper.html}, +Year={1996}, Month=nov, pages={1--11}} + +@TechReport{Boneh+95, +author={D. Boneh and R.A. DeMillo and R.J. Lipton}, +Title={}, +institution= {Princeton University}, +month ={}, Year=1995 } + +@Article{Boneh+97, +Author={D. Boneh and R.A. DeMillo and R.J. Lipton}, +Title={On the Importance of Checking Cryptographic Protocols for Faults}, +Journal={Journal of Cryptology}, +Volume = {14}, Number = {2}, +Year={1997}, Month={}, pages={101--119}, +url ="http://www.stanford.edu/\~{}dabo/abstracts/faults.html"} + +@TechReport{Kocher95, +author={P. Kocher}, +Title={Cryptanalysis of {Diffie-Hellman, RSA, DSS,} and +Other Systems Using Timing Attacks (extended abstract)}, +institution= {Cryptography Research Inc.}, +address={607 Market St, San Francisco, California 94105}, +month ={December 7}, Year=1995 } + +@InProceedings{Kocher96, +Author={P.C. Kocher}, +Title={Timing Attacks on Implementations of {Diffie-Hellman}, +{RSA}, {DSS}, and Other Systems}, +BookTitle={Springer-Verlag, Berlin, + Lecture Notes in Computer Science, Advances in Cryptology, +Proceedings of Crypto '96}, +Organization={}, Address={Santa Barbara, California}, +Year={1996}, Month=aug, pages={104--113}} + +@InProceedings{AsonovAgrawal04, +Author={D. Asonov and R. Agrawal}, +Title={Keyboard Acoustic Emanations}, +BookTitle={Proceedings of the 2004 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2003}, Month=may, pages={3--11}} + +@ARTICLE{ShamirTromer04, +Author={A. Shamir and E. Tromer}, +TITLE = {Acoustic cryptanalysis: On nosy people and noisy machines}, +JOURNAL = {preliminary proof-of-concept presentation}, +YEAR = {2004}, VOLUME = {}, NUMBER = {}, PAGES = {}, MONTH = {}, +url ="http://www.wisdom.weizmann.ac.il/\~{}tromer/acoustic/" } + +@book{DES-crack, +Author={Electronic Frontier Foundation}, +Title={Cracking {DES}: Secrets of Encryption Research, Wiretap + Politics \& Chip Design}, +Publisher={O'Reilly and Associates, Sebastopol, California}, +Year={1998}, +Note = {See also the Risks Forum, volume 19, number 87, 17 July 1998.} } + +@InProceedings{PetersenMichels97, +Author={H. Petersen and M. Michels}, +Title={On Signature Schemes with Threshold Verification + Detecting Malicious Verifiers}, +BookTitle={Springer-Verlag, Berlin, + Lecture Notes in Computer Science, Security Protocols, +Proceedings of 5th International Workshop}, +Organization={}, Address={Paris, France}, +Year={1997}, Month=apr, pages={67--77}} + +@InProceedings{Kelsey+97, +Author={J. Kelsey and B. Schneier and D. Wagner}, +Title={Protocol Interactions and the Chosen Protocol Attacks}, +BookTitle={Springer-Verlag, Berlin, + Lecture Notes in Computer Science, Security Protocols, +Proceedings of 5th International Workshop}, +Organization={}, Address={Paris, France}, +Year={1997}, Month=apr, pages={91--104}} + +@InProceedings{Bao+97, +Author={F. Bao and R.H. Deng and Y. Han and A. Jeng and A.D. Narasimhalu + and T. Ngair}, +Title={Breaking Public Key Cryptosystems on Tamper Resistant Devices + in the Presence of Transient Faults}, +BookTitle={Springer-Verlag, Berlin, + Lecture Notes in Computer Science, Security Protocols, +Proceedings of 5th International Workshop}, +Organization={}, Address={Paris, France}, +Year={1997}, Month=apr, pages={115---123}} + +@InProceedings{AndersonKuhn97, +Author={R. Anderson and M. Kuhn}, +Title={Low Cost Attacks on Tamper Resistant Devices}, +BookTitle={Springer-Verlag, Berlin, + Lecture Notes in Computer Science, Security Protocols, +Proceedings of 5th International Workshop}, +Organization={}, Address={Paris, France}, +Year={1997}, Month=apr, pages={125--136}} + +@InProceedings{Zabarsky98, +Author={J. Zabarsky}, +Title={Failure Recovery for Distributed Processes in Single System Image + Clusters}, +BookTitle={Springer-Verlag, Berlin, + Lecture Notes in Computer Science, vol.~1388, + Parallel and Distributed Processing}, +Organization={}, Address={Berlin, Germany}, +Year={1998}, Month=apr, pages={564--583}} + +@book{RSI, +Author={Emil Pascarelli and Deborah Quilter}, +Title={Repetitive Strain Injury: A Computer User's Guide}, +Publisher={John Wiley and Sons, New York}, +Year={1994} } + +@InProceedings{Parker94, +Author = "D.B. Parker", +Title = "Demonstrating the Elements of Information Security with Threats", +Booktitle = "Proceedings of the Seventeenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1994", +Pages="", Month = "11-14 October" } + +@InProceedings{NISSC95N, +Author = "P.G. Neumann", +Title = "The Future of Formal Methods for Security: Overview statement", +Booktitle = "Proceedings of the Eighteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1995", +Pages="", month=oct } + +@TechReport{NeumannBoucher96, +author={P.G. Neumann and P. Boucher}, +Title={An Evaluation of the Security aspects of the {Army Technical +Architecture (ATA)} Document Drafts}, +institution= {Computer Science Laboratory, SRI International}, +Note = {Final report, SRI Project 7104-200, for U.S. Army CECOM, +Fort Monmouth, New Jersey}, +address={Menlo Park, California}, month ={2 January}, Year=1996 } + +@inProceedings{Neumann96CRC, +key="Neumann",Author="P.G. Neumann", Title="Security and Privacy Issues +in Computer and Communication Systems", +Booktitle="The Computer Science and Engineering Handbook (Chapter 89))", +Note =" (A.B. Tucker, ed.)", Publisher ="CRC Press, Inc.",Year="1996",Pages=""} + +@inProceedings{Neumann03CRC, +key="Neumann",Author="P.G. Neumann", Title="Network Security and Privacy", +Booktitle="The Computer Science and Engineering Handbook, 2nd Edition", +Note =" (A.B. Tucker, ed.)", Publisher ="CRC Press, Inc.",Year="2003", +Pages=""} + +@article{Neumann96Senate, +author = {P.G. Neumann}, +title = {Security Risks in the Emerging Infrastructure}, +journal = {Security in Cyberspace, Hearings, S. Hrg. 104-701}, +Pages = "350-363", Month = jun, Year = {1996}, +Note = {ISBN 0-16-053913-7. + Written testimony for the U.S. Senate Permanent Subcommittee on + Investigations of the Senate Committee on Governmental Affairs. + Oral testimony is on pages 106-111 +(\xlink{http://www.csl.sri.com/neumann/senate96.html}{http://www.csl.sri.com/neumann/senate96.html}) +}, +} + +@MANUAL{USSenate96, +author = {US-Senate}, +title = {Security in Cyberspace}, +organization = {U.S. Senate Permanent Subcommittee on Investigations + of the Senate Committee on Governmental Affairs, + Hearings, S. Hrg. 104-701}, +Note = {ISBN 0-16-053913-7}, +Pages = "", Month = jun, Year = {1996} } + +@InProceedings{Neumann98Senate, +Author = "P.G. Neumann", +Title = "Computer-Related Infrastructure Risks for Federal Agencies", +Booktitle = "Weak Computer Security in Government: Is the Public at Risk? + Hearing, Senate Hearing 105-609, ISBN 0-16-057456-0", +Organization = "U.S. Government Printing Office", +Address = "Washington, D.C.", +Year = "1998", Pages ={52--70}, +Month = "19 May", +NOTE ={(\xlink{http://www.csl.sri.com/neumann/senate98.html}{http://www.csl.sri.com/neumann/senate98.html}); +Oral testimony is on pages 5--22.} } + +@InProceedings{L0pht98Senate, +Author = "{Mudge et al.}", +Title = "Testimony of {L0pht Heavy Industries}", +Booktitle = "Weak Computer Security in Government: Is the Public at Risk? + Hearing, Senate Hearing 105-609, ISBN 0-16-057456-0", +Organization = "U.S. Government Printing Office", +Address = "Washington, D.C.", +Year = "1998", Pages ={71--91}, +Month = "19 May", +NOTE = {Oral testimony is on pages 22--41.} } + +@inProceedings{Neumann97air, +key="Neumann",Author="P.G. Neumann", Title= + "Computer Security in Aviation: Vulnerabilities, Threats, and Risks", +Booktitle="International Conference on Aviation Safety and Security + in the 21st Century, White House Commission on Safety and Security, and + George Washington University", + Year="1997", Month= "January 13-15", Pages="", + Note ="(\xlink{http://www.csl.sri.com/neumann/air.html}{http://www.csl.sri.com/neumann/air.html})" +} + +@article{Cryptographers97, +author = {Hal Abelson and Ross Anderson and Steven M. Bellovin and + Josh Benaloh and Matt Blaze and Whitfield Diffie and John Gilmore + and Peter G. Neumann and Ronald L. Rivest and Jeffrey I. Schiller + and Bruce Schneier}, +title = {The Risks of Key Recovery, Key Escrow, and + Trusted Third-Party Encryption}, +journal = {World Wide Web Journal (Web Security: A Matter of Trust)}, +NOTE = {This report was first distributed via the Internet on May 27, 1997.}, +publisher = {O'Reilly \& Associates}, volume = {2}, number = {3}, +pages = "241-257", month = {Summer}, year = {1997} } + +@article{Cryptographers98x, +author = {H. Abelson and R. Anderson and S.M. Bellovin and + J. Benaloh and M. Blaze and W. Diffie and J. Gilmore + and P.G. Neumann and R.L. Rivest and J.I. Schiller + and B. Schneier}, +title = {The Risks of Key Recovery, Key Escrow, and + Trusted Third-Party Encryption}, +journal = {(\xlink{http://www.cdt.org/crypto/risks98/}{http://www.cdt.org/crypto/risks98/})}, +NOTE = {This is a reissue of the May 27, 1997 report, with a new +preface evaluating what happened in the intervening year.}, +month = jun, year = {1998} } + +@InProceedings{Bellovin97, +Author = "S.M. Bellovin", +Title = "Probable Plaintext Cryptanalysis of the {IP} Protocols", +Booktitle= "Proceedings of the Symposium on Network and + Distributed System Security", +Organization = "Internet Society", Year = "1997", +Pages="52--59", Month = feb } + +@PhDThesis{Bellovin82, +Author={S.M. Bellovin}, +School={Department of Computer Science, University of North Carolina + at Chapel Hill}, +Title={Verifiably Correct Code Generation Using Predicate Transformers}, +Year={1982}, Month=dec, +Note="(\xlink{http://www.research.att.com/\~{}smb/dissabstract.html}{http://www.research.att.com/\~{}smb/dissabstract.html})" +} + +@InProceedings{NISSC95B, +Author = "R.W. Butler", +Title = "Formal Methods and {NASA}", +Booktitle = "Proceedings of the Eighteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1995", +Pages="", month=oct } + +@InProceedings{NISSC95K, +Author = "R. Kurshan", +Title = "Algorithmic Verification", +Booktitle = "Proceedings of the Eighteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1995", +Pages="", month=oct } + +@book{Kurshan94, +Author={R. Kurshan}, +Title={Computer-Aided Verification of Coordinating Processes}, +Publisher={Princeton University Press}, +Address = {Princeton, New Jersey}, +Year={1994} } + +@ARTICLE{BoyerYu96, + AUTHOR = {R.S. Boyer and Y. Yu}, + TITLE = {Automated proofs of object code for a widely used microprocessor}, + Journal={Journal of the ACM}, + YEAR = {1996}, VOLUME = {43}, NUMBER = {1}, PAGES = {529--543}, + MONTH = jan } + +@InProceedings{NISSC95L, +Author = "W. Legato", +Title = "Formal Methods: Changing Directions", +Booktitle = "Proceedings of the Eighteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1995", +Pages="", month=oct } + +@TechReport{JohnsonNSA+95, +author={D.R. Johnson and F.F. Saydjari and J.P. {Van Tassel}}, +Title={{MISSI} Security Policy: A Formal Approach}, +institution= {NSA R2SPO-TR001-95}, +address={}, month ={18 August}, Year=1995 } + +@article{Saiedian+, +author={H. {Saiedian et al.}}, +title = {An Invitation to Formal Methods}, +journal = {Computer}, year = {1996}, volume = {29}, +number = {4}, pages = {16-30}, month = apr } + +@book{SmartCards, +Author={J.L. Zoreda}, +Title={Smart Cards}, +Publisher={Artech House, Boston, Massachusetts}, +Year={1994} } + +@book{Orr90, +Author={K. Orr}, +Title={The One Minute Methodology}, +Publisher={Dorset House, New York}, +Year={1990} } + +@ARTICLE{MacKenzie94, +Author={D. MacKenzie}, +TITLE = {Computer-related accidental death: an empirical exploration}, +JOURNAL = {Science and Public Policy}, YEAR = {1994}, VOLUME = {21}, +NUMBER = {4}, PAGES = {233-248}, MONTH = aug } + +@ARTICLE{MacKenzie95, +Author={D. MacKenzie}, +TITLE = {The Automation of Proof: A Historical and Sociological Explanation}, +JOURNAL = {IEEE Annals of the History of Computing}, YEAR = {1995}, +VOLUME = {17}, NUMBER = {3}, PAGES = {7--29}, MONTH = {Fall} } + +@InProceedings{RoscoeWulf95, +Author={A.W. Roscoe and L. Wulf}, +Title={Composing and Decomposing Systems under Security Properties}, +BookTitle={Proceedings of the 8th IEEE Computer Security Foundations Workshop}, +Address={Kenmare, County Kerry, Ireland}, +Year={1995},Month=jun,Pages={} } + +@InProceedings{ZakinthinosLee95, +Author={A. Zakinthinos and E.S. Lee}, +Title={The Composability of Non-Interference}, +BookTitle={Proceedings of the 8th IEEE Computer Security Foundations Workshop}, +Address={Kenmare, County Kerry, Ireland}, +Year={1995},Month=jun,Pages={} } + +@InProceedings{ZakinthinosLee98, +Author={A. Zakinthinos and E.S. Lee}, +Title={Composing Secure Systems that have Emergent Properties}, +BookTitle={Proceedings of the 11th IEEE Computer Security + Foundations Workshop}, +Address={Rockport, Massachusetts}, +Year={1998},Month=jun,Pages={117--122} } + +@InProceedings{Maneki95, +Author={A.P. Maneki}, +Title={Algebraic Properties of System Composition in the {Loral}, + {Ulysses} and {McLean} Trace Models}, +BookTitle={Proceedings of the 8th IEEE Computer Security Foundations Workshop}, +Address={Kenmare, County Kerry, Ireland}, +Year={1995},Month=jun,Pages={} } + +@InProceedings{Mao95, +Author={W. Mao}, +Title={An Augmentation of {BAN}-Like Logics}, +BookTitle={Proceedings of the 8th IEEE Computer Security Foundations Workshop}, +Address={Kenmare, County Kerry, Ireland}, +Year={1995},Month=jun,Pages={} } + +@PhDThesis{Hinton95, +Author={H.M. Hinton}, School={University of Toronto}, +Title={Composable Safety and Progress Properties}, +Year={1995}, Month={} } + +@InProceedings{Knight+94, +Author = {J.C. Knight and J.C. Prey and W.A. Wulf}, +Title = {Undergraduate Computer Science Education: A New Curriculum + Philosophy and Overview}, +Booktitle = {Proceedings of the ACMCSE}, +Organization = {}, Address = {Phoenix, Arizona}, +Year = {1994}, +Pages={}, Month = mar } + +@InProceedings{Browne96, +Author={J.C. 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Perlman}, +School={MIT, Cambridge, Massachusetts}, +Title={Network Layer Protocols with {Byzantine} Robustness}, +Year={1988}, Month={} } + +@book{Wayner96, +Author={P. Wayner}, +Title={Disappearing Cryptography: Being and Nothingness on the Net}, +Publisher={AP Professional (Academic Press), Chestnut Hill, Massachusetts}, +Year={1996} } + +@book{Wayner02, +Author={P. Wayner}, +Title={Translucent Databases}, +Publisher={Flyzone Press, Baltimore, Maryland}, +Year={2002} } + +@InProceedings{Dean+96, +Author={D. Dean and E.W. Felten and D.S. Wallach}, +Title={{Java} Security: From {HotJava} to {Netscape} and Beyond}, +BookTitle={Proceedings of the 1996 Symposium on +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1996}, Month=may, pages={190--200}} + +@book{McGrawFelten97, +Author={G. McGraw and E.W. Felten}, +Title={{Java} Security: Hostile Applets, Holes, and Antidotes}, +Publisher={John Wiley and Sons, New York}, +Year={1997} } + +@book{McGrawFelten99, +Author={G. McGraw and E.W. Felten}, +Title={Securing {Java}: Getting Down to Business with Mobile Code}, +Publisher={John Wiley and Sons, New York}, +Note={This is the second edition of~\cite{McGrawFelten97}.}, +Year={1999} } + +@book{FriedmanVoas95, +Author={M. Friedman and J.M. Voas}, +Title={Software Assessment: Reliability, Safety, and Testability}, +Publisher={John Wiley and Sons, New York}, +Year={1998} } + +@book{VoasMcGraw98, +Author={J.M. Voas and G. McGraw}, +Title={Software Fault Injection: Inoculating Programs Against Errors}, +Publisher={John Wiley and Sons, New York}, +Year={1998} } + +@book{ViegaMcGraw02, +Author={J. Viega and G. McGraw}, +Title={Building Secure Software: How to Avoid Security Problems the + Right Way}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={2002} } + +@book{McGraw06, +Author={G. McGraw}, +Title={Software Security: Building Secure In}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={2006} } + +@Article{Kulkarni97, + author = {S.S. Kulkarni and A. Arora}, + title = {Compositional Design of Multitolerant Repetitive {Byzantine} + Agreement}, + journal = {Proceedings of the Seventeenth International Conference on + Foundations of Software Technology and Theoretical Computer Science, + Kharagpur, India}, + year = {1997}, + month = dec, + pages = {169-183}, +} + +@Article{AroraKulkarni98Multitolerance, + author = {A. Arora and S.S. Kulkarni}, + title = {Component Based Design of Multitolerance}, + journal = {IEEE Transactions on Software Engineering}, + year = {1998}, + volume = {24}, + number = {1}, + month = jan, + pages = {63--78}, +} + +@InProceedings{AroraKulkarni98Detectors, + author = {A. Arora and S.S. Kulkarni}, + title = {Detectors and Correctors: A Theory of Fault-Tolerance Components}, + booktitle = {Proceedings of the Eighteenth International Conference on + Distributed Computing Systems}, Month=may, Year={1998}, pages={}, + organization = {IEEE Computer Society} } + +@InProceedings{LeLann98a, +Author={G. {Le Lann}}, +Title={Predictability in Critical Systems}, +BookTitle={Springer-Verlag, Berlin, + Lecture Notes in Computer Science, + Formal Techniques in Real-Time and Fault-Tolerant Systems}, +Organization={}, Address={Lyngby, Denmark}, +Year={1998}, Month=sep, pages={}} + +@InProceedings{LeLann98b, +Author={G. {Le Lann}}, +Title={Proof-Based System Engineering and Embedded Systems}, +BookTitle={Springer-Verlag, Berlin, + Lecture Notes in Computer Science, + Embedded Systems}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={}} + +@Article{Fugetta+98, + author = {A. Fuggetta and G.P. Picco and G. Vigna}, + title = {Understanding Code Mobility}, + journal = {IEEE Transactions on Software Engineering}, + year = {1998}, + volume = {24}, + number = {5}, + month = may, + pages = {342--361}, +} + +@Article{Heitmeyer+98, + author = {C. Heitmeyer and J. {Kirby, Jr.} and B. Labaw and + M. Archer and R. Bharadwaj}, + title = {Using Abstraction and Model Checking to Detect + Safety Violations in Requirements Specifications}, + journal = {IEEE Transactions on Software Engineering}, + year = {1998}, + volume = {24}, + number = {11}, + month = nov, + pages = {927--948}, +} + +@Article{Feather98, + author = {M. Feather}, + title = {Rapid Application of Lightweight Formal Methods + for Consistency Analyses}, + journal = {IEEE Transactions on Software Engineering}, + year = {1998}, + volume = {24}, + number = {11}, + month = nov, + pages = {949--959}, +} + +@PhDThesis{Blume97, +Author={M. Blume}, +School={Computer Science Department, Princeton University}, +Title={Hierarchical Modularity and Intermodule Optimization}, +Year={1997}, Month=nov } + +@ARTICLE{BlumeAppel97, +Author={M. Blume and A.W. Appel}, +TITLE = {Hierarchical Modularity: Compilation Management for Standard ML}, +JOURNAL = {}, YEAR = {1997}, VOLUME = {}, +NUMBER = {}, PAGES = {}, MONTH = {} } + +@Article{BauerAppelFelten03, + Author={L. Bauer and A.W. Appel and E.W. Felten}, + Journal={Software--Practice and Experience}, + Title={Mechanisms for Secure Modular Programming in {Java}}, + Year={2003}, + Month={}, + Pages={461--480}, + Volume={33}, + Number={} + } + +@article{BlumeAppel99, + author = "M. Blume and A.W. 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Heberlein}, +Title={Holding Intruders Accountable on the {Internet}}, +BookTitle={Proceedings of the 1995 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1995}, Month=may, pages={}} + +@InProceedings{Klig95, +Author={S. Kliger and S. Yemini and Y. Yemini and D. Ohsie and S. Stolfo}, + Key ={Klig96}, +TITLE = {A coding approach to event correlation}, +Booktitle = "Proceedings of the Fourth International Symposium on + Integrated Network Management (IFIP/IEEE), + Santa Barbara, California, May 1995", +Organization = "Chapman \& Hall, London, England", +YEAR = {1995}, PAGES = {266-277} } + +@InProceedings{Wies95, +Author = "R. Wies", +Title = "Using a Classification of Management Policies for Policy + Specification and Policy Transformation", +Booktitle = "Proceedings of the Fourth International Symposium on + Integrated Network Management (IFIP/IEEE), + Santa Barbara, California, May 1995", +Organization = "Chapman \& Hall, London, England", +Year = "1995", Pages="44--56" } + +@InProceedings{Alpers+95, +Author = "B. Alpers and H. Plansky", +Title = "Concepts and Application of Policy-Based Management", +Booktitle = "Proceedings of the Fourth International Symposium on + Integrated Network Management (IFIP/IEEE), + Santa Barbara, California, May 1995", +Organization = "Chapman \& Hall, London, England", +Year = "1995", Pages="57--68" } + +@InProceedings{Putter+95, +Author = "P. Putter and J. Bishop and J. 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Stern}, +Title={Automated Analysis of Cryptographic Protocols Using Mur$\varphi$}, +BookTitle={Proceedings of the 1997 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1997}, Month=may, pages={141--151}} + +@InProceedings{Syverson97, +Author={P.F. Syverson and D.M. Goldschlag and M.G. Reed}, +Title={Anonymous Connections and Onion Routing}, +BookTitle={Proceedings of the 1997 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1997}, Month=may, pages={44-54}} + +@InProceedings{Moriconi97, +Author={M. Moriconi and X. Qian and R.A. Riemenschneider and L. Gong}, +Title={Secure Software Architectures}, +BookTitle={Proceedings of the 1997 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1997}, Month=may, pages={94-93}} + +@InProceedings{Zakinthos97, +Author={A. Zakinthos and E.S. Lee}, +Title={A General Theory of Security Properties}, +BookTitle={Proceedings of the 1997 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1997}, Month=may, pages={94-102}} + +@InProceedings{Lindqvist, +Author={U. Lindqvist and E. Jonsson}, +Title={How to Systematically Classify Computer System Intrusions}, +BookTitle={Proceedings of the 1997 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1997}, Month=may, pages={154-163}} + +@book{Amoroso99, +Author={E. Amoroso}, +Title={Intrusion Detection: An Introduction to Internet Surveillance, +Correlation, Trace Back, Traps, and Response}, +Publisher={Intrusion.Net Books}, +Year={1999} } + +@InProceedings{Ammann97, +Author={P. Ammann and S. Jajodia and C.D. McCollum and B.T. Blaustein}, +Title={Surviving Information Warfare Attacks on Databases}, +BookTitle={Proceedings of the 1997 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1997}, Month=may, pages={164-174}} + +@InProceedings{Ko97, +Author={C. Ko and M. Ruschitzka and K. Levitt}, +Title={Execution Monitoring of Security-Critical Programs in + Distributed Systems: A Specification-Based Approach}, +BookTitle={Proceedings of the 1997 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1997}, Month=may, pages={175-187}} + +@InProceedings{Gligor98, +Author={V.D. Gligor and S.I. Gavrila}, +Title={Application-Oriented Security Policies + and Their Composition}, +BookTitle={Proceedings of the 1998 Workshop on + Security Paradigms}, +Organization={}, Address={Cambridge, England}, +Year={1998}, Month={}, pages={}} + +@InProceedings{GligorGavrila98, +Author={V.D. Gligor and S.I. Gavrila and D. Ferraiolo}, +Title={On the Formal Definition of Separation-of-Duty Policies and their + Composition}, +BookTitle={Proceedings of the 1998 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1998}, Month=may, pages={}} + +@book{ShimomuraMarkoff, +Author={T. Shimomura and J. Markoff}, +Title={Takedown: The Pursuit and Capture of Kevin Mitnick, America's Most +Wanted Computer Outlaw -- By the Man Who Did It}, +Publisher={Hyperion, New York, New York}, Year={1996} } + +@book{AlexanderC, +Author={C. Alexander}, +Title={The Timeless Way of Building}, +Publisher={Oxford University Press, Oxford, England}, +Year={1979} } + +@book{Coplien95, +Author = {J.O. Coplien and D.C. {Schmidt (eds.)}}, +Title = {Pattern Languages of Program Design}, +Publisher = {Addison-Wesley, Reading, Massachusetts}, +Year = {1995} } + +@book{Forrester94, +Author = {T. Forester and P. Morrison}, +title = {Computer Ethics (2nd ed.)}, +Publisher = {The MIT Press, Cambridge, Massachusetts}, +Year = {1994}} + +@book{DiffieLandau98, +Author={W. Diffie and S. Landau}, +Title={Privacy on the Line: The Politics of Wiretapping and Encryption}, +Publisher={MIT Press}, +Year={1998} } + +@book{Agre97, +Author={P.E. Agre}, +Title={Computation and Human Experience}, +Publisher={Cambridge University Press}, +Year={1997} } + +@book{AgreRotenberg97, +Author={P.E. Agre and M. {Rotenberg, editors}}, +Title={Technology and Privacy: The New Landscape}, +Publisher={MIT Press, Cambridge, Massachusetts}, +Year={1997} } + +@book{SchneierBanisar97, +Author={B. Schneier and D. Banisar}, +Title={The Electronic Privacy Papers}, +Publisher={John Wiley and Sons, New York}, +Year={1997} } + +@ARTICLE{Ewusi-Mensah97, +Author={K. Ewusi-Mensah}, +TITLE={Critical Issues in Abandoned Information Systems Development Projects}, +JOURNAL = {Communications of the ACM}, YEAR = {1997}, VOLUME = {40}, +NUMBER = {9}, PAGES = {74--80}, MONTH = sep } + +@ARTICLE{BrynHitt98, +Author={E. Brynjolfsson and L.M. Hitt}, +TITLE={Beyond the Productivity Paradox}, +JOURNAL = {Communications of the ACM}, YEAR = {1998}, VOLUME = {41}, +NUMBER = {8}, PAGES = {11--12}, MONTH = aug } + +@InProceedings{RothfussParrett97, +Author = "J.S. Rothfuss and J.W. Parrett", +Title = "Go ahead, visit those {Websites}, you can't get hurt ... can you? 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Wallach", +Title = "Web spoofing: An {Internet} con game", +Booktitle = "Proceedings of the Nineteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1997", +Pages="95--103", month=oct } + +@InProceedings{Ladue97, +Author = "M.D. Ladue", +Title = "When {Java} was one: Threats from hostile byte code", +Booktitle="Proceedings of the Nineteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1997", +Pages="104--115", month=oct } + +@InProceedings{GongQian94, +Author={L. Gong and X. Qian}, +Title={The Complexibility and Composability of Secure Interoperation}, +BookTitle={Proceedings of the 1994 Symposium on Research in +Security and Privacy}, Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1994}, Month=may, pages={190--200}} + +@InProceedings{Gong+97, +Author = {L. Gong and M. Mueller and H. Prafullchandra and R. Schemers}, +Title = {Going Beyond the Sandbox: An Overview of the New Security + Architecture in the {Java Development Kit} 1.2}, +Booktitle = {Proceedings of the USENIX Symposium on Internet Technologies + and Systems}, +Organization = {}, Address = {Monterey, California}, +Year = {1997}, +Pages={}, Month = dec } + +@InProceedings{Gong+98, +Author = {L. Gong and R. Schemers}, +Title = {Implementing Protection Domains in the {Java Development Kit} 1.2}, +Booktitle = {Proceedings of the Internet Society Symposium on Network and + Distributed System Security}, +Organization = {}, Address = {San Diego, California}, +Year = {1998}, +Pages={}, Month = mar } + +@Book{Gong99, +Author={L. Gong}, +Title={Inside Java(TM) 2 Platform Security: Architecture, {API} Design, + and Implementation}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={1999} } + +@article{FeustelMayfield98, +author={E.A. Feustel and T. Mayfield}, +title = {The {DGSA}: Unmet Information Security Challenges for + Operating System Designers}, +journal = {Operating Systems Review}, volume = {32}, number = {1}, +pages = {3--22}, month = jan, year = {1998}} + +@InProceedings{LowmanMosier97, +Author = {T. Lowman and D. Mosier}, +Title = {Applying the {DoD} {Goal} {Security} {Architecture} as a Methodology + for the Development of System and Enterprise Security Architectures}, +Booktitle = {Proceedings of the Thirteenth Annual Computer Security + Applications Conference}, +Organization = {IEEE Computer Society}, Address = {San Diego, California}, +Year = {1997}, +Pages={183--193}, Month = dec } + +@InProceedings{Kang+96, +Author = {M.H. Kang and I. Moskowitz and B. Montrose and J. Parsonese}, +Title = {A Case Study of Two {NRL} Pump Prototypes}, +Booktitle = {Proceedings of the Twelfth Annual Computer Security + Applications Conference}, +Organization = {IEEE Computer Society}, Address = {San Diego, California}, +Year = {1996}, +Pages={32--43}, Month = dec } + +@InProceedings{Davidson96, +Author = {J.A. Davidson}, +Title = {Asymmetric Isolation}, +Booktitle = {Proceedings of the Twelfth Annual Computer Security + Applications Conference}, +Organization = {IEEE Computer Society}, Address = {San Diego, California}, +Year = {1996}, +Pages={44--54}, Month = dec } + +@InProceedings{Anderson+96, +Author = {M. Anderson and C. North and J. Griffin and J. Yesberg and K. Yiu}, +Title = {Starlight: Interactive Link}, +Booktitle = {Proceedings of the Twelfth Annual Computer Security + Applications Conference}, +Organization = {IEEE Computer Society}, Address = {San Diego, California}, +Year = {1996}, +Pages={55--63}, Month = dec } + +@InProceedings{Kang+97, +Author = {M.H. Kang and J.N. Froscher and I.S. Moskowitz}, +Title = {An Architecture for Multilevel Secure Interoperability}, +Booktitle = {Proceedings of the Thirteenth Annual Computer Security + Applications Conference}, +Organization = {IEEE Computer Society}, Address = {San Diego, California}, +Year = {1997}, +Pages={194--204}, Month = dec } + +@InProceedings{Pollitt97, +Author = "M. Pollitt", +Title = "Cyberterrorism: Fact or fancy?", +Booktitle = "Proceedings of the Nineteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1997", +Pages="285--289", month=oct } + +@InProceedings{Alves-Foss97, +Author = "J. Alves-Foss", +Title = "The Use of Belief Logics in the Presence of Causal Consistency + Attacks", +Booktitle = "Proceedings of the Nineteenth National Computer Security Conference", +Organization = "NIST/NCSC", Address = "Baltimore, Maryland", Year = "1997", +Pages="406--417", month=oct } + +@techreport{Lincoln+94, + AUTHOR = {P.D. Lincoln and N. Marti-Oliet and J. Meseguer}, + TITLE = {Specification, Transformation, and Programming + of Concurrent Systems in Rewriting Logic}, + NUMBER = {SRI-CSL-94-11}, + INSTITUTION = {Computer Science Laboratory, SRI International}, + YEAR = "1994", + ADDRESS = "Menlo Park, California", + MONTH = may, +} + +@InProceedings{Meseguer93, +Author = "J. Meseguer", +Title = "A Logical Theory of Concurrent Objects and its + Realization in the {Maude} Language", +Booktitle = "Research Directions on Concurrent Object-Oriented Programming", +editors = {P. Wegner and A. Yonezawa}, +Publisher = {MIT Press, Cambridge, Massachusetts}, +Year = "1993" } + +@TechReport{JTA97, +author={{Department of the Army}}, +Title={{Joint Technical Architecture,} Version 5.0}, +institution= {Office of the Secretary of the Army}, +address={}, month =sep, Year=1997 } + +@InProceedings{Green97, +Author = "P. Green", +Title = "The Art of Creating Reliable Software-based Systems Using + Off-the-Shelf Software Components", +Booktitle = "Proceedings of the + Sixteenth International Symposium on Reliable Distributed Systems", +Organization = "IEEE Computer Society", +Address = {Durham, North Carolina}, Year = "1997", +Pages="118--120", Month = "22-24 October" } + +@InProceedings{Arbaugh+97, +Author={W.A. Arbaugh and D.J. Farber and J.M. Smith}, +Title={A Secure and Reliable Bootstrap Architecture}, +BookTitle={Proceedings of the 1997 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1997}, Month=may, pages={65--71}} + +@InProceedings{Arbaugh+98a, +Author={W.A. Arbaugh and A.D. Keromytis and D.J. Farber and J.M. Smith}, +Title={Automated Recovery in a Secure Bootstrap Process}, +BookTitle={Proceedings of the 1998 Network and Distributed System + Security Symposium}, +Organization={Internet Society}, Address={San Diego, California}, +Year={1998}, Month=mar, pages={}} + +@Article{Arbaugh+98b, +Author={W.A. Arbaugh and J.R. Davin and D.J. Farber and J.M. Smith}, +Title={Security for Private Intranets}, +Journal={IEEE Computer}, +Volume={31}, +number={9}, +pages = {48--55}, +Note = {Special issue on broadband networking security.}, +Year={1998} } + +@Article{MelliarMoser98, + Author={P.M. Melliar-Smith and L.E. Moser}, + Journal={Computer}, + Title={Surviving Network Partitioning}, + Year={1998}, + Month=mar, + Pages={62--68}, + Volume={31}, + Number={3} + } + +@InProceedings{Raynal98, +Author={M. Raynal}, +Title={A Case Study of Agreement Problems in Distributed Systems: + Non-Blocking Atomic Commitment}, +BookTitle={Proceedings of the 1997 High-Assurance Systems + Engineering Workshop}, +Organization={IEEE Computer Society}, Address={Washington, D.C.}, +Year={1997}, Month=aug, pages={209--214}} + +@InProceedings{NeculaLee97, +Author={G.C. Necula and P. Lee}, +Title={Research on Proof-Carrying Code for Untrusted-Code Security}, +BookTitle={Proceedings of the 1997 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1997}, Month=may, pages={204}} + +@PhDThesis{Necula98, +Author={G.C. Necula}, +School={Computer Science Department, Carnegie-Mellon University}, +Title={Compiling with Proofs}, +Year={1998}, Month={} } + +@PhDThesis{Dean99, +Author={D. Dean}, +School={Computer Science Department, Princeton University}, +Title={Formal Aspects of Mobile Code Security}, +Note = +{(\xlink{http://www.cs.princeton.edu/sip/pub/ddean-dissertation.php3}{http://www.cs.princeton.edu/sip/pub/ddean-dissertation.php3})}, +Year={1999}, Month=jan } + +@PhDThesis{Wallach99, +Author={D.S. Wallach}, +School={Computer Science Department, Princeton University}, +Title={A New Approach to Mobile Code Security}, +Note = +{(\xlink{http://www.cs.rice.edu/\~{}dwallach/}{http://www.cs.rice.edu/\~{}dwallach/})}, +Year={1999}, Month=jan } + +@PhDThesis{Stringer-Calvert98, +Author={D.W.J. Stringer-Calvert}, +School={Department of Computer Science, University of York}, +Title={Mechanical Verification of Compiler Correctness}, +Year={1998}, Month={} } + +@TechReport{Dold+02, +author={A. Dold and F.W. von Henke and V. Vialard and W. Goerigk}, +Title="A Mechanically Verified Compiling Specification for + a Realistic Compiler", +type={Technical Report {UIB} 03-02}, +institution="Universit{\"a}t Ulm, Fakult{\"a}t f{\"u}r Informatik", +address={Ulm, Germany}, +Month = dec, Year=2002 } + +@TechReport{Dold++02, +author={A. Dold and F.W. von Henke and V. Vialard and W. Goerigk}, +Title="A Mechanically Verified Compiling Specification for + a Realistic Compiler", +type={Technical Report {UIB} 03-02}, +institution="Universit{\"a}t Ulm, Fakult{\"a}t f{\"u}r Informatik", +address={Ulm, Germany}, +Month = dec, Year=2002, +NOTE = "\xlink{http://www.informatik.uni-ulm.de/ki/Verifix/initcomp\_uib-02-03.html}{http://www.informatik.uni-ulm.de/ki/Verifix/initcomp_uib-02-03.html}" } + +@PhDThesis{Prasad98, +Author={D. Prasad}, +School={Department of Computer Science, University of York}, +Title={Dependable Systems Integration Using the Theories of + Measurement and Decision Analysis}, +Year={1998}, Month=aug } + +@InProceedings{Prasad98b, +Author = {D. Prasad and J. McDermid}, +Title = {Dependability Evaluation using a Multi-Criteria + Decision Analysis Procedure}, +Booktitle = {To appear}, +Year = "1999", +Pages="", Month = "" } + +@Proceedings{CNLS, +Editor={S. Forrest}, +Title={Emergent Computation}, +ORGANIZATION={Proceedings of the Ninth Annual CNLS Conference}, +Address ={MIT Press, Cambridge, Massachusetts}, +Month={}, +Year={1991} } + +@InProceedings{Hinton97, +Author={H.M. Hinton}, +Title={Under-Specification, Composition, and Emergent Properties}, +BookTitle={Proceedings of the 1997 New Security Paradigms Workshop}, +Organization={ACM SIGSAC}, Address={Langdale, Cumbria, United Kingdom}, +Year={1997}, Month=sep, pages={83--93}} + +@InProceedings{Hinton98, +Author={H.M. Hinton}, +Title={Composing Partially-Specified Systems}, +BookTitle={Proceedings of the 1998 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1998}, Month=may, pages={}} + +@InProceedings{Bradley+98, +Author={K.A. Bradley and B. Mukherjee and R.A. Olsson and N. Puketza}, +Title={Detecting Disruptive Routers: + A Distributed Network Monitoring Approach}, +BookTitle={Proceedings of the 1998 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1998}, Month=may, pages={}} + +@InProceedings{Trostle98, +Author={J.T. Trostle}, +Title={Timing Attacks Against Trusted Path}, +BookTitle={Proceedings of the 1998 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1998}, Month=may, pages={}} + +@InProceedings{Malkhi+98, +Author={D. Malkhi and M.K. Reiter and A.D. Rubin}, +Title={Secure Execution of {Java} Applets using a Remote Playground}, +BookTitle={Proceedings of the 1998 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1998}, Month=may, pages={}} + +@InProceedings{WallachFelten98, +Author={D.S. Wallach and E.W. Felten}, +Title={Understanding {Java} Stack Inspection}, +BookTitle={Proceedings of the 1998 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1998}, Month=may, pages={}} + +@InProceedings{SanderTschudin98, +Author={T. Sander and C.F. Tschudin}, +Title={Towards Mobile Cryptography}, +BookTitle={Proceedings of the 1998 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1998}, Month=may, pages={}} + +@InProceedings{Salter+98, +author={C. Salter and O.S. Saydjari and B. Schneier and J. Wallner}, +Title={Toward A Secure System Engineering Methodology}, +BookTitle = {New Security Paradigms Workshop}, +NOTE= {(\xlink{http://www.counterpane.com/secure-methodology.html}{http://www.counterpane.com/secure-methodology.html}), Draft was at +\xlink{http://www.hokie.bs1.prc.com/ipa/PREPUB\~{}2.html}{http://www.hokie.bs1.prc.com/ipa/PREPUB\~{}2.html}}, +address={}, month =sep, Year=1998 } + +@TechReport{Blumenstiel85, +author={A.D. Blumenstiel}, +Title={Security Assessment Considerations for {ADL ADP} Systems}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center}, +address={Cambridge, Massachusetts}, month ={}, Year=1985 } + +@TechReport{Blumenstiel86a, +author={A.D. Blumenstiel}, +Title={Potential Consequences of and Countermeasures for Advanced Automation + System Electronic Penetration}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center}, +address={Cambridge, Massachusetts}, month ={}, Year=1986 } + +@TechReport{Blumenstiel86b, +author={A.D. Blumenstiel}, +Title={{FAA} Computer Security Candidate Countermeasures for Electronic + Penetration of {ADP} Systems}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center}, +address={Cambridge, Massachusetts}, month ={}, Year=1986 } + +@TechReport{Blumenstiel86c, +author={A.D. Blumenstiel}, +Title={Operation Manual for the {HH-65A} Data Link}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center}, +address={Cambridge, Massachusetts}, month ={}, Year=1986 } + +@TechReport{BlumenstielManning86, +author={A.D. Blumenstiel and P.E. Manning}, +Title={{Advanced Automation System} Vulnerabilities to Electronic Attack}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center}, +address={Cambridge, Massachusetts}, month =jul, Year=1986 } + +@TechReport{Blumenstiel87, +author={A.D. Blumenstiel}, +Title={Guidelines for {National Airspace System} Electronic Security}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center}, +address={Cambridge, Massachusetts}, month ={}, Year=1987 } + +@TechReport{Blumenstiel88a, +author={A.D. Blumenstiel}, +Title={{Federal Aviation Administration} Computer Security Plans}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center, +produced by Science Resources Associates}, +address={Cambridge, Massachusetts}, month ={}, Year=1988 } + +@TechReport{Blumenstiel88b, +author={A.D. Blumenstiel}, +Title={{National Airspace System} Electronic Security}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center}, +address={Cambridge, Massachusetts}, month ={}, Year=1988 } + +@TechReport{Blumenstiel88c, +author={A.D. Blumenstiel and J. Itz}, +Title={{National Airspace System} {Data Interchange Network} + Electronic Security}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center}, +address={Cambridge, Massachusetts}, month ={}, Year=1988 } + +@TechReport{Blumenstiel90, +author={A.D. Blumenstiel}, +Title={{Federal Aviation Administration AIS} Security Accreditation Guidelines}, +institution= {National Institute on Standards and Technology}, +address={Gaithersburg, Maryland}, month ={}, Year=1990 } + +@TechReport{Blumenstiel91, +author={A.D. Blumenstiel}, +Title={{Federal Aviation Administration AIS} Security + Accreditation Application Design}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center}, +address={Cambridge, Massachusetts}, month ={}, Year=1991 } + +@TechReport{Blumenstiel92a, +author={A.D. Blumenstiel}, +Title={{Federal Aviation Administration AIS} Security Accreditation Program + Instructions}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center}, +address={Cambridge, Massachusetts}, month ={}, Year=1992 } + +@TechReport{Blumenstiel92b, +author={A.D. Blumenstiel}, +Title={{Federal Aviation Administration} Sensitive Application Security + Accreditation Guideline}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center}, +address={Cambridge, Massachusetts}, month ={}, Year=1992 } + +@TechReport{Blumenstiel93, +author={A.D. {Blumenstiel et al.}}, +Title={{Federal Aviation Administration} Report to {Congress} on Air Traffic + Control Data and Communications Vulnerabilities and Security}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center}, +address={Cambridge, Massachusetts}, month ={}, Year=1993 } + +@TechReport{Blumenstiel94, +author={A.D. Blumenstiel}, +Title={Briefing on Electronic Security in the {Communications,} {Navigation} + and {Surveillance} {(CNS)} Environment}, +institution= {U.S. Department of Transportation/RSPA/Volpe Center}, +address={Cambridge, Massachusetts}, month ={}, Year=1994 } + +@TechReport{HeathTeramac97, +Author={J.R. Heath and P.J. Kuekes and R.S. Williams}, +TITLE = {A Defect Tolerant Architecture for Chemically Assembled Computers: + The Lessons of {Teramac} for the Aspiring Nanotechnologist}, +institution ={UCLA}, +YEAR = {1997}, VOLUME = {}, NUMBER = {}, PAGES = {}, MONTH = {}, +NOTE = {(\xlink{http://neon.chem.ucla.edu/\~{}schung/Hgrp/teramac.html}{http://neon.chem.ucla.edu/\~{}schung/Hgrp/teramac.html})} +} + +@ARTICLE{Vaidya98, +Author={N.H. Vaidya}, +TITLE = {A Case for Two-Level Recovery Schemes}, +JOURNAL = {IEEE Transactions on Computers}, YEAR = {1998}, VOLUME = {47}, +NUMBER = {6}, PAGES = {656--666}, MONTH = jun } + +@TechReport{RielyHennessy98, +author={J. Riely and M. Hennessy}, +Title={Trust and Partial Typing in Open Systems of Mobile Agents}, +institution= {University of Sussex}, +address={}, month =jul, Year=1998, +Note ={ftp://ftp.cogs.susx.ac.uk/pub/reports/compsci/cs0498.ps.Z}} + +@TechReport{IEEE-P1363, +author={IEEE}, +Title={Standard Specifications for Public Key Cryptography}, +institution= {IEEE Standards Department}, +address={445 Hoes Lane, P.O. Box 1331, Piscataway, New Jersey 08855-1331}, +month ={}, Year={2000 and ongoing}, +note = {(\xlink{http://grouper.ieee.org/groups/1363/}{http://grouper.ieee.org/groups/1363/})} } + +@TechReport{JASAdraft, +author={JASA Standards Working Group}, +Title={Joint Airborne {SIGINT} Architecture}, +institution= {TASC}, +address={131 National Business Parkway, + Annapolis Junction, MD 20701}, +month ={June-July}, Year=1998, +note ={Draft, Version 3; + contact Paul L. Washington, Jr., 1-301-483-6000, ext. 2017, + \verb+PLWashington@jswg.org+} } + +@ARTICLE{Stevenson98, +Author={D.E. Stevenson}, TITLE = {Validation and Verification Methodologies + for Large Scale Simulations: There are no Silver Hammers, Either}, +JOURNAL = {IEEE Computational Science and Engineering}, +YEAR = {1998}, VOLUME = {}, +NUMBER = {}, PAGES = {}, MONTH = {} } + +@ARTICLE{Stevenson98x, +Author={D.E. Stevenson}, TITLE = {Validation and Verification Methodologies + for Large Scale Simulations: There are no Silver Hammers, Either}, +JOURNAL = {IEEE Computational Science and Engineering}, +YEAR = {1998}, VOLUME = {}, +NUMBER = {}, PAGES = {}, MONTH = {} } + +@book{Bass+98, +Author={L. Bass and P. Clements and R. Kazman}, +Title={Software Architecture in Practice}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={1998} } + +@TechReport{OSTF98, +author={W.L. {O'Hern, Jr., task force chairman}}, +Title={An Open Systems Process for {DoD}}, +institution= {Open Systems Task Force, Defense Science Board}, +address={}, month =oct, Year="1998" } + +@Book{VignaEd98, +Author={G. {Vigna, ed.}}, +Title={Mobile Agents and Security}, +Publisher={Springer-Verlag, Berlin, Lecture Notes in Computer Science 1419}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={}} + +@InProceedings{Chess98, +Author={D.M. Chess}, +Title={Security Issues in Mobile Code Systems}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science, + vol.~1419, Mobile Agents and Security}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={1--14}} + +@InProceedings{RiordanSchneier98, +Author={J. Riordan and B. Schneier}, +Title={Environmental Key Generation Toward Clueless Agents}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science + vol.~1419, Mobile Agents and Security}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={15--24}} + +@InProceedings{VolpanoSmith98, +Author={D. Volpano and G. Smith}, +Title={Language Issues in Mobile Program Security}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science, + vol.~1419, Mobile Agents and Security}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={25--43}} + +@InProceedings{SanderTschudin, +Author={T. Sander and C.F. Tschudin}, +Title={Protecting Mobile Agents Against Malicious Hosts}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science 1419, + Mobile Agents and Security}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={44--60}} + +@InProceedings{NeculaLee98, +Author={G.C. Necula and P. Lee}, +Title={Safe, Untrusted Agents Using Proof-Carrying Code}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science, + vol.~1419, Mobile Agents and Security}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={61--91}} + +@InProceedings{Hohl98, +Author={F. Hohl}, +Title={Time Limited Blackbox Security: Protecting Mobile Agents from + Malicious Hosts}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science, + vol.~1419, Mobile Agents and Security}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={92--113}} + +@InProceedings{Berkovits+98, +Author={S. Berkovits and J.D. Guttman and V. Swarup}, +Title={Authentication for Mobile Agents}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science, + vol.~1419, Mobile Agents and Security}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={114--136}} + +@InProceedings{Vigna98, +Author={G. Vigna}, +Title={Cryptographic Traces for Mobile Agents}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science, + vol.~1419, Mobile Agents and Security}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={137--153}} + +@InProceedings{Gray+98, +Author={R.S. Gray and D. Kotz and G. Cybenko and D. Rus}, +Title={D'Agents: Security in a Multiple-Language, Mobile-Agent System}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science 1419, + Mobile Agents and Security}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={154--187}} + +@InProceedings{Karjoth+98, +Author={G. Karjoth and D.B. Lange and M. Oshima}, +Title={A Security Model for Aglets}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science, + vol.~1419, Mobile Agents and Security}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={188--205}} + +@InProceedings{GongSchemers98, +Author={L. Gong and R. Schemers}, +Title={Signing, Sealing, and Guarding {Java} Objects}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science 1419, + Mobile Agents and Security}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={206--216}} + +@InProceedings{Ousterhout+98, +Author={J.K. Ousterhout and J.Y. Levy and B.B. Welch}, +Title={The {Safe-Tcl} Security Model}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science, + vol.~1419, Mobile Agents and Security}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={217--234}} + +@InProceedings{DePaoli+98, +Author={F. {De Paoli} and A.L. {Dos Santos} and R.A. Kemmerer}, +Title={Web Browsers and Security}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science, + vol.~1419, Mobile Agents and Security}, +Organization={}, Address={}, +Year={1998}, Month={}, pages={235--256}} + +@TechReport{PDD63, +author={W.J. Clinton}, +Title={{The Clinton Administration's Policy on Critical Infrastructure + Protection: Presidential Decision Directive 63}}, +institution= {U.S. Government White Paper}, +address={}, month ={22 May}, Year=1998 } + +@InProceedings{Anderson98, +Author = "R.H. Anderson", +Title = "A ``Minimum Essential Information + Infrastructure'' {(MEII)} for {U.S.} Defense + Systems: Meaningful? Feasible? Useful?", +Booktitle = "Position Papers for the 1998 Information Survivability Workshop +--- ISW '98", +Organization = "IEEE", Address = "Orlando, Florida", Year = "1998", +Pages="11--14", month=oct } + +@InProceedings{Winkler98, +Author = "I.S. Winkler", +Title = "Position Paper", +Booktitle = "Position Papers for the 1998 Information Survivability Workshop +--- ISW '98", +Organization = "IEEE", Address = "Orlando, Florida", Year = "1998", +Pages="189--191", month=oct } + +@InProceedings{CowanPu98, +Author = "C. Cowan and C. Pu", +Title = "Survivability from a Sow's Ear: The Retrofit Security Requirement", +Booktitle = "Position Papers for the 1998 Information Survivability Workshop +--- ISW '98", +Organization = "IEEE", Address = "Orlando, Florida", Year = "1998", +Pages="43--47", month=oct } + +@InProceedings{LevesonHeimdahl98, +Author = "N.G. Leveson and M.P.E. Heimdahl", +Title = "New Approaches to Critical-System Survivability", +Booktitle = "Position Papers for the 1998 Information Survivability Workshop +--- ISW '98", +Organization = "IEEE", Address = "Orlando, Florida", Year = "1998", +Pages="111--114", month=oct } + +@InProceedings{ThomasFeiertag98, +Author = "R. Thomas and R. Feiertag", +Title = "Addressing Survivability in the Composable Replaceable + Security Services Infrastructure", +Booktitle = "Position Papers for the 1998 Information Survivability Workshop +--- ISW '98", +Organization = "IEEE", Address = "Orlando, Florida", Year = "1998", +Pages="159--162", month=oct } + +@InProceedings{TidswellPotter98, +Author={J.E. Tidswell and J.M. Potter}, +Title={A Dynamically Typed Access Control Model}, +BookTitle={Springer-Verlag, Berlin, Lecture Notes in Computer Science + vol.~1438, + Information Security and Privacy, Third Australasian Conference, + ACISP'98, Brisbane, Australia}, +Organization={}, Address={}, +Year={1998}, Month=jun, pages={308--319}} + +@InProceedings{Goldberg98, +Author={A. Goldberg}, +TITLE = {A specification of {Java} loading and bytecode verification}, +Booktitle = {Fifth ACM Conference on Computer and Communications Security}, +Organization = {ACM SIGSAC}, Address = {San Francisco, California}, +Year = {1998}, +Pages={49--58}, Month = nov } + +@InProceedings{Lincoln+98, +Author={P. Lincoln and J. Mitchell and M. Mitchell and A. Scedrov}, +TITLE = {A probabilistic poly-time framework for protocol analysis}, +Booktitle = {Fifth ACM Conference on Computer and Communications Security}, +Organization = {ACM SIGSAC}, Address = {San Francisco, California}, +Year = {1998}, +Pages={112--121}, Month = nov } + +@InProceedings{HaleviKrawczyk98, +Author={S. Halevi and H. Krawczyk}, +TITLE = {Public-key cryptography and password protocols}, +Booktitle = {Fifth ACM Conference on Computer and Communications Security}, +Organization = {ACM SIGSAC}, Address = {San Francisco, California}, +Year = {1998}, +Pages={122--131}, Month = nov } + +@InProceedings{SchneierMudge98, +Author={B. Schneier and {Mudge}}, +TITLE = {{Cryptanalysis of Microsoft's Point-to-Point Tunneling Protocol} + {(PPTP)}}, +Booktitle = {Fifth ACM Conference on Computer and Communications Security}, +Organization = {ACM SIGSAC}, Address = {San Francisco, California}, +Year = {1998}, +Pages={132--141}, Month = nov } + +@InProceedings{SchneierKelsey98, +Author = {B. Schneier and J. Kelsey}, +Title = {Cryptographic support for secure logs on untrusted machines}, +Booktitle = {Proceedings of the Seventh USENIX Security Symposium}, +Organization = {USENIX}, Address = {}, +Year = {1998}, +Pages={53--62}, Month = jan} + +@InProceedings{An+02, +Author={J.H. An and Y. Dodis and T. Rabin}, +Title={On the Security of Joint Signature and Encryption}, +BookTitle={Advances in Cryptology, EUROCRYPT 2002, Amsterdam, The + Netherlands, Springer-Verlag, Berlin, Lecture Notes in Computer Science}, +Organization={}, Address={}, +Year={2002}, Month=may, pages={83--107}} + +@InProceedings{Paulson97a, +Author={L. Paulson}, +Title={Mechanized Proofs for a Recursive Authentication Protocol}, +BookTitle={10th IEEE Computer Security Foundations Workshop}, +Organization={IEEE Computer Society}, Address={}, +Year={1997}, Month={}, pages={84--95}} + +@InProceedings{Paulson97b, +Author={L. Paulson}, +Title={Proving Properties of Security Protocols by Induction}, +BookTitle={10th IEEE Computer Security Foundations Workshop}, +Organization={IEEE Computer Society}, Address={}, +Year={1997}, Month={}, pages={70--83}} + +@InProceedings{Sullivan+99, +Author = "K. Sullivan and J.C. Knight and X. Du and S. Geist", +Title = "Information Survivability Control Systems", +Booktitle = "Proceedings of the 1999 International Conference on + Software Engineering (ICSE)", +Organization = "", Address = "", Year = "1999", +Pages="", Month = "" } + +@InProceedings{FetzerCristian99, +Author={C. Fetzer and F. Cristian}, +Title={Building Fault-Tolerant Hardware Clocks from {COTS} Components}, +BookTitle ={Proceedings of the 1999 Conference on Dependable Computing for +Critical Applications}, +Organization={}, Address={San Jose, California}, +Year={1998}, Month=jan, pages={59--78} } + +@InProceedings{PfeiferSchwier+vonHenke99, +Author={H. Pfeifer and D. Schwier and F.W. {von Henke}}, +Title={Formal Verification for Time-Triggered Clock Synchronization}, +BookTitle ={Proceedings of the 1999 Conference on Dependable Computing for +Critical Applications}, +Organization={}, Address={San Jose, California}, +Year={1998}, Month=jan, pages={193--212} } + +@TechReport{Millen98, +author={J.K. Millen}, +Title={Service Survivability}, +institution= {SRI International Computer Science Laboratory}, +address={Menlo Park, California}, month ={draft, June}, Year=1998 } + +@InProceedings{Millen99, +Author={J. Millen}, +Title={20 years of covert channel modeling and analysis}, +BookTitle={Proceedings of the 1999 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={1999}, Month=may, pages={113--114}, + NOTE= {(\xlink{http://www.csl.sri.com/\~{}millen/papers/20yrcc.ps}{http://www.csl.sri.com/\~{}millen/paper/20yrcc.ps})} +} + +@InProceedings{Millen99b, +author={J.K. Millen}, +Title={Local Reconfiguration Policies}, +BookTitle ={Proceedings of the 1999 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, +California}, Year={1999}, Month=may, pages={48--56}, + NOTE= {(\xlink{http://www.csl.sri.com/\~{}millen/papers/reconfig.ps}{http://www.csl.sri.com/\~{}millen/paper/reconfig.ps})} + } + +@TechReport{Millen99a, +author={J.K. Millen}, +Title={Survivability Measure}, +institution= {SRI International Computer Science Laboratory}, +address={Menlo Park, California}, month =jan, Year=1999, + } + +@TechReport{Millen00b, +author={J.K. Millen}, +Title={Survivability Measure}, +institution= {SRI International Computer Science Laboratory}, +address={Menlo Park, California}, month =jun, Year=2000, +NOTE= {(\xlink{http://www.csl.sri.com/\~{}millen/papers/measure.ps}{http://www.csl.sri.com/\~{}millen/papers/measure.ps})} + } + +@InProceedings{MillenWright98, +author={J.K. Millen and R. Wright}, +Title={Certificate revocation the responsible way}, +BookTitle ={Proceedings of a workshop on + Computer Security, Dependability, and Assurance (CSDA '98): + From Needs to Solutions workshop}, +Organization={}, Address={}, Year={1998}, Month={}, pages={}, + NOTE= {(\xlink{http://www.csl.sri.com/\~{}millen/papers/needs.ps}{http://www.csl.sri.com/\~{}millen/papers/needs.ps})} + } + +@InProceedings{MillenWright00, +author={J.K. Millen and R. Wright}, +Title={Reasoning about trust and insurance in a public-key infrastructure}, +BookTitle ={Proceedings of the Computer Security Foundations Workshop}, +Organization={}, Address={Cambridge, England}, Year={2000}, Month=jul, + pages={}, + NOTE={(\xlink{http://www.csl.sri.com/\~{}millen/papers/insurance.ps}{http://www.csl.sri.com/\~{}millen/papers/insurance.ps})} + } + +@InProceedings{Millen00a, +Author={J. Millen}, +TITLE = {Efficient Fault-Tolerant Certificate Revocation}, +Booktitle = {Seventh ACM Conference on Computer and Communications Security}, +Organization = {ACM SIGSAC}, Address = {}, +Year = {2000}, Note = {Submitted.}, +Pages={}, Month = {} } + +@InProceedings{BI93, +author = {M. Boyd and D. Iverson}, +title={Digraphs and fault trees: a tale of two combinatorial modeling methods}, +Booktitle ={Proceedings of the Annual Reliability and Maintainability Symposium}, +Organization = {},Pages={}, Month = {}, +Year = {1993} } + +@TechReport{Carney98, +author={D.J. Carney}, +Title={Quotations from {Chairman David}: A {Little Red Book} of Truths to + Enlighten and Guide on the Long March Toward the {COTS} Revolution}, +institution= {Carnegie-Mellon University Software Engineering Institute}, +address={Pittsburgh, Pennsylvania}, +month ={}, Year=1998, url={http://www.sei.cmu.edu/publications/documents/99.reports/lrb/little-red-book.html} + } + +@article{Bacon99, +author={J. Bacon}, +title = {Report on the {Eighth} {ACM SIGOPS} {European Workshop}, + {System Support for Composing Distributed Applications}}, +journal = {Operating Systems Review}, volume = {33}, number = {1}, +pages = {6--17}, month = jan, year = {1999} } + +@article{OSDebate99, +author={T. Kindberg}, +title = {Debate: This house believes the development of robust + distributed systems from components to be impossible}, +journal = {Operating Systems Review}, volume = {33}, number = {1}, +pages = {15--17}, month = jan, year = {1999}, +Note={The description of this debate appeared in ``Report on the Eighth + ACM SIGOPS European Workshop,'' System Support for Composing Distributed + Applications, {\it loc.cit.}, pp. 6--17.}} + +@book{SecDepAss99, +Author={P. Ammann and B.H. Barnes and S. Jajodia and {E.H. Sibley (editors)}}, +Title={Computer Security, Dependability, and Assurance}, +Publisher={IEEE Computer Society}, +Year={1999} } + +@book{SDolev00, +Author={S. Dolev}, +Title={Self-Stabilization}, +Publisher={MIT Press, Cambridge, Massachusetts}, +Year={2000} } + +@Proceedings{NATO00, +Author = "NATO", +Title = "Proceedings of the NATO Conference on Commercial Off-The-Shelf + Products in Defence Applications: The Ruthless Pursuit of COTS", +Organization = "NATO", Address = "Brussels, Belgium", Year = "2000", +Pages="", Month = apr } + +@InProceedings{Neumann00NATO, +Author = "P.G. Neumann", +Title = "The Potentials of Open-Box Source Code in Developing + Robust Systems", +Booktitle = "Proceedings of the NATO Conference on Commercial Off-The-Shelf + Products in Defence Applications: The Ruthless Pursuit of COTS", +Organization = "NATO", Address = "Brussels, Belgium", Year = "2000", +Pages="", Month = apr } + +@InProceedings{White00, +Author = "I. White", +Title = "Wrapping the {COTS} Dilemma", +Booktitle = "Proceedings of the NATO Conference on Commercial Off-The-Shelf + Products in Defence Applications: The Ruthless Pursuit of COTS", +Organization = "NATO", Address = "Brussels, Belgium", Year = "2000", +Pages="", Month = apr } + +@InProceedings{PeelingTaylor00, +Author = {N. Peeling and R. Taylor}, +Title = {Standards -- Myths, Delusions and Opportunities}, +Booktitle = "Proceedings of the NATO Conference on Commercial Off-The-Shelf + Products in Defence Applications: The Ruthless Pursuit of COTS", +Organization = "NATO", Address = "Brussels, Belgium", Year = "2000", +Pages="", Month = apr } + +@InProceedings{Barbarello00, +Author = {J. Bararello and W. Kasian}, +Title = {{United States Army Commercial Off-The-Shelf (COTS)} Experience: + The Promises and Realities}, +Booktitle = "Proceedings of the NATO Conference on Commercial Off-The-Shelf + Products in Defence Applications: The Ruthless Pursuit of COTS", +Organization = "NATO", Address = "Brussels, Belgium", Year = "2000", +Pages="", Month = apr } + +@InProceedings{VidgerDean00, +Author = {M. Vidger and J. Dean}, +Title = {Maintaining {COTS}-Based Systems}, +Booktitle = "Proceedings of the NATO Conference on Commercial Off-The-Shelf + Products in Defence Applications: The Ruthless Pursuit of COTS", +Organization = "NATO", Address = "Brussels, Belgium", Year = "2000", +Pages="", Month = apr } + +@InProceedings{Jantsch00, +Author = {S. Jantsch}, +Title = {Risks by Using {COTS} Products and Commercial {ICT} Services}, +Booktitle = "Proceedings of the NATO Conference on Commercial Off-The-Shelf + Products in Defence Applications: The Ruthless Pursuit of COTS", +Organization = "NATO", Address = "Brussels, Belgium", Year = "2000", +Pages="", Month = apr } + +@InProceedings{Charpentier00, +Author = "R. Charpentier and M. Salois", +Title = "{MaliCOTS:} Detecting Malicious Code in {COTS} Software", +Booktitle = "Proceedings of the NATO Conference on Commercial Off-The-Shelf + Products in Defence Applications: The Ruthless Pursuit of COTS", +Organization = "NATO", Address = "Brussels, Belgium", Year = "2000", +Pages="", Month = apr } + +@InProceedings{Salois00, +Author = "M. Salois and R. Charpentier", +Title = "Dynamic Detection of Malicious Code in {COTS} Software", +Booktitle = "Proceedings of the NATO Conference on Commercial Off-The-Shelf + Products in Defence Applications: The Ruthless Pursuit of COTS", +Organization = "NATO", Address = "Brussels, Belgium", Year = "2000", +Pages="", Month = apr } + +@InProceedings{Rowlingson00, +Author = {R. Rowlingson}, +Title = {The Convergence of Military and Civil Approaches to Information + Security}, +Booktitle = "Proceedings of the NATO Conference on Commercial Off-The-Shelf + Products in Defence Applications: The Ruthless Pursuit of COTS", +Organization = "NATO", Address = "Brussels, Belgium", Year = "2000", +Pages="", Month = apr } + +@InProceedings{Schneidewind00, +Author = {N. Schneidewind}, +Title = {The Ruthless Pursuit of the Truth about {COTS}}, +Booktitle = "Proceedings of the NATO Conference on Commercial Off-The-Shelf + Products in Defence Applications: The Ruthless Pursuit of COTS", +Organization = "NATO", Address = "Brussels, Belgium", Year = "2000", +Pages="", Month = apr } + +@InProceedings{KerrMcCarthy00, +Author = "P. Kerr and J. McCarthy", +Title = "Application of {COTS} Communications Services for Command and + Control of Military Forces", +Booktitle = "Proceedings of the NATO Conference on Commercial Off-The-Shelf + Products in Defence Applications: The Ruthless Pursuit of COTS", +Organization = "NATO", Address = "Brussels, Belgium", Year = "2000", +Pages="", Month = apr } + +@InProceedings{Spinellis99, +Author={D. Spinellis}, +Title={Software Reliability: Modern Challenges}, +BookTitle={Proceedings of ESREL 99, Tenth European Conference on + Safety and Reliablity}, +Organization={}, Address={Munich-Garching, Germany}, +Year={1999}, Month=sep, pages={589--592}, +Note={Summarized in the Risks Forum, volume 20, number 64, 4 November 1998 + and ACM SIGSOFT {\it Software Engineering Notes 25,} 2, 17--18, March 2000.}} + +@InProceedings{Neumann00ICRE, +Author = "P.G. Neumann", +Title = "Certitude and Rectitude", +BookTitle={Proceedings of the 2000 International Conference on + Requirements Engineering}, +Organization={IEEE Computer Society}, Address={Schaumberg, Illinois}, +Year={2000}, Month=jun, pages={153}} + +@InProceedings{Parnas00ICRE, +Author = "D.L. Parnas", +Title = "Two Positions on Licensing", +BookTitle={Proceedings of the 2000 International Conference on + Requirements Engineering}, +Organization={IEEE Computer Society}, Address={Schaumberg, Illinois}, +Year={2000}, Month=jun, pages={154--155}} + +@InProceedings{Neumann00IEEE, +Author = "P.G. Neumann", +Title = "Robust Nonproprietary Software", +BookTitle={Proceedings of the 2000 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2000}, Month=may, pages={122--123}, +NOTE = {(\xlink{http://www.csl.sri.com/neumann/ieee00.ps}{http://www.csl.sri.com/neumann/ieee00.ps} and +\xlink{http://www.csl.sri.com/neumann/ieee00.pdf}{http://www.csl.sri.com/neumann/ieee00.pdf}) } } + +@InProceedings{Lipner00, +Author={S.B. Lipner}, +Title={Security and Source Code Access: Issues and Realities}, +BookTitle={Proceedings of the 2000 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2000}, Month=may, pages={124--125}} + +@InProceedings{Schneider00, +Author={F.B. Schneider}, +Title={Open Source in Security: Visiting the Bizarre}, +BookTitle={Proceedings of the 2000 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2000}, Month=may, pages={126--127}} + +@InProceedings{McGraw00, +Author={G. McGraw}, +Title={Will openish source really improve security?}, +BookTitle={Proceedings of the 2000 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2000}, Month=may, pages={128--129}} + +@InProceedings{Witten00, +Author={B. Witten and C. Landwehr and M. Caloyannides}, +Title={Will Open Source Really Improve Security?}, +BookTitle={2000 Symposium on Security and Privacy, oral presentation only}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2000}, Month=may, pages={}, +NOTE = "Paper available online: +\xlink{http://www.csl.sri.com/neumann/witten.pdf}{http://www.csl.sri.com/neumann/witten.pdf}."} + +@TechReport{Hissam01, +author={S. Hissam and C.B. Weinstock and D. Plakosh and J. Asundi}, +Title={Perspectives on Open Source Software}, +institution= {Carnegie-Mellon Software Engineering Institute}, +address={Pittsburgh, Pennsylvania 15213-3890}, +month =nov, Year=2001, +NOTE = {CMU/SEI-2001-TR-019\\ +(\xlink{http://www.sei.cmu.edu/publications/pubweb.html}{http://www.sei.cmu.edu/publications/pubweb.html}) } } + +@TechReport{Gacek01a, +author={C. Gacek and T. Lawrie and B. Arief}, +Title={The Many Meanings of Open Source}, +institution= {Department of Computing Science, + University of Newcastle upon Tyne}, +NOTE = "Technical Report CS-TR-737", +address={Newcastle, England}, month =aug, Year=2001 +} + +@TechReport{Gacek01b, +author={C. Gacek and C. Jones}, +Title={Dependability Issues in Open Source Software}, +institution= {Department of Computing Science, Dependable Interdisciplinary + Research Collaboration, University of Newcastle upon Tyne}, +NOTE = "Final report for PA5, part of ongoing related work.", +address={Newcastle, England}, month ={}, Year=2001 +} + +@TechReport{Jones02a, +author={C. Jones}, +Title={Providing a Formal Basis for Dependability Notions}, +institution= {Department of Computing Science, Dependable Interdisciplinary + Research Collaboration, University of Newcastle upon Tyne}, +NOTE = "UNU/IIST Anniversary Colloquium.", +address={Newcastle, England}, month ={}, Year=2002 +} + +@InProceedings{Balfanz+00, +Author={D. Balfanz and D. Dean and M. Spreitzer}, +Title={A Security Infrastructure for Distributed {Java} Applications}, +BookTitle={Proceedings of the 2000 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2000}, Month=may, pages={15--26}} + +@InProceedings{MillenRuess00, +Author={J. Millen and H. Ruess}, +Title={Protocol-Independent Secrecy}, +BookTitle={Proceedings of the 2000 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2000}, Month=may, pages={110--119}} + +@InProceedings{DM00, + author = {G. Denker and J. Millen}, + title = {{CAPSL} Integrated Protocol Environment}, + booktitle = {DARPA Information Survivability Conference (DISCEX 2000)}, + pages = {207--221}, + year = 2000, + publisher = {IEEE Computer Society} +} + +@Article{MD02, + author = {J. Millen and G. Denker}, + title = {{CAPSL} and {MuCAPSL}}, + journal = {Journal of Telecommunications and Information Technology}, + year = 2002, + volume = {}, + number = {4}, + pages = {16--27} +} + +@Unpublished{CAP02, + author = {J. Millen}, + title = {{CAPSL} {W}eb Site}, + year = 2002, + note = {{\tt http://www.csl.sri.com/\~{}millen/capsl}} +} + +@book{BowenHinchey, +Author={J.P. Bowen and M.G. Hinchey}, +Title={High-Integrity System Specification and Design}, +Publisher={Springer-Verlag, Berlin}, +Year={1999} } + +@article{Simons00UCITA, +author={B. Simons}, title = {Shrink-Wrapping Our Rights}, +journal = {Communications of the ACM}, volume = {43}, number = {8}, +pages = {}, month = aug, year = {2000} } + +@PhDThesis{MercuriThesis00, +Author={R. Mercuri}, +School={Department of Computer Science, University of Pennsylvania}, +Title={Electronic Vote Tabulation Checks and Balances}, +Year={2001}, Month={}, +NOTE = +"\xlink{http://www.notablesoftware.com/evote.html}{http://www.notablesoftware.com/evote.html}" } + +@Article{Mercuri02, +Author={R. Mercuri}, +Title={A Better Ballot Box: New electronic voting systems + pose risks as well as solutions}, +Journal={IEEE Spectrum}, +month=oct, pages ={46--50}, +year="2002"} + +@Article{Mercuri02x, +Author={H. Riebeek}, +Title={Brazil Holds All-Electronic National Election}, +Journal={IEEE Spectrum}, +month=nov, pages ={25--26}, +year="2002"} + +@article{Mercuri03, +author={R. Mercuri}, title = {On Auditing Audit Trails}, +journal = {Communications of the ACM}, volume = {46}, number = {1}, +pages = {17--20}, month = jan, year = {2003} } + +@InProceedings{Holt03, +Author={R. Holt}, +Title={Introduction of the Voter Confidence and Increased +Accessibility Act of 2003}, +BookTitle={U.S. Congressional Record, Extensions of Remarks}, +Organization={U.S. Congress}, Address={}, +Year={2003}, Month={May 23}, pages={E1081-2}} + +@inProceedings{Neumann03Open, +Author="P.G. Neumann", +Title="Attaining Robust Open-Source Software", +Booktitle= + "Making Sense of the Bazaar: Perspectives on Open Source and Free Software", +Note ="Joseph Feller, Brian Fitzgerald, Scott Hissam and Karim Lakhani + (editors)", +Publisher = "O'Reilly and Associates, Sebastopol, California", + Year="2003", Pages="123--126"} + +@Book{Feller+05, +Author="J. Feller and B. Fitzgerald and S.A. Hissam and {K.R. Lakhani, +editors}", +Title="Perspectives on Free and Open Source Software", +Publisher = "MIT Press, Cambridge, Massachusetts", + Year="2005", +NOTE = "The entire book is now available as a pdf file, courtesy of +the MIT Press: +http://mitpress.mit.edu/catalog/item/default.asp?ttype=2\&tid=10477\&mode=toc" +} + +@TechReport{CaltechMIT01, +author={{Caltech MIT Voting Technology Project}}, +Title={Voting What Is What Could Be}, +institution= {Caltech and MIT}, +address={}, month =jul, Year=2001 } + +@TechReport{GWU01, +author={{Democracy Online Project}}, +Title={A Debate on Computerized Voting: A New Solution for a New + Generation of Voters}, +institution= {George Washington University, Washington, D.C.}, +address={}, month =jan, Year=2001} + +@TechReport{Chaum02, +author={D. Chaum}, +Title={Secret-Ballot Receipts and Transparent Integrity: + Improving voter confidence \& electronic voting at polling places}, +institution= {}, +address={}, month =mar, Year=2002, +NOTE = "(\xlink{http://www.chaum.org}{http://www.chaum.org})" } + +@article{Rubin02, +author={A. Rubin}, title = {Security Considerations for Remote + Electronic Voting}, +journal = {Communications of the ACM}, volume = {45}, number = {12}, +pages = {39--44}, month = dec, year = {2002} } + +@article{SERVE04, +author={D. Jefferson and A.D. Rubin and B. Simons and D. Wagner}, +title = {Analyzing Internet Voting Security}, +journal = {Communications of the ACM}, volume = {47}, number = {10}, +pages = {}, month = oct, year = {2004} } + +@PhDThesis{ChenxiThesis, +Author={C. Wang}, +School={Department of Computer Science, University of Virginia}, +Title={A Security Architecture for Survivable Systems}, +Year={2001}, Month=jan, +Note="(\xlink{http://www.cs.virginia.edu}{http://www.cs.virginia.edu})" } + +@PhDThesis{WagnerThesis00, +Author={D. Wagner}, +School={Division of Computer Science, University of California, Berkeley}, +Title={Static Analysis and Computer Security: New Techniques for Software + Assurance}, +Year={2000}, Month=dec, +Note="(\xlink{http://www.cs.berkeley.edu/\~{}daw}{http://www.cs.berkeley.edu/\~{}daw})" } + +@InProceedings{WagnerDean01, +Author={D. Dean and D. Wagner}, +Title={Intrusion Detection via Static Analysis}, +BookTitle={Proceedings of the 2001 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2001}, Month=may, pages={}} + +@InProceedings{ChenWagnerDean02, +Author={H. Chen and D. Wagner and D. Dean}, +Title={Setuid Demystified}, +BookTitle={Proceedings of the 11th USENIX Security 2002}, +Organization={USENIX}, Address={San Francisco, California}, +Year={2002}, Month=aug, pages={171--190}} + +@InProceedings{ChenDeanWagner03, +Author={H. Chen and D. Dean and D. Wagner}, +Title={Model Checking One Million Lines of Code}, +BookTitle={Proceedings of the Symposium on Network and Distributed + System Security}, +Organization={Internet Society}, Address={San Diego, California}, +Year={2004}, Month=feb, pages={171--185}} + +@InProceedings{SastryKohnoWagner06, +Author={N. Sastry and T. Kohno and D. Wagner}, +Title={Designing voting machines for verification}, +BookTitle={Proceedings of the 11th USENIX Security 2006}, +Organization={USENIX}, Address={San Francisco, California}, +Year={2006}, Month=aug, pages={}, +url ="http://www.cs.berkeley.edu/~{}daw/papers/varch-use06.pdf"} + +@InProceedings{ChenWagner02, +Author={H. Chen and D. Wagner}, +Title={{MOPS:} {An} Infrastructure for Examining Security Properties + of Software}, +Organization={ACM}, Address={Washington, D.C.}, +BookTitle={Ninth ACM Conference on Computer and Communications Security}, +Year={2002}, Month=nov, pages={} } + +% http://www.cs.berkeley.edu/~daw/papers/varch-use06.pd + +@InProceedings{Chen:2004:EROS, + author = {H. Chen and J. Shapiro}, + title = {Using Build-Integrated Static Checking to Preserve +Correctness Invariants}, + booktitle = {Proceedings of the Eleventh ACM Conference on Computer and +Communications Security (CCS)}, + year = {2004}, + address = {Washington, D.C.}, + month = nov, + pages = {} +} + +@PhdThesis{Chen:2004:dissertation, + author = {H. Chen}, + title = {Lightweight Model Checking for Improving Software Security}, + school = {University of California, Berkeley}, + year = {2004}, +NOTE = "\xlink{http://www.cs.ucdavis.edu/\~{}hchen/paper/phddis.ps}{http://www.cs.ucdavis.edu/\~{}hchen/paper/phddis.ps}" +} + +@PhdThesis{Yee07, + author = {K.-P. {Yee}}, + title = {Building Reliable Voting Machine Software}, + school = {University of California, Berkeley}, + year = {2007}, + NOTE = {Technical Report 2007-167; see also Technical Note 2007-136 for + the security review; http://pvote.org} +} + +@InProceedings{Backes+03, +Author={M. Backes and B. Pfitzmann and M. Waidner}, +Title={A Universally Composable Cryptographic Library with Nested Operations}, +Organization={ACM}, Address={Washington, D.C.}, +BookTitle={Tenth ACM Conference on Computer and Communications Security}, +Year={2003}, Month=oct, pages={} } + +@InProceedings{BackesPfitzmann03, +Author={M. Backes and B. Pfitzmann}, +Title={A Cryptographically Sound Security Proof of + the {Needham-Schroeder-Lowe} Public-Key Protocol}, +Organization={}, Address={Mumbai, India}, +BookTitle={23rd Conference on Foundations of Software Technology + and Theoretical Computer Science (FSTTCS)}, +Year={2003}, Month=dec, pages={} } + +@InProceedings{Weeks01, +Author={S. Weeks}, +Title={Understanding Trust Management Systems}, +BookTitle={Proceedings of the 2001 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2001}, Month=may, pages={}, +NOTE="(\xlink{http://www.star-lab.com/tr/star-tr-01-02.html}{http://www.star-lab.com/tr/star-tr-01-02.html})" +} + +@InProceedings{Gunter+01, +Author={C. Gunter and S. Weeks and A. Wright}, +Title={Models and Languages for Digital Rights}, +BookTitle={Proceedings of the 2001 Hawaii Intenational Conference + on Systems Science}, +Organization={}, Address={Honolulu, Hawaii}, +Year={2001}, Month=mar, pages={}, +NOTE = "\xlink{http://www.star-lab.com/tr/star-tr-01-04.html}{http://www.star-lab.com/tr/star-tr-01-04.html}" +} + +@InProceedings{Goerigk00, +Author = "W. Goerigk", +Title = "Compiler Verification Revisited", +Booktitle = "{Computer Aided Reasoning: {ACL2} Case Studies}", +Editor = "M. Kaufmann and P. Maniolis and J S. Moore", +Organization = "Kluwer Academic Publishers", Address = "", Year = "2000", +Note ="Chapter 15", Pages="", Month = "" } + +@TechReport{Faughn01, +author={A.W. Faughn}, +Title={Interoperability: Is It Achievable?}, +institution= {Harvard University PIRP report}, +address={}, month ={}, Year=2001 } + +@book{Curtin02, +Author={M. Curtin}, +Title={Developing Trust: Online Security and Privacy}, +Publisher={Apress, Berkeley, California, and Springer-Verlag, Berlin}, +Year={2002} } + +@TechReport{Boudra92, +author={P. {Boudra, Jr.}}, +Title={Minutes of the Meetings of the System Composition Working Group, + Volume 1}, +institution= {National Security Agency, Information Systems Security + Organization, Office of Infosec Systems Engineering, S9 Technical + Report 6-92, Library No. S-239, 646}, +address={}, month =oct, Year=1992, NOTE ="For Official Use Only." } + +@TechReport{NSAcompose92xxx, +author={P. {Boudra, Jr.}}, +Title={Minutes of the Meetings of the System Composition Working Group, +volume 1}, +institution= {Information Systems Security Organization, Office of +INFOSEC Systems Engineering, NSA}, +Note = {S9 Technical Report 6-92, For Official Use Only}, +address={}, month ={5 October}, Year=1992 } + +@TechReport{Boudra93, +author={P. {Boudra, Jr.}}, +Title={Report on Rules of System Composition: Principles of Secure + System Design}, +institution= {National Security Agency, Information Systems Security + Organization, Office of Infosec Systems Engineering, I9 Technical + Report 1-93, Library No. S-240, 330}, +address={}, month =mar, Year=1993, NOTE ="For Official Use Only." } + +@TechReport{Lee92, +author={E.S. Lee and P.I.P. Boulton and B.W. Thompson and R.E. Soper}, +Title={Composable Trusted Systems}, +institution= {Computer Systems Research Institute, University of + Toronto, Technical Report CSRI-272}, +address={}, month =may, Year=1992 } + +@TechReport{ICS94, +author={Unspecified}, +Title={Composability Constraints of Multilevel Systems}, +institution= {Integrated Computer Systems, Inc.}, +address={215 South Rutgers Ave., Oak Ridge, Tennessee}, +month =jun, Year=1994 } + +@TechReport{Tinto92, +author={M. Tinto}, +Title={The Design and Evaluation of {INFOSEC} Systems: The Computer + Security Contribution to the Composition Discussion}, +institution= {National Computer Security Center}, +address={}, month =jun, Year=1992, Note="C Technical Report 32-92" } + +@TechReport{Abrams92, +author={M.D. Abrams and M.V. Joyce}, +Title={Composition of Trusted {IT} Systems}, +institution= {MITRE}, +address={}, month =sep, Year=1992, Note ="Draft." } + +@InProceedings{Hemenway92, +author={J. Hemenway and D. Gambel}, +Title={Issues in the Specification of Composite Trustworthy Systems}, +Booktitle = "Fourth Annual Canadian Computer Security Symposium", +address={}, month =may, Year=1992 } + +@TechReport{Ozier, +author={W. Ozier}, +Title={{GASSP: Generally Accepted Systems Security Principles}}, +institution= {International Information Security Foundation}, +address={}, month =jun, Year=1997, +NOTE ="\xlink{web.mit.edu/security/www/gassp1.html}{http://web.mit.edu/security/www/gassp1.html}" + } + +@book{Beck99, +Author={K. Beck}, +Title={Extreme Programming Explained: Embrace Change}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={1999}, +Note="(\xlink{http://www.extremeprogramming.org}{http://www.extremeprogramming.org})" +} + +@InProceedings{Chander+01, +author={A. Chander and D. Dean and J.C. Mitchell}, +Title={A State-Transition Model of Trust Management}, +BookTitle ={Proceedings of the 14th IEEE Computer Security Foundations Workshop}, +Organization= + {IEEE Computer Society Technical Committee on Security and Privacy}, + Address={Cape Breton, Nova Scotia, Canada}, + Year={2001}, Month=jun, pages={27--43} + } + +@InProceedings{Chander+02, +Author={A. Chander and D. Dean and J.C. Mitchell}, +Title={Deconstructing Trust Management}, +BookTitle= + {Proceedings of the 2002 Workshop on Issues in the Theory of Security}, +Organization={IFIP Working Group 1.7}, Address={Portland, Oregon}, +Year={2002}, Month=jan, pages={}} + +@InProceedings{Chander+04a, +Author={A. Chander and D. Dean and J.C. Mitchell}, +Title={A Distributed High Assurance Reference Monitor}, +BookTitle= {Proceedings of the Seventh Information Security Conference + Lecture Notes in Computer Science vol. 3225}, +Year={2004}, Month=sep, pages={231--244}, +Organization={Springer-Verlag}, Address={Berlin}, +url = "http://www.csl.sri.com/users/ddean/papers/isc04.pdf"} + +@Article{Chander+04, +Author={A. Chander and D. Dean and J.C. Mitchell}, +Title={Reconstructing Trust Management}, +Journal= {Journal of Computer Security}, +Volume = {12}, Number = {1}, +Year={2004}, Month=jan, pages={131--164}, +url = "http://www.csl.sri.com/users/ddean/papers/jcs04.pdf"} + +@book{deRoever01, +Author={W.-P. {de Roever} and F. de Boer and U. Hanneman and J. Hooman and + Y. Lakhnech and M. Poel and J. Zwiers}, +Title={Concurrency Verification: Introduction to Compositional and + Noncompositional Methods}, +Publisher={Cambridge University Press, New York, NY}, +Note = {Cambridge Tracts in Theoretical Computer Science no. 54}, +Year={2001} } + +@InProceedings{McDanielPrakash02, +Author={P. McDaniel and A. Prakash}, +Title={Methods and Limitations of Security Policy Reconciliation}, +BookTitle={Proceedings of the 2002 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2002}, Month=may, pages={73--87}} + +@InProceedings{Mantel01IEEE, +Author={H. Mantel}, +Title={Preserving information flow properties under refinement}, +BookTitle={Proceedings of the 2001 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2001}, Month=may, pages={78--91}} + +@InProceedings{Mantel02IEEE, +Author={H. Mantel}, +Title={On the composition of secure systems}, +BookTitle={Proceedings of the 2002 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2002}, Month=may, pages={88--101}} + +@InProceedings{AshcraftEngler02, +Author={K. Ashcraft and D. Engler}, +Title={Detecting Lots of Security Holes Using System-Specific Static Analysis}, +BookTitle={Proceedings of the 2002 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2002}, Month=may, pages={143--159}} + +@InProceedings{Chess02, +Author={B.V. Chess}, +Title={Improving Computer Security Using Extended Static Checking}, +BookTitle={Proceedings of the 2002 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2002}, Month=may, pages={160--173}} + +@InProceedings{Ko02, +Author={C. Ko}, +Title={Noninterference and Intrusion Detection}, +BookTitle={Proceedings of the 2002 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2002}, Month=may, pages={177--187}} + +@InProceedings{Dutertre02, +Author={B. Dutertre and V. Crettaz and V. Stavridou}, +Title={Intrusion-Tolerant Enclaves}, +BookTitle={Proceedings of the 2002 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2002}, Month=may, pages={216--224}} + +@InProceedings{Park+02, +Author={J.M. Park and E.K.P. Chong and H.J. Siegel}, +Title={Efficient Multicast Packet Authentication Using Signature + Amortization}, +BookTitle={Proceedings of the 2002 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2002}, Month=may, pages={227--240}} + +@InProceedings{Staddon+02, +Author={J. Staddon and S. Miner and M. Franklin and D. Balfanz and M. Malkin + and D. Dean }, +Title={Self-Healing Key Distribution with Revocation}, +BookTitle={Proceedings of the 2002 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2002}, Month=may, pages={241--257}} + +@InProceedings{Song+02, +Author={D. Song and D. Zuckerman and J.D. Tygar}, +Title={Expander Graphs for Digital Stream Authentication and Robust + Overlay Networks}, +BookTitle={Proceedings of the 2002 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2002}, Month=may, pages={258--270}} + +@InProceedings{Dean02, +Author={D. Dean}, +Title={The Impact of Programming Language Theory on Computer Security}, +BookTitle={Proceedings of the Mathematical Foundations of Programming + Semantics (MFPS)}, +Organization={}, Address={New Orleans, Louisiana}, +Year={2002}, Month=mar, pages={}, +NOTE={Slides at \xlink{http://www.csl.sri.com/neumann/ddean-MFPS02.ppt}{http://www.csl.sri.com/neumann/ddean-MFPS02.ppt}} +} + +@article{Neumann04Opt, +author={P.G. Neumann}, +title = {Optimistic Optimization}, +journal = {Communications of the ACM}, year = {2004}, volume = {47}, +number = {6}, pages = {112}, month = jun, +Note= {{\it Inside Risks} column.} } + +@article{Neumann06comp, +author={P.G. Neumann}, +title = {Risks Relating to System Compositions}, +journal = {Communications of the ACM}, year = {2006}, volume = {49}, +number = {7}, pages = {128}, month = jul, +Note= {{\it Inside Risks} column.} } + +@article{Bellovin06, +author={Steven M. Bellovin}, +title = {Virtual Machines, Virtual Security?}, +journal = {Communications of the ACM}, year = {2006}, volume = {49}, +number = {10}, pages = {104}, month = oct, +Note= {{\it Inside Risks} column.} } + +@InProceedings{Neumann06CCS, + author = {P.G. Neumann}, + title = {System and Network Trustworthiness in Perspective}, + booktitle = {Proceedings of the Thirteenth ACM Conference on Computer and +Communications Security (CCS)}, + year = {2006}, + address = {Alexandria, Virginia}, + month = nov, + pages = {1--5} +} + +@InProceedings{Neumann06ACSAC, +Author="P.G. Neumann", +Title="Risks of Untrustworthiness", +BookTitle="Proceedings of the 22nd Annual Computer Security Applications +Conference (ACSAC 2006), Classic Papers section", +Organization="IEEE Computer Society", +Address="Miami, Florida", Year="2006", Month=dec, pages="", +url={http://www.acsac.org/ and http://www.csl.sri.com/neumann/psos03.pdf} +} + +@ARTICLE{Neumann06holistic, +Author={Peter G. Neumann}, +TITLE = {Holistic Systems}, +JOURNAL = {ACM Software Engineering Notes}, YEAR = {2006}, VOLUME = {31}, +NUMBER = {6}, PAGES = {4--5}, MONTH = nov +} + +@InProceedings{Neumann07EEVS, +Author={P.G. Neumann}, +Title={Security and Privacy in the Employment Eligibility + Verification System (EEVS) and Related Systems}, +BookTitle={Congressional Record}, +Organization={U.S. House of Representatives}, Address={Washington, DC}, +Year={2007}, Month={Jun 7}, pages={}, +URL ="http://www.csl.sri.com/neumann/house07.pdf" } + +@InCollection{Neumann07Reflections, +Author = "P.G. Neumann", +Title = "Reflections on System Trustworthiness", +Editor = "Marvin Zelkowitz", +Booktitle = "Advances in Computers, volume 70", +Publisher = "Elsevier Inc.", Year = "2007 ", +Pages="269--310" } + +@book{NRC07cyber, +author = {S.E. Goodman and H.S. {Lin, editors}}, +title = {Toward a Safer and More Secure Cyberspace}, +publisher = {National Research Council, National Academies Press, +2101 Constitution Ave., Washington, D.C.}, +year = {2007}, note={Final report of the National Research +Council Committee on Improving Cybersecurity Research in the United States.} } + +@InProceedings{Neumann09CSH, +Author={P.G. Neumann}, +Title={The Future of Information Assurance}, +BookTitle={Computer Security Handbook}, +Organization={John Wiley \& Sons}, Address={New York}, +Year={2009}, Month={}, pages={}, NOTE={Volume 2, invited final chapter.}} + +@InProceedings{Neumann09LAW, +Author={P.G. Neumann}, +Title={Hierarchies, Lowerarchies, Anarchies, and Plutarchies: + Historical Perspectives of Composable High-Assurance Architectures}, +BookTitle={Third Layered Assurance Workshop}, +Organization={AFRL}, Address={San Antonio CA}, +Year={2009}, Month=aug, pages={}, Note ={Slides at + http://www.csl.sri.com/neumann/law09+x4.pdf}} + +@InProceedings{Neumann09idtrust, +Author={P.G. Neumann}, +Title={IDentity and Trust in Context}, +BookTitle={IDtrust Workshop}, +Organization={NIST}, Address={Gaithersburg, Maryland}, +Year={2009}, Month=apr, pages={}, Note ={Slides at + http://www.csl.sri.com/neumann/itrust09+x4.pdf}} + +@InProceedings{NeumannDag08, +Author={P.G. Neumann}, +Title={Combatting Insider Misuse, with Relevance to Integrity and + Accountability in Elections and Other Applications}, +BookTitle={Dagstuhl Workshop on Insider Threats}, +Organization={}, Address={Schloss Dagstuhl, Germany}, +Year={2008}, Month=jul, pages={}} + +@Inbook{Neumann09insiders, +Author={P.G. Neumann}, +Title={Combatting Insider Threats}, +BookTitle = {Insider Threats in Cybersecurity -- and Beyond}, +Editors= {M. Bishop and C.W. Probst}, +Publisher={Springer Verlag}, +Year={2010} } + +@Inbook{Neumann10Dagbook, +Author={P.G. Neumann}, +Title={Combatting Insider Threats}, +Chapter = {2}, +Note = {In {\it Insider Threats in Cybersecurity -- and Beyond,} + C.W. Probst and J. Hunker and D. Gollman and M. Bishop + (editors), Springer Verlag}, +Publisher={Springer Verlag}, +Year = {2010}, +} + +@InProceedings{Ox, +Author={P.G. Neumann and M. Bishop and S. Peisert and M. Schaefer}, +Title={Reflections on the 30th Anniversary of the IEEE Symposium on + Security and Privacy}, +BookTitle={Proceedings of the 2010 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2010}, Month=may, pages={}} + +@TechReport{HPL05, +author={IRC}, +Title={Hard Problem List}, +institution= {INFOSEC Research Council}, +address={}, month =nov, Year=2005, +url ="http://www.cyber.st.dhs.gov" +} + +@TechReport{Roadmap09, +author={D. {Maughan et al.}}, +Title={A Roadmap for Cybersecurity Research}, +institution= {Department of Homeland Security}, +address={}, month =nov, Year=2009, +url ="http://www.cyber.st.dhs.gov" +} + +@Article{Bellovin+07, +Author={}, +Title={}, +Journal={IEEE Security and Privacy}, VOLUME = {6}, NUMBER = {1}, +Year={2008}, Month={January-February}, pages={}} + +@book{HennessyPatterson95, +Author={J.L. Hennessy and D.A. Patterson}, +Title={Computer Architecture: A Quantitative Approach, Second Edition}, +Publisher={Morgan Kaufmann}, +Year={1996} } + +@book{PattersonHennessy97, +Author={D.A. Patterson and J.L. Hennessy}, +Title={Computer Organization and Design: The Hardware/Software + Interface, Second Edition}, +Publisher={Morgan Kaufmann}, +Year={1997} } + +@InProceedings{Zuck+02, +Author={L. Zuck and A. Pnueli and Y. Fang and B. Goldberg}, +Title={{VOC:} {A} Translation Validator for Optimizing Compilers}, +BookTitle={Electronic Notes in Theoretical Computer Science}, +Organization={}, Address={}, +Year={2002}, Month={}, pages={}, +URL = "http://www.cs.nyu.edu/\~{}zuck/pubs/" +} + +@book{Bishop02, +Author={M. Bishop}, +Title={Computer Security: Art and Science}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={2002} } + +@book{Bishop04, +Author={M. Bishop}, +Title={Introduction to Computer Security}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={2004} } + +@book{Bish2003, + Address = {Boston, MA}, + Author = {M. Bishop}, + Date-Modified = {2007-04-18 11:50:16 -0700}, + Publisher = {Addison-Wesley Professional}, + Title = {Computer Security: Art and Science}, + Year = {2003}} + +@InProceedings{Bishop05, +Author={M. Bishop}, +Title={Position: {`Insider'} is relative}, +BookTitle={Proceedings of the 2005 New Security Paradigms Workshop}, +Organization={}, Address={Lake Arrowhead, California}, +Year={2005}, Month=oct, pages={77-78}} + +@InProceedings{Bishop08+, +Author={M. Bishop and S. Engle and C. Gates and S. Peisert and S. Whalen}, +Title={We Have Met the Enemy and He Is Us}, +BookTitle={Proceedings of the 2008 New Security Paradigms Workshop}, +Organization={}, Address={Olympic Valley, California}, +Year={2008}, Month={}, pages={}} + +@book{Stolfo+08, +Author={S. Stolfo and S. Bellovin and S. Hershkop and S. Sinclair and + S. Smith}, +Title={Insider Attack and Cyber Security: Beyond the Hacker}, +Publisher={Springer}, +Year={2008} } + +@book{Anderson01, +Author={R.J. Anderson}, +Title={Security Engineering: {A} guide to + Building Dependable Distributed Systems}, +Publisher={John Wiley and Sons, New York}, +Year={2001} } + +@book{Sommerville01, +Author={I. Sommerville}, +Title={Software Engineering}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Note = {Sixth Edition.}, +Year={2001} } + +@book{Reppy99, +Author={J.H. Reppy}, +Title={Concurrent Programming in ML}, +Publisher={Cambridge University Press, Cambridge, U.K.}, +Year={1999} } + +@InProceedings{Giffin+02, +Author={J.T. Giffin and S. Jha and B.P. Miller}, +Title={Detecting Manipulated Remote Call Streams}, +BookTitle={Proceedings of the 11th USENIX Security 2002}, +Organization={USENIX}, Address={San Francisco, California}, +Year={2002}, Month=aug, pages={61--79}} + +@InProceedings{AppelMacQueen91, +Author={A.W. Appel and D.B. MacQueen}, +Title={Standard {ML} of {New Jersey}}, +BookTitle={Programming Language Implementation and Logic Programming, + Lecture Notes in Computer Science vol. 528}, +Organization={Springer-Verlag}, Address={Berlin}, +Year={1991}, Month={}, pages={1--26}} + +@book{Milner+97, +Author={R. Milner and M. Tofte and R. Harper and D. MacQueen}, +Title={The Definition of Standard ML}, +Publisher={MIT Press, Cambridge, Massachusetts}, +Year={1997} } + +@book{WrightStevens95, +Author={G.R. Wright and W.R. Stevens}, +Title={TCP/IP Illustrated, Volume 2}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={1995} } + +@book{HuntTCP/IP02, +Author={C. Hunt}, +Title={TCP/IP Network Administration, 3rd Edition}, +Publisher={O'Reilly \& Associates, Sebastopol, California}, +Year={2002} } + +@InProceedings{Sheyner+02, +author={O. Sheyner and J. Haines and S. Jha and R. Lippmann and J.M. Wing}, +Title={Automated Generation and Analysis of Attack Graphs}, +BookTitle={Proceedings of the 2003 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2003}, Month=may, pages={273--284}} + +@InProceedings{JhaSheynerWing02, +author={S. Jha and O. Sheyner and J. Wing}, +Title={Two Formal Analyses of Attack Graphs}, +BookTitle ={Proceedings of the 15th IEEE Computer Security Foundations Workshop}, +Organization= + {IEEE Computer Society Technical Committee on Security and Privacy}, + Address={Cape Breton, Nova Scotia, Canada}, + Year={2002}, Month=jun, pages={49--64} + } + +@InProceedings{Govinda+03, +Author={S. Govindavajhala and A.W. Appel}, +Title={Using Memory Errors to Attack a Virtual Machine}, +BookTitle={Proceedings of the 2003 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2003}, Month=may, pages={154--165}} + +@book{Barnes03, +Author={J. Barnes}, +Title={High Integrity Software: The SPARK Approach to Safety and Security}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +NOTE = {Reviewed in The ACM Risks Forum, 23, 01.}, +Year={2003} } + +@article{Weinstein03-12, +author={L. Weinstein}, +title = {The Devil You Know}, +journal = {Communications of the ACM}, year = {2003}, volume = {46}, +number = {12}, pages = {144}, month = dec } + +@TechReport{Weinstein:tripoli, +author = {L. Weinstein}, +title = {{TRIPOLI: An Empowered E-Mail Environment}}, +institution ={People for Internet Responsibility}, +url = "http://www.pfir.org/tripoli-overview", +year ={2004}, month = jan +} + +@TechReport{Cusumano03, +author={M. Cusumano and A. MacCormack and C.F. Kemerer and W. Crandall}, +Title={A Global Survey of Software Development Practices}, +institution= {MIT Sloan School of Management}, +address={Cambridge, Massachusetts}, month =jun, Year=2003, +url = "http://ebusiness.mit.edu/research/papers/178_Cusumano_Intl_Comp.pdf" } + +@Article{McGraw04, +Author={G. McGraw}, +Title={Software Security}, +Journal={IEEE Security and Privacy}, +Organization={IEEE Computer Society}, +Year={2004}, Month={March-April}, volume ={2}, number = {2}, pages={80--83}} + +@article{Chaum04, +author={D. Chaum}, +Title={Secret-Ballot Receipts: True Voter-Verifiable Elections}, +Journal={IEEE Security and Privacy}, +Organization={IEEE Computer Society}, +Year={2004}, Month={January-February}, volume ={2}, number = {1}, +pages={38--47}} + +@TechReport{Rivest06, +author={R.L. Rivest}, +Title={The {ThreeBallot Voting System}}, +institution= {MIT}, +address={Cambridge, Massachusetts}, month =oct, Year=2006, +URL= +"http://theory.csail.mit.edu/~{}rivest/Rivest-TheThreeBallotVotingSystem.pdf" +} + +@InProceedings{Ratan+96, +Author={V. Ratan and K. Partridge and J. Reese and N. Leveson}, +Title={Safety Analysis Tools for Requirements Specification}, +BookTitle={Proceedings of the Eleventh Annual Conference on Computer + Assurance, COMPASS '96}, +Organization={IEEE Computer Society}, Address={}, +Year={1996}, Month={}, pages={149--160}, + url ="http://www.safeware-eng.com/index.php/publications/SafAnTooReq"} + +@TechReport{DSB01a, +author={Defense Science Board}, +Title={Protecting the Homeland, Volume I}, +institution= {Defense Science Board Task Force on Defensive Information + Operations 2000 Summer Study}, +address={}, month =feb, Year="2001" } + +@TechReport{DSB01b, +author={Defense Science Board}, +Title={Protecting the Homeland, Volume II}, +institution= {Defense Science Board Task Force on Defensive Information + Operations 2000 Summer Study}, +address={}, month =mar, Year="2001" } + +@InProceedings{Kohno+04, +Author={T. Kohno and A. Stubblefield and A.D. Rubin and D.S. Wallach}, +Title={Analysis of an Electronic Voting System}, +BookTitle={Proceedings of the 2004 Symposium on Security and Privacy}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2004}, Month=may, pages={27--40}} + +@InProceedings{Datta+04, +Author={A. Datta and R. K\"{u}sters and J.C. Mitchell and A. Ramanathan and + V. Shmatikov}, +Title={Unifying Equivalence-Based Definitions of Protocol Security}, +BookTitle={Proceedings of the ACM SIGPLAN and IFIP WG 1.7 Fourth Workshop + on Issues in the Theory of Security}, +Organization={IEEE Computer Society}, Address={Oakland, California}, +Year={2004}, Month=apr, pages={}} + +@TechReport{GAO04Acq, +author={USGAO}, +Title={Defense Acquisitions: Knowledge of Software Suppliers Needed + to Manage Risks}, +institution= {U.S. General Accounting Office, GAO-04-078}, +address={Washington, D.C.}, month =may, Year=2004 } + +@Article{Clarke04IEEE, +Author={G. Goth}, +Title={Richard {Clarke} Talks Cybersecurity and {JELL-O}}, +Journal={IEEE Security and Privacy}, VOLUME = {2}, NUMBER = {3}, +Year={2004}, Month={May-June}, pages={11--15}} + +@Article{Tsik06, +Author={K. Tsikpenyuk and B. Chess and G. McGraw}, +Title={Seven Pernicious Kingdoms: A Taxonomy of Software Security Errors}, +Journal={IEEE Security and Privacy}, VOLUME = {3}, NUMBER = {6}, +Year={2005}, Month={November-December}, pages={}, +doi="10.1109/MSP.2005.159"} + +@ARTICLE{Jackson02, +Author={D. Jackson}, TITLE = {Alloy: + {A} lightweight object modelling notation}, +JOURNAL = {ACM Transactions on Software Engineering Methodology}, +YEAR = {20}, VOLUME = {11}, +NUMBER = {2}, PAGES = {256--290}, MONTH = {}, +url ="http://sdg.lcs.mit.edu/~{}dnj/", +url ="http://alloy.mit.edu/" } + +@TechReport{Shands04+, +author={D. Shands and E. Wu and J. Horning and S. Weeks}, +Title={SPiCE: Configurationa Synthesis for Policies Enforcement}, +institution= {MacAfee Research Technical Report 04-018}, +address={}, month =jun, Year=2004 } + +@ARTICLE{Wheeler04, +Author={D.A. Wheeler}, TITLE = {Secure programmer: Minimizing Privileges; +Taking the fangs out of bugs}, +JOURNAL = {}, YEAR = {2004}, VOLUME = {}, +NUMBER = {}, PAGES = {}, MONTH = may, +URL= "http://www-106.ibm.com/developerworks/linux/library/l-sppriv.html?ca=dgr-lnxw04Privileges" } + +@book{WheelerBook, +Author={D.A. Wheeler}, +Title={Secure Programming for Linux and Unix {HOWTO}}, +Publisher={}, +Year={2003}, +URL = "http://www.dwheeler.com/secure-programs" } + +@book{USDP99, +Author={I. Jacobson and G. Booch and J. Rumbaugh}, +Title={The Unified Software Development Process}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={1999} } + +@book{Bejtlich04, +Author={R. Bejtlich}, +Title={The Tao of Network Security Monitoring}, +Publisher={Addison-Wesley, Reading, Massachusetts}, +Year={2004} } + +@Article{Smith04, + Author = {M.A. Smith}, +Title = {Portals: Toward an Application Framework for Interoperability}, + Journal = {Communications of the ACM}, + Year = {2004}, + Volume = {47}, + Number = {10}, + Pages = {93--97}, + Month = oct } + +@book{KrafzigSOA, +Author={D. Krafzig and K. Banke and D. Slama}, +Title={Enterprise SOA Service-Oriented Architecture Best Practices}, +Publisher={Prentice-Hall, Upper Saddle River, New Jersey}, +Year={2004} } + +@ARTICLE{ERCIM04, +Author={Numerous authors}, +TITLE = {Automated Software Engineering (special section)}, +JOURNAL = {ERCIM News}, YEAR = {2004}, VOLUME = {}, +NUMBER = {58}, PAGES = {12--51}, MONTH = jul } + +@ARTICLE{Blanc04, +Author={B. Blanc}, +TITLE = {{GATeL:} {A}utomatic Test Generation from {Lustre} Descriptions}, +JOURNAL = {ERCIM News}, YEAR = {2004}, VOLUME = {}, +NUMBER = {58}, PAGES = {29--30}, MONTH = jul } + +@inCollection{PetersonClark04, +author = {L. Peterson and D. Clark}, +title = {The {Internet:} {An} Experiment that Escaped from the Lab}, +booktitle = {Computer Science: Reflections on the Field, Reflections + from the Field}, +publisher = {National Research Council, + National Academies Press, 500 Fifth Ave., Washington, D.C. 20001}, +pages = {129--133}, +year = {2004} } + +@InProceedings{Crnkovic04, +Author = "I. Crnkovic and M. Larsson", +Title = "Classification of Quality Attributes for Predictability in + Component-based Systems", +Booktitle = "Workshop on Architecting Dependable Systems (DSN WADS 2004)", +Organization = "", Address = "Florence, Italy", Year = "2004", +Pages="", Month = jun, +NOTE = "\xlink{http://www.cs.kent.ac.uk/events/conf/2004/wads/DSN-WADS2004/indexProgDSN2004.html}{http://www.cs.kent.ac.uk/events/conf/2004/wads/DSN-WADS2004/indexProgDSN2004.html}" + } + +@INCOLLECTION{Smith2004, + AUTHOR = {Jonathan M. Smith and Michael B. Greenwald and Sotiris + Ioannidis and Angelos D. Keromytis and Ben Laurie and Douglas Maughan + and Dale Rahn and Jason Wright}, + TITLE = {Experiences Enhancing Open Source Security in the POSSE Project}, + BOOKTITLE = {Free/Open Source Software Development}, + EDITOR = {Stefan Koch}, + PUBLISHER = {Idea Group Publishing}, + ADDRESS = {Hershey, PA}, + YEAR = {2004}, + PAGES = {242-257} +} + +@book{Celeste+06, +author = {R. Celeste and R. Thornburg and {H. Lin (editors)}}, +title = {Asking the Right Questions about Electronic Voting}, +publisher = {National Research Council, National Academies Press, + 500 Fifth Ave., Washington, D.C. 20001}, +month = {}, year = {2006} } + +@book{Rubin06, +Author={A. Rubin}, +Title={Brave New Ballot}, +Publisher={Random House}, +Year={2006} } + +@InProceedings{Adida+06, +Author = "B. Adida and C.A. Neff", +Title = "Ballot Casting Assurance", +Booktitle = "Workshop on Electronic Voting Technology Workshop", +Organization = "USENIX", Address = "Vancouver, BC, Canada", Year = "2006 ", +Pages="", Month = aug } + +@InProceedings{Benaloh06, +Author = "J. Benaloh", +Title = "Simple Verifiable Elections", +Booktitle = "Workshop on Electronic Voting Technology Workshop", +Organization = "USENIX", Address = "Vancouver, BC, Canada", Year = "2006 ", +Pages="", Month = aug } + +@InProceedings{Neff01, +Author = "C.A. Neff", +Title = "A Verifiable Secret Shuffle and Its Application to E-Voting", +Booktitle = "Proceedings of the ACM Conference on Computer and + Communications Security", +Organization = "", Address = "Philadelphia, Pennsylvania", Year = "2001 ", +Pages="116--125", Month = nov } + +@ARTICLE{Borg06, +Author={K. Borg}, TITLE = {Re: {LA} power outages}, +JOURNAL = {ACM Risks Forum}, YEAR = {2006}, VOLUME = {24}, NUMBER = {39}, +PAGES = {}, MONTH = {August}, day=22, +NOTE="http://catless.ncl.ac.uk/Risks/24.39.html\#subj8" } + +@Book{Springer-3938, +Editor={R.H. {Reussner et al.}}, +Title={Architecting Systems with Trustworthy Components, + International Seminar, Dagstuhl, Germany, + Lecture Notes in Computer Science vol. 3938}, +Publisher={Springer-Verlag}, Address={Berlin}, +Year={2004}, Month=dec, pages={}} + +@Book{Springer-4063, +Editor={I. {Gorton et al.}}, +Title={Component-Based Software Engineering, + 9th International Symposium, + Lecture Notes in Computer Science vol. 4063}, +Publisher={Springer-Verlag}, Address={Berlin}, +Year={2006}, Month={June/July}, pages={}} + +@Book{Springer-4089, +Editor={W. {L\"{o}we et al.}}, +Title={Software Composition, +5th International Workshop, +Lecture Notes in Computer Science vol. 4089}, +Publisher={Springer-Verlag}, Address={Berlin}, +Year={2006}, Month=mar, pages={}} + +@Book{Springer-4111, +Editor={F.S. {de Boer et al.}}, +Title={Formal Methods for Components and Objects, + 4th International Symposium, + Lecture Notes in Computer Science vol. 4111}, +Publisher={Springer-Verlag}, Address={Berlin}, +Year={2005}, Month=nov, pages={}} + +@TechReport{RushbyDeLong06, +Author="J.M. Rushby and R. DeLong", +Title="Toward an Integration Framework for High-Assurance Secure Components", +Institution="Computer Science Laboratory, SRI International, Menlo Park, +California", Year="2006", Month=dec} + +@string{dasc = { AIAA/IEEE Digital Avionics Systems Conference}} +@INPROCEEDINGS{Rushby-etal:DASC08, + AUTHOR = {Carolyn Boettcher and Rance DeLong + and John Rushby and Wilmar Sifre}, + TITLE = {The {MILS} Component Integration Approach + To Secure Information Sharing}, + BOOKTITLE = {27th} # dasc, + YEAR = 2008, + ORGANIZATION = {IEEE}, + ADDRESS = {St.\ Paul MN}, + MONTH = oct +} + + +@article{Zegans08, +author={L.S. Zegans}, +title = {The Psychology of Risks}, +journal = {Communications of the ACM}, year = {2008}, volume = {51}, +number = {1}, pages = {152}, month = jan, +Note= {{\it Inside Risks} column.} } + +@InProceedings{GPYF07, +Author={G. Gu and P. Porras and V. Yegneswaran and M. Fong and W. Lee}, +Title={BotHunter: Detecting Malware Infection through IDS-driven + Dialog Correlation}, +BookTitle={Proceedings of the 16th USENIX Security 2007}, +Organization={USENIX}, Address={Boston, Massachusetts}, +Year={2007}, Month=aug, pages={}} + +@InProceedings{CLF03, +Author={S. Cheung and U. Lindqvist and M.W. Fong}, +Title={Modeling Multistep Cyber Attacks for Scenario Recognition}, +BookTitle={Proceedings of the DARPA Information Survivability Conference + and Exposition}, +Organization={DARPA}, Address={Washington, DC}, +Year={2003}, Month={}, pages={}} + +@article{Porras09, +author={P. Porras}, +title = {Reflections on Conficker}, +journal = {Communications of the ACM}, year = {2009}, volume = {52}, +number = {10}, pages = {}, month = oct, +Note= {Inside Risks column, http://www.csl.sri.com/neumann/insiderisks.html\#219} } + +@conference{blaze1996decentralized, + title={{Decentralized trust management}}, + author={M. Blaze and J. Feigenbaum and J. Lacy}, + booktitle={IEEE Symposium on Security and Privacy}, + pages={164--173}, + year={1996}, + organization={IEEE Computer Society} +} + +@conference{chan2003random, + title={{Random key predistribution schemes for sensor networks}}, + author={H. Chan and A. Perrig and D. Song}, + booktitle={IEEE Symposium on Security and Privacy}, + pages={197--215}, + year={2003}, + organization={IEEE Computer Society} +} + +@conference{forrest1996sense, + title={{A sense of self for {Unix} processes}}, + author={S. Forrest and S.A. Hofmeyr and A. Somayaji and T.A. Longstaff + {et al.}}, + booktitle={IEEE Symposium on Security and Privacy}, + pages={120--128}, + year={1996}, + organization={IEEE Computer Society} +} + +@Proceedings{Schaefer1999, +Author = "Marv Schaefer and W.C. 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Watson and Brian Feldman and Adam Migus and Christopher Vance", + title = "{Design and Implementation of the {TrustedBSD MAC Framework}}", + booktitle = {{Proceedings of the Third DARPA Information Survivability Conference and + Exhibition (DISCEX), IEEE}}, + month = apr, + year = "2003" +} + +@inproceedings{lamport:sometimes, + author = {Lamport, Leslie}, + title = {``Sometime'' is sometimes ``not never'': on the temporal logic of programs}, + booktitle = {Proceedings of the 7th ACM SIGPLAN-SIGACT symposium on Principles of programming languages}, + series = {POPL '80}, + year = {1980}, + isbn = {0-89791-011-7}, + location = {Las Vegas, Nevada}, + pages = {174--185}, + numpages = {12}, + doi = {10.1145/567446.567463}, + acmid = {567463}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@article{clark:modelchecking, + author = {Clarke, Edmund M. and Emerson, E. Allen and Sifakis, Joseph}, + title = {Model checking: algorithmic verification and debugging}, + journal = {Communications of the ACM}, + issue_date = {November 2009}, + volume = {52}, + issue = {11}, + month = nov, + year = {2009}, + issn = {0001-0782}, + pages = {74--84}, + numpages = {11}, + doi = {10.1145/1592761.1592781}, + acmid = {1592781}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@article{holzmann:spin, + author = {Holzmann, Gerard J.}, + title = {The Model Checker {SPIN}}, + journal = {IEEE Transactions on Software Engineering}, + volume = {23}, + issue = {5}, + month = may, + year = {1997}, + issn = {0098-5589}, + pages = {279--295}, + numpages = {17}, + url = {http://portal.acm.org/citation.cfm?id=260897.260902}, + doi = {10.1109/32.588521}, + acmid = {260902}, + publisher = {IEEE Press}, + address = {Piscataway, NJ, USA}, + keywords = {Formal methods, program verification, design verification, model checking, distributed systems, concurrency.}, +} + +@MISC{eisner:truncatedpaths, + author = {Cindy Eisner and Dana Fisman and John Havlicek and Yoad Lustig and Anthony Mcisaac and David Van Campenhout}, + title = {Reasoning with Temporal Logic on Truncated Paths }, + year = {2003} +} + +@inproceedings{kwon:lowfat, + title = {Low-Fat Pointers: Compact Encoding and Efficient Gate-Level Implementation of Fat Pointers for Spatial Safety and Capability-based Security}, + author = {Albert Kwon and Udit Dhawan and Jonathan M. Smith and Thomas F. {Knight, Jr.} and André DeHon}, + year = 2013, + month = nov, + booktitle = {20th ACM Conference on Computer and Communications Security} +} + +@inproceedings{woodruff:cheriisca2014, + title = {The {{CHERI Capability Model}}: {{Revisiting RISC}} in an {{Age}} of {{Risk}}}, + shorttitle = {The {{CHERI Capability Model}}}, + booktitle = {Proceeding of the 41st {{Annual International Symposium}} on {{Computer Architecuture}}}, + author = {Woodruff, Jonathan and Watson, Robert N. M. and Chisnall, David and Moore, Simon W. and Anderson, Jonathan and Davis, Brooks and Laurie, Ben and Neumann, Peter G. and Norton, Robert and Roe, Michael}, + date = {2014-06}, + pages = {457--468}, + publisher = {{IEEE Press}}, + location = {{Piscataway, NJ, USA}}, + doi = {10.1109/ISCA.2014.6853201}, + url = {https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/201406-isca2014-cheri.pdf}, + series = {{{ISCA}} '14}, + venue = {Minneapolis, Minnesota, USA} +} + +@inproceedings{watson:cheriresolve2012, + title = {{CHERI: a research platform deconflating hardware virtualization and protection}}, + author = {Robert N. M. Watson and Peter G. Neumann Jonathan Woodruff and Jonathan Anderson and Ross Anderson and Nirav Dave and Ben Laurie and Simon W. Moore and Steven J. Murdoch and Philip Paeps and Michael Roe and Hassen Saidi}, + year = 2012, + month = mar, + booktitle = {{Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE 2012)}} +} + +@TechReport{UCAM-CL-TR-850, + author = {Watson, Robert N. M. and Neumann, Peter G. and Woodruff, + Jonathan and Anderson, Jonathan and Chisnall, David and + Davis, Brooks and Laurie, Ben and Moore, Simon W. and + Murdoch, Steven J. and Roe, Michael}, + title = {{Capability Hardware Enhanced RISC Instructions (CHERI): + Instruction-Set Architecture}}, + year = 2014, + month = jun, + institution = {University of Cambridge, Computer Laboratory}, + address = {15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom}, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-850.pdf}, + number = {UCAM-CL-TR-850} +} + +@TechReport{UCAM-CL-TR-851, + author = {Watson, Robert N. M. and Chisnall, David and Davis, Brooks + and Koszek, Wojciech and Moore, Simon W. and Murdoch, + Steven J. and Neumann, Peter G. and Woodruff, Jonathan}, + title = {{Capability Hardware Enhanced RISC Instructions (CHERI): + User's guide}}, + year = 2014, + month = jun, + institution = {University of Cambridge, Computer Laboratory}, + address = {15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom}, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-851.pdf}, + number = {UCAM-CL-TR-851} +} + +@TechReport{UCAM-CL-TR-852, + author = {Watson, Robert N. M. and Woodruff, Jonathan and Chisnall, + David and Davis, Brooks and Koszek, Wojciech and Markettos, A. Theodore and Moore, + Simon W. and Murdoch, Steven J. and Neumann, Peter G. and + Norton, Robert and Roe, Michael}, + title = {{Bluespec Extensible RISC Implementation (BERI): Hardware + Reference}}, + year = 2014, + month = jun, + institution = {University of Cambridge, Computer Laboratory}, + address = {15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom}, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-852.pdf}, + number = {UCAM-CL-TR-852} +} + +@TechReport{UCAM-CL-TR-853, + author = {Watson, Robert N. M. and Chisnall, David and Davis, Brooks + and Koszek, Wojciech and Moore, Simon W. and Murdoch, + Steven J. and Neumann, Peter G. and Woodruff, Jonathan}, + title = {{Bluespec Extensible RISC Implementation (BERI): Software + Reference}}, + year = 2014, + month = jun, + institution = {University of Cambridge, Computer Laboratory}, + address = {15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom}, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-853.pdf}, + number = {UCAM-CL-TR-853} +} + +@TechReport{UCAM-CL-TR-858, + author = {Woodruff, Jonathan D.}, + title = {{CHERI: A RISC capability machine for practical memory + safety}}, + year = 2014, + month = jul, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-858.pdf}, + institution = {University of Cambridge, Computer Laboratory}, + number = {UCAM-CL-TR-858} +} + +@TechReport{UCAM-CL-TR-864, + author = {Watson, Robert N. M. and Neumann, Peter G. and Woodruff, + Jonathan and Anderson, Jonathan and Chisnall, David and + Davis, Brooks and Laurie, Ben and Moore, Simon W. and + Murdoch, Steven J. and Roe, Michael}, + title = {{Capability Hardware Enhanced RISC Instructions: CHERI + Instruction-Set Architecture}}, + year = 2014, + month = dec, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-864.pdf}, + institution = {University of Cambridge, Computer Laboratory}, + number = {UCAM-CL-TR-864} +} + +@TechReport{UCAM-CL-TR-868, + author = {Watson, Robert N. M. and Woodruff, Jonathan and Chisnall, + David and Davis, Brooks and Koszek, Wojciech and Markettos, + A. Theodore and Moore, Simon W. and Murdoch, Steven J. and + Neumann, Peter G. and Norton, Robert and Roe, Michael}, + title = {{Bluespec Extensible RISC Implementation: BERI Hardware + reference}}, + year = 2015, + month = apr, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-868.pdf}, + institution = {University of Cambridge, Computer Laboratory}, + number = {UCAM-CL-TR-868} +} + +@TechReport{UCAM-CL-TR-869, + author = {Watson, Robert N. M. and Chisnall, David and Davis, Brooks + and Koszek, Wojciech and Moore, Simon W. and Murdoch, + Steven J. and Neumann, Peter G. and Woodruff, Jonathan}, + title = {{Bluespec Extensible RISC Implementation: BERI Software + reference}}, + year = 2015, + month = apr, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-869.pdf}, + institution = {University of Cambridge, Computer Laboratory}, + number = {UCAM-CL-TR-869} +} + +@TechReport{UCAM-CL-TR-873, + author = {Gudka, Khilan and Watson, Robert N.M. and Anderson, + Jonathan and Chisnall, David and Davis, Brooks and Laurie, + Ben and Marinos, Ilias and Murdoch, Steven J. and Neumann, + Peter G. and Richardson, Alex}, + title = {{Clean application compartmentalization with SOAAP + (extended version)}}, + year = 2015, + month = dec, + institution = {University of Cambridge, Computer Laboratory}, + address = {15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom}, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-873.pdf}, + number = {UCAM-CL-TR-873} +} + +@TechReport{UCAM-CL-TR-876, + author = {Watson, Robert N. M. and Neumann, Peter G. and Woodruff, + Jonathan and Roe, Michael and Anderson, Jonathan and + Chisnall, David and Davis, Brooks and Joannou, Alexandre and + Laurie, Ben and Moore, Simon W. and Murdoch, Steven J. and + Norton, Robert and Son, Stacey}, + title = {{Capability Hardware Enhanced RISC Instructions: CHERI + Instruction-Set Architecture}}, + year = 2015, + month = nov, + institution = {University of Cambridge, Computer Laboratory}, + address = {15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom}, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-876.pdf}, + number = {UCAM-CL-TR-876} +} + +@TechReport{UCAM-CL-TR-877, + author = {Watson, Robert N. M. and Chisnall, David and Davis, Brooks + and Koszek, Wojciech and Moore, Simon W. and Murdoch, + Steven J. and Neumann, Peter G. and Woodruff, Jonathan}, + title = {{Capability Hardware Enhanced RISC Instructions: CHERI + Programmer's Guide}}, + year = 2015, + month = nov, + institution = {University of Cambridge, Computer Laboratory}, + address = {15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom}, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-877.pdf}, + number = {UCAM-CL-TR-877} +} + +@TechReport{UCAM-CL-TR-927, + author = {Watson, Robert N. M. and Neumann, Peter G. and Woodruff, + Jonathan and Roe, Michael and Almatary, Hesham and + Anderson, Jonathan and Baldwin, John and Chisnall, David + and Davis, Brooks and Filardo, Nathaniel Wesley and + Joannou, Alexandre and Laurie, Ben and Moore, Simon W. and + Murdoch, Steven J. and Nienhuis, Kyndylan and Norton, + Robert and Richardson, Alex and Sewell, Peter and Son, + Stacey and Xia, Hongyan}, + title = {{Capability Hardware Enhanced RISC Instructions: CHERI + Instruction-Set Architecture (Version 7)}}, + year = 2018, + month = oct, + institution = {University of Cambridge, Computer Laboratory}, + address = {15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom, + phone +44 1223 763500}, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-927.pdf}, + number = {UCAM-CL-TR-927} +} + +@inproceedings{Necula:2002:CTR:503272.503286, + author = {Necula, George C. and McPeak, Scott and Weimer, Westley}, + title = {CCured: Type-safe Retrofitting of Legacy Code}, + booktitle = {Proceedings of the 29th ACM SIGPLAN-SIGACT Symposium on +Principles of Programming Languages}, + series = {POPL '02}, + year = {2002}, + isbn = {1-58113-450-9}, + location = {Portland, Oregon}, + pages = {128--139}, + numpages = {12}, + doi = {10.1145/503272.503286}, + acmid = {503286}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@inproceedings{Nagarakatte:2009:SHC:1542476.1542504, + author = {Nagarakatte, Santosh and Zhao, Jianzhou and Martin, Milo M.K. and Zdancewic, Steve}, + title = {SoftBound: Highly Compatible and Complete Spatial Memory Safety for {C}}, + booktitle = {Proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation}, + series = {PLDI '09}, + year = {2009}, + isbn = {978-1-60558-392-1}, + location = {Dublin, Ireland}, + pages = {245--258}, + numpages = {14}, + doi = {10.1145/1542476.1542504}, + acmid = {1542504}, + publisher = {ACM}, + address = {New York, NY, USA}, + keywords = {buffer overflows, c, spatial memory safety}, +} + +@article{Devietti:2008:HAS:1353536.1346295, + author = {Devietti, Joe and Blundell, Colin and Martin, Milo M. K. and Zdancewic, Steve}, + title = {Hardbound: Architectural Support for Spatial Safety of the {C} Programming Language}, + journal = {SIGPLAN Not.}, + issue_date = {March 2008}, + volume = {43}, + number = {3}, + month = mar, + year = {2008}, + issn = {0362-1340}, + pages = {103--114}, + numpages = {12}, + doi = {10.1145/1353536.1346295}, + acmid = {1346295}, + publisher = {ACM}, + address = {New York, NY, USA}, + keywords = {C programming language, spatial memory safety}, +} + +@MANUAL{Bluespec:TFRG, + TITLE = "Bluespec SystemVerilog Version~3.8 Reference Guide", + ORGANIZATION = "Bluespec,~Inc.", + ADDRESS = {Waltham,~MA}, + MONTH = nov, + YEAR = {2004} +} + +@article{watson13, + author = {Watson, Robert N. M.}, + title = {A Decade of {{OS}} Access-Control Extensibility}, + date = {2013-02-01}, + journaltitle = {Communications of the ACM}, + shortjournal = {Commun. ACM}, + volume = {56}, + pages = {52--63}, + issn = {0001-0782}, + doi = {10.1145/2408776.2408792}, + number = {2} +} + +@inproceedings{ChisnallCPDP11, +author = {David Chisnall and Colin Rothwell and Brooks Davis and Robert N. M. Watson and Jonathan Woodruff and Simon W. Moore and Peter G. Neumann and Michael Roe}, +title = {Beyond the {PDP}-11: Architectural support for a memory-safe C abstract machine}, +booktitle = {Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems}, +series = {ASPLOS '15}, +year = {2015}, +location = {Istanbul, Turkey}, +numpages = {14}, +publisher = {ACM}, +address = {New York, NY, USA}, +keywords = {C, memory safety, memory models, code generation}, +} + +@inproceedings{watson15:cheri, + title = {{{CHERI}}: {{A Hybrid Capability}}-{{System Architecture}} for {{Scalable Software Compartmentalization}}}, + shorttitle = {{{CHERI}}}, + booktitle = {Proceedings of the 2015 {{IEEE Symposium}} on {{Security}} and {{Privacy}}}, + author = {Watson, Robert N. M. and Woodruff, Jonathan and Neumann, Peter G. and Moore, Simon W. and Anderson, Jonathan and Chisnall, David and Dave, Nirav and Davis, Brooks and Gudka, Khilan and Laurie, Ben and Murdoch, Steven J. and Norton, Robert and Roe, Michael and Son, Stacey and Vadera, Munraj}, + date = {2015-05}, + pages = {20--37}, + publisher = {{IEEE Computer Society}}, + location = {{Washington, DC, USA}}, + doi = {10.1109/SP.2015.9}, + url = {https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/201505-oakland2015-cheri-compartmentalization.pdf}, + eventtitle = {2015 {{IEEE Symposium}} on {{Security}} and {{Privacy}} ({{SP}})}, + isbn = {978-1-4673-6949-7}, + series = {{{SP}} '15} +} + +@inproceedings{gudka15:soaap, + author = {Khilan Gudka and Robert N. M. Watson and Jonathan Anderson and David Chisnall and Brooks Davis and Ben Laurie and Ilias Marinos and Peter G. Neumann and Alex Richardson}, + title = {{Clean Application Compartmentalization with SOAAP}}, + booktitle = {{Proceedings of the 22nd ACM Conference on Computer and Communications Security (CCS 2015)}}, + month = oct, + year = {2015}, +} + +@inproceedings{Keromytis2003, + author = {Gaurav S. Kc and Angelos D. Keromytis and Vassilis Prevelakis}, + title = {Countering Code-Injection Attacks With Instruction-Set + Randomization}, + booktitle = {Proceedings of the Tenth ACM Conference on Computer and +Communications Security (CCS)}, + month = oct, + year = 2003 +} + +@inproceedings{dhawan2014pump, + title={PUMP: a programmable unit for metadata processing}, + author={Dhawan, Udit and Vasilakis, Nikos and Rubin, Raphael and Chiricescu, Silviu and Smith, Jonathan M and Knight Jr, Thomas F and Pierce, Benjamin C and DeHon, Andr{\'e}}, + booktitle={Proceedings of the Third Workshop on Hardware and Architectural Support for Security and Privacy}, + pages={8}, + year={2014}, + organization={ACM} +} + +@phdthesis{gonzalez2015taxi, + title={Taxi: Defeating Code Reuse Attacks with Tagged Memory}, + author={Gonz{\'a}lez, Juli{\'a}n Armando}, + year={2015}, + school={Massachusetts Institute of Technology} +} + +@inproceedings{abadi2005control, + title={{Control-Flow Integrity}}, + author={Abadi, Mart{\'\i}n and Budiu, Mihai and Erlingsson, Ulfar and Ligatti, Jay}, + booktitle={Proceedings of the 12th ACM conference on Computer and communications security}, + pages={340--353}, + year={2005}, + organization={ACM} +} + +@article{mashtizadeh2014cryptographically, + title={Cryptographically enforced control flow integrity}, + author={Mashtizadeh, Ali Jose and Bittau, Andrea and Mazieres, David and Boneh, Dan}, + journal={arXiv preprint arXiv:1408.1451}, + year={2014} +} + +@inproceedings{Mashtizadeh_CCFICryptographicallyEnforced_2015, + title = {{{CCFI}}: {{Cryptographically Enforced Control Flow Integrity}}}, + shorttitle = {{{CCFI}}}, + booktitle = {Proceedings of the 22nd {{ACM SIGSAC Conference}} on {{Computer}} and {{Communications Security}}}, + author = {Mashtizadeh, Ali Jose and Bittau, Andrea and Boneh, Dan and Mazi\`eres, David}, + date = {2015-10-12}, + pages = {941--951}, + publisher = {{Association for Computing Machinery}}, + location = {{New York, NY, USA}}, + doi = {10.1145/2810103.2813676}, + urldate = {2020-09-30}, + abstract = {Control flow integrity (CFI) restricts jumps and branches within a program to prevent attackers from executing arbitrary code in vulnerable programs. However, traditional CFI still offers attackers too much freedom to chose between valid jump targets, as seen in recent attacks. We present a new approach to CFI based on cryptographic message authentication codes (MACs). Our approach, called cryptographic CFI (CCFI), uses MACs to protect control flow elements such as return addresses, function pointers, and vtable pointers. Through dynamic checks, CCFI enables much finer-grained classification of sensitive pointers than previous approaches, thwarting all known attacks and resisting even attackers with arbitrary access to program memory. We implemented CCFI in Clang/LLVM, taking advantage of recently available cryptographic CPU instructions (AES-NI). We evaluate our system on several large software packages (including nginx, Apache and memcache) as well as all their dependencies. The cost of protection ranges from a 3--18\% decrease in server request rate. We also expect this overhead to shrink as Intel improves the performance AES-NI.}, + isbn = {978-1-4503-3832-5}, + keywords = {control flow integrity,return oriented programming,vulnerabilities}, + series = {{{CCS}} '15} +} + +@inproceedings{evans2015control, + title={Control jujutsu: On the weaknesses of fine-grained control flow integrity}, + author={Evans, Isaac and Long, Fan and Otgonbaatar, Ulziibayar and Shrobe, Howard and Rinard, Martin and Okhravi, Hamed and Sidiroglou-Douskos, Stelios}, + booktitle={ACM SIGSAC Conference on Computer and Communications Security, CCS}, + year={2015} +} + +@inproceedings{conti2015losing, + title={Losing Control: On the Effectiveness of Control-Flow Integrity under Stack Attacks}, + author={Conti, Mauro and Crane, Stephen and Davi, Lucas and Franz, Michael and Larsen, Per and Liebchen, Christopher and Negro, Marco and Qunaibit, Mohaned and Sadeghi, Ahmad-Reza}, + booktitle={Proceedings of the 22nd ACM SIGSAC Conference on Computer and Communications Security}, + pages={952--963}, + year={2015}, + organization={ACM} +} + +@inproceedings{kuznetsov2014code, + title={Code-pointer integrity}, + author={Kuznetsov, Volodymyr and Szekeres, L{\'a}szl{\'o} and Payer, Mathias and Candea, George and Sekar, R and Song, Dawn}, + booktitle={USENIX Symposium on Operating Systems Design and Implementation (OSDI)}, + year={2014} +} + +@TECHREPORT{Bletsch10jump-orientedprogramming:, + author = {Tyler Bletsch and Xuxian Jiang and Vince W. Freeh and Zhenkai Liang}, + title = {Jump-Oriented Programming: A New Class of Code-Reuse Attack}, + institution = {NC State University}, + year = {2010} +} + +@article{Hardy1988, +author = "Norman Hardy", +title = "The Confused Deputy (or why capabilities might have been invented)", +journal = "{ACM SIGOPS} Operating Systems Review", +volume = 22, +number = 4, +month = oct, +year = 1988} + +@TechReport{UCAM-CL-TR-887, + author = {Norton, Robert M.}, + title = {{Hardware support for compartmentalisation}}, + year = 2016, + month = may, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-887.pdf}, + institution = {University of Cambridge, Computer Laboratory}, + number = {UCAM-CL-TR-887} +} + +@TechReport{UCAM-CL-TR-891, + author = {Watson, Robert N. M. and Neumann, Peter G. and Woodruff, + Jonathan and Roe, Michael and Anderson, Jonathan and + Chisnall, David and Davis, Brooks and Joannou, Alexandre + and Laurie, Ben and Moore, Simon W. and Murdoch, Steven J. + and Norton, Robert and Son, Stacey and Xia, Hongyan}, + title = {{Capability Hardware Enhanced RISC Instructions: CHERI + Instruction-Set Architecture (Version 5)}}, + year = 2016, + month = jun, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-891.pdf}, + institution = {University of Cambridge, Computer Laboratory}, + number = {UCAM-CL-TR-891} +} + +@manual{SKPP, +title = "U.S. Government Protection Profile for Separation Kernels in +Environments Requiring High Robustness", +key = "National Security Agency", +organization = "National Security Agency Information Assurance Directorate", +month = jun, +year = 2007} + +@manual{CC2017-1, +title = {Common Criteria for Information Technology Security Evaluation -- + Part 1: Introduction and General Model}, +author="{International Standards Organization}", +key = "International", +note = "Version 3.1, revision 5", +month = apr, +year = 2017} + +@manual{CC2012-3, +title = "Common Criteria for Information Technology Security Evaluation -- + Part 3: Security assurance components", +author="{International Standards Organization}", +key = "International", +note = "Version 3.1, revision 4.", +month = sep, +year = 2012} + +@InProceedings{Cerberus-PLDI16, + author = { +Kayvan Memarian and +Justus Matthiesen and +James Lingard and +Kyndylan Nienhuis and +David Chisnall and +Robert N.M. Watson and +Peter Sewell +}, + title = {Into the depths of {C}: elaborating the de facto standards}, + booktitle = {{Proceedings of PLDI 2016}}, + year = {2016}, + month = jun, + publisher = {ACM}, +} + +@Inbook{Fox2015, +author="Fox, Anthony", +editor="Urban, Christian +and Zhang, Xingyuan", +title="Improved Tool Support for Machine-Code Decompilation in HOL4", +bookTitle="Interactive Theorem Proving: 6th International Conference, ITP 2015, Nanjing, China, August 24-27, 2015, Proceedings", +year="2015", +publisher="Springer International Publishing", +address="Cham", +pages="187--202", +isbn="978-3-319-22102-1", +} + +@article{Gligor1979, +author = "Virgil Gligor and Bruce G. Lindsay", +title = "Object Migration and Authentication", +journal = "{IEEE} Transactions on Software Engineering", +volume = "SE-5", +number = 6, +month = nov, +year = 1979} + +@book{Heinrich:1993:MRU:154056, + author = {Heinrich, Joseph}, + title = {MIPS R4000 User's Manual}, + year = {1993}, + isbn = {0-13-105925-4}, + publisher = {Prentice-Hall, Inc.}, + address = {Upper Saddle River, NJ, USA}, +} + +@ARTICLE{watson2016:microjournal, +author={R. N. M. Watson and R. M. Norton and J. Woodruff and S. W. Moore and P. G. Neumann and J. Anderson and D. Chisnall and B. Davis and B. Laurie and M. Roe and N. H. Dave and K. Gudka and A. Joannou and A. T. Markettos and E. Maste and S. J. Murdoch and C. Rothwell and S. D. Son and M. Vadera}, +journal={IEEE Micro}, +title={{Fast Protection-Domain Crossing in the CHERI Capability-System Architecture}}, +year={2016}, +volume={36}, +number={5}, +pages={38-49}, +keywords={reduced instruction set computing;storage management chips;CHERI capability system architecture;ISA;MMU;capability hardware enhanced RISC instructions;conventional memory management unit;fast protection domain;flow-control model;hardware-software object-capability model;instruction set architecture;memory sharing;software defined protection domain transition model;Capability engineering;Memory management;Program processors;Reduced instruction set computing;Systems modeling;CHERI;ISA;capabilities;capability;capability system;compartmentalization;hardware;instruction set architecture;memory management unit;memory protection;processor;security;software;vulnerability mitigation}, +doi={10.1109/MM.2016.84}, +ISSN={0272-1732}, +month=sep,} + +@inproceedings{chisnall2017:cherijni, + title = {{{CHERI JNI}}: {{Sinking}} the {{Java Security Model}} into the {{C}}}, + shorttitle = {{{CHERI JNI}}}, + booktitle = {Proceedings of the {{Twenty}}-{{Second International Conference}} on {{Architectural Support}} for {{Programming Languages}} and {{Operating Systems}}}, + author = {Chisnall, David and Davis, Brooks and Gudka, Khilan and Brazdil, David and Joannou, Alexandre and Woodruff, Jonathan and Markettos, A. Theodore and Maste, J. Edward and Norton, Robert and Son, Stacey and Roe, Michael and Moore, Simon W. and Neumann, Peter G. and Laurie, Ben and Watson, Robert N.M.}, + date = {2017-04}, + pages = {569--583}, + publisher = {{ACM}}, + location = {{New York, NY, USA}}, + doi = {10.1145/3037697.3037725}, + url = {https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/201704-asplos-cherijni.pdf}, + isbn = {978-1-4503-4465-4}, + keywords = {architecture,capability systems,cheri,compartmentalization,compilers,hardware security,java,jni,language security,memory protection,sandboxing}, + series = {{{ASPLOS}} '17}, + venue = {Xi'an, China} +} + + +@TechReport{UCAM-CL-TR-907, + author = {Watson, Robert N. M. and Neumann, Peter G. and Woodruff, + Jonathan and Roe, Michael and Anderson, Jonathan and + Baldwin, John and Chisnall, David and Davis, Brooks and + Joannou, Alexandre and Laurie, Ben and Moore, Simon W. and + Murdoch, Steven J. and Norton, Robert and Son, Stacey and + Xia, Hongyan}, + title = {{Capability Hardware Enhanced RISC Instructions: CHERI + Instruction-Set Architecture (Version 6)}}, + year = 2017, + month = apr, + institution = {University of Cambridge, Computer Laboratory}, + address = {15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom, + phone +44 1223 763500}, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-907.pdf}, + number = {UCAM-CL-TR-907} +} + +@TechReport{UCAM-CL-TR-916, + author = {Watson, Robert N. M. and Woodruff, Jonathan and Roe, + Michael and Moore, Simon W. and Neumann, Peter G.}, + title = {{Capability Hardware Enhanced RISC Instructions (CHERI): + Notes on the Meltdown and Spectre Attacks}}, + year = 2018, + month = feb, + url = {http://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-916.pdf}, + institution = {University of Cambridge, Computer Laboratory}, + number = {UCAM-CL-TR-916} +} + +@thesis{WatermanThesis2016, + author = {Waterman, Andrew}, + title = {{Design of the RISC-V Instruction Set Architecture}}, + institution = {EECS Department, University of California, Berkeley}, + year = {2016}, + url = {http://digitalassets.lib.berkeley.edu/etd/ucb/text/Waterman_berkeley_0028E_15908.pdf} +} + +@techreport{Waterman:EECS-2016-118, + Author = {Waterman, Andrew and Lee, Yunsup and Patterson, David A. and Asanovi\'c, Krste}, + Title = {{The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.1}}, + Institution = {EECS Department, University of California, Berkeley}, + Year = {2016}, + Month = may, + URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-118.html}, + Number = {UCB/EECS-2016-118} +} + +@techreport{Waterman:EECS-2016-161, + Author = {Waterman, Andrew and Lee, Yunsup and Avizienis, Rimas and Patterson, David A. and Asanovi\'c, Krste}, + Title = {{The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.9.1}}, + Institution = {EECS Department, University of California, Berkeley}, + Year = {2016}, + Month = nov, + URL = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-161.html}, + Number = {UCB/EECS-2016-161} +} + +@Book{RISCV:User:2.2, + Editor = {Waterman, Andrew and Asanovi\'c, Krste}, + Title = {{The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.2}}, + Institution = {RISC-V Foundation}, + Year = {2017}, + Month = may, + URL = {https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf} +} + +@Book{RISCV:Privileged:1.10, + Editor = {Waterman, Andrew and Asanovi\'c, Krste}, + Title = {{The RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10}}, + Institution = {RISC-V Foundation}, + Year = {2017}, + Month = may, + URL = {https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf} +} + +@incollection{watson2017:cheri-deployability, + author = {Robert N. M. Watson and Peter G Neumann and Simon W. Moore}, + title = {{Balancing Disruption and Deployability in the CHERI Instruction-Set Architecture (ISA)}}, + editor = {H. Shrobe and D. L. Shrier and A. Pentland}, + booktitle = {New Solutions for Cybersecurity}, + publisher = {MIT Press/Connection Science}, + city = {Cambridge}, + state = {MA}, + year = {2018}, + chapter = {5} +} + +@incollection{neumann2017:cheri-principles, + author = {Peter G. Neumann}, + title = {{Fundamental Trustworthiness Principles in CHERI}}, + editor = {H. Shrobe and D. L. Shrier and A. Pentland}, + booktitle = {New Solutions for Cybersecurity}, + publisher = {MIT Press/Connection Science}, + city = {Cambridge}, + state = {MA}, + year = {2018}, + chapter = {6} +} + +@article{Lipp2018meltdown, + author = {Lipp, Moritz and Schwarz, Michael and Gruss, Daniel and Prescher, + Thomas and Haas, Werner and Mangard, Stefan and Kocher, Paul and Genkin, + Daniel and Yarom, Yuval and Hamburg, Mike}, + title = {Meltdown}, + journal = {ArXiv e-prints}, + archivePrefix = "arXiv", + eprint = {1801.01207}, + year = 2018, + month = jan, +} + +@inproceedings{Foreshadow, + title = {Foreshadow: {{Extracting}} the {{Keys}} to the {{Intel}} \{\vphantom\}{{SGX}}\vphantom\{\} {{Kingdom}} with {{Transient Out}}-of-{{Order Execution}}}, + shorttitle = {Foreshadow}, + author = {Bulck, Jo Van and Minkin, Marina and Weisse, Ofir and Genkin, Daniel and Kasikci, Baris and Piessens, Frank and Silberstein, Mark and Wenisch, Thomas F. and Yarom, Yuval and Strackx, Raoul}, + date = {2018-08}, + pages = {991--1008}, + publisher = {{USENIX Association}}, + location = {{Baltimore, MD}}, + url = {https://www.usenix.org/conference/usenixsecurity18/presentation/bulck}, + urldate = {2020-09-29}, + annotation = {http://foreshadowattack.eu/foreshadowattack.pdf}, + eventtitle = {27th {{USENIX Security Symposium}}}, + isbn = {978-1-939133-04-5}, + NOTE = {\url{http://foreshadowattack.eu/foreshadowattack.pdf}}, + series = {{{USENIX Security}} 18} +} + +@article{Foreshadow-NG, +title={Foreshadow: Breaking the Virtual Memory + Abstraction with Transient Out-of-Order Execution}, +author={Ofir Weisse and Jo {Van Bulck} and Marina Minkin and Daniel Genkin and + Boris Kasikci and Frank Piessens and Mark Silberstein and Raoul Strackx and + Thomas F. Wenisch and Yucal Yarom}, +journal={}, +year={2018}, +volume = {}, +number = {}, +day={14}, +month=aug, +publisher = {}, +NOTE = {\url{http://foreshadowattack.eu/foreshadow-NG.pdf}} +} + + +@article{Kocher2018spectre, + author = {Kocher, Paul and Genkin, Daniel and Gruss, Daniel and Haas, Werner + and Hamburg, Mike and Lipp, Moritz and Mangard, Stefan and Prescher, Thomas + and Schwarz, Michael and Yarom, Yuval}, + title = {Spectre Attacks: Exploiting Speculative Execution}, + journal = {ArXiv e-prints}, + archivePrefix = "arXiv", + eprint = {1801.01203}, + year = 2018, + month = jan, +} + +@article{N32handbook, + author = {George, Pirocanac and Susan, Wilkening and Jean, Wilson and Glen, Traefald}, + title = {{MIPSpro\textsuperscript{TM} N32 ABI Handbook}}, + publisher = {Silicon Graphics, SGI}, + year = 2002, +} + +@inproceedings{Creech69, + author={B. A. Creech}, + title={Architecture of the B-6500}, + pages={29-43}, + booktitle={Software Engineering: Proceedings of the Third Symposium on Computer and Information Sciences}, + month=dec, + year={1970}, + volume={1}, + editor={Tou, Julius T.}, + isbn={9780323157445}, +} + +@article{Organick73, + author={Elliott I. Organick}, + title={Computer System Organization}, + isbn={978-0125282505}, + publisher={Academic Press, Inc.}, + month=may, + year={1973}, + url={http://bitsavers.org/pdf/burroughs/B5000_5500_5700/Organick_Computer_System_Organization_The_B5700_B6700_Series_1973.pdf}, +} + +@article{Mayer82, + author = {Mayer, Alastair J. W.}, + title = {The Architecture of the {{Burroughs B5000}}: 20 Years Later and Still Ahead of the Times?}, + shorttitle = {The Architecture of the {{Burroughs B5000}}}, + journaltitle = {ACM SIGARCH Computer Architecture News}, + shortjournal = {SIGARCH Comput. Archit. News}, + issue_date = {June 1982}, + volume = {10}, + number = {4}, + month = jun, + year = {1982}, + issn = {0163-5964}, + pages = {3--10}, + numpages = {8}, + doi = {10.1145/641542.641543}, + acmid = {641543}, + publisher = {ACM}, + address = {New York, NY, USA}, +} + +@article{Barton87, + author={R. S. Barton and H. Berce and G. A. Collins and B. A. Creech and D. M. Dahm and B. A. Dent and V. J. Ford and B. A. Galler and J. E. S. Hale and E. A. Hauck and J. T. Hootman and P. D. King and N. L. Kreuder and W. R. Lonergan and D. MacDonald and F. B. MacKenzie and C. Oliphint and R. Pearson and R. F. Rosin and L. D. Turner and R. Waychoff}, + journal={Annals of the History of Computing}, + title={Discussion: The Burroughs B 5000 in Retrospect}, + year={1987}, + volume={9}, + number={1}, + pages={37-92}, + keywords={Computers;Hardware}, + doi={10.1109/MAHC.1987.10006}, + ISSN={0164-1239}, + month=jan, +} + +@report{Burroughs-B6700, + author={Burroughs Corporation}, + title={B 6700 Information Processing System Reference Manual}, + year={1972}, + url={http://bitsavers.trailing-edge.com/pdf/burroughs/B6500_6700/1058633_B6700_RefMan_May72.pdf} +} + +@phdthesis{Gumpertz81, + title={Error Detection with Memory Tags}, + author={Richard H. Gumpertz}, + month=dec, + year={1981}, + institution={Carnegie Mellon University}, + url={http://reports-archive.adm.cs.cmu.edu/anon/scan/CMU-CS-84-122.pdf} +} + +@inproceedings{joannou2017:tagged-memory, + author={Alexandre Joannou and Jonathan Woodruff and Robert Kovacsics and Simon W. Moore and Alex Bradbury and Hongyan Xia and Robert N. M. Watson and David Chisnall and Michael Roe and Brooks Davis and Edward Napierala and John Baldwin and Khilan Gudka and Peter G. Neumann and Alfredo Mazzinghi and Alex Richardson and Stacey Son and A. Theodore Markettos}, + title = {Efficient Tagged Memory}, + booktitle = {{Proceedings of the 2017 IEEE 35th International Conference on Computer Design (ICCD)}}, + month = nov, + year = {2017}, + city = {Boston}, + state = {MA}, + country = {USA}, +} + +@INPROCEEDINGS{Popek79, +author = {G. J. Popek and M. Kampe and M. Urban and A. Stoughton and E. J. Walton and C. S. Kline}, +booktitle = {International Workshop on Managing Requirements Knowledge (AFIPS)}, +title = {UCLA Secure UNIX}, +year = {1979}, +pages = {355}, +doi = {10.1109/AFIPS.1979.128}, +month={6} +} + +@phdthesis{doerrie2015:confinement, + author={M. Scott Doerrie}, + title={Confidence in Confinement: An Axiom-free, Mechanized Verification +of Confinement in Capability-based Systems}, + year={2015}, + institution={Johns Hopkins University}, + url={http://www.doerrie.us/assets/doerrie-dissertation-jhu.pdf} +} + +@article{Skorstengaard:2019:stktokens, + title = {{{StkTokens}}: Enforcing Well-Bracketed Control Flow and Stack Encapsulation Using Linear Capabilities}, + shorttitle = {{{StkTokens}}}, + author = {Skorstengaard, Lau and Devriese, Dominique and Birkedal, Lars}, + date = {2019-01}, + journaltitle = {Proceedings of the ACM on Programming Languages}, + shortjournal = {Proc. ACM Program. Lang.}, + volume = {3}, + pages = {19:1--19:28}, + doi = {10.1145/3290332}, + urldate = {2020-09-15}, + issue = {POPL}, + keywords = {capability machines,fully abstract compilation,fully abstract overlay semantics,linear capabilities,secure compilation,stack frame encapsulation,well-bracketed control flow} +} + +@inproceedings{chiricescu2013safe, + title={SAFE: A clean-slate architecture for secure systems}, + author={Chiricescu, Silviu and DeHon, Andr{\'e} and Demange, Delphine and Iyer, Suraj and Kliger, Aleksey and Morrisett, Greg and Pierce, Benjamin C and Reubenstein, Howard and Smith, Jonathan M and Sullivan, Gregory T and others}, + booktitle={IEEE International Conference on Technologies for Homeland Security (HST)}, + pages={570--576}, + year={2013} +} + +@INPROCEEDINGS{shapiro:2004, + author = {Jonathan Shapiro and Michael Scott Doerrie and Eric Northup and Mark Miller}, + title = {Towards a verified, general-purpose operating system kernel}, + booktitle = {Proceedings of the NICTA Invitational Workshop on Operating System Verification}, + year = {2004}, + pages = {1--19}, + url={http://www.cs.jhu.edu/~swaroop/osverify-2004.pdf} +} + +@inproceedings{carter:mmachine94, + title = {Hardware {{Support}} for {{Fast Capability}}-Based {{Addressing}}}, + booktitle = {Proceedings of the {{Sixth International Conference}} on {{Architectural Support}} for {{Programming Languages}} and {{Operating Systems}}}, + author = {Carter, Nicholas P. and Keckler, Stephen W. and Dally, William J.}, + date = {1994-11}, + pages = {319--327}, + publisher = {{ACM}}, + location = {{New York, NY, USA}}, + doi = {10.1145/195473.195579}, + url = {https://www.cs.utexas.edu/users/skeckler/pubs/asplos94.pdf}, + abstract = {Traditional methods of providing protection in memory systems do so at the cost of increased context switch time and/or increased storage to record access permissions for processes. With the advent of computers that supported cycle-by-cycle multithreading, protection schemes that increase the time to perform a context switch are unacceptable, but protecting unrelated processes from each other is still necessary if such machines are to be used in non-trusting environments. This paper examines guarded pointers, a hardware technique which uses tagged 64-bit pointer objects to implement capability-based addressing. Guarded pointers encode a segment descriptor into the upper bits of every pointer, eliminating the indirection and related performance penalties associated with traditional implementations of capabilities. All processes share a single 54-bit virtual address space, and access is limited to the data that can be referenced through the pointers that a process has been issued. Only one level of address translation is required to perform a memory reference. Sharing data between processes is efficient, and protection states are defined to allow fast protected subsystem calls and create unforgeable data keys.}, + isbn = {978-0-89791-660-8}, + series = {{{ASPLOS VI}}}, + venue = {San Jose, California, USA} +} + +@inproceedings{Fillo_MMachineMulticomputer_1995, + title = {The {{M}}-{{Machine}} Multicomputer}, + booktitle = {Proceedings of the 28th Annual International Symposium on {{Microarchitecture}}}, + author = {Fillo, Marco and Keckler, Stephen W. and Dally, William J. and Carter, Nicholas P. and Chang, Andrew and Gurevich, Yevgeny and Lee, Whay S.}, + date = {1995-12-01}, + pages = {146--156}, + publisher = {{IEEE Computer Society Press}}, + location = {{Washington, DC, USA}}, + doi = {10.1109/MICRO.1995.476822}, + abstract = {The M-Machine is an experimental multicomputer being developed to test architectural concepts motivated by the constraints of modern semiconductor technology and the demands of programming systems. The M-Machine computing nodes are connected with a 3-D mesh network; each node is a multithreaded processor incorporating 12 function units, on-chip cache, and local memory. The multiple function units are used to exploit both instruction-level and thread-level parallelism. A user accessible message passing system yields fast communication and synchronization between nodes. Rapid access to remote memory is provided transparently to the user with a combination of hardware and software mechanisms. This paper presents the architecture of the M-Machine and describes how its mechanisms attempt to maximize both single thread performance and overall system throughput. The architecture is complete and the MAP chip, which will serve as the M-Machine processing node, is currently being implemented.}, + isbn = {978-0-8186-7349-8}, + keywords = {3-D mesh network,architectural concepts testing,computer architecture,Computer architecture,Computer networks,Hardware,hardware mechanisms,instruction-level,local memory,M-Machine multicomputer,Mesh networks,message passing,Message passing,multiprocessing systems,multithreaded processor,Network-on-a-chip,on-chip cache,overall system throughput,Parallel processing,programming systems,Semiconductor device testing,single thread performance,software mechanisms,synchronisation,System testing,thread-level parallelism,user accessible message passing system,Yarn}, + series = {{{MICRO}} 28} +} + +@inproceedings{Davis_CheriABIEnforcingValid_2019, + ids = {davis2019:cheriabi}, + title = {{{CheriABI}}: {{Enforcing Valid Pointer Provenance}} and {{Minimizing Pointer Privilege}} in the {{POSIX C Run}}-Time {{Environment}}}, + shorttitle = {{{CheriABI}}}, + booktitle = {Proceedings of the {{Twenty}}-{{Fourth International Conference}} on {{Architectural Support}} for {{Programming Languages}} and {{Operating Systems}}}, + author = {Davis, Brooks and Watson, Robert N. M. and Richardson, Alexander and Neumann, Peter G. and Moore, Simon W. and Baldwin, John and Chisnall, David and Clarke, Jessica and Filardo, Nathaniel Wesley and Gudka, Khilan and Joannou, Alexandre and Laurie, Ben and Markettos, A. Theodore and Maste, J. Edward and Mazzinghi, Alfredo and Napierala, Edward Tomasz and Norton, Robert M. and Roe, Michael and Sewell, Peter and Son, Stacey and Woodruff, Jonathan}, + date = {2019-04}, + pages = {379--393}, + publisher = {{ACM}}, + location = {{New York, NY, USA}}, + doi = {10.1145/3297858.3304042}, + url = {https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/201904-asplos-cheriabi.pdf}, + urldate = {2019-06-10}, + eventtitle = {{{ASPLOS}} 2019}, + isbn = {978-1-4503-6240-5}, + series = {{{ASPLOS}} '19}, + venue = {Providence, RI, USA} +} + +@inproceedings{sail-popl2019, + author = {Alasdair Armstrong and Thomas Bauereiss and Brian Campbell and Alastair Reid and Kathryn E. Gray and Robert M. Norton and Prashanth Mundkur and Mark Wassell and Jon French and Christopher Pulte and Shaked Flur and Ian Stark and Neel Krishnaswami and Peter Sewell}, + title = {{ISA} Semantics for {ARMv8-A, RISC-V, and CHERI-MIPS}}, + optcrossref = {}, + optkey = {}, + conf = {POPL 2019}, + booktitle = {\textbf{POPL 2019}: Proc. 46th ACM SIGPLAN Symposium on Principles of Programming Languages}, + optbooktitle = {}, + year = {2019}, + opteditor = {}, + optvolume = {}, + optnumber = {}, + optseries = {}, + optpages = {}, + month = jan, + optaddress = {}, + optorganization = {}, + optpublisher = {}, + note = {Proc. ACM Program. Lang. 3, POPL, Article 71}, + optnote = {}, + optannote = {}, + doi = {10.1145/3290384}, + abstract = {Architecture specifications notionally define the fundamental interface between hardware and software: the envelope of allowed behaviour for processor implementations, and the basic assumptions for software development and verification. But in practice, they are typically prose and pseudocode documents, not rigorous or executable artifacts, leaving software and verification on shaky ground. + +In this paper, we present rigorous semantic models for the sequential behaviour of large parts of the mainstream ARMv8-A, RISC-V, and MIPS architectures, and the research CHERI-MIPS architecture, that are complete enough to boot operating systems, variously Linux, FreeBSD, or seL4. Our ARMv8-A models are automatically translated from authoritative ARM-internal definitions, and (in one variant) tested against the ARM Architecture Validation Suite. + +We do this using a custom language for ISA semantics, Sail, with a lightweight dependent type system, that supports automatic generation of emulator code in C and OCaml, and automatic generation of proof-assistant definitions for Isabelle, HOL4, and (currently only for MIPS) Coq. We use the former for validation, and to assess specification coverage. To demonstrate the usability of the latter, we prove (in Isabelle) correctness of a purely functional characterisation of ARMv8-A address translation. We moreover integrate the RISC-V model into the RMEM tool for (user-mode) relaxed-memory concurrency exploration. We prove (on paper) the soundness of the core Sail type system. + +We thereby take a big step towards making the architectural abstraction actually well-defined, establishing foundations for verification and reasoning. +}, + pdf = {http://www.cl.cam.ac.uk/users/pes20/sail/sail-popl2019.pdf}, + topic = {ISA_semantics}, + project = {http://www.cl.cam.ac.uk/~pes20/sail/}, + recent = {true} +} + +@misc{sail-url, + author = {{REMS Project}}, + title = {{Sail Language}}, + howpublished={\url{https://www.cl.cam.ac.uk/~pes20/sail/}}, + year = 2018, +} + +@inproceedings{cerberus-popl2019, + author = {Kayvan Memarian and Victor B. F. Gomes and Brooks Davis and Stephen Kell and Alexander Richardson and Robert N. M. Watson and Peter Sewell}, + title = {Exploring {C} Semantics and Pointer Provenance}, + optcrossref = {}, + optkey = {}, + conf = {POPL 2019}, + booktitle = {\textbf{POPL 2019}: Proc. 46th ACM SIGPLAN Symposium on Principles of Programming Languages}, + optbooktitle = {}, + year = {2019}, + opteditor = {}, + optvolume = {}, + optnumber = {}, + optseries = {}, + optpages = {}, + month = jan, + optaddress = {}, + optorganization = {}, + optpublisher = {}, + note = {Proc. ACM Program. Lang. 3, POPL, Article 67}, + optannote = {}, + doi = {10.1145/3290380}, + pdf = {http://www.cl.cam.ac.uk/users/pes20/cerberus/cerberus-popl2019.pdf}, + supplementarymaterial = {http://www.cl.cam.ac.uk/users/pes20/cerberus/supplementary-material-popl2019}, + topic = {Cerberus}, + project = {http://www.cl.cam.ac.uk/~pes20/cerberus}, + abstract = {The semantics of pointers and memory objects in C has been a vexed question for many years. C values cannot be treated as either purely abstract or purely concrete entities: the language exposes their representations, but compiler optimisations rely on analyses that reason about provenance and initialisation status, not just runtime representations. The ISO WG14 standard leaves much of this unclear, and in some respects differs with de facto standard usage --- which itself is difficult to investigate. + +In this paper we explore the possible source-language semantics for memory objects and pointers, in ISO C and in C as it is used and implemented in practice, focussing especially on pointer provenance. We aim to, as far as possible, reconcile the ISO C standard, mainstream compiler behaviour, and the semantics relied on by the corpus of existing C code. We present two coherent proposals, tracking provenance via integers and not; both address many design questions. We highlight some pros and cons and open questions, and illustrate the discussion with a library of test cases. We make our semantics executable as a test oracle, integrating it with the Cerberus semantics for much of the rest of C, which we have made substantially more complete and robust, and equipped with a web-interface GUI. This allows us to experimentally assess our proposals on those test cases. To assess their viability with respect to larger bodies of C code, we analyse the changes required and the resulting behaviour for a port of FreeBSD to CHERI, a research architecture supporting hardware capabilities, which (roughly speaking) traps on the memory safety violations which our proposals deem undefined behaviour. We also develop a new runtime instrumentation tool to detect possible provenance violations in normal C code, and apply it to some of the SPEC benchmarks. We compare our proposal with a source-language variant of the twin-allocation LLVM semantics proposal of Lee et al. Finally, we describe ongoing interactions with WG14, exploring how our proposals could be incorporated into the ISO standard. +}, + recent = {true} +} + +@software{sail-cheri-mips, + title = {{{CTSRD-CHERI/sail-cheri-mips: CHERI-MIPS model written in Sail}}}, + author = {{Capability Hardware Enhanced RISC Instructions}}, + shorttitle = {{{sail-cheri-riscv}}}, + url = {https://github.com/CTSRD-CHERI/sail-cheri-mips}, +} + +@software{sail-cheri-riscv, + title = {{{CTSRD-CHERI/sail-cheri-riscv: CHERI-RISC-V model written in Sail}}}, + author = {{Capability Hardware Enhanced RISC Instructions}}, + shorttitle = {{{sail-cheri-riscv}}}, + url = {https://github.com/CTSRD-CHERI/sail-cheri-riscv}, +} + +@manual{arm-a64-v8-a-beta, + title={{ARM® A64 Instruction Set Architecture ARMv8, for ARMv8-A architecture profile}}, + organization={Arm Limited}, + howpublished={\url{https://static.docs.arm.com/ddi0596/a/DDI_0596_ARM_a64_instruction_set_architecture.pdf}}, + year = 2020, +} + +@misc{sparc-m7-adi, + title={{Introduction to SPARC M7 and Application Data Integrity (ADI)}}, + howpublished={\url{https://swisdev.oracle.com/_files/What-Is-ADI.html}} +} + +@inproceedings{mazzinghi:pointer-provenance, + author={Alfredo Mazzinghi and Ripduman Sohan and Robert N. M. Watson}, + title={{Pointer Provenance in a Capability Architecture}}, + booktitle={{Proceedings of the 10th USENIX Workshop on the Theory and Practice of Provenance (TaPP'18)}}, + city={London}, + month=jul, + year=2018 +} + +@inproceedings{xia:cherirtos, + title = {{{CheriRTOS}}: {{A Capability Model}} for {{Embedded Devices}}}, + shorttitle = {{{CheriRTOS}}}, + booktitle = {2018 {{IEEE}} 36th {{International Conference}} on {{Computer Design}} ({{ICCD}})}, + author = {Xia, Hongyan and Woodruff, Jonathan and Barral, Hadrien and Esswood, Lawrence and Joannou, Alexandre and Kovacsics, Robert and Chisnall, David and Roe, Michael and Davis, Brooks and Napierala, Edward and Baldwin, John and Gudka, Khilan and Neumann, Peter G. and Richardson, Alexander and Moore, Simon W. and Watson, Robert N. M.}, + date = {2018-10}, + pages = {92--99}, + publisher = {{IEEE}}, + location = {{Orlando, FL, USA}}, + doi = {10.1109/ICCD.2018.00023}, + url = {https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/201810-iccd2018-cheri-rtos.pdf}, + abstract = {Embedded systems are deployed ubiquitously among various sectors including automotive, medical, robotics and avionics. As these devices become increasingly connected, the attack surface also increases tremendously; new mechanisms must be deployed to defend against more sophisticated attacks while not violating resource constraints. In this paper we present CheriRTOS on CHERI-64, a hardware-software platform atop Capability Hardware Enhanced RISC Instructions (CHERI) for embedded systems. Our system provides efficient and scalable task isolation, fast and secure inter-task communication, fine-grained memory safety, and real-time guarantees, using hardware capabilities as the sole protection mechanism. We summarize state-of-the-art security and memory safety for embedded systems for comparison with our platform, illustrating the superior substrate provided by CHERI's capabilities. Finally, our evaluations show that a capability system can be implemented within the constraints of embedded systems.}, + eventtitle = {2018 {{IEEE}} 36th {{International Conference}} on {{Computer Design}} ({{ICCD}})}, + keywords = {attack surface,Capability Hardware Enhanced RISC Instructions,Capability model,capability system,capability systems,CHERI,CHERI-64,CheriRTOS,embedded devices,embedded systems,Embedded systems,fine-grained memory safety,Hardware,hardware capabilities,hardware-software platform,Kernel,memory safety,real time operating systems,Real-time systems,reduced instruction set computing,Safety,security,Security,storage management,Task analysis}, + series = {{{ICCD}}} +} + +@article{Woodruff2019, + title = {{{CHERI Concentrate}}: {{Practical Compressed Capabilities}}}, + shorttitle = {{{CHERI Concentrate}}}, + author = {Woodruff, Jonathan and Joannou, Alexandre and Xia, Hongyan and Fox, Anthony and Norton, Robert and Baureiss, Thomas and Chisnall, David and Davis, Brooks and Gudka, Khilan and Filardo, Nathaniel Wesley and Markettos, A. Theodore and Roe, Michael and Neumann, Peter G. and Watson, Robert N. M. and Moore, Simon W.}, + date = {2019-10}, + journaltitle = {IEEE Transactions on Computers}, + shortjournal = {TC}, + volume = {68}, + pages = {1455--1469}, + issn = {1557-9956}, + doi = {10.1109/TC.2019.2914037}, + url = {https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/2019tc-cheri-concentrate.pdf}, + urldate = {2019-06-16}, + keywords = {Capabilities,capability compression,capability fat pointers,CHERI concentrate,commodity operating system,compiled capability code,compressed encoding,compression,computer architecture,data compression,decode,decoding,Delays,design inefficiencies,developed capability-pointer system,efficiency 75.0 percent,encoding,Encoding,encoding format,existing software base,fat pointers,fat-pointer compression scheme,field programmable gate arrays,future computer systems,increased pointer size,legacy instruction sets,legacy software stack,memory safety,microprocessor chips,nonbypassable security properties,open-source CHERI prototype processor design,pipeline problems,pipeline processing,Pipelines,pointer arithmetic,pointer-modify operations,practical compressed capabilities,program compilers,reduced instruction set computing,Registers,RISC-style processor pipelines,Safety,Semantics,Software,state-of-the-art region-encoding efficiency,storage management,theorem proving,tree data structures}, + langid = {english}, + number = {10} +} + +@TechReport{UCAM-CL-TR-936, + author = {Joannou, Alexandre J. P.}, + title = {{High-performance memory safety: optimizing the CHERI + capability machine}}, + year = 2019, + month = may, + url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-936.pdf}, + institution = {University of Cambridge, Computer Laboratory}, + number = {UCAM-CL-TR-936} +} + +@article{DBLP:journals/scp/CampbellS16, + author = {Brian Campbell and + Ian Stark}, + title = {Randomised testing of a microprocessor model using {SMT}-solver state + generation}, + journal = {Sci. Comput. Program.}, + volume = {118}, + pages = {60--76}, + year = {2016}, + doi = {10.1016/j.scico.2015.10.012}, + timestamp = {Sat, 27 May 2017 14:22:55 +0200}, + biburl = {https://dblp.org/rec/bib/journals/scp/CampbellS16}, + bibsource = {dblp computer science bibliography, https://dblp.org} +} + +@inproceedings{Xia_CHERIvokeCharacterisingPointer_2019, + title = {{{CHERIvoke}}: {{Characterising Pointer Revocation}} Using {{CHERI Capabilities}} for {{Temporal Memory Safety}}}, + shorttitle = {{{CHERIvoke}}}, + booktitle = {Proceedings of the 52nd {{Annual IEEE}}/{{ACM International Symposium}} on {{Microarchitecture}}}, + author = {Xia, Hongyan and Woodruff, Jonathan and Ainsworth, Sam and Filardo, Nathaniel W. and Roe, Michael and Richardson, Alexander and Rugg, Peter and Neumann, Peter G. and Moore, Simon W. and Watson, Robert N. M. and Jones, Timothy M.}, + date = {2019-10-12}, + pages = {545--557}, + publisher = {{ACM}}, + location = {{New York, NY, USA}}, + doi = {10.1145/3352460.3358288}, + url = {https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/201910micro-cheri-temporal-safety.pdf}, + abstract = {A lack of temporal safety in low-level languages has led to an epidemic of use-after-free exploits. These have surpassed in number and severity even the infamous buffer-overflow exploits violating spatial safety. Capability addressing can directly enforce spatial safety for the C language by enforcing bounds on pointers and by rendering pointers unforgeable. Nevertheless, an efficient solution for strong temporal memory safety remains elusive. CHERI is an architectural extension to provide hardware capability addressing that is seeing significant commercial and open-source interest. We show that CHERI capabilities can be used as a foundation to enable low-cost heap temporal safety by facilitating out-of-date pointer revocation, as capabilities enable precise and efficient identification and invalidation of pointers, even when using unsafe languages such as C. We develop CHERIvoke, a technique for deterministic and fast sweeping revocation to enforce temporal safety on CHERI systems. CHERIvoke quarantines freed data before periodically using a small shadow map to revoke all dangling pointers in a single sweep of memory, and provides a tunable trade-off between performance and heap growth. We evaluate the performance of such a system using high-performance x86 processors, and further analytically examine its primary overheads. When configured with a heap-size overhead of 25\%, we find that CHERIvoke achieves an average execution-time overhead of under 5\%, far below the overheads associated with traditional garbage collection, revocation, or page-table systems.}, + isbn = {978-1-4503-6938-1}, + keywords = {architecture,security,temporal safety,use-after-free}, + series = {{{MICRO}} '52}, + venue = {Columbus, OH, USA} +} + +@article{skillicorn:partreeskel, +title = "Parallel Implementation of Tree Skeletons", +journal = "Journal of Parallel and Distributed Computing", +volume = "39", +number = "2", +pages = "115 - 125", +year = "1996", +issn = "0743-7315", +doi = "10.1006/jpdc.1996.0160", +url = "http://www.sciencedirect.com/science/article/pii/S0743731596901604", +author = "D.B. Skillicorn", +abstract = "Trees are a useful data type, but they are not routinely included in parallel programming systems, in part because their irregular structure makes partitioning and scheduling difficult. We present a method for algebraically constructing implementations of tree skeletons, high-level homomorphic operations that execute in parallel. Many computations on binary trees can be performed inO(logn) parallel time usingnprocessors, even taking account of communication costs. We extend these results to trees with arbitrary and variable degree. Then we show that it is possible to implement a distributed version of homomorphisms on binary trees, takingO(n/p+ log2p) parallel time onp < nprocessors, for trees of any skew and taking full account of communication costs. Under slightly stronger restrictions on the underlying functions, this can be improved toO(n/p+ logp). Furthermore, the technique for deriving distributed versions is algebraic, allowing the automatic generation of code for SPMD and data-parallel architectures." +} + +@TechReport{UCAM-CL-TR-951, + author = {Watson, Robert N. M. and Neumann, Peter G. and Woodruff, + Jonathan and Roe, Michael and Almatary, Hesham and + Anderson, Jonathan and Baldwin, John and Chisnall, David + and Clarke, Jessica and Davis, Brooks and Filardo, + Nathaniel Wesley and Joannou, Alexandre and Laurie, Ben and + Markettos, A. Theodore and Moore, Simon W. and Murdoch, + Steven J. and Nienhuis, Kyndylan and Norton, Robert and + Richardson, Alexander and Rugg, Peter and Sewell, Peter and + Son, Stacey and Xia, Hongyan}, + title = {{Capability Hardware Enhanced RISC Instructions: CHERI + Instruction-Set Architecture (Version 8)}}, + institution = {University of Cambridge, Computer Laboratory}, + address = {15 JJ Thomson Avenue, Cambridge CB3 0FD, United Kingdom, + phone +44 1223 763500}, + number = {UCAM-CL-TR-951}, + year = 2020, + month = sep, + url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-951.pdf}, +} + +@inproceedings{cheri-formal-SP2020, + author = {Kyndylan Nienhuis and Alexandre Joannou and Thomas Bauereiss and Anthony Fox and Michael Roe and Brian Campbell and Matthew Naylor and Robert M. Norton and Moore, Simon W. and Neumann, Peter G. and Ian Stark and Watson, Robert N. M. and Peter Sewell}, + title = {Rigorous engineering for hardware security: Formal modelling and proof in the {CHERI} design and implementation process}, + optcrossref = {}, + optkey = {}, + conf = {Security and Privacy 2020}, + booktitle = {Proceedings of the 41st IEEE Symposium on Security and Privacy (SP)}, + year = {2020}, + opteditor = {}, + optvolume = {}, + optnumber = {}, + optseries = {}, + pages = {1007--1024}, + month = may, + optaddress = {}, + optorganization = {}, + optpublisher = {}, + optnote = {}, + optannote = {}, + abstract = {The root causes of many security vulnerabilities include a pernicious combination of two problems, often regarded as inescapable aspects of computing. First, the protection mechanisms provided by the mainstream processor architecture and C/C++ language abstractions, dating back to the 1970s and before, provide only coarse-grain virtual-memory-based protection. Second, mainstream system engineering relies almost exclusively on test-and-debug methods, with (at best) prose specifications. These methods have historically sufficed commercially for much of the computer industry, but they fail to prevent large numbers of exploitable bugs, and the security problems that this causes are becoming ever more acute. + +In this paper we show how more rigorous engineering methods can be applied to the development of a new security-enhanced processor architecture, with its accompanying hardware implementation and software stack. We use formal models of the complete instruction-set architecture (ISA) at the heart of the design and engineering process, both in lightweight ways that support and improve normal engineering practice -- as documentation, in emulators used as a test oracle for hardware and for running software, and for test generation -- and for formal verification. We formalise key intended security properties of the design, and establish that these hold with mechanised proof. This is for the same complete ISA models (complete enough to boot operating systems), without idealisation. + +We do this for CHERI, an architecture with \emph{hardware capabilities} that supports fine-grained memory protection and scalable secure compartmentalisation, while offering a smooth adoption path for existing software. CHERI is a maturing research architecture, developed since 2010, with work now underway on an Arm industrial prototype to explore its possible adoption in mass-market commercial processors. The rigorous engineering work described here has been an integral part of its development to date, enabling more rapid and confident experimentation, and boosting confidence in the design. +}, + pdf = {https://www.cl.cam.ac.uk/users/pes20/cheri-formal.pdf}, + apollourl = {https://www.repository.cam.ac.uk/handle/1810/302580}, + publisherurl = {https://www.computer.org/csdl/proceedings-article/sp/2020/349700b007/1j2Lg3o6fdK}, + doi = {10.1109/SP40000.2020.00055}, + project = {https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/}, + topic = {cheri}, + cheriformal = {true}, + recent = {true} +} + +@inproceedings{cornucopia, + author = {Nathaniel Wesley Filardo and Brett F. Gutstein and Jonathan Woodruff and Sam Ainsworth and Lucian Paul-Trifu and Brooks Davis and Hongyan Xia and Edward Tomasz Napierala and Alexander Richardson and John Baldwin and David Chisnall and Jessica Clarke and Khilan Gudka and Alexandre Joannou and A. Theodore Markettos and Alfredo Mazzinghi and Robert M. Norton and Michael Roe and Peter Sewell and Stacey Son and Timothy M. Jones and Simon W. Moore and Peter G. Neumann and Robert N. M. Watson}, + conf = {Security and Privacy 2020}, + booktitle = {Proceedings of the 41st IEEE Symposium on Security and Privacy (SP)}, + title = {Cornucopia: {{Temporal Safety}} for {{CHERI Heaps}}}, + date = {2020-05}, + volume = {}, + issn = {2375-1207}, + pages = {1507--1524}, + keywords = {}, + doi = {10.1109/SP40000.2020.00098}, + pdf = {https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/2020oakland-cornucopia.pdf}, + url = {https://www.cl.cam.ac.uk/research/security/ctsrd/pdfs/2020oakland-cornucopia.pdf}, + apollourl = {https://www.repository.cam.ac.uk/handle/1810/304040}, + publisherurl = {https://doi.ieeecomputersociety.org/10.1109/SP40000.2020.00098}, + publisher = {IEEE Computer Society}, + address = {Los Alamitos, CA, USA}, + month = may, + abstract = {Use-after-free violations of temporal memory safety continue to plague software systems, underpinning many high-impact exploits. The CHERI capability system shows great promise in achieving C and C++language spatial memory safety, preventing out-of-bounds accesses. Enforcing language-level temporal safety on CHERI requires capability revocation, traditionally achieved either via table lookups (avoided for performance in the CHERI design) or by identifying capabilities in memory to revoke them (similar to a garbage-collector sweep). CHERIvoke,a prior feasibility study, suggested that CHERI’s tagged capabilities could make this latter strategy viable, but modeled only architectural limits and did not consider the full implementation or evaluation of the approach. + +Cornucopia is a lightweight capability revocation system for CHERI that implements non-probabilistic C/C++temporal memory safety for standard heap allocations. It extends the CheriBSD virtual-memory subsystem to track capability flow through memory and provides a concurrent kernel-resident revocation service that is amenable to multi-processor and hardware acceleration. We demonstrate an average overhead of less than 2\% and a worst-case of 8.9\% for concurrent revocation on compatible SPECCPU2006 benchmarks on a multi-core CHERI CPU on FPGA, and we validate Cornucopia against the Juliet test suite’s corpus of temporally unsafe programs. We test its compatibility with a large corpus of C programs by using a revoking allocator as the system allocator while booting multi-user CheriBSD. Cornucopia is a viable strategy for always-on temporal heap memory safety, suitable for production environments. +}, + project = {https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/}, + topic = {cheri}, + recent = {true} +} + +@TechReport{UCAM-CL-TR-940, + author = {Nienhuis, Kyndylan and Joannou, Alexandre and Fox, Anthony + and Roe, Michael and Bauereiss, Thomas and Campbell, Brian + and Naylor, Matthew and Norton, Robert M. and Moore, Simon + W. and Neumann, Peter G. and Stark, Ian and Watson, Robert + N. M. and Sewell, Peter}, + title = {{Rigorous engineering for hardware security: formal + modelling and proof in the CHERI design and implementation + process}}, + year = 2019, + month = sep, + url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-940.pdf}, + institution = {University of Cambridge, Computer Laboratory}, + number = {UCAM-CL-TR-940} +} + +@TechReport{UCAM-CL-TR-941, + author = {Watson, Robert N. M. and Moore, Simon W. and Sewell, Peter + and Neumann, Peter G.}, + title = {{An Introduction to CHERI}}, + year = 2019, + month = sep, + url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-941.pdf}, + institution = {University of Cambridge, Computer Laboratory}, + number = {UCAM-CL-TR-941} +} + +@TechReport{UCAM-CL-TR-947, + author = {Watson, Robert N. M. and Richardson, Alexander and Davis, + Brooks and Baldwin, John and Chisnall, David and Clarke, + Jessica and Filardo, Nathaniel and Moore, Simon W. and + Napierala, Edward and Sewell, Peter and Neumann, Peter G.}, + title = {{CHERI C/C++ Programming Guide}}, + year = 2020, + month = jun, + url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-947.pdf}, + institution = {University of Cambridge, Computer Laboratory}, + number = {UCAM-CL-TR-947} +} + +@TechReport{UCAM-CL-TR-949, + author = {Richardson, Alexander}, + title = {{Complete spatial safety for C and C++ using CHERI + capabilities}}, + year = 2020, + month = jun, + url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-949.pdf}, + institution = {University of Cambridge, Computer Laboratory}, + number = {UCAM-CL-TR-949} +} + +@inproceedings{yu2019speculative, + langid = {english}, + title={{Speculative Taint Tracking (STT) A Comprehensive Protection for + Speculatively Accessed Data}}, + author={Yu, Jiyong and Yan, Mengjia and Khyzha, Artem and Morrison, Adam and + Torrellas, Josep and Fletcher, Christopher W}, + booktitle={Proceedings of the 52nd {{IEEE}}/{{ACM International Symposium}} on {{Microarchitecture}} ({{IEEE MICRO}} 2019)}, + series = {{{MICRO}}-52 '17}, + date = {2019-10}, + venue = {Columbus, Ohio, USA} +} + +@online{CHERI-cheri-cpu, + title = {{CTSRD-CHERI/cheri-cpu: CHERI-MIPS implementation in a 6-stage pipeline with associative caches and multi-core support}}, + url = {https://github.com/CTSRD-CHERI/cheri-cpu}, + urldate = {2020-09-16} +} + +@online{CHERI-Piccolo, + title = {{CTSRD-CHERI/Piccolo: RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)}}, + url = {https://github.com/CTSRD-CHERI/Piccolo}, + urldate = {2020-09-16} +} + +@online{CHERI-Flute, + title = {{CTSRD-CHERI/Flute: RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance}}, + url = {https://github.com/CTSRD-CHERI/Flute}, + urldate = {2020-09-16} +} + +@online{CHERI-Toooba, + title = {{CTSRD-CHERI/Toooba: RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT}}, + url = {https://github.com/CTSRD-CHERI/Toooba}, + urldate = {2020-09-16} +} + +@online{CHERI-TagController, + title = {{CTSRD-CHERI/TagController: Multi-level tag controller for emulating a tagged memory using an in-memory table}}, + url = {https://github.com/CTSRD-CHERI/TagController}, + urldate = {2020-09-16} +} + +@online{CHERI-cheri-cap-lib, + title = {{CTSRD-CHERI/cheri-cap-lib: A library of specific implementations of cheri and providing an abstract interface to those implementations}}, + url = {https://github.com/CTSRD-CHERI/cheri-cap-lib}, + urldate = {2020-09-16} +} + +@manual{arm-morello, + title={{Arm Architecture Reference Manual Supplement: Morello for A-profile + Architecture}}, + %url = {https://documentation-service.arm.com/static/5f8da6fef86e16515cdb861e}, + urldate = {2020-10-22}, + organization = {Arm Limited}, + year = 2020, +} diff --git a/def-riscv-insns-macros.tex b/def-riscv-insns-macros.tex new file mode 100644 index 00000000..f1bba4d5 --- /dev/null +++ b/def-riscv-insns-macros.tex @@ -0,0 +1,299 @@ +\ifcsname @def@riscv@insns@macros@tex\endcsname + \ea\endinput +\fi +\ea\gdef\csname @def@riscv@insns@macros@tex\endcsname{1} + +\makeatletter +% class func name tablestr +\newcommand{\@rvcheriencdef}[4]{% + \ea\ifx\csname @rvcheri@enc@func2name@#1@\the\numexpr(#2)\endcsname\relax% + \csgdef{@rvcheri@enc@func2name@#1@\the\numexpr(#2)}{#3}% + \csgdef{@rvcheri@enc@func2tablestr@#1@\the\numexpr(#2)}{#4}% + \else% + \def\@rvcheriencdef@duperror##1{% + \GenericError{[RISC-V (#1)] }{Duplicate encoding}{% + [RISC-V (#1)] Function code 0x##1 for #3\MessageBreak% + is already assigned to \csname @rvcheri@enc@func2name@#1@\the\numexpr(#2)\endcsname% + }{}% + }% + \ea\@rvcheriencdef@duperror\ea{\hex{\the\numexpr(#2)}}% + \fi% +} +\newcommand{\@rvcheriencusetablestr}[2]{\csuse{@rvcheri@enc@func2tablestr@#1@\the\numexpr(#2)}} + +\let\@rvcherisubclass@tablesuffix\@empty +\define@key{@rvcherisubclass}{tablesuffix}{\def\@rvcherisubclass@tablesuffix{#1}} +\newcommand{\rvcherisubclass}[4][]{{% + \setkeys{@rvcherisubclass}{#1}% + \def\@rvcheriencdef@partial##1{\@rvcheriencdef{#2}{"#3}{#4}{#4##1}}% + \ea\@rvcheriencdef@partial\ea{\@rvcherisubclass@tablesuffix}% +}} + +\newbool{@rvcheri@header} +\newcommand{\rvcheriheader}{\booltrue{@rvcheri@header}} +\newcommand{\@rvcheri@ifheader}[1]{% + \ifbool{@rvcheri@header}{% + \global\boolfalse{@rvcheri@header}% + #1% + }{}% +} +\newcommand{\@rvcherisrcsrcdest}[4]{ + \begin{bytefield}{32} + \@rvcheri@ifheader{% + \bitheader[endianness=big]{0,6,7,11,12,14,15,19,20,24,25,31}\\ + }% + \bitbox{7}{#1} + \bitbox{5}{#4} + \bitbox{5}{#3} + \bitbox{3}{0x0} + \bitbox{5}{#2} + \bitbox{7}{0x5b} + \end{bytefield}% +} +\newcommand{\@rvcherisrcsrcdestimm}[4]{ + \begin{bytefield}{32} + \@rvcheri@ifheader{% + \bitheader[endianness=big]{0,6,7,11,12,14,15,19,20,31}\\ + }% + \bitbox{12}{#4[11:0]} + \bitbox{5}{#3} + \bitbox{3}{#1} + \bitbox{5}{#2} + \bitbox{7}{0x5b} + \end{bytefield}% +} +\newcommand{\@rvcherisrcsrcdestclear}[4]{ + \begin{bytefield}{32} + \@rvcheri@ifheader{% + \bitheader[endianness=big]{0,6,7,11,12,14,15,17,18,19,20,24,25,31}\\ + }% + \bitbox{7}{#1} + \bitbox{5}{#4} + \bitbox{2}{#3} + \bitbox{3}{#2$_{[7:5]}$} + \bitbox{3}{0x0} + \bitbox{5}{#2$_{[4:0]}$} + \bitbox{7}{0x5b} + \end{bytefield}% +} + +\newcommand{\@rvcherisrcsrc}[3]{\@rvcherisrcsrcdest{0x7e}{#1}{#2}{#3}} +\newcommand{\@rvcherisrc}[2]{\@rvcherisrcsrc{0x1f}{#2}{#1}} +\newcommand{\@rvcherisrcdest}[3]{\@rvcherisrcsrcdest{0x7f}{#2}{#3}{#1}} +\newcommand{\@rvcheridest}[2]{\@rvcherisrcdest{0x1f}{#2}{#1}} +\newcommand{\@rvcheriscr}[4]{\@rvcherisrcsrcdest{#1}{#2}{#4}{#3}} +\newcommand{\@rvchericlear}[1]{\@rvcherisrcsrcdestclear{0x7f}{m}{q}{#1}} +\newcommand{\@rvcheriexpload}[3]{\@rvcherisrcsrcdest{0x7d}{#2}{#3}{#1}} +\newcommand{\@rvcheriexpstore}[3]{\@rvcherisrcsrcdest{0x7c}{#1}{#3}{#2}} +\newcommand{\@rvcheriexpstorecond}[4]{\@rvcherisrcsrcdest{0x7c}{#1}{#4}{#2/#3}} + +\newcommand{\@rvcheriasmdef}[2]{% + \ea\ifx\csname @rvcheri@asm@#1\endcsname\relax% + \csgdef{@rvcheri@asm@#1}{#2}% + \else% + \def\@rvcheriasmdef@duperror##1{% + \GenericError{[RISC-V] }{Duplicate assembly ID}{% + [RISC-V] Instruction ID ##1 already has an assembly definition% + }% + }% + \@rvcheriasmdef@duperror{#1}% + \fi% +} + +\newcommand{\@rvcheriasmencdef}[4]{% + \ifthenelse{\equal{\@rvcheriinsn@name}{}}{% + }{% + \ea\def% + \ea\@rvcheriasmencdef@asm@partial% + \ea##\ea1% + \ea{% + \csname rvcheriasmfmt\ea\endcsname% + \ea[\@rvcheriinsn@restriction]{\csname#2\endcsname{##1} #4}}% + \ea\ea\ea\def% + \ea\ea\ea\@rvcheriasmencdef@asm% + \ea\ea\ea{% + \ea\@rvcheriasmencdef@asm@partial% + \ea{\@rvcheriinsn@name}}% + \ea\ea\ea\@rvcheriasmdef\ea\ea\ea{\ea\@rvcheriinsn@id\ea}\ea{\@rvcheriasmencdef@asm}% + \ifthenelse{\equal{\@rvcheriinsn@id}{\@rvcheriinsn@shortid}}{% + }{% + \ea\ea\ea\@rvcheriasmdef\ea\ea\ea{\ea\@rvcheriinsn@shortid\ea}\ea{\@rvcheriasmencdef@asm}% + }% + \ifthenelse{\equal{\@rvcheriinsn@notable}{true}}{% + }{% + \def\@rvcheriasmencdef@rvcheriencdef@partial{\@rvcheriencdef{#1}{#3}}% + \ea\def\ea\@rvcheriasmencdef@hypershortname\ea{% + \csname#2\ea\endcsname\ea*\ea{\@rvcheriinsn@shortname}% + }% + \ea\ea\ea\def\ea\ea\ea\@rvcheriasmencdef@tablestr\ea\ea\ea{% + \ea\@rvcheriasmencdef@hypershortname\@rvcheriinsn@tablesuffix% + }% + \ea\ea\ea\@rvcheriasmencdef@rvcheriencdef@partial% + \ea\ea\ea{% + \ea\@rvcheriinsn@name% + \ea}% + \ea{% + \ea\unexpanded\ea{\@rvcheriasmencdef@tablestr}% + }% + }% + }% +} + +\let\@rvcheriinsn@name\@empty +\def\@rvcheriinsn@notable{false} +\def\@rvcheriinsn@rawfunc{false} +\let\@rvcheriinsn@tablesuffix\@empty +\define@key{@rvcheriinsn}{name}{\def\@rvcheriinsn@name{#1}} +\define@key{@rvcheriinsn}{notable}[true]{\def\@rvcheriinsn@notable{#1}} +\define@key{@rvcheriinsn}{rawfunc}[true]{\def\@rvcheriinsn@rawfunc{#1}} +\define@key{@rvcheriinsn}{restriction}{\def\@rvcheriinsn@restriction{#1}} +\define@key{@rvcheriinsn}{shortname}{\def\@rvcheriinsn@shortname{#1}} +\define@key{@rvcheriinsn}{tablesuffix}{\def\@rvcheriinsn@tablesuffix{#1}} +\def\@rvcheriinsnsetkeys#1{% + \setkeys{@rvcheriinsn}{#1}% + \ea\ifx\csname @rvcheriinsn@shortname\endcsname\relax% + \let\@rvcheriinsn@shortname\@rvcheriinsn@name% + \fi% + \ea\ifx\csname @rvcheriinsn@name\endcsname\relax% + \else% + \ea\def\ea\@rvcheriinsn@id\ea{\@rvcheriinsn@name}% + \ea\def\ea\@rvcheriinsn@shortid\ea{\@rvcheriinsn@shortname}% + \ea\ifx\csname @rvcheriinsn@restriction\endcsname\relax% + \let\@rvcheriinsn@restriction\@empty% + \else% + \ea\ea\ea\def\ea\ea\ea\@rvcheriinsn@id\ea\ea\ea{\ea\@rvcheriinsn@id\ea:\@rvcheriinsn@restriction}% + \ea\ea\ea\def\ea\ea\ea\@rvcheriinsn@shortid\ea\ea\ea{\ea\@rvcheriinsn@shortid\ea:\@rvcheriinsn@restriction}% + \fi% + \fi% +} +\def\@rvcheriinsnfmtfunc#1{% + \ifthenelse{\equal{\@rvcheriinsn@rawfunc}{true}}{% + #1% + }{% + 0x\lowercase{#1}% + }% +} + +\newcommand{\@rvcheribitboxdef@single}[2]{% + \ea\ifx\csname @rvcheri@bitbox@#1\endcsname\relax% + \csgdef{@rvcheri@bitbox@#1}{#2}% + \else% + \def\@rvcheribitboxdef@duperror##1{% + \GenericError{[RISC-V] }{Duplicate bitbox ID}{% + [RISC-V] Instruction ID ##1 already has a bitbox definition% + }% + }% + \@rvcheribitboxdef@duperror{#1}% + \fi% +} + +\newcommand{\@rvcheribitboxdef}[1]{% + \ea\@rvcheribitboxdef@single\ea{\@rvcheriinsn@id}{#1}% + \ifthenelse{\equal{\@rvcheriinsn@id}{\@rvcheriinsn@shortid}}{% + }{% + \ea\@rvcheribitboxdef@single\ea{\@rvcheriinsn@shortid}{#1}% + }% +} + +\def\@rvcherirawbitbox#1{% + \csname @rvcheri#1\endcsname% +} +\let\rvcherirawbitbox\@rvcherirawbitbox + +\newcommand{\rvcherisrcsrcdest}[5][]{{% + \@rvcheriinsnsetkeys{#1}% + \@rvcheribitboxdef{\@rvcherirawbitbox{srcsrcdest}{\@rvcheriinsnfmtfunc{#2}}{#3}{#4}{#5}}% + \@rvcheriasmencdef{srcsrcdest}{rvcheriasminsnref}{"#2}{#3, #4, #5}% +}} +\newcommand{\rvcherisrcsrcdestimm}[5][]{{% + \@rvcheriinsnsetkeys{#1}% + \@rvcheribitboxdef{\@rvcherirawbitbox{srcsrcdestimm}{\@rvcheriinsnfmtfunc{#2}}{#3}{#4}{#5}}% + \@rvcheriasmencdef{top}{rvcheriasminsnref}{"#2}{#3, #4, #5}% +}} +\newcommand{\rvcherisrcsrc}[4][]{{% + \@rvcheriinsnsetkeys{#1}% + \@rvcheribitboxdef{\@rvcherirawbitbox{srcsrc}{\@rvcheriinsnfmtfunc{#2}}{#3}{#4}}% + \@rvcheriasmencdef{srcsrc}{rvcheriasminsnref}{"#2}{#3, #4}% +}} +\newcommand{\rvcherisrc}[3][]{{% + \@rvcheriinsnsetkeys{#1}% + \@rvcheribitboxdef{\@rvcherirawbitbox{src}{\@rvcheriinsnfmtfunc{#2}}{#3}}% + \@rvcheriasmencdef{src}{rvcheriasminsnref}{"#2}{#3}% +}} +\newcommand{\rvcherisrcdest}[4][]{{% + \@rvcheriinsnsetkeys{#1}% + \@rvcheribitboxdef{\@rvcherirawbitbox{srcdest}{\@rvcheriinsnfmtfunc{#2}}{#3}{#4}}% + \@rvcheriasmencdef{srcdest}{rvcheriasminsnref}{"#2}{#3, #4}% +}} +\newcommand{\rvcheridest}[3][]{{% + \@rvcheriinsnsetkeys{#1}% + \@rvcheribitboxdef{\@rvcherirawbitbox{dest}{\@rvcheriinsnfmtfunc{#2}}{#3}}% + \@rvcheriasmencdef{dest}{rvcheriasminsnref}{"#2}{#3}% +}} + +\newcommand{\rvcheriscr}[5][]{{% + \@rvcheriinsnsetkeys{#1}% + \@rvcheribitboxdef{\@rvcherirawbitbox{scr}{\@rvcheriinsnfmtfunc{#2}}{#3}{#4}{#5}}% + \@rvcheriasmencdef{srcsrcdest}{rvcheriasminsnref}{"#2}{#3, #4, #5}% +}} +\newcommand{\rvchericlear}[2][]{{% + \@rvcheriinsnsetkeys{#1}% + \@rvcheribitboxdef{\@rvcherirawbitbox{clear}{\@rvcheriinsnfmtfunc{#2}}}% + \@rvcheriasmencdef{srcdest}{rvcheriasminsnref}{"#2}{q(uarter), m(ask)}% +}} + +\newcommand{\rvcheriexpload}[4][]{{% + \@rvcheriinsnsetkeys{#1}% + \@rvcheribitboxdef{\@rvcherirawbitbox{expload}{\@rvcheriinsnfmtfunc{#2}}{#3}{#4}}% + \ifthenelse{\equal{\@rvcheriinsn@restriction}{RV128}}{% + \@rvcheriasmencdef{expload}{rvcheriasminsnnoref}{"#2}{#3, #4}% + }{% + \@rvcheriasmencdef{expload}{rvcheriasminsnref}{"#2}{#3, #4}% + }% +}} +\newcommand{\rvcheriexploadres}[4][]{{% + \@rvcheriinsnsetkeys{#1}% + \@rvcheribitboxdef{\@rvcherirawbitbox{expload}{\@rvcheriinsnfmtfunc{#2}}{#3}{#4}}% + \@rvcheriasmencdef{expload}{rvcheriasminsnnoref}{"#2}{#3, #4}% +}} +\newcommand{\rvcheriexpstore}[4][]{{% + \@rvcheriinsnsetkeys{#1}% + \@rvcheribitboxdef{\@rvcherirawbitbox{expstore}{\@rvcheriinsnfmtfunc{#2}}{#3}{#4}}% + \ifthenelse{\equal{\@rvcheriinsn@restriction}{RV128}}{% + \@rvcheriasmencdef{expstore}{rvcheriasminsnnoref}{"#2}{#3, #4}% + }{% + \@rvcheriasmencdef{expstore}{rvcheriasminsnref}{"#2}{#3, #4}% + }% +}} +\newcommand{\rvcheriexpstorecond}[5][]{{% + \@rvcheriinsnsetkeys{#1}% + \@rvcheribitboxdef{\@rvcherirawbitbox{expstorecond}{\@rvcheriinsnfmtfunc{#2}}{#3}{#4}{#5}}% + \@rvcheriasmencdef{expstore}{rvcheriasminsnnoref}{"#2}{#4, #5}% +}} + +\newcommand{\rvcheribitbox}[1]{% + \ea\ifx\csname @rvcheri@bitbox@#1\endcsname\relax% + \def\rvcheribitbox@unknownerr##1{% + \GenericError{[RISC-V] }{Unknown bitbox ID}{% + [RISC-V] Instruction ID ##1 has no known bitbox definition% + }{}% + }% + \rvcheribitbox@unknownerr{#1}% + \else% + \csname @rvcheri@bitbox@#1\endcsname% + \fi% +} + +\newcommand{\rvcheriasm}[1]{% + \ea\ifx\csname @rvcheri@asm@#1\endcsname\relax% + \def\rvcheriasm@unknownerr##1{% + \GenericError{[RISC-V] }{Unknown assembly ID}{% + [RISC-V] Instruction ID ##1 has no known assembly definition% + }{}% + }% + \rvcheriasm@unknownerr{#1}% + \else% + \csname @rvcheri@asm@#1\endcsname% + \fi% +} +\makeatother diff --git a/def-riscv-insns.tex b/def-riscv-insns.tex new file mode 100644 index 00000000..7f27eed5 --- /dev/null +++ b/def-riscv-insns.tex @@ -0,0 +1,139 @@ +\ifcsname @def@riscv@insns@tex\endcsname + \ea\endinput +\fi +\ea\gdef\csname @def@riscv@insns@tex\endcsname{1} + +\input{def-riscv-insns-macros} + +\rvcherisubclass{top}{0}{Two Source \& Dest} + +\rvcherisubclass{srcsrcdest}{7C}{Stores} +\rvcherisubclass{srcsrcdest}{7D}{Loads} +\rvcherisubclass{srcsrcdest}{7E}{Two Source} +\rvcherisubclass{srcsrcdest}{7F}{Source \& Dest} + +\rvcherisubclass{srcsrc}{1F}{One Source} + +\rvcherisubclass{srcdest}{1F}{Dest-Only} + +\rvcherisrcdest[name=CGetPerm]{0}{rd}{cs1} +\rvcherisrcdest[name=CGetType]{1}{rd}{cs1} +\rvcherisrcdest[name=CGetBase]{2}{rd}{cs1} +\rvcherisrcdest[name=CGetLen]{3}{rd}{cs1} +\rvcherisrcdest[name=CGetTag]{4}{rd}{cs1} +\rvcherisrcdest[name=CGetSealed]{5}{rd}{cs1} +\rvcherisrcdest[name=CGetOffset]{6}{rd}{cs1} +\rvcherisrcdest[name=CGetFlags]{7}{rd}{cs1} +\rvcherisrcdest[name=CGetAddr]{F}{rd}{cs1} + +\rvcherisrcsrcdest[name=CSeal]{B}{cd}{cs1}{cs2} +\rvcherisrcsrcdest[name=CUnseal]{C}{cd}{cs1}{cs2} +\rvcherisrcsrcdest[name=CAndPerm]{D}{cd}{cs1}{rs2} +\rvcherisrcsrcdest[name=CSetFlags]{E}{cd}{cs1}{rs2} +\rvcherisrcsrcdest[name=CSetOffset]{F}{cd}{cs1}{rs2} +\rvcherisrcsrcdest[name=CSetAddr]{10}{cd}{cs1}{rs2} +\rvcherisrcsrcdest[name=CIncOffset]{11}{cd}{cs1}{rs2} +\rvcherisrcsrcdestimm[name=CIncOffsetImm]{1}{cd}{cs1}{imm} +\rvcherisrcsrcdest[name=CSetBounds]{8}{cd}{cs1}{rs2} +\rvcherisrcsrcdest[name=CSetBoundsExact]{9}{cd}{cs1}{rs2} +\rvcherisrcsrcdestimm[name=CSetBoundsImm]{2}{cd}{cs1}{uimm} +\rvcherisrcdest[name=CClearTag]{B}{cd}{cs1} +\rvcherisrcsrcdest[name=CBuildCap]{1D}{cd}{cs1}{cs2} +\rvcherisrcsrcdest[name=CCopyType]{1E}{cd}{cs1}{cs2} +\rvcherisrcsrcdest[name=CCSeal]{1F}{cd}{cs1}{cs2} +\rvcherisrcdest[name=CSealEntry]{11}{cd}{cs1} + +\rvcherisrcsrcdest[name=CToPtr]{12}{rd}{cs1}{cs2} +\rvcherisrcsrcdest[name=CFromPtr]{13}{cd}{cs1}{rs2} +\rvcherisrcsrcdest[name=CSub]{14}{rd}{cs1}{cs2} +\rvcherisrcdest[name=CMove]{A}{cd}{cs1} + +\rvcherisrcsrcdest[name=CTestSubset]{20}{rd}{cs1}{cs2} +\rvcherisrcsrcdest[name=CSetEqualExact,shortname=CSEQX]{21}{rd}{cs1}{cs2} + +\rvcherisrcdest[name=CJALR]{C}{cd}{cs1} +\rvcherisrcsrc[name=CInvoke]{1}{cs1}{cs2} + +\rvcheriscr[name=CSpecialRW]{1}{cd}{scr}{cs1} + +\rvchericlear[name=Clear]{D} +\rvchericlear[name=CClear]{E} +\rvchericlear[name=FPClear]{10} + +\rvcherisrcdest[name=CRoundRepresentableLength,shortname=CRRL]{8}{rd}{rs1} +\rvcherisrcdest[name=CRepresentableAlignmentMask,shortname=CRAM]{9}{rd}{rs1} + +\rvcherisrcdest[name=CLoadTags]{12}{rd}{cs1} +\rvcherisrc[name=CClearTags]{0}{cs1} + +\rvcheriexpload[name=LB.DDC]{00}{rd}{rs1} +\rvcheriexpload[name=LH.DDC]{01}{rd}{rs1} +\rvcheriexpload[name=LW.DDC]{02}{rd}{rs1} +\rvcheriexpload[name=LC.DDC,restriction=RV32,notable]{03}{cd}{rs1} +\rvcheriexpload[name=LD.DDC,restriction=RV64/128]{03}{rd}{rs1} +\rvcheriexpload[name=LC.DDC,restriction=RV64,notable]{17}{cd}{rs1} +\rvcheriexpload[name=LQ.DDC,restriction=RV128]{17}{rd}{rs1} +\rvcheriexpload[name=LBU.DDC]{04}{rd}{rs1} +\rvcheriexpload[name=LHU.DDC]{05}{rd}{rs1} +\rvcheriexpload[name=LWU.DDC,restriction=RV64/128]{06}{rd}{rs1} +\rvcheriexpload[name=LDU.DDC,restriction=RV128,tablesuffix=\rvcherildufootnotemark]{07}{rd}{rs1} + +\rvcheriexpload[name=LB.CAP]{08}{rd}{cs1} +\rvcheriexpload[name=LH.CAP]{09}{rd}{cs1} +\rvcheriexpload[name=LW.CAP]{0A}{rd}{cs1} +\rvcheriexpload[name=LC.CAP,restriction=RV32,notable]{0B}{cd}{cs1} +\rvcheriexpload[name=LD.CAP,restriction=RV64/128]{0B}{rd}{cs1} +\rvcheriexpload[name=LC.CAP,restriction=RV64,notable]{1F}{cd}{cs1} +\rvcheriexpload[name=LQ.CAP,restriction=RV128]{1F}{rd}{cs1} +\rvcheriexpload[name=LBU.CAP]{0C}{rd}{cs1} +\rvcheriexpload[name=LHU.CAP]{0D}{rd}{cs1} +\rvcheriexpload[name=LWU.CAP,restriction=RV64/128]{0E}{rd}{cs1} +\rvcheriexpload[name=LDU.CAP,restriction=RV128,tablesuffix=\rvcherildufootnotemark]{0F}{rd}{cs1} + +\rvcheriexploadres[name=LR.B.DDC,tablesuffix=\rvcheriatomicfootnotemark]{10}{rd}{rs1} +\rvcheriexploadres[name=LR.H.DDC,tablesuffix=\rvcheriatomicfootnotemark]{11}{rd}{rs1} +\rvcheriexploadres[name=LR.W.DDC,tablesuffix=\rvcheriatomicfootnotemark]{12}{rd}{rs1} +\rvcheriexploadres[name=LR.C.DDC,restriction=RV32,tablesuffix=\rvcheriatomicfootnotemark,notable]{13}{cd}{rs1} +\rvcheriexploadres[name=LR.D.DDC,restriction=RV64/128,tablesuffix=\rvcheriatomicfootnotemark]{13}{rd}{rs1} +\rvcheriexploadres[name=LR.C.DDC,restriction=RV64,tablesuffix=\rvcheriatomicfootnotemark,notable]{14}{cd}{rs1} +\rvcheriexploadres[name=LR.Q.DDC,restriction=RV128,tablesuffix=\rvcheriatomicfootnotemark]{14}{rd}{rs1} + +\rvcheriexploadres[name=LR.B.CAP,tablesuffix=\rvcheriatomicfootnotemark]{18}{rd}{cs1} +\rvcheriexploadres[name=LR.H.CAP,tablesuffix=\rvcheriatomicfootnotemark]{19}{rd}{cs1} +\rvcheriexploadres[name=LR.W.CAP,tablesuffix=\rvcheriatomicfootnotemark]{1A}{rd}{cs1} +\rvcheriexploadres[name=LR.C.CAP,restriction=RV32,tablesuffix=\rvcheriatomicfootnotemark,notable]{1B}{cd}{cs1} +\rvcheriexploadres[name=LR.D.CAP,restriction=RV64/128,tablesuffix=\rvcheriatomicfootnotemark]{1B}{rd}{cs1} +\rvcheriexploadres[name=LR.C.CAP,restriction=RV64,tablesuffix=\rvcheriatomicfootnotemark,notable]{1C}{cd}{cs1} +\rvcheriexploadres[name=LR.Q.CAP,restriction=RV128,tablesuffix=\rvcheriatomicfootnotemark]{1C}{rd}{cs1} + +\rvcheriexpstore[name=SB.DDC]{00}{rs2}{rs1} +\rvcheriexpstore[name=SH.DDC]{01}{rs2}{rs1} +\rvcheriexpstore[name=SW.DDC]{02}{rs2}{rs1} +\rvcheriexpstore[name=SC.DDC,restriction=RV32,notable]{03}{cs2}{rs1} +\rvcheriexpstore[name=SD.DDC,restriction=RV64/128]{03}{rs2}{rs1} +\rvcheriexpstore[name=SC.DDC,restriction=RV64,notable]{04}{cs2}{rs1} +\rvcheriexpstore[name=SQ.DDC,restriction=RV128]{04}{rs2}{rs1} + +\rvcheriexpstore[name=SB.CAP]{08}{rs2}{cs1} +\rvcheriexpstore[name=SH.CAP]{09}{rs2}{cs1} +\rvcheriexpstore[name=SW.CAP]{0A}{rs2}{cs1} +\rvcheriexpstore[name=SC.CAP,restriction=RV32,notable]{0B}{cs2}{cs1} +\rvcheriexpstore[name=SD.CAP,restriction=RV64/128]{0B}{rs2}{cs1} +\rvcheriexpstore[name=SC.CAP,restriction=RV64,notable]{0C}{cs2}{cs1} +\rvcheriexpstore[name=SQ.CAP,restriction=RV128]{0C}{rs2}{cs1} + +\rvcheriexpstorecond[name=SC.B.DDC,tablesuffix=\rvcheriatomicfootnotemark]{10}{rd}{rs2}{rs1} +\rvcheriexpstorecond[name=SC.H.DDC,tablesuffix=\rvcheriatomicfootnotemark]{11}{rd}{rs2}{rs1} +\rvcheriexpstorecond[name=SC.W.DDC,tablesuffix=\rvcheriatomicfootnotemark]{12}{rd}{rs2}{rs1} +\rvcheriexpstorecond[name=SC.C.DDC,restriction=RV32,tablesuffix=\rvcheriatomicfootnotemark,notable]{13}{cd}{cs2}{rs1} +\rvcheriexpstorecond[name=SC.D.DDC,restriction=RV64/128,tablesuffix=\rvcheriatomicfootnotemark]{13}{rd}{rs2}{rs1} +\rvcheriexpstorecond[name=SC.C.DDC,restriction=RV64,tablesuffix=\rvcheriatomicfootnotemark,notable]{14}{cd}{cs2}{rs1} +\rvcheriexpstorecond[name=SC.Q.DDC,restriction=RV128,tablesuffix=\rvcheriatomicfootnotemark]{14}{rd}{rs2}{rs1} + +\rvcheriexpstorecond[name=SC.B.CAP,tablesuffix=\rvcheriatomicfootnotemark]{18}{rd}{rs2}{cs1} +\rvcheriexpstorecond[name=SC.H.CAP,tablesuffix=\rvcheriatomicfootnotemark]{19}{rd}{rs2}{cs1} +\rvcheriexpstorecond[name=SC.W.CAP,tablesuffix=\rvcheriatomicfootnotemark]{1A}{rd}{rs2}{cs1} +\rvcheriexpstorecond[name=SC.C.CAP,restriction=RV32,tablesuffix=\rvcheriatomicfootnotemark,notable]{1B}{cd}{cs2}{cs1} +\rvcheriexpstorecond[name=SC.D.CAP,restriction=RV64/128,tablesuffix=\rvcheriatomicfootnotemark]{1B}{rd}{rs2}{cs1} +\rvcheriexpstorecond[name=SC.C.CAP,restriction=RV64,tablesuffix=\rvcheriatomicfootnotemark,notable]{1C}{cd}{cs2}{cs1} +\rvcheriexpstorecond[name=SC.Q.CAP,restriction=RV128,tablesuffix=\rvcheriatomicfootnotemark]{1C}{rd}{rs2}{cs1} diff --git a/fig-cheri-high-level.graffle b/fig-cheri-high-level.graffle new file mode 100644 index 00000000..82a4903c --- /dev/null +++ b/fig-cheri-high-level.graffle @@ -0,0 +1,4104 @@ + + + + + ActiveLayerIndex + 0 + ApplicationVersion + + com.omnigroup.OmniGraffle6 + 156.11.0.206384 + + AutoAdjust + + BackgroundGraphic + + Bounds + {{0, 0}, {1677, 783}} + Class + SolidGraphic + ID + 2 + Style + + stroke + + Draws + NO + + + + BaseZoom + 0 + CanvasOrigin + {0, 0} + ColumnAlign + 1 + ColumnSpacing + 36 + CreationDate + 2010-11-07 19:08:10 +0000 + Creator + Robert Watson + DisplayScale + 1.0000 cm = 1.0000 cm + GraphDocumentVersion + 11 + GraphicsList + + + Bounds + {{1243, 165}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17 + + ID + 849 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.800572 + r + 0.570245 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs34 \cf0 class3} + + + + Bounds + {{1246, 162}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 14 + + ID + 848 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.800572 + r + 0.570245 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + + + Bounds + {{1288, 120}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17 + + ID + 847 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.800572 + r + 0.570245 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs34 \cf0 class2} + + + + Bounds + {{1215, 111}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17 + + ID + 846 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.800572 + r + 0.570245 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs34 \cf0 class1} + + + + Bounds + {{1291, 117}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 14 + + ID + 845 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.800572 + r + 0.570245 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + + + Bounds + {{1218, 108}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 14 + + ID + 844 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.800572 + r + 0.570245 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + + + Bounds + {{1053, 157}, {63, 18}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 10 + + ID + 843 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.618155 + r + 0.690895 + + + shadow + + Draws + NO + + stroke + + Pattern + 5 + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs20 \cf0 ABI wrapper} + + + + Bounds + {{891, 108}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17 + + ID + 823 + Shape + Rectangle + Style + + fill + + Color + + b + 0.6 + g + 0.6 + r + 1 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs34 \cf0 libssl} + + + + Bounds + {{894, 105}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 14 + + ID + 842 + Shape + Rectangle + Style + + fill + + Color + + b + 0.6 + g + 0.6 + r + 1 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs28 \cf0 libssl} + + + + Bounds + {{1000, 183}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17 + + ID + 831 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.800572 + r + 0.570245 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs34 \cf0 class2} + + + + Bounds + {{1053, 121}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17 + + ID + 830 + Shape + Rectangle + Style + + fill + + Color + + b + 0.6 + g + 0.6 + r + 1 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs34 \cf0 libssl} + + + + Bounds + {{981, 108}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17 + + ID + 829 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.800572 + r + 0.570245 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs34 \cf0 class1} + + + + Bounds + {{1003, 180}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 14 + + ID + 841 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.800572 + r + 0.570245 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + + + Bounds + {{1056, 118}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 14 + + ID + 840 + Shape + Rectangle + Style + + fill + + Color + + b + 0.6 + g + 0.6 + r + 1 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + + + Bounds + {{984, 105}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 14 + + ID + 839 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.800572 + r + 0.570245 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + + + Bounds + {{819, 108}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17 + + ID + 821 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.800572 + r + 0.570245 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs34 \cf0 zlib} + + + + Bounds + {{822, 105}, {63, 36}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 14 + + ID + 838 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.800572 + r + 0.570245 + + + shadow + + Draws + NO + ShadowVector + {4, 0} + + stroke + + Pattern + 24 + Width + 2 + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs28 \cf0 zlib} + + + + Bounds + {{729, 108}, {63, 36}} + Class + ShapedGraphic + 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+{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs34 \cf0 \ +\ +\ +Legacy Fetch uses pure-capability zlib via an ABI wrapper} + + + + Class + LineGraphic + FontInfo + + Color + + w + 0 + + Font + Helvetica + Size + 16 + + ID + 762 + Points + + {1143, 324} + {1143, 369} + + Style + + stroke + + HeadArrow + DimensionArrow + Legacy + + TailArrow + DimensionArrow + + + + + Class + LineGraphic + FontInfo + + Color + + w + 0 + + Font + Helvetica + Size + 16 + + ID + 761 + Points + + {1143, 99} + {1143, 324} + + Style + + stroke + + HeadArrow + DimensionArrow + Legacy + + TailArrow + DimensionArrow + + + + + Class + LineGraphic + FontInfo + + Color + + w + 0 + + Font + Helvetica + Size + 16 + + ID + 760 + Points + + {468, 324} + {468.125, 369} + + Style + + stroke + + HeadArrow + DimensionArrow + Legacy + + TailArrow + DimensionArrow + + + + + Class + LineGraphic + FontInfo + + Color + + w + 0 + + Font + Helvetica + Size + 16 + + ID + 759 + Points + + {468, 279} + {468, 324} + + Style + + stroke + + HeadArrow + DimensionArrow + Legacy + + TailArrow + DimensionArrow + + + + + Class + LineGraphic + FontInfo + + Color + + w + 0 + + Font + Helvetica + Size + 16 + + ID + 758 + Points + + {468, 99} + {468, 279} + + Style + + stroke + + HeadArrow + DimensionArrow + Legacy + + TailArrow + DimensionArrow + + + + + Bounds + {{972, 306}, {153, 18}} + Class + ShapedGraphic + FontInfo + + Font + Times-Roman + Size + 13 + + ID + 752 + Shape + Rectangle + Style + + fill + + Color + + b + 0.686048 + g + 0.87529 + r + 1 + + + shadow + + Draws + NO + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs26 \cf0 Address-space executive} + + + + Bounds + {{648, 261}, {152.99999999999994, 18}} + Class + ShapedGraphic + FontInfo + + Font + Times-Roman + Size + 13 + + ID + 750 + Shape + Rectangle + Style + + fill + + Color + + b + 0.686048 + g + 0.87529 + r + 1 + + + shadow + + Draws + NO + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs26 \cf0 Address-space executive} + + + + Bounds + {{486, 261}, {153, 18}} + Class + ShapedGraphic + FontInfo + + Font + Times-Roman + Size + 13 + + ID + 749 + Shape + Rectangle + Style + + fill + + Color + + b + 0.686048 + g + 0.87529 + r + 1 + + + shadow + + Draws + NO + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs26 \cf0 Address-space executive} + + + + Bounds + {{1206, 99}, {153, 252}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17 + + ID + 748 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.800572 + r + 0.570245 + + + shadow + + Draws + NO + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs34 \cf0 \ +\ +\ +\ +\ +\ +Capability-based single-address-space OS and applications} + + + + Bounds + {{486, 324}, {639, 45}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17 + + ID + 746 + Shape + Rectangle + Style + + fill + + Color + + b + 0.6 + g + 0.6 + r + 1 + + + shadow + + Draws + NO + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs34 \cf0 Hypervisor / Separation Kernel\ ++ CHERI support for guest capabilities} + + + + Bounds + {{648, 99}, {152.99999999999994, 162}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17 + + ID + 744 + Shape + Rectangle + Style + + fill + + Color + + b + 1 + g + 0.705882 + r + 0.705882 + + + shadow + + Draws + NO + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs34 \cf0 \ +\ +\ +Hybrid Netsurf links against legacy and pure-capability code} + + + + Bounds + {{486, 279}, {477, 45}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17 + + ID + 740 + Shape + Rectangle + Style + + fill + + Color + + b + 0.6 + g + 0.6 + r + 1 + + + shadow + + Draws + NO + + + Text + + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural\qc + +\f0\fs34 \cf0 FreeBSD kernel\ ++ CHERI support for userspace capabilities} + + + + Bounds + {{684, 423}, {485.99999999999994, 18}} + Class + ShapedGraphic + FontInfo + + Font + Times-Roman + Size + 17.5 + + ID + 766 + Shape + Rectangle + Style + + fill + + Color + + a + 0.94 + b + 1 + g + 1 + r + 1 + + Draws + NO + + shadow + + Draws + NO + + stroke + + CornerRadius + 24 + Draws + NO + + + Text + + Align + 0 + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural + +\f0\fs35 \cf0 \'91Pure-capability\'92 code uses CHERI capabilities for all C pointers} + + + + Bounds + {{666, 423}, {19, 18}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17.5 + + ID + 765 + Shape + Rectangle + Style + + fill + + Color + + b + 0.999799 + g + 0.799056 + r + 0.57138 + + + shadow + + Draws + NO + + + + + Bounds + {{54, 450}, {20.169230769230769, 18}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17.5 + + ID + 763 + Shape + Rectangle + Style + + fill + + Color + + b + 0.99923 + g + 0.619122 + r + 0.688901 + + + shadow + + Draws + NO + + + + + Bounds + {{684, 450}, {485.99999999999994, 18}} + Class + ShapedGraphic + FontInfo + + Font + Times-Roman + Size + 17.5 + + ID + 757 + Shape + Rectangle + Style + + fill + + Color + + a + 0.94 + b + 1 + g + 1 + r + 1 + + Draws + NO + + shadow + + Draws + NO + + stroke + + CornerRadius + 24 + Draws + NO + + + Text + + Align + 0 + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural + +\f0\fs35 \cf0 Per-address-space memory-management and capability executive} + + + + Bounds + {{74.215384615384664, 423}, {618.78461538461534, 18}} + Class + ShapedGraphic + FontInfo + + Font + Times-Roman + Size + 17.5 + + ID + 756 + Shape + Rectangle + Style + + fill + + Color + + a + 0.94 + b + 1 + g + 1 + r + 1 + + Draws + NO + + shadow + + Draws + NO + + stroke + + CornerRadius + 24 + Draws + NO + + + Text + + Align + 0 + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural + +\f0\fs35 \cf0 \'91Legacy\'92 code compiled against a RISC ISA} + + + + Bounds + {{74.215384615384664, 450}, {618.78461538461534, 18}} + Class + ShapedGraphic + FontInfo + + Font + Times-Roman + Size + 17.5 + + ID + 755 + Shape + Rectangle + Style + + fill + + Color + + a + 0.94 + b + 1 + g + 1 + r + 1 + + Draws + NO + + shadow + + Draws + NO + + stroke + + CornerRadius + 24 + Draws + NO + + + Text + + Align + 0 + Text + {\rtf1\ansi\ansicpg1252\cocoartf1265\cocoasubrtf210 +{\fonttbl\f0\froman\fcharset0 Times-Roman;} +{\colortbl;\red255\green255\blue255;} +\pard\tx560\tx1120\tx1680\tx2240\tx2800\tx3360\tx3920\tx4480\tx5040\tx5600\tx6160\tx6720\pardirnatural + +\f0\fs35 \cf0 \'91Hybrid\'92 code uses RISC pointers or source-code annotated CHERI capabilities} + + + + Bounds + {{666, 450}, {19, 18}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17.5 + + ID + 754 + Shape + Rectangle + Style + + fill + + Color + + b + 0.686331 + g + 0.873776 + r + 0.998587 + + + shadow + + Draws + NO + + + + + Bounds + {{54, 423}, {20.169230769230769, 18}} + Class + ShapedGraphic + FontInfo + + Color + + w + 0 + + Font + Times-Roman + Size + 17.5 + + ID + 753 + Shape + Rectangle + Style + + fill + + Color + + b + 0.565423 + g + 0.556722 + r + 0.999373 + + + shadow + + Draws + NO + + + + + GridInfo + + ShowsGrid + YES + SnapsToGrid + YES + + GuidesLocked + NO + GuidesVisible + YES + HPages + 3 + ImageCounter + 1 + KeepToScale + + Layers + + + Lock + NO + Name + Layer 1 + Print + YES + View + YES + + + LayoutInfo + + Animate + NO + circoMinDist + 18 + circoSeparation + 0.0 + layoutEngine + dot + neatoLineLength + 0.20000000298023224 + neatoSeparation + 0.0 + twopiSeparation + 0.0 + + LinksVisible + NO + MagnetsVisible + NO + MasterSheets + + ModificationDate + 2014-11-14 19:27:16 +0000 + Modifier + Robert Watson + NotesVisible + NO + Orientation + 2 + OriginVisible + NO + PageBreaks + YES + PrintInfo + + NSBottomMargin + + float + 41 + + NSHorizonalPagination + + coded + BAtzdHJlYW10eXBlZIHoA4QBQISEhAhOU051bWJlcgCEhAdOU1ZhbHVlAISECE5TT2JqZWN0AIWEASqEhAFxlwCG + + NSLeftMargin + + float + 18 + + NSPaperSize + + size + {595, 842} + + NSPrintReverseOrientation + + coded + BAtzdHJlYW10eXBlZIHoA4QBQISEhAhOU051bWJlcgCEhAdOU1ZhbHVlAISECE5TT2JqZWN0AIWEASqEhAFxlwCG + + NSRightMargin + + float + 18 + + NSTopMargin + + float + 18 + + + PrintOnePage + + ReadOnly + NO + RowAlign + 1 + RowSpacing + 36 + SheetTitle + Canvas 1 + SmartAlignmentGuidesActive + YES + SmartDistanceGuidesActive + YES + UniqueID + 1 + UseEntirePage + + VPages + 1 + WindowInfo + + BottomSlabHeight + 534 + CurrentSheet + 0 + Expanded_Canvases + + Frame + {{102, -590}, {1436, 878}} + ShowInfo + + ShowRuler + + Sidebar + + SidebarWidth + 230 + VisibleRegion + {{-50, -344}, {1778, 1472}} + Zoom + 0.5 + ZoomValues + + + Canvas 1 + 0.5 + 0.25 + + + + + diff --git a/fig-cheri-high-level.pdf b/fig-cheri-high-level.pdf new file mode 100644 index 00000000..5fbdb5b1 Binary files /dev/null and b/fig-cheri-high-level.pdf differ diff --git a/fig-pointer-provenance.graffle b/fig-pointer-provenance.graffle new file mode 100644 index 00000000..8d8a4091 Binary files /dev/null and b/fig-pointer-provenance.graffle differ diff --git a/fig-pointer-provenance.pdf b/fig-pointer-provenance.pdf new file mode 100644 index 00000000..94876157 Binary files /dev/null and b/fig-pointer-provenance.pdf differ diff --git a/fig-representable-regions.tex b/fig-representable-regions.tex new file mode 100644 index 00000000..5faaf7af --- /dev/null +++ b/fig-representable-regions.tex @@ -0,0 +1,100 @@ +\documentclass[tikz]{standalone} +\input{preamble} % include all the common macros and font settings + +\colorlet{fred}{red!60} +\colorlet{fgreen}{olive!40!green} +\colorlet{famber}{orange!60} +\colorlet{dred}{red!60} +\colorlet{dgreen}{olive!40!green} +\colorlet{damber}{orange!80} + +\begin{document} + +\begin{tikzpicture}[x=\linewidth/15,y=\linewidth/15] + +% parameter coordinates +\coordinate (redbl) at (0,0); +\coordinate (redtr) at (1,7); +\coordinate (repbl) at (0,12 / 16 * 7 / 2); +\coordinate (reptr) at (1,28 / 16 * 7 / 2); +\coordinate (derbl) at (0.3,14 / 16 * 7 / 2); % Not to scale, but close, so example labels don't merge +\coordinate (dertr) at (1 ,20 / 16 * 7 / 2); +\def\extextx{-4} % Example Text X +\def\slubracex{-2.25}% Space {L,U} brace X +\def\sluseplx{-2} % Space {L,U} sep left X +\def\sluarrx{-1.5} % Space {L,U} arrow X +\def\srseplx{-1} % Space R sep left X +\def\srarrx{-0.5} % Space R arrow X +\def\rlabelx{-0.3} % R phase label x +\def\sdseplx{0.3} % Space D sep left X +\def\sdseprx{1.5} % Space D sep right X +\def\srseprx{1.5} % Space R sep right X +\def\sluseprx{2} % Space {L,U} sep right X +\def\srbracex{2.25} % Space R brace X +\def\sdbracex{2.5} % Space D brace X + +% central rectangles +\filldraw[pattern=crosshatch, pattern color=fred, draw=dred, thick] (redbl) rectangle coordinate (redc) (redtr); +\draw[preaction={fill, white}, pattern=north west lines, pattern color=famber, draw=damber, thick] (repbl) rectangle (reptr); +\draw[preaction={fill, white}, pattern=north east lines, pattern color=fgreen, draw=dgreen, thick] (derbl) rectangle (dertr); + +% dereferencable region (space D) labels +\coordinate (sdseplx) at (\sdseplx,0); +\coordinate (sdseprx) at (\sdseprx,0); +\draw[dgreen] (sdseplx |- derbl) -- (sdseprx |- derbl) node [pos=1,anchor=base west] {$b$}; +\draw[dgreen] (sdseplx |- dertr) -- (sdseprx |- dertr) node [pos=1,anchor=base west] {$t$}; +\coordinate (sdbracex) at (\sdbracex,0); +\draw[dgreen,decoration={brace,mirror},decorate] (sdbracex |- derbl) -- (sdbracex |- dertr) node [midway,anchor=west,align=left,xshift=5pt] {dereferenceable\\region}; + +% represenatable region (space R) labels +\coordinate (srseplx) at (\srseplx,0); +\coordinate (srseprx) at (\srseprx,0); +\coordinate (srarrx) at (\srarrx,0); +\draw[damber] (srseplx |- repbl) -- (srseprx |- repbl) node [pos=1,anchor=base west] {$r_b$}; +\draw[damber] (srseplx |- reptr) -- (srseprx |- reptr) node [pos=1,anchor=base west] {$r_t$}; +\draw[<->,thick,damber] (srarrx |- repbl) -- (srarrx |- reptr) node [midway,left]{$s$}; +\coordinate (srbracex) at (\srbracex,0); +\draw[damber,decoration={brace,mirror,aspect=.85},decorate] (srbracex |- repbl) -- (srbracex |- reptr) node [pos=.85,anchor=west,align=left,xshift=5pt] {representable\\space, $space_\text{R}$}; + +\coordinate (rlabelx) at (\rlabelx,0); +\draw[<->,thick,dashed,damber] (rlabelx |- redbl) -- (rlabelx |- repbl) node [midway,left=-2pt] {\footnotesize $R 2^{E}$} ; + +\coordinate (multextbase) at ({(\sluseprx,0)} |- redbl); +\node[anchor=base west,inner sep=0pt,black,align=left] at ($(multextbase)+(0.25,0)$) {multiple of $s = 2^{E+14}$}; + +\coordinate (extextx) at (\extextx,0); +\node[anchor=base east,gray] (exbase) at (extextx |- redbl) {\footnotesize\texttt{0x10000}}; +\draw[dotted,gray] (exbase.base east) -- ({(\sluseplx,0)} |- redbl) ; +\node[anchor=base east,gray] (exsmid) at (extextx |- redc) {\footnotesize\texttt{0x20000}}; +\draw[dotted,gray] (exsmid.base east) -- ({(\sluseplx,0)} |- redc); +\node[anchor=north,gray,inner sep=0pt] (exshi) at (redtr -| exsmid) {\footnotesize\texttt{0x30000}}; +\draw[dotted,gray] (exshi.north east -| exsmid.east) -- ({(\sluseplx,0)} |- redtr); + +\node[anchor=base east,gray] (exrb) at (extextx |- repbl) {\footnotesize\texttt{0x1C000}}; +\draw[dotted,gray] (exrb.base east) -- ({(\srseplx,0)} |- repbl); + +\node[anchor=base east,gray] (exrb) at (extextx |- derbl) {\footnotesize\texttt{0x1E000}}; +\draw[dotted,gray] (exrb.base east) -- ({(\sdseplx,0)} |- derbl); + +\node[anchor=base east,gray] (exrb) at (extextx |- dertr) {\footnotesize\texttt{0x24000}}; +\draw[dotted,gray] (exrb.base east) -- ({(\sdseplx,0)} |- dertr); + +\node[anchor=base east,gray] (exrb) at (extextx |- reptr) {\footnotesize\texttt{0x2C000}}; +\draw[dotted,gray] (exrb.base east) -- ({(\srseplx,0)} |- reptr); + +% space L,U partiton lines +\draw[black] ({(\sluseplx,0)} |- redbl) -- ({(\sluseprx,0)} |- redbl); +\draw[black] ({(\sluseplx,0)} |- redc) -- ({(\sluseprx,0)} |- redc); +\draw[black] ({(\sluseplx,0)} |- redtr) -- ({(\sluseprx,0)} |- redtr); +\draw[<->,thick,black,xshift=-.5pt] ({(\sluarrx,0)} |- redbl) -- ({(\sluarrx,0)} |- redc) node [midway,left] {$s$} ; +\draw[<->,thick,black,xshift=.5pt] ({(\sluarrx,0)} |- redc) -- ({(\sluarrx,0)} |- redtr) node [midway,left] {$s$} ; + +% space label braces +\coordinate (spacebraceb) at ({(\slubracex,0)} |- redbl); +\coordinate (spacebracem) at (spacebraceb |- redc); +\coordinate (spacebracet) at (spacebraceb |- redtr); +\draw[decoration={brace},decorate] (spacebraceb) -- (spacebracem) node [midway,left] {$space_\text{L}$}; +\draw[decoration={brace},decorate] (spacebracem) -- (spacebracet) node [midway,left] {$space_\text{U}$}; + +\end{tikzpicture} +\end{document} diff --git a/fig-sentry-plt.tex b/fig-sentry-plt.tex new file mode 100644 index 00000000..928962f9 --- /dev/null +++ b/fig-sentry-plt.tex @@ -0,0 +1,43 @@ +\documentclass[tikz]{standalone} +\input{preamble} % include all the common macros and font settings + +\begin{document} +\begin{tikzpicture} + + \matrix [row sep=20pt, column sep=10pt] { + % + \node[draw] (i1w) {instance 1 read-write region} ; + % + & \node[draw] (ro) {read-only region} ; + % + & \node[draw] (i2w) {instance 2 read-write region} ; + % + \\ + % + \node[draw] (i1p) {instance 1 PLT} ; + % + & + % + & \node[draw] (i2p) {instance 2 PLT} ; \\ + % + } ; + + \draw [->] (i1p) -| (ro.230) ; + \draw [->] (i2p) -| (ro.300) ; + + \draw [dotted,->] ([xshift=-10pt]i1w.south) -- ([xshift=-20pt]i1p.north) ; + \draw [->] ([xshift=20pt]i1p.north) -- ([xshift=10pt]i1w.south) ; + + \draw [dotted,->] ([xshift=-10pt]i2w.south) -- ([xshift=-20pt]i2p.north) ; + \draw [->] ([xshift=20pt]i2p.north) -- ([xshift=10pt]i2w.south) ; + + \coordinate (i1s) at ([xshift=-05pt,yshift=-10pt]i1p.south) {} ; \draw [->] (i1s) -- ([xshift=-05pt]i1p.south) ; + \coordinate (i1s) at ([xshift=-10pt,yshift=-10pt]i1p.south) {} ; \draw [->] (i1s) -- ([xshift=-10pt]i1p.south) ; + \coordinate (i1s) at ([xshift=-15pt,yshift=-10pt]i1p.south) {} ; \draw [->] (i1s) -- ([xshift=-15pt]i1p.south) ; + + \coordinate (i2s) at ([xshift=-05pt,yshift=-10pt]i2p.south) {} ; \draw [->] (i2s) -- ([xshift=-05pt]i2p.south) ; + \coordinate (i2s) at ([xshift=-10pt,yshift=-10pt]i2p.south) {} ; \draw [->] (i2s) -- ([xshift=-10pt]i2p.south) ; + \coordinate (i2s) at ([xshift=-15pt,yshift=-10pt]i2p.south) {} ; \draw [->] (i2s) -- ([xshift=-15pt]i2p.south) ; + +\end{tikzpicture} +\end{document} diff --git a/fig-type-token.tex b/fig-type-token.tex new file mode 100644 index 00000000..59c4b0d1 --- /dev/null +++ b/fig-type-token.tex @@ -0,0 +1,84 @@ +\documentclass[tikz]{standalone} +\input{preamble} % include all the common macros and font settings + +\begin{document} +\begin{tikzpicture} + + \node[draw] (pcode) at (9.5,2) {class code} ; + + \matrix (pgtm) at (7,0) [matrix of nodes, inner sep=1pt, row sep=0pt, draw] { + unsealing right \\ + method 1 guard \\ + method 2 guard \\ + }; + \path (pgtm-1-1.south) -- (pgtm-2-1.north) coordinate (x) [midway] ; \draw (x -| pgtm.west) -- (x -| pgtm.east); + \path (pgtm-2-1.south) -- (pgtm-3-1.north) coordinate (x) [midway] ; \draw (x -| pgtm.west) -- (x -| pgtm.east); + + \draw [->,dotted] (pgtm-1-1.east -| pgtm.east) -| (pcode.south west) ; + \draw [->] (pgtm-2-1 -| pgtm.east) -| ([xshift=3pt]pcode.south) ; + \draw [->] (pgtm-3-1 -| pgtm.east) -| ([xshift=8pt]pcode.south) ; + + \matrix (pvtm) at ([xshift=-15pt]pgtm.south west) [anchor=south east, matrix of nodes, inner sep=1pt, row sep=0pt, draw] { + method 1 sentry\vphantom{guard} \\ + method 2 sentry\vphantom{guard} \\ + } ; + \path (pvtm-1-1.south) -- (pvtm-2-1.north) coordinate (x) [midway] ; \draw (x -| pvtm.west) -- (x -| pvtm.east); + + \node [above=2pt of pvtm.north west,anchor=south west,inner sep=0pt] {\emph{VTable}:} ; + + \draw [->] (pvtm-1-1 -| pvtm.east) -- (pgtm-2-1 -| pgtm.west); + \draw [->] (pvtm-2-1 -| pvtm.east) -- (pgtm-3-1 -| pgtm.west); + + \matrix (o) at (0,0.5) [matrix of nodes, inner sep=1pt, row sep=0pt, align=center] { + type token \\ + instance data \\ + {\vphantom{x}} \\ + {\vphantom{x}} \\ + {\vphantom{x}} \\ + } ; + + \matrix (oh) [matrix of nodes, inner sep=1pt, row sep=0pt, draw, above=2 pt of o.north, anchor=south] { + VTable capability \\ + |[align=center]{ sealed RW \\ data capability };| \\ + } ; + \path (oh-1-1.south) -- (oh-2-1.north) coordinate (x) [midway] ; \draw (x -| oh.west) -- (x -| oh.east); + + \draw [->] (oh-1-1 -| oh.east) -| ([xshift=-10pt]pvtm.north west) -- (pvtm.north west) ; + + \node (ofit) [draw,inner sep=0pt,outer sep=0pt,fit=(o-1-1.west -| oh.west)(o-1-1.east -| oh.east)(o)] {} ; + \path (o-1-1.south) -- (o-2-1.north) coordinate (x) [midway] ; + \draw (x -| ofit.west) -- (x -| ofit.east); + + \draw [->,dotted] (o-1-1 -| ofit.east) -| (pcode.south west) ; + + \draw [->] (oh-2-1 -| oh.east) -- +(5pt,0) |- (ofit.north east); + + \draw [decorate,decoration={brace,amplitude=10pt,mirror},xshift=0,yshift=-4pt] + ([yshift=-10pt,xshift=-5pt]pvtm.south -| ofit.west) -- ([yshift=-10pt,xshift=5pt]pvtm.south -| ofit.east) + node [midway,below=10pt] {Per instance} ; + + \matrix (pgtc) [matrix of nodes, inner sep=1pt, row sep=0pt, draw, above=55pt of pgtm.north, anchor=south east] { + constructor guard \\ + sealing capability \\ + }; + \path (pgtc-1-1.south) -- (pgtc-2-1.north) coordinate (x) [midway] ; \draw (x -| pgtc.west) -- (x -| pgtc.east); + + \draw [->,dotted] (pgtc-2-1 -| pgtc.east) -| (pcode.north west) ; + \draw [->] (pgtc-1-1 -| pgtc.east) -| ([xshift=-3pt]pcode.north) ; + + \draw [decorate,decoration={brace,amplitude=10pt,mirror},xshift=0,yshift=-4pt] + ([yshift=-10pt,xshift=-5pt]pvtm.south west) -- ([yshift=-10pt,xshift=5pt]pvtm.south -| pcode.east) + node [midway,below=10pt] {Per class} ; + + \node [anchor=east] (csentry) at ([xshift=-30pt]pgtc-1-1 -| oh.west) {constructor sentry} ; + \draw [->] (csentry.east) -- (pgtc-1-1 -| pgtc.west) ; + + \node [anchor=east] (optr) at (csentry.east |- oh.north west) {object capability} ; + \draw [->] (optr.east) -- (oh.north west) ; + + \draw [decorate,decoration={brace,amplitude=10pt,mirror},xshift=0,yshift=-4pt] + ([yshift=-10pt,xshift=-5pt]pvtm.south -| csentry.west) -- ([yshift=-10pt,xshift=5pt]pvtm.south -| optr.east) + node [midway,below=10pt] {Held by caller} ; + + \end{tikzpicture} +\end{document} diff --git a/glossary.tex b/glossary.tex new file mode 100644 index 00000000..41f7ee18 --- /dev/null +++ b/glossary.tex @@ -0,0 +1,928 @@ +\newglossaryentry{abstract capability} +{ + name=abstract capability, + description={ +% Abstract capabilities maintain the appearance of capability +% lifespan across operations that violate architectural \gls{capability +% provenance}. +% For example, abstract capabilities remain valid despite an OS kernel +% swapping them to and from disk, which requires that any architectural +% \gls{capability} in the swapped memory have its \gls{capability tag} +% restored through re-derivation + Abstract capabilities are a conceptual abstraction that overlays the + concrete capabilities of the architecture to describe the intended + maintenance of capability lifespan across operations that violate + architectural \gls{capability provenance}. + For example, if an OS kernel + swaps a page containing a capability to and from disk, + it will have to have its \gls{capability tag} + restored through re-derivation, so there is no longer an + architectural provenance relationship between the two, but for + application-level reasoning it is sometimes useful to regard there + to be one} +} + +\newglossaryentry{address} +{ + name=address, + description={An integer address suitable for dereference within an address + space. + In \gls{CHERI-MIPS}, \glspl{capability} are always interpreted in terms of + \glspl{virtual address}. + In \gls{CHERI-RISC-V}, \glspl{capability} may be interpreted as + \glspl{virtual address} -- or \glspl{physical address} when operating in + Machine Mode} +} + +\longnewglossaryentry{capability} +{ + name=capability, + plural=capabilities, +} +{ + A capability contains an \gls{address}, \gls{capability bounds} + describing a range of bytes within which addresses may be + \glslink{dereference}{dereferenced}, \gls{capability permissions} + controlling the forms of dereference that may be permitted (e.g., load or + store), a \gls{capability tag} protecting \gls{capability validity} + (integrity and \gls{capability provenance}), and a \gls{capability object type} + indicating whether it is a \gls{sealed capability} + (and, if so, under which \gls{capability object type} they are sealed) + or \gls{unsealed capability}. + The address embedded within a capability may be a \gls{virtual address} or + a \glspl{physical address} depending on the current addressing mode; when + used to authorize (un)sealing, the address is instead a + \gls{capability object type}. + + In CHERI, capabilities are used to implement \glspl{pointer} with additional + protections in aid of \gls{fine-grained memory protection}, + \gls{control-flow robustness}, and other higher-level protection models such + as \gls{software compartmentalization}. + Unlike a \gls{fat pointer}, capabilities are subject to + \gls{capability provenance}, ensuring that they are derived from a prior + valid capability only via valid manipulations, and \gls{capability + monotonicity}, which ensures that manipulation can lead only to + non-increasing rights. + CHERI capabilities provide strong compatibility with C-language pointers and + Memory Management Unit (MMU)-based system-software designs, by virtue of + its \gls{hybrid capability model}. + + Architecturally, a capability can be viewed as an \gls{address} equal to the + sum of the \gls{capability base} and \gls{capability offset}, as well as + associated metadata. +%\psnote{Perhaps this base/offset view should now be de-emphasised? It's +%arguably implementation detail in any case} + Dereferencing a capability is done relative to that address. +% The implementation may choose to store the pre-computed address +% combining the base and offset, to avoid an implied addition on each memory +% access, and to similarly store the base and length as pre-computed +% addresses. + The size of an in-memory capability may be smaller than the sum of its + architectural fields (such as base, offset, and permissions) if a + \gls{compressed capability} mechanism, such as \gls{CHERI Concentrate}, is + used. + + In the ISA, capabilities may be used explicitly via \gls{capability-based + instructions}, an application of the \gls{principle of intentional use}, + but also implicitly using \glslink{legacy instructions}{legacy load + and store instructions} via the \gls{default data capability}, and + instruction fetch via the \gls{program-counter capability}. + A capability is either sealed or unsealed, controlling whether it has + software-defined or instruction-set-defined behavior, and whether or not its + fields are immutable. + + Capabilities may be held in a \gls{capability register} in a dedicated + \gls{capability register file}, a \gls{merged register file}, or a + suitably aligned \gls{tagged memory}. +} + +\newglossaryentry{capability base} +{ + name=capability base, + description={The lower of the two \gls{capability bounds}, from which + the \gls{address} of a \gls{capability} can be calculated by using + the \gls{capability offset}} +} + +\newglossaryentry{capability bounds} +{ + name=capability bounds, + description={Upper and lower bounds, associated with each + \gls{capability}, describing a range of \glspl{address} that may + be \glslink{dereference}{dereferenced} via the capability. + Architecturally, bounds are with respect to the \gls{capability base}, + which provides the lower bound, and \gls{capability length}, which + provides the upper bound when added to the base. + The bounds may be empty, connoting no right to dereference at any + address. + The address of a capability may float outside of the + dereferenceable bounds; with a \gls{compressed capability}, it may not + be possible to represent all possible \glslink{out of + bounds}{out-of-bounds} addresses. + Bounds may be manipulated subject to \gls{capability monotonicity} + using \gls{capability-based instructions}} +} + +\newglossaryentry{capability length} +{ + name=capability length, + description={The distance between the lower and upper \gls{capability + bounds}} +} + +\newglossaryentry{capability monotonicity} +{ + name=capability monotonicity, + description={Capability monotonicity is a property of the instruction set + that any requested manipulation of a \gls{capability}, whether in a + \gls{capability register} or in memory, either leads to strictly + non-increasing rights, clearing of the \gls{capability tag}, or a + hardware exception. + \knnote{I presume that the ``rights'' of a capability are + determined by its permissions and its bounds, but not by its + sealedness. In other words, increasing the permissions or bounds + of a capability would increase its rights, but unsealing a + capability would not increase its right. If this is correct, + perhaps it could help to explicitly state this here.} + Controlled violation of monotonicity can be achieved via the exception + delivery mechanism, which grants rights to additional capability + register, and also by the \gls{CInvoke} instruction, which may + unseal (and jump to) suitably checked \glspl{sealed + capability}. + \knnote{The exception delivery mechanism and the CCall instruction + do not violate monotonicity, since they do not increase the rights of + any capability. They do violate the monotonicity of the set of + reachable rights (see \ref{sec:model-monotonicity}), because an + exception makes a capability reachable that might not have been + reachable before (namely the KCC) and the CCall instruction + unseals capabilities without needing a capability that has the + authority to unseal them. Perhaps it would be worth creating a + glossary entry for the set of reachable rights, and mention that + this set is monotonic as long as no exceptions are raised or + CCalls are executed.}} +} + +\newglossaryentry{capability object type} +{ + name=capability object type, + description={In addition to \glslink{fat pointer}{fat-pointer} metadata such + as \gls{capability bounds} and \gls{capability permissions}, \glspl{capability} also contain an integer object type. + The object type space is partitioned into a range of non-reserved and + \gls{reserved capability object type} types. + The \glspl{reserved capability object type} are hardware-interpreted and + include \glspl{unsealed capability} or \glspl{sealed entry capability}. + If the object type is one of the non-\glspl{reserved capability object type}, + the capability is a \gls{sealed capability with an object type}. + For \glspl{sealed capability with an object type}, the object type is set during a + sealing operation to the \gls{address} of the \gls{sealing capability}. + Object types can be used to link a sealed \gls{code capability} and a + sealed \gls{data capability} when used with \gls{CInvoke} to implement a + software object model or to implement software-defined tokens of authority} +} + +\newglossaryentry{capability offset} +{ + name=capability offset, + description={The distance between \gls{capability base} and the + \gls{address} accessed when the \gls{capability} is used as a \gls{pointer}} +} + +\newglossaryentry{capability permissions} +{ + name=capability permissions, + description={A bitmask, associated with each \gls{capability}, + describing a set of ISA- or software-defined operations that may be + performed via the capability. + ISA-defined permissions include load data, store data, instruction fetch, + load capability, and store capability. + Permissions may be manipulated subject to \gls{capability monotonicity} + using \gls{capability-based instructions}} +} + +\newglossaryentry{capability provenance} +{ + name=capability provenance, + description={ +% The property that, following manipulation, a \gls{capability} +% remains valid for use only if it is derived from another valid capability +% using a valid capability operation. +% Provenance is implemented using a \gls{capability tag} combined with +% \gls{capability monotonicity}, and will be preserved whether a +% capability is held in a \gls{capability register} or \gls{tagged memory}, +% subject to suitable use of \gls{capability-based instructions} +The property that a valid-for-use \gls{capability} can only be + constructed by deriving it from another valid capability + using a valid capability operation. +% PS: not totally clear what a ``valid capability operation'' is. An +% execution of a capability instruction that doesn't raise an exception? + Provenance is implemented using a \gls{capability tag} combined with + \gls{capability monotonicity}, +% PS: the text (both previous version and mine) defines provenance as +% a property of the architecture, not ``the provenance of a +% capability'' as the source capability or derivation chain, so we +% can't say ``will be preserved'' like the text did. +% Maybe we should define that more explicit notion of provenance, and +% replace this glossary entry with one for ``capability provenance +% preservation'', but I've not for now. +irrespective of +% +whether a + capability is held in a \gls{capability register} or \gls{tagged memory}} +% PS: surely ``capability provenance'' should hold universally, not only +% ``subject to suitable use of \gls{capability-based instructions''? +} + +\newglossaryentry{capability register} +{ + name=capability register, + description={A capability register is an architectural register able to hold + a \gls{capability} including its \gls{capability tag}, \gls{address}, + other \glslink{fat pointer}{fat-pointer} metadata such as + its \gls{capability bounds} and \gls{capability permissions}, and optional + \gls{capability object type}. + Capability registers may be held in a \gls{capability register file}, a + \gls{merged register file}, or be a \gls{special capability register} + accessed by dedicated instructions. + A capability register might be a dedicated register intended primarily for + capability-related operations (e.g., the capability registers described + in \gls{CHERI-MIPS}), or a general-purpose integer + register that has been extended with capability metadata (such as the + \gls{program-counter capability}, or the capability registers described in + \gls{CHERI-RISC-V} when using a merged register file). + Capability registers must be used to retain tag bits on capabilities + transiting through memory, as only \gls{capability-based instructions} + enforce \gls{capability provenance} and \gls{capability monotonicity}} +} + +\newglossaryentry{capability register file} +{ + name=capability register file, + description={The capability register file is a register file dedicated to + holding general-purpose \glspl{capability}, in contrast to a \gls{merged + register file}, in which general-purpose integer registers are extended to + be able to hold tagged capabilities. + Some general-purpose capability registers have well-known conventions for + their use in software, including the \gls{return capability} and the + \gls{stack capability}} +} + +\newglossaryentry{capability tag} +{ + name=capability tag, + description={A capability tag is a 1-bit integrity tag associated with each + \gls{capability register}, and also with each capability-sized, + capability-aligned location in memory. + If the tag is set, the \gls{capability} is valid and can be + \glslink{dereference}{dereferenced} via the ISA. + If the tag is clear, then the capability is invalid and cannot be + dereferenced via the ISA. + Tags are preserved +by ISA +operations that conform to \gls{capability + provenance} and \gls{capability monotonicity} rules -- for example, + that any attempted modification of \gls{capability bounds} leads to + non-increasing bounds, +%was ``writes'', not ``bounds'' - presume just a typo? + and that in-memory capabilities are written only + via capability stores, not data stores -- otherwise, tags are cleared} +% +% Subject to these constraints, tags will be preserved by +% \gls{capability-based instructions} +} + +\newglossaryentry{capability validity} +{ + name=capability validity, + description={A \gls{capability} is valid if its \gls{capability tag} + is set, which permits use of the capability subject to its + \gls{capability bounds}, \gls{capability permissions}, and so on. + Attempts to \gls{dereference} a capability without a tag set will lead + to a hardware exception} +} + +\newglossaryentry{capability-based instructions} +{ + name=capability-based instructions, + description={These instructions accept capabilities as operands, allowing + capabilities to be loaded from and stored memory, manipulated subject to + \gls{capability provenance} and \gls{capability monotonicity} rules, + and used for a variety of operations such as loading and storing data and + capabilities, as branch targets, and to retrieve and manipulate capability + fields -- subject to \gls{capability permissions}} +} + +\longnewglossaryentry{CInvoke} +{ + name=CInvoke +} +{ + The \insnref{CInvoke} instruction is a source of controlled + non-monotonicity in the \gls{CHERI-MIPS} and \gls{CHERI-RISC-V} ISAs. +\psnote{See Kyndylan's note for capability monotonicity} + It can directly enter any userspace domain described by a pair + of sealed capabilities with the \emph{Permit\_CInvoke} permission set. + In particular, it can + safely enter userspace domain-transition code + described by the sealed \gls{code capability} while also unsealing + the sealed \gls{data capability}. + The sealed operand \glspl{capability register} + are checked for suitable properties and correspondence, and the userspace + domain-transition routine can store any return information, perform further error + checking, and so on. +} + +\newglossaryentry{CHERI Concentrate} +{ + name=CHERI Concentrate, + description={CHERI Concentrate is a specific \gls{compressed capability} + format that represents a 64-bit \gls{address} with full precision, and + \gls{capability bounds} relative to that address with reduced precision. + Bounds have a floating-point representation, requiring that as the size of + a bounded object increases, greater alignment of its \gls{capability base} + and \gls{capability length} are required. + CHERI Concentrate is the successor compression format to \gls{CHERI-128}} +} + +\newglossaryentry{CHERI-128} +{ + name=CHERI-128, + description={CHERI-128 is a specific \gls{compressed capability} format that + represents a 64-bit \gls{address} with full precision, and + \gls{capability bounds} relative to that address with reduced precision. + Bounds have a floating-point representation, requiring that as the size of + a bounded object increases, greater alignment of its \gls{capability base} + and \gls{capability length} are required. + CHERI-128 has been replaced with \gls{CHERI Concentrate}} +} + +\newglossaryentry{CHERI-MIPS} +{ + name=CHERI-MIPS, + description={An application of the CHERI protection model to the 64-bit MIPS + ISA} +} + +\newglossaryentry{CHERI-RISC-V} +{ + name=CHERI-RISC-V, + description={An application of the CHERI protection model to the RISC-V ISA} +} + +\newglossaryentry{CHERI-x86-64} +{ + name=CHERI-x86-64, + description={An application of the CHERI protection model to the x86-64 ISA} +} + +\newglossaryentry{code capability} +{ + name=code capability, + plural=code capabilities, + description={A \gls{capability} whose \gls{capability permissions} have been + configured to permit instruction fetch (i.e., execute) rights; typically, + write permission will not be granted via an executable capability, in + contrast to a \gls{data capability}. + Code capabilities are used to implement \gls{control-flow robustness} by + constraining the available branch and jump targets} +} + +\newglossaryentry{compressed capability} +{ + name=compressed capability, + plural=compressed capabilities, + description={A \gls{capability} whose \gls{capability bounds} are + compressed with respect to its \gls{address}, allowing its + in-memory footprint to be reduced -- e.g., to 128 bits, rather than the + roughly + architectural 256 bits visible to the instruction set when a capability + is loaded into a register file. + Certain architecturally valid \glslink{out of bounds}{out-of-bounds} + addresses may not be \glslink{representable + capability}{representable} with capability compression; operations leading + to \glslink{unrepresentable capability}{unrepresentable capabilities} + will clear the \gls{capability tag} or throw an exception in order to + ensure continuing \gls{capability monotonicity}. + \gls{CHERI-128} and \gls{CHERI Concentrate} are specific compressed + capability models that select particular points in the tradeoff space + around in-memory capability size, bounds alignment requirements, and + representability} +} + +\newglossaryentry{control-flow robustness} +{ + name=control-flow robustness, + description={The use of \glspl{code capability} to constrain the set of + available branch and jump targets for executing code, such that the + potential for attacker manipulation of the \gls{program-counter + capability} to simulate injection of arbitrary code is severely + constrained; a form of \gls{vulnerability mitigation} implemented via + the \gls{principle of least privilege}} +} + +\newglossaryentry{data capability} +{ + name=data capability, + plural=data capabilities, + description={A \gls{capability} whose \gls{capability permissions} have been + configured to permit data load and store, but not instruction fetch (i.e., + execute) rights; in contrast to a \gls{code capability}} +} + +\newglossaryentry{default data capability} +{ + name=default data capability (\DDC{}), + description={A \gls{special capability register} constraining + \glslink{legacy instructions}{legacy} non-\gls{capability-based + instructions} that load and store data without awareness of the capability + model. + Any attempts to load and store will be relocated relative to the default + data capability's \gls{capability base} and \gls{capability offset}, and + controlled by its \gls{capability bounds} and \gls{capability + permissions}. + Use of the default data capability violates the \gls{principle of + intentional use}, but permits compatibility with legacy software. + A suitably configured default data capability will prevent the use of + non-capability-based load and store instructions} +} + +\newglossaryentry{dereference} +{ + name=dereference, + description={Dereferencing a \gls{address} means that it is the + target address for a load, store, or instruction fetch. + A \gls{capability} may be dereferenced only subject to it being valid + -- i.e., that its \gls{capability tag} is present -- and is also subject + to appropriate checks of its \gls{capability bounds}, \gls{capability permissions}, and + so on. + Dereference may occur as a result of explicit use of a capability via + \gls{capability-based instructions}, or implicitly as a result of the + \gls{program-counter capability} or \gls{default data capability}} +} + +\newglossaryentry{exception program-counter capability} +{ + name=exception program-counter capability (\EPCC{}), + description={A \gls{special capability register} into which the running + \gls{program-counter capability} will be moved into on an exception, and + whose value will be moved back into the program-counter capability on + exception return} +} + +\newglossaryentry{fat pointer} +{ + name=fat pointer, + description={A \gls{pointer} (\gls{address}) that has been extended + with additional metadata such as \gls{capability bounds} and + \gls{capability permissions}. + In conventional fat-pointer designs, fat pointers to not have a notion of + sealing (i.g., as in \glspl{sealed capability} and \glspl{unsealed + capability}), nor rules implementing \gls{capability provenance} and + \gls{capability monotonicity}} +} + +\newglossaryentry{fine-grained memory protection} +{ + name=fine-grained memory protection, + description={The granular description of available code and data in which + \gls{capability bounds} and \gls{capability permissions} are made as + small as possible, in order to limit the potential effects of software + bugs and vulnerabilities. + This approach applies both to \glspl{code capability} and \glspl{data + capability}, offering effective \gls{vulnerability mitigation} via + techniques such as \gls{control-flow robustness}, as well as supporting + higher-level mitigation techniques such as \gls{software + compartmentalization}. + Fine-grained memory protection will typically be driven by the goal of + implementing the \gls{principle of least privilege}} +} + +\newglossaryentry{hybrid capability model} +{ + name=hybrid capability model, + description={A \gls{capability} model in which not all interfaces to use or + manipulate capabilities conform to the \gls{principle of intentional + use}, such that legacy software is able to execute around, or within, + capability-constrained environments, as well as other features required + to improve compatibility with conventional software designs permitting + easier incremental adoption of a capability-system model. + In CHERI, composition of the capability-system model with the conventional + Memory Management Unit (MMU), the support for \gls{legacy instructions} + via the \gls{program-counter capability} and \gls{default data + capability}, and strong compatibility with the C-language \gls{pointer} + model, all constitute hybrid aspects of its design, in comparison to a + more pure capability-system model that might elide those behaviors at a + cost to compatibility and adoptability} +} + +\newglossaryentry{principle of intentional use} +{ + name=principle of intentional use, + description={A design principle in capability systems in which rights are + always explicitly, rather than implicitly exercised. + This arises in the CHERI instruction set through explicit \gls{capability} + operands to \gls{capability-based instructions}, which contributes to the + effectiveness of \gls{fine-grained memory protection} and + \gls{control-flow robustness}. + When applied, the principle limits not just the rights available in the + presence of a software vulnerability, but the extent to which software can + be manipulated into using rights in an unintended (and exploitable) + manner} +} + +\newglossaryentry{invoked data capability} +{ + name=invoked data capability (\IDC{}), + plural=invoked data capabilities, + description={A capability register reserved by convention to hold the + unsealed \gls{data capability} on the callee side of \gls{CInvoke}. + Typically, for the caller side, this will point at a frame on the caller + stack sufficient to safely restore any caller state. + On the callee side, the invoked data capability will be a data capability + describing the object's internal state} +} + +\newglossaryentry{kernel code capability} +{ + name=kernel code capability (\KCC{}), + description={A \gls{special capability register} reserved to hold a + privileged \gls{code capability} for use by the kernel during exception + handling. + This value will be installed in the \gls{program-counter capability} on + exception entry, with the previous value of the program-counter + capability stored in the \gls{exception program-counter capability}} +} + +\newglossaryentry{kernel data capability} +{ + name=kernel data capability (\KDC{}), + description={A \gls{special capability register} reserved to hold a + privileged \gls{data capability} for use by the kernel during exception + handling. + Typically, this will refer either to the data segment for a microkernel + intended to field exceptions, or for the full kernel. + Kernels compiled to primarily use \gls{legacy instructions} might install + this in the \gls{default data capability} for the duration of kernel + execution. + Use of this register is controlled by \gls{capability permissions} on + the currently executing \gls{program-counter capability}} +} + +\newglossaryentry{kernel reserved capabilities} +{ + name=kernel reserved capabilities, + description={These \glspl{capability}, modeled on the MIPS kernel reserved + registers, are set aside for use by a \gls{CHERI-MIPS} operating-system + kernel in + exception handling -- in particular, in allowing userspace registers to + be saved so that the kernel context can be installed. + As with the MIPS registers, the userspace ABI is not able to use + capability registers set aside for kernel use; unlike the MIPS registers, + the kernel reserved capabilities are available for use in the ISA only + with a suitably authorized \gls{program-counter capability} installed. + Due to a different exception-handling model in \gls{CHERI-RISC-V}, that + ISA does not have kernel reserved capabilities} +} + +\newglossaryentry{legacy instructions} +{ + name=legacy instructions, + description={Legacy instructions are those that accept integer addresses, + rather than capabilities, as their operands, requiring use of the + \gls{default data capability} for loads and stores, or that explicitly set + the program counter to a address, rather than doing setting the + \gls{program-counter capability}. + These instructions allow legacy binaries (those compiled without CHERI + awareness) to execute, but only without the benefits of + \gls{fine-grained memory protection}, granular \gls{control-flow + robustness}, or more efficient \gls{software compartmentalization}. + While still constrained, these instructions do not conform to the + \gls{principle of intentional use}} +} + +\newglossaryentry{merged register file} +{ + name=merged register file, + description={A single general-purpose register file able to hold both + integer and tagged \gls{capability} values. + In \gls{CHERI-MIPS}, a dedicated \gls{capability register file} is used, + separate from the general-purpose integer register file. + In \gls{CHERI-RISC-V} and \gls{Morello}, a merged register file is supported, reducing the + amount of control logic required for a separate register file} +} + +\newglossaryentry{Morello} +{ + name=Morello, + description={An application of the CHERI protection model to the ARMv8-A architecture} +} + +\newglossaryentry{out of bounds} +{ + name=out of bounds, + description={When a \gls{capability}'s \gls{capability offset} falls outside + of its \gls{capability bounds}, it is out of bounds, and cannot be + \glslink{dereference}{dereferenced}. + Even if a capability's offset is in bounds, the width of a data access may + cause a load, store, or instruction fetch to fall out of bounds, or the + further offset introduced via a register index or immediate operand to an + instruction. +% With 256-bit capabilities, all out-of-bounds pointers are +% \glspl{representable capability}. + With \glspl{compressed capability}, if an instruction shifts the offset + too far out of bounds, this may result in an \gls{unrepresentable + capability}, leading to the \gls{capability tag} being cleared, or an + exception being thrown} +} + +\newglossaryentry{physical address} +{ + name=physical address, + plural=physical addresses, + description={An \gls{address} that is passed directly to the memory + hierarchy without \glslink{virtual address}{virtual-address} translation. + In \gls{CHERI-MIPS}, \glspl{capability} contain only virtual addresses. + In \gls{CHERI-RISC-V}, \glspl{capability} addresses may be interpreted as + physical addresses in Machine Mode} +} + +\newglossaryentry{pointer} +{ + name=pointer, + description={A pointer is a language-level reference to a memory object. + In conventional ISAs, a pointer is typically represented as an + \gls{address}. + In CHERI, pointers can be represented either as an address + indirected via the \gls{default data capability} or \gls{program-counter + capability}, or as a \gls{capability}. + In the latter cases, its integrity and \gls{capability provenance} are + protected by the \gls{capability tag}, and its use is limited by + \gls{capability bounds} and \gls{capability permissions}. + \Gls{capability-based instructions} preserve the tag as required across + both \glspl{capability register} and \gls{tagged memory}, and also + enforce \gls{capability monotonicity}: legitimate operations on the + pointer cannot broaden the set of rights described by the capability} +} + +\newglossaryentry{principle of least privilege} +{ + name=principle of least privilege, + description={A principle of software design in which the set of rights + available to running code is minimized to only those required for it to + function, often with the aim of \gls{vulnerability mitigation}. + In CHERI, this concept applies via fine-grained memory protection for + both data and code, and also higher-level \gls{software + compartmentalization}} +} + +\newglossaryentry{program-counter capability} +{ + name=program-counter capability (\PCC{}), + description={A \gls{special capability register} that extends the existing + program counter to include + \gls{capability} metadata such as a \gls{capability tag}, \gls{capability + bounds}, and \gls{capability permissions}. + The program-counter capability ensures that instruction fetch occurs only + subject to capability protections. + When an exception fires, the value of the program-counter capability will + be moved to the \gls{exception program-counter capability}, and the value + of the \gls{kernel data capability} moved into the program-counter + capability. + On exception return, the value of the exception program-counter capability + will be moved into the program-counter capability} +} + +\newglossaryentry{representable capability} +{ + name=representable capability, + plural=representable capabilities, + description={A \gls{compressed capability} whose \gls{capability offset} + is representable with respect to its \gls{capability bounds}; this + does not imply that the offset is ``within bounds'', but does require + that it be within some broader window around the bounds} +} + +\newglossaryentry{reserved capability object type} +{ + name=reserved capability object type, + plural=reserved capability object types, + description={Certain \glspl{capability object type} are not available for software use and instead have hardware-defined semantics. + On \gls{CHERI-MIPS} and \gls{CHERI-RISC-V}, all negative \glspl{capability object type} are + reserved: \glspl{unsealed capability} use the value $2^{64}-1$ and \glspl{sealed entry capability} + have an object type of $2^{64}-2$. + The remaining \glspl{capability object type} are used for \glspl{sealed capability with an object type}} +} + +\newglossaryentry{return capability} +{ + name=return capability, + plural=return capabilities, + description={A \gls{capability} designated as the destination for the + return address when using a capability jump-and-link instruction. + A degree of \gls{control-flow robustness} is provided due to + \gls{capability bounds}, \gls{capability permissions}, and the + \gls{capability tag} on the resulting capability, which limits sites that + may be jumped back to using the return capability} +} + +\newglossaryentry{sealed capability} +{ + name=sealed capability, + plural=sealed capabilities, + description={A sealed \gls{capability} is one whose \gls{capability object type} + is not equal to the unsealed object type ($2^{64}-1$ for \gls{CHERI-MIPS} and \gls{CHERI-RISC-V}). + A sealed capability's \gls{address}, \gls{capability bounds}, + \gls{capability permissions}, and other fields are immutable -- i.e., + cannot be modified using \gls{capability-based instructions}. + A sealed capability cannot be directly \glslink{dereference}{dereferenced} + using the instruction set, and must be unsealed before it can be used. + This can be used to implement non-monotonic domain transition, as a + sealed capability may carry rights not otherwise present in the + \gls{capability register file}. + Two types exist: \glspl{sealed capability with an object type} and + \glspl{sealed entry capability}. + They have different properties catering to different use cases} +} + +\newglossaryentry{sealed capability with an object type} +{ + name=sealed capability with an object type, + plural=sealed capabilities with object types, + description={A \gls{sealed capability} whose \gls{capability object type} + is not one of the \glspl{reserved capability object type}. + These sealed capability have a \gls{capability object type} derived + from their \glspl{sealing capability}'s \gls{address}. + CHERI's sealing feature allows capabilities to be used to describe + software-defined objects, permitting implementation of encapsulation. + Unsealing can be performed using the \gls{CInvoke} instruction, or + using the \insnref{CUnseal} instruction combined with a suitable + \gls{sealing capability}. + Sealed capabilities with object types provide the necessary architectural + encapsulation support to efficiently implement fine-grained + compartmentalization using an object-oriented model} +} + +\newglossaryentry{sealed entry capability} +{ + name=sealed entry capability, + plural=sealed entry capabilities, + description={A sealed entry \gls{capability} (also known as + \gls{sentry capability}) is a \gls{sealed capability} + whose \gls{capability object type} is set to the sentry \gls{reserved capability object type} ($2^{64}-2$ for \gls{CHERI-MIPS} and \gls{CHERI-RISC-V}). + Sealed entry capabilities are commonly referred to as \glspl{sentry + capability}. + Sealed entry capabilities are do not support linking sealed code and + data capabilities, unlike \glspl{sealed capability with an object type}. + A sealed entry capability is unsealed by jumping to it using a regular + capability jump instruction} +} + +\newglossaryentry{sealing capability} +{ + name=sealing capability, + plural=sealing capabilities, + description={A sealing capability is one with the \cappermSeal + permission, allowing it to be used to create \glspl{sealed capability} + using a \gls{capability object type} set to the sealing capability's + \gls{address}, and subject to its bounds} +} + +\newglossaryentry{sentry capability} +{ + name=sentry capability, + plural=sentry capabilities, + description={Sentry capability is a convenient shorthand for a + \gls{sealed entry capability}} +} + +\newglossaryentry{software compartmentalization} +{ + name=software compartmentalization, + description={The configuration of \glspl{code capability} and \glspl{data + capability} available via the \gls{capability register file} or + \gls{merged register file}, accessible \glspl{special capability + register}, and \gls{tagged memory} such that software components can be + isolated from one another, enabling \gls{vulnerability mitigation} via the + application of the \gls{principle of least privilege} at the application + layer. + One approach to implementing software compartmentalization on CHERI is to + use \gls{CInvoke} to jump into sealed code + and data capabilities describing a trusted intermediary and destination + protection domain} +} + +\newglossaryentry{stack capability} +{ + name=stack capability, + plural=stack capabilities, + description={A \gls{capability} referring to the current stack, whose + \gls{capability bounds} are suitably configured to allow access only to + the remaining stack available to allocate at a given point in execution} +} + +\newglossaryentry{special capability register} +{ + name=special capability register, + description={Special capability registers have special architectural + meanings, and include the \gls{program-counter capability}, the + \gls{default data capability}, the \gls{exception program-counter + capability}, the \gls{kernel code capability}, and the \gls{kernel data + capability}. + Not all registers are accessible at all times; for example, some may be + available only in certain rings, or when \PCC{} has the + Access\_System\_Registers permission set} +} + +\newglossaryentry{tagged memory} +{ + name=tagged memory, + description={Tagged memory associates a 1-bit \gls{capability tag} with + each \gls{capability}-aligned, capability-sized word in memory. + \Gls{capability-based instructions} that load and store capabilities + maintain the tag as the capability transits between memory and the + \gls{capability register file}, tracking \gls{capability provenance}. + When data stores (i.e., stores of non-capabilities), the tag on the + memory location will be atomically cleared, ensuring the integrity of + in-memory capabilities} +} + +\newglossaryentry{trusted computing base} +{ + name=Trusted Computing Base (TCB), + description={The subset of hardware and software that is critical to the + security of a system; + in secure system designs, there is often a goal to minimize the size of + the TCB in order to minimize the opportunity for exploitable software + vulnerabilities} +} + +\newglossaryentry{trusted stack} +{ + name=trusted stack, + description={Some software-defined object-capability models offer strong + call-return semantics -- i.e., that if a return is issued by an invoked + object, or an uncaught exception is generated, then the appropriate caller + will be returned to -- exactly once. + This can be implemented via a trusted stack, maintained by the software + \gls{trusted computing base} via one or more handlers invoked by \gls{CInvoke}. + A trusted stack for an object-oriented model will likely maintain at least + the caller's \gls{program-counter capability} and \gls{invoked data + capability} to be restored on return} +} + +\newglossaryentry{unrepresentable capability} +{ + name=unrepresentable capability, + plural=unrepresentable capabilities, + description={A \gls{compressed capability} whose \gls{capability offset} is + sufficiently outside of its \gls{capability bounds} that the combined + \gls{pointer} value and bounds cannot be represented in the compressed format; + constructing an unrepresentable capability will lead to the tag being + cleared (and information loss) or an exception, rather than a violation + of \gls{capability provenance} or \gls{capability monotonicity}} +} + +\newglossaryentry{unsealed capability} +{ + name=unsealed capability, + plural=unsealed capabilities, + description={An unsealed \gls{capability} is one whose \gls{capability object type} + is the unsealed object type ($2^{64}-1$ for \gls{CHERI-MIPS} and \gls{CHERI-RISC-V}). + Its remaining capability fields are mutable, subject to \gls{capability + provenance} and \gls{capability monotonicity} rules. + These capabilities have hardware-defined behaviors -- i.e., subject to + \gls{capability bounds}, \gls{capability permissions}, and so on, + can be \glslink{dereference}{dereferenced}} +} + +\newglossaryentry{virtual address} +{ + name=virtual address, + plural=virtual addresses, + description={An integer \gls{address} translated by the Memory Management + Unit (MMU) into a \gls{physical address} for the purposes of load, store, + and instruction fetch. + \Glspl{capability} embed an address, represented in the instruction + set as the sum of the \gls{capability base} and \gls{capability offset}, + as well as \gls{capability bounds} relative to the address. + The integer addresses passed to \glslink{legacy instructions}{legacy load + and store instructions} that would previously have been interpreted as + virtual addresses are, with CHERI, transformed (and checked) using the + \gls{default data capability}. + Similarly, the integer addresses passed to legacy branch and jump + instructions are transformed (and checked) using the \gls{program-counter + capability}. + This in effect introduces a further relocation of legacy addresses prior + to virtual address translation} +} + +\newglossaryentry{vulnerability mitigation} +{ + name=vulnerability mitigation, + description={A set of techniques limiting the effectiveness of the attacker + to exploit a software vulnerability, typically achieved through use of + the \gls{principle of least privilege} to constrain injection of + arbitrary code, control of the \gls{program-counter capability} via + \gls{control-flow robustness} using \glspl{code capability}, minimization of + data rights granted via available \glspl{data capability}, and higher-level + \gls{software compartmentalization}} +} diff --git a/insn-mips/candaddr.tex b/insn-mips/candaddr.tex new file mode 100644 index 00000000..1f0ee67b --- /dev/null +++ b/insn-mips/candaddr.tex @@ -0,0 +1,43 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CAndAddr} +\insnmipslabel{candaddr} +\subsection*{CAndAddr: Mask Address of Capability} + +\subsubsection*{Format} + +CAndAddr cd, cb, rs + +\begin{center} +\cherithreeop[header]{0x24}{cd}{cb}{rs} +\end{center} + +\subsubsection*{Description} + +\emph{cd} is set to \emph{cb} with \emph{cb}.\caddr{} logically ANDed with \emph{rs}. +If the new address causes the capability to become unrepresentable then an untagged capability with address set to the masked address is returned. + +\subsubsection*{Semantics} + +\sailMIPScode{CAndAddr} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cb}.\ctag{} is set and \emph{cb} is sealed. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item This instruction may be appropriate for use cases in which C is masking pointers +before use, for example when the lower bits are used to store additional metadata in a pointer with known alignment. +\item This instructions also allows more efficient aligning down (and up) of capabilities. In C source code this will +almost always be a compile time constant so we might discover that we need a version of this instruction that +takes an immediate operand. Using a 5-bit immediate field we could encode align-down/align-up masks from +$2$ to $2^{32}$. +\item This instruction is also useful in order to create precisely representable bounds for heap and stack allocations. +\end{itemize} diff --git a/insn-mips/candperm.tex b/insn-mips/candperm.tex new file mode 100644 index 00000000..1f94d096 --- /dev/null +++ b/insn-mips/candperm.tex @@ -0,0 +1,37 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CAndPerm} +\insnmipslabel{candperm} +\subsection*{CAndPerm: Restrict Permissions} + +\subsubsection*{Format} + +CAndPerm cd, cb, rt + +\begin{center} +\cherithreeop[header]{0xd}{cd}{cs}{rt} +\end{center} + +\subsubsection*{Description} + +Capability register \emph{cd} is replaced with the contents of capability +register \emph{cb} with the \cperms{} field set to the bitwise and of +its previous value and bits 0 to +\hyperref[table:pseudocode-constants]{\emph{last\_hperm}} of integer register \emph{rt} +and the \cuperms{} field set to the bitwise and of its previous value +and bits \hyperref[table:pseudocode-constants]{\emph{first\_uperm}} to +\hyperref[table:pseudocode-constants]{\emph{last\_uperm}} of \emph{rd}. + +\subsubsection*{Semantics} +\sailMIPScode{CAndPerm} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\cchecktag{} +\item +\emph{cb} is sealed. +\end{itemize} diff --git a/insn-mips/cbez.tex b/insn-mips/cbez.tex new file mode 100644 index 00000000..8707ee37 --- /dev/null +++ b/insn-mips/cbez.tex @@ -0,0 +1,67 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CBEZ / CBNZ} +\insnmipslabel{cbez} +\subsection*{CBEZ / CBNZ: Branch if Capability is / is Not NULL} + +\subsubsection*{Format} + +CBEZ cb, offset + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x11} +\bitbox{5}{cb} +\bitbox{16}{offset} +\end{bytefield} +\end{center} +\phantomsection +\insnmipslabel{cbnz} +CBNZ cb, offset + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x12} +\bitbox{5}{cb} +\bitbox{16}{offset} +\end{bytefield} +\end{center} + +\subsubsection*{Description} + +Sets the \PC{} to \PC{} $+$ 4*{\em offset} $+$ 4, where {\em offset} is sign +extended, depending on whether \emph{cb} is equal to the NULL capability. + +The instruction following the branch, in the delay slot, is executed before +branching. + +\subsubsection*{Semantics} + +\sailMIPScode{CBZ} + +\subsubsection*{Notes} + +\begin{itemize} +\item +In the above Sail code {\tt notzero} is false for \insnmipsref{CBEZ} and true +for \insnmipsref{CBNZ} thus inverting the sense of the +comparison (via exclusive-or) for the latter. +\item +Like all MIPS branch instructions, \insnmipsref{CBEZ} and +\insnmipsref{CBNZ} have a branch delay slot. The instruction after +it will always be executed, regardless of whether the branch is taken +or not. +\item +This instruction is intended to resemble the conditional branch instructions +from the MIPS ISA. In particular, the shift left of the offset by 2 bits and +adding 4 is the same as MIPS conditional branches. +\item +Contrary to previous versions of the CHERI architecture the bounds check on +\PCC{} is performed during execution of the branch so an out-of-bounds target +will result in an exception. In the Sail code this check occurs in the +\lstinline{execute_branch} function. +\end{itemize} diff --git a/insn-mips/cbts.tex b/insn-mips/cbts.tex new file mode 100644 index 00000000..03ce5f30 --- /dev/null +++ b/insn-mips/cbts.tex @@ -0,0 +1,64 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CBTS / CBTU} +\insnmipslabel{cbts} +\subsection*{CBTS / CBTU: Branch if Capability Tag is Set / Unset} + +\subsubsection*{Format} + +CBTS cb, offset + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x0a} +\bitbox{5}{cb} +\bitbox{16}{offset} +\end{bytefield} +\end{center} +\phantomsection +\insnmipslabel{cbtu} +CBTU cb, offset + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x09} +\bitbox{5}{cb} +\bitbox{16}{offset} +\end{bytefield} +\end{center} + +\subsubsection*{Description} + +Sets the \PC{} to \PC{} $+$ 4*{\em offset} $+$ 4, where {\em offset} is sign +extended, depending on whether \emph{cb.tag} is set. +The instruction following the branch, in the delay slot, is executed before +branching. + +\subsubsection*{Semantics} + +\sailMIPScode{CBX} + +\subsubsection*{Notes} + +\begin{itemize} +\item +In the above Sail code {\tt notset}, is false for \insnmipsref{CBTS} and true for \insnmipsref{CBTU} thus inverting the condition (via exclusive-or) for the latter. +\item +Like all MIPS branch instructions, \insnmipsref{CBTS} and +\insnmipsref{CBTU} have a branch delay slot. The instruction after +it will always be executed, regardless of whether the branch is taken +or not. +\item +This instruction is intended to resemble the conditional branch instructions +from the MIPS ISA. In particular, the shift left of the offset by 2 bits and +adding 4 is the same as MIPS conditional branches. +\item +Contrary to previous versions of the CHERI architecture the bounds check on +\PCC{} is performed during execution of the branch so an out-of-bounds target +will result in an exception. In the Sail code this check occurs in the +\lstinline{execute_branch} function. +\end{itemize} diff --git a/insn-mips/cbuildcap.tex b/insn-mips/cbuildcap.tex new file mode 100644 index 00000000..e4318ab3 --- /dev/null +++ b/insn-mips/cbuildcap.tex @@ -0,0 +1,182 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CBuildCap} +\insnmipslabel{cbuildcap} +\subsection*{CBuildCap: Import a Capability} + +\subsubsection*{Format} + +CBuildCap cd, cb, ct + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x0} +\bitbox{5}{cd} +\bitbox{5}{cb} +\bitbox{5}{ct} +\bitbox{6}{0x1d} +\end{bytefield} +\end{center} + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Description} + +\insnmipsref{CBuildCap} attempts to interpret the contents of \emph{ct} +as if it were a valid capability (even though \emph{ct}.\ctag{} is not +required to be set and so \emph{ct} might contain any bit pattern) and +extracts its \cbase{}, \clength{}, \coffset{}, \cperms{} and \cuperms{} +fields. +If the bounds of \emph{ct} cannot be extracted because the bit +pattern in \emph{ct} does not correspond to a permitted value of the capability +type (e.g. \clength{} is negative), then an exception is raised. + +If the extracted bounds of \emph{ct} are within the bounds of \emph{cb}, and +the permissions of \emph{ct} are within the permissions of \emph{cb}, then +\emph{cd} is set equal to \emph{cb} with the \cbase{}, \clength{}, +\coffset{}, \cperms{} and \cuperms{} of \emph{ct}. + +If \emph{ct} is sealed, this instruction does not copy its \cotype{} into \emph{cd}. With +compressed capabilities, a different representation may be used for the bounds +of sealed and unsealed capabilities. If \emph{ct} is sealed, +\insnmipsref{CBuildCap} will change the representation of the bounds so +that their values are preserved. + +Because \emph{ct}.\ctag{} is not required to be set, there is no guarantee +that the bounds of \emph{ct} will be in canonical form. +\insnmipsref{CBuildCap} may convert the bounds into canonical form rather than +simply copying their bit representation. + +\insnmipsref{CBuildCap} does not copy the fields of \emph{ct} that are +reserved for future use. + +\insnmipsref{CBuildCap} can be used to set the tag bit on a capability (e.g., +one whose non-tag contents has previously been swapped to disk and than +reloaded into memory, or during dynamic linking as untagged capability values +are relocated and tagged after being loaded from a file). +This provides both improved efficiency relative to manual rederivation of the +tagged capability via a series of instructions, and also provides improved +architectural abstraction by avoiding embedding the rederivation sequence in +code. + +\subsubsection*{Semantics} +\sailMIPScode{CBuildCap} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cd}, \emph{cb} or \emph{ct} is a reserved register and \PCC.\cperms{} does +not grant \emph{Permit\_Access\_System\_Registers}. +\item +\emph{cb}.\ctag{} is not set. +\item +\emph{cb} is sealed. +\item +The bounds of \emph{ct} are outside the bounds of \emph{cb}. +\item +The values of \cbase{} and \clength{} found in \emph{ct} are not within the +range permitted for a capability with its \ctag{} bit set. +\item +\emph{ct}.\cperms{} grants a permission that is not granted by +\emph{cb}.\cperms{}. +\item +\emph{ct}.\cuperms{} grants a permission that is not granted by +\emph{cb}.\cuperms{}. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +This instruction acts both as an optimization, and to provide architectural +abstraction in the face of future change to the capability model. +A similar effect, albeit with reduced abstraction, could be achieved by +using \insnmipsref{CGetBase}, \insnmipsref{CGetLen} and +\insnmipsref{CGetPerm} to query \emph{ct}, and then using +\insnmipsref{CSetBounds} and \insnmipsref{CAndPerm} to set the bounds +and \cperms{} of \emph{cd}. +\item +Despite the description of its intended use above, \insnmipsref{CBuildCap} +does not actually require that \emph{ct} have an unset tag. +\item +\emph{ct} might be a sealed capability that has had its \ctag{} bit cleared. +In this case (assuming an exception is not raised for another reason), +\emph{cd} will be unsealed and the bit representation of +the \cbase{} and \clength{} fields might be changed to take account of +the differing compressed representations for sealed and unsealed capabilities. +\item +This instruction can not be used to break security properties of the capability +mechanism (such as monotonicity) because \emph{cb} must be a valid capability +and the instruction cannot be used to create a capability that grants rights +that were not granted by \emph{cb}. +\item +As the tag bit on \emph{ct} does not need to be set, there is no guarantee +that the bit pattern in \emph{ct} was created by clearing the tag bit on a +valid capability. It might be an arbitrary bit pattern that was created by +other means. As a result, there is no guarantee that the bit pattern in +\emph{ct} corresponds to the encoding of a valid value of the capability type, +especially when capability compression is in use. Fields might have values outside +of their defined range, and invariants such as \cbase{} $\ge 0$, \cbase{} $+$ +\clength{} $\le 2^{64}$ or \clength{} $\ge 0$ might not be true. In addition, +fields might not be in a canonical (normalized) form. +\insnmipsref{CBuildCap} checks that the \cbase{} and \clength{} fields are +within the permitted range for the type and satisfy the above invariants, +raising a length exception if they are not. If the fields are not in normalized +form, \insnmipsref{CBuildCap} may renormalize them rather than simply +copying the bit pattern from \emph{ct} into \emph{cd}. +\item +The type constraint \emph{cd}.\ctag{} $\implies$ \emph{cd}.\cbase{} $\ge 0$ is +guaranteed to be satisfied +because \emph{cb}.\cbase{} $\ge 0$ and an exception would be raised if +\emph{ct}.\cbase{} $\le$ \emph{cb}.\cbase{}. +\item +The type constraint \emph{cd}.\ctag{} $\implies$ \emph{cd}.\cbase{} $+$ +\emph{cd}.\clength{} $\le 2^{64}$ is guaranteed to be satisfied because this +constraint is true for \emph{cb}, and an exception would be raised if +\emph{ct}.\cbase $+$ \emph{ct}.\clength{} $>$ \emph{cb}.\cbase{} $+$ +\emph{cb}.\clength{}. +\item +Is the value of \emph{cd} guaranteed to be representable? +If \emph{ct} was created by clearing the tag bit on a capability, then its +bounds can be represented exactly and there will be no loss of precision. +If \emph{ct} is sealed, then there is a potential issue that the values +of the bounds that are representable in a sealed capability are not the same as +the range of bounds that are representable in an unsealed capability. We rely +on a property of the existing capability formats that if a value of the bounds +is representable in a sealed capability, then it is also representable in an +unsealed capability. +\item As \insnmipsref{CBuildCap} is not able to restore the seal on a +re-tagged capability, it is intended to be used alongside +\insnmipsref{CCSeal}, which will conditionally seal a capability based on a \cotype{} value +extracted with \insnmipsref{CCopyType}. +These instructions will normally be used in sequence to \textit{(i)} re-tag a +capability with CBuildCap, \textit{(ii)} extract a possible object type from +the untagged value with \insnmipsref{CCopyType}, and \textit{(iii)} +conditionally seal the resulting capability with \insnmipsref{CCSeal}. +\item +The typical use of \insnmipsref{CBuildCap} assumes that there is a single +capability \emph{cb} whose bounds include every capability value that is +expected to be encountered in \emph{ct} (with out of range values being an +error). The following are two examples of situations where this is not the +case, and the sequence of instructions to recreate a capability might need +to decide which capability to use as \emph{cb}: +(a) The operating system has enforced a ``write xor execute'' policy, and +the program attempting to recreate \emph{ct} has a capability with +\emph{Permit\_Write} permission and a capability with \emph{Permit\_Execute} +permission, but does not have a capability with both permissions. +(b) The capability in \emph{ct} might be a capability that authorizes sealing +with the \emph{Permit\_Seal} permission, and the program attempting to +recreate it has a capability for a range of memory addresses and a capability +for a range of \cotype{} values, but does not have a single capability that +includes both ranges. +\end{itemize} + +\mrnote{TO DO: We can solve the problem of multiple authorizing capabilities +if CBuildCap does nothing if the source already has the tag set, or if the +authorizing capability does not grant sufficient rights. Then, you can just +try all of the authorizing capabilties in turn and see if any of them worked.} diff --git a/insn-mips/cchecktag.tex b/insn-mips/cchecktag.tex new file mode 100644 index 00000000..5edd100d --- /dev/null +++ b/insn-mips/cchecktag.tex @@ -0,0 +1,39 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CCheckTag} +\insnmipslabel{cchecktag} +\subsection*{CCheckTag: Raise Exception if Tag is Unset} + +\subsubsection*{Format} + +CCheckTag cs + +\begin{center} +\cherioneop{0x6}{cs} +\end{center} + +\subsubsection*{Description} + +An exception is raised (and the capability cause register set to ``tag +violation'') if \emph{cs}.\ctag{} is not set. + +\subsubsection*{Semantics} +\sailMIPScode{CCheckTag} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cs}.\ctag{} is not set. +\end{itemize} + +\subsubsection{Notes} + +\begin{itemize} +\item +This instruction is intended to support debugging modes for compilers where +an untagged capability may result from an attempted non-monotonic operation, +rather than an exception. +\end{itemize} diff --git a/insn-mips/cclearregs.tex b/insn-mips/cclearregs.tex new file mode 100644 index 00000000..2cfbe907 --- /dev/null +++ b/insn-mips/cclearregs.tex @@ -0,0 +1,92 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CClearRegs} +\insnmipslabel{cclearregs} +\insnmipslabel{cclearhi} +\insnmipslabel{cclearlo} +\insnmipslabel{clearhi} +\insnmipslabel{clearlo} +\insnmipslabel{fpclearhi} +\insnmipslabel{fpclearlo} +\subsection*{CClearRegs: Clear Multiple Registers} + +\subsubsection*{Format} +ClearLo mask \\ +ClearHi mask \\ +CClearLo mask \\ +CClearHi mask \\ +FPClearLo mask \\ +FPClearHi mask + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x0f} +\bitbox{5}{regset} +\bitbox{16}{mask} +\end{bytefield} +\end{center} + +\subsubsection*{Description} + +The registers in the target register set, \emph{regset}, corresponding +to the set bits in the immediate \emph{mask} field are cleared. That +is, if bit 0 of \emph{mask} is set, then the lowest numbered register +in \emph{regset} is cleared, and so on. The following values are +defined for the \emph{regset} field: + +\begin{figure}[h] +\begin{center} +\begin{tabular}{l|l|l} +Mnemonic & \emph{regset} & Affected registers \\ +\midrule +ClearLo & 0 & \reg{0}--\reg{15} \\ +ClearHi & 1 & \reg{16}--\reg{31} \\ +CClearLo & 2 & \DDC, \creg{1}--\creg{15} \\ +CClearHi & 3 & \creg{16}--\creg{31} \\ +FPClearLo & 4 & {\bf F0--F15} \\ +FPClearHi & 5 & {\bf F16--F31} \\ +\end{tabular} +\end{center} +\end{figure} + +For integer registers, clearing means setting to zero. +For capability registers, clearing consists of setting all +capability fields such that the in-memory representation will be all zeroes, +with a cleared tag bit, granting no rights. + +\paragraph{Note:} For \insnmipsref{CClearLo} bit 0 in \emph{mask} refers to \DDC{} and not \creg{0} since \creg{0} is the NULL register. + +\subsubsection*{Semantics} + +\sailMIPScode{ClearRegs} + +\subsubsection*{Exceptions} + +\begin{itemize} +\item +A Reserved Instruction exception is raised for unknown or +unimplemented values of \emph{regset}. +\item +\insnmipsref{CClearLo} and \insnmipsref{CClearHi} raise a coprocessor +unusable exception if the capability coprocessor is disabled. +\item +\insnmipsref{FPClearLo} and \insnmipsref{FPClearHi} raise a coprocessor +unusable exception if the floating point unit is disabled. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +These instructions are designed to accelerate the register clearing +that is required for secure domain transitions. It is expected that +they can be implemented efficiently in hardware using a single `valid' +bit per register that is cleared by the ClearRegs instruction and set +on any subsequent write to the register. +\item +The mnemonic for the integer-register instruction does not make it +very clear what the instruction does. +It would be preferable to have a more descriptive mnemonic. +\end{itemize} diff --git a/insn-mips/ccleartag.tex b/insn-mips/ccleartag.tex new file mode 100644 index 00000000..420c8158 --- /dev/null +++ b/insn-mips/ccleartag.tex @@ -0,0 +1,24 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CClearTag} +\insnmipslabel{ccleartag} +\subsection*{CClearTag: Clear the Tag Bit} + +\subsubsection*{Format} + +CClearTag cd, cb + +\begin{center} +\cheritwoop[header]{0xb}{cd}{cb} +\end{center} + +\subsubsection*{Description} + +Capability register \emph{cd} is replaced with the contents of \emph{cb}, with +the tag bit cleared. + +\subsubsection*{Semantics} + +\sailMIPScode{CClearTag} + + diff --git a/insn-mips/ccleartags.tex b/insn-mips/ccleartags.tex new file mode 100644 index 00000000..d1e1ea06 --- /dev/null +++ b/insn-mips/ccleartags.tex @@ -0,0 +1,70 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CClearTags} +\insnmipslabel{ccleartags} +\subsection*{CClearTags: Zero Multiple Capability Tags in Memory} + +\subsubsection*{Format} + +CClearTags rd, cb \\ + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x00} +\bitbox{5}{cb} +\bitbox{5}{0x18} +\bitbox{5}{0x1F} +\bitbox{5}{0x3F} +\end{bytefield} +\end{center} + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Description} + +The \emph{tags} occupying the \emph{\insnmipsref{CLoadTags} stride} within +memory with base \emph{cb} are zeroed. The result of this instruction must be +coherent with other processors, \emph{as if} the corresponding data memory +words had been stored, untagged, with their current contents. The number of +tags zeroed is an implementation-defined constant but is equal to the number of +tags returned by \insnmipsref{CLoadTags}. + +Capability register \emph{cb} must contain a capability that grants permission +to store data; capability storage is not required as the bits could just as +well be cleared by \insnmipsref[csbhwd]{CSD}. The virtual address \emph{cb.\cbase{}} +$+$ \emph{cb.\coffset{}} must be suitably aligned, as with +\insnmipsref{CLoadTags}. If any tag to be cleared corresponds to memory out of +bounds of \emph{cb}, a length violation is indicated. + +\subsubsection*{Semantics} + +\sailMIPScode{CClearTags} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\cchecktag{} +\item +\emph{cb.\ctag{}} is clear. +\item +\emph{cb} is sealed. +\item +\emph{cb}.\cperms.\emph{Permit\_Store} is not set. +\item +\emph{cb}.\cbase{} $+$ \emph{cb}.\coffset{} + $n$ $*$ \emph{capability\_size} $>$ \emph{cb}.\cbase{} $+$ \emph{cb}.\clength{}, + where $n$ is the number of capabilities to be cleared (\isail{caps_per_cacheline} in the Sail code). +\item +\emph{cb}.\cbase{} $+$ \emph{cb}.\coffset{} $<$ \emph{cb}.\cbase{}. +\end{itemize} + +An address error during load (AdEL) exception is raised if: + +\begin{itemize} +\item +The virtual address \emph{addr} is not $n$ $*$ \emph{capability\_size} aligned. +\end{itemize} diff --git a/insn-mips/ccopytype.tex b/insn-mips/ccopytype.tex new file mode 100644 index 00000000..e9a878c2 --- /dev/null +++ b/insn-mips/ccopytype.tex @@ -0,0 +1,100 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CCopyType} +\insnmipslabel{ccopytype} +\subsection*{CCopyType: Import the otype field of a Capability} + +\subsubsection*{Format} + +CCopyType cd, cb, ct + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x0} +\bitbox{5}{cd} +\bitbox{5}{cb} +\bitbox{5}{ct} +\bitbox{6}{0x1e} +\end{bytefield} +\end{center} + +\subsubsection*{Description} + + +\insnmipsref{CCopyType} attempts to interpret the contents of \emph{ct} as +if it were a valid capability (even though \emph{ct}.\ctag{} is not required +to be set, and so might contain any bit pattern), +and extracts its \cotype{} field. +If \emph{ct} is sealed, \emph{cd} is set to \emph{cb} with its \coffset{} field set to +\emph{ct}.\cotype{} $-$ \emph{cb}.\cbase{}. If \emph{ct} is not sealed, +\emph{cd} is set to the NULL capability with its \cbase{} $+$ \coffset{} fields +set to $-1$. + +\subsubsection*{Semantics} +\sailMIPScode{CCopyType} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cd}, \emph{cb} or \emph{ct} are reserved registers and \PCC{} does not +grant \emph{Access\_System\_Registers} permission. +\item +\emph{cb}.\ctag{} is not set. +\item +\emph{cb} is sealed. +\item +\emph{ct}.\cotype{} is outside the bounds of \emph{cb}. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +The intended use case for this instruction is as part of a routine for +resetting the tag bit on a capability that has had its tag bit cleared +(e.g. by being swapped out to disk and then back into memory). + +It is a requirement of this specification that if a capability has its +tag bit cleared (either with \insnmipsref{CClearTag} or by copying it as +data), and \insnmipsref{CCopyType} is used to extract the \cotype{} field +of the result, then \emph{cd}.\cbase{} $+$ \emph{cd}.\coffset{} will be +equal to the \cotype{} of the original capability if it was sealed, +and \emph{cd}.\coffset{} will be -1 if the original capability was not +sealed. +\item +Typical usage of this instruction will be to use \insnmipsref{CBuildCap} to +extract the bounds and permissions of a capability, \insnmipsref{CCopyType} +to extract the \cotype{}, and then use \insnmipsref{CCSeal} to seal the +result of the first step with the correct \cotype{}. +\item +This instruction is an optimization. A similar effect could be achieved by +using \insnmipsref{CGetType} to get \emph{ct}.\cotype{} and then +\insnmipsref{CSetOffset} to set \emph{cd}.\coffset{}. +\item +-1 is not a valid value for the \cotype{} field, so the result distinguishes +between the case when \emph{ct} was sealed and the case when it was not +sealed. +\item +If \emph{ct} is sealed and an exception is not raised, then the result is +guaranteed to be representable, because the bounds checks ensure that +\emph{cd}'s cursor is within its bounds. +\item +If \emph{ct}.\cotype{} is outside of the bounds of \emph{ct}, this is an +error condition (attempting to reconstruct a capability that \emph{cb} does +not give you permission to create). In order to catch this error condition +near to where the problem occurred, we raise an exception. This also has +the benefit of avoiding the case where changing \emph{cb}'s \coffset{} +results in a value that is not representable, as explained in the previous +note. +\end{itemize} + +\mrnote{What if \emph{cb} covers only a portion of the \cotype{} space, +and \emph{ct}'s \cotype{} doesn't fall within it? As currently defined, +we raise an exception. But what if we want to detect this error and handle +it somehow? What if we have several capabilities covering different portions +of the type space, and want to try them in turn until one works?} diff --git a/insn-mips/ccseal.tex b/insn-mips/ccseal.tex new file mode 100644 index 00000000..bbec8be8 --- /dev/null +++ b/insn-mips/ccseal.tex @@ -0,0 +1,97 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CCSeal} +\insnmipslabel{ccseal} +\subsection*{CCSeal: Conditionally Seal a Capability} + +\subsubsection*{Format} + +CCSeal cd, cs, ct + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x0} +\bitbox{5}{cd} +\bitbox{5}{cs} +\bitbox{5}{ct} +\bitbox{6}{0x1f} +\end{bytefield} +\end{center} + +\subsubsection*{Description} + +If \emph{ct}.\ctag{} is false or \emph{ct}.\cbase{} $+$ \emph{ct}.\coffset{} +$= -1$, \emph{cs} is copied into \emph{cd}. +Otherwise, capability register \emph{cs} is sealed with an \cotype{} of +\emph{ct}.\cbase{} $+$ \emph{ct}.\coffset{} +and the result is placed in \emph{cd} as follows: + +\begin{itemize} +\item +\emph{cd} is sealed with \emph{cd}.\cotype{} set to \emph{ct}.\cbase{} + \emph{ct}.\coffset{}; +\item +and the other fields of \emph{cd} are copied from \emph{cs}. +\end{itemize} + +\emph{ct} must grant \emph{Permit\_Seal} permission, and the new \cotype{} +of \emph{cd} must be between \emph{ct}.\cbase{} and \emph{ct}.\cbase{} $+$ +\emph{ct}.\clength{} $-$ 1. + +\subsubsection*{Semantics} +\sailMIPScode{CCSeal} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cs}.\ctag{} is not set. +\item +\emph{cs} is sealed. +\item +\emph{ct}.\ctag{} is set and \emph{ct} is sealed. +\item +\emph{ct}.\cperms.\emph{Permit\_Seal} is not set. +% \item +% \emph{ct}.\cperms.\emph{Permit\_Execute} is not set. +\item +\emph{ct}.\ctag{} and \emph{ct}.\coffset{} $\ge$ \emph{ct}.length{} +\item +\emph{ct}.\ctag{} and \emph{ct}.\cbase{} $+$ \emph{ct}.\coffset{} $> \emph{max\_otype}$ +\item +The bounds of \emph{cb} cannot be represented exactly in a sealed capability. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +If capability compression is in use, the range of possible (\cbase{}, +\clength{}, \coffset{}) values might be smaller for sealed capabilities +than for unsealed capabilities. This means that \insnmipsref{CCSeal} +can fail with an exception in the case where the bounds are no longer +precisely representable. +\item +This instruction provides two means of indicating that the capability should +not be sealed: either clearing the tag bit on \emph{ct} or setting \emph{ct}'s +cursor to $-1$. A potential problem with just using a cursor of $-1$ (rather than +clearing the tag bit) to disable sealing is that, depending on \emph{ct}'s +\cbase{} and \coffset{}, setting \emph{ct}'s cursor to $-1$ might have a result +that is not representable. However, the NULL capability has \ctag{} clear +and can always have its cursor set to $-1$. (We implement casts from +\verb+int+ to \verb+int_cap_t+ by setting the cursor of NULL to the value of the +integer, and so this can hold a value of $-1$.) Directly clearing \emph{ct}'s +tag to indicate that sealing should not be performed will work, because it +is always possible to clear the tag bit. Setting \emph{ct}'s cursor to $-1$ with +\insnmipsref{CSetOffset} to indicate that sealing should not be performed will +also work, because this will either set the cursor to $-1$ or (if the result would +not be representable) both clear the tag bit and set the cursor to $-1$. The +latter method may be preferred in a code sequence that extracts the \cotype{} +of a capability with \insnmipsref{CGetType}, getting a value of $-1$ if the +capability is not sealed, setting the cursor of \emph{ct} to the result, and +then using \insnmipsref{CCSeal} to seal a new capability to the same +\cotype{} as the original. +\end{itemize} diff --git a/insn-mips/cfromptr.tex b/insn-mips/cfromptr.tex new file mode 100644 index 00000000..7271ef76 --- /dev/null +++ b/insn-mips/cfromptr.tex @@ -0,0 +1,62 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CFromPtr} +\insnmipslabel{cfromptr} + +\subsection*{CFromPtr: Create Capability from Pointer} + +\subsubsection*{Format} + +CFromPtr cd, cb, rt + +\begin{center} +\cherithreeop[header]{0x13}{cd}{cb}{rt} +\end{center} + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Description} + +\emph{rt} is a pointer using the C-language convention that a zero value +represents the NULL pointer. If \emph{rt} is zero, then \emph{cd} will be +the NULL capability (tag bit not set, all other bits also not set). If +\emph{rt} is non-zero, then \emph{cd} will be set to \emph{cb} with the +\coffset{} field set to \emph{rt}. + +\subsubsection*{Semantics} + +\sailMIPScode{CFromPtr} + +% {\bf FIXME: Is \cotype{} architecturally defined/meaningful if we don't +% have the set type permission? Also, there is a nasty interaction between the +% semantic defintion of fields and their in-memory representation here: the +% idea is that the in-memory representation is all zero bits, which does not +% sit well with the claim that the in-memory representation might be changed +% in future.} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cb}.\ctag{} is not set and \emph{rt} $\neq$ 0. +\item +\emph{cb} is sealed and \emph{rt} $\neq$ 0. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +\insnmipsref{CSetOffset} doesn't raise an exception if the tag bit is unset, +so that it can be used to implement the \emph{intcap\_t} type. +\insnmipsref{CFromPtr} raises an exception if the tag bit is unset: although +it would not be a security violation to to allow it, it is an indication +that the program is in error. +\item +The encodings of the NULL capability are chosen so that zeroing memory will +set a capability variable to NULL. +%This holds true for compressed capabilities +%as well as the 256-bit version. +\end{itemize} diff --git a/insn-mips/cgetaddr.tex b/insn-mips/cgetaddr.tex new file mode 100644 index 00000000..6245f2b4 --- /dev/null +++ b/insn-mips/cgetaddr.tex @@ -0,0 +1,32 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetAddr} +\insnmipslabel{cgetaddr} +\subsection*{CGetAddr: Move Capability Address to an Integer Register} + +\subsubsection*{Format} + +CGetAddr rd, cb + +\begin{center} +\cheritwoop[header]{0xf}{rd}{cb} +\end{center} + +\subsubsection*{Description} + +Integer register \textit{rd} is set equal to the \ccursor{} field (the address) of +capability register \textit{cb}. + + +\subsubsection*{Semantics} + +\sailMIPScode{CGetAddr} + +\subsubsection*{Notes} + +\begin{itemize} +\item +This differs from \insnmipsref{CToPtr} in that it does not perform any range +checks with respect to an authorizing capability, nor require that \emph{cb} +be a valid and unsealed capability. +\end{itemize} diff --git a/insn-mips/cgetandaddr.tex b/insn-mips/cgetandaddr.tex new file mode 100644 index 00000000..f17c97f1 --- /dev/null +++ b/insn-mips/cgetandaddr.tex @@ -0,0 +1,29 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetAndAddr} +\insnmipslabel{cgetandaddr} +\subsection*{CGetAndAddr: Get Address of Capability with mask} + +\subsubsection*{Format} + +CGetAndAddr rd, cb, rs + +\begin{center} +\cherithreeop[header]{0x23}{rd}{cb}{rs} +\end{center} + +\subsubsection*{Description} + +\emph{rd} is set to \emph{cb}.\caddr{} logically ANDed with \emph{rs}. + +\subsubsection*{Semantics} + +\sailMIPScode{CGetAndAddr} + +\subsubsection*{Notes} + +\begin{itemize} +\item This instruction may be useful when C is using the lower bits of a pointer with known alignment to store additional metadata. +\item This instruction is also useful when using a capability type as a union of pointers, integers and floating pointer numbers using a NaN-boxing representation. +\item In a merged register file this instruction would not be necessary since the integer bitwise and could be used instead. +\end{itemize} diff --git a/insn-mips/cgetbase.tex b/insn-mips/cgetbase.tex new file mode 100644 index 00000000..7a049705 --- /dev/null +++ b/insn-mips/cgetbase.tex @@ -0,0 +1,23 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetBase} +\insnmipslabel{cgetbase} +\subsection*{CGetBase: Move Base to an Integer Register} + +\subsubsection*{Format} + +CGetBase rd, cb + +\begin{center} +\cheritwoop[header]{0x2}{rd}{cb} +\end{center} + +\subsubsection*{Description} + +Integer register \textit{rd} is set equal to the \cbase{} field of capability +register \textit{cb}. + +\subsubsection*{Semantics} +\sailMIPScode{CGetBase} + + diff --git a/insn-mips/cgetcause.tex b/insn-mips/cgetcause.tex new file mode 100644 index 00000000..280200cd --- /dev/null +++ b/insn-mips/cgetcause.tex @@ -0,0 +1,29 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetCause} +\insnmipslabel{cgetcause} +\subsection*{CGetCause: Move the Capability Exception Cause Register to an Integer Register} + +\subsubsection*{Format} + +CGetCause rd + +\begin{center} +\cherioneop[header]{0x1}{rd} +\end{center} + +\subsubsection*{Description} + +Integer register \textit{rd} is set equal to the capability cause register. + +\subsubsection*{Semantics} +\sailMIPScode{CGetCause} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\PCC{}.\cperms{}.\emph{Access\_System\_Registers} is not set. +\end{itemize} diff --git a/insn-mips/cgetcid.tex b/insn-mips/cgetcid.tex new file mode 100644 index 00000000..ebff6286 --- /dev/null +++ b/insn-mips/cgetcid.tex @@ -0,0 +1,47 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetCID} +\insnmipslabel{cgetcid} +\subsection*{CGetCID: Move the Architectural Compartment ID to an Integer + Register} + +\subsubsection*{Format} + +CGetCID rd + +% +% XXXRW: Format and opcode still TODO. +\begin{center} +% XXXAR: 0x4 is currently the next available one-operand instruction +\cherioneop[header]{0x4}{rd} +\\ +\arnote{This encoding is not final -- do not implement} +\end{center} + +\subsubsection*{Description} + +Move the architectural Compartment ID (CID) to integer register \emph{rd}, +retrieving the last value set by \insnmipsref{CSetCID}. + +\subsubsection*{Semantics} + +\sailMIPScode{CGetCID} + +\subsubsection*{Exceptions} + +This instruction does not raise any exceptions. + +\subsubsection*{Notes} + +\begin{itemize} +\item + We choose not to require any additional privilege to query the CID. + An argument could be made that this is an information leak. + If so, one possible design choice would be to require + Access\_System\_Registers to retrieve the value of the CID; however, this + would be inconsistent with the access-control model for setting the CID. +\item + While this instruction has been introduced for debugging purposes, it could + also have utility in indexing state -- e.g., to implement concepts such as + compartment-local storage. +\end{itemize} diff --git a/insn-mips/cgetflags.tex b/insn-mips/cgetflags.tex new file mode 100644 index 00000000..03f6d2bc --- /dev/null +++ b/insn-mips/cgetflags.tex @@ -0,0 +1,24 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetFlags} +\insnmipslabel{cgetflags} +\subsection*{CGetFlags: Move Flags to an Integer Register} + +\subsubsection*{Format} + +CGetFlags rd, cb + +\begin{center} +\cheritwoop[header]{0x12}{rd}{cb} +\end{center} + +\subsubsection*{Description} + +The least significant bits of integer register \emph{rd} are set +equal to the \cflags{} field of capability register \emph{cb}. +The other bits of \emph{rd} are set to zero. + +\subsubsection*{Semantics} +\sailMIPScode{CGetFlags} + + diff --git a/insn-mips/cgetlen.tex b/insn-mips/cgetlen.tex new file mode 100644 index 00000000..fc11519f --- /dev/null +++ b/insn-mips/cgetlen.tex @@ -0,0 +1,32 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetLen} +\insnmipslabel{cgetlen} +\subsection*{CGetLen: Move Length to an Integer Register} + +\subsubsection*{Format} + +CGetLen rd, cb + +\begin{center} +\cheritwoop[header]{0x3}{rd}{cb} +\end{center} + +\subsubsection*{Description} + +Integer register \textit{rd} is set equal to the \clength{} field of capability +register \textit{cb}. + +\subsubsection*{Semantics} +\sailMIPScode{CGetLen} + +\subsubsection*{Notes} + +\begin{itemize} +\item +%With the 256-bit representation of capabilities, \clength{} is a 64-bit +%unsigned integer and can never be greater than $2^{64}-1$. +With the 128-bit compressed representation of capabilities, the result of +decompressing the length can be $2^{64}$; \insnmipsref{CGetLen} will return +the maximum value of $2^{64}-1$ in this case. +\end{itemize} diff --git a/insn-mips/cgetoffset.tex b/insn-mips/cgetoffset.tex new file mode 100644 index 00000000..210ee333 --- /dev/null +++ b/insn-mips/cgetoffset.tex @@ -0,0 +1,23 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetOffset} +\insnmipslabel{cgetoffset} +\subsection*{CGetOffset: Move Offset to an Integer Register} + +\subsubsection*{Format} + +CGetOffset rd, cb + +\begin{center} +\cheritwoop[header]{0x6}{rd}{cb} +\end{center} + +\subsubsection*{Description} + +Integer register \textit{rd} is set equal to the \coffset{} fields of +capability register \textit{cb}. + +\subsubsection*{Semantics} +\sailMIPScode{CGetOffset} + + diff --git a/insn-mips/cgetpcc.tex b/insn-mips/cgetpcc.tex new file mode 100644 index 00000000..3af9b4d0 --- /dev/null +++ b/insn-mips/cgetpcc.tex @@ -0,0 +1,26 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetPCC} +\insnmipslabel{cgetpcc} +\subsection*{CGetPCC: Move PCC to Capability Register} + +\subsubsection*{Format} + +CGetPCC cd + + +\begin{center} +\cherioneop[header]{0x0}{cd} +\end{center} + +\subsubsection*{Description} + +Capability register \textit{cd} is set equal to the \PCC{}, with +cd.\coffset{} set equal to \PC{}. +\ajnote{implement as CReadHwr PCC ?} + +\subsubsection*{Semantics} + +\sailMIPScode{CGetPCC} + + diff --git a/insn-mips/cgetpccincoffset.tex b/insn-mips/cgetpccincoffset.tex new file mode 100644 index 00000000..82b18727 --- /dev/null +++ b/insn-mips/cgetpccincoffset.tex @@ -0,0 +1,31 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetPCCIncOffset} +\insnmipslabel{cgetpccincoffset} +\subsection*{CGetPCCIncOffset: Move PCC to Capability Register and Increment Offset} + +\subsubsection*{Format} + +CGetPCCIncOffset cd, rs + +\begin{center} +\cheritwoop[header]{0x13}{cd}{rs} +\end{center} + +\subsubsection*{Description} + +Capability register \emph{cd} is set equal to the \PCC{}, with +cd.\caddr{} set equal to \PCC{}.\caddr{} $+$ +\emph{rs}. + +\subsubsection*{Semantics} + +\sailMIPScode{CGetPCCIncOffset} + +\subsection*{Notes} + +\begin{itemize} +\item +This instruction is a performance optimization; a similar effect can be +achieved with \insnmipsref{CGetPCC} followed by \insnmipsref{CIncOffset}. +\end{itemize} diff --git a/insn-mips/cgetpccsetaddr.tex b/insn-mips/cgetpccsetaddr.tex new file mode 100644 index 00000000..28286606 --- /dev/null +++ b/insn-mips/cgetpccsetaddr.tex @@ -0,0 +1,30 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetPCCSetAddr} +\insnmipslabel{cgetpccsetaddr} +\subsection*{CGetPCCSetAddr: Move PCC to Capability Register with New Address} + +\subsubsection*{Format} + +CGetPCCSetAddr cd, rs + +\begin{center} +\cheritwoop[header]{0x14}{cd}{rs} +\end{center} + +\subsubsection*{Description} + +Capability register \emph{cd} is set equal to the \PCC{}, with +cd.\caddr{} set equal to \emph{rs}. + +\subsubsection*{Semantics} + +\sailMIPScode{CGetPCCSetAddr} + +\subsection*{Notes} + +\begin{itemize} +\item +This instruction is a performance optimization; a similar effect can be +achieved with \insnmipsref{CGetPCC} followed by \insnmipsref{CSetAddr}. +\end{itemize} diff --git a/insn-mips/cgetpccsetoffset.tex b/insn-mips/cgetpccsetoffset.tex new file mode 100644 index 00000000..7c45e994 --- /dev/null +++ b/insn-mips/cgetpccsetoffset.tex @@ -0,0 +1,35 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetPCCSetOffset} +\insnmipslabel{cgetpccsetoffset} +\subsection*{CGetPCCSetOffset: Move PCC to Capability Register with New Offset} + +\subsubsection*{Format} + +CGetPCCSetOffset cd, rs + + +\begin{center} +\cheritwoop[header]{0x7}{cd}{rs} +\end{center} + +\subsubsection*{Description} + +Capability register \emph{cd} is set equal to the \PCC{}, with +cd.\coffset{} set equal to \emph{rs}. + +\subsubsection*{Semantics} + +\sailMIPScode{CGetPCCSetOffset} + +\subsection*{Notes} + +\begin{itemize} +\item +This instruction is a performance optimization; a similar effect can be +achieved with \insnmipsref{CGetPCC} followed by \insnmipsref{CSetOffset}. +% \note{rmn30}{is it similar or precisely the same except for performance? If not why not? } +% \note{mr101}{I believe that they are exactly the same, except that using +%two instructions will write to a temporary register, which must be +% accessible, etc.} +\end{itemize} diff --git a/insn-mips/cgetperm.tex b/insn-mips/cgetperm.tex new file mode 100644 index 00000000..235568ab --- /dev/null +++ b/insn-mips/cgetperm.tex @@ -0,0 +1,26 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetPerm} +\insnmipslabel{cgetperm} +\subsection*{CGetPerm: Move Permissions to an Integer Register} + +\subsubsection*{Format} + +CGetPerm rd, cb + +\begin{center} +\cheritwoop[header]{0x0}{rd}{cb} +\end{center} + +\subsubsection*{Description} + +The least significant \hyperref[table:pseudocode-constants]{\emph{last\_hperm}}$+1$ bits of integer register \emph{rd} are set +equal to the \cperms{} field of capability register \emph{cb}; bits +\hyperref[table:pseudocode-constants]{\emph{first\_uperm}} to +\hyperref[table:pseudocode-constants]{\emph{last\_uperm}} of \emph{rd} are set equal to the +\cuperms{} field of \emph{cb}. The other bits of \emph{rd} are set to zero. + +\subsubsection*{Semantics} +\sailMIPScode{CGetPerm} + + diff --git a/insn-mips/cgetsealed.tex b/insn-mips/cgetsealed.tex new file mode 100644 index 00000000..fe5779e1 --- /dev/null +++ b/insn-mips/cgetsealed.tex @@ -0,0 +1,24 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetSealed} +\insnmipslabel{cgetsealed} +\subsection*{CGetSealed: Test if Capability is Sealed} + +\subsubsection*{Format} + +CGetSealed rd, cb + +\begin{center} +\cheritwoop[header]{0x5}{rd}{cb} +\end{center} + +\subsubsection*{Description} + +The low-order bit of integer register \emph{rd} is set to +$0$ if \emph{cb}.\cotype{} is $2^{64}-1$ and $1$ otherwise. +All other bits of \emph{rd} are cleared. + +\subsubsection*{Semantics} +\sailMIPScode{CGetSealed} + + diff --git a/insn-mips/cgettag.tex b/insn-mips/cgettag.tex new file mode 100644 index 00000000..38bba214 --- /dev/null +++ b/insn-mips/cgettag.tex @@ -0,0 +1,24 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetTag} +\insnmipslabel{cgettag} +\subsection*{CGetTag: Move Tag Bit to an Integer Register} + +\subsubsection*{Format} + +CGetTag rd, cb + + +\begin{center} +\cheritwoop[header]{0x4}{rd}{cb} +\end{center} + +\subsubsection*{Description} + +The low bit of integer register \emph{rd} is set to the \ctag{} field of +\emph{cb}. All other bits are cleared. + +\subsubsection*{Semantics} +\sailMIPScode{CGetTag} + + diff --git a/insn-mips/cgettype.tex b/insn-mips/cgettype.tex new file mode 100644 index 00000000..7dc5db86 --- /dev/null +++ b/insn-mips/cgettype.tex @@ -0,0 +1,32 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetType} +\insnmipslabel{cgettype} +\subsection*{CGetType: Move Object Type to an Integer Register} + +\subsubsection*{Format} + +CGetType rd, cb + +\begin{center} +\cheritwoop[header]{0x1}{rd}{cb} +\end{center} + +\subsubsection*{Description} + +Integer register \textit{rd} is set equal to the \cotype{} field of capability +register \textit{cb}. + +\subsubsection*{Semantics} +\sailMIPScode{CGetType} + +\subsection*{Notes} + +\begin{itemize} +\item +If the capability is unsealed, a value of -1 is returned. +For hardware-interpreted \cotype{}s (see \cref{tab:archotypes}) a sign-extended +(negative) value is returned; for software-defined \cotype{}s +(see \cref{sec:model-sealedcapabilities}) \insnmipsref{CGetType} returns +a zero-extended value. +\end{itemize} diff --git a/insn-mips/cincoffset.tex b/insn-mips/cincoffset.tex new file mode 100644 index 00000000..346ba22b --- /dev/null +++ b/insn-mips/cincoffset.tex @@ -0,0 +1,69 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CIncOffset} +\insnmipslabel{cincoffset} +\subsection*{CIncOffset: Increment Offset} + +\subsubsection*{Format} + +CIncOffset cd, cb, rt + +\begin{center} +\cherithreeop[header]{0x11}{cd}{cb}{rt} +\end{center} + +\subsubsection*{Description} + +Capability register \emph{cd} is set equal to capability register +\emph{cb} with its \coffset{} field replaced with \emph{cb}.\coffset{} $+$ +\emph{rt}. + +If the requested \cbase{}, \clength{} +and \coffset{} cannot be represented exactly, then \emph{cd}.\ctag{} is +cleared and \emph{cd}.\ccursor{} is set equal to +\emph{cb}.\ccursor{} $+$ \emph{rt}. +\arnote{The values of the other capability fields are unspecified?} + +\subsubsection*{Semantics} +\sailMIPScode{CIncOffset} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cb}.\ctag{} is set and \emph{cb} is sealed. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +For security reasons, \insnmipsref{CIncOffset} must not change the offset +of a sealed capability. +\item +If the tag bit is not set, and the offset is being used to hold an integer, +then \insnmipsref{CIncOffset} should still increment the offset. This is +so that \insnmipsref{CIncOffset} can be used to implement increment of +a \ccode{intcap\_t} type. +Because the tag is unset, \insnmipsref{CIncOffset} +will ignore the decoded \cotype{} and so will not attempt to enforce +immutability of detagged sealed capabilities. +(The precise effect of \insnmipsref{CIncOffset} on such +non-capability data will depend on which binary representation of +capabilities is being used.) +\item +If the tag bit is not set, and capability compression is in use, +the arbitrary data in \emph{cb} might not decompress to sensible values +of the \cbase{} and \clength{} fields, and there is no guarantee that +retaining these values of \cbase{} and \clength{} while changing +\coffset{} will result in a representable value. + +From a software perspective, the requirement is that incrementing \coffset{} +on an untagged capability will work if \cbase{} and \clength{} are zero. (This +is how integers, and pointers that have lost precision, will be represented). +If \cbase{} and \clength{} have non-zero values (or \emph{cb} cannot be +decompressed at all), then the values of \cbase{} and \clength{} after this +instruction are \textbf{UNPREDICTABLE}. +\end{itemize} diff --git a/insn-mips/cincoffsetimm.tex b/insn-mips/cincoffsetimm.tex new file mode 100644 index 00000000..e6483f1c --- /dev/null +++ b/insn-mips/cincoffsetimm.tex @@ -0,0 +1,76 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CIncOffsetImm} +\insnmipslabel{cincoffsetimm} +\subsection*{CIncOffsetImm: Increment Offset by Immediate} + +\subsubsection*{Format} + +CIncOffset cd, cb, increment$_{imm}$ + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x13} +\bitbox{5}{cd} +\bitbox{5}{cb} +\bitbox{11}{increment$_{imm}$} +\end{bytefield} +\end{center} + +\arnote{The assembler supports both CIncOffset and CIncOffsetImm but I think we should always use CIncOffset} + +\subsubsection*{Description} + +Capability register \emph{cd} is set equal to capability register +\emph{cb} with its \coffset{} field replaced with \emph{cb}.\coffset{} $+$ +\emph{increment$_{imm}$}. + +If the requested \cbase{}, \clength{} and \coffset{} cannot be represented exactly, +then \emph{cd}.\ctag{} is cleared and \emph{cd}.\ccursor{} is set equal to +\emph{cb}.\ccursor{} $+$ \emph{increment$_{imm}$}. + +\subsubsection*{Semantics} +\sailMIPScode{CIncOffsetImmediate} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cb}.\ctag{} is set and \emph{cb} is sealed. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +For security reasons, \insnmipsref{CIncOffsetImm} must not change the offset +of a sealed capability. +\item +If the tag bit is not set, and the offset is being used to hold an integer, +then \insnmipsref{CIncOffsetImm} should still increment the offset. This is +so that \insnmipsref{CIncOffsetImm} can be used to implement increment of +a \ccode{intcap\_t} type. +Because the tag is unset, \insnmipsref{CIncOffset} +will ignore the decoded \cotype{} and so will not attempt to enforce +immutability of detagged sealed capabilities. +(The precise effect of \insnmipsref{CIncOffset} on such +non-capability data will depend on which binary representation of +capabilities is being used.) +\item +If the tag bit is not set, and capability compression is in use, +the arbitrary data in \emph{cb} might not decompress to sensible values +of the \cbase{} and \clength{} fields, and there is no guarantee that +retaining these values of \cbase{} and \clength{} while changing +\coffset{} will result in a representable value. + +From a software perspective, the requirement is that increasing \coffset{} +on an untagged capability will work if \cbase{} and \clength{} are zero. (This +is how integers, and pointers that have lost precision, will be represented). +If \cbase{} and \clength{} have non-zero values (or \emph{cb} cannot be +decompressed at all), then the values of \cbase{} and \clength{} after this +instruction are \textbf{UNPREDICTABLE}. +\end{itemize} diff --git a/insn-mips/cinvoke.tex b/insn-mips/cinvoke.tex new file mode 100644 index 00000000..b7bb75bd --- /dev/null +++ b/insn-mips/cinvoke.tex @@ -0,0 +1,208 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CInvoke} +\insnmipslabel{cinvoke} +\subsection*{CInvoke: Call into Another Security Domain} + +\subsubsection*{Format} + +CInvoke cs, cb + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x05} +\bitbox{5}{cs} +\bitbox{5}{cb} +\bitbox{11}{0x001} +\end{bytefield} +\end{center} + +\subsubsection*{Description} + +\insnmipsref{CInvoke} is used to jump between protection domains, +unsealing sealed code and data-capability operands, subject to checks on those +capabilities. +This allows the target protection domain to gain access to a different set of capabilities, +supporting implementation of software encapsulation. +The two operand capabilities must be accessible, be valid capabilities, be +sealed, have matching types, and have suitable permissions and bounds, or an +exception will be thrown. +\emph{cs} contains a sealed code capability for the target subsystem, which +will be unsealed and loaded into \PCC{}. +\emph{cb} contains a sealed data capability for the target subsystem, which +will be unsealed and loaded into \IDC{}. +In the parlance of object-oriented programming, \emph{cb} is a capability for +an \emph{object}'s instance data, and \emph{cs} is a capability for the +methods of the object's class. + +With \insnmipsref{CInvoke}, a constrained form of non-monotonicity is supported in +the architecture. +Privilege is escalated by virtue of \insnmipsref{CInvoke} +unsealing sealed operand capability registers during a controlled transfer of +execution to the callee in a jump-style transfer of control. +\insnmipsref{CInvoke} requires \emph{Permit\_CInvoke} to be present on both + sealed capability operands. + +\subsubsection*{Semantics} + +\sailMIPScode{CCallA} + +\noindent +\note{rmn30}{XXX There is a test that CInvoke in branch delay slot of ordinary branch raises Reserved Instruction exception. This needs to be specified if desired. Does it apply to both version of CInvoke? } +\insnmipsref{CInvoke} executes like a branch in the pipeline, but does +not have a branch delay slot. This is due to the difficulty of allowing one +instruction from the calling domain to execute in the new domain. +See Section~\ref{sec:jump-based-domain-transition}. +% XXXRW: Address note: +% +%\note{jdw57}{What is the formal notation for describing an exception condition +%for the following instruction?} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cs} is not sealed. +\item +\emph{cb} is not sealed. +\item +\emph{cs}.\cotype{} $\ne$ \emph{cb}.\cotype{} +\item +\emph{cs}.\cperms{}.\emph{Permit\_Execute} is not set. +\item +\emph{cb}.\cperms{}.\emph{Permit\_Execute} is set. +\item +\emph{cs}.\coffset{} $\ge$ \emph{cs}.\clength{}. +\item +\emph{cs}.\cperms{}.\emph{Permit\_CInvoke} is not set +\item +\emph{cb}.\cperms{}.\emph{Permit\_CInvoke} is not set +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +From the point of view of security, \insnmipsref{CInvoke} needs to be an atomic +operation (i.e. the caller cannot decide to just do some of it, because +partial execution could put the system +into an insecure state). +From a hardware perspective, more complex domain-transition implementations +(e.g., to implement function-call semantics or message passing) may need to +perform multiple memory reads and writes, which might take multiple cycles and +complicate control logic. + +\item +Implementations may choose to restrict the register numbers that may be passed as \emph{cs} and \emph{cb} in order to avoid the need to decode the instruction and identify the register arguments. +\jhbnote{Is this still true of CInvoke (selector 1) compared to CCall + selector 0?} + +\item +The unsealing of the capabilities stored to PCC and IDC may have implications +beyond just the object type of these capabilities. +When capability compression is in use, the +microarchitectural bit representation of other fields within a capability +may depend on the value of the \cotype{}, so this assignment may have the +effect of changing the bit representation of the other fields. i.e., a +hardware implementation may need to change the representation of the rest +of the capability. +(In the deprecated CHERI-128 of \cref{app:cheri-128}, +for example, which does not have a dedicated \cotype{} field, +\insnmipsref{CInvoke} clears the sealed bits of the capabilities +stored to PCC and IDC but must also zero +the bits that held the \cotype{} values +and are now part of the bounds metadata.) + +\end{itemize} + +\rwnote{Need to add notes on \insnmipsref{CSetCID} here, as well as examples + to pseudocode.} + +\subsubsection*{Expected Software Use} + +Higher-level software protection-domain transitions transform the capability +register file to reduce or expand the set of code and data rights available to +the executing thread of control. +In CHERI-based software, these transitions can be usefully modeled as function +invocation or message passing in which data and capability registers are +passed as arguments or messsages, and in which callers and callees can be +protected from undesired access to internal state from the other party (i.e., +encapsulation). +Domain transitions may implement symmetric (mutual) or asymmetric distrust +between caller and callee, depending on guarantees about limiting callee +access to caller state, and vice versa. + +\insnmipsref{CInvoke} may be used to implement mutual distrust by entering a more +privileged ``trusted intermediary'' able to perform capability and +integer register clearing, saving, and restoring, as well as tracking +properties of communications such as message passing or implementing a trusted +stack for reliable call-return semantics and error recovery. +The \insnmipsref{CInvoke} instruction performs a set of checks on sealed +operand capabilities allowing +domain transition to be more efficient. + +A number of use cases can be formulated, depending on trust +model. +To implement mutual distrust, sealed code capabilities must point to an +intermediary that is trusted by the callee to implement escalation to +callee privilege. +With respect to capabilities, the caller can perform its own register +clearing and encapsulation of (optional) return state passed via register +arguments to the callee. +\insnmipsref{CInvoke} does not implement a link register, allowing the +calling convention +to implement semantics not implying a leak of \PCC{} to the callee. +In our CheriOS software prototype, sealed code capabilities refer to one of a +set of message-passing implementations, with the sealed data capability +describing the message ring and target domain's code and data capabilities. +A second \insnmipsref{CJR} out of the message-passing implementation into the +callee, combined with suitable register clearing, is suitable to deescalate +privilege to the callee protection domain without a second use of +\insnmipsref{CInvoke}. + +\subsubsection*{Sketch of the CheriBSD CInvoke Model} + +The CheriBSD \insnmipsref{CInvoke} model implements domain transition via +privileged call and return handlers. +Modeled on function invocation, the call handler performs various +checks (such as of operand register accessibility, validity, sealing, types, +and permissions) on argument registers. +If the checks pass, the handler unseals the sealed operand capabilities, +installing them in \PCC{} and \IDC{}. +It also clears other non-argument registers to prevent data and capability +leakage from caller to callee. +In addition, CheriBSD implements a trusted stack that tracks caller \PCC{} and +\IDC{} so that the return handler can restore control (and +security state) one instruction after the original call site. +Finally, the call handler also implements a form of capability flow +control by preventing the passing of non-global capabilities between caller +and callee. +The return handler pops an entry from the trusted stack, suitably clears +non-return registers, and performs capability flow-control on non-global return +capabilities. +If the return handler is invoked on an empty trusted stack, +the handler raises an exception. +If the call handler is invoked when the trusted stack is full, +the call fails and returns an error to the caller. + +\subsubsection*{Sketch of the CheriOS CInvoke Model} + +In the CheriOS model, \insnmipsref{CInvoke} is used to implement an +asynchronous message-passing semantic. +The sealed code capability is directed to a software message-passing +implementation that acts as a ``trusted intermediary'', and the sealed data +capability refers to a description of the destination domain including message +ring. +The message-passing implementation adds argument registers to the ring, and +will then either return control to the sender context, or continue in to the +recipient context. +This is accomplished by suitable register-file manipulation to give up any +unnecessary privilege, and an ordinary capability jump to pass control to an +appropriate unprivileged domain. +As with the CheriBSD model, the message-passing routine must perform any +necessary saving of caller context, checking and clearing of registers, and +installation of callee context to support safe interactions. diff --git a/insn-mips/cjalr.tex b/insn-mips/cjalr.tex new file mode 100644 index 00000000..279ca4da --- /dev/null +++ b/insn-mips/cjalr.tex @@ -0,0 +1,70 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CJR / CJALR} +\insnmipslabel{cjalr} +\subsection*{CJR / CJALR: Jump (and Link) Capability Register} + +\subsubsection*{Format} + +CJALR cb, cd + +\begin{center} +\cheritwoop[header]{0xc}{cd}{cb} +\end{center} + +\phantomsection +\insnmipslabel{cjr} + +CJR cb + +\begin{center} +\cherioneop[header]{0x3}{cb} +\end{center} + +\note{rmn30}{Now that C0 is NULL we could encode this using CJALR with cd == 0 and save a whole opcode.} +\subsubsection*{Description} + +The current \PCC{} (with an offset of the current \PC{} $+$ 8) is +optionally saved in \textit{cd}. +\PCC{} is then loaded from capability register \textit{cb} and \PC{} +is set from its offset. + +\subsubsection*{Semantics} +\sailMIPScode{CJALR} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception will be raised if: + +\begin{itemize} +\item +\emph{cb.\ctag{}} is not set. +\item +\emph{cb} is sealed. (But see \cref{sec:arch-sentry}.) +\item +\textit{cb.\cperms.Permit\_Execute} is not set. +\item +\textit{cb.\coffset{}} + 4 is greater than \textit{cb.\clength{}}. +\end{itemize} + +An address error exception will be raised if + +\begin{itemize} +\item +\textit{cb.\cbase{}} + \textit{cb.\coffset{}} is not 4-byte word aligned. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +\insnmipsref{CJALR} has a branch delay slot. +\item +The change to \PCC{} does not take effect until the instruction in the branch +delay slot has been executed. +\item +\note{rmn30}{The following text is copied from cjr but was not present here before I merged cjr and cjalr. What is the importance of this? I think it is just to rule out offsets effectively less than zero but since we actually store the address (not offset) and compare against base in Sail I think it is redundant.} +\textit{cb.\cbase{}} and \textit{cb.\clength{}} are treated as unsigned integers, +and the result of the addition does not wrap around (i.e., an exception is +raised if \emph{cb.\cbase{}}+\emph{cb.\coffset{}} is greater than maxaddr). +\end{itemize} diff --git a/insn-mips/cl.tex b/insn-mips/cl.tex new file mode 100644 index 00000000..35c66d94 --- /dev/null +++ b/insn-mips/cl.tex @@ -0,0 +1,115 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CL[BHWD][U]} +\insnmipslabel{clbhwd} +\subsection*{Load Integer via Capability Register} + +\subsubsection*{Format} + +CLB rd, rt, offset(cb)\\ +CLH rd, rt, offset(cb)\\ +CLW rd, rt, offset(cb)\\ +CLD rd, rt, offset(cb)\\ +CLBU rd, rt, offset(cb)\\ +CLHU rd, rt, offset(cb)\\ +CLWU rd, rt, offset(cb)\\ +CLBR rd, rt(cb)\\ +CLHR rd, rt(cb)\\ +CLWR rd, rt(cb)\\ +CLDR rd, rt(cb)\\ +CLBUR rd, rt(cb)\\ +CLHUR rd, rt(cb)\\ +CLWUR rd, rt(cb)\\ +CLBI rd, offset(cb)\\ +CLHI rd, offset(cb)\\ +CLWI rd, offset(cb)\\ +CLDI rd, offset(cb)\\ +CLBUI rd, offset(cb)\\ +CLHUI rd, offset(cb)\\ +CLWUI rd, offset(cb) + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,1,3,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x32} +\bitbox{5}{rd} +\bitbox{5}{cb} +\bitbox{5}{rt} +\bitbox{8}{offset} +\bitbox{1}{s} +\bitbox{2}{t} +\end{bytefield} +\end{center} + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Purpose} + +Loads a data value via a capability register, and extends the value to fit the target register. + +\subsubsection*{Description} + +The lower part of integer register \emph{rd} is loaded from the memory +location specified by \emph{cb.\cbase{}} + \emph{cb.\coffset{}} + \emph{rt} + +$2^t$ $*$ \emph{offset}. Capability register \emph{cb} must +contain a valid capability that grants permission to load data. + +The size of the value loaded depends on the value of the \emph{t} field: + +\begin{description} + \item[0] byte (8 bits) + \item[1] halfword (16 bits) + \item[2] word (32 bits) + \item[3] doubleword (64 bits) +\end{description} + +The extension behavior depends on the value of the \emph{s} field: 1 indicates sign extend, 0 indicates zero extend. For example, \insnmipsref[clbhwd]{CLWU} is encoded by setting \emph{s} to 0 and \emph{t} to 2, \insnmipsref[clbhwd]{CLB} is encoded by setting \emph{s} to 1 and +\emph{t} to 0. + +\subsubsection*{Semantics} +\sailMIPScode{CLoad} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\cchecktag{} +\item +\emph{cb} is sealed. +\item +\emph{cb}.\cperms.\emph{Permit\_Load} is not set. +\item +\emph{addr} $+$ \emph{size} $>$ \emph{cb}.\cbase{} $+$ \emph{cb}.\clength{} + +NB: The check depends on the size of the data loaded. +\item +\emph{addr} $<$ \emph{cb}.\cbase{} +\end{itemize} + +An AdEL exception is raised if \emph{addr} is not correctly aligned. + +\subsubsection*{Notes} + +\begin{itemize} +\item +This instruction reuses the opcode from the Load Word to Coprocessor 2 +(\insnnoref{LWC2}) instruction in the MIPS Specification. +\item +\emph{rt} is treated as an unsigned integer.\note{rmn30}{since rt is 64-bit and addr is computed modulo $2^{64}$ it doesn't make any difference whether it is treated as signed or unsigned. It actually can make sense to think of it as a signed offset. Maybe we should remove this note? Important to note that immediate offset is signed, however.} +\item +\emph{offset} is treated as a signed integer. +% \item +% The result of the addition does not wrap around (i.e., an exception is +% raised if cb.\cbase{} $+$ cb.\coffset{} $+$ \emph{rt} $+$ \emph{offset} +% is less than zero, or greater than \emph{maxaddr}). +% \item +% The temporary variable \emph{addr} can have values that are less than zero +% or greater than $2^{64}-1$; the computation of \emph{addr} does not wrap +% around modulo $2^{64}$. +\item +BERI1 has a compile-time option to allow unaligned loads and stores. If BERI1 +is built with this option, an unaligned load will only raise an exception if +it crosses a cache line boundary. +\end{itemize} diff --git a/insn-mips/clc.tex b/insn-mips/clc.tex new file mode 100644 index 00000000..173687b4 --- /dev/null +++ b/insn-mips/clc.tex @@ -0,0 +1,86 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CLC} +\insnmipslabel{clc} +\label{sailMIPSzCLC} % for CLCNT +\subsection*{CLC: Load Capability via Capability} + +\subsubsection*{Format} + +CLC cd, rt, offset(cb) \\ +CLCR cd, rt(cb) \\ +CLCI cd, offset(cb) + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x36} +\bitbox{5}{cd} +\bitbox{5}{cb} +\bitbox{5}{rt} +\bitbox{11}{offset} +\end{bytefield} +\end{center} + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Description} +Capability register \emph{cd} is loaded from the memory location specified by +\emph{cb.\cbase{}} $+$ \emph{cb.\coffset{}} $+$ \emph{rt} $+$ \emph{offset}. +Capability register +\emph{cb} must +contain a capability that grants permission to load capabilities. The virtual +address \emph{cb.\cbase{}} $+$ \emph{cb.\coffset{}} $+$ \emph{rt} $+$ +\emph{offset} must be \emph{capability\_size} aligned. + +The bit in the tag memory corresponding to \emph{cb.\cbase{}} $+$ +\emph{cb.\coffset{}} $+$ \emph{rt} $+$ \emph{offset} is +loaded into the tag bit associated with \emph{cd}. +% The CBTU instruction can be used to check the value of this tag. + +\subsubsection*{Semantics} +\sailMIPScode{CLC} + +\subsubsection*{Exceptions} + + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\cchecktag{} +\item +\emph{cb} is sealed. +\item +\emph{cb}.\cperms.\emph{Permit\_Load} is not set. +\item +\emph{addr} + \emph{capability\_size} $>$ \emph{cb}.\cbase{} $+$ \emph{cb}.\clength{}. +\item +\emph{addr} $<$ \emph{cb}.\cbase{}. +\end{itemize} + + +An address error during load (AdEL) exception is raised if: + +\begin{itemize} +\item +The virtual address \emph{addr} is not \emph{capability\_size} aligned. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +This instruction reuses the opcode from the Load Doubleword to Coprocessor 2 +(\insnnoref{LDC2}) instruction in the MIPS Specification. +\item +\emph{offset} is interpreted as a signed integer. +\item +The \insnmipsref[clbhwd]{CLCI} mnemonic is equivalent to \insnmipsref{CLC} with +\emph{cb} being the zero register (\$zero). The \insnmipsref[clbhwd]{CLCR} mnemonic +is equivalent to \insnmipsref{CLC} with \emph{offset} set to +zero. +\item +Although the \emph{capability\_size} can vary, the offset is always in +multiples of 16 bytes (128 bits). +\end{itemize} diff --git a/insn-mips/clcbi.tex b/insn-mips/clcbi.tex new file mode 100644 index 00000000..b4920680 --- /dev/null +++ b/insn-mips/clcbi.tex @@ -0,0 +1,95 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CLCBI} +\insnmipslabel{clcbi} +\subsection*{CLCBI: Load Capability via Capability (Big Immediate)} + +\subsubsection*{Format} + +CLCBI cd, offset(cb) + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x1d} +\bitbox{5}{cd} +\bitbox{5}{cb} +\bitbox{16}{offset} +\end{bytefield} +\end{center} + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Description} +Capability register \emph{cd} is loaded from the memory location specified by +\emph{cb.\cbase{}} $+$ \emph{cb.\coffset{}} $+$ \emph{offset}. +Capability register +\emph{cb} must +contain a capability that grants permission to load capabilities. The virtual +address \emph{cb.\cbase{}} $+$ \emph{cb.\coffset{}} $+$ +\emph{offset} must be \emph{capability\_size} aligned. + +The bit in the tag memory corresponding to \emph{cb.\cbase{}} $+$ +\emph{cb.\coffset{}} $+$ \emph{offset} is +loaded into the tag bit associated with \emph{cd}. +% The CBTU instruction can be used to check the value of this tag. + +\subsubsection*{Semantics} +\sailMIPScode{CLCBI} + +\subsubsection*{Exceptions} + + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\cchecktag{} +\item +\emph{cb} is sealed. +\item +\emph{cb}.\cperms.\emph{Permit\_Load} is not set. +\item +\emph{addr} + \emph{capability\_size} $>$ \emph{cb}.\cbase{} $+$ \emph{cb}.\clength{}. +\item +\emph{addr} $<$ \emph{cb}.\cbase{}. +\end{itemize} + + +An address error during load (AdEL) exception is raised if: + +\begin{itemize} +\item +The virtual address \emph{addr} is not \emph{capability\_size} aligned. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +This instruction reuses the opcode from the Jump and Link Exchange +(\insnnoref{JALX}) instruction in the MIPS Specification. +Future versions of the architecture may use a different encoding +to avoid reusing an opcode with a delay slot for an instruction without a delay slot. +\item +\emph{offset} is interpreted as a signed integer. +\item +Although the \emph{capability\_size} can vary, the offset is always in +multiples of 16 bytes (128 bits). +\item +%The instruction allows accessing individual members in large arrays of capabilities +%without the need for additional instructions to generate the offset. +The larger immediate of \insnmipsref{CLCBI}) enables more efficient code generation +in pure-capability programs for accesses of global variables. +In many programs and libraries, the 11-bit immediate offset of \insnmipsref{CLC} +is not sufficient reach all entries in the table of global capabilities and +therefore the compiler must to generate a three-instruction sequence instead. +By using of \insnmipsref{CLCBI}) for accessing globals, the code size of most +pure-capability binaries can be reduced by over 10\%. + +\item +Architectures with pc-relative loads or instructions to add a large immediate to \PCC{} +(such as \insnnoref{AUIPC}) can use those instead of adding a capability +load with a larger immediate offset. + +\end{itemize} diff --git a/insn-mips/clcnt.tex b/insn-mips/clcnt.tex new file mode 100644 index 00000000..89830782 --- /dev/null +++ b/insn-mips/clcnt.tex @@ -0,0 +1,33 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CLCNT} +\insnmipslabel{clcnt} +\subsection*{CLCNT: Non-Temporal (Streaming) Load Capability via Capability} + +\subsubsection*{Format} + +CLCNT cd, rt(cb) \\ + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x00} +\bitbox{5}{cd} +\bitbox{5}{cb} +\bitbox{5}{rt} +\bitbox{6}{0x38} +\end{bytefield} +\end{center} + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Description} + +Architecturally equivalent to \insnmipsref{CLC} (q.v.), this instruction is +intended as a hint to the cache fabric that the loaded line is expected to be +used only a few times. See \cref{app:exp:clcnt} for rationale and more +discussion. + +\subsubsection*{Semantics} +\sailMIPScode{CLCNT} diff --git a/insn-mips/cllbhwd.tex b/insn-mips/cllbhwd.tex new file mode 100644 index 00000000..0a2643c5 --- /dev/null +++ b/insn-mips/cllbhwd.tex @@ -0,0 +1,72 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CLL[BHWD][U]} +\insnmipslabel{cllbhwd} +\insnmipslabel{cllb} +\insnmipslabel{cllh} +\insnmipslabel{cllw} +\insnmipslabel{clld} +\subsection*{CLL[BHWD][U]: Load Linked Integer via Capability} + +\subsubsection*{Format} + +CLLB rd, cb\\ +CLLH rd, cb\\ +CLLW rd, cb\\ +CLLD rd, cb\\ +CLLBU rd, cb\\ +CLLHU rd, cb\\ +CLLWU rd, cb + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,1,2,3,4,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x10} +\bitbox{5}{rd} +\bitbox{5}{cb} +\bitbox{7}{\color{lightgray}\rule{\width}{\height}} +\bitbox{1}{1} +\bitbox{1}{s} +\bitbox{2}{t} +\end{bytefield} +\end{center} + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Description} + +\insnnoref{CLL[BHWD][U]} and \insnnoref{CSC[BHWD]} are used to implement safe access +to data shared between different threads. The typical usage is that +\insnnoref{CLL[BHWD][U]} is followed (an arbitrary number of +instructions later) by \insnnoref{CSC[BHWD]} to the same address; the +\insnnoref{CSC[BHWD]} will only succeed if the memory location that was loaded +by the \insnnoref{CLL[BHWD][U]} has not been modified. + +The exact conditions under which \insnnoref{CSC[BHWD]} fails are implementation +dependent, particularly in multicore or multiprocessor implementations). The +following code is intended to represent the security semantics of the +instruction correctly, but should not be taken as a definition of the CPU's +memory coherence model. + +\subsubsection*{Semantics} +\sailMIPScode{CLoadLinked} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cb}.\ctag{} is not set. +\item +\emph{cb} is sealed. +\item +\emph{cb}.\cperms{}.\emph{Permit\_Load} is not set. +\item +\emph{addr} $+$ \emph{size} $>$ \emph{cb}.\cbase{} $+$ \emph{cb}.\clength{} +\item +\emph{addr} $<$ \emph{cb}.\cbase{} +\end{itemize} + +An AdEL exception is raised if \emph{addr} is not correctly aligned. diff --git a/insn-mips/cllc.tex b/insn-mips/cllc.tex new file mode 100644 index 00000000..3047dcf2 --- /dev/null +++ b/insn-mips/cllc.tex @@ -0,0 +1,52 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CLLC} +\insnmipslabel{cllc} +\subsection*{CLLC: Load Linked Capability via Capability} + +\subsubsection*{Format} + +CLLC cd, cb \\ + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,2,3,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x10} +\bitbox{5}{cd} +\bitbox{5}{cb} +\bitbox{7}{\color{lightgray}\rule{\width}{\height}} +\bitbox{4}{1111} +\end{bytefield} +\end{center} + +\usesDDCinsteadofNULL{cb} + +% \textbf{TO DO: Describe what this instruction does.} + +\subsubsection*{Semantics} +\sailMIPScode{CLLC} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cb}.\ctag{} is not set. +\item +\emph{cb} is sealed. +\item +\emph{cb}.\cperms.\emph{Permit\_Load} is not set. +\item +\emph{addr} $+$ \emph{capability\_size} $>$ \emph{cb}.\cbase{} $+$ \emph{cb}.\clength{} +\item +\emph{addr} $<$ \emph{cb}.\cbase{} +\end{itemize} + +An AdEL exception is raised if: + +\begin{itemize} +\item +\emph{addr} is not capability aligned. +\end{itemize} diff --git a/insn-mips/cloadtags.tex b/insn-mips/cloadtags.tex new file mode 100644 index 00000000..667f1fa1 --- /dev/null +++ b/insn-mips/cloadtags.tex @@ -0,0 +1,104 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CLoadTags} +\insnmipslabel{cloadtags} +\subsection*{CLoadTags: Read Multiple Tags to Integer Register} + +\subsubsection*{Format} + +CLoadTags rd, cb \\ + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x00} +\bitbox{5}{rd} +\bitbox{5}{cb} +\bitbox{5}{0x1E} +\bitbox{5}{0x3F} +\end{bytefield} +\end{center} + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Description} + +The \emph{tags} from memory referenced by \emph{cb} are loaded to \emph{rd}, +with bit significance increasing with memory address. The result of this +instruction must be coherent with other processors, \emph{as if} the +corresponding data memory words had been loaded. The number of tags loaded is +an implementation-defined constant but is constrained to be a power of two, at +least 1, and no more than the width of \emph{rd}. + +Capability register \emph{cb} must contain a capability that grants permission +to load capabilities. The virtual address \emph{cb.\cbase{}} $+$ +\emph{cb.\coffset{}} must be suitably aligned; the precise requirements are, +again, implementation defined, but must equal the width of memory corresponding +to the tags loaded. If any tag to be loaded corresponds to memory out of +bounds of \emph{cb}, a length violation is indicated. + +\subsubsection*{Semantics} + +\sailMIPScode{CLoadTags} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\cchecktag{} +\item +\emph{cb.\ctag{}} is clear. +\item +\emph{cb} is sealed. +\item +\emph{cb}.\cperms.\emph{Permit\_Load} is not set. +\item +\emph{cb}.\cbase{} $+$ \emph{cb}.\coffset{} + $n$ $*$ \emph{capability\_size} $>$ \emph{cb}.\cbase{} $+$ \emph{cb}.\clength{}, + where $n$ is the number of capabilities to be fetched (\isail{caps_per_cacheline} in the Sail code). +\item +\emph{cb}.\cbase{} $+$ \emph{cb}.\coffset{} $<$ \emph{cb}.\cbase{}. +\end{itemize} + +An address error during load (AdEL) exception is raised if: + +\begin{itemize} +\item +The virtual address \emph{addr} is not $n$ $*$ \emph{capability\_size} aligned. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +% +\item In practice, the number of tags loaded is likely less arbitrary than it +may appear. Usually, the implementation's cache fabric determines the minimum +granularity of coherency and already tracks tag bits along with each cache +line, and so this instruction fetches the tag bits from the cache line +indicated by \emph{cb}.\cbase{} $+$ \emph{cb}.\coffset{}. Of course, additional +complexity in the cache and tag cache fabric could allow this instruction to +retrieve more tags than in a cache line. +Also, the number of tags this instruction loads should be a power-of-two to +avoid alignment issues and to preserve page divisibility in systems with MMUs. +In order to reduce DRAM traffic, it is desirable that this \emph{tag fetch} not +require loading the corresponding data and not necessarily evict other lines +from caches. (However, a non-zero result is probably a reasonable hint that a +capability load is likely to follow.) + + +\item Software can easily discover the width used by any implementation by +constructing an aligned array of capabilities in memory and observing the +result of \insnmipsref{CLoadTags}. +%; for a CHERI instantiation with 256-bit +%capability representations and 64-bit integer registers, the maximal +%alignment requirement for these probes is 512 bytes. +Such probes need be done only rarely, at system or allocator startup. + +\item For multi-core or multi-processor systems with cache fabrics wherein cache +lines are of different sizes, \insnmipsref{CLoadTags} must behave as if all +cores view the memory subsystem through the \emph{smallest} cache line in +the system. + +\end{itemize} diff --git a/insn-mips/clshc.tex b/insn-mips/clshc.tex new file mode 100644 index 00000000..b390ef12 --- /dev/null +++ b/insn-mips/clshc.tex @@ -0,0 +1,78 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CLShC} +\insnmipslabel{clshc} +\insnmipslabel{clshci} +\insnmipslabel{clshcr} +\subsection*{CLShC: Load Short Capability via Capability} + +\subsubsection*{Format} + +CLShC cd, rt, offset(cb) \\ +CLShCR cd, rt(cb) \\ +CLShCI cd, offset(cb) + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Description} + +Capability register \emph{cd} is loaded with the decoded form of the short +capability located at the memory location specified by +% +\emph{addr} $\stackrel{\Delta}{=}$ \emph{cb.\cbase{}} $+$ +\emph{cb.\coffset{}} $+$ \emph{rt} $+$ 8 $*$ \emph{offset}, +% +provided this address is suitably aligned for short capabilities. +% +Capability register \emph{cb} must contain a capability that grants +permission to load capabilities. + +The tag bit associated with \emph{cd} is set if the tag bits associated with +\emph{addr} indicate that this address contain a short capability and +\emph{cb} bears Permit\_Load\_Capability. See +\cref{sec:windowedshortcaps} for possible tag representations. + +% \subsubsection*{Semantics} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\cchecktag{} +\item +\emph{cb} is sealed. +\item +\emph{cb}.\cperms.\emph{Permit\_Load} is not set. +\item +\emph{addr} + \emph{short\_capability\_size} $>$ \emph{cb}.\cbase{} $+$ \emph{cb}.\clength{}. +\item +\emph{addr} $<$ \emph{cb}.\cbase{}. +\end{itemize} + +An address error during load (AdEL) exception is raised if: + +\begin{itemize} +\item +The virtual address \emph{addr} is not \emph{capability\_size} aligned. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +\emph{offset} is interpreted as a signed integer. +\item +The \insnmipsref{CLShCI} mnemonic is equivalent to \insnmipsref{CLShC} with +\emph{cb} being the zero register (\$zero). The \insnmipsref{CLShCR} mnemonic +is equivalent to \insnmipsref{CLShC} with \emph{offset} set to +zero. +\item +Although the \emph{short\_capability\_size} may vary, the offset is always in +multiples of 8 bytes (64 bits). +\item +See \cref{sec:windowedshortcaps} for details of short capabilities. In +particular, note that several permissions are not transported in short +capabilities. +\end{itemize} diff --git a/insn-mips/cmove.tex b/insn-mips/cmove.tex new file mode 100644 index 00000000..1c206ed9 --- /dev/null +++ b/insn-mips/cmove.tex @@ -0,0 +1,31 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetAddr} +\insnmipslabel{cmove} +\subsection*{CMove: Move Capability to another Register} + +\subsubsection*{Format} + +CMove cd, cb + +\begin{center} +\cheritwoop[header]{0xa}{cd}{cb} +\end{center} + +\subsubsection*{Description} + +\insnnoref{CMove} copies \emph{cb} into \emph{cd}. + +\subsubsection*{Semantics} + +\sailMIPScode{CMove} + +\subsubsection*{Notes} + +\begin{itemize} +\item This instruction currently has a dedicated encoding but it could also be implemented as an alias for \insnmipsref{CMOVZ} \emph{\$zero}, \emph{cd}, \emph{cb}. \arnote{This is not possible on RISC-V since there is no conditional move. Should we add a note about this?} +\item Originally, \insnmipsref{CMove} was an assembler pseudo for \insnmipsref{CIncOffset} \emph{cd}, \emph{cb}, \emph{\$zero}. +However, this requires that \insnmipsref{CIncOffset} with a sealed capability succeeds if the increment is zero. +A future version of the ISA might no longer support this and require the use of \insnmipsref{CMove} for sealed capabilities. +This would allow for a simpler implementation of \insnmipsref{CIncOffset} where the behavior does not depend on one of the input values. \arnote{Some more rationale about intentionality?} +\end{itemize} diff --git a/insn-mips/cmovn.tex b/insn-mips/cmovn.tex new file mode 100644 index 00000000..ad267b12 --- /dev/null +++ b/insn-mips/cmovn.tex @@ -0,0 +1,49 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CMOVZ / CMOVN} +\insnmipslabel{cmovn} +\subsection*{CMOVZ / CMOVN: Conditionally Move Capability on Zero / Non-Zero} + +\subsubsection*{Format} + +CMOVN cd, cb, rt + +\begin{center} +\cherithreeop[header]{0x1c}{cd}{cb}{rt} +\end{center} + +\phantomsection +\insnmipslabel{cmovz} +CMOVZ cd, cb, rt + +\begin{center} +\cherithreeop[header]{0x1b}{cd}{cb}{rt} +\end{center} + +\subsubsection*{Description} + +CMOVZ copies \emph{cb} into \emph{cd} if \emph{rt} $=$ 0. \\ +CMOVN copies \emph{cb} into \emph{cd} if \emph{rt} $\neq$ 0. \\ + +\subsubsection*{Semantics} + +\sailMIPScode{CMOVX} + +\subsubsection*{Notes} + +\begin{itemize} +\item +In the Sail code {\tt ismovn} is true for \insnmipsref{CMOVN}, thus inverting the condition (via exclusive-or) in that case. +\item +Some implementations of cryptographic algorithms need a constant-time move +operation to avoid revealing secret key material through a timing channel. +(An attacker must not be able to determine whether a condition variable +inside the cryptographic implementation is true or false from observations +of how long the operation took to complete). In the current prototype +implementation of CHERI, no guarantees are made about \insnmipsref{CMOVN} +being constant time. + +If CHERI instructions are to be used in high-security cryptographic +processors, consideration should be given to making this operation +constant time. +\end{itemize} diff --git a/insn-mips/cptrcmp.tex b/insn-mips/cptrcmp.tex new file mode 100644 index 00000000..7c62834d --- /dev/null +++ b/insn-mips/cptrcmp.tex @@ -0,0 +1,170 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CPtrCmp: CEQ, CNE, CL[TE][U], CEXEQ} +\insnmipslabel{cptrcmp} +\insnmipslabel{ceq} +\insnmipslabel{cne} +\insnmipslabel{clt} +\insnmipslabel{cle} +\insnmipslabel{cltu} +\insnmipslabel{cleu} +\insnmipslabel{cexeq} +\insnmipslabel{cnexeq} +\subsection*{CPtrCmp: CEQ, CNE, CL[TE][U], CEXEQ, CNEXEQ: Capability Pointer Compare} + +\subsubsection*{Format} + +CEQ rd, cb, ct \\ +CNE rd, cb, ct \\ +CLT rd, cb, ct \\ +CLE rd, cb, ct \\ +CLTU rd, cb, ct \\ +CLEU rd, cb, ct \\ +CEXEQ rd, cb, ct \\ +CNEXEQ rd, cb, ct \\ +\cherithreeop[header]{\emph{op}}{rd}{cb}{ct} + +\subsubsection*{Description} + +Capability registers \emph{cb} and \emph{ct} are compared, and the result +of the comparison is placed in integer register \emph{rd}. +The rules for comparison are as follows: + +\begin{itemize} +\item For all operations except \insnmipsref{CExEq} and \insnmipsref{CNExEq}, +the result of comparison is the result of comparing \emph{cb}.\caddr{} with \emph{ct}.\caddr{}. +Numerical comparison is signed for \insnmipsref{CLT} and \insnmipsref{CLE}, +and unsigned for \insnmipsref{CLTU} and \insnmipsref{CLEU}. +\item +\insnmipsref{CExEq} and \insnmipsref{CNExEq} compare all the fields of the two +capabilities, including \ctag{} and the bits that are reserved for future use. +\end{itemize} + +This instruction can be used to compare capabilities so that capabilities can +replace pointers in C executables. + + +\begin{figure}[h] +\begin{center} +\begin{tabular}{l|l|l} +Mnemonic & \emph{op} & Comparison \\ \hline +\insnmipsref{CEQ} & 0x14 & = \\ +\insnmipsref{CNE} & 0x15 & $\neq$ \\ +\insnmipsref{CLT} & 0x16 & $<$ (signed) \\ +\insnmipsref{CLE} & 0x17 & $\le$ (signed) \\ +\insnmipsref{CLTU} & 0x18 & $<$ (unsigned) \\ +\insnmipsref{CLEU} & 0x19 & $\le$ (unsigned) \\ +\insnmipsref{CEXEQ} & 0x1a & all fields are equal \\ +\insnmipsref{CNEXEQ} & 0x21 & not all fields are equal \\ +\end{tabular} +\end{center} +\end{figure} + +\subsubsection*{Semantics} +\sailMIPScode{CPtrCmp} + +\subsubsection*{Exceptions} + +A reserved instruction exception is raised if + +\begin{itemize} +\item +\emph{op} does not correspond to comparison operation whose meaning has been +defined. (All possible values of \emph{op} have now been assigned meanings, +so this exception cannot occur). +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +\insnmipsref{CLTU} can be used by a C compiler to compile code that +compares two non-NULL pointers (e.g., to detect whether a pointer to a character +within a buffer has reached the end of the buffer). When two pointers to +addresses within the same object (e.g., to different offsets within an array) +are compared, the pointer to the earlier part of the object will be compared +as less. (Signed comparison would also work as long as the object did not span + address $2^{63}$; the MIPS address space layout makes it unlikely that +objects spanning $2^{63}$ will exist in user-space C code). +\item +Although the ANSI C standard does not specify whether a NULL +pointer is less than or greater than a non-NULL pointer (clearly, they must +not be equal), the comparison instructions have been designed so that when +C pointers are represented by capabilities, NULL will be less than any +non-NULL pointer. +\item +A C compiler may also use these instructions to compare two values of +type \ccode{uintptr\_t} that have been obtained by casting from +an integer value. If the cast is compiled as a \insnmipsref{CFromPtr} of +zero followed by \insnmipsref{CSetOffset} to the integer value, the +result of \insnmipsref{CPtrCmp} will be the same as comparing the original +integer values, because \insnmipsref{CFromPtr} will have set \cbase{} to +zero. Signed and unsigned capability comparison operations are provided so +that both signed and unsigned integer comparisons can be performed on +capability registers. +\item +A program could use pointer comparison to determine the value of +\cbase{}, by setting \coffset{} to different values and testing which values +cause \cbase{} $+$ \coffset{} to wrap around and be less than \cbase{} $+$ +a zero offset. This is not an attack against a security property of the ISA, +because \cbase{} is not a secret. +\item +One possible way in which garbage collection could be implemented is for the +garbage collector to move an object and fix up all capabilities that refer +to it. If there are appropriate restrictions on which capabilities the program +has to start with, the garbage collector can be sure that the program does +not have any references to the object stored as integers, and so can know +that it is safe to move the object. With this type of garbage collection, +comparing pointers by extracting their base and offset with +\insnmipsref{CGetBase} and \insnmipsref{CGetOffset} and comparing the +integer values is not guaranteed to work, because the garbage collector +might have moved the object part-way through. \insnmipsref{CPtrCmp} is +atomic, and so will work in this scenario. +\item +Some compilers may make the optimization that if a check for (\emph{a} $=$ +\emph{b}) has succeeded, then \emph{b} can be replaced with \emph{a} without +changing the semantics of the program. This optimization is not valid +for the comparison performed by \insnmipsref{CEq}, because two capabilities +can point to the same place in memory but have different bounds, permissions +etc. and so not be interchangeable. The \insnmipsref{CExEq} instruction is +provided for when a test for semantic equivalence of capabilities is +needed; it compares all the fields, even the ones that are reserved for +future use. +\item +Mathematically, \insnmipsref{CEq} divides capabilities into +\emph{equivalence classes}, and the signed or unsigned comparison operators +provide a \emph{total ordering} on these equivalence classes. +\insnmipsref{CExEq} also divides capabilities into equivalence classes, +but these are not totally ordered: two capabilities can be unequal according +to \insnmipsref{CExEq}, and also neither less or greater according to +\emph{CLT} (e.g., if they have the same \cbase{} $+$ \coffset{}, but different +\clength{}). +\item +There is an outstanding issue: when capability compression is in use, does +\insnmipsref{CExEq} compare the compressed representation or the uncompressed +capability? There might be a difference between the two if there are multiple +compressed representations that decompress to the same thing. If +\ctag{} is false, then then capability register might contain non-capability +data (e.g., an integer, or a string) and it might not decompress to anything +sensible. Clearly in this case the in-memory compressed representation should +be compared bit for bit. Is it also acceptable to compare the compressed +representations when \ctag{} is true? This might lead to two capabilities that +are sematically equivalent but have been computed by a different sequence +of operations comparing as not equal. The consequence of this for programs +that use \insnmipsref{CExEq} is for further study. +\item +If a C compiler compiles pointer equality as \insnmipsref{CExEq} (rather than +\insnmipsref{CEq}), it will catch the following example of undefined +behavior. Suppose that \emph{a} and \emph{b} are capabilities for different +objects, but \emph{a} has been incremented until its \cbase{} $+$ \coffset{} +points to the same memory location as \emph{b}. Using \insnmipsref{CExEq}, +these pointers will not compare as equal because they have different bounds. +\item +\insnmipsref{CNE} and \insnmipsref{CNExEq} are in principle redundant, +because a compiler could replace \insnmipsref{CNE} and a conditional branch +with \insnmipsref{CEq} and a conditional branch with the opposite condition +(and if the result of the comparison is assigned to a variable, the compiler +could explictly negate the result of \insnmipsref{CEq}, at a small performance +penalty). We provide explicit tests for not equal in order to simplify the +compiler back end. +\end{itemize} diff --git a/insn-mips/cram.tex b/insn-mips/cram.tex new file mode 100644 index 00000000..e947f5d7 --- /dev/null +++ b/insn-mips/cram.tex @@ -0,0 +1,34 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CRepresentableAlignmentMask} +\insnmipslabel{cram} +\insnmipslabel{crepresentablealignmentmask} +\subsection*{CRepresentableAlignmentMask: Retrieve Mask to Align Capabilities to Precisely Representable Address} + +\subsubsection*{Format} + +CRepresentableAlignmentMask rt, rs + +\begin{center} +\cheritwoop[header]{0x11}{rt}{rs} +\end{center} + +\subsubsection*{Description} + +\emph{rt} is set to a mask that can be used to align down addresses to a value that is sufficiently aligned to set precise bounds for the nearest representable length of \emph{rs} (which may be obtained using the instruction \insnmipsref{CRoundRepresentableLength}). +\arnote{TODO: this description is pretty terrible} + +\subsubsection*{Semantics} + +\sailMIPScode{CRAM} + +\subsubsection*{Notes} + +\begin{itemize} +\item The result of \insnmipsref{CRepresentableAlignmentMask} is intended to be used as the mask argument to \insnmipsref{CAndAddr} in order to create a capability with an address that is sufficiently aligned to perform \insnmipsref{CSetBoundsExact} with the specified length. This \insnmipsref{CSetBoundsExact} is guaranteed to succeed if the size is rounded using \insnmipsref{CRoundRepresentableLength}. +\item The required alignment of an allocation of size \emph{rs} can be computed by negating \emph{rt} and adding one. +\item Combined with \insnmipsref{CRoundRepresentableLength} this instruction can be used in memory allocators to guarantee non-overlapping allocations. +\item This instruction can be useful to adjust the stack pointer to an address that is suitably aligned for dynamic allocations. +\item An alternative to this instruction is the use of count-leading-zeroes and count-trailing-zeros instructions followed by shifting and masking. However, this requires encoding knowledge of the underlying precision in the resulting binary and can therefore result in incompatibilities with future architectures that use a different compression algorithm. +\end{itemize} + diff --git a/insn-mips/creadhwr.tex b/insn-mips/creadhwr.tex new file mode 100644 index 00000000..7cf232fa --- /dev/null +++ b/insn-mips/creadhwr.tex @@ -0,0 +1,79 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CReadHwr} +\insnmipslabel{creadhwr} +\subsection*{CReadHwr: Read a Special-Purpose Capability Register} + +\subsubsection*{Format} + +CReadHwr cd, selector + +\begin{center} +\cheritwoop[header]{0xd}{cd}{selector} +\end{center} + +\subsubsection*{Description} + +Load the value of special-purpose capability register \emph{selector} +into capability register \emph{cd}. +See \autoref{tab:creadhwr-permissions} for the possible values of +\emph{selector} and the permissions required in order to read the register. + +% TODO: move this to the preamble? +\newcommand{\KernelAndAccessSysRegs}{ +\begin{tabular}[c]{@{}l@{}}Supervisor Mode and\\ +\PCC{}.\cperms{}.\emph{Access\_System\_Registers} +\end{tabular} +} + +\begin{table}[h] +\centering +\caption{Access permission required to read special-purpose capability registers} +\label{tab:creadhwr-permissions} +\begin{tabular}{cll@{}} +\toprule +& \textbf{Register}& \textbf{Required for read access} \\ +\midrule + +\textbf{0} & Default data capability (\DDC) & $\emptyset$ \\ +\textbf{1} & User TLS (\CULR{}) & $\emptyset$ \\ +%\textbf{2} & \ajnote{\PCC - make this CGetPCC} & $\emptyset$ \\[1.5em] + +% \textbf{7} & Program counter capability (\PCC) & $\emptyset$ \\[1.5em] + + +\textbf{8} & Privileged TLS (\CPLR{}) & \PCC{}.\cperms{}.\emph{Access\_System\_Registers} \\ + +\textbf{22} & Kernel scratch register 1 (\KRC) & \KernelAndAccessSysRegs \\ +\textbf{23} & Kernel scratch register 2 (\KQC) & \KernelAndAccessSysRegs \\ + +\textbf{28} & Error exception program counter (\ErrorEPCC) & \KernelAndAccessSysRegs \\ +\textbf{29} & Kernel code capability (\KCC) & \KernelAndAccessSysRegs \\ +\textbf{30} & Kernel data capability (\KDC) & \KernelAndAccessSysRegs \\ +\textbf{31} & Exception program counter (\EPCC) & \KernelAndAccessSysRegs \\ +\bottomrule +\end{tabular} +\end{table} + +\note{rmn30}{currently this table is the same for read and write but need not be (e.g. rdhwr on MIPS has a register that can be written by kernel but only read by user)} + +\subsubsection*{Semantics} +\sailMIPScode{CReadHwr} + +\subsubsection*{Exceptions} + + +A reserved Instruction exception is raised for unknown or +unimplemented values of \emph{selector}. + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item the permission checks as specified in \autoref{tab:creadhwr-permissions} above were not met for \emph{selector} +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item In the future we may decide to make \PCC{} accessible via this instruction. This would save opcode space since we would no longer required a dedicated \insnmipsref{CGetPCC} instruction. +\end{itemize} diff --git a/insn-mips/crrl.tex b/insn-mips/crrl.tex new file mode 100644 index 00000000..3e97fbd2 --- /dev/null +++ b/insn-mips/crrl.tex @@ -0,0 +1,30 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CRoundRepresentableLength} +\insnmipslabel{crrl} +\insnmipslabel{croundrepresentablelength} +\subsection*{CRoundRepresentableLength: Round to Next Precisely Representable Length} + +\subsubsection*{Format} + +CRoundRepresentableLength rt, rs + +\begin{center} +\cheritwoop[header]{0x10}{rt}{rs} +\end{center} + +\subsubsection*{Description} + +\emph{rt} is set to the smallest value greater or equal to \emph{rs} that can be used by \insnmipsref{CSetBoundsExact} without trapping (assuming a suitably aligned base). + +\subsubsection*{Semantics} + +\sailMIPScode{CRAP} + +\subsubsection*{Notes} + +\begin{itemize} +\item This instruction is useful when implementing allocators to round up allocation sizes to a size that can be precisely bounded (and will therefore not overlap with any other allocations). It is also useful when using \ccode{mmap()}, since the requested size must be a precisely representable length. +\item An alternative to this instruction is the use of count-leading-zeroes and count-trailing-zeros instructions followed by shifting and masking. However, this requires encoding knowledge of the underlying precision in the resulting binary and can therefore result in incompatibilities with future architectures that use a different compression algorithm. +\item If the length has to be rounded up to $2^{64}$ then this instruction will return zero. This could happen for very large lengths that span most of the address space. Software must be careful to account for this, especially if the length comes from an untrusted source. +\end{itemize} diff --git a/insn-mips/cs.tex b/insn-mips/cs.tex new file mode 100644 index 00000000..b229bf08 --- /dev/null +++ b/insn-mips/cs.tex @@ -0,0 +1,103 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CS[BHWD]} +\insnmipslabel{csbhwd} +\subsection*{CS[BHWD]: Store Integer via Capability} + +\subsubsection*{Format} + +CSB rs, rt, offset(cb)\\ +CSH rs, rt, offset(cb)\\ +CSW rs, rt, offset(cb)\\ +CSD rs, rt, offset(cb)\\ +CSBR rs, rt(cb)\\ +CSHR rs, rt(cb)\\ +CSWR rs, rt(cb)\\ +CSDR rs, rt(cb)\\ +CSBI rs, offset(cb)\\ +CSHI rs, offset(cb)\\ +CSWI rs, offset(cb)\\ +CSDI rs, offset(cb)\\ + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,1,3,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x3A} +\bitbox{5}{rs} +\bitbox{5}{cb} +\bitbox{5}{rt} +\bitbox{8}{offset} +\bitbox{1}{0} +\bitbox{2}{t} +\end{bytefield} +\end{center} + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Purpose} + +Stores some or all of a register into a memory location. + +\subsubsection*{Description} + +Part of integer register \emph{rs} is stored to the memory location specified by +\emph{cb.\cbase{}} + \emph{cb.\coffset{}} + \emph{rt} + $2^t$ $*$ \emph{offset}. +Capability register \emph{cb} must contain a capability that grants permission +to store data. + +The \emph{t} field determines how many bits of the register are stored to memory: + +\begin{description} + \item[0] byte (8 bits) + \item[1] halfword (16 bits) + \item[2] word (32 bits) + \item[3] doubleword (64 bits) +\end{description} + +If less than 64 bits are stored, they are taken from the least-significant +end of the register. + +\subsubsection*{Semantics} +\sailMIPScode{CStore} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\cchecktag{} +\item +\emph{cb} is sealed. +\item +\emph{cb}.\cperms.\emph{Permit\_Store} is not set. +\item +\emph{addr} $+$ \emph{size} $>$ \emph{cb}.\cbase{} $+$ \emph{cb}.\clength{}. +\item +\emph{addr} $<$ \emph{cb}.\cbase{} +\end{itemize} + +An address error during store (AdES) is raised if: + +\begin{itemize} +\item +\emph{addr} is not aligned. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +This instruction reuses the opcode from the Store Word from Coprocessor 2 +(\insnnoref{SWC2}) instruction in the MIPS Specification. +\item +\emph{rt} is treated as an unsigned integer. +\item +\emph{offset} is treated as a signed integer. +% \item +% The computation of \emph{addr} does not wrap around modulo $2^{64}$. +\item +BERI1 has a compile-time option to allow unaligned loads and stores. If BERI1 +is built with this option, an unaligned store will only raise an exception if +it crosses a cache line boundary. +\end{itemize} diff --git a/insn-mips/csc.tex b/insn-mips/csc.tex new file mode 100644 index 00000000..717e5407 --- /dev/null +++ b/insn-mips/csc.tex @@ -0,0 +1,131 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSC} +\insnmipslabel{csc} +\subsection*{CSC: Store Capability via Capability} + +\subsubsection*{Format} + +CSC cs, rt, offset(cb) \\ +CSCR cs, rt(cb) \\ +CSCI cs, offset(cb) + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x3e} +\bitbox{5}{cs} +\bitbox{5}{cb} +\bitbox{5}{rt} +\bitbox{11}{offset} +\end{bytefield} +\end{center} + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Description} + +Capability register \emph{cs} is stored at the memory location specified by +\emph{cb.\cbase{}} $+$ \emph{cb.\coffset{}} $+$ \emph{rt} $+$ 16 $*$ \emph{offset}, +and the bit in the tag memory associated with \emph{cb.\cbase{}} $+$ +\emph{cb.\coffset{}} $+$ \emph{rt} $+$ 16 $*$ \emph{offset} is set to the value of +\emph{cs.tag}. +Capability register \emph{cb} must +contain a capability that grants permission to store capabilities. The virtual +address \emph{cb.\cbase{}} $+$ \emph{cb.\coffset{}} $+$ \emph{rt} $+$ +16 $*$ \emph{offset} must be \emph{capability\_size} aligned. + +% When the 256-bit representation of capabilities is in use, the capability +% is stored in memory in the format described in Figure +% \ref{fig:memory-representation-of-a-capability}. +% \cbase{}, \clength{} and \cotype{} are +% stored in memory with the same endian-ness that the CPU uses for double-word +% stores, i.e., big-endian. The bits of \cperms{} are stored with bit zero +% being the least significant bit, so that the least significant bit of the +% eighth byte stored is the \csealed{} bit, +% the next significant bit is the \emph{Global} bit, the next is +% \emph{Permit\_Execute} and so on. + +The various capability encoding schemes define bit representations in +memory. While a given instantiation of CHERI will use a particular scheme, +software should, in general, not attempt to parse capability bit patterns +from memory. Instructions for capability interrogation (e.g., +\insnmipsref{CGetAddr}, \insnmipsref{CGetType}) do not require that their +source registers be holding \emph{tagged} capabilities; software wishing to +decode memory bit patterns should rather use \insnmipsref{CLC} and +interrogate the result. + +\subsubsection*{Semantics} +\sailMIPScode{CSC} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\cchecktag{} +\item +\emph{cb} is sealed. +\item +\emph{cb}.\cperms.\emph{Permit\_Store} is not set. +\item +\emph{cb.\cperms.Permit\_Store\_Capability} is not set. +\item +\emph{cb.\cperms{}.Permit\_Store\_Local} is not set and +\emph{cs.tag} is set and \emph{cs.\cperms{}.Global} is not set. +\item +\emph{addr} $+$ \emph{capability\_size} $>$ \emph{cb}.\cbase{} +$+$ \emph{cb.\clength{}}. +\item +\emph{addr} $<$ \emph{cb}.\cbase{}. +\end{itemize} + +\noindent +A TLB Store exception is raised if: + +\begin{itemize} +\item +\emph{cs.\ctag{}} is set and the \emph{S} bit in the TLB entry for the page +containing \emph{addr} is not set. +\end{itemize} + +\noindent +An address error during store (AdES) exception is raised if: + +\begin{itemize} +\item +The virtual address \emph{addr} is not \emph{capability\_size} aligned. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +If the address alignment check fails and one of the security checks fails, +a coprocessor 2 exception (and not an address error exception) is raised. +The priority of the exceptions is security-critical, because otherwise a +malicious program could use the type of the exception that is raised to +test the bottom bits of a register that it is not permitted to access. +\item +It is permitted to store a local capability with the tag bit unset even if the permit store local bit is not set in \emph{cb}. +This is because if the tag bit is not set then the permissions have no meaning. +\item +\emph{offset} is interpreted as a signed integer. +\item +This instruction reuses the opcode from the Store Doubleword from Coprocessor 2 +(\insnnoref{SDC2}) instruction in the MIPS Specification. +\item +The \insnnoref{CSCI} mnemonic is equivalent to \insnmipsref{CSC} with +\emph{cb} being the zero register (\$zero). The \insnnoref{CSCR} mnemonic +is equivalent to \insnmipsref{CSC} with \emph{offset} set to zero. +\item +BERI1 has a compile-time option to allow unaligned loads and stores. +\insnmipsref{CSC} to an unaligned address will raise an exception even if +BERI1 has been built with this option, because it would be a security +vulnerability if an attacker could construct a corrupted capability with +\ctag{} set by writing it to an unaligned address. +\item +Although the \emph{capability\_size} can vary, the offset is always in +multiples of 16 bytes (128 bits). +\end{itemize} diff --git a/insn-mips/cscbhwd.tex b/insn-mips/cscbhwd.tex new file mode 100644 index 00000000..b97ae672 --- /dev/null +++ b/insn-mips/cscbhwd.tex @@ -0,0 +1,38 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSC[BHWD]} +\insnmipslabel{cscbhwd} +\insnmipslabel{cscb} +\insnmipslabel{csch} +\insnmipslabel{cscw} +\insnmipslabel{cscd} +\subsection*{CSC[BHWD]: Store Conditional Integer via Capability} + +\subsubsection*{Format} + +CSCB rd, rs, cb \\ +CSCH rd, rs, cb \\ +CSCW rd, rs, cb \\ +CSCD rd, rs, cb + + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,1,2,3,4,5,6,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x10} +\bitbox{5}{rs} +\bitbox{5}{cb} +\bitbox{5}{rd} +\bitbox{2}{\color{lightgray}\rule{\width}{\height}} +\bitbox{2}{00} +\bitbox{2}{t} +\end{bytefield} +\end{center} + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Semantics} +\sailMIPScode{CStoreConditional} + + diff --git a/insn-mips/cscc.tex b/insn-mips/cscc.tex new file mode 100644 index 00000000..ef8d1e51 --- /dev/null +++ b/insn-mips/cscc.tex @@ -0,0 +1,67 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSCC} +\insnmipslabel{cscc} +\subsection*{CSCC: Store Conditional Capability via Capability} + +\subsubsection*{Format} + +CSCC rd, cs, cb + + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,2,3,5,6,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x10} +\bitbox{5}{cs} +\bitbox{5}{cb} +\bitbox{5}{rd} +\bitbox{2}{\color{lightgray}\rule{\width}{\height}} +\bitbox{4}{0111} +\end{bytefield} +\end{center} +\usesDDCinsteadofNULL{cb} + +% \textbf{TO DO: Describe what this instruction does.} + +\subsubsection*{Semantics} +\sailMIPScode{CSCC} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cb}.\ctag{} is not set. +\item +\emph{cb} is sealed. +\item +\emph{cb}.\cperms.\emph{Permit\_Store} is not set. +\item +\emph{cb}.\cperms{}.\emph{Permit\_Store\_Capability} is not set. +\item +\emph{cb}.\cperms{}.\emph{Permit\_Store\_Local\_Capability} is not set +and \emph{cs}.\cperms.\emph{Global} is not set. +\item +\emph{addr} $+$ \emph{capability\_size} $>$ +\emph{cb}.\cbase{} $+$ \emph{cb}.\clength{} +\item +\emph{addr} $<$ \emph{cb}.\cbase{} +\end{itemize} + +A TLB Store exception is raised if: + +\begin{itemize} +\item +The \emph{S} bit in the TLB entry corresponding to virtual address +\emph{addr} is not set. +\end{itemize} + +An address error during store (AdES) exception is raised if: + +\begin{itemize} +\item +\emph{addr} is not correctly aligned. +\end{itemize} diff --git a/insn-mips/cseal.tex b/insn-mips/cseal.tex new file mode 100644 index 00000000..5737adfc --- /dev/null +++ b/insn-mips/cseal.tex @@ -0,0 +1,67 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSeal} +\insnmipslabel{cseal} +\subsection*{CSeal: Seal a Capability} + +\subsubsection*{Format} + +CSeal cd, cs, ct + +\begin{center} +\cherithreeop[header]{0xb}{cd}{cs}{ct} +\end{center} + +\subsubsection*{Description} + +Capability register \emph{cs} is sealed +\psnote{it's confusing phrasing to say the \emph{register} itself is sealed, as +opposed to the value the register. Instead, perhaps ``The capability + in register \emph{cs} is sealed''? I guess this idiom may occur in + many places, so I've not just fixed this one. Robert N-W?} + with an \cotype{} of +\emph{ct}.\cbase{} $+$ \emph{ct}.\coffset{} +and the result is placed in \emph{cd}: + +\begin{itemize} +\item +\emph{cd}.\cotype{} is set to \emph{ct}.\cbase{} + \emph{ct}.\coffset{}; +\item +\emph{cd} is sealed; +\item +and the other fields of \emph{cd} are copied from \emph{cs}. +\end{itemize} + +\emph{ct} must grant \emph{Permit\_Seal} permission, and the new \cotype{} +of \emph{cd} must be between \emph{ct}.\cbase{} and \emph{ct}.\cbase{} $+$ +\emph{ct}.\clength{} $-$ 1. + +\subsubsection*{Semantics} +\sailMIPScode{CSeal} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cs}.\ctag{} is not set. +\item +\emph{ct}.\ctag{} is not set. +\item +\emph{cs} is sealed. +\item +\emph{ct} is sealed. +\item +\emph{ct}.\cperms.\emph{Permit\_Seal} is not set. +% \item +% \emph{ct}.\cperms.\emph{Permit\_Execute} is not set. +\item +\emph{ct}.\coffset{} $\ge$ \emph{ct}.length{} +\item +\emph{ct}.\cbase{} $+$ \emph{ct}.\coffset{} $> \emph{max\_otype}$ +\item +The bounds of \emph{cb} cannot be represented exactly in a sealed capability. +\end{itemize} + +\subsubsection*{Notes} diff --git a/insn-mips/csealentry.tex b/insn-mips/csealentry.tex new file mode 100644 index 00000000..bfd6256e --- /dev/null +++ b/insn-mips/csealentry.tex @@ -0,0 +1,37 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSealEntry} +\insnmipslabel{csealentry} +\subsection*{CSealEntry: Construct a Sentry Capability} + +\subsubsection*{Format} + +CSealEntry cd, cs + +\begin{center} +\cheritwoop[header]{0x1d}{cd}{cs} +\end{center} + +\subsubsection*{Description} + +Constructs a sentry capability from the unsealed, valid, +Permit\_Execute-bearing capability in register \emph{cs} and places the +result into capability register \emph{cd}. Recall \cref{sec:arch-sentry}. + +\subsubsection*{Semantics} +\sailMIPScode{CSealEntry} + +\subsubsection*{Exceptions} +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cs}.\ctag{} is not set. +\item +\emph{cs} is sealed. +\item +\emph{cs}.\cperms.\emph{Permit\_Execute} is not set. +\item +The bounds of \emph{cs} cannot be represented exactly in a sealed capability. +\end{itemize} + diff --git a/insn-mips/csetaddr.tex b/insn-mips/csetaddr.tex new file mode 100644 index 00000000..106d089d --- /dev/null +++ b/insn-mips/csetaddr.tex @@ -0,0 +1,40 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetAddr} +\insnmipslabel{csetaddr} +\subsection*{CSetAddr: Set the Address of Capability} + +\subsubsection*{Format} + +CSetAddr cd, cb, rt + +\begin{center} +\cherithreeop[header]{0x22}{cd}{cb}{rt} +\end{center} + +\subsubsection*{Description} + +\emph{cd} is set to \emph{cb} with \emph{cb}.\caddr{} set to \emph{rt}. +If changing the address causes the capability to become unrepresentable, then an untagged capability with the requested address is returned. + +\subsubsection*{Semantics} + +\sailMIPScode{CSetAddr} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cb}.\ctag{} is set and \emph{cb} is sealed. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item This instruction may be useful, in combination with \insnmipsref{CGetAddr}, when C is manipulating pointers in ways that require a round trip through integer registers. +\item This instruction is also useful for \ccode{uintptr\_t} arithmetic when using an address interpretation of capabilities. When interpreting \ccode{uintptr\_t} as offsets relative +to the base, the compiler will use \insnmipsref{CGetOffset} and \insnmipsref{CSetOffset} instead. + +\end{itemize} diff --git a/insn-mips/csetbounds.tex b/insn-mips/csetbounds.tex new file mode 100644 index 00000000..a1ba7c14 --- /dev/null +++ b/insn-mips/csetbounds.tex @@ -0,0 +1,83 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetBounds} +\insnmipslabel{csetbounds} +\subsection*{CSetBounds: Set Bounds} + +\subsubsection*{Format} + +CSetBounds cd, cb, rt + +\begin{center} +\cherithreeop[header]{0x8}{cd}{cb}{rt} +\end{center} + +\subsubsection*{Description} + +Capability register \emph{cd} is replaced with a capability that: + +\begin{itemize} +\item +Grants access to a subset of the addresses authorized by \emph{cb}. +That is, \emph{cd}.\cbase{} $\ge$ \emph{cb}.\cbase{} and +\emph{cd}.\cbase{} $+$ \emph{cd}.\clength{} $\le$ \emph{cb}.\cbase{} $+$ +\emph{cb}.\clength{}. +\item +Grants access to at least the addresses \emph{cb}.\cbase{} $+$ +\emph{cb}.\coffset{} $\ldots$ \emph{cb}.\cbase{} $+$ \emph{cb}.\coffset{} +$+$ \emph{rt} $-$ 1. +That is, \emph{cd}.\cbase{} $\le$ \emph{cb}.\cbase{} +$+$ \emph{cb}.\coffset{} and \emph{cd}.\cbase{} $+$ \emph{cd}.\clength{} +$\ge$ \emph{cb}.\cbase{} $+$ \emph{cb}.\coffset{} $+$ \emph{rt}. +\item +Has an \coffset{} that points to the same memory location as \emph{cb}'s +\coffset{}. +That is, \emph{cd}.\coffset{} = \emph{cb}.\coffset{} + \emph{cb}.\cbase{} - +\emph{cd}.\cbase{}. +\item +Has the same \cperms{} as \emph{cb}, that is, \emph{cd}.\cperms{} = \emph{cb}.\cperms{}. +\end{itemize} + +%When the hardware uses a 256-bit representation for capabilities, the bounds +%of the destination capability \emph{cd} are exactly as requested. +With compressed capabilities, not all combinations of \cbase{} and \clength{} +are representable. +\emph{cd} may therefore grant access to a range of memory addresses that is +wider than requested, but is still guaranteed to be within the bounds of +\emph{cb}. +\rwnote{Check that the following statement is true.} +This cannot occur if the requested bounds have been suitably aligned and +padded using the \insnmipsref{CRAM} and \insnmipsref{CRRL} instructions. +If software is not guaranteed to provide suitable alignment and padding, it +may be desirable to use \insnmipsref{CSetBoundsExact} so that an exception will +be thrown the requested bounds cannot be represented. + +\subsubsection*{Semantics} + +\sailMIPScode{CSetBounds} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\cchecktag{} +\item +\emph{cb} is sealed. +\item +\emph{cursor} $<$ \emph{cb}.\cbase{} +\item +\emph{cursor} $+$ \emph{rt} $>$ \emph{cb}.\cbase{} $+$ cb.\clength{} +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +In the above Sail code, arithmetic is over the mathematical integers and +\emph{rt} is unsigned, so a large value of \emph{rt} cannot cause +\emph{cursor} $+$ \emph{rt} to wrap around and be less than \emph{cb}.\cbase{}. +Implementations (that, for example, will probably use a fixed number of +bits to store values) must handle this overflow case correctly. +\end{itemize} diff --git a/insn-mips/csetboundsexact.tex b/insn-mips/csetboundsexact.tex new file mode 100644 index 00000000..8c15ee28 --- /dev/null +++ b/insn-mips/csetboundsexact.tex @@ -0,0 +1,57 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetBoundsExact} +\insnmipslabel{csetboundsexact} +\subsection*{CSetBoundsExact: Set Bounds Exactly} + +\subsubsection*{Format} + +CSetBoundsExact cd, cb, rt + +\begin{center} +\cherithreeop[header]{0x9}{cd}{cb}{rt} +\end{center} + +\subsubsection*{Description} + +Capability register \emph{cd} is replaced with a capability with its \cbase{} +replaced with \emph{cb}.\cbase{} $+$ \emph{cb}.\coffset{}, \clength{} set to +\emph{rt}, and \coffset{} set to zero. +When capability compression is in use, an exception is thrown if the requested +bounds cannot be represented exactly. + +\subsubsection*{Semantics} +\sailMIPScode{CSetBoundsExact} + +An exception cannot occur if the requested bounds have been suitably aligned +and padded using the \insnmipsref{CRAM} and \insnmipsref{CRRL} instructions. +If looser bounds, rather than exception, are desired, then it may be +preferable to use \insnmipsref{CSetBounds}. + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\cchecktag{} +\item +\emph{cb} is sealed. +\item +\emph{cursor} $<$ \emph{cb}.\cbase{} +\item +\emph{cursor} $+$ \emph{rt} $>$ \emph{cb}.\cbase{} $+$ cb.\clength{} +\item +The requested bounds cannot be represented exactly. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +In the above Sail code, arithmetic is over the mathematical integers and +\emph{rt} is unsigned, so a large value of \emph{rt} cannot cause +\emph{cursor} $+$ \emph{rt} to wrap around and be less than \emph{cb}.\cbase{}. +Implementations (that, for example, will probably use a fixed number of +bits to store values) must handle this overflow case correctly. +\end{itemize} diff --git a/insn-mips/csetboundsimm.tex b/insn-mips/csetboundsimm.tex new file mode 100644 index 00000000..2f07bc05 --- /dev/null +++ b/insn-mips/csetboundsimm.tex @@ -0,0 +1,87 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetBoundsImm} +\insnmipslabel{csetboundsimm} +\subsection*{CSetBoundsImm: Set Bounds (Immediate)} + +\subsubsection*{Format} + +CSetBounds cd, cb, length$_{imm}$ + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x14} +\bitbox{5}{cd} +\bitbox{5}{cb} +\bitbox{11}{length$_{imm}$} +\end{bytefield} +\end{center} + +\arnote{The assembler supports both CSetBounds and CSetBounds but I think we should always use CSetBoundsImm} + +\subsubsection*{Description} + +Capability register \emph{cd} is replaced with a capability that: + +\begin{itemize} +\item +Grants access to a subset of the addresses authorized by \emph{cb}. +That is, \emph{cd}.\cbase{} $\ge$ \emph{cb}.\cbase{} and +\emph{cd}.\cbase{} $+$ \emph{cd}.\clength{} $\le$ \emph{cb}.\cbase{} $+$ +\emph{cb}.\clength{}. +\item +Grants access to at least the addresses \emph{cb}.\cbase{} $+$ +\emph{cb}.\coffset{} $\ldots$ \emph{cb}.\cbase{} $+$ \emph{cb}.\coffset{} +$+$ \emph{length$_{imm}$} $-$ 1. +That is, \emph{cd}.\cbase{} $\le$ \emph{cb}.\cbase{} +$+$ \emph{cb}.\coffset{} and \emph{cd}.\cbase{} $+$ \emph{cd}.\clength{} +$\ge$ \emph{cb}.\cbase{} $+$ \emph{cb}.\coffset{} $+$ \emph{length$_{imm}$}. +\item +Has an \coffset{} that points to the same memory location as \emph{cb}'s +\coffset{}. +That is, \emph{cd}.\coffset{} = \emph{cb}.\coffset{} + \emph{cb}.\cbase{} - +\emph{cd}.\cbase{}. +\item +Has the same \cperms{} as \emph{cb}, that is, \emph{cd}.\cperms{} = \emph{cb}.\cperms{}. +\end{itemize} + +%When the hardware uses a 256-bit representation for capabilities, the bounds +%of the destination capability \emph{cd} are exactly as requested. + +With compressed capabilities, not all combinations of \cbase{} and \clength{} +are representable. +\emph{cd} may therefore grant access to a range of memory addresses that is +wider than requested, but is still guaranteed to be within the bounds of +\emph{cb}. + +\subsubsection*{Semantics} +\sailMIPScode{CSetBoundsImmediate} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\cchecktag{} +\item +\emph{cb} is sealed. +\item +\emph{cursor} $<$ \emph{cb}.\cbase{} +\item +\emph{cursor} $+$ \emph{length$_{imm}$} $>$ \emph{cb}.\cbase{} $+$ cb.\clength{} +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +In the above Sail code, arithmetic is over the mathematical integers and +\emph{length$_{imm}$} is unsigned, so a large value of \emph{length$_{imm}$} cannot cause +\emph{cursor} $+$ \emph{length$_{imm}$} to wrap around and be less than \emph{cb}.\cbase{}. +Implementations (that, for example, will probably use a fixed number of +bits to store values) must handle this overflow case correctly. +\item If this instruction is used with \creg{0} as the destination register, it can be used to assert that a given capability grants access to at least \emph{length$_{imm}$} bytes. An assembler pseudo instruction \insnmipsref{CAssertInBounds} is supported for this use case. +\end{itemize} diff --git a/insn-mips/csetcause.tex b/insn-mips/csetcause.tex new file mode 100644 index 00000000..00558762 --- /dev/null +++ b/insn-mips/csetcause.tex @@ -0,0 +1,42 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetCause} +\insnmipslabel{csetcause} +\subsection*{CSetCause: Set the Capability Exception Cause Register} + +\subsubsection*{Format} + +CSetCause rt + +\begin{center} +\cherioneop[header]{0x2}{rd} +\end{center} + +\subsubsection*{Description} + +The capability cause register value is set to the low 16 bits of integer +register \textit{rt}. + +\jhbnote{Should this instruction be removed? It was only + used/relevant for CCall selector 0.} + +\subsubsection*{Semantics} + +\sailMIPScode{CSetCause} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\PCC{}.\cperms{}.\emph{Access\_System\_Registers} is not set. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +\insnmipsref{CSetCause} does not cause an exception to be raised (unless +the permission check for \emph{Access\_System\_Registers} fails). +\end{itemize} diff --git a/insn-mips/csetcid.tex b/insn-mips/csetcid.tex new file mode 100644 index 00000000..f1c45507 --- /dev/null +++ b/insn-mips/csetcid.tex @@ -0,0 +1,96 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetCID} +\insnmipslabel{csetcid} +\subsection*{CSetCID: Set the Architectural Compartment ID} + +\subsubsection*{Format} + +CSetCID cb + +% +% XXXRW: Format and opcode still TODO. +\begin{center} +% XXXAR: 0x5 is currently the second available one-operand instruction +\cherioneop[header]{0x5}{cb} +\\ +\arnote{This encoding is not final -- do not implement} +\end{center} + +\subsubsection*{Description} + +Set the architectural Compartment ID (CID) to \emph{cb}.\cbase{} + +\emph{cb}.\coffset{} if \emph{cb} has the Permit\_Set\_CID permission and +\emph{cb}.\coffset{} is in range. +The CID can then be used by the microarchitecture to tag microarchitectural +state. +CIDs can be utilized in a similar style as ASID matching in TLBs to +determine in what context microarchitectural state can be used. +Typical use will be to prevent sharing where it could otherwise be used as a +high-bandwidth microarchitectural side channel between compartments with +confidentiality requirements -- for example, to limit the impact of +Spectre-style attacks~\cite{Kocher2018spectre}. + +\subsubsection*{Semantics} + +\sailMIPScode{CSetCID} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cb}.\cperms.\emph{Permit\_Set\_CID} is not set. +\item +\emph{addr} + 1 $>$ \emph{cb}.\cbase{} $+$ \emph{cb}.\clength{}. +\item +\emph{addr} $<$ \emph{cb}.\cbase{}. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item + The CID can be queried using the \insnmipsref{CGetCID} instruction. +\item + Although \insnmipsref{CSetCID} has no architectural side effects other than + setting an integer register with a compartment ID, the intent is that the + microarchitecture can be made aware of boundaries across which + microarchitectural side channels are less acceptable. + A key design goal for \insnmipsref{CSetCID} is to provide flexible + mechanism above which a range of software policies might be implemented. +\item + For example, the software supervisor might arrange that all compartments + have unique CIDs such that branch-predictor state cannot be shared. + Other policies might use the same CID for compartments between which strong + confidentiality requirements are not present -- e.g., where only integrity + or availability protection is required. +\item + We have chosen not to protect the architectural CID using + Access\_System\_Registers in order to support virtualizability of the domain + switcher -- and, in particular, to not require Access\_System\_Registers to + implement a domain switcher. + A new permission is used, together with bounds checks, such that ranges of + CIDs can be delegated when multiple domain switchers are in use. + For example, a set of CIDs might be reserved for domain-switch + implementations themselves, and then subranges delegated to individual + language runtimes or processes within the same address space. + Note that such a model could obligate two CID operations per domain switch + involving mutual distrust: one into the domain switcher, and a second out, + in order to not just protect the two endpoint domains from one another but + also the switcher. +\item + How to ensure that \insnmipsref{CSetCID} is not speculated past (e.g., in + the case of microarchitectural side-channel attacks such as Spectre) is a + critical question. + We recommend that \insnmipsref{CSetCID} be considered serialising, and that + the CID be set immediately on switcher entry, as well as again on switcher + exit. +\item + An alternative design choice would accept an integer general-purpose + register operand, \emph{rt}, as a second argument specifying the CID to + switch to. + This might be more consistent with the behavior of \insnmipsref{CGetCID}, + but also consume more opcode space. +\end{itemize} diff --git a/insn-mips/csetflags.tex b/insn-mips/csetflags.tex new file mode 100644 index 00000000..a8f29563 --- /dev/null +++ b/insn-mips/csetflags.tex @@ -0,0 +1,33 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetFlags} +\insnmipslabel{csetflags} +\subsection*{CSetFlags: Set Flags} + +\subsubsection*{Format} + +CSetFlags cd, cb, rt + +\begin{center} +\cherithreeop[header]{0xe}{cd}{cs}{rt} +\end{center} + +\subsubsection*{Description} + +Capability register \emph{cd} is replaced with the contents of capability +register \emph{cb} with the \cflags{} field set to bits 0 .. \emph{max\_flags} of +integer register \emph{rd}. + +\pdrnote{We should define max\_flags (although max\_otype is not defined either)} + +\subsubsection*{Semantics} +\sailMIPScode{CSetFlags} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cb} is sealed. +\end{itemize} diff --git a/insn-mips/csetoffset.tex b/insn-mips/csetoffset.tex new file mode 100644 index 00000000..a9a830e1 --- /dev/null +++ b/insn-mips/csetoffset.tex @@ -0,0 +1,70 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetOffset} +\insnmipslabel{csetoffset} +\subsection*{CSetOffset: Set Cursor to an Offset from Base} + +\subsubsection*{Format} + +CSetOffset cd, cs, rt + +\begin{center} +\cherithreeop[header]{0xf}{cd}{cs}{rt} +\end{center} + +\subsubsection*{Description} + +Capability register \emph{cd} is replaced with the contents of capability +register \emph{cs} with the \coffset{} field set to the contents of integer +register \textit{rt}. + +If capability compression is in use, and the requested \cbase{}, \clength{} +and \coffset{} cannot be represented exactly, then \emph{cd}.\ctag{} is +cleared, \emph{cd}.\cbase{} and \emph{cd}.\clength{} are set to zero, +\emph{cd}.\cperms{} is cleared and \emph{cd}.\coffset{} is set equal to +\emph{cs}.\cbase $+$ \emph{rt}. + +\subsubsection*{Semantics} + +\sailMIPScode{CSetOffset} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cs}.\ctag{} is set and \emph{cs} is sealed. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +\insnmipsref{CSetOffset} can be used on a capability register whose tag bit +is not set. This can be used to store an integer value in a capability register, +and is useful when implementing a variable that is a union of a capability +and an integer (\ccode{intcap\_t} in C). +% The in-memory representation +% that will be used if the capability register is stored to memory might +% be surprising to some users (with the 256-bit representation of capabilities, +% \cbase{} $+$ \coffset{} is stored in the +% {\bf cursor} field in memory) and may change if the memory representation of +% capabilities changes, so compilers should not rely on it. +\item +With compressed capabilities, the requested offset may not not +representable. +In this case, the result preserves the requested \cbase{} $+$ \coffset{} +(i.e., the cursor) rather than the architectural field \coffset{}. This +field is mainly useful for debugging what went wrong (the capability cannot +be dereferenced, as \ctag{} has been cleared), and for debugging we considered +it more useful to know what the requested capability would have referred to +rather than its \coffset{} relative to a \cbase{} that is no longer available. +This has the disadvantage that it exposes the value of \cbase{} to a program, +but \cbase{} is not a secret and can be accessed by other means. The +main reason for not exposing \cbase{} to programs is so that a garbage +collector can stop the program, move memory, modify the capabilities and +restart the program. A capability with \ctag{} cleared cannot be dereferenced, +and so is not of interest to a garbage collector, and so it doesn't matter +if it exposes \cbase{}. +\end{itemize} diff --git a/insn-mips/csshc.tex b/insn-mips/csshc.tex new file mode 100644 index 00000000..a41ba0fa --- /dev/null +++ b/insn-mips/csshc.tex @@ -0,0 +1,120 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSShC} +\insnmipslabel{csshc} +\subsection*{CSShC: Store Short Capability via Capability} + +\subsubsection*{Format} + +CSShC cs, rt, offset(cb) \\ +CSShCR cs, rt(cb) \\ +CSShCI cs, offset(cb) + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Description} + +Capability register \emph{cs} is encoded to a short capability form and +stored at the memory location specified by +% +\emph{addr} $\stackrel{\Delta}{=}$ \emph{cb.\cbase{}} $+$ \emph{cb.\coffset{}} $+$ \emph{rt} $+$ 16 $*$ +\emph{offset}, +% +provided \emph{addr} is suitably aligned for short capabilities. +% +Capability register \emph{cb} must contain a capability that grants +permission to store capabilities. +% +The bits in the tag memory associated with \emph{addr} are updated to +indicate a short capability resides at this location if \emph{cs.\ctag{}} is +set and encoding was successful. See \cref{sec:windowedshortcaps} for +possible tag representations. + +\subsubsection*{Encoding} + +As per \cref{sec:windowedshortcaps}, several properties must hold of the +capabilities given to \insnmipsref{CSShC} for a successful store to take +place: + +\begin{itemize} + \item \emph{cs} may be out of bounds by strictly less than 4 GiB. + \item The bounds of \emph{cs} must be representable in short capabilities. + \item If \emph{cs} is sealed, its \cotype{} must be representable in short + capabilities. +\end{itemize} + +If any of the above tests fail, the store will take place but will update +the tags corresponding to \emph{addr} to indicate that the memory contains +data. + +Further, the following permission bits may not be stored in the short +capability format, and may read back (via \insnmipsref{CLShC}) as false: +Permit\_Seal, Permit\_Unseal, Permit\_SetCID, +Permit\_Access\_System\_Registers, and Permit\_Store\_Local\_Capability. +Software must, however, not depend on \insnmipsref{CSShC} to clear these +bits; an \insnmipsref{CAndPerm} must be used to ensure that these rights +are discarded. + +% \subsubsection*{Semantics} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\cchecktag{} +\item +\emph{cb} is sealed. +\item +\emph{cb}.\cperms.\emph{Permit\_Store} is not set. +\item +\emph{cb.\cperms.Permit\_Store\_Capability} is not set. +\item +\emph{cb.\cperms{}.Permit\_Store\_Local} is not set and +\emph{cs.tag} is set and \emph{cs.\cperms{}.Global} is not set. +\item +\emph{addr} $+$ \emph{short\_capability\_size} $>$ \emph{cb}.\cbase{} $+$ \emph{cb.\clength{}}. +\item +\emph{addr} $<$ \emph{cb}.\cbase{}. +\item +\emph{cs.\cbase{}}, \emph{cs.\cbase{}} $+$ \emph{cs.\clength{}}, and +the store's target memory location computed above differ in their top 32 bits. +\end{itemize} + +\noindent +A TLB Store exception is raised if: + +\begin{itemize} +\item +\emph{cs.\ctag{}} is set and the \emph{S} bit in the TLB entry for the page +containing \emph{addr} is not set. +\end{itemize} + +\noindent +An address error during store (AdES) exception is raised if: + +\begin{itemize} +\item +The virtual address \emph{addr} is not \emph{short\_capability\_size} aligned. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +If the address alignment check fails and one of the security checks fails, +a coprocessor 2 exception (and not an address error exception) is raised. +The priority of the exceptions is security-critical, because otherwise a +malicious program could use the type of the exception that is raised to +test the bottom bits of a register that it is not permitted to access. +\item +\emph{offset} is interpreted as a signed integer. +\item +The \insnnoref{CSShCI} mnemonic is equivalent to \insnmipsref{CSShC} with +\emph{cb} being the zero register (\$zero). The \insnnoref{CSShCR} mnemonic +is equivalent to \insnmipsref{CSShC} with \emph{offset} set to zero. +\item +Although the \emph{short\_capability\_size} can vary, the offset is always in +multiples of 8 bytes (64 bits). +\end{itemize} diff --git a/insn-mips/csub.tex b/insn-mips/csub.tex new file mode 100644 index 00000000..a72a3d42 --- /dev/null +++ b/insn-mips/csub.tex @@ -0,0 +1,46 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSub} +\insnmipslabel{csub} +\subsection*{CSub: Subtract Capabilities} + +\subsubsection*{Format} + +CSub rd, cb, ct + +\begin{center} +\cherithreeop[header]{0xa}{rt}{cb}{ct} +\end{center} + +\subsubsection*{Description} + +Register \emph{rd} is set equal to (\emph{cb}.\ccursor{} $-$ \emph{ct}.\ccursor{}) $\bmod~2^{64}$. + +\subsubsection*{Semantics} + +\sailMIPScode{CSub} + +\subsubsection*{Notes} + +\begin{itemize} +\item +\insnmipsref{CSub} can be used to implement C-language pointer subtraction, +or subtraction of \ccode{intcap\_t}. +\item +Like \insnmipsref{CIncOffset}, \insnmipsref{CSub} can be used on either +valid capabilities (\ctag{} set) or on integer values stored in capability +registers (\ctag{} not set). +\item +If a copying garbage collector is in use, pointer subtraction must be +implemented with an atomic operation (such as \insnmipsref{CSub}). +Implementing pointer subtraction with a non-atomic sequence of operations such +as \insnmipsref{CGetOffset} has the risk that the garbage collector will +relocate an object part way through, giving incorrect results for the +pointer difference. If \emph{cb} and \emph{ct} are both pointers into the +same object, then a copying garbage collector will either relocate both of +them or neither of them, leaving the difference the same. +If \emph{cb} and \emph{ct} are pointers into +different objects, the result of the subtraction is not defined by the ANSI +C standard, so it doesn't matter if this difference changes as the garbage +collector moves objects. +\end{itemize} diff --git a/insn-mips/ctestsubset.tex b/insn-mips/ctestsubset.tex new file mode 100644 index 00000000..49e31e94 --- /dev/null +++ b/insn-mips/ctestsubset.tex @@ -0,0 +1,78 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CTestSubset} +\insnmipslabel{ctestsubset} +\subsection*{CTestSubset: Test that Capability is a Subset of Another} + +\subsubsection*{Format} + +CTestSubset rd, cb, ct + +\begin{center} +\begin{bytefield}{32} +\bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}\\ +\bitbox{6}{0x12} +\bitbox{5}{0x0} +\bitbox{5}{rd} +\bitbox{5}{cb} +\bitbox{5}{ct} +\bitbox{6}{0x20} +\end{bytefield} +\end{center} + +\usesDDCinsteadofNULL{cb} + +\subsubsection*{Description} + +\insnmipsref{CTestSubset} tests if the bounds of \emph{ct} are within the +bounds of \emph{cb}, and the permissions of \emph{ct} are within the permissions +of \emph{cb}, setting \emph{rd} to \emph{1} if so, and \emph{0} if not. + +\note{mr101}{What should happen if one of the capabilities is NULL? Is the +NULL capability a subset of a valid capability? Comparing the \cbase{} and +\clength{} fields when the \ctag{} bit is clear seems the wrong thing to do} + +\note{mr101}{Is a zero length capability a subset of a valid capability, +even if it's \cbase{} is not within the range. If you view the operation as +a subset of the memory bytes, then it is a subset} + +\note{mr101}{The motivating use case is \insnmipsref{CToPtr}, +\insnmipsref{CTestSubset}, \insnnoref{MOVZ reg, zero}. In error cases +where \insnmipsref{CToPtr} has returned zero, we don't really care what +\insnmipsref{CTestSubset} returns, because we're going to get the NULL +pointer anyway.} + +\subsubsection*{Semantics} +\sailMIPScode{CTestSubset} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cd}, \emph{cb} or \emph{ct} is a reserved register and \PCC.\cperms{} does +not grant \emph{Permit\_Access\_System\_Registers}. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +This instruction was originally motivated as an additional check for +\insnmipsref{CToPtr}. +A conversion of a capability to a pointer with respect to a default capability +would normally expect that the entire capability is accessible within the +default capability with (at least) the original permissions. +\insnmipsref{CTestSubset} can perform this assertion, and a \insnmipsref{CMove} +instruction can replace the result of the \insnmipsref{CToPtr} with NULL upon +failure. +\item +Another use case for this instruction is in garbage collection. For this +application, we want to be able to test if one capability is a subset of +the other even if one is sealed and the other is not. (For the purposes of +garbage collection, a sealed reference to a region of memory is still a +reference to that region of memory). With compressed capabilities, the bounds +are represented differently for sealed and unsealed capabilities, but +\insnmipsref{CTestSubset} is still able to perform the subset check. +\end{itemize} diff --git a/insn-mips/ctoptr.tex b/insn-mips/ctoptr.tex new file mode 100644 index 00000000..cc5c38d3 --- /dev/null +++ b/insn-mips/ctoptr.tex @@ -0,0 +1,78 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CToPtr} +\insnmipslabel{ctoptr} +\subsection*{CToPtr: Capability to Integer Pointer} + +\subsubsection*{Format} + +CToPtr rd, cb, ct + +\begin{center} +\cherithreeop[header]{0x12}{rd}{cb}{ct} +\end{center} + +\usesDDCinsteadofNULL{ct} + +\subsubsection*{Description} + +If \emph{cb} has its tag bit unset (i.e. it is either the +NULL capability, or contains some other non-capability data), +then \emph{rd} is set to zero. Otherwise, \emph{rd} is set to +\emph{cb}.\cbase{} $+$ \emph{cb}.\coffset{} - \emph{ct}.\cbase{} + +This instruction can be used to convert a capability into a pointer that +uses the C language convention that a zero value represents the NULL pointer. +Note that \emph{rd} will also be zero if \emph{cb}.\cbase{} $+$ +\emph{cb}.\coffset{} $=$ \emph{ct}.\cbase{}; +this is similar to the C language not being able to distinguish a +NULL pointer from a pointer to a structure at address 0. +\arnote{Should we just return the address for untagged values to handle cases such as \ccode{(void* __capability)-1)}?} + +% XXXRW: Address notes: +% +%\note{dc552}{We need to output 0 if the input capability is out of bounds for the +%gsl::span and related bounds checking to work. I have added the required check +%commented out.} +% \arnote{why can't we just use the capability directly in hybrid mode?} +% +%\note{dc552}{The names cb and ct are confusing for this instruction. cb is not +%the base register and ct is not the target.} + +\arnote{The operand order here is inconsistent with cfromptr/cbuildcap: the authorizing capability is the third operand instead of the second.} + +\subsubsection*{Semantics} + +\sailMIPScode{CToPtr} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception will be raised if: + +\begin{itemize} +\item +\emph{ct}.\ctag{} is not set. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +\emph{ct} being sealed will not cause an exception to be raised. +This is for further study. +\item +This instruction has two different means of returning an error code: +raising an exception (if \emph{ct}.\ctag{} is not set, or the registers +are not accessible) and returning a NULL pointer if \emph{cb}.\ctag{} +is not set. +\item +If the range of \emph{cb} is outside the range of \emph{ct}, a pointer relative +to \emph{ct} can't always be used in place of \emph{cb}: some reads or writes +will fail because they are outside the range of \emph{ct}. To handle this case, +the application can use the \insnmipsref{CTestSubset} instruction +followed by a conditional move. + +\item \insnmipsref{CGetAddr} similarly allows access to the sum of the base +and offset of the operand capability, but without the translation relative to the +authorizing capability or validity/sealed checks on the operand. +\end{itemize} diff --git a/insn-mips/cunseal.tex b/insn-mips/cunseal.tex new file mode 100644 index 00000000..f21bbdb8 --- /dev/null +++ b/insn-mips/cunseal.tex @@ -0,0 +1,55 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CUnseal} +\insnmipslabel{cunseal} +\subsection*{CUnseal: Unseal a Sealed Capability} + +\subsubsection*{Format} + +CUnseal cd, cs, ct + +\begin{center} +\cherithreeop[header]{0xc}{cd}{cs}{ct} +\end{center} + +\subsubsection*{Description} + +The sealed capability in $cs$ is unsealed with $ct$ and the result placed +in $cd$. The global bit of $cd$ is the AND of the global bits of +$cs$ and $ct$. $ct$ must be unsealed, have \emph{Permit\_Unseal} permission, and $ct$.\cbase{} + $ct$.\coffset{} must equal $cs$.\cotype{}. + +\subsubsection*{Semantics} + +\sailMIPScode{CUnseal} + +\subsubsection*{Exceptions} + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item +\emph{cs}.\ctag{} is not set. +\item +\emph{ct}.\ctag{} is not set. +\item +\emph{cs} is not sealed. +\item +\emph{ct} is sealed. +\item +\emph{ct}.\coffset{} $\ge$ \emph{ct}.\clength{} +\item +\emph{ct}.\cperms{}.\emph{Permit\_Unseal} is not set. +\item +\emph{ct}.\cbase{} $+$ \emph{ct}.\coffset{} $\ne$ \emph{cs}.\cotype{}. +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item +There is no need to check if \emph{ct}.\cbase{} $+$ \emph{ct}.\coffset{} +$>$ \emph{max\_otype}, because this can't happen: +\emph{ct}.\cbase{} $+$ \emph{ct}.\coffset{} must equal \emph{cs}.\cotype{} +for the \cotype{} check to have succeeded, and there is no way +\emph{cs}.\cotype{} could have been set to a value that is out of range. +\end{itemize} diff --git a/insn-mips/cwritehwr.tex b/insn-mips/cwritehwr.tex new file mode 100644 index 00000000..3100f21e --- /dev/null +++ b/insn-mips/cwritehwr.tex @@ -0,0 +1,73 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CWriteHwr} +\insnmipslabel{cwritehwr} +\subsection*{CWriteHwr: Write a Special-Purpose Capability Register} + +\subsubsection*{Format} + +CWriteHwr cb, selector + +\begin{center} +\cheritwoop[header]{0xe}{cb}{selector} +\end{center} + +\subsubsection*{Description} + +The value of the capability register \emph{cb} is stored in the special-purpose +capability register \emph{selector}. +See \autoref{tab:cwritehwr-permissions} for the possible values of +\emph{selector} and the permissions required in order to write to the register. + +\begin{table}[h] +\centering +\caption{Access permission required to write special-purpose capability registers} +\label{tab:cwritehwr-permissions} +\begin{tabular}{cll@{}} +\toprule +& \textbf{Register} & Required for write access \\ +\midrule +\textbf{0} & Default data capability (\DDC) & $\emptyset$ \\ +\textbf{1} & User TLS (\CULR) & $\emptyset$ \\ +%\textbf{2} & \ajnote{\PCC - make this CJR} & $\emptyset$ \\ +% \textbf{7} & Program counter capability (\PCC) & Never writeable \\ + + +\textbf{8} & Privileged User TLS (\CPLR) & \PCC{}.\cperms{}.\emph{Access\_System\_Registers} \\ + +\textbf{22} & Kernel scratch register 1 (\KRC) & \KernelAndAccessSysRegs \\ +\textbf{23} & Kernel scratch register 2 (\KQC) & \KernelAndAccessSysRegs \\ + +\textbf{28} & Error exception program counter (\ErrorEPCC) & \KernelAndAccessSysRegs \\ +\textbf{29} & Kernel code capability (\KCC) & \KernelAndAccessSysRegs \\ +\textbf{30} & Kernel data capability (\KDC) & \KernelAndAccessSysRegs \\ +\textbf{31} & Exception program counter (\EPCC) & \KernelAndAccessSysRegs \\ +\bottomrule +\end{tabular} +\end{table} + +\note{rmn30}{should we validate the written values, for example requiring that KCC and EPCC have tag set? otherwise we can get into weird states (I think this can happen on current hw).} + +\subsubsection*{Semantics} +\sailMIPScode{CWriteHwr} + +\subsubsection*{Exceptions} + + +A reserved Instruction exception is raised for unknown or +unimplemented values of \emph{selector}. + +A coprocessor 2 exception is raised if: + +\begin{itemize} +\item the permission checks as specified in \autoref{tab:cwritehwr-permissions} above were not met for \emph{selector} +\end{itemize} + +\subsubsection*{Notes} + +\begin{itemize} +\item In the future we may decide to require \PCC{}.\cperms{}.\emph{Access\_System\_Registers} in order to modify \DDC +\item We may decide to introduce a \insnnoref{CSwapHwr} instruction that + swaps special-purpose register \emph{selector} and a general-purpose register +\end{itemize} + diff --git a/insn-riscv/auipcc.tex b/insn-riscv/auipcc.tex new file mode 100644 index 00000000..f0029081 --- /dev/null +++ b/insn-riscv/auipcc.tex @@ -0,0 +1,20 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{AUIPCC} +\insnriscvlabel{auipcc} +\subsection*{AUIPCC} + +\subsubsection*{Format} + +\rvcheriasmfmt[capability mode]{\rvcheriasminsnnoref{AUIPCC} cd, imm} + +\begin{center} +\begin{bytefield}{32} + \bitheader[endianness=big]{0,6,7,11,12,31}\\ + \bitbox{20}{imm[31:12]} + \bitbox{5}{cd} + \bitbox{7}{0x17} +\end{bytefield} +\end{center} + +\sailRISCVisarefbody{AUIPCC} diff --git a/insn-riscv/candperm.tex b/insn-riscv/candperm.tex new file mode 100644 index 00000000..c6c69768 --- /dev/null +++ b/insn-riscv/candperm.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CAndPerm} +\insnriscvlabel{candperm} +\subsection*{CAndPerm} + +\subsubsection*{Format} + +\rvcheriasm{CAndPerm} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CAndPerm} +\end{center} + +\sailRISCVisarefbody{CAndPerm} diff --git a/insn-riscv/cbuildcap.tex b/insn-riscv/cbuildcap.tex new file mode 100644 index 00000000..461f5e4d --- /dev/null +++ b/insn-riscv/cbuildcap.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CBuildCap} +\insnriscvlabel{cbuildcap} +\subsection*{CBuildCap} + +\subsubsection*{Format} + +\rvcheriasm{CBuildCap} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CBuildCap} +\end{center} + +\sailRISCVisarefbody{CBuildCap} diff --git a/insn-riscv/cclear.tex b/insn-riscv/cclear.tex new file mode 100644 index 00000000..287ca717 --- /dev/null +++ b/insn-riscv/cclear.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CClear} +\insnriscvlabel{cclear} +\subsection*{CClear} + +\subsubsection*{Format} + +\rvcheriasm{CClear} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CClear} +\end{center} + +\sailRISCVisarefbody{CClear} diff --git a/insn-riscv/ccleartag.tex b/insn-riscv/ccleartag.tex new file mode 100644 index 00000000..1c6231ce --- /dev/null +++ b/insn-riscv/ccleartag.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CClearTag} +\insnriscvlabel{ccleartag} +\subsection*{CClearTag} + +\subsubsection*{Format} + +\rvcheriasm{CClearTag} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CClearTag} +\end{center} + +\sailRISCVisarefbody{CClearTag} diff --git a/insn-riscv/ccleartags.tex b/insn-riscv/ccleartags.tex new file mode 100644 index 00000000..bb95f726 --- /dev/null +++ b/insn-riscv/ccleartags.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CClearTags} +\insnriscvlabel{ccleartags} +\subsection*{CClearTags} + +\subsubsection*{Format} + +\rvcheriasm{CClearTags} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CClearTags} +\end{center} + +\sailRISCVisarefbody{CClearTags} diff --git a/insn-riscv/ccopytype.tex b/insn-riscv/ccopytype.tex new file mode 100644 index 00000000..45ef59a4 --- /dev/null +++ b/insn-riscv/ccopytype.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CCopyType} +\insnriscvlabel{ccopytype} +\subsection*{CCopyType} + +\subsubsection*{Format} + +\rvcheriasm{CCopyType} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CCopyType} +\end{center} + +\sailRISCVisarefbody{CCopyType} diff --git a/insn-riscv/ccseal.tex b/insn-riscv/ccseal.tex new file mode 100644 index 00000000..fc440779 --- /dev/null +++ b/insn-riscv/ccseal.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CCSeal} +\insnriscvlabel{ccseal} +\subsection*{CCSeal} + +\subsubsection*{Format} + +\rvcheriasm{CCSeal} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CCSeal} +\end{center} + +\sailRISCVisarefbody{CCSeal} diff --git a/insn-riscv/cfromptr.tex b/insn-riscv/cfromptr.tex new file mode 100644 index 00000000..5c29bc5f --- /dev/null +++ b/insn-riscv/cfromptr.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CFromPtr} +\insnriscvlabel{cfromptr} +\subsection*{CFromPtr} + +\subsubsection*{Format} + +\rvcheriasm{CFromPtr} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CFromPtr} +\end{center} + +\sailRISCVisarefbody{CFromPtr} diff --git a/insn-riscv/cgetaddr.tex b/insn-riscv/cgetaddr.tex new file mode 100644 index 00000000..441ddb29 --- /dev/null +++ b/insn-riscv/cgetaddr.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetAddr} +\insnriscvlabel{cgetaddr} +\subsection*{CGetAddr} + +\subsubsection*{Format} + +\rvcheriasm{CGetAddr} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CGetAddr} +\end{center} + +\sailRISCVisarefbody{CGetAddr} diff --git a/insn-riscv/cgetbase.tex b/insn-riscv/cgetbase.tex new file mode 100644 index 00000000..88336b53 --- /dev/null +++ b/insn-riscv/cgetbase.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetBase} +\insnriscvlabel{cgetbase} +\subsection*{CGetBase} + +\subsubsection*{Format} + +\rvcheriasm{CGetBase} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CGetBase} +\end{center} + +\sailRISCVisarefbody{CGetBase} diff --git a/insn-riscv/cgetflags.tex b/insn-riscv/cgetflags.tex new file mode 100644 index 00000000..1e0c2f0d --- /dev/null +++ b/insn-riscv/cgetflags.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetFlags} +\insnriscvlabel{cgetflags} +\subsection*{CGetFlags} + +\subsubsection*{Format} + +\rvcheriasm{CGetFlags} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CGetFlags} +\end{center} + +\sailRISCVisarefbody{CGetFlags} diff --git a/insn-riscv/cgetlen.tex b/insn-riscv/cgetlen.tex new file mode 100644 index 00000000..f9468d86 --- /dev/null +++ b/insn-riscv/cgetlen.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetLen} +\insnriscvlabel{cgetlen} +\subsection*{CGetLen} + +\subsubsection*{Format} + +\rvcheriasm{CGetLen} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CGetLen} +\end{center} + +\sailRISCVisarefbody{CGetLen} diff --git a/insn-riscv/cgetoffset.tex b/insn-riscv/cgetoffset.tex new file mode 100644 index 00000000..875165a9 --- /dev/null +++ b/insn-riscv/cgetoffset.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetOffset} +\insnriscvlabel{cgetoffset} +\subsection*{CGetOffset} + +\subsubsection*{Format} + +\rvcheriasm{CGetOffset} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CGetOffset} +\end{center} + +\sailRISCVisarefbody{CGetOffset} diff --git a/insn-riscv/cgetperm.tex b/insn-riscv/cgetperm.tex new file mode 100644 index 00000000..f9a1ff89 --- /dev/null +++ b/insn-riscv/cgetperm.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetPerm} +\insnriscvlabel{cgetperm} +\subsection*{CGetPerm} + +\subsubsection*{Format} + +\rvcheriasm{CGetPerm} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CGetPerm} +\end{center} + +\sailRISCVisarefbody{CGetPerm} diff --git a/insn-riscv/cgetsealed.tex b/insn-riscv/cgetsealed.tex new file mode 100644 index 00000000..cffb89b9 --- /dev/null +++ b/insn-riscv/cgetsealed.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetSealed} +\insnriscvlabel{cgetsealed} +\subsection*{CGetSealed} + +\subsubsection*{Format} + +\rvcheriasm{CGetSealed} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CGetSealed} +\end{center} + +\sailRISCVisarefbody{CGetSealed} diff --git a/insn-riscv/cgettag.tex b/insn-riscv/cgettag.tex new file mode 100644 index 00000000..bb091900 --- /dev/null +++ b/insn-riscv/cgettag.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetTag} +\insnriscvlabel{cgettag} +\subsection*{CGetTag} + +\subsubsection*{Format} + +\rvcheriasm{CGetTag} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CGetTag} +\end{center} + +\sailRISCVisarefbody{CGetTag} diff --git a/insn-riscv/cgettype.tex b/insn-riscv/cgettype.tex new file mode 100644 index 00000000..ce5833aa --- /dev/null +++ b/insn-riscv/cgettype.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CGetType} +\insnriscvlabel{cgettype} +\subsection*{CGetType} + +\subsubsection*{Format} + +\rvcheriasm{CGetType} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CGetType} +\end{center} + +\sailRISCVisarefbody{CGetType} diff --git a/insn-riscv/cincoffset.tex b/insn-riscv/cincoffset.tex new file mode 100644 index 00000000..e8efaad0 --- /dev/null +++ b/insn-riscv/cincoffset.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CIncOffset} +\insnriscvlabel{cincoffset} +\subsection*{CIncOffset} + +\subsubsection*{Format} + +\rvcheriasm{CIncOffset} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CIncOffset} +\end{center} + +\sailRISCVisarefbody{CIncOffset} diff --git a/insn-riscv/cincoffsetimm.tex b/insn-riscv/cincoffsetimm.tex new file mode 100644 index 00000000..f8642ac9 --- /dev/null +++ b/insn-riscv/cincoffsetimm.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CIncOffsetImm} +\insnriscvlabel{cincoffsetimm} +\subsection*{CIncOffsetImm} + +\subsubsection*{Format} + +\rvcheriasm{CIncOffsetImm} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CIncOffsetImm} +\end{center} + +\sailRISCVisarefbody{CIncOffsetImmediate} diff --git a/insn-riscv/cinvoke.tex b/insn-riscv/cinvoke.tex new file mode 100644 index 00000000..6a5f82ef --- /dev/null +++ b/insn-riscv/cinvoke.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CInvoke} +\insnriscvlabel{cinvoke} +\subsection*{CInvoke} + +\subsubsection*{Format} + +\rvcheriasm{CInvoke} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CInvoke} +\end{center} + +\sailRISCVisarefbody{CInvoke} diff --git a/insn-riscv/cjalr.tex b/insn-riscv/cjalr.tex new file mode 100644 index 00000000..abacaa09 --- /dev/null +++ b/insn-riscv/cjalr.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CJALR} +\insnriscvlabel{cjalr} +\subsection*{CJALR} + +\subsubsection*{Format} + +\rvcheriasm{CJALR} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CJALR} +\end{center} + +\sailRISCVisarefbody{CJALR} diff --git a/insn-riscv/clear.tex b/insn-riscv/clear.tex new file mode 100644 index 00000000..4ac4475c --- /dev/null +++ b/insn-riscv/clear.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{Clear} +\insnriscvlabel{clear} +\subsection*{Clear} + +\subsubsection*{Format} + +\rvcheriasm{Clear} + +\begin{center} +\rvcheriheader +\rvcheribitbox{Clear} +\end{center} + +\sailRISCVisarefbody{Clear} diff --git a/insn-riscv/cloadtags.tex b/insn-riscv/cloadtags.tex new file mode 100644 index 00000000..add98ca7 --- /dev/null +++ b/insn-riscv/cloadtags.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CLoadTags} +\insnriscvlabel{cloadtags} +\subsection*{CLoadTags} + +\subsubsection*{Format} + +\rvcheriasm{CLoadTags} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CLoadTags} +\end{center} + +\sailRISCVisarefbody{CLoadTags} diff --git a/insn-riscv/cmove.tex b/insn-riscv/cmove.tex new file mode 100644 index 00000000..596f43f0 --- /dev/null +++ b/insn-riscv/cmove.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CMove} +\insnriscvlabel{cmove} +\subsection*{CMove} + +\subsubsection*{Format} + +\rvcheriasm{CMove} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CMove} +\end{center} + +\sailRISCVisarefbody{CMove} diff --git a/insn-riscv/crepresentablealignmentmask.tex b/insn-riscv/crepresentablealignmentmask.tex new file mode 100644 index 00000000..4836e92a --- /dev/null +++ b/insn-riscv/crepresentablealignmentmask.tex @@ -0,0 +1,17 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CRepresentableAlignmentMask} +\insnriscvlabel{crepresentablealignmentmask} +\insnriscvlabel{cram} +\subsection*{CRepresentableAlignmentMask} + +\subsubsection*{Format} + +\rvcheriasm{CRepresentableAlignmentMask} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CRepresentableAlignmentMask} +\end{center} + +\sailRISCVisarefbody{CRAM} diff --git a/insn-riscv/croundrepresentablelength.tex b/insn-riscv/croundrepresentablelength.tex new file mode 100644 index 00000000..015b96e2 --- /dev/null +++ b/insn-riscv/croundrepresentablelength.tex @@ -0,0 +1,17 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CRoundRepresentableLength} +\insnriscvlabel{croundrepresentablelength} +\insnriscvlabel{crrl} +\subsection*{CRoundRepresentableLength} + +\subsubsection*{Format} + +\rvcheriasm{CRoundRepresentableLength} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CRoundRepresentableLength} +\end{center} + +\sailRISCVisarefbody{CRRL} diff --git a/insn-riscv/cseal.tex b/insn-riscv/cseal.tex new file mode 100644 index 00000000..d70e40a9 --- /dev/null +++ b/insn-riscv/cseal.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSeal} +\insnriscvlabel{cseal} +\subsection*{CSeal} + +\subsubsection*{Format} + +\rvcheriasm{CSeal} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CSeal} +\end{center} + +\sailRISCVisarefbody{CSeal} diff --git a/insn-riscv/csealentry.tex b/insn-riscv/csealentry.tex new file mode 100644 index 00000000..4771750f --- /dev/null +++ b/insn-riscv/csealentry.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSealEntry} +\insnriscvlabel{csealentry} +\subsection*{CSealEntry} + +\subsubsection*{Format} + +\rvcheriasm{CSealEntry} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CSealEntry} +\end{center} + +\sailRISCVisarefbody{CSealEntry} diff --git a/insn-riscv/csetaddr.tex b/insn-riscv/csetaddr.tex new file mode 100644 index 00000000..ebc338e5 --- /dev/null +++ b/insn-riscv/csetaddr.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetAddr} +\insnriscvlabel{csetaddr} +\subsection*{CSetAddr} + +\subsubsection*{Format} + +\rvcheriasm{CSetAddr} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CSetAddr} +\end{center} + +\sailRISCVisarefbody{CSetAddr} diff --git a/insn-riscv/csetbounds.tex b/insn-riscv/csetbounds.tex new file mode 100644 index 00000000..fac728d5 --- /dev/null +++ b/insn-riscv/csetbounds.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetBounds} +\insnriscvlabel{csetbounds} +\subsection*{CSetBounds} + +\subsubsection*{Format} + +\rvcheriasm{CSetBounds} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CSetBounds} +\end{center} + +\sailRISCVisarefbody{CSetBounds} diff --git a/insn-riscv/csetboundsexact.tex b/insn-riscv/csetboundsexact.tex new file mode 100644 index 00000000..d42612fb --- /dev/null +++ b/insn-riscv/csetboundsexact.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetBoundsExact} +\insnriscvlabel{csetboundsexact} +\subsection*{CSetBoundsExact} + +\subsubsection*{Format} + +\rvcheriasm{CSetBoundsExact} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CSetBoundsExact} +\end{center} + +\sailRISCVisarefbody{CSetBoundsExact} diff --git a/insn-riscv/csetboundsimm.tex b/insn-riscv/csetboundsimm.tex new file mode 100644 index 00000000..89cb40fe --- /dev/null +++ b/insn-riscv/csetboundsimm.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetBoundsImm} +\insnriscvlabel{csetboundsimm} +\subsection*{CSetBoundsImm} + +\subsubsection*{Format} + +\rvcheriasm{CSetBoundsImm} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CSetBoundsImm} +\end{center} + +\sailRISCVisarefbody{CSetBoundsImmediate} diff --git a/insn-riscv/csetequalexact.tex b/insn-riscv/csetequalexact.tex new file mode 100644 index 00000000..091635ab --- /dev/null +++ b/insn-riscv/csetequalexact.tex @@ -0,0 +1,17 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetEqualExact} +\insnriscvlabel{csetequalexact} +\insnriscvlabel{cseqx} +\subsection*{CSetEqualExact} + +\subsubsection*{Format} + +\rvcheriasm{CSetEqualExact} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CSetEqualExact} +\end{center} + +\sailRISCVisarefbody{CSEQX} diff --git a/insn-riscv/csetflags.tex b/insn-riscv/csetflags.tex new file mode 100644 index 00000000..afca1de3 --- /dev/null +++ b/insn-riscv/csetflags.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetFlags} +\insnriscvlabel{csetflags} +\subsection*{CSetFlags} + +\subsubsection*{Format} + +\rvcheriasm{CSetFlags} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CSetFlags} +\end{center} + +\sailRISCVisarefbody{CSetFlags} diff --git a/insn-riscv/csetoffset.tex b/insn-riscv/csetoffset.tex new file mode 100644 index 00000000..8fc57b71 --- /dev/null +++ b/insn-riscv/csetoffset.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSetOffset} +\insnriscvlabel{csetoffset} +\subsection*{CSetOffset} + +\subsubsection*{Format} + +\rvcheriasm{CSetOffset} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CSetOffset} +\end{center} + +\sailRISCVisarefbody{CSetOffset} diff --git a/insn-riscv/cspecialrw.tex b/insn-riscv/cspecialrw.tex new file mode 100644 index 00000000..c8f2d172 --- /dev/null +++ b/insn-riscv/cspecialrw.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSpecialRW} +\insnriscvlabel{cspecialrw} +\subsection*{CSpecialRW} + +\subsubsection*{Format} + +\rvcheriasm{CSpecialRW} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CSpecialRW} +\end{center} + +\sailRISCVisarefbody{CSpecialRW} diff --git a/insn-riscv/csub.tex b/insn-riscv/csub.tex new file mode 100644 index 00000000..a439a7a0 --- /dev/null +++ b/insn-riscv/csub.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CSub} +\insnriscvlabel{csub} +\subsection*{CSub} + +\subsubsection*{Format} + +\rvcheriasm{CSub} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CSub} +\end{center} + +\sailRISCVisarefbody{CSub} diff --git a/insn-riscv/ctestsubset.tex b/insn-riscv/ctestsubset.tex new file mode 100644 index 00000000..f6b647b1 --- /dev/null +++ b/insn-riscv/ctestsubset.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CTestSubset} +\insnriscvlabel{ctestsubset} +\subsection*{CTestSubset} + +\subsubsection*{Format} + +\rvcheriasm{CTestSubset} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CTestSubset} +\end{center} + +\sailRISCVisarefbody{CTestSubset} diff --git a/insn-riscv/ctoptr.tex b/insn-riscv/ctoptr.tex new file mode 100644 index 00000000..67038bb8 --- /dev/null +++ b/insn-riscv/ctoptr.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CToPtr} +\insnriscvlabel{ctoptr} +\subsection*{CToPtr} + +\subsubsection*{Format} + +\rvcheriasm{CToPtr} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CToPtr} +\end{center} + +\sailRISCVisarefbody{CToPtr} diff --git a/insn-riscv/cunseal.tex b/insn-riscv/cunseal.tex new file mode 100644 index 00000000..462f7954 --- /dev/null +++ b/insn-riscv/cunseal.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{CUnseal} +\insnriscvlabel{cunseal} +\subsection*{CUnseal} + +\subsubsection*{Format} + +\rvcheriasm{CUnseal} + +\begin{center} +\rvcheriheader +\rvcheribitbox{CUnseal} +\end{center} + +\sailRISCVisarefbody{CUnseal} diff --git a/insn-riscv/fpclear.tex b/insn-riscv/fpclear.tex new file mode 100644 index 00000000..355c6944 --- /dev/null +++ b/insn-riscv/fpclear.tex @@ -0,0 +1,16 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{FPClear} +\insnriscvlabel{fpclear} +\subsection*{FPClear} + +\subsubsection*{Format} + +\rvcheriasm{FPClear} + +\begin{center} +\rvcheriheader +\rvcheribitbox{FPClear} +\end{center} + +\sailRISCVisarefbody{FPClear} diff --git a/insn-riscv/lc.tex b/insn-riscv/lc.tex new file mode 100644 index 00000000..98b8a41a --- /dev/null +++ b/insn-riscv/lc.tex @@ -0,0 +1,43 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{[C]LC} +\insnriscvlabel{lc} +\insnriscvlabel{clc} +\subsection*{[C]LC} + +\subsubsection*{Format} + +\noindent\rvcheriasmfmt[RV32, integer mode]{\rvcheriasminsnref{LC} cd, rs1, imm} + +\noindent\rvcheriasmfmt[RV32, capability mode]{\rvcheriasminsnref{CLC} cd, cs1, imm} + +\begin{center} +\begin{bytefield}{32} + \bitheader[endianness=big]{0,6,7,11,12,14,15,19,20,31}\\ + \bitbox{12}{imm} + \bitbox{5}{rs1/cs1} + \bitbox{3}{0x3} + \bitbox{5}{cd} + \bitbox{7}{0x3} +\end{bytefield} +\end{center} + +\noindent\rvcheriasmfmt[RV64, integer mode]{\rvcheriasminsnref{LC} cd, rs1, imm} + +\noindent\rvcheriasmfmt[RV64, capability mode]{\rvcheriasminsnref{CLC} cd, cs1, imm} + +\begin{center} +\begin{bytefield}{32} + \bitheader[endianness=big]{0,6,7,11,12,14,15,19,20,31}\\ + \bitbox{12}{imm} + \bitbox{5}{rs1/cs1} + \bitbox{3}{0x2} + \bitbox{5}{cd} + \bitbox{7}{0xf} +\end{bytefield} +\end{center} + +% XXX: Ideally we would be able to use [LC](LoadCapImm) in the saildoc but that +% generates a link to the literal LoadCapImm. +\label{sailRISCVzLC} +\sailRISCVisarefbody{LoadCapImm} diff --git a/insn-riscv/loadcapcap.tex b/insn-riscv/loadcapcap.tex new file mode 100644 index 00000000..fb84a9f6 --- /dev/null +++ b/insn-riscv/loadcapcap.tex @@ -0,0 +1,24 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{LC.CAP} +\insnriscvlabel{loadcapcap} +\insnriscvlabel{lc.cap} +\subsection*{LC.CAP} + +\subsubsection*{Format} + +\noindent\rvcheriasm{LC.CAP:RV32} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LC.CAP:RV32} +\end{center} + +\noindent\rvcheriasm{LC.CAP:RV64} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LC.CAP:RV64} +\end{center} + +\sailRISCVisarefbody{LoadCapCap} diff --git a/insn-riscv/loadcapddc.tex b/insn-riscv/loadcapddc.tex new file mode 100644 index 00000000..474ec1c9 --- /dev/null +++ b/insn-riscv/loadcapddc.tex @@ -0,0 +1,24 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{LC.DDC} +\insnriscvlabel{loadcapddc} +\insnriscvlabel{lc.ddc} +\subsection*{LC.DDC} + +\subsubsection*{Format} + +\noindent\rvcheriasm{LC.DDC:RV32} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LC.DDC:RV32} +\end{center} + +\noindent\rvcheriasm{LC.DDC:RV64} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LC.DDC:RV64} +\end{center} + +\sailRISCVisarefbody{LoadCapDDC} diff --git a/insn-riscv/loaddatacap.tex b/insn-riscv/loaddatacap.tex new file mode 100644 index 00000000..a6172695 --- /dev/null +++ b/insn-riscv/loaddatacap.tex @@ -0,0 +1,65 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{L[BHWD][U].CAP} +\insnriscvlabel{loaddatacap} +\insnriscvlabel{lb.cap} +\insnriscvlabel{lh.cap} +\insnriscvlabel{lw.cap} +\insnriscvlabel{ld.cap} +\insnriscvlabel{lbu.cap} +\insnriscvlabel{lhu.cap} +\insnriscvlabel{lwu.cap} +\subsection*{L[BHWD][U].CAP} + +\subsubsection*{Format} + +\noindent\rvcheriasm{LB.CAP} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LB.CAP} +\end{center} + +\noindent\rvcheriasm{LH.CAP} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LH.CAP} +\end{center} + +\noindent\rvcheriasm{LW.CAP} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LW.CAP} +\end{center} + +\noindent\rvcheriasm{LD.CAP:RV64/128} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LD.CAP:RV64/128} +\end{center} + +\noindent\rvcheriasm{LBU.CAP} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LBU.CAP} +\end{center} + +\noindent\rvcheriasm{LHU.CAP} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LHU.CAP} +\end{center} + +\noindent\rvcheriasm{LWU.CAP:RV64/128} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LWU.CAP:RV64/128} +\end{center} + +\sailRISCVisarefbody{LoadDataCap} diff --git a/insn-riscv/loaddataddc.tex b/insn-riscv/loaddataddc.tex new file mode 100644 index 00000000..d424a3cf --- /dev/null +++ b/insn-riscv/loaddataddc.tex @@ -0,0 +1,65 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{L[BHWD][U].DDC} +\insnriscvlabel{loaddataddc} +\insnriscvlabel{lb.ddc} +\insnriscvlabel{lh.ddc} +\insnriscvlabel{lw.ddc} +\insnriscvlabel{ld.ddc} +\insnriscvlabel{lbu.ddc} +\insnriscvlabel{lhu.ddc} +\insnriscvlabel{lwu.ddc} +\subsection*{L[BHWD][U].DDC} + +\subsubsection*{Format} + +\noindent\rvcheriasm{LB.DDC} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LB.DDC} +\end{center} + +\noindent\rvcheriasm{LH.DDC} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LH.DDC} +\end{center} + +\noindent\rvcheriasm{LW.DDC} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LW.DDC} +\end{center} + +\noindent\rvcheriasm{LD.DDC:RV64/128} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LD.DDC:RV64/128} +\end{center} + +\noindent\rvcheriasm{LBU.DDC} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LBU.DDC} +\end{center} + +\noindent\rvcheriasm{LHU.DDC} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LHU.DDC} +\end{center} + +\noindent\rvcheriasm{LWU.DDC:RV64/128} + +\begin{center} +\rvcheriheader +\rvcheribitbox{LWU.DDC:RV64/128} +\end{center} + +\sailRISCVisarefbody{LoadDataDDC} diff --git a/insn-riscv/sc.tex b/insn-riscv/sc.tex new file mode 100644 index 00000000..1c08a549 --- /dev/null +++ b/insn-riscv/sc.tex @@ -0,0 +1,42 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{[C]SC} +\insnriscvlabel{sc} +\insnriscvlabel{csc} +\subsection*{[C]SC} + +\subsubsection*{Format} + +\noindent\rvcheriasmfmt[RV32, integer mode]{\rvcheriasminsnref{SC} cs2, rs1, imm} + +\noindent\rvcheriasmfmt[RV32, capability mode]{\rvcheriasminsnref{CSC} cs2, cs1, imm} + +\begin{center} +\begin{bytefield}{32} + \bitheader[endianness=big]{0,6,7,11,12,14,15,19,20,24,25,31}\\ + \bitbox{7}{imm[11:5]} + \bitbox{5}{cs2} + \bitbox{5}{rs1/cs1} + \bitbox{3}{0x3} + \bitbox{5}{imm[0:4]} + \bitbox{7}{0x23} +\end{bytefield} +\end{center} + +\noindent\rvcheriasmfmt[RV64, integer mode]{\rvcheriasminsnref{SC} cs2, rs1, imm} + +\noindent\rvcheriasmfmt[RV64, capability mode]{\rvcheriasminsnref{CSC} cs2, cs1, imm} + +\begin{center} +\begin{bytefield}{32} + \bitheader[endianness=big]{0,6,7,11,12,14,15,19,20,24,25,31}\\ + \bitbox{7}{imm[11:5]} + \bitbox{5}{cs2} + \bitbox{5}{rs1/cs1} + \bitbox{3}{0x4} + \bitbox{5}{imm[0:4]} + \bitbox{7}{0x23} +\end{bytefield} +\end{center} + +\sailRISCVisarefbody{StoreCapImm} diff --git a/insn-riscv/storecapcap.tex b/insn-riscv/storecapcap.tex new file mode 100644 index 00000000..de64c096 --- /dev/null +++ b/insn-riscv/storecapcap.tex @@ -0,0 +1,24 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{SC.CAP} +\insnriscvlabel{storecapcap} +\insnriscvlabel{sc.cap} +\subsection*{SC.CAP} + +\subsubsection*{Format} + +\noindent\rvcheriasm{SC.CAP:RV32} + +\begin{center} +\rvcheriheader +\rvcheribitbox{SC.CAP:RV32} +\end{center} + +\noindent\rvcheriasm{SC.CAP:RV64} + +\begin{center} +\rvcheriheader +\rvcheribitbox{SC.CAP:RV64} +\end{center} + +\sailRISCVisarefbody{StoreCapCap} diff --git a/insn-riscv/storecapddc.tex b/insn-riscv/storecapddc.tex new file mode 100644 index 00000000..4d4dabab --- /dev/null +++ b/insn-riscv/storecapddc.tex @@ -0,0 +1,24 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{SC.DDC} +\insnriscvlabel{storecapddc} +\insnriscvlabel{sc.ddc} +\subsection*{SC.DDC} + +\subsubsection*{Format} + +\noindent\rvcheriasm{SC.DDC:RV32} + +\begin{center} +\rvcheriheader +\rvcheribitbox{SC.DDC:RV32} +\end{center} + +\noindent\rvcheriasm{SC.DDC:RV64} + +\begin{center} +\rvcheriheader +\rvcheribitbox{SC.DDC:RV64} +\end{center} + +\sailRISCVisarefbody{StoreCapDDC} diff --git a/insn-riscv/storedatacap.tex b/insn-riscv/storedatacap.tex new file mode 100644 index 00000000..c959d966 --- /dev/null +++ b/insn-riscv/storedatacap.tex @@ -0,0 +1,41 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{S[BHWD].CAP} +\insnriscvlabel{storedatacap} +\insnriscvlabel{sb.cap} +\insnriscvlabel{sh.cap} +\insnriscvlabel{sw.cap} +\insnriscvlabel{sd.cap} +\subsection*{S[BHWD].CAP} + +\subsubsection*{Format} + +\noindent\rvcheriasm{SB.CAP} + +\begin{center} +\rvcheriheader +\rvcheribitbox{SB.CAP} +\end{center} + +\noindent\rvcheriasm{SH.CAP} + +\begin{center} +\rvcheriheader +\rvcheribitbox{SH.CAP} +\end{center} + +\noindent\rvcheriasm{SW.CAP} + +\begin{center} +\rvcheriheader +\rvcheribitbox{SW.CAP} +\end{center} + +\noindent\rvcheriasm{SD.CAP:RV64/128} + +\begin{center} +\rvcheriheader +\rvcheribitbox{SD.CAP:RV64/128} +\end{center} + +\sailRISCVisarefbody{StoreDataCap} diff --git a/insn-riscv/storedataddc.tex b/insn-riscv/storedataddc.tex new file mode 100644 index 00000000..95021602 --- /dev/null +++ b/insn-riscv/storedataddc.tex @@ -0,0 +1,41 @@ +\clearpage +\phantomsection +\addcontentsline{toc}{subsection}{S[BHWD].DDC} +\insnriscvlabel{storedataddc} +\insnriscvlabel{sb.ddc} +\insnriscvlabel{sh.ddc} +\insnriscvlabel{sw.ddc} +\insnriscvlabel{sd.ddc} +\subsection*{S[BHWD].DDC} + +\subsubsection*{Format} + +\noindent\rvcheriasm{SB.DDC} + +\begin{center} +\rvcheriheader +\rvcheribitbox{SB.DDC} +\end{center} + +\noindent\rvcheriasm{SH.DDC} + +\begin{center} +\rvcheriheader +\rvcheribitbox{SH.DDC} +\end{center} + +\noindent\rvcheriasm{SW.DDC} + +\begin{center} +\rvcheriheader +\rvcheribitbox{SW.DDC} +\end{center} + +\noindent\rvcheriasm{SD.DDC:RV64/128} + +\begin{center} +\rvcheriheader +\rvcheribitbox{SD.DDC:RV64/128} +\end{center} + +\sailRISCVisarefbody{StoreDataDDC} diff --git a/latexmkrc b/latexmkrc new file mode 100644 index 00000000..ea458ca6 --- /dev/null +++ b/latexmkrc @@ -0,0 +1,168 @@ +# makeglossaries support from latexmk/example_rcfiles/glossary_latexmkrc +add_cus_dep( 'acn', 'acr', 0, 'makeglossaries' ); +add_cus_dep( 'glo', 'gls', 0, 'makeglossaries' ); +$clean_ext .= " acr acn acnh alg glo gls glg lg tmp run.xml tdo upa upb"; +$cleanup_includes_generated = 1; + +sub makeglossaries { + my ($base_name, $path) = fileparse( $_[0] ); + pushd $path; + my $return = system "makeglossaries '$base_name'"; + popd; + return $return; +} + +sub latexmk_version_at_least { + use version; + + my ($minimum_num) = @_; + + my ($version_num_version_str, $version_num_revision) = split /(?<=[0-9.])(?=([^0-9.]|$))/, $version_num, 2; + my ($minimum_num_version_str, $minimum_num_revision) = split /(?<=[0-9.])(?=([^0-9.]|$))/, $minimum_num, 2; + + my $version_num_version = version->parse($version_num_version_str); + my $minimum_num_version = version->parse($minimum_num_version_str); + + return $version_num_version > $minimum_num_version || ($version_num_version == $minimum_num_version && $version_num_revision ge $minimum_num_revision); +} + +push @generated_exts, 'glo', 'gls', 'glg'; +push @generated_exts, 'acn', 'acr', 'alg', 'acnh'; +push @generated_exts, 'soc', 'loc'; +$clean_ext .= ' %R.ist %R.xdy'; + +$bibtex_use = 2; +@default_files = ('cheri-architecture.tex'); +$pdf_mode = 1; # Default to -pdf flag + + +# We need version 4.67 to use success_cmd on normal builds: +if (latexmk_version_at_least("4.67")) { + # Use a separate aux dir and output dir, and copy the pdf from the build + # directory and scan for warnings after building: + $aux_dir = 'build'; + $out_dir = 'build'; + # + # The texloganalyser tool can be used to find all warning messages in the latex + # logfile which is useful when using interaction=batchmode. There is also + # a python package pydflatex that does the same thing (but with colours). + # However, texloganalyser is included by default in some TeX distributions so + # prefer that one. + # TODO: fix the broken sail hyperrefs so we don't have to filter the out. + $scan_logfile = "if command -v texloganalyser >/dev/null 2>/dev/null; then texloganalyser -w %Y/%R.log; fi"; + # Delete the copied file on failure: + $failure_cmd = "rm -vf %D %R.pdf; " . $scan_logfile; + # Otherwise copy it (and possibly the synctex.gz file) out of the build dir and scan the logfile. + $copy_files = "cp -v %D %R.pdf; test -f %R.synctex.gz && cp -fv %R.synctex.gz %R.synctex.gz"; + $warning_cmd = $copy_files . "; " . $scan_logfile; + $success_cmd = $copy_files . "; " . $scan_logfile; +} else { + print("Using aux dir workaround for latexmk < 4.67. Current version is " . $version_num . "\n"); + # Use a separate aux dir but output the build results in the same directory as + # the .tex file. + $aux_dir = 'build'; + # The code below is copied from CTAN/support/latexmk/example_rcfiles/fix-aux.latexmkrc + + #--------------------------- + # This shows how to implement the use of different values for $aux_dir and + # $out_dir when the latex (etc) engines don't support the -aux-directory + # option. (Of the standard distributions, MiKTeX supports -aux-directory, + # but TeXLive does not.) + foreach my $cmd ('latex', 'lualatex', 'pdflatex', 'xelatex' ) { + ${$cmd} = "internal latex_fix_aux $cmd %O %S"; + } + $xelatex =~ s/%O/-no-pdf %O/; + + sub latex_fix_aux { + # Fudge to allow use of -aux_directory option with non-MiKTeX system. + # This subroutine is called to do a compilation by one of latex, pdflatex, + # etc. It's arguments are the command name, and the command-line arguments, + # including possible uses of the options -aux-directory, -output-directory. + # Functioning: + # 1. Obtain the values of the aux and output directories from the options + # on the command line, with appropriate defaults if one or both options + # is not used. + # 2. Change the command line (a) to avoid the use of the -aux-directory + # option, and (b) to use the -output-directory to get all output + # sent to the intended aux-directory. If neither an -aux-directory + # nor an -output-directory option is used, no change is made to the + # command line. + # 3. Run the command. + # 4. If the aux and output directories are different, move any of the dvi, + # fls, pdf, ps and synctex.gz files that are present in the intended aux + # directory to the intended output directory. + # N.B. It might seem more appropriate to keep the fls file in the aux + # directory. But MiKTeX puts it in the output directory, so we must do + # the same to copy its behavior. + # It might also seem appropriate for an xdv file to go in the output + # directory, like a dvi file. But xelatex under MiKTeX puts it in the + # aux directory, so we must copy that behavior. + + my @move_exts = ('dvi', 'fls', 'pdf', 'ps', 'synctex.gz' ); + + # Determine aux and output directories from command line: + my $auxD = ''; + my $outD = ''; + foreach (@_) { + if ( /^-{1,2}aux-directory=(.*)$/ ) { + $auxD = $1; + } + elsif ( /^-{1,2}output-directory=(.*)$/ ) { + $outD = $1; + } + } + if ( $outD eq '' ) { $outD = '.'; } + if ( $auxD eq '' ) { $auxD = $outD; } + + # Construct modified command line, with at most one occurrence of -output-directory + my @args_act = (); + my $set_outD = 0; + foreach (@_) { + if ( /^-{1,2}(aux|output)-directory=.*$/ ) { + if ( ! $set_outD ) { + push @args_act, "-output-directory=$auxD"; + $set_outD = 1; + } + } else { + push @args_act, $_; + } + } + + # Construct strings for aux and output directories that are suitable + # for prepending to a file name, so that they have any necessary + # directory separators: + my $outD1 = $outD; + my $auxD1 = $auxD; + foreach ( $auxD1, $outD1 ) { + # Append directory separator '/', but only for a non-empty name + # that isn't simple an MSWin drive name. + if ( ($_ ne '') && ! m([\\/\:]$) ) { + $_ .= '/'; + } + # Clean up by removing any sequence of './'. These refer to + # current directory. + while ( s[^\.\/][] ) {} + } + + print "Running: '@args_act'\n"; + my $ret = system @args_act; + if ($auxD ne $outD) { + print "Move @move_exts files from '$auxD' to '$outD'\n"; + # Use copy and unlink, not rename, since some viewers appear to keep the + # viewed file open. So if rename were used, such viewers would see the + # old version of the file, rather than the new one. With copy, the + # contents of the old file are normally overwritten by the new contents. + # + # In addition, copy works across file system boundaries, but rename + # doesn't. + foreach my $ext (@move_exts) { + copy "$auxD1$root_filename.$ext", "$outD1$root_filename.$ext"; + unlink "$auxD1$root_filename.$ext"; + } + } + return $ret; + } + + #--------------------------- + +} # end of workaround for latexmk < 4.67 diff --git a/preamble-saildoc-macros.tex b/preamble-saildoc-macros.tex new file mode 100644 index 00000000..729c142c --- /dev/null +++ b/preamble-saildoc-macros.tex @@ -0,0 +1,280 @@ +\makeatletter +\newcommand{\makesailcmds@core}[2]{% + \input{#2/commands.tex} + \ea\newcommand\csname #1code\endcsname[1]{% + \csname #1fcl##1execute\endcsname% + \bigskip% + }% + \ea\WithSuffix\ea\newcommand\csname #1code\endcsname*[1]{% + \csname #1fcl##1execute\endcsname% + }% + \ea\newcommand\csname #1valandfun\endcsname[1]{% + \csname #1##1\endcsname \csname #1fn#1\endcsname% + }% +} + +% We could have sail macro call us back for more formatting flexibility. +%\newcommand{\saildescribe}[2]{ +% \lstinputlisting[language=sail]{#2} +% +% \hangindent=\parindent #1 +%} + +% The following macros define how we would like sail code to be documented. +% There is one per category of sail top-level (val spec, typedef, function, function clause etc) +% currently we only use val and fcl. +% They are called by latex generated by sail with +% #1 the latex for any doc-comment from the sail +% #2 a lstinputlisting invocation that +\newcommand{\saildocval}[2]{% +#2% +\par% +\hangindent=\parindent #1% +\medskip% +} +\newcommand{\saildocfcl}[2]{% +#1 #2% +} +\newcommand{\saildocfn}[2]{% +#1 #2% +} +\newcommand{\saildoctype}[2]{% +#1 #2% +} + +\newcommand{\@saildoclabelled@capture}[2]{% + \global\def\@saildoclabelled@name{#1}% + \global\def\@saildoclabelled@body{#2}% +} + +\newcommand{\@saildocfcl@capture}[2]{% + \global\def\@saildocfcl@doc{#1}% + \global\def\@saildocfcl@fcl{#2}% +} + +\newcommand{\@saildoc@makeerrcmd}[1]{% + \ea\def\csname #1@error\endcsname{% + \GenericError{[saildoc] }{Missing definition}{% + [saildoc] \@backslashchar#1 should have been defined.\MessageBreak% + Check your Sail version if you re-generated the LaTeX.% + }{}% + }% +} + +\@saildoc@makeerrcmd{@saildoclabelled@name} +\@saildoc@makeerrcmd{@saildoclabelled@body} +\@saildoc@makeerrcmd{@saildocfcl@doc} +\@saildoc@makeerrcmd{@saildocfcl@fcl} + +\newcommand{\@saildoc@makeforbiddenseccmd}[1]{% + \ea\def\csname @saildoc@#1\ea\endcsname{% + \GenericError{[saildoc] }{Forbidden command}{% + [saildoc] \@backslashchar#1 is not allowed.% + }{}% + }% +} + +% Always use starred variant +\newcommand{\@saildoc@makenestedseccmd}[2]{% + \ea\def\csname @saildoc@#1\endcsname{% + \@ifstar{}{}\csname #2\endcsname*% + }% +} + +\@saildoc@makeforbiddenseccmd{part} +\@saildoc@makeforbiddenseccmd{chapter} +\@saildoc@makeforbiddenseccmd{section} +% subsection is special (but still maps to subsubsection); see below +\@saildoc@makenestedseccmd{subsubsection}{paragraph} +\@saildoc@makenestedseccmd{paragraph}{subparagraph} +\@saildoc@makeforbiddenseccmd{subparagraph} + +\let\@saildoc@subsection@allowed\@empty +\newcommand{\@saildoc@subsection@allow}[1]{% + \ea\def\ea\@saildoc@subsection@allowed\ea{% + \@saildoc@subsection@allowed% + \@saildoc@subsection@allowed@iter{#1}% + }% +} +\@saildoc@subsection@allow{Description} +\@saildoc@subsection@allow{Exceptions} +\@saildoc@subsection@allow{Notes} + +\newcommand{\@saildoc@subsection@valid}[1]{} + +\newcommand{\@saildoc@subsection@invalid}[1]{% + \GenericError{[saildoc] }{Invalid subsection}{% + [saildoc] `#1' is not a valid subsection.% + }{}% +} + +\newcommand{\@saildoc@subsection@duplicate}[1]{% + \GenericError{[saildoc] }{Duplicate subsection}{% + [saildoc] `#1' is defined more than once.% + }{}% +} + +\newcommand{\@saildoc@subsection@validate}[1]{{% + \def\@saildoc@subsection@allowed@iter##1{% + \ifthenelse{\equal{#1}{##1}}{% + \let\@saildoc@subsection@validate@action\@saildoc@subsection@valid% + }{% + }% + }% + \ea\ifx\csname @saildoc@subsection@body@#1\endcsname\relax% + \let\@saildoc@subsection@validate@action\@saildoc@subsection@invalid% + \@saildoc@subsection@allowed% + \else% + \let\@saildoc@subsection@validate@action\@saildoc@subsection@duplicate% + \fi% + \@saildoc@subsection@validate@action{#1}% +}} + +\NewEnviron{@saildoc@subsection}[1]{% + \@saildoc@subsection@validate{#1}% + \ea\ea\ea\global\ea\ea\ea\def\ea\csname @saildoc@subsection@body@#1\ea\endcsname\ea{\BODY}% +} + +\newcommand{\@saildoc@subsection@print}[1]{% + \ea\ifx\csname @saildoc@subsection@body@#1\endcsname\relax% + \else% + \ea\ifx\csname @saildoc@subsection@body@#1\endcsname\@empty% + \else% + \subsubsection*{#1}% + \csname @saildoc@subsection@body@#1\endcsname% + \fi% + \fi% +} + +\newcommand{\@saildoc@subsection@clear}{{% + \def\@saildoc@subsection@allowed@iter##1{% + \ea\global\ea\let\csname @saildoc@subsection@body@##1\endcsname\@undefined% + }% + \@saildoc@subsection@allowed% +}} + +\newcommand{\@saildoc@xpatchcmd@repeat}[3]{% + \xpatchcmd{#1}{#2}{#3}{\@saildoc@xpatchcmd@repeat{#1}{#2}{#3}}{}% +} + +\newcommand{\@saildoc@environ@guard}[2]{% + % See \makesailcmds for why this space is needed + #1{#2} % +} + +\newcommand{\@saildoc@textbf}[1]{% + \ifcsname @capperm@\detokenize{#1}\endcsname% + \csname @capperm@\detokenize{#1}\endcsname% + \else% + \textbf{#1}% + \fi% +} + +\newcommand{\makesailcmds}[2]{% + \makesailcmds@core{#1}{#2}% + \ea\newcommand\csname #1isarefbody\endcsname[1]{{% + % + % Given: + % + % \saildoclabelled{foo}{\saildocfcl{bar}{baz}} + % + % we expand to capture foo, and expand the second argument again to capture + % bar and baz. + % + \global\let\@saildoclabelled@name\@saildoclabelled@name@error% + \global\let\@saildoclabelled@body\@saildoclabelled@body@error% + \global\let\@saildocfcl@doc\@saildocfcl@doc@error% + \global\let\@saildocfcl@fcl\@saildocfcl@fcl@error% + % + \let\saildoclabelled\@saildoclabelled@capture% + \let\saildocfcl\@saildocfcl@capture% + % + \csname #1code\endcsname*{##1}% + \@saildoclabelled@body% + % + \ea\ea\ea\ifx\ea\ea\ea\relax\ea\detokenize\ea{\@saildocfcl@doc}\relax% + \GenericWarning{}{#1 Warning: `##1` is not documented}% + \fi% + % + % Now for the fcl body, rewrite: + % + % Foo + % \subsection*{Exceptions} + % Bar + % \subsection*{Notes} + % Baz + % + % to: + % + % \@saildoc@environ@guard{\begin{@saildoc@subsection}}{Description} + % Foo + % \end{@saildoc@subsection} + % \@saildoc@environ@guard{\begin{@saildoc@subsection}}{Exceptions} + % Bar + % \end{@saildoc@subsection} + % \@saildoc@environ@guard{\begin{@saildoc@subsection}}{Notes} + % Baz + % \end{@saildoc@subsection} + % + % as well as using \@saildoc@subsubsection etc for all the other section + % commands. We allow the non-starred \subsection too. + % + % The extra space inserted by \@saildoc@environ@guard is required to avoid: + % + % \begin{@saildoc@subsection}{Foo}\end{@saildoc@subsection} + % + % as the lack of a token before \end confuses environ and makes it split + % Foo into argument "F" and body "oo". The space gets stripped away so + % \BODY will be empty. + % + \xpretocmd{\@saildocfcl@doc}{\@saildoc@environ@guard{\begin{@saildoc@subsection}}{Description}}{}{}% + \@saildoc@xpatchcmd@repeat{\@saildocfcl@doc}{\part}{\@saildoc@part}% + \@saildoc@xpatchcmd@repeat{\@saildocfcl@doc}{\chapter}{\@saildoc@chapter}% + \@saildoc@xpatchcmd@repeat{\@saildocfcl@doc}{\section}{\@saildoc@section}% + \@saildoc@xpatchcmd@repeat{\@saildocfcl@doc}{\subsection*}{\end{@saildoc@subsection}\@saildoc@environ@guard{\begin{@saildoc@subsection}}}% + \@saildoc@xpatchcmd@repeat{\@saildocfcl@doc}{\subsection}{\end{@saildoc@subsection}\@saildoc@environ@guard{\begin{@saildoc@subsection}}}% + \@saildoc@xpatchcmd@repeat{\@saildocfcl@doc}{\subsubsection}{\@saildoc@subsubsection}% + \@saildoc@xpatchcmd@repeat{\@saildocfcl@doc}{\paragraph}{\@saildoc@paragraph}% + \@saildoc@xpatchcmd@repeat{\@saildocfcl@doc}{\subparagraph}{\@saildoc@subparagraph}% + \xapptocmd{\@saildocfcl@doc}{\end{@saildoc@subsection}}{}{}% + % + % We also want to format various special names in our own way, all of which + % currently use \textbf in the saildoc output. + % + \@saildoc@xpatchcmd@repeat{\@saildocfcl@doc}{\textbf}{\@saildoc@textbf}% + % + % Now we have the right \begin and \end macros, with the latter directly + % visible to environ without any expansion, we can capture their contents + % by expanding again. + % + \@saildocfcl@doc% + % + % Finally reassemble the documentation in the right order with the Sail in + % the right place. We use \csuse to avoid having to pre-initialise + % everything to \@empty. + % + % Also add a label so that instruction references from saildoc resolve + % correctly. This label is not added by the saildoc generator so we insert + % it manually here using the sail mangling: z. This is + % really a valspec mangling, which allows us to link to the description + % rather than the function body and so saildoc's inability to reference + % function clauses in markdown turns out to be useful. + % + \label{#1z##1}% + \@saildoc@subsection@print{Description}% + % + \subsubsection*{Semantics}% + \phantomsection% + \label{\@saildoclabelled@name}% + \noindent\@saildocfcl@fcl% + % + \@saildoc@subsection@print{Exceptions}% + % + \@saildoc@subsection@print{Notes}% + % + % Reset state for next time + % + \@saildoc@subsection@clear% + }}% +} +\makeatother diff --git a/preamble.tex b/preamble.tex new file mode 100644 index 00000000..f8f61ab1 --- /dev/null +++ b/preamble.tex @@ -0,0 +1,536 @@ +\errorcontextlines 10000 +\usepackage{xparse} +\usepackage{xspace} +\usepackage{environ} +\usepackage{suffix} +\usepackage{xpatch} + +%\renewcommand{\baselinestretch}{2} % double space for editors +\usepackage[headings]{fullpage} +\usepackage{bitset} +\usepackage{comment} +\usepackage{graphicx} +\usepackage{marginnote} +\usepackage{booktabs} +\usepackage{ifthen} +\usepackage{bytefield} +\usepackage{rotating} +\input{binhex} +\makeatletter\@ifclassloaded{standalone}{% +% The svgnames option conflicts with \documentclass[tikz]{standalone} +\usepackage{xcolor} +}{% else +\usepackage[svgnames]{xcolor} +}\makeatother % end of \@ifclassloaded{standalone} +\definecolor{lightgray}{gray}{0.8} +\usepackage{times} +\usepackage{algpseudocode} +\newcommand{\note}[2]{{\color{blue}[ Note: #1 - #2]}} +%%%% +%%%% For releases, uncomment to cause notes to disappear: +%%%% +\renewcommand{\note}[2]{\relax\ifhmode\unskip\fi} +\newcommand{\deprecated}[2]{{\color{grey}[ Note: #1 - #2]}} +\newcommand{\ajnote}[1]{\note{#1}{Alexandre J.}} +\newcommand{\arnote}[1]{\note{#1}{Alex R.}} +\newcommand{\bdnote}[1]{\note{#1}{Brooks D.}} +\newcommand{\dcnote}[1]{\note{#1}{David C.}} +\newcommand{\hmnote}[1]{\note{#1}{Hesham A.}} +\newcommand{\jhbnote}[1]{\note{#1}{John B.}} +\newcommand{\jrtcnote}[1]{\note{#1}{Jess C.}} +\newcommand{\jwnote}[1]{\note{#1}{Jon W.}} +\newcommand{\knnote}[1]{\note{#1}{Kyndylan N.}} +\newcommand{\mmnote}[1]{\note{#1}{Marno vdM}} +\newcommand{\mrnote}[1]{\note{#1}{Michael R.}} +\newcommand{\nwfnote}[1]{\note{#1}{nwf}} +\newcommand{\pdrnote}[1]{\note{#1}{Peter R.}} +\newcommand{\pgnnote}[1]{\note{#1}{Peter N.}} +\newcommand{\pmnote}[1]{\note{#1}{Prashanth M.}} +\newcommand{\psnote}[1]{\note{#1}{Peter S.}} +\newcommand{\rmnnote}[1]{\note{#1}{Robert N.}} +\newcommand{\rwnote}[1]{\note{#1}{Robert W.}} +\newcommand{\smnote}[1]{\note{#1}{Simon M.}} +\newcommand{\tmnote}[1]{\note{#1}{Theo M.}} + +\usepackage{listings} +\usepackage{rotating} +\usepackage{setspace} +\usepackage{enumitem} +\usepackage{amsmath} +\usepackage{amssymb} +\usepackage{makecell} +\usepackage{hyphenat} + +\usepackage[utf8]{inputenc} +\usepackage[T1]{fontenc} + +\usepackage{tikz} + \usetikzlibrary{calc} + \usetikzlibrary{decorations.pathreplacing} + \usetikzlibrary{fit} + \usetikzlibrary{matrix} + \usetikzlibrary{positioning} + \usetikzlibrary{shapes} + \usetikzlibrary{patterns} + +\newcommand*{\circnum}[2][gray!25]{% + \protect\tikz[baseline={([yshift=-1.5pt]n.base)}]% + \protect\node[fill=#1,shape=circle,inner sep=1pt,draw](n){\tiny #2};} +\newlist{inenum}{enumerate*}{1} +\setlist[inenum]{label={\circnum{\arabic*}}} + +% Makes complex expansions slightly more readable +\let\ea\expandafter + +\usepackage[scaled=0.82]{beramono} + +\input{preamble-saildoc-macros} + +\makesailcmds{sailMIPS}{sail_latex_mips} +\makesailcmds{sailRISCV}{sail_latex_riscv} + +% Must be included later than setspace, otherwise all footnote hyperlinks +% point to the title page. +% PS HACK +%\usepackage[hidelinks]{hyperref} +\usepackage[colorlinks]{hyperref} +% Glossaries must be included after hyperref. +\usepackage[toc,nonumberlist]{glossaries} +\usepackage[nottoc]{tocbibind} +\usepackage[capitalise]{cleveref} + \Crefname{appendix}{Appendix}{Appendices} + \Crefname{figure}{Figure}{Figures} +\usepackage{footnote} +\usepackage{threeparttable} +\definecolor{CodeColour}{rgb}{0.9,0.9,0.9} %Light grey +\lstset{basicstyle=\small\ttfamily, + stringstyle=\textit, %italic strings + keywordstyle=\textbf, %Bold keywords + commentstyle=, + breaklines=true, % Wrap long lines + numbers=left, % Line numbers on the left + frame=l, %Border on the left + framerule=0.8pt, % Thick border + backgroundcolor=\color{CodeColour}, %Coloured code listings + numberstyle={\small \oldstylenums}, %tiny, old style line numbers + %stepnumber=5, % Number every fifth line + numbersep=5pt, % Five points between the line numbers and the text + tabsize=4 +} +\lstdefinelanguage{llvm} +{ + morekeywords={private, constant, i8, i32, define, icmp, label, i64, call, void, ret, getelementptr, br, load, align, nounwind}, + morekeywords={addrspace, inttoptr, ptrtoint, tail}, + morecomment=[l]; +}% + +\lstdefinelanguage{sail} + { morekeywords={val,function,cast,type,forall,foreach,from,to,overload,operator,enum,union,undefined,exit,and,assert,sizeof, + scattered,register,inc,dec,if,then,else,effect,let,as,@,in,end,Type,Int,Order,match,clause,struct}, + morestring=[b]", + stringstyle={\ttfamily\color{red}}, + showstringspaces=false, + morecomment=[l][\itshape\color{DarkGreen}]{//}, + morecomment=[s][\itshape\color{DarkGreen}]{/*}{*/}, + deletestring=[bd]{'}, + escapechar=\#, + emphstyle={\it}, + numbers=none, + frame=none, + backgroundcolor=\color{White}, + aboveskip=0em, + belowskip=0em, + } + +\lstdefinelanguage{bluespec} +{ morekeywords={function,endfunction,for,struct,typedef,Integer,Bit,Bool,TSub,TAdd,return,if,method}, + morestring=[b]"'=’-<>, + stringstyle={\ttfamily\color{red}}, + morecomment=[l][\itshape\color{DarkGreen}]{//}, + morecomment=[s][\itshape\color{DarkGreen}]{/*}{*/}, + emphstyle={\it}, +} + +\lstnewenvironment{ccodelisting}{\lstset{language=C}}{} +\lstnewenvironment{llvmlisting}{\lstset{language={llvm}}}{} +\newcommand{\ccode}[1]{\lstinline[backgroundcolor=\color{white},language=C]|#1|} +\newcommand{\llvmir}[1]{\lstinline[backgroundcolor=\color{white},language={llvm}]|#1|} +\newcommand{\asm}[1]{\lstinline[backgroundcolor=\color{white},language={}]|#1|} +\lstnewenvironment{asmcode}{\lstset{language=}}{} +\newcommand{\regname}[1]{{\small\ttfamily\$#1}} + +\newcommand{\baselineboxformatting}[1]{% + % Measure size of contents + \sbox0{#1}% + % Use the difference between the contents' height and the bitbox's height, + % clamped to [-.44\baselineskip, 0], as our minimum depth. + \setlength{\skip0}{\ht0 - \height}% + \ifdim\skip0>0pt% + \setlength{\skip0}{0}% + \else% + \ifdim\skip0<-.44\baselineskip% + \setlength{\skip0}{-.44\baselineskip}% + \fi% + \fi% + \centering\rule[\skip0]{0pt}{\height}#1% +} +\bytefieldsetup{boxformatting=\baselineboxformatting} + +% Well this is gross, but it lets us align baselines between labels and +% bytefields in tabular environments... by pretending that the label is +% a "bytefield" of one bit of the right width, with no bounding lines. +\newcommand{\raiseforbf}[1]{% + {\begin{bytefield}[bitwidth=\widthof{#1}]{1} \bitbox[]{1}{#1} \end{bytefield}}% +} + +\makeatletter +\newdimen\rotateinbitbox@height +\newcommand{\rotateinbitbox}[1]{% + \rotateinbitbox@height=\height% + \rotatebox{90}{\makebox[\rotateinbitbox@height][c]{#1}}% +} +\makeatother + +\hyphenation{CheriBSD} +\hyphenation{FreeBSD} +\hyphenation{CTSRD} +\hyphenation{CheriRTOS} + +\reversemarginpar +\setlength{\marginparwidth}{1.2in} +\let\oldmarginpar\marginpar +\renewcommand\marginpar[1]{\-\oldmarginpar[\raggedright\footnotesize #1]% +{\raggedright\footnotesize #1}} + +\newcommand{\pathname}[1]{\tt \small #1} +\newcommand{\literal}[1]{{\tt \small #1}} +\newcommand{\function}[1]{{\tt \small #1}} + +% Register names +\newcommand{\reg}[1]{{\bf R#1}} % MIPS register numbers +\newcommand{\creg}[1]{{\bf C#1}} % Capability register numbers +\newcommand{\mreg}[1]{{\bf \$#1}} % MIPS ABI register names +\newcommand{\PC}{{\bf PC}} +\newcommand{\SP}{{\bf SP}} +\newcommand{\EPC}{{\bf EPC}} +\newcommand{\PCC}{{\bf PCC}} +\newcommand{\DDC}{{\bf DDC}} +\newcommand{\CNULL}{{\bf CNULL}} +\newcommand{\IDC}{{\bf IDC}} +\newcommand{\TSC}{{\bf TSC}} +\newcommand{\KRC}{{\bf KR1C}} +\newcommand{\KQC}{{\bf KR2C}} +\newcommand{\KCC}{{\bf KCC}} +\newcommand{\KDC}{{\bf KDC}} +\newcommand{\ErrorEPCC}{{\bf ErrorEPCC}} +\newcommand{\EPCC}{{\bf EPCC}} +\newcommand{\CULR}{{\bf CULR}} +\newcommand{\CPLR}{{\bf CPLR}} +\newcommand{\EXL}{{\bf EXL}} +\newcommand{\KSU}{{\bf KSU}} +\newcommand{\ErrorEPC}{{\bf ErrorEPC}} +\newcommand{\causereg}{{\bf cause}} +\newcommand{\capcausereg}{{\bf capcause}} + +% RISC-V new register names +\newcommand{\UTCC}{{\bf UTCC}} +\newcommand{\UTDC}{{\bf UTDC}} +\newcommand{\UScratchC}{{\bf UScratchC}} +\newcommand{\UEPCC}{{\bf UEPCC}} +\newcommand{\STCC}{{\bf STCC}} +\newcommand{\STDC}{{\bf STDC}} +\newcommand{\SScratchC}{{\bf SScratchC}} +\newcommand{\SEPCC}{{\bf SEPCC}} +\newcommand{\MTCC}{{\bf MTCC}} +\newcommand{\MTDC}{{\bf MTDC}} +\newcommand{\MScratchC}{{\bf MScratchC}} +\newcommand{\MEPCC}{{\bf MEPCC}} +\newcommand{\xTCC}{{\bf {\it x}TCC}} +\newcommand{\xTDC}{{\bf {\it x}TDC}} +\newcommand{\xScratchC}{{\bf {\it x}ScratchC}} +\newcommand{\xEPCC}{{\bf {\it x}EPCC}} +\newcommand{\xccsr}{\texttt{{\it x}ccsr}} +\newcommand{\mccsr}{\texttt{mccsr}} +\newcommand{\sccsr}{\texttt{sccsr}} +\newcommand{\uccsr}{\texttt{uccsr}} +% RISC-V existing registers +\newcommand{\xtval}{\texttt{{\it x}tval}} +\newcommand{\xtvec}{\texttt{{\it x}tvec}} +\newcommand{\mtvec}{\texttt{mtvec}} +\newcommand{\stvec}{\texttt{stvec}} +\newcommand{\utvec}{\texttt{utvec}} +\newcommand{\xepc}{\texttt{{\it x}epc}} +\newcommand{\mepc}{\texttt{mepc}} +\newcommand{\sepc}{\texttt{sepc}} +\newcommand{\uepc}{\texttt{uepc}} +\newcommand{\xcause}{\texttt{{\it x}cause}} +\newcommand{\mcause}{\texttt{mcause}} +\newcommand{\scause}{\texttt{scause}} +\newcommand{\ucause}{\texttt{ucause}} +\newcommand{\xRET}{\insnnoref{{\it x}RET}} + +\newcommand{\AL}{{\bf AL}} +\newcommand{\AX}{{\bf AX}} +\newcommand{\FS}{{\bf FS}} +\newcommand{\GS}{{\bf GS}} +\newcommand{\EAX}{{\bf EAX}} +\newcommand{\CAX}{{\bf CAX}} +\newcommand{\CBP}{{\bf CBP}} +\newcommand{\CBX}{{\bf CBX}} +\newcommand{\CFS}{{\bf CFS}} +\newcommand{\CGS}{{\bf CGS}} +\newcommand{\CDI}{{\bf CDI}} +\newcommand{\CIP}{{\bf CIP}} +\newcommand{\KGS}{{\bf KGS}} +\newcommand{\CRTWO}{{\bf CR2}} +\newcommand{\CRFOUR}{{\bf CR4}} +\newcommand{\CRFIVE}{{\bf CR5}} +\newcommand{\CRTWELVE}{{\bf CR12}} +\newcommand{\CS}{{\bf CS}} +\newcommand{\CSI}{{\bf CSI}} +\newcommand{\CSP}{{\bf CSP}} +\newcommand{\IDT}{{\bf IDT}} +\newcommand{\IST}{{\bf IST}} +\newcommand{\KSC}{{\bf KSC}} +\newcommand{\RAX}{{\bf RAX}} +\newcommand{\RBP}{{\bf RBP}} +\newcommand{\RBX}{{\bf RBX}} +\newcommand{\RCX}{{\bf RCX}} +\newcommand{\RDI}{{\bf RDI}} +\newcommand{\REX}{{\bf REX}} +\newcommand{\RIP}{{\bf RIP}} +\newcommand{\RSI}{{\bf RSI}} +\newcommand{\RSP}{{\bf RSP}} +\newcommand{\RFLAGS}{{\bf RFLAGS}} +\newcommand{\TSS}{{\bf TSS}} +\newcommand{\CSTAR}{{\bf CSTAR}} +\newcommand{\STAR}{{\bf IA32\_STAR}} +\newcommand{\LSTAR}{{\bf IA32\_LSTAR}} +\newcommand{\KGSBASE}{{\bf IA32\_KERNEL\_GS\_BASE}} + +% Capability register fields +\newcommand{\ctag}{{\bf tag}} +\newcommand{\csealed}{{\bf s}} +\newcommand{\cperms}{{\bf perms}} +\newcommand{\cuperms}{{\bf uperms}} +\newcommand{\cflags}{{\bf flags}} +\newcommand{\cotype}{{\bf otype}} +\newcommand{\ccursor}{{\bf cursor}} +\newcommand{\cbase}{{\bf base}} +\newcommand{\clength}{{\bf length}} +\newcommand{\coffset}{{\bf offset}} +\newcommand{\cbound}{{\bf top}} + +% CHERI-128 v1 capability fields +\newcommand{\ctobase}{{\bf toBase}} +\newcommand{\ctobound}{{\bf toBound}} +\newcommand{\cformat}{{\bf FT}} +\newcommand{\cexponent}{{\bf e}} +\newcommand{\csign}{{\bf SN}} + +% CHERI-128 v1 capability fields +\newcommand{\cbasebits}{{\bf baseBits}} +\newcommand{\ctopbits}{{\bf topBits}} +\newcommand{\ccarries}{{\bf C}} + +% CHERI-128 candidate 3 fields +\newcommand{\ctop}{{\bf top}} +%\newcommand{\rbase}{\textbf{base\textsubscript{req}}} +\newcommand{\rbase}{\textbf{base\_req}} +\newcommand{\cbasecorrection}{\textbf{c\textsubscript{b}}} +%\newcommand{\cbasecorrection}{\textbf{c\_b}} +%\newcommand{\rlength}{\textbf{length\textsubscript{req}}} +\newcommand{\rlength}{\textbf{rlength}} +\newcommand{\ctopcorrection}{\textbf{c\textsubscript{t}}} +%\newcommand{\ctopcorrection}{\textbf{ctop}} - SWM: why use this version? +\newcommand{\cB}{{\bf B}} +\newcommand{\cT}{{\bf T}} +\newcommand{\caddr}{{\bf a}} + +% Architectural parameters +\newcommand{\xlen}{{\texttt{XLEN}}} +\newcommand{\clen}{{\texttt{CLEN}}} + +% Field used in several compression formats +\newcommand{\cmuperms}{$\boldsymbol{\mu}\textbf{perms}$} + +% Stylized permission bit. Starred form omits Permit\_ prefix for informal +% references. +\NewDocumentCommand{\capperm}{sm}{\textsc{\small\IfBooleanTF{#1}{}{Permit\_}#2}\xspace} +% Permission bit convenience macros +% We define a short form for normal use and a long @-command form for internal +% use by saildoc. +\makeatletter +\NewDocumentCommand{\makecapperm}{smm}{% + \def\@make@capperm##1##2{% + \ea\NewDocumentCommand\csname @capperm@\detokenize{##2#3}\endcsname{s}{% + \IfBooleanTF{####1}{\capperm*}{\capperm##1}{#3}% + }% + \ea\ea\ea\let\ea\csname capperm#2\ea\endcsname% + \csname @capperm@\detokenize{##2#3}\endcsname% + }% + \IfBooleanTF{#1}{\@make@capperm{*}{}}{\@make@capperm{}{Permit\_}}% + \let\@make@capperm\undefined% +} +\makeatother +\makecapperm{ASR}{Access\_System\_Registers} +\makecapperm{Cid}{Set\_CID} +\makecapperm{CInvoke}{CInvoke} +\makecapperm{L}{Load} +\makecapperm{LC}{Load\_Capability} +\makecapperm{S}{Store} +\makecapperm{Seal}{Seal} +\makecapperm{SC}{Store\_Capability} +\makecapperm{SLC}{Store\_Local\_Capability} +\makecapperm{Unseal}{Unseal} +\makecapperm{X}{Execute} +% No Permit_, so always use starred form even if not given +\makecapperm*{G}{Global} + +\makeatletter +\newcommand{\@insnlabelname}[2]{insn:#1:#2} +\newcommand{\@insnlabel}[2]{\label{\@insnlabelname{#1}{#2}}} + +% If no optional argument is passed (internally, if an empty second argument is +% passed), the lowercased text is the label reference +\newcommand{\@insnrefnofont}[3]{{% + \if\relax\detokenize{#2}\relax% optional arg not passed + % NB: \lowercase is not expandable so is outside the \def. + \lowercase{\def\@insnrefnofont@insnname{#3}}% + \else% optional arg passed + \def\@insnrefnofont@insnname{#2}% + \fi% + \hyperref[\@insnlabelname{#1}{\@insnrefnofont@insnname}]{#3}% +}} + +\NewDocumentCommand{\@insnfmt}{sm}{% + \IfBooleanTF{#1}{#2}{{\tt \small #2}}% +} + +\NewDocumentCommand{\@insnref}{smmm}{% + \IfBooleanTF{#1}{\@insnfmt*}{\@insnfmt}{\@insnrefnofont{#2}{#3}{#4}}% +} + +\newcommand{\@makeinsncmds@explicit}[2]{% + \ea\newcommand\csname insn#1labelname\endcsname[1]{\@insnlabelname{#2}{##1}}% + \ea\newcommand\csname insn#1label\endcsname[1]{\@insnlabel{#2}{##1}}% + \ea\NewDocumentCommand\csname insn#1ref\endcsname{sO{}m}{% + \IfBooleanTF{##1}{\@insnref*}{\@insnref}{#2}{##2}{##3}% + }% +} +\newcommand{\@makeinsncmds}[1]{\@makeinsncmds@explicit{#1}{#1}} + +\@makeinsncmds{mips} +\@makeinsncmds{riscv} + +% Default is currently MIPS +\@makeinsncmds@explicit{}{mips} + +\let\insnnoref\@insnfmt +\makeatother + +\newcommand{\cherithreeop}[5][NOHEADER]{ +\begin{bytefield}{32} + \ifthenelse{\equal{#1}{NOHEADER}}{} + {\bitheader[endianness=big]{0,5,6,10,11,15,16,20,21,25,26,31}}\\ + \bitbox{6}{{\color{Grey}0x12}} + \bitbox{5}{0x0} + \bitbox{5}{#3} + \bitbox{5}{#4} + \bitbox{5}{#5} + \bitbox{6}{#2} +\end{bytefield}% +} +\newcommand{\cheritwoop}[4][NOHEADER]{\cherithreeop[#1]{{\color{Grey}0x3f}}{#3}{#4}{#2}} +\newcommand{\cherioneop}[3][NOHEADER]{\cheritwoop[#1]{{\color{Grey}0x1f}}{#3}{#2}} + + +\newcommand{\usesDDCinsteadofNULL}[1]{% +\paragraph{Note:} +If the encoded value of \emph{#1} is zero, this instruction will use +\DDC{} as the \emph{#1} operand +} + +% When specifying instructions in pseudocode: +\newcommand{\algorithmicnot}{\textbf{not}} +\newcommand{\algorithmicand}{\textbf{and}} +\newcommand{\algorithmicor}{\textbf{or}} +\newcommand{\algorithmictrue}{\textbf{true}} +\newcommand{\algorithmicfalse}{\textbf{false}} +\newcommand{\algorithmicwith}{\textbf{with}} + +% Markdown and Sail's LaTeX backend don't do well with literal < and >, so add +% \lt and \gt macros like \le and \ge. +\let\lt< +\let\gt> + +\makeatletter +\newcount\@autogrid@col +\newcount\@autogrid@cols +\def\@autogrid@cr{% + \global\advance\@autogrid@col 1\relax% + \ifnum\@autogrid@col=\@autogrid@cols% + \def\@autogrid@cr@body{\cr}% + \global\@autogrid@col=0\relax% + \else% + \def\@autogrid@cr@body{&}% + \fi% + \@autogrid@cr@body% + \let\\\@autogrid@cr% +} +\newenvironment{autogrid}[1]{% + \let\@autogrid@format\@empty% + \@autogrid@cols=\numexpr(#1)\relax% + \@autogrid@col=0\relax% + \loop\ifnum\@autogrid@col<\@autogrid@cols% + \ea\def\ea\@autogrid@format\ea{\@autogrid@format l}% + \advance\@autogrid@col 1\relax% + \repeat% + \@autogrid@col=0\relax% + \def\@autogrid@begintabular{\begin{tabular}}% + \ea\@autogrid@begintabular\ea{\@autogrid@format}% + \let\\\@autogrid@cr% +}{% + \end{tabular}% +} +\makeatother + + +\makeatletter\@ifclassloaded{standalone}{% +% No need for glossary or bibliography when building tikz figures +}{% else +\renewcommand{\glossarypreamble}{\label{glossary}} +\makeglossaries + +\input{glossary} + + +%% bibliography setup: +% UK date format in bibliography: +\usepackage[british]{babel} +\usepackage{csquotes} % recommended for biblatex +% list up to 99 names instead of the default 3 and set +% giveninits=true to match the abbrv bibtex style. +\usepackage[backend=biber,bibencoding=utf8,style=numeric,sortcites,maxnames=99,giveninits=true]{biblatex} +\addbibresource{cheri.bib} +% Note: \citetitle formats the title differently depending on the type of entry, +% whereas this macro always uses \textit{} +\newcommand*{\citetitleit}[1]{\textit{\citefield{#1}{title}}} + + +% Skip unncessary bibtex fields in the bibliography +\AtEveryBibitem{% +\clearfield{issn}% +\clearfield{urldate}% +\clearfield{urlyear}% +\clearfield{review}% +\clearfield{series}% +\clearfield{note}% +\clearfield{address}% +% avoid printing both isbn and DOI +\iffieldundef{doi}{}{\clearfield{isbn}}% +% we don't want 15 JJ Thomson Avenue, Cambridge for every techreport +% Note: location is a list not a field so we need \clearlist +\clearlist{location}% +} +}\makeatother % end of \@ifclassloaded{standalone} diff --git a/sail_latex_mips/0GENERATED_FILES_DO_NOT_EDIT b/sail_latex_mips/0GENERATED_FILES_DO_NOT_EDIT new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_mips/block06715b2a132b169cecda227894974882.sail b/sail_latex_mips/block06715b2a132b169cecda227894974882.sail new file mode 100644 index 00000000..282aa290 --- /dev/null +++ b/sail_latex_mips/block06715b2a132b169cecda227894974882.sail @@ -0,0 +1,2 @@ +Note that this includes both sealed (e.g. sentry) and unsealed (e.g. all ones) +otypes. \ No newline at end of file diff --git a/sail_latex_mips/block7c9393e4ce2c29e4e1dc024db508cec2.sail b/sail_latex_mips/block7c9393e4ce2c29e4e1dc024db508cec2.sail new file mode 100644 index 00000000..4201c101 --- /dev/null +++ b/sail_latex_mips/block7c9393e4ce2c29e4e1dc024db508cec2.sail @@ -0,0 +1 @@ +let elsize = shl_int(8, UInt(size)) \ No newline at end of file diff --git a/sail_latex_mips/commands.tex b/sail_latex_mips/commands.tex new file mode 100644 index 00000000..f60eaa78 --- /dev/null +++ b/sail_latex_mips/commands.tex @@ -0,0 +1,4698 @@ +\providecommand\saildoclabelled[2]{\phantomsection\label{#1}#2} +\providecommand\saildocval[2]{#1 #2} +\providecommand\saildocfcl[2]{#1 #2} +\providecommand\saildoctype[2]{#1 #2} +\providecommand\saildocfn[2]{#1 #2} +\providecommand\saildocoverload[2]{#1 #2} +\providecommand\saildocabbrev[1]{#1\@} + +\newcommand{\sailMIPSvaleqBitTwo}{\saildoclabelled{sailMIPSzeqzybit2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzeq_bit250da3631e266dec9fd09db78de2c816f.tex}}}} + +\newcommand{\sailMIPSoverloadBzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailMIPSoverloadBzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadBzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} + +\newcommand{\sailMIPSvaledivInt}{\saildoclabelled{sailMIPSzedivzyint}{\saildocval{Euclidean division + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzediv_int5aaf4d3d5a3d15a7aebaf90d3bfb6650.tex}}}} + +\newcommand{\sailMIPSvalemodInt}{\saildoclabelled{sailMIPSzemodzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzemod_int8e3d74b3b6a72e24e6bd03570d8e21ba.tex}}}} + +\newcommand{\sailMIPSvalabsIntAtom}{\saildoclabelled{sailMIPSzabszyintzyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzabs_int_atom414063313cc5ac5d9a742f9c8a111704.tex}}}} + +\newcommand{\sailMIPSoverloadCabsInt}{\saildoclabelled{sailMIPSoverloadCzabszyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadCzabs_intef5fbb521189282054dc80dc7173013d.tex}}}} + +\newcommand{\sailMIPSvaleqUnit}{\saildoclabelled{sailMIPSzeqzyunit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzeq_unit996f84433ac0995f4aadfca5b68cd358.tex}}}} + +\newcommand{\sailMIPSvaleqBit}{\saildoclabelled{sailMIPSzeqzybit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzeq_bit7182cc37406e2c0d4c1e739a98e248ea.tex}}}} + +\newcommand{\sailMIPSfneqUnit}{\saildoclabelled{sailMIPSfnzeqzyunit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzeq_unit996f84433ac0995f4aadfca5b68cd358.tex}}}} + +\newcommand{\sailMIPSvalnotBool}{\saildoclabelled{sailMIPSznotzybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznot_boole1dd3e44bc87a2a10d8e257004c2d36a.tex}}}} + +\newcommand{\sailMIPSvalandBool}{\saildoclabelled{sailMIPSzandzybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzand_boola4a2cf9ccaa44106300961b15ab20e79.tex}}}} + +\newcommand{\sailMIPSvalandBoolNoFlow}{\saildoclabelled{sailMIPSzandzyboolzynozyflow}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzand_bool_no_flow5d5041fa8ff689136cdc03e3a11eda3a.tex}}}} + +\newcommand{\sailMIPSvalorBool}{\saildoclabelled{sailMIPSzorzybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzor_bool5f07f9d72d4d1495c45a3531c787546a.tex}}}} + +\newcommand{\sailMIPSvaleqInt}{\saildoclabelled{sailMIPSzeqzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzeq_int364a98dbf8a9faa70e666cce41d8c1aa.tex}}}} + +\newcommand{\sailMIPSvaleqBool}{\saildoclabelled{sailMIPSzeqzybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzeq_bool0e93587306381c3f984dc7cea6ae190d.tex}}}} + +\newcommand{\sailMIPSvalneqInt}{\saildoclabelled{sailMIPSzneqzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex}}}} + +\newcommand{\sailMIPSfnneqInt}{\saildoclabelled{sailMIPSfnzneqzyint}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex}}}} + +\newcommand{\sailMIPSvalneqBool}{\saildoclabelled{sailMIPSzneqzybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex}}}} + +\newcommand{\sailMIPSfnneqBool}{\saildoclabelled{sailMIPSfnzneqzybool}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex}}}} + +\newcommand{\sailMIPSvallteqInt}{\saildoclabelled{sailMIPSzlteqzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzlteq_intc80d1082e443aa434e39355e493ece1e.tex}}}} + +\newcommand{\sailMIPSvalgteqInt}{\saildoclabelled{sailMIPSzgteqzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzgteq_inte32033a8d137f46d187455cff7dbe40e.tex}}}} + +\newcommand{\sailMIPSvalltInt}{\saildoclabelled{sailMIPSzltzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzlt_int996a8b8c361a31bed6b5509ca6686e1a.tex}}}} + +\newcommand{\sailMIPSvalgtInt}{\saildoclabelled{sailMIPSzgtzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzgt_intef94a8c66f39b1f715cb72941ed95921.tex}}}} + +\newcommand{\sailMIPSoverloadDzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailMIPSoverloadDzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadDzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} + +\newcommand{\sailMIPSoverloadEzEightoperatorzZerozOnezJzNine}{\saildoclabelled{sailMIPSoverloadEzz8operatorz0z1zJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadEzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex}}}} + +\newcommand{\sailMIPSoverloadFzEightoperatorzZerozUzNine}{\saildoclabelled{sailMIPSoverloadFzz8operatorz0zUz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadFzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex}}}} + +\newcommand{\sailMIPSoverloadGzEightoperatorzZerozSixzNine}{\saildoclabelled{sailMIPSoverloadGzz8operatorz0z6z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadGzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex}}}} + +\newcommand{\sailMIPSoverloadHzEightoperatorzZerozIzJzNine}{\saildoclabelled{sailMIPSoverloadHzz8operatorz0zIzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadHzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex}}}} + +\newcommand{\sailMIPSoverloadIzEightoperatorzZerozIzNine}{\saildoclabelled{sailMIPSoverloadIzz8operatorz0zIz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadIzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex}}}} + +\newcommand{\sailMIPSoverloadJzEightoperatorzZerozKzJzNine}{\saildoclabelled{sailMIPSoverloadJzz8operatorz0zKzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadJzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex}}}} + +\newcommand{\sailMIPSoverloadKzEightoperatorzZerozKzNine}{\saildoclabelled{sailMIPSoverloadKzz8operatorz0zKz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadKzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex}}}} + +\newcommand{\sailMIPSvalId}{\saildoclabelled{sailMIPSzzyzyid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz__ided888b8991a27578d5dd72f84db80bce.tex}}}} + +\newcommand{\sailMIPSfnId}{\saildoclabelled{sailMIPSfnzzyzyid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz__ided888b8991a27578d5dd72f84db80bce.tex}}}} + +\newcommand{\sailMIPSoverloadLSizze}{\saildoclabelled{sailMIPSoverloadLzzyzysizze}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadLz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex}}}} + +\newcommand{\sailMIPSvalDeref}{\saildoclabelled{sailMIPSzzyzyderef}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz__deref1dbc379e24bd1b182e1db755dea8c453.tex}}}} + +\newcommand{\sailMIPSvalBitfieldDeref}{\saildoclabelled{sailMIPSzzyzybitfieldzyderef}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz__bitfield_deref5ed587b7c1b91cf82e42f865304262ca.tex}}}} + +\newcommand{\sailMIPSvaladdAtom}{\saildoclabelled{sailMIPSzaddzyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzadd_atomd34efc9e611b6d3b6757e17f4932b12b.tex}}}} + +\newcommand{\sailMIPSvaladdInt}{\saildoclabelled{sailMIPSzaddzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzadd_intb17710be4fd02ace68d83b9dba907034.tex}}}} + +\newcommand{\sailMIPSoverloadMzEightoperatorzZerozBzNine}{\saildoclabelled{sailMIPSoverloadMzz8operatorz0zBz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadMzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex}}}} + +\newcommand{\sailMIPSvalsubAtom}{\saildoclabelled{sailMIPSzsubzyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsub_atom328a68dfbab1a07c42d4e7b98eac766f.tex}}}} + +\newcommand{\sailMIPSvalsubInt}{\saildoclabelled{sailMIPSzsubzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsub_intf17f348f33594e77fdc3ef8b6a46b569.tex}}}} + +\newcommand{\sailMIPSoverloadNzEightoperatorzZerozDzNine}{\saildoclabelled{sailMIPSoverloadNzz8operatorz0zDz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadNzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex}}}} + +\newcommand{\sailMIPSvalsubNat}{\saildoclabelled{sailMIPSzsubzynat}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsub_nat1e51a6ef44b288dd12f7f69af44dfd3e.tex}}}} + +\newcommand{\sailMIPSvalnegateAtom}{\saildoclabelled{sailMIPSznegatezyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznegate_atomfefdbde89b468d9df54837e864426d70.tex}}}} + +\newcommand{\sailMIPSvalnegateInt}{\saildoclabelled{sailMIPSznegatezyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznegate_int42f776f84c124d77c3e367500082e43f.tex}}}} + +\newcommand{\sailMIPSoverloadOnegate}{\saildoclabelled{sailMIPSoverloadOznegate}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadOznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex}}}} + +\newcommand{\sailMIPSvalmultAtom}{\saildoclabelled{sailMIPSzmultzyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmult_atomdbad478b99777b7676dde1f5a7900711.tex}}}} + +\newcommand{\sailMIPSvalmultInt}{\saildoclabelled{sailMIPSzmultzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmult_inte25d1b032a27b461f0eaf0c84be37a2b.tex}}}} + +\newcommand{\sailMIPSoverloadPzEightoperatorzZerozAzNine}{\saildoclabelled{sailMIPSoverloadPzz8operatorz0zAz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadPzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex}}}} + +\newcommand{\sailMIPSvalprintInt}{\saildoclabelled{sailMIPSzprintzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzprint_intfb625bfb7a4021903513aeb4396bd878.tex}}}} + +\newcommand{\sailMIPSvalprerrInt}{\saildoclabelled{sailMIPSzprerrzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzprerr_int00b48f715fbb32df5901801dff63b643.tex}}}} + +\newcommand{\sailMIPSvalShlEight}{\saildoclabelled{sailMIPSzzyshl8}{\saildocval{A common idiom in asl is to take two bits of an opcode and convert in into a variable like + +\lstinputlisting[language=sail]{sail_latex_mips/block7c9393e4ce2c29e4e1dc024db508cec2.sail}\lstinline{_shl8} ensures that in this case the typechecker knows that the end result will be a value in the set \lstinline`{8, 16, 32, 64}` + +Similarly, we define shifts of 32 and 1 (i.e., powers of two). + +}{\lstinputlisting[language=sail]{sail_latex_mips/valz_shl8e01c74b934d4c323501a597baa8e6f73.tex}}}} + +\newcommand{\sailMIPSvalShlThreeTwo}{\saildoclabelled{sailMIPSzzyshl32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_shl32469ae968a52f81e1a28aeacf7e2d496b.tex}}}} + +\newcommand{\sailMIPSvalShlOne}{\saildoclabelled{sailMIPSzzyshl1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_shl1b261f5995acb90d475c10ee0cdbc12ce.tex}}}} + +\newcommand{\sailMIPSvalShlInt}{\saildoclabelled{sailMIPSzzyshlzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_shl_int86f4e1bc3609625860bc16734d7f2614.tex}}}} + +\newcommand{\sailMIPSoverloadQshlInt}{\saildoclabelled{sailMIPSoverloadQzshlzyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadQzshl_int4772030e3fc0913189e795ec25e86dc5.tex}}}} + +\newcommand{\sailMIPSvalShrThreeTwo}{\saildoclabelled{sailMIPSzzyshr32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_shr328ec48e4bcaebfdbf5c374b77ca7b535b.tex}}}} + +\newcommand{\sailMIPSvalShrInt}{\saildoclabelled{sailMIPSzzyshrzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_shr_int34025c843d841a08930cb64bf99a1693.tex}}}} + +\newcommand{\sailMIPSoverloadRshrInt}{\saildoclabelled{sailMIPSoverloadRzshrzyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadRzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex}}}} + +\newcommand{\sailMIPSvaltdivInt}{\saildoclabelled{sailMIPSztdivzyint}{\saildocval{Truncating division (rounds towards zero) + +}{\lstinputlisting[language=sail]{sail_latex_mips/valztdiv_int5e119ac7ab9ff04c8877846f345d1159.tex}}}} + +\newcommand{\sailMIPSvalTmodInt}{\saildoclabelled{sailMIPSzzytmodzyint}{\saildocval{Remainder for truncating division (has sign of dividend) + +}{\lstinputlisting[language=sail]{sail_latex_mips/valz_tmod_inta2984ba6dbfa10758476d9b3b7f62560.tex}}}} + +\newcommand{\sailMIPSvalTmodIntPositive}{\saildoclabelled{sailMIPSzzytmodzyintzypositive}{\saildocval{If we know the second argument is positive, we know the result is positive + +}{\lstinputlisting[language=sail]{sail_latex_mips/valz_tmod_int_positive6f0621d972182279e90a43c082e50c10.tex}}}} + +\newcommand{\sailMIPSoverloadStmodInt}{\saildoclabelled{sailMIPSoverloadSztmodzyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadSztmod_int76b131b53b88df8b201279295eacebbe.tex}}}} + +\newcommand{\sailMIPSvalfdivInt}{\saildoclabelled{sailMIPSzfdivzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex}}}} + +\newcommand{\sailMIPSfnfdivInt}{\saildoclabelled{sailMIPSfnzfdivzyint}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex}}}} + +\newcommand{\sailMIPSvalfmodInt}{\saildoclabelled{sailMIPSzfmodzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzfmod_int7e215ca2b888f4e92201959fd40958a5.tex}}}} + +\newcommand{\sailMIPSfnfmodInt}{\saildoclabelled{sailMIPSfnzfmodzyint}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzfmod_int7e215ca2b888f4e92201959fd40958a5.tex}}}} + +\newcommand{\sailMIPSvalabsIntPlain}{\saildoclabelled{sailMIPSzabszyintzyplain}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzabs_int_plainb54aa4afeed2c86b519a464eb2e4c77c.tex}}}} + +\newcommand{\sailMIPSoverloadTabsInt}{\saildoclabelled{sailMIPSoverloadTzabszyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadTzabs_intef5fbb521189282054dc80dc7173013d.tex}}}} + +\newcommand{\sailMIPStypeoption}{\saildoclabelled{sailMIPStypezoption}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezoptiona3271ef8b6a63c78e6db36dac0ee6547.tex}}}} + +\newcommand{\sailMIPSvalisNone}{\saildoclabelled{sailMIPSziszynone}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzis_nonebebf4558161c4d567fb50f7df9e82374.tex}}}} + +\newcommand{\sailMIPSfnisNone}{\saildoclabelled{sailMIPSfnziszynone}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzis_nonebebf4558161c4d567fb50f7df9e82374.tex}}}} + +\newcommand{\sailMIPSvalisSome}{\saildoclabelled{sailMIPSziszysome}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex}}}} + +\newcommand{\sailMIPSfnisSome}{\saildoclabelled{sailMIPSfnziszysome}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex}}}} + +\newcommand{\sailMIPStypebits}{\saildoclabelled{sailMIPStypezbits}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezbitsa4b31f9b3dc11c921007b665e0d0fce6.tex}}}} + +\newcommand{\sailMIPSvaleqBits}{\saildoclabelled{sailMIPSzeqzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzeq_bits886ce7cf3ec93a28308e8d4e9d63f4be.tex}}}} + +\newcommand{\sailMIPSoverloadUzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailMIPSoverloadUzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadUzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} + +\newcommand{\sailMIPSvalneqBits}{\saildoclabelled{sailMIPSzneqzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzneq_bits167748c906c068e62596c88540a84f42.tex}}}} + +\newcommand{\sailMIPSfnneqBits}{\saildoclabelled{sailMIPSfnzneqzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzneq_bits167748c906c068e62596c88540a84f42.tex}}}} + +\newcommand{\sailMIPSoverloadVzEightoperatorzZerozOnezJzNine}{\saildoclabelled{sailMIPSoverloadVzz8operatorz0z1zJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadVzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex}}}} + +\newcommand{\sailMIPSvalbitvectorLength}{\saildoclabelled{sailMIPSzbitvectorzylength}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzbitvector_lengthcd74a5cced7567d19500671e4b6e1031.tex}}}} + +\newcommand{\sailMIPSvalvectorLength}{\saildoclabelled{sailMIPSzvectorzylength}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzvector_length9ee541b308cdfd9738d44bfb3dff4b46.tex}}}} + +\newcommand{\sailMIPSoverloadWlength}{\saildoclabelled{sailMIPSoverloadWzlength}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadWzlength469e3f917f7b24f4691faf3caf842eba.tex}}}} + +\newcommand{\sailMIPSvalcountLeadingZeros}{\saildoclabelled{sailMIPSzcountzyleadingzyzzeros}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcount_leading_zzeros315ae28f559df1d42a7d2ca4cfff2905.tex}}}} + +\newcommand{\sailMIPSvalprintBits}{\saildoclabelled{sailMIPSzprintzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzprint_bits30cf225474fbf3e575d7aa83aa309559.tex}}}} + +\newcommand{\sailMIPSvalprerrBits}{\saildoclabelled{sailMIPSzprerrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzprerr_bits932899725108ebe483d3226f250f2b92.tex}}}} + +\newcommand{\sailMIPSvalsailSignExtend}{\saildoclabelled{sailMIPSzsailzysignzyextend}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsail_sign_extendb66ac7c1aaedb0cb21bdf07e4518af5e.tex}}}} + +\newcommand{\sailMIPSvalsailZeroExtend}{\saildoclabelled{sailMIPSzsailzyzzerozyextend}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsail_zzero_extend411875c18d3b332113845d17151890c2.tex}}}} + +\newcommand{\sailMIPSvaltruncate}{\saildoclabelled{sailMIPSztruncate}{\saildocval{\lstinline{truncate}\lstinline`(v, n)` truncates \lstinline`v`, keeping only the \emph{least} significant \lstinline`n` bits. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valztruncatea666e28ae0c8ca7327a2b3fcd1ed4ec7.tex}}}} + +\newcommand{\sailMIPSvaltruncateLSB}{\saildoclabelled{sailMIPSztruncateLSB}{\saildocval{\lstinline{truncateLSB}\lstinline`(v, n)` truncates \lstinline`v`, keeping only the \emph{most} significant \lstinline`n` bits. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valztruncatelsb4d124c6ec672453343dc0b20d295e82d.tex}}}} + +\newcommand{\sailMIPSvalsailMask}{\saildoclabelled{sailMIPSzsailzymask}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsail_maske146b73afc824e90813dd8234bfa3053.tex}}}} + +\newcommand{\sailMIPSfnsailMask}{\saildoclabelled{sailMIPSfnzsailzymask}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzsail_maske146b73afc824e90813dd8234bfa3053.tex}}}} + +\newcommand{\sailMIPSoverloadXzEightoperatorzZerozQzNine}{\saildoclabelled{sailMIPSoverloadXzz8operatorz0zQz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadXzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex}}}} + +\newcommand{\sailMIPSvalbitvectorConcat}{\saildoclabelled{sailMIPSzbitvectorzyconcat}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzbitvector_concat6176f8be1468d8779ee8370fd3b4a6e0.tex}}}} + +\newcommand{\sailMIPSoverloadYappend}{\saildoclabelled{sailMIPSoverloadYzappend}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadYzappend88575169e0ec1639b6ae3851df999710.tex}}}} + +\newcommand{\sailMIPSvalappendSixFour}{\saildoclabelled{sailMIPSzappendzy64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzappend_6433ef192058d4bf5f092d6f8b6d97f4c4.tex}}}} + +\newcommand{\sailMIPSvalbitvectorAccess}{\saildoclabelled{sailMIPSzbitvectorzyaccess}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzbitvector_access8b584ca86770abb6b0da5ef059a02ed9.tex}}}} + +\newcommand{\sailMIPSvalplainVectorAccess}{\saildoclabelled{sailMIPSzplainzyvectorzyaccess}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzplain_vector_access792547dd734d4ff2e6078cbb88967469.tex}}}} + +\newcommand{\sailMIPSoverloadZvectorAccess}{\saildoclabelled{sailMIPSoverloadZzvectorzyaccess}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadZzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex}}}} + +\newcommand{\sailMIPSvalbitvectorUpdate}{\saildoclabelled{sailMIPSzbitvectorzyupdate}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzbitvector_update20826799a1ff3ff40895206db0df14bb.tex}}}} + +\newcommand{\sailMIPSvalplainVectorUpdate}{\saildoclabelled{sailMIPSzplainzyvectorzyupdate}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzplain_vector_updateb31d67bfe51b1a6f79983347dfc57da0.tex}}}} + +\newcommand{\sailMIPSoverloadAAvectorUpdate}{\saildoclabelled{sailMIPSoverloadAAzvectorzyupdate}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadAAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex}}}} + +\newcommand{\sailMIPSvaladdBits}{\saildoclabelled{sailMIPSzaddzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzadd_bits24373ffc11f289d5bb648df2f4f41b25.tex}}}} + +\newcommand{\sailMIPSvaladdBitsInt}{\saildoclabelled{sailMIPSzaddzybitszyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzadd_bits_inta5424052402522ff4653275c899f7543.tex}}}} + +\newcommand{\sailMIPSoverloadBBzEightoperatorzZerozBzNine}{\saildoclabelled{sailMIPSoverloadBBzz8operatorz0zBz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadBBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex}}}} + +\newcommand{\sailMIPSvalsubBits}{\saildoclabelled{sailMIPSzsubzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsub_bitsf0dc4fc3429d45517c523db21af72127.tex}}}} + +\newcommand{\sailMIPSvalnotVec}{\saildoclabelled{sailMIPSznotzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznot_vecfb45897f737be88160f5363827ef4a4b.tex}}}} + +\newcommand{\sailMIPSvalandVec}{\saildoclabelled{sailMIPSzandzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzand_vec99be3fe45d23194b597520c9e407ad35.tex}}}} + +\newcommand{\sailMIPSoverloadCCzEightoperatorzZerozSixzNine}{\saildoclabelled{sailMIPSoverloadCCzz8operatorz0z6z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadCCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex}}}} + +\newcommand{\sailMIPSvalorVec}{\saildoclabelled{sailMIPSzorzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzor_vec467c7a3f74be27085fe1b2aa3651ffe7.tex}}}} + +\newcommand{\sailMIPSoverloadDDzEightoperatorzZerozUzNine}{\saildoclabelled{sailMIPSoverloadDDzz8operatorz0zUz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadDDzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex}}}} + +\newcommand{\sailMIPSvalsubrangeBits}{\saildoclabelled{sailMIPSzsubrangezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsubrange_bits6c497c14df4f4754bd345a6c56ca2aad.tex}}}} + +\newcommand{\sailMIPSoverloadEEvectorSubrange}{\saildoclabelled{sailMIPSoverloadEEzvectorzysubrange}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadEEzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex}}}} + +\newcommand{\sailMIPSvalupdateSubrangeBits}{\saildoclabelled{sailMIPSzupdatezysubrangezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzupdate_subrange_bitsb5ffe862b26310b45a779cd45bbf041e.tex}}}} + +\newcommand{\sailMIPSoverloadFFvectorUpdateSubrange}{\saildoclabelled{sailMIPSoverloadFFzvectorzyupdatezysubrange}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadFFzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex}}}} + +\newcommand{\sailMIPSvalsailShiftleft}{\saildoclabelled{sailMIPSzsailzyshiftleft}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsail_shiftlefta7bc10407d10355c4e981688c9926084.tex}}}} + +\newcommand{\sailMIPSvalsailShiftright}{\saildoclabelled{sailMIPSzsailzyshiftright}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsail_shiftrighte403ac5c2740b7767c2bdfe689082562.tex}}}} + +\newcommand{\sailMIPSvalsailArithShiftright}{\saildoclabelled{sailMIPSzsailzyarithzyshiftright}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsail_arith_shiftrighta24f06e92ffcd84e26ed61085c833371.tex}}}} + +\newcommand{\sailMIPSvalsailZeros}{\saildoclabelled{sailMIPSzsailzyzzeros}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsail_zzeros174d4d4928427d9df9fa9749f1df5f96.tex}}}} + +\newcommand{\sailMIPSvalsailOnes}{\saildoclabelled{sailMIPSzsailzyones}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex}}}} + +\newcommand{\sailMIPSfnsailOnes}{\saildoclabelled{sailMIPSfnzsailzyones}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex}}}} + +\newcommand{\sailMIPSvalslice}{\saildoclabelled{sailMIPSzslice}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzslice9979e992fd48f77a2c3fef7fbcce068e.tex}}}} + +\newcommand{\sailMIPSvalreplicateBits}{\saildoclabelled{sailMIPSzreplicatezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzreplicate_bitsb29bdab6bb9437712accf2dc81ea3d3e.tex}}}} + +\newcommand{\sailMIPSvalsliceMask}{\saildoclabelled{sailMIPSzslicezymask}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex}}}} + +\newcommand{\sailMIPSfnsliceMask}{\saildoclabelled{sailMIPSfnzslicezymask}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex}}}} + +\newcommand{\sailMIPSvalgetSliceInt}{\saildoclabelled{sailMIPSzgetzyslicezyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzget_slice_int3c313e973dc436aff309f66096377164.tex}}}} + +\newcommand{\sailMIPSvalsetSliceInt}{\saildoclabelled{sailMIPSzsetzyslicezyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzset_slice_intf4b6b0ed3d8b3bb2f2e0d7a492959629.tex}}}} + +\newcommand{\sailMIPSvalsetSliceBits}{\saildoclabelled{sailMIPSzsetzyslicezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzset_slice_bits5956200094c551f35973411fcc90a521.tex}}}} + +\newcommand{\sailMIPSvalunsigned}{\saildoclabelled{sailMIPSzunsigned}{\saildocval{converts a bit vector of length $n$ to an integer in the range $0$ to $2^n - 1$. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzunsigned1010eda2cdd2666cd8fd0ddf82ac526f.tex}}}} + +\newcommand{\sailMIPSvalsigned}{\saildoclabelled{sailMIPSzsigned}{\saildocval{converts a bit vector of length $n$ to an integer in the range $-2^{n-1}$ to $2^{n-1} - 1$ using twos-complement. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzsigned36d2317f34f1dacb4e465e6e56b185e6.tex}}}} + +\newcommand{\sailMIPSoverloadGGSizze}{\saildoclabelled{sailMIPSoverloadGGzzyzysizze}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadGGz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex}}}} + +\newcommand{\sailMIPSvaleqString}{\saildoclabelled{sailMIPSzeqzystring}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzeq_string75dfa57c0476ae3f43f8e55ffe51a116.tex}}}} + +\newcommand{\sailMIPSoverloadHHzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailMIPSoverloadHHzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadHHzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} + +\newcommand{\sailMIPSvalconcatStr}{\saildoclabelled{sailMIPSzconcatzystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzconcat_str366019c233188ef65ab3d1f977f04112.tex}}}} + +\newcommand{\sailMIPSvaldecStr}{\saildoclabelled{sailMIPSzdeczystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzdec_str7582ccea1482759c248b1f1ac9f6ae63.tex}}}} + +\newcommand{\sailMIPSvalhexStr}{\saildoclabelled{sailMIPSzhexzystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzhex_str47c735e2941ef5c87d4f7502a5e92a2a.tex}}}} + +\newcommand{\sailMIPSvalbitsStr}{\saildoclabelled{sailMIPSzbitszystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzbits_strae053d842c21f0867dea1e830d1773cc.tex}}}} + +\newcommand{\sailMIPSvalconcatStrBits}{\saildoclabelled{sailMIPSzconcatzystrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex}}}} + +\newcommand{\sailMIPSfnconcatStrBits}{\saildoclabelled{sailMIPSfnzconcatzystrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex}}}} + +\newcommand{\sailMIPSvalconcatStrDec}{\saildoclabelled{sailMIPSzconcatzystrzydec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex}}}} + +\newcommand{\sailMIPSfnconcatStrDec}{\saildoclabelled{sailMIPSfnzconcatzystrzydec}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex}}}} + +\newcommand{\sailMIPSvalprintEndline}{\saildoclabelled{sailMIPSzprintzyendline}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzprint_endline03a43e2779561cb054d0761733c27e9b.tex}}}} + +\newcommand{\sailMIPSvalprerrEndline}{\saildoclabelled{sailMIPSzprerrzyendline}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzprerr_endline73ce57fcf6e847727670556577cb2de0.tex}}}} + +\newcommand{\sailMIPSvaleqAnything}{\saildoclabelled{sailMIPSzeqzyanything}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzeq_anything99dff1d931070d33dac5c755eae24439.tex}}}} + +\newcommand{\sailMIPSoverloadIIzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailMIPSoverloadIIzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadIIzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} + +\newcommand{\sailMIPSoverloadJJzW}{\saildoclabelled{sailMIPSoverloadJJzzW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadJJzzw805a9067649c7cfeedcb41b57a7e2c86.tex}}}} + +\newcommand{\sailMIPSoverloadKKnot}{\saildoclabelled{sailMIPSoverloadKKznot}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadKKznotcbe861867f25b28c34f5ae99957794ed.tex}}}} + +\newcommand{\sailMIPSvalneqAnything}{\saildoclabelled{sailMIPSzneqzyanything}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzneq_anythingf220233154ca93d75c0323f604bb8d16.tex}}}} + +\newcommand{\sailMIPSfnneqAnything}{\saildoclabelled{sailMIPSfnzneqzyanything}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzneq_anythingf220233154ca93d75c0323f604bb8d16.tex}}}} + +\newcommand{\sailMIPSoverloadLLzEightoperatorzZerozOnezJzNine}{\saildoclabelled{sailMIPSoverloadLLzz8operatorz0z1zJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadLLzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex}}}} + +\newcommand{\sailMIPSvalcastUnitVec}{\saildoclabelled{sailMIPSzcastzyunitzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcast_unit_vec98272b7fb05a703213e98272ec5486c8.tex}}}} + +\newcommand{\sailMIPSfncastUnitVec}{\saildoclabelled{sailMIPSfnzcastzyunitzyvec}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcast_unit_vec98272b7fb05a703213e98272ec5486c8.tex}}}} + +\newcommand{\sailMIPSoverloadMMprint}{\saildoclabelled{sailMIPSoverloadMMzprint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadMMzprintc9b8c9c569def1934362480628956c85.tex}}}} + +\newcommand{\sailMIPSvalprerr}{\saildoclabelled{sailMIPSzprerr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzprerre641bc17ebf3c7131851f8df33a62260.tex}}}} + +\newcommand{\sailMIPSvalputchar}{\saildoclabelled{sailMIPSzputchar}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzputchare63a26733a4ffbee3ab40a4ee6cd644b.tex}}}} + +\newcommand{\sailMIPSvalstringOfInt}{\saildoclabelled{sailMIPSzstringzyofzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstring_of_int03988e4e2d2976513793427ac823afbe.tex}}}} + +\newcommand{\sailMIPSvalBitStr}{\saildoclabelled{sailMIPSzBitStr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzbitstr0d04da018975c4776e05a9c59c2e380e.tex}}}} + +\newcommand{\sailMIPSvalxorVec}{\saildoclabelled{sailMIPSzxorzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzxor_vecdacd54acc32f073fb01d1c188177bc8c.tex}}}} + +\newcommand{\sailMIPSvalintPower}{\saildoclabelled{sailMIPSzintzypower}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzint_powerb0c5fc1a9fb0852260414607a93aeae6.tex}}}} + +\newcommand{\sailMIPSoverloadNNzEightoperatorzZerozQzNine}{\saildoclabelled{sailMIPSoverloadNNzz8operatorz0zQz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadNNzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex}}}} + +\newcommand{\sailMIPSvaladdRange}{\saildoclabelled{sailMIPSzaddzyrange}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzadd_range42e075ccf1451df2036e21ab04adc98a.tex}}}} + +\newcommand{\sailMIPSvaladdVec}{\saildoclabelled{sailMIPSzaddzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzadd_vecaede33d991aa6e29010fb4562c8ae5de.tex}}}} + +\newcommand{\sailMIPSvaladdVecInt}{\saildoclabelled{sailMIPSzaddzyveczyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzadd_vec_intba4788367d6a85d666f0c19861d4bd77.tex}}}} + +\newcommand{\sailMIPSoverloadOOzEightoperatorzZerozBzNine}{\saildoclabelled{sailMIPSoverloadOOzz8operatorz0zBz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadOOzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex}}}} + +\newcommand{\sailMIPSvalsubRange}{\saildoclabelled{sailMIPSzsubzyrange}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsub_range14f5685922761f99e3753835c40db01f.tex}}}} + +\newcommand{\sailMIPSvalsubVec}{\saildoclabelled{sailMIPSzsubzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsub_vec326e0ba0bb00229be26645e2d44dbd83.tex}}}} + +\newcommand{\sailMIPSvalsubVecInt}{\saildoclabelled{sailMIPSzsubzyveczyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsub_vec_int5e6c04459782b1b8cc706ba2e4c8a435.tex}}}} + +\newcommand{\sailMIPSvalnegateRange}{\saildoclabelled{sailMIPSznegatezyrange}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznegate_range78b007ae673ca039d425d3facc380863.tex}}}} + +\newcommand{\sailMIPSoverloadPPzEightoperatorzZerozDzNine}{\saildoclabelled{sailMIPSoverloadPPzz8operatorz0zDz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadPPzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex}}}} + +\newcommand{\sailMIPSoverloadQQnegate}{\saildoclabelled{sailMIPSoverloadQQznegate}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadQQznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex}}}} + +\newcommand{\sailMIPSoverloadRRzEightoperatorzZerozAzNine}{\saildoclabelled{sailMIPSoverloadRRzz8operatorz0zAz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadRRzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex}}}} + +\newcommand{\sailMIPSoverloadSSzEightoperatorzZerozFzNine}{\saildoclabelled{sailMIPSoverloadSSzz8operatorz0zFz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadSSzz8operatorz0zfz9413c2bc7cb07ce1db42a50ad1459c051.tex}}}} + +\newcommand{\sailMIPSoverloadTTzEightoperatorzZerozFivezNine}{\saildoclabelled{sailMIPSoverloadTTzz8operatorz0z5z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadTTzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex}}}} + +\newcommand{\sailMIPSvalquotRoundZero}{\saildoclabelled{sailMIPSzquotzyroundzyzzero}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzquot_round_zzeroa8d9d278dc91a14956dfe19d01766403.tex}}}} + +\newcommand{\sailMIPSvalremRoundZero}{\saildoclabelled{sailMIPSzremzyroundzyzzero}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzrem_round_zzero90d115d6c3e756b94f7766d1b76fbb83.tex}}}} + +\newcommand{\sailMIPSvalminNat}{\saildoclabelled{sailMIPSzminzynat}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmin_nat7dddd2b4f1427434a323cd17c0426f93.tex}}}} + +\newcommand{\sailMIPSvalminInt}{\saildoclabelled{sailMIPSzminzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmin_intaf4626ab3b9c2d0b9494d7e8d265dd26.tex}}}} + +\newcommand{\sailMIPSvalmaxNat}{\saildoclabelled{sailMIPSzmaxzynat}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmax_nat266559c9edd4c969dc9a8a0472e3379e.tex}}}} + +\newcommand{\sailMIPSvalmaxInt}{\saildoclabelled{sailMIPSzmaxzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmax_inta8f95a0baf723be8373221a893afa8f3.tex}}}} + +\newcommand{\sailMIPSvalminAtom}{\saildoclabelled{sailMIPSzminzyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmin_atombf865ffed8d1a7f4606db9d6d968a016.tex}}}} + +\newcommand{\sailMIPSvalmaxAtom}{\saildoclabelled{sailMIPSzmaxzyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmax_atom2691d513aec6d2154c7685b5a93fac12.tex}}}} + +\newcommand{\sailMIPSoverloadUUmin}{\saildoclabelled{sailMIPSoverloadUUzmin}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadUUzmin95ae3c0ebde1421750e6db87bdf74801.tex}}}} + +\newcommand{\sailMIPSoverloadVVmax}{\saildoclabelled{sailMIPSoverloadVVzmax}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadVVzmax91b641c464c0dc87660499321a356d93.tex}}}} + +\newcommand{\sailMIPSvalWriteRAM}{\saildoclabelled{sailMIPSzzyzyWriteRAM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz__writeram67df92b8173868b4341c66bb37bdc8da.tex}}}} + +\newcommand{\sailMIPSvalMIPSWrite}{\saildoclabelled{sailMIPSzzyzyMIPSzywrite}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz__mips_writed13fe4a15e9bfd2a9e702a585b5a7e1c.tex}}}} + +\newcommand{\sailMIPSfnMIPSWrite}{\saildoclabelled{sailMIPSfnzzyzyMIPSzywrite}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz__mips_writed13fe4a15e9bfd2a9e702a585b5a7e1c.tex}}}} + +\newcommand{\sailMIPSvalReadRAM}{\saildoclabelled{sailMIPSzzyzyReadRAM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz__readram468758162486e62876c2678a7e769399.tex}}}} + +\newcommand{\sailMIPSvalMIPSRead}{\saildoclabelled{sailMIPSzzyzyMIPSzyread}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz__mips_read6caa8fcafb5a40e544d3165028b605fb.tex}}}} + +\newcommand{\sailMIPSfnMIPSRead}{\saildoclabelled{sailMIPSfnzzyzyMIPSzyread}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz__mips_read6caa8fcafb5a40e544d3165028b605fb.tex}}}} + +\newcommand{\sailMIPSvalzEightoperatorzZerozQzQzNine}{\saildoclabelled{sailMIPSzz8operatorz0zQzQz9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzz8operatorz0zqzqz93d1b5248b83463c11188367c0486a3fd.tex}}}} + +\newcommand{\sailMIPSfnzEightoperatorzZerozQzQzNine}{\saildoclabelled{sailMIPSfnzz8operatorz0zQzQz9}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzz8operatorz0zqzqz93d1b5248b83463c11188367c0486a3fd.tex}}}} + +\newcommand{\sailMIPSvalpowTwo}{\saildoclabelled{sailMIPSzpow2}{\saildocval{\lstinline{pow2}(n) returns 2 raised to the power \emph{n}. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzpow2e971ce2f9ebb899590551317286dfd1b.tex}}}} + +\newcommand{\sailMIPStypeexception}{\saildoclabelled{sailMIPStypezexception}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezexceptionfaa4db8fab65c538edad4222e766a71a.tex}}}} + +\newcommand{\sailMIPSvalmipsSignExtend}{\saildoclabelled{sailMIPSzmipszysignzyextend}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmips_sign_extenddff82d4ceaaa72d7146e15c8674216ac.tex}}}} + +\newcommand{\sailMIPSvalmipsZeroExtend}{\saildoclabelled{sailMIPSzmipszyzzerozyextend}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmips_zzero_extend6340d2cbae7a2266a4e1077b06a57276.tex}}}} + +\newcommand{\sailMIPSfnmipsSignExtend}{\saildoclabelled{sailMIPSfnzmipszysignzyextend}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmips_sign_extenddff82d4ceaaa72d7146e15c8674216ac.tex}}}} + +\newcommand{\sailMIPSfnmipsZeroExtend}{\saildoclabelled{sailMIPSfnzmipszyzzerozyextend}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmips_zzero_extend6340d2cbae7a2266a4e1077b06a57276.tex}}}} + +\newcommand{\sailMIPSoverloadWWsignExtend}{\saildoclabelled{sailMIPSoverloadWWzsignzyextend}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadWWzsign_extendd299e34344c466213b3253f0d877453d.tex}}}} + +\newcommand{\sailMIPSoverloadXXzzeroExtend}{\saildoclabelled{sailMIPSoverloadXXzzzerozyextend}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadXXzzzero_extendd7d8b08ed1667724fd3dfa843cf0ae78.tex}}}} + +\newcommand{\sailMIPSvalzzerosImplicit}{\saildoclabelled{sailMIPSzzzeroszyimplicit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex}}}} + +\newcommand{\sailMIPSfnzzerosImplicit}{\saildoclabelled{sailMIPSfnzzzeroszyimplicit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex}}}} + +\newcommand{\sailMIPSoverloadYYzzeros}{\saildoclabelled{sailMIPSoverloadYYzzzeros}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadYYzzzerosc530711942e216cef3921733c1c5d101.tex}}}} + +\newcommand{\sailMIPSvalonesImplicit}{\saildoclabelled{sailMIPSzoneszyimplicit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzones_implicitd278a7fa4099e3986b30108716d3adc5.tex}}}} + +\newcommand{\sailMIPSfnonesImplicit}{\saildoclabelled{sailMIPSfnzoneszyimplicit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzones_implicitd278a7fa4099e3986b30108716d3adc5.tex}}}} + +\newcommand{\sailMIPSoverloadZZones}{\saildoclabelled{sailMIPSoverloadZZzones}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadZZzones26f94136f5db8afd4e9df1e512f7fdc5.tex}}}} + +\newcommand{\sailMIPSvalzEightoperatorzZerozISzNine}{\saildoclabelled{sailMIPSzz8operatorz0zIzysz9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex}}}} + +\newcommand{\sailMIPSvalzEightoperatorzZerozKzJSzNine}{\saildoclabelled{sailMIPSzz8operatorz0zKzJzysz9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex}}}} + +\newcommand{\sailMIPSvalzEightoperatorzZerozIUzNine}{\saildoclabelled{sailMIPSzz8operatorz0zIzyuz9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex}}}} + +\newcommand{\sailMIPSvalzEightoperatorzZerozKzJUzNine}{\saildoclabelled{sailMIPSzz8operatorz0zKzJzyuz9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex}}}} + +\newcommand{\sailMIPSfnzEightoperatorzZerozISzNine}{\saildoclabelled{sailMIPSfnzz8operatorz0zIzysz9}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex}}}} + +\newcommand{\sailMIPSfnzEightoperatorzZerozKzJSzNine}{\saildoclabelled{sailMIPSfnzz8operatorz0zKzJzysz9}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex}}}} + +\newcommand{\sailMIPSfnzEightoperatorzZerozIUzNine}{\saildoclabelled{sailMIPSfnzz8operatorz0zIzyuz9}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex}}}} + +\newcommand{\sailMIPSfnzEightoperatorzZerozKzJUzNine}{\saildoclabelled{sailMIPSfnzz8operatorz0zKzJzyuz9}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex}}}} + +\newcommand{\sailMIPSvalboolToBits}{\saildoclabelled{sailMIPSzboolzytozybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex}}}} + +\newcommand{\sailMIPSfnboolToBits}{\saildoclabelled{sailMIPSfnzboolzytozybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex}}}} + +\newcommand{\sailMIPSvalboolToBit}{\saildoclabelled{sailMIPSzboolzytozybit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex}}}} + +\newcommand{\sailMIPSfnboolToBit}{\saildoclabelled{sailMIPSfnzboolzytozybit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex}}}} + +\newcommand{\sailMIPSvalbitToBool}{\saildoclabelled{sailMIPSzbitzytozybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex}}}} + +\newcommand{\sailMIPSfnbitToBool}{\saildoclabelled{sailMIPSfnzbitzytozybool}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex}}}} + +\newcommand{\sailMIPSvalbitsToBool}{\saildoclabelled{sailMIPSzbitszytozybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzbits_to_bool40d71a119a1093f6caa36e2aa93bd193.tex}}}} + +\newcommand{\sailMIPSfnbitsToBool}{\saildoclabelled{sailMIPSfnzbitszytozybool}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzbits_to_bool40d71a119a1093f6caa36e2aa93bd193.tex}}}} + +\newcommand{\sailMIPSvalshiftBitsRight}{\saildoclabelled{sailMIPSzshiftzybitszyright}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzshift_bits_right281f5e6a28fe3c92d35fe5c78a0deb41.tex}}}} + +\newcommand{\sailMIPSvalshiftBitsLeft}{\saildoclabelled{sailMIPSzshiftzybitszyleft}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzshift_bits_left0754e8b870e2a3ba46646c35dac7af10.tex}}}} + +\newcommand{\sailMIPSvalshiftl}{\saildoclabelled{sailMIPSzshiftl}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzshiftl7827d0dcac29bd8258f158e7c1e77658.tex}}}} + +\newcommand{\sailMIPSvalshiftr}{\saildoclabelled{sailMIPSzshiftr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzshiftr173b7dba7206ed1b61a12344bdf9182a.tex}}}} + +\newcommand{\sailMIPSoverloadAAAzEightoperatorzZerozKzKzNine}{\saildoclabelled{sailMIPSoverloadAAAzz8operatorz0zKzKz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadAAAzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex}}}} + +\newcommand{\sailMIPSoverloadBBBzEightoperatorzZerozIzIzNine}{\saildoclabelled{sailMIPSoverloadBBBzz8operatorz0zIzIz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadBBBzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex}}}} + +\newcommand{\sailMIPSvalzEightoperatorzZerozKzKSzNine}{\saildoclabelled{sailMIPSzz8operatorz0zKzKzysz9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex}}}} + +\newcommand{\sailMIPSvalzEightoperatorzZerozASzNine}{\saildoclabelled{sailMIPSzz8operatorz0zAzysz9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzz8operatorz0za_sz9e046109c9d98ebd1683e514a3e2f3f5d.tex}}}} + +\newcommand{\sailMIPSvalzEightoperatorzZerozAUzNine}{\saildoclabelled{sailMIPSzz8operatorz0zAzyuz9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzz8operatorz0za_uz98194b6fb241100892f8fe90018275deb.tex}}}} + +\newcommand{\sailMIPSvaltoBits}{\saildoclabelled{sailMIPSztozybits}{\saildocval{\lstinline{to_bits}\lstinline`(l, v)` converts an integer, \lstinline`v`, to a bit vector of length \lstinline`l`. If \lstinline`v` is negative a twos-complement representation is used. If \lstinline`v` is too large (or too negative) to fit in the requested length then it is truncated to the least significant bits. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex}}}} + +\newcommand{\sailMIPSfntoBits}{\saildoclabelled{sailMIPSfnztozybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex}}}} + +\newcommand{\sailMIPSvalmask}{\saildoclabelled{sailMIPSzmask}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmask357329ae84e03dd27d4454a1873fc3dd.tex}}}} + +\newcommand{\sailMIPSfnmask}{\saildoclabelled{sailMIPSfnzmask}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmask357329ae84e03dd27d4454a1873fc3dd.tex}}}} + +\newcommand{\sailMIPSvalgetTimeNs}{\saildoclabelled{sailMIPSzgetzytimezyns}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzget_time_ns76b2aba2c98dedb9e71b52add49642c4.tex}}}} + +\newcommand{\sailMIPStypeCauseReg}{\saildoclabelled{sailMIPStypezCauseReg}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezcauseregda69bedc009933948dd9b8b2c8a67377.tex}}}} + +\newcommand{\sailMIPSvalMkCauseReg}{\saildoclabelled{sailMIPSzMkzyCauseReg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmk_causereg8c2dd932a95a40841ae776546777d7fb.tex}}}} + +\newcommand{\sailMIPSfnMkCauseReg}{\saildoclabelled{sailMIPSfnzMkzyCauseReg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmk_causereg8c2dd932a95a40841ae776546777d7fb.tex}}}} + +\newcommand{\sailMIPSvalGetCauseRegBits}{\saildoclabelled{sailMIPSzzygetzyCauseRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_causereg_bits8438dd7e3e82e5a62db2fbe5d4c93611.tex}}}} + +\newcommand{\sailMIPSfnGetCauseRegBits}{\saildoclabelled{sailMIPSfnzzygetzyCauseRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_causereg_bits8438dd7e3e82e5a62db2fbe5d4c93611.tex}}}} + +\newcommand{\sailMIPSvalSetCauseRegBits}{\saildoclabelled{sailMIPSzzysetzyCauseRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_causereg_bits73c1fb63898bc74942a3c60d0ceacd0a.tex}}}} + +\newcommand{\sailMIPSfnSetCauseRegBits}{\saildoclabelled{sailMIPSfnzzysetzyCauseRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_causereg_bits73c1fb63898bc74942a3c60d0ceacd0a.tex}}}} + +\newcommand{\sailMIPSvalUpdateCauseRegBits}{\saildoclabelled{sailMIPSzzyupdatezyCauseRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_causereg_bitsb063e035edb33b2c5f07e3df533bf948.tex}}}} + +\newcommand{\sailMIPSfnUpdateCauseRegBits}{\saildoclabelled{sailMIPSfnzzyupdatezyCauseRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_causereg_bitsb063e035edb33b2c5f07e3df533bf948.tex}}}} + +\newcommand{\sailMIPSoverloadCCCupdateBits}{\saildoclabelled{sailMIPSoverloadCCCzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadCCCzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailMIPSoverloadDDDModBits}{\saildoclabelled{sailMIPSoverloadDDDzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadDDDz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailMIPSvalGetCauseRegBD}{\saildoclabelled{sailMIPSzzygetzyCauseRegzyBD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_causereg_bd96afa963ea8fd0967157eb8bd72a1b1b.tex}}}} + +\newcommand{\sailMIPSfnGetCauseRegBD}{\saildoclabelled{sailMIPSfnzzygetzyCauseRegzyBD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_causereg_bd96afa963ea8fd0967157eb8bd72a1b1b.tex}}}} + +\newcommand{\sailMIPSvalSetCauseRegBD}{\saildoclabelled{sailMIPSzzysetzyCauseRegzyBD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_causereg_bdb5f488f812625b8e1f8d3846c87da635.tex}}}} + +\newcommand{\sailMIPSfnSetCauseRegBD}{\saildoclabelled{sailMIPSfnzzysetzyCauseRegzyBD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_causereg_bdb5f488f812625b8e1f8d3846c87da635.tex}}}} + +\newcommand{\sailMIPSvalUpdateCauseRegBD}{\saildoclabelled{sailMIPSzzyupdatezyCauseRegzyBD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_causereg_bd1341a4dd118508995044054898160c72.tex}}}} + +\newcommand{\sailMIPSfnUpdateCauseRegBD}{\saildoclabelled{sailMIPSfnzzyupdatezyCauseRegzyBD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_causereg_bd1341a4dd118508995044054898160c72.tex}}}} + +\newcommand{\sailMIPSoverloadEEEupdateBD}{\saildoclabelled{sailMIPSoverloadEEEzupdatezyBD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadEEEzupdate_bd472c903f3ae609529b16dd7fa25cbef2.tex}}}} + +\newcommand{\sailMIPSoverloadFFFModBD}{\saildoclabelled{sailMIPSoverloadFFFzzymodzyBD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadFFFz_mod_bdd84f0971ca04f14c3accaf99182a8375.tex}}}} + +\newcommand{\sailMIPSvalGetCauseRegCE}{\saildoclabelled{sailMIPSzzygetzyCauseRegzyCE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_causereg_cec50f9f4ac0a1b657a7733fa87526be2d.tex}}}} + +\newcommand{\sailMIPSfnGetCauseRegCE}{\saildoclabelled{sailMIPSfnzzygetzyCauseRegzyCE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_causereg_cec50f9f4ac0a1b657a7733fa87526be2d.tex}}}} + +\newcommand{\sailMIPSvalSetCauseRegCE}{\saildoclabelled{sailMIPSzzysetzyCauseRegzyCE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_causereg_ce01fc3f03d0d74f4e0d5a0942681ed38a.tex}}}} + +\newcommand{\sailMIPSfnSetCauseRegCE}{\saildoclabelled{sailMIPSfnzzysetzyCauseRegzyCE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_causereg_ce01fc3f03d0d74f4e0d5a0942681ed38a.tex}}}} + +\newcommand{\sailMIPSvalUpdateCauseRegCE}{\saildoclabelled{sailMIPSzzyupdatezyCauseRegzyCE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_causereg_ce99326d83612c25800d2accb6a9f4508b.tex}}}} + +\newcommand{\sailMIPSfnUpdateCauseRegCE}{\saildoclabelled{sailMIPSfnzzyupdatezyCauseRegzyCE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_causereg_ce99326d83612c25800d2accb6a9f4508b.tex}}}} + +\newcommand{\sailMIPSoverloadGGGupdateCE}{\saildoclabelled{sailMIPSoverloadGGGzupdatezyCE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadGGGzupdate_ce14dd97255abc19f0f457743517c0d047.tex}}}} + +\newcommand{\sailMIPSoverloadHHHModCE}{\saildoclabelled{sailMIPSoverloadHHHzzymodzyCE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadHHHz_mod_ceea2953e9544c0c54dc69ff3e4ffbe7f8.tex}}}} + +\newcommand{\sailMIPSvalGetCauseRegIV}{\saildoclabelled{sailMIPSzzygetzyCauseRegzyIV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_causereg_iv8d01550ba34aa421cfc2ce657745d131.tex}}}} + +\newcommand{\sailMIPSfnGetCauseRegIV}{\saildoclabelled{sailMIPSfnzzygetzyCauseRegzyIV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_causereg_iv8d01550ba34aa421cfc2ce657745d131.tex}}}} + +\newcommand{\sailMIPSvalSetCauseRegIV}{\saildoclabelled{sailMIPSzzysetzyCauseRegzyIV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_causereg_iv526ac3c679cca6391db51d524d6d72ad.tex}}}} + +\newcommand{\sailMIPSfnSetCauseRegIV}{\saildoclabelled{sailMIPSfnzzysetzyCauseRegzyIV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_causereg_iv526ac3c679cca6391db51d524d6d72ad.tex}}}} + +\newcommand{\sailMIPSvalUpdateCauseRegIV}{\saildoclabelled{sailMIPSzzyupdatezyCauseRegzyIV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_causereg_iv2946c68395a7cdb8aa45a8668627e8d5.tex}}}} + +\newcommand{\sailMIPSfnUpdateCauseRegIV}{\saildoclabelled{sailMIPSfnzzyupdatezyCauseRegzyIV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_causereg_iv2946c68395a7cdb8aa45a8668627e8d5.tex}}}} + +\newcommand{\sailMIPSoverloadIIIupdateIV}{\saildoclabelled{sailMIPSoverloadIIIzupdatezyIV}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadIIIzupdate_iv53a8e0f57ddb36f890734859eaba53ae.tex}}}} + +\newcommand{\sailMIPSoverloadJJJModIV}{\saildoclabelled{sailMIPSoverloadJJJzzymodzyIV}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadJJJz_mod_ivb088aebc9bfea2ab389f62ea44fbb3a9.tex}}}} + +\newcommand{\sailMIPSvalGetCauseRegWP}{\saildoclabelled{sailMIPSzzygetzyCauseRegzyWP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_causereg_wpcbfccc2e0292d6f04b091ed268698e68.tex}}}} + +\newcommand{\sailMIPSfnGetCauseRegWP}{\saildoclabelled{sailMIPSfnzzygetzyCauseRegzyWP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_causereg_wpcbfccc2e0292d6f04b091ed268698e68.tex}}}} + +\newcommand{\sailMIPSvalSetCauseRegWP}{\saildoclabelled{sailMIPSzzysetzyCauseRegzyWP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_causereg_wpff070e6ed3da50f2ad0a0d32ca5c1969.tex}}}} + +\newcommand{\sailMIPSfnSetCauseRegWP}{\saildoclabelled{sailMIPSfnzzysetzyCauseRegzyWP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_causereg_wpff070e6ed3da50f2ad0a0d32ca5c1969.tex}}}} + +\newcommand{\sailMIPSvalUpdateCauseRegWP}{\saildoclabelled{sailMIPSzzyupdatezyCauseRegzyWP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_causereg_wpd6c4c462af40f65a59a3ad83cf90ff81.tex}}}} + +\newcommand{\sailMIPSfnUpdateCauseRegWP}{\saildoclabelled{sailMIPSfnzzyupdatezyCauseRegzyWP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_causereg_wpd6c4c462af40f65a59a3ad83cf90ff81.tex}}}} + +\newcommand{\sailMIPSoverloadKKKupdateWP}{\saildoclabelled{sailMIPSoverloadKKKzupdatezyWP}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadKKKzupdate_wpb2578310c293c0bfbbb1919aa78e107e.tex}}}} + +\newcommand{\sailMIPSoverloadLLLModWP}{\saildoclabelled{sailMIPSoverloadLLLzzymodzyWP}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadLLLz_mod_wp16ea1a9b8f1e9595a992f51656917f4c.tex}}}} + +\newcommand{\sailMIPSvalGetCauseRegIP}{\saildoclabelled{sailMIPSzzygetzyCauseRegzyIP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_causereg_ip959fa0662dd3554fca2b54c9afdd9ed2.tex}}}} + +\newcommand{\sailMIPSfnGetCauseRegIP}{\saildoclabelled{sailMIPSfnzzygetzyCauseRegzyIP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_causereg_ip959fa0662dd3554fca2b54c9afdd9ed2.tex}}}} + +\newcommand{\sailMIPSvalSetCauseRegIP}{\saildoclabelled{sailMIPSzzysetzyCauseRegzyIP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_causereg_ip2026aa5013ac14eda0adff00c82c7a29.tex}}}} + +\newcommand{\sailMIPSfnSetCauseRegIP}{\saildoclabelled{sailMIPSfnzzysetzyCauseRegzyIP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_causereg_ip2026aa5013ac14eda0adff00c82c7a29.tex}}}} + +\newcommand{\sailMIPSvalUpdateCauseRegIP}{\saildoclabelled{sailMIPSzzyupdatezyCauseRegzyIP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_causereg_ipa7f214043fd244817e8d07b9783a4f4a.tex}}}} + +\newcommand{\sailMIPSfnUpdateCauseRegIP}{\saildoclabelled{sailMIPSfnzzyupdatezyCauseRegzyIP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_causereg_ipa7f214043fd244817e8d07b9783a4f4a.tex}}}} + +\newcommand{\sailMIPSoverloadMMMupdateIP}{\saildoclabelled{sailMIPSoverloadMMMzupdatezyIP}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadMMMzupdate_ip04d62e571c5f0df4e13fef5ee848bfb6.tex}}}} + +\newcommand{\sailMIPSoverloadNNNModIP}{\saildoclabelled{sailMIPSoverloadNNNzzymodzyIP}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadNNNz_mod_ipe8feebf60b7d37429ca83cdc1369f3b4.tex}}}} + +\newcommand{\sailMIPSvalGetCauseRegExcCode}{\saildoclabelled{sailMIPSzzygetzyCauseRegzyExcCode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_causereg_exccode8a67289fbe422c3b2420033795ebefa2.tex}}}} + +\newcommand{\sailMIPSfnGetCauseRegExcCode}{\saildoclabelled{sailMIPSfnzzygetzyCauseRegzyExcCode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_causereg_exccode8a67289fbe422c3b2420033795ebefa2.tex}}}} + +\newcommand{\sailMIPSvalSetCauseRegExcCode}{\saildoclabelled{sailMIPSzzysetzyCauseRegzyExcCode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_causereg_exccode9170f535490a825d67ffd95250c51021.tex}}}} + +\newcommand{\sailMIPSfnSetCauseRegExcCode}{\saildoclabelled{sailMIPSfnzzysetzyCauseRegzyExcCode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_causereg_exccode9170f535490a825d67ffd95250c51021.tex}}}} + +\newcommand{\sailMIPSvalUpdateCauseRegExcCode}{\saildoclabelled{sailMIPSzzyupdatezyCauseRegzyExcCode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_causereg_exccodeead7d2a9d8ec53cba96f7218e48b092f.tex}}}} + +\newcommand{\sailMIPSfnUpdateCauseRegExcCode}{\saildoclabelled{sailMIPSfnzzyupdatezyCauseRegzyExcCode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_causereg_exccodeead7d2a9d8ec53cba96f7218e48b092f.tex}}}} + +\newcommand{\sailMIPSoverloadOOOupdateExcCode}{\saildoclabelled{sailMIPSoverloadOOOzupdatezyExcCode}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadOOOzupdate_exccode286b5e0163b588d6fbc04a06efd36aa1.tex}}}} + +\newcommand{\sailMIPSoverloadPPPModExcCode}{\saildoclabelled{sailMIPSoverloadPPPzzymodzyExcCode}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadPPPz_mod_exccode24886ea7a19912378ba2030097458ff1.tex}}}} + +\newcommand{\sailMIPStypeTLBEntryLoReg}{\saildoclabelled{sailMIPStypezTLBEntryLoReg}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typeztlbentryloregdfc9845e9d6ede4af1453459f39832af.tex}}}} + +\newcommand{\sailMIPSvalMkTLBEntryLoReg}{\saildoclabelled{sailMIPSzMkzyTLBEntryLoReg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmk_tlbentryloreg686ea4d498fae1c365c28583f86fcdf2.tex}}}} + +\newcommand{\sailMIPSfnMkTLBEntryLoReg}{\saildoclabelled{sailMIPSfnzMkzyTLBEntryLoReg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmk_tlbentryloreg686ea4d498fae1c365c28583f86fcdf2.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryLoRegBits}{\saildoclabelled{sailMIPSzzygetzyTLBEntryLoRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryloreg_bitsb5a9322379b7dc75d999a3feb221ea39.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryLoRegBits}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryLoRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryloreg_bitsb5a9322379b7dc75d999a3feb221ea39.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryLoRegBits}{\saildoclabelled{sailMIPSzzysetzyTLBEntryLoRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryloreg_bits87cab4acff2760983bfddd23367d445c.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryLoRegBits}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryLoRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryloreg_bits87cab4acff2760983bfddd23367d445c.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryLoRegBits}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryLoRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryloreg_bits6c2ff3e7af20e35dd45bf50ea68f8ec8.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryLoRegBits}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryLoRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryloreg_bits6c2ff3e7af20e35dd45bf50ea68f8ec8.tex}}}} + +\newcommand{\sailMIPSoverloadQQQupdateBits}{\saildoclabelled{sailMIPSoverloadQQQzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadQQQzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailMIPSoverloadRRRModBits}{\saildoclabelled{sailMIPSoverloadRRRzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadRRRz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryLoRegCapS}{\saildoclabelled{sailMIPSzzygetzyTLBEntryLoRegzyCapS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryloreg_capsde4f5c8e764147c851f8e5e575b0078e.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryLoRegCapS}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryLoRegzyCapS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryloreg_capsde4f5c8e764147c851f8e5e575b0078e.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryLoRegCapS}{\saildoclabelled{sailMIPSzzysetzyTLBEntryLoRegzyCapS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryloreg_caps9a042f9111a8f78fcfe31c8c94e92925.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryLoRegCapS}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryLoRegzyCapS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryloreg_caps9a042f9111a8f78fcfe31c8c94e92925.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryLoRegCapS}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryLoRegzyCapS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryloreg_caps3f8fe0c48d5361758dc7ef0fa4a84990.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryLoRegCapS}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryLoRegzyCapS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryloreg_caps3f8fe0c48d5361758dc7ef0fa4a84990.tex}}}} + +\newcommand{\sailMIPSoverloadSSSupdateCapS}{\saildoclabelled{sailMIPSoverloadSSSzupdatezyCapS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadSSSzupdate_caps182d8368466ed813c4844f76ddfa2941.tex}}}} + +\newcommand{\sailMIPSoverloadTTTModCapS}{\saildoclabelled{sailMIPSoverloadTTTzzymodzyCapS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadTTTz_mod_capsa1d49b1f09b7425502aaa6953965c67a.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryLoRegCapL}{\saildoclabelled{sailMIPSzzygetzyTLBEntryLoRegzyCapL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryloreg_capl1cbdda840b22f0691c3ea7fd12bfa8a7.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryLoRegCapL}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryLoRegzyCapL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryloreg_capl1cbdda840b22f0691c3ea7fd12bfa8a7.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryLoRegCapL}{\saildoclabelled{sailMIPSzzysetzyTLBEntryLoRegzyCapL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryloreg_capl4afafd253b55dd9505958742ee8cb6f7.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryLoRegCapL}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryLoRegzyCapL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryloreg_capl4afafd253b55dd9505958742ee8cb6f7.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryLoRegCapL}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryLoRegzyCapL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryloreg_caplaaf9a58642f1ed8b0226e13fd635715e.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryLoRegCapL}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryLoRegzyCapL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryloreg_caplaaf9a58642f1ed8b0226e13fd635715e.tex}}}} + +\newcommand{\sailMIPSoverloadUUUupdateCapL}{\saildoclabelled{sailMIPSoverloadUUUzupdatezyCapL}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadUUUzupdate_capl39cb169bd618aef99d542cc3963c1b03.tex}}}} + +\newcommand{\sailMIPSoverloadVVVModCapL}{\saildoclabelled{sailMIPSoverloadVVVzzymodzyCapL}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadVVVz_mod_capl59410c98d5bb0afa60ac05ecd01d9fdd.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryLoRegCapLG}{\saildoclabelled{sailMIPSzzygetzyTLBEntryLoRegzyCapLG}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryloreg_caplg786d24724304fa8846dc63540a94622b.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryLoRegCapLG}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryLoRegzyCapLG}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryloreg_caplg786d24724304fa8846dc63540a94622b.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryLoRegCapLG}{\saildoclabelled{sailMIPSzzysetzyTLBEntryLoRegzyCapLG}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryloreg_caplg3dd41e627a6f13d73dc55778a444e440.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryLoRegCapLG}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryLoRegzyCapLG}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryloreg_caplg3dd41e627a6f13d73dc55778a444e440.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryLoRegCapLG}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryLoRegzyCapLG}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryloreg_caplg74d3e13531d835cb013f9516a2c860b5.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryLoRegCapLG}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryLoRegzyCapLG}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryloreg_caplg74d3e13531d835cb013f9516a2c860b5.tex}}}} + +\newcommand{\sailMIPSoverloadWWWupdateCapLG}{\saildoclabelled{sailMIPSoverloadWWWzupdatezyCapLG}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadWWWzupdate_caplgb9408b2c97a868b24bf4fafd9a974c0d.tex}}}} + +\newcommand{\sailMIPSoverloadXXXModCapLG}{\saildoclabelled{sailMIPSoverloadXXXzzymodzyCapLG}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadXXXz_mod_caplgde160c8f451c418f4014f00afcc95766.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryLoRegPFN}{\saildoclabelled{sailMIPSzzygetzyTLBEntryLoRegzyPFN}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryloreg_pfn7485f8da186fc5d3d7c7c1b76ae7d61a.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryLoRegPFN}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryLoRegzyPFN}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryloreg_pfn7485f8da186fc5d3d7c7c1b76ae7d61a.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryLoRegPFN}{\saildoclabelled{sailMIPSzzysetzyTLBEntryLoRegzyPFN}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryloreg_pfn6136b1f7a14537cfb91196ba247d881e.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryLoRegPFN}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryLoRegzyPFN}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryloreg_pfn6136b1f7a14537cfb91196ba247d881e.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryLoRegPFN}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryLoRegzyPFN}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryloreg_pfn09564a0f7205bf65c965dda38fd2c7b1.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryLoRegPFN}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryLoRegzyPFN}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryloreg_pfn09564a0f7205bf65c965dda38fd2c7b1.tex}}}} + +\newcommand{\sailMIPSoverloadYYYupdatePFN}{\saildoclabelled{sailMIPSoverloadYYYzupdatezyPFN}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadYYYzupdate_pfn8465b5dd902528d594c32acf79e47d31.tex}}}} + +\newcommand{\sailMIPSoverloadZZZModPFN}{\saildoclabelled{sailMIPSoverloadZZZzzymodzyPFN}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadZZZz_mod_pfnd0a43f9c31fe271df6057856de04c9d4.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryLoRegC}{\saildoclabelled{sailMIPSzzygetzyTLBEntryLoRegzyC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryloreg_c2c40f3d64ca0b68a2277af1f60c581c1.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryLoRegC}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryLoRegzyC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryloreg_c2c40f3d64ca0b68a2277af1f60c581c1.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryLoRegC}{\saildoclabelled{sailMIPSzzysetzyTLBEntryLoRegzyC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryloreg_c08e3096dbb8171c7d2a2c6b6c853e622.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryLoRegC}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryLoRegzyC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryloreg_c08e3096dbb8171c7d2a2c6b6c853e622.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryLoRegC}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryLoRegzyC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryloreg_c720c1b6d680bdb0fc873d902ab9e3854.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryLoRegC}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryLoRegzyC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryloreg_c720c1b6d680bdb0fc873d902ab9e3854.tex}}}} + +\newcommand{\sailMIPSoverloadAAAAupdateC}{\saildoclabelled{sailMIPSoverloadAAAAzupdatezyC}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadAAAAzupdate_c58b96a6767db6cbc4e0bfce6023a35b9.tex}}}} + +\newcommand{\sailMIPSoverloadBBBBModC}{\saildoclabelled{sailMIPSoverloadBBBBzzymodzyC}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadBBBBz_mod_ceb8c62eaf4804c4722a6c0c552f18d93.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryLoRegD}{\saildoclabelled{sailMIPSzzygetzyTLBEntryLoRegzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryloreg_d4b10819936f555836fbb97995377cad3.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryLoRegD}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryLoRegzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryloreg_d4b10819936f555836fbb97995377cad3.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryLoRegD}{\saildoclabelled{sailMIPSzzysetzyTLBEntryLoRegzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryloreg_d04572c2344c6e87906ebf8c78d44671a.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryLoRegD}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryLoRegzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryloreg_d04572c2344c6e87906ebf8c78d44671a.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryLoRegD}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryLoRegzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryloreg_ddadb2d338250cae60e5c96dc8dc2f118.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryLoRegD}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryLoRegzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryloreg_ddadb2d338250cae60e5c96dc8dc2f118.tex}}}} + +\newcommand{\sailMIPSoverloadCCCCupdateD}{\saildoclabelled{sailMIPSoverloadCCCCzupdatezyD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadCCCCzupdate_da9201c8a6710e680d16238f3581a0227.tex}}}} + +\newcommand{\sailMIPSoverloadDDDDModD}{\saildoclabelled{sailMIPSoverloadDDDDzzymodzyD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadDDDDz_mod_d8c29507d9735e49d608a373bd2e2c599.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryLoRegV}{\saildoclabelled{sailMIPSzzygetzyTLBEntryLoRegzyV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryloreg_v92356d3167d468ba946d0be3ad44b292.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryLoRegV}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryLoRegzyV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryloreg_v92356d3167d468ba946d0be3ad44b292.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryLoRegV}{\saildoclabelled{sailMIPSzzysetzyTLBEntryLoRegzyV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryloreg_v479a48bad10c13e1834cb43c00f02400.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryLoRegV}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryLoRegzyV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryloreg_v479a48bad10c13e1834cb43c00f02400.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryLoRegV}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryLoRegzyV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryloreg_v464571bc28acefba62b6c96884a2ac5e.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryLoRegV}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryLoRegzyV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryloreg_v464571bc28acefba62b6c96884a2ac5e.tex}}}} + +\newcommand{\sailMIPSoverloadEEEEupdateV}{\saildoclabelled{sailMIPSoverloadEEEEzupdatezyV}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadEEEEzupdate_v550d76e01b2aee2bcdcdd8fcb788e6ae.tex}}}} + +\newcommand{\sailMIPSoverloadFFFFModV}{\saildoclabelled{sailMIPSoverloadFFFFzzymodzyV}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadFFFFz_mod_v136fe7ecc31e11f2521faa02b71b57fa.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryLoRegG}{\saildoclabelled{sailMIPSzzygetzyTLBEntryLoRegzyG}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryloreg_g502b190f751a82f1efdb937a5164a942.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryLoRegG}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryLoRegzyG}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryloreg_g502b190f751a82f1efdb937a5164a942.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryLoRegG}{\saildoclabelled{sailMIPSzzysetzyTLBEntryLoRegzyG}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryloreg_g81ecbc57653a1477c15cea1541c708f3.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryLoRegG}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryLoRegzyG}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryloreg_g81ecbc57653a1477c15cea1541c708f3.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryLoRegG}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryLoRegzyG}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryloreg_gcbb777750a024300d463c99664060b0e.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryLoRegG}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryLoRegzyG}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryloreg_gcbb777750a024300d463c99664060b0e.tex}}}} + +\newcommand{\sailMIPSoverloadGGGGupdateG}{\saildoclabelled{sailMIPSoverloadGGGGzupdatezyG}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadGGGGzupdate_ga61979e0097ae60f8598f57688dbae8b.tex}}}} + +\newcommand{\sailMIPSoverloadHHHHModG}{\saildoclabelled{sailMIPSoverloadHHHHzzymodzyG}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadHHHHz_mod_g521053c016cb3f20bf7b96843a7a2cf4.tex}}}} + +\newcommand{\sailMIPStypeTLBEntryHiReg}{\saildoclabelled{sailMIPStypezTLBEntryHiReg}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typeztlbentryhireg6a2dd5c7437ed3c296ee69b189e6879f.tex}}}} + +\newcommand{\sailMIPSvalMkTLBEntryHiReg}{\saildoclabelled{sailMIPSzMkzyTLBEntryHiReg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmk_tlbentryhireg6533ea9a44dee28d4b6d342ff77ceb66.tex}}}} + +\newcommand{\sailMIPSfnMkTLBEntryHiReg}{\saildoclabelled{sailMIPSfnzMkzyTLBEntryHiReg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmk_tlbentryhireg6533ea9a44dee28d4b6d342ff77ceb66.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryHiRegBits}{\saildoclabelled{sailMIPSzzygetzyTLBEntryHiRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryhireg_bitsc1fe8d0802182557771e92e1a4937cbe.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryHiRegBits}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryHiRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryhireg_bitsc1fe8d0802182557771e92e1a4937cbe.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryHiRegBits}{\saildoclabelled{sailMIPSzzysetzyTLBEntryHiRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryhireg_bits830f40aea8b421a1ac74662681c59991.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryHiRegBits}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryHiRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryhireg_bits830f40aea8b421a1ac74662681c59991.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryHiRegBits}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryHiRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryhireg_bitsa10c10b31a1704b4bbb65828e235738a.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryHiRegBits}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryHiRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryhireg_bitsa10c10b31a1704b4bbb65828e235738a.tex}}}} + +\newcommand{\sailMIPSoverloadIIIIupdateBits}{\saildoclabelled{sailMIPSoverloadIIIIzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadIIIIzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailMIPSoverloadJJJJModBits}{\saildoclabelled{sailMIPSoverloadJJJJzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadJJJJz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryHiRegR}{\saildoclabelled{sailMIPSzzygetzyTLBEntryHiRegzyR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryhireg_r44dfedd92d1d8ea253c1ecd027897188.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryHiRegR}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryHiRegzyR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryhireg_r44dfedd92d1d8ea253c1ecd027897188.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryHiRegR}{\saildoclabelled{sailMIPSzzysetzyTLBEntryHiRegzyR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryhireg_rdbcd78e9049138ceacd56be71478b061.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryHiRegR}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryHiRegzyR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryhireg_rdbcd78e9049138ceacd56be71478b061.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryHiRegR}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryHiRegzyR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryhireg_r06c8b0ecb6f68f0d45d384366fd03e59.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryHiRegR}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryHiRegzyR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryhireg_r06c8b0ecb6f68f0d45d384366fd03e59.tex}}}} + +\newcommand{\sailMIPSoverloadKKKKupdateR}{\saildoclabelled{sailMIPSoverloadKKKKzupdatezyR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadKKKKzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex}}}} + +\newcommand{\sailMIPSoverloadLLLLModR}{\saildoclabelled{sailMIPSoverloadLLLLzzymodzyR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadLLLLz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryHiRegCLGK}{\saildoclabelled{sailMIPSzzygetzyTLBEntryHiRegzyCLGK}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryhireg_clgkfdb82e0b9411605641d3f9425136dfa9.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryHiRegCLGK}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryHiRegzyCLGK}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryhireg_clgkfdb82e0b9411605641d3f9425136dfa9.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryHiRegCLGK}{\saildoclabelled{sailMIPSzzysetzyTLBEntryHiRegzyCLGK}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryhireg_clgkf7b384835e909bb74e4373c5c929ab4a.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryHiRegCLGK}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryHiRegzyCLGK}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryhireg_clgkf7b384835e909bb74e4373c5c929ab4a.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryHiRegCLGK}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryHiRegzyCLGK}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryhireg_clgk635276a161c10c3ac2a0c446f734a32a.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryHiRegCLGK}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryHiRegzyCLGK}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryhireg_clgk635276a161c10c3ac2a0c446f734a32a.tex}}}} + +\newcommand{\sailMIPSoverloadMMMMupdateCLGK}{\saildoclabelled{sailMIPSoverloadMMMMzupdatezyCLGK}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadMMMMzupdate_clgk1d75cd5573a5f7f252a6ee39f19e5a48.tex}}}} + +\newcommand{\sailMIPSoverloadNNNNModCLGK}{\saildoclabelled{sailMIPSoverloadNNNNzzymodzyCLGK}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadNNNNz_mod_clgkd08fc6d828d08c1745c289a488c357c7.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryHiRegCLGS}{\saildoclabelled{sailMIPSzzygetzyTLBEntryHiRegzyCLGS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryhireg_clgseb7676dc6f5a395d559518d6f85dcb64.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryHiRegCLGS}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryHiRegzyCLGS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryhireg_clgseb7676dc6f5a395d559518d6f85dcb64.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryHiRegCLGS}{\saildoclabelled{sailMIPSzzysetzyTLBEntryHiRegzyCLGS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryhireg_clgse8c691628327ecea822d37b3003caf39.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryHiRegCLGS}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryHiRegzyCLGS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryhireg_clgse8c691628327ecea822d37b3003caf39.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryHiRegCLGS}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryHiRegzyCLGS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryhireg_clgs2a321d8cde93a407a0a48e78b11f8b02.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryHiRegCLGS}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryHiRegzyCLGS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryhireg_clgs2a321d8cde93a407a0a48e78b11f8b02.tex}}}} + +\newcommand{\sailMIPSoverloadOOOOupdateCLGS}{\saildoclabelled{sailMIPSoverloadOOOOzupdatezyCLGS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadOOOOzupdate_clgs3865dc13c1369c4c0ed0f110f40dc15c.tex}}}} + +\newcommand{\sailMIPSoverloadPPPPModCLGS}{\saildoclabelled{sailMIPSoverloadPPPPzzymodzyCLGS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadPPPPz_mod_clgsb2cb4479fedb595ba53b27015c4e69b4.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryHiRegCLGU}{\saildoclabelled{sailMIPSzzygetzyTLBEntryHiRegzyCLGU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryhireg_clgu64e2f125adf86091d1447f203f4ee7c6.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryHiRegCLGU}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryHiRegzyCLGU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryhireg_clgu64e2f125adf86091d1447f203f4ee7c6.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryHiRegCLGU}{\saildoclabelled{sailMIPSzzysetzyTLBEntryHiRegzyCLGU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryhireg_clgua9dab1e5d85bccd1023c42cf9f9bc70a.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryHiRegCLGU}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryHiRegzyCLGU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryhireg_clgua9dab1e5d85bccd1023c42cf9f9bc70a.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryHiRegCLGU}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryHiRegzyCLGU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryhireg_clgub94d1691569cf6e49d6171ef49e4c86b.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryHiRegCLGU}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryHiRegzyCLGU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryhireg_clgub94d1691569cf6e49d6171ef49e4c86b.tex}}}} + +\newcommand{\sailMIPSoverloadQQQQupdateCLGU}{\saildoclabelled{sailMIPSoverloadQQQQzupdatezyCLGU}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadQQQQzupdate_clgubec52b9e8fec05b1bfd801a107f6888b.tex}}}} + +\newcommand{\sailMIPSoverloadRRRRModCLGU}{\saildoclabelled{sailMIPSoverloadRRRRzzymodzyCLGU}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadRRRRz_mod_clgu3d6fa470ec4a04451aa9e951adaa6909.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryHiRegVPNTwo}{\saildoclabelled{sailMIPSzzygetzyTLBEntryHiRegzyVPN2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryhireg_vpn226453e167422a9d6ebc21b19f1c01475.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryHiRegVPNTwo}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryHiRegzyVPN2}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryhireg_vpn226453e167422a9d6ebc21b19f1c01475.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryHiRegVPNTwo}{\saildoclabelled{sailMIPSzzysetzyTLBEntryHiRegzyVPN2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryhireg_vpn2ea6ff2e6ee98b0eaf79e756b606dd7f7.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryHiRegVPNTwo}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryHiRegzyVPN2}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryhireg_vpn2ea6ff2e6ee98b0eaf79e756b606dd7f7.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryHiRegVPNTwo}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryHiRegzyVPN2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryhireg_vpn2a5a0eafdc27da5a10c42b69c9f6e759f.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryHiRegVPNTwo}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryHiRegzyVPN2}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryhireg_vpn2a5a0eafdc27da5a10c42b69c9f6e759f.tex}}}} + +\newcommand{\sailMIPSoverloadSSSSupdateVPNTwo}{\saildoclabelled{sailMIPSoverloadSSSSzupdatezyVPN2}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadSSSSzupdate_vpn220be6c7a0b8945ad28c3a3e621dd8e79.tex}}}} + +\newcommand{\sailMIPSoverloadTTTTModVPNTwo}{\saildoclabelled{sailMIPSoverloadTTTTzzymodzyVPN2}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadTTTTz_mod_vpn28c8a281e6dcbd5a2c649a7902b509b16.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryHiRegASID}{\saildoclabelled{sailMIPSzzygetzyTLBEntryHiRegzyASID}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentryhireg_asidf305efdb6fafa938b0b36e9cf1064c32.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryHiRegASID}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryHiRegzyASID}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentryhireg_asidf305efdb6fafa938b0b36e9cf1064c32.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryHiRegASID}{\saildoclabelled{sailMIPSzzysetzyTLBEntryHiRegzyASID}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentryhireg_asid321161cd55126c8938237eb466aaf985.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryHiRegASID}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryHiRegzyASID}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentryhireg_asid321161cd55126c8938237eb466aaf985.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryHiRegASID}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryHiRegzyASID}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentryhireg_asidb7a77785e726aa2fce0d7e93a9630b8d.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryHiRegASID}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryHiRegzyASID}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentryhireg_asidb7a77785e726aa2fce0d7e93a9630b8d.tex}}}} + +\newcommand{\sailMIPSoverloadUUUUupdateASID}{\saildoclabelled{sailMIPSoverloadUUUUzupdatezyASID}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadUUUUzupdate_asid68eb6e5d121a0aa3f8a040a0f4751c40.tex}}}} + +\newcommand{\sailMIPSoverloadVVVVModASID}{\saildoclabelled{sailMIPSoverloadVVVVzzymodzyASID}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadVVVVz_mod_asid4980346bfaaf5eeb3565141f722852d6.tex}}}} + +\newcommand{\sailMIPStypeContextReg}{\saildoclabelled{sailMIPStypezContextReg}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezcontextreg4859b14bb9c8e2fac453ab6f118b53e5.tex}}}} + +\newcommand{\sailMIPSvalMkContextReg}{\saildoclabelled{sailMIPSzMkzyContextReg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmk_contextreg1279723b7ab574992f73b31ca621ca0c.tex}}}} + +\newcommand{\sailMIPSfnMkContextReg}{\saildoclabelled{sailMIPSfnzMkzyContextReg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmk_contextreg1279723b7ab574992f73b31ca621ca0c.tex}}}} + +\newcommand{\sailMIPSvalGetContextRegBits}{\saildoclabelled{sailMIPSzzygetzyContextRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_contextreg_bits47e3c1ae3f3d71fe07d89e26af0dbb84.tex}}}} + +\newcommand{\sailMIPSfnGetContextRegBits}{\saildoclabelled{sailMIPSfnzzygetzyContextRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_contextreg_bits47e3c1ae3f3d71fe07d89e26af0dbb84.tex}}}} + +\newcommand{\sailMIPSvalSetContextRegBits}{\saildoclabelled{sailMIPSzzysetzyContextRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_contextreg_bitsbbc1c515c2c901309dcbe9d97b5823cc.tex}}}} + +\newcommand{\sailMIPSfnSetContextRegBits}{\saildoclabelled{sailMIPSfnzzysetzyContextRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_contextreg_bitsbbc1c515c2c901309dcbe9d97b5823cc.tex}}}} + +\newcommand{\sailMIPSvalUpdateContextRegBits}{\saildoclabelled{sailMIPSzzyupdatezyContextRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_contextreg_bits0df4e43fe9f13b5860f4e758b65c124c.tex}}}} + +\newcommand{\sailMIPSfnUpdateContextRegBits}{\saildoclabelled{sailMIPSfnzzyupdatezyContextRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_contextreg_bits0df4e43fe9f13b5860f4e758b65c124c.tex}}}} + +\newcommand{\sailMIPSoverloadWWWWupdateBits}{\saildoclabelled{sailMIPSoverloadWWWWzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailMIPSoverloadXXXXModBits}{\saildoclabelled{sailMIPSoverloadXXXXzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailMIPSvalGetContextRegPTEBase}{\saildoclabelled{sailMIPSzzygetzyContextRegzyPTEBase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_contextreg_ptebasebf430c35bdc563e19c3245773b4235dd.tex}}}} + +\newcommand{\sailMIPSfnGetContextRegPTEBase}{\saildoclabelled{sailMIPSfnzzygetzyContextRegzyPTEBase}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_contextreg_ptebasebf430c35bdc563e19c3245773b4235dd.tex}}}} + +\newcommand{\sailMIPSvalSetContextRegPTEBase}{\saildoclabelled{sailMIPSzzysetzyContextRegzyPTEBase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_contextreg_ptebase3d2c746ed33c90438134f4f612df5252.tex}}}} + +\newcommand{\sailMIPSfnSetContextRegPTEBase}{\saildoclabelled{sailMIPSfnzzysetzyContextRegzyPTEBase}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_contextreg_ptebase3d2c746ed33c90438134f4f612df5252.tex}}}} + +\newcommand{\sailMIPSvalUpdateContextRegPTEBase}{\saildoclabelled{sailMIPSzzyupdatezyContextRegzyPTEBase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_contextreg_ptebase3ac56067efaf9c4426e60d8d4f9e4827.tex}}}} + +\newcommand{\sailMIPSfnUpdateContextRegPTEBase}{\saildoclabelled{sailMIPSfnzzyupdatezyContextRegzyPTEBase}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_contextreg_ptebase3ac56067efaf9c4426e60d8d4f9e4827.tex}}}} + +\newcommand{\sailMIPSoverloadYYYYupdatePTEBase}{\saildoclabelled{sailMIPSoverloadYYYYzupdatezyPTEBase}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadYYYYzupdate_ptebase2ea26e695d7955da0671b82b96885404.tex}}}} + +\newcommand{\sailMIPSoverloadZZZZModPTEBase}{\saildoclabelled{sailMIPSoverloadZZZZzzymodzyPTEBase}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadZZZZz_mod_ptebase2f0d0b71640e150cfba79584bdbb2c74.tex}}}} + +\newcommand{\sailMIPSvalGetContextRegBadVPNTwo}{\saildoclabelled{sailMIPSzzygetzyContextRegzyBadVPN2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_contextreg_badvpn2e4bacc76aa9f96063f0745bd9686a16d.tex}}}} + +\newcommand{\sailMIPSfnGetContextRegBadVPNTwo}{\saildoclabelled{sailMIPSfnzzygetzyContextRegzyBadVPN2}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_contextreg_badvpn2e4bacc76aa9f96063f0745bd9686a16d.tex}}}} + +\newcommand{\sailMIPSvalSetContextRegBadVPNTwo}{\saildoclabelled{sailMIPSzzysetzyContextRegzyBadVPN2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_contextreg_badvpn29fd378dc6ecdfabb3a91f7deb59e56a1.tex}}}} + +\newcommand{\sailMIPSfnSetContextRegBadVPNTwo}{\saildoclabelled{sailMIPSfnzzysetzyContextRegzyBadVPN2}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_contextreg_badvpn29fd378dc6ecdfabb3a91f7deb59e56a1.tex}}}} + +\newcommand{\sailMIPSvalUpdateContextRegBadVPNTwo}{\saildoclabelled{sailMIPSzzyupdatezyContextRegzyBadVPN2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_contextreg_badvpn29dd1d7ba9698b94e95d082c38f1eab84.tex}}}} + +\newcommand{\sailMIPSfnUpdateContextRegBadVPNTwo}{\saildoclabelled{sailMIPSfnzzyupdatezyContextRegzyBadVPN2}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_contextreg_badvpn29dd1d7ba9698b94e95d082c38f1eab84.tex}}}} + +\newcommand{\sailMIPSoverloadAAAAAupdateBadVPNTwo}{\saildoclabelled{sailMIPSoverloadAAAAAzupdatezyBadVPN2}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadAAAAAzupdate_badvpn2ed07cfb17ee4c0ba07ba1ed27c407cd5.tex}}}} + +\newcommand{\sailMIPSoverloadBBBBBModBadVPNTwo}{\saildoclabelled{sailMIPSoverloadBBBBBzzymodzyBadVPN2}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadBBBBBz_mod_badvpn27f29c44b4acbb87554b40dfacc46aca6.tex}}}} + +\newcommand{\sailMIPStypeXContextReg}{\saildoclabelled{sailMIPStypezXContextReg}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezxcontextregbafb1e34c421e40a1ce1b569d5083916.tex}}}} + +\newcommand{\sailMIPSvalMkXContextReg}{\saildoclabelled{sailMIPSzMkzyXContextReg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmk_xcontextregea90f6c75d17b6f2b8452e8764f15274.tex}}}} + +\newcommand{\sailMIPSfnMkXContextReg}{\saildoclabelled{sailMIPSfnzMkzyXContextReg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmk_xcontextregea90f6c75d17b6f2b8452e8764f15274.tex}}}} + +\newcommand{\sailMIPSvalGetXContextRegBits}{\saildoclabelled{sailMIPSzzygetzyXContextRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_xcontextreg_bits2bb965f07f7084015cb7fcd7fddaa172.tex}}}} + +\newcommand{\sailMIPSfnGetXContextRegBits}{\saildoclabelled{sailMIPSfnzzygetzyXContextRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_xcontextreg_bits2bb965f07f7084015cb7fcd7fddaa172.tex}}}} + +\newcommand{\sailMIPSvalSetXContextRegBits}{\saildoclabelled{sailMIPSzzysetzyXContextRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_xcontextreg_bitsa93b9f55af87e5c9507e10f4f90444f6.tex}}}} + +\newcommand{\sailMIPSfnSetXContextRegBits}{\saildoclabelled{sailMIPSfnzzysetzyXContextRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_xcontextreg_bitsa93b9f55af87e5c9507e10f4f90444f6.tex}}}} + +\newcommand{\sailMIPSvalUpdateXContextRegBits}{\saildoclabelled{sailMIPSzzyupdatezyXContextRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_xcontextreg_bitsdb6e2157fa47608aa5622abf4b763efc.tex}}}} + +\newcommand{\sailMIPSfnUpdateXContextRegBits}{\saildoclabelled{sailMIPSfnzzyupdatezyXContextRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_xcontextreg_bitsdb6e2157fa47608aa5622abf4b763efc.tex}}}} + +\newcommand{\sailMIPSoverloadCCCCCupdateBits}{\saildoclabelled{sailMIPSoverloadCCCCCzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadCCCCCzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailMIPSoverloadDDDDDModBits}{\saildoclabelled{sailMIPSoverloadDDDDDzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadDDDDDz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailMIPSvalGetXContextRegXPTEBase}{\saildoclabelled{sailMIPSzzygetzyXContextRegzyXPTEBase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_xcontextreg_xptebase0f9f79f33119625b2142eafc017db467.tex}}}} + +\newcommand{\sailMIPSfnGetXContextRegXPTEBase}{\saildoclabelled{sailMIPSfnzzygetzyXContextRegzyXPTEBase}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_xcontextreg_xptebase0f9f79f33119625b2142eafc017db467.tex}}}} + +\newcommand{\sailMIPSvalSetXContextRegXPTEBase}{\saildoclabelled{sailMIPSzzysetzyXContextRegzyXPTEBase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_xcontextreg_xptebase1de10092cc0e6fbd31d9a47e20069af7.tex}}}} + +\newcommand{\sailMIPSfnSetXContextRegXPTEBase}{\saildoclabelled{sailMIPSfnzzysetzyXContextRegzyXPTEBase}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_xcontextreg_xptebase1de10092cc0e6fbd31d9a47e20069af7.tex}}}} + +\newcommand{\sailMIPSvalUpdateXContextRegXPTEBase}{\saildoclabelled{sailMIPSzzyupdatezyXContextRegzyXPTEBase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_xcontextreg_xptebase729a58cc2ea0bab68cb0c93124af9313.tex}}}} + +\newcommand{\sailMIPSfnUpdateXContextRegXPTEBase}{\saildoclabelled{sailMIPSfnzzyupdatezyXContextRegzyXPTEBase}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_xcontextreg_xptebase729a58cc2ea0bab68cb0c93124af9313.tex}}}} + +\newcommand{\sailMIPSoverloadEEEEEupdateXPTEBase}{\saildoclabelled{sailMIPSoverloadEEEEEzupdatezyXPTEBase}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadEEEEEzupdate_xptebase824212fd8ab34e381399a9fd3bdbacb2.tex}}}} + +\newcommand{\sailMIPSoverloadFFFFFModXPTEBase}{\saildoclabelled{sailMIPSoverloadFFFFFzzymodzyXPTEBase}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadFFFFFz_mod_xptebase52f38d47c32d7dae47f1a4a036025464.tex}}}} + +\newcommand{\sailMIPSvalGetXContextRegXR}{\saildoclabelled{sailMIPSzzygetzyXContextRegzyXR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_xcontextreg_xrbc5c747b1b3124406ffd75a370867ebf.tex}}}} + +\newcommand{\sailMIPSfnGetXContextRegXR}{\saildoclabelled{sailMIPSfnzzygetzyXContextRegzyXR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_xcontextreg_xrbc5c747b1b3124406ffd75a370867ebf.tex}}}} + +\newcommand{\sailMIPSvalSetXContextRegXR}{\saildoclabelled{sailMIPSzzysetzyXContextRegzyXR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_xcontextreg_xr0085c3da7716883767dbf111c432fb50.tex}}}} + +\newcommand{\sailMIPSfnSetXContextRegXR}{\saildoclabelled{sailMIPSfnzzysetzyXContextRegzyXR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_xcontextreg_xr0085c3da7716883767dbf111c432fb50.tex}}}} + +\newcommand{\sailMIPSvalUpdateXContextRegXR}{\saildoclabelled{sailMIPSzzyupdatezyXContextRegzyXR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_xcontextreg_xrfb95bbc02275c03eb4bc1562a36f7671.tex}}}} + +\newcommand{\sailMIPSfnUpdateXContextRegXR}{\saildoclabelled{sailMIPSfnzzyupdatezyXContextRegzyXR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_xcontextreg_xrfb95bbc02275c03eb4bc1562a36f7671.tex}}}} + +\newcommand{\sailMIPSoverloadGGGGGupdateXR}{\saildoclabelled{sailMIPSoverloadGGGGGzupdatezyXR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadGGGGGzupdate_xr0dfb3b8608abe69ac3ecb9ebe1723645.tex}}}} + +\newcommand{\sailMIPSoverloadHHHHHModXR}{\saildoclabelled{sailMIPSoverloadHHHHHzzymodzyXR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadHHHHHz_mod_xr58438b12ce6dc4c713fa978abe898f59.tex}}}} + +\newcommand{\sailMIPSvalGetXContextRegXBadVPNTwo}{\saildoclabelled{sailMIPSzzygetzyXContextRegzyXBadVPN2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_xcontextreg_xbadvpn2404ed71ef244d675e19fa66dceb1c9c3.tex}}}} + +\newcommand{\sailMIPSfnGetXContextRegXBadVPNTwo}{\saildoclabelled{sailMIPSfnzzygetzyXContextRegzyXBadVPN2}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_xcontextreg_xbadvpn2404ed71ef244d675e19fa66dceb1c9c3.tex}}}} + +\newcommand{\sailMIPSvalSetXContextRegXBadVPNTwo}{\saildoclabelled{sailMIPSzzysetzyXContextRegzyXBadVPN2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_xcontextreg_xbadvpn2b3e73a92b43f1a839bc59b518dda6dc3.tex}}}} + +\newcommand{\sailMIPSfnSetXContextRegXBadVPNTwo}{\saildoclabelled{sailMIPSfnzzysetzyXContextRegzyXBadVPN2}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_xcontextreg_xbadvpn2b3e73a92b43f1a839bc59b518dda6dc3.tex}}}} + +\newcommand{\sailMIPSvalUpdateXContextRegXBadVPNTwo}{\saildoclabelled{sailMIPSzzyupdatezyXContextRegzyXBadVPN2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_xcontextreg_xbadvpn271be6846d4092b3dba3bc6c81857b1b9.tex}}}} + +\newcommand{\sailMIPSfnUpdateXContextRegXBadVPNTwo}{\saildoclabelled{sailMIPSfnzzyupdatezyXContextRegzyXBadVPN2}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_xcontextreg_xbadvpn271be6846d4092b3dba3bc6c81857b1b9.tex}}}} + +\newcommand{\sailMIPSoverloadIIIIIupdateXBadVPNTwo}{\saildoclabelled{sailMIPSoverloadIIIIIzupdatezyXBadVPN2}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadIIIIIzupdate_xbadvpn239829bed7a81273818a992030fb566e4.tex}}}} + +\newcommand{\sailMIPSoverloadJJJJJModXBadVPNTwo}{\saildoclabelled{sailMIPSoverloadJJJJJzzymodzyXBadVPN2}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadJJJJJz_mod_xbadvpn2b779444a2db61a5e00de492489d3d5d5.tex}}}} + +\newcommand{\sailMIPStypeTLBIndexT}{\saildoclabelled{sailMIPStypezTLBIndexT}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typeztlbindext3787f4de8ebd404a524c1c53e1adc1c9.tex}}}} + +\newcommand{\sailMIPSvalMAX}{\saildoclabelled{sailMIPSzMAX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex}}}} + +\newcommand{\sailMIPSfnMAX}{\saildoclabelled{sailMIPSfnzMAX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex}}}} + +\newcommand{\sailMIPStypeTLBEntry}{\saildoclabelled{sailMIPStypezTLBEntry}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typeztlbentrydb6733ff232beb81c7ffa4ec6b366366.tex}}}} + +\newcommand{\sailMIPSvalMkTLBEntry}{\saildoclabelled{sailMIPSzMkzyTLBEntry}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmk_tlbentry1b93a8ab49c4923ac3e577c5f28836c1.tex}}}} + +\newcommand{\sailMIPSfnMkTLBEntry}{\saildoclabelled{sailMIPSfnzMkzyTLBEntry}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmk_tlbentry1b93a8ab49c4923ac3e577c5f28836c1.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryBits}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_bits2da520175dbc548dab43cb481dedc49b.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryBits}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_bits2da520175dbc548dab43cb481dedc49b.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryBits}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_bits757b4b8be4b3d6e342d238326f83470b.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryBits}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_bits757b4b8be4b3d6e342d238326f83470b.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryBits}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_bits1b789098a048790468b840f08f48d3fd.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryBits}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_bits1b789098a048790468b840f08f48d3fd.tex}}}} + +\newcommand{\sailMIPSoverloadKKKKKupdateBits}{\saildoclabelled{sailMIPSoverloadKKKKKzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadKKKKKzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailMIPSoverloadLLLLLModBits}{\saildoclabelled{sailMIPSoverloadLLLLLzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadLLLLLz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryPagemask}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzypagemask}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_pagemask3eb7a6727c91e807993723589bef84a0.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryPagemask}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzypagemask}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_pagemask3eb7a6727c91e807993723589bef84a0.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryPagemask}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzypagemask}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_pagemask688109458a7688b3fb0c4bd96cc468ce.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryPagemask}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzypagemask}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_pagemask688109458a7688b3fb0c4bd96cc468ce.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryPagemask}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzypagemask}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_pagemaskbb0f8a2bdd38e987c7a2e2b338e3b75f.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryPagemask}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzypagemask}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_pagemaskbb0f8a2bdd38e987c7a2e2b338e3b75f.tex}}}} + +\newcommand{\sailMIPSoverloadMMMMMupdatePagemask}{\saildoclabelled{sailMIPSoverloadMMMMMzupdatezypagemask}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadMMMMMzupdate_pagemaskc94cf18779cd739c7f8909b768b97fb8.tex}}}} + +\newcommand{\sailMIPSoverloadNNNNNModPagemask}{\saildoclabelled{sailMIPSoverloadNNNNNzzymodzypagemask}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadNNNNNz_mod_pagemask324eab4b891010bfc717c1f9165ad98d.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryR}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzyr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_ra5d843d822ff9bbef3239d0723cdb795.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryR}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzyr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_ra5d843d822ff9bbef3239d0723cdb795.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryR}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzyr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_r13eb1c39c82ca214056fd1b1c838ef2f.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryR}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzyr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_r13eb1c39c82ca214056fd1b1c838ef2f.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryR}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzyr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_r9a41b411e6ff9bebfc4172a28c5dbdee.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryR}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzyr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_r9a41b411e6ff9bebfc4172a28c5dbdee.tex}}}} + +\newcommand{\sailMIPSoverloadOOOOOupdateRA}{\saildoclabelled{sailMIPSoverloadOOOOOzupdatezyr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadOOOOOzupdate_rce22633bb855a1c8b994977adc9d3b46.tex}}}} + +\newcommand{\sailMIPSoverloadPPPPPModRA}{\saildoclabelled{sailMIPSoverloadPPPPPzzymodzyr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadPPPPPz_mod_r9af13eeb7ae69634b901ce634288d493.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryVpnTwo}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzyvpn2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_vpn28db0f6d71609de412536d5cf13f67255.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryVpnTwo}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzyvpn2}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_vpn28db0f6d71609de412536d5cf13f67255.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryVpnTwo}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzyvpn2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_vpn298a5bd5fa3b51188021ac781ba6fee98.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryVpnTwo}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzyvpn2}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_vpn298a5bd5fa3b51188021ac781ba6fee98.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryVpnTwo}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzyvpn2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_vpn24c1efd2008ce4086cb554186508bd63a.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryVpnTwo}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzyvpn2}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_vpn24c1efd2008ce4086cb554186508bd63a.tex}}}} + +\newcommand{\sailMIPSoverloadQQQQQupdateVpnTwo}{\saildoclabelled{sailMIPSoverloadQQQQQzupdatezyvpn2}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadQQQQQzupdate_vpn2865beffbfb51948cd997d2f75fbf5170.tex}}}} + +\newcommand{\sailMIPSoverloadRRRRRModVpnTwo}{\saildoclabelled{sailMIPSoverloadRRRRRzzymodzyvpn2}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadRRRRRz_mod_vpn25e147a36ddcf1023cffabc717f9bd2da.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryAsid}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzyasid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_asidfa47e24a47d583f491181ee21931f29a.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryAsid}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzyasid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_asidfa47e24a47d583f491181ee21931f29a.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryAsid}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzyasid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_asid24ada87abf0e962f7eae9b5498024297.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryAsid}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzyasid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_asid24ada87abf0e962f7eae9b5498024297.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryAsid}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzyasid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_asidb6b5d414b15c08829bdf389448396971.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryAsid}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzyasid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_asidb6b5d414b15c08829bdf389448396971.tex}}}} + +\newcommand{\sailMIPSoverloadSSSSSupdateAsid}{\saildoclabelled{sailMIPSoverloadSSSSSzupdatezyasid}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadSSSSSzupdate_asid326dfb0feb114271dfb6df15f22a2ec1.tex}}}} + +\newcommand{\sailMIPSoverloadTTTTTModAsid}{\saildoclabelled{sailMIPSoverloadTTTTTzzymodzyasid}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadTTTTTz_mod_asid57efb91e5ea152ff241933923e49a84a.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryG}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzyg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_geeba2979d3314ef4d79ccdc6321d56cf.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryG}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzyg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_geeba2979d3314ef4d79ccdc6321d56cf.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryG}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzyg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_g2bf85ee100b3f01a0e05550245e7babe.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryG}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzyg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_g2bf85ee100b3f01a0e05550245e7babe.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryG}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzyg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_g20222955c3b959c9ff4647404fedbfef.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryG}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzyg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_g20222955c3b959c9ff4647404fedbfef.tex}}}} + +\newcommand{\sailMIPSoverloadUUUUUupdateGA}{\saildoclabelled{sailMIPSoverloadUUUUUzupdatezyg}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadUUUUUzupdate_ga643ac581ef3df825870fe6e052d11dd.tex}}}} + +\newcommand{\sailMIPSoverloadVVVVVModGA}{\saildoclabelled{sailMIPSoverloadVVVVVzzymodzyg}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadVVVVVz_mod_gf55a79d4c50aa120c58f85267f7f6a6a.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryValid}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzyvalid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_valid270ce68bc126e75f8229aa1123921cdb.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryValid}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzyvalid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_valid270ce68bc126e75f8229aa1123921cdb.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryValid}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzyvalid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_valida29af220299133e11c38510f27092e5d.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryValid}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzyvalid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_valida29af220299133e11c38510f27092e5d.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryValid}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzyvalid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_valid7dd0569211421c835b46068a7bd34a5a.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryValid}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzyvalid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_valid7dd0569211421c835b46068a7bd34a5a.tex}}}} + +\newcommand{\sailMIPSoverloadWWWWWupdateValid}{\saildoclabelled{sailMIPSoverloadWWWWWzupdatezyvalid}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadWWWWWzupdate_validbb04574208bf9cb85093acf3fade71d1.tex}}}} + +\newcommand{\sailMIPSoverloadXXXXXModValid}{\saildoclabelled{sailMIPSoverloadXXXXXzzymodzyvalid}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadXXXXXz_mod_valid8d7cbb6b22e8da4e1c2a35c063b16cbe.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryCaplgOne}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzycaplg1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_caplg177ddc2b577eec904043a0416c9132f3d.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryCaplgOne}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzycaplg1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_caplg177ddc2b577eec904043a0416c9132f3d.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryCaplgOne}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzycaplg1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_caplg1c568708bced17cbfbd6bc97c09748e38.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryCaplgOne}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzycaplg1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_caplg1c568708bced17cbfbd6bc97c09748e38.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryCaplgOne}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzycaplg1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_caplg14ef4abe6e9dfaa69cfd379930a53acda.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryCaplgOne}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzycaplg1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_caplg14ef4abe6e9dfaa69cfd379930a53acda.tex}}}} + +\newcommand{\sailMIPSoverloadYYYYYupdateCaplgOne}{\saildoclabelled{sailMIPSoverloadYYYYYzupdatezycaplg1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadYYYYYzupdate_caplg14947cfbf12f2f7c0f3ac633b9a022476.tex}}}} + +\newcommand{\sailMIPSoverloadZZZZZModCaplgOne}{\saildoclabelled{sailMIPSoverloadZZZZZzzymodzycaplg1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadZZZZZz_mod_caplg1d0010882f7db95a2821cae370f0dbe42.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryCapsOne}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzycaps1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_caps1be8ae1b776f69c2c07935aba85396d3e.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryCapsOne}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzycaps1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_caps1be8ae1b776f69c2c07935aba85396d3e.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryCapsOne}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzycaps1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_caps14e73f26c66b0f5dd767fc96d260e533e.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryCapsOne}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzycaps1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_caps14e73f26c66b0f5dd767fc96d260e533e.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryCapsOne}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzycaps1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_caps1c9648031a984830f7ce96fdd1e079e8a.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryCapsOne}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzycaps1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_caps1c9648031a984830f7ce96fdd1e079e8a.tex}}}} + +\newcommand{\sailMIPSoverloadAAAAAAupdateCapsOne}{\saildoclabelled{sailMIPSoverloadAAAAAAzupdatezycaps1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadAAAAAAzupdate_caps11a0c8b14f627fc4bdd72e123c39905cd.tex}}}} + +\newcommand{\sailMIPSoverloadBBBBBBModCapsOne}{\saildoclabelled{sailMIPSoverloadBBBBBBzzymodzycaps1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadBBBBBBz_mod_caps1f41407643ae768a227e254f27ceaa814.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryCaplOne}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzycapl1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_capl18435a7d1c69be8be8044b9bb801ed828.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryCaplOne}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzycapl1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_capl18435a7d1c69be8be8044b9bb801ed828.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryCaplOne}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzycapl1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_capl11a35d84794ef9016f4f97c80e21c876e.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryCaplOne}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzycapl1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_capl11a35d84794ef9016f4f97c80e21c876e.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryCaplOne}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzycapl1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_capl1c69e2b6d6e2466af2769ae5f3b3a70cc.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryCaplOne}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzycapl1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_capl1c69e2b6d6e2466af2769ae5f3b3a70cc.tex}}}} + +\newcommand{\sailMIPSoverloadCCCCCCupdateCaplOne}{\saildoclabelled{sailMIPSoverloadCCCCCCzupdatezycapl1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadCCCCCCzupdate_capl15a836258329872f209ff11538ab6bd46.tex}}}} + +\newcommand{\sailMIPSoverloadDDDDDDModCaplOne}{\saildoclabelled{sailMIPSoverloadDDDDDDzzymodzycapl1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadDDDDDDz_mod_capl1be097b5150627138c8925b6940717f8f.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryPfnOne}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzypfn1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_pfn18a458700cdc028cfe46524e00f6a420b.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryPfnOne}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzypfn1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_pfn18a458700cdc028cfe46524e00f6a420b.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryPfnOne}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzypfn1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_pfn199862dd67e6305081f59d2d64ffa6977.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryPfnOne}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzypfn1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_pfn199862dd67e6305081f59d2d64ffa6977.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryPfnOne}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzypfn1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_pfn190b25e06aacd9ec8fd6e571532937e98.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryPfnOne}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzypfn1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_pfn190b25e06aacd9ec8fd6e571532937e98.tex}}}} + +\newcommand{\sailMIPSoverloadEEEEEEupdatePfnOne}{\saildoclabelled{sailMIPSoverloadEEEEEEzupdatezypfn1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadEEEEEEzupdate_pfn1214da6ee34bca766359dbffcc3547b0a.tex}}}} + +\newcommand{\sailMIPSoverloadFFFFFFModPfnOne}{\saildoclabelled{sailMIPSoverloadFFFFFFzzymodzypfn1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadFFFFFFz_mod_pfn1a0d295636b191ae9d64a838099f830ba.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryCOne}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzyc1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_c1d9106b812c3987770aecb7aeee7f8fda.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryCOne}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzyc1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_c1d9106b812c3987770aecb7aeee7f8fda.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryCOne}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzyc1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_c148e5c1e1296cfbf56bc100936b91f1e1.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryCOne}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzyc1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_c148e5c1e1296cfbf56bc100936b91f1e1.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryCOne}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzyc1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_c1cecd7e476eb8d0b72ce187ac166f9443.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryCOne}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzyc1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_c1cecd7e476eb8d0b72ce187ac166f9443.tex}}}} + +\newcommand{\sailMIPSoverloadGGGGGGupdateCOne}{\saildoclabelled{sailMIPSoverloadGGGGGGzupdatezyc1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadGGGGGGzupdate_c18c11b21bde25ad918fdd25ea7ff6927b.tex}}}} + +\newcommand{\sailMIPSoverloadHHHHHHModCOne}{\saildoclabelled{sailMIPSoverloadHHHHHHzzymodzyc1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadHHHHHHz_mod_c1ea997b12acb6722314c7b19e41b1677b.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryDOne}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzyd1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_d13706a372dd719081d99230fe90f050d9.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryDOne}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzyd1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_d13706a372dd719081d99230fe90f050d9.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryDOne}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzyd1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_d1f392ee8bca5cfc128a0ed08500399129.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryDOne}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzyd1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_d1f392ee8bca5cfc128a0ed08500399129.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryDOne}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzyd1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_d101453a2a5999d48250bdc176e05e3f5e.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryDOne}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzyd1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_d101453a2a5999d48250bdc176e05e3f5e.tex}}}} + +\newcommand{\sailMIPSoverloadIIIIIIupdateDOne}{\saildoclabelled{sailMIPSoverloadIIIIIIzupdatezyd1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadIIIIIIzupdate_d1de65b1d3efdd740536c08b95a2842c0b.tex}}}} + +\newcommand{\sailMIPSoverloadJJJJJJModDOne}{\saildoclabelled{sailMIPSoverloadJJJJJJzzymodzyd1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadJJJJJJz_mod_d133bac8bf84adab553084245a59d8d0d0.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryVOne}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzyv1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_v13ee360aa18ead69581f7606800abe3c1.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryVOne}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzyv1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_v13ee360aa18ead69581f7606800abe3c1.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryVOne}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzyv1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_v17258e9ab7f5388c5e3cc6aaba8474f00.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryVOne}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzyv1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_v17258e9ab7f5388c5e3cc6aaba8474f00.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryVOne}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzyv1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_v163c9fd3074a5ad5e092a27e64a5fb55e.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryVOne}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzyv1}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_v163c9fd3074a5ad5e092a27e64a5fb55e.tex}}}} + +\newcommand{\sailMIPSoverloadKKKKKKupdateVOne}{\saildoclabelled{sailMIPSoverloadKKKKKKzupdatezyv1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadKKKKKKzupdate_v14252d1d08166b61257da4bf063a2ac6c.tex}}}} + +\newcommand{\sailMIPSoverloadLLLLLLModVOne}{\saildoclabelled{sailMIPSoverloadLLLLLLzzymodzyv1}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadLLLLLLz_mod_v1a0cfae3094149828b19dab3880946df6.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryCaplgZero}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzycaplg0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_caplg09c840f382389fcdb91e393c6d35109de.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryCaplgZero}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzycaplg0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_caplg09c840f382389fcdb91e393c6d35109de.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryCaplgZero}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzycaplg0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_caplg0226ebad6aa3e6193defac30a2d1ea82d.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryCaplgZero}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzycaplg0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_caplg0226ebad6aa3e6193defac30a2d1ea82d.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryCaplgZero}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzycaplg0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_caplg0fc35336b4b0b170579cd74d3e9641075.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryCaplgZero}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzycaplg0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_caplg0fc35336b4b0b170579cd74d3e9641075.tex}}}} + +\newcommand{\sailMIPSoverloadMMMMMMupdateCaplgZero}{\saildoclabelled{sailMIPSoverloadMMMMMMzupdatezycaplg0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadMMMMMMzupdate_caplg0359c196dd43c44a7240d7baa93725c98.tex}}}} + +\newcommand{\sailMIPSoverloadNNNNNNModCaplgZero}{\saildoclabelled{sailMIPSoverloadNNNNNNzzymodzycaplg0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadNNNNNNz_mod_caplg02551d3482d21e938bc88d44876afb940.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryCapsZero}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzycaps0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_caps0426df7440d2fbd940d22c5ff5d90fe0a.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryCapsZero}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzycaps0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_caps0426df7440d2fbd940d22c5ff5d90fe0a.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryCapsZero}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzycaps0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_caps0857000eddf4e4fae631d006dab5b1e0b.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryCapsZero}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzycaps0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_caps0857000eddf4e4fae631d006dab5b1e0b.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryCapsZero}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzycaps0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_caps0a1dc65eb853d421759956887a045ad45.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryCapsZero}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzycaps0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_caps0a1dc65eb853d421759956887a045ad45.tex}}}} + +\newcommand{\sailMIPSoverloadOOOOOOupdateCapsZero}{\saildoclabelled{sailMIPSoverloadOOOOOOzupdatezycaps0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadOOOOOOzupdate_caps04531fbe85f52baa76fbfc27f443b0c46.tex}}}} + +\newcommand{\sailMIPSoverloadPPPPPPModCapsZero}{\saildoclabelled{sailMIPSoverloadPPPPPPzzymodzycaps0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadPPPPPPz_mod_caps01dd0b1fbe9d02d2c772e450c0c776db0.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryCaplZero}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzycapl0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_capl002a98d71ed3a8b3eadd001ccafb63932.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryCaplZero}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzycapl0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_capl002a98d71ed3a8b3eadd001ccafb63932.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryCaplZero}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzycapl0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_capl02f9386e56e409f94f40b03eb58643a70.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryCaplZero}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzycapl0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_capl02f9386e56e409f94f40b03eb58643a70.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryCaplZero}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzycapl0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_capl074805e4eecd0f55c383efab32c765007.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryCaplZero}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzycapl0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_capl074805e4eecd0f55c383efab32c765007.tex}}}} + +\newcommand{\sailMIPSoverloadQQQQQQupdateCaplZero}{\saildoclabelled{sailMIPSoverloadQQQQQQzupdatezycapl0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadQQQQQQzupdate_capl04aa55c1d4284f9eacf5ccdab3c24fb08.tex}}}} + +\newcommand{\sailMIPSoverloadRRRRRRModCaplZero}{\saildoclabelled{sailMIPSoverloadRRRRRRzzymodzycapl0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadRRRRRRz_mod_capl0933e030a2faa459f5db9e9c3882a7ece.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryPfnZero}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzypfn0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_pfn0a3de4c4c668cdca3f146093a35068cb5.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryPfnZero}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzypfn0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_pfn0a3de4c4c668cdca3f146093a35068cb5.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryPfnZero}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzypfn0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_pfn0572e8586307e418abaeebb59ab57b8fb.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryPfnZero}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzypfn0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_pfn0572e8586307e418abaeebb59ab57b8fb.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryPfnZero}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzypfn0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_pfn0d99c89c789d61112a1918a4433ab048d.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryPfnZero}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzypfn0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_pfn0d99c89c789d61112a1918a4433ab048d.tex}}}} + +\newcommand{\sailMIPSoverloadSSSSSSupdatePfnZero}{\saildoclabelled{sailMIPSoverloadSSSSSSzupdatezypfn0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadSSSSSSzupdate_pfn06b632277e9d982792668ad250ca9f560.tex}}}} + +\newcommand{\sailMIPSoverloadTTTTTTModPfnZero}{\saildoclabelled{sailMIPSoverloadTTTTTTzzymodzypfn0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadTTTTTTz_mod_pfn0252a199d91d6fa495671378701e0ec97.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryCZero}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzyc0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_c0b08789b6ce25b380e3b34466198a7af1.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryCZero}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzyc0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_c0b08789b6ce25b380e3b34466198a7af1.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryCZero}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzyc0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_c06c71cb666e35c0f50388fb49595583ae.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryCZero}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzyc0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_c06c71cb666e35c0f50388fb49595583ae.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryCZero}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzyc0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_c0fd743ae9faadd346132a35189c2cd342.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryCZero}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzyc0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_c0fd743ae9faadd346132a35189c2cd342.tex}}}} + +\newcommand{\sailMIPSoverloadUUUUUUupdateCZero}{\saildoclabelled{sailMIPSoverloadUUUUUUzupdatezyc0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadUUUUUUzupdate_c088d2acc9880658f13c362f6dc5200a76.tex}}}} + +\newcommand{\sailMIPSoverloadVVVVVVModCZero}{\saildoclabelled{sailMIPSoverloadVVVVVVzzymodzyc0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadVVVVVVz_mod_c01d0fea16f0e52022abf675f827cc5045.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryDZero}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzyd0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_d0b7eda1bce555ea7549a9dffbb9e46114.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryDZero}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzyd0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_d0b7eda1bce555ea7549a9dffbb9e46114.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryDZero}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzyd0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_d0868263c352cb541c47607b23c5681223.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryDZero}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzyd0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_d0868263c352cb541c47607b23c5681223.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryDZero}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzyd0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_d0e93ed2ed33cbc5c5f202914a237de360.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryDZero}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzyd0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_d0e93ed2ed33cbc5c5f202914a237de360.tex}}}} + +\newcommand{\sailMIPSoverloadWWWWWWupdateDZero}{\saildoclabelled{sailMIPSoverloadWWWWWWzupdatezyd0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadWWWWWWzupdate_d0fb9c19324c8c7805805d2aa368b9f928.tex}}}} + +\newcommand{\sailMIPSoverloadXXXXXXModDZero}{\saildoclabelled{sailMIPSoverloadXXXXXXzzymodzyd0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadXXXXXXz_mod_d0f37cbe87852175a6e90f15df1e64f6bf.tex}}}} + +\newcommand{\sailMIPSvalGetTLBEntryVZero}{\saildoclabelled{sailMIPSzzygetzyTLBEntryzyv0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_tlbentry_v035b9c796665ee176973e82b6ca9389bf.tex}}}} + +\newcommand{\sailMIPSfnGetTLBEntryVZero}{\saildoclabelled{sailMIPSfnzzygetzyTLBEntryzyv0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_tlbentry_v035b9c796665ee176973e82b6ca9389bf.tex}}}} + +\newcommand{\sailMIPSvalSetTLBEntryVZero}{\saildoclabelled{sailMIPSzzysetzyTLBEntryzyv0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_tlbentry_v03152956c4a42e1c80db703a10c7a43d4.tex}}}} + +\newcommand{\sailMIPSfnSetTLBEntryVZero}{\saildoclabelled{sailMIPSfnzzysetzyTLBEntryzyv0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_tlbentry_v03152956c4a42e1c80db703a10c7a43d4.tex}}}} + +\newcommand{\sailMIPSvalUpdateTLBEntryVZero}{\saildoclabelled{sailMIPSzzyupdatezyTLBEntryzyv0}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_tlbentry_v042084d06370a232031d509c4cb3b4ff6.tex}}}} + +\newcommand{\sailMIPSfnUpdateTLBEntryVZero}{\saildoclabelled{sailMIPSfnzzyupdatezyTLBEntryzyv0}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_tlbentry_v042084d06370a232031d509c4cb3b4ff6.tex}}}} + +\newcommand{\sailMIPSoverloadYYYYYYupdateVZero}{\saildoclabelled{sailMIPSoverloadYYYYYYzupdatezyv0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadYYYYYYzupdate_v083f35e3b61c4e09f8255bb126113bf81.tex}}}} + +\newcommand{\sailMIPSoverloadZZZZZZModVZero}{\saildoclabelled{sailMIPSoverloadZZZZZZzzymodzyv0}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadZZZZZZz_mod_v022aed16ab1f8b5385c37e6eef8f1094a.tex}}}} + +\newcommand{\sailMIPSvalgetCPZeroEPC}{\saildoclabelled{sailMIPSzgetzyCP0EPC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzget_cp0epc947f8a8e6dac5833e002f1ea37a79de2.tex}}}} + +\newcommand{\sailMIPSvalsetCPZeroEPC}{\saildoclabelled{sailMIPSzsetzyCP0EPC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzset_cp0epc28b8527a6fc9d9c7e3708c9379630443.tex}}}} + +\newcommand{\sailMIPSvalgetCPZeroErrorEPC}{\saildoclabelled{sailMIPSzgetzyCP0ErrorEPC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzget_cp0errorepc1188335ff3decc7c914ce1ba3a7904dd.tex}}}} + +\newcommand{\sailMIPSvalsetCPZeroErrorEPC}{\saildoclabelled{sailMIPSzsetzyCP0ErrorEPC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzset_cp0errorepc99aeab8b8e922eeb71df49885a629b5d.tex}}}} + +\newcommand{\sailMIPStypeStatusReg}{\saildoclabelled{sailMIPStypezStatusReg}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezstatusreg08ee55655052654d784e0e380989b896.tex}}}} + +\newcommand{\sailMIPSvalMkStatusReg}{\saildoclabelled{sailMIPSzMkzyStatusReg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmk_statusreg3621c22662d06bd540ae8fffe8f9e08c.tex}}}} + +\newcommand{\sailMIPSfnMkStatusReg}{\saildoclabelled{sailMIPSfnzMkzyStatusReg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmk_statusreg3621c22662d06bd540ae8fffe8f9e08c.tex}}}} + +\newcommand{\sailMIPSvalGetStatusRegBits}{\saildoclabelled{sailMIPSzzygetzyStatusRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_statusreg_bits13ab4975f147071137062e2fb2cba87b.tex}}}} + +\newcommand{\sailMIPSfnGetStatusRegBits}{\saildoclabelled{sailMIPSfnzzygetzyStatusRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_statusreg_bits13ab4975f147071137062e2fb2cba87b.tex}}}} + +\newcommand{\sailMIPSvalSetStatusRegBits}{\saildoclabelled{sailMIPSzzysetzyStatusRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_statusreg_bits4f92ee35af828325dd4c014bea381e05.tex}}}} + +\newcommand{\sailMIPSfnSetStatusRegBits}{\saildoclabelled{sailMIPSfnzzysetzyStatusRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_statusreg_bits4f92ee35af828325dd4c014bea381e05.tex}}}} + +\newcommand{\sailMIPSvalUpdateStatusRegBits}{\saildoclabelled{sailMIPSzzyupdatezyStatusRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_statusreg_bits61d5a9099337276f42cc674faed1b40b.tex}}}} + +\newcommand{\sailMIPSfnUpdateStatusRegBits}{\saildoclabelled{sailMIPSfnzzyupdatezyStatusRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_statusreg_bits61d5a9099337276f42cc674faed1b40b.tex}}}} + +\newcommand{\sailMIPSoverloadAAAAAAAupdateBits}{\saildoclabelled{sailMIPSoverloadAAAAAAAzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadAAAAAAAzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailMIPSoverloadBBBBBBBModBits}{\saildoclabelled{sailMIPSoverloadBBBBBBBzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadBBBBBBBz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailMIPSvalGetStatusRegCU}{\saildoclabelled{sailMIPSzzygetzyStatusRegzyCU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_statusreg_cuedce8fb3afbd16db31018057f7ad0656.tex}}}} + +\newcommand{\sailMIPSfnGetStatusRegCU}{\saildoclabelled{sailMIPSfnzzygetzyStatusRegzyCU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_statusreg_cuedce8fb3afbd16db31018057f7ad0656.tex}}}} + +\newcommand{\sailMIPSvalSetStatusRegCU}{\saildoclabelled{sailMIPSzzysetzyStatusRegzyCU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_statusreg_cu382e74466b55efdc144bb605d76fa627.tex}}}} + +\newcommand{\sailMIPSfnSetStatusRegCU}{\saildoclabelled{sailMIPSfnzzysetzyStatusRegzyCU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_statusreg_cu382e74466b55efdc144bb605d76fa627.tex}}}} + +\newcommand{\sailMIPSvalUpdateStatusRegCU}{\saildoclabelled{sailMIPSzzyupdatezyStatusRegzyCU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_statusreg_cud909b281d996784c876e6637f1435066.tex}}}} + +\newcommand{\sailMIPSfnUpdateStatusRegCU}{\saildoclabelled{sailMIPSfnzzyupdatezyStatusRegzyCU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_statusreg_cud909b281d996784c876e6637f1435066.tex}}}} + +\newcommand{\sailMIPSoverloadCCCCCCCupdateCU}{\saildoclabelled{sailMIPSoverloadCCCCCCCzupdatezyCU}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadCCCCCCCzupdate_cu412b8245b493377692f4da2838d4372d.tex}}}} + +\newcommand{\sailMIPSoverloadDDDDDDDModCU}{\saildoclabelled{sailMIPSoverloadDDDDDDDzzymodzyCU}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadDDDDDDDz_mod_cu360fcd6846ac7960b6ce1cf37eaac7f4.tex}}}} + +\newcommand{\sailMIPSvalGetStatusRegBEV}{\saildoclabelled{sailMIPSzzygetzyStatusRegzyBEV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_statusreg_bev76c45f173f7808e1e76c2d52dda65632.tex}}}} + +\newcommand{\sailMIPSfnGetStatusRegBEV}{\saildoclabelled{sailMIPSfnzzygetzyStatusRegzyBEV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_statusreg_bev76c45f173f7808e1e76c2d52dda65632.tex}}}} + +\newcommand{\sailMIPSvalSetStatusRegBEV}{\saildoclabelled{sailMIPSzzysetzyStatusRegzyBEV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_statusreg_bev924ce14fffca002f9543765ad1071fc1.tex}}}} + +\newcommand{\sailMIPSfnSetStatusRegBEV}{\saildoclabelled{sailMIPSfnzzysetzyStatusRegzyBEV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_statusreg_bev924ce14fffca002f9543765ad1071fc1.tex}}}} + +\newcommand{\sailMIPSvalUpdateStatusRegBEV}{\saildoclabelled{sailMIPSzzyupdatezyStatusRegzyBEV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_statusreg_bevf40892c6f5ac28088b99d5e42005036f.tex}}}} + +\newcommand{\sailMIPSfnUpdateStatusRegBEV}{\saildoclabelled{sailMIPSfnzzyupdatezyStatusRegzyBEV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_statusreg_bevf40892c6f5ac28088b99d5e42005036f.tex}}}} + +\newcommand{\sailMIPSoverloadEEEEEEEupdateBEV}{\saildoclabelled{sailMIPSoverloadEEEEEEEzupdatezyBEV}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadEEEEEEEzupdate_bevfd852bec522e475c2cd0b5fcd3214f94.tex}}}} + +\newcommand{\sailMIPSoverloadFFFFFFFModBEV}{\saildoclabelled{sailMIPSoverloadFFFFFFFzzymodzyBEV}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadFFFFFFFz_mod_bev3b9dcc4a8986f6731f7c23d6ed0a794e.tex}}}} + +\newcommand{\sailMIPSvalGetStatusRegIM}{\saildoclabelled{sailMIPSzzygetzyStatusRegzyIM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_statusreg_im66d47baebca79600073ab942220bcc99.tex}}}} + +\newcommand{\sailMIPSfnGetStatusRegIM}{\saildoclabelled{sailMIPSfnzzygetzyStatusRegzyIM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_statusreg_im66d47baebca79600073ab942220bcc99.tex}}}} + +\newcommand{\sailMIPSvalSetStatusRegIM}{\saildoclabelled{sailMIPSzzysetzyStatusRegzyIM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_statusreg_imfe5182ff0da7697ee27eb5e78eae3abc.tex}}}} + +\newcommand{\sailMIPSfnSetStatusRegIM}{\saildoclabelled{sailMIPSfnzzysetzyStatusRegzyIM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_statusreg_imfe5182ff0da7697ee27eb5e78eae3abc.tex}}}} + +\newcommand{\sailMIPSvalUpdateStatusRegIM}{\saildoclabelled{sailMIPSzzyupdatezyStatusRegzyIM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_statusreg_im62a68e4b88599a5038c9e71290e24f71.tex}}}} + +\newcommand{\sailMIPSfnUpdateStatusRegIM}{\saildoclabelled{sailMIPSfnzzyupdatezyStatusRegzyIM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_statusreg_im62a68e4b88599a5038c9e71290e24f71.tex}}}} + +\newcommand{\sailMIPSoverloadGGGGGGGupdateIM}{\saildoclabelled{sailMIPSoverloadGGGGGGGzupdatezyIM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadGGGGGGGzupdate_imb21cdd8456dfd134eec8cf19991410ad.tex}}}} + +\newcommand{\sailMIPSoverloadHHHHHHHModIM}{\saildoclabelled{sailMIPSoverloadHHHHHHHzzymodzyIM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadHHHHHHHz_mod_ima8a9d7a125ed51b1dae576dc7330719b.tex}}}} + +\newcommand{\sailMIPSvalGetStatusRegKX}{\saildoclabelled{sailMIPSzzygetzyStatusRegzyKX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_statusreg_kxc88611604b607976b47f459ed5655112.tex}}}} + +\newcommand{\sailMIPSfnGetStatusRegKX}{\saildoclabelled{sailMIPSfnzzygetzyStatusRegzyKX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_statusreg_kxc88611604b607976b47f459ed5655112.tex}}}} + +\newcommand{\sailMIPSvalSetStatusRegKX}{\saildoclabelled{sailMIPSzzysetzyStatusRegzyKX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_statusreg_kxca8ee85879aede01e75749335f0c00c9.tex}}}} + +\newcommand{\sailMIPSfnSetStatusRegKX}{\saildoclabelled{sailMIPSfnzzysetzyStatusRegzyKX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_statusreg_kxca8ee85879aede01e75749335f0c00c9.tex}}}} + +\newcommand{\sailMIPSvalUpdateStatusRegKX}{\saildoclabelled{sailMIPSzzyupdatezyStatusRegzyKX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_statusreg_kx6234e7159a5ec0749a63e66e635b26d6.tex}}}} + +\newcommand{\sailMIPSfnUpdateStatusRegKX}{\saildoclabelled{sailMIPSfnzzyupdatezyStatusRegzyKX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_statusreg_kx6234e7159a5ec0749a63e66e635b26d6.tex}}}} + +\newcommand{\sailMIPSoverloadIIIIIIIupdateKX}{\saildoclabelled{sailMIPSoverloadIIIIIIIzupdatezyKX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadIIIIIIIzupdate_kxed26c42ef95a8d8da42bca4da6bd4eab.tex}}}} + +\newcommand{\sailMIPSoverloadJJJJJJJModKX}{\saildoclabelled{sailMIPSoverloadJJJJJJJzzymodzyKX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadJJJJJJJz_mod_kx3c410091f5b2b941ccec438ead435325.tex}}}} + +\newcommand{\sailMIPSvalGetStatusRegSX}{\saildoclabelled{sailMIPSzzygetzyStatusRegzySX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_statusreg_sx3938519915fcbea54772a8fb5488c993.tex}}}} + +\newcommand{\sailMIPSfnGetStatusRegSX}{\saildoclabelled{sailMIPSfnzzygetzyStatusRegzySX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_statusreg_sx3938519915fcbea54772a8fb5488c993.tex}}}} + +\newcommand{\sailMIPSvalSetStatusRegSX}{\saildoclabelled{sailMIPSzzysetzyStatusRegzySX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_statusreg_sx7f79d23ff0ae6a043165750f8bb87713.tex}}}} + +\newcommand{\sailMIPSfnSetStatusRegSX}{\saildoclabelled{sailMIPSfnzzysetzyStatusRegzySX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_statusreg_sx7f79d23ff0ae6a043165750f8bb87713.tex}}}} + +\newcommand{\sailMIPSvalUpdateStatusRegSX}{\saildoclabelled{sailMIPSzzyupdatezyStatusRegzySX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_statusreg_sx78cadd5bf0c1cae59c3b60a27b83c481.tex}}}} + +\newcommand{\sailMIPSfnUpdateStatusRegSX}{\saildoclabelled{sailMIPSfnzzyupdatezyStatusRegzySX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_statusreg_sx78cadd5bf0c1cae59c3b60a27b83c481.tex}}}} + +\newcommand{\sailMIPSoverloadKKKKKKKupdateSX}{\saildoclabelled{sailMIPSoverloadKKKKKKKzupdatezySX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadKKKKKKKzupdate_sx5980678135ef3f9835076e9f123ea63b.tex}}}} + +\newcommand{\sailMIPSoverloadLLLLLLLModSX}{\saildoclabelled{sailMIPSoverloadLLLLLLLzzymodzySX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadLLLLLLLz_mod_sxba2453170d929599232993cb6cd9b3e8.tex}}}} + +\newcommand{\sailMIPSvalGetStatusRegUX}{\saildoclabelled{sailMIPSzzygetzyStatusRegzyUX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_statusreg_ux8cca4453438a4350fa4cd09d63ecb142.tex}}}} + +\newcommand{\sailMIPSfnGetStatusRegUX}{\saildoclabelled{sailMIPSfnzzygetzyStatusRegzyUX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_statusreg_ux8cca4453438a4350fa4cd09d63ecb142.tex}}}} + +\newcommand{\sailMIPSvalSetStatusRegUX}{\saildoclabelled{sailMIPSzzysetzyStatusRegzyUX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_statusreg_uxedb360d1d15e38d213f56b0eaa07f3a6.tex}}}} + +\newcommand{\sailMIPSfnSetStatusRegUX}{\saildoclabelled{sailMIPSfnzzysetzyStatusRegzyUX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_statusreg_uxedb360d1d15e38d213f56b0eaa07f3a6.tex}}}} + +\newcommand{\sailMIPSvalUpdateStatusRegUX}{\saildoclabelled{sailMIPSzzyupdatezyStatusRegzyUX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_statusreg_ux17bbf86e5756c6d01048f3d473eb1430.tex}}}} + +\newcommand{\sailMIPSfnUpdateStatusRegUX}{\saildoclabelled{sailMIPSfnzzyupdatezyStatusRegzyUX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_statusreg_ux17bbf86e5756c6d01048f3d473eb1430.tex}}}} + +\newcommand{\sailMIPSoverloadMMMMMMMupdateUX}{\saildoclabelled{sailMIPSoverloadMMMMMMMzupdatezyUX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadMMMMMMMzupdate_uxccea386a1abae1373e5e385a6585f028.tex}}}} + +\newcommand{\sailMIPSoverloadNNNNNNNModUX}{\saildoclabelled{sailMIPSoverloadNNNNNNNzzymodzyUX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadNNNNNNNz_mod_uxcb4904e2e9ec40177ef84b51b9cfd37a.tex}}}} + +\newcommand{\sailMIPSvalGetStatusRegKSU}{\saildoclabelled{sailMIPSzzygetzyStatusRegzyKSU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_statusreg_ksuf8d380201accc76c9427799218dced26.tex}}}} + +\newcommand{\sailMIPSfnGetStatusRegKSU}{\saildoclabelled{sailMIPSfnzzygetzyStatusRegzyKSU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_statusreg_ksuf8d380201accc76c9427799218dced26.tex}}}} + +\newcommand{\sailMIPSvalSetStatusRegKSU}{\saildoclabelled{sailMIPSzzysetzyStatusRegzyKSU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_statusreg_ksu10d20f93e7ee13723bb4b72cd7d3ea0a.tex}}}} + +\newcommand{\sailMIPSfnSetStatusRegKSU}{\saildoclabelled{sailMIPSfnzzysetzyStatusRegzyKSU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_statusreg_ksu10d20f93e7ee13723bb4b72cd7d3ea0a.tex}}}} + +\newcommand{\sailMIPSvalUpdateStatusRegKSU}{\saildoclabelled{sailMIPSzzyupdatezyStatusRegzyKSU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_statusreg_ksu27debd025189cf0d6d72638cd289acac.tex}}}} + +\newcommand{\sailMIPSfnUpdateStatusRegKSU}{\saildoclabelled{sailMIPSfnzzyupdatezyStatusRegzyKSU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_statusreg_ksu27debd025189cf0d6d72638cd289acac.tex}}}} + +\newcommand{\sailMIPSoverloadOOOOOOOupdateKSU}{\saildoclabelled{sailMIPSoverloadOOOOOOOzupdatezyKSU}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadOOOOOOOzupdate_ksu4fc7e63c0a91673b7b5e846838116134.tex}}}} + +\newcommand{\sailMIPSoverloadPPPPPPPModKSU}{\saildoclabelled{sailMIPSoverloadPPPPPPPzzymodzyKSU}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadPPPPPPPz_mod_ksu36b842dd8b87192857fac2c000672740.tex}}}} + +\newcommand{\sailMIPSvalGetStatusRegERL}{\saildoclabelled{sailMIPSzzygetzyStatusRegzyERL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_statusreg_erl047dd24d9a0767af7b83a9fcc72aa531.tex}}}} + +\newcommand{\sailMIPSfnGetStatusRegERL}{\saildoclabelled{sailMIPSfnzzygetzyStatusRegzyERL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_statusreg_erl047dd24d9a0767af7b83a9fcc72aa531.tex}}}} + +\newcommand{\sailMIPSvalSetStatusRegERL}{\saildoclabelled{sailMIPSzzysetzyStatusRegzyERL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_statusreg_erld7df28f36a304a50bf4b1ac7531ab82d.tex}}}} + +\newcommand{\sailMIPSfnSetStatusRegERL}{\saildoclabelled{sailMIPSfnzzysetzyStatusRegzyERL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_statusreg_erld7df28f36a304a50bf4b1ac7531ab82d.tex}}}} + +\newcommand{\sailMIPSvalUpdateStatusRegERL}{\saildoclabelled{sailMIPSzzyupdatezyStatusRegzyERL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_statusreg_erl22b56df06e65c8a9f44b830961367edf.tex}}}} + +\newcommand{\sailMIPSfnUpdateStatusRegERL}{\saildoclabelled{sailMIPSfnzzyupdatezyStatusRegzyERL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_statusreg_erl22b56df06e65c8a9f44b830961367edf.tex}}}} + +\newcommand{\sailMIPSoverloadQQQQQQQupdateERL}{\saildoclabelled{sailMIPSoverloadQQQQQQQzupdatezyERL}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadQQQQQQQzupdate_erl7a543a72f3f62df97cce89d42e9c61af.tex}}}} + +\newcommand{\sailMIPSoverloadRRRRRRRModERL}{\saildoclabelled{sailMIPSoverloadRRRRRRRzzymodzyERL}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadRRRRRRRz_mod_erlfbb04d75a1342f1a5085a19a27d8dc07.tex}}}} + +\newcommand{\sailMIPSvalGetStatusRegEXL}{\saildoclabelled{sailMIPSzzygetzyStatusRegzyEXL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_statusreg_exlf7067c47c7863a4f0a8be94eba05edef.tex}}}} + +\newcommand{\sailMIPSfnGetStatusRegEXL}{\saildoclabelled{sailMIPSfnzzygetzyStatusRegzyEXL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_statusreg_exlf7067c47c7863a4f0a8be94eba05edef.tex}}}} + +\newcommand{\sailMIPSvalSetStatusRegEXL}{\saildoclabelled{sailMIPSzzysetzyStatusRegzyEXL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_statusreg_exl9372beedcb66769ffb9a665777e1daaf.tex}}}} + +\newcommand{\sailMIPSfnSetStatusRegEXL}{\saildoclabelled{sailMIPSfnzzysetzyStatusRegzyEXL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_statusreg_exl9372beedcb66769ffb9a665777e1daaf.tex}}}} + +\newcommand{\sailMIPSvalUpdateStatusRegEXL}{\saildoclabelled{sailMIPSzzyupdatezyStatusRegzyEXL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_statusreg_exl680444bbc9dec1a34d9a0cf68ddde857.tex}}}} + +\newcommand{\sailMIPSfnUpdateStatusRegEXL}{\saildoclabelled{sailMIPSfnzzyupdatezyStatusRegzyEXL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_statusreg_exl680444bbc9dec1a34d9a0cf68ddde857.tex}}}} + +\newcommand{\sailMIPSoverloadSSSSSSSupdateEXL}{\saildoclabelled{sailMIPSoverloadSSSSSSSzupdatezyEXL}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadSSSSSSSzupdate_exl309dd848770b0a36e5ff6acac4ecce98.tex}}}} + +\newcommand{\sailMIPSoverloadTTTTTTTModEXL}{\saildoclabelled{sailMIPSoverloadTTTTTTTzzymodzyEXL}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadTTTTTTTz_mod_exl357e313bacd4edb774aa1ef0b156e134.tex}}}} + +\newcommand{\sailMIPSvalGetStatusRegIE}{\saildoclabelled{sailMIPSzzygetzyStatusRegzyIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_statusreg_ie87acfa5c96aee0f703b36a2c55d5a4de.tex}}}} + +\newcommand{\sailMIPSfnGetStatusRegIE}{\saildoclabelled{sailMIPSfnzzygetzyStatusRegzyIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_statusreg_ie87acfa5c96aee0f703b36a2c55d5a4de.tex}}}} + +\newcommand{\sailMIPSvalSetStatusRegIE}{\saildoclabelled{sailMIPSzzysetzyStatusRegzyIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_statusreg_ie25e69e4e6e9e37925cebd95113995258.tex}}}} + +\newcommand{\sailMIPSfnSetStatusRegIE}{\saildoclabelled{sailMIPSfnzzysetzyStatusRegzyIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_statusreg_ie25e69e4e6e9e37925cebd95113995258.tex}}}} + +\newcommand{\sailMIPSvalUpdateStatusRegIE}{\saildoclabelled{sailMIPSzzyupdatezyStatusRegzyIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_statusreg_ie8d238c97ac1693bad8b62c61215ea16b.tex}}}} + +\newcommand{\sailMIPSfnUpdateStatusRegIE}{\saildoclabelled{sailMIPSfnzzyupdatezyStatusRegzyIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_statusreg_ie8d238c97ac1693bad8b62c61215ea16b.tex}}}} + +\newcommand{\sailMIPSoverloadUUUUUUUupdateIE}{\saildoclabelled{sailMIPSoverloadUUUUUUUzupdatezyIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadUUUUUUUzupdate_ie315fd57324c5c7cae42210a2b9ce386e.tex}}}} + +\newcommand{\sailMIPSoverloadVVVVVVVModIE}{\saildoclabelled{sailMIPSoverloadVVVVVVVzzymodzyIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadVVVVVVVz_mod_ie0ede9f8235b89b5d2499f8cd2edeb1d6.tex}}}} + +\newcommand{\sailMIPSvalexecuteBranch}{\saildoclabelled{sailMIPSzexecutezybranch}{\saildocval{\lstinline{execute_branch} checks the given offset against the bounds of PCC and raises a capability length exception if it is out of bounds, otherwise a branch occurs in the normal manner for the architecture (on MIPS this implies a branch delay slot, so \lstinline`NextInBranchDelay` is set to true). + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzexecute_branch311b9f285cc52d66c683fa3ecaee2918.tex}}}} + +\newcommand{\sailMIPSvalexecuteBranchMips}{\saildoclabelled{sailMIPSzexecutezybranchzymips}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzexecute_branch_mipse0f90fc63954012c1f04b5f4841d0bbb.tex}}}} + +\newcommand{\sailMIPSfnexecuteBranchMips}{\saildoclabelled{sailMIPSfnzexecutezybranchzymips}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzexecute_branch_mipse0f90fc63954012c1f04b5f4841d0bbb.tex}}}} + +\newcommand{\sailMIPSvalNotWordVal}{\saildoclabelled{sailMIPSzNotWordVal}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznotwordvald5d5f9e6d06ea0a5cece40166646a4b4.tex}}}} + +\newcommand{\sailMIPSfnNotWordVal}{\saildoclabelled{sailMIPSfnzNotWordVal}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnznotwordvald5d5f9e6d06ea0a5cece40166646a4b4.tex}}}} + +\newcommand{\sailMIPSvalrGPR}{\saildoclabelled{sailMIPSzrGPR}{\saildocval{Reads the value of the given general purpose register as a 64-bit vector. Register zero is always zero. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzrgpr9bb3f998022d0674cf437905d0ab2e62.tex}}}} + +\newcommand{\sailMIPSfnrGPR}{\saildoclabelled{sailMIPSfnzrGPR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzrgpr9bb3f998022d0674cf437905d0ab2e62.tex}}}} + +\newcommand{\sailMIPSvalwGPR}{\saildoclabelled{sailMIPSzwGPR}{\saildocval{\lstinline{wGPR}(rd, v) writes the 64-bit value, \emph{v}, to the general purpose register \emph{rd}. Writes to register zero are ignored. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzwgpra4abc6baa21fcdee487f02c739ccf251.tex}}}} + +\newcommand{\sailMIPSfnwGPR}{\saildoclabelled{sailMIPSfnzwGPR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzwgpra4abc6baa21fcdee487f02c739ccf251.tex}}}} + +\newcommand{\sailMIPSvalMEMr}{\saildoclabelled{sailMIPSzMEMr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemr1e9f36dc3a59118d83f70ffa5fe2dd9e.tex}}}} + +\newcommand{\sailMIPSvalMEMrReserve}{\saildoclabelled{sailMIPSzMEMrzyreserve}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemr_reserved9c4ade13430d97ec20a414fa45cde6a.tex}}}} + +\newcommand{\sailMIPSvalMEMSync}{\saildoclabelled{sailMIPSzMEMzysync}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmem_synca6b7cb44064bf3e0998ab455e0247f73.tex}}}} + +\newcommand{\sailMIPSvalMEMea}{\saildoclabelled{sailMIPSzMEMea}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemea4fc0f7b33124f774de07c06ff98ca952.tex}}}} + +\newcommand{\sailMIPSvalMEMeaConditional}{\saildoclabelled{sailMIPSzMEMeazyconditional}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemea_conditionalac126f332517db0f6fcc745fef2e377d.tex}}}} + +\newcommand{\sailMIPSvalMEMval}{\saildoclabelled{sailMIPSzMEMval}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemvala388891903ef64c4b894bb339a9ee3eb.tex}}}} + +\newcommand{\sailMIPSvalMEMvalConditional}{\saildoclabelled{sailMIPSzMEMvalzyconditional}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemval_conditional81b75b657c8ad34bfa8410067d19f50e.tex}}}} + +\newcommand{\sailMIPSvalskipEamem}{\saildoclabelled{sailMIPSzskipzyeamem}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzskip_eamem49a4d980d609bd796bfdb904e8da6711.tex}}}} + +\newcommand{\sailMIPSvalskipBarr}{\saildoclabelled{sailMIPSzskipzybarr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzskip_barrca673f4460442e7803a2c93bd2aef700.tex}}}} + +\newcommand{\sailMIPSvalskipWreg}{\saildoclabelled{sailMIPSzskipzywreg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzskip_wregb2a3498732e32cc0df842c55bfcee6e1.tex}}}} + +\newcommand{\sailMIPSvalskipRreg}{\saildoclabelled{sailMIPSzskipzyrreg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzskip_rreg6c7d871275e33b7ca21079a068ab8ac7.tex}}}} + +\newcommand{\sailMIPSvalskipWmvt}{\saildoclabelled{sailMIPSzskipzywmvt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzskip_wmvtf5881f8ed4b4116848ad7bdbc67bd918.tex}}}} + +\newcommand{\sailMIPSvalskipRmemt}{\saildoclabelled{sailMIPSzskipzyrmemt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzskip_rmemt7f62986f7ef50679aaa016cb24b25d65.tex}}}} + +\newcommand{\sailMIPSvalskipEscape}{\saildoclabelled{sailMIPSzskipzyescape}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzskip_escape40337081b9eda6abe558d971128fc98c.tex}}}} + +\newcommand{\sailMIPSfnMEMr}{\saildoclabelled{sailMIPSfnzMEMr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemr1e9f36dc3a59118d83f70ffa5fe2dd9e.tex}}}} + +\newcommand{\sailMIPSfnMEMrReserve}{\saildoclabelled{sailMIPSfnzMEMrzyreserve}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemr_reserved9c4ade13430d97ec20a414fa45cde6a.tex}}}} + +\newcommand{\sailMIPSfnMEMSync}{\saildoclabelled{sailMIPSfnzMEMzysync}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmem_synca6b7cb44064bf3e0998ab455e0247f73.tex}}}} + +\newcommand{\sailMIPSfnMEMea}{\saildoclabelled{sailMIPSfnzMEMea}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemea4fc0f7b33124f774de07c06ff98ca952.tex}}}} + +\newcommand{\sailMIPSfnMEMeaConditional}{\saildoclabelled{sailMIPSfnzMEMeazyconditional}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemea_conditionalac126f332517db0f6fcc745fef2e377d.tex}}}} + +\newcommand{\sailMIPSfnMEMval}{\saildoclabelled{sailMIPSfnzMEMval}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemvala388891903ef64c4b894bb339a9ee3eb.tex}}}} + +\newcommand{\sailMIPSfnMEMvalConditional}{\saildoclabelled{sailMIPSfnzMEMvalzyconditional}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemval_conditional81b75b657c8ad34bfa8410067d19f50e.tex}}}} + +\newcommand{\sailMIPStypeException}{\saildoclabelled{sailMIPStypezException}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezexception6ac3a0452a7a8420f2be999d05ad1183.tex}}}} + +\newcommand{\sailMIPSvalExceptionOfNum}{\saildoclabelled{sailMIPSzExceptionzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzexception_of_num7e2e38eb3f1c380a425392cb53ad450c.tex}}}} + +\newcommand{\sailMIPSfnExceptionOfNum}{\saildoclabelled{sailMIPSfnzExceptionzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzexception_of_num7e2e38eb3f1c380a425392cb53ad450c.tex}}}} + +\newcommand{\sailMIPSvalnumOfException}{\saildoclabelled{sailMIPSznumzyofzyException}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznum_of_exception9e1669909ce7707290888338ffbcc8f8.tex}}}} + +\newcommand{\sailMIPSfnnumOfException}{\saildoclabelled{sailMIPSfnznumzyofzyException}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnznum_of_exception9e1669909ce7707290888338ffbcc8f8.tex}}}} + +\newcommand{\sailMIPSvalExceptionCode}{\saildoclabelled{sailMIPSzExceptionCode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzexceptioncodef7807000fba49ff7759f4a4cbdf3d902.tex}}}} + +\newcommand{\sailMIPSfnExceptionCode}{\saildoclabelled{sailMIPSfnzExceptionCode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzexceptioncodef7807000fba49ff7759f4a4cbdf3d902.tex}}}} + +\newcommand{\sailMIPSvalstringOfException}{\saildoclabelled{sailMIPSzstringzyofzyexception}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstring_of_exception7734103b8f1c3a7c884e4dea77d7cf9d.tex}}}} + +\newcommand{\sailMIPSfnstringOfException}{\saildoclabelled{sailMIPSfnzstringzyofzyexception}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstring_of_exception7734103b8f1c3a7c884e4dea77d7cf9d.tex}}}} + +\newcommand{\sailMIPSvaltraceException}{\saildoclabelled{sailMIPSztraceException}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valztraceexceptiond1f5e2367606477eb2b33940325e3e87.tex}}}} + +\newcommand{\sailMIPSfntraceException}{\saildoclabelled{sailMIPSfnztraceException}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnztraceexceptiond1f5e2367606477eb2b33940325e3e87.tex}}}} + +\newcommand{\sailMIPSvalexceptionVectorOffset}{\saildoclabelled{sailMIPSzexceptionVectorOffset}{\saildocval{Choose an exception vector offset based on current state of processor +and exception type. Some are not supported \saildocabbrev{e.g.} Reset. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzexceptionvectoroffset5c95f15ec5e635d417858fb601d0a766.tex}}}} + +\newcommand{\sailMIPSfnexceptionVectorOffset}{\saildoclabelled{sailMIPSfnzexceptionVectorOffset}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzexceptionvectoroffset5c95f15ec5e635d417858fb601d0a766.tex}}}} + +\newcommand{\sailMIPSvalexceptionVectorBase}{\saildoclabelled{sailMIPSzexceptionVectorBase}{\saildocval{Choose appropariate exception vector base for current processor state. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzexceptionvectorbase2dabb9cbc70df89c064ff6ef9c281b30.tex}}}} + +\newcommand{\sailMIPSfnexceptionVectorBase}{\saildoclabelled{sailMIPSfnzexceptionVectorBase}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzexceptionvectorbase2dabb9cbc70df89c064ff6ef9c281b30.tex}}}} + +\newcommand{\sailMIPSvalupdateBadInstr}{\saildoclabelled{sailMIPSzupdateBadInstr}{\saildocval{Update CP0BadInstr and CP0BadInstrP for exception. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzupdatebadinstr950852e9ede642484051c5622ba3c67c.tex}}}} + +\newcommand{\sailMIPSfnupdateBadInstr}{\saildoclabelled{sailMIPSfnzupdateBadInstr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzupdatebadinstr950852e9ede642484051c5622ba3c67c.tex}}}} + +\newcommand{\sailMIPSvalSignalException}{\saildoclabelled{sailMIPSzSignalException}{\saildocval{Causes the processor to raise the given exception in the usual manner defined by the processor architecture (as modified for CHERI). + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzsignalexception586f3a4c7da76085e25c98aff442160c.tex}}}} + +\newcommand{\sailMIPSvalSignalExceptionBadAddr}{\saildoclabelled{sailMIPSzSignalExceptionBadAddr}{\saildocval{causes the processor to raise the given exception as per \hyperref[sailMIPSzSignalException]{\lstinline{SignalException}}, but with an associated bad address (on MIPS this is written to the BadVAddr register to aid with exception handling). + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzsignalexceptionbadaddr6cdef872a446a09f2a94b2675a181fe8.tex}}}} + +\newcommand{\sailMIPSfnSignalExceptionBadAddr}{\saildoclabelled{sailMIPSfnzSignalExceptionBadAddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzsignalexceptionbadaddr6cdef872a446a09f2a94b2675a181fe8.tex}}}} + +\newcommand{\sailMIPSvalSignalExceptionTLB}{\saildoclabelled{sailMIPSzSignalExceptionTLB}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsignalexceptiontlbddf65d69af94bbb390cc24d557f99883.tex}}}} + +\newcommand{\sailMIPSfnSignalExceptionTLB}{\saildoclabelled{sailMIPSfnzSignalExceptionTLB}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzsignalexceptiontlbddf65d69af94bbb390cc24d557f99883.tex}}}} + +\newcommand{\sailMIPStypeMemAccessType}{\saildoclabelled{sailMIPStypezMemAccessType}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezmemaccesstype6fcf71ced82759af01458f3bc64be72a.tex}}}} + +\newcommand{\sailMIPSvalMemAccessTypeOfNum}{\saildoclabelled{sailMIPSzMemAccessTypezyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemaccesstype_of_nume9bc7b384750bfb019a26074bf441f44.tex}}}} + +\newcommand{\sailMIPSfnMemAccessTypeOfNum}{\saildoclabelled{sailMIPSfnzMemAccessTypezyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemaccesstype_of_nume9bc7b384750bfb019a26074bf441f44.tex}}}} + +\newcommand{\sailMIPSvalnumOfMemAccessType}{\saildoclabelled{sailMIPSznumzyofzyMemAccessType}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznum_of_memaccesstype1f8a90d42ae8b06c64b096b6b6eb7e6b.tex}}}} + +\newcommand{\sailMIPSfnnumOfMemAccessType}{\saildoclabelled{sailMIPSfnznumzyofzyMemAccessType}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnznum_of_memaccesstype1f8a90d42ae8b06c64b096b6b6eb7e6b.tex}}}} + +\newcommand{\sailMIPStypeMemAccessCapRestriction}{\saildoclabelled{sailMIPStypezMemAccessCapRestriction}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezmemaccesscaprestriction340c8f66dcf0e8588b00a8db8a47687d.tex}}}} + +\newcommand{\sailMIPSvalMemAccessCapRestrictionOfNum}{\saildoclabelled{sailMIPSzMemAccessCapRestrictionzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemaccesscaprestriction_of_num40cccde77213084744ee3677231b6055.tex}}}} + +\newcommand{\sailMIPSfnMemAccessCapRestrictionOfNum}{\saildoclabelled{sailMIPSfnzMemAccessCapRestrictionzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemaccesscaprestriction_of_num40cccde77213084744ee3677231b6055.tex}}}} + +\newcommand{\sailMIPSvalnumOfMemAccessCapRestriction}{\saildoclabelled{sailMIPSznumzyofzyMemAccessCapRestriction}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznum_of_memaccesscaprestriction4f02267c2f3610530a623ffeb2b0f8f5.tex}}}} + +\newcommand{\sailMIPSfnnumOfMemAccessCapRestriction}{\saildoclabelled{sailMIPSfnznumzyofzyMemAccessCapRestriction}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnznum_of_memaccesscaprestriction4f02267c2f3610530a623ffeb2b0f8f5.tex}}}} + +\newcommand{\sailMIPStypeAccessLevel}{\saildoclabelled{sailMIPStypezAccessLevel}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezaccesslevel34c3ad2092ac418806acf43082692dd8.tex}}}} + +\newcommand{\sailMIPSvalAccessLevelOfNum}{\saildoclabelled{sailMIPSzAccessLevelzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzaccesslevel_of_num43666996140cb5f36631de9d7d4748b1.tex}}}} + +\newcommand{\sailMIPSfnAccessLevelOfNum}{\saildoclabelled{sailMIPSfnzAccessLevelzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzaccesslevel_of_num43666996140cb5f36631de9d7d4748b1.tex}}}} + +\newcommand{\sailMIPSvalnumOfAccessLevel}{\saildoclabelled{sailMIPSznumzyofzyAccessLevel}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznum_of_accessleveld0fc11b6a25cf84b4b09fd5eb5a37980.tex}}}} + +\newcommand{\sailMIPSfnnumOfAccessLevel}{\saildoclabelled{sailMIPSfnznumzyofzyAccessLevel}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnznum_of_accessleveld0fc11b6a25cf84b4b09fd5eb5a37980.tex}}}} + +\newcommand{\sailMIPSvalintOfAccessLevel}{\saildoclabelled{sailMIPSzintzyofzyAccessLevel}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzint_of_accessleveld511598513a474f4d799d64651770863.tex}}}} + +\newcommand{\sailMIPSfnintOfAccessLevel}{\saildoclabelled{sailMIPSfnzintzyofzyAccessLevel}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzint_of_accessleveld511598513a474f4d799d64651770863.tex}}}} + +\newcommand{\sailMIPSvalgrantsAccess}{\saildoclabelled{sailMIPSzgrantsAccess}{\saildocval{Returns whether the first AccessLevel is sufficient to grant access at the second, required, access level. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzgrantsaccess1c25b864354b7175e1d8d7ec4e5e27b6.tex}}}} + +\newcommand{\sailMIPSfngrantsAccess}{\saildoclabelled{sailMIPSfnzgrantsAccess}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzgrantsaccess1c25b864354b7175e1d8d7ec4e5e27b6.tex}}}} + +\newcommand{\sailMIPSvalgetAccessLevel}{\saildoclabelled{sailMIPSzgetAccessLevel}{\saildocval{Returns the current effective access level (User, Supervisor or Kernel) determined by accessing the relevant parts of the MIPS status register. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzgetaccesslevel40127125b18eb6336d48aa4638317128.tex}}}} + +\newcommand{\sailMIPSfngetAccessLevel}{\saildoclabelled{sailMIPSfnzgetAccessLevel}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzgetaccesslevel40127125b18eb6336d48aa4638317128.tex}}}} + +\newcommand{\sailMIPSvalcheckCPZeroAccessHook}{\saildoclabelled{sailMIPSzcheckCP0AccessHook}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcheckcp0accesshook3dae675d70bdcddbd36c77cdbf07a44f.tex}}}} + +\newcommand{\sailMIPSvalcheckCPZeroAccess}{\saildoclabelled{sailMIPSzcheckCP0Access}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcheckcp0accesse535c637cac3118020cdac54870326df.tex}}}} + +\newcommand{\sailMIPSfncheckCPZeroAccess}{\saildoclabelled{sailMIPSfnzcheckCP0Access}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcheckcp0accesse535c637cac3118020cdac54870326df.tex}}}} + +\newcommand{\sailMIPSvalincrementCPZeroCount}{\saildoclabelled{sailMIPSzincrementCP0Count}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzincrementcp0count9449093588dc2365295e37dd55af742d.tex}}}} + +\newcommand{\sailMIPSfnincrementCPZeroCount}{\saildoclabelled{sailMIPSfnzincrementCP0Count}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzincrementcp0count9449093588dc2365295e37dd55af742d.tex}}}} + +\newcommand{\sailMIPStyperegno}{\saildoclabelled{sailMIPStypezregno}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezregno1c2cd9b00ff5d991528ec5d711c3ace5.tex}}}} + +\newcommand{\sailMIPStypeIntRegEnc}{\saildoclabelled{sailMIPStypezIntRegEnc}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezintregencbffd4c4bbb18a759cfd88ad299ff3a72.tex}}}} + +\newcommand{\sailMIPStypeimmOneSix}{\saildoclabelled{sailMIPStypezimm16}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezimm16dc4af7d5aca495b5bf0191384a060883.tex}}}} + +\newcommand{\sailMIPSvalstrReg}{\saildoclabelled{sailMIPSzstrReg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrregedcb07cf94fecef4256c866403497f4d.tex}}}} + +\newcommand{\sailMIPSfnstrReg}{\saildoclabelled{sailMIPSfnzstrReg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrregedcb07cf94fecef4256c866403497f4d.tex}}}} + +\newcommand{\sailMIPSvalstrRRRArgs}{\saildoclabelled{sailMIPSzstrRRRArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrrrrargsfab462065fa0ad4bda2870b02f212fd9.tex}}}} + +\newcommand{\sailMIPSfnstrRRRArgs}{\saildoclabelled{sailMIPSfnzstrRRRArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrrrrargsfab462065fa0ad4bda2870b02f212fd9.tex}}}} + +\newcommand{\sailMIPSvalstrRRIArgs}{\saildoclabelled{sailMIPSzstrRRIArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrrriargs4a7c2ee7b410ff0bb51f74553cdca297.tex}}}} + +\newcommand{\sailMIPSfnstrRRIArgs}{\saildoclabelled{sailMIPSfnzstrRRIArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrrriargs4a7c2ee7b410ff0bb51f74553cdca297.tex}}}} + +\newcommand{\sailMIPSvalstrRRIUArgs}{\saildoclabelled{sailMIPSzstrRRIUArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrrriuargs3f59ed041a358c4238ca651c777a80e7.tex}}}} + +\newcommand{\sailMIPSfnstrRRIUArgs}{\saildoclabelled{sailMIPSfnzstrRRIUArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrrriuargs3f59ed041a358c4238ca651c777a80e7.tex}}}} + +\newcommand{\sailMIPSvalstrRIArgs}{\saildoclabelled{sailMIPSzstrRIArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrriargsf5ce4d067df93e7be3e1beacd5b4d9a7.tex}}}} + +\newcommand{\sailMIPSfnstrRIArgs}{\saildoclabelled{sailMIPSfnzstrRIArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrriargsf5ce4d067df93e7be3e1beacd5b4d9a7.tex}}}} + +\newcommand{\sailMIPSvalstrMemArgs}{\saildoclabelled{sailMIPSzstrMemArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrmemargs353ff7043a1935f05717327694c74036.tex}}}} + +\newcommand{\sailMIPSfnstrMemArgs}{\saildoclabelled{sailMIPSfnzstrMemArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrmemargs353ff7043a1935f05717327694c74036.tex}}}} + +\newcommand{\sailMIPStypedecodeFailure}{\saildoclabelled{sailMIPStypezdecodezyfailure}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezdecode_failure1d4a2f8a2ba670570ead3264488ec7db.tex}}}} + +\newcommand{\sailMIPSvaldecodeFailureOfNum}{\saildoclabelled{sailMIPSzdecodezyfailurezyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzdecode_failure_of_numcefdc025bb5d8d74839d8f9f65058d32.tex}}}} + +\newcommand{\sailMIPSfndecodeFailureOfNum}{\saildoclabelled{sailMIPSfnzdecodezyfailurezyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzdecode_failure_of_numcefdc025bb5d8d74839d8f9f65058d32.tex}}}} + +\newcommand{\sailMIPSvalnumOfDecodeFailure}{\saildoclabelled{sailMIPSznumzyofzydecodezyfailure}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznum_of_decode_failure25ef6d99c7154f39444aafcc89394acd.tex}}}} + +\newcommand{\sailMIPSfnnumOfDecodeFailure}{\saildoclabelled{sailMIPSfnznumzyofzydecodezyfailure}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnznum_of_decode_failure25ef6d99c7154f39444aafcc89394acd.tex}}}} + +\newcommand{\sailMIPStypeComparison}{\saildoclabelled{sailMIPStypezComparison}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezcomparisoncd0f719b5c6f4fc29b93a9e3721bf4a5.tex}}}} + +\newcommand{\sailMIPSvalComparisonOfNum}{\saildoclabelled{sailMIPSzComparisonzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcomparison_of_num2a18f2d9a572dd906b510535c629d4f0.tex}}}} + +\newcommand{\sailMIPSfnComparisonOfNum}{\saildoclabelled{sailMIPSfnzComparisonzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcomparison_of_num2a18f2d9a572dd906b510535c629d4f0.tex}}}} + +\newcommand{\sailMIPSvalnumOfComparison}{\saildoclabelled{sailMIPSznumzyofzyComparison}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznum_of_comparisonacdefcc370a45e5aec6df49e5b5d9b12.tex}}}} + +\newcommand{\sailMIPSfnnumOfComparison}{\saildoclabelled{sailMIPSfnznumzyofzyComparison}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnznum_of_comparisonacdefcc370a45e5aec6df49e5b5d9b12.tex}}}} + +\newcommand{\sailMIPSvalstrCmp}{\saildoclabelled{sailMIPSzstrCmp}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrcmp377172000af45c28fe84b78c43e6af4d.tex}}}} + +\newcommand{\sailMIPSfnstrCmp}{\saildoclabelled{sailMIPSfnzstrCmp}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrcmp377172000af45c28fe84b78c43e6af4d.tex}}}} + +\newcommand{\sailMIPSvalcompare}{\saildoclabelled{sailMIPSzcompare}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcomparee9b34cffaaa4473cdff7ece5c1a05374.tex}}}} + +\newcommand{\sailMIPSfncompare}{\saildoclabelled{sailMIPSfnzcompare}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcomparee9b34cffaaa4473cdff7ece5c1a05374.tex}}}} + +\newcommand{\sailMIPStypeWordType}{\saildoclabelled{sailMIPStypezWordType}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezwordtype6cf92a33f38f7f38030a409847a13ce4.tex}}}} + +\newcommand{\sailMIPSvalWordTypeOfNum}{\saildoclabelled{sailMIPSzWordTypezyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzwordtype_of_num3fb8b8a30f6fb7e01768c7e63da4fa79.tex}}}} + +\newcommand{\sailMIPSfnWordTypeOfNum}{\saildoclabelled{sailMIPSfnzWordTypezyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzwordtype_of_num3fb8b8a30f6fb7e01768c7e63da4fa79.tex}}}} + +\newcommand{\sailMIPSvalnumOfWordType}{\saildoclabelled{sailMIPSznumzyofzyWordType}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznum_of_wordtypef0e59bab28a4b7f5e903a6c47ab403a5.tex}}}} + +\newcommand{\sailMIPSfnnumOfWordType}{\saildoclabelled{sailMIPSfnznumzyofzyWordType}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnznum_of_wordtypef0e59bab28a4b7f5e903a6c47ab403a5.tex}}}} + +\newcommand{\sailMIPStypeWordTypeUnaligned}{\saildoclabelled{sailMIPStypezWordTypeUnaligned}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezwordtypeunalignedeae3a0458f9fb4fc24aa62dc6e172d35.tex}}}} + +\newcommand{\sailMIPSvalWordTypeUnalignedOfNum}{\saildoclabelled{sailMIPSzWordTypeUnalignedzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzwordtypeunaligned_of_num9534254c2a95ab15ea143c0eb1f767d5.tex}}}} + +\newcommand{\sailMIPSfnWordTypeUnalignedOfNum}{\saildoclabelled{sailMIPSfnzWordTypeUnalignedzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzwordtypeunaligned_of_num9534254c2a95ab15ea143c0eb1f767d5.tex}}}} + +\newcommand{\sailMIPSvalnumOfWordTypeUnaligned}{\saildoclabelled{sailMIPSznumzyofzyWordTypeUnaligned}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznum_of_wordtypeunaligned443855cd2b4cc93af964642e98c1b412.tex}}}} + +\newcommand{\sailMIPSfnnumOfWordTypeUnaligned}{\saildoclabelled{sailMIPSfnznumzyofzyWordTypeUnaligned}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnznum_of_wordtypeunaligned443855cd2b4cc93af964642e98c1b412.tex}}}} + +\newcommand{\sailMIPSvalstrWordType}{\saildoclabelled{sailMIPSzstrWordType}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrwordtype0dceaa7680ceade7afd7f75be57ac461.tex}}}} + +\newcommand{\sailMIPSfnstrWordType}{\saildoclabelled{sailMIPSfnzstrWordType}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrwordtype0dceaa7680ceade7afd7f75be57ac461.tex}}}} + +\newcommand{\sailMIPSvalunalignedBytesTouched}{\saildoclabelled{sailMIPSzunalignedBytesTouched}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzunalignedbytestouched30e9b9e5c4f2d5085ce71a02d1964f0c.tex}}}} + +\newcommand{\sailMIPSfnunalignedBytesTouched}{\saildoclabelled{sailMIPSfnzunalignedBytesTouched}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzunalignedbytestouched30e9b9e5c4f2d5085ce71a02d1964f0c.tex}}}} + +\newcommand{\sailMIPSvalwordWidthBytes}{\saildoclabelled{sailMIPSzwordWidthBytes}{\saildocval{ Returns the width of the given WordType (byte, half, word, double) in bytes. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzwordwidthbyteseabb026e3f94d82320b5d4a77ee9fcc4.tex}}}} + +\newcommand{\sailMIPSfnwordWidthBytes}{\saildoclabelled{sailMIPSfnzwordWidthBytes}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzwordwidthbyteseabb026e3f94d82320b5d4a77ee9fcc4.tex}}}} + +\newcommand{\sailMIPSvalisAddressAligned}{\saildoclabelled{sailMIPSzisAddressAligned}{\saildocval{ \lstinline{isAddressAligned}\lstinline`(address, wordtype)` returns whether \lstinline`address` is naturally aligned for the given \lstinline`wordtype`. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzisaddressaligned9b5d757d64e55546134bbc396b0d9129.tex}}}} + +\newcommand{\sailMIPSfnisAddressAligned}{\saildoclabelled{sailMIPSfnzisAddressAligned}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzisaddressaligned9b5d757d64e55546134bbc396b0d9129.tex}}}} + +\newcommand{\sailMIPSvalreverseEndianness}{\saildoclabelled{sailMIPSzreversezyendianness}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzreverse_endianness67387713ef62b5e52d27f28369230428.tex}}}} + +\newcommand{\sailMIPSvalextendLoad}{\saildoclabelled{sailMIPSzextendLoad}{\saildocval{ \lstinline{extendLoad}\lstinline`(val, signed)` extends \lstinline`val` to 64-bits in either sign extended or zero extended fashion according to \lstinline`signed`. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzextendload386a20971b3dbdcd10ee9b8b44e2c2f7.tex}}}} + +\newcommand{\sailMIPSfnextendLoad}{\saildoclabelled{sailMIPSfnzextendLoad}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzextendload386a20971b3dbdcd10ee9b8b44e2c2f7.tex}}}} + +\newcommand{\sailMIPSvalMEMrWrapper}{\saildoclabelled{sailMIPSzMEMrzywrapper}{\saildocval{\lstinline{MEMr_wrapper}\lstinline`(addr, size)` reads a vector of \lstinline`size` bytes of memory from physical address \lstinline`addr` (big-endian byte order on CHERI-MIPS). + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemr_wrapper75f1a468d1dba11a7720be7f66d3c8e2.tex}}}} + +\newcommand{\sailMIPSfnMEMrWrapper}{\saildoclabelled{sailMIPSfnzMEMrzywrapper}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemr_wrapper75f1a468d1dba11a7720be7f66d3c8e2.tex}}}} + +\newcommand{\sailMIPSvalMEMrReserveWrapper}{\saildoclabelled{sailMIPSzMEMrzyreservezywrapper}{\saildocval{is the same as \hyperref[sailMIPSzMEMrzywrapper]{\lstinline{MEMr_wrapper}} except that the read is marked as part of a load linked / store conditional pair. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemr_reserve_wrapper69fc87b2d98dbfe1febc5c11d3d298c6.tex}}}} + +\newcommand{\sailMIPSfnMEMrReserveWrapper}{\saildoclabelled{sailMIPSfnzMEMrzyreservezywrapper}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemr_reserve_wrapper69fc87b2d98dbfe1febc5c11d3d298c6.tex}}}} + +\newcommand{\sailMIPSvalinitCpZeroState}{\saildoclabelled{sailMIPSzinitzycp0zystate}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzinit_cp0_state82b3d81150b612dca26217241b94da87.tex}}}} + +\newcommand{\sailMIPSfninitCpZeroState}{\saildoclabelled{sailMIPSfnzinitzycp0zystate}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzinit_cp0_state82b3d81150b612dca26217241b94da87.tex}}}} + +\newcommand{\sailMIPSvalinitCpTwoState}{\saildoclabelled{sailMIPSzinitzycp2zystate}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzinit_cp2_state7056c424b16f2ae2f851216ae32427b0.tex}}}} + +\newcommand{\sailMIPSvalcpTwoNextPc}{\saildoclabelled{sailMIPSzcp2zynextzypc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcp2_next_pc33094c95220fdc4b0a67b83ac21fc047.tex}}}} + +\newcommand{\sailMIPSvaldumpCpTwoState}{\saildoclabelled{sailMIPSzdumpzycp2zystate}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzdump_cp2_statee501e37d7b82b621f6ff3cd1f225d5f1.tex}}}} + +\newcommand{\sailMIPSvaltlbEntryMatch}{\saildoclabelled{sailMIPSztlbEntryMatch}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valztlbentrymatch022ae8f81d6f9221e858534a26d34f7f.tex}}}} + +\newcommand{\sailMIPSfntlbEntryMatch}{\saildoclabelled{sailMIPSfnztlbEntryMatch}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnztlbentrymatch022ae8f81d6f9221e858534a26d34f7f.tex}}}} + +\newcommand{\sailMIPSvaltlbSearch}{\saildoclabelled{sailMIPSztlbSearch}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valztlbsearchccbd0fc555e67dbea1dd6e8748394f51.tex}}}} + +\newcommand{\sailMIPSfntlbSearch}{\saildoclabelled{sailMIPSfnztlbSearch}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnztlbsearchccbd0fc555e67dbea1dd6e8748394f51.tex}}}} + +\newcommand{\sailMIPSvalMIPSSegmentOf}{\saildoclabelled{sailMIPSzMIPSSegmentOf}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmipssegmentof3db6164251b0305648a8f4d8f750299e.tex}}}} + +\newcommand{\sailMIPSfnMIPSSegmentOf}{\saildoclabelled{sailMIPSfnzMIPSSegmentOf}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmipssegmentof3db6164251b0305648a8f4d8f750299e.tex}}}} + +\newcommand{\sailMIPSvalTLBTranslateTwo}{\saildoclabelled{sailMIPSzTLBTranslate2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valztlbtranslate2472aa8aca18a66cca2beeaa89cbec740.tex}}}} + +\newcommand{\sailMIPSfnTLBTranslateTwo}{\saildoclabelled{sailMIPSfnzTLBTranslate2}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnztlbtranslate2472aa8aca18a66cca2beeaa89cbec740.tex}}}} + +\newcommand{\sailMIPSvalTLBTranslateC}{\saildoclabelled{sailMIPSzTLBTranslateC}{\saildocval{\lstinline{TLBTranslateC} is the same as \hyperref[sailMIPSzTLBTranslate]{\lstinline{TLBTranslate}} except that it also returns any +constraints on tagged capability operations. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valztlbtranslateccd99b29205e9558b4443d89bd7791f84.tex}}}} + +\newcommand{\sailMIPSfnTLBTranslateC}{\saildoclabelled{sailMIPSfnzTLBTranslateC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnztlbtranslateccd99b29205e9558b4443d89bd7791f84.tex}}}} + +\newcommand{\sailMIPSvalTLBTranslate}{\saildoclabelled{sailMIPSzTLBTranslate}{\saildocval{\lstinline{TLBTranslate}\lstinline`(addr, acces_type)` translates the virtual address, \lstinline`addr`, to a physical address assuming the given \lstinline`access_type` (load or store). If the TLB lookup fails an ISA exception is raised. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valztlbtranslateea36ded227d6adddf8c6c2ae662895be.tex}}}} + +\newcommand{\sailMIPSfnTLBTranslate}{\saildoclabelled{sailMIPSfnzTLBTranslate}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnztlbtranslateea36ded227d6adddf8c6c2ae662895be.tex}}}} + +\newcommand{\sailMIPStypeCapLen}{\saildoclabelled{sailMIPStypezCapLen}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezcaplenf6618af706b03f95ca9741cffae7687d.tex}}}} + +\newcommand{\sailMIPStypeuintSixFour}{\saildoclabelled{sailMIPStypezuint64}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezuint6439284932ed72321603dafa0ae33d84aa.tex}}}} + +\newcommand{\sailMIPStypeCPtrCmpOp}{\saildoclabelled{sailMIPStypezCPtrCmpOp}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezcptrcmpopb3b1dde403387930c5431415f0c993e5.tex}}}} + +\newcommand{\sailMIPSvalCPtrCmpOpOfNum}{\saildoclabelled{sailMIPSzCPtrCmpOpzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex}}}} + +\newcommand{\sailMIPSfnCPtrCmpOpOfNum}{\saildoclabelled{sailMIPSfnzCPtrCmpOpzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex}}}} + +\newcommand{\sailMIPSvalnumOfCPtrCmpOp}{\saildoclabelled{sailMIPSznumzyofzyCPtrCmpOp}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex}}}} + +\newcommand{\sailMIPSfnnumOfCPtrCmpOp}{\saildoclabelled{sailMIPSfnznumzyofzyCPtrCmpOp}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex}}}} + +\newcommand{\sailMIPStypeClearRegSet}{\saildoclabelled{sailMIPStypezClearRegSet}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezclearregsete5eab3e282a2a338ddb8311b5edbb561.tex}}}} + +\newcommand{\sailMIPSvalClearRegSetOfNum}{\saildoclabelled{sailMIPSzClearRegSetzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex}}}} + +\newcommand{\sailMIPSfnClearRegSetOfNum}{\saildoclabelled{sailMIPSfnzClearRegSetzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex}}}} + +\newcommand{\sailMIPSvalnumOfClearRegSet}{\saildoclabelled{sailMIPSznumzyofzyClearRegSet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznum_of_clearregset49e10f200544574f819f7f660071e10b.tex}}}} + +\newcommand{\sailMIPSfnnumOfClearRegSet}{\saildoclabelled{sailMIPSfnznumzyofzyClearRegSet}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnznum_of_clearregset49e10f200544574f819f7f660071e10b.tex}}}} + +\newcommand{\sailMIPStypenumFlagsT}{\saildoclabelled{sailMIPStypeznumzyflagszyt}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typeznum_flags_t473b430862704b86668aeb0b48744535.tex}}}} + +\newcommand{\sailMIPStypeCFlags}{\saildoclabelled{sailMIPStypezCFlags}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezcflags0d98257ead736171e7ed77965597f4f0.tex}}}} + +\newcommand{\sailMIPStypeCapBits}{\saildoclabelled{sailMIPStypezCapBits}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezcapbits32830b87cefa69a0cdb78ef00d25b781.tex}}}} + +\newcommand{\sailMIPStypeCapability}{\saildoclabelled{sailMIPStypezCapability}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezcapability5646515621fe4c3bb7fe8874d1909f0e.tex}}}} + +\newcommand{\sailMIPSvalcapBitsToCapability}{\saildoclabelled{sailMIPSzcapBitsToCapability}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex}}}} + +\newcommand{\sailMIPSfncapBitsToCapability}{\saildoclabelled{sailMIPSfnzcapBitsToCapability}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex}}}} + +\newcommand{\sailMIPSvalgetCapHardPerms}{\saildoclabelled{sailMIPSzgetCapHardPerms}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex}}}} + +\newcommand{\sailMIPSfngetCapHardPerms}{\saildoclabelled{sailMIPSfnzgetCapHardPerms}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex}}}} + +\newcommand{\sailMIPSvalcapToBits}{\saildoclabelled{sailMIPSzcapToBits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcaptobits025010a6e8c284beecc438f72babcc70.tex}}}} + +\newcommand{\sailMIPSfncapToBits}{\saildoclabelled{sailMIPSfnzcapToBits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcaptobits025010a6e8c284beecc438f72babcc70.tex}}}} + +\newcommand{\sailMIPSvalcapToMemBits}{\saildoclabelled{sailMIPSzcapToMemBits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex}}}} + +\newcommand{\sailMIPSfncapToMemBits}{\saildoclabelled{sailMIPSfnzcapToMemBits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex}}}} + +\newcommand{\sailMIPSvalmemBitsToCapability}{\saildoclabelled{sailMIPSzmemBitsToCapability}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex}}}} + +\newcommand{\sailMIPSfnmemBitsToCapability}{\saildoclabelled{sailMIPSfnzmemBitsToCapability}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex}}}} + +\newcommand{\sailMIPSvalgetCapPerms}{\saildoclabelled{sailMIPSzgetCapPerms}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzgetcapperms6aed04c1602f540bb5d604425f922d92.tex}}}} + +\newcommand{\sailMIPSfngetCapPerms}{\saildoclabelled{sailMIPSfnzgetCapPerms}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzgetcapperms6aed04c1602f540bb5d604425f922d92.tex}}}} + +\newcommand{\sailMIPSvalsetCapPerms}{\saildoclabelled{sailMIPSzsetCapPerms}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex}}}} + +\newcommand{\sailMIPSfnsetCapPerms}{\saildoclabelled{sailMIPSfnzsetCapPerms}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex}}}} + +\newcommand{\sailMIPSvalsealCap}{\saildoclabelled{sailMIPSzsealCap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex}}}} + +\newcommand{\sailMIPSfnsealCap}{\saildoclabelled{sailMIPSfnzsealCap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex}}}} + +\newcommand{\sailMIPSvalunsealCap}{\saildoclabelled{sailMIPSzunsealCap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzunsealcap58689ae49a7317c60147327414a678d2.tex}}}} + +\newcommand{\sailMIPSfnunsealCap}{\saildoclabelled{sailMIPSfnzunsealCap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzunsealcap58689ae49a7317c60147327414a678d2.tex}}}} + +\newcommand{\sailMIPSvalgetCapBounds}{\saildoclabelled{sailMIPSzgetCapBounds}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex}}}} + +\newcommand{\sailMIPSfngetCapBounds}{\saildoclabelled{sailMIPSfnzgetCapBounds}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex}}}} + +\newcommand{\sailMIPSvalgetCapBase}{\saildoclabelled{sailMIPSzgetCapBase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex}}}} + +\newcommand{\sailMIPSfngetCapBase}{\saildoclabelled{sailMIPSfnzgetCapBase}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex}}}} + +\newcommand{\sailMIPSvalgetCapTop}{\saildoclabelled{sailMIPSzgetCapTop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex}}}} + +\newcommand{\sailMIPSfngetCapTop}{\saildoclabelled{sailMIPSfnzgetCapTop}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex}}}} + +\newcommand{\sailMIPSvalgetCapOffset}{\saildoclabelled{sailMIPSzgetCapOffset}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex}}}} + +\newcommand{\sailMIPSfngetCapOffset}{\saildoclabelled{sailMIPSfnzgetCapOffset}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex}}}} + +\newcommand{\sailMIPSvalgetCapLength}{\saildoclabelled{sailMIPSzgetCapLength}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex}}}} + +\newcommand{\sailMIPSfngetCapLength}{\saildoclabelled{sailMIPSfnzgetCapLength}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex}}}} + +\newcommand{\sailMIPSvalgetCapCursor}{\saildoclabelled{sailMIPSzgetCapCursor}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex}}}} + +\newcommand{\sailMIPSfngetCapCursor}{\saildoclabelled{sailMIPSfnzgetCapCursor}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex}}}} + +\newcommand{\sailMIPSvalcapBoundsEqual}{\saildoclabelled{sailMIPSzcapBoundsEqual}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex}}}} + +\newcommand{\sailMIPSfncapBoundsEqual}{\saildoclabelled{sailMIPSfnzcapBoundsEqual}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex}}}} + +\newcommand{\sailMIPSvalsetCapAddr}{\saildoclabelled{sailMIPSzsetCapAddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex}}}} + +\newcommand{\sailMIPSfnsetCapAddr}{\saildoclabelled{sailMIPSfnzsetCapAddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex}}}} + +\newcommand{\sailMIPSvalsetCapOffset}{\saildoclabelled{sailMIPSzsetCapOffset}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex}}}} + +\newcommand{\sailMIPSfnsetCapOffset}{\saildoclabelled{sailMIPSfnzsetCapOffset}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex}}}} + +\newcommand{\sailMIPSvalincCapOffset}{\saildoclabelled{sailMIPSzincCapOffset}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzinccapoffsetc4735d243650e78b90bacb6efb419260.tex}}}} + +\newcommand{\sailMIPSfnincCapOffset}{\saildoclabelled{sailMIPSfnzincCapOffset}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzinccapoffsetc4735d243650e78b90bacb6efb419260.tex}}}} + +\newcommand{\sailMIPSvalsetCapBounds}{\saildoclabelled{sailMIPSzsetCapBounds}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex}}}} + +\newcommand{\sailMIPSfnsetCapBounds}{\saildoclabelled{sailMIPSfnzsetCapBounds}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex}}}} + +\newcommand{\sailMIPSvalgetRepresentableAlignmentMask}{\saildoclabelled{sailMIPSzgetRepresentableAlignmentMask}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex}}}} + +\newcommand{\sailMIPSfngetRepresentableAlignmentMask}{\saildoclabelled{sailMIPSfnzgetRepresentableAlignmentMask}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex}}}} + +\newcommand{\sailMIPSvalgetRepresentableLength}{\saildoclabelled{sailMIPSzgetRepresentableLength}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex}}}} + +\newcommand{\sailMIPSfngetRepresentableLength}{\saildoclabelled{sailMIPSfnzgetRepresentableLength}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex}}}} + +\newcommand{\sailMIPStypeCapRegEnc}{\saildoclabelled{sailMIPStypezCapRegEnc}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezcapregenc81083d19fcdcf94728bdf9c6360cc203.tex}}}} + +\newcommand{\sailMIPStypeCapRegOrDDCEnc}{\saildoclabelled{sailMIPStypezCapRegOrDDCEnc}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezcapregorddcenc4d797db90f106a69ff753815af67f927.tex}}}} + +\newcommand{\sailMIPStypeCapHwrEnc}{\saildoclabelled{sailMIPStypezCapHwrEnc}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezcaphwrenc2bb0321c08e3f230e2bc09240b4b0441.tex}}}} + +\newcommand{\sailMIPSvalcapToString}{\saildoclabelled{sailMIPSzcapToString}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex}}}} + +\newcommand{\sailMIPSvalreadCapReg}{\saildoclabelled{sailMIPSzreadCapReg}{\saildocval{\lstinline{readCapReg} reads a given capability register or, +the null capabiility if the argument is zero. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzreadcapreg0fe08ef5bf06c41ffed8e12baf8ddd85.tex}}}} + +\newcommand{\sailMIPSfnreadCapReg}{\saildoclabelled{sailMIPSfnzreadCapReg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzreadcapreg0fe08ef5bf06c41ffed8e12baf8ddd85.tex}}}} + +\newcommand{\sailMIPSvalreadCapRegDDC}{\saildoclabelled{sailMIPSzreadCapRegDDC}{\saildocval{\lstinline{readCapRegDDC} is the same as \hyperref[sailMIPSzreadCapReg]{\lstinline{readCapReg}} except that when the argument is zero the value of DDC is returned +instead of the null capability. This is used for instructions that expect an address, where using +null would always generate an exception. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzreadcapregddc65f046a34609a089c9bf681a6893bca6.tex}}}} + +\newcommand{\sailMIPSfnreadCapRegDDC}{\saildoclabelled{sailMIPSfnzreadCapRegDDC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzreadcapregddc65f046a34609a089c9bf681a6893bca6.tex}}}} + +\newcommand{\sailMIPSvalwriteCapReg}{\saildoclabelled{sailMIPSzwriteCapReg}{\saildocval{\lstinline{writeCapReg}\lstinline`(cd, cap_val)` writes capability, \lstinline`cap_val` capability register \lstinline`cd`. Writes to register zero are ignored. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzwritecapreg902f20f3d4ba5384b97aa04a7a1756f4.tex}}}} + +\newcommand{\sailMIPSfnwriteCapReg}{\saildoclabelled{sailMIPSfnzwriteCapReg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzwritecapreg902f20f3d4ba5384b97aa04a7a1756f4.tex}}}} + +\newcommand{\sailMIPSvalunrepCap}{\saildoclabelled{sailMIPSzunrepCap}{\saildocval{\lstinline{unrepCap}\lstinline`(cap)` returns \lstinline`cap` with the tag unset. It is used when the +result of a capability operation (\saildocabbrev{e.g.} setting the address) has +caused it to become unrepresentable. The result of subsequent +operations such as \hyperref[sailMIPSzgetCapBase]{\lstinline{getCapBase}} will depend on the exact capability +format in use but in general the address, length, object type and +permissions will remain the same, with the expected operation having +been applied to the address. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzunrepcap312d66f4391d908cc0a7a87a38e8881a.tex}}}} + +\newcommand{\sailMIPSfnunrepCap}{\saildoclabelled{sailMIPSfnzunrepCap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzunrepcap312d66f4391d908cc0a7a87a38e8881a.tex}}}} + +\newcommand{\sailMIPStypeCapEx}{\saildoclabelled{sailMIPStypezCapEx}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezcapexbc9797bf8ddff0359677ca6657edba93.tex}}}} + +\newcommand{\sailMIPSvalCapExOfNum}{\saildoclabelled{sailMIPSzCapExzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex}}}} + +\newcommand{\sailMIPSfnCapExOfNum}{\saildoclabelled{sailMIPSfnzCapExzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex}}}} + +\newcommand{\sailMIPSvalnumOfCapEx}{\saildoclabelled{sailMIPSznumzyofzyCapEx}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valznum_of_capexa430f3db535161473e26bac337cc3ffe.tex}}}} + +\newcommand{\sailMIPSfnnumOfCapEx}{\saildoclabelled{sailMIPSfnznumzyofzyCapEx}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnznum_of_capexa430f3db535161473e26bac337cc3ffe.tex}}}} + +\newcommand{\sailMIPSvalCapExCode}{\saildoclabelled{sailMIPSzCapExCode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcapexcodee065d40e92bb99703db21c8c18bedf11.tex}}}} + +\newcommand{\sailMIPSfnCapExCode}{\saildoclabelled{sailMIPSfnzCapExCode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcapexcodee065d40e92bb99703db21c8c18bedf11.tex}}}} + +\newcommand{\sailMIPSvalstringOfCapex}{\saildoclabelled{sailMIPSzstringzyofzycapex}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex}}}} + +\newcommand{\sailMIPSfnstringOfCapex}{\saildoclabelled{sailMIPSfnzstringzyofzycapex}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex}}}} + +\newcommand{\sailMIPStypeCapCauseReg}{\saildoclabelled{sailMIPStypezCapCauseReg}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezcapcausereg4dd1a4671e3fabc92350ed31d9f5303e.tex}}}} + +\newcommand{\sailMIPSvalMkCapCauseReg}{\saildoclabelled{sailMIPSzMkzyCapCauseReg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzmk_capcauseregd8ae0b1c037e066a22724fe6a3d3a9a6.tex}}}} + +\newcommand{\sailMIPSfnMkCapCauseReg}{\saildoclabelled{sailMIPSfnzMkzyCapCauseReg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmk_capcauseregd8ae0b1c037e066a22724fe6a3d3a9a6.tex}}}} + +\newcommand{\sailMIPSvalGetCapCauseRegBits}{\saildoclabelled{sailMIPSzzygetzyCapCauseRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_capcausereg_bits52bfda42e15401e97a3be8662ec10017.tex}}}} + +\newcommand{\sailMIPSfnGetCapCauseRegBits}{\saildoclabelled{sailMIPSfnzzygetzyCapCauseRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_capcausereg_bits52bfda42e15401e97a3be8662ec10017.tex}}}} + +\newcommand{\sailMIPSvalSetCapCauseRegBits}{\saildoclabelled{sailMIPSzzysetzyCapCauseRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_capcausereg_bits0f09722beb30b9b32d98ac38786a393b.tex}}}} + +\newcommand{\sailMIPSfnSetCapCauseRegBits}{\saildoclabelled{sailMIPSfnzzysetzyCapCauseRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_capcausereg_bits0f09722beb30b9b32d98ac38786a393b.tex}}}} + +\newcommand{\sailMIPSvalUpdateCapCauseRegBits}{\saildoclabelled{sailMIPSzzyupdatezyCapCauseRegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_capcausereg_bitsc7253ec47586740f3fd1b2b2e8cdca5a.tex}}}} + +\newcommand{\sailMIPSfnUpdateCapCauseRegBits}{\saildoclabelled{sailMIPSfnzzyupdatezyCapCauseRegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_capcausereg_bitsc7253ec47586740f3fd1b2b2e8cdca5a.tex}}}} + +\newcommand{\sailMIPSoverloadWWWWWWWupdateBits}{\saildoclabelled{sailMIPSoverloadWWWWWWWzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadWWWWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailMIPSoverloadXXXXXXXModBits}{\saildoclabelled{sailMIPSoverloadXXXXXXXzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadXXXXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailMIPSvalGetCapCauseRegExcCode}{\saildoclabelled{sailMIPSzzygetzyCapCauseRegzyExcCode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_capcausereg_exccode52aba9ba1e3306797490b273879487fc.tex}}}} + +\newcommand{\sailMIPSfnGetCapCauseRegExcCode}{\saildoclabelled{sailMIPSfnzzygetzyCapCauseRegzyExcCode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_capcausereg_exccode52aba9ba1e3306797490b273879487fc.tex}}}} + +\newcommand{\sailMIPSvalSetCapCauseRegExcCode}{\saildoclabelled{sailMIPSzzysetzyCapCauseRegzyExcCode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_capcausereg_exccode61e56f7469922be2cde66ae4460b17ee.tex}}}} + +\newcommand{\sailMIPSfnSetCapCauseRegExcCode}{\saildoclabelled{sailMIPSfnzzysetzyCapCauseRegzyExcCode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_capcausereg_exccode61e56f7469922be2cde66ae4460b17ee.tex}}}} + +\newcommand{\sailMIPSvalUpdateCapCauseRegExcCode}{\saildoclabelled{sailMIPSzzyupdatezyCapCauseRegzyExcCode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_capcausereg_exccode831973db379fbc7fc58a62fad27d1e48.tex}}}} + +\newcommand{\sailMIPSfnUpdateCapCauseRegExcCode}{\saildoclabelled{sailMIPSfnzzyupdatezyCapCauseRegzyExcCode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_capcausereg_exccode831973db379fbc7fc58a62fad27d1e48.tex}}}} + +\newcommand{\sailMIPSoverloadYYYYYYYupdateExcCode}{\saildoclabelled{sailMIPSoverloadYYYYYYYzupdatezyExcCode}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadYYYYYYYzupdate_exccode286b5e0163b588d6fbc04a06efd36aa1.tex}}}} + +\newcommand{\sailMIPSoverloadZZZZZZZModExcCode}{\saildoclabelled{sailMIPSoverloadZZZZZZZzzymodzyExcCode}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadZZZZZZZz_mod_exccode24886ea7a19912378ba2030097458ff1.tex}}}} + +\newcommand{\sailMIPSvalGetCapCauseRegRegNum}{\saildoclabelled{sailMIPSzzygetzyCapCauseRegzyRegNum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_get_capcausereg_regnumb581772dd095764cdd19b6f0e8c03d06.tex}}}} + +\newcommand{\sailMIPSfnGetCapCauseRegRegNum}{\saildoclabelled{sailMIPSfnzzygetzyCapCauseRegzyRegNum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_get_capcausereg_regnumb581772dd095764cdd19b6f0e8c03d06.tex}}}} + +\newcommand{\sailMIPSvalSetCapCauseRegRegNum}{\saildoclabelled{sailMIPSzzysetzyCapCauseRegzyRegNum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_set_capcausereg_regnum2d65e24c7a9625fc0aed9327369188a6.tex}}}} + +\newcommand{\sailMIPSfnSetCapCauseRegRegNum}{\saildoclabelled{sailMIPSfnzzysetzyCapCauseRegzyRegNum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_set_capcausereg_regnum2d65e24c7a9625fc0aed9327369188a6.tex}}}} + +\newcommand{\sailMIPSvalUpdateCapCauseRegRegNum}{\saildoclabelled{sailMIPSzzyupdatezyCapCauseRegzyRegNum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valz_update_capcausereg_regnumdfccaf21a7f843566ceea99a5e20969b.tex}}}} + +\newcommand{\sailMIPSfnUpdateCapCauseRegRegNum}{\saildoclabelled{sailMIPSfnzzyupdatezyCapCauseRegzyRegNum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnz_update_capcausereg_regnumdfccaf21a7f843566ceea99a5e20969b.tex}}}} + +\newcommand{\sailMIPSoverloadAAAAAAAAupdateRegNum}{\saildoclabelled{sailMIPSoverloadAAAAAAAAzupdatezyRegNum}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadAAAAAAAAzupdate_regnumf38b56d427844345bd870b4ea07d3f5b.tex}}}} + +\newcommand{\sailMIPSoverloadBBBBBBBBModRegNum}{\saildoclabelled{sailMIPSoverloadBBBBBBBBzzymodzyRegNum}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_mips/overloadBBBBBBBBz_mod_regnumf3e57f0335af5095cca3b6786298d47b.tex}}}} + +\newcommand{\sailMIPSvalexecuteBranchPcc}{\saildoclabelled{sailMIPSzexecutezybranchzypcc}{\saildocval{\lstinline{execute_branch_pcc} executes a branch to the given capability, replacing PCC and taking the new PC from the offset field. Note that on MIPS the new PCC does not take effect until after the branch delay slot. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzexecute_branch_pcc8b6a454691b25b72e01ecd191988286f.tex}}}} + +\newcommand{\sailMIPSfnexecuteBranchPcc}{\saildoclabelled{sailMIPSfnzexecutezybranchzypcc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzexecute_branch_pcc8b6a454691b25b72e01ecd191988286f.tex}}}} + +\newcommand{\sailMIPSvalsetNextPcc}{\saildoclabelled{sailMIPSzsetzynextzypcc}{\saildocval{\lstinline{set_next_pcc} sets PCC to the given capability before executing the next instruction. It is used for CCall, which has no branch delay. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzset_next_pcce92395a303a64d3216ddb0601b37e83f.tex}}}} + +\newcommand{\sailMIPSfnsetNextPcc}{\saildoclabelled{sailMIPSfnzsetzynextzypcc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzset_next_pcce92395a303a64d3216ddb0601b37e83f.tex}}}} + +\newcommand{\sailMIPSfnSignalException}{\saildoclabelled{sailMIPSfnzSignalException}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzsignalexception586f3a4c7da76085e25c98aff442160c.tex}}}} + +\newcommand{\sailMIPSvalraiseCTwoExceptionEight}{\saildoclabelled{sailMIPSzraisezyc2zyexception8}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzraise_c2_exception8c17523e86ae9ef48da8a222c10be2ee1.tex}}}} + +\newcommand{\sailMIPSfnraiseCTwoExceptionEight}{\saildoclabelled{sailMIPSfnzraisezyc2zyexception8}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzraise_c2_exception8c17523e86ae9ef48da8a222c10be2ee1.tex}}}} + +\newcommand{\sailMIPSvalraiseCTwoException}{\saildoclabelled{sailMIPSzraisezyc2zyexception}{\saildocval{causes the processor to raise a capability exception by writing the given capability exception cause and register number to the CapCause register then signalling an exception using \hyperref[sailMIPSzSignalException]{\lstinline{SignalException}} (on CHERI-MIPS this is a C2E exception in most cases, or a special C2Trap for CCall and CReturn). + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzraise_c2_exceptionb9a632810adbd99dc25a5f3a28ddb9f2.tex}}}} + +\newcommand{\sailMIPSfnraiseCTwoException}{\saildoclabelled{sailMIPSfnzraisezyc2zyexception}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzraise_c2_exceptionb9a632810adbd99dc25a5f3a28ddb9f2.tex}}}} + +\newcommand{\sailMIPSvalraiseCTwoExceptionNoreg}{\saildoclabelled{sailMIPSzraisezyc2zyexceptionzynoreg}{\saildocval{is as \hyperref[sailMIPSzraisezyc2zyexception]{\lstinline{raise_c2_exception}} except that CapCause.RegNum is written with the special value 0xff indicating PCC or no register. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzraise_c2_exception_noregaf4f146af9490f033f39a46e2216dccb.tex}}}} + +\newcommand{\sailMIPSfnraiseCTwoExceptionNoreg}{\saildoclabelled{sailMIPSfnzraisezyc2zyexceptionzynoreg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzraise_c2_exception_noregaf4f146af9490f033f39a46e2216dccb.tex}}}} + +\newcommand{\sailMIPSvalraiseCTwoExceptionBadaddr}{\saildoclabelled{sailMIPSzraisezyc2zyexceptionzybadaddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzraise_c2_exception_badaddrd8f6a78fc18067d06626bbc713515a9a.tex}}}} + +\newcommand{\sailMIPSfnraiseCTwoExceptionBadaddr}{\saildoclabelled{sailMIPSfnzraisezyc2zyexceptionzybadaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzraise_c2_exception_badaddrd8f6a78fc18067d06626bbc713515a9a.tex}}}} + +\newcommand{\sailMIPSvalpccAccessSystemRegs}{\saildoclabelled{sailMIPSzpcczyaccesszysystemzyregs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex}}}} + +\newcommand{\sailMIPSfnpccAccessSystemRegs}{\saildoclabelled{sailMIPSfnzpcczyaccesszysystemzyregs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex}}}} + +\newcommand{\sailMIPSfncheckCPZeroAccessHook}{\saildoclabelled{sailMIPSfnzcheckCP0AccessHook}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcheckcp0accesshook3dae675d70bdcddbd36c77cdbf07a44f.tex}}}} + +\newcommand{\sailMIPSvalreadTagBool}{\saildoclabelled{sailMIPSzreadzytagzybool}{\saildocval{reads the tag associated with the given physical address. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzread_tag_bool44af427aafdd59e3a8c85269cd4adf9e.tex}}}} + +\newcommand{\sailMIPSvalwriteTagBool}{\saildoclabelled{sailMIPSzwritezytagzybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzwrite_tag_bool760f89ee258516fba3e938c2e532f5b8.tex}}}} + +\newcommand{\sailMIPSvalMEMrTagged}{\saildoclabelled{sailMIPSzMEMrzytagged}{\saildocval{\lstinline{MEMr_tagged}\lstinline`(addr, size, allowTag)` reads \lstinline`size` bytes from the given physical address in memory and, if \lstinline`allowTag` is true, the associated tag value. If \lstinline`allowTag` is false then the returned tag value is always false. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemr_tagged440beee75c90056a7102115b9b1125be.tex}}}} + +\newcommand{\sailMIPSfnMEMrTagged}{\saildoclabelled{sailMIPSfnzMEMrzytagged}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemr_tagged440beee75c90056a7102115b9b1125be.tex}}}} + +\newcommand{\sailMIPSvalMEMrTaggedReserve}{\saildoclabelled{sailMIPSzMEMrzytaggedzyreserve}{\saildocval{is as \hyperref[sailMIPSzMEMrzytagged]{\lstinline{MEMr_tagged}} except that the load is marked as part of a load linked / store conditional. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemr_tagged_reserve7e4b5410eb1183e7621342e1939f17e1.tex}}}} + +\newcommand{\sailMIPSfnMEMrTaggedReserve}{\saildoclabelled{sailMIPSfnzMEMrzytaggedzyreserve}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemr_tagged_reserve7e4b5410eb1183e7621342e1939f17e1.tex}}}} + +\newcommand{\sailMIPSvalMEMwTagged}{\saildoclabelled{sailMIPSzMEMwzytagged}{\saildocval{\lstinline{MEMw_tagged}\lstinline`(addr, size, t, value)` writes \lstinline`size` bytes, \lstinline`value`, to physical address, \lstinline`addr`, with associated tag value, \lstinline`t`. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemw_tagged27267fa3fd60f13e6d2e22ac409b93e4.tex}}}} + +\newcommand{\sailMIPSfnMEMwTagged}{\saildoclabelled{sailMIPSfnzMEMwzytagged}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemw_tagged27267fa3fd60f13e6d2e22ac409b93e4.tex}}}} + +\newcommand{\sailMIPSvalMEMwTaggedConditional}{\saildoclabelled{sailMIPSzMEMwzytaggedzyconditional}{\saildocval{\lstinline{MEMw_tagged_conditional}\lstinline`(addr, size, t, value)` writes \lstinline`size` bytes, \lstinline`value`, to physical address, \lstinline`addr`, with associated tag value, \lstinline`t` and returns store conditional success or failure. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemw_tagged_conditionalb0f4ab03bc3ed7705702651cf1750e40.tex}}}} + +\newcommand{\sailMIPSfnMEMwTaggedConditional}{\saildoclabelled{sailMIPSfnzMEMwzytaggedzyconditional}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemw_tagged_conditionalb0f4ab03bc3ed7705702651cf1750e40.tex}}}} + +\newcommand{\sailMIPSvalMEMwWrapper}{\saildoclabelled{sailMIPSzMEMwzywrapper}{\saildocval{\lstinline{MEMw_wrapper}\lstinline`(addr, size, value)` writes \lstinline`size` bytes of \lstinline`value` to physical address \lstinline`addr`. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemw_wrapper2b3f4fb31f9ea0001f534fade943e5e3.tex}}}} + +\newcommand{\sailMIPSfnMEMwWrapper}{\saildoclabelled{sailMIPSfnzMEMwzywrapper}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemw_wrapper2b3f4fb31f9ea0001f534fade943e5e3.tex}}}} + +\newcommand{\sailMIPSvalMEMwConditionalWrapper}{\saildoclabelled{sailMIPSzMEMwzyconditionalzywrapper}{\saildocval{\lstinline{MEMw_conditional_wrapper}\lstinline`(addr, size, value)` attempts to write \lstinline`size` bytes of \lstinline`value` to physical address \lstinline`addr` and returns a boolean indicating store conditional success or failure. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzmemw_conditional_wrapperc4ec3508a0b7f04fee187cfb25d4f05b.tex}}}} + +\newcommand{\sailMIPSfnMEMwConditionalWrapper}{\saildoclabelled{sailMIPSfnzMEMwzyconditionalzywrapper}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzmemw_conditional_wrapperc4ec3508a0b7f04fee187cfb25d4f05b.tex}}}} + +\newcommand{\sailMIPSvalcheckDDCPerms}{\saildoclabelled{sailMIPSzcheckDDCPerms}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzcheckddcperms07cb3f56bec26901cdf69beab49d8910.tex}}}} + +\newcommand{\sailMIPSfncheckDDCPerms}{\saildoclabelled{sailMIPSfnzcheckDDCPerms}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcheckddcperms07cb3f56bec26901cdf69beab49d8910.tex}}}} + +\newcommand{\sailMIPSvaladdrWrapper}{\saildoclabelled{sailMIPSzaddrWrapper}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzaddrwrapperbff37cfeb3c9276bfa58f5d99b0ca05e.tex}}}} + +\newcommand{\sailMIPSfnaddrWrapper}{\saildoclabelled{sailMIPSfnzaddrWrapper}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzaddrwrapperbff37cfeb3c9276bfa58f5d99b0ca05e.tex}}}} + +\newcommand{\sailMIPSvaladdrWrapperUnaligned}{\saildoclabelled{sailMIPSzaddrWrapperUnaligned}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzaddrwrapperunaligned2c4b1b84884abfd7091faab6f7aed047.tex}}}} + +\newcommand{\sailMIPSfnaddrWrapperUnaligned}{\saildoclabelled{sailMIPSfnzaddrWrapperUnaligned}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzaddrwrapperunaligned2c4b1b84884abfd7091faab6f7aed047.tex}}}} + +\newcommand{\sailMIPSfnexecuteBranch}{\saildoclabelled{sailMIPSfnzexecutezybranch}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzexecute_branch311b9f285cc52d66c683fa3ecaee2918.tex}}}} + +\newcommand{\sailMIPSvalTranslatePC}{\saildoclabelled{sailMIPSzTranslatePC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valztranslatepca9eb30b515fe139216afcb3a9118ead3.tex}}}} + +\newcommand{\sailMIPSfnTranslatePC}{\saildoclabelled{sailMIPSfnzTranslatePC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnztranslatepca9eb30b515fe139216afcb3a9118ead3.tex}}}} + +\newcommand{\sailMIPSvalcheckCPTwousable}{\saildoclabelled{sailMIPSzcheckCP2usable}{\saildocval{\lstinline{checkCP2usable} raises a co-processor unusable exception if \lstinline`CP0Status.CU[2]` +is not set. All capability instructions must first check that the +capability co-processor is enabled. This allows the operating system +to only save and restore the full capability context for processes +that use capabilities. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzcheckcp2usable5e31fa40adaccfcd7791aafdb7b9d2de.tex}}}} + +\newcommand{\sailMIPSfncheckCPTwousable}{\saildoclabelled{sailMIPSfnzcheckCP2usable}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcheckcp2usable5e31fa40adaccfcd7791aafdb7b9d2de.tex}}}} + +\newcommand{\sailMIPSfninitCpTwoState}{\saildoclabelled{sailMIPSfnzinitzycp2zystate}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzinit_cp2_state7056c424b16f2ae2f851216ae32427b0.tex}}}} + +\newcommand{\sailMIPSfncpTwoNextPc}{\saildoclabelled{sailMIPSfnzcp2zynextzypc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcp2_next_pc33094c95220fdc4b0a67b83ac21fc047.tex}}}} + +\newcommand{\sailMIPSfngetCPZeroEPC}{\saildoclabelled{sailMIPSfnzgetzyCP0EPC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzget_cp0epc947f8a8e6dac5833e002f1ea37a79de2.tex}}}} + +\newcommand{\sailMIPSfnsetCPZeroEPC}{\saildoclabelled{sailMIPSfnzsetzyCP0EPC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzset_cp0epc28b8527a6fc9d9c7e3708c9379630443.tex}}}} + +\newcommand{\sailMIPSfngetCPZeroErrorEPC}{\saildoclabelled{sailMIPSfnzgetzyCP0ErrorEPC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzget_cp0errorepc1188335ff3decc7c914ce1ba3a7904dd.tex}}}} + +\newcommand{\sailMIPSfnsetCPZeroErrorEPC}{\saildoclabelled{sailMIPSfnzsetzyCP0ErrorEPC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzset_cp0errorepc99aeab8b8e922eeb71df49885a629b5d.tex}}}} + +\newcommand{\sailMIPSvalhasReservedOType}{\saildoclabelled{sailMIPSzhasReservedOType}{\saildocval{Tests whether the capability has a reserved otype (larger than max\_otype). + +\lstinputlisting[language=sail]{sail_latex_mips/block06715b2a132b169cecda227894974882.sail}}{\lstinputlisting[language=sail]{sail_latex_mips/valzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex}}}} + +\newcommand{\sailMIPSfnhasReservedOType}{\saildoclabelled{sailMIPSfnzhasReservedOType}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex}}}} + +\newcommand{\sailMIPSfncapToString}{\saildoclabelled{sailMIPSfnzcapToString}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex}}}} + +\newcommand{\sailMIPSfndumpCpTwoState}{\saildoclabelled{sailMIPSfnzdumpzycp2zystate}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzdump_cp2_statee501e37d7b82b621f6ff3cd1f225d5f1.tex}}}} + +\newcommand{\sailMIPSvalgetCapFlags}{\saildoclabelled{sailMIPSzgetCapFlags}{\saildocval{Gets the architecture specific capability flags for given capability. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex}}}} + +\newcommand{\sailMIPSfngetCapFlags}{\saildoclabelled{sailMIPSfnzgetCapFlags}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex}}}} + +\newcommand{\sailMIPSvalsetCapFlags}{\saildoclabelled{sailMIPSzsetCapFlags}{\saildocval{\lstinline{setCapFlags}\lstinline`(cap, flags)` sets the architecture specific capability flags on \lstinline`cap` to \lstinline`flags` and returns the result as new capability. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex}}}} + +\newcommand{\sailMIPSfnsetCapFlags}{\saildoclabelled{sailMIPSfnzsetCapFlags}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex}}}} + +\newcommand{\sailMIPSvalisSentryCap}{\saildoclabelled{sailMIPSzisSentryCap}{\saildocval{Returns true if the given capability is a sealed entry capability. + +}{\lstinputlisting[language=sail]{sail_latex_mips/valzissentrycapede72a679ee46914361276c4bacdaf18.tex}}}} + +\newcommand{\sailMIPSfnisSentryCap}{\saildoclabelled{sailMIPSfnzisSentryCap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzissentrycapede72a679ee46914361276c4bacdaf18.tex}}}} + +\newcommand{\sailMIPSvalERETHook}{\saildoclabelled{sailMIPSzERETHook}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzerethook15fc4e665e3e6cc75e445b15faa26b37.tex}}}} + +\newcommand{\sailMIPSfnERETHook}{\saildoclabelled{sailMIPSfnzERETHook}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzerethook15fc4e665e3e6cc75e445b15faa26b37.tex}}}} + +\newcommand{\sailMIPStypeast}{\saildoclabelled{sailMIPStypezast}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_mips/typezast6bb070d12e82e4887160cdfd016230c8.tex}}}} + +\newcommand{\sailMIPSvalexecute}{\saildoclabelled{sailMIPSzexecute}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSvaldecode}{\saildoclabelled{sailMIPSzdecode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSvalassembly}{\saildoclabelled{sailMIPSzassembly}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSvalstrCReg}{\saildoclabelled{sailMIPSzstrCReg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrcreg6eee441123c442c07d3b63b65e2c6a32.tex}}}} + +\newcommand{\sailMIPSfnstrCReg}{\saildoclabelled{sailMIPSfnzstrCReg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrcreg6eee441123c442c07d3b63b65e2c6a32.tex}}}} + +\newcommand{\sailMIPSvalstrRRArgs}{\saildoclabelled{sailMIPSzstrRRArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrrrargs01af3a4171de69de622a434d53850810.tex}}}} + +\newcommand{\sailMIPSfnstrRRArgs}{\saildoclabelled{sailMIPSfnzstrRRArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrrrargs01af3a4171de69de622a434d53850810.tex}}}} + +\newcommand{\sailMIPSvalstrRCArgs}{\saildoclabelled{sailMIPSzstrRCArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrrcargs77cbd4ae00a8aeed40f03673c45f3bf3.tex}}}} + +\newcommand{\sailMIPSfnstrRCArgs}{\saildoclabelled{sailMIPSfnzstrRCArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrrcargs77cbd4ae00a8aeed40f03673c45f3bf3.tex}}}} + +\newcommand{\sailMIPSvalstrCRArgs}{\saildoclabelled{sailMIPSzstrCRArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrcrargsa5dba43a853a6048828d7d473fcaedfb.tex}}}} + +\newcommand{\sailMIPSfnstrCRArgs}{\saildoclabelled{sailMIPSfnzstrCRArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrcrargsa5dba43a853a6048828d7d473fcaedfb.tex}}}} + +\newcommand{\sailMIPSvalstrCCArgs}{\saildoclabelled{sailMIPSzstrCCArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrccargs8d27f740eb5185eb67906b78fb166677.tex}}}} + +\newcommand{\sailMIPSfnstrCCArgs}{\saildoclabelled{sailMIPSfnzstrCCArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrccargs8d27f740eb5185eb67906b78fb166677.tex}}}} + +\newcommand{\sailMIPSvalstrCCCArgs}{\saildoclabelled{sailMIPSzstrCCCArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrcccargsd0cf13cbe0c477ce0624778eee44a85e.tex}}}} + +\newcommand{\sailMIPSfnstrCCCArgs}{\saildoclabelled{sailMIPSfnzstrCCCArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrcccargsd0cf13cbe0c477ce0624778eee44a85e.tex}}}} + +\newcommand{\sailMIPSvalstrCCRArgs}{\saildoclabelled{sailMIPSzstrCCRArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrccrargs496b2890b8e21e5bd6d7197ea4c075c8.tex}}}} + +\newcommand{\sailMIPSfnstrCCRArgs}{\saildoclabelled{sailMIPSfnzstrCCRArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrccrargs496b2890b8e21e5bd6d7197ea4c075c8.tex}}}} + +\newcommand{\sailMIPSvalstrRCCArgs}{\saildoclabelled{sailMIPSzstrRCCArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrrccargscb2c61998351777a60f6fb0c1be5bc73.tex}}}} + +\newcommand{\sailMIPSfnstrRCCArgs}{\saildoclabelled{sailMIPSfnzstrRCCArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrrccargscb2c61998351777a60f6fb0c1be5bc73.tex}}}} + +\newcommand{\sailMIPSvalstrRCRArgs}{\saildoclabelled{sailMIPSzstrRCRArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrrcrargs2a6690343bcd1d4f5aaa9410842cee4f.tex}}}} + +\newcommand{\sailMIPSfnstrRCRArgs}{\saildoclabelled{sailMIPSfnzstrRCRArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrrcrargs2a6690343bcd1d4f5aaa9410842cee4f.tex}}}} + +\newcommand{\sailMIPSvalstrCCIArgs}{\saildoclabelled{sailMIPSzstrCCIArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrcciargs33bcd057cc20ec3a9ddc520c721764a9.tex}}}} + +\newcommand{\sailMIPSfnstrCCIArgs}{\saildoclabelled{sailMIPSfnzstrCCIArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrcciargs33bcd057cc20ec3a9ddc520c721764a9.tex}}}} + +\newcommand{\sailMIPSvalstrCCIUArgs}{\saildoclabelled{sailMIPSzstrCCIUArgs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzstrcciuargs995341ac60a90e598fe5209db4db77a3.tex}}}} + +\newcommand{\sailMIPSfnstrCCIUArgs}{\saildoclabelled{sailMIPSfnzstrCCIUArgs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzstrcciuargs995341ac60a90e598fe5209db4db77a3.tex}}}} + +\newcommand{\sailMIPSfclCGetPermdecode}{\saildoclabelled{sailMIPSfclCGetPermzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPermzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetTypedecode}{\saildoclabelled{sailMIPSfclCGetTypezdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetTypezdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetBasedecode}{\saildoclabelled{sailMIPSfclCGetBasezdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetBasezdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetLendecode}{\saildoclabelled{sailMIPSfclCGetLenzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetLenzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetTagdecode}{\saildoclabelled{sailMIPSfclCGetTagzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetTagzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetSealeddecode}{\saildoclabelled{sailMIPSfclCGetSealedzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetSealedzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetCauserddecode}{\saildoclabelled{sailMIPSfclCGetCauserdzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetCauserdzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCReturndecode}{\saildoclabelled{sailMIPSfclCReturnzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCReturnzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetOffsetdecode}{\saildoclabelled{sailMIPSfclCGetOffsetzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSetCausertdecode}{\saildoclabelled{sailMIPSfclCSetCausertzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetCausertzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCAndPermdecode}{\saildoclabelled{sailMIPSfclCAndPermzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCAndPermzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCToPtrdecode}{\saildoclabelled{sailMIPSfclCToPtrzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCToPtrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpdecode}{\saildoclabelled{sailMIPSfclCPtrCmpzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpAdecode}{\saildoclabelled{sailMIPSfclCPtrCmpAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpBdecode}{\saildoclabelled{sailMIPSfclCPtrCmpBzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpCdecode}{\saildoclabelled{sailMIPSfclCPtrCmpCzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpDdecode}{\saildoclabelled{sailMIPSfclCPtrCmpDzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpDzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpEdecode}{\saildoclabelled{sailMIPSfclCPtrCmpEzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpEzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpFdecode}{\saildoclabelled{sailMIPSfclCPtrCmpFzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpFzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpGdecode}{\saildoclabelled{sailMIPSfclCPtrCmpGzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpGzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCIncOffsetdecode}{\saildoclabelled{sailMIPSfclCIncOffsetzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCIncOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSetOffsetdecode}{\saildoclabelled{sailMIPSfclCSetOffsetzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSetBoundsdecode}{\saildoclabelled{sailMIPSfclCSetBoundszdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetBoundszdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCClearTagdecode}{\saildoclabelled{sailMIPSfclCClearTagzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCClearTagzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCFromPtrdecode}{\saildoclabelled{sailMIPSfclCFromPtrzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCFromPtrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCCheckPermdecode}{\saildoclabelled{sailMIPSfclCCheckPermzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCheckPermzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCCheckTypedecode}{\saildoclabelled{sailMIPSfclCCheckTypezdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCheckTypezdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSealdecode}{\saildoclabelled{sailMIPSfclCSealzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSealzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCUnsealdecode}{\saildoclabelled{sailMIPSfclCUnsealzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCUnsealzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCJALRdecode}{\saildoclabelled{sailMIPSfclCJALRzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCJALRzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCJALRAdecode}{\saildoclabelled{sailMIPSfclCJALRAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCJALRAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetCauserdAdecode}{\saildoclabelled{sailMIPSfclCGetCauserdAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetCauserdAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSetCausersdecode}{\saildoclabelled{sailMIPSfclCSetCauserszdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetCauserszdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetPCCcddecode}{\saildoclabelled{sailMIPSfclCGetPCCcdzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPCCcdzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCJALRBdecode}{\saildoclabelled{sailMIPSfclCJALRBzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCJALRBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetCIDrddecode}{\saildoclabelled{sailMIPSfclCGetCIDrdzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetCIDrdzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSetCIDcbdecode}{\saildoclabelled{sailMIPSfclCSetCIDcbzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetCIDcbzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCClearTagscbdecode}{\saildoclabelled{sailMIPSfclCClearTagscbzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCClearTagscbzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCCheckPermAdecode}{\saildoclabelled{sailMIPSfclCCheckPermAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCheckPermAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCCheckTypeAdecode}{\saildoclabelled{sailMIPSfclCCheckTypeAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCheckTypeAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCClearTagAdecode}{\saildoclabelled{sailMIPSfclCClearTagAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCClearTagAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCMovedecode}{\saildoclabelled{sailMIPSfclCMovezdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCMovezdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCJALRCdecode}{\saildoclabelled{sailMIPSfclCJALRCzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCJALRCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSealEntrydecode}{\saildoclabelled{sailMIPSfclCSealEntryzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSealEntryzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadTagsdecode}{\saildoclabelled{sailMIPSfclCLoadTagszdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadTagszdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetPermAdecode}{\saildoclabelled{sailMIPSfclCGetPermAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPermAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetTypeAdecode}{\saildoclabelled{sailMIPSfclCGetTypeAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetTypeAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetBaseAdecode}{\saildoclabelled{sailMIPSfclCGetBaseAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetBaseAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetLenAdecode}{\saildoclabelled{sailMIPSfclCGetLenAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetLenAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetTagAdecode}{\saildoclabelled{sailMIPSfclCGetTagAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetTagAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetSealedAdecode}{\saildoclabelled{sailMIPSfclCGetSealedAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetSealedAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetOffsetAdecode}{\saildoclabelled{sailMIPSfclCGetOffsetAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetOffsetAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetPCCSetOffsetdecode}{\saildoclabelled{sailMIPSfclCGetPCCSetOffsetzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPCCSetOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCReadHwrdecode}{\saildoclabelled{sailMIPSfclCReadHwrzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCReadHwrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCWriteHwrdecode}{\saildoclabelled{sailMIPSfclCWriteHwrzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCWriteHwrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetAddrdecode}{\saildoclabelled{sailMIPSfclCGetAddrzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetFlagsdecode}{\saildoclabelled{sailMIPSfclCGetFlagszdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetFlagszdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetPCCIncOffsetdecode}{\saildoclabelled{sailMIPSfclCGetPCCIncOffsetzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPCCIncOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetPCCSetAddrdecode}{\saildoclabelled{sailMIPSfclCGetPCCSetAddrzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPCCSetAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCRAPdecode}{\saildoclabelled{sailMIPSfclCRAPzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCRAPzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCRAMdecode}{\saildoclabelled{sailMIPSfclCRAMzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCRAMzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSealAdecode}{\saildoclabelled{sailMIPSfclCSealAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSealAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCUnsealAdecode}{\saildoclabelled{sailMIPSfclCUnsealAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCUnsealAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCAndPermAdecode}{\saildoclabelled{sailMIPSfclCAndPermAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCAndPermAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSetOffsetAdecode}{\saildoclabelled{sailMIPSfclCSetOffsetAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetOffsetAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSetBoundsAdecode}{\saildoclabelled{sailMIPSfclCSetBoundsAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetBoundsAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSetBoundsExactdecode}{\saildoclabelled{sailMIPSfclCSetBoundsExactzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetBoundsExactzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSetFlagsdecode}{\saildoclabelled{sailMIPSfclCSetFlagszdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetFlagszdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCIncOffsetAdecode}{\saildoclabelled{sailMIPSfclCIncOffsetAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCIncOffsetAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCBuildCapdecode}{\saildoclabelled{sailMIPSfclCBuildCapzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCBuildCapzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCCopyTypedecode}{\saildoclabelled{sailMIPSfclCCopyTypezdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCopyTypezdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCCSealdecode}{\saildoclabelled{sailMIPSfclCCSealzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCSealzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCToPtrAdecode}{\saildoclabelled{sailMIPSfclCToPtrAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCToPtrAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCFromPtrAdecode}{\saildoclabelled{sailMIPSfclCFromPtrAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCFromPtrAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSubdecode}{\saildoclabelled{sailMIPSfclCSubzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSubzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCMOVXdecode}{\saildoclabelled{sailMIPSfclCMOVXzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCMOVXzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCMOVXAdecode}{\saildoclabelled{sailMIPSfclCMOVXAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCMOVXAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSetAddrdecode}{\saildoclabelled{sailMIPSfclCSetAddrzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCGetAndAddrdecode}{\saildoclabelled{sailMIPSfclCGetAndAddrzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetAndAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCAndAddrdecode}{\saildoclabelled{sailMIPSfclCAndAddrzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCAndAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpHdecode}{\saildoclabelled{sailMIPSfclCPtrCmpHzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpHzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpIdecode}{\saildoclabelled{sailMIPSfclCPtrCmpIzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpIzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpJdecode}{\saildoclabelled{sailMIPSfclCPtrCmpJzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpJzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpKdecode}{\saildoclabelled{sailMIPSfclCPtrCmpKzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpKzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpLdecode}{\saildoclabelled{sailMIPSfclCPtrCmpLzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpLzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpMdecode}{\saildoclabelled{sailMIPSfclCPtrCmpMzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpMzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpNdecode}{\saildoclabelled{sailMIPSfclCPtrCmpNzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpNzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpOdecode}{\saildoclabelled{sailMIPSfclCPtrCmpOzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpOzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCTestSubsetdecode}{\saildoclabelled{sailMIPSfclCTestSubsetzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCTestSubsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLCNTdecode}{\saildoclabelled{sailMIPSfclCLCNTzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLCNTzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCBXdecode}{\saildoclabelled{sailMIPSfclCBXzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCBXzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCBXAdecode}{\saildoclabelled{sailMIPSfclCBXAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCBXAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCBZdecode}{\saildoclabelled{sailMIPSfclCBZzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCBZzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCBZAdecode}{\saildoclabelled{sailMIPSfclCBZAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCBZAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCReturnAdecode}{\saildoclabelled{sailMIPSfclCReturnAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCReturnAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCCalldecode}{\saildoclabelled{sailMIPSfclCCallzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCallzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclClearRegsdecode}{\saildoclabelled{sailMIPSfclClearRegszdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclClearRegszdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclClearRegsAdecode}{\saildoclabelled{sailMIPSfclClearRegsAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclClearRegsAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclClearRegsBdecode}{\saildoclabelled{sailMIPSfclClearRegsBzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclClearRegsBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclClearRegsCdecode}{\saildoclabelled{sailMIPSfclClearRegsCzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclClearRegsCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCIncOffsetImmediatedecode}{\saildoclabelled{sailMIPSfclCIncOffsetImmediatezdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCIncOffsetImmediatezdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSetBoundsImmediatedecode}{\saildoclabelled{sailMIPSfclCSetBoundsImmediatezdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetBoundsImmediatezdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoaddecode}{\saildoclabelled{sailMIPSfclCLoadzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadAdecode}{\saildoclabelled{sailMIPSfclCLoadAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadBdecode}{\saildoclabelled{sailMIPSfclCLoadBzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadCdecode}{\saildoclabelled{sailMIPSfclCLoadCzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadDdecode}{\saildoclabelled{sailMIPSfclCLoadDzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadDzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadEdecode}{\saildoclabelled{sailMIPSfclCLoadEzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadEzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadFdecode}{\saildoclabelled{sailMIPSfclCLoadFzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadFzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadLinkeddecode}{\saildoclabelled{sailMIPSfclCLoadLinkedzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadLinkedzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadLinkedAdecode}{\saildoclabelled{sailMIPSfclCLoadLinkedAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadLinkedAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadLinkedBdecode}{\saildoclabelled{sailMIPSfclCLoadLinkedBzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadLinkedBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadLinkedCdecode}{\saildoclabelled{sailMIPSfclCLoadLinkedCzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadLinkedCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadLinkedDdecode}{\saildoclabelled{sailMIPSfclCLoadLinkedDzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadLinkedDzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadLinkedEdecode}{\saildoclabelled{sailMIPSfclCLoadLinkedEzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadLinkedEzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLoadLinkedFdecode}{\saildoclabelled{sailMIPSfclCLoadLinkedFzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadLinkedFzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCStoredecode}{\saildoclabelled{sailMIPSfclCStorezdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCStorezdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCStoreAdecode}{\saildoclabelled{sailMIPSfclCStoreAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCStoreAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCStoreBdecode}{\saildoclabelled{sailMIPSfclCStoreBzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCStoreBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCStoreCdecode}{\saildoclabelled{sailMIPSfclCStoreCzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCStoreCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCStoreConditionaldecode}{\saildoclabelled{sailMIPSfclCStoreConditionalzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCStoreConditionalzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCStoreConditionalAdecode}{\saildoclabelled{sailMIPSfclCStoreConditionalAzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCStoreConditionalAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCStoreConditionalBdecode}{\saildoclabelled{sailMIPSfclCStoreConditionalBzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCStoreConditionalBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCStoreConditionalCdecode}{\saildoclabelled{sailMIPSfclCStoreConditionalCzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCStoreConditionalCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSCdecode}{\saildoclabelled{sailMIPSfclCSCzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCSCCdecode}{\saildoclabelled{sailMIPSfclCSCCzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSCCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLCdecode}{\saildoclabelled{sailMIPSfclCLCzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLLCdecode}{\saildoclabelled{sailMIPSfclCLLCzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLLCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCLCBIdecode}{\saildoclabelled{sailMIPSfclCLCBIzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLCBIzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclCTwoDumprtdecode}{\saildoclabelled{sailMIPSfclCTwoDumprtzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCTwoDumprtzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailMIPSfclRIdecode}{\saildoclabelled{sailMIPSfclRIzdecode}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclRIzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + + + +\newcommand{\sailMIPSfclCGetPermexecute}{\saildoclabelled{sailMIPSfclCGetPermzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPermzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetFlagsexecute}{\saildoclabelled{sailMIPSfclCGetFlagszexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetFlagszexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetTypeexecute}{\saildoclabelled{sailMIPSfclCGetTypezexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetTypezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetBaseexecute}{\saildoclabelled{sailMIPSfclCGetBasezexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetBasezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetOffsetexecute}{\saildoclabelled{sailMIPSfclCGetOffsetzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetLenexecute}{\saildoclabelled{sailMIPSfclCGetLenzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetLenzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetTagexecute}{\saildoclabelled{sailMIPSfclCGetTagzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetTagzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetSealedexecute}{\saildoclabelled{sailMIPSfclCGetSealedzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetSealedzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetAddrexecute}{\saildoclabelled{sailMIPSfclCGetAddrzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetAddrzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetAndAddrexecute}{\saildoclabelled{sailMIPSfclCGetAndAddrzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetAndAddrzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetPCCexecute}{\saildoclabelled{sailMIPSfclCGetPCCzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPCCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetPCCSetOffsetexecute}{\saildoclabelled{sailMIPSfclCGetPCCSetOffsetzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPCCSetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetPCCIncOffsetexecute}{\saildoclabelled{sailMIPSfclCGetPCCIncOffsetzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPCCIncOffsetzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetPCCSetAddrexecute}{\saildoclabelled{sailMIPSfclCGetPCCSetAddrzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPCCSetAddrzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetCauseexecute}{\saildoclabelled{sailMIPSfclCGetCausezexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetCausezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCSetCauseexecute}{\saildoclabelled{sailMIPSfclCSetCausezexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetCausezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCGetCIDexecute}{\saildoclabelled{sailMIPSfclCGetCIDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetCIDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCSetCIDexecute}{\saildoclabelled{sailMIPSfclCSetCIDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetCIDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCRAPexecute}{\saildoclabelled{sailMIPSfclCRAPzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCRAPzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCRAMexecute}{\saildoclabelled{sailMIPSfclCRAMzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCRAMzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCReadHwrexecute}{\saildoclabelled{sailMIPSfclCReadHwrzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCReadHwrzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCWriteHwrexecute}{\saildoclabelled{sailMIPSfclCWriteHwrzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCWriteHwrzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCAndPermexecute}{\saildoclabelled{sailMIPSfclCAndPermzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCAndPermzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCSetFlagsexecute}{\saildoclabelled{sailMIPSfclCSetFlagszexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetFlagszexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCToPtrexecute}{\saildoclabelled{sailMIPSfclCToPtrzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCToPtrzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCSubexecute}{\saildoclabelled{sailMIPSfclCSubzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSubzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCPtrCmpexecute}{\saildoclabelled{sailMIPSfclCPtrCmpzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCPtrCmpzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCIncOffsetexecute}{\saildoclabelled{sailMIPSfclCIncOffsetzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCIncOffsetzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCIncOffsetImmediateexecute}{\saildoclabelled{sailMIPSfclCIncOffsetImmediatezexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCIncOffsetImmediatezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCSetOffsetexecute}{\saildoclabelled{sailMIPSfclCSetOffsetzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCSetAddrexecute}{\saildoclabelled{sailMIPSfclCSetAddrzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetAddrzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCAndAddrexecute}{\saildoclabelled{sailMIPSfclCAndAddrzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCAndAddrzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCSetBoundsexecute}{\saildoclabelled{sailMIPSfclCSetBoundszexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetBoundszexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCSetBoundsImmediateexecute}{\saildoclabelled{sailMIPSfclCSetBoundsImmediatezexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetBoundsImmediatezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCSetBoundsExactexecute}{\saildoclabelled{sailMIPSfclCSetBoundsExactzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetBoundsExactzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCClearTagexecute}{\saildoclabelled{sailMIPSfclCClearTagzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCClearTagzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCMOVXexecute}{\saildoclabelled{sailMIPSfclCMOVXzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCMOVXzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCMoveexecute}{\saildoclabelled{sailMIPSfclCMovezexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCMovezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclClearRegsexecute}{\saildoclabelled{sailMIPSfclClearRegszexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclClearRegszexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCFromPtrexecute}{\saildoclabelled{sailMIPSfclCFromPtrzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCFromPtrzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCBuildCapexecute}{\saildoclabelled{sailMIPSfclCBuildCapzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCBuildCapzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCCopyTypeexecute}{\saildoclabelled{sailMIPSfclCCopyTypezexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCopyTypezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCCheckPermexecute}{\saildoclabelled{sailMIPSfclCCheckPermzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCheckPermzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCCheckTypeexecute}{\saildoclabelled{sailMIPSfclCCheckTypezexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCheckTypezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCCheckTagexecute}{\saildoclabelled{sailMIPSfclCCheckTagzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCheckTagzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCTestSubsetexecute}{\saildoclabelled{sailMIPSfclCTestSubsetzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCTestSubsetzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCSealexecute}{\saildoclabelled{sailMIPSfclCSealzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSealzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCCSealexecute}{\saildoclabelled{sailMIPSfclCCSealzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCSealzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCSealEntryexecute}{\saildoclabelled{sailMIPSfclCSealEntryzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSealEntryzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCUnsealexecute}{\saildoclabelled{sailMIPSfclCUnsealzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCUnsealzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCCallexecute}{\saildoclabelled{sailMIPSfclCCallzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCallzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCCallAexecute}{\saildoclabelled{sailMIPSfclCCallAzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCallAzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCReturnexecute}{\saildoclabelled{sailMIPSfclCReturnzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCReturnzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCBXexecute}{\saildoclabelled{sailMIPSfclCBXzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCBXzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCBZexecute}{\saildoclabelled{sailMIPSfclCBZzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCBZzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCJALRexecute}{\saildoclabelled{sailMIPSfclCJALRzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCJALRzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCLoadexecute}{\saildoclabelled{sailMIPSfclCLoadzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCLoadLinkedexecute}{\saildoclabelled{sailMIPSfclCLoadLinkedzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadLinkedzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCLoadTagsexecute}{\saildoclabelled{sailMIPSfclCLoadTagszexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadTagszexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCStoreexecute}{\saildoclabelled{sailMIPSfclCStorezexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCStorezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCStoreConditionalexecute}{\saildoclabelled{sailMIPSfclCStoreConditionalzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCStoreConditionalzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCSCexecute}{\saildoclabelled{sailMIPSfclCSCzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCSCCexecute}{\saildoclabelled{sailMIPSfclCSCCzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSCCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCLCexecute}{\saildoclabelled{sailMIPSfclCLCzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCLCNTexecute}{\saildoclabelled{sailMIPSfclCLCNTzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLCNTzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCLCBIexecute}{\saildoclabelled{sailMIPSfclCLCBIzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLCBIzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCLLCexecute}{\saildoclabelled{sailMIPSfclCLLCzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLLCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCClearTagsexecute}{\saildoclabelled{sailMIPSfclCClearTagszexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCClearTagszexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclCTwoDumpexecute}{\saildoclabelled{sailMIPSfclCTwoDumpzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCTwoDumpzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailMIPSfclRIexecute}{\saildoclabelled{sailMIPSfclRIzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclRIzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + + + +\newcommand{\sailMIPSfclCGetCauseassembly}{\saildoclabelled{sailMIPSfclCGetCausezassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetCausezassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCSetCauseassembly}{\saildoclabelled{sailMIPSfclCSetCausezassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetCausezassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetPCCassembly}{\saildoclabelled{sailMIPSfclCGetPCCzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPCCzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCJALRassembly}{\saildoclabelled{sailMIPSfclCJALRzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCJALRzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetCIDassembly}{\saildoclabelled{sailMIPSfclCGetCIDzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetCIDzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCSetCIDassembly}{\saildoclabelled{sailMIPSfclCSetCIDzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetCIDzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCClearTagsassembly}{\saildoclabelled{sailMIPSfclCClearTagszassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCClearTagszassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCCheckPermassembly}{\saildoclabelled{sailMIPSfclCCheckPermzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCheckPermzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCCheckTypeassembly}{\saildoclabelled{sailMIPSfclCCheckTypezassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCheckTypezassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCClearTagassembly}{\saildoclabelled{sailMIPSfclCClearTagzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCClearTagzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCMoveassembly}{\saildoclabelled{sailMIPSfclCMovezassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCMovezassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCJALRAassembly}{\saildoclabelled{sailMIPSfclCJALRAzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCJALRAzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCSealEntryassembly}{\saildoclabelled{sailMIPSfclCSealEntryzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSealEntryzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCLoadTagsassembly}{\saildoclabelled{sailMIPSfclCLoadTagszassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCLoadTagszassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetPermassembly}{\saildoclabelled{sailMIPSfclCGetPermzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPermzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetTypeassembly}{\saildoclabelled{sailMIPSfclCGetTypezassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetTypezassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetBaseassembly}{\saildoclabelled{sailMIPSfclCGetBasezassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetBasezassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetLenassembly}{\saildoclabelled{sailMIPSfclCGetLenzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetLenzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetTagassembly}{\saildoclabelled{sailMIPSfclCGetTagzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetTagzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetSealedassembly}{\saildoclabelled{sailMIPSfclCGetSealedzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetSealedzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetOffsetassembly}{\saildoclabelled{sailMIPSfclCGetOffsetzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetOffsetzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetPCCSetOffsetassembly}{\saildoclabelled{sailMIPSfclCGetPCCSetOffsetzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPCCSetOffsetzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCReadHwrassembly}{\saildoclabelled{sailMIPSfclCReadHwrzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCReadHwrzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCWriteHwrassembly}{\saildoclabelled{sailMIPSfclCWriteHwrzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCWriteHwrzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetAddrassembly}{\saildoclabelled{sailMIPSfclCGetAddrzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetAddrzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetFlagsassembly}{\saildoclabelled{sailMIPSfclCGetFlagszassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetFlagszassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetPCCIncOffsetassembly}{\saildoclabelled{sailMIPSfclCGetPCCIncOffsetzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPCCIncOffsetzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetPCCSetOffsetAassembly}{\saildoclabelled{sailMIPSfclCGetPCCSetOffsetAzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetPCCSetOffsetAzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCRAPassembly}{\saildoclabelled{sailMIPSfclCRAPzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCRAPzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCRAMassembly}{\saildoclabelled{sailMIPSfclCRAMzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCRAMzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCSealassembly}{\saildoclabelled{sailMIPSfclCSealzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSealzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCUnsealassembly}{\saildoclabelled{sailMIPSfclCUnsealzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCUnsealzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCAndPermassembly}{\saildoclabelled{sailMIPSfclCAndPermzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCAndPermzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCSetOffsetassembly}{\saildoclabelled{sailMIPSfclCSetOffsetzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetOffsetzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCSetBoundsassembly}{\saildoclabelled{sailMIPSfclCSetBoundszassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetBoundszassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCSetBoundsExactassembly}{\saildoclabelled{sailMIPSfclCSetBoundsExactzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetBoundsExactzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCSetFlagsassembly}{\saildoclabelled{sailMIPSfclCSetFlagszassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetFlagszassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCIncOffsetassembly}{\saildoclabelled{sailMIPSfclCIncOffsetzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCIncOffsetzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCBuildCapassembly}{\saildoclabelled{sailMIPSfclCBuildCapzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCBuildCapzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCCopyTypeassembly}{\saildoclabelled{sailMIPSfclCCopyTypezassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCopyTypezassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCCSealassembly}{\saildoclabelled{sailMIPSfclCCSealzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCSealzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCToPtrassembly}{\saildoclabelled{sailMIPSfclCToPtrzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCToPtrzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCFromPtrassembly}{\saildoclabelled{sailMIPSfclCFromPtrzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCFromPtrzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCSubassembly}{\saildoclabelled{sailMIPSfclCSubzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSubzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCMOVXassembly}{\saildoclabelled{sailMIPSfclCMOVXzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCMOVXzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCMOVXAassembly}{\saildoclabelled{sailMIPSfclCMOVXAzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCMOVXAzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCSetAddrassembly}{\saildoclabelled{sailMIPSfclCSetAddrzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetAddrzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCGetAndAddrassembly}{\saildoclabelled{sailMIPSfclCGetAndAddrzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCGetAndAddrzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCAndAddrassembly}{\saildoclabelled{sailMIPSfclCAndAddrzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCAndAddrzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCReturnassembly}{\saildoclabelled{sailMIPSfclCReturnzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCReturnzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCCallassembly}{\saildoclabelled{sailMIPSfclCCallzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCCallzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCIncOffsetImmediateassembly}{\saildoclabelled{sailMIPSfclCIncOffsetImmediatezassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCIncOffsetImmediatezassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclCSetBoundsImmediateassembly}{\saildoclabelled{sailMIPSfclCSetBoundsImmediatezassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclCSetBoundsImmediatezassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclRIassembly}{\saildoclabelled{sailMIPSfclRIzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclRIzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailMIPSfclassembly}{\saildoclabelled{sailMIPSfclzassembly}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_mips/fclzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + + + +\newcommand{\sailMIPSvalsupportedInstructions}{\saildoclabelled{sailMIPSzsupportedzyinstructions}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_mips/valzsupported_instructionsa556d55bb4bf818f15e811f8fa119862.tex}}}} + +\newcommand{\sailMIPSfnsupportedInstructions}{\saildoclabelled{sailMIPSfnzsupportedzyinstructions}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_mips/fnzsupported_instructionsa556d55bb4bf818f15e811f8fa119862.tex}}}} + +\newcommand{\sailMIPSval}[1]{ + \ifstrequal{#1}{AccessLevel\_of\_num}{\sailMIPSvalAccessLevelOfNum}{}% + \ifstrequal{#1}{BitStr}{\sailMIPSvalBitStr}{}% + \ifstrequal{#1}{CPtrCmpOp\_of\_num}{\sailMIPSvalCPtrCmpOpOfNum}{}% + \ifstrequal{#1}{CapExCode}{\sailMIPSvalCapExCode}{}% + \ifstrequal{#1}{CapEx\_of\_num}{\sailMIPSvalCapExOfNum}{}% + \ifstrequal{#1}{ClearRegSet\_of\_num}{\sailMIPSvalClearRegSetOfNum}{}% + \ifstrequal{#1}{Comparison\_of\_num}{\sailMIPSvalComparisonOfNum}{}% + \ifstrequal{#1}{ERETHook}{\sailMIPSvalERETHook}{}% + \ifstrequal{#1}{ExceptionCode}{\sailMIPSvalExceptionCode}{}% + \ifstrequal{#1}{Exception\_of\_num}{\sailMIPSvalExceptionOfNum}{}% + \ifstrequal{#1}{MAX}{\sailMIPSvalMAX}{}% + \ifstrequal{#1}{MEM\_sync}{\sailMIPSvalMEMSync}{}% + \ifstrequal{#1}{MEMea}{\sailMIPSvalMEMea}{}% + \ifstrequal{#1}{MEMea\_conditional}{\sailMIPSvalMEMeaConditional}{}% + \ifstrequal{#1}{MEMr}{\sailMIPSvalMEMr}{}% + \ifstrequal{#1}{MEMr\_reserve}{\sailMIPSvalMEMrReserve}{}% + \ifstrequal{#1}{MEMr\_reserve\_wrapper}{\sailMIPSvalMEMrReserveWrapper}{}% + \ifstrequal{#1}{MEMr\_tagged}{\sailMIPSvalMEMrTagged}{}% + \ifstrequal{#1}{MEMr\_tagged\_reserve}{\sailMIPSvalMEMrTaggedReserve}{}% + \ifstrequal{#1}{MEMr\_wrapper}{\sailMIPSvalMEMrWrapper}{}% + \ifstrequal{#1}{MEMval}{\sailMIPSvalMEMval}{}% + \ifstrequal{#1}{MEMval\_conditional}{\sailMIPSvalMEMvalConditional}{}% + \ifstrequal{#1}{MEMw\_conditional\_wrapper}{\sailMIPSvalMEMwConditionalWrapper}{}% + \ifstrequal{#1}{MEMw\_tagged}{\sailMIPSvalMEMwTagged}{}% + \ifstrequal{#1}{MEMw\_tagged\_conditional}{\sailMIPSvalMEMwTaggedConditional}{}% + \ifstrequal{#1}{MEMw\_wrapper}{\sailMIPSvalMEMwWrapper}{}% + \ifstrequal{#1}{MIPSSegmentOf}{\sailMIPSvalMIPSSegmentOf}{}% + \ifstrequal{#1}{MemAccessCapRestriction\_of\_num}{\sailMIPSvalMemAccessCapRestrictionOfNum}{}% + \ifstrequal{#1}{MemAccessType\_of\_num}{\sailMIPSvalMemAccessTypeOfNum}{}% + \ifstrequal{#1}{Mk\_CapCauseReg}{\sailMIPSvalMkCapCauseReg}{}% + \ifstrequal{#1}{Mk\_CauseReg}{\sailMIPSvalMkCauseReg}{}% + \ifstrequal{#1}{Mk\_ContextReg}{\sailMIPSvalMkContextReg}{}% + \ifstrequal{#1}{Mk\_StatusReg}{\sailMIPSvalMkStatusReg}{}% + \ifstrequal{#1}{Mk\_TLBEntry}{\sailMIPSvalMkTLBEntry}{}% + \ifstrequal{#1}{Mk\_TLBEntryHiReg}{\sailMIPSvalMkTLBEntryHiReg}{}% + \ifstrequal{#1}{Mk\_TLBEntryLoReg}{\sailMIPSvalMkTLBEntryLoReg}{}% + \ifstrequal{#1}{Mk\_XContextReg}{\sailMIPSvalMkXContextReg}{}% + \ifstrequal{#1}{NotWordVal}{\sailMIPSvalNotWordVal}{}% + \ifstrequal{#1}{SignalException}{\sailMIPSvalSignalException}{}% + \ifstrequal{#1}{SignalExceptionBadAddr}{\sailMIPSvalSignalExceptionBadAddr}{}% + \ifstrequal{#1}{SignalExceptionTLB}{\sailMIPSvalSignalExceptionTLB}{}% + \ifstrequal{#1}{TLBTranslate}{\sailMIPSvalTLBTranslate}{}% + \ifstrequal{#1}{TLBTranslate2}{\sailMIPSvalTLBTranslateTwo}{}% + \ifstrequal{#1}{TLBTranslateC}{\sailMIPSvalTLBTranslateC}{}% + \ifstrequal{#1}{TranslatePC}{\sailMIPSvalTranslatePC}{}% + \ifstrequal{#1}{WordTypeUnaligned\_of\_num}{\sailMIPSvalWordTypeUnalignedOfNum}{}% + \ifstrequal{#1}{WordType\_of\_num}{\sailMIPSvalWordTypeOfNum}{}% + \ifstrequal{#1}{\_\_MIPS\_read}{\sailMIPSvalMIPSRead}{}% + \ifstrequal{#1}{\_\_MIPS\_write}{\sailMIPSvalMIPSWrite}{}% + \ifstrequal{#1}{\_\_ReadRAM}{\sailMIPSvalReadRAM}{}% + \ifstrequal{#1}{\_\_WriteRAM}{\sailMIPSvalWriteRAM}{}% + \ifstrequal{#1}{\_\_bitfield\_deref}{\sailMIPSvalBitfieldDeref}{}% + \ifstrequal{#1}{\_\_deref}{\sailMIPSvalDeref}{}% + \ifstrequal{#1}{\_\_id}{\sailMIPSvalId}{}% + \ifstrequal{#1}{\_get\_CapCauseReg\_ExcCode}{\sailMIPSvalGetCapCauseRegExcCode}{}% + \ifstrequal{#1}{\_get\_CapCauseReg\_RegNum}{\sailMIPSvalGetCapCauseRegRegNum}{}% + \ifstrequal{#1}{\_get\_CapCauseReg\_bits}{\sailMIPSvalGetCapCauseRegBits}{}% + \ifstrequal{#1}{\_get\_CauseReg\_BD}{\sailMIPSvalGetCauseRegBD}{}% + \ifstrequal{#1}{\_get\_CauseReg\_CE}{\sailMIPSvalGetCauseRegCE}{}% + \ifstrequal{#1}{\_get\_CauseReg\_ExcCode}{\sailMIPSvalGetCauseRegExcCode}{}% + \ifstrequal{#1}{\_get\_CauseReg\_IP}{\sailMIPSvalGetCauseRegIP}{}% + \ifstrequal{#1}{\_get\_CauseReg\_IV}{\sailMIPSvalGetCauseRegIV}{}% + \ifstrequal{#1}{\_get\_CauseReg\_WP}{\sailMIPSvalGetCauseRegWP}{}% + \ifstrequal{#1}{\_get\_CauseReg\_bits}{\sailMIPSvalGetCauseRegBits}{}% + \ifstrequal{#1}{\_get\_ContextReg\_BadVPN2}{\sailMIPSvalGetContextRegBadVPNTwo}{}% + \ifstrequal{#1}{\_get\_ContextReg\_PTEBase}{\sailMIPSvalGetContextRegPTEBase}{}% + \ifstrequal{#1}{\_get\_ContextReg\_bits}{\sailMIPSvalGetContextRegBits}{}% + \ifstrequal{#1}{\_get\_StatusReg\_BEV}{\sailMIPSvalGetStatusRegBEV}{}% + \ifstrequal{#1}{\_get\_StatusReg\_CU}{\sailMIPSvalGetStatusRegCU}{}% + \ifstrequal{#1}{\_get\_StatusReg\_ERL}{\sailMIPSvalGetStatusRegERL}{}% + \ifstrequal{#1}{\_get\_StatusReg\_EXL}{\sailMIPSvalGetStatusRegEXL}{}% + \ifstrequal{#1}{\_get\_StatusReg\_IE}{\sailMIPSvalGetStatusRegIE}{}% + \ifstrequal{#1}{\_get\_StatusReg\_IM}{\sailMIPSvalGetStatusRegIM}{}% + \ifstrequal{#1}{\_get\_StatusReg\_KSU}{\sailMIPSvalGetStatusRegKSU}{}% + \ifstrequal{#1}{\_get\_StatusReg\_KX}{\sailMIPSvalGetStatusRegKX}{}% + \ifstrequal{#1}{\_get\_StatusReg\_SX}{\sailMIPSvalGetStatusRegSX}{}% + \ifstrequal{#1}{\_get\_StatusReg\_UX}{\sailMIPSvalGetStatusRegUX}{}% + \ifstrequal{#1}{\_get\_StatusReg\_bits}{\sailMIPSvalGetStatusRegBits}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_ASID}{\sailMIPSvalGetTLBEntryHiRegASID}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_CLGK}{\sailMIPSvalGetTLBEntryHiRegCLGK}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_CLGS}{\sailMIPSvalGetTLBEntryHiRegCLGS}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_CLGU}{\sailMIPSvalGetTLBEntryHiRegCLGU}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_R}{\sailMIPSvalGetTLBEntryHiRegR}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_VPN2}{\sailMIPSvalGetTLBEntryHiRegVPNTwo}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_bits}{\sailMIPSvalGetTLBEntryHiRegBits}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_C}{\sailMIPSvalGetTLBEntryLoRegC}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_CapL}{\sailMIPSvalGetTLBEntryLoRegCapL}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_CapLG}{\sailMIPSvalGetTLBEntryLoRegCapLG}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_CapS}{\sailMIPSvalGetTLBEntryLoRegCapS}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_D}{\sailMIPSvalGetTLBEntryLoRegD}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_G}{\sailMIPSvalGetTLBEntryLoRegG}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_PFN}{\sailMIPSvalGetTLBEntryLoRegPFN}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_V}{\sailMIPSvalGetTLBEntryLoRegV}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_bits}{\sailMIPSvalGetTLBEntryLoRegBits}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_asid}{\sailMIPSvalGetTLBEntryAsid}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_bits}{\sailMIPSvalGetTLBEntryBits}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_c0}{\sailMIPSvalGetTLBEntryCZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_c1}{\sailMIPSvalGetTLBEntryCOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_capl0}{\sailMIPSvalGetTLBEntryCaplZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_capl1}{\sailMIPSvalGetTLBEntryCaplOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_caplg0}{\sailMIPSvalGetTLBEntryCaplgZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_caplg1}{\sailMIPSvalGetTLBEntryCaplgOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_caps0}{\sailMIPSvalGetTLBEntryCapsZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_caps1}{\sailMIPSvalGetTLBEntryCapsOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_d0}{\sailMIPSvalGetTLBEntryDZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_d1}{\sailMIPSvalGetTLBEntryDOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_g}{\sailMIPSvalGetTLBEntryG}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_pagemask}{\sailMIPSvalGetTLBEntryPagemask}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_pfn0}{\sailMIPSvalGetTLBEntryPfnZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_pfn1}{\sailMIPSvalGetTLBEntryPfnOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_r}{\sailMIPSvalGetTLBEntryR}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_v0}{\sailMIPSvalGetTLBEntryVZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_v1}{\sailMIPSvalGetTLBEntryVOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_valid}{\sailMIPSvalGetTLBEntryValid}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_vpn2}{\sailMIPSvalGetTLBEntryVpnTwo}{}% + \ifstrequal{#1}{\_get\_XContextReg\_XBadVPN2}{\sailMIPSvalGetXContextRegXBadVPNTwo}{}% + \ifstrequal{#1}{\_get\_XContextReg\_XPTEBase}{\sailMIPSvalGetXContextRegXPTEBase}{}% + \ifstrequal{#1}{\_get\_XContextReg\_XR}{\sailMIPSvalGetXContextRegXR}{}% + \ifstrequal{#1}{\_get\_XContextReg\_bits}{\sailMIPSvalGetXContextRegBits}{}% + \ifstrequal{#1}{\_set\_CapCauseReg\_ExcCode}{\sailMIPSvalSetCapCauseRegExcCode}{}% + \ifstrequal{#1}{\_set\_CapCauseReg\_RegNum}{\sailMIPSvalSetCapCauseRegRegNum}{}% + \ifstrequal{#1}{\_set\_CapCauseReg\_bits}{\sailMIPSvalSetCapCauseRegBits}{}% + \ifstrequal{#1}{\_set\_CauseReg\_BD}{\sailMIPSvalSetCauseRegBD}{}% + \ifstrequal{#1}{\_set\_CauseReg\_CE}{\sailMIPSvalSetCauseRegCE}{}% + \ifstrequal{#1}{\_set\_CauseReg\_ExcCode}{\sailMIPSvalSetCauseRegExcCode}{}% + \ifstrequal{#1}{\_set\_CauseReg\_IP}{\sailMIPSvalSetCauseRegIP}{}% + \ifstrequal{#1}{\_set\_CauseReg\_IV}{\sailMIPSvalSetCauseRegIV}{}% + \ifstrequal{#1}{\_set\_CauseReg\_WP}{\sailMIPSvalSetCauseRegWP}{}% + \ifstrequal{#1}{\_set\_CauseReg\_bits}{\sailMIPSvalSetCauseRegBits}{}% + \ifstrequal{#1}{\_set\_ContextReg\_BadVPN2}{\sailMIPSvalSetContextRegBadVPNTwo}{}% + \ifstrequal{#1}{\_set\_ContextReg\_PTEBase}{\sailMIPSvalSetContextRegPTEBase}{}% + \ifstrequal{#1}{\_set\_ContextReg\_bits}{\sailMIPSvalSetContextRegBits}{}% + \ifstrequal{#1}{\_set\_StatusReg\_BEV}{\sailMIPSvalSetStatusRegBEV}{}% + \ifstrequal{#1}{\_set\_StatusReg\_CU}{\sailMIPSvalSetStatusRegCU}{}% + \ifstrequal{#1}{\_set\_StatusReg\_ERL}{\sailMIPSvalSetStatusRegERL}{}% + \ifstrequal{#1}{\_set\_StatusReg\_EXL}{\sailMIPSvalSetStatusRegEXL}{}% + \ifstrequal{#1}{\_set\_StatusReg\_IE}{\sailMIPSvalSetStatusRegIE}{}% + \ifstrequal{#1}{\_set\_StatusReg\_IM}{\sailMIPSvalSetStatusRegIM}{}% + \ifstrequal{#1}{\_set\_StatusReg\_KSU}{\sailMIPSvalSetStatusRegKSU}{}% + \ifstrequal{#1}{\_set\_StatusReg\_KX}{\sailMIPSvalSetStatusRegKX}{}% + \ifstrequal{#1}{\_set\_StatusReg\_SX}{\sailMIPSvalSetStatusRegSX}{}% + \ifstrequal{#1}{\_set\_StatusReg\_UX}{\sailMIPSvalSetStatusRegUX}{}% + \ifstrequal{#1}{\_set\_StatusReg\_bits}{\sailMIPSvalSetStatusRegBits}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_ASID}{\sailMIPSvalSetTLBEntryHiRegASID}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_CLGK}{\sailMIPSvalSetTLBEntryHiRegCLGK}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_CLGS}{\sailMIPSvalSetTLBEntryHiRegCLGS}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_CLGU}{\sailMIPSvalSetTLBEntryHiRegCLGU}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_R}{\sailMIPSvalSetTLBEntryHiRegR}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_VPN2}{\sailMIPSvalSetTLBEntryHiRegVPNTwo}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_bits}{\sailMIPSvalSetTLBEntryHiRegBits}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_C}{\sailMIPSvalSetTLBEntryLoRegC}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_CapL}{\sailMIPSvalSetTLBEntryLoRegCapL}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_CapLG}{\sailMIPSvalSetTLBEntryLoRegCapLG}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_CapS}{\sailMIPSvalSetTLBEntryLoRegCapS}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_D}{\sailMIPSvalSetTLBEntryLoRegD}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_G}{\sailMIPSvalSetTLBEntryLoRegG}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_PFN}{\sailMIPSvalSetTLBEntryLoRegPFN}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_V}{\sailMIPSvalSetTLBEntryLoRegV}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_bits}{\sailMIPSvalSetTLBEntryLoRegBits}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_asid}{\sailMIPSvalSetTLBEntryAsid}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_bits}{\sailMIPSvalSetTLBEntryBits}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_c0}{\sailMIPSvalSetTLBEntryCZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_c1}{\sailMIPSvalSetTLBEntryCOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_capl0}{\sailMIPSvalSetTLBEntryCaplZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_capl1}{\sailMIPSvalSetTLBEntryCaplOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_caplg0}{\sailMIPSvalSetTLBEntryCaplgZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_caplg1}{\sailMIPSvalSetTLBEntryCaplgOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_caps0}{\sailMIPSvalSetTLBEntryCapsZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_caps1}{\sailMIPSvalSetTLBEntryCapsOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_d0}{\sailMIPSvalSetTLBEntryDZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_d1}{\sailMIPSvalSetTLBEntryDOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_g}{\sailMIPSvalSetTLBEntryG}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_pagemask}{\sailMIPSvalSetTLBEntryPagemask}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_pfn0}{\sailMIPSvalSetTLBEntryPfnZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_pfn1}{\sailMIPSvalSetTLBEntryPfnOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_r}{\sailMIPSvalSetTLBEntryR}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_v0}{\sailMIPSvalSetTLBEntryVZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_v1}{\sailMIPSvalSetTLBEntryVOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_valid}{\sailMIPSvalSetTLBEntryValid}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_vpn2}{\sailMIPSvalSetTLBEntryVpnTwo}{}% + \ifstrequal{#1}{\_set\_XContextReg\_XBadVPN2}{\sailMIPSvalSetXContextRegXBadVPNTwo}{}% + \ifstrequal{#1}{\_set\_XContextReg\_XPTEBase}{\sailMIPSvalSetXContextRegXPTEBase}{}% + \ifstrequal{#1}{\_set\_XContextReg\_XR}{\sailMIPSvalSetXContextRegXR}{}% + \ifstrequal{#1}{\_set\_XContextReg\_bits}{\sailMIPSvalSetXContextRegBits}{}% + \ifstrequal{#1}{\_shl1}{\sailMIPSvalShlOne}{}% + \ifstrequal{#1}{\_shl32}{\sailMIPSvalShlThreeTwo}{}% + \ifstrequal{#1}{\_shl8}{\sailMIPSvalShlEight}{}% + \ifstrequal{#1}{\_shl\_int}{\sailMIPSvalShlInt}{}% + \ifstrequal{#1}{\_shr32}{\sailMIPSvalShrThreeTwo}{}% + \ifstrequal{#1}{\_shr\_int}{\sailMIPSvalShrInt}{}% + \ifstrequal{#1}{\_tmod\_int}{\sailMIPSvalTmodInt}{}% + \ifstrequal{#1}{\_tmod\_int\_positive}{\sailMIPSvalTmodIntPositive}{}% + \ifstrequal{#1}{\_update\_CapCauseReg\_ExcCode}{\sailMIPSvalUpdateCapCauseRegExcCode}{}% + \ifstrequal{#1}{\_update\_CapCauseReg\_RegNum}{\sailMIPSvalUpdateCapCauseRegRegNum}{}% + \ifstrequal{#1}{\_update\_CapCauseReg\_bits}{\sailMIPSvalUpdateCapCauseRegBits}{}% + \ifstrequal{#1}{\_update\_CauseReg\_BD}{\sailMIPSvalUpdateCauseRegBD}{}% + \ifstrequal{#1}{\_update\_CauseReg\_CE}{\sailMIPSvalUpdateCauseRegCE}{}% + \ifstrequal{#1}{\_update\_CauseReg\_ExcCode}{\sailMIPSvalUpdateCauseRegExcCode}{}% + \ifstrequal{#1}{\_update\_CauseReg\_IP}{\sailMIPSvalUpdateCauseRegIP}{}% + \ifstrequal{#1}{\_update\_CauseReg\_IV}{\sailMIPSvalUpdateCauseRegIV}{}% + \ifstrequal{#1}{\_update\_CauseReg\_WP}{\sailMIPSvalUpdateCauseRegWP}{}% + \ifstrequal{#1}{\_update\_CauseReg\_bits}{\sailMIPSvalUpdateCauseRegBits}{}% + \ifstrequal{#1}{\_update\_ContextReg\_BadVPN2}{\sailMIPSvalUpdateContextRegBadVPNTwo}{}% + \ifstrequal{#1}{\_update\_ContextReg\_PTEBase}{\sailMIPSvalUpdateContextRegPTEBase}{}% + \ifstrequal{#1}{\_update\_ContextReg\_bits}{\sailMIPSvalUpdateContextRegBits}{}% + \ifstrequal{#1}{\_update\_StatusReg\_BEV}{\sailMIPSvalUpdateStatusRegBEV}{}% + \ifstrequal{#1}{\_update\_StatusReg\_CU}{\sailMIPSvalUpdateStatusRegCU}{}% + \ifstrequal{#1}{\_update\_StatusReg\_ERL}{\sailMIPSvalUpdateStatusRegERL}{}% + \ifstrequal{#1}{\_update\_StatusReg\_EXL}{\sailMIPSvalUpdateStatusRegEXL}{}% + \ifstrequal{#1}{\_update\_StatusReg\_IE}{\sailMIPSvalUpdateStatusRegIE}{}% + \ifstrequal{#1}{\_update\_StatusReg\_IM}{\sailMIPSvalUpdateStatusRegIM}{}% + \ifstrequal{#1}{\_update\_StatusReg\_KSU}{\sailMIPSvalUpdateStatusRegKSU}{}% + \ifstrequal{#1}{\_update\_StatusReg\_KX}{\sailMIPSvalUpdateStatusRegKX}{}% + \ifstrequal{#1}{\_update\_StatusReg\_SX}{\sailMIPSvalUpdateStatusRegSX}{}% + \ifstrequal{#1}{\_update\_StatusReg\_UX}{\sailMIPSvalUpdateStatusRegUX}{}% + \ifstrequal{#1}{\_update\_StatusReg\_bits}{\sailMIPSvalUpdateStatusRegBits}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_ASID}{\sailMIPSvalUpdateTLBEntryHiRegASID}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_CLGK}{\sailMIPSvalUpdateTLBEntryHiRegCLGK}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_CLGS}{\sailMIPSvalUpdateTLBEntryHiRegCLGS}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_CLGU}{\sailMIPSvalUpdateTLBEntryHiRegCLGU}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_R}{\sailMIPSvalUpdateTLBEntryHiRegR}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_VPN2}{\sailMIPSvalUpdateTLBEntryHiRegVPNTwo}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_bits}{\sailMIPSvalUpdateTLBEntryHiRegBits}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_C}{\sailMIPSvalUpdateTLBEntryLoRegC}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_CapL}{\sailMIPSvalUpdateTLBEntryLoRegCapL}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_CapLG}{\sailMIPSvalUpdateTLBEntryLoRegCapLG}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_CapS}{\sailMIPSvalUpdateTLBEntryLoRegCapS}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_D}{\sailMIPSvalUpdateTLBEntryLoRegD}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_G}{\sailMIPSvalUpdateTLBEntryLoRegG}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_PFN}{\sailMIPSvalUpdateTLBEntryLoRegPFN}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_V}{\sailMIPSvalUpdateTLBEntryLoRegV}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_bits}{\sailMIPSvalUpdateTLBEntryLoRegBits}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_asid}{\sailMIPSvalUpdateTLBEntryAsid}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_bits}{\sailMIPSvalUpdateTLBEntryBits}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_c0}{\sailMIPSvalUpdateTLBEntryCZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_c1}{\sailMIPSvalUpdateTLBEntryCOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_capl0}{\sailMIPSvalUpdateTLBEntryCaplZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_capl1}{\sailMIPSvalUpdateTLBEntryCaplOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_caplg0}{\sailMIPSvalUpdateTLBEntryCaplgZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_caplg1}{\sailMIPSvalUpdateTLBEntryCaplgOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_caps0}{\sailMIPSvalUpdateTLBEntryCapsZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_caps1}{\sailMIPSvalUpdateTLBEntryCapsOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_d0}{\sailMIPSvalUpdateTLBEntryDZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_d1}{\sailMIPSvalUpdateTLBEntryDOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_g}{\sailMIPSvalUpdateTLBEntryG}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_pagemask}{\sailMIPSvalUpdateTLBEntryPagemask}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_pfn0}{\sailMIPSvalUpdateTLBEntryPfnZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_pfn1}{\sailMIPSvalUpdateTLBEntryPfnOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_r}{\sailMIPSvalUpdateTLBEntryR}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_v0}{\sailMIPSvalUpdateTLBEntryVZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_v1}{\sailMIPSvalUpdateTLBEntryVOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_valid}{\sailMIPSvalUpdateTLBEntryValid}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_vpn2}{\sailMIPSvalUpdateTLBEntryVpnTwo}{}% + \ifstrequal{#1}{\_update\_XContextReg\_XBadVPN2}{\sailMIPSvalUpdateXContextRegXBadVPNTwo}{}% + \ifstrequal{#1}{\_update\_XContextReg\_XPTEBase}{\sailMIPSvalUpdateXContextRegXPTEBase}{}% + \ifstrequal{#1}{\_update\_XContextReg\_XR}{\sailMIPSvalUpdateXContextRegXR}{}% + \ifstrequal{#1}{\_update\_XContextReg\_bits}{\sailMIPSvalUpdateXContextRegBits}{}% + \ifstrequal{#1}{abs\_int\_atom}{\sailMIPSvalabsIntAtom}{}% + \ifstrequal{#1}{abs\_int\_plain}{\sailMIPSvalabsIntPlain}{}% + \ifstrequal{#1}{add\_atom}{\sailMIPSvaladdAtom}{}% + \ifstrequal{#1}{add\_bits}{\sailMIPSvaladdBits}{}% + \ifstrequal{#1}{add\_bits\_int}{\sailMIPSvaladdBitsInt}{}% + \ifstrequal{#1}{add\_int}{\sailMIPSvaladdInt}{}% + \ifstrequal{#1}{add\_range}{\sailMIPSvaladdRange}{}% + \ifstrequal{#1}{add\_vec}{\sailMIPSvaladdVec}{}% + \ifstrequal{#1}{add\_vec\_int}{\sailMIPSvaladdVecInt}{}% + \ifstrequal{#1}{addrWrapper}{\sailMIPSvaladdrWrapper}{}% + \ifstrequal{#1}{addrWrapperUnaligned}{\sailMIPSvaladdrWrapperUnaligned}{}% + \ifstrequal{#1}{and\_bool}{\sailMIPSvalandBool}{}% + \ifstrequal{#1}{and\_bool\_no\_flow}{\sailMIPSvalandBoolNoFlow}{}% + \ifstrequal{#1}{and\_vec}{\sailMIPSvalandVec}{}% + \ifstrequal{#1}{append\_64}{\sailMIPSvalappendSixFour}{}% + \ifstrequal{#1}{assembly}{\sailMIPSvalassembly}{}% + \ifstrequal{#1}{bit\_to\_bool}{\sailMIPSvalbitToBool}{}% + \ifstrequal{#1}{bits\_str}{\sailMIPSvalbitsStr}{}% + \ifstrequal{#1}{bits\_to\_bool}{\sailMIPSvalbitsToBool}{}% + \ifstrequal{#1}{bitvector\_access}{\sailMIPSvalbitvectorAccess}{}% + \ifstrequal{#1}{bitvector\_concat}{\sailMIPSvalbitvectorConcat}{}% + \ifstrequal{#1}{bitvector\_length}{\sailMIPSvalbitvectorLength}{}% + \ifstrequal{#1}{bitvector\_update}{\sailMIPSvalbitvectorUpdate}{}% + \ifstrequal{#1}{bool\_to\_bit}{\sailMIPSvalboolToBit}{}% + \ifstrequal{#1}{bool\_to\_bits}{\sailMIPSvalboolToBits}{}% + \ifstrequal{#1}{capBitsToCapability}{\sailMIPSvalcapBitsToCapability}{}% + \ifstrequal{#1}{capBoundsEqual}{\sailMIPSvalcapBoundsEqual}{}% + \ifstrequal{#1}{capToBits}{\sailMIPSvalcapToBits}{}% + \ifstrequal{#1}{capToMemBits}{\sailMIPSvalcapToMemBits}{}% + \ifstrequal{#1}{capToString}{\sailMIPSvalcapToString}{}% + \ifstrequal{#1}{cast\_unit\_vec}{\sailMIPSvalcastUnitVec}{}% + \ifstrequal{#1}{checkCP0Access}{\sailMIPSvalcheckCPZeroAccess}{}% + \ifstrequal{#1}{checkCP0AccessHook}{\sailMIPSvalcheckCPZeroAccessHook}{}% + \ifstrequal{#1}{checkCP2usable}{\sailMIPSvalcheckCPTwousable}{}% + \ifstrequal{#1}{checkDDCPerms}{\sailMIPSvalcheckDDCPerms}{}% + \ifstrequal{#1}{compare}{\sailMIPSvalcompare}{}% + \ifstrequal{#1}{concat\_str}{\sailMIPSvalconcatStr}{}% + \ifstrequal{#1}{concat\_str\_bits}{\sailMIPSvalconcatStrBits}{}% + \ifstrequal{#1}{concat\_str\_dec}{\sailMIPSvalconcatStrDec}{}% + \ifstrequal{#1}{count\_leading\_zeros}{\sailMIPSvalcountLeadingZeros}{}% + \ifstrequal{#1}{cp2\_next\_pc}{\sailMIPSvalcpTwoNextPc}{}% + \ifstrequal{#1}{dec\_str}{\sailMIPSvaldecStr}{}% + \ifstrequal{#1}{decode}{\sailMIPSvaldecode}{}% + \ifstrequal{#1}{decode\_failure\_of\_num}{\sailMIPSvaldecodeFailureOfNum}{}% + \ifstrequal{#1}{dump\_cp2\_state}{\sailMIPSvaldumpCpTwoState}{}% + \ifstrequal{#1}{ediv\_int}{\sailMIPSvaledivInt}{}% + \ifstrequal{#1}{emod\_int}{\sailMIPSvalemodInt}{}% + \ifstrequal{#1}{eq\_anything}{\sailMIPSvaleqAnything}{}% + \ifstrequal{#1}{eq\_bit}{\sailMIPSvaleqBit}{}% + \ifstrequal{#1}{eq\_bit2}{\sailMIPSvaleqBitTwo}{}% + \ifstrequal{#1}{eq\_bits}{\sailMIPSvaleqBits}{}% + \ifstrequal{#1}{eq\_bool}{\sailMIPSvaleqBool}{}% + \ifstrequal{#1}{eq\_int}{\sailMIPSvaleqInt}{}% + \ifstrequal{#1}{eq\_string}{\sailMIPSvaleqString}{}% + \ifstrequal{#1}{eq\_unit}{\sailMIPSvaleqUnit}{}% + \ifstrequal{#1}{exceptionVectorBase}{\sailMIPSvalexceptionVectorBase}{}% + \ifstrequal{#1}{exceptionVectorOffset}{\sailMIPSvalexceptionVectorOffset}{}% + \ifstrequal{#1}{execute}{\sailMIPSvalexecute}{}% + \ifstrequal{#1}{execute\_branch}{\sailMIPSvalexecuteBranch}{}% + \ifstrequal{#1}{execute\_branch\_mips}{\sailMIPSvalexecuteBranchMips}{}% + \ifstrequal{#1}{execute\_branch\_pcc}{\sailMIPSvalexecuteBranchPcc}{}% + \ifstrequal{#1}{extendLoad}{\sailMIPSvalextendLoad}{}% + \ifstrequal{#1}{fdiv\_int}{\sailMIPSvalfdivInt}{}% + \ifstrequal{#1}{fmod\_int}{\sailMIPSvalfmodInt}{}% + \ifstrequal{#1}{getAccessLevel}{\sailMIPSvalgetAccessLevel}{}% + \ifstrequal{#1}{getCapBase}{\sailMIPSvalgetCapBase}{}% + \ifstrequal{#1}{getCapBounds}{\sailMIPSvalgetCapBounds}{}% + \ifstrequal{#1}{getCapCursor}{\sailMIPSvalgetCapCursor}{}% + \ifstrequal{#1}{getCapFlags}{\sailMIPSvalgetCapFlags}{}% + \ifstrequal{#1}{getCapHardPerms}{\sailMIPSvalgetCapHardPerms}{}% + \ifstrequal{#1}{getCapLength}{\sailMIPSvalgetCapLength}{}% + \ifstrequal{#1}{getCapOffset}{\sailMIPSvalgetCapOffset}{}% + \ifstrequal{#1}{getCapPerms}{\sailMIPSvalgetCapPerms}{}% + \ifstrequal{#1}{getCapTop}{\sailMIPSvalgetCapTop}{}% + \ifstrequal{#1}{getRepresentableAlignmentMask}{\sailMIPSvalgetRepresentableAlignmentMask}{}% + \ifstrequal{#1}{getRepresentableLength}{\sailMIPSvalgetRepresentableLength}{}% + \ifstrequal{#1}{get\_CP0EPC}{\sailMIPSvalgetCPZeroEPC}{}% + \ifstrequal{#1}{get\_CP0ErrorEPC}{\sailMIPSvalgetCPZeroErrorEPC}{}% + \ifstrequal{#1}{get\_slice\_int}{\sailMIPSvalgetSliceInt}{}% + \ifstrequal{#1}{get\_time\_ns}{\sailMIPSvalgetTimeNs}{}% + \ifstrequal{#1}{grantsAccess}{\sailMIPSvalgrantsAccess}{}% + \ifstrequal{#1}{gt\_int}{\sailMIPSvalgtInt}{}% + \ifstrequal{#1}{gteq\_int}{\sailMIPSvalgteqInt}{}% + \ifstrequal{#1}{hasReservedOType}{\sailMIPSvalhasReservedOType}{}% + \ifstrequal{#1}{hex\_str}{\sailMIPSvalhexStr}{}% + \ifstrequal{#1}{incCapOffset}{\sailMIPSvalincCapOffset}{}% + \ifstrequal{#1}{incrementCP0Count}{\sailMIPSvalincrementCPZeroCount}{}% + \ifstrequal{#1}{init\_cp0\_state}{\sailMIPSvalinitCpZeroState}{}% + \ifstrequal{#1}{init\_cp2\_state}{\sailMIPSvalinitCpTwoState}{}% + \ifstrequal{#1}{int\_of\_AccessLevel}{\sailMIPSvalintOfAccessLevel}{}% + \ifstrequal{#1}{int\_power}{\sailMIPSvalintPower}{}% + \ifstrequal{#1}{isAddressAligned}{\sailMIPSvalisAddressAligned}{}% + \ifstrequal{#1}{isSentryCap}{\sailMIPSvalisSentryCap}{}% + \ifstrequal{#1}{is\_none}{\sailMIPSvalisNone}{}% + \ifstrequal{#1}{is\_some}{\sailMIPSvalisSome}{}% + \ifstrequal{#1}{lt\_int}{\sailMIPSvalltInt}{}% + \ifstrequal{#1}{lteq\_int}{\sailMIPSvallteqInt}{}% + \ifstrequal{#1}{mask}{\sailMIPSvalmask}{}% + \ifstrequal{#1}{max\_atom}{\sailMIPSvalmaxAtom}{}% + \ifstrequal{#1}{max\_int}{\sailMIPSvalmaxInt}{}% + \ifstrequal{#1}{max\_nat}{\sailMIPSvalmaxNat}{}% + \ifstrequal{#1}{memBitsToCapability}{\sailMIPSvalmemBitsToCapability}{}% + \ifstrequal{#1}{min\_atom}{\sailMIPSvalminAtom}{}% + \ifstrequal{#1}{min\_int}{\sailMIPSvalminInt}{}% + \ifstrequal{#1}{min\_nat}{\sailMIPSvalminNat}{}% + \ifstrequal{#1}{mips\_sign\_extend}{\sailMIPSvalmipsSignExtend}{}% + \ifstrequal{#1}{mips\_zero\_extend}{\sailMIPSvalmipsZeroExtend}{}% + \ifstrequal{#1}{mult\_atom}{\sailMIPSvalmultAtom}{}% + \ifstrequal{#1}{mult\_int}{\sailMIPSvalmultInt}{}% + \ifstrequal{#1}{negate\_atom}{\sailMIPSvalnegateAtom}{}% + \ifstrequal{#1}{negate\_int}{\sailMIPSvalnegateInt}{}% + \ifstrequal{#1}{negate\_range}{\sailMIPSvalnegateRange}{}% + \ifstrequal{#1}{neq\_anything}{\sailMIPSvalneqAnything}{}% + \ifstrequal{#1}{neq\_bits}{\sailMIPSvalneqBits}{}% + \ifstrequal{#1}{neq\_bool}{\sailMIPSvalneqBool}{}% + \ifstrequal{#1}{neq\_int}{\sailMIPSvalneqInt}{}% + \ifstrequal{#1}{not\_bool}{\sailMIPSvalnotBool}{}% + \ifstrequal{#1}{not\_vec}{\sailMIPSvalnotVec}{}% + \ifstrequal{#1}{num\_of\_AccessLevel}{\sailMIPSvalnumOfAccessLevel}{}% + \ifstrequal{#1}{num\_of\_CPtrCmpOp}{\sailMIPSvalnumOfCPtrCmpOp}{}% + \ifstrequal{#1}{num\_of\_CapEx}{\sailMIPSvalnumOfCapEx}{}% + \ifstrequal{#1}{num\_of\_ClearRegSet}{\sailMIPSvalnumOfClearRegSet}{}% + \ifstrequal{#1}{num\_of\_Comparison}{\sailMIPSvalnumOfComparison}{}% + \ifstrequal{#1}{num\_of\_Exception}{\sailMIPSvalnumOfException}{}% + \ifstrequal{#1}{num\_of\_MemAccessCapRestriction}{\sailMIPSvalnumOfMemAccessCapRestriction}{}% + \ifstrequal{#1}{num\_of\_MemAccessType}{\sailMIPSvalnumOfMemAccessType}{}% + \ifstrequal{#1}{num\_of\_WordType}{\sailMIPSvalnumOfWordType}{}% + \ifstrequal{#1}{num\_of\_WordTypeUnaligned}{\sailMIPSvalnumOfWordTypeUnaligned}{}% + \ifstrequal{#1}{num\_of\_decode\_failure}{\sailMIPSvalnumOfDecodeFailure}{}% + \ifstrequal{#1}{ones\_implicit}{\sailMIPSvalonesImplicit}{}% + \ifstrequal{#1}{or\_bool}{\sailMIPSvalorBool}{}% + \ifstrequal{#1}{or\_vec}{\sailMIPSvalorVec}{}% + \ifstrequal{#1}{pcc\_access\_system\_regs}{\sailMIPSvalpccAccessSystemRegs}{}% + \ifstrequal{#1}{plain\_vector\_access}{\sailMIPSvalplainVectorAccess}{}% + \ifstrequal{#1}{plain\_vector\_update}{\sailMIPSvalplainVectorUpdate}{}% + \ifstrequal{#1}{pow2}{\sailMIPSvalpowTwo}{}% + \ifstrequal{#1}{prerr}{\sailMIPSvalprerr}{}% + \ifstrequal{#1}{prerr\_bits}{\sailMIPSvalprerrBits}{}% + \ifstrequal{#1}{prerr\_endline}{\sailMIPSvalprerrEndline}{}% + \ifstrequal{#1}{prerr\_int}{\sailMIPSvalprerrInt}{}% + \ifstrequal{#1}{print\_bits}{\sailMIPSvalprintBits}{}% + \ifstrequal{#1}{print\_endline}{\sailMIPSvalprintEndline}{}% + \ifstrequal{#1}{print\_int}{\sailMIPSvalprintInt}{}% + \ifstrequal{#1}{putchar}{\sailMIPSvalputchar}{}% + \ifstrequal{#1}{quot\_round\_zero}{\sailMIPSvalquotRoundZero}{}% + \ifstrequal{#1}{rGPR}{\sailMIPSvalrGPR}{}% + \ifstrequal{#1}{raise\_c2\_exception}{\sailMIPSvalraiseCTwoException}{}% + \ifstrequal{#1}{raise\_c2\_exception8}{\sailMIPSvalraiseCTwoExceptionEight}{}% + \ifstrequal{#1}{raise\_c2\_exception\_badaddr}{\sailMIPSvalraiseCTwoExceptionBadaddr}{}% + \ifstrequal{#1}{raise\_c2\_exception\_noreg}{\sailMIPSvalraiseCTwoExceptionNoreg}{}% + \ifstrequal{#1}{readCapReg}{\sailMIPSvalreadCapReg}{}% + \ifstrequal{#1}{readCapRegDDC}{\sailMIPSvalreadCapRegDDC}{}% + \ifstrequal{#1}{read\_tag\_bool}{\sailMIPSvalreadTagBool}{}% + \ifstrequal{#1}{rem\_round\_zero}{\sailMIPSvalremRoundZero}{}% + \ifstrequal{#1}{replicate\_bits}{\sailMIPSvalreplicateBits}{}% + \ifstrequal{#1}{reverse\_endianness}{\sailMIPSvalreverseEndianness}{}% + \ifstrequal{#1}{sail\_arith\_shiftright}{\sailMIPSvalsailArithShiftright}{}% + \ifstrequal{#1}{sail\_mask}{\sailMIPSvalsailMask}{}% + \ifstrequal{#1}{sail\_ones}{\sailMIPSvalsailOnes}{}% + \ifstrequal{#1}{sail\_shiftleft}{\sailMIPSvalsailShiftleft}{}% + \ifstrequal{#1}{sail\_shiftright}{\sailMIPSvalsailShiftright}{}% + \ifstrequal{#1}{sail\_sign\_extend}{\sailMIPSvalsailSignExtend}{}% + \ifstrequal{#1}{sail\_zero\_extend}{\sailMIPSvalsailZeroExtend}{}% + \ifstrequal{#1}{sail\_zeros}{\sailMIPSvalsailZeros}{}% + \ifstrequal{#1}{sealCap}{\sailMIPSvalsealCap}{}% + \ifstrequal{#1}{setCapAddr}{\sailMIPSvalsetCapAddr}{}% + \ifstrequal{#1}{setCapBounds}{\sailMIPSvalsetCapBounds}{}% + \ifstrequal{#1}{setCapFlags}{\sailMIPSvalsetCapFlags}{}% + \ifstrequal{#1}{setCapOffset}{\sailMIPSvalsetCapOffset}{}% + \ifstrequal{#1}{setCapPerms}{\sailMIPSvalsetCapPerms}{}% + \ifstrequal{#1}{set\_CP0EPC}{\sailMIPSvalsetCPZeroEPC}{}% + \ifstrequal{#1}{set\_CP0ErrorEPC}{\sailMIPSvalsetCPZeroErrorEPC}{}% + \ifstrequal{#1}{set\_next\_pcc}{\sailMIPSvalsetNextPcc}{}% + \ifstrequal{#1}{set\_slice\_bits}{\sailMIPSvalsetSliceBits}{}% + \ifstrequal{#1}{set\_slice\_int}{\sailMIPSvalsetSliceInt}{}% + \ifstrequal{#1}{shift\_bits\_left}{\sailMIPSvalshiftBitsLeft}{}% + \ifstrequal{#1}{shift\_bits\_right}{\sailMIPSvalshiftBitsRight}{}% + \ifstrequal{#1}{shiftl}{\sailMIPSvalshiftl}{}% + \ifstrequal{#1}{shiftr}{\sailMIPSvalshiftr}{}% + \ifstrequal{#1}{signed}{\sailMIPSvalsigned}{}% + \ifstrequal{#1}{skip\_barr}{\sailMIPSvalskipBarr}{}% + \ifstrequal{#1}{skip\_eamem}{\sailMIPSvalskipEamem}{}% + \ifstrequal{#1}{skip\_escape}{\sailMIPSvalskipEscape}{}% + \ifstrequal{#1}{skip\_rmemt}{\sailMIPSvalskipRmemt}{}% + \ifstrequal{#1}{skip\_rreg}{\sailMIPSvalskipRreg}{}% + \ifstrequal{#1}{skip\_wmvt}{\sailMIPSvalskipWmvt}{}% + \ifstrequal{#1}{skip\_wreg}{\sailMIPSvalskipWreg}{}% + \ifstrequal{#1}{slice}{\sailMIPSvalslice}{}% + \ifstrequal{#1}{slice\_mask}{\sailMIPSvalsliceMask}{}% + \ifstrequal{#1}{strCCArgs}{\sailMIPSvalstrCCArgs}{}% + \ifstrequal{#1}{strCCCArgs}{\sailMIPSvalstrCCCArgs}{}% + \ifstrequal{#1}{strCCIArgs}{\sailMIPSvalstrCCIArgs}{}% + \ifstrequal{#1}{strCCIUArgs}{\sailMIPSvalstrCCIUArgs}{}% + \ifstrequal{#1}{strCCRArgs}{\sailMIPSvalstrCCRArgs}{}% + \ifstrequal{#1}{strCRArgs}{\sailMIPSvalstrCRArgs}{}% + \ifstrequal{#1}{strCReg}{\sailMIPSvalstrCReg}{}% + \ifstrequal{#1}{strCmp}{\sailMIPSvalstrCmp}{}% + \ifstrequal{#1}{strMemArgs}{\sailMIPSvalstrMemArgs}{}% + \ifstrequal{#1}{strRCArgs}{\sailMIPSvalstrRCArgs}{}% + \ifstrequal{#1}{strRCCArgs}{\sailMIPSvalstrRCCArgs}{}% + \ifstrequal{#1}{strRCRArgs}{\sailMIPSvalstrRCRArgs}{}% + \ifstrequal{#1}{strRIArgs}{\sailMIPSvalstrRIArgs}{}% + \ifstrequal{#1}{strRRArgs}{\sailMIPSvalstrRRArgs}{}% + \ifstrequal{#1}{strRRIArgs}{\sailMIPSvalstrRRIArgs}{}% + \ifstrequal{#1}{strRRIUArgs}{\sailMIPSvalstrRRIUArgs}{}% + \ifstrequal{#1}{strRRRArgs}{\sailMIPSvalstrRRRArgs}{}% + \ifstrequal{#1}{strReg}{\sailMIPSvalstrReg}{}% + \ifstrequal{#1}{strWordType}{\sailMIPSvalstrWordType}{}% + \ifstrequal{#1}{string\_of\_capex}{\sailMIPSvalstringOfCapex}{}% + \ifstrequal{#1}{string\_of\_exception}{\sailMIPSvalstringOfException}{}% + \ifstrequal{#1}{string\_of\_int}{\sailMIPSvalstringOfInt}{}% + \ifstrequal{#1}{sub\_atom}{\sailMIPSvalsubAtom}{}% + \ifstrequal{#1}{sub\_bits}{\sailMIPSvalsubBits}{}% + \ifstrequal{#1}{sub\_int}{\sailMIPSvalsubInt}{}% + \ifstrequal{#1}{sub\_nat}{\sailMIPSvalsubNat}{}% + \ifstrequal{#1}{sub\_range}{\sailMIPSvalsubRange}{}% + \ifstrequal{#1}{sub\_vec}{\sailMIPSvalsubVec}{}% + \ifstrequal{#1}{sub\_vec\_int}{\sailMIPSvalsubVecInt}{}% + \ifstrequal{#1}{subrange\_bits}{\sailMIPSvalsubrangeBits}{}% + \ifstrequal{#1}{supported\_instructions}{\sailMIPSvalsupportedInstructions}{}% + \ifstrequal{#1}{tdiv\_int}{\sailMIPSvaltdivInt}{}% + \ifstrequal{#1}{tlbEntryMatch}{\sailMIPSvaltlbEntryMatch}{}% + \ifstrequal{#1}{tlbSearch}{\sailMIPSvaltlbSearch}{}% + \ifstrequal{#1}{to\_bits}{\sailMIPSvaltoBits}{}% + \ifstrequal{#1}{traceException}{\sailMIPSvaltraceException}{}% + \ifstrequal{#1}{truncate}{\sailMIPSvaltruncate}{}% + \ifstrequal{#1}{truncateLSB}{\sailMIPSvaltruncateLSB}{}% + \ifstrequal{#1}{unalignedBytesTouched}{\sailMIPSvalunalignedBytesTouched}{}% + \ifstrequal{#1}{unrepCap}{\sailMIPSvalunrepCap}{}% + \ifstrequal{#1}{unsealCap}{\sailMIPSvalunsealCap}{}% + \ifstrequal{#1}{unsigned}{\sailMIPSvalunsigned}{}% + \ifstrequal{#1}{updateBadInstr}{\sailMIPSvalupdateBadInstr}{}% + \ifstrequal{#1}{update\_subrange\_bits}{\sailMIPSvalupdateSubrangeBits}{}% + \ifstrequal{#1}{vector\_length}{\sailMIPSvalvectorLength}{}% + \ifstrequal{#1}{wGPR}{\sailMIPSvalwGPR}{}% + \ifstrequal{#1}{wordWidthBytes}{\sailMIPSvalwordWidthBytes}{}% + \ifstrequal{#1}{writeCapReg}{\sailMIPSvalwriteCapReg}{}% + \ifstrequal{#1}{write\_tag\_bool}{\sailMIPSvalwriteTagBool}{}% + \ifstrequal{#1}{xor\_vec}{\sailMIPSvalxorVec}{}% + \ifstrequal{#1}{zeros\_implicit}{\sailMIPSvalzzerosImplicit}{}% + \ifstrequal{#1}{(operator *\_s)}{\sailMIPSvalzEightoperatorzZerozASzNine}{}% + \ifstrequal{#1}{(operator *\_u)}{\sailMIPSvalzEightoperatorzZerozAUzNine}{}% + \ifstrequal{#1}{(operator $>$\_s)}{\sailMIPSvalzEightoperatorzZerozISzNine}{}% + \ifstrequal{#1}{(operator $>$\_u)}{\sailMIPSvalzEightoperatorzZerozIUzNine}{}% + \ifstrequal{#1}{(operator $$>$$=\_s)}{\sailMIPSvalzEightoperatorzZerozKzJSzNine}{}% + \ifstrequal{#1}{(operator $$>$$=\_u)}{\sailMIPSvalzEightoperatorzZerozKzJUzNine}{}% + \ifstrequal{#1}{(operator $$>$$$$>$$\_s)}{\sailMIPSvalzEightoperatorzZerozKzKSzNine}{}% + \ifstrequal{#1}{(operator ^^)}{\sailMIPSvalzEightoperatorzZerozQzQzNine}{}} + +\newcommand{\sailMIPSrefval}[2]{ + \ifstrequal{#1}{AccessLevel_of_num}{\hyperref[sailMIPSzAccessLevelzyofzynum]{#2}}{}% + \ifstrequal{#1}{BitStr}{\hyperref[sailMIPSzBitStr]{#2}}{}% + \ifstrequal{#1}{CPtrCmpOp_of_num}{\hyperref[sailMIPSzCPtrCmpOpzyofzynum]{#2}}{}% + \ifstrequal{#1}{CapExCode}{\hyperref[sailMIPSzCapExCode]{#2}}{}% + \ifstrequal{#1}{CapEx_of_num}{\hyperref[sailMIPSzCapExzyofzynum]{#2}}{}% + \ifstrequal{#1}{ClearRegSet_of_num}{\hyperref[sailMIPSzClearRegSetzyofzynum]{#2}}{}% + \ifstrequal{#1}{Comparison_of_num}{\hyperref[sailMIPSzComparisonzyofzynum]{#2}}{}% + \ifstrequal{#1}{ERETHook}{\hyperref[sailMIPSzERETHook]{#2}}{}% + \ifstrequal{#1}{ExceptionCode}{\hyperref[sailMIPSzExceptionCode]{#2}}{}% + \ifstrequal{#1}{Exception_of_num}{\hyperref[sailMIPSzExceptionzyofzynum]{#2}}{}% + \ifstrequal{#1}{MAX}{\hyperref[sailMIPSzMAX]{#2}}{}% + \ifstrequal{#1}{MEM_sync}{\hyperref[sailMIPSzMEMzysync]{#2}}{}% + \ifstrequal{#1}{MEMea}{\hyperref[sailMIPSzMEMea]{#2}}{}% + \ifstrequal{#1}{MEMea_conditional}{\hyperref[sailMIPSzMEMeazyconditional]{#2}}{}% + \ifstrequal{#1}{MEMr}{\hyperref[sailMIPSzMEMr]{#2}}{}% + \ifstrequal{#1}{MEMr_reserve}{\hyperref[sailMIPSzMEMrzyreserve]{#2}}{}% + \ifstrequal{#1}{MEMr_reserve_wrapper}{\hyperref[sailMIPSzMEMrzyreservezywrapper]{#2}}{}% + \ifstrequal{#1}{MEMr_tagged}{\hyperref[sailMIPSzMEMrzytagged]{#2}}{}% + \ifstrequal{#1}{MEMr_tagged_reserve}{\hyperref[sailMIPSzMEMrzytaggedzyreserve]{#2}}{}% + \ifstrequal{#1}{MEMr_wrapper}{\hyperref[sailMIPSzMEMrzywrapper]{#2}}{}% + \ifstrequal{#1}{MEMval}{\hyperref[sailMIPSzMEMval]{#2}}{}% + \ifstrequal{#1}{MEMval_conditional}{\hyperref[sailMIPSzMEMvalzyconditional]{#2}}{}% + \ifstrequal{#1}{MEMw_conditional_wrapper}{\hyperref[sailMIPSzMEMwzyconditionalzywrapper]{#2}}{}% + \ifstrequal{#1}{MEMw_tagged}{\hyperref[sailMIPSzMEMwzytagged]{#2}}{}% + \ifstrequal{#1}{MEMw_tagged_conditional}{\hyperref[sailMIPSzMEMwzytaggedzyconditional]{#2}}{}% + \ifstrequal{#1}{MEMw_wrapper}{\hyperref[sailMIPSzMEMwzywrapper]{#2}}{}% + \ifstrequal{#1}{MIPSSegmentOf}{\hyperref[sailMIPSzMIPSSegmentOf]{#2}}{}% + \ifstrequal{#1}{MemAccessCapRestriction_of_num}{\hyperref[sailMIPSzMemAccessCapRestrictionzyofzynum]{#2}}{}% + \ifstrequal{#1}{MemAccessType_of_num}{\hyperref[sailMIPSzMemAccessTypezyofzynum]{#2}}{}% + \ifstrequal{#1}{Mk_CapCauseReg}{\hyperref[sailMIPSzMkzyCapCauseReg]{#2}}{}% + \ifstrequal{#1}{Mk_CauseReg}{\hyperref[sailMIPSzMkzyCauseReg]{#2}}{}% + \ifstrequal{#1}{Mk_ContextReg}{\hyperref[sailMIPSzMkzyContextReg]{#2}}{}% + \ifstrequal{#1}{Mk_StatusReg}{\hyperref[sailMIPSzMkzyStatusReg]{#2}}{}% + \ifstrequal{#1}{Mk_TLBEntry}{\hyperref[sailMIPSzMkzyTLBEntry]{#2}}{}% + \ifstrequal{#1}{Mk_TLBEntryHiReg}{\hyperref[sailMIPSzMkzyTLBEntryHiReg]{#2}}{}% + \ifstrequal{#1}{Mk_TLBEntryLoReg}{\hyperref[sailMIPSzMkzyTLBEntryLoReg]{#2}}{}% + \ifstrequal{#1}{Mk_XContextReg}{\hyperref[sailMIPSzMkzyXContextReg]{#2}}{}% + \ifstrequal{#1}{NotWordVal}{\hyperref[sailMIPSzNotWordVal]{#2}}{}% + \ifstrequal{#1}{SignalException}{\hyperref[sailMIPSzSignalException]{#2}}{}% + \ifstrequal{#1}{SignalExceptionBadAddr}{\hyperref[sailMIPSzSignalExceptionBadAddr]{#2}}{}% + \ifstrequal{#1}{SignalExceptionTLB}{\hyperref[sailMIPSzSignalExceptionTLB]{#2}}{}% + \ifstrequal{#1}{TLBTranslate}{\hyperref[sailMIPSzTLBTranslate]{#2}}{}% + \ifstrequal{#1}{TLBTranslate2}{\hyperref[sailMIPSzTLBTranslate2]{#2}}{}% + \ifstrequal{#1}{TLBTranslateC}{\hyperref[sailMIPSzTLBTranslateC]{#2}}{}% + \ifstrequal{#1}{TranslatePC}{\hyperref[sailMIPSzTranslatePC]{#2}}{}% + \ifstrequal{#1}{WordTypeUnaligned_of_num}{\hyperref[sailMIPSzWordTypeUnalignedzyofzynum]{#2}}{}% + \ifstrequal{#1}{WordType_of_num}{\hyperref[sailMIPSzWordTypezyofzynum]{#2}}{}% + \ifstrequal{#1}{__MIPS_read}{\hyperref[sailMIPSzzyzyMIPSzyread]{#2}}{}% + \ifstrequal{#1}{__MIPS_write}{\hyperref[sailMIPSzzyzyMIPSzywrite]{#2}}{}% + \ifstrequal{#1}{__ReadRAM}{\hyperref[sailMIPSzzyzyReadRAM]{#2}}{}% + \ifstrequal{#1}{__WriteRAM}{\hyperref[sailMIPSzzyzyWriteRAM]{#2}}{}% + \ifstrequal{#1}{__bitfield_deref}{\hyperref[sailMIPSzzyzybitfieldzyderef]{#2}}{}% + \ifstrequal{#1}{__deref}{\hyperref[sailMIPSzzyzyderef]{#2}}{}% + \ifstrequal{#1}{__id}{\hyperref[sailMIPSzzyzyid]{#2}}{}% + \ifstrequal{#1}{_get_CapCauseReg_ExcCode}{\hyperref[sailMIPSzzygetzyCapCauseRegzyExcCode]{#2}}{}% + \ifstrequal{#1}{_get_CapCauseReg_RegNum}{\hyperref[sailMIPSzzygetzyCapCauseRegzyRegNum]{#2}}{}% + \ifstrequal{#1}{_get_CapCauseReg_bits}{\hyperref[sailMIPSzzygetzyCapCauseRegzybits]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_BD}{\hyperref[sailMIPSzzygetzyCauseRegzyBD]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_CE}{\hyperref[sailMIPSzzygetzyCauseRegzyCE]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_ExcCode}{\hyperref[sailMIPSzzygetzyCauseRegzyExcCode]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_IP}{\hyperref[sailMIPSzzygetzyCauseRegzyIP]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_IV}{\hyperref[sailMIPSzzygetzyCauseRegzyIV]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_WP}{\hyperref[sailMIPSzzygetzyCauseRegzyWP]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_bits}{\hyperref[sailMIPSzzygetzyCauseRegzybits]{#2}}{}% + \ifstrequal{#1}{_get_ContextReg_BadVPN2}{\hyperref[sailMIPSzzygetzyContextRegzyBadVPN2]{#2}}{}% + \ifstrequal{#1}{_get_ContextReg_PTEBase}{\hyperref[sailMIPSzzygetzyContextRegzyPTEBase]{#2}}{}% + \ifstrequal{#1}{_get_ContextReg_bits}{\hyperref[sailMIPSzzygetzyContextRegzybits]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_BEV}{\hyperref[sailMIPSzzygetzyStatusRegzyBEV]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_CU}{\hyperref[sailMIPSzzygetzyStatusRegzyCU]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_ERL}{\hyperref[sailMIPSzzygetzyStatusRegzyERL]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_EXL}{\hyperref[sailMIPSzzygetzyStatusRegzyEXL]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_IE}{\hyperref[sailMIPSzzygetzyStatusRegzyIE]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_IM}{\hyperref[sailMIPSzzygetzyStatusRegzyIM]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_KSU}{\hyperref[sailMIPSzzygetzyStatusRegzyKSU]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_KX}{\hyperref[sailMIPSzzygetzyStatusRegzyKX]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_SX}{\hyperref[sailMIPSzzygetzyStatusRegzySX]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_UX}{\hyperref[sailMIPSzzygetzyStatusRegzyUX]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_bits}{\hyperref[sailMIPSzzygetzyStatusRegzybits]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_ASID}{\hyperref[sailMIPSzzygetzyTLBEntryHiRegzyASID]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_CLGK}{\hyperref[sailMIPSzzygetzyTLBEntryHiRegzyCLGK]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_CLGS}{\hyperref[sailMIPSzzygetzyTLBEntryHiRegzyCLGS]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_CLGU}{\hyperref[sailMIPSzzygetzyTLBEntryHiRegzyCLGU]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_R}{\hyperref[sailMIPSzzygetzyTLBEntryHiRegzyR]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_VPN2}{\hyperref[sailMIPSzzygetzyTLBEntryHiRegzyVPN2]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_bits}{\hyperref[sailMIPSzzygetzyTLBEntryHiRegzybits]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_C}{\hyperref[sailMIPSzzygetzyTLBEntryLoRegzyC]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_CapL}{\hyperref[sailMIPSzzygetzyTLBEntryLoRegzyCapL]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_CapLG}{\hyperref[sailMIPSzzygetzyTLBEntryLoRegzyCapLG]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_CapS}{\hyperref[sailMIPSzzygetzyTLBEntryLoRegzyCapS]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_D}{\hyperref[sailMIPSzzygetzyTLBEntryLoRegzyD]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_G}{\hyperref[sailMIPSzzygetzyTLBEntryLoRegzyG]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_PFN}{\hyperref[sailMIPSzzygetzyTLBEntryLoRegzyPFN]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_V}{\hyperref[sailMIPSzzygetzyTLBEntryLoRegzyV]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_bits}{\hyperref[sailMIPSzzygetzyTLBEntryLoRegzybits]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_asid}{\hyperref[sailMIPSzzygetzyTLBEntryzyasid]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_bits}{\hyperref[sailMIPSzzygetzyTLBEntryzybits]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_c0}{\hyperref[sailMIPSzzygetzyTLBEntryzyc0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_c1}{\hyperref[sailMIPSzzygetzyTLBEntryzyc1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_capl0}{\hyperref[sailMIPSzzygetzyTLBEntryzycapl0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_capl1}{\hyperref[sailMIPSzzygetzyTLBEntryzycapl1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_caplg0}{\hyperref[sailMIPSzzygetzyTLBEntryzycaplg0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_caplg1}{\hyperref[sailMIPSzzygetzyTLBEntryzycaplg1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_caps0}{\hyperref[sailMIPSzzygetzyTLBEntryzycaps0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_caps1}{\hyperref[sailMIPSzzygetzyTLBEntryzycaps1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_d0}{\hyperref[sailMIPSzzygetzyTLBEntryzyd0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_d1}{\hyperref[sailMIPSzzygetzyTLBEntryzyd1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_g}{\hyperref[sailMIPSzzygetzyTLBEntryzyg]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_pagemask}{\hyperref[sailMIPSzzygetzyTLBEntryzypagemask]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_pfn0}{\hyperref[sailMIPSzzygetzyTLBEntryzypfn0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_pfn1}{\hyperref[sailMIPSzzygetzyTLBEntryzypfn1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_r}{\hyperref[sailMIPSzzygetzyTLBEntryzyr]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_v0}{\hyperref[sailMIPSzzygetzyTLBEntryzyv0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_v1}{\hyperref[sailMIPSzzygetzyTLBEntryzyv1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_valid}{\hyperref[sailMIPSzzygetzyTLBEntryzyvalid]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_vpn2}{\hyperref[sailMIPSzzygetzyTLBEntryzyvpn2]{#2}}{}% + \ifstrequal{#1}{_get_XContextReg_XBadVPN2}{\hyperref[sailMIPSzzygetzyXContextRegzyXBadVPN2]{#2}}{}% + \ifstrequal{#1}{_get_XContextReg_XPTEBase}{\hyperref[sailMIPSzzygetzyXContextRegzyXPTEBase]{#2}}{}% + \ifstrequal{#1}{_get_XContextReg_XR}{\hyperref[sailMIPSzzygetzyXContextRegzyXR]{#2}}{}% + \ifstrequal{#1}{_get_XContextReg_bits}{\hyperref[sailMIPSzzygetzyXContextRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_CapCauseReg_ExcCode}{\hyperref[sailMIPSzzysetzyCapCauseRegzyExcCode]{#2}}{}% + \ifstrequal{#1}{_set_CapCauseReg_RegNum}{\hyperref[sailMIPSzzysetzyCapCauseRegzyRegNum]{#2}}{}% + \ifstrequal{#1}{_set_CapCauseReg_bits}{\hyperref[sailMIPSzzysetzyCapCauseRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_BD}{\hyperref[sailMIPSzzysetzyCauseRegzyBD]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_CE}{\hyperref[sailMIPSzzysetzyCauseRegzyCE]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_ExcCode}{\hyperref[sailMIPSzzysetzyCauseRegzyExcCode]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_IP}{\hyperref[sailMIPSzzysetzyCauseRegzyIP]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_IV}{\hyperref[sailMIPSzzysetzyCauseRegzyIV]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_WP}{\hyperref[sailMIPSzzysetzyCauseRegzyWP]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_bits}{\hyperref[sailMIPSzzysetzyCauseRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_ContextReg_BadVPN2}{\hyperref[sailMIPSzzysetzyContextRegzyBadVPN2]{#2}}{}% + \ifstrequal{#1}{_set_ContextReg_PTEBase}{\hyperref[sailMIPSzzysetzyContextRegzyPTEBase]{#2}}{}% + \ifstrequal{#1}{_set_ContextReg_bits}{\hyperref[sailMIPSzzysetzyContextRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_BEV}{\hyperref[sailMIPSzzysetzyStatusRegzyBEV]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_CU}{\hyperref[sailMIPSzzysetzyStatusRegzyCU]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_ERL}{\hyperref[sailMIPSzzysetzyStatusRegzyERL]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_EXL}{\hyperref[sailMIPSzzysetzyStatusRegzyEXL]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_IE}{\hyperref[sailMIPSzzysetzyStatusRegzyIE]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_IM}{\hyperref[sailMIPSzzysetzyStatusRegzyIM]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_KSU}{\hyperref[sailMIPSzzysetzyStatusRegzyKSU]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_KX}{\hyperref[sailMIPSzzysetzyStatusRegzyKX]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_SX}{\hyperref[sailMIPSzzysetzyStatusRegzySX]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_UX}{\hyperref[sailMIPSzzysetzyStatusRegzyUX]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_bits}{\hyperref[sailMIPSzzysetzyStatusRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_ASID}{\hyperref[sailMIPSzzysetzyTLBEntryHiRegzyASID]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_CLGK}{\hyperref[sailMIPSzzysetzyTLBEntryHiRegzyCLGK]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_CLGS}{\hyperref[sailMIPSzzysetzyTLBEntryHiRegzyCLGS]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_CLGU}{\hyperref[sailMIPSzzysetzyTLBEntryHiRegzyCLGU]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_R}{\hyperref[sailMIPSzzysetzyTLBEntryHiRegzyR]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_VPN2}{\hyperref[sailMIPSzzysetzyTLBEntryHiRegzyVPN2]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_bits}{\hyperref[sailMIPSzzysetzyTLBEntryHiRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_C}{\hyperref[sailMIPSzzysetzyTLBEntryLoRegzyC]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_CapL}{\hyperref[sailMIPSzzysetzyTLBEntryLoRegzyCapL]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_CapLG}{\hyperref[sailMIPSzzysetzyTLBEntryLoRegzyCapLG]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_CapS}{\hyperref[sailMIPSzzysetzyTLBEntryLoRegzyCapS]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_D}{\hyperref[sailMIPSzzysetzyTLBEntryLoRegzyD]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_G}{\hyperref[sailMIPSzzysetzyTLBEntryLoRegzyG]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_PFN}{\hyperref[sailMIPSzzysetzyTLBEntryLoRegzyPFN]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_V}{\hyperref[sailMIPSzzysetzyTLBEntryLoRegzyV]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_bits}{\hyperref[sailMIPSzzysetzyTLBEntryLoRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_asid}{\hyperref[sailMIPSzzysetzyTLBEntryzyasid]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_bits}{\hyperref[sailMIPSzzysetzyTLBEntryzybits]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_c0}{\hyperref[sailMIPSzzysetzyTLBEntryzyc0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_c1}{\hyperref[sailMIPSzzysetzyTLBEntryzyc1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_capl0}{\hyperref[sailMIPSzzysetzyTLBEntryzycapl0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_capl1}{\hyperref[sailMIPSzzysetzyTLBEntryzycapl1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_caplg0}{\hyperref[sailMIPSzzysetzyTLBEntryzycaplg0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_caplg1}{\hyperref[sailMIPSzzysetzyTLBEntryzycaplg1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_caps0}{\hyperref[sailMIPSzzysetzyTLBEntryzycaps0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_caps1}{\hyperref[sailMIPSzzysetzyTLBEntryzycaps1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_d0}{\hyperref[sailMIPSzzysetzyTLBEntryzyd0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_d1}{\hyperref[sailMIPSzzysetzyTLBEntryzyd1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_g}{\hyperref[sailMIPSzzysetzyTLBEntryzyg]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_pagemask}{\hyperref[sailMIPSzzysetzyTLBEntryzypagemask]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_pfn0}{\hyperref[sailMIPSzzysetzyTLBEntryzypfn0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_pfn1}{\hyperref[sailMIPSzzysetzyTLBEntryzypfn1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_r}{\hyperref[sailMIPSzzysetzyTLBEntryzyr]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_v0}{\hyperref[sailMIPSzzysetzyTLBEntryzyv0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_v1}{\hyperref[sailMIPSzzysetzyTLBEntryzyv1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_valid}{\hyperref[sailMIPSzzysetzyTLBEntryzyvalid]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_vpn2}{\hyperref[sailMIPSzzysetzyTLBEntryzyvpn2]{#2}}{}% + \ifstrequal{#1}{_set_XContextReg_XBadVPN2}{\hyperref[sailMIPSzzysetzyXContextRegzyXBadVPN2]{#2}}{}% + \ifstrequal{#1}{_set_XContextReg_XPTEBase}{\hyperref[sailMIPSzzysetzyXContextRegzyXPTEBase]{#2}}{}% + \ifstrequal{#1}{_set_XContextReg_XR}{\hyperref[sailMIPSzzysetzyXContextRegzyXR]{#2}}{}% + \ifstrequal{#1}{_set_XContextReg_bits}{\hyperref[sailMIPSzzysetzyXContextRegzybits]{#2}}{}% + \ifstrequal{#1}{_shl1}{\hyperref[sailMIPSzzyshl1]{#2}}{}% + \ifstrequal{#1}{_shl32}{\hyperref[sailMIPSzzyshl32]{#2}}{}% + \ifstrequal{#1}{_shl8}{\hyperref[sailMIPSzzyshl8]{#2}}{}% + \ifstrequal{#1}{_shl_int}{\hyperref[sailMIPSzzyshlzyint]{#2}}{}% + \ifstrequal{#1}{_shr32}{\hyperref[sailMIPSzzyshr32]{#2}}{}% + \ifstrequal{#1}{_shr_int}{\hyperref[sailMIPSzzyshrzyint]{#2}}{}% + \ifstrequal{#1}{_tmod_int}{\hyperref[sailMIPSzzytmodzyint]{#2}}{}% + \ifstrequal{#1}{_tmod_int_positive}{\hyperref[sailMIPSzzytmodzyintzypositive]{#2}}{}% + \ifstrequal{#1}{_update_CapCauseReg_ExcCode}{\hyperref[sailMIPSzzyupdatezyCapCauseRegzyExcCode]{#2}}{}% + \ifstrequal{#1}{_update_CapCauseReg_RegNum}{\hyperref[sailMIPSzzyupdatezyCapCauseRegzyRegNum]{#2}}{}% + \ifstrequal{#1}{_update_CapCauseReg_bits}{\hyperref[sailMIPSzzyupdatezyCapCauseRegzybits]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_BD}{\hyperref[sailMIPSzzyupdatezyCauseRegzyBD]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_CE}{\hyperref[sailMIPSzzyupdatezyCauseRegzyCE]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_ExcCode}{\hyperref[sailMIPSzzyupdatezyCauseRegzyExcCode]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_IP}{\hyperref[sailMIPSzzyupdatezyCauseRegzyIP]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_IV}{\hyperref[sailMIPSzzyupdatezyCauseRegzyIV]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_WP}{\hyperref[sailMIPSzzyupdatezyCauseRegzyWP]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_bits}{\hyperref[sailMIPSzzyupdatezyCauseRegzybits]{#2}}{}% + \ifstrequal{#1}{_update_ContextReg_BadVPN2}{\hyperref[sailMIPSzzyupdatezyContextRegzyBadVPN2]{#2}}{}% + \ifstrequal{#1}{_update_ContextReg_PTEBase}{\hyperref[sailMIPSzzyupdatezyContextRegzyPTEBase]{#2}}{}% + \ifstrequal{#1}{_update_ContextReg_bits}{\hyperref[sailMIPSzzyupdatezyContextRegzybits]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_BEV}{\hyperref[sailMIPSzzyupdatezyStatusRegzyBEV]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_CU}{\hyperref[sailMIPSzzyupdatezyStatusRegzyCU]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_ERL}{\hyperref[sailMIPSzzyupdatezyStatusRegzyERL]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_EXL}{\hyperref[sailMIPSzzyupdatezyStatusRegzyEXL]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_IE}{\hyperref[sailMIPSzzyupdatezyStatusRegzyIE]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_IM}{\hyperref[sailMIPSzzyupdatezyStatusRegzyIM]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_KSU}{\hyperref[sailMIPSzzyupdatezyStatusRegzyKSU]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_KX}{\hyperref[sailMIPSzzyupdatezyStatusRegzyKX]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_SX}{\hyperref[sailMIPSzzyupdatezyStatusRegzySX]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_UX}{\hyperref[sailMIPSzzyupdatezyStatusRegzyUX]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_bits}{\hyperref[sailMIPSzzyupdatezyStatusRegzybits]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_ASID}{\hyperref[sailMIPSzzyupdatezyTLBEntryHiRegzyASID]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_CLGK}{\hyperref[sailMIPSzzyupdatezyTLBEntryHiRegzyCLGK]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_CLGS}{\hyperref[sailMIPSzzyupdatezyTLBEntryHiRegzyCLGS]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_CLGU}{\hyperref[sailMIPSzzyupdatezyTLBEntryHiRegzyCLGU]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_R}{\hyperref[sailMIPSzzyupdatezyTLBEntryHiRegzyR]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_VPN2}{\hyperref[sailMIPSzzyupdatezyTLBEntryHiRegzyVPN2]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_bits}{\hyperref[sailMIPSzzyupdatezyTLBEntryHiRegzybits]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_C}{\hyperref[sailMIPSzzyupdatezyTLBEntryLoRegzyC]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_CapL}{\hyperref[sailMIPSzzyupdatezyTLBEntryLoRegzyCapL]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_CapLG}{\hyperref[sailMIPSzzyupdatezyTLBEntryLoRegzyCapLG]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_CapS}{\hyperref[sailMIPSzzyupdatezyTLBEntryLoRegzyCapS]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_D}{\hyperref[sailMIPSzzyupdatezyTLBEntryLoRegzyD]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_G}{\hyperref[sailMIPSzzyupdatezyTLBEntryLoRegzyG]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_PFN}{\hyperref[sailMIPSzzyupdatezyTLBEntryLoRegzyPFN]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_V}{\hyperref[sailMIPSzzyupdatezyTLBEntryLoRegzyV]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_bits}{\hyperref[sailMIPSzzyupdatezyTLBEntryLoRegzybits]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_asid}{\hyperref[sailMIPSzzyupdatezyTLBEntryzyasid]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_bits}{\hyperref[sailMIPSzzyupdatezyTLBEntryzybits]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_c0}{\hyperref[sailMIPSzzyupdatezyTLBEntryzyc0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_c1}{\hyperref[sailMIPSzzyupdatezyTLBEntryzyc1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_capl0}{\hyperref[sailMIPSzzyupdatezyTLBEntryzycapl0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_capl1}{\hyperref[sailMIPSzzyupdatezyTLBEntryzycapl1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_caplg0}{\hyperref[sailMIPSzzyupdatezyTLBEntryzycaplg0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_caplg1}{\hyperref[sailMIPSzzyupdatezyTLBEntryzycaplg1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_caps0}{\hyperref[sailMIPSzzyupdatezyTLBEntryzycaps0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_caps1}{\hyperref[sailMIPSzzyupdatezyTLBEntryzycaps1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_d0}{\hyperref[sailMIPSzzyupdatezyTLBEntryzyd0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_d1}{\hyperref[sailMIPSzzyupdatezyTLBEntryzyd1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_g}{\hyperref[sailMIPSzzyupdatezyTLBEntryzyg]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_pagemask}{\hyperref[sailMIPSzzyupdatezyTLBEntryzypagemask]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_pfn0}{\hyperref[sailMIPSzzyupdatezyTLBEntryzypfn0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_pfn1}{\hyperref[sailMIPSzzyupdatezyTLBEntryzypfn1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_r}{\hyperref[sailMIPSzzyupdatezyTLBEntryzyr]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_v0}{\hyperref[sailMIPSzzyupdatezyTLBEntryzyv0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_v1}{\hyperref[sailMIPSzzyupdatezyTLBEntryzyv1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_valid}{\hyperref[sailMIPSzzyupdatezyTLBEntryzyvalid]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_vpn2}{\hyperref[sailMIPSzzyupdatezyTLBEntryzyvpn2]{#2}}{}% + \ifstrequal{#1}{_update_XContextReg_XBadVPN2}{\hyperref[sailMIPSzzyupdatezyXContextRegzyXBadVPN2]{#2}}{}% + \ifstrequal{#1}{_update_XContextReg_XPTEBase}{\hyperref[sailMIPSzzyupdatezyXContextRegzyXPTEBase]{#2}}{}% + \ifstrequal{#1}{_update_XContextReg_XR}{\hyperref[sailMIPSzzyupdatezyXContextRegzyXR]{#2}}{}% + \ifstrequal{#1}{_update_XContextReg_bits}{\hyperref[sailMIPSzzyupdatezyXContextRegzybits]{#2}}{}% + \ifstrequal{#1}{abs_int_atom}{\hyperref[sailMIPSzabszyintzyatom]{#2}}{}% + \ifstrequal{#1}{abs_int_plain}{\hyperref[sailMIPSzabszyintzyplain]{#2}}{}% + \ifstrequal{#1}{add_atom}{\hyperref[sailMIPSzaddzyatom]{#2}}{}% + \ifstrequal{#1}{add_bits}{\hyperref[sailMIPSzaddzybits]{#2}}{}% + \ifstrequal{#1}{add_bits_int}{\hyperref[sailMIPSzaddzybitszyint]{#2}}{}% + \ifstrequal{#1}{add_int}{\hyperref[sailMIPSzaddzyint]{#2}}{}% + \ifstrequal{#1}{add_range}{\hyperref[sailMIPSzaddzyrange]{#2}}{}% + \ifstrequal{#1}{add_vec}{\hyperref[sailMIPSzaddzyvec]{#2}}{}% + \ifstrequal{#1}{add_vec_int}{\hyperref[sailMIPSzaddzyveczyint]{#2}}{}% + \ifstrequal{#1}{addrWrapper}{\hyperref[sailMIPSzaddrWrapper]{#2}}{}% + \ifstrequal{#1}{addrWrapperUnaligned}{\hyperref[sailMIPSzaddrWrapperUnaligned]{#2}}{}% + \ifstrequal{#1}{and_bool}{\hyperref[sailMIPSzandzybool]{#2}}{}% + \ifstrequal{#1}{and_bool_no_flow}{\hyperref[sailMIPSzandzyboolzynozyflow]{#2}}{}% + \ifstrequal{#1}{and_vec}{\hyperref[sailMIPSzandzyvec]{#2}}{}% + \ifstrequal{#1}{append_64}{\hyperref[sailMIPSzappendzy64]{#2}}{}% + \ifstrequal{#1}{assembly}{\hyperref[sailMIPSzassembly]{#2}}{}% + \ifstrequal{#1}{bit_to_bool}{\hyperref[sailMIPSzbitzytozybool]{#2}}{}% + \ifstrequal{#1}{bits_str}{\hyperref[sailMIPSzbitszystr]{#2}}{}% + \ifstrequal{#1}{bits_to_bool}{\hyperref[sailMIPSzbitszytozybool]{#2}}{}% + \ifstrequal{#1}{bitvector_access}{\hyperref[sailMIPSzbitvectorzyaccess]{#2}}{}% + \ifstrequal{#1}{bitvector_concat}{\hyperref[sailMIPSzbitvectorzyconcat]{#2}}{}% + \ifstrequal{#1}{bitvector_length}{\hyperref[sailMIPSzbitvectorzylength]{#2}}{}% + \ifstrequal{#1}{bitvector_update}{\hyperref[sailMIPSzbitvectorzyupdate]{#2}}{}% + \ifstrequal{#1}{bool_to_bit}{\hyperref[sailMIPSzboolzytozybit]{#2}}{}% + \ifstrequal{#1}{bool_to_bits}{\hyperref[sailMIPSzboolzytozybits]{#2}}{}% + \ifstrequal{#1}{capBitsToCapability}{\hyperref[sailMIPSzcapBitsToCapability]{#2}}{}% + \ifstrequal{#1}{capBoundsEqual}{\hyperref[sailMIPSzcapBoundsEqual]{#2}}{}% + \ifstrequal{#1}{capToBits}{\hyperref[sailMIPSzcapToBits]{#2}}{}% + \ifstrequal{#1}{capToMemBits}{\hyperref[sailMIPSzcapToMemBits]{#2}}{}% + \ifstrequal{#1}{capToString}{\hyperref[sailMIPSzcapToString]{#2}}{}% + \ifstrequal{#1}{cast_unit_vec}{\hyperref[sailMIPSzcastzyunitzyvec]{#2}}{}% + \ifstrequal{#1}{checkCP0Access}{\hyperref[sailMIPSzcheckCP0Access]{#2}}{}% + \ifstrequal{#1}{checkCP0AccessHook}{\hyperref[sailMIPSzcheckCP0AccessHook]{#2}}{}% + \ifstrequal{#1}{checkCP2usable}{\hyperref[sailMIPSzcheckCP2usable]{#2}}{}% + \ifstrequal{#1}{checkDDCPerms}{\hyperref[sailMIPSzcheckDDCPerms]{#2}}{}% + \ifstrequal{#1}{compare}{\hyperref[sailMIPSzcompare]{#2}}{}% + \ifstrequal{#1}{concat_str}{\hyperref[sailMIPSzconcatzystr]{#2}}{}% + \ifstrequal{#1}{concat_str_bits}{\hyperref[sailMIPSzconcatzystrzybits]{#2}}{}% + \ifstrequal{#1}{concat_str_dec}{\hyperref[sailMIPSzconcatzystrzydec]{#2}}{}% + \ifstrequal{#1}{count_leading_zeros}{\hyperref[sailMIPSzcountzyleadingzyzzeros]{#2}}{}% + \ifstrequal{#1}{cp2_next_pc}{\hyperref[sailMIPSzcp2zynextzypc]{#2}}{}% + \ifstrequal{#1}{dec_str}{\hyperref[sailMIPSzdeczystr]{#2}}{}% + \ifstrequal{#1}{decode}{\hyperref[sailMIPSzdecode]{#2}}{}% + \ifstrequal{#1}{decode_failure_of_num}{\hyperref[sailMIPSzdecodezyfailurezyofzynum]{#2}}{}% + \ifstrequal{#1}{dump_cp2_state}{\hyperref[sailMIPSzdumpzycp2zystate]{#2}}{}% + \ifstrequal{#1}{ediv_int}{\hyperref[sailMIPSzedivzyint]{#2}}{}% + \ifstrequal{#1}{emod_int}{\hyperref[sailMIPSzemodzyint]{#2}}{}% + \ifstrequal{#1}{eq_anything}{\hyperref[sailMIPSzeqzyanything]{#2}}{}% + \ifstrequal{#1}{eq_bit}{\hyperref[sailMIPSzeqzybit]{#2}}{}% + \ifstrequal{#1}{eq_bit2}{\hyperref[sailMIPSzeqzybit2]{#2}}{}% + \ifstrequal{#1}{eq_bits}{\hyperref[sailMIPSzeqzybits]{#2}}{}% + \ifstrequal{#1}{eq_bool}{\hyperref[sailMIPSzeqzybool]{#2}}{}% + \ifstrequal{#1}{eq_int}{\hyperref[sailMIPSzeqzyint]{#2}}{}% + \ifstrequal{#1}{eq_string}{\hyperref[sailMIPSzeqzystring]{#2}}{}% + \ifstrequal{#1}{eq_unit}{\hyperref[sailMIPSzeqzyunit]{#2}}{}% + \ifstrequal{#1}{exceptionVectorBase}{\hyperref[sailMIPSzexceptionVectorBase]{#2}}{}% + \ifstrequal{#1}{exceptionVectorOffset}{\hyperref[sailMIPSzexceptionVectorOffset]{#2}}{}% + \ifstrequal{#1}{execute}{\hyperref[sailMIPSzexecute]{#2}}{}% + \ifstrequal{#1}{execute_branch}{\hyperref[sailMIPSzexecutezybranch]{#2}}{}% + \ifstrequal{#1}{execute_branch_mips}{\hyperref[sailMIPSzexecutezybranchzymips]{#2}}{}% + \ifstrequal{#1}{execute_branch_pcc}{\hyperref[sailMIPSzexecutezybranchzypcc]{#2}}{}% + \ifstrequal{#1}{extendLoad}{\hyperref[sailMIPSzextendLoad]{#2}}{}% + \ifstrequal{#1}{fdiv_int}{\hyperref[sailMIPSzfdivzyint]{#2}}{}% + \ifstrequal{#1}{fmod_int}{\hyperref[sailMIPSzfmodzyint]{#2}}{}% + \ifstrequal{#1}{getAccessLevel}{\hyperref[sailMIPSzgetAccessLevel]{#2}}{}% + \ifstrequal{#1}{getCapBase}{\hyperref[sailMIPSzgetCapBase]{#2}}{}% + \ifstrequal{#1}{getCapBounds}{\hyperref[sailMIPSzgetCapBounds]{#2}}{}% + \ifstrequal{#1}{getCapCursor}{\hyperref[sailMIPSzgetCapCursor]{#2}}{}% + \ifstrequal{#1}{getCapFlags}{\hyperref[sailMIPSzgetCapFlags]{#2}}{}% + \ifstrequal{#1}{getCapHardPerms}{\hyperref[sailMIPSzgetCapHardPerms]{#2}}{}% + \ifstrequal{#1}{getCapLength}{\hyperref[sailMIPSzgetCapLength]{#2}}{}% + \ifstrequal{#1}{getCapOffset}{\hyperref[sailMIPSzgetCapOffset]{#2}}{}% + \ifstrequal{#1}{getCapPerms}{\hyperref[sailMIPSzgetCapPerms]{#2}}{}% + \ifstrequal{#1}{getCapTop}{\hyperref[sailMIPSzgetCapTop]{#2}}{}% + \ifstrequal{#1}{getRepresentableAlignmentMask}{\hyperref[sailMIPSzgetRepresentableAlignmentMask]{#2}}{}% + \ifstrequal{#1}{getRepresentableLength}{\hyperref[sailMIPSzgetRepresentableLength]{#2}}{}% + \ifstrequal{#1}{get_CP0EPC}{\hyperref[sailMIPSzgetzyCP0EPC]{#2}}{}% + \ifstrequal{#1}{get_CP0ErrorEPC}{\hyperref[sailMIPSzgetzyCP0ErrorEPC]{#2}}{}% + \ifstrequal{#1}{get_slice_int}{\hyperref[sailMIPSzgetzyslicezyint]{#2}}{}% + \ifstrequal{#1}{get_time_ns}{\hyperref[sailMIPSzgetzytimezyns]{#2}}{}% + \ifstrequal{#1}{grantsAccess}{\hyperref[sailMIPSzgrantsAccess]{#2}}{}% + \ifstrequal{#1}{gt_int}{\hyperref[sailMIPSzgtzyint]{#2}}{}% + \ifstrequal{#1}{gteq_int}{\hyperref[sailMIPSzgteqzyint]{#2}}{}% + \ifstrequal{#1}{hasReservedOType}{\hyperref[sailMIPSzhasReservedOType]{#2}}{}% + \ifstrequal{#1}{hex_str}{\hyperref[sailMIPSzhexzystr]{#2}}{}% + \ifstrequal{#1}{incCapOffset}{\hyperref[sailMIPSzincCapOffset]{#2}}{}% + \ifstrequal{#1}{incrementCP0Count}{\hyperref[sailMIPSzincrementCP0Count]{#2}}{}% + \ifstrequal{#1}{init_cp0_state}{\hyperref[sailMIPSzinitzycp0zystate]{#2}}{}% + \ifstrequal{#1}{init_cp2_state}{\hyperref[sailMIPSzinitzycp2zystate]{#2}}{}% + \ifstrequal{#1}{int_of_AccessLevel}{\hyperref[sailMIPSzintzyofzyAccessLevel]{#2}}{}% + \ifstrequal{#1}{int_power}{\hyperref[sailMIPSzintzypower]{#2}}{}% + \ifstrequal{#1}{isAddressAligned}{\hyperref[sailMIPSzisAddressAligned]{#2}}{}% + \ifstrequal{#1}{isSentryCap}{\hyperref[sailMIPSzisSentryCap]{#2}}{}% + \ifstrequal{#1}{is_none}{\hyperref[sailMIPSziszynone]{#2}}{}% + \ifstrequal{#1}{is_some}{\hyperref[sailMIPSziszysome]{#2}}{}% + \ifstrequal{#1}{lt_int}{\hyperref[sailMIPSzltzyint]{#2}}{}% + \ifstrequal{#1}{lteq_int}{\hyperref[sailMIPSzlteqzyint]{#2}}{}% + \ifstrequal{#1}{mask}{\hyperref[sailMIPSzmask]{#2}}{}% + \ifstrequal{#1}{max_atom}{\hyperref[sailMIPSzmaxzyatom]{#2}}{}% + \ifstrequal{#1}{max_int}{\hyperref[sailMIPSzmaxzyint]{#2}}{}% + \ifstrequal{#1}{max_nat}{\hyperref[sailMIPSzmaxzynat]{#2}}{}% + \ifstrequal{#1}{memBitsToCapability}{\hyperref[sailMIPSzmemBitsToCapability]{#2}}{}% + \ifstrequal{#1}{min_atom}{\hyperref[sailMIPSzminzyatom]{#2}}{}% + \ifstrequal{#1}{min_int}{\hyperref[sailMIPSzminzyint]{#2}}{}% + \ifstrequal{#1}{min_nat}{\hyperref[sailMIPSzminzynat]{#2}}{}% + \ifstrequal{#1}{mips_sign_extend}{\hyperref[sailMIPSzmipszysignzyextend]{#2}}{}% + \ifstrequal{#1}{mips_zero_extend}{\hyperref[sailMIPSzmipszyzzerozyextend]{#2}}{}% + \ifstrequal{#1}{mult_atom}{\hyperref[sailMIPSzmultzyatom]{#2}}{}% + \ifstrequal{#1}{mult_int}{\hyperref[sailMIPSzmultzyint]{#2}}{}% + \ifstrequal{#1}{negate_atom}{\hyperref[sailMIPSznegatezyatom]{#2}}{}% + \ifstrequal{#1}{negate_int}{\hyperref[sailMIPSznegatezyint]{#2}}{}% + \ifstrequal{#1}{negate_range}{\hyperref[sailMIPSznegatezyrange]{#2}}{}% + \ifstrequal{#1}{neq_anything}{\hyperref[sailMIPSzneqzyanything]{#2}}{}% + \ifstrequal{#1}{neq_bits}{\hyperref[sailMIPSzneqzybits]{#2}}{}% + \ifstrequal{#1}{neq_bool}{\hyperref[sailMIPSzneqzybool]{#2}}{}% + \ifstrequal{#1}{neq_int}{\hyperref[sailMIPSzneqzyint]{#2}}{}% + \ifstrequal{#1}{not_bool}{\hyperref[sailMIPSznotzybool]{#2}}{}% + \ifstrequal{#1}{not_vec}{\hyperref[sailMIPSznotzyvec]{#2}}{}% + \ifstrequal{#1}{num_of_AccessLevel}{\hyperref[sailMIPSznumzyofzyAccessLevel]{#2}}{}% + \ifstrequal{#1}{num_of_CPtrCmpOp}{\hyperref[sailMIPSznumzyofzyCPtrCmpOp]{#2}}{}% + \ifstrequal{#1}{num_of_CapEx}{\hyperref[sailMIPSznumzyofzyCapEx]{#2}}{}% + \ifstrequal{#1}{num_of_ClearRegSet}{\hyperref[sailMIPSznumzyofzyClearRegSet]{#2}}{}% + \ifstrequal{#1}{num_of_Comparison}{\hyperref[sailMIPSznumzyofzyComparison]{#2}}{}% + \ifstrequal{#1}{num_of_Exception}{\hyperref[sailMIPSznumzyofzyException]{#2}}{}% + \ifstrequal{#1}{num_of_MemAccessCapRestriction}{\hyperref[sailMIPSznumzyofzyMemAccessCapRestriction]{#2}}{}% + \ifstrequal{#1}{num_of_MemAccessType}{\hyperref[sailMIPSznumzyofzyMemAccessType]{#2}}{}% + \ifstrequal{#1}{num_of_WordType}{\hyperref[sailMIPSznumzyofzyWordType]{#2}}{}% + \ifstrequal{#1}{num_of_WordTypeUnaligned}{\hyperref[sailMIPSznumzyofzyWordTypeUnaligned]{#2}}{}% + \ifstrequal{#1}{num_of_decode_failure}{\hyperref[sailMIPSznumzyofzydecodezyfailure]{#2}}{}% + \ifstrequal{#1}{ones_implicit}{\hyperref[sailMIPSzoneszyimplicit]{#2}}{}% + \ifstrequal{#1}{or_bool}{\hyperref[sailMIPSzorzybool]{#2}}{}% + \ifstrequal{#1}{or_vec}{\hyperref[sailMIPSzorzyvec]{#2}}{}% + \ifstrequal{#1}{pcc_access_system_regs}{\hyperref[sailMIPSzpcczyaccesszysystemzyregs]{#2}}{}% + \ifstrequal{#1}{plain_vector_access}{\hyperref[sailMIPSzplainzyvectorzyaccess]{#2}}{}% + \ifstrequal{#1}{plain_vector_update}{\hyperref[sailMIPSzplainzyvectorzyupdate]{#2}}{}% + \ifstrequal{#1}{pow2}{\hyperref[sailMIPSzpow2]{#2}}{}% + \ifstrequal{#1}{prerr}{\hyperref[sailMIPSzprerr]{#2}}{}% + \ifstrequal{#1}{prerr_bits}{\hyperref[sailMIPSzprerrzybits]{#2}}{}% + \ifstrequal{#1}{prerr_endline}{\hyperref[sailMIPSzprerrzyendline]{#2}}{}% + \ifstrequal{#1}{prerr_int}{\hyperref[sailMIPSzprerrzyint]{#2}}{}% + \ifstrequal{#1}{print_bits}{\hyperref[sailMIPSzprintzybits]{#2}}{}% + \ifstrequal{#1}{print_endline}{\hyperref[sailMIPSzprintzyendline]{#2}}{}% + \ifstrequal{#1}{print_int}{\hyperref[sailMIPSzprintzyint]{#2}}{}% + \ifstrequal{#1}{putchar}{\hyperref[sailMIPSzputchar]{#2}}{}% + \ifstrequal{#1}{quot_round_zero}{\hyperref[sailMIPSzquotzyroundzyzzero]{#2}}{}% + \ifstrequal{#1}{rGPR}{\hyperref[sailMIPSzrGPR]{#2}}{}% + \ifstrequal{#1}{raise_c2_exception}{\hyperref[sailMIPSzraisezyc2zyexception]{#2}}{}% + \ifstrequal{#1}{raise_c2_exception8}{\hyperref[sailMIPSzraisezyc2zyexception8]{#2}}{}% + \ifstrequal{#1}{raise_c2_exception_badaddr}{\hyperref[sailMIPSzraisezyc2zyexceptionzybadaddr]{#2}}{}% + \ifstrequal{#1}{raise_c2_exception_noreg}{\hyperref[sailMIPSzraisezyc2zyexceptionzynoreg]{#2}}{}% + \ifstrequal{#1}{readCapReg}{\hyperref[sailMIPSzreadCapReg]{#2}}{}% + \ifstrequal{#1}{readCapRegDDC}{\hyperref[sailMIPSzreadCapRegDDC]{#2}}{}% + \ifstrequal{#1}{read_tag_bool}{\hyperref[sailMIPSzreadzytagzybool]{#2}}{}% + \ifstrequal{#1}{rem_round_zero}{\hyperref[sailMIPSzremzyroundzyzzero]{#2}}{}% + \ifstrequal{#1}{replicate_bits}{\hyperref[sailMIPSzreplicatezybits]{#2}}{}% + \ifstrequal{#1}{reverse_endianness}{\hyperref[sailMIPSzreversezyendianness]{#2}}{}% + \ifstrequal{#1}{sail_arith_shiftright}{\hyperref[sailMIPSzsailzyarithzyshiftright]{#2}}{}% + \ifstrequal{#1}{sail_mask}{\hyperref[sailMIPSzsailzymask]{#2}}{}% + \ifstrequal{#1}{sail_ones}{\hyperref[sailMIPSzsailzyones]{#2}}{}% + \ifstrequal{#1}{sail_shiftleft}{\hyperref[sailMIPSzsailzyshiftleft]{#2}}{}% + \ifstrequal{#1}{sail_shiftright}{\hyperref[sailMIPSzsailzyshiftright]{#2}}{}% + \ifstrequal{#1}{sail_sign_extend}{\hyperref[sailMIPSzsailzysignzyextend]{#2}}{}% + \ifstrequal{#1}{sail_zero_extend}{\hyperref[sailMIPSzsailzyzzerozyextend]{#2}}{}% + \ifstrequal{#1}{sail_zeros}{\hyperref[sailMIPSzsailzyzzeros]{#2}}{}% + \ifstrequal{#1}{sealCap}{\hyperref[sailMIPSzsealCap]{#2}}{}% + \ifstrequal{#1}{setCapAddr}{\hyperref[sailMIPSzsetCapAddr]{#2}}{}% + \ifstrequal{#1}{setCapBounds}{\hyperref[sailMIPSzsetCapBounds]{#2}}{}% + \ifstrequal{#1}{setCapFlags}{\hyperref[sailMIPSzsetCapFlags]{#2}}{}% + \ifstrequal{#1}{setCapOffset}{\hyperref[sailMIPSzsetCapOffset]{#2}}{}% + \ifstrequal{#1}{setCapPerms}{\hyperref[sailMIPSzsetCapPerms]{#2}}{}% + \ifstrequal{#1}{set_CP0EPC}{\hyperref[sailMIPSzsetzyCP0EPC]{#2}}{}% + \ifstrequal{#1}{set_CP0ErrorEPC}{\hyperref[sailMIPSzsetzyCP0ErrorEPC]{#2}}{}% + \ifstrequal{#1}{set_next_pcc}{\hyperref[sailMIPSzsetzynextzypcc]{#2}}{}% + \ifstrequal{#1}{set_slice_bits}{\hyperref[sailMIPSzsetzyslicezybits]{#2}}{}% + \ifstrequal{#1}{set_slice_int}{\hyperref[sailMIPSzsetzyslicezyint]{#2}}{}% + \ifstrequal{#1}{shift_bits_left}{\hyperref[sailMIPSzshiftzybitszyleft]{#2}}{}% + \ifstrequal{#1}{shift_bits_right}{\hyperref[sailMIPSzshiftzybitszyright]{#2}}{}% + \ifstrequal{#1}{shiftl}{\hyperref[sailMIPSzshiftl]{#2}}{}% + \ifstrequal{#1}{shiftr}{\hyperref[sailMIPSzshiftr]{#2}}{}% + \ifstrequal{#1}{signed}{\hyperref[sailMIPSzsigned]{#2}}{}% + \ifstrequal{#1}{skip_barr}{\hyperref[sailMIPSzskipzybarr]{#2}}{}% + \ifstrequal{#1}{skip_eamem}{\hyperref[sailMIPSzskipzyeamem]{#2}}{}% + \ifstrequal{#1}{skip_escape}{\hyperref[sailMIPSzskipzyescape]{#2}}{}% + \ifstrequal{#1}{skip_rmemt}{\hyperref[sailMIPSzskipzyrmemt]{#2}}{}% + \ifstrequal{#1}{skip_rreg}{\hyperref[sailMIPSzskipzyrreg]{#2}}{}% + \ifstrequal{#1}{skip_wmvt}{\hyperref[sailMIPSzskipzywmvt]{#2}}{}% + \ifstrequal{#1}{skip_wreg}{\hyperref[sailMIPSzskipzywreg]{#2}}{}% + \ifstrequal{#1}{slice}{\hyperref[sailMIPSzslice]{#2}}{}% + \ifstrequal{#1}{slice_mask}{\hyperref[sailMIPSzslicezymask]{#2}}{}% + \ifstrequal{#1}{strCCArgs}{\hyperref[sailMIPSzstrCCArgs]{#2}}{}% + \ifstrequal{#1}{strCCCArgs}{\hyperref[sailMIPSzstrCCCArgs]{#2}}{}% + \ifstrequal{#1}{strCCIArgs}{\hyperref[sailMIPSzstrCCIArgs]{#2}}{}% + \ifstrequal{#1}{strCCIUArgs}{\hyperref[sailMIPSzstrCCIUArgs]{#2}}{}% + \ifstrequal{#1}{strCCRArgs}{\hyperref[sailMIPSzstrCCRArgs]{#2}}{}% + \ifstrequal{#1}{strCRArgs}{\hyperref[sailMIPSzstrCRArgs]{#2}}{}% + \ifstrequal{#1}{strCReg}{\hyperref[sailMIPSzstrCReg]{#2}}{}% + \ifstrequal{#1}{strCmp}{\hyperref[sailMIPSzstrCmp]{#2}}{}% + \ifstrequal{#1}{strMemArgs}{\hyperref[sailMIPSzstrMemArgs]{#2}}{}% + \ifstrequal{#1}{strRCArgs}{\hyperref[sailMIPSzstrRCArgs]{#2}}{}% + \ifstrequal{#1}{strRCCArgs}{\hyperref[sailMIPSzstrRCCArgs]{#2}}{}% + \ifstrequal{#1}{strRCRArgs}{\hyperref[sailMIPSzstrRCRArgs]{#2}}{}% + \ifstrequal{#1}{strRIArgs}{\hyperref[sailMIPSzstrRIArgs]{#2}}{}% + \ifstrequal{#1}{strRRArgs}{\hyperref[sailMIPSzstrRRArgs]{#2}}{}% + \ifstrequal{#1}{strRRIArgs}{\hyperref[sailMIPSzstrRRIArgs]{#2}}{}% + \ifstrequal{#1}{strRRIUArgs}{\hyperref[sailMIPSzstrRRIUArgs]{#2}}{}% + \ifstrequal{#1}{strRRRArgs}{\hyperref[sailMIPSzstrRRRArgs]{#2}}{}% + \ifstrequal{#1}{strReg}{\hyperref[sailMIPSzstrReg]{#2}}{}% + \ifstrequal{#1}{strWordType}{\hyperref[sailMIPSzstrWordType]{#2}}{}% + \ifstrequal{#1}{string_of_capex}{\hyperref[sailMIPSzstringzyofzycapex]{#2}}{}% + \ifstrequal{#1}{string_of_exception}{\hyperref[sailMIPSzstringzyofzyexception]{#2}}{}% + \ifstrequal{#1}{string_of_int}{\hyperref[sailMIPSzstringzyofzyint]{#2}}{}% + \ifstrequal{#1}{sub_atom}{\hyperref[sailMIPSzsubzyatom]{#2}}{}% + \ifstrequal{#1}{sub_bits}{\hyperref[sailMIPSzsubzybits]{#2}}{}% + \ifstrequal{#1}{sub_int}{\hyperref[sailMIPSzsubzyint]{#2}}{}% + \ifstrequal{#1}{sub_nat}{\hyperref[sailMIPSzsubzynat]{#2}}{}% + \ifstrequal{#1}{sub_range}{\hyperref[sailMIPSzsubzyrange]{#2}}{}% + \ifstrequal{#1}{sub_vec}{\hyperref[sailMIPSzsubzyvec]{#2}}{}% + \ifstrequal{#1}{sub_vec_int}{\hyperref[sailMIPSzsubzyveczyint]{#2}}{}% + \ifstrequal{#1}{subrange_bits}{\hyperref[sailMIPSzsubrangezybits]{#2}}{}% + \ifstrequal{#1}{supported_instructions}{\hyperref[sailMIPSzsupportedzyinstructions]{#2}}{}% + \ifstrequal{#1}{tdiv_int}{\hyperref[sailMIPSztdivzyint]{#2}}{}% + \ifstrequal{#1}{tlbEntryMatch}{\hyperref[sailMIPSztlbEntryMatch]{#2}}{}% + \ifstrequal{#1}{tlbSearch}{\hyperref[sailMIPSztlbSearch]{#2}}{}% + \ifstrequal{#1}{to_bits}{\hyperref[sailMIPSztozybits]{#2}}{}% + \ifstrequal{#1}{traceException}{\hyperref[sailMIPSztraceException]{#2}}{}% + \ifstrequal{#1}{truncate}{\hyperref[sailMIPSztruncate]{#2}}{}% + \ifstrequal{#1}{truncateLSB}{\hyperref[sailMIPSztruncateLSB]{#2}}{}% + \ifstrequal{#1}{unalignedBytesTouched}{\hyperref[sailMIPSzunalignedBytesTouched]{#2}}{}% + \ifstrequal{#1}{unrepCap}{\hyperref[sailMIPSzunrepCap]{#2}}{}% + \ifstrequal{#1}{unsealCap}{\hyperref[sailMIPSzunsealCap]{#2}}{}% + \ifstrequal{#1}{unsigned}{\hyperref[sailMIPSzunsigned]{#2}}{}% + \ifstrequal{#1}{updateBadInstr}{\hyperref[sailMIPSzupdateBadInstr]{#2}}{}% + \ifstrequal{#1}{update_subrange_bits}{\hyperref[sailMIPSzupdatezysubrangezybits]{#2}}{}% + \ifstrequal{#1}{vector_length}{\hyperref[sailMIPSzvectorzylength]{#2}}{}% + \ifstrequal{#1}{wGPR}{\hyperref[sailMIPSzwGPR]{#2}}{}% + \ifstrequal{#1}{wordWidthBytes}{\hyperref[sailMIPSzwordWidthBytes]{#2}}{}% + \ifstrequal{#1}{writeCapReg}{\hyperref[sailMIPSzwriteCapReg]{#2}}{}% + \ifstrequal{#1}{write_tag_bool}{\hyperref[sailMIPSzwritezytagzybool]{#2}}{}% + \ifstrequal{#1}{xor_vec}{\hyperref[sailMIPSzxorzyvec]{#2}}{}% + \ifstrequal{#1}{zeros_implicit}{\hyperref[sailMIPSzzzeroszyimplicit]{#2}}{}% + \ifstrequal{#1}{(operator *_s)}{\hyperref[sailMIPSzz8operatorz0zAzysz9]{#2}}{}% + \ifstrequal{#1}{(operator *_u)}{\hyperref[sailMIPSzz8operatorz0zAzyuz9]{#2}}{}% + \ifstrequal{#1}{(operator <_s)}{\hyperref[sailMIPSzz8operatorz0zIzysz9]{#2}}{}% + \ifstrequal{#1}{(operator <_u)}{\hyperref[sailMIPSzz8operatorz0zIzyuz9]{#2}}{}% + \ifstrequal{#1}{(operator >=_s)}{\hyperref[sailMIPSzz8operatorz0zKzJzysz9]{#2}}{}% + \ifstrequal{#1}{(operator >=_u)}{\hyperref[sailMIPSzz8operatorz0zKzJzyuz9]{#2}}{}% + \ifstrequal{#1}{(operator >>_s)}{\hyperref[sailMIPSzz8operatorz0zKzKzysz9]{#2}}{}% + \ifstrequal{#1}{(operator ^^)}{\hyperref[sailMIPSzz8operatorz0zQzQz9]{#2}}{}} + +\newcommand{\sailMIPSfn}[1]{ + \ifstrequal{#1}{AccessLevel\_of\_num}{\sailMIPSfnAccessLevelOfNum}{}% + \ifstrequal{#1}{CPtrCmpOp\_of\_num}{\sailMIPSfnCPtrCmpOpOfNum}{}% + \ifstrequal{#1}{CapExCode}{\sailMIPSfnCapExCode}{}% + \ifstrequal{#1}{CapEx\_of\_num}{\sailMIPSfnCapExOfNum}{}% + \ifstrequal{#1}{ClearRegSet\_of\_num}{\sailMIPSfnClearRegSetOfNum}{}% + \ifstrequal{#1}{Comparison\_of\_num}{\sailMIPSfnComparisonOfNum}{}% + \ifstrequal{#1}{ERETHook}{\sailMIPSfnERETHook}{}% + \ifstrequal{#1}{ExceptionCode}{\sailMIPSfnExceptionCode}{}% + \ifstrequal{#1}{Exception\_of\_num}{\sailMIPSfnExceptionOfNum}{}% + \ifstrequal{#1}{MAX}{\sailMIPSfnMAX}{}% + \ifstrequal{#1}{MEM\_sync}{\sailMIPSfnMEMSync}{}% + \ifstrequal{#1}{MEMea}{\sailMIPSfnMEMea}{}% + \ifstrequal{#1}{MEMea\_conditional}{\sailMIPSfnMEMeaConditional}{}% + \ifstrequal{#1}{MEMr}{\sailMIPSfnMEMr}{}% + \ifstrequal{#1}{MEMr\_reserve}{\sailMIPSfnMEMrReserve}{}% + \ifstrequal{#1}{MEMr\_reserve\_wrapper}{\sailMIPSfnMEMrReserveWrapper}{}% + \ifstrequal{#1}{MEMr\_tagged}{\sailMIPSfnMEMrTagged}{}% + \ifstrequal{#1}{MEMr\_tagged\_reserve}{\sailMIPSfnMEMrTaggedReserve}{}% + \ifstrequal{#1}{MEMr\_wrapper}{\sailMIPSfnMEMrWrapper}{}% + \ifstrequal{#1}{MEMval}{\sailMIPSfnMEMval}{}% + \ifstrequal{#1}{MEMval\_conditional}{\sailMIPSfnMEMvalConditional}{}% + \ifstrequal{#1}{MEMw\_conditional\_wrapper}{\sailMIPSfnMEMwConditionalWrapper}{}% + \ifstrequal{#1}{MEMw\_tagged}{\sailMIPSfnMEMwTagged}{}% + \ifstrequal{#1}{MEMw\_tagged\_conditional}{\sailMIPSfnMEMwTaggedConditional}{}% + \ifstrequal{#1}{MEMw\_wrapper}{\sailMIPSfnMEMwWrapper}{}% + \ifstrequal{#1}{MIPSSegmentOf}{\sailMIPSfnMIPSSegmentOf}{}% + \ifstrequal{#1}{MemAccessCapRestriction\_of\_num}{\sailMIPSfnMemAccessCapRestrictionOfNum}{}% + \ifstrequal{#1}{MemAccessType\_of\_num}{\sailMIPSfnMemAccessTypeOfNum}{}% + \ifstrequal{#1}{Mk\_CapCauseReg}{\sailMIPSfnMkCapCauseReg}{}% + \ifstrequal{#1}{Mk\_CauseReg}{\sailMIPSfnMkCauseReg}{}% + \ifstrequal{#1}{Mk\_ContextReg}{\sailMIPSfnMkContextReg}{}% + \ifstrequal{#1}{Mk\_StatusReg}{\sailMIPSfnMkStatusReg}{}% + \ifstrequal{#1}{Mk\_TLBEntry}{\sailMIPSfnMkTLBEntry}{}% + \ifstrequal{#1}{Mk\_TLBEntryHiReg}{\sailMIPSfnMkTLBEntryHiReg}{}% + \ifstrequal{#1}{Mk\_TLBEntryLoReg}{\sailMIPSfnMkTLBEntryLoReg}{}% + \ifstrequal{#1}{Mk\_XContextReg}{\sailMIPSfnMkXContextReg}{}% + \ifstrequal{#1}{NotWordVal}{\sailMIPSfnNotWordVal}{}% + \ifstrequal{#1}{SignalException}{\sailMIPSfnSignalException}{}% + \ifstrequal{#1}{SignalExceptionBadAddr}{\sailMIPSfnSignalExceptionBadAddr}{}% + \ifstrequal{#1}{SignalExceptionTLB}{\sailMIPSfnSignalExceptionTLB}{}% + \ifstrequal{#1}{TLBTranslate}{\sailMIPSfnTLBTranslate}{}% + \ifstrequal{#1}{TLBTranslate2}{\sailMIPSfnTLBTranslateTwo}{}% + \ifstrequal{#1}{TLBTranslateC}{\sailMIPSfnTLBTranslateC}{}% + \ifstrequal{#1}{TranslatePC}{\sailMIPSfnTranslatePC}{}% + \ifstrequal{#1}{WordTypeUnaligned\_of\_num}{\sailMIPSfnWordTypeUnalignedOfNum}{}% + \ifstrequal{#1}{WordType\_of\_num}{\sailMIPSfnWordTypeOfNum}{}% + \ifstrequal{#1}{\_\_MIPS\_read}{\sailMIPSfnMIPSRead}{}% + \ifstrequal{#1}{\_\_MIPS\_write}{\sailMIPSfnMIPSWrite}{}% + \ifstrequal{#1}{\_\_id}{\sailMIPSfnId}{}% + \ifstrequal{#1}{\_get\_CapCauseReg\_ExcCode}{\sailMIPSfnGetCapCauseRegExcCode}{}% + \ifstrequal{#1}{\_get\_CapCauseReg\_RegNum}{\sailMIPSfnGetCapCauseRegRegNum}{}% + \ifstrequal{#1}{\_get\_CapCauseReg\_bits}{\sailMIPSfnGetCapCauseRegBits}{}% + \ifstrequal{#1}{\_get\_CauseReg\_BD}{\sailMIPSfnGetCauseRegBD}{}% + \ifstrequal{#1}{\_get\_CauseReg\_CE}{\sailMIPSfnGetCauseRegCE}{}% + \ifstrequal{#1}{\_get\_CauseReg\_ExcCode}{\sailMIPSfnGetCauseRegExcCode}{}% + \ifstrequal{#1}{\_get\_CauseReg\_IP}{\sailMIPSfnGetCauseRegIP}{}% + \ifstrequal{#1}{\_get\_CauseReg\_IV}{\sailMIPSfnGetCauseRegIV}{}% + \ifstrequal{#1}{\_get\_CauseReg\_WP}{\sailMIPSfnGetCauseRegWP}{}% + \ifstrequal{#1}{\_get\_CauseReg\_bits}{\sailMIPSfnGetCauseRegBits}{}% + \ifstrequal{#1}{\_get\_ContextReg\_BadVPN2}{\sailMIPSfnGetContextRegBadVPNTwo}{}% + \ifstrequal{#1}{\_get\_ContextReg\_PTEBase}{\sailMIPSfnGetContextRegPTEBase}{}% + \ifstrequal{#1}{\_get\_ContextReg\_bits}{\sailMIPSfnGetContextRegBits}{}% + \ifstrequal{#1}{\_get\_StatusReg\_BEV}{\sailMIPSfnGetStatusRegBEV}{}% + \ifstrequal{#1}{\_get\_StatusReg\_CU}{\sailMIPSfnGetStatusRegCU}{}% + \ifstrequal{#1}{\_get\_StatusReg\_ERL}{\sailMIPSfnGetStatusRegERL}{}% + \ifstrequal{#1}{\_get\_StatusReg\_EXL}{\sailMIPSfnGetStatusRegEXL}{}% + \ifstrequal{#1}{\_get\_StatusReg\_IE}{\sailMIPSfnGetStatusRegIE}{}% + \ifstrequal{#1}{\_get\_StatusReg\_IM}{\sailMIPSfnGetStatusRegIM}{}% + \ifstrequal{#1}{\_get\_StatusReg\_KSU}{\sailMIPSfnGetStatusRegKSU}{}% + \ifstrequal{#1}{\_get\_StatusReg\_KX}{\sailMIPSfnGetStatusRegKX}{}% + \ifstrequal{#1}{\_get\_StatusReg\_SX}{\sailMIPSfnGetStatusRegSX}{}% + \ifstrequal{#1}{\_get\_StatusReg\_UX}{\sailMIPSfnGetStatusRegUX}{}% + \ifstrequal{#1}{\_get\_StatusReg\_bits}{\sailMIPSfnGetStatusRegBits}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_ASID}{\sailMIPSfnGetTLBEntryHiRegASID}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_CLGK}{\sailMIPSfnGetTLBEntryHiRegCLGK}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_CLGS}{\sailMIPSfnGetTLBEntryHiRegCLGS}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_CLGU}{\sailMIPSfnGetTLBEntryHiRegCLGU}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_R}{\sailMIPSfnGetTLBEntryHiRegR}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_VPN2}{\sailMIPSfnGetTLBEntryHiRegVPNTwo}{}% + \ifstrequal{#1}{\_get\_TLBEntryHiReg\_bits}{\sailMIPSfnGetTLBEntryHiRegBits}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_C}{\sailMIPSfnGetTLBEntryLoRegC}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_CapL}{\sailMIPSfnGetTLBEntryLoRegCapL}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_CapLG}{\sailMIPSfnGetTLBEntryLoRegCapLG}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_CapS}{\sailMIPSfnGetTLBEntryLoRegCapS}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_D}{\sailMIPSfnGetTLBEntryLoRegD}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_G}{\sailMIPSfnGetTLBEntryLoRegG}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_PFN}{\sailMIPSfnGetTLBEntryLoRegPFN}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_V}{\sailMIPSfnGetTLBEntryLoRegV}{}% + \ifstrequal{#1}{\_get\_TLBEntryLoReg\_bits}{\sailMIPSfnGetTLBEntryLoRegBits}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_asid}{\sailMIPSfnGetTLBEntryAsid}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_bits}{\sailMIPSfnGetTLBEntryBits}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_c0}{\sailMIPSfnGetTLBEntryCZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_c1}{\sailMIPSfnGetTLBEntryCOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_capl0}{\sailMIPSfnGetTLBEntryCaplZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_capl1}{\sailMIPSfnGetTLBEntryCaplOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_caplg0}{\sailMIPSfnGetTLBEntryCaplgZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_caplg1}{\sailMIPSfnGetTLBEntryCaplgOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_caps0}{\sailMIPSfnGetTLBEntryCapsZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_caps1}{\sailMIPSfnGetTLBEntryCapsOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_d0}{\sailMIPSfnGetTLBEntryDZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_d1}{\sailMIPSfnGetTLBEntryDOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_g}{\sailMIPSfnGetTLBEntryG}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_pagemask}{\sailMIPSfnGetTLBEntryPagemask}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_pfn0}{\sailMIPSfnGetTLBEntryPfnZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_pfn1}{\sailMIPSfnGetTLBEntryPfnOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_r}{\sailMIPSfnGetTLBEntryR}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_v0}{\sailMIPSfnGetTLBEntryVZero}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_v1}{\sailMIPSfnGetTLBEntryVOne}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_valid}{\sailMIPSfnGetTLBEntryValid}{}% + \ifstrequal{#1}{\_get\_TLBEntry\_vpn2}{\sailMIPSfnGetTLBEntryVpnTwo}{}% + \ifstrequal{#1}{\_get\_XContextReg\_XBadVPN2}{\sailMIPSfnGetXContextRegXBadVPNTwo}{}% + \ifstrequal{#1}{\_get\_XContextReg\_XPTEBase}{\sailMIPSfnGetXContextRegXPTEBase}{}% + \ifstrequal{#1}{\_get\_XContextReg\_XR}{\sailMIPSfnGetXContextRegXR}{}% + \ifstrequal{#1}{\_get\_XContextReg\_bits}{\sailMIPSfnGetXContextRegBits}{}% + \ifstrequal{#1}{\_set\_CapCauseReg\_ExcCode}{\sailMIPSfnSetCapCauseRegExcCode}{}% + \ifstrequal{#1}{\_set\_CapCauseReg\_RegNum}{\sailMIPSfnSetCapCauseRegRegNum}{}% + \ifstrequal{#1}{\_set\_CapCauseReg\_bits}{\sailMIPSfnSetCapCauseRegBits}{}% + \ifstrequal{#1}{\_set\_CauseReg\_BD}{\sailMIPSfnSetCauseRegBD}{}% + \ifstrequal{#1}{\_set\_CauseReg\_CE}{\sailMIPSfnSetCauseRegCE}{}% + \ifstrequal{#1}{\_set\_CauseReg\_ExcCode}{\sailMIPSfnSetCauseRegExcCode}{}% + \ifstrequal{#1}{\_set\_CauseReg\_IP}{\sailMIPSfnSetCauseRegIP}{}% + \ifstrequal{#1}{\_set\_CauseReg\_IV}{\sailMIPSfnSetCauseRegIV}{}% + \ifstrequal{#1}{\_set\_CauseReg\_WP}{\sailMIPSfnSetCauseRegWP}{}% + \ifstrequal{#1}{\_set\_CauseReg\_bits}{\sailMIPSfnSetCauseRegBits}{}% + \ifstrequal{#1}{\_set\_ContextReg\_BadVPN2}{\sailMIPSfnSetContextRegBadVPNTwo}{}% + \ifstrequal{#1}{\_set\_ContextReg\_PTEBase}{\sailMIPSfnSetContextRegPTEBase}{}% + \ifstrequal{#1}{\_set\_ContextReg\_bits}{\sailMIPSfnSetContextRegBits}{}% + \ifstrequal{#1}{\_set\_StatusReg\_BEV}{\sailMIPSfnSetStatusRegBEV}{}% + \ifstrequal{#1}{\_set\_StatusReg\_CU}{\sailMIPSfnSetStatusRegCU}{}% + \ifstrequal{#1}{\_set\_StatusReg\_ERL}{\sailMIPSfnSetStatusRegERL}{}% + \ifstrequal{#1}{\_set\_StatusReg\_EXL}{\sailMIPSfnSetStatusRegEXL}{}% + \ifstrequal{#1}{\_set\_StatusReg\_IE}{\sailMIPSfnSetStatusRegIE}{}% + \ifstrequal{#1}{\_set\_StatusReg\_IM}{\sailMIPSfnSetStatusRegIM}{}% + \ifstrequal{#1}{\_set\_StatusReg\_KSU}{\sailMIPSfnSetStatusRegKSU}{}% + \ifstrequal{#1}{\_set\_StatusReg\_KX}{\sailMIPSfnSetStatusRegKX}{}% + \ifstrequal{#1}{\_set\_StatusReg\_SX}{\sailMIPSfnSetStatusRegSX}{}% + \ifstrequal{#1}{\_set\_StatusReg\_UX}{\sailMIPSfnSetStatusRegUX}{}% + \ifstrequal{#1}{\_set\_StatusReg\_bits}{\sailMIPSfnSetStatusRegBits}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_ASID}{\sailMIPSfnSetTLBEntryHiRegASID}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_CLGK}{\sailMIPSfnSetTLBEntryHiRegCLGK}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_CLGS}{\sailMIPSfnSetTLBEntryHiRegCLGS}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_CLGU}{\sailMIPSfnSetTLBEntryHiRegCLGU}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_R}{\sailMIPSfnSetTLBEntryHiRegR}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_VPN2}{\sailMIPSfnSetTLBEntryHiRegVPNTwo}{}% + \ifstrequal{#1}{\_set\_TLBEntryHiReg\_bits}{\sailMIPSfnSetTLBEntryHiRegBits}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_C}{\sailMIPSfnSetTLBEntryLoRegC}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_CapL}{\sailMIPSfnSetTLBEntryLoRegCapL}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_CapLG}{\sailMIPSfnSetTLBEntryLoRegCapLG}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_CapS}{\sailMIPSfnSetTLBEntryLoRegCapS}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_D}{\sailMIPSfnSetTLBEntryLoRegD}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_G}{\sailMIPSfnSetTLBEntryLoRegG}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_PFN}{\sailMIPSfnSetTLBEntryLoRegPFN}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_V}{\sailMIPSfnSetTLBEntryLoRegV}{}% + \ifstrequal{#1}{\_set\_TLBEntryLoReg\_bits}{\sailMIPSfnSetTLBEntryLoRegBits}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_asid}{\sailMIPSfnSetTLBEntryAsid}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_bits}{\sailMIPSfnSetTLBEntryBits}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_c0}{\sailMIPSfnSetTLBEntryCZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_c1}{\sailMIPSfnSetTLBEntryCOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_capl0}{\sailMIPSfnSetTLBEntryCaplZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_capl1}{\sailMIPSfnSetTLBEntryCaplOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_caplg0}{\sailMIPSfnSetTLBEntryCaplgZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_caplg1}{\sailMIPSfnSetTLBEntryCaplgOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_caps0}{\sailMIPSfnSetTLBEntryCapsZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_caps1}{\sailMIPSfnSetTLBEntryCapsOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_d0}{\sailMIPSfnSetTLBEntryDZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_d1}{\sailMIPSfnSetTLBEntryDOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_g}{\sailMIPSfnSetTLBEntryG}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_pagemask}{\sailMIPSfnSetTLBEntryPagemask}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_pfn0}{\sailMIPSfnSetTLBEntryPfnZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_pfn1}{\sailMIPSfnSetTLBEntryPfnOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_r}{\sailMIPSfnSetTLBEntryR}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_v0}{\sailMIPSfnSetTLBEntryVZero}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_v1}{\sailMIPSfnSetTLBEntryVOne}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_valid}{\sailMIPSfnSetTLBEntryValid}{}% + \ifstrequal{#1}{\_set\_TLBEntry\_vpn2}{\sailMIPSfnSetTLBEntryVpnTwo}{}% + \ifstrequal{#1}{\_set\_XContextReg\_XBadVPN2}{\sailMIPSfnSetXContextRegXBadVPNTwo}{}% + \ifstrequal{#1}{\_set\_XContextReg\_XPTEBase}{\sailMIPSfnSetXContextRegXPTEBase}{}% + \ifstrequal{#1}{\_set\_XContextReg\_XR}{\sailMIPSfnSetXContextRegXR}{}% + \ifstrequal{#1}{\_set\_XContextReg\_bits}{\sailMIPSfnSetXContextRegBits}{}% + \ifstrequal{#1}{\_update\_CapCauseReg\_ExcCode}{\sailMIPSfnUpdateCapCauseRegExcCode}{}% + \ifstrequal{#1}{\_update\_CapCauseReg\_RegNum}{\sailMIPSfnUpdateCapCauseRegRegNum}{}% + \ifstrequal{#1}{\_update\_CapCauseReg\_bits}{\sailMIPSfnUpdateCapCauseRegBits}{}% + \ifstrequal{#1}{\_update\_CauseReg\_BD}{\sailMIPSfnUpdateCauseRegBD}{}% + \ifstrequal{#1}{\_update\_CauseReg\_CE}{\sailMIPSfnUpdateCauseRegCE}{}% + \ifstrequal{#1}{\_update\_CauseReg\_ExcCode}{\sailMIPSfnUpdateCauseRegExcCode}{}% + \ifstrequal{#1}{\_update\_CauseReg\_IP}{\sailMIPSfnUpdateCauseRegIP}{}% + \ifstrequal{#1}{\_update\_CauseReg\_IV}{\sailMIPSfnUpdateCauseRegIV}{}% + \ifstrequal{#1}{\_update\_CauseReg\_WP}{\sailMIPSfnUpdateCauseRegWP}{}% + \ifstrequal{#1}{\_update\_CauseReg\_bits}{\sailMIPSfnUpdateCauseRegBits}{}% + \ifstrequal{#1}{\_update\_ContextReg\_BadVPN2}{\sailMIPSfnUpdateContextRegBadVPNTwo}{}% + \ifstrequal{#1}{\_update\_ContextReg\_PTEBase}{\sailMIPSfnUpdateContextRegPTEBase}{}% + \ifstrequal{#1}{\_update\_ContextReg\_bits}{\sailMIPSfnUpdateContextRegBits}{}% + \ifstrequal{#1}{\_update\_StatusReg\_BEV}{\sailMIPSfnUpdateStatusRegBEV}{}% + \ifstrequal{#1}{\_update\_StatusReg\_CU}{\sailMIPSfnUpdateStatusRegCU}{}% + \ifstrequal{#1}{\_update\_StatusReg\_ERL}{\sailMIPSfnUpdateStatusRegERL}{}% + \ifstrequal{#1}{\_update\_StatusReg\_EXL}{\sailMIPSfnUpdateStatusRegEXL}{}% + \ifstrequal{#1}{\_update\_StatusReg\_IE}{\sailMIPSfnUpdateStatusRegIE}{}% + \ifstrequal{#1}{\_update\_StatusReg\_IM}{\sailMIPSfnUpdateStatusRegIM}{}% + \ifstrequal{#1}{\_update\_StatusReg\_KSU}{\sailMIPSfnUpdateStatusRegKSU}{}% + \ifstrequal{#1}{\_update\_StatusReg\_KX}{\sailMIPSfnUpdateStatusRegKX}{}% + \ifstrequal{#1}{\_update\_StatusReg\_SX}{\sailMIPSfnUpdateStatusRegSX}{}% + \ifstrequal{#1}{\_update\_StatusReg\_UX}{\sailMIPSfnUpdateStatusRegUX}{}% + \ifstrequal{#1}{\_update\_StatusReg\_bits}{\sailMIPSfnUpdateStatusRegBits}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_ASID}{\sailMIPSfnUpdateTLBEntryHiRegASID}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_CLGK}{\sailMIPSfnUpdateTLBEntryHiRegCLGK}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_CLGS}{\sailMIPSfnUpdateTLBEntryHiRegCLGS}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_CLGU}{\sailMIPSfnUpdateTLBEntryHiRegCLGU}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_R}{\sailMIPSfnUpdateTLBEntryHiRegR}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_VPN2}{\sailMIPSfnUpdateTLBEntryHiRegVPNTwo}{}% + \ifstrequal{#1}{\_update\_TLBEntryHiReg\_bits}{\sailMIPSfnUpdateTLBEntryHiRegBits}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_C}{\sailMIPSfnUpdateTLBEntryLoRegC}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_CapL}{\sailMIPSfnUpdateTLBEntryLoRegCapL}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_CapLG}{\sailMIPSfnUpdateTLBEntryLoRegCapLG}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_CapS}{\sailMIPSfnUpdateTLBEntryLoRegCapS}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_D}{\sailMIPSfnUpdateTLBEntryLoRegD}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_G}{\sailMIPSfnUpdateTLBEntryLoRegG}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_PFN}{\sailMIPSfnUpdateTLBEntryLoRegPFN}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_V}{\sailMIPSfnUpdateTLBEntryLoRegV}{}% + \ifstrequal{#1}{\_update\_TLBEntryLoReg\_bits}{\sailMIPSfnUpdateTLBEntryLoRegBits}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_asid}{\sailMIPSfnUpdateTLBEntryAsid}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_bits}{\sailMIPSfnUpdateTLBEntryBits}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_c0}{\sailMIPSfnUpdateTLBEntryCZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_c1}{\sailMIPSfnUpdateTLBEntryCOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_capl0}{\sailMIPSfnUpdateTLBEntryCaplZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_capl1}{\sailMIPSfnUpdateTLBEntryCaplOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_caplg0}{\sailMIPSfnUpdateTLBEntryCaplgZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_caplg1}{\sailMIPSfnUpdateTLBEntryCaplgOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_caps0}{\sailMIPSfnUpdateTLBEntryCapsZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_caps1}{\sailMIPSfnUpdateTLBEntryCapsOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_d0}{\sailMIPSfnUpdateTLBEntryDZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_d1}{\sailMIPSfnUpdateTLBEntryDOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_g}{\sailMIPSfnUpdateTLBEntryG}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_pagemask}{\sailMIPSfnUpdateTLBEntryPagemask}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_pfn0}{\sailMIPSfnUpdateTLBEntryPfnZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_pfn1}{\sailMIPSfnUpdateTLBEntryPfnOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_r}{\sailMIPSfnUpdateTLBEntryR}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_v0}{\sailMIPSfnUpdateTLBEntryVZero}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_v1}{\sailMIPSfnUpdateTLBEntryVOne}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_valid}{\sailMIPSfnUpdateTLBEntryValid}{}% + \ifstrequal{#1}{\_update\_TLBEntry\_vpn2}{\sailMIPSfnUpdateTLBEntryVpnTwo}{}% + \ifstrequal{#1}{\_update\_XContextReg\_XBadVPN2}{\sailMIPSfnUpdateXContextRegXBadVPNTwo}{}% + \ifstrequal{#1}{\_update\_XContextReg\_XPTEBase}{\sailMIPSfnUpdateXContextRegXPTEBase}{}% + \ifstrequal{#1}{\_update\_XContextReg\_XR}{\sailMIPSfnUpdateXContextRegXR}{}% + \ifstrequal{#1}{\_update\_XContextReg\_bits}{\sailMIPSfnUpdateXContextRegBits}{}% + \ifstrequal{#1}{addrWrapper}{\sailMIPSfnaddrWrapper}{}% + \ifstrequal{#1}{addrWrapperUnaligned}{\sailMIPSfnaddrWrapperUnaligned}{}% + \ifstrequal{#1}{bit\_to\_bool}{\sailMIPSfnbitToBool}{}% + \ifstrequal{#1}{bits\_to\_bool}{\sailMIPSfnbitsToBool}{}% + \ifstrequal{#1}{bool\_to\_bit}{\sailMIPSfnboolToBit}{}% + \ifstrequal{#1}{bool\_to\_bits}{\sailMIPSfnboolToBits}{}% + \ifstrequal{#1}{capBitsToCapability}{\sailMIPSfncapBitsToCapability}{}% + \ifstrequal{#1}{capBoundsEqual}{\sailMIPSfncapBoundsEqual}{}% + \ifstrequal{#1}{capToBits}{\sailMIPSfncapToBits}{}% + \ifstrequal{#1}{capToMemBits}{\sailMIPSfncapToMemBits}{}% + \ifstrequal{#1}{capToString}{\sailMIPSfncapToString}{}% + \ifstrequal{#1}{cast\_unit\_vec}{\sailMIPSfncastUnitVec}{}% + \ifstrequal{#1}{checkCP0Access}{\sailMIPSfncheckCPZeroAccess}{}% + \ifstrequal{#1}{checkCP0AccessHook}{\sailMIPSfncheckCPZeroAccessHook}{}% + \ifstrequal{#1}{checkCP2usable}{\sailMIPSfncheckCPTwousable}{}% + \ifstrequal{#1}{checkDDCPerms}{\sailMIPSfncheckDDCPerms}{}% + \ifstrequal{#1}{compare}{\sailMIPSfncompare}{}% + \ifstrequal{#1}{concat\_str\_bits}{\sailMIPSfnconcatStrBits}{}% + \ifstrequal{#1}{concat\_str\_dec}{\sailMIPSfnconcatStrDec}{}% + \ifstrequal{#1}{cp2\_next\_pc}{\sailMIPSfncpTwoNextPc}{}% + \ifstrequal{#1}{decode\_failure\_of\_num}{\sailMIPSfndecodeFailureOfNum}{}% + \ifstrequal{#1}{dump\_cp2\_state}{\sailMIPSfndumpCpTwoState}{}% + \ifstrequal{#1}{eq\_unit}{\sailMIPSfneqUnit}{}% + \ifstrequal{#1}{exceptionVectorBase}{\sailMIPSfnexceptionVectorBase}{}% + \ifstrequal{#1}{exceptionVectorOffset}{\sailMIPSfnexceptionVectorOffset}{}% + \ifstrequal{#1}{execute\_branch}{\sailMIPSfnexecuteBranch}{}% + \ifstrequal{#1}{execute\_branch\_mips}{\sailMIPSfnexecuteBranchMips}{}% + \ifstrequal{#1}{execute\_branch\_pcc}{\sailMIPSfnexecuteBranchPcc}{}% + \ifstrequal{#1}{extendLoad}{\sailMIPSfnextendLoad}{}% + \ifstrequal{#1}{fdiv\_int}{\sailMIPSfnfdivInt}{}% + \ifstrequal{#1}{fmod\_int}{\sailMIPSfnfmodInt}{}% + \ifstrequal{#1}{getAccessLevel}{\sailMIPSfngetAccessLevel}{}% + \ifstrequal{#1}{getCapBase}{\sailMIPSfngetCapBase}{}% + \ifstrequal{#1}{getCapBounds}{\sailMIPSfngetCapBounds}{}% + \ifstrequal{#1}{getCapCursor}{\sailMIPSfngetCapCursor}{}% + \ifstrequal{#1}{getCapFlags}{\sailMIPSfngetCapFlags}{}% + \ifstrequal{#1}{getCapHardPerms}{\sailMIPSfngetCapHardPerms}{}% + \ifstrequal{#1}{getCapLength}{\sailMIPSfngetCapLength}{}% + \ifstrequal{#1}{getCapOffset}{\sailMIPSfngetCapOffset}{}% + \ifstrequal{#1}{getCapPerms}{\sailMIPSfngetCapPerms}{}% + \ifstrequal{#1}{getCapTop}{\sailMIPSfngetCapTop}{}% + \ifstrequal{#1}{getRepresentableAlignmentMask}{\sailMIPSfngetRepresentableAlignmentMask}{}% + \ifstrequal{#1}{getRepresentableLength}{\sailMIPSfngetRepresentableLength}{}% + \ifstrequal{#1}{get\_CP0EPC}{\sailMIPSfngetCPZeroEPC}{}% + \ifstrequal{#1}{get\_CP0ErrorEPC}{\sailMIPSfngetCPZeroErrorEPC}{}% + \ifstrequal{#1}{grantsAccess}{\sailMIPSfngrantsAccess}{}% + \ifstrequal{#1}{hasReservedOType}{\sailMIPSfnhasReservedOType}{}% + \ifstrequal{#1}{incCapOffset}{\sailMIPSfnincCapOffset}{}% + \ifstrequal{#1}{incrementCP0Count}{\sailMIPSfnincrementCPZeroCount}{}% + \ifstrequal{#1}{init\_cp0\_state}{\sailMIPSfninitCpZeroState}{}% + \ifstrequal{#1}{init\_cp2\_state}{\sailMIPSfninitCpTwoState}{}% + \ifstrequal{#1}{int\_of\_AccessLevel}{\sailMIPSfnintOfAccessLevel}{}% + \ifstrequal{#1}{isAddressAligned}{\sailMIPSfnisAddressAligned}{}% + \ifstrequal{#1}{isSentryCap}{\sailMIPSfnisSentryCap}{}% + \ifstrequal{#1}{is\_none}{\sailMIPSfnisNone}{}% + \ifstrequal{#1}{is\_some}{\sailMIPSfnisSome}{}% + \ifstrequal{#1}{mask}{\sailMIPSfnmask}{}% + \ifstrequal{#1}{memBitsToCapability}{\sailMIPSfnmemBitsToCapability}{}% + \ifstrequal{#1}{mips\_sign\_extend}{\sailMIPSfnmipsSignExtend}{}% + \ifstrequal{#1}{mips\_zero\_extend}{\sailMIPSfnmipsZeroExtend}{}% + \ifstrequal{#1}{neq\_anything}{\sailMIPSfnneqAnything}{}% + \ifstrequal{#1}{neq\_bits}{\sailMIPSfnneqBits}{}% + \ifstrequal{#1}{neq\_bool}{\sailMIPSfnneqBool}{}% + \ifstrequal{#1}{neq\_int}{\sailMIPSfnneqInt}{}% + \ifstrequal{#1}{num\_of\_AccessLevel}{\sailMIPSfnnumOfAccessLevel}{}% + \ifstrequal{#1}{num\_of\_CPtrCmpOp}{\sailMIPSfnnumOfCPtrCmpOp}{}% + \ifstrequal{#1}{num\_of\_CapEx}{\sailMIPSfnnumOfCapEx}{}% + \ifstrequal{#1}{num\_of\_ClearRegSet}{\sailMIPSfnnumOfClearRegSet}{}% + \ifstrequal{#1}{num\_of\_Comparison}{\sailMIPSfnnumOfComparison}{}% + \ifstrequal{#1}{num\_of\_Exception}{\sailMIPSfnnumOfException}{}% + \ifstrequal{#1}{num\_of\_MemAccessCapRestriction}{\sailMIPSfnnumOfMemAccessCapRestriction}{}% + \ifstrequal{#1}{num\_of\_MemAccessType}{\sailMIPSfnnumOfMemAccessType}{}% + \ifstrequal{#1}{num\_of\_WordType}{\sailMIPSfnnumOfWordType}{}% + \ifstrequal{#1}{num\_of\_WordTypeUnaligned}{\sailMIPSfnnumOfWordTypeUnaligned}{}% + \ifstrequal{#1}{num\_of\_decode\_failure}{\sailMIPSfnnumOfDecodeFailure}{}% + \ifstrequal{#1}{ones\_implicit}{\sailMIPSfnonesImplicit}{}% + \ifstrequal{#1}{pcc\_access\_system\_regs}{\sailMIPSfnpccAccessSystemRegs}{}% + \ifstrequal{#1}{rGPR}{\sailMIPSfnrGPR}{}% + \ifstrequal{#1}{raise\_c2\_exception}{\sailMIPSfnraiseCTwoException}{}% + \ifstrequal{#1}{raise\_c2\_exception8}{\sailMIPSfnraiseCTwoExceptionEight}{}% + \ifstrequal{#1}{raise\_c2\_exception\_badaddr}{\sailMIPSfnraiseCTwoExceptionBadaddr}{}% + \ifstrequal{#1}{raise\_c2\_exception\_noreg}{\sailMIPSfnraiseCTwoExceptionNoreg}{}% + \ifstrequal{#1}{readCapReg}{\sailMIPSfnreadCapReg}{}% + \ifstrequal{#1}{readCapRegDDC}{\sailMIPSfnreadCapRegDDC}{}% + \ifstrequal{#1}{sail\_mask}{\sailMIPSfnsailMask}{}% + \ifstrequal{#1}{sail\_ones}{\sailMIPSfnsailOnes}{}% + \ifstrequal{#1}{sealCap}{\sailMIPSfnsealCap}{}% + \ifstrequal{#1}{setCapAddr}{\sailMIPSfnsetCapAddr}{}% + \ifstrequal{#1}{setCapBounds}{\sailMIPSfnsetCapBounds}{}% + \ifstrequal{#1}{setCapFlags}{\sailMIPSfnsetCapFlags}{}% + \ifstrequal{#1}{setCapOffset}{\sailMIPSfnsetCapOffset}{}% + \ifstrequal{#1}{setCapPerms}{\sailMIPSfnsetCapPerms}{}% + \ifstrequal{#1}{set\_CP0EPC}{\sailMIPSfnsetCPZeroEPC}{}% + \ifstrequal{#1}{set\_CP0ErrorEPC}{\sailMIPSfnsetCPZeroErrorEPC}{}% + \ifstrequal{#1}{set\_next\_pcc}{\sailMIPSfnsetNextPcc}{}% + \ifstrequal{#1}{slice\_mask}{\sailMIPSfnsliceMask}{}% + \ifstrequal{#1}{strCCArgs}{\sailMIPSfnstrCCArgs}{}% + \ifstrequal{#1}{strCCCArgs}{\sailMIPSfnstrCCCArgs}{}% + \ifstrequal{#1}{strCCIArgs}{\sailMIPSfnstrCCIArgs}{}% + \ifstrequal{#1}{strCCIUArgs}{\sailMIPSfnstrCCIUArgs}{}% + \ifstrequal{#1}{strCCRArgs}{\sailMIPSfnstrCCRArgs}{}% + \ifstrequal{#1}{strCRArgs}{\sailMIPSfnstrCRArgs}{}% + \ifstrequal{#1}{strCReg}{\sailMIPSfnstrCReg}{}% + \ifstrequal{#1}{strCmp}{\sailMIPSfnstrCmp}{}% + \ifstrequal{#1}{strMemArgs}{\sailMIPSfnstrMemArgs}{}% + \ifstrequal{#1}{strRCArgs}{\sailMIPSfnstrRCArgs}{}% + \ifstrequal{#1}{strRCCArgs}{\sailMIPSfnstrRCCArgs}{}% + \ifstrequal{#1}{strRCRArgs}{\sailMIPSfnstrRCRArgs}{}% + \ifstrequal{#1}{strRIArgs}{\sailMIPSfnstrRIArgs}{}% + \ifstrequal{#1}{strRRArgs}{\sailMIPSfnstrRRArgs}{}% + \ifstrequal{#1}{strRRIArgs}{\sailMIPSfnstrRRIArgs}{}% + \ifstrequal{#1}{strRRIUArgs}{\sailMIPSfnstrRRIUArgs}{}% + \ifstrequal{#1}{strRRRArgs}{\sailMIPSfnstrRRRArgs}{}% + \ifstrequal{#1}{strReg}{\sailMIPSfnstrReg}{}% + \ifstrequal{#1}{strWordType}{\sailMIPSfnstrWordType}{}% + \ifstrequal{#1}{string\_of\_capex}{\sailMIPSfnstringOfCapex}{}% + \ifstrequal{#1}{string\_of\_exception}{\sailMIPSfnstringOfException}{}% + \ifstrequal{#1}{supported\_instructions}{\sailMIPSfnsupportedInstructions}{}% + \ifstrequal{#1}{tlbEntryMatch}{\sailMIPSfntlbEntryMatch}{}% + \ifstrequal{#1}{tlbSearch}{\sailMIPSfntlbSearch}{}% + \ifstrequal{#1}{to\_bits}{\sailMIPSfntoBits}{}% + \ifstrequal{#1}{traceException}{\sailMIPSfntraceException}{}% + \ifstrequal{#1}{unalignedBytesTouched}{\sailMIPSfnunalignedBytesTouched}{}% + \ifstrequal{#1}{unrepCap}{\sailMIPSfnunrepCap}{}% + \ifstrequal{#1}{unsealCap}{\sailMIPSfnunsealCap}{}% + \ifstrequal{#1}{updateBadInstr}{\sailMIPSfnupdateBadInstr}{}% + \ifstrequal{#1}{wGPR}{\sailMIPSfnwGPR}{}% + \ifstrequal{#1}{wordWidthBytes}{\sailMIPSfnwordWidthBytes}{}% + \ifstrequal{#1}{writeCapReg}{\sailMIPSfnwriteCapReg}{}% + \ifstrequal{#1}{zeros\_implicit}{\sailMIPSfnzzerosImplicit}{}% + \ifstrequal{#1}{(operator $>$\_s)}{\sailMIPSfnzEightoperatorzZerozISzNine}{}% + \ifstrequal{#1}{(operator $>$\_u)}{\sailMIPSfnzEightoperatorzZerozIUzNine}{}% + \ifstrequal{#1}{(operator $$>$$=\_s)}{\sailMIPSfnzEightoperatorzZerozKzJSzNine}{}% + \ifstrequal{#1}{(operator $$>$$=\_u)}{\sailMIPSfnzEightoperatorzZerozKzJUzNine}{}% + \ifstrequal{#1}{(operator ^^)}{\sailMIPSfnzEightoperatorzZerozQzQzNine}{}} + +\newcommand{\sailMIPSreffn}[2]{ + \ifstrequal{#1}{AccessLevel_of_num}{\hyperref[sailMIPSfnzAccessLevelzyofzynum]{#2}}{}% + \ifstrequal{#1}{CPtrCmpOp_of_num}{\hyperref[sailMIPSfnzCPtrCmpOpzyofzynum]{#2}}{}% + \ifstrequal{#1}{CapExCode}{\hyperref[sailMIPSfnzCapExCode]{#2}}{}% + \ifstrequal{#1}{CapEx_of_num}{\hyperref[sailMIPSfnzCapExzyofzynum]{#2}}{}% + \ifstrequal{#1}{ClearRegSet_of_num}{\hyperref[sailMIPSfnzClearRegSetzyofzynum]{#2}}{}% + \ifstrequal{#1}{Comparison_of_num}{\hyperref[sailMIPSfnzComparisonzyofzynum]{#2}}{}% + \ifstrequal{#1}{ERETHook}{\hyperref[sailMIPSfnzERETHook]{#2}}{}% + \ifstrequal{#1}{ExceptionCode}{\hyperref[sailMIPSfnzExceptionCode]{#2}}{}% + \ifstrequal{#1}{Exception_of_num}{\hyperref[sailMIPSfnzExceptionzyofzynum]{#2}}{}% + \ifstrequal{#1}{MAX}{\hyperref[sailMIPSfnzMAX]{#2}}{}% + \ifstrequal{#1}{MEM_sync}{\hyperref[sailMIPSfnzMEMzysync]{#2}}{}% + \ifstrequal{#1}{MEMea}{\hyperref[sailMIPSfnzMEMea]{#2}}{}% + \ifstrequal{#1}{MEMea_conditional}{\hyperref[sailMIPSfnzMEMeazyconditional]{#2}}{}% + \ifstrequal{#1}{MEMr}{\hyperref[sailMIPSfnzMEMr]{#2}}{}% + \ifstrequal{#1}{MEMr_reserve}{\hyperref[sailMIPSfnzMEMrzyreserve]{#2}}{}% + \ifstrequal{#1}{MEMr_reserve_wrapper}{\hyperref[sailMIPSfnzMEMrzyreservezywrapper]{#2}}{}% + \ifstrequal{#1}{MEMr_tagged}{\hyperref[sailMIPSfnzMEMrzytagged]{#2}}{}% + \ifstrequal{#1}{MEMr_tagged_reserve}{\hyperref[sailMIPSfnzMEMrzytaggedzyreserve]{#2}}{}% + \ifstrequal{#1}{MEMr_wrapper}{\hyperref[sailMIPSfnzMEMrzywrapper]{#2}}{}% + \ifstrequal{#1}{MEMval}{\hyperref[sailMIPSfnzMEMval]{#2}}{}% + \ifstrequal{#1}{MEMval_conditional}{\hyperref[sailMIPSfnzMEMvalzyconditional]{#2}}{}% + \ifstrequal{#1}{MEMw_conditional_wrapper}{\hyperref[sailMIPSfnzMEMwzyconditionalzywrapper]{#2}}{}% + \ifstrequal{#1}{MEMw_tagged}{\hyperref[sailMIPSfnzMEMwzytagged]{#2}}{}% + \ifstrequal{#1}{MEMw_tagged_conditional}{\hyperref[sailMIPSfnzMEMwzytaggedzyconditional]{#2}}{}% + \ifstrequal{#1}{MEMw_wrapper}{\hyperref[sailMIPSfnzMEMwzywrapper]{#2}}{}% + \ifstrequal{#1}{MIPSSegmentOf}{\hyperref[sailMIPSfnzMIPSSegmentOf]{#2}}{}% + \ifstrequal{#1}{MemAccessCapRestriction_of_num}{\hyperref[sailMIPSfnzMemAccessCapRestrictionzyofzynum]{#2}}{}% + \ifstrequal{#1}{MemAccessType_of_num}{\hyperref[sailMIPSfnzMemAccessTypezyofzynum]{#2}}{}% + \ifstrequal{#1}{Mk_CapCauseReg}{\hyperref[sailMIPSfnzMkzyCapCauseReg]{#2}}{}% + \ifstrequal{#1}{Mk_CauseReg}{\hyperref[sailMIPSfnzMkzyCauseReg]{#2}}{}% + \ifstrequal{#1}{Mk_ContextReg}{\hyperref[sailMIPSfnzMkzyContextReg]{#2}}{}% + \ifstrequal{#1}{Mk_StatusReg}{\hyperref[sailMIPSfnzMkzyStatusReg]{#2}}{}% + \ifstrequal{#1}{Mk_TLBEntry}{\hyperref[sailMIPSfnzMkzyTLBEntry]{#2}}{}% + \ifstrequal{#1}{Mk_TLBEntryHiReg}{\hyperref[sailMIPSfnzMkzyTLBEntryHiReg]{#2}}{}% + \ifstrequal{#1}{Mk_TLBEntryLoReg}{\hyperref[sailMIPSfnzMkzyTLBEntryLoReg]{#2}}{}% + \ifstrequal{#1}{Mk_XContextReg}{\hyperref[sailMIPSfnzMkzyXContextReg]{#2}}{}% + \ifstrequal{#1}{NotWordVal}{\hyperref[sailMIPSfnzNotWordVal]{#2}}{}% + \ifstrequal{#1}{SignalException}{\hyperref[sailMIPSfnzSignalException]{#2}}{}% + \ifstrequal{#1}{SignalExceptionBadAddr}{\hyperref[sailMIPSfnzSignalExceptionBadAddr]{#2}}{}% + \ifstrequal{#1}{SignalExceptionTLB}{\hyperref[sailMIPSfnzSignalExceptionTLB]{#2}}{}% + \ifstrequal{#1}{TLBTranslate}{\hyperref[sailMIPSfnzTLBTranslate]{#2}}{}% + \ifstrequal{#1}{TLBTranslate2}{\hyperref[sailMIPSfnzTLBTranslate2]{#2}}{}% + \ifstrequal{#1}{TLBTranslateC}{\hyperref[sailMIPSfnzTLBTranslateC]{#2}}{}% + \ifstrequal{#1}{TranslatePC}{\hyperref[sailMIPSfnzTranslatePC]{#2}}{}% + \ifstrequal{#1}{WordTypeUnaligned_of_num}{\hyperref[sailMIPSfnzWordTypeUnalignedzyofzynum]{#2}}{}% + \ifstrequal{#1}{WordType_of_num}{\hyperref[sailMIPSfnzWordTypezyofzynum]{#2}}{}% + \ifstrequal{#1}{__MIPS_read}{\hyperref[sailMIPSfnzzyzyMIPSzyread]{#2}}{}% + \ifstrequal{#1}{__MIPS_write}{\hyperref[sailMIPSfnzzyzyMIPSzywrite]{#2}}{}% + \ifstrequal{#1}{__id}{\hyperref[sailMIPSfnzzyzyid]{#2}}{}% + \ifstrequal{#1}{_get_CapCauseReg_ExcCode}{\hyperref[sailMIPSfnzzygetzyCapCauseRegzyExcCode]{#2}}{}% + \ifstrequal{#1}{_get_CapCauseReg_RegNum}{\hyperref[sailMIPSfnzzygetzyCapCauseRegzyRegNum]{#2}}{}% + \ifstrequal{#1}{_get_CapCauseReg_bits}{\hyperref[sailMIPSfnzzygetzyCapCauseRegzybits]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_BD}{\hyperref[sailMIPSfnzzygetzyCauseRegzyBD]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_CE}{\hyperref[sailMIPSfnzzygetzyCauseRegzyCE]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_ExcCode}{\hyperref[sailMIPSfnzzygetzyCauseRegzyExcCode]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_IP}{\hyperref[sailMIPSfnzzygetzyCauseRegzyIP]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_IV}{\hyperref[sailMIPSfnzzygetzyCauseRegzyIV]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_WP}{\hyperref[sailMIPSfnzzygetzyCauseRegzyWP]{#2}}{}% + \ifstrequal{#1}{_get_CauseReg_bits}{\hyperref[sailMIPSfnzzygetzyCauseRegzybits]{#2}}{}% + \ifstrequal{#1}{_get_ContextReg_BadVPN2}{\hyperref[sailMIPSfnzzygetzyContextRegzyBadVPN2]{#2}}{}% + \ifstrequal{#1}{_get_ContextReg_PTEBase}{\hyperref[sailMIPSfnzzygetzyContextRegzyPTEBase]{#2}}{}% + \ifstrequal{#1}{_get_ContextReg_bits}{\hyperref[sailMIPSfnzzygetzyContextRegzybits]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_BEV}{\hyperref[sailMIPSfnzzygetzyStatusRegzyBEV]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_CU}{\hyperref[sailMIPSfnzzygetzyStatusRegzyCU]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_ERL}{\hyperref[sailMIPSfnzzygetzyStatusRegzyERL]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_EXL}{\hyperref[sailMIPSfnzzygetzyStatusRegzyEXL]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_IE}{\hyperref[sailMIPSfnzzygetzyStatusRegzyIE]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_IM}{\hyperref[sailMIPSfnzzygetzyStatusRegzyIM]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_KSU}{\hyperref[sailMIPSfnzzygetzyStatusRegzyKSU]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_KX}{\hyperref[sailMIPSfnzzygetzyStatusRegzyKX]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_SX}{\hyperref[sailMIPSfnzzygetzyStatusRegzySX]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_UX}{\hyperref[sailMIPSfnzzygetzyStatusRegzyUX]{#2}}{}% + \ifstrequal{#1}{_get_StatusReg_bits}{\hyperref[sailMIPSfnzzygetzyStatusRegzybits]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_ASID}{\hyperref[sailMIPSfnzzygetzyTLBEntryHiRegzyASID]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_CLGK}{\hyperref[sailMIPSfnzzygetzyTLBEntryHiRegzyCLGK]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_CLGS}{\hyperref[sailMIPSfnzzygetzyTLBEntryHiRegzyCLGS]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_CLGU}{\hyperref[sailMIPSfnzzygetzyTLBEntryHiRegzyCLGU]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_R}{\hyperref[sailMIPSfnzzygetzyTLBEntryHiRegzyR]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_VPN2}{\hyperref[sailMIPSfnzzygetzyTLBEntryHiRegzyVPN2]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryHiReg_bits}{\hyperref[sailMIPSfnzzygetzyTLBEntryHiRegzybits]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_C}{\hyperref[sailMIPSfnzzygetzyTLBEntryLoRegzyC]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_CapL}{\hyperref[sailMIPSfnzzygetzyTLBEntryLoRegzyCapL]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_CapLG}{\hyperref[sailMIPSfnzzygetzyTLBEntryLoRegzyCapLG]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_CapS}{\hyperref[sailMIPSfnzzygetzyTLBEntryLoRegzyCapS]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_D}{\hyperref[sailMIPSfnzzygetzyTLBEntryLoRegzyD]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_G}{\hyperref[sailMIPSfnzzygetzyTLBEntryLoRegzyG]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_PFN}{\hyperref[sailMIPSfnzzygetzyTLBEntryLoRegzyPFN]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_V}{\hyperref[sailMIPSfnzzygetzyTLBEntryLoRegzyV]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntryLoReg_bits}{\hyperref[sailMIPSfnzzygetzyTLBEntryLoRegzybits]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_asid}{\hyperref[sailMIPSfnzzygetzyTLBEntryzyasid]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_bits}{\hyperref[sailMIPSfnzzygetzyTLBEntryzybits]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_c0}{\hyperref[sailMIPSfnzzygetzyTLBEntryzyc0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_c1}{\hyperref[sailMIPSfnzzygetzyTLBEntryzyc1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_capl0}{\hyperref[sailMIPSfnzzygetzyTLBEntryzycapl0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_capl1}{\hyperref[sailMIPSfnzzygetzyTLBEntryzycapl1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_caplg0}{\hyperref[sailMIPSfnzzygetzyTLBEntryzycaplg0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_caplg1}{\hyperref[sailMIPSfnzzygetzyTLBEntryzycaplg1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_caps0}{\hyperref[sailMIPSfnzzygetzyTLBEntryzycaps0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_caps1}{\hyperref[sailMIPSfnzzygetzyTLBEntryzycaps1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_d0}{\hyperref[sailMIPSfnzzygetzyTLBEntryzyd0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_d1}{\hyperref[sailMIPSfnzzygetzyTLBEntryzyd1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_g}{\hyperref[sailMIPSfnzzygetzyTLBEntryzyg]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_pagemask}{\hyperref[sailMIPSfnzzygetzyTLBEntryzypagemask]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_pfn0}{\hyperref[sailMIPSfnzzygetzyTLBEntryzypfn0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_pfn1}{\hyperref[sailMIPSfnzzygetzyTLBEntryzypfn1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_r}{\hyperref[sailMIPSfnzzygetzyTLBEntryzyr]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_v0}{\hyperref[sailMIPSfnzzygetzyTLBEntryzyv0]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_v1}{\hyperref[sailMIPSfnzzygetzyTLBEntryzyv1]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_valid}{\hyperref[sailMIPSfnzzygetzyTLBEntryzyvalid]{#2}}{}% + \ifstrequal{#1}{_get_TLBEntry_vpn2}{\hyperref[sailMIPSfnzzygetzyTLBEntryzyvpn2]{#2}}{}% + \ifstrequal{#1}{_get_XContextReg_XBadVPN2}{\hyperref[sailMIPSfnzzygetzyXContextRegzyXBadVPN2]{#2}}{}% + \ifstrequal{#1}{_get_XContextReg_XPTEBase}{\hyperref[sailMIPSfnzzygetzyXContextRegzyXPTEBase]{#2}}{}% + \ifstrequal{#1}{_get_XContextReg_XR}{\hyperref[sailMIPSfnzzygetzyXContextRegzyXR]{#2}}{}% + \ifstrequal{#1}{_get_XContextReg_bits}{\hyperref[sailMIPSfnzzygetzyXContextRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_CapCauseReg_ExcCode}{\hyperref[sailMIPSfnzzysetzyCapCauseRegzyExcCode]{#2}}{}% + \ifstrequal{#1}{_set_CapCauseReg_RegNum}{\hyperref[sailMIPSfnzzysetzyCapCauseRegzyRegNum]{#2}}{}% + \ifstrequal{#1}{_set_CapCauseReg_bits}{\hyperref[sailMIPSfnzzysetzyCapCauseRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_BD}{\hyperref[sailMIPSfnzzysetzyCauseRegzyBD]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_CE}{\hyperref[sailMIPSfnzzysetzyCauseRegzyCE]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_ExcCode}{\hyperref[sailMIPSfnzzysetzyCauseRegzyExcCode]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_IP}{\hyperref[sailMIPSfnzzysetzyCauseRegzyIP]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_IV}{\hyperref[sailMIPSfnzzysetzyCauseRegzyIV]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_WP}{\hyperref[sailMIPSfnzzysetzyCauseRegzyWP]{#2}}{}% + \ifstrequal{#1}{_set_CauseReg_bits}{\hyperref[sailMIPSfnzzysetzyCauseRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_ContextReg_BadVPN2}{\hyperref[sailMIPSfnzzysetzyContextRegzyBadVPN2]{#2}}{}% + \ifstrequal{#1}{_set_ContextReg_PTEBase}{\hyperref[sailMIPSfnzzysetzyContextRegzyPTEBase]{#2}}{}% + \ifstrequal{#1}{_set_ContextReg_bits}{\hyperref[sailMIPSfnzzysetzyContextRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_BEV}{\hyperref[sailMIPSfnzzysetzyStatusRegzyBEV]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_CU}{\hyperref[sailMIPSfnzzysetzyStatusRegzyCU]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_ERL}{\hyperref[sailMIPSfnzzysetzyStatusRegzyERL]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_EXL}{\hyperref[sailMIPSfnzzysetzyStatusRegzyEXL]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_IE}{\hyperref[sailMIPSfnzzysetzyStatusRegzyIE]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_IM}{\hyperref[sailMIPSfnzzysetzyStatusRegzyIM]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_KSU}{\hyperref[sailMIPSfnzzysetzyStatusRegzyKSU]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_KX}{\hyperref[sailMIPSfnzzysetzyStatusRegzyKX]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_SX}{\hyperref[sailMIPSfnzzysetzyStatusRegzySX]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_UX}{\hyperref[sailMIPSfnzzysetzyStatusRegzyUX]{#2}}{}% + \ifstrequal{#1}{_set_StatusReg_bits}{\hyperref[sailMIPSfnzzysetzyStatusRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_ASID}{\hyperref[sailMIPSfnzzysetzyTLBEntryHiRegzyASID]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_CLGK}{\hyperref[sailMIPSfnzzysetzyTLBEntryHiRegzyCLGK]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_CLGS}{\hyperref[sailMIPSfnzzysetzyTLBEntryHiRegzyCLGS]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_CLGU}{\hyperref[sailMIPSfnzzysetzyTLBEntryHiRegzyCLGU]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_R}{\hyperref[sailMIPSfnzzysetzyTLBEntryHiRegzyR]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_VPN2}{\hyperref[sailMIPSfnzzysetzyTLBEntryHiRegzyVPN2]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryHiReg_bits}{\hyperref[sailMIPSfnzzysetzyTLBEntryHiRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_C}{\hyperref[sailMIPSfnzzysetzyTLBEntryLoRegzyC]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_CapL}{\hyperref[sailMIPSfnzzysetzyTLBEntryLoRegzyCapL]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_CapLG}{\hyperref[sailMIPSfnzzysetzyTLBEntryLoRegzyCapLG]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_CapS}{\hyperref[sailMIPSfnzzysetzyTLBEntryLoRegzyCapS]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_D}{\hyperref[sailMIPSfnzzysetzyTLBEntryLoRegzyD]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_G}{\hyperref[sailMIPSfnzzysetzyTLBEntryLoRegzyG]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_PFN}{\hyperref[sailMIPSfnzzysetzyTLBEntryLoRegzyPFN]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_V}{\hyperref[sailMIPSfnzzysetzyTLBEntryLoRegzyV]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntryLoReg_bits}{\hyperref[sailMIPSfnzzysetzyTLBEntryLoRegzybits]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_asid}{\hyperref[sailMIPSfnzzysetzyTLBEntryzyasid]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_bits}{\hyperref[sailMIPSfnzzysetzyTLBEntryzybits]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_c0}{\hyperref[sailMIPSfnzzysetzyTLBEntryzyc0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_c1}{\hyperref[sailMIPSfnzzysetzyTLBEntryzyc1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_capl0}{\hyperref[sailMIPSfnzzysetzyTLBEntryzycapl0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_capl1}{\hyperref[sailMIPSfnzzysetzyTLBEntryzycapl1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_caplg0}{\hyperref[sailMIPSfnzzysetzyTLBEntryzycaplg0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_caplg1}{\hyperref[sailMIPSfnzzysetzyTLBEntryzycaplg1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_caps0}{\hyperref[sailMIPSfnzzysetzyTLBEntryzycaps0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_caps1}{\hyperref[sailMIPSfnzzysetzyTLBEntryzycaps1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_d0}{\hyperref[sailMIPSfnzzysetzyTLBEntryzyd0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_d1}{\hyperref[sailMIPSfnzzysetzyTLBEntryzyd1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_g}{\hyperref[sailMIPSfnzzysetzyTLBEntryzyg]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_pagemask}{\hyperref[sailMIPSfnzzysetzyTLBEntryzypagemask]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_pfn0}{\hyperref[sailMIPSfnzzysetzyTLBEntryzypfn0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_pfn1}{\hyperref[sailMIPSfnzzysetzyTLBEntryzypfn1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_r}{\hyperref[sailMIPSfnzzysetzyTLBEntryzyr]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_v0}{\hyperref[sailMIPSfnzzysetzyTLBEntryzyv0]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_v1}{\hyperref[sailMIPSfnzzysetzyTLBEntryzyv1]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_valid}{\hyperref[sailMIPSfnzzysetzyTLBEntryzyvalid]{#2}}{}% + \ifstrequal{#1}{_set_TLBEntry_vpn2}{\hyperref[sailMIPSfnzzysetzyTLBEntryzyvpn2]{#2}}{}% + \ifstrequal{#1}{_set_XContextReg_XBadVPN2}{\hyperref[sailMIPSfnzzysetzyXContextRegzyXBadVPN2]{#2}}{}% + \ifstrequal{#1}{_set_XContextReg_XPTEBase}{\hyperref[sailMIPSfnzzysetzyXContextRegzyXPTEBase]{#2}}{}% + \ifstrequal{#1}{_set_XContextReg_XR}{\hyperref[sailMIPSfnzzysetzyXContextRegzyXR]{#2}}{}% + \ifstrequal{#1}{_set_XContextReg_bits}{\hyperref[sailMIPSfnzzysetzyXContextRegzybits]{#2}}{}% + \ifstrequal{#1}{_update_CapCauseReg_ExcCode}{\hyperref[sailMIPSfnzzyupdatezyCapCauseRegzyExcCode]{#2}}{}% + \ifstrequal{#1}{_update_CapCauseReg_RegNum}{\hyperref[sailMIPSfnzzyupdatezyCapCauseRegzyRegNum]{#2}}{}% + \ifstrequal{#1}{_update_CapCauseReg_bits}{\hyperref[sailMIPSfnzzyupdatezyCapCauseRegzybits]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_BD}{\hyperref[sailMIPSfnzzyupdatezyCauseRegzyBD]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_CE}{\hyperref[sailMIPSfnzzyupdatezyCauseRegzyCE]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_ExcCode}{\hyperref[sailMIPSfnzzyupdatezyCauseRegzyExcCode]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_IP}{\hyperref[sailMIPSfnzzyupdatezyCauseRegzyIP]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_IV}{\hyperref[sailMIPSfnzzyupdatezyCauseRegzyIV]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_WP}{\hyperref[sailMIPSfnzzyupdatezyCauseRegzyWP]{#2}}{}% + \ifstrequal{#1}{_update_CauseReg_bits}{\hyperref[sailMIPSfnzzyupdatezyCauseRegzybits]{#2}}{}% + \ifstrequal{#1}{_update_ContextReg_BadVPN2}{\hyperref[sailMIPSfnzzyupdatezyContextRegzyBadVPN2]{#2}}{}% + \ifstrequal{#1}{_update_ContextReg_PTEBase}{\hyperref[sailMIPSfnzzyupdatezyContextRegzyPTEBase]{#2}}{}% + \ifstrequal{#1}{_update_ContextReg_bits}{\hyperref[sailMIPSfnzzyupdatezyContextRegzybits]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_BEV}{\hyperref[sailMIPSfnzzyupdatezyStatusRegzyBEV]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_CU}{\hyperref[sailMIPSfnzzyupdatezyStatusRegzyCU]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_ERL}{\hyperref[sailMIPSfnzzyupdatezyStatusRegzyERL]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_EXL}{\hyperref[sailMIPSfnzzyupdatezyStatusRegzyEXL]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_IE}{\hyperref[sailMIPSfnzzyupdatezyStatusRegzyIE]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_IM}{\hyperref[sailMIPSfnzzyupdatezyStatusRegzyIM]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_KSU}{\hyperref[sailMIPSfnzzyupdatezyStatusRegzyKSU]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_KX}{\hyperref[sailMIPSfnzzyupdatezyStatusRegzyKX]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_SX}{\hyperref[sailMIPSfnzzyupdatezyStatusRegzySX]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_UX}{\hyperref[sailMIPSfnzzyupdatezyStatusRegzyUX]{#2}}{}% + \ifstrequal{#1}{_update_StatusReg_bits}{\hyperref[sailMIPSfnzzyupdatezyStatusRegzybits]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_ASID}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryHiRegzyASID]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_CLGK}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryHiRegzyCLGK]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_CLGS}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryHiRegzyCLGS]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_CLGU}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryHiRegzyCLGU]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_R}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryHiRegzyR]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_VPN2}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryHiRegzyVPN2]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryHiReg_bits}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryHiRegzybits]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_C}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryLoRegzyC]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_CapL}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryLoRegzyCapL]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_CapLG}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryLoRegzyCapLG]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_CapS}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryLoRegzyCapS]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_D}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryLoRegzyD]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_G}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryLoRegzyG]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_PFN}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryLoRegzyPFN]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_V}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryLoRegzyV]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntryLoReg_bits}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryLoRegzybits]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_asid}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzyasid]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_bits}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzybits]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_c0}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzyc0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_c1}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzyc1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_capl0}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzycapl0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_capl1}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzycapl1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_caplg0}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzycaplg0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_caplg1}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzycaplg1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_caps0}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzycaps0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_caps1}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzycaps1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_d0}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzyd0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_d1}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzyd1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_g}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzyg]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_pagemask}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzypagemask]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_pfn0}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzypfn0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_pfn1}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzypfn1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_r}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzyr]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_v0}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzyv0]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_v1}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzyv1]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_valid}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzyvalid]{#2}}{}% + \ifstrequal{#1}{_update_TLBEntry_vpn2}{\hyperref[sailMIPSfnzzyupdatezyTLBEntryzyvpn2]{#2}}{}% + \ifstrequal{#1}{_update_XContextReg_XBadVPN2}{\hyperref[sailMIPSfnzzyupdatezyXContextRegzyXBadVPN2]{#2}}{}% + \ifstrequal{#1}{_update_XContextReg_XPTEBase}{\hyperref[sailMIPSfnzzyupdatezyXContextRegzyXPTEBase]{#2}}{}% + \ifstrequal{#1}{_update_XContextReg_XR}{\hyperref[sailMIPSfnzzyupdatezyXContextRegzyXR]{#2}}{}% + \ifstrequal{#1}{_update_XContextReg_bits}{\hyperref[sailMIPSfnzzyupdatezyXContextRegzybits]{#2}}{}% + \ifstrequal{#1}{addrWrapper}{\hyperref[sailMIPSfnzaddrWrapper]{#2}}{}% + \ifstrequal{#1}{addrWrapperUnaligned}{\hyperref[sailMIPSfnzaddrWrapperUnaligned]{#2}}{}% + \ifstrequal{#1}{bit_to_bool}{\hyperref[sailMIPSfnzbitzytozybool]{#2}}{}% + \ifstrequal{#1}{bits_to_bool}{\hyperref[sailMIPSfnzbitszytozybool]{#2}}{}% + \ifstrequal{#1}{bool_to_bit}{\hyperref[sailMIPSfnzboolzytozybit]{#2}}{}% + \ifstrequal{#1}{bool_to_bits}{\hyperref[sailMIPSfnzboolzytozybits]{#2}}{}% + \ifstrequal{#1}{capBitsToCapability}{\hyperref[sailMIPSfnzcapBitsToCapability]{#2}}{}% + \ifstrequal{#1}{capBoundsEqual}{\hyperref[sailMIPSfnzcapBoundsEqual]{#2}}{}% + \ifstrequal{#1}{capToBits}{\hyperref[sailMIPSfnzcapToBits]{#2}}{}% + \ifstrequal{#1}{capToMemBits}{\hyperref[sailMIPSfnzcapToMemBits]{#2}}{}% + \ifstrequal{#1}{capToString}{\hyperref[sailMIPSfnzcapToString]{#2}}{}% + \ifstrequal{#1}{cast_unit_vec}{\hyperref[sailMIPSfnzcastzyunitzyvec]{#2}}{}% + \ifstrequal{#1}{checkCP0Access}{\hyperref[sailMIPSfnzcheckCP0Access]{#2}}{}% + \ifstrequal{#1}{checkCP0AccessHook}{\hyperref[sailMIPSfnzcheckCP0AccessHook]{#2}}{}% + \ifstrequal{#1}{checkCP2usable}{\hyperref[sailMIPSfnzcheckCP2usable]{#2}}{}% + \ifstrequal{#1}{checkDDCPerms}{\hyperref[sailMIPSfnzcheckDDCPerms]{#2}}{}% + \ifstrequal{#1}{compare}{\hyperref[sailMIPSfnzcompare]{#2}}{}% + \ifstrequal{#1}{concat_str_bits}{\hyperref[sailMIPSfnzconcatzystrzybits]{#2}}{}% + \ifstrequal{#1}{concat_str_dec}{\hyperref[sailMIPSfnzconcatzystrzydec]{#2}}{}% + \ifstrequal{#1}{cp2_next_pc}{\hyperref[sailMIPSfnzcp2zynextzypc]{#2}}{}% + \ifstrequal{#1}{decode_failure_of_num}{\hyperref[sailMIPSfnzdecodezyfailurezyofzynum]{#2}}{}% + \ifstrequal{#1}{dump_cp2_state}{\hyperref[sailMIPSfnzdumpzycp2zystate]{#2}}{}% + \ifstrequal{#1}{eq_unit}{\hyperref[sailMIPSfnzeqzyunit]{#2}}{}% + \ifstrequal{#1}{exceptionVectorBase}{\hyperref[sailMIPSfnzexceptionVectorBase]{#2}}{}% + \ifstrequal{#1}{exceptionVectorOffset}{\hyperref[sailMIPSfnzexceptionVectorOffset]{#2}}{}% + \ifstrequal{#1}{execute_branch}{\hyperref[sailMIPSfnzexecutezybranch]{#2}}{}% + \ifstrequal{#1}{execute_branch_mips}{\hyperref[sailMIPSfnzexecutezybranchzymips]{#2}}{}% + \ifstrequal{#1}{execute_branch_pcc}{\hyperref[sailMIPSfnzexecutezybranchzypcc]{#2}}{}% + \ifstrequal{#1}{extendLoad}{\hyperref[sailMIPSfnzextendLoad]{#2}}{}% + \ifstrequal{#1}{fdiv_int}{\hyperref[sailMIPSfnzfdivzyint]{#2}}{}% + \ifstrequal{#1}{fmod_int}{\hyperref[sailMIPSfnzfmodzyint]{#2}}{}% + \ifstrequal{#1}{getAccessLevel}{\hyperref[sailMIPSfnzgetAccessLevel]{#2}}{}% + \ifstrequal{#1}{getCapBase}{\hyperref[sailMIPSfnzgetCapBase]{#2}}{}% + \ifstrequal{#1}{getCapBounds}{\hyperref[sailMIPSfnzgetCapBounds]{#2}}{}% + \ifstrequal{#1}{getCapCursor}{\hyperref[sailMIPSfnzgetCapCursor]{#2}}{}% + \ifstrequal{#1}{getCapFlags}{\hyperref[sailMIPSfnzgetCapFlags]{#2}}{}% + \ifstrequal{#1}{getCapHardPerms}{\hyperref[sailMIPSfnzgetCapHardPerms]{#2}}{}% + \ifstrequal{#1}{getCapLength}{\hyperref[sailMIPSfnzgetCapLength]{#2}}{}% + \ifstrequal{#1}{getCapOffset}{\hyperref[sailMIPSfnzgetCapOffset]{#2}}{}% + \ifstrequal{#1}{getCapPerms}{\hyperref[sailMIPSfnzgetCapPerms]{#2}}{}% + \ifstrequal{#1}{getCapTop}{\hyperref[sailMIPSfnzgetCapTop]{#2}}{}% + \ifstrequal{#1}{getRepresentableAlignmentMask}{\hyperref[sailMIPSfnzgetRepresentableAlignmentMask]{#2}}{}% + \ifstrequal{#1}{getRepresentableLength}{\hyperref[sailMIPSfnzgetRepresentableLength]{#2}}{}% + \ifstrequal{#1}{get_CP0EPC}{\hyperref[sailMIPSfnzgetzyCP0EPC]{#2}}{}% + \ifstrequal{#1}{get_CP0ErrorEPC}{\hyperref[sailMIPSfnzgetzyCP0ErrorEPC]{#2}}{}% + \ifstrequal{#1}{grantsAccess}{\hyperref[sailMIPSfnzgrantsAccess]{#2}}{}% + \ifstrequal{#1}{hasReservedOType}{\hyperref[sailMIPSfnzhasReservedOType]{#2}}{}% + \ifstrequal{#1}{incCapOffset}{\hyperref[sailMIPSfnzincCapOffset]{#2}}{}% + \ifstrequal{#1}{incrementCP0Count}{\hyperref[sailMIPSfnzincrementCP0Count]{#2}}{}% + \ifstrequal{#1}{init_cp0_state}{\hyperref[sailMIPSfnzinitzycp0zystate]{#2}}{}% + \ifstrequal{#1}{init_cp2_state}{\hyperref[sailMIPSfnzinitzycp2zystate]{#2}}{}% + \ifstrequal{#1}{int_of_AccessLevel}{\hyperref[sailMIPSfnzintzyofzyAccessLevel]{#2}}{}% + \ifstrequal{#1}{isAddressAligned}{\hyperref[sailMIPSfnzisAddressAligned]{#2}}{}% + \ifstrequal{#1}{isSentryCap}{\hyperref[sailMIPSfnzisSentryCap]{#2}}{}% + \ifstrequal{#1}{is_none}{\hyperref[sailMIPSfnziszynone]{#2}}{}% + \ifstrequal{#1}{is_some}{\hyperref[sailMIPSfnziszysome]{#2}}{}% + \ifstrequal{#1}{mask}{\hyperref[sailMIPSfnzmask]{#2}}{}% + \ifstrequal{#1}{memBitsToCapability}{\hyperref[sailMIPSfnzmemBitsToCapability]{#2}}{}% + \ifstrequal{#1}{mips_sign_extend}{\hyperref[sailMIPSfnzmipszysignzyextend]{#2}}{}% + \ifstrequal{#1}{mips_zero_extend}{\hyperref[sailMIPSfnzmipszyzzerozyextend]{#2}}{}% + \ifstrequal{#1}{neq_anything}{\hyperref[sailMIPSfnzneqzyanything]{#2}}{}% + \ifstrequal{#1}{neq_bits}{\hyperref[sailMIPSfnzneqzybits]{#2}}{}% + \ifstrequal{#1}{neq_bool}{\hyperref[sailMIPSfnzneqzybool]{#2}}{}% + \ifstrequal{#1}{neq_int}{\hyperref[sailMIPSfnzneqzyint]{#2}}{}% + \ifstrequal{#1}{num_of_AccessLevel}{\hyperref[sailMIPSfnznumzyofzyAccessLevel]{#2}}{}% + \ifstrequal{#1}{num_of_CPtrCmpOp}{\hyperref[sailMIPSfnznumzyofzyCPtrCmpOp]{#2}}{}% + \ifstrequal{#1}{num_of_CapEx}{\hyperref[sailMIPSfnznumzyofzyCapEx]{#2}}{}% + \ifstrequal{#1}{num_of_ClearRegSet}{\hyperref[sailMIPSfnznumzyofzyClearRegSet]{#2}}{}% + \ifstrequal{#1}{num_of_Comparison}{\hyperref[sailMIPSfnznumzyofzyComparison]{#2}}{}% + \ifstrequal{#1}{num_of_Exception}{\hyperref[sailMIPSfnznumzyofzyException]{#2}}{}% + \ifstrequal{#1}{num_of_MemAccessCapRestriction}{\hyperref[sailMIPSfnznumzyofzyMemAccessCapRestriction]{#2}}{}% + \ifstrequal{#1}{num_of_MemAccessType}{\hyperref[sailMIPSfnznumzyofzyMemAccessType]{#2}}{}% + \ifstrequal{#1}{num_of_WordType}{\hyperref[sailMIPSfnznumzyofzyWordType]{#2}}{}% + \ifstrequal{#1}{num_of_WordTypeUnaligned}{\hyperref[sailMIPSfnznumzyofzyWordTypeUnaligned]{#2}}{}% + \ifstrequal{#1}{num_of_decode_failure}{\hyperref[sailMIPSfnznumzyofzydecodezyfailure]{#2}}{}% + \ifstrequal{#1}{ones_implicit}{\hyperref[sailMIPSfnzoneszyimplicit]{#2}}{}% + \ifstrequal{#1}{pcc_access_system_regs}{\hyperref[sailMIPSfnzpcczyaccesszysystemzyregs]{#2}}{}% + \ifstrequal{#1}{rGPR}{\hyperref[sailMIPSfnzrGPR]{#2}}{}% + \ifstrequal{#1}{raise_c2_exception}{\hyperref[sailMIPSfnzraisezyc2zyexception]{#2}}{}% + \ifstrequal{#1}{raise_c2_exception8}{\hyperref[sailMIPSfnzraisezyc2zyexception8]{#2}}{}% + \ifstrequal{#1}{raise_c2_exception_badaddr}{\hyperref[sailMIPSfnzraisezyc2zyexceptionzybadaddr]{#2}}{}% + \ifstrequal{#1}{raise_c2_exception_noreg}{\hyperref[sailMIPSfnzraisezyc2zyexceptionzynoreg]{#2}}{}% + \ifstrequal{#1}{readCapReg}{\hyperref[sailMIPSfnzreadCapReg]{#2}}{}% + \ifstrequal{#1}{readCapRegDDC}{\hyperref[sailMIPSfnzreadCapRegDDC]{#2}}{}% + \ifstrequal{#1}{sail_mask}{\hyperref[sailMIPSfnzsailzymask]{#2}}{}% + \ifstrequal{#1}{sail_ones}{\hyperref[sailMIPSfnzsailzyones]{#2}}{}% + \ifstrequal{#1}{sealCap}{\hyperref[sailMIPSfnzsealCap]{#2}}{}% + \ifstrequal{#1}{setCapAddr}{\hyperref[sailMIPSfnzsetCapAddr]{#2}}{}% + \ifstrequal{#1}{setCapBounds}{\hyperref[sailMIPSfnzsetCapBounds]{#2}}{}% + \ifstrequal{#1}{setCapFlags}{\hyperref[sailMIPSfnzsetCapFlags]{#2}}{}% + \ifstrequal{#1}{setCapOffset}{\hyperref[sailMIPSfnzsetCapOffset]{#2}}{}% + \ifstrequal{#1}{setCapPerms}{\hyperref[sailMIPSfnzsetCapPerms]{#2}}{}% + \ifstrequal{#1}{set_CP0EPC}{\hyperref[sailMIPSfnzsetzyCP0EPC]{#2}}{}% + \ifstrequal{#1}{set_CP0ErrorEPC}{\hyperref[sailMIPSfnzsetzyCP0ErrorEPC]{#2}}{}% + \ifstrequal{#1}{set_next_pcc}{\hyperref[sailMIPSfnzsetzynextzypcc]{#2}}{}% + \ifstrequal{#1}{slice_mask}{\hyperref[sailMIPSfnzslicezymask]{#2}}{}% + \ifstrequal{#1}{strCCArgs}{\hyperref[sailMIPSfnzstrCCArgs]{#2}}{}% + \ifstrequal{#1}{strCCCArgs}{\hyperref[sailMIPSfnzstrCCCArgs]{#2}}{}% + \ifstrequal{#1}{strCCIArgs}{\hyperref[sailMIPSfnzstrCCIArgs]{#2}}{}% + \ifstrequal{#1}{strCCIUArgs}{\hyperref[sailMIPSfnzstrCCIUArgs]{#2}}{}% + \ifstrequal{#1}{strCCRArgs}{\hyperref[sailMIPSfnzstrCCRArgs]{#2}}{}% + \ifstrequal{#1}{strCRArgs}{\hyperref[sailMIPSfnzstrCRArgs]{#2}}{}% + \ifstrequal{#1}{strCReg}{\hyperref[sailMIPSfnzstrCReg]{#2}}{}% + \ifstrequal{#1}{strCmp}{\hyperref[sailMIPSfnzstrCmp]{#2}}{}% + \ifstrequal{#1}{strMemArgs}{\hyperref[sailMIPSfnzstrMemArgs]{#2}}{}% + \ifstrequal{#1}{strRCArgs}{\hyperref[sailMIPSfnzstrRCArgs]{#2}}{}% + \ifstrequal{#1}{strRCCArgs}{\hyperref[sailMIPSfnzstrRCCArgs]{#2}}{}% + \ifstrequal{#1}{strRCRArgs}{\hyperref[sailMIPSfnzstrRCRArgs]{#2}}{}% + \ifstrequal{#1}{strRIArgs}{\hyperref[sailMIPSfnzstrRIArgs]{#2}}{}% + \ifstrequal{#1}{strRRArgs}{\hyperref[sailMIPSfnzstrRRArgs]{#2}}{}% + \ifstrequal{#1}{strRRIArgs}{\hyperref[sailMIPSfnzstrRRIArgs]{#2}}{}% + \ifstrequal{#1}{strRRIUArgs}{\hyperref[sailMIPSfnzstrRRIUArgs]{#2}}{}% + \ifstrequal{#1}{strRRRArgs}{\hyperref[sailMIPSfnzstrRRRArgs]{#2}}{}% + \ifstrequal{#1}{strReg}{\hyperref[sailMIPSfnzstrReg]{#2}}{}% + \ifstrequal{#1}{strWordType}{\hyperref[sailMIPSfnzstrWordType]{#2}}{}% + \ifstrequal{#1}{string_of_capex}{\hyperref[sailMIPSfnzstringzyofzycapex]{#2}}{}% + \ifstrequal{#1}{string_of_exception}{\hyperref[sailMIPSfnzstringzyofzyexception]{#2}}{}% + \ifstrequal{#1}{supported_instructions}{\hyperref[sailMIPSfnzsupportedzyinstructions]{#2}}{}% + \ifstrequal{#1}{tlbEntryMatch}{\hyperref[sailMIPSfnztlbEntryMatch]{#2}}{}% + \ifstrequal{#1}{tlbSearch}{\hyperref[sailMIPSfnztlbSearch]{#2}}{}% + \ifstrequal{#1}{to_bits}{\hyperref[sailMIPSfnztozybits]{#2}}{}% + \ifstrequal{#1}{traceException}{\hyperref[sailMIPSfnztraceException]{#2}}{}% + \ifstrequal{#1}{unalignedBytesTouched}{\hyperref[sailMIPSfnzunalignedBytesTouched]{#2}}{}% + \ifstrequal{#1}{unrepCap}{\hyperref[sailMIPSfnzunrepCap]{#2}}{}% + \ifstrequal{#1}{unsealCap}{\hyperref[sailMIPSfnzunsealCap]{#2}}{}% + \ifstrequal{#1}{updateBadInstr}{\hyperref[sailMIPSfnzupdateBadInstr]{#2}}{}% + \ifstrequal{#1}{wGPR}{\hyperref[sailMIPSfnzwGPR]{#2}}{}% + \ifstrequal{#1}{wordWidthBytes}{\hyperref[sailMIPSfnzwordWidthBytes]{#2}}{}% + \ifstrequal{#1}{writeCapReg}{\hyperref[sailMIPSfnzwriteCapReg]{#2}}{}% + \ifstrequal{#1}{zeros_implicit}{\hyperref[sailMIPSfnzzzeroszyimplicit]{#2}}{}% + \ifstrequal{#1}{(operator <_s)}{\hyperref[sailMIPSfnzz8operatorz0zIzysz9]{#2}}{}% + \ifstrequal{#1}{(operator <_u)}{\hyperref[sailMIPSfnzz8operatorz0zIzyuz9]{#2}}{}% + \ifstrequal{#1}{(operator >=_s)}{\hyperref[sailMIPSfnzz8operatorz0zKzJzysz9]{#2}}{}% + \ifstrequal{#1}{(operator >=_u)}{\hyperref[sailMIPSfnzz8operatorz0zKzJzyuz9]{#2}}{}% + \ifstrequal{#1}{(operator ^^)}{\hyperref[sailMIPSfnzz8operatorz0zQzQz9]{#2}}{}} + +\newcommand{\sailMIPStype}[1]{ + \ifstrequal{#1}{AccessLevel}{\sailMIPStypeAccessLevel}{}% + \ifstrequal{#1}{CFlags}{\sailMIPStypeCFlags}{}% + \ifstrequal{#1}{CPtrCmpOp}{\sailMIPStypeCPtrCmpOp}{}% + \ifstrequal{#1}{CapBits}{\sailMIPStypeCapBits}{}% + \ifstrequal{#1}{CapCauseReg}{\sailMIPStypeCapCauseReg}{}% + \ifstrequal{#1}{CapEx}{\sailMIPStypeCapEx}{}% + \ifstrequal{#1}{CapHwrEnc}{\sailMIPStypeCapHwrEnc}{}% + \ifstrequal{#1}{CapLen}{\sailMIPStypeCapLen}{}% + \ifstrequal{#1}{CapRegEnc}{\sailMIPStypeCapRegEnc}{}% + \ifstrequal{#1}{CapRegOrDDCEnc}{\sailMIPStypeCapRegOrDDCEnc}{}% + \ifstrequal{#1}{Capability}{\sailMIPStypeCapability}{}% + \ifstrequal{#1}{CauseReg}{\sailMIPStypeCauseReg}{}% + \ifstrequal{#1}{ClearRegSet}{\sailMIPStypeClearRegSet}{}% + \ifstrequal{#1}{Comparison}{\sailMIPStypeComparison}{}% + \ifstrequal{#1}{ContextReg}{\sailMIPStypeContextReg}{}% + \ifstrequal{#1}{Exception}{\sailMIPStypeException}{}% + \ifstrequal{#1}{IntRegEnc}{\sailMIPStypeIntRegEnc}{}% + \ifstrequal{#1}{MemAccessCapRestriction}{\sailMIPStypeMemAccessCapRestriction}{}% + \ifstrequal{#1}{MemAccessType}{\sailMIPStypeMemAccessType}{}% + \ifstrequal{#1}{StatusReg}{\sailMIPStypeStatusReg}{}% + \ifstrequal{#1}{TLBEntry}{\sailMIPStypeTLBEntry}{}% + \ifstrequal{#1}{TLBEntryHiReg}{\sailMIPStypeTLBEntryHiReg}{}% + \ifstrequal{#1}{TLBEntryLoReg}{\sailMIPStypeTLBEntryLoReg}{}% + \ifstrequal{#1}{TLBIndexT}{\sailMIPStypeTLBIndexT}{}% + \ifstrequal{#1}{WordType}{\sailMIPStypeWordType}{}% + \ifstrequal{#1}{WordTypeUnaligned}{\sailMIPStypeWordTypeUnaligned}{}% + \ifstrequal{#1}{XContextReg}{\sailMIPStypeXContextReg}{}% + \ifstrequal{#1}{ast}{\sailMIPStypeast}{}% + \ifstrequal{#1}{bits}{\sailMIPStypebits}{}% + \ifstrequal{#1}{decode\_failure}{\sailMIPStypedecodeFailure}{}% + \ifstrequal{#1}{exception}{\sailMIPStypeexception}{}% + \ifstrequal{#1}{imm16}{\sailMIPStypeimmOneSix}{}% + \ifstrequal{#1}{num\_flags\_t}{\sailMIPStypenumFlagsT}{}% + \ifstrequal{#1}{option}{\sailMIPStypeoption}{}% + \ifstrequal{#1}{regno}{\sailMIPStyperegno}{}% + \ifstrequal{#1}{uint64}{\sailMIPStypeuintSixFour}{}} + +\newcommand{\sailMIPSreftype}[2]{ + \ifstrequal{#1}{AccessLevel}{\hyperref[sailMIPStypezAccessLevel]{#2}}{}% + \ifstrequal{#1}{CFlags}{\hyperref[sailMIPStypezCFlags]{#2}}{}% + \ifstrequal{#1}{CPtrCmpOp}{\hyperref[sailMIPStypezCPtrCmpOp]{#2}}{}% + \ifstrequal{#1}{CapBits}{\hyperref[sailMIPStypezCapBits]{#2}}{}% + \ifstrequal{#1}{CapCauseReg}{\hyperref[sailMIPStypezCapCauseReg]{#2}}{}% + \ifstrequal{#1}{CapEx}{\hyperref[sailMIPStypezCapEx]{#2}}{}% + \ifstrequal{#1}{CapHwrEnc}{\hyperref[sailMIPStypezCapHwrEnc]{#2}}{}% + \ifstrequal{#1}{CapLen}{\hyperref[sailMIPStypezCapLen]{#2}}{}% + \ifstrequal{#1}{CapRegEnc}{\hyperref[sailMIPStypezCapRegEnc]{#2}}{}% + \ifstrequal{#1}{CapRegOrDDCEnc}{\hyperref[sailMIPStypezCapRegOrDDCEnc]{#2}}{}% + \ifstrequal{#1}{Capability}{\hyperref[sailMIPStypezCapability]{#2}}{}% + \ifstrequal{#1}{CauseReg}{\hyperref[sailMIPStypezCauseReg]{#2}}{}% + \ifstrequal{#1}{ClearRegSet}{\hyperref[sailMIPStypezClearRegSet]{#2}}{}% + \ifstrequal{#1}{Comparison}{\hyperref[sailMIPStypezComparison]{#2}}{}% + \ifstrequal{#1}{ContextReg}{\hyperref[sailMIPStypezContextReg]{#2}}{}% + \ifstrequal{#1}{Exception}{\hyperref[sailMIPStypezException]{#2}}{}% + \ifstrequal{#1}{IntRegEnc}{\hyperref[sailMIPStypezIntRegEnc]{#2}}{}% + \ifstrequal{#1}{MemAccessCapRestriction}{\hyperref[sailMIPStypezMemAccessCapRestriction]{#2}}{}% + \ifstrequal{#1}{MemAccessType}{\hyperref[sailMIPStypezMemAccessType]{#2}}{}% + \ifstrequal{#1}{StatusReg}{\hyperref[sailMIPStypezStatusReg]{#2}}{}% + \ifstrequal{#1}{TLBEntry}{\hyperref[sailMIPStypezTLBEntry]{#2}}{}% + \ifstrequal{#1}{TLBEntryHiReg}{\hyperref[sailMIPStypezTLBEntryHiReg]{#2}}{}% + \ifstrequal{#1}{TLBEntryLoReg}{\hyperref[sailMIPStypezTLBEntryLoReg]{#2}}{}% + \ifstrequal{#1}{TLBIndexT}{\hyperref[sailMIPStypezTLBIndexT]{#2}}{}% + \ifstrequal{#1}{WordType}{\hyperref[sailMIPStypezWordType]{#2}}{}% + \ifstrequal{#1}{WordTypeUnaligned}{\hyperref[sailMIPStypezWordTypeUnaligned]{#2}}{}% + \ifstrequal{#1}{XContextReg}{\hyperref[sailMIPStypezXContextReg]{#2}}{}% + \ifstrequal{#1}{ast}{\hyperref[sailMIPStypezast]{#2}}{}% + \ifstrequal{#1}{bits}{\hyperref[sailMIPStypezbits]{#2}}{}% + \ifstrequal{#1}{decode_failure}{\hyperref[sailMIPStypezdecodezyfailure]{#2}}{}% + \ifstrequal{#1}{exception}{\hyperref[sailMIPStypezexception]{#2}}{}% + \ifstrequal{#1}{imm16}{\hyperref[sailMIPStypezimm16]{#2}}{}% + \ifstrequal{#1}{num_flags_t}{\hyperref[sailMIPStypeznumzyflagszyt]{#2}}{}% + \ifstrequal{#1}{option}{\hyperref[sailMIPStypezoption]{#2}}{}% + \ifstrequal{#1}{regno}{\hyperref[sailMIPStypezregno]{#2}}{}% + \ifstrequal{#1}{uint64}{\hyperref[sailMIPStypezuint64]{#2}}{}} diff --git a/sail_latex_mips/fclCAndAddrzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCAndAddrzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..8504b3b5 --- /dev/null +++ b/sail_latex_mips/fclCAndAddrzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCAndAddr]{CAndAddr}#(cd, cs, rt)) = "candaddr " ^ #\hyperref[sailMIPSzstrCCRArgs]{strCCRArgs}#(cd, cs, rt) diff --git a/sail_latex_mips/fclCAndAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCAndAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..71195c79 --- /dev/null +++ b/sail_latex_mips/fclCAndAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegEnc @ rt : IntRegEnc @ 0b100100) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCAndAddr]{CAndAddr}#(cd, cs, rt)) diff --git a/sail_latex_mips/fclCAndAddrzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCAndAddrzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..fbc32682 --- /dev/null +++ b/sail_latex_mips/fclCAndAddrzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let rt_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rt); +if cb_val.tag & cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else +{ + let newAddr = cb_val.address & rt_val; + let (representable, newCap) = #\hyperref[sailMIPSzsetCapAddr]{setCapAddr}#(cb_val, newAddr); + if representable then + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) + else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, #\hyperref[sailMIPSzunrepCap]{unrepCap}#(newCap)); +} diff --git a/sail_latex_mips/fclCAndPermAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCAndPermAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..1c0515fb --- /dev/null +++ b/sail_latex_mips/fclCAndPermAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegEnc @ rt : IntRegEnc @ 0b001101) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCAndPerm]{CAndPerm}#(cd, cs, rt)) diff --git a/sail_latex_mips/fclCAndPermzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCAndPermzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..0e3a12c9 --- /dev/null +++ b/sail_latex_mips/fclCAndPermzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCAndPerm]{CAndPerm}#(cd, cs, rt)) = "candperm " ^ #\hyperref[sailMIPSzstrCCRArgs]{strCCRArgs}#(cd, cs, rt) diff --git a/sail_latex_mips/fclCAndPermzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCAndPermzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..e58ec1fb --- /dev/null +++ b/sail_latex_mips/fclCAndPermzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00100 @ cd : CapRegEnc @ cb : CapRegEnc @ rt : IntRegEnc @ 0b000 @ 0b000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCAndPerm]{CAndPerm}#(cd, cb, rt)) diff --git a/sail_latex_mips/fclCAndPermzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCAndPermzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d3558afd --- /dev/null +++ b/sail_latex_mips/fclCAndPermzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,13 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let rt_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rt); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else +{ + let perms = #\hyperref[sailMIPSzgetCapPerms]{getCapPerms}#(cb_val); + let newCap = #\hyperref[sailMIPSzsetCapPerms]{setCapPerms}#(cb_val, (perms & rt_val[30..0])); + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap); +} diff --git a/sail_latex_mips/fclCBXAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCBXAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..2bb5bef8 --- /dev/null +++ b/sail_latex_mips/fclCBXAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01010 @ cd : CapRegEnc @ imm : #\hyperref[sailMIPSzbits]{bits}#(16)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCBX]{CBX}#(cd, imm, false)) /* CBTS */ diff --git a/sail_latex_mips/fclCBXzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCBXzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..7a11cb89 --- /dev/null +++ b/sail_latex_mips/fclCBXzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01001 @ cd : CapRegEnc @ imm : #\hyperref[sailMIPSzbits]{bits}#(16)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCBX]{CBX}#(cd, imm, true)) /* CBTU */ diff --git a/sail_latex_mips/fclCBXzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCBXzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..8359fb43 --- /dev/null +++ b/sail_latex_mips/fclCBXzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,10 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +if InBranchDelay then + #\hyperref[sailMIPSzSignalException]{SignalException}#(ResI); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +if cb_val.tag ^ notset then +{ + let offset : #\hyperref[sailMIPSzbits]{bits}#(64) = #\hyperref[sailMIPSzsignzyextend]{sign\_extend}#(imm @ 0b00) + 4; + #\hyperref[sailMIPSzexecutezybranch]{execute\_branch}#(PC + offset); +}; +NextInBranchDelay = 0b1; diff --git a/sail_latex_mips/fclCBZAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCBZAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..0a6fddd7 --- /dev/null +++ b/sail_latex_mips/fclCBZAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10010 @ cd : CapRegEnc @ imm : #\hyperref[sailMIPSzbits]{bits}#(16)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCBZ]{CBZ}#(cd, imm, true)) /* CBNZ */ diff --git a/sail_latex_mips/fclCBZzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCBZzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..54d3c09d --- /dev/null +++ b/sail_latex_mips/fclCBZzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10001 @ cd : CapRegEnc @ imm : #\hyperref[sailMIPSzbits]{bits}#(16)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCBZ]{CBZ}#(cd, imm, false)) /* CBEZ */ diff --git a/sail_latex_mips/fclCBZzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCBZzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..ad77933d --- /dev/null +++ b/sail_latex_mips/fclCBZzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,10 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +if InBranchDelay then + #\hyperref[sailMIPSzSignalException]{SignalException}#(ResI); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +if (cb_val == null_cap) ^ notzero then +{ + let offset : #\hyperref[sailMIPSzbits]{bits}#(64) = #\hyperref[sailMIPSzsignzyextend]{sign\_extend}#(imm @ 0b00) + 4; + #\hyperref[sailMIPSzexecutezybranch]{execute\_branch}#(PC + offset); +}; +NextInBranchDelay = 0b1; diff --git a/sail_latex_mips/fclCBuildCapzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCBuildCapzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..997bcb26 --- /dev/null +++ b/sail_latex_mips/fclCBuildCapzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCBuildCap]{CBuildCap}#(cd, cs, ct)) = "cbuildcap " ^ #\hyperref[sailMIPSzstrCCCArgs]{strCCCArgs}#(cd, cs, ct) diff --git a/sail_latex_mips/fclCBuildCapzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCBuildCapzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..c07a7824 --- /dev/null +++ b/sail_latex_mips/fclCBuildCapzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cb : CapRegOrDDCEnc @ ct : CapRegEnc @ 0b011101) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCBuildCap]{CBuildCap}#(cd, cb, ct)) diff --git a/sail_latex_mips/fclCBuildCapzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCBuildCapzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e1e60c1e --- /dev/null +++ b/sail_latex_mips/fclCBuildCapzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,33 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +let ct_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(ct); +let cb_base = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val); +let ct_base = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(ct_val); +let cb_top = #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val); +let ct_top = #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(ct_val); +let cb_perms = #\hyperref[sailMIPSzgetCapPerms]{getCapPerms}#(cb_val); +let ct_perms = #\hyperref[sailMIPSzgetCapPerms]{getCapPerms}#(ct_val); +let ct_offset = #\hyperref[sailMIPSzgetCapOffset]{getCapOffset}#(ct_val); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if ct_base < cb_base then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) +else if ct_top > cb_top then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if ct_base > ct_top then /* check for length < 0 - possible because ct might be untagged */ + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) + else if (ct_perms & cb_perms) != ct_perms then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_UserDefViolation, cb) +else +{ + let (exact, cd1) = #\hyperref[sailMIPSzsetCapBounds]{setCapBounds}#(cb_val, #\hyperref[sailMIPSztozybits]{to\_bits}#(64, ct_base), #\hyperref[sailMIPSztozybits]{to\_bits}#(65, ct_top)); + let (representable, cd2) = #\hyperref[sailMIPSzsetCapOffset]{setCapOffset}#(cd1, #\hyperref[sailMIPSztozybits]{to\_bits}#(64, ct_offset)); + let cd3 = #\hyperref[sailMIPSzsetCapPerms]{setCapPerms}#(cd2, ct_perms); + { + assert(exact, "CBuildCap: setCapBounds was not exact"); /* base and top came from ct originally so will be exact */ + assert(representable, "CBuildCap: offset was not representable"); /* similarly offset should be representable XXX except for fastRepCheck */ + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, cd3); + } +} diff --git a/sail_latex_mips/fclCCSealzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCCSealzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..642ee629 --- /dev/null +++ b/sail_latex_mips/fclCCSealzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCCSeal]{CCSeal}#(cd, cs, ct)) = "ccseal " ^ #\hyperref[sailMIPSzstrCCCArgs]{strCCCArgs}#(cd, cs, ct) diff --git a/sail_latex_mips/fclCCSealzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCCSealzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..68952676 --- /dev/null +++ b/sail_latex_mips/fclCCSealzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegEnc @ ct : CapRegEnc @ 0b011111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCCSeal]{CCSeal}#(cd, cs, ct)) diff --git a/sail_latex_mips/fclCCSealzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCCSealzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..cba9834a --- /dev/null +++ b/sail_latex_mips/fclCCSealzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,43 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cs_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cs); +let ct_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(ct); +let ct_cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(ct_val); +let ct_top = #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(ct_val); +let ct_base = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(ct_val); +if not (cs_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) +else if (ct_val.address == otype_sentry_bits) then { + if cs_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) + else if not(cs_val.permit_execute) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitExecuteViolation, cs) + else + { + let (success, newCap) = #\hyperref[sailMIPSzsealCap]{sealCap}#(cs_val, #\hyperref[sailMIPSztozybits]{to\_bits}#(24, otype_sentry)); + if not (success) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_InexactBounds, cs) + else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) + } +} else if not(ct_val.tag) | (ct_val.address == otype_unsealed_bits) then + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, cs_val) /* unsealed, just copy cs */ +else if cs_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) +else if ct_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, ct) +else if not (ct_val.permit_seal) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitSealViolation, ct) +else if ct_cursor < ct_base then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) +else if ct_cursor >= ct_top then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) +else if ct_cursor > max_otype then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TypeViolation, ct) +else +{ + let (success, newCap) = #\hyperref[sailMIPSzsealCap]{sealCap}#(cs_val, #\hyperref[sailMIPSztozybits]{to\_bits}#(24, ct_cursor)); + if not (success) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_InexactBounds, cs) + else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) +} diff --git a/sail_latex_mips/fclCCallAzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCCallAzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..ec442347 --- /dev/null +++ b/sail_latex_mips/fclCCallAzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,35 @@ +/* Jump-like implementation of CCall that unseals arguments */ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +if InBranchDelay then + #\hyperref[sailMIPSzSignalException]{SignalException}#(ResI); +let cs_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cs); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let cs_cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cs_val); +if not (cs_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) +else if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if #\hyperref[sailMIPSzhasReservedOType]{hasReservedOType}#(cs_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) +else if #\hyperref[sailMIPSzhasReservedOType]{hasReservedOType}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if cs_val.otype != cb_val.otype then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TypeViolation, cs) +else if not (cs_val.permit_ccall) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitCCallViolation, cs) +else if not (cb_val.permit_ccall) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitCCallViolation, cb) +else if not (cs_val.permit_execute) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitExecuteViolation, cs) +else if cb_val.permit_execute then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitExecuteViolation, cb) +else if cs_cursor < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cs_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cs) +else if cs_cursor >= #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cs_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cs) +else +{ + #\hyperref[sailMIPSzsetzynextzypcc]{set\_next\_pcc}#(#\hyperref[sailMIPSzunsealCap]{unsealCap}#(cs_val)); + C26 = #\hyperref[sailMIPSzunsealCap]{unsealCap}#(cb_val); + NextPC = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzgetCapOffset]{getCapOffset}#(cs_val)); +} diff --git a/sail_latex_mips/fclCCallzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCCallzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..29f1fb09 --- /dev/null +++ b/sail_latex_mips/fclCCallzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCCall]{CCall}#(cs, cb, selector)) = "ccall " ^ #\hyperref[sailMIPSzstrCCIUArgs]{strCCIUArgs}#(cs, cb, selector) diff --git a/sail_latex_mips/fclCCallzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCCallzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..08dce182 --- /dev/null +++ b/sail_latex_mips/fclCCallzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00101 @ cs : CapRegEnc @ cb : CapRegEnc @ selector : #\hyperref[sailMIPSzbits]{bits}#(11)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCCall]{CCall}#(cs, cb, selector)) diff --git a/sail_latex_mips/fclCCallzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCCallzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..ed780f1f --- /dev/null +++ b/sail_latex_mips/fclCCallzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,27 @@ +/* Partial implementation of CCall with checks in hardware, but raising a trap to perform trusted stack manipulation */ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +if InBranchDelay then + #\hyperref[sailMIPSzSignalException]{SignalException}#(ResI); +let cs_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cs); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let cs_cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cs_val); +if not (cs_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) +else if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if not(cs_val.sealed) | #\hyperref[sailMIPSzhasReservedOType]{hasReservedOType}#(cs_val) then /* XXX Should latter be type violation? */ + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) +else if not(cb_val.sealed) | #\hyperref[sailMIPSzhasReservedOType]{hasReservedOType}#(cb_val) then /* XXX Should latter be type violation? */ + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if cs_val.otype != cb_val.otype then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TypeViolation, cs) +else if not (cs_val.permit_execute) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitExecuteViolation, cs) +else if cb_val.permit_execute then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitExecuteViolation, cb) +else if cs_cursor < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cs_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cs) +else if cs_cursor >= #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cs_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cs) +else + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_CallTrap, cs); diff --git a/sail_latex_mips/fclCCheckPermAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCCheckPermAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..f3e186eb --- /dev/null +++ b/sail_latex_mips/fclCCheckPermAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cs : CapRegEnc @ rt : IntRegEnc @ 0b01000 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCCheckPerm]{CCheckPerm}#(cs, rt)) diff --git a/sail_latex_mips/fclCCheckPermzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCCheckPermzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..72714586 --- /dev/null +++ b/sail_latex_mips/fclCCheckPermzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCCheckPerm]{CCheckPerm}#(cs, rt)) = "ccheckperm " ^ #\hyperref[sailMIPSzstrCRArgs]{strCRArgs}#(cs, rt) diff --git a/sail_latex_mips/fclCCheckPermzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCCheckPermzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..851c3f13 --- /dev/null +++ b/sail_latex_mips/fclCCheckPermzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01011 @ cs : CapRegEnc @ 0b00000 @ rt : IntRegEnc @ 0b000@ 0b000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCCheckPerm]{CCheckPerm}#(cs, rt)) diff --git a/sail_latex_mips/fclCCheckPermzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCCheckPermzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..564eda0a --- /dev/null +++ b/sail_latex_mips/fclCCheckPermzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cs_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cs); +let cs_perms : #\hyperref[sailMIPSzbits]{bits}#(64) = #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(#\hyperref[sailMIPSzgetCapPerms]{getCapPerms}#(cs_val)); +let rt_perms = #\hyperref[sailMIPSzrGPR]{rGPR}#(rt); +if not (cs_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) +else if (cs_perms & rt_perms) != rt_perms then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_UserDefViolation, cs) diff --git a/sail_latex_mips/fclCCheckTagzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCCheckTagzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..fa41e8dd --- /dev/null +++ b/sail_latex_mips/fclCCheckTagzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cs_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cs); +if not(cs_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs); diff --git a/sail_latex_mips/fclCCheckTypeAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCCheckTypeAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..d9837898 --- /dev/null +++ b/sail_latex_mips/fclCCheckTypeAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cs : CapRegEnc @ cb : CapRegEnc @ 0b01001 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCCheckType]{CCheckType}#(cs, cb)) diff --git a/sail_latex_mips/fclCCheckTypezassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCCheckTypezassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..35bbc2d6 --- /dev/null +++ b/sail_latex_mips/fclCCheckTypezassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCCheckType]{CCheckType}#(cs, cb)) = "cchecktype " ^ #\hyperref[sailMIPSzstrCCArgs]{strCCArgs}#(cs, cb) diff --git a/sail_latex_mips/fclCCheckTypezdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCCheckTypezdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..e79a662b --- /dev/null +++ b/sail_latex_mips/fclCCheckTypezdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01011 @ cs : CapRegEnc @ cb : CapRegEnc @ 0b00000 @ 0b000@ 0b001) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCCheckType]{CCheckType}#(cs, cb)) diff --git a/sail_latex_mips/fclCCheckTypezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCCheckTypezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..3898779e --- /dev/null +++ b/sail_latex_mips/fclCCheckTypezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,13 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cs_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cs); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +if not (cs_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) +else if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if not(cs_val.sealed) | #\hyperref[sailMIPSzhasReservedOType]{hasReservedOType}#(cs_val) then /* XXX should make latter a TypeViolation? */ + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) +else if not(cb_val.sealed) | #\hyperref[sailMIPSzhasReservedOType]{hasReservedOType}#(cb_val) then /* XXX should make latter a TypeViolation? */ + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if cs_val.otype != cb_val.otype then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TypeViolation, cs) diff --git a/sail_latex_mips/fclCClearTagAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCClearTagAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..63e5a8cb --- /dev/null +++ b/sail_latex_mips/fclCClearTagAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cb : CapRegEnc @ 0b01011 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCClearTag]{CClearTag}#(cd, cb)) diff --git a/sail_latex_mips/fclCClearTagscbzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCClearTagscbzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..9c02b704 --- /dev/null +++ b/sail_latex_mips/fclCClearTagscbzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cb : CapRegOrDDCEnc @ 0b11000 @ 0b11111 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCClearTags]{CClearTags}#(cb)) diff --git a/sail_latex_mips/fclCClearTagszassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCClearTagszassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..d25754f7 --- /dev/null +++ b/sail_latex_mips/fclCClearTagszassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCClearTags]{CClearTags}#(cb)) = "ccleartags " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(cb) diff --git a/sail_latex_mips/fclCClearTagszexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCClearTagszexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..2ee49d44 --- /dev/null +++ b/sail_latex_mips/fclCClearTagszexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,31 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not (cb_val.permit_store) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitStoreViolation, cb) +else +{ + let vAddr = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); + let vAddr64 = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val)); + if (vAddr + caps_per_cacheline * cap_size) > #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if vAddr < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if not(vAddr % (cap_size * caps_per_cacheline) == 0) then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdEL, vAddr64) + else + { + let pAddr = #\hyperref[sailMIPSzTLBTranslate]{TLBTranslate}#(vAddr64, StoreData); + foreach (i from 0 #\hyperref[sailMIPSzto]{to}# (caps_per_cacheline - 1)) + { + /* We could use write_tag_bool instead of reading data and writing it out again + but that would be incompatible with the way proofs are currently done. + There are concurrency implications to this method. */ + let (_, mem) = #\hyperref[sailMIPSzMEMrzytagged]{MEMr\_tagged}#(pAddr + i*cap_size, cap_size, false); + #\hyperref[sailMIPSzMEMwzytagged]{MEMw\_tagged}#(pAddr + i*cap_size, cap_size, false, mem); + } + } +} diff --git a/sail_latex_mips/fclCClearTagzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCClearTagzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..416a881f --- /dev/null +++ b/sail_latex_mips/fclCClearTagzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCClearTag]{CClearTag}#(cd, cb)) = "ccleartag " ^ #\hyperref[sailMIPSzstrCCArgs]{strCCArgs}#(cd, cb) diff --git a/sail_latex_mips/fclCClearTagzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCClearTagzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..a35e7df6 --- /dev/null +++ b/sail_latex_mips/fclCClearTagzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00100 @ cd : CapRegEnc @ cb : CapRegEnc @ 0b00000 @ 0b000@ 0b101) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCClearTag]{CClearTag}#(cd, cb)) diff --git a/sail_latex_mips/fclCClearTagzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCClearTagzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..4b950a45 --- /dev/null +++ b/sail_latex_mips/fclCClearTagzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +#\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, {cb_val with tag=false}); diff --git a/sail_latex_mips/fclCCopyTypezassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCCopyTypezassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..999f8ac9 --- /dev/null +++ b/sail_latex_mips/fclCCopyTypezassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCCopyType]{CCopyType}#(cd, cs, ct)) = "ccopytype " ^ #\hyperref[sailMIPSzstrCCCArgs]{strCCCArgs}#(cd, cs, ct) diff --git a/sail_latex_mips/fclCCopyTypezdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCCopyTypezdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..a5c8ee13 --- /dev/null +++ b/sail_latex_mips/fclCCopyTypezdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cb : CapRegEnc @ ct : CapRegEnc @ 0b011110) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCCopyType]{CCopyType}#(cd, cb, ct)) diff --git a/sail_latex_mips/fclCCopyTypezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCCopyTypezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..b79b5776 --- /dev/null +++ b/sail_latex_mips/fclCCopyTypezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,22 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let ct_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(ct); +let cb_base = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val); +let cb_top = #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val); +let ct_otype = #\hyperref[sailMIPSzunsigned]{unsigned}#(ct_val.otype); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not(ct_val.sealed) | #\hyperref[sailMIPSzhasReservedOType]{hasReservedOType}#(ct_val) then + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, {null_cap with address = #\hyperref[sailMIPSzsignzyextend]{sign\_extend}#(ct_val.otype)}) +else if ct_otype < cb_base then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) +else if ct_otype >= cb_top then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) +else +{ + let (success, cap) = #\hyperref[sailMIPSzsetCapOffset]{setCapOffset}#(cb_val, #\hyperref[sailMIPSztozybits]{to\_bits}#(64, ct_otype - cb_base)); + assert(success, "CopyType: offset is in bounds so should be representable"); + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, cap); +} diff --git a/sail_latex_mips/fclCFromPtrAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCFromPtrAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..2058b62a --- /dev/null +++ b/sail_latex_mips/fclCFromPtrAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cb : CapRegOrDDCEnc @ rs : IntRegEnc @ 0b010011) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCFromPtr]{CFromPtr}#(cd, cb, rs)) diff --git a/sail_latex_mips/fclCFromPtrzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCFromPtrzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..384717e6 --- /dev/null +++ b/sail_latex_mips/fclCFromPtrzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCFromPtr]{CFromPtr}#(cd, cb, rs)) = "cfromptr " ^ #\hyperref[sailMIPSzstrCCRArgs]{strCCRArgs}#(cd, cb, rs) diff --git a/sail_latex_mips/fclCFromPtrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCFromPtrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..dba62b6d --- /dev/null +++ b/sail_latex_mips/fclCFromPtrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00100 @ cd : CapRegEnc @ cb : CapRegEnc @ rt : IntRegEnc @ 0b000@ 0b111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCFromPtr]{CFromPtr}#(cd, cb, rt)) diff --git a/sail_latex_mips/fclCFromPtrzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCFromPtrzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..a8d0de25 --- /dev/null +++ b/sail_latex_mips/fclCFromPtrzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,17 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +let rt_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rt); +if rt_val == 0x0000000000000000 then + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, null_cap) +else if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else +{ + let (success, newCap) = #\hyperref[sailMIPSzsetCapOffset]{setCapOffset}#(cb_val, rt_val); + if success then + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) + else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, #\hyperref[sailMIPSzunrepCap]{unrepCap}#(newCap)) +} diff --git a/sail_latex_mips/fclCGetAddrzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetAddrzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..cb377a32 --- /dev/null +++ b/sail_latex_mips/fclCGetAddrzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetAddr]{CGetAddr}#(rd, cb)) = "cgetaddr " ^ #\hyperref[sailMIPSzstrRCArgs]{strRCArgs}#(rd, cb) diff --git a/sail_latex_mips/fclCGetAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..f1d2137e --- /dev/null +++ b/sail_latex_mips/fclCGetAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b01111 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetAddr]{CGetAddr}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetAddrzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetAddrzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..07308784 --- /dev/null +++ b/sail_latex_mips/fclCGetAddrzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let capVal = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = capVal.address; diff --git a/sail_latex_mips/fclCGetAndAddrzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetAndAddrzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..c2ea7f9e --- /dev/null +++ b/sail_latex_mips/fclCGetAndAddrzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetAndAddr]{CGetAndAddr}#(rd, cs, rs)) = "cgetandaddr " ^ #\hyperref[sailMIPSzstrRCRArgs]{strRCRArgs}#(rd, cs, rs) diff --git a/sail_latex_mips/fclCGetAndAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetAndAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..d37fbf86 --- /dev/null +++ b/sail_latex_mips/fclCGetAndAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cs : CapRegEnc @ rs : IntRegEnc @ 0b100011) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetAndAddr]{CGetAndAddr}#(rd, cs, rs)) diff --git a/sail_latex_mips/fclCGetAndAddrzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetAndAddrzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..4d4eb32e --- /dev/null +++ b/sail_latex_mips/fclCGetAndAddrzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let capVal = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let rs_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rs); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = capVal.address & rs_val; diff --git a/sail_latex_mips/fclCGetBaseAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetBaseAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..5cf6ad06 --- /dev/null +++ b/sail_latex_mips/fclCGetBaseAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00010 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetBase]{CGetBase}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetBasezassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetBasezassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..a5b322a2 --- /dev/null +++ b/sail_latex_mips/fclCGetBasezassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetBase]{CGetBase}#(rd, cb)) = "cgetbase " ^ #\hyperref[sailMIPSzstrRCArgs]{strRCArgs}#(rd, cb) diff --git a/sail_latex_mips/fclCGetBasezdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetBasezdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..ff1a6f4c --- /dev/null +++ b/sail_latex_mips/fclCGetBasezdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00000000 @ 0b010) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetBase]{CGetBase}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetBasezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetBasezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..82500bf9 --- /dev/null +++ b/sail_latex_mips/fclCGetBasezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let capVal = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(capVal)); diff --git a/sail_latex_mips/fclCGetCIDrdzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetCIDrdzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..66c3ccbe --- /dev/null +++ b/sail_latex_mips/fclCGetCIDrdzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ 0b00100 @ 0b11111 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetCID]{CGetCID}#(rd)) diff --git a/sail_latex_mips/fclCGetCIDzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetCIDzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..9e990aa8 --- /dev/null +++ b/sail_latex_mips/fclCGetCIDzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetCID]{CGetCID}#(rd)) = "cgetcid " ^ #\hyperref[sailMIPSzstrReg]{strReg}#(rd) diff --git a/sail_latex_mips/fclCGetCIDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetCIDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..b9352d40 --- /dev/null +++ b/sail_latex_mips/fclCGetCIDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = CID; diff --git a/sail_latex_mips/fclCGetCauserdAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetCauserdAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..2627eb39 --- /dev/null +++ b/sail_latex_mips/fclCGetCauserdAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ 0b00001 @ 0b11111 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetCause]{CGetCause}#(rd)) diff --git a/sail_latex_mips/fclCGetCauserdzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetCauserdzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..d125d617 --- /dev/null +++ b/sail_latex_mips/fclCGetCauserdzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ 0b00000 @ 0b00000000 @ 0b100) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetCause]{CGetCause}#(rd)) diff --git a/sail_latex_mips/fclCGetCausezassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetCausezassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..1d593871 --- /dev/null +++ b/sail_latex_mips/fclCGetCausezassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetCause]{CGetCause}#(rd)) = "cgetcause " ^ #\hyperref[sailMIPSzstrReg]{strReg}#(rd) diff --git a/sail_latex_mips/fclCGetCausezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetCausezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e9f2f5d6 --- /dev/null +++ b/sail_latex_mips/fclCGetCausezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,5 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +if not (#\hyperref[sailMIPSzpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}# ()) then + #\hyperref[sailMIPSzraisezyc2zyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_AccessSystemRegsViolation) +else + #\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(CapCause.#\hyperref[sailMIPSzbits]{bits}#()) diff --git a/sail_latex_mips/fclCGetFlagszassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetFlagszassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..d84a933c --- /dev/null +++ b/sail_latex_mips/fclCGetFlagszassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetFlags]{CGetFlags}#(rd, cb)) = "cgetflags " ^ #\hyperref[sailMIPSzstrRCArgs]{strRCArgs}#(rd, cb) diff --git a/sail_latex_mips/fclCGetFlagszdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetFlagszdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..8b05a263 --- /dev/null +++ b/sail_latex_mips/fclCGetFlagszdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b10010 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetFlags]{CGetFlags}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetFlagszexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetFlagszexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..fa883da9 --- /dev/null +++ b/sail_latex_mips/fclCGetFlagszexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let capVal = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(#\hyperref[sailMIPSzgetCapFlags]{getCapFlags}#(capVal)); diff --git a/sail_latex_mips/fclCGetLenAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetLenAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..f04ebbb0 --- /dev/null +++ b/sail_latex_mips/fclCGetLenAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00011 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetLen]{CGetLen}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetLenzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetLenzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..fbc94977 --- /dev/null +++ b/sail_latex_mips/fclCGetLenzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetLen]{CGetLen}#(rd, cb)) = "cgetlen " ^ #\hyperref[sailMIPSzstrRCArgs]{strRCArgs}#(rd, cb) diff --git a/sail_latex_mips/fclCGetLenzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetLenzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..42812d93 --- /dev/null +++ b/sail_latex_mips/fclCGetLenzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00000000 @ 0b011) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetLen]{CGetLen}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetLenzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetLenzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..fac42efa --- /dev/null +++ b/sail_latex_mips/fclCGetLenzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let capVal = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let len65 = #\hyperref[sailMIPSzgetCapLength]{getCapLength}#(capVal); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, if len65 > MAX_U64 then MAX_U64 else len65); diff --git a/sail_latex_mips/fclCGetOffsetAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetOffsetAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..b8789c58 --- /dev/null +++ b/sail_latex_mips/fclCGetOffsetAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00110 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetOffset]{CGetOffset}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetOffsetzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetOffsetzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..d450df20 --- /dev/null +++ b/sail_latex_mips/fclCGetOffsetzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetOffset]{CGetOffset}#(rd, cb)) = "cgetoffset " ^ #\hyperref[sailMIPSzstrRCArgs]{strRCArgs}#(rd, cb) diff --git a/sail_latex_mips/fclCGetOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..65b440dc --- /dev/null +++ b/sail_latex_mips/fclCGetOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01101 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00000000 @ 0b010) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetOffset]{CGetOffset}#(rd, cb)) /* NB encoding does not follow pattern */ diff --git a/sail_latex_mips/fclCGetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..c36c735b --- /dev/null +++ b/sail_latex_mips/fclCGetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let capVal = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzgetCapOffset]{getCapOffset}#(capVal)); diff --git a/sail_latex_mips/fclCGetPCCIncOffsetzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetPCCIncOffsetzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..51c1e75f --- /dev/null +++ b/sail_latex_mips/fclCGetPCCIncOffsetzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetPCCIncOffset]{CGetPCCIncOffset}#(cd, rs)) = "cgetpccincoffset " ^ #\hyperref[sailMIPSzstrCRArgs]{strCRArgs}#(cd, rs) diff --git a/sail_latex_mips/fclCGetPCCIncOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetPCCIncOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..b3e354f0 --- /dev/null +++ b/sail_latex_mips/fclCGetPCCIncOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ rs : IntRegEnc @ 0b10011 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetPCCIncOffset]{CGetPCCIncOffset}#(cd, rs)) diff --git a/sail_latex_mips/fclCGetPCCIncOffsetzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetPCCIncOffsetzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..f9d6213d --- /dev/null +++ b/sail_latex_mips/fclCGetPCCIncOffsetzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,7 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let rs_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rs); +let (success, newCap) = #\hyperref[sailMIPSzsetCapOffset]{setCapOffset}#(PCC, PC + rs_val); +if success then + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) +else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, #\hyperref[sailMIPSzunrepCap]{unrepCap}#(newCap)) diff --git a/sail_latex_mips/fclCGetPCCSetAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetPCCSetAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..0cbcd35f --- /dev/null +++ b/sail_latex_mips/fclCGetPCCSetAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ rs : IntRegEnc @ 0b10100 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetPCCSetAddr]{CGetPCCSetAddr}#(cd, rs)) diff --git a/sail_latex_mips/fclCGetPCCSetAddrzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetPCCSetAddrzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d6b33c7b --- /dev/null +++ b/sail_latex_mips/fclCGetPCCSetAddrzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,7 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let rs_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rs); +let (success, newCap) = #\hyperref[sailMIPSzsetCapAddr]{setCapAddr}#(PCC, rs_val); +if success then + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) +else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, #\hyperref[sailMIPSzunrepCap]{unrepCap}#(newCap)) diff --git a/sail_latex_mips/fclCGetPCCSetOffsetAzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetPCCSetOffsetAzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..54208438 --- /dev/null +++ b/sail_latex_mips/fclCGetPCCSetOffsetAzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetPCCSetOffset]{CGetPCCSetOffset}#(cd, rs)) = "cgetpccsetaddr " ^ #\hyperref[sailMIPSzstrCRArgs]{strCRArgs}#(cd, rs) diff --git a/sail_latex_mips/fclCGetPCCSetOffsetzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetPCCSetOffsetzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..b6f0e49e --- /dev/null +++ b/sail_latex_mips/fclCGetPCCSetOffsetzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetPCCSetOffset]{CGetPCCSetOffset}#(cd, rs)) = "cgetpccsetoffset " ^ #\hyperref[sailMIPSzstrCRArgs]{strCRArgs}#(cd, rs) diff --git a/sail_latex_mips/fclCGetPCCSetOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetPCCSetOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..a0f77d72 --- /dev/null +++ b/sail_latex_mips/fclCGetPCCSetOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ rs : IntRegEnc @ 0b00111 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetPCCSetOffset]{CGetPCCSetOffset}#(cd, rs)) diff --git a/sail_latex_mips/fclCGetPCCSetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetPCCSetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..ee47b590 --- /dev/null +++ b/sail_latex_mips/fclCGetPCCSetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,7 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let rs_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rs); +let (success, newPCC) = #\hyperref[sailMIPSzsetCapOffset]{setCapOffset}#(PCC, rs_val); +if (success) then + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newPCC) +else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, #\hyperref[sailMIPSzunrepCap]{unrepCap}#(newPCC)); diff --git a/sail_latex_mips/fclCGetPCCcdzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetPCCcdzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..68deb603 --- /dev/null +++ b/sail_latex_mips/fclCGetPCCcdzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ 0b00000 @ 0b11111 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetPCC]{CGetPCC}#(cd)) diff --git a/sail_latex_mips/fclCGetPCCzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetPCCzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..5aebb32e --- /dev/null +++ b/sail_latex_mips/fclCGetPCCzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetPCC]{CGetPCC}#(cd)) = "cgetpcc " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(cd) diff --git a/sail_latex_mips/fclCGetPCCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetPCCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d769f161 --- /dev/null +++ b/sail_latex_mips/fclCGetPCCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let (success, pcc) = #\hyperref[sailMIPSzsetCapOffset]{setCapOffset}#(PCC, PC); +assert (success, "PCC with offset PC should always be representable"); +#\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, pcc); diff --git a/sail_latex_mips/fclCGetPermAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetPermAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..0086495f --- /dev/null +++ b/sail_latex_mips/fclCGetPermAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00000 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetPerm]{CGetPerm}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetPermzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetPermzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..8e093b4f --- /dev/null +++ b/sail_latex_mips/fclCGetPermzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetPerm]{CGetPerm}#(rd, cb)) = "cgetperm " ^ #\hyperref[sailMIPSzstrRCArgs]{strRCArgs}#(rd, cb) diff --git a/sail_latex_mips/fclCGetPermzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetPermzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..aa6ee2c5 --- /dev/null +++ b/sail_latex_mips/fclCGetPermzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00000000 @ 0b000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetPerm]{CGetPerm}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetPermzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetPermzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..a88c8df5 --- /dev/null +++ b/sail_latex_mips/fclCGetPermzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let capVal = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(#\hyperref[sailMIPSzgetCapPerms]{getCapPerms}#(capVal)); diff --git a/sail_latex_mips/fclCGetSealedAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetSealedAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..7cce5930 --- /dev/null +++ b/sail_latex_mips/fclCGetSealedAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00101 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetSealed]{CGetSealed}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetSealedzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetSealedzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..fc4c7106 --- /dev/null +++ b/sail_latex_mips/fclCGetSealedzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetSealed]{CGetSealed}#(rd, cb)) = "cgetsealed " ^ #\hyperref[sailMIPSzstrRCArgs]{strRCArgs}#(rd, cb) diff --git a/sail_latex_mips/fclCGetSealedzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetSealedzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..ee13b342 --- /dev/null +++ b/sail_latex_mips/fclCGetSealedzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00000000 @ 0b110) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetSealed]{CGetSealed}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetSealedzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetSealedzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..1d4cc8e6 --- /dev/null +++ b/sail_latex_mips/fclCGetSealedzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let capVal = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(capVal.sealed); diff --git a/sail_latex_mips/fclCGetTagAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetTagAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..bb0164c7 --- /dev/null +++ b/sail_latex_mips/fclCGetTagAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00100 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetTag]{CGetTag}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetTagzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetTagzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..9df44a24 --- /dev/null +++ b/sail_latex_mips/fclCGetTagzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetTag]{CGetTag}#(rd, cb)) = "cgettag " ^ #\hyperref[sailMIPSzstrRCArgs]{strRCArgs}#(rd, cb) diff --git a/sail_latex_mips/fclCGetTagzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetTagzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..cc527962 --- /dev/null +++ b/sail_latex_mips/fclCGetTagzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00000000 @ 0b101) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetTag]{CGetTag}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetTagzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetTagzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e52a9dba --- /dev/null +++ b/sail_latex_mips/fclCGetTagzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let capVal = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(capVal.tag); diff --git a/sail_latex_mips/fclCGetTypeAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetTypeAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..d2407de2 --- /dev/null +++ b/sail_latex_mips/fclCGetTypeAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00001 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetType]{CGetType}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetTypezassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCGetTypezassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..e4d335e7 --- /dev/null +++ b/sail_latex_mips/fclCGetTypezassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCGetType]{CGetType}#(rd, cb)) = "cgettype " ^ #\hyperref[sailMIPSzstrRCArgs]{strRCArgs}#(rd, cb) diff --git a/sail_latex_mips/fclCGetTypezdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCGetTypezdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..6c802b86 --- /dev/null +++ b/sail_latex_mips/fclCGetTypezdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ 0b00000000 @ 0b001) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCGetType]{CGetType}#(rd, cb)) diff --git a/sail_latex_mips/fclCGetTypezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCGetTypezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..4668ee93 --- /dev/null +++ b/sail_latex_mips/fclCGetTypezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,5 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let capVal = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = if #\hyperref[sailMIPSzhasReservedOType]{hasReservedOType}#(capVal) + then #\hyperref[sailMIPSzsignzyextend]{sign\_extend}#(capVal.otype) /* return negative for reserved otypes */ + else #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(capVal.otype) diff --git a/sail_latex_mips/fclCIncOffsetAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCIncOffsetAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..569f2a45 --- /dev/null +++ b/sail_latex_mips/fclCIncOffsetAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cb : CapRegEnc @ rt : IntRegEnc @ 0b010001) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCIncOffset]{CIncOffset}#(cd, cb, rt)) diff --git a/sail_latex_mips/fclCIncOffsetImmediatezassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCIncOffsetImmediatezassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..adc47da4 --- /dev/null +++ b/sail_latex_mips/fclCIncOffsetImmediatezassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCIncOffsetImmediate]{CIncOffsetImmediate}#(cd, cb, imm)) = "cincoffsetimm " ^ #\hyperref[sailMIPSzstrCCIArgs]{strCCIArgs}#(cd, cb, imm) diff --git a/sail_latex_mips/fclCIncOffsetImmediatezdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCIncOffsetImmediatezdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..b381970e --- /dev/null +++ b/sail_latex_mips/fclCIncOffsetImmediatezdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10011 @ cd : CapRegEnc @ cb : CapRegEnc @ imm : #\hyperref[sailMIPSzbits]{bits}#(11)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCIncOffsetImmediate]{CIncOffsetImmediate}#(cd, cb, imm)) diff --git a/sail_latex_mips/fclCIncOffsetImmediatezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCIncOffsetImmediatezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e5a655bb --- /dev/null +++ b/sail_latex_mips/fclCIncOffsetImmediatezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,13 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let imm64 : #\hyperref[sailMIPSzbits]{bits}#(64) = #\hyperref[sailMIPSzsignzyextend]{sign\_extend}#(imm); +if cb_val.tag & cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else +{ + let (success, newCap) = #\hyperref[sailMIPSzincCapOffset]{incCapOffset}#(cb_val, imm64); + if success then + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) + else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, #\hyperref[sailMIPSzunrepCap]{unrepCap}#(newCap)) +} diff --git a/sail_latex_mips/fclCIncOffsetzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCIncOffsetzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..4a18ecae --- /dev/null +++ b/sail_latex_mips/fclCIncOffsetzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCIncOffset]{CIncOffset}#(cd, cs, rt)) = "cincoffset " ^ #\hyperref[sailMIPSzstrCCRArgs]{strCCRArgs}#(cd, cs, rt) diff --git a/sail_latex_mips/fclCIncOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCIncOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..5cc98099 --- /dev/null +++ b/sail_latex_mips/fclCIncOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01101 @ cd : CapRegEnc @ cb : CapRegEnc @ rt : IntRegEnc @ 0b000 @ 0b000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCIncOffset]{CIncOffset}#(cd, cb, rt)) diff --git a/sail_latex_mips/fclCIncOffsetzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCIncOffsetzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..89bf2e45 --- /dev/null +++ b/sail_latex_mips/fclCIncOffsetzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,13 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let rt_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rt); +if cb_val.tag & cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else +{ + let (success, newCap) = #\hyperref[sailMIPSzincCapOffset]{incCapOffset}#(cb_val, rt_val); + if success then + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) + else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, #\hyperref[sailMIPSzunrepCap]{unrepCap}#(newCap)) +} diff --git a/sail_latex_mips/fclCJALRAzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCJALRAzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..4f714d26 --- /dev/null +++ b/sail_latex_mips/fclCJALRAzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCJALR]{CJALR}#(cd, cb, true)) = "cjalr " ^ #\hyperref[sailMIPSzstrCCArgs]{strCCArgs}#(cd, cb) diff --git a/sail_latex_mips/fclCJALRAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCJALRAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..6ca8de69 --- /dev/null +++ b/sail_latex_mips/fclCJALRAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01000 @ 0b00000 @ cb : CapRegEnc @ 0b00000 @ 0b000000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCJALR]{CJALR}#(0b00000, cb, false)) /* CJR */ diff --git a/sail_latex_mips/fclCJALRBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCJALRBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..98c8bd05 --- /dev/null +++ b/sail_latex_mips/fclCJALRBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cb : CapRegEnc @ 0b00011 @ 0b11111 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCJALR]{CJALR}#(0b00000, cb, false)) /* CJR */ diff --git a/sail_latex_mips/fclCJALRCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCJALRCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..f8820ddb --- /dev/null +++ b/sail_latex_mips/fclCJALRCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cb : CapRegEnc @ 0b01100 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCJALR]{CJALR}#(cd, cb, true)) /* CJALR */ diff --git a/sail_latex_mips/fclCJALRzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCJALRzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..178c89c3 --- /dev/null +++ b/sail_latex_mips/fclCJALRzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCJALR]{CJALR}#(0b00000, cb, false)) = "cjr " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(cb) diff --git a/sail_latex_mips/fclCJALRzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCJALRzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..afb60623 --- /dev/null +++ b/sail_latex_mips/fclCJALRzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00111 @ cd : CapRegEnc @ cb : CapRegEnc @ 0b00000 @ 0b000000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCJALR]{CJALR}#(cd, cb, true)) /* CJALR */ diff --git a/sail_latex_mips/fclCJALRzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCJALRzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..28796c9b --- /dev/null +++ b/sail_latex_mips/fclCJALRzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,35 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +if InBranchDelay then + #\hyperref[sailMIPSzSignalException]{SignalException}#(ResI); +cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let cb_ptr = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); +let cb_top = #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val); +let cb_base= #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val); +let sentry = #\hyperref[sailMIPSzisSentryCap]{isSentryCap}#(cb_val); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if (cb_val.sealed & not(sentry)) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not (cb_val.permit_execute) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitExecuteViolation, cb) +else if cb_ptr < cb_base then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) +else if (cb_ptr + 4) > cb_top then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) +else if (cb_ptr % 4) != 0 then + #\hyperref[sailMIPSzSignalException]{SignalException}#(AdEL) +else +{ + if sentry then + cb_val = #\hyperref[sailMIPSzunsealCap]{unsealCap}#(cb_val); + if link then + { + let (success, linkCap) = #\hyperref[sailMIPSzsetCapOffset]{setCapOffset}#(PCC, PC+8); + assert(success, "Link cap should always be representable."); + let (success2, sealedLink) = #\hyperref[sailMIPSzsealCap]{sealCap}#(linkCap, #\hyperref[sailMIPSztozybits]{to\_bits}#(24, otype_sentry)); + assert(success2, "Sealing should always be possible with current format."); + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, sealedLink); + }; + #\hyperref[sailMIPSzexecutezybranchzypcc]{execute\_branch\_pcc}#(cb_val); +}; +NextInBranchDelay = 0b1; diff --git a/sail_latex_mips/fclCLCBIzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLCBIzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..a719cc2b --- /dev/null +++ b/sail_latex_mips/fclCLCBIzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b011101 @ cd : CapRegEnc @ cb : CapRegOrDDCEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(16)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLCBI]{CLCBI}#(cd, cb, offset)) diff --git a/sail_latex_mips/fclCLCBIzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCLCBIzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..5f6b5008 --- /dev/null +++ b/sail_latex_mips/fclCLCBIzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,31 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not (cb_val.permit_load) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitLoadViolation, cb) +else +{ + let cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); + let vAddr = (cursor + 16 * #\hyperref[sailMIPSzsigned]{signed}#(offset)) % #\hyperref[sailMIPSzpow2]{pow2}#(64); + let vAddr64 = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, vAddr); + if (vAddr + cap_size) > #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if vAddr < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if (vAddr % cap_size) != 0 then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdEL, vAddr64) + else + { + let (pAddr, macr) = #\hyperref[sailMIPSzTLBTranslateC]{TLBTranslateC}#(vAddr64, LoadData); + let (tag, mem) = + #\hyperref[sailMIPSzMEMrzytagged]{MEMr\_tagged}#(pAddr, cap_size, cb_val.permit_load_cap & not (macr == Clear)) + in + if tag & macr == Trap then + #\hyperref[sailMIPSzraisezyc2zyexceptionzybadaddr]{raise\_c2\_exception\_badaddr}#(CapEx_TLBLoadCap, cb, vAddr64) + else let cap = #\hyperref[sailMIPSzmemBitsToCapability]{memBitsToCapability}#(tag, mem) in + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, cap); + } +} diff --git a/sail_latex_mips/fclCLCNTzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLCNTzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..1879c5e0 --- /dev/null +++ b/sail_latex_mips/fclCLCNTzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegOrDDCEnc @ rs : IntRegEnc @ 0b111000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLCNT]{CLCNT}#(cd, cs, rs)) diff --git a/sail_latex_mips/fclCLCNTzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCLCNTzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d58f25da --- /dev/null +++ b/sail_latex_mips/fclCLCNTzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1 @@ +#\hyperref[sailMIPSzexecute]{execute}# (#\hyperref[sailMIPSzCLC]{CLC}#(cd, cb, rt, #\hyperref[sailMIPSztozybits]{to\_bits}#(11, 0))) diff --git a/sail_latex_mips/fclCLCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..aba9cb76 --- /dev/null +++ b/sail_latex_mips/fclCLCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b110110 @ cd : CapRegEnc @ cb : CapRegOrDDCEnc @ rt : IntRegEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(11)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLC]{CLC}#(cd, cb, rt, offset)) diff --git a/sail_latex_mips/fclCLCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCLCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..5a9df790 --- /dev/null +++ b/sail_latex_mips/fclCLCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,31 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not (cb_val.permit_load) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitLoadViolation, cb) +else +{ + let cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); + let vAddr = (cursor + #\hyperref[sailMIPSzunsigned]{unsigned}#(#\hyperref[sailMIPSzrGPR]{rGPR}#(rt)) + 16 * #\hyperref[sailMIPSzsigned]{signed}#(offset)) % #\hyperref[sailMIPSzpow2]{pow2}#(64); + let vAddr64 = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, vAddr); + if (vAddr + cap_size) > #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if vAddr < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if (vAddr % cap_size) != 0 then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdEL, vAddr64) + else + { + let (pAddr, macr) = #\hyperref[sailMIPSzTLBTranslateC]{TLBTranslateC}#(vAddr64, LoadData); + let (tag, mem) = + #\hyperref[sailMIPSzMEMrzytagged]{MEMr\_tagged}#(pAddr, cap_size, cb_val.permit_load_cap & not (macr == Clear)) + in + if tag & macr == Trap then + #\hyperref[sailMIPSzraisezyc2zyexceptionzybadaddr]{raise\_c2\_exception\_badaddr}#(CapEx_TLBLoadCap, cb, vAddr64) + else let cap = #\hyperref[sailMIPSzmemBitsToCapability]{memBitsToCapability}#(tag, mem) in + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, cap); + } +} diff --git a/sail_latex_mips/fclCLLCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLLCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..faef169a --- /dev/null +++ b/sail_latex_mips/fclCLLCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10000 @ cd : CapRegEnc @ cb : CapRegOrDDCEnc @ 0b0000000 @ 0b1111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLLC]{CLLC}#(cd, cb)) diff --git a/sail_latex_mips/fclCLLCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCLLCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..c6b274ac --- /dev/null +++ b/sail_latex_mips/fclCLLCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,34 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not (cb_val.permit_load) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitLoadViolation, cb) +else +{ + let vAddr = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); + let vAddr64 = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, vAddr); + if (vAddr + cap_size) > #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if vAddr < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if (vAddr % cap_size) != 0 then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdEL, vAddr64) + else + { + let (pAddr, macr) = #\hyperref[sailMIPSzTLBTranslateC]{TLBTranslateC}#(vAddr64, LoadData); + let (tag, mem) = + #\hyperref[sailMIPSzMEMrzytaggedzyreserve]{MEMr\_tagged\_reserve}#(pAddr, cap_size, cb_val.permit_load_cap & not (macr == Clear)) + in + if tag & macr == Trap then + #\hyperref[sailMIPSzraisezyc2zyexceptionzybadaddr]{raise\_c2\_exception\_badaddr}#(CapEx_TLBLoadCap, cb, vAddr64) + else { + let cap = #\hyperref[sailMIPSzmemBitsToCapability]{memBitsToCapability}#(tag, mem) in + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, cap); + CP0LLBit = 0b1; + CP0LLAddr = pAddr; + } + } +} diff --git a/sail_latex_mips/fclCLoadAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..e55c88ea --- /dev/null +++ b/sail_latex_mips/fclCLoadAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b110010 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ rt : IntRegEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(8) @ 0b1 @ 0b00) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoad]{CLoad}#(rd, cb, rt, offset, true, B)) /* CLB */ diff --git a/sail_latex_mips/fclCLoadBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..cf726d91 --- /dev/null +++ b/sail_latex_mips/fclCLoadBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b110010 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ rt : IntRegEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(8) @ 0b0 @ 0b01) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoad]{CLoad}#(rd, cb, rt, offset, false, H)) /* CLHU */ diff --git a/sail_latex_mips/fclCLoadCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..a1d426ec --- /dev/null +++ b/sail_latex_mips/fclCLoadCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b110010 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ rt : IntRegEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(8) @ 0b1 @ 0b01) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoad]{CLoad}#(rd, cb, rt, offset, true, H)) /* CLH */ diff --git a/sail_latex_mips/fclCLoadDzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadDzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..39b27ea7 --- /dev/null +++ b/sail_latex_mips/fclCLoadDzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b110010 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ rt : IntRegEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(8) @ 0b0 @ 0b10) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoad]{CLoad}#(rd, cb, rt, offset, false, W)) /* CLWU */ diff --git a/sail_latex_mips/fclCLoadEzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadEzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..e15a314b --- /dev/null +++ b/sail_latex_mips/fclCLoadEzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b110010 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ rt : IntRegEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(8) @ 0b1 @ 0b10) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoad]{CLoad}#(rd, cb, rt, offset, true, W)) /* CLW */ diff --git a/sail_latex_mips/fclCLoadFzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadFzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..1605b94e --- /dev/null +++ b/sail_latex_mips/fclCLoadFzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b110010 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ rt : IntRegEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(8) @ 0b0 @ 0b11) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoad]{CLoad}#(rd, cb, rt, offset, false, D)) /* CLD */ diff --git a/sail_latex_mips/fclCLoadLinkedAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadLinkedAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..092bb2d4 --- /dev/null +++ b/sail_latex_mips/fclCLoadLinkedAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10000 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ 0b00000001 @ 0b1 @ 0b00) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoadLinked]{CLoadLinked}#(rd, cb, true, B)) /* CLLB */ diff --git a/sail_latex_mips/fclCLoadLinkedBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadLinkedBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..50d4b0e4 --- /dev/null +++ b/sail_latex_mips/fclCLoadLinkedBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10000 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ 0b00000001 @ 0b0 @ 0b01) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoadLinked]{CLoadLinked}#(rd, cb, false, H)) /* CLLHU */ diff --git a/sail_latex_mips/fclCLoadLinkedCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadLinkedCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..01274eb3 --- /dev/null +++ b/sail_latex_mips/fclCLoadLinkedCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10000 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ 0b00000001 @ 0b1 @ 0b01) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoadLinked]{CLoadLinked}#(rd, cb, true, H)) /* CLLH */ diff --git a/sail_latex_mips/fclCLoadLinkedDzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadLinkedDzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..0989a15b --- /dev/null +++ b/sail_latex_mips/fclCLoadLinkedDzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10000 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ 0b00000001 @ 0b0 @ 0b10) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoadLinked]{CLoadLinked}#(rd, cb, false, W)) /* CLLWU */ diff --git a/sail_latex_mips/fclCLoadLinkedEzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadLinkedEzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..80a9cf6c --- /dev/null +++ b/sail_latex_mips/fclCLoadLinkedEzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10000 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ 0b00000001 @ 0b1 @ 0b10) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoadLinked]{CLoadLinked}#(rd, cb, true, W)) /* CLLW */ diff --git a/sail_latex_mips/fclCLoadLinkedFzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadLinkedFzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..1c6a190f --- /dev/null +++ b/sail_latex_mips/fclCLoadLinkedFzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10000 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ 0b00000001 @ 0b0 @ 0b11) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoadLinked]{CLoadLinked}#(rd, cb, false, D)) /* CLLD */ diff --git a/sail_latex_mips/fclCLoadLinkedzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadLinkedzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..6c9f8513 --- /dev/null +++ b/sail_latex_mips/fclCLoadLinkedzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10000 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ 0b00000001 @ 0b0 @ 0b00) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoadLinked]{CLoadLinked}#(rd, cb, false, B)) /* CLLBU */ diff --git a/sail_latex_mips/fclCLoadLinkedzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCLoadLinkedzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..b8052dc4 --- /dev/null +++ b/sail_latex_mips/fclCLoadLinkedzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,28 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not (cb_val.permit_load) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitLoadViolation, cb) +else +{ + let 'size = #\hyperref[sailMIPSzwordWidthBytes]{wordWidthBytes}#(width); + let vAddr = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); + let vAddr64 = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, vAddr); + if (vAddr + size) > #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if vAddr < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if not (#\hyperref[sailMIPSzisAddressAligned]{isAddressAligned}#(vAddr64, width)) then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdEL, vAddr64) + else + { + let pAddr = #\hyperref[sailMIPSzTLBTranslate]{TLBTranslate}#(vAddr64, LoadData); + let memResult : #\hyperref[sailMIPSzbits]{bits}#(64) = #\hyperref[sailMIPSzextendLoad]{extendLoad}#(#\hyperref[sailMIPSzMEMrzyreservezywrapper]{MEMr\_reserve\_wrapper}#(pAddr, size), signext); + CP0LLBit = 0b1; + CP0LLAddr = pAddr; + #\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = memResult; + } +} diff --git a/sail_latex_mips/fclCLoadTagszassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCLoadTagszassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..d6e74aed --- /dev/null +++ b/sail_latex_mips/fclCLoadTagszassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCLoadTags]{CLoadTags}#(rd, cb)) = "cloadtags " ^ #\hyperref[sailMIPSzstrRCArgs]{strRCArgs}#(rd, cb) diff --git a/sail_latex_mips/fclCLoadTagszdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadTagszdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..768f8822 --- /dev/null +++ b/sail_latex_mips/fclCLoadTagszdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ 0b11110 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoadTags]{CLoadTags}#(rd, cb)) diff --git a/sail_latex_mips/fclCLoadTagszexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCLoadTagszexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..a2802927 --- /dev/null +++ b/sail_latex_mips/fclCLoadTagszexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,39 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not (cb_val.permit_load) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitLoadViolation, cb) +else if not (cb_val.permit_load_cap) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitLoadCapViolation, cb) +else +{ + let vAddr = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); + let vAddr64 = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val)); + if (vAddr + caps_per_cacheline * cap_size) > #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if vAddr < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if not(vAddr % (cap_size * caps_per_cacheline) == 0) then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdEL, vAddr64) + else + { + let (pAddr, macr) = #\hyperref[sailMIPSzTLBTranslateC]{TLBTranslateC}#(vAddr64, LoadData); + + match macr { + Clear => #\hyperref[sailMIPSzraisezyc2zyexceptionzybadaddr]{raise\_c2\_exception\_badaddr}#(CapEx_TLBLoadCap, cb, vAddr64), + Trap => #\hyperref[sailMIPSzraisezyc2zyexceptionzybadaddr]{raise\_c2\_exception\_badaddr}#(CapEx_TLBLoadCap, cb, vAddr64), + + Unrestricted => { + x : #\hyperref[sailMIPSzbits]{bits}#(64) = #\hyperref[sailMIPSzzzeros]{zeros}#(); + foreach (i from 0 #\hyperref[sailMIPSzto]{to}# (caps_per_cacheline - 1)) { + let (tag, _) = #\hyperref[sailMIPSzMEMrzytagged]{MEMr\_tagged}#(pAddr + i*cap_size, cap_size, true); + x[i] = tag; + }; + #\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = x; + } + } + } +} diff --git a/sail_latex_mips/fclCLoadzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCLoadzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..d9541cb2 --- /dev/null +++ b/sail_latex_mips/fclCLoadzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b110010 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ rt : IntRegEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(8) @ 0b0 @ 0b00) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCLoad]{CLoad}#(rd, cb, rt, offset, false, B)) /* CLBU */ diff --git a/sail_latex_mips/fclCLoadzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCLoadzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..a4f396b5 --- /dev/null +++ b/sail_latex_mips/fclCLoadzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,27 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not (cb_val.permit_load) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitLoadViolation, cb) +else +{ + let 'size = #\hyperref[sailMIPSzwordWidthBytes]{wordWidthBytes}#(width); + let cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); + let vAddr = (cursor + #\hyperref[sailMIPSzunsigned]{unsigned}#(#\hyperref[sailMIPSzrGPR]{rGPR}#(rt)) + size*#\hyperref[sailMIPSzsigned]{signed}#(offset)) % #\hyperref[sailMIPSzpow2]{pow2}#(64); + let vAddr64 = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, vAddr); + if (vAddr + size) > #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if vAddr < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if not (#\hyperref[sailMIPSzisAddressAligned]{isAddressAligned}#(vAddr64, width)) then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdEL, vAddr64) + else + { + let pAddr = #\hyperref[sailMIPSzTLBTranslate]{TLBTranslate}#(vAddr64, LoadData); + memResult : #\hyperref[sailMIPSzbits]{bits}#(64) = #\hyperref[sailMIPSzextendLoad]{extendLoad}#(#\hyperref[sailMIPSzMEMrzywrapper]{MEMr\_wrapper}#(pAddr, size), signext); + #\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = memResult; + } +} diff --git a/sail_latex_mips/fclCMOVXAzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCMOVXAzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..74f81b39 --- /dev/null +++ b/sail_latex_mips/fclCMOVXAzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCMOVX]{CMOVX}#(cd, cs, rs, true)) = "cmovn " ^ #\hyperref[sailMIPSzstrCCRArgs]{strCCRArgs}#(cd, cs, rs) diff --git a/sail_latex_mips/fclCMOVXAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCMOVXAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..ca392aef --- /dev/null +++ b/sail_latex_mips/fclCMOVXAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegEnc @ rs : IntRegEnc @ 0b011100) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCMOVX]{CMOVX}#(cd, cs, rs, true)) /* CMOVN */ diff --git a/sail_latex_mips/fclCMOVXzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCMOVXzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..bfc37e91 --- /dev/null +++ b/sail_latex_mips/fclCMOVXzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCMOVX]{CMOVX}#(cd, cs, rs, false)) = "cmovz " ^ #\hyperref[sailMIPSzstrCCRArgs]{strCCRArgs}#(cd, cs, rs) diff --git a/sail_latex_mips/fclCMOVXzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCMOVXzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..857291df --- /dev/null +++ b/sail_latex_mips/fclCMOVXzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegEnc @ rs : IntRegEnc @ 0b011011) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCMOVX]{CMOVX}#(cd, cs, rs, false)) /* CMOVZ */ diff --git a/sail_latex_mips/fclCMOVXzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCMOVXzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..1932c303 --- /dev/null +++ b/sail_latex_mips/fclCMOVXzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +if (#\hyperref[sailMIPSzrGPR]{rGPR}#(rt) == #\hyperref[sailMIPSzzzeros]{zeros}#()) ^ ismovn then + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd) = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); diff --git a/sail_latex_mips/fclCMovezassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCMovezassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..54b69046 --- /dev/null +++ b/sail_latex_mips/fclCMovezassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCMove]{CMove}#(cd, cs)) = "cmove " ^ #\hyperref[sailMIPSzstrCCArgs]{strCCArgs}#(cd, cs) diff --git a/sail_latex_mips/fclCMovezdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCMovezdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..60ce3adb --- /dev/null +++ b/sail_latex_mips/fclCMovezdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegEnc @ 0b01010 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCMove]{CMove}#(cd, cs)) /* CMOVE */ diff --git a/sail_latex_mips/fclCMovezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCMovezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..3ffa4960 --- /dev/null +++ b/sail_latex_mips/fclCMovezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +#\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd) = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); diff --git a/sail_latex_mips/fclCPtrCmpAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..68dd62e2 --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01110 @ rd : IntRegEnc @ cb : CapRegEnc @ ct : CapRegEnc @ 0b000 @ 0b001) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, ct, CNE)) diff --git a/sail_latex_mips/fclCPtrCmpBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..1bcf081f --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01110 @ rd : IntRegEnc @ cb : CapRegEnc @ ct : CapRegEnc @ 0b000 @ 0b010) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, ct, CLT)) diff --git a/sail_latex_mips/fclCPtrCmpCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..adcb9422 --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01110 @ rd : IntRegEnc @ cb : CapRegEnc @ ct : CapRegEnc @ 0b000 @ 0b011) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, ct, CLE)) diff --git a/sail_latex_mips/fclCPtrCmpDzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpDzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..c9b02c87 --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpDzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01110 @ rd : IntRegEnc @ cb : CapRegEnc @ ct : CapRegEnc @ 0b000 @ 0b100) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, ct, CLTU)) diff --git a/sail_latex_mips/fclCPtrCmpEzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpEzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..6e9e11fb --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpEzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01110 @ rd : IntRegEnc @ cb : CapRegEnc @ ct : CapRegEnc @ 0b000 @ 0b101) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, ct, CLEU)) diff --git a/sail_latex_mips/fclCPtrCmpFzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpFzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..4520541b --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpFzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01110 @ rd : IntRegEnc @ cb : CapRegEnc @ ct : CapRegEnc @ 0b000 @ 0b110) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, ct, CEXEQ)) diff --git a/sail_latex_mips/fclCPtrCmpGzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpGzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..1e2dbcad --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpGzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01110 @ rd : IntRegEnc @ cb : CapRegEnc @ ct : CapRegEnc @ 0b000 @ 0b111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, ct, CNEXEQ)) diff --git a/sail_latex_mips/fclCPtrCmpHzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpHzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..6f921b3a --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpHzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ cs : CapRegEnc @ 0b010100) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, cs, CEQ)) diff --git a/sail_latex_mips/fclCPtrCmpIzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpIzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..f44d00ce --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpIzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ cs : CapRegEnc @ 0b010101) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, cs, CNE)) diff --git a/sail_latex_mips/fclCPtrCmpJzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpJzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..c489b233 --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpJzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ cs : CapRegEnc @ 0b010110) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, cs, CLT)) diff --git a/sail_latex_mips/fclCPtrCmpKzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpKzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..7d172937 --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpKzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ cs : CapRegEnc @ 0b010111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, cs, CLE)) diff --git a/sail_latex_mips/fclCPtrCmpLzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpLzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..ad481981 --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpLzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ cs : CapRegEnc @ 0b011000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, cs, CLTU)) diff --git a/sail_latex_mips/fclCPtrCmpMzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpMzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..ca1136ff --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpMzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ cs : CapRegEnc @ 0b011001) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, cs, CLEU)) diff --git a/sail_latex_mips/fclCPtrCmpNzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpNzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..2ca77259 --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpNzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ cs : CapRegEnc @ 0b011010) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, cs, CEXEQ)) diff --git a/sail_latex_mips/fclCPtrCmpOzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpOzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..b13a043f --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpOzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ cs : CapRegEnc @ 0b100001) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, cs, CNEXEQ)) diff --git a/sail_latex_mips/fclCPtrCmpzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCPtrCmpzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..0cdc6bd4 --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01110 @ rd : IntRegEnc @ cb : CapRegEnc @ ct : CapRegEnc @ 0b000 @ 0b000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCPtrCmp]{CPtrCmp}#(rd, cb, ct, CEQ)) diff --git a/sail_latex_mips/fclCPtrCmpzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCPtrCmpzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..a4589b0d --- /dev/null +++ b/sail_latex_mips/fclCPtrCmpzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,17 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let ct_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(ct); +let equal : bool = cb_val.address == ct_val.address; +let ltu : bool = cb_val.address <_u ct_val.address; +let lts : bool = cb_val.address <_s ct_val.address; +let cmp : bool = match op { + CEQ => equal, + CNE => not (equal), + CLT => lts, + CLE => lts | equal, + CLTU => ltu, + CLEU => ltu | equal, + CEXEQ => cb_val == ct_val, + CNEXEQ => cb_val != ct_val +}; +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}# (cmp) diff --git a/sail_latex_mips/fclCRAMzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCRAMzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..c11973c5 --- /dev/null +++ b/sail_latex_mips/fclCRAMzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCRAM]{CRAM}#(rt, rs)) = "cram " ^ #\hyperref[sailMIPSzstrRRArgs]{strRRArgs}#(rt, rs) diff --git a/sail_latex_mips/fclCRAMzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCRAMzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..d20f34cd --- /dev/null +++ b/sail_latex_mips/fclCRAMzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rt : IntRegEnc @ rs : IntRegEnc @ 0b10001 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCRAM]{CRAM}#(rt, rs)) diff --git a/sail_latex_mips/fclCRAMzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCRAMzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..bbe0cdac --- /dev/null +++ b/sail_latex_mips/fclCRAMzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let len = #\hyperref[sailMIPSzrGPR]{rGPR}#(rs); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rt) = #\hyperref[sailMIPSzgetRepresentableAlignmentMask]{getRepresentableAlignmentMask}#(len); diff --git a/sail_latex_mips/fclCRAPzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCRAPzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..5510b1d1 --- /dev/null +++ b/sail_latex_mips/fclCRAPzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCRAP]{CRAP}#(rt, rs)) = "crrl " ^ #\hyperref[sailMIPSzstrRRArgs]{strRRArgs}#(rt, rs) diff --git a/sail_latex_mips/fclCRAPzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCRAPzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..2ac91d01 --- /dev/null +++ b/sail_latex_mips/fclCRAPzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rt : IntRegEnc @ rs : IntRegEnc @ 0b10000 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCRAP]{CRAP}#(rt, rs)) diff --git a/sail_latex_mips/fclCRAPzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCRAPzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..aa85620b --- /dev/null +++ b/sail_latex_mips/fclCRAPzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let len = #\hyperref[sailMIPSzrGPR]{rGPR}#(rs); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rt) = #\hyperref[sailMIPSzgetRepresentableLength]{getRepresentableLength}#(len); diff --git a/sail_latex_mips/fclCReadHwrzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCReadHwrzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..f7c4b6c0 --- /dev/null +++ b/sail_latex_mips/fclCReadHwrzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCReadHwr]{CReadHwr}#(cd, sel)) = "creadhwr " ^ #\hyperref[sailMIPSzstrCRArgs]{strCRArgs}#(cd, sel) diff --git a/sail_latex_mips/fclCReadHwrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCReadHwrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..ff0bf883 --- /dev/null +++ b/sail_latex_mips/fclCReadHwrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ sel : CapHwrEnc @ 0b01101 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCReadHwr]{CReadHwr}#(cd, sel)) diff --git a/sail_latex_mips/fclCReadHwrzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCReadHwrzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..9161e531 --- /dev/null +++ b/sail_latex_mips/fclCReadHwrzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,32 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let (needSup, needAccessSys) : (bool, bool) = match #\hyperref[sailMIPSzunsigned]{unsigned}#(sel) { + 0 => (false, false), /* DDC -- no access control */ + 1 => (false, false), /* CULR -- no access control */ + 8 => (false, true), /* CPLR -- privileged TLS */ + 22 => (true, true), /* KR1C */ + 23 => (true, true), /* KR2C */ + 28 => (true, true), /* ErrorEPCC */ + 29 => (true, true), /* KCC */ + 30 => (true, true), /* KDC */ + 31 => (true, true), /* EPCC */ + _ => #\hyperref[sailMIPSzSignalException]{SignalException}#(ResI) +}; +if needAccessSys & not(#\hyperref[sailMIPSzpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}#()) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, sel) +else if needSup & not(#\hyperref[sailMIPSzgrantsAccess]{grantsAccess}#(#\hyperref[sailMIPSzgetAccessLevel]{getAccessLevel}#(), Supervisor)) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, sel) +else { + let capVal : Capability = match #\hyperref[sailMIPSzunsigned]{unsigned}#(sel) { + 0 => DDC, + 1 => CULR, + 8 => CPLR, + 22 => KR1C, + 23 => KR2C, + 28 => ErrorEPCC, + 29 => KCC, + 30 => KDC, + 31 => EPCC, + _ => {assert(false, "CReadHwr: should be unreachable code"); undefined} + }; + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, capVal); +}; diff --git a/sail_latex_mips/fclCReturnAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCReturnAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..12f08e35 --- /dev/null +++ b/sail_latex_mips/fclCReturnAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00101 @ 0b00000 @ 0b00000 @ 0b11111111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCReturn]{CReturn}#()) diff --git a/sail_latex_mips/fclCReturnzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCReturnzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..4a15489f --- /dev/null +++ b/sail_latex_mips/fclCReturnzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCReturn]{CReturn}#()) = "creturn" diff --git a/sail_latex_mips/fclCReturnzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCReturnzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..421966ce --- /dev/null +++ b/sail_latex_mips/fclCReturnzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00110 @ 0b000000000000000000000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCReturn]{CReturn}#()) diff --git a/sail_latex_mips/fclCReturnzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCReturnzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..ebabf695 --- /dev/null +++ b/sail_latex_mips/fclCReturnzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +#\hyperref[sailMIPSzraisezyc2zyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_ReturnTrap) diff --git a/sail_latex_mips/fclCSCCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSCCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..257f2b3a --- /dev/null +++ b/sail_latex_mips/fclCSCCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10000 @ cs : CapRegEnc @ cb : CapRegOrDDCEnc @ rd : IntRegEnc @ 0b00 @ 0b0111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSCC]{CSCC}#(cs, cb, rd)) diff --git a/sail_latex_mips/fclCSCCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCSCCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..eb22848c --- /dev/null +++ b/sail_latex_mips/fclCSCCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,38 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cs_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cs); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not (cb_val.permit_store) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitStoreViolation, cb) +else if not (cb_val.permit_store_cap) & (cs_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitStoreCapViolation, cb) +else if not (cb_val.permit_store_local_cap) & (cs_val.tag) & not (cs_val.global) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitStoreLocalCapViolation, cb) +else +{ + let vAddr = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); + let vAddr64 = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, vAddr); + if (vAddr + cap_size) > #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if vAddr < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if (vAddr % cap_size) != 0 then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdES, vAddr64) + else + { + let (pAddr, macr) = #\hyperref[sailMIPSzTLBTranslateC]{TLBTranslateC}#(vAddr64, StoreData); + let mtag : bool = match (if cs_val.tag == false then Unrestricted else macr) { + Trap => #\hyperref[sailMIPSzraisezyc2zyexceptionzybadaddr]{raise\_c2\_exception\_badaddr}#(CapEx_TLBNoStoreCap, cs, vAddr64), + Clear => false, + Unrestricted => cs_val.tag + }; + let success = if (CP0LLBit[0]) then + #\hyperref[sailMIPSzMEMwzytaggedzyconditional]{MEMw\_tagged\_conditional}#(pAddr, cap_size, mtag, #\hyperref[sailMIPSzcapToMemBits]{capToMemBits}#(cs_val)) + else + false; + #\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(success); + } +} diff --git a/sail_latex_mips/fclCSCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..4d38bcb0 --- /dev/null +++ b/sail_latex_mips/fclCSCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b111110 @ cs : CapRegEnc @ cb : CapRegOrDDCEnc @ rt : IntRegEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(11)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSC]{CSC}#(cs, cb, rt, offset)) diff --git a/sail_latex_mips/fclCSCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCSCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..71ec5890 --- /dev/null +++ b/sail_latex_mips/fclCSCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,35 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cs_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cs); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not (cb_val.permit_store) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitStoreViolation, cb) +else if not (cb_val.permit_store_cap) & (cs_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitStoreCapViolation, cb) +else if not (cb_val.permit_store_local_cap) & (cs_val.tag) & not (cs_val.global) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitStoreLocalCapViolation, cb) +else +{ + let cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); + let vAddr = (cursor + #\hyperref[sailMIPSzunsigned]{unsigned}#(#\hyperref[sailMIPSzrGPR]{rGPR}#(rt)) + 16 * #\hyperref[sailMIPSzsigned]{signed}#(offset)) % #\hyperref[sailMIPSzpow2]{pow2}#(64); + let vAddr64 = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, vAddr); + if (vAddr + cap_size) > #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if vAddr < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if (vAddr % cap_size) != 0 then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdES, vAddr64) + else + { + let (pAddr, macr) = #\hyperref[sailMIPSzTLBTranslateC]{TLBTranslateC}#(vAddr64, StoreData); + let mtag : bool = match (if cs_val.tag == false then Unrestricted else macr) { + Unrestricted => cs_val.tag, + Clear => false, + Trap => #\hyperref[sailMIPSzraisezyc2zyexceptionzybadaddr]{raise\_c2\_exception\_badaddr}#(CapEx_TLBNoStoreCap, cs, vAddr64) + }; + #\hyperref[sailMIPSzMEMwzytagged]{MEMw\_tagged}#(pAddr, cap_size, mtag, #\hyperref[sailMIPSzcapToMemBits]{capToMemBits}#(cs_val)) + } +} diff --git a/sail_latex_mips/fclCSealAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSealAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..dc7e3c78 --- /dev/null +++ b/sail_latex_mips/fclCSealAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegEnc @ ct : CapRegEnc @ 0b001011) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSeal]{CSeal}#(cd, cs, ct)) diff --git a/sail_latex_mips/fclCSealEntryzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCSealEntryzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..4f5e896e --- /dev/null +++ b/sail_latex_mips/fclCSealEntryzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCSealEntry]{CSealEntry}#(cd, cb)) = "csealentry " ^ #\hyperref[sailMIPSzstrCCArgs]{strCCArgs}#(cd, cb) diff --git a/sail_latex_mips/fclCSealEntryzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSealEntryzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..5ae8d15e --- /dev/null +++ b/sail_latex_mips/fclCSealEntryzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cb : CapRegEnc @ 0b11101 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSealEntry]{CSealEntry}#(cd, cb)) diff --git a/sail_latex_mips/fclCSealEntryzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCSealEntryzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..ab9d3cf6 --- /dev/null +++ b/sail_latex_mips/fclCSealEntryzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,19 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cs_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cs); +let cs_cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cs_val); +let cs_top = #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cs_val); +let cs_base = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cs_val); +if not (cs_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) +else if cs_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) +else if not (cs_val.permit_execute) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitExecuteViolation, cs) +else +{ + let (success, newCap) = #\hyperref[sailMIPSzsealCap]{sealCap}#(cs_val, #\hyperref[sailMIPSztozybits]{to\_bits}#(24, otype_sentry)); + if not (success) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_InexactBounds, cs) + else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) +} diff --git a/sail_latex_mips/fclCSealzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCSealzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..c796c953 --- /dev/null +++ b/sail_latex_mips/fclCSealzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCSeal]{CSeal}#(cd, cs, ct)) = "cseal " ^ #\hyperref[sailMIPSzstrCCCArgs]{strCCCArgs}#(cd, cs, ct) diff --git a/sail_latex_mips/fclCSealzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSealzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..585dd4d0 --- /dev/null +++ b/sail_latex_mips/fclCSealzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00010 @ cd : CapRegEnc @ cs : CapRegEnc @ ct : CapRegEnc @ 0b000@ 0b000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSeal]{CSeal}#(cd, cs, ct)) diff --git a/sail_latex_mips/fclCSealzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCSealzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e04d54f8 --- /dev/null +++ b/sail_latex_mips/fclCSealzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,30 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cs_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cs); +let ct_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(ct); +let ct_cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(ct_val); +let ct_top = #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(ct_val); +let ct_base = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(ct_val); +if not (cs_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) +else if not (ct_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, ct) +else if cs_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) +else if ct_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, ct) +else if not (ct_val.permit_seal) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitSealViolation, ct) +else if ct_cursor < ct_base then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) +else if ct_cursor >= ct_top then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) +else if ct_cursor > max_otype then /* prevents sealing with reserved or invalid otypes */ + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) +else +{ + let (success, newCap) = #\hyperref[sailMIPSzsealCap]{sealCap}#(cs_val, #\hyperref[sailMIPSztozybits]{to\_bits}#(24, ct_cursor)); + if not (success) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_InexactBounds, cs) + else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) +} diff --git a/sail_latex_mips/fclCSetAddrzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCSetAddrzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..47d4a959 --- /dev/null +++ b/sail_latex_mips/fclCSetAddrzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCSetAddr]{CSetAddr}#(cd, cs, rt)) = "csetaddr " ^ #\hyperref[sailMIPSzstrCCRArgs]{strCCRArgs}#(cd, cs, rt) diff --git a/sail_latex_mips/fclCSetAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSetAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..45fdc46a --- /dev/null +++ b/sail_latex_mips/fclCSetAddrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegEnc @ rs : IntRegEnc @ 0b100010) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSetAddr]{CSetAddr}#(cd, cs, rs)) diff --git a/sail_latex_mips/fclCSetAddrzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCSetAddrzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..f6bec2d3 --- /dev/null +++ b/sail_latex_mips/fclCSetAddrzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,13 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let rt_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rt); +if cb_val.tag & cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else +{ + let (representable, newCap) = #\hyperref[sailMIPSzsetCapAddr]{setCapAddr}#(cb_val, rt_val); + if representable then + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) + else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, #\hyperref[sailMIPSzunrepCap]{unrepCap}#(newCap)); +} diff --git a/sail_latex_mips/fclCSetBoundsAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSetBoundsAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..c077f7ce --- /dev/null +++ b/sail_latex_mips/fclCSetBoundsAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegEnc @ rt : IntRegEnc @ 0b001000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSetBounds]{CSetBounds}#(cd, cs, rt)) diff --git a/sail_latex_mips/fclCSetBoundsExactzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCSetBoundsExactzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..63abdb60 --- /dev/null +++ b/sail_latex_mips/fclCSetBoundsExactzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCSetBoundsExact]{CSetBoundsExact}#(cd, cs, rt)) = "csetboundsexact " ^ #\hyperref[sailMIPSzstrCCRArgs]{strCCRArgs}#(cd, cs, rt) diff --git a/sail_latex_mips/fclCSetBoundsExactzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSetBoundsExactzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..58257f3a --- /dev/null +++ b/sail_latex_mips/fclCSetBoundsExactzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegEnc @ rt : IntRegEnc @ 0b001001) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSetBoundsExact]{CSetBoundsExact}#(cd, cs, rt)) diff --git a/sail_latex_mips/fclCSetBoundsExactzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCSetBoundsExactzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..61c3d3eb --- /dev/null +++ b/sail_latex_mips/fclCSetBoundsExactzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,23 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let rt_val = #\hyperref[sailMIPSzunsigned]{unsigned}#(#\hyperref[sailMIPSzrGPR]{rGPR}#(rt)); +let cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); +let base = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val); +let top = #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val); +let newTop = cursor + rt_val; +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if cursor < base then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) +else if newTop > top then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) +else +{ + let (exact, newCap) = #\hyperref[sailMIPSzsetCapBounds]{setCapBounds}#(cb_val, #\hyperref[sailMIPSztozybits]{to\_bits}#(64, cursor), #\hyperref[sailMIPSztozybits]{to\_bits}#(65, newTop)); + if not (exact) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_InexactBounds, cb) + else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) +} diff --git a/sail_latex_mips/fclCSetBoundsImmediatezassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCSetBoundsImmediatezassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..5853713a --- /dev/null +++ b/sail_latex_mips/fclCSetBoundsImmediatezassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCSetBoundsImmediate]{CSetBoundsImmediate}#(cd, cb, imm)) = "csetboundsimm " ^ #\hyperref[sailMIPSzstrCCIUArgs]{strCCIUArgs}#(cd, cb, imm) diff --git a/sail_latex_mips/fclCSetBoundsImmediatezdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSetBoundsImmediatezdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..ca001629 --- /dev/null +++ b/sail_latex_mips/fclCSetBoundsImmediatezdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10100 @ cd : CapRegEnc @ cb : CapRegEnc @ imm : #\hyperref[sailMIPSzbits]{bits}#(11)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSetBoundsImmediate]{CSetBoundsImmediate}#(cd, cb, imm)) diff --git a/sail_latex_mips/fclCSetBoundsImmediatezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCSetBoundsImmediatezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..c9b8b1d6 --- /dev/null +++ b/sail_latex_mips/fclCSetBoundsImmediatezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,20 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let immU = #\hyperref[sailMIPSzunsigned]{unsigned}#(imm); +let cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); +let base = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val); +let top = #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val); +let newTop = cursor + immU; +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if cursor < base then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) +else if newTop > top then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) +else +{ + let (_, newCap) = #\hyperref[sailMIPSzsetCapBounds]{setCapBounds}#(cb_val, #\hyperref[sailMIPSztozybits]{to\_bits}#(64, cursor), #\hyperref[sailMIPSztozybits]{to\_bits}#(65, newTop)); + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) /* ignore exact */ +} diff --git a/sail_latex_mips/fclCSetBoundszassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCSetBoundszassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..b1a13d8c --- /dev/null +++ b/sail_latex_mips/fclCSetBoundszassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCSetBounds]{CSetBounds}#(cd, cs, rt)) = "csetbounds " ^ #\hyperref[sailMIPSzstrCCRArgs]{strCCRArgs}#(cd, cs, rt) diff --git a/sail_latex_mips/fclCSetBoundszdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSetBoundszdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..9d67fd45 --- /dev/null +++ b/sail_latex_mips/fclCSetBoundszdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00001 @ cd : CapRegEnc @ cb : CapRegEnc @ rt : IntRegEnc @ 0b000000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSetBounds]{CSetBounds}#(cd, cb, rt)) diff --git a/sail_latex_mips/fclCSetBoundszexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCSetBoundszexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..6518ee3c --- /dev/null +++ b/sail_latex_mips/fclCSetBoundszexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,20 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let rt_val = #\hyperref[sailMIPSzunsigned]{unsigned}#(#\hyperref[sailMIPSzrGPR]{rGPR}#(rt)); +let cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); +let base = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val); +let top = #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val); +let newTop = cursor + rt_val; +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if cursor < base then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) +else if newTop > top then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) +else +{ + let (_, newCap) = #\hyperref[sailMIPSzsetCapBounds]{setCapBounds}#(cb_val, #\hyperref[sailMIPSztozybits]{to\_bits}#(64, cursor), #\hyperref[sailMIPSztozybits]{to\_bits}#(65, newTop)); + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) /* ignore exact */ +} diff --git a/sail_latex_mips/fclCSetCIDcbzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSetCIDcbzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..744c3da8 --- /dev/null +++ b/sail_latex_mips/fclCSetCIDcbzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cb : CapRegEnc @ 0b00101 @ 0b11111 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSetCID]{CSetCID}#(cb)) diff --git a/sail_latex_mips/fclCSetCIDzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCSetCIDzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..b04be00f --- /dev/null +++ b/sail_latex_mips/fclCSetCIDzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCSetCID]{CSetCID}#(cb)) = "csetcid " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(cb) diff --git a/sail_latex_mips/fclCSetCIDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCSetCIDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..c91846e5 --- /dev/null +++ b/sail_latex_mips/fclCSetCIDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,18 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not (cb_val.permit_set_CID) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitSetCIDViolation, cb) +else +{ + let addr = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); + if addr < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if addr >= #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else + CID = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, addr); +} diff --git a/sail_latex_mips/fclCSetCauserszdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSetCauserszdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..97e6fca9 --- /dev/null +++ b/sail_latex_mips/fclCSetCauserszdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rs : IntRegEnc @ 0b00010 @ 0b11111 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSetCause]{CSetCause}#(rs)) diff --git a/sail_latex_mips/fclCSetCausertzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSetCausertzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..d0a8a580 --- /dev/null +++ b/sail_latex_mips/fclCSetCausertzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00100 @ 0b00000 @ 0b00000 @ rt : IntRegEnc @ 0b000 @ 0b100) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSetCause]{CSetCause}#(rt)) diff --git a/sail_latex_mips/fclCSetCausezassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCSetCausezassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..587300fe --- /dev/null +++ b/sail_latex_mips/fclCSetCausezassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCSetCause]{CSetCause}#(rs)) = "csetcause " ^ #\hyperref[sailMIPSzstrReg]{strReg}#(rs) diff --git a/sail_latex_mips/fclCSetCausezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCSetCausezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..574a9d2a --- /dev/null +++ b/sail_latex_mips/fclCSetCausezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,9 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +if not (#\hyperref[sailMIPSzpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}# ()) then + #\hyperref[sailMIPSzraisezyc2zyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_AccessSystemRegsViolation) +else +{ + let rt_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rt); + CapCause->#\hyperref[sailMIPSzExcCode]{ExcCode}#() = rt_val[15..8]; + CapCause->#\hyperref[sailMIPSzRegNum]{RegNum}#() = rt_val[7..0]; +} diff --git a/sail_latex_mips/fclCSetFlagszassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCSetFlagszassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..62e291c7 --- /dev/null +++ b/sail_latex_mips/fclCSetFlagszassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCSetFlags]{CSetFlags}#(cd, cs, rt)) = "csetflags " ^ #\hyperref[sailMIPSzstrCCRArgs]{strCCRArgs}#(cd, cs, rt) diff --git a/sail_latex_mips/fclCSetFlagszdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSetFlagszdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..8ef52d81 --- /dev/null +++ b/sail_latex_mips/fclCSetFlagszdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegEnc @ rt : IntRegEnc @ 0b001110) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSetFlags]{CSetFlags}#(cd, cs, rt)) diff --git a/sail_latex_mips/fclCSetFlagszexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCSetFlagszexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..073faac4 --- /dev/null +++ b/sail_latex_mips/fclCSetFlagszexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,10 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let rt_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rt); +if cb_val.tag & cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else +{ + let newCap = #\hyperref[sailMIPSzsetCapFlags]{setCapFlags}#(cb_val, #\hyperref[sailMIPSztruncate]{truncate}#(rt_val, num_flags)); + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap); +} diff --git a/sail_latex_mips/fclCSetOffsetAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSetOffsetAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..850777a5 --- /dev/null +++ b/sail_latex_mips/fclCSetOffsetAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegEnc @ rt : IntRegEnc @ 0b001111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSetOffset]{CSetOffset}#(cd, cs, rt)) diff --git a/sail_latex_mips/fclCSetOffsetzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCSetOffsetzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..481277c0 --- /dev/null +++ b/sail_latex_mips/fclCSetOffsetzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCSetOffset]{CSetOffset}#(cd, cs, rt)) = "csetoffset " ^ #\hyperref[sailMIPSzstrCCRArgs]{strCCRArgs}#(cd, cs, rt) diff --git a/sail_latex_mips/fclCSetOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSetOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..ba83fb55 --- /dev/null +++ b/sail_latex_mips/fclCSetOffsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01101 @ cd : CapRegEnc @ cb : CapRegEnc @ rt : IntRegEnc @ 0b000 @ 0b001) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSetOffset]{CSetOffset}#(cd, cb, rt)) diff --git a/sail_latex_mips/fclCSetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCSetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..8a39f657 --- /dev/null +++ b/sail_latex_mips/fclCSetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,13 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +let rt_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rt); +if cb_val.tag & cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else +{ + let (success, newCap) = #\hyperref[sailMIPSzsetCapOffset]{setCapOffset}#(cb_val, rt_val); + if success then + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, newCap) + else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, #\hyperref[sailMIPSzunrepCap]{unrepCap}#(newCap)) +} diff --git a/sail_latex_mips/fclCStoreAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCStoreAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..dd673c8e --- /dev/null +++ b/sail_latex_mips/fclCStoreAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b111010 @ rs : IntRegEnc @ cb : CapRegOrDDCEnc @ rt : IntRegEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(8) @ 0b0 @ 0b01) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCStore]{CStore}#(rs, cb, rt, offset, H)) /* CSH */ diff --git a/sail_latex_mips/fclCStoreBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCStoreBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..79f0a84b --- /dev/null +++ b/sail_latex_mips/fclCStoreBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b111010 @ rs : IntRegEnc @ cb : CapRegOrDDCEnc @ rt : IntRegEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(8) @ 0b0 @ 0b10) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCStore]{CStore}#(rs, cb, rt, offset, W)) /* CSW */ diff --git a/sail_latex_mips/fclCStoreConditionalAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCStoreConditionalAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..0cf11db9 --- /dev/null +++ b/sail_latex_mips/fclCStoreConditionalAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10000 @ rs : IntRegEnc @ cb : CapRegOrDDCEnc @ rd : IntRegEnc @ 0b0000 @ 0b01) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCStoreConditional]{CStoreConditional}#(rs, cb, rd, H)) /* CSCH */ diff --git a/sail_latex_mips/fclCStoreConditionalBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCStoreConditionalBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..c8afa321 --- /dev/null +++ b/sail_latex_mips/fclCStoreConditionalBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10000 @ rs : IntRegEnc @ cb : CapRegOrDDCEnc @ rd : IntRegEnc @ 0b0000 @ 0b10) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCStoreConditional]{CStoreConditional}#(rs, cb, rd, W)) /* CSCW */ diff --git a/sail_latex_mips/fclCStoreConditionalCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCStoreConditionalCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..3bade1a8 --- /dev/null +++ b/sail_latex_mips/fclCStoreConditionalCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10000 @ rs : IntRegEnc @ cb : CapRegOrDDCEnc @ rd : IntRegEnc @ 0b0000 @ 0b11) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCStoreConditional]{CStoreConditional}#(rs, cb, rd, D)) /* CSCD */ diff --git a/sail_latex_mips/fclCStoreConditionalzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCStoreConditionalzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..ed3e7e37 --- /dev/null +++ b/sail_latex_mips/fclCStoreConditionalzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b10000 @ rs : IntRegEnc @ cb : CapRegOrDDCEnc @ rd : IntRegEnc @ 0b0000 @ 0b00) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCStoreConditional]{CStoreConditional}#(rs, cb, rd, B)) /* CSCB */ diff --git a/sail_latex_mips/fclCStoreConditionalzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCStoreConditionalzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..178c373e --- /dev/null +++ b/sail_latex_mips/fclCStoreConditionalzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,36 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not (cb_val.permit_store) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitStoreViolation, cb) +else +{ + let size = #\hyperref[sailMIPSzwordWidthBytes]{wordWidthBytes}#(width); + let vAddr = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); + let vAddr64 = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, vAddr); + if (vAddr + size) > #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if vAddr < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if not (#\hyperref[sailMIPSzisAddressAligned]{isAddressAligned}#(vAddr64, width)) then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdES, vAddr64) + else + { + let pAddr = #\hyperref[sailMIPSzTLBTranslate]{TLBTranslate}#(vAddr64, StoreData); + let rs_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rs); + let success : bool = if (CP0LLBit[0]) then + match width + { + B => #\hyperref[sailMIPSzMEMwzyconditionalzywrapper]{MEMw\_conditional\_wrapper}#(pAddr, 1, rs_val[7..0]), + H => #\hyperref[sailMIPSzMEMwzyconditionalzywrapper]{MEMw\_conditional\_wrapper}#(pAddr, 2, rs_val[15..0]), + W => #\hyperref[sailMIPSzMEMwzyconditionalzywrapper]{MEMw\_conditional\_wrapper}#(pAddr, 4, rs_val[31..0]), + D => #\hyperref[sailMIPSzMEMwzyconditionalzywrapper]{MEMw\_conditional\_wrapper}#(pAddr, 8, rs_val) + } + else + false; + #\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(success); + } +} diff --git a/sail_latex_mips/fclCStoreCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCStoreCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..af2d0c1b --- /dev/null +++ b/sail_latex_mips/fclCStoreCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b111010 @ rs : IntRegEnc @ cb : CapRegOrDDCEnc @ rt : IntRegEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(8) @ 0b0 @ 0b11) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCStore]{CStore}#(rs, cb, rt, offset, D)) /* CSD */ diff --git a/sail_latex_mips/fclCStorezdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCStorezdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..aa47f88c --- /dev/null +++ b/sail_latex_mips/fclCStorezdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b111010 @ rs : IntRegEnc @ cb : CapRegOrDDCEnc @ rt : IntRegEnc @ offset : #\hyperref[sailMIPSzbits]{bits}#(8) @ 0b0 @ 0b00) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCStore]{CStore}#(rs, cb, rt, offset, B)) /* CSB */ diff --git a/sail_latex_mips/fclCStorezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCStorezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..54b467ab --- /dev/null +++ b/sail_latex_mips/fclCStorezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,33 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +if not (cb_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cb) +else if cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else if not (cb_val.permit_store) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitStoreViolation, cb) +else +{ + let size = #\hyperref[sailMIPSzwordWidthBytes]{wordWidthBytes}#(width); + let cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val); + let vAddr = (cursor + #\hyperref[sailMIPSzunsigned]{unsigned}#(#\hyperref[sailMIPSzrGPR]{rGPR}#(rt)) + size * #\hyperref[sailMIPSzsigned]{signed}#(offset)) % #\hyperref[sailMIPSzpow2]{pow2}#(64); + let vAddr64= #\hyperref[sailMIPSztozybits]{to\_bits}#(64, vAddr); + if (vAddr + size) > #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if vAddr < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, cb) + else if not (#\hyperref[sailMIPSzisAddressAligned]{isAddressAligned}#(vAddr64, width)) then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdES, vAddr64) + else + { + let pAddr = #\hyperref[sailMIPSzTLBTranslate]{TLBTranslate}#(vAddr64, StoreData); + let rs_val = #\hyperref[sailMIPSzrGPR]{rGPR}#(rs); + match width + { + B => #\hyperref[sailMIPSzMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 1) = rs_val[7..0], + H => #\hyperref[sailMIPSzMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 2) = rs_val[15..0], + W => #\hyperref[sailMIPSzMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 4) = rs_val[31..0], + D => #\hyperref[sailMIPSzMEMwzywrapper]{MEMw\_wrapper}#(pAddr, 8) = rs_val + } + } +} diff --git a/sail_latex_mips/fclCSubzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCSubzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..a4771d8b --- /dev/null +++ b/sail_latex_mips/fclCSubzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCSub]{CSub}#(rt, cb, cs)) = "csub " ^ #\hyperref[sailMIPSzstrRCCArgs]{strRCCArgs}#(rt, cb, cs) diff --git a/sail_latex_mips/fclCSubzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCSubzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..7d4ea2d1 --- /dev/null +++ b/sail_latex_mips/fclCSubzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rt : IntRegEnc @ cb : CapRegEnc @ cs : CapRegEnc @ 0b001010) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCSub]{CSub}#(rt, cb, cs)) diff --git a/sail_latex_mips/fclCSubzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCSubzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d19f5dc0 --- /dev/null +++ b/sail_latex_mips/fclCSubzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let ct_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(ct); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val) - #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(ct_val)) diff --git a/sail_latex_mips/fclCTestSubsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCTestSubsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..0e4458c6 --- /dev/null +++ b/sail_latex_mips/fclCTestSubsetzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegOrDDCEnc @ ct : CapRegEnc @ 0b100000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCTestSubset]{CTestSubset}#(rd, cb, ct)) diff --git a/sail_latex_mips/fclCTestSubsetzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCTestSubsetzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..927fd86c --- /dev/null +++ b/sail_latex_mips/fclCTestSubsetzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,20 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cb_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(cb); +let ct_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(ct); +let ct_top = #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(ct_val); +let ct_base = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(ct_val); +let ct_perms = #\hyperref[sailMIPSzgetCapPerms]{getCapPerms}#(ct_val); +let cb_top = #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(cb_val); +let cb_base = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cb_val); +let cb_perms = #\hyperref[sailMIPSzgetCapPerms]{getCapPerms}#(cb_val); +let result = if cb_val.tag != ct_val.tag then + 0b0 + else if ct_base < cb_base then + 0b0 + else if ct_top > cb_top then + 0b0 + else if (ct_perms & cb_perms) != ct_perms then + 0b0 + else + 0b1; +#\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(result); diff --git a/sail_latex_mips/fclCToPtrAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCToPtrAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..e9ac792c --- /dev/null +++ b/sail_latex_mips/fclCToPtrAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ rd : IntRegEnc @ cb : CapRegEnc @ ct : CapRegEnc @ 0b010010) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCToPtr]{CToPtr}#(rd, cb, ct)) diff --git a/sail_latex_mips/fclCToPtrzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCToPtrzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..3900e6c6 --- /dev/null +++ b/sail_latex_mips/fclCToPtrzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCToPtr]{CToPtr}#(rd, cb, ct)) = "ctoptr " ^ #\hyperref[sailMIPSzstrRCRArgs]{strRCRArgs}#(rd, cb, ct) diff --git a/sail_latex_mips/fclCToPtrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCToPtrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..31ffc13b --- /dev/null +++ b/sail_latex_mips/fclCToPtrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01100 @ rd : IntRegEnc @ cb : CapRegEnc @ ct : CapRegOrDDCEnc @ 0b000 @ 0b000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCToPtr]{CToPtr}#(rd, cb, ct)) diff --git a/sail_latex_mips/fclCToPtrzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCToPtrzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e84c13f1 --- /dev/null +++ b/sail_latex_mips/fclCToPtrzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,16 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let ct_val = #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(ct); +let cb_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); +if not (ct_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, ct) +else if cb_val.tag & cb_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cb) +else +{ + let ctBase = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(ct_val); + /* Note: returning zero for untagged values breaks magic constants such as SIG_IGN */ + #\hyperref[sailMIPSzwGPR]{wGPR}#(rd) = if not (cb_val.tag) then + #\hyperref[sailMIPSzzzeros]{zeros}#() + else + #\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cb_val) - ctBase) +} diff --git a/sail_latex_mips/fclCTwoDumprtzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCTwoDumprtzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..7c954102 --- /dev/null +++ b/sail_latex_mips/fclCTwoDumprtzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00100 @ rt : IntRegEnc @ 0x0006) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzC2Dump]{C2Dump}#(rt)) diff --git a/sail_latex_mips/fclCTwoDumpzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCTwoDumpzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_mips/fclCUnsealAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCUnsealAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..0493f5f2 --- /dev/null +++ b/sail_latex_mips/fclCUnsealAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cd : CapRegEnc @ cs : CapRegEnc @ ct : CapRegEnc @ 0b001100) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCUnseal]{CUnseal}#(cd, cs, ct)) diff --git a/sail_latex_mips/fclCUnsealzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCUnsealzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..e94f0d34 --- /dev/null +++ b/sail_latex_mips/fclCUnsealzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCUnseal]{CUnseal}#(cd, cs, ct)) = "cunseal " ^ #\hyperref[sailMIPSzstrCCCArgs]{strCCCArgs}#(cd, cs, ct) diff --git a/sail_latex_mips/fclCUnsealzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCUnsealzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..127f6630 --- /dev/null +++ b/sail_latex_mips/fclCUnsealzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00011 @ cd : CapRegEnc @ cs : CapRegEnc @ ct : CapRegEnc @ 0b000@ 0b000) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCUnseal]{CUnseal}#(cd, cs, ct)) diff --git a/sail_latex_mips/fclCUnsealzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCUnsealzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..cccdd245 --- /dev/null +++ b/sail_latex_mips/fclCUnsealzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,27 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let cs_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cs); +let cs_otype = #\hyperref[sailMIPSzunsigned]{unsigned}#(cs_val.otype); +let ct_val = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(ct); +let ct_cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(ct_val); +if not (cs_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, cs) +else if not (ct_val.tag) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, ct) +else if not (cs_val.sealed) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, cs) +else if ct_val.sealed then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, ct) +else if #\hyperref[sailMIPSzhasReservedOType]{hasReservedOType}#(cs_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TypeViolation, cs) +else if ct_cursor != cs_otype then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TypeViolation, ct) +else if not (ct_val.permit_unseal) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitUnsealViolation, ct) +else if ct_cursor < #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(ct_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) +else if ct_cursor >= #\hyperref[sailMIPSzgetCapTop]{getCapTop}#(ct_val) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, ct) +else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(cd, {#\hyperref[sailMIPSzunsealCap]{unsealCap}#(cs_val) with + global=(cs_val.global & ct_val.global) + }) diff --git a/sail_latex_mips/fclCWriteHwrzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclCWriteHwrzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..7069c863 --- /dev/null +++ b/sail_latex_mips/fclCWriteHwrzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzCWriteHwr]{CWriteHwr}#(cb, sel)) = "cwritehwr " ^ #\hyperref[sailMIPSzstrCRArgs]{strCRArgs}#(cb, sel) diff --git a/sail_latex_mips/fclCWriteHwrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclCWriteHwrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..dcb8a277 --- /dev/null +++ b/sail_latex_mips/fclCWriteHwrzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b00000 @ cb : CapRegEnc @ sel : CapHwrEnc @ 0b01110 @ 0b111111) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzCWriteHwr]{CWriteHwr}#(cb, sel)) diff --git a/sail_latex_mips/fclCWriteHwrzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclCWriteHwrzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..c13522b2 --- /dev/null +++ b/sail_latex_mips/fclCWriteHwrzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,32 @@ +#\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +let (needSup, needAccessSys) : (bool, bool) = match #\hyperref[sailMIPSzunsigned]{unsigned}#(sel) { + 0 => (false, false), /* DDC -- no access control */ + 1 => (false, false), /* CULR -- no access control */ + 8 => (false, true), /* CPLR -- privileged TLS */ + 22 => (true, true), /* KR1C */ + 23 => (true, true), /* KR2C */ + 28 => (true, true), /* ErrorEPCC */ + 29 => (true, true), /* KCC */ + 30 => (true, true), /* KDC */ + 31 => (true, true), /* EPCC */ + _ => #\hyperref[sailMIPSzSignalException]{SignalException}#(ResI) +}; +if needAccessSys & not(#\hyperref[sailMIPSzpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}#()) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, sel) +else if needSup & not(#\hyperref[sailMIPSzgrantsAccess]{grantsAccess}#(#\hyperref[sailMIPSzgetAccessLevel]{getAccessLevel}#(), Supervisor)) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_AccessSystemRegsViolation, sel) +else { + let capVal = #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(cb); + match #\hyperref[sailMIPSzunsigned]{unsigned}#(sel) { + 0 => DDC = capVal, + 1 => CULR = capVal, + 8 => CPLR = capVal, + 22 => KR1C = capVal, + 23 => KR2C = capVal, + 28 => ErrorEPCC = capVal, + 29 => KCC = capVal, + 30 => KDC = capVal, + 31 => EPCC = capVal, + _ => assert(false, "CWriteHwr: should be unreachable code") + }; +}; diff --git a/sail_latex_mips/fclClearRegsAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclClearRegsAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..b41741c1 --- /dev/null +++ b/sail_latex_mips/fclClearRegsAzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01111 @ 0b00001 @ imm : #\hyperref[sailMIPSzbits]{bits}#(16)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzClearRegs]{ClearRegs}#(GPHi, imm)) diff --git a/sail_latex_mips/fclClearRegsBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclClearRegsBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..d9c61a2b --- /dev/null +++ b/sail_latex_mips/fclClearRegsBzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01111 @ 0b00010 @ imm : #\hyperref[sailMIPSzbits]{bits}#(16)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzClearRegs]{ClearRegs}#(CLo, imm)) diff --git a/sail_latex_mips/fclClearRegsCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclClearRegsCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..5f6980ab --- /dev/null +++ b/sail_latex_mips/fclClearRegsCzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01111 @ 0b00011 @ imm : #\hyperref[sailMIPSzbits]{bits}#(16)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzClearRegs]{ClearRegs}#(CHi, imm)) diff --git a/sail_latex_mips/fclClearRegszdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclClearRegszdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..e4796136 --- /dev/null +++ b/sail_latex_mips/fclClearRegszdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzdecode]{decode}# (0b010010 @ 0b01111 @ 0b00000 @ imm : #\hyperref[sailMIPSzbits]{bits}#(16)) = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzClearRegs]{ClearRegs}#(GPLo, imm)) diff --git a/sail_latex_mips/fclClearRegszexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclClearRegszexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..151a82e5 --- /dev/null +++ b/sail_latex_mips/fclClearRegszexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,13 @@ +if ((regset == CLo) | (regset == CHi)) then + #\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}#(); +foreach (i from 0 to 15) + if (m[i]) then + match regset { + GPLo => #\hyperref[sailMIPSzwGPR]{wGPR}#(#\hyperref[sailMIPSztozybits]{to\_bits}#(5, i)) = #\hyperref[sailMIPSzzzeros]{zeros}#(), + GPHi => #\hyperref[sailMIPSzwGPR]{wGPR}#(#\hyperref[sailMIPSztozybits]{to\_bits}#(5, i+16)) = #\hyperref[sailMIPSzzzeros]{zeros}#(), + CLo => if i == 0 then + DDC = null_cap + else + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(#\hyperref[sailMIPSztozybits]{to\_bits}#(5, i)) = null_cap, + CHi => #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(#\hyperref[sailMIPSztozybits]{to\_bits}#(5, i+16)) = null_cap + } diff --git a/sail_latex_mips/fclRIzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclRIzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..80e3c892 --- /dev/null +++ b/sail_latex_mips/fclRIzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}# (#\hyperref[sailMIPSzRI]{RI}#()) = "reserved instruction" diff --git a/sail_latex_mips/fclRIzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/fclRIzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..b514c858 --- /dev/null +++ b/sail_latex_mips/fclRIzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function clause decode _ = #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSzRI]{RI}#()) diff --git a/sail_latex_mips/fclRIzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/fclRIzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..16db89a6 --- /dev/null +++ b/sail_latex_mips/fclRIzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +#\hyperref[sailMIPSzskipzybarr]{skip\_barr}#(); /* so we can build CHERI without MIPS for latex */ +#\hyperref[sailMIPSzSignalException]{SignalException}# (ResI) diff --git a/sail_latex_mips/fclzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/fclzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..62eb6d0d --- /dev/null +++ b/sail_latex_mips/fclzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailMIPSzassembly]{assembly}#(_) = "assembly unimplemented" diff --git a/sail_latex_mips/fnz__ided888b8991a27578d5dd72f84db80bce.tex b/sail_latex_mips/fnz__ided888b8991a27578d5dd72f84db80bce.tex new file mode 100644 index 00000000..475cf0a9 --- /dev/null +++ b/sail_latex_mips/fnz__ided888b8991a27578d5dd72f84db80bce.tex @@ -0,0 +1 @@ +function __id forall 'n. (x: #\hyperref[sailMIPSzint]{int}#('n)) -> #\hyperref[sailMIPSzint]{int}#('n) = x diff --git a/sail_latex_mips/fnz__mips_read6caa8fcafb5a40e544d3165028b605fb.tex b/sail_latex_mips/fnz__mips_read6caa8fcafb5a40e544d3165028b605fb.tex new file mode 100644 index 00000000..3f98a8f9 --- /dev/null +++ b/sail_latex_mips/fnz__mips_read6caa8fcafb5a40e544d3165028b605fb.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzzyzyMIPSzyread]{\_\_MIPS\_read}# (addr, width) = #\hyperref[sailMIPSzzyzyReadRAM]{\_\_ReadRAM}#(64, width, 0x0000_0000_0000_0000, addr) diff --git a/sail_latex_mips/fnz__mips_writed13fe4a15e9bfd2a9e702a585b5a7e1c.tex b/sail_latex_mips/fnz__mips_writed13fe4a15e9bfd2a9e702a585b5a7e1c.tex new file mode 100644 index 00000000..ed0aaeb2 --- /dev/null +++ b/sail_latex_mips/fnz__mips_writed13fe4a15e9bfd2a9e702a585b5a7e1c.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzzyzyMIPSzywrite]{\_\_MIPS\_write}# (addr, width, data) = let _ = #\hyperref[sailMIPSzzyzyWriteRAM]{\_\_WriteRAM}#(64, width, 0x0000_0000_0000_0000, addr, data) in () diff --git a/sail_latex_mips/fnz_get_capcausereg_bits52bfda42e15401e97a3be8662ec10017.tex b/sail_latex_mips/fnz_get_capcausereg_bits52bfda42e15401e97a3be8662ec10017.tex new file mode 100644 index 00000000..41426137 --- /dev/null +++ b/sail_latex_mips/fnz_get_capcausereg_bits52bfda42e15401e97a3be8662ec10017.tex @@ -0,0 +1 @@ +function _get_CapCauseReg_bits v = subrange_bits(v.CapCauseReg_chunk_0, 15, 0) diff --git a/sail_latex_mips/fnz_get_capcausereg_exccode52aba9ba1e3306797490b273879487fc.tex b/sail_latex_mips/fnz_get_capcausereg_exccode52aba9ba1e3306797490b273879487fc.tex new file mode 100644 index 00000000..00d9432c --- /dev/null +++ b/sail_latex_mips/fnz_get_capcausereg_exccode52aba9ba1e3306797490b273879487fc.tex @@ -0,0 +1 @@ +function _get_CapCauseReg_ExcCode v = subrange_bits(v.CapCauseReg_chunk_0, 15, 8) diff --git a/sail_latex_mips/fnz_get_capcausereg_regnumb581772dd095764cdd19b6f0e8c03d06.tex b/sail_latex_mips/fnz_get_capcausereg_regnumb581772dd095764cdd19b6f0e8c03d06.tex new file mode 100644 index 00000000..fa0a671c --- /dev/null +++ b/sail_latex_mips/fnz_get_capcausereg_regnumb581772dd095764cdd19b6f0e8c03d06.tex @@ -0,0 +1 @@ +function _get_CapCauseReg_RegNum v = subrange_bits(v.CapCauseReg_chunk_0, 7, 0) diff --git a/sail_latex_mips/fnz_get_causereg_bd96afa963ea8fd0967157eb8bd72a1b1b.tex b/sail_latex_mips/fnz_get_causereg_bd96afa963ea8fd0967157eb8bd72a1b1b.tex new file mode 100644 index 00000000..bc190d2e --- /dev/null +++ b/sail_latex_mips/fnz_get_causereg_bd96afa963ea8fd0967157eb8bd72a1b1b.tex @@ -0,0 +1 @@ +function _get_CauseReg_BD v = subrange_bits(v.CauseReg_chunk_0, 31, 31) diff --git a/sail_latex_mips/fnz_get_causereg_bits8438dd7e3e82e5a62db2fbe5d4c93611.tex b/sail_latex_mips/fnz_get_causereg_bits8438dd7e3e82e5a62db2fbe5d4c93611.tex new file mode 100644 index 00000000..28113e3f --- /dev/null +++ b/sail_latex_mips/fnz_get_causereg_bits8438dd7e3e82e5a62db2fbe5d4c93611.tex @@ -0,0 +1 @@ +function _get_CauseReg_bits v = subrange_bits(v.CauseReg_chunk_0, 31, 0) diff --git a/sail_latex_mips/fnz_get_causereg_cec50f9f4ac0a1b657a7733fa87526be2d.tex b/sail_latex_mips/fnz_get_causereg_cec50f9f4ac0a1b657a7733fa87526be2d.tex new file mode 100644 index 00000000..5cc65e26 --- /dev/null +++ b/sail_latex_mips/fnz_get_causereg_cec50f9f4ac0a1b657a7733fa87526be2d.tex @@ -0,0 +1 @@ +function _get_CauseReg_CE v = subrange_bits(v.CauseReg_chunk_0, 29, 28) diff --git a/sail_latex_mips/fnz_get_causereg_exccode8a67289fbe422c3b2420033795ebefa2.tex b/sail_latex_mips/fnz_get_causereg_exccode8a67289fbe422c3b2420033795ebefa2.tex new file mode 100644 index 00000000..3f731e44 --- /dev/null +++ b/sail_latex_mips/fnz_get_causereg_exccode8a67289fbe422c3b2420033795ebefa2.tex @@ -0,0 +1 @@ +function _get_CauseReg_ExcCode v = subrange_bits(v.CauseReg_chunk_0, 6, 2) diff --git a/sail_latex_mips/fnz_get_causereg_ip959fa0662dd3554fca2b54c9afdd9ed2.tex b/sail_latex_mips/fnz_get_causereg_ip959fa0662dd3554fca2b54c9afdd9ed2.tex new file mode 100644 index 00000000..ec9451ce --- /dev/null +++ b/sail_latex_mips/fnz_get_causereg_ip959fa0662dd3554fca2b54c9afdd9ed2.tex @@ -0,0 +1 @@ +function _get_CauseReg_IP v = subrange_bits(v.CauseReg_chunk_0, 15, 8) diff --git a/sail_latex_mips/fnz_get_causereg_iv8d01550ba34aa421cfc2ce657745d131.tex b/sail_latex_mips/fnz_get_causereg_iv8d01550ba34aa421cfc2ce657745d131.tex new file mode 100644 index 00000000..35a4e9ff --- /dev/null +++ b/sail_latex_mips/fnz_get_causereg_iv8d01550ba34aa421cfc2ce657745d131.tex @@ -0,0 +1 @@ +function _get_CauseReg_IV v = subrange_bits(v.CauseReg_chunk_0, 23, 23) diff --git a/sail_latex_mips/fnz_get_causereg_wpcbfccc2e0292d6f04b091ed268698e68.tex b/sail_latex_mips/fnz_get_causereg_wpcbfccc2e0292d6f04b091ed268698e68.tex new file mode 100644 index 00000000..9cb44c37 --- /dev/null +++ b/sail_latex_mips/fnz_get_causereg_wpcbfccc2e0292d6f04b091ed268698e68.tex @@ -0,0 +1 @@ +function _get_CauseReg_WP v = subrange_bits(v.CauseReg_chunk_0, 22, 22) diff --git a/sail_latex_mips/fnz_get_contextreg_badvpn2e4bacc76aa9f96063f0745bd9686a16d.tex b/sail_latex_mips/fnz_get_contextreg_badvpn2e4bacc76aa9f96063f0745bd9686a16d.tex new file mode 100644 index 00000000..25fb8061 --- /dev/null +++ b/sail_latex_mips/fnz_get_contextreg_badvpn2e4bacc76aa9f96063f0745bd9686a16d.tex @@ -0,0 +1 @@ +function _get_ContextReg_BadVPN2 v = subrange_bits(v.ContextReg_chunk_0, 22, 4) diff --git a/sail_latex_mips/fnz_get_contextreg_bits47e3c1ae3f3d71fe07d89e26af0dbb84.tex b/sail_latex_mips/fnz_get_contextreg_bits47e3c1ae3f3d71fe07d89e26af0dbb84.tex new file mode 100644 index 00000000..aedb853d --- /dev/null +++ b/sail_latex_mips/fnz_get_contextreg_bits47e3c1ae3f3d71fe07d89e26af0dbb84.tex @@ -0,0 +1 @@ +function _get_ContextReg_bits v = subrange_bits(v.ContextReg_chunk_0, 63, 0) diff --git a/sail_latex_mips/fnz_get_contextreg_ptebasebf430c35bdc563e19c3245773b4235dd.tex b/sail_latex_mips/fnz_get_contextreg_ptebasebf430c35bdc563e19c3245773b4235dd.tex new file mode 100644 index 00000000..87472bc6 --- /dev/null +++ b/sail_latex_mips/fnz_get_contextreg_ptebasebf430c35bdc563e19c3245773b4235dd.tex @@ -0,0 +1 @@ +function _get_ContextReg_PTEBase v = subrange_bits(v.ContextReg_chunk_0, 63, 23) diff --git a/sail_latex_mips/fnz_get_statusreg_bev76c45f173f7808e1e76c2d52dda65632.tex b/sail_latex_mips/fnz_get_statusreg_bev76c45f173f7808e1e76c2d52dda65632.tex new file mode 100644 index 00000000..9a36e3e3 --- /dev/null +++ b/sail_latex_mips/fnz_get_statusreg_bev76c45f173f7808e1e76c2d52dda65632.tex @@ -0,0 +1 @@ +function _get_StatusReg_BEV v = subrange_bits(v.StatusReg_chunk_0, 22, 22) diff --git a/sail_latex_mips/fnz_get_statusreg_bits13ab4975f147071137062e2fb2cba87b.tex b/sail_latex_mips/fnz_get_statusreg_bits13ab4975f147071137062e2fb2cba87b.tex new file mode 100644 index 00000000..cc02f3ac --- /dev/null +++ b/sail_latex_mips/fnz_get_statusreg_bits13ab4975f147071137062e2fb2cba87b.tex @@ -0,0 +1 @@ +function _get_StatusReg_bits v = subrange_bits(v.StatusReg_chunk_0, 31, 0) diff --git a/sail_latex_mips/fnz_get_statusreg_cuedce8fb3afbd16db31018057f7ad0656.tex b/sail_latex_mips/fnz_get_statusreg_cuedce8fb3afbd16db31018057f7ad0656.tex new file mode 100644 index 00000000..57799a3f --- /dev/null +++ b/sail_latex_mips/fnz_get_statusreg_cuedce8fb3afbd16db31018057f7ad0656.tex @@ -0,0 +1 @@ +function _get_StatusReg_CU v = subrange_bits(v.StatusReg_chunk_0, 31, 28) diff --git a/sail_latex_mips/fnz_get_statusreg_erl047dd24d9a0767af7b83a9fcc72aa531.tex b/sail_latex_mips/fnz_get_statusreg_erl047dd24d9a0767af7b83a9fcc72aa531.tex new file mode 100644 index 00000000..99a8fb4d --- /dev/null +++ b/sail_latex_mips/fnz_get_statusreg_erl047dd24d9a0767af7b83a9fcc72aa531.tex @@ -0,0 +1 @@ +function _get_StatusReg_ERL v = subrange_bits(v.StatusReg_chunk_0, 2, 2) diff --git a/sail_latex_mips/fnz_get_statusreg_exlf7067c47c7863a4f0a8be94eba05edef.tex b/sail_latex_mips/fnz_get_statusreg_exlf7067c47c7863a4f0a8be94eba05edef.tex new file mode 100644 index 00000000..0838e694 --- /dev/null +++ b/sail_latex_mips/fnz_get_statusreg_exlf7067c47c7863a4f0a8be94eba05edef.tex @@ -0,0 +1 @@ +function _get_StatusReg_EXL v = subrange_bits(v.StatusReg_chunk_0, 1, 1) diff --git a/sail_latex_mips/fnz_get_statusreg_ie87acfa5c96aee0f703b36a2c55d5a4de.tex b/sail_latex_mips/fnz_get_statusreg_ie87acfa5c96aee0f703b36a2c55d5a4de.tex new file mode 100644 index 00000000..7f33c519 --- /dev/null +++ b/sail_latex_mips/fnz_get_statusreg_ie87acfa5c96aee0f703b36a2c55d5a4de.tex @@ -0,0 +1 @@ +function _get_StatusReg_IE v = subrange_bits(v.StatusReg_chunk_0, 0, 0) diff --git a/sail_latex_mips/fnz_get_statusreg_im66d47baebca79600073ab942220bcc99.tex b/sail_latex_mips/fnz_get_statusreg_im66d47baebca79600073ab942220bcc99.tex new file mode 100644 index 00000000..d38f59e2 --- /dev/null +++ b/sail_latex_mips/fnz_get_statusreg_im66d47baebca79600073ab942220bcc99.tex @@ -0,0 +1 @@ +function _get_StatusReg_IM v = subrange_bits(v.StatusReg_chunk_0, 15, 8) diff --git a/sail_latex_mips/fnz_get_statusreg_ksuf8d380201accc76c9427799218dced26.tex b/sail_latex_mips/fnz_get_statusreg_ksuf8d380201accc76c9427799218dced26.tex new file mode 100644 index 00000000..1a102f2e --- /dev/null +++ b/sail_latex_mips/fnz_get_statusreg_ksuf8d380201accc76c9427799218dced26.tex @@ -0,0 +1 @@ +function _get_StatusReg_KSU v = subrange_bits(v.StatusReg_chunk_0, 4, 3) diff --git a/sail_latex_mips/fnz_get_statusreg_kxc88611604b607976b47f459ed5655112.tex b/sail_latex_mips/fnz_get_statusreg_kxc88611604b607976b47f459ed5655112.tex new file mode 100644 index 00000000..0b8d1ced --- /dev/null +++ b/sail_latex_mips/fnz_get_statusreg_kxc88611604b607976b47f459ed5655112.tex @@ -0,0 +1 @@ +function _get_StatusReg_KX v = subrange_bits(v.StatusReg_chunk_0, 7, 7) diff --git a/sail_latex_mips/fnz_get_statusreg_sx3938519915fcbea54772a8fb5488c993.tex b/sail_latex_mips/fnz_get_statusreg_sx3938519915fcbea54772a8fb5488c993.tex new file mode 100644 index 00000000..611907b7 --- /dev/null +++ b/sail_latex_mips/fnz_get_statusreg_sx3938519915fcbea54772a8fb5488c993.tex @@ -0,0 +1 @@ +function _get_StatusReg_SX v = subrange_bits(v.StatusReg_chunk_0, 6, 6) diff --git a/sail_latex_mips/fnz_get_statusreg_ux8cca4453438a4350fa4cd09d63ecb142.tex b/sail_latex_mips/fnz_get_statusreg_ux8cca4453438a4350fa4cd09d63ecb142.tex new file mode 100644 index 00000000..ee60670b --- /dev/null +++ b/sail_latex_mips/fnz_get_statusreg_ux8cca4453438a4350fa4cd09d63ecb142.tex @@ -0,0 +1 @@ +function _get_StatusReg_UX v = subrange_bits(v.StatusReg_chunk_0, 5, 5) diff --git a/sail_latex_mips/fnz_get_tlbentry_asidfa47e24a47d583f491181ee21931f29a.tex b/sail_latex_mips/fnz_get_tlbentry_asidfa47e24a47d583f491181ee21931f29a.tex new file mode 100644 index 00000000..98a5cc7e --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_asidfa47e24a47d583f491181ee21931f29a.tex @@ -0,0 +1 @@ +function _get_TLBEntry_asid v = subrange_bits(v.TLBEntry_chunk_1, 9, 2) diff --git a/sail_latex_mips/fnz_get_tlbentry_bits2da520175dbc548dab43cb481dedc49b.tex b/sail_latex_mips/fnz_get_tlbentry_bits2da520175dbc548dab43cb481dedc49b.tex new file mode 100644 index 00000000..92695402 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_bits2da520175dbc548dab43cb481dedc49b.tex @@ -0,0 +1 @@ +function _get_TLBEntry_bits v = bitvector_concat(subrange_bits(v.TLBEntry_chunk_1, 54, 0), subrange_bits(v.TLBEntry_chunk_0, 63, 0)) diff --git a/sail_latex_mips/fnz_get_tlbentry_c0b08789b6ce25b380e3b34466198a7af1.tex b/sail_latex_mips/fnz_get_tlbentry_c0b08789b6ce25b380e3b34466198a7af1.tex new file mode 100644 index 00000000..3bf11fa5 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_c0b08789b6ce25b380e3b34466198a7af1.tex @@ -0,0 +1 @@ +function _get_TLBEntry_c0 v = subrange_bits(v.TLBEntry_chunk_0, 4, 2) diff --git a/sail_latex_mips/fnz_get_tlbentry_c1d9106b812c3987770aecb7aeee7f8fda.tex b/sail_latex_mips/fnz_get_tlbentry_c1d9106b812c3987770aecb7aeee7f8fda.tex new file mode 100644 index 00000000..277403be --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_c1d9106b812c3987770aecb7aeee7f8fda.tex @@ -0,0 +1 @@ +function _get_TLBEntry_c1 v = subrange_bits(v.TLBEntry_chunk_0, 36, 34) diff --git a/sail_latex_mips/fnz_get_tlbentry_capl002a98d71ed3a8b3eadd001ccafb63932.tex b/sail_latex_mips/fnz_get_tlbentry_capl002a98d71ed3a8b3eadd001ccafb63932.tex new file mode 100644 index 00000000..6efed736 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_capl002a98d71ed3a8b3eadd001ccafb63932.tex @@ -0,0 +1 @@ +function _get_TLBEntry_capl0 v = subrange_bits(v.TLBEntry_chunk_0, 29, 29) diff --git a/sail_latex_mips/fnz_get_tlbentry_capl18435a7d1c69be8be8044b9bb801ed828.tex b/sail_latex_mips/fnz_get_tlbentry_capl18435a7d1c69be8be8044b9bb801ed828.tex new file mode 100644 index 00000000..39e1c956 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_capl18435a7d1c69be8be8044b9bb801ed828.tex @@ -0,0 +1 @@ +function _get_TLBEntry_capl1 v = subrange_bits(v.TLBEntry_chunk_0, 61, 61) diff --git a/sail_latex_mips/fnz_get_tlbentry_caplg09c840f382389fcdb91e393c6d35109de.tex b/sail_latex_mips/fnz_get_tlbentry_caplg09c840f382389fcdb91e393c6d35109de.tex new file mode 100644 index 00000000..2391904a --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_caplg09c840f382389fcdb91e393c6d35109de.tex @@ -0,0 +1 @@ +function _get_TLBEntry_caplg0 v = subrange_bits(v.TLBEntry_chunk_0, 31, 31) diff --git a/sail_latex_mips/fnz_get_tlbentry_caplg177ddc2b577eec904043a0416c9132f3d.tex b/sail_latex_mips/fnz_get_tlbentry_caplg177ddc2b577eec904043a0416c9132f3d.tex new file mode 100644 index 00000000..8c772361 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_caplg177ddc2b577eec904043a0416c9132f3d.tex @@ -0,0 +1 @@ +function _get_TLBEntry_caplg1 v = subrange_bits(v.TLBEntry_chunk_0, 63, 63) diff --git a/sail_latex_mips/fnz_get_tlbentry_caps0426df7440d2fbd940d22c5ff5d90fe0a.tex b/sail_latex_mips/fnz_get_tlbentry_caps0426df7440d2fbd940d22c5ff5d90fe0a.tex new file mode 100644 index 00000000..5cd599f2 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_caps0426df7440d2fbd940d22c5ff5d90fe0a.tex @@ -0,0 +1 @@ +function _get_TLBEntry_caps0 v = subrange_bits(v.TLBEntry_chunk_0, 30, 30) diff --git a/sail_latex_mips/fnz_get_tlbentry_caps1be8ae1b776f69c2c07935aba85396d3e.tex b/sail_latex_mips/fnz_get_tlbentry_caps1be8ae1b776f69c2c07935aba85396d3e.tex new file mode 100644 index 00000000..8f680e69 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_caps1be8ae1b776f69c2c07935aba85396d3e.tex @@ -0,0 +1 @@ +function _get_TLBEntry_caps1 v = subrange_bits(v.TLBEntry_chunk_0, 62, 62) diff --git a/sail_latex_mips/fnz_get_tlbentry_d0b7eda1bce555ea7549a9dffbb9e46114.tex b/sail_latex_mips/fnz_get_tlbentry_d0b7eda1bce555ea7549a9dffbb9e46114.tex new file mode 100644 index 00000000..5c99ed0e --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_d0b7eda1bce555ea7549a9dffbb9e46114.tex @@ -0,0 +1 @@ +function _get_TLBEntry_d0 v = subrange_bits(v.TLBEntry_chunk_0, 1, 1) diff --git a/sail_latex_mips/fnz_get_tlbentry_d13706a372dd719081d99230fe90f050d9.tex b/sail_latex_mips/fnz_get_tlbentry_d13706a372dd719081d99230fe90f050d9.tex new file mode 100644 index 00000000..77cd90b8 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_d13706a372dd719081d99230fe90f050d9.tex @@ -0,0 +1 @@ +function _get_TLBEntry_d1 v = subrange_bits(v.TLBEntry_chunk_0, 33, 33) diff --git a/sail_latex_mips/fnz_get_tlbentry_geeba2979d3314ef4d79ccdc6321d56cf.tex b/sail_latex_mips/fnz_get_tlbentry_geeba2979d3314ef4d79ccdc6321d56cf.tex new file mode 100644 index 00000000..b3d70e48 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_geeba2979d3314ef4d79ccdc6321d56cf.tex @@ -0,0 +1 @@ +function _get_TLBEntry_g v = subrange_bits(v.TLBEntry_chunk_1, 1, 1) diff --git a/sail_latex_mips/fnz_get_tlbentry_pagemask3eb7a6727c91e807993723589bef84a0.tex b/sail_latex_mips/fnz_get_tlbentry_pagemask3eb7a6727c91e807993723589bef84a0.tex new file mode 100644 index 00000000..4486ec7a --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_pagemask3eb7a6727c91e807993723589bef84a0.tex @@ -0,0 +1 @@ +function _get_TLBEntry_pagemask v = subrange_bits(v.TLBEntry_chunk_1, 54, 39) diff --git a/sail_latex_mips/fnz_get_tlbentry_pfn0a3de4c4c668cdca3f146093a35068cb5.tex b/sail_latex_mips/fnz_get_tlbentry_pfn0a3de4c4c668cdca3f146093a35068cb5.tex new file mode 100644 index 00000000..c0213031 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_pfn0a3de4c4c668cdca3f146093a35068cb5.tex @@ -0,0 +1 @@ +function _get_TLBEntry_pfn0 v = subrange_bits(v.TLBEntry_chunk_0, 28, 5) diff --git a/sail_latex_mips/fnz_get_tlbentry_pfn18a458700cdc028cfe46524e00f6a420b.tex b/sail_latex_mips/fnz_get_tlbentry_pfn18a458700cdc028cfe46524e00f6a420b.tex new file mode 100644 index 00000000..dac19225 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_pfn18a458700cdc028cfe46524e00f6a420b.tex @@ -0,0 +1 @@ +function _get_TLBEntry_pfn1 v = subrange_bits(v.TLBEntry_chunk_0, 60, 37) diff --git a/sail_latex_mips/fnz_get_tlbentry_ra5d843d822ff9bbef3239d0723cdb795.tex b/sail_latex_mips/fnz_get_tlbentry_ra5d843d822ff9bbef3239d0723cdb795.tex new file mode 100644 index 00000000..67bccbb2 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_ra5d843d822ff9bbef3239d0723cdb795.tex @@ -0,0 +1 @@ +function _get_TLBEntry_r v = subrange_bits(v.TLBEntry_chunk_1, 38, 37) diff --git a/sail_latex_mips/fnz_get_tlbentry_v035b9c796665ee176973e82b6ca9389bf.tex b/sail_latex_mips/fnz_get_tlbentry_v035b9c796665ee176973e82b6ca9389bf.tex new file mode 100644 index 00000000..f27369a3 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_v035b9c796665ee176973e82b6ca9389bf.tex @@ -0,0 +1 @@ +function _get_TLBEntry_v0 v = subrange_bits(v.TLBEntry_chunk_0, 0, 0) diff --git a/sail_latex_mips/fnz_get_tlbentry_v13ee360aa18ead69581f7606800abe3c1.tex b/sail_latex_mips/fnz_get_tlbentry_v13ee360aa18ead69581f7606800abe3c1.tex new file mode 100644 index 00000000..23e167a6 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_v13ee360aa18ead69581f7606800abe3c1.tex @@ -0,0 +1 @@ +function _get_TLBEntry_v1 v = subrange_bits(v.TLBEntry_chunk_0, 32, 32) diff --git a/sail_latex_mips/fnz_get_tlbentry_valid270ce68bc126e75f8229aa1123921cdb.tex b/sail_latex_mips/fnz_get_tlbentry_valid270ce68bc126e75f8229aa1123921cdb.tex new file mode 100644 index 00000000..34bdef8d --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_valid270ce68bc126e75f8229aa1123921cdb.tex @@ -0,0 +1 @@ +function _get_TLBEntry_valid v = subrange_bits(v.TLBEntry_chunk_1, 0, 0) diff --git a/sail_latex_mips/fnz_get_tlbentry_vpn28db0f6d71609de412536d5cf13f67255.tex b/sail_latex_mips/fnz_get_tlbentry_vpn28db0f6d71609de412536d5cf13f67255.tex new file mode 100644 index 00000000..14fe9f27 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentry_vpn28db0f6d71609de412536d5cf13f67255.tex @@ -0,0 +1 @@ +function _get_TLBEntry_vpn2 v = subrange_bits(v.TLBEntry_chunk_1, 36, 10) diff --git a/sail_latex_mips/fnz_get_tlbentryhireg_asidf305efdb6fafa938b0b36e9cf1064c32.tex b/sail_latex_mips/fnz_get_tlbentryhireg_asidf305efdb6fafa938b0b36e9cf1064c32.tex new file mode 100644 index 00000000..e7569bb0 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryhireg_asidf305efdb6fafa938b0b36e9cf1064c32.tex @@ -0,0 +1 @@ +function _get_TLBEntryHiReg_ASID v = subrange_bits(v.TLBEntryHiReg_chunk_0, 7, 0) diff --git a/sail_latex_mips/fnz_get_tlbentryhireg_bitsc1fe8d0802182557771e92e1a4937cbe.tex b/sail_latex_mips/fnz_get_tlbentryhireg_bitsc1fe8d0802182557771e92e1a4937cbe.tex new file mode 100644 index 00000000..28cd95c6 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryhireg_bitsc1fe8d0802182557771e92e1a4937cbe.tex @@ -0,0 +1 @@ +function _get_TLBEntryHiReg_bits v = subrange_bits(v.TLBEntryHiReg_chunk_0, 63, 0) diff --git a/sail_latex_mips/fnz_get_tlbentryhireg_clgkfdb82e0b9411605641d3f9425136dfa9.tex b/sail_latex_mips/fnz_get_tlbentryhireg_clgkfdb82e0b9411605641d3f9425136dfa9.tex new file mode 100644 index 00000000..591059e3 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryhireg_clgkfdb82e0b9411605641d3f9425136dfa9.tex @@ -0,0 +1 @@ +function _get_TLBEntryHiReg_CLGK v = subrange_bits(v.TLBEntryHiReg_chunk_0, 61, 61) diff --git a/sail_latex_mips/fnz_get_tlbentryhireg_clgseb7676dc6f5a395d559518d6f85dcb64.tex b/sail_latex_mips/fnz_get_tlbentryhireg_clgseb7676dc6f5a395d559518d6f85dcb64.tex new file mode 100644 index 00000000..96e5fb61 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryhireg_clgseb7676dc6f5a395d559518d6f85dcb64.tex @@ -0,0 +1 @@ +function _get_TLBEntryHiReg_CLGS v = subrange_bits(v.TLBEntryHiReg_chunk_0, 60, 60) diff --git a/sail_latex_mips/fnz_get_tlbentryhireg_clgu64e2f125adf86091d1447f203f4ee7c6.tex b/sail_latex_mips/fnz_get_tlbentryhireg_clgu64e2f125adf86091d1447f203f4ee7c6.tex new file mode 100644 index 00000000..c902d458 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryhireg_clgu64e2f125adf86091d1447f203f4ee7c6.tex @@ -0,0 +1 @@ +function _get_TLBEntryHiReg_CLGU v = subrange_bits(v.TLBEntryHiReg_chunk_0, 59, 59) diff --git a/sail_latex_mips/fnz_get_tlbentryhireg_r44dfedd92d1d8ea253c1ecd027897188.tex b/sail_latex_mips/fnz_get_tlbentryhireg_r44dfedd92d1d8ea253c1ecd027897188.tex new file mode 100644 index 00000000..318ba390 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryhireg_r44dfedd92d1d8ea253c1ecd027897188.tex @@ -0,0 +1 @@ +function _get_TLBEntryHiReg_R v = subrange_bits(v.TLBEntryHiReg_chunk_0, 63, 62) diff --git a/sail_latex_mips/fnz_get_tlbentryhireg_vpn226453e167422a9d6ebc21b19f1c01475.tex b/sail_latex_mips/fnz_get_tlbentryhireg_vpn226453e167422a9d6ebc21b19f1c01475.tex new file mode 100644 index 00000000..0247513d --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryhireg_vpn226453e167422a9d6ebc21b19f1c01475.tex @@ -0,0 +1 @@ +function _get_TLBEntryHiReg_VPN2 v = subrange_bits(v.TLBEntryHiReg_chunk_0, 39, 13) diff --git a/sail_latex_mips/fnz_get_tlbentryloreg_bitsb5a9322379b7dc75d999a3feb221ea39.tex b/sail_latex_mips/fnz_get_tlbentryloreg_bitsb5a9322379b7dc75d999a3feb221ea39.tex new file mode 100644 index 00000000..6c33b4dd --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryloreg_bitsb5a9322379b7dc75d999a3feb221ea39.tex @@ -0,0 +1 @@ +function _get_TLBEntryLoReg_bits v = subrange_bits(v.TLBEntryLoReg_chunk_0, 63, 0) diff --git a/sail_latex_mips/fnz_get_tlbentryloreg_c2c40f3d64ca0b68a2277af1f60c581c1.tex b/sail_latex_mips/fnz_get_tlbentryloreg_c2c40f3d64ca0b68a2277af1f60c581c1.tex new file mode 100644 index 00000000..0fddf8d0 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryloreg_c2c40f3d64ca0b68a2277af1f60c581c1.tex @@ -0,0 +1 @@ +function _get_TLBEntryLoReg_C v = subrange_bits(v.TLBEntryLoReg_chunk_0, 5, 3) diff --git a/sail_latex_mips/fnz_get_tlbentryloreg_capl1cbdda840b22f0691c3ea7fd12bfa8a7.tex b/sail_latex_mips/fnz_get_tlbentryloreg_capl1cbdda840b22f0691c3ea7fd12bfa8a7.tex new file mode 100644 index 00000000..cf5d856d --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryloreg_capl1cbdda840b22f0691c3ea7fd12bfa8a7.tex @@ -0,0 +1 @@ +function _get_TLBEntryLoReg_CapL v = subrange_bits(v.TLBEntryLoReg_chunk_0, 62, 62) diff --git a/sail_latex_mips/fnz_get_tlbentryloreg_caplg786d24724304fa8846dc63540a94622b.tex b/sail_latex_mips/fnz_get_tlbentryloreg_caplg786d24724304fa8846dc63540a94622b.tex new file mode 100644 index 00000000..1a54ba02 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryloreg_caplg786d24724304fa8846dc63540a94622b.tex @@ -0,0 +1 @@ +function _get_TLBEntryLoReg_CapLG v = subrange_bits(v.TLBEntryLoReg_chunk_0, 61, 61) diff --git a/sail_latex_mips/fnz_get_tlbentryloreg_capsde4f5c8e764147c851f8e5e575b0078e.tex b/sail_latex_mips/fnz_get_tlbentryloreg_capsde4f5c8e764147c851f8e5e575b0078e.tex new file mode 100644 index 00000000..f871cf38 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryloreg_capsde4f5c8e764147c851f8e5e575b0078e.tex @@ -0,0 +1 @@ +function _get_TLBEntryLoReg_CapS v = subrange_bits(v.TLBEntryLoReg_chunk_0, 63, 63) diff --git a/sail_latex_mips/fnz_get_tlbentryloreg_d4b10819936f555836fbb97995377cad3.tex b/sail_latex_mips/fnz_get_tlbentryloreg_d4b10819936f555836fbb97995377cad3.tex new file mode 100644 index 00000000..63b6ef1c --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryloreg_d4b10819936f555836fbb97995377cad3.tex @@ -0,0 +1 @@ +function _get_TLBEntryLoReg_D v = subrange_bits(v.TLBEntryLoReg_chunk_0, 2, 2) diff --git a/sail_latex_mips/fnz_get_tlbentryloreg_g502b190f751a82f1efdb937a5164a942.tex b/sail_latex_mips/fnz_get_tlbentryloreg_g502b190f751a82f1efdb937a5164a942.tex new file mode 100644 index 00000000..240b8bb5 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryloreg_g502b190f751a82f1efdb937a5164a942.tex @@ -0,0 +1 @@ +function _get_TLBEntryLoReg_G v = subrange_bits(v.TLBEntryLoReg_chunk_0, 0, 0) diff --git a/sail_latex_mips/fnz_get_tlbentryloreg_pfn7485f8da186fc5d3d7c7c1b76ae7d61a.tex b/sail_latex_mips/fnz_get_tlbentryloreg_pfn7485f8da186fc5d3d7c7c1b76ae7d61a.tex new file mode 100644 index 00000000..6f6a0bca --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryloreg_pfn7485f8da186fc5d3d7c7c1b76ae7d61a.tex @@ -0,0 +1 @@ +function _get_TLBEntryLoReg_PFN v = subrange_bits(v.TLBEntryLoReg_chunk_0, 29, 6) diff --git a/sail_latex_mips/fnz_get_tlbentryloreg_v92356d3167d468ba946d0be3ad44b292.tex b/sail_latex_mips/fnz_get_tlbentryloreg_v92356d3167d468ba946d0be3ad44b292.tex new file mode 100644 index 00000000..199c9bd3 --- /dev/null +++ b/sail_latex_mips/fnz_get_tlbentryloreg_v92356d3167d468ba946d0be3ad44b292.tex @@ -0,0 +1 @@ +function _get_TLBEntryLoReg_V v = subrange_bits(v.TLBEntryLoReg_chunk_0, 1, 1) diff --git a/sail_latex_mips/fnz_get_xcontextreg_bits2bb965f07f7084015cb7fcd7fddaa172.tex b/sail_latex_mips/fnz_get_xcontextreg_bits2bb965f07f7084015cb7fcd7fddaa172.tex new file mode 100644 index 00000000..e3d66276 --- /dev/null +++ b/sail_latex_mips/fnz_get_xcontextreg_bits2bb965f07f7084015cb7fcd7fddaa172.tex @@ -0,0 +1 @@ +function _get_XContextReg_bits v = subrange_bits(v.XContextReg_chunk_0, 63, 0) diff --git a/sail_latex_mips/fnz_get_xcontextreg_xbadvpn2404ed71ef244d675e19fa66dceb1c9c3.tex b/sail_latex_mips/fnz_get_xcontextreg_xbadvpn2404ed71ef244d675e19fa66dceb1c9c3.tex new file mode 100644 index 00000000..b709b952 --- /dev/null +++ b/sail_latex_mips/fnz_get_xcontextreg_xbadvpn2404ed71ef244d675e19fa66dceb1c9c3.tex @@ -0,0 +1 @@ +function _get_XContextReg_XBadVPN2 v = subrange_bits(v.XContextReg_chunk_0, 30, 4) diff --git a/sail_latex_mips/fnz_get_xcontextreg_xptebase0f9f79f33119625b2142eafc017db467.tex b/sail_latex_mips/fnz_get_xcontextreg_xptebase0f9f79f33119625b2142eafc017db467.tex new file mode 100644 index 00000000..e30ed783 --- /dev/null +++ b/sail_latex_mips/fnz_get_xcontextreg_xptebase0f9f79f33119625b2142eafc017db467.tex @@ -0,0 +1 @@ +function _get_XContextReg_XPTEBase v = subrange_bits(v.XContextReg_chunk_0, 63, 33) diff --git a/sail_latex_mips/fnz_get_xcontextreg_xrbc5c747b1b3124406ffd75a370867ebf.tex b/sail_latex_mips/fnz_get_xcontextreg_xrbc5c747b1b3124406ffd75a370867ebf.tex new file mode 100644 index 00000000..69c633df --- /dev/null +++ b/sail_latex_mips/fnz_get_xcontextreg_xrbc5c747b1b3124406ffd75a370867ebf.tex @@ -0,0 +1 @@ +function _get_XContextReg_XR v = subrange_bits(v.XContextReg_chunk_0, 32, 31) diff --git a/sail_latex_mips/fnz_set_capcausereg_bits0f09722beb30b9b32d98ac38786a393b.tex b/sail_latex_mips/fnz_set_capcausereg_bits0f09722beb30b9b32d98ac38786a393b.tex new file mode 100644 index 00000000..abc23af5 --- /dev/null +++ b/sail_latex_mips/fnz_set_capcausereg_bits0f09722beb30b9b32d98ac38786a393b.tex @@ -0,0 +1,5 @@ +function _set_CapCauseReg_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.CapCauseReg_chunk_0 = update_subrange_bits(r.CapCauseReg_chunk_0, 15, 0, subrange_bits(v, 15, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_capcausereg_exccode61e56f7469922be2cde66ae4460b17ee.tex b/sail_latex_mips/fnz_set_capcausereg_exccode61e56f7469922be2cde66ae4460b17ee.tex new file mode 100644 index 00000000..fde1945e --- /dev/null +++ b/sail_latex_mips/fnz_set_capcausereg_exccode61e56f7469922be2cde66ae4460b17ee.tex @@ -0,0 +1,5 @@ +function _set_CapCauseReg_ExcCode (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.CapCauseReg_chunk_0 = update_subrange_bits(r.CapCauseReg_chunk_0, 15, 8, subrange_bits(v, 7, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_capcausereg_regnum2d65e24c7a9625fc0aed9327369188a6.tex b/sail_latex_mips/fnz_set_capcausereg_regnum2d65e24c7a9625fc0aed9327369188a6.tex new file mode 100644 index 00000000..7bba0c0a --- /dev/null +++ b/sail_latex_mips/fnz_set_capcausereg_regnum2d65e24c7a9625fc0aed9327369188a6.tex @@ -0,0 +1,5 @@ +function _set_CapCauseReg_RegNum (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.CapCauseReg_chunk_0 = update_subrange_bits(r.CapCauseReg_chunk_0, 7, 0, subrange_bits(v, 7, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_causereg_bdb5f488f812625b8e1f8d3846c87da635.tex b/sail_latex_mips/fnz_set_causereg_bdb5f488f812625b8e1f8d3846c87da635.tex new file mode 100644 index 00000000..d10b4440 --- /dev/null +++ b/sail_latex_mips/fnz_set_causereg_bdb5f488f812625b8e1f8d3846c87da635.tex @@ -0,0 +1,5 @@ +function _set_CauseReg_BD (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.CauseReg_chunk_0 = update_subrange_bits(r.CauseReg_chunk_0, 31, 31, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_causereg_bits73c1fb63898bc74942a3c60d0ceacd0a.tex b/sail_latex_mips/fnz_set_causereg_bits73c1fb63898bc74942a3c60d0ceacd0a.tex new file mode 100644 index 00000000..db52cb50 --- /dev/null +++ b/sail_latex_mips/fnz_set_causereg_bits73c1fb63898bc74942a3c60d0ceacd0a.tex @@ -0,0 +1,5 @@ +function _set_CauseReg_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.CauseReg_chunk_0 = update_subrange_bits(r.CauseReg_chunk_0, 31, 0, subrange_bits(v, 31, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_causereg_ce01fc3f03d0d74f4e0d5a0942681ed38a.tex b/sail_latex_mips/fnz_set_causereg_ce01fc3f03d0d74f4e0d5a0942681ed38a.tex new file mode 100644 index 00000000..4423e9a2 --- /dev/null +++ b/sail_latex_mips/fnz_set_causereg_ce01fc3f03d0d74f4e0d5a0942681ed38a.tex @@ -0,0 +1,5 @@ +function _set_CauseReg_CE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.CauseReg_chunk_0 = update_subrange_bits(r.CauseReg_chunk_0, 29, 28, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_causereg_exccode9170f535490a825d67ffd95250c51021.tex b/sail_latex_mips/fnz_set_causereg_exccode9170f535490a825d67ffd95250c51021.tex new file mode 100644 index 00000000..f80cfe15 --- /dev/null +++ b/sail_latex_mips/fnz_set_causereg_exccode9170f535490a825d67ffd95250c51021.tex @@ -0,0 +1,5 @@ +function _set_CauseReg_ExcCode (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.CauseReg_chunk_0 = update_subrange_bits(r.CauseReg_chunk_0, 6, 2, subrange_bits(v, 4, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_causereg_ip2026aa5013ac14eda0adff00c82c7a29.tex b/sail_latex_mips/fnz_set_causereg_ip2026aa5013ac14eda0adff00c82c7a29.tex new file mode 100644 index 00000000..6ed9fe39 --- /dev/null +++ b/sail_latex_mips/fnz_set_causereg_ip2026aa5013ac14eda0adff00c82c7a29.tex @@ -0,0 +1,5 @@ +function _set_CauseReg_IP (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.CauseReg_chunk_0 = update_subrange_bits(r.CauseReg_chunk_0, 15, 8, subrange_bits(v, 7, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_causereg_iv526ac3c679cca6391db51d524d6d72ad.tex b/sail_latex_mips/fnz_set_causereg_iv526ac3c679cca6391db51d524d6d72ad.tex new file mode 100644 index 00000000..152c3cec --- /dev/null +++ b/sail_latex_mips/fnz_set_causereg_iv526ac3c679cca6391db51d524d6d72ad.tex @@ -0,0 +1,5 @@ +function _set_CauseReg_IV (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.CauseReg_chunk_0 = update_subrange_bits(r.CauseReg_chunk_0, 23, 23, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_causereg_wpff070e6ed3da50f2ad0a0d32ca5c1969.tex b/sail_latex_mips/fnz_set_causereg_wpff070e6ed3da50f2ad0a0d32ca5c1969.tex new file mode 100644 index 00000000..1dcaf1e8 --- /dev/null +++ b/sail_latex_mips/fnz_set_causereg_wpff070e6ed3da50f2ad0a0d32ca5c1969.tex @@ -0,0 +1,5 @@ +function _set_CauseReg_WP (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.CauseReg_chunk_0 = update_subrange_bits(r.CauseReg_chunk_0, 22, 22, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_contextreg_badvpn29fd378dc6ecdfabb3a91f7deb59e56a1.tex b/sail_latex_mips/fnz_set_contextreg_badvpn29fd378dc6ecdfabb3a91f7deb59e56a1.tex new file mode 100644 index 00000000..a4a40829 --- /dev/null +++ b/sail_latex_mips/fnz_set_contextreg_badvpn29fd378dc6ecdfabb3a91f7deb59e56a1.tex @@ -0,0 +1,5 @@ +function _set_ContextReg_BadVPN2 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.ContextReg_chunk_0 = update_subrange_bits(r.ContextReg_chunk_0, 22, 4, subrange_bits(v, 18, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_contextreg_bitsbbc1c515c2c901309dcbe9d97b5823cc.tex b/sail_latex_mips/fnz_set_contextreg_bitsbbc1c515c2c901309dcbe9d97b5823cc.tex new file mode 100644 index 00000000..41cb9df7 --- /dev/null +++ b/sail_latex_mips/fnz_set_contextreg_bitsbbc1c515c2c901309dcbe9d97b5823cc.tex @@ -0,0 +1,5 @@ +function _set_ContextReg_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.ContextReg_chunk_0 = update_subrange_bits(r.ContextReg_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_contextreg_ptebase3d2c746ed33c90438134f4f612df5252.tex b/sail_latex_mips/fnz_set_contextreg_ptebase3d2c746ed33c90438134f4f612df5252.tex new file mode 100644 index 00000000..3725e25d --- /dev/null +++ b/sail_latex_mips/fnz_set_contextreg_ptebase3d2c746ed33c90438134f4f612df5252.tex @@ -0,0 +1,5 @@ +function _set_ContextReg_PTEBase (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.ContextReg_chunk_0 = update_subrange_bits(r.ContextReg_chunk_0, 63, 23, subrange_bits(v, 40, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_statusreg_bev924ce14fffca002f9543765ad1071fc1.tex b/sail_latex_mips/fnz_set_statusreg_bev924ce14fffca002f9543765ad1071fc1.tex new file mode 100644 index 00000000..e01c39cb --- /dev/null +++ b/sail_latex_mips/fnz_set_statusreg_bev924ce14fffca002f9543765ad1071fc1.tex @@ -0,0 +1,5 @@ +function _set_StatusReg_BEV (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.StatusReg_chunk_0 = update_subrange_bits(r.StatusReg_chunk_0, 22, 22, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_statusreg_bits4f92ee35af828325dd4c014bea381e05.tex b/sail_latex_mips/fnz_set_statusreg_bits4f92ee35af828325dd4c014bea381e05.tex new file mode 100644 index 00000000..5a51d48d --- /dev/null +++ b/sail_latex_mips/fnz_set_statusreg_bits4f92ee35af828325dd4c014bea381e05.tex @@ -0,0 +1,5 @@ +function _set_StatusReg_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.StatusReg_chunk_0 = update_subrange_bits(r.StatusReg_chunk_0, 31, 0, subrange_bits(v, 31, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_statusreg_cu382e74466b55efdc144bb605d76fa627.tex b/sail_latex_mips/fnz_set_statusreg_cu382e74466b55efdc144bb605d76fa627.tex new file mode 100644 index 00000000..dd86f345 --- /dev/null +++ b/sail_latex_mips/fnz_set_statusreg_cu382e74466b55efdc144bb605d76fa627.tex @@ -0,0 +1,5 @@ +function _set_StatusReg_CU (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.StatusReg_chunk_0 = update_subrange_bits(r.StatusReg_chunk_0, 31, 28, subrange_bits(v, 3, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_statusreg_erld7df28f36a304a50bf4b1ac7531ab82d.tex b/sail_latex_mips/fnz_set_statusreg_erld7df28f36a304a50bf4b1ac7531ab82d.tex new file mode 100644 index 00000000..3413e283 --- /dev/null +++ b/sail_latex_mips/fnz_set_statusreg_erld7df28f36a304a50bf4b1ac7531ab82d.tex @@ -0,0 +1,5 @@ +function _set_StatusReg_ERL (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.StatusReg_chunk_0 = update_subrange_bits(r.StatusReg_chunk_0, 2, 2, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_statusreg_exl9372beedcb66769ffb9a665777e1daaf.tex b/sail_latex_mips/fnz_set_statusreg_exl9372beedcb66769ffb9a665777e1daaf.tex new file mode 100644 index 00000000..94866a80 --- /dev/null +++ b/sail_latex_mips/fnz_set_statusreg_exl9372beedcb66769ffb9a665777e1daaf.tex @@ -0,0 +1,5 @@ +function _set_StatusReg_EXL (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.StatusReg_chunk_0 = update_subrange_bits(r.StatusReg_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_statusreg_ie25e69e4e6e9e37925cebd95113995258.tex b/sail_latex_mips/fnz_set_statusreg_ie25e69e4e6e9e37925cebd95113995258.tex new file mode 100644 index 00000000..928bf8cd --- /dev/null +++ b/sail_latex_mips/fnz_set_statusreg_ie25e69e4e6e9e37925cebd95113995258.tex @@ -0,0 +1,5 @@ +function _set_StatusReg_IE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.StatusReg_chunk_0 = update_subrange_bits(r.StatusReg_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_statusreg_imfe5182ff0da7697ee27eb5e78eae3abc.tex b/sail_latex_mips/fnz_set_statusreg_imfe5182ff0da7697ee27eb5e78eae3abc.tex new file mode 100644 index 00000000..c06ba0a7 --- /dev/null +++ b/sail_latex_mips/fnz_set_statusreg_imfe5182ff0da7697ee27eb5e78eae3abc.tex @@ -0,0 +1,5 @@ +function _set_StatusReg_IM (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.StatusReg_chunk_0 = update_subrange_bits(r.StatusReg_chunk_0, 15, 8, subrange_bits(v, 7, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_statusreg_ksu10d20f93e7ee13723bb4b72cd7d3ea0a.tex b/sail_latex_mips/fnz_set_statusreg_ksu10d20f93e7ee13723bb4b72cd7d3ea0a.tex new file mode 100644 index 00000000..508d48ab --- /dev/null +++ b/sail_latex_mips/fnz_set_statusreg_ksu10d20f93e7ee13723bb4b72cd7d3ea0a.tex @@ -0,0 +1,5 @@ +function _set_StatusReg_KSU (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.StatusReg_chunk_0 = update_subrange_bits(r.StatusReg_chunk_0, 4, 3, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_statusreg_kxca8ee85879aede01e75749335f0c00c9.tex b/sail_latex_mips/fnz_set_statusreg_kxca8ee85879aede01e75749335f0c00c9.tex new file mode 100644 index 00000000..297a9458 --- /dev/null +++ b/sail_latex_mips/fnz_set_statusreg_kxca8ee85879aede01e75749335f0c00c9.tex @@ -0,0 +1,5 @@ +function _set_StatusReg_KX (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.StatusReg_chunk_0 = update_subrange_bits(r.StatusReg_chunk_0, 7, 7, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_statusreg_sx7f79d23ff0ae6a043165750f8bb87713.tex b/sail_latex_mips/fnz_set_statusreg_sx7f79d23ff0ae6a043165750f8bb87713.tex new file mode 100644 index 00000000..3116657a --- /dev/null +++ b/sail_latex_mips/fnz_set_statusreg_sx7f79d23ff0ae6a043165750f8bb87713.tex @@ -0,0 +1,5 @@ +function _set_StatusReg_SX (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.StatusReg_chunk_0 = update_subrange_bits(r.StatusReg_chunk_0, 6, 6, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_statusreg_uxedb360d1d15e38d213f56b0eaa07f3a6.tex b/sail_latex_mips/fnz_set_statusreg_uxedb360d1d15e38d213f56b0eaa07f3a6.tex new file mode 100644 index 00000000..6bc23ada --- /dev/null +++ b/sail_latex_mips/fnz_set_statusreg_uxedb360d1d15e38d213f56b0eaa07f3a6.tex @@ -0,0 +1,5 @@ +function _set_StatusReg_UX (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.StatusReg_chunk_0 = update_subrange_bits(r.StatusReg_chunk_0, 5, 5, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_asid24ada87abf0e962f7eae9b5498024297.tex b/sail_latex_mips/fnz_set_tlbentry_asid24ada87abf0e962f7eae9b5498024297.tex new file mode 100644 index 00000000..006d59d1 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_asid24ada87abf0e962f7eae9b5498024297.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_asid (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_1 = update_subrange_bits(r.TLBEntry_chunk_1, 9, 2, subrange_bits(v, 7, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_bits757b4b8be4b3d6e342d238326f83470b.tex b/sail_latex_mips/fnz_set_tlbentry_bits757b4b8be4b3d6e342d238326f83470b.tex new file mode 100644 index 00000000..ba843b5d --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_bits757b4b8be4b3d6e342d238326f83470b.tex @@ -0,0 +1,6 @@ +function _set_TLBEntry_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_1 = update_subrange_bits(r.TLBEntry_chunk_1, 54, 0, subrange_bits(v, 118, 64)); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_c06c71cb666e35c0f50388fb49595583ae.tex b/sail_latex_mips/fnz_set_tlbentry_c06c71cb666e35c0f50388fb49595583ae.tex new file mode 100644 index 00000000..2963e6b1 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_c06c71cb666e35c0f50388fb49595583ae.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_c0 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 4, 2, subrange_bits(v, 2, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_c148e5c1e1296cfbf56bc100936b91f1e1.tex b/sail_latex_mips/fnz_set_tlbentry_c148e5c1e1296cfbf56bc100936b91f1e1.tex new file mode 100644 index 00000000..5daaea6b --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_c148e5c1e1296cfbf56bc100936b91f1e1.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_c1 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 36, 34, subrange_bits(v, 2, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_capl02f9386e56e409f94f40b03eb58643a70.tex b/sail_latex_mips/fnz_set_tlbentry_capl02f9386e56e409f94f40b03eb58643a70.tex new file mode 100644 index 00000000..4db116c9 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_capl02f9386e56e409f94f40b03eb58643a70.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_capl0 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 29, 29, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_capl11a35d84794ef9016f4f97c80e21c876e.tex b/sail_latex_mips/fnz_set_tlbentry_capl11a35d84794ef9016f4f97c80e21c876e.tex new file mode 100644 index 00000000..d9b86579 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_capl11a35d84794ef9016f4f97c80e21c876e.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_capl1 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 61, 61, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_caplg0226ebad6aa3e6193defac30a2d1ea82d.tex b/sail_latex_mips/fnz_set_tlbentry_caplg0226ebad6aa3e6193defac30a2d1ea82d.tex new file mode 100644 index 00000000..29ac8edc --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_caplg0226ebad6aa3e6193defac30a2d1ea82d.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_caplg0 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 31, 31, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_caplg1c568708bced17cbfbd6bc97c09748e38.tex b/sail_latex_mips/fnz_set_tlbentry_caplg1c568708bced17cbfbd6bc97c09748e38.tex new file mode 100644 index 00000000..9b7dae75 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_caplg1c568708bced17cbfbd6bc97c09748e38.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_caplg1 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 63, 63, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_caps0857000eddf4e4fae631d006dab5b1e0b.tex b/sail_latex_mips/fnz_set_tlbentry_caps0857000eddf4e4fae631d006dab5b1e0b.tex new file mode 100644 index 00000000..69b24032 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_caps0857000eddf4e4fae631d006dab5b1e0b.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_caps0 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 30, 30, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_caps14e73f26c66b0f5dd767fc96d260e533e.tex b/sail_latex_mips/fnz_set_tlbentry_caps14e73f26c66b0f5dd767fc96d260e533e.tex new file mode 100644 index 00000000..82952c9d --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_caps14e73f26c66b0f5dd767fc96d260e533e.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_caps1 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 62, 62, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_d0868263c352cb541c47607b23c5681223.tex b/sail_latex_mips/fnz_set_tlbentry_d0868263c352cb541c47607b23c5681223.tex new file mode 100644 index 00000000..a66cdd74 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_d0868263c352cb541c47607b23c5681223.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_d0 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_d1f392ee8bca5cfc128a0ed08500399129.tex b/sail_latex_mips/fnz_set_tlbentry_d1f392ee8bca5cfc128a0ed08500399129.tex new file mode 100644 index 00000000..e719b747 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_d1f392ee8bca5cfc128a0ed08500399129.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_d1 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 33, 33, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_g2bf85ee100b3f01a0e05550245e7babe.tex b/sail_latex_mips/fnz_set_tlbentry_g2bf85ee100b3f01a0e05550245e7babe.tex new file mode 100644 index 00000000..09b7d55a --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_g2bf85ee100b3f01a0e05550245e7babe.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_g (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_1 = update_subrange_bits(r.TLBEntry_chunk_1, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_pagemask688109458a7688b3fb0c4bd96cc468ce.tex b/sail_latex_mips/fnz_set_tlbentry_pagemask688109458a7688b3fb0c4bd96cc468ce.tex new file mode 100644 index 00000000..1ade21ea --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_pagemask688109458a7688b3fb0c4bd96cc468ce.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_pagemask (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_1 = update_subrange_bits(r.TLBEntry_chunk_1, 54, 39, subrange_bits(v, 15, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_pfn0572e8586307e418abaeebb59ab57b8fb.tex b/sail_latex_mips/fnz_set_tlbentry_pfn0572e8586307e418abaeebb59ab57b8fb.tex new file mode 100644 index 00000000..26630612 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_pfn0572e8586307e418abaeebb59ab57b8fb.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_pfn0 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 28, 5, subrange_bits(v, 23, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_pfn199862dd67e6305081f59d2d64ffa6977.tex b/sail_latex_mips/fnz_set_tlbentry_pfn199862dd67e6305081f59d2d64ffa6977.tex new file mode 100644 index 00000000..ce84cae5 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_pfn199862dd67e6305081f59d2d64ffa6977.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_pfn1 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 60, 37, subrange_bits(v, 23, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_r13eb1c39c82ca214056fd1b1c838ef2f.tex b/sail_latex_mips/fnz_set_tlbentry_r13eb1c39c82ca214056fd1b1c838ef2f.tex new file mode 100644 index 00000000..b019169b --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_r13eb1c39c82ca214056fd1b1c838ef2f.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_r (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_1 = update_subrange_bits(r.TLBEntry_chunk_1, 38, 37, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_v03152956c4a42e1c80db703a10c7a43d4.tex b/sail_latex_mips/fnz_set_tlbentry_v03152956c4a42e1c80db703a10c7a43d4.tex new file mode 100644 index 00000000..16863387 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_v03152956c4a42e1c80db703a10c7a43d4.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_v0 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_v17258e9ab7f5388c5e3cc6aaba8474f00.tex b/sail_latex_mips/fnz_set_tlbentry_v17258e9ab7f5388c5e3cc6aaba8474f00.tex new file mode 100644 index 00000000..00de8404 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_v17258e9ab7f5388c5e3cc6aaba8474f00.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_v1 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_0 = update_subrange_bits(r.TLBEntry_chunk_0, 32, 32, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_valida29af220299133e11c38510f27092e5d.tex b/sail_latex_mips/fnz_set_tlbentry_valida29af220299133e11c38510f27092e5d.tex new file mode 100644 index 00000000..99d8e6db --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_valida29af220299133e11c38510f27092e5d.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_valid (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_1 = update_subrange_bits(r.TLBEntry_chunk_1, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentry_vpn298a5bd5fa3b51188021ac781ba6fee98.tex b/sail_latex_mips/fnz_set_tlbentry_vpn298a5bd5fa3b51188021ac781ba6fee98.tex new file mode 100644 index 00000000..8f3ba971 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentry_vpn298a5bd5fa3b51188021ac781ba6fee98.tex @@ -0,0 +1,5 @@ +function _set_TLBEntry_vpn2 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntry_chunk_1 = update_subrange_bits(r.TLBEntry_chunk_1, 36, 10, subrange_bits(v, 26, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryhireg_asid321161cd55126c8938237eb466aaf985.tex b/sail_latex_mips/fnz_set_tlbentryhireg_asid321161cd55126c8938237eb466aaf985.tex new file mode 100644 index 00000000..0a9d7e79 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryhireg_asid321161cd55126c8938237eb466aaf985.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryHiReg_ASID (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryHiReg_chunk_0 = update_subrange_bits(r.TLBEntryHiReg_chunk_0, 7, 0, subrange_bits(v, 7, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryhireg_bits830f40aea8b421a1ac74662681c59991.tex b/sail_latex_mips/fnz_set_tlbentryhireg_bits830f40aea8b421a1ac74662681c59991.tex new file mode 100644 index 00000000..d588b086 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryhireg_bits830f40aea8b421a1ac74662681c59991.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryHiReg_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryHiReg_chunk_0 = update_subrange_bits(r.TLBEntryHiReg_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryhireg_clgkf7b384835e909bb74e4373c5c929ab4a.tex b/sail_latex_mips/fnz_set_tlbentryhireg_clgkf7b384835e909bb74e4373c5c929ab4a.tex new file mode 100644 index 00000000..fbe93b62 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryhireg_clgkf7b384835e909bb74e4373c5c929ab4a.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryHiReg_CLGK (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryHiReg_chunk_0 = update_subrange_bits(r.TLBEntryHiReg_chunk_0, 61, 61, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryhireg_clgse8c691628327ecea822d37b3003caf39.tex b/sail_latex_mips/fnz_set_tlbentryhireg_clgse8c691628327ecea822d37b3003caf39.tex new file mode 100644 index 00000000..5fe50210 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryhireg_clgse8c691628327ecea822d37b3003caf39.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryHiReg_CLGS (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryHiReg_chunk_0 = update_subrange_bits(r.TLBEntryHiReg_chunk_0, 60, 60, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryhireg_clgua9dab1e5d85bccd1023c42cf9f9bc70a.tex b/sail_latex_mips/fnz_set_tlbentryhireg_clgua9dab1e5d85bccd1023c42cf9f9bc70a.tex new file mode 100644 index 00000000..c3268e72 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryhireg_clgua9dab1e5d85bccd1023c42cf9f9bc70a.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryHiReg_CLGU (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryHiReg_chunk_0 = update_subrange_bits(r.TLBEntryHiReg_chunk_0, 59, 59, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryhireg_rdbcd78e9049138ceacd56be71478b061.tex b/sail_latex_mips/fnz_set_tlbentryhireg_rdbcd78e9049138ceacd56be71478b061.tex new file mode 100644 index 00000000..a3e99313 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryhireg_rdbcd78e9049138ceacd56be71478b061.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryHiReg_R (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryHiReg_chunk_0 = update_subrange_bits(r.TLBEntryHiReg_chunk_0, 63, 62, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryhireg_vpn2ea6ff2e6ee98b0eaf79e756b606dd7f7.tex b/sail_latex_mips/fnz_set_tlbentryhireg_vpn2ea6ff2e6ee98b0eaf79e756b606dd7f7.tex new file mode 100644 index 00000000..634ecc43 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryhireg_vpn2ea6ff2e6ee98b0eaf79e756b606dd7f7.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryHiReg_VPN2 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryHiReg_chunk_0 = update_subrange_bits(r.TLBEntryHiReg_chunk_0, 39, 13, subrange_bits(v, 26, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryloreg_bits87cab4acff2760983bfddd23367d445c.tex b/sail_latex_mips/fnz_set_tlbentryloreg_bits87cab4acff2760983bfddd23367d445c.tex new file mode 100644 index 00000000..dad4eceb --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryloreg_bits87cab4acff2760983bfddd23367d445c.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryLoReg_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryLoReg_chunk_0 = update_subrange_bits(r.TLBEntryLoReg_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryloreg_c08e3096dbb8171c7d2a2c6b6c853e622.tex b/sail_latex_mips/fnz_set_tlbentryloreg_c08e3096dbb8171c7d2a2c6b6c853e622.tex new file mode 100644 index 00000000..25690a91 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryloreg_c08e3096dbb8171c7d2a2c6b6c853e622.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryLoReg_C (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryLoReg_chunk_0 = update_subrange_bits(r.TLBEntryLoReg_chunk_0, 5, 3, subrange_bits(v, 2, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryloreg_capl4afafd253b55dd9505958742ee8cb6f7.tex b/sail_latex_mips/fnz_set_tlbentryloreg_capl4afafd253b55dd9505958742ee8cb6f7.tex new file mode 100644 index 00000000..2c7dedbf --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryloreg_capl4afafd253b55dd9505958742ee8cb6f7.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryLoReg_CapL (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryLoReg_chunk_0 = update_subrange_bits(r.TLBEntryLoReg_chunk_0, 62, 62, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryloreg_caplg3dd41e627a6f13d73dc55778a444e440.tex b/sail_latex_mips/fnz_set_tlbentryloreg_caplg3dd41e627a6f13d73dc55778a444e440.tex new file mode 100644 index 00000000..a5a58d4b --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryloreg_caplg3dd41e627a6f13d73dc55778a444e440.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryLoReg_CapLG (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryLoReg_chunk_0 = update_subrange_bits(r.TLBEntryLoReg_chunk_0, 61, 61, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryloreg_caps9a042f9111a8f78fcfe31c8c94e92925.tex b/sail_latex_mips/fnz_set_tlbentryloreg_caps9a042f9111a8f78fcfe31c8c94e92925.tex new file mode 100644 index 00000000..a5d39bb8 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryloreg_caps9a042f9111a8f78fcfe31c8c94e92925.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryLoReg_CapS (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryLoReg_chunk_0 = update_subrange_bits(r.TLBEntryLoReg_chunk_0, 63, 63, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryloreg_d04572c2344c6e87906ebf8c78d44671a.tex b/sail_latex_mips/fnz_set_tlbentryloreg_d04572c2344c6e87906ebf8c78d44671a.tex new file mode 100644 index 00000000..fe838470 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryloreg_d04572c2344c6e87906ebf8c78d44671a.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryLoReg_D (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryLoReg_chunk_0 = update_subrange_bits(r.TLBEntryLoReg_chunk_0, 2, 2, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryloreg_g81ecbc57653a1477c15cea1541c708f3.tex b/sail_latex_mips/fnz_set_tlbentryloreg_g81ecbc57653a1477c15cea1541c708f3.tex new file mode 100644 index 00000000..2e9790b6 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryloreg_g81ecbc57653a1477c15cea1541c708f3.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryLoReg_G (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryLoReg_chunk_0 = update_subrange_bits(r.TLBEntryLoReg_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryloreg_pfn6136b1f7a14537cfb91196ba247d881e.tex b/sail_latex_mips/fnz_set_tlbentryloreg_pfn6136b1f7a14537cfb91196ba247d881e.tex new file mode 100644 index 00000000..7e14c6d7 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryloreg_pfn6136b1f7a14537cfb91196ba247d881e.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryLoReg_PFN (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryLoReg_chunk_0 = update_subrange_bits(r.TLBEntryLoReg_chunk_0, 29, 6, subrange_bits(v, 23, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_tlbentryloreg_v479a48bad10c13e1834cb43c00f02400.tex b/sail_latex_mips/fnz_set_tlbentryloreg_v479a48bad10c13e1834cb43c00f02400.tex new file mode 100644 index 00000000..62dd7dc8 --- /dev/null +++ b/sail_latex_mips/fnz_set_tlbentryloreg_v479a48bad10c13e1834cb43c00f02400.tex @@ -0,0 +1,5 @@ +function _set_TLBEntryLoReg_V (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.TLBEntryLoReg_chunk_0 = update_subrange_bits(r.TLBEntryLoReg_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_xcontextreg_bitsa93b9f55af87e5c9507e10f4f90444f6.tex b/sail_latex_mips/fnz_set_xcontextreg_bitsa93b9f55af87e5c9507e10f4f90444f6.tex new file mode 100644 index 00000000..661394c8 --- /dev/null +++ b/sail_latex_mips/fnz_set_xcontextreg_bitsa93b9f55af87e5c9507e10f4f90444f6.tex @@ -0,0 +1,5 @@ +function _set_XContextReg_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.XContextReg_chunk_0 = update_subrange_bits(r.XContextReg_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_xcontextreg_xbadvpn2b3e73a92b43f1a839bc59b518dda6dc3.tex b/sail_latex_mips/fnz_set_xcontextreg_xbadvpn2b3e73a92b43f1a839bc59b518dda6dc3.tex new file mode 100644 index 00000000..198d17be --- /dev/null +++ b/sail_latex_mips/fnz_set_xcontextreg_xbadvpn2b3e73a92b43f1a839bc59b518dda6dc3.tex @@ -0,0 +1,5 @@ +function _set_XContextReg_XBadVPN2 (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.XContextReg_chunk_0 = update_subrange_bits(r.XContextReg_chunk_0, 30, 4, subrange_bits(v, 26, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_xcontextreg_xptebase1de10092cc0e6fbd31d9a47e20069af7.tex b/sail_latex_mips/fnz_set_xcontextreg_xptebase1de10092cc0e6fbd31d9a47e20069af7.tex new file mode 100644 index 00000000..8d31ea00 --- /dev/null +++ b/sail_latex_mips/fnz_set_xcontextreg_xptebase1de10092cc0e6fbd31d9a47e20069af7.tex @@ -0,0 +1,5 @@ +function _set_XContextReg_XPTEBase (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.XContextReg_chunk_0 = update_subrange_bits(r.XContextReg_chunk_0, 63, 33, subrange_bits(v, 30, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_set_xcontextreg_xr0085c3da7716883767dbf111c432fb50.tex b/sail_latex_mips/fnz_set_xcontextreg_xr0085c3da7716883767dbf111c432fb50.tex new file mode 100644 index 00000000..11014429 --- /dev/null +++ b/sail_latex_mips/fnz_set_xcontextreg_xr0085c3da7716883767dbf111c432fb50.tex @@ -0,0 +1,5 @@ +function _set_XContextReg_XR (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.XContextReg_chunk_0 = update_subrange_bits(r.XContextReg_chunk_0, 32, 31, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_mips/fnz_update_capcausereg_bitsc7253ec47586740f3fd1b2b2e8cdca5a.tex b/sail_latex_mips/fnz_update_capcausereg_bitsc7253ec47586740f3fd1b2b2e8cdca5a.tex new file mode 100644 index 00000000..53fe92eb --- /dev/null +++ b/sail_latex_mips/fnz_update_capcausereg_bitsc7253ec47586740f3fd1b2b2e8cdca5a.tex @@ -0,0 +1,2 @@ +function _update_CapCauseReg_bits (v, x) = let v = { v with CapCauseReg_chunk_0 = update_subrange_bits(v.CapCauseReg_chunk_0, 15, 0, subrange_bits(x, 15, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_capcausereg_exccode831973db379fbc7fc58a62fad27d1e48.tex b/sail_latex_mips/fnz_update_capcausereg_exccode831973db379fbc7fc58a62fad27d1e48.tex new file mode 100644 index 00000000..b4ea47a8 --- /dev/null +++ b/sail_latex_mips/fnz_update_capcausereg_exccode831973db379fbc7fc58a62fad27d1e48.tex @@ -0,0 +1,2 @@ +function _update_CapCauseReg_ExcCode (v, x) = let v = { v with CapCauseReg_chunk_0 = update_subrange_bits(v.CapCauseReg_chunk_0, 15, 8, subrange_bits(x, 7, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_capcausereg_regnumdfccaf21a7f843566ceea99a5e20969b.tex b/sail_latex_mips/fnz_update_capcausereg_regnumdfccaf21a7f843566ceea99a5e20969b.tex new file mode 100644 index 00000000..f2732850 --- /dev/null +++ b/sail_latex_mips/fnz_update_capcausereg_regnumdfccaf21a7f843566ceea99a5e20969b.tex @@ -0,0 +1,2 @@ +function _update_CapCauseReg_RegNum (v, x) = let v = { v with CapCauseReg_chunk_0 = update_subrange_bits(v.CapCauseReg_chunk_0, 7, 0, subrange_bits(x, 7, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_causereg_bd1341a4dd118508995044054898160c72.tex b/sail_latex_mips/fnz_update_causereg_bd1341a4dd118508995044054898160c72.tex new file mode 100644 index 00000000..ea52c633 --- /dev/null +++ b/sail_latex_mips/fnz_update_causereg_bd1341a4dd118508995044054898160c72.tex @@ -0,0 +1,2 @@ +function _update_CauseReg_BD (v, x) = let v = { v with CauseReg_chunk_0 = update_subrange_bits(v.CauseReg_chunk_0, 31, 31, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_causereg_bitsb063e035edb33b2c5f07e3df533bf948.tex b/sail_latex_mips/fnz_update_causereg_bitsb063e035edb33b2c5f07e3df533bf948.tex new file mode 100644 index 00000000..31a503a9 --- /dev/null +++ b/sail_latex_mips/fnz_update_causereg_bitsb063e035edb33b2c5f07e3df533bf948.tex @@ -0,0 +1,2 @@ +function _update_CauseReg_bits (v, x) = let v = { v with CauseReg_chunk_0 = update_subrange_bits(v.CauseReg_chunk_0, 31, 0, subrange_bits(x, 31, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_causereg_ce99326d83612c25800d2accb6a9f4508b.tex b/sail_latex_mips/fnz_update_causereg_ce99326d83612c25800d2accb6a9f4508b.tex new file mode 100644 index 00000000..1919bbc2 --- /dev/null +++ b/sail_latex_mips/fnz_update_causereg_ce99326d83612c25800d2accb6a9f4508b.tex @@ -0,0 +1,2 @@ +function _update_CauseReg_CE (v, x) = let v = { v with CauseReg_chunk_0 = update_subrange_bits(v.CauseReg_chunk_0, 29, 28, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_causereg_exccodeead7d2a9d8ec53cba96f7218e48b092f.tex b/sail_latex_mips/fnz_update_causereg_exccodeead7d2a9d8ec53cba96f7218e48b092f.tex new file mode 100644 index 00000000..8573c925 --- /dev/null +++ b/sail_latex_mips/fnz_update_causereg_exccodeead7d2a9d8ec53cba96f7218e48b092f.tex @@ -0,0 +1,2 @@ +function _update_CauseReg_ExcCode (v, x) = let v = { v with CauseReg_chunk_0 = update_subrange_bits(v.CauseReg_chunk_0, 6, 2, subrange_bits(x, 4, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_causereg_ipa7f214043fd244817e8d07b9783a4f4a.tex b/sail_latex_mips/fnz_update_causereg_ipa7f214043fd244817e8d07b9783a4f4a.tex new file mode 100644 index 00000000..68d6f094 --- /dev/null +++ b/sail_latex_mips/fnz_update_causereg_ipa7f214043fd244817e8d07b9783a4f4a.tex @@ -0,0 +1,2 @@ +function _update_CauseReg_IP (v, x) = let v = { v with CauseReg_chunk_0 = update_subrange_bits(v.CauseReg_chunk_0, 15, 8, subrange_bits(x, 7, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_causereg_iv2946c68395a7cdb8aa45a8668627e8d5.tex b/sail_latex_mips/fnz_update_causereg_iv2946c68395a7cdb8aa45a8668627e8d5.tex new file mode 100644 index 00000000..af98e5ea --- /dev/null +++ b/sail_latex_mips/fnz_update_causereg_iv2946c68395a7cdb8aa45a8668627e8d5.tex @@ -0,0 +1,2 @@ +function _update_CauseReg_IV (v, x) = let v = { v with CauseReg_chunk_0 = update_subrange_bits(v.CauseReg_chunk_0, 23, 23, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_causereg_wpd6c4c462af40f65a59a3ad83cf90ff81.tex b/sail_latex_mips/fnz_update_causereg_wpd6c4c462af40f65a59a3ad83cf90ff81.tex new file mode 100644 index 00000000..9e1079ab --- /dev/null +++ b/sail_latex_mips/fnz_update_causereg_wpd6c4c462af40f65a59a3ad83cf90ff81.tex @@ -0,0 +1,2 @@ +function _update_CauseReg_WP (v, x) = let v = { v with CauseReg_chunk_0 = update_subrange_bits(v.CauseReg_chunk_0, 22, 22, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_contextreg_badvpn29dd1d7ba9698b94e95d082c38f1eab84.tex b/sail_latex_mips/fnz_update_contextreg_badvpn29dd1d7ba9698b94e95d082c38f1eab84.tex new file mode 100644 index 00000000..766190cd --- /dev/null +++ b/sail_latex_mips/fnz_update_contextreg_badvpn29dd1d7ba9698b94e95d082c38f1eab84.tex @@ -0,0 +1,2 @@ +function _update_ContextReg_BadVPN2 (v, x) = let v = { v with ContextReg_chunk_0 = update_subrange_bits(v.ContextReg_chunk_0, 22, 4, subrange_bits(x, 18, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_contextreg_bits0df4e43fe9f13b5860f4e758b65c124c.tex b/sail_latex_mips/fnz_update_contextreg_bits0df4e43fe9f13b5860f4e758b65c124c.tex new file mode 100644 index 00000000..0cf53875 --- /dev/null +++ b/sail_latex_mips/fnz_update_contextreg_bits0df4e43fe9f13b5860f4e758b65c124c.tex @@ -0,0 +1,2 @@ +function _update_ContextReg_bits (v, x) = let v = { v with ContextReg_chunk_0 = update_subrange_bits(v.ContextReg_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_contextreg_ptebase3ac56067efaf9c4426e60d8d4f9e4827.tex b/sail_latex_mips/fnz_update_contextreg_ptebase3ac56067efaf9c4426e60d8d4f9e4827.tex new file mode 100644 index 00000000..20b67cdb --- /dev/null +++ b/sail_latex_mips/fnz_update_contextreg_ptebase3ac56067efaf9c4426e60d8d4f9e4827.tex @@ -0,0 +1,2 @@ +function _update_ContextReg_PTEBase (v, x) = let v = { v with ContextReg_chunk_0 = update_subrange_bits(v.ContextReg_chunk_0, 63, 23, subrange_bits(x, 40, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_statusreg_bevf40892c6f5ac28088b99d5e42005036f.tex b/sail_latex_mips/fnz_update_statusreg_bevf40892c6f5ac28088b99d5e42005036f.tex new file mode 100644 index 00000000..2c7aed39 --- /dev/null +++ b/sail_latex_mips/fnz_update_statusreg_bevf40892c6f5ac28088b99d5e42005036f.tex @@ -0,0 +1,2 @@ +function _update_StatusReg_BEV (v, x) = let v = { v with StatusReg_chunk_0 = update_subrange_bits(v.StatusReg_chunk_0, 22, 22, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_statusreg_bits61d5a9099337276f42cc674faed1b40b.tex b/sail_latex_mips/fnz_update_statusreg_bits61d5a9099337276f42cc674faed1b40b.tex new file mode 100644 index 00000000..a034cd80 --- /dev/null +++ b/sail_latex_mips/fnz_update_statusreg_bits61d5a9099337276f42cc674faed1b40b.tex @@ -0,0 +1,2 @@ +function _update_StatusReg_bits (v, x) = let v = { v with StatusReg_chunk_0 = update_subrange_bits(v.StatusReg_chunk_0, 31, 0, subrange_bits(x, 31, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_statusreg_cud909b281d996784c876e6637f1435066.tex b/sail_latex_mips/fnz_update_statusreg_cud909b281d996784c876e6637f1435066.tex new file mode 100644 index 00000000..36200fcb --- /dev/null +++ b/sail_latex_mips/fnz_update_statusreg_cud909b281d996784c876e6637f1435066.tex @@ -0,0 +1,2 @@ +function _update_StatusReg_CU (v, x) = let v = { v with StatusReg_chunk_0 = update_subrange_bits(v.StatusReg_chunk_0, 31, 28, subrange_bits(x, 3, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_statusreg_erl22b56df06e65c8a9f44b830961367edf.tex b/sail_latex_mips/fnz_update_statusreg_erl22b56df06e65c8a9f44b830961367edf.tex new file mode 100644 index 00000000..ee3cd35f --- /dev/null +++ b/sail_latex_mips/fnz_update_statusreg_erl22b56df06e65c8a9f44b830961367edf.tex @@ -0,0 +1,2 @@ +function _update_StatusReg_ERL (v, x) = let v = { v with StatusReg_chunk_0 = update_subrange_bits(v.StatusReg_chunk_0, 2, 2, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_statusreg_exl680444bbc9dec1a34d9a0cf68ddde857.tex b/sail_latex_mips/fnz_update_statusreg_exl680444bbc9dec1a34d9a0cf68ddde857.tex new file mode 100644 index 00000000..1b40d35f --- /dev/null +++ b/sail_latex_mips/fnz_update_statusreg_exl680444bbc9dec1a34d9a0cf68ddde857.tex @@ -0,0 +1,2 @@ +function _update_StatusReg_EXL (v, x) = let v = { v with StatusReg_chunk_0 = update_subrange_bits(v.StatusReg_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_statusreg_ie8d238c97ac1693bad8b62c61215ea16b.tex b/sail_latex_mips/fnz_update_statusreg_ie8d238c97ac1693bad8b62c61215ea16b.tex new file mode 100644 index 00000000..16310678 --- /dev/null +++ b/sail_latex_mips/fnz_update_statusreg_ie8d238c97ac1693bad8b62c61215ea16b.tex @@ -0,0 +1,2 @@ +function _update_StatusReg_IE (v, x) = let v = { v with StatusReg_chunk_0 = update_subrange_bits(v.StatusReg_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_statusreg_im62a68e4b88599a5038c9e71290e24f71.tex b/sail_latex_mips/fnz_update_statusreg_im62a68e4b88599a5038c9e71290e24f71.tex new file mode 100644 index 00000000..90341f8e --- /dev/null +++ b/sail_latex_mips/fnz_update_statusreg_im62a68e4b88599a5038c9e71290e24f71.tex @@ -0,0 +1,2 @@ +function _update_StatusReg_IM (v, x) = let v = { v with StatusReg_chunk_0 = update_subrange_bits(v.StatusReg_chunk_0, 15, 8, subrange_bits(x, 7, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_statusreg_ksu27debd025189cf0d6d72638cd289acac.tex b/sail_latex_mips/fnz_update_statusreg_ksu27debd025189cf0d6d72638cd289acac.tex new file mode 100644 index 00000000..39b9532e --- /dev/null +++ b/sail_latex_mips/fnz_update_statusreg_ksu27debd025189cf0d6d72638cd289acac.tex @@ -0,0 +1,2 @@ +function _update_StatusReg_KSU (v, x) = let v = { v with StatusReg_chunk_0 = update_subrange_bits(v.StatusReg_chunk_0, 4, 3, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_statusreg_kx6234e7159a5ec0749a63e66e635b26d6.tex b/sail_latex_mips/fnz_update_statusreg_kx6234e7159a5ec0749a63e66e635b26d6.tex new file mode 100644 index 00000000..1baef0aa --- /dev/null +++ b/sail_latex_mips/fnz_update_statusreg_kx6234e7159a5ec0749a63e66e635b26d6.tex @@ -0,0 +1,2 @@ +function _update_StatusReg_KX (v, x) = let v = { v with StatusReg_chunk_0 = update_subrange_bits(v.StatusReg_chunk_0, 7, 7, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_statusreg_sx78cadd5bf0c1cae59c3b60a27b83c481.tex b/sail_latex_mips/fnz_update_statusreg_sx78cadd5bf0c1cae59c3b60a27b83c481.tex new file mode 100644 index 00000000..c8734953 --- /dev/null +++ b/sail_latex_mips/fnz_update_statusreg_sx78cadd5bf0c1cae59c3b60a27b83c481.tex @@ -0,0 +1,2 @@ +function _update_StatusReg_SX (v, x) = let v = { v with StatusReg_chunk_0 = update_subrange_bits(v.StatusReg_chunk_0, 6, 6, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_statusreg_ux17bbf86e5756c6d01048f3d473eb1430.tex b/sail_latex_mips/fnz_update_statusreg_ux17bbf86e5756c6d01048f3d473eb1430.tex new file mode 100644 index 00000000..fb4c1979 --- /dev/null +++ b/sail_latex_mips/fnz_update_statusreg_ux17bbf86e5756c6d01048f3d473eb1430.tex @@ -0,0 +1,2 @@ +function _update_StatusReg_UX (v, x) = let v = { v with StatusReg_chunk_0 = update_subrange_bits(v.StatusReg_chunk_0, 5, 5, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_asidb6b5d414b15c08829bdf389448396971.tex b/sail_latex_mips/fnz_update_tlbentry_asidb6b5d414b15c08829bdf389448396971.tex new file mode 100644 index 00000000..322e5295 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_asidb6b5d414b15c08829bdf389448396971.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_asid (v, x) = let v = { v with TLBEntry_chunk_1 = update_subrange_bits(v.TLBEntry_chunk_1, 9, 2, subrange_bits(x, 7, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_bits1b789098a048790468b840f08f48d3fd.tex b/sail_latex_mips/fnz_update_tlbentry_bits1b789098a048790468b840f08f48d3fd.tex new file mode 100644 index 00000000..07993430 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_bits1b789098a048790468b840f08f48d3fd.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_bits (v, x) = let v = { v with TLBEntry_chunk_1 = update_subrange_bits(v.TLBEntry_chunk_1, 54, 0, subrange_bits(x, 118, 64)) } in + let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in v diff --git a/sail_latex_mips/fnz_update_tlbentry_c0fd743ae9faadd346132a35189c2cd342.tex b/sail_latex_mips/fnz_update_tlbentry_c0fd743ae9faadd346132a35189c2cd342.tex new file mode 100644 index 00000000..b3cd497c --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_c0fd743ae9faadd346132a35189c2cd342.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_c0 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 4, 2, subrange_bits(x, 2, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_c1cecd7e476eb8d0b72ce187ac166f9443.tex b/sail_latex_mips/fnz_update_tlbentry_c1cecd7e476eb8d0b72ce187ac166f9443.tex new file mode 100644 index 00000000..3815ea11 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_c1cecd7e476eb8d0b72ce187ac166f9443.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_c1 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 36, 34, subrange_bits(x, 2, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_capl074805e4eecd0f55c383efab32c765007.tex b/sail_latex_mips/fnz_update_tlbentry_capl074805e4eecd0f55c383efab32c765007.tex new file mode 100644 index 00000000..e85ff93c --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_capl074805e4eecd0f55c383efab32c765007.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_capl0 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 29, 29, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_capl1c69e2b6d6e2466af2769ae5f3b3a70cc.tex b/sail_latex_mips/fnz_update_tlbentry_capl1c69e2b6d6e2466af2769ae5f3b3a70cc.tex new file mode 100644 index 00000000..f21f69f9 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_capl1c69e2b6d6e2466af2769ae5f3b3a70cc.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_capl1 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 61, 61, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_caplg0fc35336b4b0b170579cd74d3e9641075.tex b/sail_latex_mips/fnz_update_tlbentry_caplg0fc35336b4b0b170579cd74d3e9641075.tex new file mode 100644 index 00000000..c4b9b5e6 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_caplg0fc35336b4b0b170579cd74d3e9641075.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_caplg0 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 31, 31, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_caplg14ef4abe6e9dfaa69cfd379930a53acda.tex b/sail_latex_mips/fnz_update_tlbentry_caplg14ef4abe6e9dfaa69cfd379930a53acda.tex new file mode 100644 index 00000000..195920b2 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_caplg14ef4abe6e9dfaa69cfd379930a53acda.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_caplg1 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 63, 63, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_caps0a1dc65eb853d421759956887a045ad45.tex b/sail_latex_mips/fnz_update_tlbentry_caps0a1dc65eb853d421759956887a045ad45.tex new file mode 100644 index 00000000..a5a6e304 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_caps0a1dc65eb853d421759956887a045ad45.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_caps0 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 30, 30, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_caps1c9648031a984830f7ce96fdd1e079e8a.tex b/sail_latex_mips/fnz_update_tlbentry_caps1c9648031a984830f7ce96fdd1e079e8a.tex new file mode 100644 index 00000000..134896f8 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_caps1c9648031a984830f7ce96fdd1e079e8a.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_caps1 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 62, 62, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_d0e93ed2ed33cbc5c5f202914a237de360.tex b/sail_latex_mips/fnz_update_tlbentry_d0e93ed2ed33cbc5c5f202914a237de360.tex new file mode 100644 index 00000000..6c131ddf --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_d0e93ed2ed33cbc5c5f202914a237de360.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_d0 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_d101453a2a5999d48250bdc176e05e3f5e.tex b/sail_latex_mips/fnz_update_tlbentry_d101453a2a5999d48250bdc176e05e3f5e.tex new file mode 100644 index 00000000..53985a09 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_d101453a2a5999d48250bdc176e05e3f5e.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_d1 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 33, 33, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_g20222955c3b959c9ff4647404fedbfef.tex b/sail_latex_mips/fnz_update_tlbentry_g20222955c3b959c9ff4647404fedbfef.tex new file mode 100644 index 00000000..d8656239 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_g20222955c3b959c9ff4647404fedbfef.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_g (v, x) = let v = { v with TLBEntry_chunk_1 = update_subrange_bits(v.TLBEntry_chunk_1, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_pagemaskbb0f8a2bdd38e987c7a2e2b338e3b75f.tex b/sail_latex_mips/fnz_update_tlbentry_pagemaskbb0f8a2bdd38e987c7a2e2b338e3b75f.tex new file mode 100644 index 00000000..d6a8032a --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_pagemaskbb0f8a2bdd38e987c7a2e2b338e3b75f.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_pagemask (v, x) = let v = { v with TLBEntry_chunk_1 = update_subrange_bits(v.TLBEntry_chunk_1, 54, 39, subrange_bits(x, 15, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_pfn0d99c89c789d61112a1918a4433ab048d.tex b/sail_latex_mips/fnz_update_tlbentry_pfn0d99c89c789d61112a1918a4433ab048d.tex new file mode 100644 index 00000000..d0e337eb --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_pfn0d99c89c789d61112a1918a4433ab048d.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_pfn0 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 28, 5, subrange_bits(x, 23, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_pfn190b25e06aacd9ec8fd6e571532937e98.tex b/sail_latex_mips/fnz_update_tlbentry_pfn190b25e06aacd9ec8fd6e571532937e98.tex new file mode 100644 index 00000000..7910ec50 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_pfn190b25e06aacd9ec8fd6e571532937e98.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_pfn1 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 60, 37, subrange_bits(x, 23, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_r9a41b411e6ff9bebfc4172a28c5dbdee.tex b/sail_latex_mips/fnz_update_tlbentry_r9a41b411e6ff9bebfc4172a28c5dbdee.tex new file mode 100644 index 00000000..156b316c --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_r9a41b411e6ff9bebfc4172a28c5dbdee.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_r (v, x) = let v = { v with TLBEntry_chunk_1 = update_subrange_bits(v.TLBEntry_chunk_1, 38, 37, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_v042084d06370a232031d509c4cb3b4ff6.tex b/sail_latex_mips/fnz_update_tlbentry_v042084d06370a232031d509c4cb3b4ff6.tex new file mode 100644 index 00000000..029a3322 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_v042084d06370a232031d509c4cb3b4ff6.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_v0 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_v163c9fd3074a5ad5e092a27e64a5fb55e.tex b/sail_latex_mips/fnz_update_tlbentry_v163c9fd3074a5ad5e092a27e64a5fb55e.tex new file mode 100644 index 00000000..ec65c913 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_v163c9fd3074a5ad5e092a27e64a5fb55e.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_v1 (v, x) = let v = { v with TLBEntry_chunk_0 = update_subrange_bits(v.TLBEntry_chunk_0, 32, 32, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_valid7dd0569211421c835b46068a7bd34a5a.tex b/sail_latex_mips/fnz_update_tlbentry_valid7dd0569211421c835b46068a7bd34a5a.tex new file mode 100644 index 00000000..1d58f548 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_valid7dd0569211421c835b46068a7bd34a5a.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_valid (v, x) = let v = { v with TLBEntry_chunk_1 = update_subrange_bits(v.TLBEntry_chunk_1, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentry_vpn24c1efd2008ce4086cb554186508bd63a.tex b/sail_latex_mips/fnz_update_tlbentry_vpn24c1efd2008ce4086cb554186508bd63a.tex new file mode 100644 index 00000000..89c38b86 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentry_vpn24c1efd2008ce4086cb554186508bd63a.tex @@ -0,0 +1,2 @@ +function _update_TLBEntry_vpn2 (v, x) = let v = { v with TLBEntry_chunk_1 = update_subrange_bits(v.TLBEntry_chunk_1, 36, 10, subrange_bits(x, 26, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryhireg_asidb7a77785e726aa2fce0d7e93a9630b8d.tex b/sail_latex_mips/fnz_update_tlbentryhireg_asidb7a77785e726aa2fce0d7e93a9630b8d.tex new file mode 100644 index 00000000..d2ecd477 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryhireg_asidb7a77785e726aa2fce0d7e93a9630b8d.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryHiReg_ASID (v, x) = let v = { v with TLBEntryHiReg_chunk_0 = update_subrange_bits(v.TLBEntryHiReg_chunk_0, 7, 0, subrange_bits(x, 7, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryhireg_bitsa10c10b31a1704b4bbb65828e235738a.tex b/sail_latex_mips/fnz_update_tlbentryhireg_bitsa10c10b31a1704b4bbb65828e235738a.tex new file mode 100644 index 00000000..d98e1dab --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryhireg_bitsa10c10b31a1704b4bbb65828e235738a.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryHiReg_bits (v, x) = let v = { v with TLBEntryHiReg_chunk_0 = update_subrange_bits(v.TLBEntryHiReg_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryhireg_clgk635276a161c10c3ac2a0c446f734a32a.tex b/sail_latex_mips/fnz_update_tlbentryhireg_clgk635276a161c10c3ac2a0c446f734a32a.tex new file mode 100644 index 00000000..2ae83e19 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryhireg_clgk635276a161c10c3ac2a0c446f734a32a.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryHiReg_CLGK (v, x) = let v = { v with TLBEntryHiReg_chunk_0 = update_subrange_bits(v.TLBEntryHiReg_chunk_0, 61, 61, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryhireg_clgs2a321d8cde93a407a0a48e78b11f8b02.tex b/sail_latex_mips/fnz_update_tlbentryhireg_clgs2a321d8cde93a407a0a48e78b11f8b02.tex new file mode 100644 index 00000000..24a75b1c --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryhireg_clgs2a321d8cde93a407a0a48e78b11f8b02.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryHiReg_CLGS (v, x) = let v = { v with TLBEntryHiReg_chunk_0 = update_subrange_bits(v.TLBEntryHiReg_chunk_0, 60, 60, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryhireg_clgub94d1691569cf6e49d6171ef49e4c86b.tex b/sail_latex_mips/fnz_update_tlbentryhireg_clgub94d1691569cf6e49d6171ef49e4c86b.tex new file mode 100644 index 00000000..8ba8a0c5 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryhireg_clgub94d1691569cf6e49d6171ef49e4c86b.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryHiReg_CLGU (v, x) = let v = { v with TLBEntryHiReg_chunk_0 = update_subrange_bits(v.TLBEntryHiReg_chunk_0, 59, 59, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryhireg_r06c8b0ecb6f68f0d45d384366fd03e59.tex b/sail_latex_mips/fnz_update_tlbentryhireg_r06c8b0ecb6f68f0d45d384366fd03e59.tex new file mode 100644 index 00000000..0d60c888 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryhireg_r06c8b0ecb6f68f0d45d384366fd03e59.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryHiReg_R (v, x) = let v = { v with TLBEntryHiReg_chunk_0 = update_subrange_bits(v.TLBEntryHiReg_chunk_0, 63, 62, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryhireg_vpn2a5a0eafdc27da5a10c42b69c9f6e759f.tex b/sail_latex_mips/fnz_update_tlbentryhireg_vpn2a5a0eafdc27da5a10c42b69c9f6e759f.tex new file mode 100644 index 00000000..d1185be3 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryhireg_vpn2a5a0eafdc27da5a10c42b69c9f6e759f.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryHiReg_VPN2 (v, x) = let v = { v with TLBEntryHiReg_chunk_0 = update_subrange_bits(v.TLBEntryHiReg_chunk_0, 39, 13, subrange_bits(x, 26, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryloreg_bits6c2ff3e7af20e35dd45bf50ea68f8ec8.tex b/sail_latex_mips/fnz_update_tlbentryloreg_bits6c2ff3e7af20e35dd45bf50ea68f8ec8.tex new file mode 100644 index 00000000..887c1798 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryloreg_bits6c2ff3e7af20e35dd45bf50ea68f8ec8.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryLoReg_bits (v, x) = let v = { v with TLBEntryLoReg_chunk_0 = update_subrange_bits(v.TLBEntryLoReg_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryloreg_c720c1b6d680bdb0fc873d902ab9e3854.tex b/sail_latex_mips/fnz_update_tlbentryloreg_c720c1b6d680bdb0fc873d902ab9e3854.tex new file mode 100644 index 00000000..5148d29d --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryloreg_c720c1b6d680bdb0fc873d902ab9e3854.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryLoReg_C (v, x) = let v = { v with TLBEntryLoReg_chunk_0 = update_subrange_bits(v.TLBEntryLoReg_chunk_0, 5, 3, subrange_bits(x, 2, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryloreg_caplaaf9a58642f1ed8b0226e13fd635715e.tex b/sail_latex_mips/fnz_update_tlbentryloreg_caplaaf9a58642f1ed8b0226e13fd635715e.tex new file mode 100644 index 00000000..2f105eee --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryloreg_caplaaf9a58642f1ed8b0226e13fd635715e.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryLoReg_CapL (v, x) = let v = { v with TLBEntryLoReg_chunk_0 = update_subrange_bits(v.TLBEntryLoReg_chunk_0, 62, 62, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryloreg_caplg74d3e13531d835cb013f9516a2c860b5.tex b/sail_latex_mips/fnz_update_tlbentryloreg_caplg74d3e13531d835cb013f9516a2c860b5.tex new file mode 100644 index 00000000..9fca2b27 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryloreg_caplg74d3e13531d835cb013f9516a2c860b5.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryLoReg_CapLG (v, x) = let v = { v with TLBEntryLoReg_chunk_0 = update_subrange_bits(v.TLBEntryLoReg_chunk_0, 61, 61, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryloreg_caps3f8fe0c48d5361758dc7ef0fa4a84990.tex b/sail_latex_mips/fnz_update_tlbentryloreg_caps3f8fe0c48d5361758dc7ef0fa4a84990.tex new file mode 100644 index 00000000..a5cd6737 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryloreg_caps3f8fe0c48d5361758dc7ef0fa4a84990.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryLoReg_CapS (v, x) = let v = { v with TLBEntryLoReg_chunk_0 = update_subrange_bits(v.TLBEntryLoReg_chunk_0, 63, 63, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryloreg_ddadb2d338250cae60e5c96dc8dc2f118.tex b/sail_latex_mips/fnz_update_tlbentryloreg_ddadb2d338250cae60e5c96dc8dc2f118.tex new file mode 100644 index 00000000..2ba7228d --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryloreg_ddadb2d338250cae60e5c96dc8dc2f118.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryLoReg_D (v, x) = let v = { v with TLBEntryLoReg_chunk_0 = update_subrange_bits(v.TLBEntryLoReg_chunk_0, 2, 2, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryloreg_gcbb777750a024300d463c99664060b0e.tex b/sail_latex_mips/fnz_update_tlbentryloreg_gcbb777750a024300d463c99664060b0e.tex new file mode 100644 index 00000000..96f97995 --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryloreg_gcbb777750a024300d463c99664060b0e.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryLoReg_G (v, x) = let v = { v with TLBEntryLoReg_chunk_0 = update_subrange_bits(v.TLBEntryLoReg_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryloreg_pfn09564a0f7205bf65c965dda38fd2c7b1.tex b/sail_latex_mips/fnz_update_tlbentryloreg_pfn09564a0f7205bf65c965dda38fd2c7b1.tex new file mode 100644 index 00000000..3e0a604b --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryloreg_pfn09564a0f7205bf65c965dda38fd2c7b1.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryLoReg_PFN (v, x) = let v = { v with TLBEntryLoReg_chunk_0 = update_subrange_bits(v.TLBEntryLoReg_chunk_0, 29, 6, subrange_bits(x, 23, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_tlbentryloreg_v464571bc28acefba62b6c96884a2ac5e.tex b/sail_latex_mips/fnz_update_tlbentryloreg_v464571bc28acefba62b6c96884a2ac5e.tex new file mode 100644 index 00000000..24320a6b --- /dev/null +++ b/sail_latex_mips/fnz_update_tlbentryloreg_v464571bc28acefba62b6c96884a2ac5e.tex @@ -0,0 +1,2 @@ +function _update_TLBEntryLoReg_V (v, x) = let v = { v with TLBEntryLoReg_chunk_0 = update_subrange_bits(v.TLBEntryLoReg_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_xcontextreg_bitsdb6e2157fa47608aa5622abf4b763efc.tex b/sail_latex_mips/fnz_update_xcontextreg_bitsdb6e2157fa47608aa5622abf4b763efc.tex new file mode 100644 index 00000000..eac599fc --- /dev/null +++ b/sail_latex_mips/fnz_update_xcontextreg_bitsdb6e2157fa47608aa5622abf4b763efc.tex @@ -0,0 +1,2 @@ +function _update_XContextReg_bits (v, x) = let v = { v with XContextReg_chunk_0 = update_subrange_bits(v.XContextReg_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_xcontextreg_xbadvpn271be6846d4092b3dba3bc6c81857b1b9.tex b/sail_latex_mips/fnz_update_xcontextreg_xbadvpn271be6846d4092b3dba3bc6c81857b1b9.tex new file mode 100644 index 00000000..31184a07 --- /dev/null +++ b/sail_latex_mips/fnz_update_xcontextreg_xbadvpn271be6846d4092b3dba3bc6c81857b1b9.tex @@ -0,0 +1,2 @@ +function _update_XContextReg_XBadVPN2 (v, x) = let v = { v with XContextReg_chunk_0 = update_subrange_bits(v.XContextReg_chunk_0, 30, 4, subrange_bits(x, 26, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_xcontextreg_xptebase729a58cc2ea0bab68cb0c93124af9313.tex b/sail_latex_mips/fnz_update_xcontextreg_xptebase729a58cc2ea0bab68cb0c93124af9313.tex new file mode 100644 index 00000000..d1879ed7 --- /dev/null +++ b/sail_latex_mips/fnz_update_xcontextreg_xptebase729a58cc2ea0bab68cb0c93124af9313.tex @@ -0,0 +1,2 @@ +function _update_XContextReg_XPTEBase (v, x) = let v = { v with XContextReg_chunk_0 = update_subrange_bits(v.XContextReg_chunk_0, 63, 33, subrange_bits(x, 30, 0)) } in + v diff --git a/sail_latex_mips/fnz_update_xcontextreg_xrfb95bbc02275c03eb4bc1562a36f7671.tex b/sail_latex_mips/fnz_update_xcontextreg_xrfb95bbc02275c03eb4bc1562a36f7671.tex new file mode 100644 index 00000000..25665f01 --- /dev/null +++ b/sail_latex_mips/fnz_update_xcontextreg_xrfb95bbc02275c03eb4bc1562a36f7671.tex @@ -0,0 +1,2 @@ +function _update_XContextReg_XR (v, x) = let v = { v with XContextReg_chunk_0 = update_subrange_bits(v.XContextReg_chunk_0, 32, 31, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_mips/fnzaccesslevel_of_num43666996140cb5f36631de9d7d4748b1.tex b/sail_latex_mips/fnzaccesslevel_of_num43666996140cb5f36631de9d7d4748b1.tex new file mode 100644 index 00000000..a8446000 --- /dev/null +++ b/sail_latex_mips/fnzaccesslevel_of_num43666996140cb5f36631de9d7d4748b1.tex @@ -0,0 +1,5 @@ +function AccessLevel_of_num arg# = match arg# { + 0 => User, + 1 => Supervisor, + _ => Kernel +} diff --git a/sail_latex_mips/fnzaddrwrapperbff37cfeb3c9276bfa58f5d99b0ca05e.tex b/sail_latex_mips/fnzaddrwrapperbff37cfeb3c9276bfa58f5d99b0ca05e.tex new file mode 100644 index 00000000..af3e0515 --- /dev/null +++ b/sail_latex_mips/fnzaddrwrapperbff37cfeb3c9276bfa58f5d99b0ca05e.tex @@ -0,0 +1,15 @@ +function #\hyperref[sailMIPSzaddrWrapper]{addrWrapper}#(addr, accessType, width) = + { + let ddc = DDC; + #\hyperref[sailMIPSzcheckDDCPerms]{checkDDCPerms}#(ddc, accessType); + cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(ddc); + vAddr = (cursor + #\hyperref[sailMIPSzunsigned]{unsigned}#(addr)) % #\hyperref[sailMIPSzpow2]{pow2}#(64); + size = #\hyperref[sailMIPSzwordWidthBytes]{wordWidthBytes}#(width); + let (base, top) = #\hyperref[sailMIPSzgetCapBounds]{getCapBounds}#(ddc); + if ((vAddr + size) > top) then + (#\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, 0b00000)) + else if (vAddr < base) then + (#\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, 0b00000)) + else + #\hyperref[sailMIPSztozybits]{to\_bits}#(64, vAddr); + } diff --git a/sail_latex_mips/fnzaddrwrapperunaligned2c4b1b84884abfd7091faab6f7aed047.tex b/sail_latex_mips/fnzaddrwrapperunaligned2c4b1b84884abfd7091faab6f7aed047.tex new file mode 100644 index 00000000..127d18aa --- /dev/null +++ b/sail_latex_mips/fnzaddrwrapperunaligned2c4b1b84884abfd7091faab6f7aed047.tex @@ -0,0 +1,15 @@ +function #\hyperref[sailMIPSzaddrWrapperUnaligned]{addrWrapperUnaligned}#(addr, accessType, width) = + { + let ddc = DDC; + #\hyperref[sailMIPSzcheckDDCPerms]{checkDDCPerms}#(ddc, accessType); + cursor = #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(ddc); + vAddr = (cursor + #\hyperref[sailMIPSzunsigned]{unsigned}#(addr)) % #\hyperref[sailMIPSzpow2]{pow2}#(64); + let (waddr, size) = #\hyperref[sailMIPSzunalignedBytesTouched]{unalignedBytesTouched}#(vAddr, width); + let (base, top) = #\hyperref[sailMIPSzgetCapBounds]{getCapBounds}#(ddc); + if ((waddr + size) > top) then + (#\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, 0b00000)) + else if (waddr < base) then + (#\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_LengthViolation, 0b00000)) + else + (#\hyperref[sailMIPSztozybits]{to\_bits}#(64, waddr), size); + } diff --git a/sail_latex_mips/fnzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex b/sail_latex_mips/fnzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex new file mode 100644 index 00000000..a5eea578 --- /dev/null +++ b/sail_latex_mips/fnzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex @@ -0,0 +1,4 @@ +function bit_to_bool b = match b { + bitone => true, + _ => false +} diff --git a/sail_latex_mips/fnzbits_to_bool40d71a119a1093f6caa36e2aa93bd193.tex b/sail_latex_mips/fnzbits_to_bool40d71a119a1093f6caa36e2aa93bd193.tex new file mode 100644 index 00000000..fdb9bf1c --- /dev/null +++ b/sail_latex_mips/fnzbits_to_bool40d71a119a1093f6caa36e2aa93bd193.tex @@ -0,0 +1 @@ +function bits_to_bool x = #\hyperref[sailMIPSzbitzytozybool]{bit\_to\_bool}#(x[0]) diff --git a/sail_latex_mips/fnzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex b/sail_latex_mips/fnzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex new file mode 100644 index 00000000..d20ce1c9 --- /dev/null +++ b/sail_latex_mips/fnzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex @@ -0,0 +1 @@ +function bool_to_bit x = if x then bitone else bitzero diff --git a/sail_latex_mips/fnzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex b/sail_latex_mips/fnzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex new file mode 100644 index 00000000..99075369 --- /dev/null +++ b/sail_latex_mips/fnzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex @@ -0,0 +1 @@ +function bool_to_bits x = if x then 0b1 else 0b0 diff --git a/sail_latex_mips/fnzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex b/sail_latex_mips/fnzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex new file mode 100644 index 00000000..8839a06d --- /dev/null +++ b/sail_latex_mips/fnzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex @@ -0,0 +1,54 @@ +function #\hyperref[sailMIPSzcapBitsToCapability]{capBitsToCapability}#(t, c) : (bool, CapBits) -> Capability = { + internal_exponent : bool = c[90]; + otype : #\hyperref[sailMIPSzbits]{bits}#(18) = c[108..91]; + let sealed : bool = otype != #\hyperref[sailMIPSzones]{ones}#(); + E : #\hyperref[sailMIPSzbits]{bits}#(6) = #\hyperref[sailMIPSzzzeros]{zeros}#(); + Bs : #\hyperref[sailMIPSzbits]{bits}#(14) = #\hyperref[sailMIPSzzzeros]{zeros}#(); + T : #\hyperref[sailMIPSzbits]{bits}#(12) = #\hyperref[sailMIPSzzzeros]{zeros}#(); + lenMSBs : #\hyperref[sailMIPSzbits]{bits}#(2) = #\hyperref[sailMIPSzzzeros]{zeros}#(); + if internal_exponent then { + /* Exponent stored instead of T[2..0] and B[2..0] */ + E = c[80..78] @ c [66..64]; + /* Exponent chosen so that length MSBs is 01 */ + lenMSBs = 0b01; + T = c[89..81] @ 0b000; + Bs = c[77..67] @ 0b000; + } else { + /* Exponent zero */ + lenMSBs = 0b00; + T = c[89..78]; + Bs = c[77..64]; + }; + /* + Reconstruct top two bits of T given T = B + len and: + 1) the top two bits of B + 2) most significant two bits of length derived from format above + 3) carry out of B[20..0] + len[20..0] that is implied if T[20..0] < B[20..0] + */ + carry_out = if T <_u Bs[11..0] then 0b01 else 0b00; + Ttop2 = Bs[13..12] + lenMSBs + carry_out; + return struct { + tag = t, + uperms = c[127..124], + permit_set_CID = c[123], + access_system_regs = c[122], + permit_unseal = c[121], + permit_ccall = c[120], + permit_seal = c[119], + permit_store_local_cap = c[118], + permit_store_cap = c[117], + permit_load_cap = c[116], + permit_store = c[115], + permit_load = c[114], + permit_execute = c[113], + global = c[112], + reserved = c[111..109], + internal_e = internal_exponent, + E = E, + sealed = sealed, + B = Bs, + T = Ttop2 @ T, + otype = otype, + address = c[63..0] + } +} diff --git a/sail_latex_mips/fnzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex b/sail_latex_mips/fnzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex new file mode 100644 index 00000000..80eff608 --- /dev/null +++ b/sail_latex_mips/fnzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailMIPSzcapBoundsEqual]{capBoundsEqual}# (c1, c2) : (Capability, Capability) -> bool = + let (base1, top1) = #\hyperref[sailMIPSzgetCapBounds]{getCapBounds}#(c1) in + let (base2, top2) = #\hyperref[sailMIPSzgetCapBounds]{getCapBounds}#(c2) in + (base1 == base2) & (top1 == top2) diff --git a/sail_latex_mips/fnzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex b/sail_latex_mips/fnzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex new file mode 100644 index 00000000..2d508372 --- /dev/null +++ b/sail_latex_mips/fnzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex @@ -0,0 +1,27 @@ +function CapEx_of_num arg# = match arg# { + 0 => CapEx_None, + 1 => CapEx_LengthViolation, + 2 => CapEx_TagViolation, + 3 => CapEx_SealViolation, + 4 => CapEx_TypeViolation, + 5 => CapEx_CallTrap, + 6 => CapEx_ReturnTrap, + 7 => CapEx_TSSUnderFlow, + 8 => CapEx_UserDefViolation, + 9 => CapEx_TLBNoStoreCap, + 10 => CapEx_InexactBounds, + 11 => CapEx_GlobalViolation, + 12 => CapEx_PermitExecuteViolation, + 13 => CapEx_PermitLoadViolation, + 14 => CapEx_PermitStoreViolation, + 15 => CapEx_PermitLoadCapViolation, + 16 => CapEx_PermitStoreCapViolation, + 17 => CapEx_PermitStoreLocalCapViolation, + 18 => CapEx_PermitSealViolation, + 19 => CapEx_AccessSystemRegsViolation, + 20 => CapEx_PermitCCallViolation, + 21 => CapEx_AccessCCallIDCViolation, + 22 => CapEx_PermitUnsealViolation, + 23 => CapEx_PermitSetCIDViolation, + _ => CapEx_TLBLoadCap +} diff --git a/sail_latex_mips/fnzcapexcodee065d40e92bb99703db21c8c18bedf11.tex b/sail_latex_mips/fnzcapexcodee065d40e92bb99703db21c8c18bedf11.tex new file mode 100644 index 00000000..ddf431c7 --- /dev/null +++ b/sail_latex_mips/fnzcapexcodee065d40e92bb99703db21c8c18bedf11.tex @@ -0,0 +1,28 @@ +function #\hyperref[sailMIPSzCapExCode]{CapExCode}#(ex) : CapEx -> #\hyperref[sailMIPSzbits]{bits}#(8)= + match ex { + CapEx_None => 0x00, + CapEx_LengthViolation => 0x01, + CapEx_TagViolation => 0x02, + CapEx_SealViolation => 0x03, + CapEx_TypeViolation => 0x04, + CapEx_CallTrap => 0x05, + CapEx_ReturnTrap => 0x06, + CapEx_TSSUnderFlow => 0x07, + CapEx_UserDefViolation => 0x08, + CapEx_TLBNoStoreCap => 0x09, + CapEx_InexactBounds => 0x0a, + CapEx_TLBLoadCap => 0x0c, + CapEx_GlobalViolation => 0x10, + CapEx_PermitExecuteViolation => 0x11, + CapEx_PermitLoadViolation => 0x12, + CapEx_PermitStoreViolation => 0x13, + CapEx_PermitLoadCapViolation => 0x14, + CapEx_PermitStoreCapViolation => 0x15, + CapEx_PermitStoreLocalCapViolation => 0x16, + CapEx_PermitSealViolation => 0x17, + CapEx_AccessSystemRegsViolation => 0x18, + CapEx_PermitCCallViolation => 0x19, + CapEx_AccessCCallIDCViolation => 0x1a, + CapEx_PermitUnsealViolation => 0x1b, + CapEx_PermitSetCIDViolation => 0x1c + } diff --git a/sail_latex_mips/fnzcaptobits025010a6e8c284beecc438f72babcc70.tex b/sail_latex_mips/fnzcaptobits025010a6e8c284beecc438f72babcc70.tex new file mode 100644 index 00000000..849efcdb --- /dev/null +++ b/sail_latex_mips/fnzcaptobits025010a6e8c284beecc438f72babcc70.tex @@ -0,0 +1,21 @@ +function #\hyperref[sailMIPSzcapToBits]{capToBits}#(cap) : Capability -> #\hyperref[sailMIPSzbits]{bits}#(128) = { + t_hi : #\hyperref[sailMIPSzbits]{bits}#(9) = cap.T[11..3]; + t_lo : #\hyperref[sailMIPSzbits]{bits}#(3) = cap.T[2..0]; + b_hi : #\hyperref[sailMIPSzbits]{bits}#(11) = cap.B[13..3]; + b_lo : #\hyperref[sailMIPSzbits]{bits}#(3) = cap.B[2..0]; + if cap.internal_e then { + t_lo = cap.E[5..3]; + b_lo = cap.E[2..0]; + }; + return (cap.uperms + @ #\hyperref[sailMIPSzgetCapHardPerms]{getCapHardPerms}#(cap) + @ cap.reserved + @ cap.otype + @ cap.internal_e + @ t_hi + @ t_lo + @ b_hi + @ b_lo + @ cap.address + ); +} diff --git a/sail_latex_mips/fnzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex b/sail_latex_mips/fnzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex new file mode 100644 index 00000000..962681a1 --- /dev/null +++ b/sail_latex_mips/fnzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailMIPSzcapToMemBits]{capToMemBits}#(cap) : Capability -> #\hyperref[sailMIPSzbits]{bits}#(128) = + #\hyperref[sailMIPSzcapToBits]{capToBits}#(cap) ^ null_cap_bits diff --git a/sail_latex_mips/fnzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex b/sail_latex_mips/fnzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex new file mode 100644 index 00000000..a8886b8f --- /dev/null +++ b/sail_latex_mips/fnzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex @@ -0,0 +1,21 @@ +function #\hyperref[sailMIPSzcapToString]{capToString}# (cap, fixlen) = { + #\hyperref[sailMIPSzskipzyescape]{skip\_escape}#(); /* because cheri128 getCapX functions contain asserts but cheri256 ones do not */ + len = #\hyperref[sailMIPSzgetCapLength]{getCapLength}#(cap); + /* When dumping caps at end of test we cap length at 64 bits for compatibility with test suite, when tracing we print the actual value */ + len_str = if fixlen then #\hyperref[sailMIPSzBitStr]{BitStr}#(#\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzmin]{min}#(len, #\hyperref[sailMIPSzMAX]{MAX}#(64)))) else #\hyperref[sailMIPSzBitStr]{BitStr}#(#\hyperref[sailMIPSztozybits]{to\_bits}#(68, len)); + /* Print architectural type which is -1 for unsealed caps */ + let otype64 : #\hyperref[sailMIPSzbits]{bits}#(64) = if #\hyperref[sailMIPSzhasReservedOType]{hasReservedOType}#(cap) then #\hyperref[sailMIPSzsignzyextend]{sign\_extend}#(cap.otype) else #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(cap.otype); + #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(" t:", + #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(if cap.tag then "1" else "0", + #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(" s:", + #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(if cap.sealed then "1" else "0", + #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(" perms:", + #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(#\hyperref[sailMIPSzBitStr]{BitStr}#(0b0 @ #\hyperref[sailMIPSzgetCapPerms]{getCapPerms}#(cap)), + #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(" type:", + #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(#\hyperref[sailMIPSzBitStr]{BitStr}#(otype64), + #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(" offset:", + #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(#\hyperref[sailMIPSzBitStr]{BitStr}#(#\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzgetCapOffset]{getCapOffset}#(cap))), + #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(" base:", + #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(#\hyperref[sailMIPSzBitStr]{BitStr}#(#\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(cap))), + #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(" length:", len_str))))))))))))) + } diff --git a/sail_latex_mips/fnzcast_unit_vec98272b7fb05a703213e98272ec5486c8.tex b/sail_latex_mips/fnzcast_unit_vec98272b7fb05a703213e98272ec5486c8.tex new file mode 100644 index 00000000..1bb7a9e0 --- /dev/null +++ b/sail_latex_mips/fnzcast_unit_vec98272b7fb05a703213e98272ec5486c8.tex @@ -0,0 +1,4 @@ +function cast_unit_vec b = match b { + bitzero => 0b0, + _ => 0b1 +} diff --git a/sail_latex_mips/fnzcheckcp0accesse535c637cac3118020cdac54870326df.tex b/sail_latex_mips/fnzcheckcp0accesse535c637cac3118020cdac54870326df.tex new file mode 100644 index 00000000..083516d5 --- /dev/null +++ b/sail_latex_mips/fnzcheckcp0accesse535c637cac3118020cdac54870326df.tex @@ -0,0 +1,10 @@ +function #\hyperref[sailMIPSzcheckCP0Access]{checkCP0Access}# () = + { + let accessLevel = #\hyperref[sailMIPSzgetAccessLevel]{getAccessLevel}#() in + if ((accessLevel != Kernel) & (~(CP0Status.#\hyperref[sailMIPSzCU]{CU}#()[0]))) then + { + CP0Cause->#\hyperref[sailMIPSzCE]{CE}#() = 0b00; + #\hyperref[sailMIPSzSignalException]{SignalException}#(CpU); + }; + #\hyperref[sailMIPSzcheckCP0AccessHook]{checkCP0AccessHook}#(); + } diff --git a/sail_latex_mips/fnzcheckcp0accesshook3dae675d70bdcddbd36c77cdbf07a44f.tex b/sail_latex_mips/fnzcheckcp0accesshook3dae675d70bdcddbd36c77cdbf07a44f.tex new file mode 100644 index 00000000..abceaabe --- /dev/null +++ b/sail_latex_mips/fnzcheckcp0accesshook3dae675d70bdcddbd36c77cdbf07a44f.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailMIPSzcheckCP0AccessHook]{checkCP0AccessHook}# () : unit -> unit = { + if not(#\hyperref[sailMIPSzpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}#()) then + #\hyperref[sailMIPSzraisezyc2zyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_AccessSystemRegsViolation) +} diff --git a/sail_latex_mips/fnzcheckcp2usable5e31fa40adaccfcd7791aafdb7b9d2de.tex b/sail_latex_mips/fnzcheckcp2usable5e31fa40adaccfcd7791aafdb7b9d2de.tex new file mode 100644 index 00000000..a244f684 --- /dev/null +++ b/sail_latex_mips/fnzcheckcp2usable5e31fa40adaccfcd7791aafdb7b9d2de.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailMIPSzcheckCP2usable]{checkCP2usable}# () = + if not (CP0Status.#\hyperref[sailMIPSzCU]{CU}#()[2]) then { + CP0Cause->#\hyperref[sailMIPSzCE]{CE}#() = 0b10; + #\hyperref[sailMIPSzSignalException]{SignalException}#(CpU); + } diff --git a/sail_latex_mips/fnzcheckddcperms07cb3f56bec26901cdf69beab49d8910.tex b/sail_latex_mips/fnzcheckddcperms07cb3f56bec26901cdf69beab49d8910.tex new file mode 100644 index 00000000..3133683b --- /dev/null +++ b/sail_latex_mips/fnzcheckddcperms07cb3f56bec26901cdf69beab49d8910.tex @@ -0,0 +1,12 @@ +function #\hyperref[sailMIPSzcheckDDCPerms]{checkDDCPerms}#(ddc : Capability, accessType: MemAccessType) = + { + if (not (ddc.tag)) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_TagViolation, 0b00000) + else if (ddc.sealed) then + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_SealViolation, 0b00000); + match accessType { + Instruction => assert(false), /* Only data accesses use DDC */ + LoadData => if (~(ddc.permit_load)) then (#\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitLoadViolation, 0b00000)), + StoreData => if (~(ddc.permit_store)) then (#\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(CapEx_PermitStoreViolation, 0b00000)) + }; + } diff --git a/sail_latex_mips/fnzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex b/sail_latex_mips/fnzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex new file mode 100644 index 00000000..edfe64e3 --- /dev/null +++ b/sail_latex_mips/fnzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex @@ -0,0 +1,6 @@ +function ClearRegSet_of_num arg# = match arg# { + 0 => GPLo, + 1 => GPHi, + 2 => CLo, + _ => CHi +} diff --git a/sail_latex_mips/fnzcomparee9b34cffaaa4473cdff7ece5c1a05374.tex b/sail_latex_mips/fnzcomparee9b34cffaaa4473cdff7ece5c1a05374.tex new file mode 100644 index 00000000..c49474d5 --- /dev/null +++ b/sail_latex_mips/fnzcomparee9b34cffaaa4473cdff7ece5c1a05374.tex @@ -0,0 +1,11 @@ +function #\hyperref[sailMIPSzcompare]{compare}# (cmp, valA, valB) = + match cmp { + EQ => valA == valB, + NE => valA != valB, + GE => valA >=_s valB, + GEU => valA >=_u valB, + GT => valB <_s valA, + LE => valB >=_s valA, + LT => valA <_s valB, + LTU => valA <_u valB + } diff --git a/sail_latex_mips/fnzcomparison_of_num2a18f2d9a572dd906b510535c629d4f0.tex b/sail_latex_mips/fnzcomparison_of_num2a18f2d9a572dd906b510535c629d4f0.tex new file mode 100644 index 00000000..8ff4bfc1 --- /dev/null +++ b/sail_latex_mips/fnzcomparison_of_num2a18f2d9a572dd906b510535c629d4f0.tex @@ -0,0 +1,10 @@ +function Comparison_of_num arg# = match arg# { + 0 => EQ, + 1 => NE, + 2 => GE, + 3 => GEU, + 4 => GT, + 5 => LE, + 6 => LT, + _ => LTU +} diff --git a/sail_latex_mips/fnzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex b/sail_latex_mips/fnzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex new file mode 100644 index 00000000..1e39fee4 --- /dev/null +++ b/sail_latex_mips/fnzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzconcatzystrzybits]{concat\_str\_bits}#(str, x) = #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(str, #\hyperref[sailMIPSzbitszystr]{bits\_str}#(x)) diff --git a/sail_latex_mips/fnzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex b/sail_latex_mips/fnzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex new file mode 100644 index 00000000..5062f27a --- /dev/null +++ b/sail_latex_mips/fnzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzconcatzystrzydec]{concat\_str\_dec}#(str, x) = #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(str, #\hyperref[sailMIPSzdeczystr]{dec\_str}#(x)) diff --git a/sail_latex_mips/fnzcp2_next_pc33094c95220fdc4b0a67b83ac21fc047.tex b/sail_latex_mips/fnzcp2_next_pc33094c95220fdc4b0a67b83ac21fc047.tex new file mode 100644 index 00000000..bec7996b --- /dev/null +++ b/sail_latex_mips/fnzcp2_next_pc33094c95220fdc4b0a67b83ac21fc047.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailMIPSzcp2zynextzypc]{cp2\_next\_pc}# () = { + PCC = NextPCC; + if InBranchDelay then { + NextPCC = DelayedPCC; + }; +} diff --git a/sail_latex_mips/fnzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex b/sail_latex_mips/fnzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex new file mode 100644 index 00000000..6ab563f3 --- /dev/null +++ b/sail_latex_mips/fnzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex @@ -0,0 +1,10 @@ +function CPtrCmpOp_of_num arg# = match arg# { + 0 => CEQ, + 1 => CNE, + 2 => CLT, + 3 => CLE, + 4 => CLTU, + 5 => CLEU, + 6 => CEXEQ, + _ => CNEXEQ +} diff --git a/sail_latex_mips/fnzdecode_failure_of_numcefdc025bb5d8d74839d8f9f65058d32.tex b/sail_latex_mips/fnzdecode_failure_of_numcefdc025bb5d8d74839d8f9f65058d32.tex new file mode 100644 index 00000000..2ad9ff6d --- /dev/null +++ b/sail_latex_mips/fnzdecode_failure_of_numcefdc025bb5d8d74839d8f9f65058d32.tex @@ -0,0 +1,6 @@ +function decode_failure_of_num arg# = match arg# { + 0 => no_matching_pattern, + 1 => unsupported_instruction, + 2 => illegal_instruction, + _ => internal_error +} diff --git a/sail_latex_mips/fnzdump_cp2_statee501e37d7b82b621f6ff3cd1f225d5f1.tex b/sail_latex_mips/fnzdump_cp2_statee501e37d7b82b621f6ff3cd1f225d5f1.tex new file mode 100644 index 00000000..a19c7b8c --- /dev/null +++ b/sail_latex_mips/fnzdump_cp2_statee501e37d7b82b621f6ff3cd1f225d5f1.tex @@ -0,0 +1,18 @@ +function #\hyperref[sailMIPSzdumpzycp2zystate]{dump\_cp2\_state}# () = { + #\hyperref[sailMIPSzprint]{print}#(#\hyperref[sailMIPSzconcatzystr]{concat\_str}#("DEBUG CAP PCC", #\hyperref[sailMIPSzcapToString]{capToString}#(PCC, true))); + foreach (i from 0 to 31) { + #\hyperref[sailMIPSzprint]{print}#(#\hyperref[sailMIPSzconcatzystr]{concat\_str}#("DEBUG CAP REG ", #\hyperref[sailMIPSzconcatzystr]{concat\_str}#(#\hyperref[sailMIPSzstringzyofzyint]{string\_of\_int}#(i), #\hyperref[sailMIPSzcapToString]{capToString}#(#\hyperref[sailMIPSzreadCapReg]{readCapReg}#(#\hyperref[sailMIPSztozybits]{to\_bits}#(5, i)), true)))) + }; + #\hyperref[sailMIPSzprint]{print}#(#\hyperref[sailMIPSzconcatzystr]{concat\_str}#("DEBUG CAP HWREG 00", #\hyperref[sailMIPSzcapToString]{capToString}#(DDC, true))); + #\hyperref[sailMIPSzprint]{print}#(#\hyperref[sailMIPSzconcatzystr]{concat\_str}#("DEBUG CAP HWREG 01", #\hyperref[sailMIPSzcapToString]{capToString}#(CULR, true))); + #\hyperref[sailMIPSzprint]{print}#(#\hyperref[sailMIPSzconcatzystr]{concat\_str}#("DEBUG CAP HWREG 08", #\hyperref[sailMIPSzcapToString]{capToString}#(CPLR, true))); + /* TODO: these two should not be mirrored to match the FPGA */ + #\hyperref[sailMIPSzprint]{print}#(#\hyperref[sailMIPSzconcatzystr]{concat\_str}#("DEBUG CAP HWREG 22", #\hyperref[sailMIPSzcapToString]{capToString}#(KR1C, true))); + #\hyperref[sailMIPSzprint]{print}#(#\hyperref[sailMIPSzconcatzystr]{concat\_str}#("DEBUG CAP HWREG 23", #\hyperref[sailMIPSzcapToString]{capToString}#(KR2C, true))); + /* ErrorEPCC, KCC, KDC, EPCC */ + #\hyperref[sailMIPSzprint]{print}#(#\hyperref[sailMIPSzconcatzystr]{concat\_str}#("DEBUG CAP HWREG 28", #\hyperref[sailMIPSzcapToString]{capToString}#(ErrorEPCC, true))); + #\hyperref[sailMIPSzprint]{print}#(#\hyperref[sailMIPSzconcatzystr]{concat\_str}#("DEBUG CAP HWREG 29", #\hyperref[sailMIPSzcapToString]{capToString}#(KCC, true))); + #\hyperref[sailMIPSzprint]{print}#(#\hyperref[sailMIPSzconcatzystr]{concat\_str}#("DEBUG CAP HWREG 30", #\hyperref[sailMIPSzcapToString]{capToString}#(KDC, true))); + #\hyperref[sailMIPSzprint]{print}#(#\hyperref[sailMIPSzconcatzystr]{concat\_str}#("DEBUG CAP HWREG 31", #\hyperref[sailMIPSzcapToString]{capToString}#(EPCC, true))); + +} diff --git a/sail_latex_mips/fnzeq_unit996f84433ac0995f4aadfca5b68cd358.tex b/sail_latex_mips/fnzeq_unit996f84433ac0995f4aadfca5b68cd358.tex new file mode 100644 index 00000000..62366d51 --- /dev/null +++ b/sail_latex_mips/fnzeq_unit996f84433ac0995f4aadfca5b68cd358.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzeqzyunit]{eq\_unit}#(_, _) = true diff --git a/sail_latex_mips/fnzerethook15fc4e665e3e6cc75e445b15faa26b37.tex b/sail_latex_mips/fnzerethook15fc4e665e3e6cc75e445b15faa26b37.tex new file mode 100644 index 00000000..b2234ae1 --- /dev/null +++ b/sail_latex_mips/fnzerethook15fc4e665e3e6cc75e445b15faa26b37.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailMIPSzERETHook]{ERETHook}#() : unit -> unit = + { + let epcc_val = if (CP0Status.#\hyperref[sailMIPSzERL]{ERL}#() == bitone) then ErrorEPCC else EPCC; + let new_pcc = if #\hyperref[sailMIPSzisSentryCap]{isSentryCap}#(epcc_val) then #\hyperref[sailMIPSzunsealCap]{unsealCap}#(epcc_val) else epcc_val; + #\hyperref[sailMIPSzsetzynextzypcc]{set\_next\_pcc}#(new_pcc) + } diff --git a/sail_latex_mips/fnzexception_of_num7e2e38eb3f1c380a425392cb53ad450c.tex b/sail_latex_mips/fnzexception_of_num7e2e38eb3f1c380a425392cb53ad450c.tex new file mode 100644 index 00000000..0ffd2ef1 --- /dev/null +++ b/sail_latex_mips/fnzexception_of_num7e2e38eb3f1c380a425392cb53ad450c.tex @@ -0,0 +1,21 @@ +function Exception_of_num arg# = match arg# { + 0 => Interrupt, + 1 => TLBMod, + 2 => TLBL, + 3 => TLBS, + 4 => AdEL, + 5 => AdES, + 6 => Sys, + 7 => Bp, + 8 => ResI, + 9 => CpU, + 10 => Ov, + 11 => Tr, + 12 => C2E, + 13 => C2Trap, + 14 => XTLBRefillL, + 15 => XTLBRefillS, + 16 => XTLBInvL, + 17 => XTLBInvS, + _ => MCheck +} diff --git a/sail_latex_mips/fnzexceptioncodef7807000fba49ff7759f4a4cbdf3d902.tex b/sail_latex_mips/fnzexceptioncodef7807000fba49ff7759f4a4cbdf3d902.tex new file mode 100644 index 00000000..4c41ff96 --- /dev/null +++ b/sail_latex_mips/fnzexceptioncodef7807000fba49ff7759f4a4cbdf3d902.tex @@ -0,0 +1,23 @@ +function #\hyperref[sailMIPSzExceptionCode]{ExceptionCode}# (ex) : Exception -> #\hyperref[sailMIPSzbits]{bits}#(5)= + let x : #\hyperref[sailMIPSzbits]{bits}#(8) = match ex + { + Interrupt => 0x00, /* Interrupt */ + TLBMod => 0x01, /* TLB modification exception */ + TLBL => 0x02, /* TLB #\hyperref[sailMIPSzexception]{exception}# (load or fetch) */ + TLBS => 0x03, /* TLB #\hyperref[sailMIPSzexception]{exception}# (store) */ + AdEL => 0x04, /* Address #\hyperref[sailMIPSzerror]{error}# (load or fetch) */ + AdES => 0x05, /* Address #\hyperref[sailMIPSzerror]{error}# (store) */ + Sys => 0x08, /* Syscall */ + Bp => 0x09, /* Breakpoint */ + ResI => 0x0a, /* Reserved instruction */ + CpU => 0x0b, /* Coprocessor Unusable */ + Ov => 0x0c, /* Arithmetic overflow */ + Tr => 0x0d, /* Trap */ + C2E => 0x12, /* C2E coprocessor 2 exception */ + C2Trap => 0x12, /* C2Trap maps to same exception code, different vector */ + XTLBRefillL => 0x02, + XTLBRefillS => 0x03, + XTLBInvL => 0x02, + XTLBInvS => 0x03, + MCheck => 0x18 + } in x[4..0] diff --git a/sail_latex_mips/fnzexceptionvectorbase2dabb9cbc70df89c064ff6ef9c281b30.tex b/sail_latex_mips/fnzexceptionvectorbase2dabb9cbc70df89c064ff6ef9c281b30.tex new file mode 100644 index 00000000..4f765b83 --- /dev/null +++ b/sail_latex_mips/fnzexceptionvectorbase2dabb9cbc70df89c064ff6ef9c281b30.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailMIPSzexceptionVectorBase]{exceptionVectorBase}# () = + if CP0Status.#\hyperref[sailMIPSzBEV]{BEV}#() then + 0xFFFFFFFFBFC00200 + else + 0xFFFFFFFF80000000 diff --git a/sail_latex_mips/fnzexceptionvectoroffset5c95f15ec5e635d417858fb601d0a766.tex b/sail_latex_mips/fnzexceptionvectoroffset5c95f15ec5e635d417858fb601d0a766.tex new file mode 100644 index 00000000..dc3170a0 --- /dev/null +++ b/sail_latex_mips/fnzexceptionvectoroffset5c95f15ec5e635d417858fb601d0a766.tex @@ -0,0 +1,9 @@ +function #\hyperref[sailMIPSzexceptionVectorOffset]{exceptionVectorOffset}# (ex) = + if (CP0Status.#\hyperref[sailMIPSzEXL]{EXL}#()) then + 0x180 /* Always use common vector if in exception mode already */ + else if ((ex == XTLBRefillL) | (ex == XTLBRefillS)) then + 0x080 + else if (ex == C2Trap) then + 0x280 /* Special vector for CHERI traps */ + else + 0x180 /* Common vector */ diff --git a/sail_latex_mips/fnzexecute_branch311b9f285cc52d66c683fa3ecaee2918.tex b/sail_latex_mips/fnzexecute_branch311b9f285cc52d66c683fa3ecaee2918.tex new file mode 100644 index 00000000..b0c8cfa3 --- /dev/null +++ b/sail_latex_mips/fnzexecute_branch311b9f285cc52d66c683fa3ecaee2918.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailMIPSzexecutezybranch]{execute\_branch}# (pc) = { + let len = #\hyperref[sailMIPSzgetCapLength]{getCapLength}#(PCC); + /* Check the branch is within PCC bounds. Note that PC is offset to + base so branches below base will be negative / very large and + greater than top. */ + if #\hyperref[sailMIPSzunsigned]{unsigned}#(pc) + 4 > len then + #\hyperref[sailMIPSzraisezyc2zyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_LengthViolation); + #\hyperref[sailMIPSzexecutezybranchzymips]{execute\_branch\_mips}#(pc); } diff --git a/sail_latex_mips/fnzexecute_branch_mipse0f90fc63954012c1f04b5f4841d0bbb.tex b/sail_latex_mips/fnzexecute_branch_mipse0f90fc63954012c1f04b5f4841d0bbb.tex new file mode 100644 index 00000000..ac435400 --- /dev/null +++ b/sail_latex_mips/fnzexecute_branch_mipse0f90fc63954012c1f04b5f4841d0bbb.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailMIPSzexecutezybranchzymips]{execute\_branch\_mips}#(pc) = { + DelayedPC = pc; + BranchPending = 0b1; + NextInBranchDelay = 0b1; +} diff --git a/sail_latex_mips/fnzexecute_branch_pcc8b6a454691b25b72e01ecd191988286f.tex b/sail_latex_mips/fnzexecute_branch_pcc8b6a454691b25b72e01ecd191988286f.tex new file mode 100644 index 00000000..530783b2 --- /dev/null +++ b/sail_latex_mips/fnzexecute_branch_pcc8b6a454691b25b72e01ecd191988286f.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailMIPSzexecutezybranchzypcc]{execute\_branch\_pcc}#(newPCC) = { + DelayedPC = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzgetCapOffset]{getCapOffset}#(newPCC)); + DelayedPCC = newPCC; + BranchPending = 0b1; + NextInBranchDelay = 0b1; +} diff --git a/sail_latex_mips/fnzextendload386a20971b3dbdcd10ee9b8b44e2c2f7.tex b/sail_latex_mips/fnzextendload386a20971b3dbdcd10ee9b8b44e2c2f7.tex new file mode 100644 index 00000000..a5712a29 --- /dev/null +++ b/sail_latex_mips/fnzextendload386a20971b3dbdcd10ee9b8b44e2c2f7.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailMIPSzextendLoad]{extendLoad}#(memResult, sign) = { + if (sign) then + #\hyperref[sailMIPSzsignzyextend]{sign\_extend}#(memResult) + else + #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(memResult) +} diff --git a/sail_latex_mips/fnzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex b/sail_latex_mips/fnzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex new file mode 100644 index 00000000..4fce6eb5 --- /dev/null +++ b/sail_latex_mips/fnzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex @@ -0,0 +1,9 @@ +function #\hyperref[sailMIPSzfdivzyint]{fdiv\_int}#(n: int, m: int) -> int = { + if n < 0 & m > 0 then { + #\hyperref[sailMIPSztdivzyint]{tdiv\_int}#(n + 1, m) - 1 + } else if n > 0 & m < 0 then { + #\hyperref[sailMIPSztdivzyint]{tdiv\_int}#(n - 1, m) - 1 + } else { + #\hyperref[sailMIPSztdivzyint]{tdiv\_int}#(n, m) + } +} diff --git a/sail_latex_mips/fnzfmod_int7e215ca2b888f4e92201959fd40958a5.tex b/sail_latex_mips/fnzfmod_int7e215ca2b888f4e92201959fd40958a5.tex new file mode 100644 index 00000000..f03fa18c --- /dev/null +++ b/sail_latex_mips/fnzfmod_int7e215ca2b888f4e92201959fd40958a5.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailMIPSzfmodzyint]{fmod\_int}#(n: int, m: int) -> int = { + n - (m * #\hyperref[sailMIPSzfdivzyint]{fdiv\_int}#(n, m)) +} diff --git a/sail_latex_mips/fnzget_cp0epc947f8a8e6dac5833e002f1ea37a79de2.tex b/sail_latex_mips/fnzget_cp0epc947f8a8e6dac5833e002f1ea37a79de2.tex new file mode 100644 index 00000000..a11a6e81 --- /dev/null +++ b/sail_latex_mips/fnzget_cp0epc947f8a8e6dac5833e002f1ea37a79de2.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailMIPSzgetzyCP0EPC]{get\_CP0EPC}# () = + #\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzgetCapOffset]{getCapOffset}#(EPCC)) diff --git a/sail_latex_mips/fnzget_cp0errorepc1188335ff3decc7c914ce1ba3a7904dd.tex b/sail_latex_mips/fnzget_cp0errorepc1188335ff3decc7c914ce1ba3a7904dd.tex new file mode 100644 index 00000000..475e3ac5 --- /dev/null +++ b/sail_latex_mips/fnzget_cp0errorepc1188335ff3decc7c914ce1ba3a7904dd.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailMIPSzgetzyCP0ErrorEPC]{get\_CP0ErrorEPC}# () = + #\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzgetCapOffset]{getCapOffset}#(ErrorEPCC)) diff --git a/sail_latex_mips/fnzgetaccesslevel40127125b18eb6336d48aa4638317128.tex b/sail_latex_mips/fnzgetaccesslevel40127125b18eb6336d48aa4638317128.tex new file mode 100644 index 00000000..e37537e7 --- /dev/null +++ b/sail_latex_mips/fnzgetaccesslevel40127125b18eb6336d48aa4638317128.tex @@ -0,0 +1,10 @@ +function #\hyperref[sailMIPSzgetAccessLevel]{getAccessLevel}#() = + if ((CP0Status.#\hyperref[sailMIPSzEXL]{EXL}#()) | (CP0Status.#\hyperref[sailMIPSzERL]{ERL}#())) then + Kernel + else match CP0Status.#\hyperref[sailMIPSzKSU]{KSU}#() + { + 0b00 => Kernel, + 0b01 => Supervisor, + 0b10 => User, + _ => User /* behaviour undefined, assume user */ + } diff --git a/sail_latex_mips/fnzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex b/sail_latex_mips/fnzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex new file mode 100644 index 00000000..63a206ae --- /dev/null +++ b/sail_latex_mips/fnzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(c) : Capability -> uint64 = + let (base, _) = #\hyperref[sailMIPSzgetCapBounds]{getCapBounds}#(c) in + base diff --git a/sail_latex_mips/fnzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex b/sail_latex_mips/fnzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex new file mode 100644 index 00000000..390a669c --- /dev/null +++ b/sail_latex_mips/fnzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex @@ -0,0 +1,35 @@ +function #\hyperref[sailMIPSzgetCapBounds]{getCapBounds}#(c) : Capability -> (uint64, CapLen) = + let E = #\hyperref[sailMIPSzunsigned]{unsigned}#(c.E) in + let a : #\hyperref[sailMIPSzbits]{bits}#(64) = c.address in + /* Extract bits we need to make the top correction and calculate representable limit */ + let a3 = #\hyperref[sailMIPSztruncate]{truncate}#(a >> (E + 11), 3) in + let B3 = #\hyperref[sailMIPSztruncateLSB]{truncateLSB}#(c.B, 3) in + let T3 = #\hyperref[sailMIPSztruncateLSB]{truncateLSB}#(c.T, 3) in + let R3 = B3 - 0b001 in /* wraps */ + /* Do address, base and top lie in the R aligned region above the one containing R? */ + let aHi = if a3 <_u R3 then 1 else 0 in + let bHi = if B3 <_u R3 then 1 else 0 in + let tHi = if T3 <_u R3 then 1 else 0 in + /* Compute region corrections for top and base relative to a */ + let correction_base = bHi - aHi in + let correction_top = tHi - aHi in + let a_top = (a >> (E + 14)) in { + base : #\hyperref[sailMIPSzbits]{bits}#(65) = #\hyperref[sailMIPSztruncate]{truncate}#((a_top + correction_base) @ c.B @ #\hyperref[sailMIPSzzzeros]{zeros}#(E), 65); + top : #\hyperref[sailMIPSzbits]{bits}#(65) = #\hyperref[sailMIPSztruncate]{truncate}#((a_top + correction_top) @ c.T @ #\hyperref[sailMIPSzzzeros]{zeros}#(E), 65); + if (base[64] == bitone) then { + /* If base[64] is set this indicates under or overflow i.e. a has + wrapped around the address space and been corrected. In this case + we need to correct top[64] because top is not quite modulo 2**64 due + to having max top == 2**64 in one particular case: */ + top[64] = if (aHi == 1) & (tHi == 1) then bitone else bitzero; + }; + /* The following is apparently equivalent to above and used by hw. */ + /* + let base2 : #\hyperref[sailMIPSzbits]{bits}#(2) = bitzero @ base[63]; + let top2 : #\hyperref[sailMIPSzbits]{bits}#(2) = top[64..63]; + if (E < (#\hyperref[sailMIPSzunsigned]{unsigned}#(resetE) - 1)) & (#\hyperref[sailMIPSzunsigned]{unsigned}#(top2 - base2) > 1) then { + top[64] = ~(top[64]); + }; + */ + (#\hyperref[sailMIPSzunsigned]{unsigned}#(base[63..0]), #\hyperref[sailMIPSzunsigned]{unsigned}#(top)) + } diff --git a/sail_latex_mips/fnzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex b/sail_latex_mips/fnzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex new file mode 100644 index 00000000..8dc29e71 --- /dev/null +++ b/sail_latex_mips/fnzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzgetCapCursor]{getCapCursor}#(cap) : Capability -> uint64 = #\hyperref[sailMIPSzunsigned]{unsigned}#(cap.address) diff --git a/sail_latex_mips/fnzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex b/sail_latex_mips/fnzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex new file mode 100644 index 00000000..eb7f5f81 --- /dev/null +++ b/sail_latex_mips/fnzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzgetCapFlags]{getCapFlags}#(cap) = 0b0 /* Should be [] but breaks HOL */ diff --git a/sail_latex_mips/fnzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex b/sail_latex_mips/fnzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex new file mode 100644 index 00000000..2bc6a6f7 --- /dev/null +++ b/sail_latex_mips/fnzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex @@ -0,0 +1,13 @@ +function #\hyperref[sailMIPSzgetCapHardPerms]{getCapHardPerms}#(cap) : Capability -> #\hyperref[sailMIPSzbits]{bits}#(12) = + (cap.permit_set_CID + @ cap.access_system_regs + @ cap.permit_unseal + @ cap.permit_ccall + @ cap.permit_seal + @ cap.permit_store_local_cap + @ cap.permit_store_cap + @ cap.permit_load_cap + @ cap.permit_store + @ cap.permit_load + @ cap.permit_execute + @ cap.global) diff --git a/sail_latex_mips/fnzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex b/sail_latex_mips/fnzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex new file mode 100644 index 00000000..7c4b27cd --- /dev/null +++ b/sail_latex_mips/fnzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex @@ -0,0 +1,9 @@ +function #\hyperref[sailMIPSzgetCapLength]{getCapLength}#(c) : Capability -> CapLen = + let ('base, 'top) = #\hyperref[sailMIPSzgetCapBounds]{getCapBounds}#(c) in { + /* For valid capabilties we expect top >= base and hence + length >= 0 but representation does allow top < base in some + cases so might encounter on untagged capabilities. Here we just + pretend it is a 65-bit quantitiy and wrap. */ + assert (not(c.tag) | top >= base); + (top - base) % #\hyperref[sailMIPSzpow2]{pow2}#(65) + } diff --git a/sail_latex_mips/fnzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex b/sail_latex_mips/fnzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex new file mode 100644 index 00000000..502da664 --- /dev/null +++ b/sail_latex_mips/fnzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailMIPSzgetCapOffset]{getCapOffset}#(c) : Capability -> uint64 = + let base = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(c) in + (#\hyperref[sailMIPSzunsigned]{unsigned}#(c.address) - base) % #\hyperref[sailMIPSzpow2]{pow2}#(64) diff --git a/sail_latex_mips/fnzgetcapperms6aed04c1602f540bb5d604425f922d92.tex b/sail_latex_mips/fnzgetcapperms6aed04c1602f540bb5d604425f922d92.tex new file mode 100644 index 00000000..317f4ca7 --- /dev/null +++ b/sail_latex_mips/fnzgetcapperms6aed04c1602f540bb5d604425f922d92.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailMIPSzgetCapPerms]{getCapPerms}#(cap) : Capability -> #\hyperref[sailMIPSzbits]{bits}#(31) = + let perms : #\hyperref[sailMIPSzbits]{bits}#(15) = #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(#\hyperref[sailMIPSzgetCapHardPerms]{getCapHardPerms}#(cap)) in + (0x000 /* uperms 30-19 */ + @ cap.uperms + @ perms) diff --git a/sail_latex_mips/fnzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex b/sail_latex_mips/fnzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex new file mode 100644 index 00000000..a9d0bba5 --- /dev/null +++ b/sail_latex_mips/fnzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailMIPSzgetCapTop]{getCapTop}# (c) : Capability -> CapLen = + let (_, top) = #\hyperref[sailMIPSzgetCapBounds]{getCapBounds}#(c) in + top diff --git a/sail_latex_mips/fnzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex b/sail_latex_mips/fnzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex new file mode 100644 index 00000000..70bf22bb --- /dev/null +++ b/sail_latex_mips/fnzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailMIPSzgetRepresentableAlignmentMask]{getRepresentableAlignmentMask}#(len) : #\hyperref[sailMIPSzbits]{bits}#(64) -> #\hyperref[sailMIPSzbits]{bits}#(64) = { + let (exact, c) = #\hyperref[sailMIPSzsetCapBounds]{setCapBounds}#(default_cap, #\hyperref[sailMIPSzones]{ones}#() - len, 0b0 @ 0xffffffffffffffff); + let e : range(0, 52) = #\hyperref[sailMIPSzmin]{min}#(#\hyperref[sailMIPSzunsigned]{unsigned}#(c.E), 52); + let e' : range(0, 55) = if c.internal_e then e + 3 else 0; + #\hyperref[sailMIPSzones]{ones}#(64-e') @ #\hyperref[sailMIPSzzzeros]{zeros}#(e') +} diff --git a/sail_latex_mips/fnzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex b/sail_latex_mips/fnzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex new file mode 100644 index 00000000..08ca7120 --- /dev/null +++ b/sail_latex_mips/fnzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailMIPSzgetRepresentableLength]{getRepresentableLength}#(len) : #\hyperref[sailMIPSzbits]{bits}#(64) -> #\hyperref[sailMIPSzbits]{bits}#(64) = { + let m = #\hyperref[sailMIPSzgetRepresentableAlignmentMask]{getRepresentableAlignmentMask}#(len); + (len + ~(m)) & m +} diff --git a/sail_latex_mips/fnzgrantsaccess1c25b864354b7175e1d8d7ec4e5e27b6.tex b/sail_latex_mips/fnzgrantsaccess1c25b864354b7175e1d8d7ec4e5e27b6.tex new file mode 100644 index 00000000..4e81f4ca --- /dev/null +++ b/sail_latex_mips/fnzgrantsaccess1c25b864354b7175e1d8d7ec4e5e27b6.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailMIPSzgrantsAccess]{grantsAccess}# (currentLevel, requiredLevel) = + #\hyperref[sailMIPSzintzyofzyAccessLevel]{int\_of\_AccessLevel}#(currentLevel) >= #\hyperref[sailMIPSzintzyofzyAccessLevel]{int\_of\_AccessLevel}#(requiredLevel) diff --git a/sail_latex_mips/fnzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex b/sail_latex_mips/fnzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex new file mode 100644 index 00000000..80df6c41 --- /dev/null +++ b/sail_latex_mips/fnzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzhasReservedOType]{hasReservedOType}#(cap) = #\hyperref[sailMIPSzunsigned]{unsigned}#(cap.otype) > max_otype diff --git a/sail_latex_mips/fnzinccapoffsetc4735d243650e78b90bacb6efb419260.tex b/sail_latex_mips/fnzinccapoffsetc4735d243650e78b90bacb6efb419260.tex new file mode 100644 index 00000000..f4d9fb79 --- /dev/null +++ b/sail_latex_mips/fnzinccapoffsetc4735d243650e78b90bacb6efb419260.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailMIPSzincCapOffset]{incCapOffset}#(c, delta) : (Capability, #\hyperref[sailMIPSzbits]{bits}#(64)) -> (bool, Capability) = + let newAddress : #\hyperref[sailMIPSzbits]{bits}#(64) = c.address + delta in + let newCap = { c with address = newAddress } in + let representable = #\hyperref[sailMIPSzcapBoundsEqual]{capBoundsEqual}#(c, newCap) in +/* let representable = #\hyperref[sailMIPSzfastRepCheck]{fastRepCheck}#(c, delta) in*/ + (representable, newCap) diff --git a/sail_latex_mips/fnzincrementcp0count9449093588dc2365295e37dd55af742d.tex b/sail_latex_mips/fnzincrementcp0count9449093588dc2365295e37dd55af742d.tex new file mode 100644 index 00000000..08d05212 --- /dev/null +++ b/sail_latex_mips/fnzincrementcp0count9449093588dc2365295e37dd55af742d.tex @@ -0,0 +1,17 @@ +function #\hyperref[sailMIPSzincrementCP0Count]{incrementCP0Count}#() = { + TLBRandom = (if (TLBRandom == TLBWired) + then (TLBIndexMax) else (TLBRandom - 1)); + + CP0Count = (CP0Count + 1); + if (CP0Count == CP0Compare) then { + CP0Cause->#\hyperref[sailMIPSzIP]{IP}#() = CP0Cause.#\hyperref[sailMIPSzIP]{IP}#() | 0x80; /* IP7 is timer interrupt */ + }; + + let ims = CP0Status.#\hyperref[sailMIPSzIM]{IM}#() in + let ips = CP0Cause.#\hyperref[sailMIPSzIP]{IP}#() in + let ie = CP0Status.#\hyperref[sailMIPSzIE]{IE}#() in + let exl = CP0Status.#\hyperref[sailMIPSzEXL]{EXL}#() in + let erl = CP0Status.#\hyperref[sailMIPSzERL]{ERL}#() in + if ((~(exl)) & (~(erl)) & ie & ((ips & ims) != 0x00)) then + #\hyperref[sailMIPSzSignalException]{SignalException}#(Interrupt); +} diff --git a/sail_latex_mips/fnzinit_cp0_state82b3d81150b612dca26217241b94da87.tex b/sail_latex_mips/fnzinit_cp0_state82b3d81150b612dca26217241b94da87.tex new file mode 100644 index 00000000..f3b5f5f6 --- /dev/null +++ b/sail_latex_mips/fnzinit_cp0_state82b3d81150b612dca26217241b94da87.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailMIPSzinitzycp0zystate]{init\_cp0\_state}# () : unit -> unit = { + CP0Status->#\hyperref[sailMIPSzBEV]{BEV}#() = bitone; +} diff --git a/sail_latex_mips/fnzinit_cp2_state7056c424b16f2ae2f851216ae32427b0.tex b/sail_latex_mips/fnzinit_cp2_state7056c424b16f2ae2f851216ae32427b0.tex new file mode 100644 index 00000000..1cb1a89b --- /dev/null +++ b/sail_latex_mips/fnzinit_cp2_state7056c424b16f2ae2f851216ae32427b0.tex @@ -0,0 +1,18 @@ +function #\hyperref[sailMIPSzinitzycp2zystate]{init\_cp2\_state}# () = { + PCC = default_cap; + NextPCC = default_cap; + DelayedPCC = default_cap; + DDC = default_cap; + KCC = default_cap; + EPCC = default_cap; + ErrorEPCC = default_cap; + KDC = null_cap; + KR1C = null_cap; + KR2C = null_cap; + CPLR = null_cap; + CULR = null_cap; + foreach (i from 1 to 31) { + let idx = #\hyperref[sailMIPSztozybits]{to\_bits}#(5, i) in + #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(idx, null_cap) + } +} diff --git a/sail_latex_mips/fnzint_of_accessleveld511598513a474f4d799d64651770863.tex b/sail_latex_mips/fnzint_of_accessleveld511598513a474f4d799d64651770863.tex new file mode 100644 index 00000000..0a5bb3c6 --- /dev/null +++ b/sail_latex_mips/fnzint_of_accessleveld511598513a474f4d799d64651770863.tex @@ -0,0 +1,6 @@ +function int_of_AccessLevel level = + match level { + User => 0, + Supervisor => 1, + Kernel => 2 + } diff --git a/sail_latex_mips/fnzis_nonebebf4558161c4d567fb50f7df9e82374.tex b/sail_latex_mips/fnzis_nonebebf4558161c4d567fb50f7df9e82374.tex new file mode 100644 index 00000000..4cc2a624 --- /dev/null +++ b/sail_latex_mips/fnzis_nonebebf4558161c4d567fb50f7df9e82374.tex @@ -0,0 +1,4 @@ +function is_none opt = match opt { + #\hyperref[sailMIPSzSome]{Some}#(_) => false, + #\hyperref[sailMIPSzNone]{None}#() => true +} diff --git a/sail_latex_mips/fnzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex b/sail_latex_mips/fnzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex new file mode 100644 index 00000000..1c59e614 --- /dev/null +++ b/sail_latex_mips/fnzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex @@ -0,0 +1,4 @@ +function is_some opt = match opt { + #\hyperref[sailMIPSzSome]{Some}#(_) => true, + #\hyperref[sailMIPSzNone]{None}#() => false +} diff --git a/sail_latex_mips/fnzisaddressaligned9b5d757d64e55546134bbc396b0d9129.tex b/sail_latex_mips/fnzisaddressaligned9b5d757d64e55546134bbc396b0d9129.tex new file mode 100644 index 00000000..15cabe81 --- /dev/null +++ b/sail_latex_mips/fnzisaddressaligned9b5d757d64e55546134bbc396b0d9129.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailMIPSzisAddressAligned]{isAddressAligned}# (addr, wordType) = + let a = #\hyperref[sailMIPSzunsigned]{unsigned}#(addr) in + a / alignment_width == (a + #\hyperref[sailMIPSzwordWidthBytes]{wordWidthBytes}#(wordType) - 1) / alignment_width diff --git a/sail_latex_mips/fnzissentrycapede72a679ee46914361276c4bacdaf18.tex b/sail_latex_mips/fnzissentrycapede72a679ee46914361276c4bacdaf18.tex new file mode 100644 index 00000000..dbb083da --- /dev/null +++ b/sail_latex_mips/fnzissentrycapede72a679ee46914361276c4bacdaf18.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzisSentryCap]{isSentryCap}# (cap) = #\hyperref[sailMIPSzsigned]{signed}#(cap.otype) == otype_sentry diff --git a/sail_latex_mips/fnzmask357329ae84e03dd27d4454a1873fc3dd.tex b/sail_latex_mips/fnzmask357329ae84e03dd27d4454a1873fc3dd.tex new file mode 100644 index 00000000..8bf0f4d4 --- /dev/null +++ b/sail_latex_mips/fnzmask357329ae84e03dd27d4454a1873fc3dd.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzmask]{mask}#(n, bs) = bs[n - 1 .. 0] diff --git a/sail_latex_mips/fnzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex b/sail_latex_mips/fnzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex new file mode 100644 index 00000000..fa888232 --- /dev/null +++ b/sail_latex_mips/fnzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzMAX]{MAX}#(n) = #\hyperref[sailMIPSzpow2]{pow2}#(n) - 1 diff --git a/sail_latex_mips/fnzmem_synca6b7cb44064bf3e0998ab455e0247f73.tex b/sail_latex_mips/fnzmem_synca6b7cb44064bf3e0998ab455e0247f73.tex new file mode 100644 index 00000000..8618cfed --- /dev/null +++ b/sail_latex_mips/fnzmem_synca6b7cb44064bf3e0998ab455e0247f73.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzMEMzysync]{MEM\_sync}# () = #\hyperref[sailMIPSzskipzybarr]{skip\_barr}#() diff --git a/sail_latex_mips/fnzmemaccesscaprestriction_of_num40cccde77213084744ee3677231b6055.tex b/sail_latex_mips/fnzmemaccesscaprestriction_of_num40cccde77213084744ee3677231b6055.tex new file mode 100644 index 00000000..8a528482 --- /dev/null +++ b/sail_latex_mips/fnzmemaccesscaprestriction_of_num40cccde77213084744ee3677231b6055.tex @@ -0,0 +1,5 @@ +function MemAccessCapRestriction_of_num arg# = match arg# { + 0 => Unrestricted, + 1 => Trap, + _ => Clear +} diff --git a/sail_latex_mips/fnzmemaccesstype_of_nume9bc7b384750bfb019a26074bf441f44.tex b/sail_latex_mips/fnzmemaccesstype_of_nume9bc7b384750bfb019a26074bf441f44.tex new file mode 100644 index 00000000..a16af4e9 --- /dev/null +++ b/sail_latex_mips/fnzmemaccesstype_of_nume9bc7b384750bfb019a26074bf441f44.tex @@ -0,0 +1,5 @@ +function MemAccessType_of_num arg# = match arg# { + 0 => Instruction, + 1 => LoadData, + _ => StoreData +} diff --git a/sail_latex_mips/fnzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex b/sail_latex_mips/fnzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex new file mode 100644 index 00000000..eb2a681c --- /dev/null +++ b/sail_latex_mips/fnzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailMIPSzmemBitsToCapability]{memBitsToCapability}#(tag, b) : (bool, #\hyperref[sailMIPSzbits]{bits}#(128)) -> Capability = + #\hyperref[sailMIPSzcapBitsToCapability]{capBitsToCapability}#(tag, b ^ null_cap_bits) diff --git a/sail_latex_mips/fnzmemea4fc0f7b33124f774de07c06ff98ca952.tex b/sail_latex_mips/fnzmemea4fc0f7b33124f774de07c06ff98ca952.tex new file mode 100644 index 00000000..d0cd72ff --- /dev/null +++ b/sail_latex_mips/fnzmemea4fc0f7b33124f774de07c06ff98ca952.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzMEMea]{MEMea}# (addr, size) = #\hyperref[sailMIPSzskipzyeamem]{skip\_eamem}#() diff --git a/sail_latex_mips/fnzmemea_conditionalac126f332517db0f6fcc745fef2e377d.tex b/sail_latex_mips/fnzmemea_conditionalac126f332517db0f6fcc745fef2e377d.tex new file mode 100644 index 00000000..b65579b6 --- /dev/null +++ b/sail_latex_mips/fnzmemea_conditionalac126f332517db0f6fcc745fef2e377d.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzMEMeazyconditional]{MEMea\_conditional}# (addr, size) = #\hyperref[sailMIPSzskipzyeamem]{skip\_eamem}#() diff --git a/sail_latex_mips/fnzmemr1e9f36dc3a59118d83f70ffa5fe2dd9e.tex b/sail_latex_mips/fnzmemr1e9f36dc3a59118d83f70ffa5fe2dd9e.tex new file mode 100644 index 00000000..bf5ff5f3 --- /dev/null +++ b/sail_latex_mips/fnzmemr1e9f36dc3a59118d83f70ffa5fe2dd9e.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzMEMr]{MEMr}# (addr, size) = #\hyperref[sailMIPSzzyzyMIPSzyread]{\_\_MIPS\_read}#(addr, size) diff --git a/sail_latex_mips/fnzmemr_reserve_wrapper69fc87b2d98dbfe1febc5c11d3d298c6.tex b/sail_latex_mips/fnzmemr_reserve_wrapper69fc87b2d98dbfe1febc5c11d3d298c6.tex new file mode 100644 index 00000000..4a57144f --- /dev/null +++ b/sail_latex_mips/fnzmemr_reserve_wrapper69fc87b2d98dbfe1febc5c11d3d298c6.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailMIPSzMEMrzyreservezywrapper]{MEMr\_reserve\_wrapper}# (addr , size) = + #\hyperref[sailMIPSzreversezyendianness]{reverse\_endianness}#(#\hyperref[sailMIPSzMEMrzyreserve]{MEMr\_reserve}#(addr, size)) diff --git a/sail_latex_mips/fnzmemr_reserved9c4ade13430d97ec20a414fa45cde6a.tex b/sail_latex_mips/fnzmemr_reserved9c4ade13430d97ec20a414fa45cde6a.tex new file mode 100644 index 00000000..1b756508 --- /dev/null +++ b/sail_latex_mips/fnzmemr_reserved9c4ade13430d97ec20a414fa45cde6a.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzMEMrzyreserve]{MEMr\_reserve}# (addr, size) = #\hyperref[sailMIPSzzyzyMIPSzyread]{\_\_MIPS\_read}#(addr, size) diff --git a/sail_latex_mips/fnzmemr_tagged440beee75c90056a7102115b9b1125be.tex b/sail_latex_mips/fnzmemr_tagged440beee75c90056a7102115b9b1125be.tex new file mode 100644 index 00000000..973954a8 --- /dev/null +++ b/sail_latex_mips/fnzmemr_tagged440beee75c90056a7102115b9b1125be.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailMIPSzMEMrzytagged]{MEMr\_tagged}# (addr, size, allowTag) = +{ + let tag = if allowTag then #\hyperref[sailMIPSzreadzytagzybool]{read\_tag\_bool}#(addr & cap_addr_mask) else false in + let data = #\hyperref[sailMIPSzMEMr]{MEMr}#(addr, size) in + (tag, #\hyperref[sailMIPSzreversezyendianness]{reverse\_endianness}#(data)) +} diff --git a/sail_latex_mips/fnzmemr_tagged_reserve7e4b5410eb1183e7621342e1939f17e1.tex b/sail_latex_mips/fnzmemr_tagged_reserve7e4b5410eb1183e7621342e1939f17e1.tex new file mode 100644 index 00000000..96e799de --- /dev/null +++ b/sail_latex_mips/fnzmemr_tagged_reserve7e4b5410eb1183e7621342e1939f17e1.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailMIPSzMEMrzytaggedzyreserve]{MEMr\_tagged\_reserve}# (addr, size, allowTag) = +{ + let tag = if allowTag then #\hyperref[sailMIPSzreadzytagzybool]{read\_tag\_bool}#(addr & cap_addr_mask) else false in + let data = #\hyperref[sailMIPSzMEMrzyreserve]{MEMr\_reserve}#(addr, size) in + (tag, #\hyperref[sailMIPSzreversezyendianness]{reverse\_endianness}#(data)) +} diff --git a/sail_latex_mips/fnzmemr_wrapper75f1a468d1dba11a7720be7f66d3c8e2.tex b/sail_latex_mips/fnzmemr_wrapper75f1a468d1dba11a7720be7f66d3c8e2.tex new file mode 100644 index 00000000..8d66c5ac --- /dev/null +++ b/sail_latex_mips/fnzmemr_wrapper75f1a468d1dba11a7720be7f66d3c8e2.tex @@ -0,0 +1,13 @@ +function #\hyperref[sailMIPSzMEMrzywrapper]{MEMr\_wrapper}# (addr, size) = + if (addr == 0x000000007f000000) then + { + let rvalid = UART_RVALID in + { + UART_RVALID = [bitzero]; + #\hyperref[sailMIPSzmask]{mask}#(0x00000000 @ UART_RDATA @ rvalid @ 0b0000000 @ 0x0000) + } + } + else if (addr == 0x000000007f000004) then + #\hyperref[sailMIPSzmask]{mask}#(0x000000000004ffff) /* Always plenty of write space available and jtag activity */ + else + #\hyperref[sailMIPSzreversezyendianness]{reverse\_endianness}#(#\hyperref[sailMIPSzMEMr]{MEMr}#(addr, size)) /* MEMr assumes little endian */ diff --git a/sail_latex_mips/fnzmemval_conditional81b75b657c8ad34bfa8410067d19f50e.tex b/sail_latex_mips/fnzmemval_conditional81b75b657c8ad34bfa8410067d19f50e.tex new file mode 100644 index 00000000..dc957e05 --- /dev/null +++ b/sail_latex_mips/fnzmemval_conditional81b75b657c8ad34bfa8410067d19f50e.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzMEMvalzyconditional]{MEMval\_conditional}# (addr, size, data) = { #\hyperref[sailMIPSzzyzyMIPSzywrite]{\_\_MIPS\_write}#(addr, size, data); true } diff --git a/sail_latex_mips/fnzmemvala388891903ef64c4b894bb339a9ee3eb.tex b/sail_latex_mips/fnzmemvala388891903ef64c4b894bb339a9ee3eb.tex new file mode 100644 index 00000000..e7c0bb73 --- /dev/null +++ b/sail_latex_mips/fnzmemvala388891903ef64c4b894bb339a9ee3eb.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzMEMval]{MEMval}# (addr, size, data) = #\hyperref[sailMIPSzzyzyMIPSzywrite]{\_\_MIPS\_write}#(addr, size, data) diff --git a/sail_latex_mips/fnzmemw_conditional_wrapperc4ec3508a0b7f04fee187cfb25d4f05b.tex b/sail_latex_mips/fnzmemw_conditional_wrapperc4ec3508a0b7f04fee187cfb25d4f05b.tex new file mode 100644 index 00000000..e233cfb6 --- /dev/null +++ b/sail_latex_mips/fnzmemw_conditional_wrapperc4ec3508a0b7f04fee187cfb25d4f05b.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailMIPSzMEMwzyconditionalzywrapper]{MEMw\_conditional\_wrapper}#(addr, size, data) = + { + /* require that writes don't cross capability #\hyperref[sailMIPSzboundaries]{boundaries}# (should be true due to mips alignment requirements) */ + assert((addr & cap_addr_mask) == ((addr + #\hyperref[sailMIPSztozybits]{to\_bits}#(64, size - 1)) & cap_addr_mask)); + /* On cheri non-capability writes must clear the corresponding tag */ + #\hyperref[sailMIPSzMEMwzytaggedzyconditional]{MEMw\_tagged\_conditional}#(addr, size, false, data) + } diff --git a/sail_latex_mips/fnzmemw_tagged27267fa3fd60f13e6d2e22ac409b93e4.tex b/sail_latex_mips/fnzmemw_tagged27267fa3fd60f13e6d2e22ac409b93e4.tex new file mode 100644 index 00000000..3233663f --- /dev/null +++ b/sail_latex_mips/fnzmemw_tagged27267fa3fd60f13e6d2e22ac409b93e4.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailMIPSzMEMwzytagged]{MEMw\_tagged}#(addr, size, tag, data) = +{ + #\hyperref[sailMIPSzMEMea]{MEMea}#(addr, size); + #\hyperref[sailMIPSzMEMval]{MEMval}#(addr, size, #\hyperref[sailMIPSzreversezyendianness]{reverse\_endianness}#(data)); + #\hyperref[sailMIPSzwritezytagzybool]{write\_tag\_bool}#(addr & cap_addr_mask, tag); +} diff --git a/sail_latex_mips/fnzmemw_tagged_conditionalb0f4ab03bc3ed7705702651cf1750e40.tex b/sail_latex_mips/fnzmemw_tagged_conditionalb0f4ab03bc3ed7705702651cf1750e40.tex new file mode 100644 index 00000000..bc43decf --- /dev/null +++ b/sail_latex_mips/fnzmemw_tagged_conditionalb0f4ab03bc3ed7705702651cf1750e40.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailMIPSzMEMwzytaggedzyconditional]{MEMw\_tagged\_conditional}#(addr, size, tag, data) = +{ + #\hyperref[sailMIPSzMEMeazyconditional]{MEMea\_conditional}#(addr, size); + success = #\hyperref[sailMIPSzMEMvalzyconditional]{MEMval\_conditional}#(addr, size, #\hyperref[sailMIPSzreversezyendianness]{reverse\_endianness}#(data)); + if success then + #\hyperref[sailMIPSzwritezytagzybool]{write\_tag\_bool}#(addr & cap_addr_mask, tag); + success; +} diff --git a/sail_latex_mips/fnzmemw_wrapper2b3f4fb31f9ea0001f534fade943e5e3.tex b/sail_latex_mips/fnzmemw_wrapper2b3f4fb31f9ea0001f534fade943e5e3.tex new file mode 100644 index 00000000..e149276c --- /dev/null +++ b/sail_latex_mips/fnzmemw_wrapper2b3f4fb31f9ea0001f534fade943e5e3.tex @@ -0,0 +1,14 @@ +function #\hyperref[sailMIPSzMEMwzywrapper]{MEMw\_wrapper}#(addr, size, data) = + if (addr == 0x000000007f000000) then + { + let ledata = #\hyperref[sailMIPSzreversezyendianness]{reverse\_endianness}#(data) in + UART_WDATA = ledata[7..0]; + UART_WRITTEN = 0b1; + } + else + { + /* require that writes don't cross capability #\hyperref[sailMIPSzboundaries]{boundaries}# (should be true due to mips alignment requirements) */ + assert((addr & cap_addr_mask) == ((addr + #\hyperref[sailMIPSztozybits]{to\_bits}#(64, size - 1)) & cap_addr_mask)); + /* On cheri non-capability writes must clear the corresponding tag */ + #\hyperref[sailMIPSzMEMwzytagged]{MEMw\_tagged}#(addr, size, false, data); + } diff --git a/sail_latex_mips/fnzmips_sign_extenddff82d4ceaaa72d7146e15c8674216ac.tex b/sail_latex_mips/fnzmips_sign_extenddff82d4ceaaa72d7146e15c8674216ac.tex new file mode 100644 index 00000000..4cc9f10c --- /dev/null +++ b/sail_latex_mips/fnzmips_sign_extenddff82d4ceaaa72d7146e15c8674216ac.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzmipszysignzyextend]{mips\_sign\_extend}#(m, v) = #\hyperref[sailMIPSzsailzysignzyextend]{sail\_sign\_extend}#(v, m) diff --git a/sail_latex_mips/fnzmips_zzero_extend6340d2cbae7a2266a4e1077b06a57276.tex b/sail_latex_mips/fnzmips_zzero_extend6340d2cbae7a2266a4e1077b06a57276.tex new file mode 100644 index 00000000..258afa9b --- /dev/null +++ b/sail_latex_mips/fnzmips_zzero_extend6340d2cbae7a2266a4e1077b06a57276.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzmipszyzzerozyextend]{mips\_zero\_extend}#(m, v) = #\hyperref[sailMIPSzsailzyzzerozyextend]{sail\_zero\_extend}#(v, m) diff --git a/sail_latex_mips/fnzmipssegmentof3db6164251b0305648a8f4d8f750299e.tex b/sail_latex_mips/fnzmipssegmentof3db6164251b0305648a8f4d8f750299e.tex new file mode 100644 index 00000000..cbb84aa5 --- /dev/null +++ b/sail_latex_mips/fnzmipssegmentof3db6164251b0305648a8f4d8f750299e.tex @@ -0,0 +1,15 @@ +function #\hyperref[sailMIPSzMIPSSegmentOf]{MIPSSegmentOf}# (vAddr) = { + let compat32 = (vAddr[61..31] == 0b1111111111111111111111111111111) in + match (vAddr[63..62]) { + 0b11 => match (compat32, vAddr[30..29]) { /* xkseg */ + (true, 0b11) => (Kernel, #\hyperref[sailMIPSzNone]{None}#() : #\hyperref[sailMIPSzoption]{option}#(#\hyperref[sailMIPSzbits]{bits}#(64))), /* kseg3 mapped 32-bit compat */ + (true, 0b10) => (Supervisor, #\hyperref[sailMIPSzNone]{None}#() : #\hyperref[sailMIPSzoption]{option}#(#\hyperref[sailMIPSzbits]{bits}#(64))), /* sseg mapped 32-bit compat */ + (true, 0b01) => (Kernel, #\hyperref[sailMIPSzSome]{Some}#(0x00000000 @ 0b000 @ vAddr[28..0])), /* kseg1 unmapped uncached 32-bit compat */ + (true, 0b00) => (Kernel, #\hyperref[sailMIPSzSome]{Some}#(0x00000000 @ 0b000 @ vAddr[28..0])), /* kseg0 unmapped cached 32-bit compat */ + (_, _) => (Kernel, #\hyperref[sailMIPSzNone]{None}#() : #\hyperref[sailMIPSzoption]{option}#(#\hyperref[sailMIPSzbits]{bits}#(64))) /* xkseg mapped */ + }, + 0b10 => (Kernel, #\hyperref[sailMIPSzSome]{Some}#(0b00000 @ vAddr[58..0])), /* xkphys bits 61-59 are cache #\hyperref[sailMIPSzmode]{mode}# (ignored) */ + 0b01 => (Supervisor, #\hyperref[sailMIPSzNone]{None}#() : #\hyperref[sailMIPSzoption]{option}#(#\hyperref[sailMIPSzbits]{bits}#(64))), /* xsseg - supervisor mapped */ + 0b00 => (User, #\hyperref[sailMIPSzNone]{None}#() : #\hyperref[sailMIPSzoption]{option}#(#\hyperref[sailMIPSzbits]{bits}#(64))) /* xuseg - user mapped */ + } +} diff --git a/sail_latex_mips/fnzmk_capcauseregd8ae0b1c037e066a22724fe6a3d3a9a6.tex b/sail_latex_mips/fnzmk_capcauseregd8ae0b1c037e066a22724fe6a3d3a9a6.tex new file mode 100644 index 00000000..2f42991f --- /dev/null +++ b/sail_latex_mips/fnzmk_capcauseregd8ae0b1c037e066a22724fe6a3d3a9a6.tex @@ -0,0 +1 @@ +function Mk_CapCauseReg v = struct { CapCauseReg_chunk_0 = subrange_bits(v, 15, 0) } diff --git a/sail_latex_mips/fnzmk_causereg8c2dd932a95a40841ae776546777d7fb.tex b/sail_latex_mips/fnzmk_causereg8c2dd932a95a40841ae776546777d7fb.tex new file mode 100644 index 00000000..2980787a --- /dev/null +++ b/sail_latex_mips/fnzmk_causereg8c2dd932a95a40841ae776546777d7fb.tex @@ -0,0 +1 @@ +function Mk_CauseReg v = struct { CauseReg_chunk_0 = subrange_bits(v, 31, 0) } diff --git a/sail_latex_mips/fnzmk_contextreg1279723b7ab574992f73b31ca621ca0c.tex b/sail_latex_mips/fnzmk_contextreg1279723b7ab574992f73b31ca621ca0c.tex new file mode 100644 index 00000000..77654e7d --- /dev/null +++ b/sail_latex_mips/fnzmk_contextreg1279723b7ab574992f73b31ca621ca0c.tex @@ -0,0 +1 @@ +function Mk_ContextReg v = struct { ContextReg_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_mips/fnzmk_statusreg3621c22662d06bd540ae8fffe8f9e08c.tex b/sail_latex_mips/fnzmk_statusreg3621c22662d06bd540ae8fffe8f9e08c.tex new file mode 100644 index 00000000..9800d874 --- /dev/null +++ b/sail_latex_mips/fnzmk_statusreg3621c22662d06bd540ae8fffe8f9e08c.tex @@ -0,0 +1 @@ +function Mk_StatusReg v = struct { StatusReg_chunk_0 = subrange_bits(v, 31, 0) } diff --git a/sail_latex_mips/fnzmk_tlbentry1b93a8ab49c4923ac3e577c5f28836c1.tex b/sail_latex_mips/fnzmk_tlbentry1b93a8ab49c4923ac3e577c5f28836c1.tex new file mode 100644 index 00000000..3ef4a82b --- /dev/null +++ b/sail_latex_mips/fnzmk_tlbentry1b93a8ab49c4923ac3e577c5f28836c1.tex @@ -0,0 +1 @@ +function Mk_TLBEntry v = struct { TLBEntry_chunk_1 = subrange_bits(v, 118, 64), TLBEntry_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_mips/fnzmk_tlbentryhireg6533ea9a44dee28d4b6d342ff77ceb66.tex b/sail_latex_mips/fnzmk_tlbentryhireg6533ea9a44dee28d4b6d342ff77ceb66.tex new file mode 100644 index 00000000..91204285 --- /dev/null +++ b/sail_latex_mips/fnzmk_tlbentryhireg6533ea9a44dee28d4b6d342ff77ceb66.tex @@ -0,0 +1 @@ +function Mk_TLBEntryHiReg v = struct { TLBEntryHiReg_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_mips/fnzmk_tlbentryloreg686ea4d498fae1c365c28583f86fcdf2.tex b/sail_latex_mips/fnzmk_tlbentryloreg686ea4d498fae1c365c28583f86fcdf2.tex new file mode 100644 index 00000000..e039be85 --- /dev/null +++ b/sail_latex_mips/fnzmk_tlbentryloreg686ea4d498fae1c365c28583f86fcdf2.tex @@ -0,0 +1 @@ +function Mk_TLBEntryLoReg v = struct { TLBEntryLoReg_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_mips/fnzmk_xcontextregea90f6c75d17b6f2b8452e8764f15274.tex b/sail_latex_mips/fnzmk_xcontextregea90f6c75d17b6f2b8452e8764f15274.tex new file mode 100644 index 00000000..34b4ec3b --- /dev/null +++ b/sail_latex_mips/fnzmk_xcontextregea90f6c75d17b6f2b8452e8764f15274.tex @@ -0,0 +1 @@ +function Mk_XContextReg v = struct { XContextReg_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_mips/fnzneq_anythingf220233154ca93d75c0323f604bb8d16.tex b/sail_latex_mips/fnzneq_anythingf220233154ca93d75c0323f604bb8d16.tex new file mode 100644 index 00000000..6601d760 --- /dev/null +++ b/sail_latex_mips/fnzneq_anythingf220233154ca93d75c0323f604bb8d16.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzneqzyanything]{neq\_anything}# (x, y) = #\hyperref[sailMIPSznotzybool]{not\_bool}#(x == y) diff --git a/sail_latex_mips/fnzneq_bits167748c906c068e62596c88540a84f42.tex b/sail_latex_mips/fnzneq_bits167748c906c068e62596c88540a84f42.tex new file mode 100644 index 00000000..5ce6a627 --- /dev/null +++ b/sail_latex_mips/fnzneq_bits167748c906c068e62596c88540a84f42.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzneqzybits]{neq\_bits}#(x, y) = #\hyperref[sailMIPSznotzybool]{not\_bool}#(#\hyperref[sailMIPSzeqzybits]{eq\_bits}#(x, y)) diff --git a/sail_latex_mips/fnzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex b/sail_latex_mips/fnzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex new file mode 100644 index 00000000..26302dda --- /dev/null +++ b/sail_latex_mips/fnzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzneqzybool]{neq\_bool}# (x, y) = #\hyperref[sailMIPSznotzybool]{not\_bool}#(#\hyperref[sailMIPSzeqzybool]{eq\_bool}#(x, y)) diff --git a/sail_latex_mips/fnzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex b/sail_latex_mips/fnzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex new file mode 100644 index 00000000..af064cba --- /dev/null +++ b/sail_latex_mips/fnzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzneqzyint]{neq\_int}# (x, y) = #\hyperref[sailMIPSznotzybool]{not\_bool}#(#\hyperref[sailMIPSzeqzyint]{eq\_int}#(x, y)) diff --git a/sail_latex_mips/fnznotwordvald5d5f9e6d06ea0a5cece40166646a4b4.tex b/sail_latex_mips/fnznotwordvald5d5f9e6d06ea0a5cece40166646a4b4.tex new file mode 100644 index 00000000..e3f1a5a1 --- /dev/null +++ b/sail_latex_mips/fnznotwordvald5d5f9e6d06ea0a5cece40166646a4b4.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailMIPSzNotWordVal]{NotWordVal}# (word) = + (word[31] ^^ 32) != word[63..32] diff --git a/sail_latex_mips/fnznum_of_accessleveld0fc11b6a25cf84b4b09fd5eb5a37980.tex b/sail_latex_mips/fnznum_of_accessleveld0fc11b6a25cf84b4b09fd5eb5a37980.tex new file mode 100644 index 00000000..a5a1d8af --- /dev/null +++ b/sail_latex_mips/fnznum_of_accessleveld0fc11b6a25cf84b4b09fd5eb5a37980.tex @@ -0,0 +1,5 @@ +function num_of_AccessLevel arg# = match arg# { + User => 0, + Supervisor => 1, + Kernel => 2 +} diff --git a/sail_latex_mips/fnznum_of_capexa430f3db535161473e26bac337cc3ffe.tex b/sail_latex_mips/fnznum_of_capexa430f3db535161473e26bac337cc3ffe.tex new file mode 100644 index 00000000..eb27d2af --- /dev/null +++ b/sail_latex_mips/fnznum_of_capexa430f3db535161473e26bac337cc3ffe.tex @@ -0,0 +1,27 @@ +function num_of_CapEx arg# = match arg# { + CapEx_None => 0, + CapEx_LengthViolation => 1, + CapEx_TagViolation => 2, + CapEx_SealViolation => 3, + CapEx_TypeViolation => 4, + CapEx_CallTrap => 5, + CapEx_ReturnTrap => 6, + CapEx_TSSUnderFlow => 7, + CapEx_UserDefViolation => 8, + CapEx_TLBNoStoreCap => 9, + CapEx_InexactBounds => 10, + CapEx_GlobalViolation => 11, + CapEx_PermitExecuteViolation => 12, + CapEx_PermitLoadViolation => 13, + CapEx_PermitStoreViolation => 14, + CapEx_PermitLoadCapViolation => 15, + CapEx_PermitStoreCapViolation => 16, + CapEx_PermitStoreLocalCapViolation => 17, + CapEx_PermitSealViolation => 18, + CapEx_AccessSystemRegsViolation => 19, + CapEx_PermitCCallViolation => 20, + CapEx_AccessCCallIDCViolation => 21, + CapEx_PermitUnsealViolation => 22, + CapEx_PermitSetCIDViolation => 23, + CapEx_TLBLoadCap => 24 +} diff --git a/sail_latex_mips/fnznum_of_clearregset49e10f200544574f819f7f660071e10b.tex b/sail_latex_mips/fnznum_of_clearregset49e10f200544574f819f7f660071e10b.tex new file mode 100644 index 00000000..3dd58b89 --- /dev/null +++ b/sail_latex_mips/fnznum_of_clearregset49e10f200544574f819f7f660071e10b.tex @@ -0,0 +1,6 @@ +function num_of_ClearRegSet arg# = match arg# { + GPLo => 0, + GPHi => 1, + CLo => 2, + CHi => 3 +} diff --git a/sail_latex_mips/fnznum_of_comparisonacdefcc370a45e5aec6df49e5b5d9b12.tex b/sail_latex_mips/fnznum_of_comparisonacdefcc370a45e5aec6df49e5b5d9b12.tex new file mode 100644 index 00000000..d98bebc2 --- /dev/null +++ b/sail_latex_mips/fnznum_of_comparisonacdefcc370a45e5aec6df49e5b5d9b12.tex @@ -0,0 +1,10 @@ +function num_of_Comparison arg# = match arg# { + EQ => 0, + NE => 1, + GE => 2, + GEU => 3, + GT => 4, + LE => 5, + LT => 6, + LTU => 7 +} diff --git a/sail_latex_mips/fnznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex b/sail_latex_mips/fnznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex new file mode 100644 index 00000000..4d20546b --- /dev/null +++ b/sail_latex_mips/fnznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex @@ -0,0 +1,10 @@ +function num_of_CPtrCmpOp arg# = match arg# { + CEQ => 0, + CNE => 1, + CLT => 2, + CLE => 3, + CLTU => 4, + CLEU => 5, + CEXEQ => 6, + CNEXEQ => 7 +} diff --git a/sail_latex_mips/fnznum_of_decode_failure25ef6d99c7154f39444aafcc89394acd.tex b/sail_latex_mips/fnznum_of_decode_failure25ef6d99c7154f39444aafcc89394acd.tex new file mode 100644 index 00000000..3b5fadb3 --- /dev/null +++ b/sail_latex_mips/fnznum_of_decode_failure25ef6d99c7154f39444aafcc89394acd.tex @@ -0,0 +1,6 @@ +function num_of_decode_failure arg# = match arg# { + no_matching_pattern => 0, + unsupported_instruction => 1, + illegal_instruction => 2, + internal_error => 3 +} diff --git a/sail_latex_mips/fnznum_of_exception9e1669909ce7707290888338ffbcc8f8.tex b/sail_latex_mips/fnznum_of_exception9e1669909ce7707290888338ffbcc8f8.tex new file mode 100644 index 00000000..02bad081 --- /dev/null +++ b/sail_latex_mips/fnznum_of_exception9e1669909ce7707290888338ffbcc8f8.tex @@ -0,0 +1,21 @@ +function num_of_Exception arg# = match arg# { + Interrupt => 0, + TLBMod => 1, + TLBL => 2, + TLBS => 3, + AdEL => 4, + AdES => 5, + Sys => 6, + Bp => 7, + ResI => 8, + CpU => 9, + Ov => 10, + Tr => 11, + C2E => 12, + C2Trap => 13, + XTLBRefillL => 14, + XTLBRefillS => 15, + XTLBInvL => 16, + XTLBInvS => 17, + MCheck => 18 +} diff --git a/sail_latex_mips/fnznum_of_memaccesscaprestriction4f02267c2f3610530a623ffeb2b0f8f5.tex b/sail_latex_mips/fnznum_of_memaccesscaprestriction4f02267c2f3610530a623ffeb2b0f8f5.tex new file mode 100644 index 00000000..472a8874 --- /dev/null +++ b/sail_latex_mips/fnznum_of_memaccesscaprestriction4f02267c2f3610530a623ffeb2b0f8f5.tex @@ -0,0 +1,5 @@ +function num_of_MemAccessCapRestriction arg# = match arg# { + Unrestricted => 0, + Trap => 1, + Clear => 2 +} diff --git a/sail_latex_mips/fnznum_of_memaccesstype1f8a90d42ae8b06c64b096b6b6eb7e6b.tex b/sail_latex_mips/fnznum_of_memaccesstype1f8a90d42ae8b06c64b096b6b6eb7e6b.tex new file mode 100644 index 00000000..47b1af66 --- /dev/null +++ b/sail_latex_mips/fnznum_of_memaccesstype1f8a90d42ae8b06c64b096b6b6eb7e6b.tex @@ -0,0 +1,5 @@ +function num_of_MemAccessType arg# = match arg# { + Instruction => 0, + LoadData => 1, + StoreData => 2 +} diff --git a/sail_latex_mips/fnznum_of_wordtypef0e59bab28a4b7f5e903a6c47ab403a5.tex b/sail_latex_mips/fnznum_of_wordtypef0e59bab28a4b7f5e903a6c47ab403a5.tex new file mode 100644 index 00000000..0ed09f63 --- /dev/null +++ b/sail_latex_mips/fnznum_of_wordtypef0e59bab28a4b7f5e903a6c47ab403a5.tex @@ -0,0 +1,6 @@ +function num_of_WordType arg# = match arg# { + B => 0, + H => 1, + W => 2, + D => 3 +} diff --git a/sail_latex_mips/fnznum_of_wordtypeunaligned443855cd2b4cc93af964642e98c1b412.tex b/sail_latex_mips/fnznum_of_wordtypeunaligned443855cd2b4cc93af964642e98c1b412.tex new file mode 100644 index 00000000..f6b61ce7 --- /dev/null +++ b/sail_latex_mips/fnznum_of_wordtypeunaligned443855cd2b4cc93af964642e98c1b412.tex @@ -0,0 +1,6 @@ +function num_of_WordTypeUnaligned arg# = match arg# { + WL => 0, + WR => 1, + DL => 2, + DR => 3 +} diff --git a/sail_latex_mips/fnzones_implicitd278a7fa4099e3986b30108716d3adc5.tex b/sail_latex_mips/fnzones_implicitd278a7fa4099e3986b30108716d3adc5.tex new file mode 100644 index 00000000..4717d165 --- /dev/null +++ b/sail_latex_mips/fnzones_implicitd278a7fa4099e3986b30108716d3adc5.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzoneszyimplicit]{ones\_implicit}#(n, _) = #\hyperref[sailMIPSzsailzyones]{sail\_ones}#(n) diff --git a/sail_latex_mips/fnzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex b/sail_latex_mips/fnzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex new file mode 100644 index 00000000..33e04a5c --- /dev/null +++ b/sail_latex_mips/fnzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}# () = PCC.access_system_regs diff --git a/sail_latex_mips/fnzraise_c2_exception8c17523e86ae9ef48da8a222c10be2ee1.tex b/sail_latex_mips/fnzraise_c2_exception8c17523e86ae9ef48da8a222c10be2ee1.tex new file mode 100644 index 00000000..b2b3fbc2 --- /dev/null +++ b/sail_latex_mips/fnzraise_c2_exception8c17523e86ae9ef48da8a222c10be2ee1.tex @@ -0,0 +1,15 @@ +function #\hyperref[sailMIPSzraisezyc2zyexception8]{raise\_c2\_exception8}#(capEx, regnum) = + { + if trace then { + #\hyperref[sailMIPSzprerr]{prerr}#(" C2Ex "); + #\hyperref[sailMIPSzprerr]{prerr}#(#\hyperref[sailMIPSzstringzyofzycapex]{string\_of\_capex}#(capEx)); + #\hyperref[sailMIPSzprerr]{prerr}#(" reg: "); + #\hyperref[sailMIPSzprerrzyendline]{prerr\_endline}#(#\hyperref[sailMIPSzBitStr]{BitStr}#(regnum)); + }; + CapCause->#\hyperref[sailMIPSzExcCode]{ExcCode}#() = #\hyperref[sailMIPSzCapExCode]{CapExCode}#(capEx); + CapCause->#\hyperref[sailMIPSzRegNum]{RegNum}#() = regnum; + let mipsEx = + if ((capEx == CapEx_CallTrap) | (capEx == CapEx_ReturnTrap)) + then C2Trap else C2E in + #\hyperref[sailMIPSzSignalException]{SignalException}#(mipsEx); + } diff --git a/sail_latex_mips/fnzraise_c2_exception_badaddrd8f6a78fc18067d06626bbc713515a9a.tex b/sail_latex_mips/fnzraise_c2_exception_badaddrd8f6a78fc18067d06626bbc713515a9a.tex new file mode 100644 index 00000000..461135ac --- /dev/null +++ b/sail_latex_mips/fnzraise_c2_exception_badaddrd8f6a78fc18067d06626bbc713515a9a.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailMIPSzraisezyc2zyexceptionzybadaddr]{raise\_c2\_exception\_badaddr}#(capEx, regnum, badAddr) = { + CP0BadVAddr = badAddr; + #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(capEx, regnum); +} diff --git a/sail_latex_mips/fnzraise_c2_exception_noregaf4f146af9490f033f39a46e2216dccb.tex b/sail_latex_mips/fnzraise_c2_exception_noregaf4f146af9490f033f39a46e2216dccb.tex new file mode 100644 index 00000000..adeaa882 --- /dev/null +++ b/sail_latex_mips/fnzraise_c2_exception_noregaf4f146af9490f033f39a46e2216dccb.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailMIPSzraisezyc2zyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(capEx) = + #\hyperref[sailMIPSzraisezyc2zyexception8]{raise\_c2\_exception8}#(capEx, 0xff) diff --git a/sail_latex_mips/fnzraise_c2_exceptionb9a632810adbd99dc25a5f3a28ddb9f2.tex b/sail_latex_mips/fnzraise_c2_exceptionb9a632810adbd99dc25a5f3a28ddb9f2.tex new file mode 100644 index 00000000..3fdfef71 --- /dev/null +++ b/sail_latex_mips/fnzraise_c2_exceptionb9a632810adbd99dc25a5f3a28ddb9f2.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailMIPSzraisezyc2zyexception]{raise\_c2\_exception}#(capEx, regnum) = + let reg8 = 0b000 @ regnum in + #\hyperref[sailMIPSzraisezyc2zyexception8]{raise\_c2\_exception8}#(capEx, reg8) diff --git a/sail_latex_mips/fnzreadcapreg0fe08ef5bf06c41ffed8e12baf8ddd85.tex b/sail_latex_mips/fnzreadcapreg0fe08ef5bf06c41ffed8e12baf8ddd85.tex new file mode 100644 index 00000000..09230edd --- /dev/null +++ b/sail_latex_mips/fnzreadcapreg0fe08ef5bf06c41ffed8e12baf8ddd85.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailMIPSzreadCapReg]{readCapReg}#(n) = + if (n == 0b00000) then + null_cap + else + let i = #\hyperref[sailMIPSzunsigned]{unsigned}#(n) in + *(CapRegs[i]) diff --git a/sail_latex_mips/fnzreadcapregddc65f046a34609a089c9bf681a6893bca6.tex b/sail_latex_mips/fnzreadcapregddc65f046a34609a089c9bf681a6893bca6.tex new file mode 100644 index 00000000..5154fe7f --- /dev/null +++ b/sail_latex_mips/fnzreadcapregddc65f046a34609a089c9bf681a6893bca6.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailMIPSzreadCapRegDDC]{readCapRegDDC}#(n) = + let i = #\hyperref[sailMIPSzunsigned]{unsigned}#(n) in + *(CapRegs[i]) /* NB CapRegs[0] is points to DDC */ diff --git a/sail_latex_mips/fnzrgpr9bb3f998022d0674cf437905d0ab2e62.tex b/sail_latex_mips/fnzrgpr9bb3f998022d0674cf437905d0ab2e62.tex new file mode 100644 index 00000000..cb319146 --- /dev/null +++ b/sail_latex_mips/fnzrgpr9bb3f998022d0674cf437905d0ab2e62.tex @@ -0,0 +1,4 @@ +function rGPR idx = { + let i as atom(_) = #\hyperref[sailMIPSzunsigned]{unsigned}#(idx) in + if i == 0 then 0x0000000000000000 else GPR[i] +} diff --git a/sail_latex_mips/fnzsail_maske146b73afc824e90813dd8234bfa3053.tex b/sail_latex_mips/fnzsail_maske146b73afc824e90813dd8234bfa3053.tex new file mode 100644 index 00000000..42e70223 --- /dev/null +++ b/sail_latex_mips/fnzsail_maske146b73afc824e90813dd8234bfa3053.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzsailzymask]{sail\_mask}#(len, v) = if len <= #\hyperref[sailMIPSzlength]{length}#(v) then #\hyperref[sailMIPSztruncate]{truncate}#(v, len) else #\hyperref[sailMIPSzsailzyzzerozyextend]{sail\_zero\_extend}#(v, len) diff --git a/sail_latex_mips/fnzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex b/sail_latex_mips/fnzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex new file mode 100644 index 00000000..bdddb2e1 --- /dev/null +++ b/sail_latex_mips/fnzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzsailzyones]{sail\_ones}#(n) = #\hyperref[sailMIPSznotzyvec]{not\_vec}#(#\hyperref[sailMIPSzsailzyzzeros]{sail\_zeros}#(n)) diff --git a/sail_latex_mips/fnzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex b/sail_latex_mips/fnzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex new file mode 100644 index 00000000..044bb0fd --- /dev/null +++ b/sail_latex_mips/fnzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailMIPSzsealCap]{sealCap}#(cap, otyp) : (Capability, #\hyperref[sailMIPSzbits]{bits}#(24)) -> (bool, Capability) = + (true, {cap with sealed=true, otype=otyp[17..0]}) diff --git a/sail_latex_mips/fnzset_cp0epc28b8527a6fc9d9c7e3708c9379630443.tex b/sail_latex_mips/fnzset_cp0epc28b8527a6fc9d9c7e3708c9379630443.tex new file mode 100644 index 00000000..53d5ae7b --- /dev/null +++ b/sail_latex_mips/fnzset_cp0epc28b8527a6fc9d9c7e3708c9379630443.tex @@ -0,0 +1,13 @@ +function #\hyperref[sailMIPSzsetzyCP0EPC]{set\_CP0EPC}# (newEPC) = { + let (representable, newEPCC) = #\hyperref[sailMIPSzsetCapOffset]{setCapOffset}#(EPCC, newEPC); + /* Unrepresentable EPCC should only happen if CP0EPC is + written with something far outside bounds of EPCC. Exceptions should + not cause an unrepresentable EPCC because the PC of the faulting + instruction is necessarily in-#\hyperref[sailMIPSzbounds]{bounds}# (or nearly in-bounds). For jumps + that take the PC out-of-bounds the CP2 exception occurs on the jump, + not the target. */ + EPCC = if representable then + {newEPCC with tag = newEPCC.tag & not(newEPCC.sealed)} + else + #\hyperref[sailMIPSzunrepCap]{unrepCap}#(newEPCC); +} diff --git a/sail_latex_mips/fnzset_cp0errorepc99aeab8b8e922eeb71df49885a629b5d.tex b/sail_latex_mips/fnzset_cp0errorepc99aeab8b8e922eeb71df49885a629b5d.tex new file mode 100644 index 00000000..abd778c5 --- /dev/null +++ b/sail_latex_mips/fnzset_cp0errorepc99aeab8b8e922eeb71df49885a629b5d.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailMIPSzsetzyCP0ErrorEPC]{set\_CP0ErrorEPC}# (v) = { + let (representable, newErrorEPCC) = #\hyperref[sailMIPSzsetCapOffset]{setCapOffset}#(ErrorEPCC, v); + ErrorEPCC = if representable then + {newErrorEPCC with tag = newErrorEPCC.tag & not(newErrorEPCC.sealed)} + else + #\hyperref[sailMIPSzunrepCap]{unrepCap}#(newErrorEPCC); +} diff --git a/sail_latex_mips/fnzset_next_pcce92395a303a64d3216ddb0601b37e83f.tex b/sail_latex_mips/fnzset_next_pcce92395a303a64d3216ddb0601b37e83f.tex new file mode 100644 index 00000000..2edd325b --- /dev/null +++ b/sail_latex_mips/fnzset_next_pcce92395a303a64d3216ddb0601b37e83f.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailMIPSzsetzynextzypcc]{set\_next\_pcc}#(newPCC) = { + NextPCC = newPCC; + DelayedPCC = newPCC; /* always write DelayedPCC together with NextPCC so + that non-capability branches don't override PCC */ +} diff --git a/sail_latex_mips/fnzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex b/sail_latex_mips/fnzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex new file mode 100644 index 00000000..fef7a876 --- /dev/null +++ b/sail_latex_mips/fnzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailMIPSzsetCapAddr]{setCapAddr}#(c, addr) = + let newCap = { c with address = addr } in + let representable = #\hyperref[sailMIPSzcapBoundsEqual]{capBoundsEqual}#(c, newCap) in + (representable, newCap) diff --git a/sail_latex_mips/fnzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex b/sail_latex_mips/fnzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex new file mode 100644 index 00000000..db96abf8 --- /dev/null +++ b/sail_latex_mips/fnzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex @@ -0,0 +1,62 @@ +function #\hyperref[sailMIPSzsetCapBounds]{setCapBounds}#(cap, base, top) : (Capability, #\hyperref[sailMIPSzbits]{bits}#(64), #\hyperref[sailMIPSzbits]{bits}#(65)) -> (bool, Capability) = { + /* {cap with base=base; length=(#\hyperref[sailMIPSzbits]{bits}#(64)) length; offset=0} */ + let base65 = 0b0 @ base; + let length = top - base65; + /* Find an exponent that will put the most significant bit of length + second from the top as assumed during decoding. We ignore the bottom + MW - 1 bits because those are handled by the ie = 0 format. */ + let e = 52 - #\hyperref[sailMIPSzcountzyleadingzyzzeros]{count\_leading\_zeros}#(length[64..13]); + // Use use internal exponent if e is non-zero or if e is zero but + // but the implied bit of length is not #\hyperref[sailMIPSzzzero]{zero}# (denormal vs. normal case) + let ie = (e != 0) | length[12]; + + /* The non-ie e == 0 case is easy. It is exact so just extract relevant bits. */ + Bbits = #\hyperref[sailMIPSztruncate]{truncate}#(base, 14); + Tbits = #\hyperref[sailMIPSztruncate]{truncate}#(top, 14); + lostSignificantTop : bool = false; + lostSignificantBase : bool = false; + incE : bool = false; + + if ie then { + /* the internal exponent case is trickier */ + + /* Extract B and T #\hyperref[sailMIPSzbits]{bits}# (we lose 3 bits of each to store the exponent) */ + B_ie = #\hyperref[sailMIPSztruncate]{truncate}#(base >> (e + 3), 11); + T_ie = #\hyperref[sailMIPSztruncate]{truncate}#(top >> (e + 3), 11); + + /* Find out whether we have lost significant bits of base and top using a + mask of bits that we will #\hyperref[sailMIPSzlose]{lose}# (including 3 extra for exp). */ + maskLo : #\hyperref[sailMIPSzbits]{bits}#(65) = #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(#\hyperref[sailMIPSzones]{ones}#(e + 3)); + z65 : #\hyperref[sailMIPSzbits]{bits}#(65) = #\hyperref[sailMIPSzzzeros]{zeros}#(); + lostSignificantBase = (base65 & maskLo) != z65; + lostSignificantTop = (top & maskLo) != z65; + + if lostSignificantTop then { + /* we must increment T to make sure it is still above top even with lost bits. + It might wrap around but if that makes B> (e + 4), 11); + let incT : range(0,1) = if lostSignificantTop then 1 else 0; + T_ie = #\hyperref[sailMIPSztruncate]{truncate}#(top >> (e + 4), 11) + incT; + }; + + Bbits = B_ie @ 0b000; + Tbits = T_ie @ 0b000; + }; + let newCap = {cap with address=base, E=#\hyperref[sailMIPSztozybits]{to\_bits}#(6, if incE then e + 1 else e), B=Bbits, T=Tbits, internal_e=ie}; + let exact = not(lostSignificantBase | lostSignificantTop); + (exact, newCap) +} diff --git a/sail_latex_mips/fnzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex b/sail_latex_mips/fnzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex new file mode 100644 index 00000000..96e6bec1 --- /dev/null +++ b/sail_latex_mips/fnzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzsetCapFlags]{setCapFlags}#(cap, flags) = cap diff --git a/sail_latex_mips/fnzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex b/sail_latex_mips/fnzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex new file mode 100644 index 00000000..a351e3a1 --- /dev/null +++ b/sail_latex_mips/fnzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailMIPSzsetCapOffset]{setCapOffset}#(c, offset) : (Capability, #\hyperref[sailMIPSzbits]{bits}#(64)) -> (bool, Capability) = + let base64 : #\hyperref[sailMIPSzbits]{bits}#(64) = #\hyperref[sailMIPSztozybits]{to\_bits}#(64, #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(c)) in + let newAddress : #\hyperref[sailMIPSzbits]{bits}#(64) = base64 + offset in + let newCap = { c with address = newAddress } in + let representable = #\hyperref[sailMIPSzcapBoundsEqual]{capBoundsEqual}#(c, newCap) in +/* let representable = #\hyperref[sailMIPSzfastRepCheck]{fastRepCheck}#(c, (newAddress - c.address)) in*/ + (representable, newCap) diff --git a/sail_latex_mips/fnzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex b/sail_latex_mips/fnzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex new file mode 100644 index 00000000..0c300967 --- /dev/null +++ b/sail_latex_mips/fnzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex @@ -0,0 +1,17 @@ +function #\hyperref[sailMIPSzsetCapPerms]{setCapPerms}#(cap, perms) : (Capability, #\hyperref[sailMIPSzbits]{bits}#(31)) -> Capability = + { cap with + uperms = perms[18..15], + /* 14..12 reserved -- ignore */ + permit_set_CID = perms[11], + access_system_regs = perms[10], + permit_unseal = perms[9], + permit_ccall = perms[8], + permit_seal = perms[7], + permit_store_local_cap = perms[6], + permit_store_cap = perms[5], + permit_load_cap = perms[4], + permit_store = perms[3], + permit_load = perms[2], + permit_execute = perms[1], + global = perms[0] + } diff --git a/sail_latex_mips/fnzsignalexception586f3a4c7da76085e25c98aff442160c.tex b/sail_latex_mips/fnzsignalexception586f3a4c7da76085e25c98aff442160c.tex new file mode 100644 index 00000000..e9b0aec1 --- /dev/null +++ b/sail_latex_mips/fnzsignalexception586f3a4c7da76085e25c98aff442160c.tex @@ -0,0 +1,40 @@ +function #\hyperref[sailMIPSzSignalException]{SignalException}# (ex) = { + #\hyperref[sailMIPSztraceException]{traceException}#(ex); + /* Only update EPC and BD if not already in EXL mode */ + if (~ (CP0Status.#\hyperref[sailMIPSzEXL]{EXL}#())) then + { + let epc : #\hyperref[sailMIPSzbits]{bits}#(64) = if (InBranchDelay[0]) then + { + CP0Cause->#\hyperref[sailMIPSzBD]{BD}#() = 0b1; + PC - 4 + } + else { + CP0Cause->#\hyperref[sailMIPSzBD]{BD}#() = 0b0; + PC + }; + let (representable, newEPCC) = #\hyperref[sailMIPSzsetCapOffset]{setCapOffset}#(PCC, epc); + /* EPCC should almost always be representable because PC should always be nearly in bounds. + It might happen if KCC does not include the exception vector which would probably + result in an exception loop. */ + if (not(representable)) then + #\hyperref[sailMIPSzprint]{print}#("UNREPRESENTABLE EPCC!"); + /* Similarly PCC should not be sealed unless EPCC was sealed on ERET or KCC was sealed + on exception */ + if (newEPCC.sealed) then + #\hyperref[sailMIPSzprint]{print}#("SEALED PCC!"); + /* If either of the above cases happens we clear the tag on EPCC to preserve invariants. */ + EPCC = if representable & not(newEPCC.sealed) then newEPCC else #\hyperref[sailMIPSzunrepCap]{unrepCap}#(newEPCC); + }; + /* Fill in BadInstr + BadInstrP. */ + #\hyperref[sailMIPSzupdateBadInstr]{updateBadInstr}#(); + let vectorOffset = #\hyperref[sailMIPSzexceptionVectorOffset]{exceptionVectorOffset}#(ex); + let vectorBase = #\hyperref[sailMIPSzexceptionVectorBase]{exceptionVectorBase}#(); + /* On CHERI we have to subtract KCC.base so that we end up at the + right absolute vector address after indirecting via new PCC */ + let kccBase = #\hyperref[sailMIPSzgetCapBase]{getCapBase}#(KCC) in + NextPC = vectorBase + #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(vectorOffset) - #\hyperref[sailMIPSztozybits]{to\_bits}#(64, kccBase); + #\hyperref[sailMIPSzsetzynextzypcc]{set\_next\_pcc}#(KCC); + CP0Cause->#\hyperref[sailMIPSzExcCode]{ExcCode}#() = #\hyperref[sailMIPSzExceptionCode]{ExceptionCode}#(ex); + CP0Status->#\hyperref[sailMIPSzEXL]{EXL}#() = 0b1; + throw (#\hyperref[sailMIPSzISAException]{ISAException}#()); +} diff --git a/sail_latex_mips/fnzsignalexceptionbadaddr6cdef872a446a09f2a94b2675a181fe8.tex b/sail_latex_mips/fnzsignalexceptionbadaddr6cdef872a446a09f2a94b2675a181fe8.tex new file mode 100644 index 00000000..b8330a01 --- /dev/null +++ b/sail_latex_mips/fnzsignalexceptionbadaddr6cdef872a446a09f2a94b2675a181fe8.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(ex, badAddr) = + { + CP0BadVAddr = badAddr; + #\hyperref[sailMIPSzSignalException]{SignalException}#(ex); + } diff --git a/sail_latex_mips/fnzsignalexceptiontlbddf65d69af94bbb390cc24d557f99883.tex b/sail_latex_mips/fnzsignalexceptiontlbddf65d69af94bbb390cc24d557f99883.tex new file mode 100644 index 00000000..8b98e55b --- /dev/null +++ b/sail_latex_mips/fnzsignalexceptiontlbddf65d69af94bbb390cc24d557f99883.tex @@ -0,0 +1,9 @@ +function #\hyperref[sailMIPSzSignalExceptionTLB]{SignalExceptionTLB}#(ex, badAddr) = { + CP0BadVAddr = badAddr; + TLBContext->#\hyperref[sailMIPSzBadVPN2]{BadVPN2}#() = (badAddr[31..13]); + TLBXContext->#\hyperref[sailMIPSzXBadVPN2]{XBadVPN2}#()= (badAddr[39..13]); + TLBXContext->#\hyperref[sailMIPSzXR]{XR}#() = (badAddr[63..62]); + TLBEntryHi->#\hyperref[sailMIPSzR]{R}#() = (badAddr[63..62]); + TLBEntryHi->#\hyperref[sailMIPSzVPN2]{VPN2}#() = (badAddr[39..13]); + #\hyperref[sailMIPSzSignalException]{SignalException}#(ex); +} diff --git a/sail_latex_mips/fnzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex b/sail_latex_mips/fnzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex new file mode 100644 index 00000000..390a66af --- /dev/null +++ b/sail_latex_mips/fnzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailMIPSzslicezymask]{slice\_mask}#(n,i,l) = + if l >= n then { + #\hyperref[sailMIPSzsailzyshiftleft]{sail\_shiftleft}#(#\hyperref[sailMIPSzsailzyones]{sail\_ones}#(n), i) + } else { + let one : #\hyperref[sailMIPSzbits]{bits}#('n) = #\hyperref[sailMIPSzsailzymask]{sail\_mask}#(n, [bitone] : #\hyperref[sailMIPSzbits]{bits}#(1)) in + #\hyperref[sailMIPSzsailzyshiftleft]{sail\_shiftleft}#(#\hyperref[sailMIPSzsubzybits]{sub\_bits}#(#\hyperref[sailMIPSzsailzyshiftleft]{sail\_shiftleft}#(one, l), one), i) + } diff --git a/sail_latex_mips/fnzstrccargs8d27f740eb5185eb67906b78fb166677.tex b/sail_latex_mips/fnzstrccargs8d27f740eb5185eb67906b78fb166677.tex new file mode 100644 index 00000000..ff61cfb1 --- /dev/null +++ b/sail_latex_mips/fnzstrccargs8d27f740eb5185eb67906b78fb166677.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrCCArgs]{strCCArgs}#(cd : CapRegEnc, c1 : CapRegEnc) -> string = #\hyperref[sailMIPSzstrCReg]{strCReg}#(cd) ^ ", " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(c1) diff --git a/sail_latex_mips/fnzstrcccargsd0cf13cbe0c477ce0624778eee44a85e.tex b/sail_latex_mips/fnzstrcccargsd0cf13cbe0c477ce0624778eee44a85e.tex new file mode 100644 index 00000000..c09e2341 --- /dev/null +++ b/sail_latex_mips/fnzstrcccargsd0cf13cbe0c477ce0624778eee44a85e.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrCCCArgs]{strCCCArgs}#(cd : CapRegEnc, c1 : CapRegEnc, c2 : CapRegEnc) -> string = #\hyperref[sailMIPSzstrCReg]{strCReg}#(cd) ^ ", " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(c1) ^ ", " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(c2) diff --git a/sail_latex_mips/fnzstrcciargs33bcd057cc20ec3a9ddc520c721764a9.tex b/sail_latex_mips/fnzstrcciargs33bcd057cc20ec3a9ddc520c721764a9.tex new file mode 100644 index 00000000..93f6cc27 --- /dev/null +++ b/sail_latex_mips/fnzstrcciargs33bcd057cc20ec3a9ddc520c721764a9.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrCCIArgs]{strCCIArgs}#(cd, cs, imm) = #\hyperref[sailMIPSzstrCReg]{strCReg}#(cd) ^ ", " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(cs) ^ ", " ^ #\hyperref[sailMIPSzdeczystr]{dec\_str}#(#\hyperref[sailMIPSzsigned]{signed}#(imm)) diff --git a/sail_latex_mips/fnzstrcciuargs995341ac60a90e598fe5209db4db77a3.tex b/sail_latex_mips/fnzstrcciuargs995341ac60a90e598fe5209db4db77a3.tex new file mode 100644 index 00000000..64ca50af --- /dev/null +++ b/sail_latex_mips/fnzstrcciuargs995341ac60a90e598fe5209db4db77a3.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrCCIUArgs]{strCCIUArgs}#(cd, cs, imm) = #\hyperref[sailMIPSzstrCReg]{strCReg}#(cd) ^ ", " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(cs) ^ ", " ^ #\hyperref[sailMIPSzhexzystr]{hex\_str}#(#\hyperref[sailMIPSzunsigned]{unsigned}#(imm)) diff --git a/sail_latex_mips/fnzstrccrargs496b2890b8e21e5bd6d7197ea4c075c8.tex b/sail_latex_mips/fnzstrccrargs496b2890b8e21e5bd6d7197ea4c075c8.tex new file mode 100644 index 00000000..ab0aa69f --- /dev/null +++ b/sail_latex_mips/fnzstrccrargs496b2890b8e21e5bd6d7197ea4c075c8.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrCCRArgs]{strCCRArgs}#(cd : CapRegEnc, c1 : CapRegEnc, r2 : IntRegEnc) -> string = #\hyperref[sailMIPSzstrCReg]{strCReg}#(cd) ^ ", " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(c1) ^ ", " ^ #\hyperref[sailMIPSzstrReg]{strReg}#(r2) diff --git a/sail_latex_mips/fnzstrcmp377172000af45c28fe84b78c43e6af4d.tex b/sail_latex_mips/fnzstrcmp377172000af45c28fe84b78c43e6af4d.tex new file mode 100644 index 00000000..8f3f1c15 --- /dev/null +++ b/sail_latex_mips/fnzstrcmp377172000af45c28fe84b78c43e6af4d.tex @@ -0,0 +1,10 @@ +function #\hyperref[sailMIPSzstrCmp]{strCmp}# (cmp : Comparison) -> string = match cmp { + EQ => "eq", + NE => "ne", + GE => "ge", + GEU => "geu", + GT => "gt", + LE => "le", + LT => "lt", + LTU => "ltu" +} diff --git a/sail_latex_mips/fnzstrcrargsa5dba43a853a6048828d7d473fcaedfb.tex b/sail_latex_mips/fnzstrcrargsa5dba43a853a6048828d7d473fcaedfb.tex new file mode 100644 index 00000000..a97f1070 --- /dev/null +++ b/sail_latex_mips/fnzstrcrargsa5dba43a853a6048828d7d473fcaedfb.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrCRArgs]{strCRArgs}#(cd : CapRegEnc, r1 : IntRegEnc) -> string = #\hyperref[sailMIPSzstrCReg]{strCReg}#(cd) ^ ", " ^ #\hyperref[sailMIPSzstrReg]{strReg}#(r1) diff --git a/sail_latex_mips/fnzstrcreg6eee441123c442c07d3b63b65e2c6a32.tex b/sail_latex_mips/fnzstrcreg6eee441123c442c07d3b63b65e2c6a32.tex new file mode 100644 index 00000000..1086a01b --- /dev/null +++ b/sail_latex_mips/fnzstrcreg6eee441123c442c07d3b63b65e2c6a32.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrCReg]{strCReg}#(r) : regno -> string = #\hyperref[sailMIPSzconcatzystrzydec]{concat\_str\_dec}#("$c", #\hyperref[sailMIPSzunsigned]{unsigned}#(r)) diff --git a/sail_latex_mips/fnzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex b/sail_latex_mips/fnzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex new file mode 100644 index 00000000..b1ad129d --- /dev/null +++ b/sail_latex_mips/fnzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex @@ -0,0 +1,28 @@ +function #\hyperref[sailMIPSzstringzyofzycapex]{string\_of\_capex}# (ex) : CapEx -> string = + match ex { + CapEx_None => "None" , + CapEx_LengthViolation => "LengthViolation" , + CapEx_TagViolation => "TagViolation" , + CapEx_SealViolation => "SealViolation" , + CapEx_TypeViolation => "TypeViolation" , + CapEx_CallTrap => "CallTrap" , + CapEx_ReturnTrap => "ReturnTrap" , + CapEx_TSSUnderFlow => "TSSUnderFlow" , + CapEx_UserDefViolation => "UserDefViolation" , + CapEx_TLBNoStoreCap => "TLBNoStoreCap" , + CapEx_InexactBounds => "InexactBounds" , + CapEx_GlobalViolation => "GlobalViolation" , + CapEx_PermitExecuteViolation => "PermitExecuteViolation" , + CapEx_PermitLoadViolation => "PermitLoadViolation" , + CapEx_PermitStoreViolation => "PermitStoreViolation" , + CapEx_PermitLoadCapViolation => "PermitLoadCapViolation" , + CapEx_PermitStoreCapViolation => "PermitStoreCapViolation" , + CapEx_PermitStoreLocalCapViolation => "PermitStoreLocalCapViolation", + CapEx_PermitSealViolation => "PermitSealViolation" , + CapEx_AccessSystemRegsViolation => "AccessSystemRegsViolation" , + CapEx_PermitCCallViolation => "PermitCCallViolation" , + CapEx_AccessCCallIDCViolation => "AccessCCallIDCViolation" , + CapEx_PermitUnsealViolation => "PermitUnsealViolation" , + CapEx_PermitSetCIDViolation => "PermitSetCIDViolation" , + CapEx_TLBLoadCap => "TLBLoadCap" + } diff --git a/sail_latex_mips/fnzstring_of_exception7734103b8f1c3a7c884e4dea77d7cf9d.tex b/sail_latex_mips/fnzstring_of_exception7734103b8f1c3a7c884e4dea77d7cf9d.tex new file mode 100644 index 00000000..8374dc4e --- /dev/null +++ b/sail_latex_mips/fnzstring_of_exception7734103b8f1c3a7c884e4dea77d7cf9d.tex @@ -0,0 +1,22 @@ +function #\hyperref[sailMIPSzstringzyofzyexception]{string\_of\_exception}#(ex) : Exception -> string = + match ex { + Interrupt => "Interrupt", + TLBMod => "TLBMod", + TLBL => "TLBL", + TLBS => "TLBS", + AdEL => "AdEL", + AdES => "AdES", + Sys => "Sys", + Bp => "Bp ", + ResI => "ResI", + CpU => "CpU", + Ov => "Ov", + Tr => "Tr", + C2E => "C2E", + C2Trap => "C2Trap", + XTLBRefillL => "XTLBRefillL", + XTLBRefillS => "XTLBRefillS", + XTLBInvL => "XTLBInvL", + XTLBInvS => "XTLBInvS", + MCheck => "MCheck" + } diff --git a/sail_latex_mips/fnzstrmemargs353ff7043a1935f05717327694c74036.tex b/sail_latex_mips/fnzstrmemargs353ff7043a1935f05717327694c74036.tex new file mode 100644 index 00000000..cd6295d7 --- /dev/null +++ b/sail_latex_mips/fnzstrmemargs353ff7043a1935f05717327694c74036.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrMemArgs]{strMemArgs}#(base, rt, offset) = #\hyperref[sailMIPSzstrReg]{strReg}#(rt) ^ ", " ^ #\hyperref[sailMIPSzdeczystr]{dec\_str}#(#\hyperref[sailMIPSzsigned]{signed}#(offset)) ^ "(" ^ #\hyperref[sailMIPSzstrReg]{strReg}#(base) ^ ")" diff --git a/sail_latex_mips/fnzstrrcargs77cbd4ae00a8aeed40f03673c45f3bf3.tex b/sail_latex_mips/fnzstrrcargs77cbd4ae00a8aeed40f03673c45f3bf3.tex new file mode 100644 index 00000000..4477d54c --- /dev/null +++ b/sail_latex_mips/fnzstrrcargs77cbd4ae00a8aeed40f03673c45f3bf3.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrRCArgs]{strRCArgs}#(rd : IntRegEnc, c1 : CapRegEnc) -> string = #\hyperref[sailMIPSzstrReg]{strReg}#(rd) ^ ", " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(c1) diff --git a/sail_latex_mips/fnzstrrccargscb2c61998351777a60f6fb0c1be5bc73.tex b/sail_latex_mips/fnzstrrccargscb2c61998351777a60f6fb0c1be5bc73.tex new file mode 100644 index 00000000..071c67c8 --- /dev/null +++ b/sail_latex_mips/fnzstrrccargscb2c61998351777a60f6fb0c1be5bc73.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrRCCArgs]{strRCCArgs}#(rd : IntRegEnc, c1 : CapRegEnc, c2 : CapRegEnc) -> string = #\hyperref[sailMIPSzstrReg]{strReg}#(rd) ^ ", " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(c1) ^ ", " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(c2) diff --git a/sail_latex_mips/fnzstrrcrargs2a6690343bcd1d4f5aaa9410842cee4f.tex b/sail_latex_mips/fnzstrrcrargs2a6690343bcd1d4f5aaa9410842cee4f.tex new file mode 100644 index 00000000..45f300b2 --- /dev/null +++ b/sail_latex_mips/fnzstrrcrargs2a6690343bcd1d4f5aaa9410842cee4f.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrRCRArgs]{strRCRArgs}#(rd : IntRegEnc, c1 : CapRegEnc, r2 : IntRegEnc) -> string = #\hyperref[sailMIPSzstrReg]{strReg}#(rd) ^ ", " ^ #\hyperref[sailMIPSzstrCReg]{strCReg}#(c1) ^ ", " ^ #\hyperref[sailMIPSzstrReg]{strReg}#(r2) diff --git a/sail_latex_mips/fnzstrregedcb07cf94fecef4256c866403497f4d.tex b/sail_latex_mips/fnzstrregedcb07cf94fecef4256c866403497f4d.tex new file mode 100644 index 00000000..a1c812ac --- /dev/null +++ b/sail_latex_mips/fnzstrregedcb07cf94fecef4256c866403497f4d.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrReg]{strReg}#(r) : regno -> string = #\hyperref[sailMIPSzconcatzystrzydec]{concat\_str\_dec}#("$", #\hyperref[sailMIPSzunsigned]{unsigned}#(r)) diff --git a/sail_latex_mips/fnzstrriargsf5ce4d067df93e7be3e1beacd5b4d9a7.tex b/sail_latex_mips/fnzstrriargsf5ce4d067df93e7be3e1beacd5b4d9a7.tex new file mode 100644 index 00000000..733b51c3 --- /dev/null +++ b/sail_latex_mips/fnzstrriargsf5ce4d067df93e7be3e1beacd5b4d9a7.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrRIArgs]{strRIArgs}#(rd, imm) = #\hyperref[sailMIPSzstrReg]{strReg}#(rd) ^ ", " ^ #\hyperref[sailMIPSzhexzystr]{hex\_str}#(#\hyperref[sailMIPSzunsigned]{unsigned}#(imm)) diff --git a/sail_latex_mips/fnzstrrrargs01af3a4171de69de622a434d53850810.tex b/sail_latex_mips/fnzstrrrargs01af3a4171de69de622a434d53850810.tex new file mode 100644 index 00000000..fa6643d0 --- /dev/null +++ b/sail_latex_mips/fnzstrrrargs01af3a4171de69de622a434d53850810.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrRRArgs]{strRRArgs}#(rd : IntRegEnc, r1 : IntRegEnc) -> string = #\hyperref[sailMIPSzstrReg]{strReg}#(rd) ^ ", " ^ #\hyperref[sailMIPSzstrReg]{strReg}#(r1) diff --git a/sail_latex_mips/fnzstrrriargs4a7c2ee7b410ff0bb51f74553cdca297.tex b/sail_latex_mips/fnzstrrriargs4a7c2ee7b410ff0bb51f74553cdca297.tex new file mode 100644 index 00000000..db51e3c1 --- /dev/null +++ b/sail_latex_mips/fnzstrrriargs4a7c2ee7b410ff0bb51f74553cdca297.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrRRIArgs]{strRRIArgs}#(rs, rd, imm) = #\hyperref[sailMIPSzstrReg]{strReg}#(rd) ^ ", " ^ #\hyperref[sailMIPSzstrReg]{strReg}#(rs) ^ ", " ^ #\hyperref[sailMIPSzdeczystr]{dec\_str}#(#\hyperref[sailMIPSzsigned]{signed}#(imm)) diff --git a/sail_latex_mips/fnzstrrriuargs3f59ed041a358c4238ca651c777a80e7.tex b/sail_latex_mips/fnzstrrriuargs3f59ed041a358c4238ca651c777a80e7.tex new file mode 100644 index 00000000..d96c1b1b --- /dev/null +++ b/sail_latex_mips/fnzstrrriuargs3f59ed041a358c4238ca651c777a80e7.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrRRIUArgs]{strRRIUArgs}#(rs, rd, imm) = #\hyperref[sailMIPSzstrReg]{strReg}#(rd) ^ ", " ^ #\hyperref[sailMIPSzstrReg]{strReg}#(rs) ^ ", " ^ #\hyperref[sailMIPSzhexzystr]{hex\_str}#(#\hyperref[sailMIPSzunsigned]{unsigned}#(imm)) diff --git a/sail_latex_mips/fnzstrrrrargsfab462065fa0ad4bda2870b02f212fd9.tex b/sail_latex_mips/fnzstrrrrargsfab462065fa0ad4bda2870b02f212fd9.tex new file mode 100644 index 00000000..02512944 --- /dev/null +++ b/sail_latex_mips/fnzstrrrrargsfab462065fa0ad4bda2870b02f212fd9.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzstrRRRArgs]{strRRRArgs}#(r2 : regno, r1 : regno, rd : regno) -> string = #\hyperref[sailMIPSzstrReg]{strReg}#(rd) ^ ", " ^ #\hyperref[sailMIPSzstrReg]{strReg}#(r1) ^ ", " ^ #\hyperref[sailMIPSzstrReg]{strReg}#(r2) diff --git a/sail_latex_mips/fnzstrwordtype0dceaa7680ceade7afd7f75be57ac461.tex b/sail_latex_mips/fnzstrwordtype0dceaa7680ceade7afd7f75be57ac461.tex new file mode 100644 index 00000000..d149c1d9 --- /dev/null +++ b/sail_latex_mips/fnzstrwordtype0dceaa7680ceade7afd7f75be57ac461.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailMIPSzstrWordType]{strWordType}#(w : WordType) -> string = match w { + B => "b", + H => "h", + W => "w", + D => "d" +} diff --git a/sail_latex_mips/fnzsupported_instructionsa556d55bb4bf818f15e811f8fa119862.tex b/sail_latex_mips/fnzsupported_instructionsa556d55bb4bf818f15e811f8fa119862.tex new file mode 100644 index 00000000..9d15520b --- /dev/null +++ b/sail_latex_mips/fnzsupported_instructionsa556d55bb4bf818f15e811f8fa119862.tex @@ -0,0 +1 @@ +function supported_instructions instr = #\hyperref[sailMIPSzSome]{Some}#(instr) diff --git a/sail_latex_mips/fnztlbentrymatch022ae8f81d6f9221e858534a26d34f7f.tex b/sail_latex_mips/fnztlbentrymatch022ae8f81d6f9221e858534a26d34f7f.tex new file mode 100644 index 00000000..26917a60 --- /dev/null +++ b/sail_latex_mips/fnztlbentrymatch022ae8f81d6f9221e858534a26d34f7f.tex @@ -0,0 +1,12 @@ +function #\hyperref[sailMIPSztlbEntryMatch]{tlbEntryMatch}#(r, vpn2, asid, entry) = + let entryValid = entry.#\hyperref[sailMIPSzvalid]{valid}#() in + let entryR = entry.#\hyperref[sailMIPSzr]{r}#() in + let entryMask = entry.#\hyperref[sailMIPSzpagemask]{pagemask}#() in + let entryVPN = entry.#\hyperref[sailMIPSzvpn2]{vpn2}#() in + let entryASID = entry.#\hyperref[sailMIPSzasid]{asid}#() in + let entryG = entry.#\hyperref[sailMIPSzg]{g}#() in + let vpnMask : #\hyperref[sailMIPSzbits]{bits}#(27) = ~(#\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(entryMask)) in + (entryValid & + (r == entryR) & + ((vpn2 & vpnMask) == ((entryVPN) & vpnMask)) & + ((asid == (entryASID)) | (entryG))) diff --git a/sail_latex_mips/fnztlbsearchccbd0fc555e67dbea1dd6e8748394f51.tex b/sail_latex_mips/fnztlbsearchccbd0fc555e67dbea1dd6e8748394f51.tex new file mode 100644 index 00000000..0b24772c --- /dev/null +++ b/sail_latex_mips/fnztlbsearchccbd0fc555e67dbea1dd6e8748394f51.tex @@ -0,0 +1,10 @@ +function #\hyperref[sailMIPSztlbSearch]{tlbSearch}#(VAddr) = + let r = (VAddr[63..62]) in + let vpn2 = (VAddr[39..13]) in + let asid = TLBEntryHi.#\hyperref[sailMIPSzASID]{ASID}#() in { + foreach (idx from 0 to 63) { + if(#\hyperref[sailMIPSztlbEntryMatch]{tlbEntryMatch}#(r, vpn2, asid, *TLBEntries[idx])) then + return #\hyperref[sailMIPSzSome]{Some}#(#\hyperref[sailMIPSztozybits]{to\_bits}#(6, idx)) + }; + #\hyperref[sailMIPSzNone]{None}#() + } diff --git a/sail_latex_mips/fnztlbtranslate2472aa8aca18a66cca2beeaa89cbec740.tex b/sail_latex_mips/fnztlbtranslate2472aa8aca18a66cca2beeaa89cbec740.tex new file mode 100644 index 00000000..56e9c123 --- /dev/null +++ b/sail_latex_mips/fnztlbtranslate2472aa8aca18a66cca2beeaa89cbec740.tex @@ -0,0 +1,48 @@ +function #\hyperref[sailMIPSzTLBTranslate2]{TLBTranslate2}# (vAddr, accessType, accessLevel) = { + let idx = #\hyperref[sailMIPSztlbSearch]{tlbSearch}#(vAddr) in + match idx { + #\hyperref[sailMIPSzSome]{Some}#(idx) => + let i as atom(_) = #\hyperref[sailMIPSzunsigned]{unsigned}#(idx) in + let entry = *TLBEntries[i] in + let entryMask = entry.#\hyperref[sailMIPSzpagemask]{pagemask}#() in + let 'evenOddBit : range(12,28) = match (entryMask) { + 0x0000 => 12, + 0x0003 => 14, + 0x000f => 16, + 0x003f => 18, + 0x00ff => 20, + 0x03ff => 22, + 0x0fff => 24, + 0x3fff => 26, + 0xffff => 28, + _ => undefined + } in + let isOdd = (vAddr[evenOddBit]) in + let (caps : #\hyperref[sailMIPSzbits]{bits}#(1), caplg : #\hyperref[sailMIPSzbits]{bits}#(1), capl : #\hyperref[sailMIPSzbits]{bits}#(1), pfn : #\hyperref[sailMIPSzbits]{bits}#(24), d : #\hyperref[sailMIPSzbits]{bits}#(1), v : #\hyperref[sailMIPSzbits]{bits}#(1)) = + if (isOdd) then + (entry.#\hyperref[sailMIPSzcaps1]{caps1}#(), entry.#\hyperref[sailMIPSzcaplg1]{caplg1}#(), entry.#\hyperref[sailMIPSzcapl1]{capl1}#(), entry.#\hyperref[sailMIPSzpfn1]{pfn1}#(), entry.#\hyperref[sailMIPSzd1]{d1}#(), entry.#\hyperref[sailMIPSzv1]{v1}#()) + else + (entry.#\hyperref[sailMIPSzcaps0]{caps0}#(), entry.#\hyperref[sailMIPSzcaplg0]{caplg0}#(), entry.#\hyperref[sailMIPSzcapl0]{capl0}#(), entry.#\hyperref[sailMIPSzpfn0]{pfn0}#(), entry.#\hyperref[sailMIPSzd0]{d0}#(), entry.#\hyperref[sailMIPSzv0]{v0}#()) in + if (~(v)) then + #\hyperref[sailMIPSzSignalExceptionTLB]{SignalExceptionTLB}#(if (accessType == StoreData) then XTLBInvS else XTLBInvL, vAddr) + else if ((accessType == StoreData) & ~(d)) then + #\hyperref[sailMIPSzSignalExceptionTLB]{SignalExceptionTLB}#(TLBMod, vAddr) + else + let res : #\hyperref[sailMIPSzbits]{bits}#(64) = #\hyperref[sailMIPSzzzerozyextend]{zero\_extend}#(pfn[23..(evenOddBit - 12)] @ vAddr[(evenOddBit - 1) .. 0]) in + let macr = if (accessType == StoreData) then + if caps then Trap else Unrestricted + else + if capl then Clear + else + let gclg : #\hyperref[sailMIPSzbits]{bits}#(1) = match accessLevel { + User => TLBEntryHi.#\hyperref[sailMIPSzCLGU]{CLGU}#(), + Supervisor => TLBEntryHi.#\hyperref[sailMIPSzCLGS]{CLGS}#(), + Kernel => TLBEntryHi.#\hyperref[sailMIPSzCLGK]{CLGK}#() + } in + if gclg != caplg then Trap else Unrestricted + in + (res, macr), + #\hyperref[sailMIPSzNone]{None}#() => #\hyperref[sailMIPSzSignalExceptionTLB]{SignalExceptionTLB}#( + if (accessType == StoreData) then XTLBRefillS else XTLBRefillL, vAddr) + } +} diff --git a/sail_latex_mips/fnztlbtranslateccd99b29205e9558b4443d89bd7791f84.tex b/sail_latex_mips/fnztlbtranslateccd99b29205e9558b4443d89bd7791f84.tex new file mode 100644 index 00000000..f9c088ea --- /dev/null +++ b/sail_latex_mips/fnztlbtranslateccd99b29205e9558b4443d89bd7791f84.tex @@ -0,0 +1,21 @@ +function #\hyperref[sailMIPSzTLBTranslateC]{TLBTranslateC}# (vAddr, accessType) = + { + let currentAccessLevel = #\hyperref[sailMIPSzgetAccessLevel]{getAccessLevel}#() in + let compat32 = (vAddr[61..31] == 0b1111111111111111111111111111111) in + let (requiredLevel, addr) : (AccessLevel, #\hyperref[sailMIPSzoption]{option}#(#\hyperref[sailMIPSzbits]{bits}#(64))) = #\hyperref[sailMIPSzMIPSSegmentOf]{MIPSSegmentOf}#(vAddr) + in + if not(#\hyperref[sailMIPSzgrantsAccess]{grantsAccess}#(currentAccessLevel, requiredLevel)) then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(if (accessType == StoreData) then AdES else AdEL, vAddr) + else + let (pa, c) : (#\hyperref[sailMIPSzbits]{bits}#(64), MemAccessCapRestriction) = match addr { + #\hyperref[sailMIPSzSome]{Some}#(a) => (a, Unrestricted), + #\hyperref[sailMIPSzNone]{None}#() => if ((~(compat32)) & (#\hyperref[sailMIPSzunsigned]{unsigned}#(vAddr[61..0]) > MAX_VA)) then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(if (accessType == StoreData) then AdES else AdEL, vAddr) + else + #\hyperref[sailMIPSzTLBTranslate2]{TLBTranslate2}#(vAddr, accessType, requiredLevel) + } + in if (#\hyperref[sailMIPSzunsigned]{unsigned}#(pa) > MAX_PA) then + #\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(if (accessType == StoreData) then AdES else AdEL, vAddr) + else + (pa, c) + } diff --git a/sail_latex_mips/fnztlbtranslateea36ded227d6adddf8c6c2ae662895be.tex b/sail_latex_mips/fnztlbtranslateea36ded227d6adddf8c6c2ae662895be.tex new file mode 100644 index 00000000..e41a4631 --- /dev/null +++ b/sail_latex_mips/fnztlbtranslateea36ded227d6adddf8c6c2ae662895be.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailMIPSzTLBTranslate]{TLBTranslate}# (vAddr, accessType) = + let (addr, c) = #\hyperref[sailMIPSzTLBTranslateC]{TLBTranslateC}#(vAddr, accessType) in addr diff --git a/sail_latex_mips/fnzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex b/sail_latex_mips/fnzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex new file mode 100644 index 00000000..2358024b --- /dev/null +++ b/sail_latex_mips/fnzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSztozybits]{to\_bits}# (l, n) = #\hyperref[sailMIPSzgetzyslicezyint]{get\_slice\_int}#(l, n, 0) diff --git a/sail_latex_mips/fnztraceexceptiond1f5e2367606477eb2b33940325e3e87.tex b/sail_latex_mips/fnztraceexceptiond1f5e2367606477eb2b33940325e3e87.tex new file mode 100644 index 00000000..78f7b85c --- /dev/null +++ b/sail_latex_mips/fnztraceexceptiond1f5e2367606477eb2b33940325e3e87.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailMIPSztraceException]{traceException}# (ex : Exception) = { + if trace then { + #\hyperref[sailMIPSzprerr]{prerr}#(" EXCEPTION "); + #\hyperref[sailMIPSzprerrzyendline]{prerr\_endline}#(#\hyperref[sailMIPSzstringzyofzyexception]{string\_of\_exception}#(ex)); + }; +} diff --git a/sail_latex_mips/fnztranslatepca9eb30b515fe139216afcb3a9118ead3.tex b/sail_latex_mips/fnztranslatepca9eb30b515fe139216afcb3a9118ead3.tex new file mode 100644 index 00000000..61f7ffc2 --- /dev/null +++ b/sail_latex_mips/fnztranslatepca9eb30b515fe139216afcb3a9118ead3.tex @@ -0,0 +1,18 @@ +function #\hyperref[sailMIPSzTranslatePC]{TranslatePC}# (vAddr) = { + #\hyperref[sailMIPSzincrementCP0Count]{incrementCP0Count}#(); + let pcc = PCC; + let (base, top) = #\hyperref[sailMIPSzgetCapBounds]{getCapBounds}#(pcc); + let absPC = base + #\hyperref[sailMIPSzunsigned]{unsigned}#(vAddr); + if ((absPC % 4) != 0) then /* bad PC alignment */ + (#\hyperref[sailMIPSzSignalExceptionBadAddr]{SignalExceptionBadAddr}#(AdEL, #\hyperref[sailMIPSztozybits]{to\_bits}#(64, absPC))) /* XXX absPC may be truncated */ + else if not (pcc.tag) then + (#\hyperref[sailMIPSzraisezyc2zyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_TagViolation)) + else if (pcc.sealed) then + (#\hyperref[sailMIPSzraisezyc2zyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_SealViolation)) + else if not(pcc.permit_execute) then + (#\hyperref[sailMIPSzraisezyc2zyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_PermitExecuteViolation)) + else if ((absPC + 4) > top) then + (#\hyperref[sailMIPSzraisezyc2zyexceptionzynoreg]{raise\_c2\_exception\_noreg}#(CapEx_LengthViolation)) + else + #\hyperref[sailMIPSzTLBTranslate]{TLBTranslate}#(#\hyperref[sailMIPSztozybits]{to\_bits}#(64, absPC), Instruction) /* XXX assert absPC never gets truncated due to above check and top <= 2^64 for valid caps */ +} diff --git a/sail_latex_mips/fnzunalignedbytestouched30e9b9e5c4f2d5085ce71a02d1964f0c.tex b/sail_latex_mips/fnzunalignedbytestouched30e9b9e5c4f2d5085ce71a02d1964f0c.tex new file mode 100644 index 00000000..6a771779 --- /dev/null +++ b/sail_latex_mips/fnzunalignedbytestouched30e9b9e5c4f2d5085ce71a02d1964f0c.tex @@ -0,0 +1,10 @@ +function #\hyperref[sailMIPSzunalignedBytesTouched]{unalignedBytesTouched}#(vAddr : int, width : WordTypeUnaligned) -> (int, int) = { + woffset = vAddr % 4; + doffset = vAddr % 8; + match width { + WL => (vAddr, 4 - woffset), + WR => (vAddr - woffset, woffset + 1), + DL => (vAddr, 8 - doffset), + DR => (vAddr - doffset, doffset + 1) + } +} diff --git a/sail_latex_mips/fnzunrepcap312d66f4391d908cc0a7a87a38e8881a.tex b/sail_latex_mips/fnzunrepcap312d66f4391d908cc0a7a87a38e8881a.tex new file mode 100644 index 00000000..045a0210 --- /dev/null +++ b/sail_latex_mips/fnzunrepcap312d66f4391d908cc0a7a87a38e8881a.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzunrepCap]{unrepCap}#(cap) = {cap with tag = false} diff --git a/sail_latex_mips/fnzunsealcap58689ae49a7317c60147327414a678d2.tex b/sail_latex_mips/fnzunsealcap58689ae49a7317c60147327414a678d2.tex new file mode 100644 index 00000000..66c9069a --- /dev/null +++ b/sail_latex_mips/fnzunsealcap58689ae49a7317c60147327414a678d2.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailMIPSzunsealCap]{unsealCap}#(cap) : Capability -> Capability = + {cap with sealed=false, otype=#\hyperref[sailMIPSzones]{ones}#()} diff --git a/sail_latex_mips/fnzupdatebadinstr950852e9ede642484051c5622ba3c67c.tex b/sail_latex_mips/fnzupdatebadinstr950852e9ede642484051c5622ba3c67c.tex new file mode 100644 index 00000000..9859e7d7 --- /dev/null +++ b/sail_latex_mips/fnzupdatebadinstr950852e9ede642484051c5622ba3c67c.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailMIPSzupdateBadInstr]{updateBadInstr}# () = { + if (InBranchDelay[0]) then { + CP0BadInstrP = LastInstrBits; /* PC - 4 */ + }; + CP0BadInstr = CurrentInstrBits; /* PC */ +} diff --git a/sail_latex_mips/fnzwgpra4abc6baa21fcdee487f02c739ccf251.tex b/sail_latex_mips/fnzwgpra4abc6baa21fcdee487f02c739ccf251.tex new file mode 100644 index 00000000..1d49f203 --- /dev/null +++ b/sail_latex_mips/fnzwgpra4abc6baa21fcdee487f02c739ccf251.tex @@ -0,0 +1,10 @@ +function #\hyperref[sailMIPSzwGPR]{wGPR}# (idx, v) = { + let i as atom(_) = #\hyperref[sailMIPSzunsigned]{unsigned}#(idx) in + if i != 0 then { + if trace then { + #\hyperref[sailMIPSzprerr]{prerr}#(#\hyperref[sailMIPSzstringzyofzyint]{string\_of\_int}#(i)); + #\hyperref[sailMIPSzprerrzybits]{prerr\_bits}#(" <- ", v); + }; + GPR[i] = v; + }; +} diff --git a/sail_latex_mips/fnzwordtype_of_num3fb8b8a30f6fb7e01768c7e63da4fa79.tex b/sail_latex_mips/fnzwordtype_of_num3fb8b8a30f6fb7e01768c7e63da4fa79.tex new file mode 100644 index 00000000..f431606a --- /dev/null +++ b/sail_latex_mips/fnzwordtype_of_num3fb8b8a30f6fb7e01768c7e63da4fa79.tex @@ -0,0 +1,6 @@ +function WordType_of_num arg# = match arg# { + 0 => B, + 1 => H, + 2 => W, + _ => D +} diff --git a/sail_latex_mips/fnzwordtypeunaligned_of_num9534254c2a95ab15ea143c0eb1f767d5.tex b/sail_latex_mips/fnzwordtypeunaligned_of_num9534254c2a95ab15ea143c0eb1f767d5.tex new file mode 100644 index 00000000..7b690587 --- /dev/null +++ b/sail_latex_mips/fnzwordtypeunaligned_of_num9534254c2a95ab15ea143c0eb1f767d5.tex @@ -0,0 +1,6 @@ +function WordTypeUnaligned_of_num arg# = match arg# { + 0 => WL, + 1 => WR, + 2 => DL, + _ => DR +} diff --git a/sail_latex_mips/fnzwordwidthbyteseabb026e3f94d82320b5d4a77ee9fcc4.tex b/sail_latex_mips/fnzwordwidthbyteseabb026e3f94d82320b5d4a77ee9fcc4.tex new file mode 100644 index 00000000..eb59b121 --- /dev/null +++ b/sail_latex_mips/fnzwordwidthbyteseabb026e3f94d82320b5d4a77ee9fcc4.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailMIPSzwordWidthBytes]{wordWidthBytes}#(w) = + match w { + B => 1, + H => 2, + W => 4, + D => 8 + } diff --git a/sail_latex_mips/fnzwritecapreg902f20f3d4ba5384b97aa04a7a1756f4.tex b/sail_latex_mips/fnzwritecapreg902f20f3d4ba5384b97aa04a7a1756f4.tex new file mode 100644 index 00000000..03ad991b --- /dev/null +++ b/sail_latex_mips/fnzwritecapreg902f20f3d4ba5384b97aa04a7a1756f4.tex @@ -0,0 +1,29 @@ +function #\hyperref[sailMIPSzwriteCapReg]{writeCapReg}#(n, cap) = + if (n == 0b00000) then + () + else { + let i = #\hyperref[sailMIPSzunsigned]{unsigned}#(n); + if trace then { + #\hyperref[sailMIPSzprerr]{prerr}#(#\hyperref[sailMIPSzstringzyofzyint]{string\_of\_int}#(i)); + #\hyperref[sailMIPSzprerr]{prerr}#(" <- "); + #\hyperref[sailMIPSzprerrzyendline]{prerr\_endline}#(#\hyperref[sailMIPSzcapToString]{capToString}#(cap, false)); + /* Additionally check that the cap we are storing is in normal + form i.e. it is unchanged by round-tripping through bits. + This is quite a strong check because caps might differ from + normal form in ways that don't really #\hyperref[sailMIPSzmatter]{matter}# (e.g. otype + non-zero for unsealed capability) but it is probably a good + idea to maintain this invariant. It's disabled if not tracing + because it is slow. We might be able to eliminate the + non-normal values with a better type... */ + let cap2 = #\hyperref[sailMIPSzcapBitsToCapability]{capBitsToCapability}#(cap.tag, #\hyperref[sailMIPSzcapToBits]{capToBits}#(cap)); + if (cap != cap2) then { + #\hyperref[sailMIPSzprerrzyendline]{prerr\_endline}#("Wrote non-normal cap:"); + #\hyperref[sailMIPSzprerrzyendline]{prerr\_endline}#(#\hyperref[sailMIPSzcapToString]{capToString}#(cap, false)); + #\hyperref[sailMIPSzprerrzyendline]{prerr\_endline}#(#\hyperref[sailMIPSzcapToString]{capToString}#(cap2, false)); + assert(false, "wrote non-normal capability"); + }; + } else { + #\hyperref[sailMIPSzskipzyescape]{skip\_escape}#(); + }; + (*CapRegs[i]) = cap; + } diff --git a/sail_latex_mips/fnzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex b/sail_latex_mips/fnzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex new file mode 100644 index 00000000..3629ee5f --- /dev/null +++ b/sail_latex_mips/fnzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex @@ -0,0 +1 @@ +function operator <#\hyperref[sailMIPSzzys]{\_s}# (x, y) = #\hyperref[sailMIPSzsigned]{signed}#(x) < #\hyperref[sailMIPSzsigned]{signed}#(y) diff --git a/sail_latex_mips/fnzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex b/sail_latex_mips/fnzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex new file mode 100644 index 00000000..45317d2b --- /dev/null +++ b/sail_latex_mips/fnzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex @@ -0,0 +1 @@ +function operator <#\hyperref[sailMIPSzzyu]{\_u}# (x, y) = #\hyperref[sailMIPSzunsigned]{unsigned}#(x) < #\hyperref[sailMIPSzunsigned]{unsigned}#(y) diff --git a/sail_latex_mips/fnzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex b/sail_latex_mips/fnzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex new file mode 100644 index 00000000..31a47178 --- /dev/null +++ b/sail_latex_mips/fnzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex @@ -0,0 +1 @@ +function operator >=#\hyperref[sailMIPSzzys]{\_s}# (x, y) = #\hyperref[sailMIPSzsigned]{signed}#(x) >= #\hyperref[sailMIPSzsigned]{signed}#(y) diff --git a/sail_latex_mips/fnzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex b/sail_latex_mips/fnzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex new file mode 100644 index 00000000..ca15af31 --- /dev/null +++ b/sail_latex_mips/fnzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex @@ -0,0 +1 @@ +function operator >=#\hyperref[sailMIPSzzyu]{\_u}# (x, y) = #\hyperref[sailMIPSzunsigned]{unsigned}#(x) >= #\hyperref[sailMIPSzunsigned]{unsigned}#(y) diff --git a/sail_latex_mips/fnzz8operatorz0zqzqz93d1b5248b83463c11188367c0486a3fd.tex b/sail_latex_mips/fnzz8operatorz0zqzqz93d1b5248b83463c11188367c0486a3fd.tex new file mode 100644 index 00000000..1cccab4f --- /dev/null +++ b/sail_latex_mips/fnzz8operatorz0zqzqz93d1b5248b83463c11188367c0486a3fd.tex @@ -0,0 +1 @@ +function operator ^^ (bs, n) = #\hyperref[sailMIPSzreplicatezybits]{replicate\_bits}# (bs, n) diff --git a/sail_latex_mips/fnzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex b/sail_latex_mips/fnzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex new file mode 100644 index 00000000..d1cf130b --- /dev/null +++ b/sail_latex_mips/fnzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex @@ -0,0 +1 @@ +function #\hyperref[sailMIPSzzzeroszyimplicit]{zeros\_implicit}#(n, _) = #\hyperref[sailMIPSzsailzyzzeros]{sail\_zeros}#(n) diff --git a/sail_latex_mips/overloadAAAAAAAAzupdate_regnumf38b56d427844345bd870b4ea07d3f5b.tex b/sail_latex_mips/overloadAAAAAAAAzupdate_regnumf38b56d427844345bd870b4ea07d3f5b.tex new file mode 100644 index 00000000..61c4abe6 --- /dev/null +++ b/sail_latex_mips/overloadAAAAAAAAzupdate_regnumf38b56d427844345bd870b4ea07d3f5b.tex @@ -0,0 +1 @@ +overload update_RegNum = {_update_CapCauseReg_RegNum} \ No newline at end of file diff --git a/sail_latex_mips/overloadAAAAAAAzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_mips/overloadAAAAAAAzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..cc90c98a --- /dev/null +++ b/sail_latex_mips/overloadAAAAAAAzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_StatusReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadAAAAAAzupdate_caps11a0c8b14f627fc4bdd72e123c39905cd.tex b/sail_latex_mips/overloadAAAAAAzupdate_caps11a0c8b14f627fc4bdd72e123c39905cd.tex new file mode 100644 index 00000000..6449364e --- /dev/null +++ b/sail_latex_mips/overloadAAAAAAzupdate_caps11a0c8b14f627fc4bdd72e123c39905cd.tex @@ -0,0 +1 @@ +overload update_caps1 = {_update_TLBEntry_caps1} \ No newline at end of file diff --git a/sail_latex_mips/overloadAAAAAzupdate_badvpn2ed07cfb17ee4c0ba07ba1ed27c407cd5.tex b/sail_latex_mips/overloadAAAAAzupdate_badvpn2ed07cfb17ee4c0ba07ba1ed27c407cd5.tex new file mode 100644 index 00000000..7b9f2827 --- /dev/null +++ b/sail_latex_mips/overloadAAAAAzupdate_badvpn2ed07cfb17ee4c0ba07ba1ed27c407cd5.tex @@ -0,0 +1 @@ +overload update_BadVPN2 = {_update_ContextReg_BadVPN2} \ No newline at end of file diff --git a/sail_latex_mips/overloadAAAAzupdate_c58b96a6767db6cbc4e0bfce6023a35b9.tex b/sail_latex_mips/overloadAAAAzupdate_c58b96a6767db6cbc4e0bfce6023a35b9.tex new file mode 100644 index 00000000..4e4756e3 --- /dev/null +++ b/sail_latex_mips/overloadAAAAzupdate_c58b96a6767db6cbc4e0bfce6023a35b9.tex @@ -0,0 +1 @@ +overload update_C = {_update_TLBEntryLoReg_C} \ No newline at end of file diff --git a/sail_latex_mips/overloadAAAzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex b/sail_latex_mips/overloadAAAzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex new file mode 100644 index 00000000..589b0b26 --- /dev/null +++ b/sail_latex_mips/overloadAAAzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex @@ -0,0 +1 @@ +overload operator >> = {shift_bits_right, shiftr} diff --git a/sail_latex_mips/overloadAAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex b/sail_latex_mips/overloadAAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex new file mode 100644 index 00000000..e121fc77 --- /dev/null +++ b/sail_latex_mips/overloadAAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex @@ -0,0 +1 @@ +overload vector_update = {bitvector_update, plain_vector_update} diff --git a/sail_latex_mips/overloadBBBBBBBBz_mod_regnumf3e57f0335af5095cca3b6786298d47b.tex b/sail_latex_mips/overloadBBBBBBBBz_mod_regnumf3e57f0335af5095cca3b6786298d47b.tex new file mode 100644 index 00000000..6cc28de3 --- /dev/null +++ b/sail_latex_mips/overloadBBBBBBBBz_mod_regnumf3e57f0335af5095cca3b6786298d47b.tex @@ -0,0 +1 @@ +overload _mod_RegNum = {_get_CapCauseReg_RegNum, _set_CapCauseReg_RegNum} \ No newline at end of file diff --git a/sail_latex_mips/overloadBBBBBBBz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_mips/overloadBBBBBBBz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..f27daebb --- /dev/null +++ b/sail_latex_mips/overloadBBBBBBBz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_StatusReg_bits, _set_StatusReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadBBBBBBz_mod_caps1f41407643ae768a227e254f27ceaa814.tex b/sail_latex_mips/overloadBBBBBBz_mod_caps1f41407643ae768a227e254f27ceaa814.tex new file mode 100644 index 00000000..c2aa1743 --- /dev/null +++ b/sail_latex_mips/overloadBBBBBBz_mod_caps1f41407643ae768a227e254f27ceaa814.tex @@ -0,0 +1 @@ +overload _mod_caps1 = {_get_TLBEntry_caps1, _set_TLBEntry_caps1} \ No newline at end of file diff --git a/sail_latex_mips/overloadBBBBBz_mod_badvpn27f29c44b4acbb87554b40dfacc46aca6.tex b/sail_latex_mips/overloadBBBBBz_mod_badvpn27f29c44b4acbb87554b40dfacc46aca6.tex new file mode 100644 index 00000000..c2578121 --- /dev/null +++ b/sail_latex_mips/overloadBBBBBz_mod_badvpn27f29c44b4acbb87554b40dfacc46aca6.tex @@ -0,0 +1 @@ +overload _mod_BadVPN2 = {_get_ContextReg_BadVPN2, _set_ContextReg_BadVPN2} \ No newline at end of file diff --git a/sail_latex_mips/overloadBBBBz_mod_ceb8c62eaf4804c4722a6c0c552f18d93.tex b/sail_latex_mips/overloadBBBBz_mod_ceb8c62eaf4804c4722a6c0c552f18d93.tex new file mode 100644 index 00000000..01df09e2 --- /dev/null +++ b/sail_latex_mips/overloadBBBBz_mod_ceb8c62eaf4804c4722a6c0c552f18d93.tex @@ -0,0 +1 @@ +overload _mod_C = {_get_TLBEntryLoReg_C, _set_TLBEntryLoReg_C} \ No newline at end of file diff --git a/sail_latex_mips/overloadBBBzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex b/sail_latex_mips/overloadBBBzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex new file mode 100644 index 00000000..07b14b4f --- /dev/null +++ b/sail_latex_mips/overloadBBBzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex @@ -0,0 +1 @@ +overload operator << = {shift_bits_left, shiftl} diff --git a/sail_latex_mips/overloadBBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex b/sail_latex_mips/overloadBBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex new file mode 100644 index 00000000..2ffe7431 --- /dev/null +++ b/sail_latex_mips/overloadBBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex @@ -0,0 +1 @@ +overload operator + = {add_bits, add_bits_int} diff --git a/sail_latex_mips/overloadBzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_mips/overloadBzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex new file mode 100644 index 00000000..8a01dd4f --- /dev/null +++ b/sail_latex_mips/overloadBzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex @@ -0,0 +1 @@ +overload operator == = {eq_bit2} diff --git a/sail_latex_mips/overloadCCCCCCCzupdate_cu412b8245b493377692f4da2838d4372d.tex b/sail_latex_mips/overloadCCCCCCCzupdate_cu412b8245b493377692f4da2838d4372d.tex new file mode 100644 index 00000000..fcc82986 --- /dev/null +++ b/sail_latex_mips/overloadCCCCCCCzupdate_cu412b8245b493377692f4da2838d4372d.tex @@ -0,0 +1 @@ +overload update_CU = {_update_StatusReg_CU} \ No newline at end of file diff --git a/sail_latex_mips/overloadCCCCCCzupdate_capl15a836258329872f209ff11538ab6bd46.tex b/sail_latex_mips/overloadCCCCCCzupdate_capl15a836258329872f209ff11538ab6bd46.tex new file mode 100644 index 00000000..a0ce007c --- /dev/null +++ b/sail_latex_mips/overloadCCCCCCzupdate_capl15a836258329872f209ff11538ab6bd46.tex @@ -0,0 +1 @@ +overload update_capl1 = {_update_TLBEntry_capl1} \ No newline at end of file diff --git a/sail_latex_mips/overloadCCCCCzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_mips/overloadCCCCCzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..28ee31f9 --- /dev/null +++ b/sail_latex_mips/overloadCCCCCzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_XContextReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadCCCCzupdate_da9201c8a6710e680d16238f3581a0227.tex b/sail_latex_mips/overloadCCCCzupdate_da9201c8a6710e680d16238f3581a0227.tex new file mode 100644 index 00000000..2f367d1e --- /dev/null +++ b/sail_latex_mips/overloadCCCCzupdate_da9201c8a6710e680d16238f3581a0227.tex @@ -0,0 +1 @@ +overload update_D = {_update_TLBEntryLoReg_D} \ No newline at end of file diff --git a/sail_latex_mips/overloadCCCzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_mips/overloadCCCzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..1be74427 --- /dev/null +++ b/sail_latex_mips/overloadCCCzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_CauseReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadCCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex b/sail_latex_mips/overloadCCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex new file mode 100644 index 00000000..cf01736a --- /dev/null +++ b/sail_latex_mips/overloadCCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex @@ -0,0 +1 @@ +overload operator & = {and_vec} diff --git a/sail_latex_mips/overloadCzabs_intef5fbb521189282054dc80dc7173013d.tex b/sail_latex_mips/overloadCzabs_intef5fbb521189282054dc80dc7173013d.tex new file mode 100644 index 00000000..047f6d0c --- /dev/null +++ b/sail_latex_mips/overloadCzabs_intef5fbb521189282054dc80dc7173013d.tex @@ -0,0 +1 @@ +overload abs_int = {abs_int_atom} diff --git a/sail_latex_mips/overloadDDDDDDDz_mod_cu360fcd6846ac7960b6ce1cf37eaac7f4.tex b/sail_latex_mips/overloadDDDDDDDz_mod_cu360fcd6846ac7960b6ce1cf37eaac7f4.tex new file mode 100644 index 00000000..2a2b7db3 --- /dev/null +++ b/sail_latex_mips/overloadDDDDDDDz_mod_cu360fcd6846ac7960b6ce1cf37eaac7f4.tex @@ -0,0 +1 @@ +overload _mod_CU = {_get_StatusReg_CU, _set_StatusReg_CU} \ No newline at end of file diff --git a/sail_latex_mips/overloadDDDDDDz_mod_capl1be097b5150627138c8925b6940717f8f.tex b/sail_latex_mips/overloadDDDDDDz_mod_capl1be097b5150627138c8925b6940717f8f.tex new file mode 100644 index 00000000..cc216500 --- /dev/null +++ b/sail_latex_mips/overloadDDDDDDz_mod_capl1be097b5150627138c8925b6940717f8f.tex @@ -0,0 +1 @@ +overload _mod_capl1 = {_get_TLBEntry_capl1, _set_TLBEntry_capl1} \ No newline at end of file diff --git a/sail_latex_mips/overloadDDDDDz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_mips/overloadDDDDDz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..bde40ee8 --- /dev/null +++ b/sail_latex_mips/overloadDDDDDz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_XContextReg_bits, _set_XContextReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadDDDDz_mod_d8c29507d9735e49d608a373bd2e2c599.tex b/sail_latex_mips/overloadDDDDz_mod_d8c29507d9735e49d608a373bd2e2c599.tex new file mode 100644 index 00000000..af4cad2e --- /dev/null +++ b/sail_latex_mips/overloadDDDDz_mod_d8c29507d9735e49d608a373bd2e2c599.tex @@ -0,0 +1 @@ +overload _mod_D = {_get_TLBEntryLoReg_D, _set_TLBEntryLoReg_D} \ No newline at end of file diff --git a/sail_latex_mips/overloadDDDz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_mips/overloadDDDz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..b9059538 --- /dev/null +++ b/sail_latex_mips/overloadDDDz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_CauseReg_bits, _set_CauseReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadDDzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex b/sail_latex_mips/overloadDDzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex new file mode 100644 index 00000000..0bb9bf01 --- /dev/null +++ b/sail_latex_mips/overloadDDzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex @@ -0,0 +1 @@ +overload operator | = {or_vec} diff --git a/sail_latex_mips/overloadDzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_mips/overloadDzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex new file mode 100644 index 00000000..751094be --- /dev/null +++ b/sail_latex_mips/overloadDzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex @@ -0,0 +1 @@ +overload operator == = {eq_int, eq_bit, eq_bool, eq_unit} diff --git a/sail_latex_mips/overloadEEEEEEEzupdate_bevfd852bec522e475c2cd0b5fcd3214f94.tex b/sail_latex_mips/overloadEEEEEEEzupdate_bevfd852bec522e475c2cd0b5fcd3214f94.tex new file mode 100644 index 00000000..e45f5c7d --- /dev/null +++ b/sail_latex_mips/overloadEEEEEEEzupdate_bevfd852bec522e475c2cd0b5fcd3214f94.tex @@ -0,0 +1 @@ +overload update_BEV = {_update_StatusReg_BEV} \ No newline at end of file diff --git a/sail_latex_mips/overloadEEEEEEzupdate_pfn1214da6ee34bca766359dbffcc3547b0a.tex b/sail_latex_mips/overloadEEEEEEzupdate_pfn1214da6ee34bca766359dbffcc3547b0a.tex new file mode 100644 index 00000000..a6e7a80d --- /dev/null +++ b/sail_latex_mips/overloadEEEEEEzupdate_pfn1214da6ee34bca766359dbffcc3547b0a.tex @@ -0,0 +1 @@ +overload update_pfn1 = {_update_TLBEntry_pfn1} \ No newline at end of file diff --git a/sail_latex_mips/overloadEEEEEzupdate_xptebase824212fd8ab34e381399a9fd3bdbacb2.tex b/sail_latex_mips/overloadEEEEEzupdate_xptebase824212fd8ab34e381399a9fd3bdbacb2.tex new file mode 100644 index 00000000..8a203d30 --- /dev/null +++ b/sail_latex_mips/overloadEEEEEzupdate_xptebase824212fd8ab34e381399a9fd3bdbacb2.tex @@ -0,0 +1 @@ +overload update_XPTEBase = {_update_XContextReg_XPTEBase} \ No newline at end of file diff --git a/sail_latex_mips/overloadEEEEzupdate_v550d76e01b2aee2bcdcdd8fcb788e6ae.tex b/sail_latex_mips/overloadEEEEzupdate_v550d76e01b2aee2bcdcdd8fcb788e6ae.tex new file mode 100644 index 00000000..336f76d5 --- /dev/null +++ b/sail_latex_mips/overloadEEEEzupdate_v550d76e01b2aee2bcdcdd8fcb788e6ae.tex @@ -0,0 +1 @@ +overload update_V = {_update_TLBEntryLoReg_V} \ No newline at end of file diff --git a/sail_latex_mips/overloadEEEzupdate_bd472c903f3ae609529b16dd7fa25cbef2.tex b/sail_latex_mips/overloadEEEzupdate_bd472c903f3ae609529b16dd7fa25cbef2.tex new file mode 100644 index 00000000..db94f260 --- /dev/null +++ b/sail_latex_mips/overloadEEEzupdate_bd472c903f3ae609529b16dd7fa25cbef2.tex @@ -0,0 +1 @@ +overload update_BD = {_update_CauseReg_BD} \ No newline at end of file diff --git a/sail_latex_mips/overloadEEzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex b/sail_latex_mips/overloadEEzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex new file mode 100644 index 00000000..30bebb96 --- /dev/null +++ b/sail_latex_mips/overloadEEzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex @@ -0,0 +1 @@ +overload vector_subrange = {subrange_bits} diff --git a/sail_latex_mips/overloadEzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex b/sail_latex_mips/overloadEzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex new file mode 100644 index 00000000..8be31818 --- /dev/null +++ b/sail_latex_mips/overloadEzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex @@ -0,0 +1 @@ +overload operator != = {neq_int, neq_bool} diff --git a/sail_latex_mips/overloadFFFFFFFz_mod_bev3b9dcc4a8986f6731f7c23d6ed0a794e.tex b/sail_latex_mips/overloadFFFFFFFz_mod_bev3b9dcc4a8986f6731f7c23d6ed0a794e.tex new file mode 100644 index 00000000..beee53c1 --- /dev/null +++ b/sail_latex_mips/overloadFFFFFFFz_mod_bev3b9dcc4a8986f6731f7c23d6ed0a794e.tex @@ -0,0 +1 @@ +overload _mod_BEV = {_get_StatusReg_BEV, _set_StatusReg_BEV} \ No newline at end of file diff --git a/sail_latex_mips/overloadFFFFFFz_mod_pfn1a0d295636b191ae9d64a838099f830ba.tex b/sail_latex_mips/overloadFFFFFFz_mod_pfn1a0d295636b191ae9d64a838099f830ba.tex new file mode 100644 index 00000000..3e703530 --- /dev/null +++ b/sail_latex_mips/overloadFFFFFFz_mod_pfn1a0d295636b191ae9d64a838099f830ba.tex @@ -0,0 +1 @@ +overload _mod_pfn1 = {_get_TLBEntry_pfn1, _set_TLBEntry_pfn1} \ No newline at end of file diff --git a/sail_latex_mips/overloadFFFFFz_mod_xptebase52f38d47c32d7dae47f1a4a036025464.tex b/sail_latex_mips/overloadFFFFFz_mod_xptebase52f38d47c32d7dae47f1a4a036025464.tex new file mode 100644 index 00000000..67e094bf --- /dev/null +++ b/sail_latex_mips/overloadFFFFFz_mod_xptebase52f38d47c32d7dae47f1a4a036025464.tex @@ -0,0 +1 @@ +overload _mod_XPTEBase = {_get_XContextReg_XPTEBase, _set_XContextReg_XPTEBase} \ No newline at end of file diff --git a/sail_latex_mips/overloadFFFFz_mod_v136fe7ecc31e11f2521faa02b71b57fa.tex b/sail_latex_mips/overloadFFFFz_mod_v136fe7ecc31e11f2521faa02b71b57fa.tex new file mode 100644 index 00000000..964f5eab --- /dev/null +++ b/sail_latex_mips/overloadFFFFz_mod_v136fe7ecc31e11f2521faa02b71b57fa.tex @@ -0,0 +1 @@ +overload _mod_V = {_get_TLBEntryLoReg_V, _set_TLBEntryLoReg_V} \ No newline at end of file diff --git a/sail_latex_mips/overloadFFFz_mod_bdd84f0971ca04f14c3accaf99182a8375.tex b/sail_latex_mips/overloadFFFz_mod_bdd84f0971ca04f14c3accaf99182a8375.tex new file mode 100644 index 00000000..f3e58d9b --- /dev/null +++ b/sail_latex_mips/overloadFFFz_mod_bdd84f0971ca04f14c3accaf99182a8375.tex @@ -0,0 +1 @@ +overload _mod_BD = {_get_CauseReg_BD, _set_CauseReg_BD} \ No newline at end of file diff --git a/sail_latex_mips/overloadFFzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex b/sail_latex_mips/overloadFFzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex new file mode 100644 index 00000000..22e3a8b8 --- /dev/null +++ b/sail_latex_mips/overloadFFzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex @@ -0,0 +1 @@ +overload vector_update_subrange = {update_subrange_bits} diff --git a/sail_latex_mips/overloadFzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex b/sail_latex_mips/overloadFzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex new file mode 100644 index 00000000..acd09503 --- /dev/null +++ b/sail_latex_mips/overloadFzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex @@ -0,0 +1 @@ +overload operator | = {or_bool} diff --git a/sail_latex_mips/overloadGGGGGGGzupdate_imb21cdd8456dfd134eec8cf19991410ad.tex b/sail_latex_mips/overloadGGGGGGGzupdate_imb21cdd8456dfd134eec8cf19991410ad.tex new file mode 100644 index 00000000..6128559a --- /dev/null +++ b/sail_latex_mips/overloadGGGGGGGzupdate_imb21cdd8456dfd134eec8cf19991410ad.tex @@ -0,0 +1 @@ +overload update_IM = {_update_StatusReg_IM} \ No newline at end of file diff --git a/sail_latex_mips/overloadGGGGGGzupdate_c18c11b21bde25ad918fdd25ea7ff6927b.tex b/sail_latex_mips/overloadGGGGGGzupdate_c18c11b21bde25ad918fdd25ea7ff6927b.tex new file mode 100644 index 00000000..f8e39aea --- /dev/null +++ b/sail_latex_mips/overloadGGGGGGzupdate_c18c11b21bde25ad918fdd25ea7ff6927b.tex @@ -0,0 +1 @@ +overload update_c1 = {_update_TLBEntry_c1} \ No newline at end of file diff --git a/sail_latex_mips/overloadGGGGGzupdate_xr0dfb3b8608abe69ac3ecb9ebe1723645.tex b/sail_latex_mips/overloadGGGGGzupdate_xr0dfb3b8608abe69ac3ecb9ebe1723645.tex new file mode 100644 index 00000000..1854ca65 --- /dev/null +++ b/sail_latex_mips/overloadGGGGGzupdate_xr0dfb3b8608abe69ac3ecb9ebe1723645.tex @@ -0,0 +1 @@ +overload update_XR = {_update_XContextReg_XR} \ No newline at end of file diff --git a/sail_latex_mips/overloadGGGGzupdate_ga61979e0097ae60f8598f57688dbae8b.tex b/sail_latex_mips/overloadGGGGzupdate_ga61979e0097ae60f8598f57688dbae8b.tex new file mode 100644 index 00000000..23f7bf3c --- /dev/null +++ b/sail_latex_mips/overloadGGGGzupdate_ga61979e0097ae60f8598f57688dbae8b.tex @@ -0,0 +1 @@ +overload update_G = {_update_TLBEntryLoReg_G} \ No newline at end of file diff --git a/sail_latex_mips/overloadGGGzupdate_ce14dd97255abc19f0f457743517c0d047.tex b/sail_latex_mips/overloadGGGzupdate_ce14dd97255abc19f0f457743517c0d047.tex new file mode 100644 index 00000000..12be67a2 --- /dev/null +++ b/sail_latex_mips/overloadGGGzupdate_ce14dd97255abc19f0f457743517c0d047.tex @@ -0,0 +1 @@ +overload update_CE = {_update_CauseReg_CE} \ No newline at end of file diff --git a/sail_latex_mips/overloadGGz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex b/sail_latex_mips/overloadGGz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex new file mode 100644 index 00000000..a32ee3d7 --- /dev/null +++ b/sail_latex_mips/overloadGGz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex @@ -0,0 +1 @@ +overload __size = {__id, bitvector_length} diff --git a/sail_latex_mips/overloadGzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex b/sail_latex_mips/overloadGzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex new file mode 100644 index 00000000..68ff151b --- /dev/null +++ b/sail_latex_mips/overloadGzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex @@ -0,0 +1 @@ +overload operator & = {and_bool} diff --git a/sail_latex_mips/overloadHHHHHHHz_mod_ima8a9d7a125ed51b1dae576dc7330719b.tex b/sail_latex_mips/overloadHHHHHHHz_mod_ima8a9d7a125ed51b1dae576dc7330719b.tex new file mode 100644 index 00000000..d3a58dd0 --- /dev/null +++ b/sail_latex_mips/overloadHHHHHHHz_mod_ima8a9d7a125ed51b1dae576dc7330719b.tex @@ -0,0 +1 @@ +overload _mod_IM = {_get_StatusReg_IM, _set_StatusReg_IM} \ No newline at end of file diff --git a/sail_latex_mips/overloadHHHHHHz_mod_c1ea997b12acb6722314c7b19e41b1677b.tex b/sail_latex_mips/overloadHHHHHHz_mod_c1ea997b12acb6722314c7b19e41b1677b.tex new file mode 100644 index 00000000..70d2a78c --- /dev/null +++ b/sail_latex_mips/overloadHHHHHHz_mod_c1ea997b12acb6722314c7b19e41b1677b.tex @@ -0,0 +1 @@ +overload _mod_c1 = {_get_TLBEntry_c1, _set_TLBEntry_c1} \ No newline at end of file diff --git a/sail_latex_mips/overloadHHHHHz_mod_xr58438b12ce6dc4c713fa978abe898f59.tex b/sail_latex_mips/overloadHHHHHz_mod_xr58438b12ce6dc4c713fa978abe898f59.tex new file mode 100644 index 00000000..a3c5ab29 --- /dev/null +++ b/sail_latex_mips/overloadHHHHHz_mod_xr58438b12ce6dc4c713fa978abe898f59.tex @@ -0,0 +1 @@ +overload _mod_XR = {_get_XContextReg_XR, _set_XContextReg_XR} \ No newline at end of file diff --git a/sail_latex_mips/overloadHHHHz_mod_g521053c016cb3f20bf7b96843a7a2cf4.tex b/sail_latex_mips/overloadHHHHz_mod_g521053c016cb3f20bf7b96843a7a2cf4.tex new file mode 100644 index 00000000..ddb88eaa --- /dev/null +++ b/sail_latex_mips/overloadHHHHz_mod_g521053c016cb3f20bf7b96843a7a2cf4.tex @@ -0,0 +1 @@ +overload _mod_G = {_get_TLBEntryLoReg_G, _set_TLBEntryLoReg_G} \ No newline at end of file diff --git a/sail_latex_mips/overloadHHHz_mod_ceea2953e9544c0c54dc69ff3e4ffbe7f8.tex b/sail_latex_mips/overloadHHHz_mod_ceea2953e9544c0c54dc69ff3e4ffbe7f8.tex new file mode 100644 index 00000000..9136541c --- /dev/null +++ b/sail_latex_mips/overloadHHHz_mod_ceea2953e9544c0c54dc69ff3e4ffbe7f8.tex @@ -0,0 +1 @@ +overload _mod_CE = {_get_CauseReg_CE, _set_CauseReg_CE} \ No newline at end of file diff --git a/sail_latex_mips/overloadHHzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_mips/overloadHHzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex new file mode 100644 index 00000000..b5ecaaae --- /dev/null +++ b/sail_latex_mips/overloadHHzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex @@ -0,0 +1 @@ +overload operator == = {eq_string} diff --git a/sail_latex_mips/overloadHzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex b/sail_latex_mips/overloadHzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex new file mode 100644 index 00000000..a31bd82c --- /dev/null +++ b/sail_latex_mips/overloadHzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex @@ -0,0 +1 @@ +overload operator <= = {lteq_int} diff --git a/sail_latex_mips/overloadIIIIIIIzupdate_kxed26c42ef95a8d8da42bca4da6bd4eab.tex b/sail_latex_mips/overloadIIIIIIIzupdate_kxed26c42ef95a8d8da42bca4da6bd4eab.tex new file mode 100644 index 00000000..ff23da68 --- /dev/null +++ b/sail_latex_mips/overloadIIIIIIIzupdate_kxed26c42ef95a8d8da42bca4da6bd4eab.tex @@ -0,0 +1 @@ +overload update_KX = {_update_StatusReg_KX} \ No newline at end of file diff --git a/sail_latex_mips/overloadIIIIIIzupdate_d1de65b1d3efdd740536c08b95a2842c0b.tex b/sail_latex_mips/overloadIIIIIIzupdate_d1de65b1d3efdd740536c08b95a2842c0b.tex new file mode 100644 index 00000000..ee303126 --- /dev/null +++ b/sail_latex_mips/overloadIIIIIIzupdate_d1de65b1d3efdd740536c08b95a2842c0b.tex @@ -0,0 +1 @@ +overload update_d1 = {_update_TLBEntry_d1} \ No newline at end of file diff --git a/sail_latex_mips/overloadIIIIIzupdate_xbadvpn239829bed7a81273818a992030fb566e4.tex b/sail_latex_mips/overloadIIIIIzupdate_xbadvpn239829bed7a81273818a992030fb566e4.tex new file mode 100644 index 00000000..9bb69796 --- /dev/null +++ b/sail_latex_mips/overloadIIIIIzupdate_xbadvpn239829bed7a81273818a992030fb566e4.tex @@ -0,0 +1 @@ +overload update_XBadVPN2 = {_update_XContextReg_XBadVPN2} \ No newline at end of file diff --git a/sail_latex_mips/overloadIIIIzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_mips/overloadIIIIzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..efc2c5b0 --- /dev/null +++ b/sail_latex_mips/overloadIIIIzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_TLBEntryHiReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadIIIzupdate_iv53a8e0f57ddb36f890734859eaba53ae.tex b/sail_latex_mips/overloadIIIzupdate_iv53a8e0f57ddb36f890734859eaba53ae.tex new file mode 100644 index 00000000..7cfa3a60 --- /dev/null +++ b/sail_latex_mips/overloadIIIzupdate_iv53a8e0f57ddb36f890734859eaba53ae.tex @@ -0,0 +1 @@ +overload update_IV = {_update_CauseReg_IV} \ No newline at end of file diff --git a/sail_latex_mips/overloadIIzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_mips/overloadIIzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex new file mode 100644 index 00000000..4bf80965 --- /dev/null +++ b/sail_latex_mips/overloadIIzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex @@ -0,0 +1 @@ +overload operator == = {eq_anything} diff --git a/sail_latex_mips/overloadIzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex b/sail_latex_mips/overloadIzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex new file mode 100644 index 00000000..12e27dc2 --- /dev/null +++ b/sail_latex_mips/overloadIzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex @@ -0,0 +1 @@ +overload operator < = {lt_int} diff --git a/sail_latex_mips/overloadJJJJJJJz_mod_kx3c410091f5b2b941ccec438ead435325.tex b/sail_latex_mips/overloadJJJJJJJz_mod_kx3c410091f5b2b941ccec438ead435325.tex new file mode 100644 index 00000000..a90ad274 --- /dev/null +++ b/sail_latex_mips/overloadJJJJJJJz_mod_kx3c410091f5b2b941ccec438ead435325.tex @@ -0,0 +1 @@ +overload _mod_KX = {_get_StatusReg_KX, _set_StatusReg_KX} \ No newline at end of file diff --git a/sail_latex_mips/overloadJJJJJJz_mod_d133bac8bf84adab553084245a59d8d0d0.tex b/sail_latex_mips/overloadJJJJJJz_mod_d133bac8bf84adab553084245a59d8d0d0.tex new file mode 100644 index 00000000..d970eb5b --- /dev/null +++ b/sail_latex_mips/overloadJJJJJJz_mod_d133bac8bf84adab553084245a59d8d0d0.tex @@ -0,0 +1 @@ +overload _mod_d1 = {_get_TLBEntry_d1, _set_TLBEntry_d1} \ No newline at end of file diff --git a/sail_latex_mips/overloadJJJJJz_mod_xbadvpn2b779444a2db61a5e00de492489d3d5d5.tex b/sail_latex_mips/overloadJJJJJz_mod_xbadvpn2b779444a2db61a5e00de492489d3d5d5.tex new file mode 100644 index 00000000..9122b39d --- /dev/null +++ b/sail_latex_mips/overloadJJJJJz_mod_xbadvpn2b779444a2db61a5e00de492489d3d5d5.tex @@ -0,0 +1 @@ +overload _mod_XBadVPN2 = {_get_XContextReg_XBadVPN2, _set_XContextReg_XBadVPN2} \ No newline at end of file diff --git a/sail_latex_mips/overloadJJJJz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_mips/overloadJJJJz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..d52fa2ec --- /dev/null +++ b/sail_latex_mips/overloadJJJJz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_TLBEntryHiReg_bits, _set_TLBEntryHiReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadJJJz_mod_ivb088aebc9bfea2ab389f62ea44fbb3a9.tex b/sail_latex_mips/overloadJJJz_mod_ivb088aebc9bfea2ab389f62ea44fbb3a9.tex new file mode 100644 index 00000000..1222520b --- /dev/null +++ b/sail_latex_mips/overloadJJJz_mod_ivb088aebc9bfea2ab389f62ea44fbb3a9.tex @@ -0,0 +1 @@ +overload _mod_IV = {_get_CauseReg_IV, _set_CauseReg_IV} \ No newline at end of file diff --git a/sail_latex_mips/overloadJJzzw805a9067649c7cfeedcb41b57a7e2c86.tex b/sail_latex_mips/overloadJJzzw805a9067649c7cfeedcb41b57a7e2c86.tex new file mode 100644 index 00000000..3b79da5b --- /dev/null +++ b/sail_latex_mips/overloadJJzzw805a9067649c7cfeedcb41b57a7e2c86.tex @@ -0,0 +1 @@ +overload ~ = {not_bool, not_vec} diff --git a/sail_latex_mips/overloadJzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex b/sail_latex_mips/overloadJzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex new file mode 100644 index 00000000..dfbcc136 --- /dev/null +++ b/sail_latex_mips/overloadJzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex @@ -0,0 +1 @@ +overload operator >= = {gteq_int} diff --git a/sail_latex_mips/overloadKKKKKKKzupdate_sx5980678135ef3f9835076e9f123ea63b.tex b/sail_latex_mips/overloadKKKKKKKzupdate_sx5980678135ef3f9835076e9f123ea63b.tex new file mode 100644 index 00000000..4e416154 --- /dev/null +++ b/sail_latex_mips/overloadKKKKKKKzupdate_sx5980678135ef3f9835076e9f123ea63b.tex @@ -0,0 +1 @@ +overload update_SX = {_update_StatusReg_SX} \ No newline at end of file diff --git a/sail_latex_mips/overloadKKKKKKzupdate_v14252d1d08166b61257da4bf063a2ac6c.tex b/sail_latex_mips/overloadKKKKKKzupdate_v14252d1d08166b61257da4bf063a2ac6c.tex new file mode 100644 index 00000000..5da0a4e9 --- /dev/null +++ b/sail_latex_mips/overloadKKKKKKzupdate_v14252d1d08166b61257da4bf063a2ac6c.tex @@ -0,0 +1 @@ +overload update_v1 = {_update_TLBEntry_v1} \ No newline at end of file diff --git a/sail_latex_mips/overloadKKKKKzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_mips/overloadKKKKKzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..64d81afd --- /dev/null +++ b/sail_latex_mips/overloadKKKKKzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_TLBEntry_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadKKKKzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex b/sail_latex_mips/overloadKKKKzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex new file mode 100644 index 00000000..03a3a143 --- /dev/null +++ b/sail_latex_mips/overloadKKKKzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex @@ -0,0 +1 @@ +overload update_R = {_update_TLBEntryHiReg_R} \ No newline at end of file diff --git a/sail_latex_mips/overloadKKKzupdate_wpb2578310c293c0bfbbb1919aa78e107e.tex b/sail_latex_mips/overloadKKKzupdate_wpb2578310c293c0bfbbb1919aa78e107e.tex new file mode 100644 index 00000000..d4528672 --- /dev/null +++ b/sail_latex_mips/overloadKKKzupdate_wpb2578310c293c0bfbbb1919aa78e107e.tex @@ -0,0 +1 @@ +overload update_WP = {_update_CauseReg_WP} \ No newline at end of file diff --git a/sail_latex_mips/overloadKKznotcbe861867f25b28c34f5ae99957794ed.tex b/sail_latex_mips/overloadKKznotcbe861867f25b28c34f5ae99957794ed.tex new file mode 100644 index 00000000..30523ab7 --- /dev/null +++ b/sail_latex_mips/overloadKKznotcbe861867f25b28c34f5ae99957794ed.tex @@ -0,0 +1 @@ +overload not = {not_bool} diff --git a/sail_latex_mips/overloadKzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex b/sail_latex_mips/overloadKzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex new file mode 100644 index 00000000..86b47f92 --- /dev/null +++ b/sail_latex_mips/overloadKzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex @@ -0,0 +1 @@ +overload operator > = {gt_int} diff --git a/sail_latex_mips/overloadLLLLLLLz_mod_sxba2453170d929599232993cb6cd9b3e8.tex b/sail_latex_mips/overloadLLLLLLLz_mod_sxba2453170d929599232993cb6cd9b3e8.tex new file mode 100644 index 00000000..4ea62484 --- /dev/null +++ b/sail_latex_mips/overloadLLLLLLLz_mod_sxba2453170d929599232993cb6cd9b3e8.tex @@ -0,0 +1 @@ +overload _mod_SX = {_get_StatusReg_SX, _set_StatusReg_SX} \ No newline at end of file diff --git a/sail_latex_mips/overloadLLLLLLz_mod_v1a0cfae3094149828b19dab3880946df6.tex b/sail_latex_mips/overloadLLLLLLz_mod_v1a0cfae3094149828b19dab3880946df6.tex new file mode 100644 index 00000000..30619a05 --- /dev/null +++ b/sail_latex_mips/overloadLLLLLLz_mod_v1a0cfae3094149828b19dab3880946df6.tex @@ -0,0 +1 @@ +overload _mod_v1 = {_get_TLBEntry_v1, _set_TLBEntry_v1} \ No newline at end of file diff --git a/sail_latex_mips/overloadLLLLLz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_mips/overloadLLLLLz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..7f154d12 --- /dev/null +++ b/sail_latex_mips/overloadLLLLLz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_TLBEntry_bits, _set_TLBEntry_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadLLLLz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex b/sail_latex_mips/overloadLLLLz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex new file mode 100644 index 00000000..85ef85fa --- /dev/null +++ b/sail_latex_mips/overloadLLLLz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex @@ -0,0 +1 @@ +overload _mod_R = {_get_TLBEntryHiReg_R, _set_TLBEntryHiReg_R} \ No newline at end of file diff --git a/sail_latex_mips/overloadLLLz_mod_wp16ea1a9b8f1e9595a992f51656917f4c.tex b/sail_latex_mips/overloadLLLz_mod_wp16ea1a9b8f1e9595a992f51656917f4c.tex new file mode 100644 index 00000000..1ab7fbf7 --- /dev/null +++ b/sail_latex_mips/overloadLLLz_mod_wp16ea1a9b8f1e9595a992f51656917f4c.tex @@ -0,0 +1 @@ +overload _mod_WP = {_get_CauseReg_WP, _set_CauseReg_WP} \ No newline at end of file diff --git a/sail_latex_mips/overloadLLzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex b/sail_latex_mips/overloadLLzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex new file mode 100644 index 00000000..5fa1886a --- /dev/null +++ b/sail_latex_mips/overloadLLzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex @@ -0,0 +1 @@ +overload operator != = {neq_anything} diff --git a/sail_latex_mips/overloadLz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex b/sail_latex_mips/overloadLz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex new file mode 100644 index 00000000..ec898306 --- /dev/null +++ b/sail_latex_mips/overloadLz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex @@ -0,0 +1 @@ +overload __size = {__id} diff --git a/sail_latex_mips/overloadMMMMMMMzupdate_uxccea386a1abae1373e5e385a6585f028.tex b/sail_latex_mips/overloadMMMMMMMzupdate_uxccea386a1abae1373e5e385a6585f028.tex new file mode 100644 index 00000000..d0d2a663 --- /dev/null +++ b/sail_latex_mips/overloadMMMMMMMzupdate_uxccea386a1abae1373e5e385a6585f028.tex @@ -0,0 +1 @@ +overload update_UX = {_update_StatusReg_UX} \ No newline at end of file diff --git a/sail_latex_mips/overloadMMMMMMzupdate_caplg0359c196dd43c44a7240d7baa93725c98.tex b/sail_latex_mips/overloadMMMMMMzupdate_caplg0359c196dd43c44a7240d7baa93725c98.tex new file mode 100644 index 00000000..80844c7f --- /dev/null +++ b/sail_latex_mips/overloadMMMMMMzupdate_caplg0359c196dd43c44a7240d7baa93725c98.tex @@ -0,0 +1 @@ +overload update_caplg0 = {_update_TLBEntry_caplg0} \ No newline at end of file diff --git a/sail_latex_mips/overloadMMMMMzupdate_pagemaskc94cf18779cd739c7f8909b768b97fb8.tex b/sail_latex_mips/overloadMMMMMzupdate_pagemaskc94cf18779cd739c7f8909b768b97fb8.tex new file mode 100644 index 00000000..e57ea1df --- /dev/null +++ b/sail_latex_mips/overloadMMMMMzupdate_pagemaskc94cf18779cd739c7f8909b768b97fb8.tex @@ -0,0 +1 @@ +overload update_pagemask = {_update_TLBEntry_pagemask} \ No newline at end of file diff --git a/sail_latex_mips/overloadMMMMzupdate_clgk1d75cd5573a5f7f252a6ee39f19e5a48.tex b/sail_latex_mips/overloadMMMMzupdate_clgk1d75cd5573a5f7f252a6ee39f19e5a48.tex new file mode 100644 index 00000000..e29039ac --- /dev/null +++ b/sail_latex_mips/overloadMMMMzupdate_clgk1d75cd5573a5f7f252a6ee39f19e5a48.tex @@ -0,0 +1 @@ +overload update_CLGK = {_update_TLBEntryHiReg_CLGK} \ No newline at end of file diff --git a/sail_latex_mips/overloadMMMzupdate_ip04d62e571c5f0df4e13fef5ee848bfb6.tex b/sail_latex_mips/overloadMMMzupdate_ip04d62e571c5f0df4e13fef5ee848bfb6.tex new file mode 100644 index 00000000..1b855a0b --- /dev/null +++ b/sail_latex_mips/overloadMMMzupdate_ip04d62e571c5f0df4e13fef5ee848bfb6.tex @@ -0,0 +1 @@ +overload update_IP = {_update_CauseReg_IP} \ No newline at end of file diff --git a/sail_latex_mips/overloadMMzprintc9b8c9c569def1934362480628956c85.tex b/sail_latex_mips/overloadMMzprintc9b8c9c569def1934362480628956c85.tex new file mode 100644 index 00000000..e2509acc --- /dev/null +++ b/sail_latex_mips/overloadMMzprintc9b8c9c569def1934362480628956c85.tex @@ -0,0 +1 @@ +overload print = {print_endline} diff --git a/sail_latex_mips/overloadMzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex b/sail_latex_mips/overloadMzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex new file mode 100644 index 00000000..2b2f05b1 --- /dev/null +++ b/sail_latex_mips/overloadMzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex @@ -0,0 +1 @@ +overload operator + = {add_atom, add_int} diff --git a/sail_latex_mips/overloadNNNNNNNz_mod_uxcb4904e2e9ec40177ef84b51b9cfd37a.tex b/sail_latex_mips/overloadNNNNNNNz_mod_uxcb4904e2e9ec40177ef84b51b9cfd37a.tex new file mode 100644 index 00000000..aa31242d --- /dev/null +++ b/sail_latex_mips/overloadNNNNNNNz_mod_uxcb4904e2e9ec40177ef84b51b9cfd37a.tex @@ -0,0 +1 @@ +overload _mod_UX = {_get_StatusReg_UX, _set_StatusReg_UX} \ No newline at end of file diff --git a/sail_latex_mips/overloadNNNNNNz_mod_caplg02551d3482d21e938bc88d44876afb940.tex b/sail_latex_mips/overloadNNNNNNz_mod_caplg02551d3482d21e938bc88d44876afb940.tex new file mode 100644 index 00000000..6b300e6a --- /dev/null +++ b/sail_latex_mips/overloadNNNNNNz_mod_caplg02551d3482d21e938bc88d44876afb940.tex @@ -0,0 +1 @@ +overload _mod_caplg0 = {_get_TLBEntry_caplg0, _set_TLBEntry_caplg0} \ No newline at end of file diff --git a/sail_latex_mips/overloadNNNNNz_mod_pagemask324eab4b891010bfc717c1f9165ad98d.tex b/sail_latex_mips/overloadNNNNNz_mod_pagemask324eab4b891010bfc717c1f9165ad98d.tex new file mode 100644 index 00000000..130ccab2 --- /dev/null +++ b/sail_latex_mips/overloadNNNNNz_mod_pagemask324eab4b891010bfc717c1f9165ad98d.tex @@ -0,0 +1 @@ +overload _mod_pagemask = {_get_TLBEntry_pagemask, _set_TLBEntry_pagemask} \ No newline at end of file diff --git a/sail_latex_mips/overloadNNNNz_mod_clgkd08fc6d828d08c1745c289a488c357c7.tex b/sail_latex_mips/overloadNNNNz_mod_clgkd08fc6d828d08c1745c289a488c357c7.tex new file mode 100644 index 00000000..b20c5059 --- /dev/null +++ b/sail_latex_mips/overloadNNNNz_mod_clgkd08fc6d828d08c1745c289a488c357c7.tex @@ -0,0 +1 @@ +overload _mod_CLGK = {_get_TLBEntryHiReg_CLGK, _set_TLBEntryHiReg_CLGK} \ No newline at end of file diff --git a/sail_latex_mips/overloadNNNz_mod_ipe8feebf60b7d37429ca83cdc1369f3b4.tex b/sail_latex_mips/overloadNNNz_mod_ipe8feebf60b7d37429ca83cdc1369f3b4.tex new file mode 100644 index 00000000..361230bf --- /dev/null +++ b/sail_latex_mips/overloadNNNz_mod_ipe8feebf60b7d37429ca83cdc1369f3b4.tex @@ -0,0 +1 @@ +overload _mod_IP = {_get_CauseReg_IP, _set_CauseReg_IP} \ No newline at end of file diff --git a/sail_latex_mips/overloadNNzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex b/sail_latex_mips/overloadNNzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex new file mode 100644 index 00000000..5de31eee --- /dev/null +++ b/sail_latex_mips/overloadNNzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex @@ -0,0 +1 @@ +overload operator ^ = {xor_vec, int_power, concat_str} diff --git a/sail_latex_mips/overloadNzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex b/sail_latex_mips/overloadNzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex new file mode 100644 index 00000000..15a078ce --- /dev/null +++ b/sail_latex_mips/overloadNzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex @@ -0,0 +1 @@ +overload operator - = {sub_atom, sub_int} diff --git a/sail_latex_mips/overloadOOOOOOOzupdate_ksu4fc7e63c0a91673b7b5e846838116134.tex b/sail_latex_mips/overloadOOOOOOOzupdate_ksu4fc7e63c0a91673b7b5e846838116134.tex new file mode 100644 index 00000000..b5688537 --- /dev/null +++ b/sail_latex_mips/overloadOOOOOOOzupdate_ksu4fc7e63c0a91673b7b5e846838116134.tex @@ -0,0 +1 @@ +overload update_KSU = {_update_StatusReg_KSU} \ No newline at end of file diff --git a/sail_latex_mips/overloadOOOOOOzupdate_caps04531fbe85f52baa76fbfc27f443b0c46.tex b/sail_latex_mips/overloadOOOOOOzupdate_caps04531fbe85f52baa76fbfc27f443b0c46.tex new file mode 100644 index 00000000..1791d720 --- /dev/null +++ b/sail_latex_mips/overloadOOOOOOzupdate_caps04531fbe85f52baa76fbfc27f443b0c46.tex @@ -0,0 +1 @@ +overload update_caps0 = {_update_TLBEntry_caps0} \ No newline at end of file diff --git a/sail_latex_mips/overloadOOOOOzupdate_rce22633bb855a1c8b994977adc9d3b46.tex b/sail_latex_mips/overloadOOOOOzupdate_rce22633bb855a1c8b994977adc9d3b46.tex new file mode 100644 index 00000000..485fdf99 --- /dev/null +++ b/sail_latex_mips/overloadOOOOOzupdate_rce22633bb855a1c8b994977adc9d3b46.tex @@ -0,0 +1 @@ +overload update_r = {_update_TLBEntry_r} \ No newline at end of file diff --git a/sail_latex_mips/overloadOOOOzupdate_clgs3865dc13c1369c4c0ed0f110f40dc15c.tex b/sail_latex_mips/overloadOOOOzupdate_clgs3865dc13c1369c4c0ed0f110f40dc15c.tex new file mode 100644 index 00000000..34c84928 --- /dev/null +++ b/sail_latex_mips/overloadOOOOzupdate_clgs3865dc13c1369c4c0ed0f110f40dc15c.tex @@ -0,0 +1 @@ +overload update_CLGS = {_update_TLBEntryHiReg_CLGS} \ No newline at end of file diff --git a/sail_latex_mips/overloadOOOzupdate_exccode286b5e0163b588d6fbc04a06efd36aa1.tex b/sail_latex_mips/overloadOOOzupdate_exccode286b5e0163b588d6fbc04a06efd36aa1.tex new file mode 100644 index 00000000..041de51c --- /dev/null +++ b/sail_latex_mips/overloadOOOzupdate_exccode286b5e0163b588d6fbc04a06efd36aa1.tex @@ -0,0 +1 @@ +overload update_ExcCode = {_update_CauseReg_ExcCode} \ No newline at end of file diff --git a/sail_latex_mips/overloadOOzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex b/sail_latex_mips/overloadOOzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex new file mode 100644 index 00000000..fcf2d81f --- /dev/null +++ b/sail_latex_mips/overloadOOzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex @@ -0,0 +1 @@ +overload operator + = {add_range, add_int, add_vec, add_vec_int} diff --git a/sail_latex_mips/overloadOznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex b/sail_latex_mips/overloadOznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex new file mode 100644 index 00000000..335dc856 --- /dev/null +++ b/sail_latex_mips/overloadOznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex @@ -0,0 +1 @@ +overload negate = {negate_atom, negate_int} diff --git a/sail_latex_mips/overloadPPPPPPPz_mod_ksu36b842dd8b87192857fac2c000672740.tex b/sail_latex_mips/overloadPPPPPPPz_mod_ksu36b842dd8b87192857fac2c000672740.tex new file mode 100644 index 00000000..7cff9a26 --- /dev/null +++ b/sail_latex_mips/overloadPPPPPPPz_mod_ksu36b842dd8b87192857fac2c000672740.tex @@ -0,0 +1 @@ +overload _mod_KSU = {_get_StatusReg_KSU, _set_StatusReg_KSU} \ No newline at end of file diff --git a/sail_latex_mips/overloadPPPPPPz_mod_caps01dd0b1fbe9d02d2c772e450c0c776db0.tex b/sail_latex_mips/overloadPPPPPPz_mod_caps01dd0b1fbe9d02d2c772e450c0c776db0.tex new file mode 100644 index 00000000..36fbc5bb --- /dev/null +++ b/sail_latex_mips/overloadPPPPPPz_mod_caps01dd0b1fbe9d02d2c772e450c0c776db0.tex @@ -0,0 +1 @@ +overload _mod_caps0 = {_get_TLBEntry_caps0, _set_TLBEntry_caps0} \ No newline at end of file diff --git a/sail_latex_mips/overloadPPPPPz_mod_r9af13eeb7ae69634b901ce634288d493.tex b/sail_latex_mips/overloadPPPPPz_mod_r9af13eeb7ae69634b901ce634288d493.tex new file mode 100644 index 00000000..ca85fe92 --- /dev/null +++ b/sail_latex_mips/overloadPPPPPz_mod_r9af13eeb7ae69634b901ce634288d493.tex @@ -0,0 +1 @@ +overload _mod_r = {_get_TLBEntry_r, _set_TLBEntry_r} \ No newline at end of file diff --git a/sail_latex_mips/overloadPPPPz_mod_clgsb2cb4479fedb595ba53b27015c4e69b4.tex b/sail_latex_mips/overloadPPPPz_mod_clgsb2cb4479fedb595ba53b27015c4e69b4.tex new file mode 100644 index 00000000..db6ff252 --- /dev/null +++ b/sail_latex_mips/overloadPPPPz_mod_clgsb2cb4479fedb595ba53b27015c4e69b4.tex @@ -0,0 +1 @@ +overload _mod_CLGS = {_get_TLBEntryHiReg_CLGS, _set_TLBEntryHiReg_CLGS} \ No newline at end of file diff --git a/sail_latex_mips/overloadPPPz_mod_exccode24886ea7a19912378ba2030097458ff1.tex b/sail_latex_mips/overloadPPPz_mod_exccode24886ea7a19912378ba2030097458ff1.tex new file mode 100644 index 00000000..95bd4a1b --- /dev/null +++ b/sail_latex_mips/overloadPPPz_mod_exccode24886ea7a19912378ba2030097458ff1.tex @@ -0,0 +1 @@ +overload _mod_ExcCode = {_get_CauseReg_ExcCode, _set_CauseReg_ExcCode} \ No newline at end of file diff --git a/sail_latex_mips/overloadPPzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex b/sail_latex_mips/overloadPPzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex new file mode 100644 index 00000000..58be6497 --- /dev/null +++ b/sail_latex_mips/overloadPPzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex @@ -0,0 +1 @@ +overload operator - = {sub_range, sub_int, sub_vec, sub_vec_int} diff --git a/sail_latex_mips/overloadPzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex b/sail_latex_mips/overloadPzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex new file mode 100644 index 00000000..9e2c8c85 --- /dev/null +++ b/sail_latex_mips/overloadPzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex @@ -0,0 +1 @@ +overload operator * = {mult_atom, mult_int} diff --git a/sail_latex_mips/overloadQQQQQQQzupdate_erl7a543a72f3f62df97cce89d42e9c61af.tex b/sail_latex_mips/overloadQQQQQQQzupdate_erl7a543a72f3f62df97cce89d42e9c61af.tex new file mode 100644 index 00000000..d1f9da12 --- /dev/null +++ b/sail_latex_mips/overloadQQQQQQQzupdate_erl7a543a72f3f62df97cce89d42e9c61af.tex @@ -0,0 +1 @@ +overload update_ERL = {_update_StatusReg_ERL} \ No newline at end of file diff --git a/sail_latex_mips/overloadQQQQQQzupdate_capl04aa55c1d4284f9eacf5ccdab3c24fb08.tex b/sail_latex_mips/overloadQQQQQQzupdate_capl04aa55c1d4284f9eacf5ccdab3c24fb08.tex new file mode 100644 index 00000000..11747581 --- /dev/null +++ b/sail_latex_mips/overloadQQQQQQzupdate_capl04aa55c1d4284f9eacf5ccdab3c24fb08.tex @@ -0,0 +1 @@ +overload update_capl0 = {_update_TLBEntry_capl0} \ No newline at end of file diff --git a/sail_latex_mips/overloadQQQQQzupdate_vpn2865beffbfb51948cd997d2f75fbf5170.tex b/sail_latex_mips/overloadQQQQQzupdate_vpn2865beffbfb51948cd997d2f75fbf5170.tex new file mode 100644 index 00000000..b4743a0c --- /dev/null +++ b/sail_latex_mips/overloadQQQQQzupdate_vpn2865beffbfb51948cd997d2f75fbf5170.tex @@ -0,0 +1 @@ +overload update_vpn2 = {_update_TLBEntry_vpn2} \ No newline at end of file diff --git a/sail_latex_mips/overloadQQQQzupdate_clgubec52b9e8fec05b1bfd801a107f6888b.tex b/sail_latex_mips/overloadQQQQzupdate_clgubec52b9e8fec05b1bfd801a107f6888b.tex new file mode 100644 index 00000000..5a3cc03a --- /dev/null +++ b/sail_latex_mips/overloadQQQQzupdate_clgubec52b9e8fec05b1bfd801a107f6888b.tex @@ -0,0 +1 @@ +overload update_CLGU = {_update_TLBEntryHiReg_CLGU} \ No newline at end of file diff --git a/sail_latex_mips/overloadQQQzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_mips/overloadQQQzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..60c5e7a6 --- /dev/null +++ b/sail_latex_mips/overloadQQQzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_TLBEntryLoReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadQQznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex b/sail_latex_mips/overloadQQznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex new file mode 100644 index 00000000..67dd7073 --- /dev/null +++ b/sail_latex_mips/overloadQQznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex @@ -0,0 +1 @@ +overload negate = {negate_range, negate_int} diff --git a/sail_latex_mips/overloadQzshl_int4772030e3fc0913189e795ec25e86dc5.tex b/sail_latex_mips/overloadQzshl_int4772030e3fc0913189e795ec25e86dc5.tex new file mode 100644 index 00000000..0aba6dd2 --- /dev/null +++ b/sail_latex_mips/overloadQzshl_int4772030e3fc0913189e795ec25e86dc5.tex @@ -0,0 +1 @@ +overload shl_int = {_shl1, _shl8, _shl32, _shl_int} diff --git a/sail_latex_mips/overloadRRRRRRRz_mod_erlfbb04d75a1342f1a5085a19a27d8dc07.tex b/sail_latex_mips/overloadRRRRRRRz_mod_erlfbb04d75a1342f1a5085a19a27d8dc07.tex new file mode 100644 index 00000000..b334b7dc --- /dev/null +++ b/sail_latex_mips/overloadRRRRRRRz_mod_erlfbb04d75a1342f1a5085a19a27d8dc07.tex @@ -0,0 +1 @@ +overload _mod_ERL = {_get_StatusReg_ERL, _set_StatusReg_ERL} \ No newline at end of file diff --git a/sail_latex_mips/overloadRRRRRRz_mod_capl0933e030a2faa459f5db9e9c3882a7ece.tex b/sail_latex_mips/overloadRRRRRRz_mod_capl0933e030a2faa459f5db9e9c3882a7ece.tex new file mode 100644 index 00000000..91969233 --- /dev/null +++ b/sail_latex_mips/overloadRRRRRRz_mod_capl0933e030a2faa459f5db9e9c3882a7ece.tex @@ -0,0 +1 @@ +overload _mod_capl0 = {_get_TLBEntry_capl0, _set_TLBEntry_capl0} \ No newline at end of file diff --git a/sail_latex_mips/overloadRRRRRz_mod_vpn25e147a36ddcf1023cffabc717f9bd2da.tex b/sail_latex_mips/overloadRRRRRz_mod_vpn25e147a36ddcf1023cffabc717f9bd2da.tex new file mode 100644 index 00000000..08cd1947 --- /dev/null +++ b/sail_latex_mips/overloadRRRRRz_mod_vpn25e147a36ddcf1023cffabc717f9bd2da.tex @@ -0,0 +1 @@ +overload _mod_vpn2 = {_get_TLBEntry_vpn2, _set_TLBEntry_vpn2} \ No newline at end of file diff --git a/sail_latex_mips/overloadRRRRz_mod_clgu3d6fa470ec4a04451aa9e951adaa6909.tex b/sail_latex_mips/overloadRRRRz_mod_clgu3d6fa470ec4a04451aa9e951adaa6909.tex new file mode 100644 index 00000000..873184fe --- /dev/null +++ b/sail_latex_mips/overloadRRRRz_mod_clgu3d6fa470ec4a04451aa9e951adaa6909.tex @@ -0,0 +1 @@ +overload _mod_CLGU = {_get_TLBEntryHiReg_CLGU, _set_TLBEntryHiReg_CLGU} \ No newline at end of file diff --git a/sail_latex_mips/overloadRRRz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_mips/overloadRRRz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..7ba9e37c --- /dev/null +++ b/sail_latex_mips/overloadRRRz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_TLBEntryLoReg_bits, _set_TLBEntryLoReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadRRzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex b/sail_latex_mips/overloadRRzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex new file mode 100644 index 00000000..58465290 --- /dev/null +++ b/sail_latex_mips/overloadRRzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex @@ -0,0 +1 @@ +overload operator * = {mult_int} diff --git a/sail_latex_mips/overloadRzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex b/sail_latex_mips/overloadRzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex new file mode 100644 index 00000000..be2ecb2a --- /dev/null +++ b/sail_latex_mips/overloadRzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex @@ -0,0 +1 @@ +overload shr_int = {_shr32, _shr_int} diff --git a/sail_latex_mips/overloadSSSSSSSzupdate_exl309dd848770b0a36e5ff6acac4ecce98.tex b/sail_latex_mips/overloadSSSSSSSzupdate_exl309dd848770b0a36e5ff6acac4ecce98.tex new file mode 100644 index 00000000..9d82b64d --- /dev/null +++ b/sail_latex_mips/overloadSSSSSSSzupdate_exl309dd848770b0a36e5ff6acac4ecce98.tex @@ -0,0 +1 @@ +overload update_EXL = {_update_StatusReg_EXL} \ No newline at end of file diff --git a/sail_latex_mips/overloadSSSSSSzupdate_pfn06b632277e9d982792668ad250ca9f560.tex b/sail_latex_mips/overloadSSSSSSzupdate_pfn06b632277e9d982792668ad250ca9f560.tex new file mode 100644 index 00000000..54244083 --- /dev/null +++ b/sail_latex_mips/overloadSSSSSSzupdate_pfn06b632277e9d982792668ad250ca9f560.tex @@ -0,0 +1 @@ +overload update_pfn0 = {_update_TLBEntry_pfn0} \ No newline at end of file diff --git a/sail_latex_mips/overloadSSSSSzupdate_asid326dfb0feb114271dfb6df15f22a2ec1.tex b/sail_latex_mips/overloadSSSSSzupdate_asid326dfb0feb114271dfb6df15f22a2ec1.tex new file mode 100644 index 00000000..8fa9f60a --- /dev/null +++ b/sail_latex_mips/overloadSSSSSzupdate_asid326dfb0feb114271dfb6df15f22a2ec1.tex @@ -0,0 +1 @@ +overload update_asid = {_update_TLBEntry_asid} \ No newline at end of file diff --git a/sail_latex_mips/overloadSSSSzupdate_vpn220be6c7a0b8945ad28c3a3e621dd8e79.tex b/sail_latex_mips/overloadSSSSzupdate_vpn220be6c7a0b8945ad28c3a3e621dd8e79.tex new file mode 100644 index 00000000..e2b42a9a --- /dev/null +++ b/sail_latex_mips/overloadSSSSzupdate_vpn220be6c7a0b8945ad28c3a3e621dd8e79.tex @@ -0,0 +1 @@ +overload update_VPN2 = {_update_TLBEntryHiReg_VPN2} \ No newline at end of file diff --git a/sail_latex_mips/overloadSSSzupdate_caps182d8368466ed813c4844f76ddfa2941.tex b/sail_latex_mips/overloadSSSzupdate_caps182d8368466ed813c4844f76ddfa2941.tex new file mode 100644 index 00000000..dfe685ee --- /dev/null +++ b/sail_latex_mips/overloadSSSzupdate_caps182d8368466ed813c4844f76ddfa2941.tex @@ -0,0 +1 @@ +overload update_CapS = {_update_TLBEntryLoReg_CapS} \ No newline at end of file diff --git a/sail_latex_mips/overloadSSzz8operatorz0zfz9413c2bc7cb07ce1db42a50ad1459c051.tex b/sail_latex_mips/overloadSSzz8operatorz0zfz9413c2bc7cb07ce1db42a50ad1459c051.tex new file mode 100644 index 00000000..1bacba9f --- /dev/null +++ b/sail_latex_mips/overloadSSzz8operatorz0zfz9413c2bc7cb07ce1db42a50ad1459c051.tex @@ -0,0 +1 @@ +overload operator / = {ediv_int, div} diff --git a/sail_latex_mips/overloadSztmod_int76b131b53b88df8b201279295eacebbe.tex b/sail_latex_mips/overloadSztmod_int76b131b53b88df8b201279295eacebbe.tex new file mode 100644 index 00000000..7a8e2210 --- /dev/null +++ b/sail_latex_mips/overloadSztmod_int76b131b53b88df8b201279295eacebbe.tex @@ -0,0 +1 @@ +overload tmod_int = {_tmod_int_positive, _tmod_int} diff --git a/sail_latex_mips/overloadTTTTTTTz_mod_exl357e313bacd4edb774aa1ef0b156e134.tex b/sail_latex_mips/overloadTTTTTTTz_mod_exl357e313bacd4edb774aa1ef0b156e134.tex new file mode 100644 index 00000000..16b2bc8c --- /dev/null +++ b/sail_latex_mips/overloadTTTTTTTz_mod_exl357e313bacd4edb774aa1ef0b156e134.tex @@ -0,0 +1 @@ +overload _mod_EXL = {_get_StatusReg_EXL, _set_StatusReg_EXL} \ No newline at end of file diff --git a/sail_latex_mips/overloadTTTTTTz_mod_pfn0252a199d91d6fa495671378701e0ec97.tex b/sail_latex_mips/overloadTTTTTTz_mod_pfn0252a199d91d6fa495671378701e0ec97.tex new file mode 100644 index 00000000..e3e2bfb2 --- /dev/null +++ b/sail_latex_mips/overloadTTTTTTz_mod_pfn0252a199d91d6fa495671378701e0ec97.tex @@ -0,0 +1 @@ +overload _mod_pfn0 = {_get_TLBEntry_pfn0, _set_TLBEntry_pfn0} \ No newline at end of file diff --git a/sail_latex_mips/overloadTTTTTz_mod_asid57efb91e5ea152ff241933923e49a84a.tex b/sail_latex_mips/overloadTTTTTz_mod_asid57efb91e5ea152ff241933923e49a84a.tex new file mode 100644 index 00000000..b80fbc05 --- /dev/null +++ b/sail_latex_mips/overloadTTTTTz_mod_asid57efb91e5ea152ff241933923e49a84a.tex @@ -0,0 +1 @@ +overload _mod_asid = {_get_TLBEntry_asid, _set_TLBEntry_asid} \ No newline at end of file diff --git a/sail_latex_mips/overloadTTTTz_mod_vpn28c8a281e6dcbd5a2c649a7902b509b16.tex b/sail_latex_mips/overloadTTTTz_mod_vpn28c8a281e6dcbd5a2c649a7902b509b16.tex new file mode 100644 index 00000000..7de971a8 --- /dev/null +++ b/sail_latex_mips/overloadTTTTz_mod_vpn28c8a281e6dcbd5a2c649a7902b509b16.tex @@ -0,0 +1 @@ +overload _mod_VPN2 = {_get_TLBEntryHiReg_VPN2, _set_TLBEntryHiReg_VPN2} \ No newline at end of file diff --git a/sail_latex_mips/overloadTTTz_mod_capsa1d49b1f09b7425502aaa6953965c67a.tex b/sail_latex_mips/overloadTTTz_mod_capsa1d49b1f09b7425502aaa6953965c67a.tex new file mode 100644 index 00000000..bdacef07 --- /dev/null +++ b/sail_latex_mips/overloadTTTz_mod_capsa1d49b1f09b7425502aaa6953965c67a.tex @@ -0,0 +1 @@ +overload _mod_CapS = {_get_TLBEntryLoReg_CapS, _set_TLBEntryLoReg_CapS} \ No newline at end of file diff --git a/sail_latex_mips/overloadTTzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex b/sail_latex_mips/overloadTTzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex new file mode 100644 index 00000000..df6e19c0 --- /dev/null +++ b/sail_latex_mips/overloadTTzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex @@ -0,0 +1 @@ +overload operator % = {emod_int, mod} diff --git a/sail_latex_mips/overloadTzabs_intef5fbb521189282054dc80dc7173013d.tex b/sail_latex_mips/overloadTzabs_intef5fbb521189282054dc80dc7173013d.tex new file mode 100644 index 00000000..6598a227 --- /dev/null +++ b/sail_latex_mips/overloadTzabs_intef5fbb521189282054dc80dc7173013d.tex @@ -0,0 +1 @@ +overload abs_int = {abs_int_plain} diff --git a/sail_latex_mips/overloadUUUUUUUzupdate_ie315fd57324c5c7cae42210a2b9ce386e.tex b/sail_latex_mips/overloadUUUUUUUzupdate_ie315fd57324c5c7cae42210a2b9ce386e.tex new file mode 100644 index 00000000..421e8744 --- /dev/null +++ b/sail_latex_mips/overloadUUUUUUUzupdate_ie315fd57324c5c7cae42210a2b9ce386e.tex @@ -0,0 +1 @@ +overload update_IE = {_update_StatusReg_IE} \ No newline at end of file diff --git a/sail_latex_mips/overloadUUUUUUzupdate_c088d2acc9880658f13c362f6dc5200a76.tex b/sail_latex_mips/overloadUUUUUUzupdate_c088d2acc9880658f13c362f6dc5200a76.tex new file mode 100644 index 00000000..ccb2da58 --- /dev/null +++ b/sail_latex_mips/overloadUUUUUUzupdate_c088d2acc9880658f13c362f6dc5200a76.tex @@ -0,0 +1 @@ +overload update_c0 = {_update_TLBEntry_c0} \ No newline at end of file diff --git a/sail_latex_mips/overloadUUUUUzupdate_ga643ac581ef3df825870fe6e052d11dd.tex b/sail_latex_mips/overloadUUUUUzupdate_ga643ac581ef3df825870fe6e052d11dd.tex new file mode 100644 index 00000000..988d87b6 --- /dev/null +++ b/sail_latex_mips/overloadUUUUUzupdate_ga643ac581ef3df825870fe6e052d11dd.tex @@ -0,0 +1 @@ +overload update_g = {_update_TLBEntry_g} \ No newline at end of file diff --git a/sail_latex_mips/overloadUUUUzupdate_asid68eb6e5d121a0aa3f8a040a0f4751c40.tex b/sail_latex_mips/overloadUUUUzupdate_asid68eb6e5d121a0aa3f8a040a0f4751c40.tex new file mode 100644 index 00000000..f415980a --- /dev/null +++ b/sail_latex_mips/overloadUUUUzupdate_asid68eb6e5d121a0aa3f8a040a0f4751c40.tex @@ -0,0 +1 @@ +overload update_ASID = {_update_TLBEntryHiReg_ASID} \ No newline at end of file diff --git a/sail_latex_mips/overloadUUUzupdate_capl39cb169bd618aef99d542cc3963c1b03.tex b/sail_latex_mips/overloadUUUzupdate_capl39cb169bd618aef99d542cc3963c1b03.tex new file mode 100644 index 00000000..7b0d8471 --- /dev/null +++ b/sail_latex_mips/overloadUUUzupdate_capl39cb169bd618aef99d542cc3963c1b03.tex @@ -0,0 +1 @@ +overload update_CapL = {_update_TLBEntryLoReg_CapL} \ No newline at end of file diff --git a/sail_latex_mips/overloadUUzmin95ae3c0ebde1421750e6db87bdf74801.tex b/sail_latex_mips/overloadUUzmin95ae3c0ebde1421750e6db87bdf74801.tex new file mode 100644 index 00000000..665f1bea --- /dev/null +++ b/sail_latex_mips/overloadUUzmin95ae3c0ebde1421750e6db87bdf74801.tex @@ -0,0 +1 @@ +overload min = {min_atom, min_nat, min_int} diff --git a/sail_latex_mips/overloadUzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_mips/overloadUzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex new file mode 100644 index 00000000..49daed5c --- /dev/null +++ b/sail_latex_mips/overloadUzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex @@ -0,0 +1 @@ +overload operator == = {eq_bit, eq_bits} diff --git a/sail_latex_mips/overloadVVVVVVVz_mod_ie0ede9f8235b89b5d2499f8cd2edeb1d6.tex b/sail_latex_mips/overloadVVVVVVVz_mod_ie0ede9f8235b89b5d2499f8cd2edeb1d6.tex new file mode 100644 index 00000000..940ad6f3 --- /dev/null +++ b/sail_latex_mips/overloadVVVVVVVz_mod_ie0ede9f8235b89b5d2499f8cd2edeb1d6.tex @@ -0,0 +1 @@ +overload _mod_IE = {_get_StatusReg_IE, _set_StatusReg_IE} \ No newline at end of file diff --git a/sail_latex_mips/overloadVVVVVVz_mod_c01d0fea16f0e52022abf675f827cc5045.tex b/sail_latex_mips/overloadVVVVVVz_mod_c01d0fea16f0e52022abf675f827cc5045.tex new file mode 100644 index 00000000..56a19643 --- /dev/null +++ b/sail_latex_mips/overloadVVVVVVz_mod_c01d0fea16f0e52022abf675f827cc5045.tex @@ -0,0 +1 @@ +overload _mod_c0 = {_get_TLBEntry_c0, _set_TLBEntry_c0} \ No newline at end of file diff --git a/sail_latex_mips/overloadVVVVVz_mod_gf55a79d4c50aa120c58f85267f7f6a6a.tex b/sail_latex_mips/overloadVVVVVz_mod_gf55a79d4c50aa120c58f85267f7f6a6a.tex new file mode 100644 index 00000000..6c46a49a --- /dev/null +++ b/sail_latex_mips/overloadVVVVVz_mod_gf55a79d4c50aa120c58f85267f7f6a6a.tex @@ -0,0 +1 @@ +overload _mod_g = {_get_TLBEntry_g, _set_TLBEntry_g} \ No newline at end of file diff --git a/sail_latex_mips/overloadVVVVz_mod_asid4980346bfaaf5eeb3565141f722852d6.tex b/sail_latex_mips/overloadVVVVz_mod_asid4980346bfaaf5eeb3565141f722852d6.tex new file mode 100644 index 00000000..4e4c154c --- /dev/null +++ b/sail_latex_mips/overloadVVVVz_mod_asid4980346bfaaf5eeb3565141f722852d6.tex @@ -0,0 +1 @@ +overload _mod_ASID = {_get_TLBEntryHiReg_ASID, _set_TLBEntryHiReg_ASID} \ No newline at end of file diff --git a/sail_latex_mips/overloadVVVz_mod_capl59410c98d5bb0afa60ac05ecd01d9fdd.tex b/sail_latex_mips/overloadVVVz_mod_capl59410c98d5bb0afa60ac05ecd01d9fdd.tex new file mode 100644 index 00000000..1e92b0d4 --- /dev/null +++ b/sail_latex_mips/overloadVVVz_mod_capl59410c98d5bb0afa60ac05ecd01d9fdd.tex @@ -0,0 +1 @@ +overload _mod_CapL = {_get_TLBEntryLoReg_CapL, _set_TLBEntryLoReg_CapL} \ No newline at end of file diff --git a/sail_latex_mips/overloadVVzmax91b641c464c0dc87660499321a356d93.tex b/sail_latex_mips/overloadVVzmax91b641c464c0dc87660499321a356d93.tex new file mode 100644 index 00000000..3fb7929b --- /dev/null +++ b/sail_latex_mips/overloadVVzmax91b641c464c0dc87660499321a356d93.tex @@ -0,0 +1 @@ +overload max = {max_atom, max_nat, max_int} diff --git a/sail_latex_mips/overloadVzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex b/sail_latex_mips/overloadVzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex new file mode 100644 index 00000000..a97ec66d --- /dev/null +++ b/sail_latex_mips/overloadVzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex @@ -0,0 +1 @@ +overload operator != = {neq_bits} diff --git a/sail_latex_mips/overloadWWWWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_mips/overloadWWWWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..84c93c53 --- /dev/null +++ b/sail_latex_mips/overloadWWWWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_CapCauseReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadWWWWWWzupdate_d0fb9c19324c8c7805805d2aa368b9f928.tex b/sail_latex_mips/overloadWWWWWWzupdate_d0fb9c19324c8c7805805d2aa368b9f928.tex new file mode 100644 index 00000000..799b9f2f --- /dev/null +++ b/sail_latex_mips/overloadWWWWWWzupdate_d0fb9c19324c8c7805805d2aa368b9f928.tex @@ -0,0 +1 @@ +overload update_d0 = {_update_TLBEntry_d0} \ No newline at end of file diff --git a/sail_latex_mips/overloadWWWWWzupdate_validbb04574208bf9cb85093acf3fade71d1.tex b/sail_latex_mips/overloadWWWWWzupdate_validbb04574208bf9cb85093acf3fade71d1.tex new file mode 100644 index 00000000..9c19b5b5 --- /dev/null +++ b/sail_latex_mips/overloadWWWWWzupdate_validbb04574208bf9cb85093acf3fade71d1.tex @@ -0,0 +1 @@ +overload update_valid = {_update_TLBEntry_valid} \ No newline at end of file diff --git a/sail_latex_mips/overloadWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_mips/overloadWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..c4d81402 --- /dev/null +++ b/sail_latex_mips/overloadWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_ContextReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadWWWzupdate_caplgb9408b2c97a868b24bf4fafd9a974c0d.tex b/sail_latex_mips/overloadWWWzupdate_caplgb9408b2c97a868b24bf4fafd9a974c0d.tex new file mode 100644 index 00000000..af53d7df --- /dev/null +++ b/sail_latex_mips/overloadWWWzupdate_caplgb9408b2c97a868b24bf4fafd9a974c0d.tex @@ -0,0 +1 @@ +overload update_CapLG = {_update_TLBEntryLoReg_CapLG} \ No newline at end of file diff --git a/sail_latex_mips/overloadWWzsign_extendd299e34344c466213b3253f0d877453d.tex b/sail_latex_mips/overloadWWzsign_extendd299e34344c466213b3253f0d877453d.tex new file mode 100644 index 00000000..2f1c2981 --- /dev/null +++ b/sail_latex_mips/overloadWWzsign_extendd299e34344c466213b3253f0d877453d.tex @@ -0,0 +1 @@ +overload sign_extend = {mips_sign_extend} diff --git a/sail_latex_mips/overloadWzlength469e3f917f7b24f4691faf3caf842eba.tex b/sail_latex_mips/overloadWzlength469e3f917f7b24f4691faf3caf842eba.tex new file mode 100644 index 00000000..bff07a35 --- /dev/null +++ b/sail_latex_mips/overloadWzlength469e3f917f7b24f4691faf3caf842eba.tex @@ -0,0 +1 @@ +overload length = {bitvector_length, vector_length} diff --git a/sail_latex_mips/overloadXXXXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_mips/overloadXXXXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..b14554ac --- /dev/null +++ b/sail_latex_mips/overloadXXXXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_CapCauseReg_bits, _set_CapCauseReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadXXXXXXz_mod_d0f37cbe87852175a6e90f15df1e64f6bf.tex b/sail_latex_mips/overloadXXXXXXz_mod_d0f37cbe87852175a6e90f15df1e64f6bf.tex new file mode 100644 index 00000000..0e860884 --- /dev/null +++ b/sail_latex_mips/overloadXXXXXXz_mod_d0f37cbe87852175a6e90f15df1e64f6bf.tex @@ -0,0 +1 @@ +overload _mod_d0 = {_get_TLBEntry_d0, _set_TLBEntry_d0} \ No newline at end of file diff --git a/sail_latex_mips/overloadXXXXXz_mod_valid8d7cbb6b22e8da4e1c2a35c063b16cbe.tex b/sail_latex_mips/overloadXXXXXz_mod_valid8d7cbb6b22e8da4e1c2a35c063b16cbe.tex new file mode 100644 index 00000000..21baa26c --- /dev/null +++ b/sail_latex_mips/overloadXXXXXz_mod_valid8d7cbb6b22e8da4e1c2a35c063b16cbe.tex @@ -0,0 +1 @@ +overload _mod_valid = {_get_TLBEntry_valid, _set_TLBEntry_valid} \ No newline at end of file diff --git a/sail_latex_mips/overloadXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_mips/overloadXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..8b2aac3e --- /dev/null +++ b/sail_latex_mips/overloadXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_ContextReg_bits, _set_ContextReg_bits} \ No newline at end of file diff --git a/sail_latex_mips/overloadXXXz_mod_caplgde160c8f451c418f4014f00afcc95766.tex b/sail_latex_mips/overloadXXXz_mod_caplgde160c8f451c418f4014f00afcc95766.tex new file mode 100644 index 00000000..0348ed9e --- /dev/null +++ b/sail_latex_mips/overloadXXXz_mod_caplgde160c8f451c418f4014f00afcc95766.tex @@ -0,0 +1 @@ +overload _mod_CapLG = {_get_TLBEntryLoReg_CapLG, _set_TLBEntryLoReg_CapLG} \ No newline at end of file diff --git a/sail_latex_mips/overloadXXzzzero_extendd7d8b08ed1667724fd3dfa843cf0ae78.tex b/sail_latex_mips/overloadXXzzzero_extendd7d8b08ed1667724fd3dfa843cf0ae78.tex new file mode 100644 index 00000000..813e897a --- /dev/null +++ b/sail_latex_mips/overloadXXzzzero_extendd7d8b08ed1667724fd3dfa843cf0ae78.tex @@ -0,0 +1 @@ +overload zero_extend = {mips_zero_extend} diff --git a/sail_latex_mips/overloadXzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex b/sail_latex_mips/overloadXzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex new file mode 100644 index 00000000..eab71d1d --- /dev/null +++ b/sail_latex_mips/overloadXzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex @@ -0,0 +1 @@ +overload operator ^ = {sail_mask} diff --git a/sail_latex_mips/overloadYYYYYYYzupdate_exccode286b5e0163b588d6fbc04a06efd36aa1.tex b/sail_latex_mips/overloadYYYYYYYzupdate_exccode286b5e0163b588d6fbc04a06efd36aa1.tex new file mode 100644 index 00000000..38736fe7 --- /dev/null +++ b/sail_latex_mips/overloadYYYYYYYzupdate_exccode286b5e0163b588d6fbc04a06efd36aa1.tex @@ -0,0 +1 @@ +overload update_ExcCode = {_update_CapCauseReg_ExcCode} \ No newline at end of file diff --git a/sail_latex_mips/overloadYYYYYYzupdate_v083f35e3b61c4e09f8255bb126113bf81.tex b/sail_latex_mips/overloadYYYYYYzupdate_v083f35e3b61c4e09f8255bb126113bf81.tex new file mode 100644 index 00000000..0405f0c0 --- /dev/null +++ b/sail_latex_mips/overloadYYYYYYzupdate_v083f35e3b61c4e09f8255bb126113bf81.tex @@ -0,0 +1 @@ +overload update_v0 = {_update_TLBEntry_v0} \ No newline at end of file diff --git a/sail_latex_mips/overloadYYYYYzupdate_caplg14947cfbf12f2f7c0f3ac633b9a022476.tex b/sail_latex_mips/overloadYYYYYzupdate_caplg14947cfbf12f2f7c0f3ac633b9a022476.tex new file mode 100644 index 00000000..2f72b3f4 --- /dev/null +++ b/sail_latex_mips/overloadYYYYYzupdate_caplg14947cfbf12f2f7c0f3ac633b9a022476.tex @@ -0,0 +1 @@ +overload update_caplg1 = {_update_TLBEntry_caplg1} \ No newline at end of file diff --git a/sail_latex_mips/overloadYYYYzupdate_ptebase2ea26e695d7955da0671b82b96885404.tex b/sail_latex_mips/overloadYYYYzupdate_ptebase2ea26e695d7955da0671b82b96885404.tex new file mode 100644 index 00000000..8826eee7 --- /dev/null +++ b/sail_latex_mips/overloadYYYYzupdate_ptebase2ea26e695d7955da0671b82b96885404.tex @@ -0,0 +1 @@ +overload update_PTEBase = {_update_ContextReg_PTEBase} \ No newline at end of file diff --git a/sail_latex_mips/overloadYYYzupdate_pfn8465b5dd902528d594c32acf79e47d31.tex b/sail_latex_mips/overloadYYYzupdate_pfn8465b5dd902528d594c32acf79e47d31.tex new file mode 100644 index 00000000..fa32c59b --- /dev/null +++ b/sail_latex_mips/overloadYYYzupdate_pfn8465b5dd902528d594c32acf79e47d31.tex @@ -0,0 +1 @@ +overload update_PFN = {_update_TLBEntryLoReg_PFN} \ No newline at end of file diff --git a/sail_latex_mips/overloadYYzzzerosc530711942e216cef3921733c1c5d101.tex b/sail_latex_mips/overloadYYzzzerosc530711942e216cef3921733c1c5d101.tex new file mode 100644 index 00000000..5129b7fd --- /dev/null +++ b/sail_latex_mips/overloadYYzzzerosc530711942e216cef3921733c1c5d101.tex @@ -0,0 +1 @@ +overload zeros = {zeros_implicit, sail_zeros} diff --git a/sail_latex_mips/overloadYzappend88575169e0ec1639b6ae3851df999710.tex b/sail_latex_mips/overloadYzappend88575169e0ec1639b6ae3851df999710.tex new file mode 100644 index 00000000..4897992d --- /dev/null +++ b/sail_latex_mips/overloadYzappend88575169e0ec1639b6ae3851df999710.tex @@ -0,0 +1 @@ +overload append = {bitvector_concat} diff --git a/sail_latex_mips/overloadZZZZZZZz_mod_exccode24886ea7a19912378ba2030097458ff1.tex b/sail_latex_mips/overloadZZZZZZZz_mod_exccode24886ea7a19912378ba2030097458ff1.tex new file mode 100644 index 00000000..baa16ec2 --- /dev/null +++ b/sail_latex_mips/overloadZZZZZZZz_mod_exccode24886ea7a19912378ba2030097458ff1.tex @@ -0,0 +1 @@ +overload _mod_ExcCode = {_get_CapCauseReg_ExcCode, _set_CapCauseReg_ExcCode} \ No newline at end of file diff --git a/sail_latex_mips/overloadZZZZZZz_mod_v022aed16ab1f8b5385c37e6eef8f1094a.tex b/sail_latex_mips/overloadZZZZZZz_mod_v022aed16ab1f8b5385c37e6eef8f1094a.tex new file mode 100644 index 00000000..3e05b3f3 --- /dev/null +++ b/sail_latex_mips/overloadZZZZZZz_mod_v022aed16ab1f8b5385c37e6eef8f1094a.tex @@ -0,0 +1 @@ +overload _mod_v0 = {_get_TLBEntry_v0, _set_TLBEntry_v0} \ No newline at end of file diff --git a/sail_latex_mips/overloadZZZZZz_mod_caplg1d0010882f7db95a2821cae370f0dbe42.tex b/sail_latex_mips/overloadZZZZZz_mod_caplg1d0010882f7db95a2821cae370f0dbe42.tex new file mode 100644 index 00000000..c236e292 --- /dev/null +++ b/sail_latex_mips/overloadZZZZZz_mod_caplg1d0010882f7db95a2821cae370f0dbe42.tex @@ -0,0 +1 @@ +overload _mod_caplg1 = {_get_TLBEntry_caplg1, _set_TLBEntry_caplg1} \ No newline at end of file diff --git a/sail_latex_mips/overloadZZZZz_mod_ptebase2f0d0b71640e150cfba79584bdbb2c74.tex b/sail_latex_mips/overloadZZZZz_mod_ptebase2f0d0b71640e150cfba79584bdbb2c74.tex new file mode 100644 index 00000000..890eb57c --- /dev/null +++ b/sail_latex_mips/overloadZZZZz_mod_ptebase2f0d0b71640e150cfba79584bdbb2c74.tex @@ -0,0 +1 @@ +overload _mod_PTEBase = {_get_ContextReg_PTEBase, _set_ContextReg_PTEBase} \ No newline at end of file diff --git a/sail_latex_mips/overloadZZZz_mod_pfnd0a43f9c31fe271df6057856de04c9d4.tex b/sail_latex_mips/overloadZZZz_mod_pfnd0a43f9c31fe271df6057856de04c9d4.tex new file mode 100644 index 00000000..bba40f6d --- /dev/null +++ b/sail_latex_mips/overloadZZZz_mod_pfnd0a43f9c31fe271df6057856de04c9d4.tex @@ -0,0 +1 @@ +overload _mod_PFN = {_get_TLBEntryLoReg_PFN, _set_TLBEntryLoReg_PFN} \ No newline at end of file diff --git a/sail_latex_mips/overloadZZzones26f94136f5db8afd4e9df1e512f7fdc5.tex b/sail_latex_mips/overloadZZzones26f94136f5db8afd4e9df1e512f7fdc5.tex new file mode 100644 index 00000000..20cf601f --- /dev/null +++ b/sail_latex_mips/overloadZZzones26f94136f5db8afd4e9df1e512f7fdc5.tex @@ -0,0 +1 @@ +overload ones = {ones_implicit, sail_ones} diff --git a/sail_latex_mips/overloadZzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex b/sail_latex_mips/overloadZzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex new file mode 100644 index 00000000..07e283d8 --- /dev/null +++ b/sail_latex_mips/overloadZzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex @@ -0,0 +1 @@ +overload vector_access = {bitvector_access, plain_vector_access} diff --git a/sail_latex_mips/typezaccesslevel34c3ad2092ac418806acf43082692dd8.tex b/sail_latex_mips/typezaccesslevel34c3ad2092ac418806acf43082692dd8.tex new file mode 100644 index 00000000..557f2582 --- /dev/null +++ b/sail_latex_mips/typezaccesslevel34c3ad2092ac418806acf43082692dd8.tex @@ -0,0 +1 @@ +enum AccessLevel = {User, Supervisor, Kernel} diff --git a/sail_latex_mips/typezast6bb070d12e82e4887160cdfd016230c8.tex b/sail_latex_mips/typezast6bb070d12e82e4887160cdfd016230c8.tex new file mode 100644 index 00000000..bcfcbb35 --- /dev/null +++ b/sail_latex_mips/typezast6bb070d12e82e4887160cdfd016230c8.tex @@ -0,0 +1 @@ +scattered union ast diff --git a/sail_latex_mips/typezbitsa4b31f9b3dc11c921007b665e0d0fce6.tex b/sail_latex_mips/typezbitsa4b31f9b3dc11c921007b665e0d0fce6.tex new file mode 100644 index 00000000..32124d36 --- /dev/null +++ b/sail_latex_mips/typezbitsa4b31f9b3dc11c921007b665e0d0fce6.tex @@ -0,0 +1 @@ +type #\hyperref[sailMIPSzbits]{bits}# ('n : Int) = #\hyperref[sailMIPSzbitvector]{bitvector}#('n, dec) diff --git a/sail_latex_mips/typezcapability5646515621fe4c3bb7fe8874d1909f0e.tex b/sail_latex_mips/typezcapability5646515621fe4c3bb7fe8874d1909f0e.tex new file mode 100644 index 00000000..1f818156 --- /dev/null +++ b/sail_latex_mips/typezcapability5646515621fe4c3bb7fe8874d1909f0e.tex @@ -0,0 +1,24 @@ +struct Capability = { + tag : bool , + uperms : #\hyperref[sailMIPSzbits]{bits}#(4) , + permit_set_CID : bool , + access_system_regs : bool , + permit_unseal : bool , + permit_ccall : bool , + permit_seal : bool , + permit_store_local_cap : bool , + permit_store_cap : bool , + permit_load_cap : bool , + permit_store : bool , + permit_load : bool , + permit_execute : bool , + global : bool , + reserved : #\hyperref[sailMIPSzbits]{bits}#(3) , + internal_e : bool , + E : #\hyperref[sailMIPSzbits]{bits}#(6) , + sealed : bool , + B : #\hyperref[sailMIPSzbits]{bits}#(14), + T : #\hyperref[sailMIPSzbits]{bits}#(14), + otype : #\hyperref[sailMIPSzbits]{bits}#(18), + address : #\hyperref[sailMIPSzbits]{bits}#(64) +} diff --git a/sail_latex_mips/typezcapbits32830b87cefa69a0cdb78ef00d25b781.tex b/sail_latex_mips/typezcapbits32830b87cefa69a0cdb78ef00d25b781.tex new file mode 100644 index 00000000..e48b2f24 --- /dev/null +++ b/sail_latex_mips/typezcapbits32830b87cefa69a0cdb78ef00d25b781.tex @@ -0,0 +1 @@ +type CapBits = #\hyperref[sailMIPSzbits]{bits}#(128) diff --git a/sail_latex_mips/typezcapcausereg4dd1a4671e3fabc92350ed31d9f5303e.tex b/sail_latex_mips/typezcapcausereg4dd1a4671e3fabc92350ed31d9f5303e.tex new file mode 100644 index 00000000..5195f8f8 --- /dev/null +++ b/sail_latex_mips/typezcapcausereg4dd1a4671e3fabc92350ed31d9f5303e.tex @@ -0,0 +1 @@ +struct CapCauseReg = {CapCauseReg_chunk_0 : bitvector(16, dec)} diff --git a/sail_latex_mips/typezcapexbc9797bf8ddff0359677ca6657edba93.tex b/sail_latex_mips/typezcapexbc9797bf8ddff0359677ca6657edba93.tex new file mode 100644 index 00000000..bd3230cf --- /dev/null +++ b/sail_latex_mips/typezcapexbc9797bf8ddff0359677ca6657edba93.tex @@ -0,0 +1,27 @@ +enum CapEx = { + CapEx_None, + CapEx_LengthViolation, + CapEx_TagViolation, + CapEx_SealViolation, + CapEx_TypeViolation, + CapEx_CallTrap, + CapEx_ReturnTrap, + CapEx_TSSUnderFlow, + CapEx_UserDefViolation, + CapEx_TLBNoStoreCap, + CapEx_InexactBounds, + CapEx_GlobalViolation, + CapEx_PermitExecuteViolation, + CapEx_PermitLoadViolation, + CapEx_PermitStoreViolation, + CapEx_PermitLoadCapViolation, + CapEx_PermitStoreCapViolation, + CapEx_PermitStoreLocalCapViolation, + CapEx_PermitSealViolation, + CapEx_AccessSystemRegsViolation, + CapEx_PermitCCallViolation, + CapEx_AccessCCallIDCViolation, + CapEx_PermitUnsealViolation, + CapEx_PermitSetCIDViolation, + CapEx_TLBLoadCap +} diff --git a/sail_latex_mips/typezcaphwrenc2bb0321c08e3f230e2bc09240b4b0441.tex b/sail_latex_mips/typezcaphwrenc2bb0321c08e3f230e2bc09240b4b0441.tex new file mode 100644 index 00000000..af41df87 --- /dev/null +++ b/sail_latex_mips/typezcaphwrenc2bb0321c08e3f230e2bc09240b4b0441.tex @@ -0,0 +1 @@ +type CapHwrEnc = #\hyperref[sailMIPSzbits]{bits}#(5) /* a register number */ diff --git a/sail_latex_mips/typezcaplenf6618af706b03f95ca9741cffae7687d.tex b/sail_latex_mips/typezcaplenf6618af706b03f95ca9741cffae7687d.tex new file mode 100644 index 00000000..812f45ff --- /dev/null +++ b/sail_latex_mips/typezcaplenf6618af706b03f95ca9741cffae7687d.tex @@ -0,0 +1 @@ +type CapLen = range(0, 2 ^ 65) diff --git a/sail_latex_mips/typezcapregenc81083d19fcdcf94728bdf9c6360cc203.tex b/sail_latex_mips/typezcapregenc81083d19fcdcf94728bdf9c6360cc203.tex new file mode 100644 index 00000000..69c93490 --- /dev/null +++ b/sail_latex_mips/typezcapregenc81083d19fcdcf94728bdf9c6360cc203.tex @@ -0,0 +1 @@ +type CapRegEnc = #\hyperref[sailMIPSzbits]{bits}#(5) /* a register number */ diff --git a/sail_latex_mips/typezcapregorddcenc4d797db90f106a69ff753815af67f927.tex b/sail_latex_mips/typezcapregorddcenc4d797db90f106a69ff753815af67f927.tex new file mode 100644 index 00000000..597a918f --- /dev/null +++ b/sail_latex_mips/typezcapregorddcenc4d797db90f106a69ff753815af67f927.tex @@ -0,0 +1 @@ +type CapRegOrDDCEnc = #\hyperref[sailMIPSzbits]{bits}#(5) /* a register number */ diff --git a/sail_latex_mips/typezcauseregda69bedc009933948dd9b8b2c8a67377.tex b/sail_latex_mips/typezcauseregda69bedc009933948dd9b8b2c8a67377.tex new file mode 100644 index 00000000..d5b4bc5d --- /dev/null +++ b/sail_latex_mips/typezcauseregda69bedc009933948dd9b8b2c8a67377.tex @@ -0,0 +1 @@ +struct CauseReg = {CauseReg_chunk_0 : bitvector(32, dec)} diff --git a/sail_latex_mips/typezcflags0d98257ead736171e7ed77965597f4f0.tex b/sail_latex_mips/typezcflags0d98257ead736171e7ed77965597f4f0.tex new file mode 100644 index 00000000..f6ce8961 --- /dev/null +++ b/sail_latex_mips/typezcflags0d98257ead736171e7ed77965597f4f0.tex @@ -0,0 +1 @@ +type CFlags = #\hyperref[sailMIPSzbits]{bits}#(num_flags_t) diff --git a/sail_latex_mips/typezclearregsete5eab3e282a2a338ddb8311b5edbb561.tex b/sail_latex_mips/typezclearregsete5eab3e282a2a338ddb8311b5edbb561.tex new file mode 100644 index 00000000..c04ea7d4 --- /dev/null +++ b/sail_latex_mips/typezclearregsete5eab3e282a2a338ddb8311b5edbb561.tex @@ -0,0 +1,6 @@ +enum ClearRegSet = { +GPLo, +GPHi, +CLo, +CHi +} diff --git a/sail_latex_mips/typezcomparisoncd0f719b5c6f4fc29b93a9e3721bf4a5.tex b/sail_latex_mips/typezcomparisoncd0f719b5c6f4fc29b93a9e3721bf4a5.tex new file mode 100644 index 00000000..5ada1deb --- /dev/null +++ b/sail_latex_mips/typezcomparisoncd0f719b5c6f4fc29b93a9e3721bf4a5.tex @@ -0,0 +1,10 @@ +enum Comparison = { + EQ, /* equal */ + NE, /* not equal */ + GE, /* signed greater than or equal */ + GEU,/* unsigned greater than or equal */ + GT, /* signed strictly greater than */ + LE, /* signed less than or equal */ + LT, /* signed strictly less than */ + LTU /* unsigned less than or qual */ +} diff --git a/sail_latex_mips/typezcontextreg4859b14bb9c8e2fac453ab6f118b53e5.tex b/sail_latex_mips/typezcontextreg4859b14bb9c8e2fac453ab6f118b53e5.tex new file mode 100644 index 00000000..0ecb5ade --- /dev/null +++ b/sail_latex_mips/typezcontextreg4859b14bb9c8e2fac453ab6f118b53e5.tex @@ -0,0 +1 @@ +struct ContextReg = {ContextReg_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_mips/typezcptrcmpopb3b1dde403387930c5431415f0c993e5.tex b/sail_latex_mips/typezcptrcmpopb3b1dde403387930c5431415f0c993e5.tex new file mode 100644 index 00000000..cb0a73ae --- /dev/null +++ b/sail_latex_mips/typezcptrcmpopb3b1dde403387930c5431415f0c993e5.tex @@ -0,0 +1,10 @@ +enum CPtrCmpOp = { + CEQ, + CNE, + CLT, + CLE, + CLTU, + CLEU, + CEXEQ, + CNEXEQ +} diff --git a/sail_latex_mips/typezdecode_failure1d4a2f8a2ba670570ead3264488ec7db.tex b/sail_latex_mips/typezdecode_failure1d4a2f8a2ba670570ead3264488ec7db.tex new file mode 100644 index 00000000..46a1330b --- /dev/null +++ b/sail_latex_mips/typezdecode_failure1d4a2f8a2ba670570ead3264488ec7db.tex @@ -0,0 +1,6 @@ +enum decode_failure = { + no_matching_pattern, + unsupported_instruction, + illegal_instruction, + internal_error +} diff --git a/sail_latex_mips/typezexception6ac3a0452a7a8420f2be999d05ad1183.tex b/sail_latex_mips/typezexception6ac3a0452a7a8420f2be999d05ad1183.tex new file mode 100644 index 00000000..800328ec --- /dev/null +++ b/sail_latex_mips/typezexception6ac3a0452a7a8420f2be999d05ad1183.tex @@ -0,0 +1,5 @@ +enum Exception = +{ + Interrupt, TLBMod, TLBL, TLBS, AdEL, AdES, Sys, Bp, ResI, CpU, Ov, Tr, C2E, C2Trap, + XTLBRefillL, XTLBRefillS, XTLBInvL, XTLBInvS, MCheck +} diff --git a/sail_latex_mips/typezexceptionfaa4db8fab65c538edad4222e766a71a.tex b/sail_latex_mips/typezexceptionfaa4db8fab65c538edad4222e766a71a.tex new file mode 100644 index 00000000..9c462dce --- /dev/null +++ b/sail_latex_mips/typezexceptionfaa4db8fab65c538edad4222e766a71a.tex @@ -0,0 +1,7 @@ +union exception = { + ISAException : unit, + Error_not_implemented : string, + Error_misaligned_access : unit, + Error_EBREAK : unit, + Error_internal_error : unit +} diff --git a/sail_latex_mips/typezimm16dc4af7d5aca495b5bf0191384a060883.tex b/sail_latex_mips/typezimm16dc4af7d5aca495b5bf0191384a060883.tex new file mode 100644 index 00000000..150d14a5 --- /dev/null +++ b/sail_latex_mips/typezimm16dc4af7d5aca495b5bf0191384a060883.tex @@ -0,0 +1 @@ +type imm16 = #\hyperref[sailMIPSzbits]{bits}#(16) /* 16-bit immediate */ diff --git a/sail_latex_mips/typezintregencbffd4c4bbb18a759cfd88ad299ff3a72.tex b/sail_latex_mips/typezintregencbffd4c4bbb18a759cfd88ad299ff3a72.tex new file mode 100644 index 00000000..7ba893e5 --- /dev/null +++ b/sail_latex_mips/typezintregencbffd4c4bbb18a759cfd88ad299ff3a72.tex @@ -0,0 +1 @@ +type IntRegEnc = #\hyperref[sailMIPSzbits]{bits}#(5) /* a register number */ diff --git a/sail_latex_mips/typezmemaccesscaprestriction340c8f66dcf0e8588b00a8db8a47687d.tex b/sail_latex_mips/typezmemaccesscaprestriction340c8f66dcf0e8588b00a8db8a47687d.tex new file mode 100644 index 00000000..aabd1928 --- /dev/null +++ b/sail_latex_mips/typezmemaccesscaprestriction340c8f66dcf0e8588b00a8db8a47687d.tex @@ -0,0 +1 @@ +enum MemAccessCapRestriction = { Unrestricted, Trap, Clear } diff --git a/sail_latex_mips/typezmemaccesstype6fcf71ced82759af01458f3bc64be72a.tex b/sail_latex_mips/typezmemaccesstype6fcf71ced82759af01458f3bc64be72a.tex new file mode 100644 index 00000000..436b40bc --- /dev/null +++ b/sail_latex_mips/typezmemaccesstype6fcf71ced82759af01458f3bc64be72a.tex @@ -0,0 +1 @@ +enum MemAccessType = {Instruction, LoadData, StoreData} diff --git a/sail_latex_mips/typeznum_flags_t473b430862704b86668aeb0b48744535.tex b/sail_latex_mips/typeznum_flags_t473b430862704b86668aeb0b48744535.tex new file mode 100644 index 00000000..364cfb1e --- /dev/null +++ b/sail_latex_mips/typeznum_flags_t473b430862704b86668aeb0b48744535.tex @@ -0,0 +1 @@ +type num_flags_t : Int = 1 diff --git a/sail_latex_mips/typezoptiona3271ef8b6a63c78e6db36dac0ee6547.tex b/sail_latex_mips/typezoptiona3271ef8b6a63c78e6db36dac0ee6547.tex new file mode 100644 index 00000000..917ecbb5 --- /dev/null +++ b/sail_latex_mips/typezoptiona3271ef8b6a63c78e6db36dac0ee6547.tex @@ -0,0 +1,4 @@ +union #\hyperref[sailMIPSzoption]{option}#('a: Type) = { + Some : 'a, + None : unit +} diff --git a/sail_latex_mips/typezregno1c2cd9b00ff5d991528ec5d711c3ace5.tex b/sail_latex_mips/typezregno1c2cd9b00ff5d991528ec5d711c3ace5.tex new file mode 100644 index 00000000..9a0ceada --- /dev/null +++ b/sail_latex_mips/typezregno1c2cd9b00ff5d991528ec5d711c3ace5.tex @@ -0,0 +1 @@ +type regno = #\hyperref[sailMIPSzbits]{bits}#(5) /* a register number */ diff --git a/sail_latex_mips/typezstatusreg08ee55655052654d784e0e380989b896.tex b/sail_latex_mips/typezstatusreg08ee55655052654d784e0e380989b896.tex new file mode 100644 index 00000000..aea04995 --- /dev/null +++ b/sail_latex_mips/typezstatusreg08ee55655052654d784e0e380989b896.tex @@ -0,0 +1 @@ +struct StatusReg = {StatusReg_chunk_0 : bitvector(32, dec)} diff --git a/sail_latex_mips/typeztlbentrydb6733ff232beb81c7ffa4ec6b366366.tex b/sail_latex_mips/typeztlbentrydb6733ff232beb81c7ffa4ec6b366366.tex new file mode 100644 index 00000000..11463c96 --- /dev/null +++ b/sail_latex_mips/typeztlbentrydb6733ff232beb81c7ffa4ec6b366366.tex @@ -0,0 +1 @@ +struct TLBEntry = {TLBEntry_chunk_1 : bitvector(55, dec), TLBEntry_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_mips/typeztlbentryhireg6a2dd5c7437ed3c296ee69b189e6879f.tex b/sail_latex_mips/typeztlbentryhireg6a2dd5c7437ed3c296ee69b189e6879f.tex new file mode 100644 index 00000000..a2f99b99 --- /dev/null +++ b/sail_latex_mips/typeztlbentryhireg6a2dd5c7437ed3c296ee69b189e6879f.tex @@ -0,0 +1 @@ +struct TLBEntryHiReg = {TLBEntryHiReg_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_mips/typeztlbentryloregdfc9845e9d6ede4af1453459f39832af.tex b/sail_latex_mips/typeztlbentryloregdfc9845e9d6ede4af1453459f39832af.tex new file mode 100644 index 00000000..f37e7d21 --- /dev/null +++ b/sail_latex_mips/typeztlbentryloregdfc9845e9d6ede4af1453459f39832af.tex @@ -0,0 +1 @@ +struct TLBEntryLoReg = {TLBEntryLoReg_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_mips/typeztlbindext3787f4de8ebd404a524c1c53e1adc1c9.tex b/sail_latex_mips/typeztlbindext3787f4de8ebd404a524c1c53e1adc1c9.tex new file mode 100644 index 00000000..47e63c83 --- /dev/null +++ b/sail_latex_mips/typeztlbindext3787f4de8ebd404a524c1c53e1adc1c9.tex @@ -0,0 +1 @@ +type TLBIndexT = (#\hyperref[sailMIPSzbits]{bits}#(6)) diff --git a/sail_latex_mips/typezuint6439284932ed72321603dafa0ae33d84aa.tex b/sail_latex_mips/typezuint6439284932ed72321603dafa0ae33d84aa.tex new file mode 100644 index 00000000..a0d52c8f --- /dev/null +++ b/sail_latex_mips/typezuint6439284932ed72321603dafa0ae33d84aa.tex @@ -0,0 +1 @@ +type uint64 = range(0, (2 ^ 64) - 1) diff --git a/sail_latex_mips/typezwordtype6cf92a33f38f7f38030a409847a13ce4.tex b/sail_latex_mips/typezwordtype6cf92a33f38f7f38030a409847a13ce4.tex new file mode 100644 index 00000000..632efe95 --- /dev/null +++ b/sail_latex_mips/typezwordtype6cf92a33f38f7f38030a409847a13ce4.tex @@ -0,0 +1 @@ +enum WordType = { B, H, W, D} diff --git a/sail_latex_mips/typezwordtypeunalignedeae3a0458f9fb4fc24aa62dc6e172d35.tex b/sail_latex_mips/typezwordtypeunalignedeae3a0458f9fb4fc24aa62dc6e172d35.tex new file mode 100644 index 00000000..3724733e --- /dev/null +++ b/sail_latex_mips/typezwordtypeunalignedeae3a0458f9fb4fc24aa62dc6e172d35.tex @@ -0,0 +1 @@ +enum WordTypeUnaligned = { WL, WR, DL, DR } diff --git a/sail_latex_mips/typezxcontextregbafb1e34c421e40a1ce1b569d5083916.tex b/sail_latex_mips/typezxcontextregbafb1e34c421e40a1ce1b569d5083916.tex new file mode 100644 index 00000000..5f161bed --- /dev/null +++ b/sail_latex_mips/typezxcontextregbafb1e34c421e40a1ce1b569d5083916.tex @@ -0,0 +1 @@ +struct XContextReg = {XContextReg_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_mips/valz__bitfield_deref5ed587b7c1b91cf82e42f865304262ca.tex b/sail_latex_mips/valz__bitfield_deref5ed587b7c1b91cf82e42f865304262ca.tex new file mode 100644 index 00000000..3e8b4d9b --- /dev/null +++ b/sail_latex_mips/valz__bitfield_deref5ed587b7c1b91cf82e42f865304262ca.tex @@ -0,0 +1 @@ +__bitfield_deref : forall ('a : Type). register('a) -> 'a \ No newline at end of file diff --git a/sail_latex_mips/valz__deref1dbc379e24bd1b182e1db755dea8c453.tex b/sail_latex_mips/valz__deref1dbc379e24bd1b182e1db755dea8c453.tex new file mode 100644 index 00000000..66b83401 --- /dev/null +++ b/sail_latex_mips/valz__deref1dbc379e24bd1b182e1db755dea8c453.tex @@ -0,0 +1 @@ +__deref : forall ('a : Type). register('a) -> 'a \ No newline at end of file diff --git a/sail_latex_mips/valz__ided888b8991a27578d5dd72f84db80bce.tex b/sail_latex_mips/valz__ided888b8991a27578d5dd72f84db80bce.tex new file mode 100644 index 00000000..323b76d9 --- /dev/null +++ b/sail_latex_mips/valz__ided888b8991a27578d5dd72f84db80bce.tex @@ -0,0 +1 @@ +__id : forall ('n : Int). int('n) -> int('n) \ No newline at end of file diff --git a/sail_latex_mips/valz__mips_read6caa8fcafb5a40e544d3165028b605fb.tex b/sail_latex_mips/valz__mips_read6caa8fcafb5a40e544d3165028b605fb.tex new file mode 100644 index 00000000..c617ba1c --- /dev/null +++ b/sail_latex_mips/valz__mips_read6caa8fcafb5a40e544d3165028b605fb.tex @@ -0,0 +1 @@ +__MIPS_read : forall ('n : Int), 'n >= 0. (bits(64), int('n)) -> bits(8 * 'n) \ No newline at end of file diff --git a/sail_latex_mips/valz__mips_writed13fe4a15e9bfd2a9e702a585b5a7e1c.tex b/sail_latex_mips/valz__mips_writed13fe4a15e9bfd2a9e702a585b5a7e1c.tex new file mode 100644 index 00000000..82abee31 --- /dev/null +++ b/sail_latex_mips/valz__mips_writed13fe4a15e9bfd2a9e702a585b5a7e1c.tex @@ -0,0 +1 @@ +__MIPS_write : forall ('n : Int). (bits(64), int('n), bits(8 * 'n)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz__readram468758162486e62876c2678a7e769399.tex b/sail_latex_mips/valz__readram468758162486e62876c2678a7e769399.tex new file mode 100644 index 00000000..3a1b4106 --- /dev/null +++ b/sail_latex_mips/valz__readram468758162486e62876c2678a7e769399.tex @@ -0,0 +1 @@ +__ReadRAM : forall ('n 'm : Int), 'n >= 0. (int('m), int('n), bits('m), bits('m)) -> bits(8 * 'n) \ No newline at end of file diff --git a/sail_latex_mips/valz__writeram67df92b8173868b4341c66bb37bdc8da.tex b/sail_latex_mips/valz__writeram67df92b8173868b4341c66bb37bdc8da.tex new file mode 100644 index 00000000..ec0eaadf --- /dev/null +++ b/sail_latex_mips/valz__writeram67df92b8173868b4341c66bb37bdc8da.tex @@ -0,0 +1 @@ +__WriteRAM : forall ('n 'm : Int). (int('m), int('n), bits('m), bits('m), bits(8 * 'n)) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valz_get_capcausereg_bits52bfda42e15401e97a3be8662ec10017.tex b/sail_latex_mips/valz_get_capcausereg_bits52bfda42e15401e97a3be8662ec10017.tex new file mode 100644 index 00000000..bed56746 --- /dev/null +++ b/sail_latex_mips/valz_get_capcausereg_bits52bfda42e15401e97a3be8662ec10017.tex @@ -0,0 +1 @@ +_get_CapCauseReg_bits : CapCauseReg -> bitvector(16, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_capcausereg_exccode52aba9ba1e3306797490b273879487fc.tex b/sail_latex_mips/valz_get_capcausereg_exccode52aba9ba1e3306797490b273879487fc.tex new file mode 100644 index 00000000..4343911a --- /dev/null +++ b/sail_latex_mips/valz_get_capcausereg_exccode52aba9ba1e3306797490b273879487fc.tex @@ -0,0 +1 @@ +_get_CapCauseReg_ExcCode : CapCauseReg -> bitvector(8, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_capcausereg_regnumb581772dd095764cdd19b6f0e8c03d06.tex b/sail_latex_mips/valz_get_capcausereg_regnumb581772dd095764cdd19b6f0e8c03d06.tex new file mode 100644 index 00000000..cadecc81 --- /dev/null +++ b/sail_latex_mips/valz_get_capcausereg_regnumb581772dd095764cdd19b6f0e8c03d06.tex @@ -0,0 +1 @@ +_get_CapCauseReg_RegNum : CapCauseReg -> bitvector(8, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_causereg_bd96afa963ea8fd0967157eb8bd72a1b1b.tex b/sail_latex_mips/valz_get_causereg_bd96afa963ea8fd0967157eb8bd72a1b1b.tex new file mode 100644 index 00000000..b6788d3e --- /dev/null +++ b/sail_latex_mips/valz_get_causereg_bd96afa963ea8fd0967157eb8bd72a1b1b.tex @@ -0,0 +1 @@ +_get_CauseReg_BD : CauseReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_causereg_bits8438dd7e3e82e5a62db2fbe5d4c93611.tex b/sail_latex_mips/valz_get_causereg_bits8438dd7e3e82e5a62db2fbe5d4c93611.tex new file mode 100644 index 00000000..4c3bdb2e --- /dev/null +++ b/sail_latex_mips/valz_get_causereg_bits8438dd7e3e82e5a62db2fbe5d4c93611.tex @@ -0,0 +1 @@ +_get_CauseReg_bits : CauseReg -> bitvector(32, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_causereg_cec50f9f4ac0a1b657a7733fa87526be2d.tex b/sail_latex_mips/valz_get_causereg_cec50f9f4ac0a1b657a7733fa87526be2d.tex new file mode 100644 index 00000000..fbc5be99 --- /dev/null +++ b/sail_latex_mips/valz_get_causereg_cec50f9f4ac0a1b657a7733fa87526be2d.tex @@ -0,0 +1 @@ +_get_CauseReg_CE : CauseReg -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_causereg_exccode8a67289fbe422c3b2420033795ebefa2.tex b/sail_latex_mips/valz_get_causereg_exccode8a67289fbe422c3b2420033795ebefa2.tex new file mode 100644 index 00000000..30698fc5 --- /dev/null +++ b/sail_latex_mips/valz_get_causereg_exccode8a67289fbe422c3b2420033795ebefa2.tex @@ -0,0 +1 @@ +_get_CauseReg_ExcCode : CauseReg -> bitvector(5, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_causereg_ip959fa0662dd3554fca2b54c9afdd9ed2.tex b/sail_latex_mips/valz_get_causereg_ip959fa0662dd3554fca2b54c9afdd9ed2.tex new file mode 100644 index 00000000..6ff9e028 --- /dev/null +++ b/sail_latex_mips/valz_get_causereg_ip959fa0662dd3554fca2b54c9afdd9ed2.tex @@ -0,0 +1 @@ +_get_CauseReg_IP : CauseReg -> bitvector(8, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_causereg_iv8d01550ba34aa421cfc2ce657745d131.tex b/sail_latex_mips/valz_get_causereg_iv8d01550ba34aa421cfc2ce657745d131.tex new file mode 100644 index 00000000..c40eabe0 --- /dev/null +++ b/sail_latex_mips/valz_get_causereg_iv8d01550ba34aa421cfc2ce657745d131.tex @@ -0,0 +1 @@ +_get_CauseReg_IV : CauseReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_causereg_wpcbfccc2e0292d6f04b091ed268698e68.tex b/sail_latex_mips/valz_get_causereg_wpcbfccc2e0292d6f04b091ed268698e68.tex new file mode 100644 index 00000000..2a9e698e --- /dev/null +++ b/sail_latex_mips/valz_get_causereg_wpcbfccc2e0292d6f04b091ed268698e68.tex @@ -0,0 +1 @@ +_get_CauseReg_WP : CauseReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_contextreg_badvpn2e4bacc76aa9f96063f0745bd9686a16d.tex b/sail_latex_mips/valz_get_contextreg_badvpn2e4bacc76aa9f96063f0745bd9686a16d.tex new file mode 100644 index 00000000..87bc54a6 --- /dev/null +++ b/sail_latex_mips/valz_get_contextreg_badvpn2e4bacc76aa9f96063f0745bd9686a16d.tex @@ -0,0 +1 @@ +_get_ContextReg_BadVPN2 : ContextReg -> bitvector(19, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_contextreg_bits47e3c1ae3f3d71fe07d89e26af0dbb84.tex b/sail_latex_mips/valz_get_contextreg_bits47e3c1ae3f3d71fe07d89e26af0dbb84.tex new file mode 100644 index 00000000..b821650a --- /dev/null +++ b/sail_latex_mips/valz_get_contextreg_bits47e3c1ae3f3d71fe07d89e26af0dbb84.tex @@ -0,0 +1 @@ +_get_ContextReg_bits : ContextReg -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_contextreg_ptebasebf430c35bdc563e19c3245773b4235dd.tex b/sail_latex_mips/valz_get_contextreg_ptebasebf430c35bdc563e19c3245773b4235dd.tex new file mode 100644 index 00000000..768d05db --- /dev/null +++ b/sail_latex_mips/valz_get_contextreg_ptebasebf430c35bdc563e19c3245773b4235dd.tex @@ -0,0 +1 @@ +_get_ContextReg_PTEBase : ContextReg -> bitvector(41, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_statusreg_bev76c45f173f7808e1e76c2d52dda65632.tex b/sail_latex_mips/valz_get_statusreg_bev76c45f173f7808e1e76c2d52dda65632.tex new file mode 100644 index 00000000..375572e4 --- /dev/null +++ b/sail_latex_mips/valz_get_statusreg_bev76c45f173f7808e1e76c2d52dda65632.tex @@ -0,0 +1 @@ +_get_StatusReg_BEV : StatusReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_statusreg_bits13ab4975f147071137062e2fb2cba87b.tex b/sail_latex_mips/valz_get_statusreg_bits13ab4975f147071137062e2fb2cba87b.tex new file mode 100644 index 00000000..357e68f9 --- /dev/null +++ b/sail_latex_mips/valz_get_statusreg_bits13ab4975f147071137062e2fb2cba87b.tex @@ -0,0 +1 @@ +_get_StatusReg_bits : StatusReg -> bitvector(32, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_statusreg_cuedce8fb3afbd16db31018057f7ad0656.tex b/sail_latex_mips/valz_get_statusreg_cuedce8fb3afbd16db31018057f7ad0656.tex new file mode 100644 index 00000000..d31191f3 --- /dev/null +++ b/sail_latex_mips/valz_get_statusreg_cuedce8fb3afbd16db31018057f7ad0656.tex @@ -0,0 +1 @@ +_get_StatusReg_CU : StatusReg -> bitvector(4, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_statusreg_erl047dd24d9a0767af7b83a9fcc72aa531.tex b/sail_latex_mips/valz_get_statusreg_erl047dd24d9a0767af7b83a9fcc72aa531.tex new file mode 100644 index 00000000..41f81e73 --- /dev/null +++ b/sail_latex_mips/valz_get_statusreg_erl047dd24d9a0767af7b83a9fcc72aa531.tex @@ -0,0 +1 @@ +_get_StatusReg_ERL : StatusReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_statusreg_exlf7067c47c7863a4f0a8be94eba05edef.tex b/sail_latex_mips/valz_get_statusreg_exlf7067c47c7863a4f0a8be94eba05edef.tex new file mode 100644 index 00000000..a75bd981 --- /dev/null +++ b/sail_latex_mips/valz_get_statusreg_exlf7067c47c7863a4f0a8be94eba05edef.tex @@ -0,0 +1 @@ +_get_StatusReg_EXL : StatusReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_statusreg_ie87acfa5c96aee0f703b36a2c55d5a4de.tex b/sail_latex_mips/valz_get_statusreg_ie87acfa5c96aee0f703b36a2c55d5a4de.tex new file mode 100644 index 00000000..483fb22c --- /dev/null +++ b/sail_latex_mips/valz_get_statusreg_ie87acfa5c96aee0f703b36a2c55d5a4de.tex @@ -0,0 +1 @@ +_get_StatusReg_IE : StatusReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_statusreg_im66d47baebca79600073ab942220bcc99.tex b/sail_latex_mips/valz_get_statusreg_im66d47baebca79600073ab942220bcc99.tex new file mode 100644 index 00000000..9e6b32da --- /dev/null +++ b/sail_latex_mips/valz_get_statusreg_im66d47baebca79600073ab942220bcc99.tex @@ -0,0 +1 @@ +_get_StatusReg_IM : StatusReg -> bitvector(8, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_statusreg_ksuf8d380201accc76c9427799218dced26.tex b/sail_latex_mips/valz_get_statusreg_ksuf8d380201accc76c9427799218dced26.tex new file mode 100644 index 00000000..ee5aafd2 --- /dev/null +++ b/sail_latex_mips/valz_get_statusreg_ksuf8d380201accc76c9427799218dced26.tex @@ -0,0 +1 @@ +_get_StatusReg_KSU : StatusReg -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_statusreg_kxc88611604b607976b47f459ed5655112.tex b/sail_latex_mips/valz_get_statusreg_kxc88611604b607976b47f459ed5655112.tex new file mode 100644 index 00000000..139e13c2 --- /dev/null +++ b/sail_latex_mips/valz_get_statusreg_kxc88611604b607976b47f459ed5655112.tex @@ -0,0 +1 @@ +_get_StatusReg_KX : StatusReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_statusreg_sx3938519915fcbea54772a8fb5488c993.tex b/sail_latex_mips/valz_get_statusreg_sx3938519915fcbea54772a8fb5488c993.tex new file mode 100644 index 00000000..418d82c2 --- /dev/null +++ b/sail_latex_mips/valz_get_statusreg_sx3938519915fcbea54772a8fb5488c993.tex @@ -0,0 +1 @@ +_get_StatusReg_SX : StatusReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_statusreg_ux8cca4453438a4350fa4cd09d63ecb142.tex b/sail_latex_mips/valz_get_statusreg_ux8cca4453438a4350fa4cd09d63ecb142.tex new file mode 100644 index 00000000..783c7e57 --- /dev/null +++ b/sail_latex_mips/valz_get_statusreg_ux8cca4453438a4350fa4cd09d63ecb142.tex @@ -0,0 +1 @@ +_get_StatusReg_UX : StatusReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_asidfa47e24a47d583f491181ee21931f29a.tex b/sail_latex_mips/valz_get_tlbentry_asidfa47e24a47d583f491181ee21931f29a.tex new file mode 100644 index 00000000..59a53d49 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_asidfa47e24a47d583f491181ee21931f29a.tex @@ -0,0 +1 @@ +_get_TLBEntry_asid : TLBEntry -> bitvector(8, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_bits2da520175dbc548dab43cb481dedc49b.tex b/sail_latex_mips/valz_get_tlbentry_bits2da520175dbc548dab43cb481dedc49b.tex new file mode 100644 index 00000000..d061e075 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_bits2da520175dbc548dab43cb481dedc49b.tex @@ -0,0 +1 @@ +_get_TLBEntry_bits : TLBEntry -> bitvector(119, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_c0b08789b6ce25b380e3b34466198a7af1.tex b/sail_latex_mips/valz_get_tlbentry_c0b08789b6ce25b380e3b34466198a7af1.tex new file mode 100644 index 00000000..09efab33 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_c0b08789b6ce25b380e3b34466198a7af1.tex @@ -0,0 +1 @@ +_get_TLBEntry_c0 : TLBEntry -> bitvector(3, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_c1d9106b812c3987770aecb7aeee7f8fda.tex b/sail_latex_mips/valz_get_tlbentry_c1d9106b812c3987770aecb7aeee7f8fda.tex new file mode 100644 index 00000000..1740905c --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_c1d9106b812c3987770aecb7aeee7f8fda.tex @@ -0,0 +1 @@ +_get_TLBEntry_c1 : TLBEntry -> bitvector(3, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_capl002a98d71ed3a8b3eadd001ccafb63932.tex b/sail_latex_mips/valz_get_tlbentry_capl002a98d71ed3a8b3eadd001ccafb63932.tex new file mode 100644 index 00000000..660da6e9 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_capl002a98d71ed3a8b3eadd001ccafb63932.tex @@ -0,0 +1 @@ +_get_TLBEntry_capl0 : TLBEntry -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_capl18435a7d1c69be8be8044b9bb801ed828.tex b/sail_latex_mips/valz_get_tlbentry_capl18435a7d1c69be8be8044b9bb801ed828.tex new file mode 100644 index 00000000..918c3cb4 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_capl18435a7d1c69be8be8044b9bb801ed828.tex @@ -0,0 +1 @@ +_get_TLBEntry_capl1 : TLBEntry -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_caplg09c840f382389fcdb91e393c6d35109de.tex b/sail_latex_mips/valz_get_tlbentry_caplg09c840f382389fcdb91e393c6d35109de.tex new file mode 100644 index 00000000..51ac4b07 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_caplg09c840f382389fcdb91e393c6d35109de.tex @@ -0,0 +1 @@ +_get_TLBEntry_caplg0 : TLBEntry -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_caplg177ddc2b577eec904043a0416c9132f3d.tex b/sail_latex_mips/valz_get_tlbentry_caplg177ddc2b577eec904043a0416c9132f3d.tex new file mode 100644 index 00000000..57fdb28b --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_caplg177ddc2b577eec904043a0416c9132f3d.tex @@ -0,0 +1 @@ +_get_TLBEntry_caplg1 : TLBEntry -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_caps0426df7440d2fbd940d22c5ff5d90fe0a.tex b/sail_latex_mips/valz_get_tlbentry_caps0426df7440d2fbd940d22c5ff5d90fe0a.tex new file mode 100644 index 00000000..03fee695 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_caps0426df7440d2fbd940d22c5ff5d90fe0a.tex @@ -0,0 +1 @@ +_get_TLBEntry_caps0 : TLBEntry -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_caps1be8ae1b776f69c2c07935aba85396d3e.tex b/sail_latex_mips/valz_get_tlbentry_caps1be8ae1b776f69c2c07935aba85396d3e.tex new file mode 100644 index 00000000..abf8a9b6 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_caps1be8ae1b776f69c2c07935aba85396d3e.tex @@ -0,0 +1 @@ +_get_TLBEntry_caps1 : TLBEntry -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_d0b7eda1bce555ea7549a9dffbb9e46114.tex b/sail_latex_mips/valz_get_tlbentry_d0b7eda1bce555ea7549a9dffbb9e46114.tex new file mode 100644 index 00000000..69fc8e96 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_d0b7eda1bce555ea7549a9dffbb9e46114.tex @@ -0,0 +1 @@ +_get_TLBEntry_d0 : TLBEntry -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_d13706a372dd719081d99230fe90f050d9.tex b/sail_latex_mips/valz_get_tlbentry_d13706a372dd719081d99230fe90f050d9.tex new file mode 100644 index 00000000..3a0dd235 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_d13706a372dd719081d99230fe90f050d9.tex @@ -0,0 +1 @@ +_get_TLBEntry_d1 : TLBEntry -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_geeba2979d3314ef4d79ccdc6321d56cf.tex b/sail_latex_mips/valz_get_tlbentry_geeba2979d3314ef4d79ccdc6321d56cf.tex new file mode 100644 index 00000000..bc35dd57 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_geeba2979d3314ef4d79ccdc6321d56cf.tex @@ -0,0 +1 @@ +_get_TLBEntry_g : TLBEntry -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_pagemask3eb7a6727c91e807993723589bef84a0.tex b/sail_latex_mips/valz_get_tlbentry_pagemask3eb7a6727c91e807993723589bef84a0.tex new file mode 100644 index 00000000..cc452bb9 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_pagemask3eb7a6727c91e807993723589bef84a0.tex @@ -0,0 +1 @@ +_get_TLBEntry_pagemask : TLBEntry -> bitvector(16, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_pfn0a3de4c4c668cdca3f146093a35068cb5.tex b/sail_latex_mips/valz_get_tlbentry_pfn0a3de4c4c668cdca3f146093a35068cb5.tex new file mode 100644 index 00000000..6e15e617 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_pfn0a3de4c4c668cdca3f146093a35068cb5.tex @@ -0,0 +1 @@ +_get_TLBEntry_pfn0 : TLBEntry -> bitvector(24, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_pfn18a458700cdc028cfe46524e00f6a420b.tex b/sail_latex_mips/valz_get_tlbentry_pfn18a458700cdc028cfe46524e00f6a420b.tex new file mode 100644 index 00000000..f42ac1cb --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_pfn18a458700cdc028cfe46524e00f6a420b.tex @@ -0,0 +1 @@ +_get_TLBEntry_pfn1 : TLBEntry -> bitvector(24, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_ra5d843d822ff9bbef3239d0723cdb795.tex b/sail_latex_mips/valz_get_tlbentry_ra5d843d822ff9bbef3239d0723cdb795.tex new file mode 100644 index 00000000..7163a4f6 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_ra5d843d822ff9bbef3239d0723cdb795.tex @@ -0,0 +1 @@ +_get_TLBEntry_r : TLBEntry -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_v035b9c796665ee176973e82b6ca9389bf.tex b/sail_latex_mips/valz_get_tlbentry_v035b9c796665ee176973e82b6ca9389bf.tex new file mode 100644 index 00000000..14fa3092 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_v035b9c796665ee176973e82b6ca9389bf.tex @@ -0,0 +1 @@ +_get_TLBEntry_v0 : TLBEntry -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_v13ee360aa18ead69581f7606800abe3c1.tex b/sail_latex_mips/valz_get_tlbentry_v13ee360aa18ead69581f7606800abe3c1.tex new file mode 100644 index 00000000..2822a7c2 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_v13ee360aa18ead69581f7606800abe3c1.tex @@ -0,0 +1 @@ +_get_TLBEntry_v1 : TLBEntry -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_valid270ce68bc126e75f8229aa1123921cdb.tex b/sail_latex_mips/valz_get_tlbentry_valid270ce68bc126e75f8229aa1123921cdb.tex new file mode 100644 index 00000000..7e772d47 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_valid270ce68bc126e75f8229aa1123921cdb.tex @@ -0,0 +1 @@ +_get_TLBEntry_valid : TLBEntry -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentry_vpn28db0f6d71609de412536d5cf13f67255.tex b/sail_latex_mips/valz_get_tlbentry_vpn28db0f6d71609de412536d5cf13f67255.tex new file mode 100644 index 00000000..907fa879 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentry_vpn28db0f6d71609de412536d5cf13f67255.tex @@ -0,0 +1 @@ +_get_TLBEntry_vpn2 : TLBEntry -> bitvector(27, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryhireg_asidf305efdb6fafa938b0b36e9cf1064c32.tex b/sail_latex_mips/valz_get_tlbentryhireg_asidf305efdb6fafa938b0b36e9cf1064c32.tex new file mode 100644 index 00000000..dda3da7d --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryhireg_asidf305efdb6fafa938b0b36e9cf1064c32.tex @@ -0,0 +1 @@ +_get_TLBEntryHiReg_ASID : TLBEntryHiReg -> bitvector(8, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryhireg_bitsc1fe8d0802182557771e92e1a4937cbe.tex b/sail_latex_mips/valz_get_tlbentryhireg_bitsc1fe8d0802182557771e92e1a4937cbe.tex new file mode 100644 index 00000000..b3c97fb8 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryhireg_bitsc1fe8d0802182557771e92e1a4937cbe.tex @@ -0,0 +1 @@ +_get_TLBEntryHiReg_bits : TLBEntryHiReg -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryhireg_clgkfdb82e0b9411605641d3f9425136dfa9.tex b/sail_latex_mips/valz_get_tlbentryhireg_clgkfdb82e0b9411605641d3f9425136dfa9.tex new file mode 100644 index 00000000..8b1694fd --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryhireg_clgkfdb82e0b9411605641d3f9425136dfa9.tex @@ -0,0 +1 @@ +_get_TLBEntryHiReg_CLGK : TLBEntryHiReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryhireg_clgseb7676dc6f5a395d559518d6f85dcb64.tex b/sail_latex_mips/valz_get_tlbentryhireg_clgseb7676dc6f5a395d559518d6f85dcb64.tex new file mode 100644 index 00000000..fa31b0dc --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryhireg_clgseb7676dc6f5a395d559518d6f85dcb64.tex @@ -0,0 +1 @@ +_get_TLBEntryHiReg_CLGS : TLBEntryHiReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryhireg_clgu64e2f125adf86091d1447f203f4ee7c6.tex b/sail_latex_mips/valz_get_tlbentryhireg_clgu64e2f125adf86091d1447f203f4ee7c6.tex new file mode 100644 index 00000000..394ce109 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryhireg_clgu64e2f125adf86091d1447f203f4ee7c6.tex @@ -0,0 +1 @@ +_get_TLBEntryHiReg_CLGU : TLBEntryHiReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryhireg_r44dfedd92d1d8ea253c1ecd027897188.tex b/sail_latex_mips/valz_get_tlbentryhireg_r44dfedd92d1d8ea253c1ecd027897188.tex new file mode 100644 index 00000000..1cc7d6e2 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryhireg_r44dfedd92d1d8ea253c1ecd027897188.tex @@ -0,0 +1 @@ +_get_TLBEntryHiReg_R : TLBEntryHiReg -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryhireg_vpn226453e167422a9d6ebc21b19f1c01475.tex b/sail_latex_mips/valz_get_tlbentryhireg_vpn226453e167422a9d6ebc21b19f1c01475.tex new file mode 100644 index 00000000..52dfec68 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryhireg_vpn226453e167422a9d6ebc21b19f1c01475.tex @@ -0,0 +1 @@ +_get_TLBEntryHiReg_VPN2 : TLBEntryHiReg -> bitvector(27, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryloreg_bitsb5a9322379b7dc75d999a3feb221ea39.tex b/sail_latex_mips/valz_get_tlbentryloreg_bitsb5a9322379b7dc75d999a3feb221ea39.tex new file mode 100644 index 00000000..2573edb5 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryloreg_bitsb5a9322379b7dc75d999a3feb221ea39.tex @@ -0,0 +1 @@ +_get_TLBEntryLoReg_bits : TLBEntryLoReg -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryloreg_c2c40f3d64ca0b68a2277af1f60c581c1.tex b/sail_latex_mips/valz_get_tlbentryloreg_c2c40f3d64ca0b68a2277af1f60c581c1.tex new file mode 100644 index 00000000..b71d8bfb --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryloreg_c2c40f3d64ca0b68a2277af1f60c581c1.tex @@ -0,0 +1 @@ +_get_TLBEntryLoReg_C : TLBEntryLoReg -> bitvector(3, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryloreg_capl1cbdda840b22f0691c3ea7fd12bfa8a7.tex b/sail_latex_mips/valz_get_tlbentryloreg_capl1cbdda840b22f0691c3ea7fd12bfa8a7.tex new file mode 100644 index 00000000..1378b479 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryloreg_capl1cbdda840b22f0691c3ea7fd12bfa8a7.tex @@ -0,0 +1 @@ +_get_TLBEntryLoReg_CapL : TLBEntryLoReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryloreg_caplg786d24724304fa8846dc63540a94622b.tex b/sail_latex_mips/valz_get_tlbentryloreg_caplg786d24724304fa8846dc63540a94622b.tex new file mode 100644 index 00000000..0abb56dd --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryloreg_caplg786d24724304fa8846dc63540a94622b.tex @@ -0,0 +1 @@ +_get_TLBEntryLoReg_CapLG : TLBEntryLoReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryloreg_capsde4f5c8e764147c851f8e5e575b0078e.tex b/sail_latex_mips/valz_get_tlbentryloreg_capsde4f5c8e764147c851f8e5e575b0078e.tex new file mode 100644 index 00000000..3e0e722e --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryloreg_capsde4f5c8e764147c851f8e5e575b0078e.tex @@ -0,0 +1 @@ +_get_TLBEntryLoReg_CapS : TLBEntryLoReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryloreg_d4b10819936f555836fbb97995377cad3.tex b/sail_latex_mips/valz_get_tlbentryloreg_d4b10819936f555836fbb97995377cad3.tex new file mode 100644 index 00000000..a7c81232 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryloreg_d4b10819936f555836fbb97995377cad3.tex @@ -0,0 +1 @@ +_get_TLBEntryLoReg_D : TLBEntryLoReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryloreg_g502b190f751a82f1efdb937a5164a942.tex b/sail_latex_mips/valz_get_tlbentryloreg_g502b190f751a82f1efdb937a5164a942.tex new file mode 100644 index 00000000..a0d6fbff --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryloreg_g502b190f751a82f1efdb937a5164a942.tex @@ -0,0 +1 @@ +_get_TLBEntryLoReg_G : TLBEntryLoReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryloreg_pfn7485f8da186fc5d3d7c7c1b76ae7d61a.tex b/sail_latex_mips/valz_get_tlbentryloreg_pfn7485f8da186fc5d3d7c7c1b76ae7d61a.tex new file mode 100644 index 00000000..6981b4f8 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryloreg_pfn7485f8da186fc5d3d7c7c1b76ae7d61a.tex @@ -0,0 +1 @@ +_get_TLBEntryLoReg_PFN : TLBEntryLoReg -> bitvector(24, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_tlbentryloreg_v92356d3167d468ba946d0be3ad44b292.tex b/sail_latex_mips/valz_get_tlbentryloreg_v92356d3167d468ba946d0be3ad44b292.tex new file mode 100644 index 00000000..b2dbe4d9 --- /dev/null +++ b/sail_latex_mips/valz_get_tlbentryloreg_v92356d3167d468ba946d0be3ad44b292.tex @@ -0,0 +1 @@ +_get_TLBEntryLoReg_V : TLBEntryLoReg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_xcontextreg_bits2bb965f07f7084015cb7fcd7fddaa172.tex b/sail_latex_mips/valz_get_xcontextreg_bits2bb965f07f7084015cb7fcd7fddaa172.tex new file mode 100644 index 00000000..bb997fa0 --- /dev/null +++ b/sail_latex_mips/valz_get_xcontextreg_bits2bb965f07f7084015cb7fcd7fddaa172.tex @@ -0,0 +1 @@ +_get_XContextReg_bits : XContextReg -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_xcontextreg_xbadvpn2404ed71ef244d675e19fa66dceb1c9c3.tex b/sail_latex_mips/valz_get_xcontextreg_xbadvpn2404ed71ef244d675e19fa66dceb1c9c3.tex new file mode 100644 index 00000000..2ffd964e --- /dev/null +++ b/sail_latex_mips/valz_get_xcontextreg_xbadvpn2404ed71ef244d675e19fa66dceb1c9c3.tex @@ -0,0 +1 @@ +_get_XContextReg_XBadVPN2 : XContextReg -> bitvector(27, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_xcontextreg_xptebase0f9f79f33119625b2142eafc017db467.tex b/sail_latex_mips/valz_get_xcontextreg_xptebase0f9f79f33119625b2142eafc017db467.tex new file mode 100644 index 00000000..5c7e12a9 --- /dev/null +++ b/sail_latex_mips/valz_get_xcontextreg_xptebase0f9f79f33119625b2142eafc017db467.tex @@ -0,0 +1 @@ +_get_XContextReg_XPTEBase : XContextReg -> bitvector(31, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_get_xcontextreg_xrbc5c747b1b3124406ffd75a370867ebf.tex b/sail_latex_mips/valz_get_xcontextreg_xrbc5c747b1b3124406ffd75a370867ebf.tex new file mode 100644 index 00000000..5005d487 --- /dev/null +++ b/sail_latex_mips/valz_get_xcontextreg_xrbc5c747b1b3124406ffd75a370867ebf.tex @@ -0,0 +1 @@ +_get_XContextReg_XR : XContextReg -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_mips/valz_set_capcausereg_bits0f09722beb30b9b32d98ac38786a393b.tex b/sail_latex_mips/valz_set_capcausereg_bits0f09722beb30b9b32d98ac38786a393b.tex new file mode 100644 index 00000000..d5c143ee --- /dev/null +++ b/sail_latex_mips/valz_set_capcausereg_bits0f09722beb30b9b32d98ac38786a393b.tex @@ -0,0 +1 @@ +_set_CapCauseReg_bits : (register(CapCauseReg), bitvector(16, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_capcausereg_exccode61e56f7469922be2cde66ae4460b17ee.tex b/sail_latex_mips/valz_set_capcausereg_exccode61e56f7469922be2cde66ae4460b17ee.tex new file mode 100644 index 00000000..99af8814 --- /dev/null +++ b/sail_latex_mips/valz_set_capcausereg_exccode61e56f7469922be2cde66ae4460b17ee.tex @@ -0,0 +1 @@ +_set_CapCauseReg_ExcCode : (register(CapCauseReg), bitvector(8, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_capcausereg_regnum2d65e24c7a9625fc0aed9327369188a6.tex b/sail_latex_mips/valz_set_capcausereg_regnum2d65e24c7a9625fc0aed9327369188a6.tex new file mode 100644 index 00000000..3b9dc92e --- /dev/null +++ b/sail_latex_mips/valz_set_capcausereg_regnum2d65e24c7a9625fc0aed9327369188a6.tex @@ -0,0 +1 @@ +_set_CapCauseReg_RegNum : (register(CapCauseReg), bitvector(8, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_causereg_bdb5f488f812625b8e1f8d3846c87da635.tex b/sail_latex_mips/valz_set_causereg_bdb5f488f812625b8e1f8d3846c87da635.tex new file mode 100644 index 00000000..82695f88 --- /dev/null +++ b/sail_latex_mips/valz_set_causereg_bdb5f488f812625b8e1f8d3846c87da635.tex @@ -0,0 +1 @@ +_set_CauseReg_BD : (register(CauseReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_causereg_bits73c1fb63898bc74942a3c60d0ceacd0a.tex b/sail_latex_mips/valz_set_causereg_bits73c1fb63898bc74942a3c60d0ceacd0a.tex new file mode 100644 index 00000000..01d2536e --- /dev/null +++ b/sail_latex_mips/valz_set_causereg_bits73c1fb63898bc74942a3c60d0ceacd0a.tex @@ -0,0 +1 @@ +_set_CauseReg_bits : (register(CauseReg), bitvector(32, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_causereg_ce01fc3f03d0d74f4e0d5a0942681ed38a.tex b/sail_latex_mips/valz_set_causereg_ce01fc3f03d0d74f4e0d5a0942681ed38a.tex new file mode 100644 index 00000000..b6bb1031 --- /dev/null +++ b/sail_latex_mips/valz_set_causereg_ce01fc3f03d0d74f4e0d5a0942681ed38a.tex @@ -0,0 +1 @@ +_set_CauseReg_CE : (register(CauseReg), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_causereg_exccode9170f535490a825d67ffd95250c51021.tex b/sail_latex_mips/valz_set_causereg_exccode9170f535490a825d67ffd95250c51021.tex new file mode 100644 index 00000000..e32ada92 --- /dev/null +++ b/sail_latex_mips/valz_set_causereg_exccode9170f535490a825d67ffd95250c51021.tex @@ -0,0 +1 @@ +_set_CauseReg_ExcCode : (register(CauseReg), bitvector(5, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_causereg_ip2026aa5013ac14eda0adff00c82c7a29.tex b/sail_latex_mips/valz_set_causereg_ip2026aa5013ac14eda0adff00c82c7a29.tex new file mode 100644 index 00000000..b30207a2 --- /dev/null +++ b/sail_latex_mips/valz_set_causereg_ip2026aa5013ac14eda0adff00c82c7a29.tex @@ -0,0 +1 @@ +_set_CauseReg_IP : (register(CauseReg), bitvector(8, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_causereg_iv526ac3c679cca6391db51d524d6d72ad.tex b/sail_latex_mips/valz_set_causereg_iv526ac3c679cca6391db51d524d6d72ad.tex new file mode 100644 index 00000000..4b0c145d --- /dev/null +++ b/sail_latex_mips/valz_set_causereg_iv526ac3c679cca6391db51d524d6d72ad.tex @@ -0,0 +1 @@ +_set_CauseReg_IV : (register(CauseReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_causereg_wpff070e6ed3da50f2ad0a0d32ca5c1969.tex b/sail_latex_mips/valz_set_causereg_wpff070e6ed3da50f2ad0a0d32ca5c1969.tex new file mode 100644 index 00000000..d06ea1ad --- /dev/null +++ b/sail_latex_mips/valz_set_causereg_wpff070e6ed3da50f2ad0a0d32ca5c1969.tex @@ -0,0 +1 @@ +_set_CauseReg_WP : (register(CauseReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_contextreg_badvpn29fd378dc6ecdfabb3a91f7deb59e56a1.tex b/sail_latex_mips/valz_set_contextreg_badvpn29fd378dc6ecdfabb3a91f7deb59e56a1.tex new file mode 100644 index 00000000..50cb7113 --- /dev/null +++ b/sail_latex_mips/valz_set_contextreg_badvpn29fd378dc6ecdfabb3a91f7deb59e56a1.tex @@ -0,0 +1 @@ +_set_ContextReg_BadVPN2 : (register(ContextReg), bitvector(19, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_contextreg_bitsbbc1c515c2c901309dcbe9d97b5823cc.tex b/sail_latex_mips/valz_set_contextreg_bitsbbc1c515c2c901309dcbe9d97b5823cc.tex new file mode 100644 index 00000000..0af81883 --- /dev/null +++ b/sail_latex_mips/valz_set_contextreg_bitsbbc1c515c2c901309dcbe9d97b5823cc.tex @@ -0,0 +1 @@ +_set_ContextReg_bits : (register(ContextReg), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_contextreg_ptebase3d2c746ed33c90438134f4f612df5252.tex b/sail_latex_mips/valz_set_contextreg_ptebase3d2c746ed33c90438134f4f612df5252.tex new file mode 100644 index 00000000..93eb20c0 --- /dev/null +++ b/sail_latex_mips/valz_set_contextreg_ptebase3d2c746ed33c90438134f4f612df5252.tex @@ -0,0 +1 @@ +_set_ContextReg_PTEBase : (register(ContextReg), bitvector(41, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_statusreg_bev924ce14fffca002f9543765ad1071fc1.tex b/sail_latex_mips/valz_set_statusreg_bev924ce14fffca002f9543765ad1071fc1.tex new file mode 100644 index 00000000..e81b3925 --- /dev/null +++ b/sail_latex_mips/valz_set_statusreg_bev924ce14fffca002f9543765ad1071fc1.tex @@ -0,0 +1 @@ +_set_StatusReg_BEV : (register(StatusReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_statusreg_bits4f92ee35af828325dd4c014bea381e05.tex b/sail_latex_mips/valz_set_statusreg_bits4f92ee35af828325dd4c014bea381e05.tex new file mode 100644 index 00000000..f64b6c7d --- /dev/null +++ b/sail_latex_mips/valz_set_statusreg_bits4f92ee35af828325dd4c014bea381e05.tex @@ -0,0 +1 @@ +_set_StatusReg_bits : (register(StatusReg), bitvector(32, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_statusreg_cu382e74466b55efdc144bb605d76fa627.tex b/sail_latex_mips/valz_set_statusreg_cu382e74466b55efdc144bb605d76fa627.tex new file mode 100644 index 00000000..17c795e0 --- /dev/null +++ b/sail_latex_mips/valz_set_statusreg_cu382e74466b55efdc144bb605d76fa627.tex @@ -0,0 +1 @@ +_set_StatusReg_CU : (register(StatusReg), bitvector(4, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_statusreg_erld7df28f36a304a50bf4b1ac7531ab82d.tex b/sail_latex_mips/valz_set_statusreg_erld7df28f36a304a50bf4b1ac7531ab82d.tex new file mode 100644 index 00000000..a829a18e --- /dev/null +++ b/sail_latex_mips/valz_set_statusreg_erld7df28f36a304a50bf4b1ac7531ab82d.tex @@ -0,0 +1 @@ +_set_StatusReg_ERL : (register(StatusReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_statusreg_exl9372beedcb66769ffb9a665777e1daaf.tex b/sail_latex_mips/valz_set_statusreg_exl9372beedcb66769ffb9a665777e1daaf.tex new file mode 100644 index 00000000..b97e1ff9 --- /dev/null +++ b/sail_latex_mips/valz_set_statusreg_exl9372beedcb66769ffb9a665777e1daaf.tex @@ -0,0 +1 @@ +_set_StatusReg_EXL : (register(StatusReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_statusreg_ie25e69e4e6e9e37925cebd95113995258.tex b/sail_latex_mips/valz_set_statusreg_ie25e69e4e6e9e37925cebd95113995258.tex new file mode 100644 index 00000000..2b7a5516 --- /dev/null +++ b/sail_latex_mips/valz_set_statusreg_ie25e69e4e6e9e37925cebd95113995258.tex @@ -0,0 +1 @@ +_set_StatusReg_IE : (register(StatusReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_statusreg_imfe5182ff0da7697ee27eb5e78eae3abc.tex b/sail_latex_mips/valz_set_statusreg_imfe5182ff0da7697ee27eb5e78eae3abc.tex new file mode 100644 index 00000000..dd0f2774 --- /dev/null +++ b/sail_latex_mips/valz_set_statusreg_imfe5182ff0da7697ee27eb5e78eae3abc.tex @@ -0,0 +1 @@ +_set_StatusReg_IM : (register(StatusReg), bitvector(8, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_statusreg_ksu10d20f93e7ee13723bb4b72cd7d3ea0a.tex b/sail_latex_mips/valz_set_statusreg_ksu10d20f93e7ee13723bb4b72cd7d3ea0a.tex new file mode 100644 index 00000000..b0c88170 --- /dev/null +++ b/sail_latex_mips/valz_set_statusreg_ksu10d20f93e7ee13723bb4b72cd7d3ea0a.tex @@ -0,0 +1 @@ +_set_StatusReg_KSU : (register(StatusReg), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_statusreg_kxca8ee85879aede01e75749335f0c00c9.tex b/sail_latex_mips/valz_set_statusreg_kxca8ee85879aede01e75749335f0c00c9.tex new file mode 100644 index 00000000..d85d44da --- /dev/null +++ b/sail_latex_mips/valz_set_statusreg_kxca8ee85879aede01e75749335f0c00c9.tex @@ -0,0 +1 @@ +_set_StatusReg_KX : (register(StatusReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_statusreg_sx7f79d23ff0ae6a043165750f8bb87713.tex b/sail_latex_mips/valz_set_statusreg_sx7f79d23ff0ae6a043165750f8bb87713.tex new file mode 100644 index 00000000..3a004295 --- /dev/null +++ b/sail_latex_mips/valz_set_statusreg_sx7f79d23ff0ae6a043165750f8bb87713.tex @@ -0,0 +1 @@ +_set_StatusReg_SX : (register(StatusReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_statusreg_uxedb360d1d15e38d213f56b0eaa07f3a6.tex b/sail_latex_mips/valz_set_statusreg_uxedb360d1d15e38d213f56b0eaa07f3a6.tex new file mode 100644 index 00000000..ab367cd0 --- /dev/null +++ b/sail_latex_mips/valz_set_statusreg_uxedb360d1d15e38d213f56b0eaa07f3a6.tex @@ -0,0 +1 @@ +_set_StatusReg_UX : (register(StatusReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_asid24ada87abf0e962f7eae9b5498024297.tex b/sail_latex_mips/valz_set_tlbentry_asid24ada87abf0e962f7eae9b5498024297.tex new file mode 100644 index 00000000..27cd9a06 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_asid24ada87abf0e962f7eae9b5498024297.tex @@ -0,0 +1 @@ +_set_TLBEntry_asid : (register(TLBEntry), bitvector(8, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_bits757b4b8be4b3d6e342d238326f83470b.tex b/sail_latex_mips/valz_set_tlbentry_bits757b4b8be4b3d6e342d238326f83470b.tex new file mode 100644 index 00000000..7a00fae1 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_bits757b4b8be4b3d6e342d238326f83470b.tex @@ -0,0 +1 @@ +_set_TLBEntry_bits : (register(TLBEntry), bitvector(119, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_c06c71cb666e35c0f50388fb49595583ae.tex b/sail_latex_mips/valz_set_tlbentry_c06c71cb666e35c0f50388fb49595583ae.tex new file mode 100644 index 00000000..57f19ef6 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_c06c71cb666e35c0f50388fb49595583ae.tex @@ -0,0 +1 @@ +_set_TLBEntry_c0 : (register(TLBEntry), bitvector(3, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_c148e5c1e1296cfbf56bc100936b91f1e1.tex b/sail_latex_mips/valz_set_tlbentry_c148e5c1e1296cfbf56bc100936b91f1e1.tex new file mode 100644 index 00000000..3eb28c67 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_c148e5c1e1296cfbf56bc100936b91f1e1.tex @@ -0,0 +1 @@ +_set_TLBEntry_c1 : (register(TLBEntry), bitvector(3, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_capl02f9386e56e409f94f40b03eb58643a70.tex b/sail_latex_mips/valz_set_tlbentry_capl02f9386e56e409f94f40b03eb58643a70.tex new file mode 100644 index 00000000..1800e4cf --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_capl02f9386e56e409f94f40b03eb58643a70.tex @@ -0,0 +1 @@ +_set_TLBEntry_capl0 : (register(TLBEntry), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_capl11a35d84794ef9016f4f97c80e21c876e.tex b/sail_latex_mips/valz_set_tlbentry_capl11a35d84794ef9016f4f97c80e21c876e.tex new file mode 100644 index 00000000..cb67f2dc --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_capl11a35d84794ef9016f4f97c80e21c876e.tex @@ -0,0 +1 @@ +_set_TLBEntry_capl1 : (register(TLBEntry), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_caplg0226ebad6aa3e6193defac30a2d1ea82d.tex b/sail_latex_mips/valz_set_tlbentry_caplg0226ebad6aa3e6193defac30a2d1ea82d.tex new file mode 100644 index 00000000..001f94a9 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_caplg0226ebad6aa3e6193defac30a2d1ea82d.tex @@ -0,0 +1 @@ +_set_TLBEntry_caplg0 : (register(TLBEntry), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_caplg1c568708bced17cbfbd6bc97c09748e38.tex b/sail_latex_mips/valz_set_tlbentry_caplg1c568708bced17cbfbd6bc97c09748e38.tex new file mode 100644 index 00000000..12272d71 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_caplg1c568708bced17cbfbd6bc97c09748e38.tex @@ -0,0 +1 @@ +_set_TLBEntry_caplg1 : (register(TLBEntry), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_caps0857000eddf4e4fae631d006dab5b1e0b.tex b/sail_latex_mips/valz_set_tlbentry_caps0857000eddf4e4fae631d006dab5b1e0b.tex new file mode 100644 index 00000000..6f4360e0 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_caps0857000eddf4e4fae631d006dab5b1e0b.tex @@ -0,0 +1 @@ +_set_TLBEntry_caps0 : (register(TLBEntry), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_caps14e73f26c66b0f5dd767fc96d260e533e.tex b/sail_latex_mips/valz_set_tlbentry_caps14e73f26c66b0f5dd767fc96d260e533e.tex new file mode 100644 index 00000000..96b2156c --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_caps14e73f26c66b0f5dd767fc96d260e533e.tex @@ -0,0 +1 @@ +_set_TLBEntry_caps1 : (register(TLBEntry), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_d0868263c352cb541c47607b23c5681223.tex b/sail_latex_mips/valz_set_tlbentry_d0868263c352cb541c47607b23c5681223.tex new file mode 100644 index 00000000..b6565303 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_d0868263c352cb541c47607b23c5681223.tex @@ -0,0 +1 @@ +_set_TLBEntry_d0 : (register(TLBEntry), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_d1f392ee8bca5cfc128a0ed08500399129.tex b/sail_latex_mips/valz_set_tlbentry_d1f392ee8bca5cfc128a0ed08500399129.tex new file mode 100644 index 00000000..95103f34 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_d1f392ee8bca5cfc128a0ed08500399129.tex @@ -0,0 +1 @@ +_set_TLBEntry_d1 : (register(TLBEntry), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_g2bf85ee100b3f01a0e05550245e7babe.tex b/sail_latex_mips/valz_set_tlbentry_g2bf85ee100b3f01a0e05550245e7babe.tex new file mode 100644 index 00000000..d9f3b53c --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_g2bf85ee100b3f01a0e05550245e7babe.tex @@ -0,0 +1 @@ +_set_TLBEntry_g : (register(TLBEntry), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_pagemask688109458a7688b3fb0c4bd96cc468ce.tex b/sail_latex_mips/valz_set_tlbentry_pagemask688109458a7688b3fb0c4bd96cc468ce.tex new file mode 100644 index 00000000..7c88c058 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_pagemask688109458a7688b3fb0c4bd96cc468ce.tex @@ -0,0 +1 @@ +_set_TLBEntry_pagemask : (register(TLBEntry), bitvector(16, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_pfn0572e8586307e418abaeebb59ab57b8fb.tex b/sail_latex_mips/valz_set_tlbentry_pfn0572e8586307e418abaeebb59ab57b8fb.tex new file mode 100644 index 00000000..edbd502f --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_pfn0572e8586307e418abaeebb59ab57b8fb.tex @@ -0,0 +1 @@ +_set_TLBEntry_pfn0 : (register(TLBEntry), bitvector(24, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_pfn199862dd67e6305081f59d2d64ffa6977.tex b/sail_latex_mips/valz_set_tlbentry_pfn199862dd67e6305081f59d2d64ffa6977.tex new file mode 100644 index 00000000..863c99fa --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_pfn199862dd67e6305081f59d2d64ffa6977.tex @@ -0,0 +1 @@ +_set_TLBEntry_pfn1 : (register(TLBEntry), bitvector(24, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_r13eb1c39c82ca214056fd1b1c838ef2f.tex b/sail_latex_mips/valz_set_tlbentry_r13eb1c39c82ca214056fd1b1c838ef2f.tex new file mode 100644 index 00000000..02600b7d --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_r13eb1c39c82ca214056fd1b1c838ef2f.tex @@ -0,0 +1 @@ +_set_TLBEntry_r : (register(TLBEntry), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_v03152956c4a42e1c80db703a10c7a43d4.tex b/sail_latex_mips/valz_set_tlbentry_v03152956c4a42e1c80db703a10c7a43d4.tex new file mode 100644 index 00000000..cbfeacab --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_v03152956c4a42e1c80db703a10c7a43d4.tex @@ -0,0 +1 @@ +_set_TLBEntry_v0 : (register(TLBEntry), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_v17258e9ab7f5388c5e3cc6aaba8474f00.tex b/sail_latex_mips/valz_set_tlbentry_v17258e9ab7f5388c5e3cc6aaba8474f00.tex new file mode 100644 index 00000000..9b867682 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_v17258e9ab7f5388c5e3cc6aaba8474f00.tex @@ -0,0 +1 @@ +_set_TLBEntry_v1 : (register(TLBEntry), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_valida29af220299133e11c38510f27092e5d.tex b/sail_latex_mips/valz_set_tlbentry_valida29af220299133e11c38510f27092e5d.tex new file mode 100644 index 00000000..facf216e --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_valida29af220299133e11c38510f27092e5d.tex @@ -0,0 +1 @@ +_set_TLBEntry_valid : (register(TLBEntry), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentry_vpn298a5bd5fa3b51188021ac781ba6fee98.tex b/sail_latex_mips/valz_set_tlbentry_vpn298a5bd5fa3b51188021ac781ba6fee98.tex new file mode 100644 index 00000000..d318d805 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentry_vpn298a5bd5fa3b51188021ac781ba6fee98.tex @@ -0,0 +1 @@ +_set_TLBEntry_vpn2 : (register(TLBEntry), bitvector(27, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryhireg_asid321161cd55126c8938237eb466aaf985.tex b/sail_latex_mips/valz_set_tlbentryhireg_asid321161cd55126c8938237eb466aaf985.tex new file mode 100644 index 00000000..85172b8b --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryhireg_asid321161cd55126c8938237eb466aaf985.tex @@ -0,0 +1 @@ +_set_TLBEntryHiReg_ASID : (register(TLBEntryHiReg), bitvector(8, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryhireg_bits830f40aea8b421a1ac74662681c59991.tex b/sail_latex_mips/valz_set_tlbentryhireg_bits830f40aea8b421a1ac74662681c59991.tex new file mode 100644 index 00000000..2cb44379 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryhireg_bits830f40aea8b421a1ac74662681c59991.tex @@ -0,0 +1 @@ +_set_TLBEntryHiReg_bits : (register(TLBEntryHiReg), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryhireg_clgkf7b384835e909bb74e4373c5c929ab4a.tex b/sail_latex_mips/valz_set_tlbentryhireg_clgkf7b384835e909bb74e4373c5c929ab4a.tex new file mode 100644 index 00000000..c03159e0 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryhireg_clgkf7b384835e909bb74e4373c5c929ab4a.tex @@ -0,0 +1 @@ +_set_TLBEntryHiReg_CLGK : (register(TLBEntryHiReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryhireg_clgse8c691628327ecea822d37b3003caf39.tex b/sail_latex_mips/valz_set_tlbentryhireg_clgse8c691628327ecea822d37b3003caf39.tex new file mode 100644 index 00000000..e012192e --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryhireg_clgse8c691628327ecea822d37b3003caf39.tex @@ -0,0 +1 @@ +_set_TLBEntryHiReg_CLGS : (register(TLBEntryHiReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryhireg_clgua9dab1e5d85bccd1023c42cf9f9bc70a.tex b/sail_latex_mips/valz_set_tlbentryhireg_clgua9dab1e5d85bccd1023c42cf9f9bc70a.tex new file mode 100644 index 00000000..ef0fa901 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryhireg_clgua9dab1e5d85bccd1023c42cf9f9bc70a.tex @@ -0,0 +1 @@ +_set_TLBEntryHiReg_CLGU : (register(TLBEntryHiReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryhireg_rdbcd78e9049138ceacd56be71478b061.tex b/sail_latex_mips/valz_set_tlbentryhireg_rdbcd78e9049138ceacd56be71478b061.tex new file mode 100644 index 00000000..dd04affd --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryhireg_rdbcd78e9049138ceacd56be71478b061.tex @@ -0,0 +1 @@ +_set_TLBEntryHiReg_R : (register(TLBEntryHiReg), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryhireg_vpn2ea6ff2e6ee98b0eaf79e756b606dd7f7.tex b/sail_latex_mips/valz_set_tlbentryhireg_vpn2ea6ff2e6ee98b0eaf79e756b606dd7f7.tex new file mode 100644 index 00000000..e5d9572b --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryhireg_vpn2ea6ff2e6ee98b0eaf79e756b606dd7f7.tex @@ -0,0 +1 @@ +_set_TLBEntryHiReg_VPN2 : (register(TLBEntryHiReg), bitvector(27, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryloreg_bits87cab4acff2760983bfddd23367d445c.tex b/sail_latex_mips/valz_set_tlbentryloreg_bits87cab4acff2760983bfddd23367d445c.tex new file mode 100644 index 00000000..1ac7bbe2 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryloreg_bits87cab4acff2760983bfddd23367d445c.tex @@ -0,0 +1 @@ +_set_TLBEntryLoReg_bits : (register(TLBEntryLoReg), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryloreg_c08e3096dbb8171c7d2a2c6b6c853e622.tex b/sail_latex_mips/valz_set_tlbentryloreg_c08e3096dbb8171c7d2a2c6b6c853e622.tex new file mode 100644 index 00000000..8cd0071d --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryloreg_c08e3096dbb8171c7d2a2c6b6c853e622.tex @@ -0,0 +1 @@ +_set_TLBEntryLoReg_C : (register(TLBEntryLoReg), bitvector(3, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryloreg_capl4afafd253b55dd9505958742ee8cb6f7.tex b/sail_latex_mips/valz_set_tlbentryloreg_capl4afafd253b55dd9505958742ee8cb6f7.tex new file mode 100644 index 00000000..cecc432f --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryloreg_capl4afafd253b55dd9505958742ee8cb6f7.tex @@ -0,0 +1 @@ +_set_TLBEntryLoReg_CapL : (register(TLBEntryLoReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryloreg_caplg3dd41e627a6f13d73dc55778a444e440.tex b/sail_latex_mips/valz_set_tlbentryloreg_caplg3dd41e627a6f13d73dc55778a444e440.tex new file mode 100644 index 00000000..67b53b1a --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryloreg_caplg3dd41e627a6f13d73dc55778a444e440.tex @@ -0,0 +1 @@ +_set_TLBEntryLoReg_CapLG : (register(TLBEntryLoReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryloreg_caps9a042f9111a8f78fcfe31c8c94e92925.tex b/sail_latex_mips/valz_set_tlbentryloreg_caps9a042f9111a8f78fcfe31c8c94e92925.tex new file mode 100644 index 00000000..7a1879f9 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryloreg_caps9a042f9111a8f78fcfe31c8c94e92925.tex @@ -0,0 +1 @@ +_set_TLBEntryLoReg_CapS : (register(TLBEntryLoReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryloreg_d04572c2344c6e87906ebf8c78d44671a.tex b/sail_latex_mips/valz_set_tlbentryloreg_d04572c2344c6e87906ebf8c78d44671a.tex new file mode 100644 index 00000000..c435b156 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryloreg_d04572c2344c6e87906ebf8c78d44671a.tex @@ -0,0 +1 @@ +_set_TLBEntryLoReg_D : (register(TLBEntryLoReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryloreg_g81ecbc57653a1477c15cea1541c708f3.tex b/sail_latex_mips/valz_set_tlbentryloreg_g81ecbc57653a1477c15cea1541c708f3.tex new file mode 100644 index 00000000..84b76225 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryloreg_g81ecbc57653a1477c15cea1541c708f3.tex @@ -0,0 +1 @@ +_set_TLBEntryLoReg_G : (register(TLBEntryLoReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryloreg_pfn6136b1f7a14537cfb91196ba247d881e.tex b/sail_latex_mips/valz_set_tlbentryloreg_pfn6136b1f7a14537cfb91196ba247d881e.tex new file mode 100644 index 00000000..d714a810 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryloreg_pfn6136b1f7a14537cfb91196ba247d881e.tex @@ -0,0 +1 @@ +_set_TLBEntryLoReg_PFN : (register(TLBEntryLoReg), bitvector(24, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_tlbentryloreg_v479a48bad10c13e1834cb43c00f02400.tex b/sail_latex_mips/valz_set_tlbentryloreg_v479a48bad10c13e1834cb43c00f02400.tex new file mode 100644 index 00000000..01663124 --- /dev/null +++ b/sail_latex_mips/valz_set_tlbentryloreg_v479a48bad10c13e1834cb43c00f02400.tex @@ -0,0 +1 @@ +_set_TLBEntryLoReg_V : (register(TLBEntryLoReg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_xcontextreg_bitsa93b9f55af87e5c9507e10f4f90444f6.tex b/sail_latex_mips/valz_set_xcontextreg_bitsa93b9f55af87e5c9507e10f4f90444f6.tex new file mode 100644 index 00000000..a489f4a3 --- /dev/null +++ b/sail_latex_mips/valz_set_xcontextreg_bitsa93b9f55af87e5c9507e10f4f90444f6.tex @@ -0,0 +1 @@ +_set_XContextReg_bits : (register(XContextReg), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_xcontextreg_xbadvpn2b3e73a92b43f1a839bc59b518dda6dc3.tex b/sail_latex_mips/valz_set_xcontextreg_xbadvpn2b3e73a92b43f1a839bc59b518dda6dc3.tex new file mode 100644 index 00000000..b05356ff --- /dev/null +++ b/sail_latex_mips/valz_set_xcontextreg_xbadvpn2b3e73a92b43f1a839bc59b518dda6dc3.tex @@ -0,0 +1 @@ +_set_XContextReg_XBadVPN2 : (register(XContextReg), bitvector(27, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_xcontextreg_xptebase1de10092cc0e6fbd31d9a47e20069af7.tex b/sail_latex_mips/valz_set_xcontextreg_xptebase1de10092cc0e6fbd31d9a47e20069af7.tex new file mode 100644 index 00000000..5773fbf2 --- /dev/null +++ b/sail_latex_mips/valz_set_xcontextreg_xptebase1de10092cc0e6fbd31d9a47e20069af7.tex @@ -0,0 +1 @@ +_set_XContextReg_XPTEBase : (register(XContextReg), bitvector(31, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_set_xcontextreg_xr0085c3da7716883767dbf111c432fb50.tex b/sail_latex_mips/valz_set_xcontextreg_xr0085c3da7716883767dbf111c432fb50.tex new file mode 100644 index 00000000..709a5b9a --- /dev/null +++ b/sail_latex_mips/valz_set_xcontextreg_xr0085c3da7716883767dbf111c432fb50.tex @@ -0,0 +1 @@ +_set_XContextReg_XR : (register(XContextReg), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valz_shl1b261f5995acb90d475c10ee0cdbc12ce.tex b/sail_latex_mips/valz_shl1b261f5995acb90d475c10ee0cdbc12ce.tex new file mode 100644 index 00000000..0c0d1c19 --- /dev/null +++ b/sail_latex_mips/valz_shl1b261f5995acb90d475c10ee0cdbc12ce.tex @@ -0,0 +1 @@ +_shl1 : forall ('n : Int), (0 <= 'n & 'n <= 3). (int(1), int('n)) -> {|1, 2, 4, 8|} \ No newline at end of file diff --git a/sail_latex_mips/valz_shl32469ae968a52f81e1a28aeacf7e2d496b.tex b/sail_latex_mips/valz_shl32469ae968a52f81e1a28aeacf7e2d496b.tex new file mode 100644 index 00000000..eab4d671 --- /dev/null +++ b/sail_latex_mips/valz_shl32469ae968a52f81e1a28aeacf7e2d496b.tex @@ -0,0 +1 @@ +_shl32 : forall ('n : Int), 'n in {0, 1}. (int(32), int('n)) -> {|32, 64|} \ No newline at end of file diff --git a/sail_latex_mips/valz_shl8e01c74b934d4c323501a597baa8e6f73.tex b/sail_latex_mips/valz_shl8e01c74b934d4c323501a597baa8e6f73.tex new file mode 100644 index 00000000..1c3bf9d3 --- /dev/null +++ b/sail_latex_mips/valz_shl8e01c74b934d4c323501a597baa8e6f73.tex @@ -0,0 +1 @@ +_shl8 : forall ('n : Int), (0 <= 'n & 'n <= 3). (int(8), int('n)) -> {|8, 16, 32, 64|} \ No newline at end of file diff --git a/sail_latex_mips/valz_shl_int86f4e1bc3609625860bc16734d7f2614.tex b/sail_latex_mips/valz_shl_int86f4e1bc3609625860bc16734d7f2614.tex new file mode 100644 index 00000000..840e98cf --- /dev/null +++ b/sail_latex_mips/valz_shl_int86f4e1bc3609625860bc16734d7f2614.tex @@ -0,0 +1 @@ +_shl_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valz_shr328ec48e4bcaebfdbf5c374b77ca7b535b.tex b/sail_latex_mips/valz_shr328ec48e4bcaebfdbf5c374b77ca7b535b.tex new file mode 100644 index 00000000..ddf9ffa7 --- /dev/null +++ b/sail_latex_mips/valz_shr328ec48e4bcaebfdbf5c374b77ca7b535b.tex @@ -0,0 +1 @@ +_shr32 : forall ('n : Int), (0 <= 'n & 'n <= 31). (int('n), int(1)) -> {'m, (0 <= 'm & 'm <= 15). int('m)} \ No newline at end of file diff --git a/sail_latex_mips/valz_shr_int34025c843d841a08930cb64bf99a1693.tex b/sail_latex_mips/valz_shr_int34025c843d841a08930cb64bf99a1693.tex new file mode 100644 index 00000000..ed0e407c --- /dev/null +++ b/sail_latex_mips/valz_shr_int34025c843d841a08930cb64bf99a1693.tex @@ -0,0 +1 @@ +_shr_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valz_tmod_int_positive6f0621d972182279e90a43c082e50c10.tex b/sail_latex_mips/valz_tmod_int_positive6f0621d972182279e90a43c082e50c10.tex new file mode 100644 index 00000000..f187115a --- /dev/null +++ b/sail_latex_mips/valz_tmod_int_positive6f0621d972182279e90a43c082e50c10.tex @@ -0,0 +1 @@ +_tmod_int_positive : forall ('n : Int), 'n >= 1. (int, int('n)) -> nat \ No newline at end of file diff --git a/sail_latex_mips/valz_tmod_inta2984ba6dbfa10758476d9b3b7f62560.tex b/sail_latex_mips/valz_tmod_inta2984ba6dbfa10758476d9b3b7f62560.tex new file mode 100644 index 00000000..c861b270 --- /dev/null +++ b/sail_latex_mips/valz_tmod_inta2984ba6dbfa10758476d9b3b7f62560.tex @@ -0,0 +1 @@ +_tmod_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valz_update_capcausereg_bitsc7253ec47586740f3fd1b2b2e8cdca5a.tex b/sail_latex_mips/valz_update_capcausereg_bitsc7253ec47586740f3fd1b2b2e8cdca5a.tex new file mode 100644 index 00000000..8b9a3c05 --- /dev/null +++ b/sail_latex_mips/valz_update_capcausereg_bitsc7253ec47586740f3fd1b2b2e8cdca5a.tex @@ -0,0 +1 @@ +_update_CapCauseReg_bits : (CapCauseReg, bitvector(16, dec)) -> CapCauseReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_capcausereg_exccode831973db379fbc7fc58a62fad27d1e48.tex b/sail_latex_mips/valz_update_capcausereg_exccode831973db379fbc7fc58a62fad27d1e48.tex new file mode 100644 index 00000000..02e64f09 --- /dev/null +++ b/sail_latex_mips/valz_update_capcausereg_exccode831973db379fbc7fc58a62fad27d1e48.tex @@ -0,0 +1 @@ +_update_CapCauseReg_ExcCode : (CapCauseReg, bitvector(8, dec)) -> CapCauseReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_capcausereg_regnumdfccaf21a7f843566ceea99a5e20969b.tex b/sail_latex_mips/valz_update_capcausereg_regnumdfccaf21a7f843566ceea99a5e20969b.tex new file mode 100644 index 00000000..c70fdecf --- /dev/null +++ b/sail_latex_mips/valz_update_capcausereg_regnumdfccaf21a7f843566ceea99a5e20969b.tex @@ -0,0 +1 @@ +_update_CapCauseReg_RegNum : (CapCauseReg, bitvector(8, dec)) -> CapCauseReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_causereg_bd1341a4dd118508995044054898160c72.tex b/sail_latex_mips/valz_update_causereg_bd1341a4dd118508995044054898160c72.tex new file mode 100644 index 00000000..0177babd --- /dev/null +++ b/sail_latex_mips/valz_update_causereg_bd1341a4dd118508995044054898160c72.tex @@ -0,0 +1 @@ +_update_CauseReg_BD : (CauseReg, bitvector(1, dec)) -> CauseReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_causereg_bitsb063e035edb33b2c5f07e3df533bf948.tex b/sail_latex_mips/valz_update_causereg_bitsb063e035edb33b2c5f07e3df533bf948.tex new file mode 100644 index 00000000..9eb07bd8 --- /dev/null +++ b/sail_latex_mips/valz_update_causereg_bitsb063e035edb33b2c5f07e3df533bf948.tex @@ -0,0 +1 @@ +_update_CauseReg_bits : (CauseReg, bitvector(32, dec)) -> CauseReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_causereg_ce99326d83612c25800d2accb6a9f4508b.tex b/sail_latex_mips/valz_update_causereg_ce99326d83612c25800d2accb6a9f4508b.tex new file mode 100644 index 00000000..0dbcd6b8 --- /dev/null +++ b/sail_latex_mips/valz_update_causereg_ce99326d83612c25800d2accb6a9f4508b.tex @@ -0,0 +1 @@ +_update_CauseReg_CE : (CauseReg, bitvector(2, dec)) -> CauseReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_causereg_exccodeead7d2a9d8ec53cba96f7218e48b092f.tex b/sail_latex_mips/valz_update_causereg_exccodeead7d2a9d8ec53cba96f7218e48b092f.tex new file mode 100644 index 00000000..b0ec25f5 --- /dev/null +++ b/sail_latex_mips/valz_update_causereg_exccodeead7d2a9d8ec53cba96f7218e48b092f.tex @@ -0,0 +1 @@ +_update_CauseReg_ExcCode : (CauseReg, bitvector(5, dec)) -> CauseReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_causereg_ipa7f214043fd244817e8d07b9783a4f4a.tex b/sail_latex_mips/valz_update_causereg_ipa7f214043fd244817e8d07b9783a4f4a.tex new file mode 100644 index 00000000..d7a7086b --- /dev/null +++ b/sail_latex_mips/valz_update_causereg_ipa7f214043fd244817e8d07b9783a4f4a.tex @@ -0,0 +1 @@ +_update_CauseReg_IP : (CauseReg, bitvector(8, dec)) -> CauseReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_causereg_iv2946c68395a7cdb8aa45a8668627e8d5.tex b/sail_latex_mips/valz_update_causereg_iv2946c68395a7cdb8aa45a8668627e8d5.tex new file mode 100644 index 00000000..2c83550a --- /dev/null +++ b/sail_latex_mips/valz_update_causereg_iv2946c68395a7cdb8aa45a8668627e8d5.tex @@ -0,0 +1 @@ +_update_CauseReg_IV : (CauseReg, bitvector(1, dec)) -> CauseReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_causereg_wpd6c4c462af40f65a59a3ad83cf90ff81.tex b/sail_latex_mips/valz_update_causereg_wpd6c4c462af40f65a59a3ad83cf90ff81.tex new file mode 100644 index 00000000..43286b8e --- /dev/null +++ b/sail_latex_mips/valz_update_causereg_wpd6c4c462af40f65a59a3ad83cf90ff81.tex @@ -0,0 +1 @@ +_update_CauseReg_WP : (CauseReg, bitvector(1, dec)) -> CauseReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_contextreg_badvpn29dd1d7ba9698b94e95d082c38f1eab84.tex b/sail_latex_mips/valz_update_contextreg_badvpn29dd1d7ba9698b94e95d082c38f1eab84.tex new file mode 100644 index 00000000..9ecd4c87 --- /dev/null +++ b/sail_latex_mips/valz_update_contextreg_badvpn29dd1d7ba9698b94e95d082c38f1eab84.tex @@ -0,0 +1 @@ +_update_ContextReg_BadVPN2 : (ContextReg, bitvector(19, dec)) -> ContextReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_contextreg_bits0df4e43fe9f13b5860f4e758b65c124c.tex b/sail_latex_mips/valz_update_contextreg_bits0df4e43fe9f13b5860f4e758b65c124c.tex new file mode 100644 index 00000000..1b4a7a3d --- /dev/null +++ b/sail_latex_mips/valz_update_contextreg_bits0df4e43fe9f13b5860f4e758b65c124c.tex @@ -0,0 +1 @@ +_update_ContextReg_bits : (ContextReg, bitvector(64, dec)) -> ContextReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_contextreg_ptebase3ac56067efaf9c4426e60d8d4f9e4827.tex b/sail_latex_mips/valz_update_contextreg_ptebase3ac56067efaf9c4426e60d8d4f9e4827.tex new file mode 100644 index 00000000..1f99adb2 --- /dev/null +++ b/sail_latex_mips/valz_update_contextreg_ptebase3ac56067efaf9c4426e60d8d4f9e4827.tex @@ -0,0 +1 @@ +_update_ContextReg_PTEBase : (ContextReg, bitvector(41, dec)) -> ContextReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_statusreg_bevf40892c6f5ac28088b99d5e42005036f.tex b/sail_latex_mips/valz_update_statusreg_bevf40892c6f5ac28088b99d5e42005036f.tex new file mode 100644 index 00000000..0dc20a28 --- /dev/null +++ b/sail_latex_mips/valz_update_statusreg_bevf40892c6f5ac28088b99d5e42005036f.tex @@ -0,0 +1 @@ +_update_StatusReg_BEV : (StatusReg, bitvector(1, dec)) -> StatusReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_statusreg_bits61d5a9099337276f42cc674faed1b40b.tex b/sail_latex_mips/valz_update_statusreg_bits61d5a9099337276f42cc674faed1b40b.tex new file mode 100644 index 00000000..621dde7d --- /dev/null +++ b/sail_latex_mips/valz_update_statusreg_bits61d5a9099337276f42cc674faed1b40b.tex @@ -0,0 +1 @@ +_update_StatusReg_bits : (StatusReg, bitvector(32, dec)) -> StatusReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_statusreg_cud909b281d996784c876e6637f1435066.tex b/sail_latex_mips/valz_update_statusreg_cud909b281d996784c876e6637f1435066.tex new file mode 100644 index 00000000..d772bdec --- /dev/null +++ b/sail_latex_mips/valz_update_statusreg_cud909b281d996784c876e6637f1435066.tex @@ -0,0 +1 @@ +_update_StatusReg_CU : (StatusReg, bitvector(4, dec)) -> StatusReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_statusreg_erl22b56df06e65c8a9f44b830961367edf.tex b/sail_latex_mips/valz_update_statusreg_erl22b56df06e65c8a9f44b830961367edf.tex new file mode 100644 index 00000000..b3762679 --- /dev/null +++ b/sail_latex_mips/valz_update_statusreg_erl22b56df06e65c8a9f44b830961367edf.tex @@ -0,0 +1 @@ +_update_StatusReg_ERL : (StatusReg, bitvector(1, dec)) -> StatusReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_statusreg_exl680444bbc9dec1a34d9a0cf68ddde857.tex b/sail_latex_mips/valz_update_statusreg_exl680444bbc9dec1a34d9a0cf68ddde857.tex new file mode 100644 index 00000000..ee5026e5 --- /dev/null +++ b/sail_latex_mips/valz_update_statusreg_exl680444bbc9dec1a34d9a0cf68ddde857.tex @@ -0,0 +1 @@ +_update_StatusReg_EXL : (StatusReg, bitvector(1, dec)) -> StatusReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_statusreg_ie8d238c97ac1693bad8b62c61215ea16b.tex b/sail_latex_mips/valz_update_statusreg_ie8d238c97ac1693bad8b62c61215ea16b.tex new file mode 100644 index 00000000..f9888b7e --- /dev/null +++ b/sail_latex_mips/valz_update_statusreg_ie8d238c97ac1693bad8b62c61215ea16b.tex @@ -0,0 +1 @@ +_update_StatusReg_IE : (StatusReg, bitvector(1, dec)) -> StatusReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_statusreg_im62a68e4b88599a5038c9e71290e24f71.tex b/sail_latex_mips/valz_update_statusreg_im62a68e4b88599a5038c9e71290e24f71.tex new file mode 100644 index 00000000..9ff6ae30 --- /dev/null +++ b/sail_latex_mips/valz_update_statusreg_im62a68e4b88599a5038c9e71290e24f71.tex @@ -0,0 +1 @@ +_update_StatusReg_IM : (StatusReg, bitvector(8, dec)) -> StatusReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_statusreg_ksu27debd025189cf0d6d72638cd289acac.tex b/sail_latex_mips/valz_update_statusreg_ksu27debd025189cf0d6d72638cd289acac.tex new file mode 100644 index 00000000..ca04afce --- /dev/null +++ b/sail_latex_mips/valz_update_statusreg_ksu27debd025189cf0d6d72638cd289acac.tex @@ -0,0 +1 @@ +_update_StatusReg_KSU : (StatusReg, bitvector(2, dec)) -> StatusReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_statusreg_kx6234e7159a5ec0749a63e66e635b26d6.tex b/sail_latex_mips/valz_update_statusreg_kx6234e7159a5ec0749a63e66e635b26d6.tex new file mode 100644 index 00000000..7e690a31 --- /dev/null +++ b/sail_latex_mips/valz_update_statusreg_kx6234e7159a5ec0749a63e66e635b26d6.tex @@ -0,0 +1 @@ +_update_StatusReg_KX : (StatusReg, bitvector(1, dec)) -> StatusReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_statusreg_sx78cadd5bf0c1cae59c3b60a27b83c481.tex b/sail_latex_mips/valz_update_statusreg_sx78cadd5bf0c1cae59c3b60a27b83c481.tex new file mode 100644 index 00000000..3ee21e91 --- /dev/null +++ b/sail_latex_mips/valz_update_statusreg_sx78cadd5bf0c1cae59c3b60a27b83c481.tex @@ -0,0 +1 @@ +_update_StatusReg_SX : (StatusReg, bitvector(1, dec)) -> StatusReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_statusreg_ux17bbf86e5756c6d01048f3d473eb1430.tex b/sail_latex_mips/valz_update_statusreg_ux17bbf86e5756c6d01048f3d473eb1430.tex new file mode 100644 index 00000000..65f669b5 --- /dev/null +++ b/sail_latex_mips/valz_update_statusreg_ux17bbf86e5756c6d01048f3d473eb1430.tex @@ -0,0 +1 @@ +_update_StatusReg_UX : (StatusReg, bitvector(1, dec)) -> StatusReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_asidb6b5d414b15c08829bdf389448396971.tex b/sail_latex_mips/valz_update_tlbentry_asidb6b5d414b15c08829bdf389448396971.tex new file mode 100644 index 00000000..3df016de --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_asidb6b5d414b15c08829bdf389448396971.tex @@ -0,0 +1 @@ +_update_TLBEntry_asid : (TLBEntry, bitvector(8, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_bits1b789098a048790468b840f08f48d3fd.tex b/sail_latex_mips/valz_update_tlbentry_bits1b789098a048790468b840f08f48d3fd.tex new file mode 100644 index 00000000..17a57d4d --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_bits1b789098a048790468b840f08f48d3fd.tex @@ -0,0 +1 @@ +_update_TLBEntry_bits : (TLBEntry, bitvector(119, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_c0fd743ae9faadd346132a35189c2cd342.tex b/sail_latex_mips/valz_update_tlbentry_c0fd743ae9faadd346132a35189c2cd342.tex new file mode 100644 index 00000000..02723c3a --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_c0fd743ae9faadd346132a35189c2cd342.tex @@ -0,0 +1 @@ +_update_TLBEntry_c0 : (TLBEntry, bitvector(3, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_c1cecd7e476eb8d0b72ce187ac166f9443.tex b/sail_latex_mips/valz_update_tlbentry_c1cecd7e476eb8d0b72ce187ac166f9443.tex new file mode 100644 index 00000000..591c5101 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_c1cecd7e476eb8d0b72ce187ac166f9443.tex @@ -0,0 +1 @@ +_update_TLBEntry_c1 : (TLBEntry, bitvector(3, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_capl074805e4eecd0f55c383efab32c765007.tex b/sail_latex_mips/valz_update_tlbentry_capl074805e4eecd0f55c383efab32c765007.tex new file mode 100644 index 00000000..4953cbbc --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_capl074805e4eecd0f55c383efab32c765007.tex @@ -0,0 +1 @@ +_update_TLBEntry_capl0 : (TLBEntry, bitvector(1, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_capl1c69e2b6d6e2466af2769ae5f3b3a70cc.tex b/sail_latex_mips/valz_update_tlbentry_capl1c69e2b6d6e2466af2769ae5f3b3a70cc.tex new file mode 100644 index 00000000..51ca9b50 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_capl1c69e2b6d6e2466af2769ae5f3b3a70cc.tex @@ -0,0 +1 @@ +_update_TLBEntry_capl1 : (TLBEntry, bitvector(1, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_caplg0fc35336b4b0b170579cd74d3e9641075.tex b/sail_latex_mips/valz_update_tlbentry_caplg0fc35336b4b0b170579cd74d3e9641075.tex new file mode 100644 index 00000000..f0bdc077 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_caplg0fc35336b4b0b170579cd74d3e9641075.tex @@ -0,0 +1 @@ +_update_TLBEntry_caplg0 : (TLBEntry, bitvector(1, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_caplg14ef4abe6e9dfaa69cfd379930a53acda.tex b/sail_latex_mips/valz_update_tlbentry_caplg14ef4abe6e9dfaa69cfd379930a53acda.tex new file mode 100644 index 00000000..f70d0756 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_caplg14ef4abe6e9dfaa69cfd379930a53acda.tex @@ -0,0 +1 @@ +_update_TLBEntry_caplg1 : (TLBEntry, bitvector(1, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_caps0a1dc65eb853d421759956887a045ad45.tex b/sail_latex_mips/valz_update_tlbentry_caps0a1dc65eb853d421759956887a045ad45.tex new file mode 100644 index 00000000..3c4d5f36 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_caps0a1dc65eb853d421759956887a045ad45.tex @@ -0,0 +1 @@ +_update_TLBEntry_caps0 : (TLBEntry, bitvector(1, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_caps1c9648031a984830f7ce96fdd1e079e8a.tex b/sail_latex_mips/valz_update_tlbentry_caps1c9648031a984830f7ce96fdd1e079e8a.tex new file mode 100644 index 00000000..3475b248 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_caps1c9648031a984830f7ce96fdd1e079e8a.tex @@ -0,0 +1 @@ +_update_TLBEntry_caps1 : (TLBEntry, bitvector(1, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_d0e93ed2ed33cbc5c5f202914a237de360.tex b/sail_latex_mips/valz_update_tlbentry_d0e93ed2ed33cbc5c5f202914a237de360.tex new file mode 100644 index 00000000..83103c1a --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_d0e93ed2ed33cbc5c5f202914a237de360.tex @@ -0,0 +1 @@ +_update_TLBEntry_d0 : (TLBEntry, bitvector(1, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_d101453a2a5999d48250bdc176e05e3f5e.tex b/sail_latex_mips/valz_update_tlbentry_d101453a2a5999d48250bdc176e05e3f5e.tex new file mode 100644 index 00000000..098e7329 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_d101453a2a5999d48250bdc176e05e3f5e.tex @@ -0,0 +1 @@ +_update_TLBEntry_d1 : (TLBEntry, bitvector(1, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_g20222955c3b959c9ff4647404fedbfef.tex b/sail_latex_mips/valz_update_tlbentry_g20222955c3b959c9ff4647404fedbfef.tex new file mode 100644 index 00000000..3dce325d --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_g20222955c3b959c9ff4647404fedbfef.tex @@ -0,0 +1 @@ +_update_TLBEntry_g : (TLBEntry, bitvector(1, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_pagemaskbb0f8a2bdd38e987c7a2e2b338e3b75f.tex b/sail_latex_mips/valz_update_tlbentry_pagemaskbb0f8a2bdd38e987c7a2e2b338e3b75f.tex new file mode 100644 index 00000000..fea8fe1e --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_pagemaskbb0f8a2bdd38e987c7a2e2b338e3b75f.tex @@ -0,0 +1 @@ +_update_TLBEntry_pagemask : (TLBEntry, bitvector(16, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_pfn0d99c89c789d61112a1918a4433ab048d.tex b/sail_latex_mips/valz_update_tlbentry_pfn0d99c89c789d61112a1918a4433ab048d.tex new file mode 100644 index 00000000..4dc89bd6 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_pfn0d99c89c789d61112a1918a4433ab048d.tex @@ -0,0 +1 @@ +_update_TLBEntry_pfn0 : (TLBEntry, bitvector(24, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_pfn190b25e06aacd9ec8fd6e571532937e98.tex b/sail_latex_mips/valz_update_tlbentry_pfn190b25e06aacd9ec8fd6e571532937e98.tex new file mode 100644 index 00000000..29dbfc7b --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_pfn190b25e06aacd9ec8fd6e571532937e98.tex @@ -0,0 +1 @@ +_update_TLBEntry_pfn1 : (TLBEntry, bitvector(24, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_r9a41b411e6ff9bebfc4172a28c5dbdee.tex b/sail_latex_mips/valz_update_tlbentry_r9a41b411e6ff9bebfc4172a28c5dbdee.tex new file mode 100644 index 00000000..9063f4b0 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_r9a41b411e6ff9bebfc4172a28c5dbdee.tex @@ -0,0 +1 @@ +_update_TLBEntry_r : (TLBEntry, bitvector(2, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_v042084d06370a232031d509c4cb3b4ff6.tex b/sail_latex_mips/valz_update_tlbentry_v042084d06370a232031d509c4cb3b4ff6.tex new file mode 100644 index 00000000..15293099 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_v042084d06370a232031d509c4cb3b4ff6.tex @@ -0,0 +1 @@ +_update_TLBEntry_v0 : (TLBEntry, bitvector(1, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_v163c9fd3074a5ad5e092a27e64a5fb55e.tex b/sail_latex_mips/valz_update_tlbentry_v163c9fd3074a5ad5e092a27e64a5fb55e.tex new file mode 100644 index 00000000..e0f97ad2 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_v163c9fd3074a5ad5e092a27e64a5fb55e.tex @@ -0,0 +1 @@ +_update_TLBEntry_v1 : (TLBEntry, bitvector(1, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_valid7dd0569211421c835b46068a7bd34a5a.tex b/sail_latex_mips/valz_update_tlbentry_valid7dd0569211421c835b46068a7bd34a5a.tex new file mode 100644 index 00000000..150d4a83 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_valid7dd0569211421c835b46068a7bd34a5a.tex @@ -0,0 +1 @@ +_update_TLBEntry_valid : (TLBEntry, bitvector(1, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentry_vpn24c1efd2008ce4086cb554186508bd63a.tex b/sail_latex_mips/valz_update_tlbentry_vpn24c1efd2008ce4086cb554186508bd63a.tex new file mode 100644 index 00000000..34ea9de6 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentry_vpn24c1efd2008ce4086cb554186508bd63a.tex @@ -0,0 +1 @@ +_update_TLBEntry_vpn2 : (TLBEntry, bitvector(27, dec)) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryhireg_asidb7a77785e726aa2fce0d7e93a9630b8d.tex b/sail_latex_mips/valz_update_tlbentryhireg_asidb7a77785e726aa2fce0d7e93a9630b8d.tex new file mode 100644 index 00000000..d6563eaf --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryhireg_asidb7a77785e726aa2fce0d7e93a9630b8d.tex @@ -0,0 +1 @@ +_update_TLBEntryHiReg_ASID : (TLBEntryHiReg, bitvector(8, dec)) -> TLBEntryHiReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryhireg_bitsa10c10b31a1704b4bbb65828e235738a.tex b/sail_latex_mips/valz_update_tlbentryhireg_bitsa10c10b31a1704b4bbb65828e235738a.tex new file mode 100644 index 00000000..a6544f0b --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryhireg_bitsa10c10b31a1704b4bbb65828e235738a.tex @@ -0,0 +1 @@ +_update_TLBEntryHiReg_bits : (TLBEntryHiReg, bitvector(64, dec)) -> TLBEntryHiReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryhireg_clgk635276a161c10c3ac2a0c446f734a32a.tex b/sail_latex_mips/valz_update_tlbentryhireg_clgk635276a161c10c3ac2a0c446f734a32a.tex new file mode 100644 index 00000000..cdfec10c --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryhireg_clgk635276a161c10c3ac2a0c446f734a32a.tex @@ -0,0 +1 @@ +_update_TLBEntryHiReg_CLGK : (TLBEntryHiReg, bitvector(1, dec)) -> TLBEntryHiReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryhireg_clgs2a321d8cde93a407a0a48e78b11f8b02.tex b/sail_latex_mips/valz_update_tlbentryhireg_clgs2a321d8cde93a407a0a48e78b11f8b02.tex new file mode 100644 index 00000000..9b679ec2 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryhireg_clgs2a321d8cde93a407a0a48e78b11f8b02.tex @@ -0,0 +1 @@ +_update_TLBEntryHiReg_CLGS : (TLBEntryHiReg, bitvector(1, dec)) -> TLBEntryHiReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryhireg_clgub94d1691569cf6e49d6171ef49e4c86b.tex b/sail_latex_mips/valz_update_tlbentryhireg_clgub94d1691569cf6e49d6171ef49e4c86b.tex new file mode 100644 index 00000000..986891c5 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryhireg_clgub94d1691569cf6e49d6171ef49e4c86b.tex @@ -0,0 +1 @@ +_update_TLBEntryHiReg_CLGU : (TLBEntryHiReg, bitvector(1, dec)) -> TLBEntryHiReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryhireg_r06c8b0ecb6f68f0d45d384366fd03e59.tex b/sail_latex_mips/valz_update_tlbentryhireg_r06c8b0ecb6f68f0d45d384366fd03e59.tex new file mode 100644 index 00000000..31c69d45 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryhireg_r06c8b0ecb6f68f0d45d384366fd03e59.tex @@ -0,0 +1 @@ +_update_TLBEntryHiReg_R : (TLBEntryHiReg, bitvector(2, dec)) -> TLBEntryHiReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryhireg_vpn2a5a0eafdc27da5a10c42b69c9f6e759f.tex b/sail_latex_mips/valz_update_tlbentryhireg_vpn2a5a0eafdc27da5a10c42b69c9f6e759f.tex new file mode 100644 index 00000000..78a41451 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryhireg_vpn2a5a0eafdc27da5a10c42b69c9f6e759f.tex @@ -0,0 +1 @@ +_update_TLBEntryHiReg_VPN2 : (TLBEntryHiReg, bitvector(27, dec)) -> TLBEntryHiReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryloreg_bits6c2ff3e7af20e35dd45bf50ea68f8ec8.tex b/sail_latex_mips/valz_update_tlbentryloreg_bits6c2ff3e7af20e35dd45bf50ea68f8ec8.tex new file mode 100644 index 00000000..53aeb647 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryloreg_bits6c2ff3e7af20e35dd45bf50ea68f8ec8.tex @@ -0,0 +1 @@ +_update_TLBEntryLoReg_bits : (TLBEntryLoReg, bitvector(64, dec)) -> TLBEntryLoReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryloreg_c720c1b6d680bdb0fc873d902ab9e3854.tex b/sail_latex_mips/valz_update_tlbentryloreg_c720c1b6d680bdb0fc873d902ab9e3854.tex new file mode 100644 index 00000000..745131b5 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryloreg_c720c1b6d680bdb0fc873d902ab9e3854.tex @@ -0,0 +1 @@ +_update_TLBEntryLoReg_C : (TLBEntryLoReg, bitvector(3, dec)) -> TLBEntryLoReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryloreg_caplaaf9a58642f1ed8b0226e13fd635715e.tex b/sail_latex_mips/valz_update_tlbentryloreg_caplaaf9a58642f1ed8b0226e13fd635715e.tex new file mode 100644 index 00000000..dbd954f0 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryloreg_caplaaf9a58642f1ed8b0226e13fd635715e.tex @@ -0,0 +1 @@ +_update_TLBEntryLoReg_CapL : (TLBEntryLoReg, bitvector(1, dec)) -> TLBEntryLoReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryloreg_caplg74d3e13531d835cb013f9516a2c860b5.tex b/sail_latex_mips/valz_update_tlbentryloreg_caplg74d3e13531d835cb013f9516a2c860b5.tex new file mode 100644 index 00000000..e4d78b2d --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryloreg_caplg74d3e13531d835cb013f9516a2c860b5.tex @@ -0,0 +1 @@ +_update_TLBEntryLoReg_CapLG : (TLBEntryLoReg, bitvector(1, dec)) -> TLBEntryLoReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryloreg_caps3f8fe0c48d5361758dc7ef0fa4a84990.tex b/sail_latex_mips/valz_update_tlbentryloreg_caps3f8fe0c48d5361758dc7ef0fa4a84990.tex new file mode 100644 index 00000000..aea80207 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryloreg_caps3f8fe0c48d5361758dc7ef0fa4a84990.tex @@ -0,0 +1 @@ +_update_TLBEntryLoReg_CapS : (TLBEntryLoReg, bitvector(1, dec)) -> TLBEntryLoReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryloreg_ddadb2d338250cae60e5c96dc8dc2f118.tex b/sail_latex_mips/valz_update_tlbentryloreg_ddadb2d338250cae60e5c96dc8dc2f118.tex new file mode 100644 index 00000000..d6c8d5dc --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryloreg_ddadb2d338250cae60e5c96dc8dc2f118.tex @@ -0,0 +1 @@ +_update_TLBEntryLoReg_D : (TLBEntryLoReg, bitvector(1, dec)) -> TLBEntryLoReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryloreg_gcbb777750a024300d463c99664060b0e.tex b/sail_latex_mips/valz_update_tlbentryloreg_gcbb777750a024300d463c99664060b0e.tex new file mode 100644 index 00000000..0772e833 --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryloreg_gcbb777750a024300d463c99664060b0e.tex @@ -0,0 +1 @@ +_update_TLBEntryLoReg_G : (TLBEntryLoReg, bitvector(1, dec)) -> TLBEntryLoReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryloreg_pfn09564a0f7205bf65c965dda38fd2c7b1.tex b/sail_latex_mips/valz_update_tlbentryloreg_pfn09564a0f7205bf65c965dda38fd2c7b1.tex new file mode 100644 index 00000000..1642740e --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryloreg_pfn09564a0f7205bf65c965dda38fd2c7b1.tex @@ -0,0 +1 @@ +_update_TLBEntryLoReg_PFN : (TLBEntryLoReg, bitvector(24, dec)) -> TLBEntryLoReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_tlbentryloreg_v464571bc28acefba62b6c96884a2ac5e.tex b/sail_latex_mips/valz_update_tlbentryloreg_v464571bc28acefba62b6c96884a2ac5e.tex new file mode 100644 index 00000000..e9accb3f --- /dev/null +++ b/sail_latex_mips/valz_update_tlbentryloreg_v464571bc28acefba62b6c96884a2ac5e.tex @@ -0,0 +1 @@ +_update_TLBEntryLoReg_V : (TLBEntryLoReg, bitvector(1, dec)) -> TLBEntryLoReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_xcontextreg_bitsdb6e2157fa47608aa5622abf4b763efc.tex b/sail_latex_mips/valz_update_xcontextreg_bitsdb6e2157fa47608aa5622abf4b763efc.tex new file mode 100644 index 00000000..c81d7fc4 --- /dev/null +++ b/sail_latex_mips/valz_update_xcontextreg_bitsdb6e2157fa47608aa5622abf4b763efc.tex @@ -0,0 +1 @@ +_update_XContextReg_bits : (XContextReg, bitvector(64, dec)) -> XContextReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_xcontextreg_xbadvpn271be6846d4092b3dba3bc6c81857b1b9.tex b/sail_latex_mips/valz_update_xcontextreg_xbadvpn271be6846d4092b3dba3bc6c81857b1b9.tex new file mode 100644 index 00000000..5e71bb3e --- /dev/null +++ b/sail_latex_mips/valz_update_xcontextreg_xbadvpn271be6846d4092b3dba3bc6c81857b1b9.tex @@ -0,0 +1 @@ +_update_XContextReg_XBadVPN2 : (XContextReg, bitvector(27, dec)) -> XContextReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_xcontextreg_xptebase729a58cc2ea0bab68cb0c93124af9313.tex b/sail_latex_mips/valz_update_xcontextreg_xptebase729a58cc2ea0bab68cb0c93124af9313.tex new file mode 100644 index 00000000..92c8703b --- /dev/null +++ b/sail_latex_mips/valz_update_xcontextreg_xptebase729a58cc2ea0bab68cb0c93124af9313.tex @@ -0,0 +1 @@ +_update_XContextReg_XPTEBase : (XContextReg, bitvector(31, dec)) -> XContextReg \ No newline at end of file diff --git a/sail_latex_mips/valz_update_xcontextreg_xrfb95bbc02275c03eb4bc1562a36f7671.tex b/sail_latex_mips/valz_update_xcontextreg_xrfb95bbc02275c03eb4bc1562a36f7671.tex new file mode 100644 index 00000000..6e1515b0 --- /dev/null +++ b/sail_latex_mips/valz_update_xcontextreg_xrfb95bbc02275c03eb4bc1562a36f7671.tex @@ -0,0 +1 @@ +_update_XContextReg_XR : (XContextReg, bitvector(2, dec)) -> XContextReg \ No newline at end of file diff --git a/sail_latex_mips/valzabs_int_atom414063313cc5ac5d9a742f9c8a111704.tex b/sail_latex_mips/valzabs_int_atom414063313cc5ac5d9a742f9c8a111704.tex new file mode 100644 index 00000000..bafc4750 --- /dev/null +++ b/sail_latex_mips/valzabs_int_atom414063313cc5ac5d9a742f9c8a111704.tex @@ -0,0 +1 @@ +abs_int_atom : forall ('n : Int). int('n) -> int(abs('n)) \ No newline at end of file diff --git a/sail_latex_mips/valzabs_int_plainb54aa4afeed2c86b519a464eb2e4c77c.tex b/sail_latex_mips/valzabs_int_plainb54aa4afeed2c86b519a464eb2e4c77c.tex new file mode 100644 index 00000000..327250de --- /dev/null +++ b/sail_latex_mips/valzabs_int_plainb54aa4afeed2c86b519a464eb2e4c77c.tex @@ -0,0 +1 @@ +abs_int_plain : int -> int \ No newline at end of file diff --git a/sail_latex_mips/valzaccesslevel_of_num43666996140cb5f36631de9d7d4748b1.tex b/sail_latex_mips/valzaccesslevel_of_num43666996140cb5f36631de9d7d4748b1.tex new file mode 100644 index 00000000..a8fa3788 --- /dev/null +++ b/sail_latex_mips/valzaccesslevel_of_num43666996140cb5f36631de9d7d4748b1.tex @@ -0,0 +1 @@ +AccessLevel_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> AccessLevel \ No newline at end of file diff --git a/sail_latex_mips/valzadd_atomd34efc9e611b6d3b6757e17f4932b12b.tex b/sail_latex_mips/valzadd_atomd34efc9e611b6d3b6757e17f4932b12b.tex new file mode 100644 index 00000000..baf41c80 --- /dev/null +++ b/sail_latex_mips/valzadd_atomd34efc9e611b6d3b6757e17f4932b12b.tex @@ -0,0 +1 @@ +add_atom : forall ('n 'm : Int). (int('n), int('m)) -> int('n + 'm) \ No newline at end of file diff --git a/sail_latex_mips/valzadd_bits24373ffc11f289d5bb648df2f4f41b25.tex b/sail_latex_mips/valzadd_bits24373ffc11f289d5bb648df2f4f41b25.tex new file mode 100644 index 00000000..1e6dd7d0 --- /dev/null +++ b/sail_latex_mips/valzadd_bits24373ffc11f289d5bb648df2f4f41b25.tex @@ -0,0 +1 @@ +add_bits : forall ('n : Int). (bits('n), bits('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzadd_bits_inta5424052402522ff4653275c899f7543.tex b/sail_latex_mips/valzadd_bits_inta5424052402522ff4653275c899f7543.tex new file mode 100644 index 00000000..b08b96d2 --- /dev/null +++ b/sail_latex_mips/valzadd_bits_inta5424052402522ff4653275c899f7543.tex @@ -0,0 +1 @@ +add_bits_int : forall ('n : Int). (bits('n), int) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzadd_intb17710be4fd02ace68d83b9dba907034.tex b/sail_latex_mips/valzadd_intb17710be4fd02ace68d83b9dba907034.tex new file mode 100644 index 00000000..67398a30 --- /dev/null +++ b/sail_latex_mips/valzadd_intb17710be4fd02ace68d83b9dba907034.tex @@ -0,0 +1 @@ +add_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valzadd_range42e075ccf1451df2036e21ab04adc98a.tex b/sail_latex_mips/valzadd_range42e075ccf1451df2036e21ab04adc98a.tex new file mode 100644 index 00000000..5d8162de --- /dev/null +++ b/sail_latex_mips/valzadd_range42e075ccf1451df2036e21ab04adc98a.tex @@ -0,0 +1 @@ +add_range : forall ('n 'm 'o 'p : Int). (range('n, 'm), range('o, 'p)) -> range('n + 'o, 'm + 'p) \ No newline at end of file diff --git a/sail_latex_mips/valzadd_vec_intba4788367d6a85d666f0c19861d4bd77.tex b/sail_latex_mips/valzadd_vec_intba4788367d6a85d666f0c19861d4bd77.tex new file mode 100644 index 00000000..49606e37 --- /dev/null +++ b/sail_latex_mips/valzadd_vec_intba4788367d6a85d666f0c19861d4bd77.tex @@ -0,0 +1 @@ +add_vec_int : forall ('n : Int). (bits('n), int) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzadd_vecaede33d991aa6e29010fb4562c8ae5de.tex b/sail_latex_mips/valzadd_vecaede33d991aa6e29010fb4562c8ae5de.tex new file mode 100644 index 00000000..d4c4fb52 --- /dev/null +++ b/sail_latex_mips/valzadd_vecaede33d991aa6e29010fb4562c8ae5de.tex @@ -0,0 +1 @@ +add_vec : forall ('n : Int). (bits('n), bits('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzaddrwrapperbff37cfeb3c9276bfa58f5d99b0ca05e.tex b/sail_latex_mips/valzaddrwrapperbff37cfeb3c9276bfa58f5d99b0ca05e.tex new file mode 100644 index 00000000..90a3829d --- /dev/null +++ b/sail_latex_mips/valzaddrwrapperbff37cfeb3c9276bfa58f5d99b0ca05e.tex @@ -0,0 +1 @@ +addrWrapper : (bits(64), MemAccessType, WordType) -> bits(64) \ No newline at end of file diff --git a/sail_latex_mips/valzaddrwrapperunaligned2c4b1b84884abfd7091faab6f7aed047.tex b/sail_latex_mips/valzaddrwrapperunaligned2c4b1b84884abfd7091faab6f7aed047.tex new file mode 100644 index 00000000..0af0059d --- /dev/null +++ b/sail_latex_mips/valzaddrwrapperunaligned2c4b1b84884abfd7091faab6f7aed047.tex @@ -0,0 +1 @@ +addrWrapperUnaligned : (bits(64), MemAccessType, WordTypeUnaligned) -> (bits(64), int) \ No newline at end of file diff --git a/sail_latex_mips/valzand_bool_no_flow5d5041fa8ff689136cdc03e3a11eda3a.tex b/sail_latex_mips/valzand_bool_no_flow5d5041fa8ff689136cdc03e3a11eda3a.tex new file mode 100644 index 00000000..7de0f497 --- /dev/null +++ b/sail_latex_mips/valzand_bool_no_flow5d5041fa8ff689136cdc03e3a11eda3a.tex @@ -0,0 +1 @@ +and_bool_no_flow : (bool, bool) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzand_boola4a2cf9ccaa44106300961b15ab20e79.tex b/sail_latex_mips/valzand_boola4a2cf9ccaa44106300961b15ab20e79.tex new file mode 100644 index 00000000..1840123d --- /dev/null +++ b/sail_latex_mips/valzand_boola4a2cf9ccaa44106300961b15ab20e79.tex @@ -0,0 +1 @@ +and_bool : forall ('p 'q : Bool). (bool('p), bool('q)) -> bool(('p & 'q)) \ No newline at end of file diff --git a/sail_latex_mips/valzand_vec99be3fe45d23194b597520c9e407ad35.tex b/sail_latex_mips/valzand_vec99be3fe45d23194b597520c9e407ad35.tex new file mode 100644 index 00000000..0b8e5e04 --- /dev/null +++ b/sail_latex_mips/valzand_vec99be3fe45d23194b597520c9e407ad35.tex @@ -0,0 +1 @@ +and_vec : forall ('n : Int). (bits('n), bits('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzappend_6433ef192058d4bf5f092d6f8b6d97f4c4.tex b/sail_latex_mips/valzappend_6433ef192058d4bf5f092d6f8b6d97f4c4.tex new file mode 100644 index 00000000..eccf4152 --- /dev/null +++ b/sail_latex_mips/valzappend_6433ef192058d4bf5f092d6f8b6d97f4c4.tex @@ -0,0 +1 @@ +append_64 : forall ('n : Int). (bits('n), bits(64)) -> bits('n + 64) \ No newline at end of file diff --git a/sail_latex_mips/valzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_mips/valzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..5c3466df --- /dev/null +++ b/sail_latex_mips/valzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +assembly : ast -> string \ No newline at end of file diff --git a/sail_latex_mips/valzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex b/sail_latex_mips/valzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex new file mode 100644 index 00000000..9268010b --- /dev/null +++ b/sail_latex_mips/valzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex @@ -0,0 +1 @@ +bit_to_bool : bit -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzbits_strae053d842c21f0867dea1e830d1773cc.tex b/sail_latex_mips/valzbits_strae053d842c21f0867dea1e830d1773cc.tex new file mode 100644 index 00000000..eacc131f --- /dev/null +++ b/sail_latex_mips/valzbits_strae053d842c21f0867dea1e830d1773cc.tex @@ -0,0 +1 @@ +bits_str : forall ('n : Int). bitvector('n, dec) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzbits_to_bool40d71a119a1093f6caa36e2aa93bd193.tex b/sail_latex_mips/valzbits_to_bool40d71a119a1093f6caa36e2aa93bd193.tex new file mode 100644 index 00000000..cb81f635 --- /dev/null +++ b/sail_latex_mips/valzbits_to_bool40d71a119a1093f6caa36e2aa93bd193.tex @@ -0,0 +1 @@ +bits_to_bool : bits(1) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzbitstr0d04da018975c4776e05a9c59c2e380e.tex b/sail_latex_mips/valzbitstr0d04da018975c4776e05a9c59c2e380e.tex new file mode 100644 index 00000000..0db41781 --- /dev/null +++ b/sail_latex_mips/valzbitstr0d04da018975c4776e05a9c59c2e380e.tex @@ -0,0 +1 @@ +BitStr : forall ('n : Int). bits('n) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzbitvector_access8b584ca86770abb6b0da5ef059a02ed9.tex b/sail_latex_mips/valzbitvector_access8b584ca86770abb6b0da5ef059a02ed9.tex new file mode 100644 index 00000000..626dd0f9 --- /dev/null +++ b/sail_latex_mips/valzbitvector_access8b584ca86770abb6b0da5ef059a02ed9.tex @@ -0,0 +1 @@ +bitvector_access : forall ('n 'm : Int), (0 <= 'm & 'm < 'n). (bits('n), int('m)) -> bit \ No newline at end of file diff --git a/sail_latex_mips/valzbitvector_concat6176f8be1468d8779ee8370fd3b4a6e0.tex b/sail_latex_mips/valzbitvector_concat6176f8be1468d8779ee8370fd3b4a6e0.tex new file mode 100644 index 00000000..2fd31ec8 --- /dev/null +++ b/sail_latex_mips/valzbitvector_concat6176f8be1468d8779ee8370fd3b4a6e0.tex @@ -0,0 +1 @@ +bitvector_concat : forall ('n 'm : Int). (bits('n), bits('m)) -> bits('n + 'm) \ No newline at end of file diff --git a/sail_latex_mips/valzbitvector_lengthcd74a5cced7567d19500671e4b6e1031.tex b/sail_latex_mips/valzbitvector_lengthcd74a5cced7567d19500671e4b6e1031.tex new file mode 100644 index 00000000..1b17c963 --- /dev/null +++ b/sail_latex_mips/valzbitvector_lengthcd74a5cced7567d19500671e4b6e1031.tex @@ -0,0 +1 @@ +bitvector_length : forall ('n : Int). bits('n) -> int('n) \ No newline at end of file diff --git a/sail_latex_mips/valzbitvector_update20826799a1ff3ff40895206db0df14bb.tex b/sail_latex_mips/valzbitvector_update20826799a1ff3ff40895206db0df14bb.tex new file mode 100644 index 00000000..d6e4114f --- /dev/null +++ b/sail_latex_mips/valzbitvector_update20826799a1ff3ff40895206db0df14bb.tex @@ -0,0 +1 @@ +bitvector_update : forall ('n 'm : Int), (0 <= 'm & 'm < 'n). (bits('n), int('m), bit) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex b/sail_latex_mips/valzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex new file mode 100644 index 00000000..4299f74f --- /dev/null +++ b/sail_latex_mips/valzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex @@ -0,0 +1 @@ +bool_to_bit : bool -> bit \ No newline at end of file diff --git a/sail_latex_mips/valzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex b/sail_latex_mips/valzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex new file mode 100644 index 00000000..5707b3bd --- /dev/null +++ b/sail_latex_mips/valzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex @@ -0,0 +1 @@ +bool_to_bits : bool -> bits(1) \ No newline at end of file diff --git a/sail_latex_mips/valzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex b/sail_latex_mips/valzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex new file mode 100644 index 00000000..e687ee6d --- /dev/null +++ b/sail_latex_mips/valzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex @@ -0,0 +1 @@ +capBitsToCapability : (bool, CapBits) -> Capability \ No newline at end of file diff --git a/sail_latex_mips/valzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex b/sail_latex_mips/valzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex new file mode 100644 index 00000000..58cec3b3 --- /dev/null +++ b/sail_latex_mips/valzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex @@ -0,0 +1 @@ +capBoundsEqual : (Capability, Capability) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex b/sail_latex_mips/valzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex new file mode 100644 index 00000000..ec9c9661 --- /dev/null +++ b/sail_latex_mips/valzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex @@ -0,0 +1 @@ +CapEx_of_num : forall ('e : Int), (0 <= 'e & 'e <= 24). int('e) -> CapEx \ No newline at end of file diff --git a/sail_latex_mips/valzcapexcodee065d40e92bb99703db21c8c18bedf11.tex b/sail_latex_mips/valzcapexcodee065d40e92bb99703db21c8c18bedf11.tex new file mode 100644 index 00000000..f687a2e5 --- /dev/null +++ b/sail_latex_mips/valzcapexcodee065d40e92bb99703db21c8c18bedf11.tex @@ -0,0 +1 @@ +CapExCode : CapEx -> bits(8) \ No newline at end of file diff --git a/sail_latex_mips/valzcaptobits025010a6e8c284beecc438f72babcc70.tex b/sail_latex_mips/valzcaptobits025010a6e8c284beecc438f72babcc70.tex new file mode 100644 index 00000000..65455d39 --- /dev/null +++ b/sail_latex_mips/valzcaptobits025010a6e8c284beecc438f72babcc70.tex @@ -0,0 +1 @@ +capToBits : Capability -> bits(128) \ No newline at end of file diff --git a/sail_latex_mips/valzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex b/sail_latex_mips/valzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex new file mode 100644 index 00000000..a561615e --- /dev/null +++ b/sail_latex_mips/valzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex @@ -0,0 +1 @@ +capToMemBits : Capability -> bits(128) \ No newline at end of file diff --git a/sail_latex_mips/valzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex b/sail_latex_mips/valzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex new file mode 100644 index 00000000..3fc4869b --- /dev/null +++ b/sail_latex_mips/valzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex @@ -0,0 +1 @@ +capToString : (Capability, bool) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzcast_unit_vec98272b7fb05a703213e98272ec5486c8.tex b/sail_latex_mips/valzcast_unit_vec98272b7fb05a703213e98272ec5486c8.tex new file mode 100644 index 00000000..139f5981 --- /dev/null +++ b/sail_latex_mips/valzcast_unit_vec98272b7fb05a703213e98272ec5486c8.tex @@ -0,0 +1 @@ +cast_unit_vec : bit -> bits(1) \ No newline at end of file diff --git a/sail_latex_mips/valzcheckcp0accesse535c637cac3118020cdac54870326df.tex b/sail_latex_mips/valzcheckcp0accesse535c637cac3118020cdac54870326df.tex new file mode 100644 index 00000000..173f0a4e --- /dev/null +++ b/sail_latex_mips/valzcheckcp0accesse535c637cac3118020cdac54870326df.tex @@ -0,0 +1 @@ +checkCP0Access : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzcheckcp0accesshook3dae675d70bdcddbd36c77cdbf07a44f.tex b/sail_latex_mips/valzcheckcp0accesshook3dae675d70bdcddbd36c77cdbf07a44f.tex new file mode 100644 index 00000000..81b6de08 --- /dev/null +++ b/sail_latex_mips/valzcheckcp0accesshook3dae675d70bdcddbd36c77cdbf07a44f.tex @@ -0,0 +1 @@ +checkCP0AccessHook : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzcheckcp2usable5e31fa40adaccfcd7791aafdb7b9d2de.tex b/sail_latex_mips/valzcheckcp2usable5e31fa40adaccfcd7791aafdb7b9d2de.tex new file mode 100644 index 00000000..2c5951b5 --- /dev/null +++ b/sail_latex_mips/valzcheckcp2usable5e31fa40adaccfcd7791aafdb7b9d2de.tex @@ -0,0 +1 @@ +checkCP2usable : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzcheckddcperms07cb3f56bec26901cdf69beab49d8910.tex b/sail_latex_mips/valzcheckddcperms07cb3f56bec26901cdf69beab49d8910.tex new file mode 100644 index 00000000..17ccbb58 --- /dev/null +++ b/sail_latex_mips/valzcheckddcperms07cb3f56bec26901cdf69beab49d8910.tex @@ -0,0 +1 @@ +checkDDCPerms : (Capability, MemAccessType) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex b/sail_latex_mips/valzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex new file mode 100644 index 00000000..4a2d1164 --- /dev/null +++ b/sail_latex_mips/valzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex @@ -0,0 +1 @@ +ClearRegSet_of_num : forall ('e : Int), (0 <= 'e & 'e <= 3). int('e) -> ClearRegSet \ No newline at end of file diff --git a/sail_latex_mips/valzcomparee9b34cffaaa4473cdff7ece5c1a05374.tex b/sail_latex_mips/valzcomparee9b34cffaaa4473cdff7ece5c1a05374.tex new file mode 100644 index 00000000..60e9837b --- /dev/null +++ b/sail_latex_mips/valzcomparee9b34cffaaa4473cdff7ece5c1a05374.tex @@ -0,0 +1 @@ +compare : (Comparison, bits(64), bits(64)) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzcomparison_of_num2a18f2d9a572dd906b510535c629d4f0.tex b/sail_latex_mips/valzcomparison_of_num2a18f2d9a572dd906b510535c629d4f0.tex new file mode 100644 index 00000000..81509434 --- /dev/null +++ b/sail_latex_mips/valzcomparison_of_num2a18f2d9a572dd906b510535c629d4f0.tex @@ -0,0 +1 @@ +Comparison_of_num : forall ('e : Int), (0 <= 'e & 'e <= 7). int('e) -> Comparison \ No newline at end of file diff --git a/sail_latex_mips/valzconcat_str366019c233188ef65ab3d1f977f04112.tex b/sail_latex_mips/valzconcat_str366019c233188ef65ab3d1f977f04112.tex new file mode 100644 index 00000000..4a38f2a2 --- /dev/null +++ b/sail_latex_mips/valzconcat_str366019c233188ef65ab3d1f977f04112.tex @@ -0,0 +1 @@ +concat_str : (string, string) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex b/sail_latex_mips/valzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex new file mode 100644 index 00000000..2daf03b4 --- /dev/null +++ b/sail_latex_mips/valzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex @@ -0,0 +1 @@ +concat_str_bits : forall ('n : Int). (string, bitvector('n, dec)) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex b/sail_latex_mips/valzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex new file mode 100644 index 00000000..0654a682 --- /dev/null +++ b/sail_latex_mips/valzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex @@ -0,0 +1 @@ +concat_str_dec : (string, int) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzcount_leading_zzeros315ae28f559df1d42a7d2ca4cfff2905.tex b/sail_latex_mips/valzcount_leading_zzeros315ae28f559df1d42a7d2ca4cfff2905.tex new file mode 100644 index 00000000..9036ecb3 --- /dev/null +++ b/sail_latex_mips/valzcount_leading_zzeros315ae28f559df1d42a7d2ca4cfff2905.tex @@ -0,0 +1 @@ +count_leading_zeros : forall ('N : Int), 'N >= 1. bits('N) -> {'n, (0 <= 'n & 'n <= 'N). int('n)} \ No newline at end of file diff --git a/sail_latex_mips/valzcp2_next_pc33094c95220fdc4b0a67b83ac21fc047.tex b/sail_latex_mips/valzcp2_next_pc33094c95220fdc4b0a67b83ac21fc047.tex new file mode 100644 index 00000000..ada7ed6a --- /dev/null +++ b/sail_latex_mips/valzcp2_next_pc33094c95220fdc4b0a67b83ac21fc047.tex @@ -0,0 +1 @@ +cp2_next_pc : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex b/sail_latex_mips/valzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex new file mode 100644 index 00000000..18dbe4c8 --- /dev/null +++ b/sail_latex_mips/valzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex @@ -0,0 +1 @@ +CPtrCmpOp_of_num : forall ('e : Int), (0 <= 'e & 'e <= 7). int('e) -> CPtrCmpOp \ No newline at end of file diff --git a/sail_latex_mips/valzdec_str7582ccea1482759c248b1f1ac9f6ae63.tex b/sail_latex_mips/valzdec_str7582ccea1482759c248b1f1ac9f6ae63.tex new file mode 100644 index 00000000..ed6cf9db --- /dev/null +++ b/sail_latex_mips/valzdec_str7582ccea1482759c248b1f1ac9f6ae63.tex @@ -0,0 +1 @@ +dec_str : int -> string \ No newline at end of file diff --git a/sail_latex_mips/valzdecode_failure_of_numcefdc025bb5d8d74839d8f9f65058d32.tex b/sail_latex_mips/valzdecode_failure_of_numcefdc025bb5d8d74839d8f9f65058d32.tex new file mode 100644 index 00000000..61c759d7 --- /dev/null +++ b/sail_latex_mips/valzdecode_failure_of_numcefdc025bb5d8d74839d8f9f65058d32.tex @@ -0,0 +1 @@ +decode_failure_of_num : forall ('e : Int), (0 <= 'e & 'e <= 3). int('e) -> decode_failure \ No newline at end of file diff --git a/sail_latex_mips/valzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_mips/valzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..68a11e48 --- /dev/null +++ b/sail_latex_mips/valzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +decode : bits(32) -> option(ast) \ No newline at end of file diff --git a/sail_latex_mips/valzdump_cp2_statee501e37d7b82b621f6ff3cd1f225d5f1.tex b/sail_latex_mips/valzdump_cp2_statee501e37d7b82b621f6ff3cd1f225d5f1.tex new file mode 100644 index 00000000..ee0ffe99 --- /dev/null +++ b/sail_latex_mips/valzdump_cp2_statee501e37d7b82b621f6ff3cd1f225d5f1.tex @@ -0,0 +1 @@ +dump_cp2_state : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzediv_int5aaf4d3d5a3d15a7aebaf90d3bfb6650.tex b/sail_latex_mips/valzediv_int5aaf4d3d5a3d15a7aebaf90d3bfb6650.tex new file mode 100644 index 00000000..c61a86f5 --- /dev/null +++ b/sail_latex_mips/valzediv_int5aaf4d3d5a3d15a7aebaf90d3bfb6650.tex @@ -0,0 +1 @@ +ediv_int : forall ('n 'm : Int). (int('n), int('m)) -> int(div('n, 'm)) \ No newline at end of file diff --git a/sail_latex_mips/valzemod_int8e3d74b3b6a72e24e6bd03570d8e21ba.tex b/sail_latex_mips/valzemod_int8e3d74b3b6a72e24e6bd03570d8e21ba.tex new file mode 100644 index 00000000..f1269583 --- /dev/null +++ b/sail_latex_mips/valzemod_int8e3d74b3b6a72e24e6bd03570d8e21ba.tex @@ -0,0 +1 @@ +emod_int : forall ('n 'm : Int). (int('n), int('m)) -> int(mod('n, 'm)) \ No newline at end of file diff --git a/sail_latex_mips/valzeq_anything99dff1d931070d33dac5c755eae24439.tex b/sail_latex_mips/valzeq_anything99dff1d931070d33dac5c755eae24439.tex new file mode 100644 index 00000000..85bdae62 --- /dev/null +++ b/sail_latex_mips/valzeq_anything99dff1d931070d33dac5c755eae24439.tex @@ -0,0 +1 @@ +eq_anything : forall ('a : Type). ('a, 'a) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzeq_bit250da3631e266dec9fd09db78de2c816f.tex b/sail_latex_mips/valzeq_bit250da3631e266dec9fd09db78de2c816f.tex new file mode 100644 index 00000000..51dd0051 --- /dev/null +++ b/sail_latex_mips/valzeq_bit250da3631e266dec9fd09db78de2c816f.tex @@ -0,0 +1 @@ +eq_bit2 : (bit, bit) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzeq_bit7182cc37406e2c0d4c1e739a98e248ea.tex b/sail_latex_mips/valzeq_bit7182cc37406e2c0d4c1e739a98e248ea.tex new file mode 100644 index 00000000..6ed18ab3 --- /dev/null +++ b/sail_latex_mips/valzeq_bit7182cc37406e2c0d4c1e739a98e248ea.tex @@ -0,0 +1 @@ +eq_bit : (bit, bit) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzeq_bits886ce7cf3ec93a28308e8d4e9d63f4be.tex b/sail_latex_mips/valzeq_bits886ce7cf3ec93a28308e8d4e9d63f4be.tex new file mode 100644 index 00000000..afb10eb0 --- /dev/null +++ b/sail_latex_mips/valzeq_bits886ce7cf3ec93a28308e8d4e9d63f4be.tex @@ -0,0 +1 @@ +eq_bits : forall ('n : Int). (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzeq_bool0e93587306381c3f984dc7cea6ae190d.tex b/sail_latex_mips/valzeq_bool0e93587306381c3f984dc7cea6ae190d.tex new file mode 100644 index 00000000..d5ef476b --- /dev/null +++ b/sail_latex_mips/valzeq_bool0e93587306381c3f984dc7cea6ae190d.tex @@ -0,0 +1 @@ +eq_bool : (bool, bool) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzeq_int364a98dbf8a9faa70e666cce41d8c1aa.tex b/sail_latex_mips/valzeq_int364a98dbf8a9faa70e666cce41d8c1aa.tex new file mode 100644 index 00000000..7d3ae0f1 --- /dev/null +++ b/sail_latex_mips/valzeq_int364a98dbf8a9faa70e666cce41d8c1aa.tex @@ -0,0 +1 @@ +eq_int : forall ('n 'm : Int). (int('n), int('m)) -> bool('n == 'm) \ No newline at end of file diff --git a/sail_latex_mips/valzeq_string75dfa57c0476ae3f43f8e55ffe51a116.tex b/sail_latex_mips/valzeq_string75dfa57c0476ae3f43f8e55ffe51a116.tex new file mode 100644 index 00000000..d6db7aeb --- /dev/null +++ b/sail_latex_mips/valzeq_string75dfa57c0476ae3f43f8e55ffe51a116.tex @@ -0,0 +1 @@ +eq_string : (string, string) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzeq_unit996f84433ac0995f4aadfca5b68cd358.tex b/sail_latex_mips/valzeq_unit996f84433ac0995f4aadfca5b68cd358.tex new file mode 100644 index 00000000..3df558bf --- /dev/null +++ b/sail_latex_mips/valzeq_unit996f84433ac0995f4aadfca5b68cd358.tex @@ -0,0 +1 @@ +eq_unit : (unit, unit) -> bool(true) \ No newline at end of file diff --git a/sail_latex_mips/valzerethook15fc4e665e3e6cc75e445b15faa26b37.tex b/sail_latex_mips/valzerethook15fc4e665e3e6cc75e445b15faa26b37.tex new file mode 100644 index 00000000..dde7fbca --- /dev/null +++ b/sail_latex_mips/valzerethook15fc4e665e3e6cc75e445b15faa26b37.tex @@ -0,0 +1 @@ +ERETHook : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzexception_of_num7e2e38eb3f1c380a425392cb53ad450c.tex b/sail_latex_mips/valzexception_of_num7e2e38eb3f1c380a425392cb53ad450c.tex new file mode 100644 index 00000000..b6a907fe --- /dev/null +++ b/sail_latex_mips/valzexception_of_num7e2e38eb3f1c380a425392cb53ad450c.tex @@ -0,0 +1 @@ +Exception_of_num : forall ('e : Int), (0 <= 'e & 'e <= 18). int('e) -> Exception \ No newline at end of file diff --git a/sail_latex_mips/valzexceptioncodef7807000fba49ff7759f4a4cbdf3d902.tex b/sail_latex_mips/valzexceptioncodef7807000fba49ff7759f4a4cbdf3d902.tex new file mode 100644 index 00000000..5b223d3b --- /dev/null +++ b/sail_latex_mips/valzexceptioncodef7807000fba49ff7759f4a4cbdf3d902.tex @@ -0,0 +1 @@ +ExceptionCode : Exception -> bits(5) \ No newline at end of file diff --git a/sail_latex_mips/valzexceptionvectorbase2dabb9cbc70df89c064ff6ef9c281b30.tex b/sail_latex_mips/valzexceptionvectorbase2dabb9cbc70df89c064ff6ef9c281b30.tex new file mode 100644 index 00000000..e1ffae0d --- /dev/null +++ b/sail_latex_mips/valzexceptionvectorbase2dabb9cbc70df89c064ff6ef9c281b30.tex @@ -0,0 +1 @@ +exceptionVectorBase : unit -> bits(64) \ No newline at end of file diff --git a/sail_latex_mips/valzexceptionvectoroffset5c95f15ec5e635d417858fb601d0a766.tex b/sail_latex_mips/valzexceptionvectoroffset5c95f15ec5e635d417858fb601d0a766.tex new file mode 100644 index 00000000..e76f6010 --- /dev/null +++ b/sail_latex_mips/valzexceptionvectoroffset5c95f15ec5e635d417858fb601d0a766.tex @@ -0,0 +1 @@ +exceptionVectorOffset : Exception -> bits(12) \ No newline at end of file diff --git a/sail_latex_mips/valzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_mips/valzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..18397e8e --- /dev/null +++ b/sail_latex_mips/valzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1 @@ +execute : ast -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzexecute_branch311b9f285cc52d66c683fa3ecaee2918.tex b/sail_latex_mips/valzexecute_branch311b9f285cc52d66c683fa3ecaee2918.tex new file mode 100644 index 00000000..f60140dd --- /dev/null +++ b/sail_latex_mips/valzexecute_branch311b9f285cc52d66c683fa3ecaee2918.tex @@ -0,0 +1 @@ +execute_branch : bits(64) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzexecute_branch_mipse0f90fc63954012c1f04b5f4841d0bbb.tex b/sail_latex_mips/valzexecute_branch_mipse0f90fc63954012c1f04b5f4841d0bbb.tex new file mode 100644 index 00000000..df1c3696 --- /dev/null +++ b/sail_latex_mips/valzexecute_branch_mipse0f90fc63954012c1f04b5f4841d0bbb.tex @@ -0,0 +1 @@ +execute_branch_mips : bits(64) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzexecute_branch_pcc8b6a454691b25b72e01ecd191988286f.tex b/sail_latex_mips/valzexecute_branch_pcc8b6a454691b25b72e01ecd191988286f.tex new file mode 100644 index 00000000..55e55cd9 --- /dev/null +++ b/sail_latex_mips/valzexecute_branch_pcc8b6a454691b25b72e01ecd191988286f.tex @@ -0,0 +1 @@ +execute_branch_pcc : Capability -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzextendload386a20971b3dbdcd10ee9b8b44e2c2f7.tex b/sail_latex_mips/valzextendload386a20971b3dbdcd10ee9b8b44e2c2f7.tex new file mode 100644 index 00000000..37505dad --- /dev/null +++ b/sail_latex_mips/valzextendload386a20971b3dbdcd10ee9b8b44e2c2f7.tex @@ -0,0 +1 @@ +extendLoad : forall ('sz : Int), 'sz <= 64. (bits('sz), bool) -> bits(64) \ No newline at end of file diff --git a/sail_latex_mips/valzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex b/sail_latex_mips/valzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex new file mode 100644 index 00000000..4dbd41ef --- /dev/null +++ b/sail_latex_mips/valzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex @@ -0,0 +1 @@ +fdiv_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valzfmod_int7e215ca2b888f4e92201959fd40958a5.tex b/sail_latex_mips/valzfmod_int7e215ca2b888f4e92201959fd40958a5.tex new file mode 100644 index 00000000..4a0c1688 --- /dev/null +++ b/sail_latex_mips/valzfmod_int7e215ca2b888f4e92201959fd40958a5.tex @@ -0,0 +1 @@ +fmod_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valzget_cp0epc947f8a8e6dac5833e002f1ea37a79de2.tex b/sail_latex_mips/valzget_cp0epc947f8a8e6dac5833e002f1ea37a79de2.tex new file mode 100644 index 00000000..6b891ca2 --- /dev/null +++ b/sail_latex_mips/valzget_cp0epc947f8a8e6dac5833e002f1ea37a79de2.tex @@ -0,0 +1 @@ +get_CP0EPC : unit -> bits(64) \ No newline at end of file diff --git a/sail_latex_mips/valzget_cp0errorepc1188335ff3decc7c914ce1ba3a7904dd.tex b/sail_latex_mips/valzget_cp0errorepc1188335ff3decc7c914ce1ba3a7904dd.tex new file mode 100644 index 00000000..54c86496 --- /dev/null +++ b/sail_latex_mips/valzget_cp0errorepc1188335ff3decc7c914ce1ba3a7904dd.tex @@ -0,0 +1 @@ +get_CP0ErrorEPC : unit -> bits(64) \ No newline at end of file diff --git a/sail_latex_mips/valzget_slice_int3c313e973dc436aff309f66096377164.tex b/sail_latex_mips/valzget_slice_int3c313e973dc436aff309f66096377164.tex new file mode 100644 index 00000000..2401b150 --- /dev/null +++ b/sail_latex_mips/valzget_slice_int3c313e973dc436aff309f66096377164.tex @@ -0,0 +1 @@ +get_slice_int : forall ('w : Int). (int('w), int, int) -> bits('w) \ No newline at end of file diff --git a/sail_latex_mips/valzget_time_ns76b2aba2c98dedb9e71b52add49642c4.tex b/sail_latex_mips/valzget_time_ns76b2aba2c98dedb9e71b52add49642c4.tex new file mode 100644 index 00000000..60c13e38 --- /dev/null +++ b/sail_latex_mips/valzget_time_ns76b2aba2c98dedb9e71b52add49642c4.tex @@ -0,0 +1 @@ +get_time_ns : unit -> int \ No newline at end of file diff --git a/sail_latex_mips/valzgetaccesslevel40127125b18eb6336d48aa4638317128.tex b/sail_latex_mips/valzgetaccesslevel40127125b18eb6336d48aa4638317128.tex new file mode 100644 index 00000000..8773d82b --- /dev/null +++ b/sail_latex_mips/valzgetaccesslevel40127125b18eb6336d48aa4638317128.tex @@ -0,0 +1 @@ +getAccessLevel : unit -> AccessLevel \ No newline at end of file diff --git a/sail_latex_mips/valzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex b/sail_latex_mips/valzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex new file mode 100644 index 00000000..98faa22e --- /dev/null +++ b/sail_latex_mips/valzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex @@ -0,0 +1 @@ +getCapBase : Capability -> uint64 \ No newline at end of file diff --git a/sail_latex_mips/valzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex b/sail_latex_mips/valzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex new file mode 100644 index 00000000..2566f933 --- /dev/null +++ b/sail_latex_mips/valzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex @@ -0,0 +1 @@ +getCapBounds : Capability -> (uint64, CapLen) \ No newline at end of file diff --git a/sail_latex_mips/valzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex b/sail_latex_mips/valzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex new file mode 100644 index 00000000..0778cbbe --- /dev/null +++ b/sail_latex_mips/valzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex @@ -0,0 +1 @@ +getCapCursor : Capability -> uint64 \ No newline at end of file diff --git a/sail_latex_mips/valzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex b/sail_latex_mips/valzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex new file mode 100644 index 00000000..01e62954 --- /dev/null +++ b/sail_latex_mips/valzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex @@ -0,0 +1 @@ +getCapFlags : Capability -> CFlags \ No newline at end of file diff --git a/sail_latex_mips/valzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex b/sail_latex_mips/valzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex new file mode 100644 index 00000000..5b1496f2 --- /dev/null +++ b/sail_latex_mips/valzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex @@ -0,0 +1 @@ +getCapHardPerms : Capability -> bits(12) \ No newline at end of file diff --git a/sail_latex_mips/valzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex b/sail_latex_mips/valzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex new file mode 100644 index 00000000..4405c72e --- /dev/null +++ b/sail_latex_mips/valzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex @@ -0,0 +1 @@ +getCapLength : Capability -> CapLen \ No newline at end of file diff --git a/sail_latex_mips/valzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex b/sail_latex_mips/valzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex new file mode 100644 index 00000000..a57f6f1e --- /dev/null +++ b/sail_latex_mips/valzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex @@ -0,0 +1 @@ +getCapOffset : Capability -> uint64 \ No newline at end of file diff --git a/sail_latex_mips/valzgetcapperms6aed04c1602f540bb5d604425f922d92.tex b/sail_latex_mips/valzgetcapperms6aed04c1602f540bb5d604425f922d92.tex new file mode 100644 index 00000000..b6033b7a --- /dev/null +++ b/sail_latex_mips/valzgetcapperms6aed04c1602f540bb5d604425f922d92.tex @@ -0,0 +1 @@ +getCapPerms : Capability -> bits(31) \ No newline at end of file diff --git a/sail_latex_mips/valzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex b/sail_latex_mips/valzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex new file mode 100644 index 00000000..b9aaae07 --- /dev/null +++ b/sail_latex_mips/valzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex @@ -0,0 +1 @@ +getCapTop : Capability -> CapLen \ No newline at end of file diff --git a/sail_latex_mips/valzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex b/sail_latex_mips/valzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex new file mode 100644 index 00000000..793feb8a --- /dev/null +++ b/sail_latex_mips/valzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex @@ -0,0 +1 @@ +getRepresentableAlignmentMask : bits(64) -> bits(64) \ No newline at end of file diff --git a/sail_latex_mips/valzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex b/sail_latex_mips/valzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex new file mode 100644 index 00000000..d274b522 --- /dev/null +++ b/sail_latex_mips/valzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex @@ -0,0 +1 @@ +getRepresentableLength : bits(64) -> bits(64) \ No newline at end of file diff --git a/sail_latex_mips/valzgrantsaccess1c25b864354b7175e1d8d7ec4e5e27b6.tex b/sail_latex_mips/valzgrantsaccess1c25b864354b7175e1d8d7ec4e5e27b6.tex new file mode 100644 index 00000000..3d54414d --- /dev/null +++ b/sail_latex_mips/valzgrantsaccess1c25b864354b7175e1d8d7ec4e5e27b6.tex @@ -0,0 +1 @@ +grantsAccess : (AccessLevel, AccessLevel) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzgt_intef94a8c66f39b1f715cb72941ed95921.tex b/sail_latex_mips/valzgt_intef94a8c66f39b1f715cb72941ed95921.tex new file mode 100644 index 00000000..fd5e09b1 --- /dev/null +++ b/sail_latex_mips/valzgt_intef94a8c66f39b1f715cb72941ed95921.tex @@ -0,0 +1 @@ +gt_int : forall ('n 'm : Int). (int('n), int('m)) -> bool('n > 'm) \ No newline at end of file diff --git a/sail_latex_mips/valzgteq_inte32033a8d137f46d187455cff7dbe40e.tex b/sail_latex_mips/valzgteq_inte32033a8d137f46d187455cff7dbe40e.tex new file mode 100644 index 00000000..236c5717 --- /dev/null +++ b/sail_latex_mips/valzgteq_inte32033a8d137f46d187455cff7dbe40e.tex @@ -0,0 +1 @@ +gteq_int : forall ('n 'm : Int). (int('n), int('m)) -> bool('n >= 'm) \ No newline at end of file diff --git a/sail_latex_mips/valzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex b/sail_latex_mips/valzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex new file mode 100644 index 00000000..a0375115 --- /dev/null +++ b/sail_latex_mips/valzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex @@ -0,0 +1 @@ +hasReservedOType : Capability -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzhex_str47c735e2941ef5c87d4f7502a5e92a2a.tex b/sail_latex_mips/valzhex_str47c735e2941ef5c87d4f7502a5e92a2a.tex new file mode 100644 index 00000000..cb910794 --- /dev/null +++ b/sail_latex_mips/valzhex_str47c735e2941ef5c87d4f7502a5e92a2a.tex @@ -0,0 +1 @@ +hex_str : int -> string \ No newline at end of file diff --git a/sail_latex_mips/valzinccapoffsetc4735d243650e78b90bacb6efb419260.tex b/sail_latex_mips/valzinccapoffsetc4735d243650e78b90bacb6efb419260.tex new file mode 100644 index 00000000..b8f637bc --- /dev/null +++ b/sail_latex_mips/valzinccapoffsetc4735d243650e78b90bacb6efb419260.tex @@ -0,0 +1 @@ +incCapOffset : (Capability, bits(64)) -> (bool, Capability) \ No newline at end of file diff --git a/sail_latex_mips/valzincrementcp0count9449093588dc2365295e37dd55af742d.tex b/sail_latex_mips/valzincrementcp0count9449093588dc2365295e37dd55af742d.tex new file mode 100644 index 00000000..f493f955 --- /dev/null +++ b/sail_latex_mips/valzincrementcp0count9449093588dc2365295e37dd55af742d.tex @@ -0,0 +1 @@ +incrementCP0Count : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzinit_cp0_state82b3d81150b612dca26217241b94da87.tex b/sail_latex_mips/valzinit_cp0_state82b3d81150b612dca26217241b94da87.tex new file mode 100644 index 00000000..70ed3c7f --- /dev/null +++ b/sail_latex_mips/valzinit_cp0_state82b3d81150b612dca26217241b94da87.tex @@ -0,0 +1 @@ +init_cp0_state : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzinit_cp2_state7056c424b16f2ae2f851216ae32427b0.tex b/sail_latex_mips/valzinit_cp2_state7056c424b16f2ae2f851216ae32427b0.tex new file mode 100644 index 00000000..5d6afc6b --- /dev/null +++ b/sail_latex_mips/valzinit_cp2_state7056c424b16f2ae2f851216ae32427b0.tex @@ -0,0 +1 @@ +init_cp2_state : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzint_of_accessleveld511598513a474f4d799d64651770863.tex b/sail_latex_mips/valzint_of_accessleveld511598513a474f4d799d64651770863.tex new file mode 100644 index 00000000..745ca2d5 --- /dev/null +++ b/sail_latex_mips/valzint_of_accessleveld511598513a474f4d799d64651770863.tex @@ -0,0 +1 @@ +int_of_AccessLevel : AccessLevel -> {|0, 1, 2|} \ No newline at end of file diff --git a/sail_latex_mips/valzint_powerb0c5fc1a9fb0852260414607a93aeae6.tex b/sail_latex_mips/valzint_powerb0c5fc1a9fb0852260414607a93aeae6.tex new file mode 100644 index 00000000..982dc808 --- /dev/null +++ b/sail_latex_mips/valzint_powerb0c5fc1a9fb0852260414607a93aeae6.tex @@ -0,0 +1 @@ +int_power : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valzis_nonebebf4558161c4d567fb50f7df9e82374.tex b/sail_latex_mips/valzis_nonebebf4558161c4d567fb50f7df9e82374.tex new file mode 100644 index 00000000..a2a9de9d --- /dev/null +++ b/sail_latex_mips/valzis_nonebebf4558161c4d567fb50f7df9e82374.tex @@ -0,0 +1 @@ +is_none : forall ('a : Type). option('a) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex b/sail_latex_mips/valzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex new file mode 100644 index 00000000..d2059f34 --- /dev/null +++ b/sail_latex_mips/valzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex @@ -0,0 +1 @@ +is_some : forall ('a : Type). option('a) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzisaddressaligned9b5d757d64e55546134bbc396b0d9129.tex b/sail_latex_mips/valzisaddressaligned9b5d757d64e55546134bbc396b0d9129.tex new file mode 100644 index 00000000..bab8e912 --- /dev/null +++ b/sail_latex_mips/valzisaddressaligned9b5d757d64e55546134bbc396b0d9129.tex @@ -0,0 +1 @@ +isAddressAligned : (bits(64), WordType) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzissentrycapede72a679ee46914361276c4bacdaf18.tex b/sail_latex_mips/valzissentrycapede72a679ee46914361276c4bacdaf18.tex new file mode 100644 index 00000000..41aaa9ba --- /dev/null +++ b/sail_latex_mips/valzissentrycapede72a679ee46914361276c4bacdaf18.tex @@ -0,0 +1 @@ +isSentryCap : Capability -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzlt_int996a8b8c361a31bed6b5509ca6686e1a.tex b/sail_latex_mips/valzlt_int996a8b8c361a31bed6b5509ca6686e1a.tex new file mode 100644 index 00000000..03401793 --- /dev/null +++ b/sail_latex_mips/valzlt_int996a8b8c361a31bed6b5509ca6686e1a.tex @@ -0,0 +1 @@ +lt_int : forall ('n 'm : Int). (int('n), int('m)) -> bool('n < 'm) \ No newline at end of file diff --git a/sail_latex_mips/valzlteq_intc80d1082e443aa434e39355e493ece1e.tex b/sail_latex_mips/valzlteq_intc80d1082e443aa434e39355e493ece1e.tex new file mode 100644 index 00000000..4e580541 --- /dev/null +++ b/sail_latex_mips/valzlteq_intc80d1082e443aa434e39355e493ece1e.tex @@ -0,0 +1 @@ +lteq_int : forall ('n 'm : Int). (int('n), int('m)) -> bool('n <= 'm) \ No newline at end of file diff --git a/sail_latex_mips/valzmask357329ae84e03dd27d4454a1873fc3dd.tex b/sail_latex_mips/valzmask357329ae84e03dd27d4454a1873fc3dd.tex new file mode 100644 index 00000000..5d375d76 --- /dev/null +++ b/sail_latex_mips/valzmask357329ae84e03dd27d4454a1873fc3dd.tex @@ -0,0 +1 @@ +mask : forall ('m 'n : Int), ('m >= 'n & 'n > 0). (implicit('n), bits('m)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex b/sail_latex_mips/valzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex new file mode 100644 index 00000000..577d6466 --- /dev/null +++ b/sail_latex_mips/valzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex @@ -0,0 +1 @@ +MAX : forall ('n : Int), 'n >= 0. int('n) -> int(2 ^ 'n - 1) \ No newline at end of file diff --git a/sail_latex_mips/valzmax_atom2691d513aec6d2154c7685b5a93fac12.tex b/sail_latex_mips/valzmax_atom2691d513aec6d2154c7685b5a93fac12.tex new file mode 100644 index 00000000..a655421a --- /dev/null +++ b/sail_latex_mips/valzmax_atom2691d513aec6d2154c7685b5a93fac12.tex @@ -0,0 +1 @@ +max_atom : forall ('a 'b : Int). (int('a), int('b)) -> {'c, (('c == 'a | 'c == 'b) & 'c >= 'a & 'c >= 'b). int('c)} \ No newline at end of file diff --git a/sail_latex_mips/valzmax_inta8f95a0baf723be8373221a893afa8f3.tex b/sail_latex_mips/valzmax_inta8f95a0baf723be8373221a893afa8f3.tex new file mode 100644 index 00000000..adef5ec1 --- /dev/null +++ b/sail_latex_mips/valzmax_inta8f95a0baf723be8373221a893afa8f3.tex @@ -0,0 +1 @@ +max_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valzmax_nat266559c9edd4c969dc9a8a0472e3379e.tex b/sail_latex_mips/valzmax_nat266559c9edd4c969dc9a8a0472e3379e.tex new file mode 100644 index 00000000..6737f77c --- /dev/null +++ b/sail_latex_mips/valzmax_nat266559c9edd4c969dc9a8a0472e3379e.tex @@ -0,0 +1 @@ +max_nat : (nat, nat) -> nat \ No newline at end of file diff --git a/sail_latex_mips/valzmem_synca6b7cb44064bf3e0998ab455e0247f73.tex b/sail_latex_mips/valzmem_synca6b7cb44064bf3e0998ab455e0247f73.tex new file mode 100644 index 00000000..9c8453e3 --- /dev/null +++ b/sail_latex_mips/valzmem_synca6b7cb44064bf3e0998ab455e0247f73.tex @@ -0,0 +1 @@ +MEM_sync : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzmemaccesscaprestriction_of_num40cccde77213084744ee3677231b6055.tex b/sail_latex_mips/valzmemaccesscaprestriction_of_num40cccde77213084744ee3677231b6055.tex new file mode 100644 index 00000000..d8e5f6a7 --- /dev/null +++ b/sail_latex_mips/valzmemaccesscaprestriction_of_num40cccde77213084744ee3677231b6055.tex @@ -0,0 +1 @@ +MemAccessCapRestriction_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> MemAccessCapRestriction \ No newline at end of file diff --git a/sail_latex_mips/valzmemaccesstype_of_nume9bc7b384750bfb019a26074bf441f44.tex b/sail_latex_mips/valzmemaccesstype_of_nume9bc7b384750bfb019a26074bf441f44.tex new file mode 100644 index 00000000..502a3567 --- /dev/null +++ b/sail_latex_mips/valzmemaccesstype_of_nume9bc7b384750bfb019a26074bf441f44.tex @@ -0,0 +1 @@ +MemAccessType_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> MemAccessType \ No newline at end of file diff --git a/sail_latex_mips/valzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex b/sail_latex_mips/valzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex new file mode 100644 index 00000000..a1aec5a8 --- /dev/null +++ b/sail_latex_mips/valzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex @@ -0,0 +1 @@ +memBitsToCapability : (bool, bits(128)) -> Capability \ No newline at end of file diff --git a/sail_latex_mips/valzmemea4fc0f7b33124f774de07c06ff98ca952.tex b/sail_latex_mips/valzmemea4fc0f7b33124f774de07c06ff98ca952.tex new file mode 100644 index 00000000..1a037cb6 --- /dev/null +++ b/sail_latex_mips/valzmemea4fc0f7b33124f774de07c06ff98ca952.tex @@ -0,0 +1 @@ +MEMea : forall ('n : Int). (bits(64), int('n)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzmemea_conditionalac126f332517db0f6fcc745fef2e377d.tex b/sail_latex_mips/valzmemea_conditionalac126f332517db0f6fcc745fef2e377d.tex new file mode 100644 index 00000000..1a1a22a3 --- /dev/null +++ b/sail_latex_mips/valzmemea_conditionalac126f332517db0f6fcc745fef2e377d.tex @@ -0,0 +1 @@ +MEMea_conditional : forall ('n : Int). (bits(64), int('n)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzmemr1e9f36dc3a59118d83f70ffa5fe2dd9e.tex b/sail_latex_mips/valzmemr1e9f36dc3a59118d83f70ffa5fe2dd9e.tex new file mode 100644 index 00000000..6bcc69a7 --- /dev/null +++ b/sail_latex_mips/valzmemr1e9f36dc3a59118d83f70ffa5fe2dd9e.tex @@ -0,0 +1 @@ +MEMr : forall ('n : Int), 'n >= 0. (bits(64), int('n)) -> bits(8 * 'n) \ No newline at end of file diff --git a/sail_latex_mips/valzmemr_reserve_wrapper69fc87b2d98dbfe1febc5c11d3d298c6.tex b/sail_latex_mips/valzmemr_reserve_wrapper69fc87b2d98dbfe1febc5c11d3d298c6.tex new file mode 100644 index 00000000..175efe51 --- /dev/null +++ b/sail_latex_mips/valzmemr_reserve_wrapper69fc87b2d98dbfe1febc5c11d3d298c6.tex @@ -0,0 +1 @@ +MEMr_reserve_wrapper : forall ('n : Int), (1 <= 'n & 'n <= 8). (bits(64), int('n)) -> bits(8 * 'n) \ No newline at end of file diff --git a/sail_latex_mips/valzmemr_reserved9c4ade13430d97ec20a414fa45cde6a.tex b/sail_latex_mips/valzmemr_reserved9c4ade13430d97ec20a414fa45cde6a.tex new file mode 100644 index 00000000..d754869c --- /dev/null +++ b/sail_latex_mips/valzmemr_reserved9c4ade13430d97ec20a414fa45cde6a.tex @@ -0,0 +1 @@ +MEMr_reserve : forall ('n : Int), 'n >= 0. (bits(64), int('n)) -> bits(8 * 'n) \ No newline at end of file diff --git a/sail_latex_mips/valzmemr_tagged440beee75c90056a7102115b9b1125be.tex b/sail_latex_mips/valzmemr_tagged440beee75c90056a7102115b9b1125be.tex new file mode 100644 index 00000000..66271406 --- /dev/null +++ b/sail_latex_mips/valzmemr_tagged440beee75c90056a7102115b9b1125be.tex @@ -0,0 +1 @@ +MEMr_tagged : forall ('size : Int), 'size > 0. (bits(64), int('size), bool) -> (bool, bits('size * 8)) \ No newline at end of file diff --git a/sail_latex_mips/valzmemr_tagged_reserve7e4b5410eb1183e7621342e1939f17e1.tex b/sail_latex_mips/valzmemr_tagged_reserve7e4b5410eb1183e7621342e1939f17e1.tex new file mode 100644 index 00000000..11b18c84 --- /dev/null +++ b/sail_latex_mips/valzmemr_tagged_reserve7e4b5410eb1183e7621342e1939f17e1.tex @@ -0,0 +1 @@ +MEMr_tagged_reserve : forall ('size : Int), 'size > 0. (bits(64), int('size), bool) -> (bool, bits('size * 8)) \ No newline at end of file diff --git a/sail_latex_mips/valzmemr_wrapper75f1a468d1dba11a7720be7f66d3c8e2.tex b/sail_latex_mips/valzmemr_wrapper75f1a468d1dba11a7720be7f66d3c8e2.tex new file mode 100644 index 00000000..5c6d2e13 --- /dev/null +++ b/sail_latex_mips/valzmemr_wrapper75f1a468d1dba11a7720be7f66d3c8e2.tex @@ -0,0 +1 @@ +MEMr_wrapper : forall ('n : Int), (1 <= 'n & 'n <= 8). (bits(64), int('n)) -> bits(8 * 'n) \ No newline at end of file diff --git a/sail_latex_mips/valzmemval_conditional81b75b657c8ad34bfa8410067d19f50e.tex b/sail_latex_mips/valzmemval_conditional81b75b657c8ad34bfa8410067d19f50e.tex new file mode 100644 index 00000000..fcdfdfb7 --- /dev/null +++ b/sail_latex_mips/valzmemval_conditional81b75b657c8ad34bfa8410067d19f50e.tex @@ -0,0 +1 @@ +MEMval_conditional : forall ('n : Int). (bits(64), int('n), bits(8 * 'n)) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzmemvala388891903ef64c4b894bb339a9ee3eb.tex b/sail_latex_mips/valzmemvala388891903ef64c4b894bb339a9ee3eb.tex new file mode 100644 index 00000000..884c1e63 --- /dev/null +++ b/sail_latex_mips/valzmemvala388891903ef64c4b894bb339a9ee3eb.tex @@ -0,0 +1 @@ +MEMval : forall ('n : Int). (bits(64), int('n), bits(8 * 'n)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzmemw_conditional_wrapperc4ec3508a0b7f04fee187cfb25d4f05b.tex b/sail_latex_mips/valzmemw_conditional_wrapperc4ec3508a0b7f04fee187cfb25d4f05b.tex new file mode 100644 index 00000000..c205ce7c --- /dev/null +++ b/sail_latex_mips/valzmemw_conditional_wrapperc4ec3508a0b7f04fee187cfb25d4f05b.tex @@ -0,0 +1 @@ +MEMw_conditional_wrapper : forall ('n : Int), 'n >= 1. (bits(64), int('n), bits(8 * 'n)) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzmemw_tagged27267fa3fd60f13e6d2e22ac409b93e4.tex b/sail_latex_mips/valzmemw_tagged27267fa3fd60f13e6d2e22ac409b93e4.tex new file mode 100644 index 00000000..2fc5d4d6 --- /dev/null +++ b/sail_latex_mips/valzmemw_tagged27267fa3fd60f13e6d2e22ac409b93e4.tex @@ -0,0 +1 @@ +MEMw_tagged : forall ('size : Int), 'size > 0. (bits(64), int('size), bool, bits('size * 8)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzmemw_tagged_conditionalb0f4ab03bc3ed7705702651cf1750e40.tex b/sail_latex_mips/valzmemw_tagged_conditionalb0f4ab03bc3ed7705702651cf1750e40.tex new file mode 100644 index 00000000..29dc26ee --- /dev/null +++ b/sail_latex_mips/valzmemw_tagged_conditionalb0f4ab03bc3ed7705702651cf1750e40.tex @@ -0,0 +1 @@ +MEMw_tagged_conditional : forall ('size : Int), 'size > 0. (bits(64), int('size), bool, bits('size * 8)) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzmemw_wrapper2b3f4fb31f9ea0001f534fade943e5e3.tex b/sail_latex_mips/valzmemw_wrapper2b3f4fb31f9ea0001f534fade943e5e3.tex new file mode 100644 index 00000000..8c162b95 --- /dev/null +++ b/sail_latex_mips/valzmemw_wrapper2b3f4fb31f9ea0001f534fade943e5e3.tex @@ -0,0 +1 @@ +MEMw_wrapper : forall ('n : Int), 'n >= 1. (bits(64), int('n), bits(8 * 'n)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzmin_atombf865ffed8d1a7f4606db9d6d968a016.tex b/sail_latex_mips/valzmin_atombf865ffed8d1a7f4606db9d6d968a016.tex new file mode 100644 index 00000000..5e5fdf47 --- /dev/null +++ b/sail_latex_mips/valzmin_atombf865ffed8d1a7f4606db9d6d968a016.tex @@ -0,0 +1 @@ +min_atom : forall ('a 'b : Int). (int('a), int('b)) -> {'c, (('c == 'a | 'c == 'b) & 'c <= 'a & 'c <= 'b). int('c)} \ No newline at end of file diff --git a/sail_latex_mips/valzmin_intaf4626ab3b9c2d0b9494d7e8d265dd26.tex b/sail_latex_mips/valzmin_intaf4626ab3b9c2d0b9494d7e8d265dd26.tex new file mode 100644 index 00000000..1013114d --- /dev/null +++ b/sail_latex_mips/valzmin_intaf4626ab3b9c2d0b9494d7e8d265dd26.tex @@ -0,0 +1 @@ +min_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valzmin_nat7dddd2b4f1427434a323cd17c0426f93.tex b/sail_latex_mips/valzmin_nat7dddd2b4f1427434a323cd17c0426f93.tex new file mode 100644 index 00000000..95c53d96 --- /dev/null +++ b/sail_latex_mips/valzmin_nat7dddd2b4f1427434a323cd17c0426f93.tex @@ -0,0 +1 @@ +min_nat : (nat, nat) -> nat \ No newline at end of file diff --git a/sail_latex_mips/valzmips_sign_extenddff82d4ceaaa72d7146e15c8674216ac.tex b/sail_latex_mips/valzmips_sign_extenddff82d4ceaaa72d7146e15c8674216ac.tex new file mode 100644 index 00000000..774799a9 --- /dev/null +++ b/sail_latex_mips/valzmips_sign_extenddff82d4ceaaa72d7146e15c8674216ac.tex @@ -0,0 +1 @@ +mips_sign_extend : forall ('n 'm : Int), 'm >= 'n. (implicit('m), bits('n)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_mips/valzmips_zzero_extend6340d2cbae7a2266a4e1077b06a57276.tex b/sail_latex_mips/valzmips_zzero_extend6340d2cbae7a2266a4e1077b06a57276.tex new file mode 100644 index 00000000..0d0e8d02 --- /dev/null +++ b/sail_latex_mips/valzmips_zzero_extend6340d2cbae7a2266a4e1077b06a57276.tex @@ -0,0 +1 @@ +mips_zero_extend : forall ('n 'm : Int), 'm >= 'n. (implicit('m), bits('n)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_mips/valzmipssegmentof3db6164251b0305648a8f4d8f750299e.tex b/sail_latex_mips/valzmipssegmentof3db6164251b0305648a8f4d8f750299e.tex new file mode 100644 index 00000000..14234c03 --- /dev/null +++ b/sail_latex_mips/valzmipssegmentof3db6164251b0305648a8f4d8f750299e.tex @@ -0,0 +1 @@ +MIPSSegmentOf : bits(64) -> (AccessLevel, option(bits(64))) \ No newline at end of file diff --git a/sail_latex_mips/valzmk_capcauseregd8ae0b1c037e066a22724fe6a3d3a9a6.tex b/sail_latex_mips/valzmk_capcauseregd8ae0b1c037e066a22724fe6a3d3a9a6.tex new file mode 100644 index 00000000..6b459399 --- /dev/null +++ b/sail_latex_mips/valzmk_capcauseregd8ae0b1c037e066a22724fe6a3d3a9a6.tex @@ -0,0 +1 @@ +Mk_CapCauseReg : bitvector(16, dec) -> CapCauseReg \ No newline at end of file diff --git a/sail_latex_mips/valzmk_causereg8c2dd932a95a40841ae776546777d7fb.tex b/sail_latex_mips/valzmk_causereg8c2dd932a95a40841ae776546777d7fb.tex new file mode 100644 index 00000000..9b1df822 --- /dev/null +++ b/sail_latex_mips/valzmk_causereg8c2dd932a95a40841ae776546777d7fb.tex @@ -0,0 +1 @@ +Mk_CauseReg : bitvector(32, dec) -> CauseReg \ No newline at end of file diff --git a/sail_latex_mips/valzmk_contextreg1279723b7ab574992f73b31ca621ca0c.tex b/sail_latex_mips/valzmk_contextreg1279723b7ab574992f73b31ca621ca0c.tex new file mode 100644 index 00000000..fd554356 --- /dev/null +++ b/sail_latex_mips/valzmk_contextreg1279723b7ab574992f73b31ca621ca0c.tex @@ -0,0 +1 @@ +Mk_ContextReg : bitvector(64, dec) -> ContextReg \ No newline at end of file diff --git a/sail_latex_mips/valzmk_statusreg3621c22662d06bd540ae8fffe8f9e08c.tex b/sail_latex_mips/valzmk_statusreg3621c22662d06bd540ae8fffe8f9e08c.tex new file mode 100644 index 00000000..4b151b12 --- /dev/null +++ b/sail_latex_mips/valzmk_statusreg3621c22662d06bd540ae8fffe8f9e08c.tex @@ -0,0 +1 @@ +Mk_StatusReg : bitvector(32, dec) -> StatusReg \ No newline at end of file diff --git a/sail_latex_mips/valzmk_tlbentry1b93a8ab49c4923ac3e577c5f28836c1.tex b/sail_latex_mips/valzmk_tlbentry1b93a8ab49c4923ac3e577c5f28836c1.tex new file mode 100644 index 00000000..a2b5be93 --- /dev/null +++ b/sail_latex_mips/valzmk_tlbentry1b93a8ab49c4923ac3e577c5f28836c1.tex @@ -0,0 +1 @@ +Mk_TLBEntry : bitvector(119, dec) -> TLBEntry \ No newline at end of file diff --git a/sail_latex_mips/valzmk_tlbentryhireg6533ea9a44dee28d4b6d342ff77ceb66.tex b/sail_latex_mips/valzmk_tlbentryhireg6533ea9a44dee28d4b6d342ff77ceb66.tex new file mode 100644 index 00000000..1ca57258 --- /dev/null +++ b/sail_latex_mips/valzmk_tlbentryhireg6533ea9a44dee28d4b6d342ff77ceb66.tex @@ -0,0 +1 @@ +Mk_TLBEntryHiReg : bitvector(64, dec) -> TLBEntryHiReg \ No newline at end of file diff --git a/sail_latex_mips/valzmk_tlbentryloreg686ea4d498fae1c365c28583f86fcdf2.tex b/sail_latex_mips/valzmk_tlbentryloreg686ea4d498fae1c365c28583f86fcdf2.tex new file mode 100644 index 00000000..1f52a5d3 --- /dev/null +++ b/sail_latex_mips/valzmk_tlbentryloreg686ea4d498fae1c365c28583f86fcdf2.tex @@ -0,0 +1 @@ +Mk_TLBEntryLoReg : bitvector(64, dec) -> TLBEntryLoReg \ No newline at end of file diff --git a/sail_latex_mips/valzmk_xcontextregea90f6c75d17b6f2b8452e8764f15274.tex b/sail_latex_mips/valzmk_xcontextregea90f6c75d17b6f2b8452e8764f15274.tex new file mode 100644 index 00000000..0c469092 --- /dev/null +++ b/sail_latex_mips/valzmk_xcontextregea90f6c75d17b6f2b8452e8764f15274.tex @@ -0,0 +1 @@ +Mk_XContextReg : bitvector(64, dec) -> XContextReg \ No newline at end of file diff --git a/sail_latex_mips/valzmult_atomdbad478b99777b7676dde1f5a7900711.tex b/sail_latex_mips/valzmult_atomdbad478b99777b7676dde1f5a7900711.tex new file mode 100644 index 00000000..6e0158b2 --- /dev/null +++ b/sail_latex_mips/valzmult_atomdbad478b99777b7676dde1f5a7900711.tex @@ -0,0 +1 @@ +mult_atom : forall ('n 'm : Int). (int('n), int('m)) -> int('n * 'm) \ No newline at end of file diff --git a/sail_latex_mips/valzmult_inte25d1b032a27b461f0eaf0c84be37a2b.tex b/sail_latex_mips/valzmult_inte25d1b032a27b461f0eaf0c84be37a2b.tex new file mode 100644 index 00000000..97f71615 --- /dev/null +++ b/sail_latex_mips/valzmult_inte25d1b032a27b461f0eaf0c84be37a2b.tex @@ -0,0 +1 @@ +mult_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valznegate_atomfefdbde89b468d9df54837e864426d70.tex b/sail_latex_mips/valznegate_atomfefdbde89b468d9df54837e864426d70.tex new file mode 100644 index 00000000..92434174 --- /dev/null +++ b/sail_latex_mips/valznegate_atomfefdbde89b468d9df54837e864426d70.tex @@ -0,0 +1 @@ +negate_atom : forall ('n : Int). int('n) -> int(- 'n) \ No newline at end of file diff --git a/sail_latex_mips/valznegate_int42f776f84c124d77c3e367500082e43f.tex b/sail_latex_mips/valznegate_int42f776f84c124d77c3e367500082e43f.tex new file mode 100644 index 00000000..a982439e --- /dev/null +++ b/sail_latex_mips/valznegate_int42f776f84c124d77c3e367500082e43f.tex @@ -0,0 +1 @@ +negate_int : int -> int \ No newline at end of file diff --git a/sail_latex_mips/valznegate_range78b007ae673ca039d425d3facc380863.tex b/sail_latex_mips/valznegate_range78b007ae673ca039d425d3facc380863.tex new file mode 100644 index 00000000..c358178a --- /dev/null +++ b/sail_latex_mips/valznegate_range78b007ae673ca039d425d3facc380863.tex @@ -0,0 +1 @@ +negate_range : forall ('n 'm : Int). range('n, 'm) -> range(- 'm, - 'n) \ No newline at end of file diff --git a/sail_latex_mips/valzneq_anythingf220233154ca93d75c0323f604bb8d16.tex b/sail_latex_mips/valzneq_anythingf220233154ca93d75c0323f604bb8d16.tex new file mode 100644 index 00000000..9ff01c44 --- /dev/null +++ b/sail_latex_mips/valzneq_anythingf220233154ca93d75c0323f604bb8d16.tex @@ -0,0 +1 @@ +neq_anything : forall ('a : Type). ('a, 'a) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzneq_bits167748c906c068e62596c88540a84f42.tex b/sail_latex_mips/valzneq_bits167748c906c068e62596c88540a84f42.tex new file mode 100644 index 00000000..e1cecec8 --- /dev/null +++ b/sail_latex_mips/valzneq_bits167748c906c068e62596c88540a84f42.tex @@ -0,0 +1 @@ +neq_bits : forall ('n : Int). (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex b/sail_latex_mips/valzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex new file mode 100644 index 00000000..f11545c3 --- /dev/null +++ b/sail_latex_mips/valzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex @@ -0,0 +1 @@ +neq_bool : (bool, bool) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex b/sail_latex_mips/valzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex new file mode 100644 index 00000000..0f7ab4f2 --- /dev/null +++ b/sail_latex_mips/valzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex @@ -0,0 +1 @@ +neq_int : forall ('n 'm : Int). (int('n), int('m)) -> bool('n != 'm) \ No newline at end of file diff --git a/sail_latex_mips/valznot_boole1dd3e44bc87a2a10d8e257004c2d36a.tex b/sail_latex_mips/valznot_boole1dd3e44bc87a2a10d8e257004c2d36a.tex new file mode 100644 index 00000000..366513fd --- /dev/null +++ b/sail_latex_mips/valznot_boole1dd3e44bc87a2a10d8e257004c2d36a.tex @@ -0,0 +1 @@ +not_bool : forall ('p : Bool). bool('p) -> bool(not('p)) \ No newline at end of file diff --git a/sail_latex_mips/valznot_vecfb45897f737be88160f5363827ef4a4b.tex b/sail_latex_mips/valznot_vecfb45897f737be88160f5363827ef4a4b.tex new file mode 100644 index 00000000..b2481577 --- /dev/null +++ b/sail_latex_mips/valznot_vecfb45897f737be88160f5363827ef4a4b.tex @@ -0,0 +1 @@ +not_vec : forall ('n : Int). bits('n) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valznotwordvald5d5f9e6d06ea0a5cece40166646a4b4.tex b/sail_latex_mips/valznotwordvald5d5f9e6d06ea0a5cece40166646a4b4.tex new file mode 100644 index 00000000..b3fe5c3b --- /dev/null +++ b/sail_latex_mips/valznotwordvald5d5f9e6d06ea0a5cece40166646a4b4.tex @@ -0,0 +1 @@ +NotWordVal : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valznum_of_accessleveld0fc11b6a25cf84b4b09fd5eb5a37980.tex b/sail_latex_mips/valznum_of_accessleveld0fc11b6a25cf84b4b09fd5eb5a37980.tex new file mode 100644 index 00000000..f651279d --- /dev/null +++ b/sail_latex_mips/valznum_of_accessleveld0fc11b6a25cf84b4b09fd5eb5a37980.tex @@ -0,0 +1 @@ +num_of_AccessLevel : AccessLevel -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_mips/valznum_of_capexa430f3db535161473e26bac337cc3ffe.tex b/sail_latex_mips/valznum_of_capexa430f3db535161473e26bac337cc3ffe.tex new file mode 100644 index 00000000..61c04758 --- /dev/null +++ b/sail_latex_mips/valznum_of_capexa430f3db535161473e26bac337cc3ffe.tex @@ -0,0 +1 @@ +num_of_CapEx : CapEx -> {'e, (0 <= 'e & 'e <= 24). int('e)} \ No newline at end of file diff --git a/sail_latex_mips/valznum_of_clearregset49e10f200544574f819f7f660071e10b.tex b/sail_latex_mips/valznum_of_clearregset49e10f200544574f819f7f660071e10b.tex new file mode 100644 index 00000000..fec8d637 --- /dev/null +++ b/sail_latex_mips/valznum_of_clearregset49e10f200544574f819f7f660071e10b.tex @@ -0,0 +1 @@ +num_of_ClearRegSet : ClearRegSet -> {'e, (0 <= 'e & 'e <= 3). int('e)} \ No newline at end of file diff --git a/sail_latex_mips/valznum_of_comparisonacdefcc370a45e5aec6df49e5b5d9b12.tex b/sail_latex_mips/valznum_of_comparisonacdefcc370a45e5aec6df49e5b5d9b12.tex new file mode 100644 index 00000000..3c14211e --- /dev/null +++ b/sail_latex_mips/valznum_of_comparisonacdefcc370a45e5aec6df49e5b5d9b12.tex @@ -0,0 +1 @@ +num_of_Comparison : Comparison -> {'e, (0 <= 'e & 'e <= 7). int('e)} \ No newline at end of file diff --git a/sail_latex_mips/valznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex b/sail_latex_mips/valznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex new file mode 100644 index 00000000..610c108e --- /dev/null +++ b/sail_latex_mips/valznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex @@ -0,0 +1 @@ +num_of_CPtrCmpOp : CPtrCmpOp -> {'e, (0 <= 'e & 'e <= 7). int('e)} \ No newline at end of file diff --git a/sail_latex_mips/valznum_of_decode_failure25ef6d99c7154f39444aafcc89394acd.tex b/sail_latex_mips/valznum_of_decode_failure25ef6d99c7154f39444aafcc89394acd.tex new file mode 100644 index 00000000..fbf1750b --- /dev/null +++ b/sail_latex_mips/valznum_of_decode_failure25ef6d99c7154f39444aafcc89394acd.tex @@ -0,0 +1 @@ +num_of_decode_failure : decode_failure -> {'e, (0 <= 'e & 'e <= 3). int('e)} \ No newline at end of file diff --git a/sail_latex_mips/valznum_of_exception9e1669909ce7707290888338ffbcc8f8.tex b/sail_latex_mips/valznum_of_exception9e1669909ce7707290888338ffbcc8f8.tex new file mode 100644 index 00000000..d9886708 --- /dev/null +++ b/sail_latex_mips/valznum_of_exception9e1669909ce7707290888338ffbcc8f8.tex @@ -0,0 +1 @@ +num_of_Exception : Exception -> {'e, (0 <= 'e & 'e <= 18). int('e)} \ No newline at end of file diff --git a/sail_latex_mips/valznum_of_memaccesscaprestriction4f02267c2f3610530a623ffeb2b0f8f5.tex b/sail_latex_mips/valznum_of_memaccesscaprestriction4f02267c2f3610530a623ffeb2b0f8f5.tex new file mode 100644 index 00000000..e42d156c --- /dev/null +++ b/sail_latex_mips/valznum_of_memaccesscaprestriction4f02267c2f3610530a623ffeb2b0f8f5.tex @@ -0,0 +1 @@ +num_of_MemAccessCapRestriction : MemAccessCapRestriction -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_mips/valznum_of_memaccesstype1f8a90d42ae8b06c64b096b6b6eb7e6b.tex b/sail_latex_mips/valznum_of_memaccesstype1f8a90d42ae8b06c64b096b6b6eb7e6b.tex new file mode 100644 index 00000000..d9265d90 --- /dev/null +++ b/sail_latex_mips/valznum_of_memaccesstype1f8a90d42ae8b06c64b096b6b6eb7e6b.tex @@ -0,0 +1 @@ +num_of_MemAccessType : MemAccessType -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_mips/valznum_of_wordtypef0e59bab28a4b7f5e903a6c47ab403a5.tex b/sail_latex_mips/valznum_of_wordtypef0e59bab28a4b7f5e903a6c47ab403a5.tex new file mode 100644 index 00000000..a0b1cf85 --- /dev/null +++ b/sail_latex_mips/valznum_of_wordtypef0e59bab28a4b7f5e903a6c47ab403a5.tex @@ -0,0 +1 @@ +num_of_WordType : WordType -> {'e, (0 <= 'e & 'e <= 3). int('e)} \ No newline at end of file diff --git a/sail_latex_mips/valznum_of_wordtypeunaligned443855cd2b4cc93af964642e98c1b412.tex b/sail_latex_mips/valznum_of_wordtypeunaligned443855cd2b4cc93af964642e98c1b412.tex new file mode 100644 index 00000000..61313837 --- /dev/null +++ b/sail_latex_mips/valznum_of_wordtypeunaligned443855cd2b4cc93af964642e98c1b412.tex @@ -0,0 +1 @@ +num_of_WordTypeUnaligned : WordTypeUnaligned -> {'e, (0 <= 'e & 'e <= 3). int('e)} \ No newline at end of file diff --git a/sail_latex_mips/valzones_implicitd278a7fa4099e3986b30108716d3adc5.tex b/sail_latex_mips/valzones_implicitd278a7fa4099e3986b30108716d3adc5.tex new file mode 100644 index 00000000..fe2c7354 --- /dev/null +++ b/sail_latex_mips/valzones_implicitd278a7fa4099e3986b30108716d3adc5.tex @@ -0,0 +1 @@ +ones_implicit : forall ('n : Int), 'n >= 0. (implicit('n), unit) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzor_bool5f07f9d72d4d1495c45a3531c787546a.tex b/sail_latex_mips/valzor_bool5f07f9d72d4d1495c45a3531c787546a.tex new file mode 100644 index 00000000..bd3bcb77 --- /dev/null +++ b/sail_latex_mips/valzor_bool5f07f9d72d4d1495c45a3531c787546a.tex @@ -0,0 +1 @@ +or_bool : forall ('p 'q : Bool). (bool('p), bool('q)) -> bool(('p | 'q)) \ No newline at end of file diff --git a/sail_latex_mips/valzor_vec467c7a3f74be27085fe1b2aa3651ffe7.tex b/sail_latex_mips/valzor_vec467c7a3f74be27085fe1b2aa3651ffe7.tex new file mode 100644 index 00000000..45e50cce --- /dev/null +++ b/sail_latex_mips/valzor_vec467c7a3f74be27085fe1b2aa3651ffe7.tex @@ -0,0 +1 @@ +or_vec : forall ('n : Int). (bits('n), bits('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex b/sail_latex_mips/valzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex new file mode 100644 index 00000000..a69a2b58 --- /dev/null +++ b/sail_latex_mips/valzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex @@ -0,0 +1 @@ +pcc_access_system_regs : unit -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzplain_vector_access792547dd734d4ff2e6078cbb88967469.tex b/sail_latex_mips/valzplain_vector_access792547dd734d4ff2e6078cbb88967469.tex new file mode 100644 index 00000000..7dbd00bd --- /dev/null +++ b/sail_latex_mips/valzplain_vector_access792547dd734d4ff2e6078cbb88967469.tex @@ -0,0 +1 @@ +plain_vector_access : forall ('n 'm : Int)('a : Type), (0 <= 'm & 'm < 'n). (vector('n, dec, 'a), int('m)) -> 'a \ No newline at end of file diff --git a/sail_latex_mips/valzplain_vector_updateb31d67bfe51b1a6f79983347dfc57da0.tex b/sail_latex_mips/valzplain_vector_updateb31d67bfe51b1a6f79983347dfc57da0.tex new file mode 100644 index 00000000..beb9b152 --- /dev/null +++ b/sail_latex_mips/valzplain_vector_updateb31d67bfe51b1a6f79983347dfc57da0.tex @@ -0,0 +1,2 @@ +plain_vector_update : forall ('n 'm : Int)('a : Type), (0 <= 'm & 'm < 'n). + (vector('n, dec, 'a), int('m), 'a) -> vector('n, dec, 'a) \ No newline at end of file diff --git a/sail_latex_mips/valzpow2e971ce2f9ebb899590551317286dfd1b.tex b/sail_latex_mips/valzpow2e971ce2f9ebb899590551317286dfd1b.tex new file mode 100644 index 00000000..a507a5d6 --- /dev/null +++ b/sail_latex_mips/valzpow2e971ce2f9ebb899590551317286dfd1b.tex @@ -0,0 +1 @@ +pow2 : forall ('n : Int), 'n >= 0. int('n) -> int(2 ^ 'n) \ No newline at end of file diff --git a/sail_latex_mips/valzprerr_bits932899725108ebe483d3226f250f2b92.tex b/sail_latex_mips/valzprerr_bits932899725108ebe483d3226f250f2b92.tex new file mode 100644 index 00000000..44097a2a --- /dev/null +++ b/sail_latex_mips/valzprerr_bits932899725108ebe483d3226f250f2b92.tex @@ -0,0 +1 @@ +prerr_bits : forall ('n : Int). (string, bits('n)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzprerr_endline73ce57fcf6e847727670556577cb2de0.tex b/sail_latex_mips/valzprerr_endline73ce57fcf6e847727670556577cb2de0.tex new file mode 100644 index 00000000..bfaafad2 --- /dev/null +++ b/sail_latex_mips/valzprerr_endline73ce57fcf6e847727670556577cb2de0.tex @@ -0,0 +1 @@ +prerr_endline : string -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzprerr_int00b48f715fbb32df5901801dff63b643.tex b/sail_latex_mips/valzprerr_int00b48f715fbb32df5901801dff63b643.tex new file mode 100644 index 00000000..0249ddb4 --- /dev/null +++ b/sail_latex_mips/valzprerr_int00b48f715fbb32df5901801dff63b643.tex @@ -0,0 +1 @@ +prerr_int : (string, int) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzprerre641bc17ebf3c7131851f8df33a62260.tex b/sail_latex_mips/valzprerre641bc17ebf3c7131851f8df33a62260.tex new file mode 100644 index 00000000..3bb9eb6a --- /dev/null +++ b/sail_latex_mips/valzprerre641bc17ebf3c7131851f8df33a62260.tex @@ -0,0 +1 @@ +prerr : string -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzprint_bits30cf225474fbf3e575d7aa83aa309559.tex b/sail_latex_mips/valzprint_bits30cf225474fbf3e575d7aa83aa309559.tex new file mode 100644 index 00000000..e2cebf75 --- /dev/null +++ b/sail_latex_mips/valzprint_bits30cf225474fbf3e575d7aa83aa309559.tex @@ -0,0 +1 @@ +print_bits : forall ('n : Int). (string, bits('n)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzprint_endline03a43e2779561cb054d0761733c27e9b.tex b/sail_latex_mips/valzprint_endline03a43e2779561cb054d0761733c27e9b.tex new file mode 100644 index 00000000..5421e009 --- /dev/null +++ b/sail_latex_mips/valzprint_endline03a43e2779561cb054d0761733c27e9b.tex @@ -0,0 +1 @@ +print_endline : string -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzprint_intfb625bfb7a4021903513aeb4396bd878.tex b/sail_latex_mips/valzprint_intfb625bfb7a4021903513aeb4396bd878.tex new file mode 100644 index 00000000..3d5a2a33 --- /dev/null +++ b/sail_latex_mips/valzprint_intfb625bfb7a4021903513aeb4396bd878.tex @@ -0,0 +1 @@ +print_int : (string, int) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzputchare63a26733a4ffbee3ab40a4ee6cd644b.tex b/sail_latex_mips/valzputchare63a26733a4ffbee3ab40a4ee6cd644b.tex new file mode 100644 index 00000000..42bb0c86 --- /dev/null +++ b/sail_latex_mips/valzputchare63a26733a4ffbee3ab40a4ee6cd644b.tex @@ -0,0 +1 @@ +putchar : int -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzquot_round_zzeroa8d9d278dc91a14956dfe19d01766403.tex b/sail_latex_mips/valzquot_round_zzeroa8d9d278dc91a14956dfe19d01766403.tex new file mode 100644 index 00000000..ac74d114 --- /dev/null +++ b/sail_latex_mips/valzquot_round_zzeroa8d9d278dc91a14956dfe19d01766403.tex @@ -0,0 +1 @@ +quot_round_zero : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valzraise_c2_exception8c17523e86ae9ef48da8a222c10be2ee1.tex b/sail_latex_mips/valzraise_c2_exception8c17523e86ae9ef48da8a222c10be2ee1.tex new file mode 100644 index 00000000..635dcd22 --- /dev/null +++ b/sail_latex_mips/valzraise_c2_exception8c17523e86ae9ef48da8a222c10be2ee1.tex @@ -0,0 +1 @@ +raise_c2_exception8 : forall ('o : Type). (CapEx, bits(8)) -> 'o \ No newline at end of file diff --git a/sail_latex_mips/valzraise_c2_exception_badaddrd8f6a78fc18067d06626bbc713515a9a.tex b/sail_latex_mips/valzraise_c2_exception_badaddrd8f6a78fc18067d06626bbc713515a9a.tex new file mode 100644 index 00000000..8d65d851 --- /dev/null +++ b/sail_latex_mips/valzraise_c2_exception_badaddrd8f6a78fc18067d06626bbc713515a9a.tex @@ -0,0 +1 @@ +raise_c2_exception_badaddr : forall ('o : Type). (CapEx, regno, bits(64)) -> 'o \ No newline at end of file diff --git a/sail_latex_mips/valzraise_c2_exception_noregaf4f146af9490f033f39a46e2216dccb.tex b/sail_latex_mips/valzraise_c2_exception_noregaf4f146af9490f033f39a46e2216dccb.tex new file mode 100644 index 00000000..dd353e59 --- /dev/null +++ b/sail_latex_mips/valzraise_c2_exception_noregaf4f146af9490f033f39a46e2216dccb.tex @@ -0,0 +1 @@ +raise_c2_exception_noreg : forall ('o : Type). CapEx -> 'o \ No newline at end of file diff --git a/sail_latex_mips/valzraise_c2_exceptionb9a632810adbd99dc25a5f3a28ddb9f2.tex b/sail_latex_mips/valzraise_c2_exceptionb9a632810adbd99dc25a5f3a28ddb9f2.tex new file mode 100644 index 00000000..d30ca98a --- /dev/null +++ b/sail_latex_mips/valzraise_c2_exceptionb9a632810adbd99dc25a5f3a28ddb9f2.tex @@ -0,0 +1 @@ +raise_c2_exception : forall ('o : Type). (CapEx, regno) -> 'o \ No newline at end of file diff --git a/sail_latex_mips/valzread_tag_bool44af427aafdd59e3a8c85269cd4adf9e.tex b/sail_latex_mips/valzread_tag_bool44af427aafdd59e3a8c85269cd4adf9e.tex new file mode 100644 index 00000000..81df4fa8 --- /dev/null +++ b/sail_latex_mips/valzread_tag_bool44af427aafdd59e3a8c85269cd4adf9e.tex @@ -0,0 +1 @@ +read_tag_bool : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzreadcapreg0fe08ef5bf06c41ffed8e12baf8ddd85.tex b/sail_latex_mips/valzreadcapreg0fe08ef5bf06c41ffed8e12baf8ddd85.tex new file mode 100644 index 00000000..19b94ee0 --- /dev/null +++ b/sail_latex_mips/valzreadcapreg0fe08ef5bf06c41ffed8e12baf8ddd85.tex @@ -0,0 +1 @@ +readCapReg : regno -> Capability \ No newline at end of file diff --git a/sail_latex_mips/valzreadcapregddc65f046a34609a089c9bf681a6893bca6.tex b/sail_latex_mips/valzreadcapregddc65f046a34609a089c9bf681a6893bca6.tex new file mode 100644 index 00000000..248c069b --- /dev/null +++ b/sail_latex_mips/valzreadcapregddc65f046a34609a089c9bf681a6893bca6.tex @@ -0,0 +1 @@ +readCapRegDDC : regno -> Capability \ No newline at end of file diff --git a/sail_latex_mips/valzrem_round_zzero90d115d6c3e756b94f7766d1b76fbb83.tex b/sail_latex_mips/valzrem_round_zzero90d115d6c3e756b94f7766d1b76fbb83.tex new file mode 100644 index 00000000..1ff854e8 --- /dev/null +++ b/sail_latex_mips/valzrem_round_zzero90d115d6c3e756b94f7766d1b76fbb83.tex @@ -0,0 +1 @@ +rem_round_zero : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valzreplicate_bitsb29bdab6bb9437712accf2dc81ea3d3e.tex b/sail_latex_mips/valzreplicate_bitsb29bdab6bb9437712accf2dc81ea3d3e.tex new file mode 100644 index 00000000..7ec5b77d --- /dev/null +++ b/sail_latex_mips/valzreplicate_bitsb29bdab6bb9437712accf2dc81ea3d3e.tex @@ -0,0 +1 @@ +replicate_bits : forall ('n 'm : Int). (bits('n), int('m)) -> bits('n * 'm) \ No newline at end of file diff --git a/sail_latex_mips/valzreverse_endianness67387713ef62b5e52d27f28369230428.tex b/sail_latex_mips/valzreverse_endianness67387713ef62b5e52d27f28369230428.tex new file mode 100644 index 00000000..1876e6dd --- /dev/null +++ b/sail_latex_mips/valzreverse_endianness67387713ef62b5e52d27f28369230428.tex @@ -0,0 +1 @@ +reverse_endianness : forall ('n : Int), (mod('n, 8) == 0 & 'n >= 8). bits('n) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzrgpr9bb3f998022d0674cf437905d0ab2e62.tex b/sail_latex_mips/valzrgpr9bb3f998022d0674cf437905d0ab2e62.tex new file mode 100644 index 00000000..7e6551dd --- /dev/null +++ b/sail_latex_mips/valzrgpr9bb3f998022d0674cf437905d0ab2e62.tex @@ -0,0 +1 @@ +rGPR : bits(5) -> bits(64) \ No newline at end of file diff --git a/sail_latex_mips/valzsail_arith_shiftrighta24f06e92ffcd84e26ed61085c833371.tex b/sail_latex_mips/valzsail_arith_shiftrighta24f06e92ffcd84e26ed61085c833371.tex new file mode 100644 index 00000000..9d15bcf4 --- /dev/null +++ b/sail_latex_mips/valzsail_arith_shiftrighta24f06e92ffcd84e26ed61085c833371.tex @@ -0,0 +1 @@ +sail_arith_shiftright : forall ('n : Int)('ord : Order). (bitvector('n, 'ord), int) -> bitvector('n, 'ord) \ No newline at end of file diff --git a/sail_latex_mips/valzsail_maske146b73afc824e90813dd8234bfa3053.tex b/sail_latex_mips/valzsail_maske146b73afc824e90813dd8234bfa3053.tex new file mode 100644 index 00000000..07d06344 --- /dev/null +++ b/sail_latex_mips/valzsail_maske146b73afc824e90813dd8234bfa3053.tex @@ -0,0 +1 @@ +sail_mask : forall ('len 'v : Int), ('len >= 0 & 'v >= 0). (int('len), bits('v)) -> bits('len) \ No newline at end of file diff --git a/sail_latex_mips/valzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex b/sail_latex_mips/valzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex new file mode 100644 index 00000000..a8014f67 --- /dev/null +++ b/sail_latex_mips/valzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex @@ -0,0 +1 @@ +sail_ones : forall ('n : Int), 'n >= 0. int('n) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzsail_shiftlefta7bc10407d10355c4e981688c9926084.tex b/sail_latex_mips/valzsail_shiftlefta7bc10407d10355c4e981688c9926084.tex new file mode 100644 index 00000000..b4eb800b --- /dev/null +++ b/sail_latex_mips/valzsail_shiftlefta7bc10407d10355c4e981688c9926084.tex @@ -0,0 +1 @@ +sail_shiftleft : forall ('n : Int)('ord : Order). (bitvector('n, 'ord), int) -> bitvector('n, 'ord) \ No newline at end of file diff --git a/sail_latex_mips/valzsail_shiftrighte403ac5c2740b7767c2bdfe689082562.tex b/sail_latex_mips/valzsail_shiftrighte403ac5c2740b7767c2bdfe689082562.tex new file mode 100644 index 00000000..1258f73f --- /dev/null +++ b/sail_latex_mips/valzsail_shiftrighte403ac5c2740b7767c2bdfe689082562.tex @@ -0,0 +1 @@ +sail_shiftright : forall ('n : Int)('ord : Order). (bitvector('n, 'ord), int) -> bitvector('n, 'ord) \ No newline at end of file diff --git a/sail_latex_mips/valzsail_sign_extendb66ac7c1aaedb0cb21bdf07e4518af5e.tex b/sail_latex_mips/valzsail_sign_extendb66ac7c1aaedb0cb21bdf07e4518af5e.tex new file mode 100644 index 00000000..3b61d758 --- /dev/null +++ b/sail_latex_mips/valzsail_sign_extendb66ac7c1aaedb0cb21bdf07e4518af5e.tex @@ -0,0 +1 @@ +sail_sign_extend : forall ('n 'm : Int), 'm >= 'n. (bits('n), int('m)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_mips/valzsail_zzero_extend411875c18d3b332113845d17151890c2.tex b/sail_latex_mips/valzsail_zzero_extend411875c18d3b332113845d17151890c2.tex new file mode 100644 index 00000000..48b6e74e --- /dev/null +++ b/sail_latex_mips/valzsail_zzero_extend411875c18d3b332113845d17151890c2.tex @@ -0,0 +1 @@ +sail_zero_extend : forall ('n 'm : Int), 'm >= 'n. (bits('n), int('m)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_mips/valzsail_zzeros174d4d4928427d9df9fa9749f1df5f96.tex b/sail_latex_mips/valzsail_zzeros174d4d4928427d9df9fa9749f1df5f96.tex new file mode 100644 index 00000000..fee38a4b --- /dev/null +++ b/sail_latex_mips/valzsail_zzeros174d4d4928427d9df9fa9749f1df5f96.tex @@ -0,0 +1 @@ +sail_zeros : forall ('n : Int), 'n >= 0. int('n) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex b/sail_latex_mips/valzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex new file mode 100644 index 00000000..0fcb90b9 --- /dev/null +++ b/sail_latex_mips/valzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex @@ -0,0 +1 @@ +sealCap : (Capability, bits(24)) -> (bool, Capability) \ No newline at end of file diff --git a/sail_latex_mips/valzset_cp0epc28b8527a6fc9d9c7e3708c9379630443.tex b/sail_latex_mips/valzset_cp0epc28b8527a6fc9d9c7e3708c9379630443.tex new file mode 100644 index 00000000..cd65fec6 --- /dev/null +++ b/sail_latex_mips/valzset_cp0epc28b8527a6fc9d9c7e3708c9379630443.tex @@ -0,0 +1 @@ +set_CP0EPC : bits(64) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzset_cp0errorepc99aeab8b8e922eeb71df49885a629b5d.tex b/sail_latex_mips/valzset_cp0errorepc99aeab8b8e922eeb71df49885a629b5d.tex new file mode 100644 index 00000000..396b3256 --- /dev/null +++ b/sail_latex_mips/valzset_cp0errorepc99aeab8b8e922eeb71df49885a629b5d.tex @@ -0,0 +1 @@ +set_CP0ErrorEPC : bits(64) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzset_next_pcce92395a303a64d3216ddb0601b37e83f.tex b/sail_latex_mips/valzset_next_pcce92395a303a64d3216ddb0601b37e83f.tex new file mode 100644 index 00000000..a7a68486 --- /dev/null +++ b/sail_latex_mips/valzset_next_pcce92395a303a64d3216ddb0601b37e83f.tex @@ -0,0 +1 @@ +set_next_pcc : Capability -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzset_slice_bits5956200094c551f35973411fcc90a521.tex b/sail_latex_mips/valzset_slice_bits5956200094c551f35973411fcc90a521.tex new file mode 100644 index 00000000..ef5ed054 --- /dev/null +++ b/sail_latex_mips/valzset_slice_bits5956200094c551f35973411fcc90a521.tex @@ -0,0 +1 @@ +set_slice_bits : forall ('n 'm : Int). (implicit('n), int('m), bits('n), int, bits('m)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzset_slice_intf4b6b0ed3d8b3bb2f2e0d7a492959629.tex b/sail_latex_mips/valzset_slice_intf4b6b0ed3d8b3bb2f2e0d7a492959629.tex new file mode 100644 index 00000000..edb9c5e7 --- /dev/null +++ b/sail_latex_mips/valzset_slice_intf4b6b0ed3d8b3bb2f2e0d7a492959629.tex @@ -0,0 +1 @@ +set_slice_int : forall ('w : Int). (int('w), int, int, bits('w)) -> int \ No newline at end of file diff --git a/sail_latex_mips/valzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex b/sail_latex_mips/valzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex new file mode 100644 index 00000000..11a00b2b --- /dev/null +++ b/sail_latex_mips/valzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex @@ -0,0 +1 @@ +setCapAddr : (Capability, bits(64)) -> (bool, Capability) \ No newline at end of file diff --git a/sail_latex_mips/valzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex b/sail_latex_mips/valzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex new file mode 100644 index 00000000..e3a2b8c7 --- /dev/null +++ b/sail_latex_mips/valzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex @@ -0,0 +1 @@ +setCapBounds : (Capability, bits(64), bits(65)) -> (bool, Capability) \ No newline at end of file diff --git a/sail_latex_mips/valzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex b/sail_latex_mips/valzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex new file mode 100644 index 00000000..b335eb03 --- /dev/null +++ b/sail_latex_mips/valzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex @@ -0,0 +1 @@ +setCapFlags : (Capability, CFlags) -> Capability \ No newline at end of file diff --git a/sail_latex_mips/valzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex b/sail_latex_mips/valzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex new file mode 100644 index 00000000..abc030a7 --- /dev/null +++ b/sail_latex_mips/valzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex @@ -0,0 +1 @@ +setCapOffset : (Capability, bits(64)) -> (bool, Capability) \ No newline at end of file diff --git a/sail_latex_mips/valzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex b/sail_latex_mips/valzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex new file mode 100644 index 00000000..d67f167f --- /dev/null +++ b/sail_latex_mips/valzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex @@ -0,0 +1 @@ +setCapPerms : (Capability, bits(31)) -> Capability \ No newline at end of file diff --git a/sail_latex_mips/valzshift_bits_left0754e8b870e2a3ba46646c35dac7af10.tex b/sail_latex_mips/valzshift_bits_left0754e8b870e2a3ba46646c35dac7af10.tex new file mode 100644 index 00000000..6eb7cdd1 --- /dev/null +++ b/sail_latex_mips/valzshift_bits_left0754e8b870e2a3ba46646c35dac7af10.tex @@ -0,0 +1 @@ +shift_bits_left : forall ('n 'm : Int). (bits('n), bits('m)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzshift_bits_right281f5e6a28fe3c92d35fe5c78a0deb41.tex b/sail_latex_mips/valzshift_bits_right281f5e6a28fe3c92d35fe5c78a0deb41.tex new file mode 100644 index 00000000..390b2b9d --- /dev/null +++ b/sail_latex_mips/valzshift_bits_right281f5e6a28fe3c92d35fe5c78a0deb41.tex @@ -0,0 +1 @@ +shift_bits_right : forall ('n 'm : Int). (bits('n), bits('m)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzshiftl7827d0dcac29bd8258f158e7c1e77658.tex b/sail_latex_mips/valzshiftl7827d0dcac29bd8258f158e7c1e77658.tex new file mode 100644 index 00000000..9d7e4aab --- /dev/null +++ b/sail_latex_mips/valzshiftl7827d0dcac29bd8258f158e7c1e77658.tex @@ -0,0 +1 @@ +shiftl : forall ('m 'n : Int), 'n >= 0. (bits('m), int('n)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_mips/valzshiftr173b7dba7206ed1b61a12344bdf9182a.tex b/sail_latex_mips/valzshiftr173b7dba7206ed1b61a12344bdf9182a.tex new file mode 100644 index 00000000..a875e70b --- /dev/null +++ b/sail_latex_mips/valzshiftr173b7dba7206ed1b61a12344bdf9182a.tex @@ -0,0 +1 @@ +shiftr : forall ('m 'n : Int), 'n >= 0. (bits('m), int('n)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_mips/valzsignalexception586f3a4c7da76085e25c98aff442160c.tex b/sail_latex_mips/valzsignalexception586f3a4c7da76085e25c98aff442160c.tex new file mode 100644 index 00000000..349d7c17 --- /dev/null +++ b/sail_latex_mips/valzsignalexception586f3a4c7da76085e25c98aff442160c.tex @@ -0,0 +1 @@ +SignalException : forall ('o : Type). Exception -> 'o \ No newline at end of file diff --git a/sail_latex_mips/valzsignalexceptionbadaddr6cdef872a446a09f2a94b2675a181fe8.tex b/sail_latex_mips/valzsignalexceptionbadaddr6cdef872a446a09f2a94b2675a181fe8.tex new file mode 100644 index 00000000..5fb4cf41 --- /dev/null +++ b/sail_latex_mips/valzsignalexceptionbadaddr6cdef872a446a09f2a94b2675a181fe8.tex @@ -0,0 +1 @@ +SignalExceptionBadAddr : forall ('o : Type). (Exception, bits(64)) -> 'o \ No newline at end of file diff --git a/sail_latex_mips/valzsignalexceptiontlbddf65d69af94bbb390cc24d557f99883.tex b/sail_latex_mips/valzsignalexceptiontlbddf65d69af94bbb390cc24d557f99883.tex new file mode 100644 index 00000000..2f1ee99f --- /dev/null +++ b/sail_latex_mips/valzsignalexceptiontlbddf65d69af94bbb390cc24d557f99883.tex @@ -0,0 +1 @@ +SignalExceptionTLB : forall ('o : Type). (Exception, bits(64)) -> 'o \ No newline at end of file diff --git a/sail_latex_mips/valzsigned36d2317f34f1dacb4e465e6e56b185e6.tex b/sail_latex_mips/valzsigned36d2317f34f1dacb4e465e6e56b185e6.tex new file mode 100644 index 00000000..75b658cf --- /dev/null +++ b/sail_latex_mips/valzsigned36d2317f34f1dacb4e465e6e56b185e6.tex @@ -0,0 +1 @@ +signed : forall ('n : Int), 'n > 0. bits('n) -> range(- (2 ^ ('n - 1)), 2 ^ ('n - 1) - 1) \ No newline at end of file diff --git a/sail_latex_mips/valzskip_barrca673f4460442e7803a2c93bd2aef700.tex b/sail_latex_mips/valzskip_barrca673f4460442e7803a2c93bd2aef700.tex new file mode 100644 index 00000000..039d5137 --- /dev/null +++ b/sail_latex_mips/valzskip_barrca673f4460442e7803a2c93bd2aef700.tex @@ -0,0 +1 @@ +skip_barr : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzskip_eamem49a4d980d609bd796bfdb904e8da6711.tex b/sail_latex_mips/valzskip_eamem49a4d980d609bd796bfdb904e8da6711.tex new file mode 100644 index 00000000..e36126d8 --- /dev/null +++ b/sail_latex_mips/valzskip_eamem49a4d980d609bd796bfdb904e8da6711.tex @@ -0,0 +1 @@ +skip_eamem : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzskip_escape40337081b9eda6abe558d971128fc98c.tex b/sail_latex_mips/valzskip_escape40337081b9eda6abe558d971128fc98c.tex new file mode 100644 index 00000000..57d6561f --- /dev/null +++ b/sail_latex_mips/valzskip_escape40337081b9eda6abe558d971128fc98c.tex @@ -0,0 +1 @@ +skip_escape : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzskip_rmemt7f62986f7ef50679aaa016cb24b25d65.tex b/sail_latex_mips/valzskip_rmemt7f62986f7ef50679aaa016cb24b25d65.tex new file mode 100644 index 00000000..ffe62779 --- /dev/null +++ b/sail_latex_mips/valzskip_rmemt7f62986f7ef50679aaa016cb24b25d65.tex @@ -0,0 +1 @@ +skip_rmemt : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzskip_rreg6c7d871275e33b7ca21079a068ab8ac7.tex b/sail_latex_mips/valzskip_rreg6c7d871275e33b7ca21079a068ab8ac7.tex new file mode 100644 index 00000000..5de52cfa --- /dev/null +++ b/sail_latex_mips/valzskip_rreg6c7d871275e33b7ca21079a068ab8ac7.tex @@ -0,0 +1 @@ +skip_rreg : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzskip_wmvtf5881f8ed4b4116848ad7bdbc67bd918.tex b/sail_latex_mips/valzskip_wmvtf5881f8ed4b4116848ad7bdbc67bd918.tex new file mode 100644 index 00000000..4ba7b277 --- /dev/null +++ b/sail_latex_mips/valzskip_wmvtf5881f8ed4b4116848ad7bdbc67bd918.tex @@ -0,0 +1 @@ +skip_wmvt : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzskip_wregb2a3498732e32cc0df842c55bfcee6e1.tex b/sail_latex_mips/valzskip_wregb2a3498732e32cc0df842c55bfcee6e1.tex new file mode 100644 index 00000000..9283cbda --- /dev/null +++ b/sail_latex_mips/valzskip_wregb2a3498732e32cc0df842c55bfcee6e1.tex @@ -0,0 +1 @@ +skip_wreg : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzslice9979e992fd48f77a2c3fef7fbcce068e.tex b/sail_latex_mips/valzslice9979e992fd48f77a2c3fef7fbcce068e.tex new file mode 100644 index 00000000..f7f53244 --- /dev/null +++ b/sail_latex_mips/valzslice9979e992fd48f77a2c3fef7fbcce068e.tex @@ -0,0 +1 @@ +slice : forall ('n 'm 'o : Int), (0 <= 'm & 0 <= 'n). (bits('m), int('o), int('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex b/sail_latex_mips/valzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex new file mode 100644 index 00000000..77bf7c81 --- /dev/null +++ b/sail_latex_mips/valzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex @@ -0,0 +1 @@ +slice_mask : forall ('n : Int), 'n >= 0. (implicit('n), int, int) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzstrccargs8d27f740eb5185eb67906b78fb166677.tex b/sail_latex_mips/valzstrccargs8d27f740eb5185eb67906b78fb166677.tex new file mode 100644 index 00000000..688ec070 --- /dev/null +++ b/sail_latex_mips/valzstrccargs8d27f740eb5185eb67906b78fb166677.tex @@ -0,0 +1 @@ +strCCArgs : (CapRegEnc, CapRegEnc) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrcccargsd0cf13cbe0c477ce0624778eee44a85e.tex b/sail_latex_mips/valzstrcccargsd0cf13cbe0c477ce0624778eee44a85e.tex new file mode 100644 index 00000000..78d71612 --- /dev/null +++ b/sail_latex_mips/valzstrcccargsd0cf13cbe0c477ce0624778eee44a85e.tex @@ -0,0 +1 @@ +strCCCArgs : (CapRegEnc, CapRegEnc, CapRegEnc) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrcciargs33bcd057cc20ec3a9ddc520c721764a9.tex b/sail_latex_mips/valzstrcciargs33bcd057cc20ec3a9ddc520c721764a9.tex new file mode 100644 index 00000000..6e28682f --- /dev/null +++ b/sail_latex_mips/valzstrcciargs33bcd057cc20ec3a9ddc520c721764a9.tex @@ -0,0 +1 @@ +strCCIArgs : forall ('n : Int), 'n > 0. (regno, regno, bits('n)) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrcciuargs995341ac60a90e598fe5209db4db77a3.tex b/sail_latex_mips/valzstrcciuargs995341ac60a90e598fe5209db4db77a3.tex new file mode 100644 index 00000000..8ad28308 --- /dev/null +++ b/sail_latex_mips/valzstrcciuargs995341ac60a90e598fe5209db4db77a3.tex @@ -0,0 +1 @@ +strCCIUArgs : forall ('n : Int), 'n > 0. (regno, regno, bits('n)) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrccrargs496b2890b8e21e5bd6d7197ea4c075c8.tex b/sail_latex_mips/valzstrccrargs496b2890b8e21e5bd6d7197ea4c075c8.tex new file mode 100644 index 00000000..10e88090 --- /dev/null +++ b/sail_latex_mips/valzstrccrargs496b2890b8e21e5bd6d7197ea4c075c8.tex @@ -0,0 +1 @@ +strCCRArgs : (CapRegEnc, CapRegEnc, IntRegEnc) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrcmp377172000af45c28fe84b78c43e6af4d.tex b/sail_latex_mips/valzstrcmp377172000af45c28fe84b78c43e6af4d.tex new file mode 100644 index 00000000..ca9279aa --- /dev/null +++ b/sail_latex_mips/valzstrcmp377172000af45c28fe84b78c43e6af4d.tex @@ -0,0 +1 @@ +strCmp : Comparison -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrcrargsa5dba43a853a6048828d7d473fcaedfb.tex b/sail_latex_mips/valzstrcrargsa5dba43a853a6048828d7d473fcaedfb.tex new file mode 100644 index 00000000..73f2d22f --- /dev/null +++ b/sail_latex_mips/valzstrcrargsa5dba43a853a6048828d7d473fcaedfb.tex @@ -0,0 +1 @@ +strCRArgs : (CapRegEnc, IntRegEnc) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrcreg6eee441123c442c07d3b63b65e2c6a32.tex b/sail_latex_mips/valzstrcreg6eee441123c442c07d3b63b65e2c6a32.tex new file mode 100644 index 00000000..64c72f19 --- /dev/null +++ b/sail_latex_mips/valzstrcreg6eee441123c442c07d3b63b65e2c6a32.tex @@ -0,0 +1 @@ +strCReg : regno -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex b/sail_latex_mips/valzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex new file mode 100644 index 00000000..c4eb2fa9 --- /dev/null +++ b/sail_latex_mips/valzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex @@ -0,0 +1 @@ +string_of_capex : CapEx -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstring_of_exception7734103b8f1c3a7c884e4dea77d7cf9d.tex b/sail_latex_mips/valzstring_of_exception7734103b8f1c3a7c884e4dea77d7cf9d.tex new file mode 100644 index 00000000..1ac5d10f --- /dev/null +++ b/sail_latex_mips/valzstring_of_exception7734103b8f1c3a7c884e4dea77d7cf9d.tex @@ -0,0 +1 @@ +string_of_exception : Exception -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstring_of_int03988e4e2d2976513793427ac823afbe.tex b/sail_latex_mips/valzstring_of_int03988e4e2d2976513793427ac823afbe.tex new file mode 100644 index 00000000..69edce40 --- /dev/null +++ b/sail_latex_mips/valzstring_of_int03988e4e2d2976513793427ac823afbe.tex @@ -0,0 +1 @@ +string_of_int : int -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrmemargs353ff7043a1935f05717327694c74036.tex b/sail_latex_mips/valzstrmemargs353ff7043a1935f05717327694c74036.tex new file mode 100644 index 00000000..5606688a --- /dev/null +++ b/sail_latex_mips/valzstrmemargs353ff7043a1935f05717327694c74036.tex @@ -0,0 +1 @@ +strMemArgs : forall ('n : Int), 'n > 0. (regno, regno, bits('n)) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrrcargs77cbd4ae00a8aeed40f03673c45f3bf3.tex b/sail_latex_mips/valzstrrcargs77cbd4ae00a8aeed40f03673c45f3bf3.tex new file mode 100644 index 00000000..398a5872 --- /dev/null +++ b/sail_latex_mips/valzstrrcargs77cbd4ae00a8aeed40f03673c45f3bf3.tex @@ -0,0 +1 @@ +strRCArgs : (IntRegEnc, CapRegEnc) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrrccargscb2c61998351777a60f6fb0c1be5bc73.tex b/sail_latex_mips/valzstrrccargscb2c61998351777a60f6fb0c1be5bc73.tex new file mode 100644 index 00000000..96b6d1e8 --- /dev/null +++ b/sail_latex_mips/valzstrrccargscb2c61998351777a60f6fb0c1be5bc73.tex @@ -0,0 +1 @@ +strRCCArgs : (IntRegEnc, CapRegEnc, CapRegEnc) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrrcrargs2a6690343bcd1d4f5aaa9410842cee4f.tex b/sail_latex_mips/valzstrrcrargs2a6690343bcd1d4f5aaa9410842cee4f.tex new file mode 100644 index 00000000..688d107e --- /dev/null +++ b/sail_latex_mips/valzstrrcrargs2a6690343bcd1d4f5aaa9410842cee4f.tex @@ -0,0 +1 @@ +strRCRArgs : (IntRegEnc, CapRegEnc, IntRegEnc) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrregedcb07cf94fecef4256c866403497f4d.tex b/sail_latex_mips/valzstrregedcb07cf94fecef4256c866403497f4d.tex new file mode 100644 index 00000000..6d9e7d36 --- /dev/null +++ b/sail_latex_mips/valzstrregedcb07cf94fecef4256c866403497f4d.tex @@ -0,0 +1 @@ +strReg : regno -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrriargsf5ce4d067df93e7be3e1beacd5b4d9a7.tex b/sail_latex_mips/valzstrriargsf5ce4d067df93e7be3e1beacd5b4d9a7.tex new file mode 100644 index 00000000..6526b6fc --- /dev/null +++ b/sail_latex_mips/valzstrriargsf5ce4d067df93e7be3e1beacd5b4d9a7.tex @@ -0,0 +1 @@ +strRIArgs : forall ('n : Int), 'n > 0. (regno, bits('n)) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrrrargs01af3a4171de69de622a434d53850810.tex b/sail_latex_mips/valzstrrrargs01af3a4171de69de622a434d53850810.tex new file mode 100644 index 00000000..606f5b03 --- /dev/null +++ b/sail_latex_mips/valzstrrrargs01af3a4171de69de622a434d53850810.tex @@ -0,0 +1 @@ +strRRArgs : (IntRegEnc, IntRegEnc) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrrriargs4a7c2ee7b410ff0bb51f74553cdca297.tex b/sail_latex_mips/valzstrrriargs4a7c2ee7b410ff0bb51f74553cdca297.tex new file mode 100644 index 00000000..d19d91df --- /dev/null +++ b/sail_latex_mips/valzstrrriargs4a7c2ee7b410ff0bb51f74553cdca297.tex @@ -0,0 +1 @@ +strRRIArgs : forall ('n : Int), 'n > 0. (regno, regno, bits('n)) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrrriuargs3f59ed041a358c4238ca651c777a80e7.tex b/sail_latex_mips/valzstrrriuargs3f59ed041a358c4238ca651c777a80e7.tex new file mode 100644 index 00000000..4b34275d --- /dev/null +++ b/sail_latex_mips/valzstrrriuargs3f59ed041a358c4238ca651c777a80e7.tex @@ -0,0 +1 @@ +strRRIUArgs : forall ('n : Int), 'n > 0. (regno, regno, bits('n)) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrrrrargsfab462065fa0ad4bda2870b02f212fd9.tex b/sail_latex_mips/valzstrrrrargsfab462065fa0ad4bda2870b02f212fd9.tex new file mode 100644 index 00000000..a8c1408b --- /dev/null +++ b/sail_latex_mips/valzstrrrrargsfab462065fa0ad4bda2870b02f212fd9.tex @@ -0,0 +1 @@ +strRRRArgs : (regno, regno, regno) -> string \ No newline at end of file diff --git a/sail_latex_mips/valzstrwordtype0dceaa7680ceade7afd7f75be57ac461.tex b/sail_latex_mips/valzstrwordtype0dceaa7680ceade7afd7f75be57ac461.tex new file mode 100644 index 00000000..246d453e --- /dev/null +++ b/sail_latex_mips/valzstrwordtype0dceaa7680ceade7afd7f75be57ac461.tex @@ -0,0 +1 @@ +strWordType : WordType -> string \ No newline at end of file diff --git a/sail_latex_mips/valzsub_atom328a68dfbab1a07c42d4e7b98eac766f.tex b/sail_latex_mips/valzsub_atom328a68dfbab1a07c42d4e7b98eac766f.tex new file mode 100644 index 00000000..d7664a15 --- /dev/null +++ b/sail_latex_mips/valzsub_atom328a68dfbab1a07c42d4e7b98eac766f.tex @@ -0,0 +1 @@ +sub_atom : forall ('n 'm : Int). (int('n), int('m)) -> int('n - 'm) \ No newline at end of file diff --git a/sail_latex_mips/valzsub_bitsf0dc4fc3429d45517c523db21af72127.tex b/sail_latex_mips/valzsub_bitsf0dc4fc3429d45517c523db21af72127.tex new file mode 100644 index 00000000..c3992272 --- /dev/null +++ b/sail_latex_mips/valzsub_bitsf0dc4fc3429d45517c523db21af72127.tex @@ -0,0 +1 @@ +sub_bits : forall ('n : Int). (bits('n), bits('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzsub_intf17f348f33594e77fdc3ef8b6a46b569.tex b/sail_latex_mips/valzsub_intf17f348f33594e77fdc3ef8b6a46b569.tex new file mode 100644 index 00000000..2cf1aebc --- /dev/null +++ b/sail_latex_mips/valzsub_intf17f348f33594e77fdc3ef8b6a46b569.tex @@ -0,0 +1 @@ +sub_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valzsub_nat1e51a6ef44b288dd12f7f69af44dfd3e.tex b/sail_latex_mips/valzsub_nat1e51a6ef44b288dd12f7f69af44dfd3e.tex new file mode 100644 index 00000000..379f1121 --- /dev/null +++ b/sail_latex_mips/valzsub_nat1e51a6ef44b288dd12f7f69af44dfd3e.tex @@ -0,0 +1 @@ +sub_nat : (nat, nat) -> nat \ No newline at end of file diff --git a/sail_latex_mips/valzsub_range14f5685922761f99e3753835c40db01f.tex b/sail_latex_mips/valzsub_range14f5685922761f99e3753835c40db01f.tex new file mode 100644 index 00000000..31045e1e --- /dev/null +++ b/sail_latex_mips/valzsub_range14f5685922761f99e3753835c40db01f.tex @@ -0,0 +1 @@ +sub_range : forall ('n 'm 'o 'p : Int). (range('n, 'm), range('o, 'p)) -> range('n - 'p, 'm - 'o) \ No newline at end of file diff --git a/sail_latex_mips/valzsub_vec326e0ba0bb00229be26645e2d44dbd83.tex b/sail_latex_mips/valzsub_vec326e0ba0bb00229be26645e2d44dbd83.tex new file mode 100644 index 00000000..b62484d5 --- /dev/null +++ b/sail_latex_mips/valzsub_vec326e0ba0bb00229be26645e2d44dbd83.tex @@ -0,0 +1 @@ +sub_vec : forall ('n : Int). (bits('n), bits('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzsub_vec_int5e6c04459782b1b8cc706ba2e4c8a435.tex b/sail_latex_mips/valzsub_vec_int5e6c04459782b1b8cc706ba2e4c8a435.tex new file mode 100644 index 00000000..568790f9 --- /dev/null +++ b/sail_latex_mips/valzsub_vec_int5e6c04459782b1b8cc706ba2e4c8a435.tex @@ -0,0 +1 @@ +sub_vec_int : forall ('n : Int). (bits('n), int) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzsubrange_bits6c497c14df4f4754bd345a6c56ca2aad.tex b/sail_latex_mips/valzsubrange_bits6c497c14df4f4754bd345a6c56ca2aad.tex new file mode 100644 index 00000000..8ca82640 --- /dev/null +++ b/sail_latex_mips/valzsubrange_bits6c497c14df4f4754bd345a6c56ca2aad.tex @@ -0,0 +1,2 @@ +subrange_bits : forall ('n 'm 'o : Int), (0 <= 'o & 'o <= 'm & 'm < 'n). + (bits('n), int('m), int('o)) -> bits('m - 'o + 1) \ No newline at end of file diff --git a/sail_latex_mips/valzsupported_instructionsa556d55bb4bf818f15e811f8fa119862.tex b/sail_latex_mips/valzsupported_instructionsa556d55bb4bf818f15e811f8fa119862.tex new file mode 100644 index 00000000..b3377d57 --- /dev/null +++ b/sail_latex_mips/valzsupported_instructionsa556d55bb4bf818f15e811f8fa119862.tex @@ -0,0 +1 @@ +supported_instructions : ast -> option(ast) \ No newline at end of file diff --git a/sail_latex_mips/valztdiv_int5e119ac7ab9ff04c8877846f345d1159.tex b/sail_latex_mips/valztdiv_int5e119ac7ab9ff04c8877846f345d1159.tex new file mode 100644 index 00000000..7d77e1a1 --- /dev/null +++ b/sail_latex_mips/valztdiv_int5e119ac7ab9ff04c8877846f345d1159.tex @@ -0,0 +1 @@ +tdiv_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_mips/valztlbentrymatch022ae8f81d6f9221e858534a26d34f7f.tex b/sail_latex_mips/valztlbentrymatch022ae8f81d6f9221e858534a26d34f7f.tex new file mode 100644 index 00000000..36c0cf85 --- /dev/null +++ b/sail_latex_mips/valztlbentrymatch022ae8f81d6f9221e858534a26d34f7f.tex @@ -0,0 +1 @@ +tlbEntryMatch : (bits(2), bits(27), bits(8), TLBEntry) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valztlbsearchccbd0fc555e67dbea1dd6e8748394f51.tex b/sail_latex_mips/valztlbsearchccbd0fc555e67dbea1dd6e8748394f51.tex new file mode 100644 index 00000000..6162e977 --- /dev/null +++ b/sail_latex_mips/valztlbsearchccbd0fc555e67dbea1dd6e8748394f51.tex @@ -0,0 +1 @@ +tlbSearch : bits(64) -> option(TLBIndexT) \ No newline at end of file diff --git a/sail_latex_mips/valztlbtranslate2472aa8aca18a66cca2beeaa89cbec740.tex b/sail_latex_mips/valztlbtranslate2472aa8aca18a66cca2beeaa89cbec740.tex new file mode 100644 index 00000000..5db514f9 --- /dev/null +++ b/sail_latex_mips/valztlbtranslate2472aa8aca18a66cca2beeaa89cbec740.tex @@ -0,0 +1 @@ +TLBTranslate2 : (bits(64), MemAccessType, AccessLevel) -> (bits(64), MemAccessCapRestriction) \ No newline at end of file diff --git a/sail_latex_mips/valztlbtranslateccd99b29205e9558b4443d89bd7791f84.tex b/sail_latex_mips/valztlbtranslateccd99b29205e9558b4443d89bd7791f84.tex new file mode 100644 index 00000000..f54612e4 --- /dev/null +++ b/sail_latex_mips/valztlbtranslateccd99b29205e9558b4443d89bd7791f84.tex @@ -0,0 +1 @@ +TLBTranslateC : (bits(64), MemAccessType) -> (bits(64), MemAccessCapRestriction) \ No newline at end of file diff --git a/sail_latex_mips/valztlbtranslateea36ded227d6adddf8c6c2ae662895be.tex b/sail_latex_mips/valztlbtranslateea36ded227d6adddf8c6c2ae662895be.tex new file mode 100644 index 00000000..933c4aae --- /dev/null +++ b/sail_latex_mips/valztlbtranslateea36ded227d6adddf8c6c2ae662895be.tex @@ -0,0 +1 @@ +TLBTranslate : (bits(64), MemAccessType) -> bits(64) \ No newline at end of file diff --git a/sail_latex_mips/valzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex b/sail_latex_mips/valzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex new file mode 100644 index 00000000..e8880e05 --- /dev/null +++ b/sail_latex_mips/valzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex @@ -0,0 +1 @@ +to_bits : forall ('l : Int), 'l >= 0. (int('l), int) -> bits('l) \ No newline at end of file diff --git a/sail_latex_mips/valztraceexceptiond1f5e2367606477eb2b33940325e3e87.tex b/sail_latex_mips/valztraceexceptiond1f5e2367606477eb2b33940325e3e87.tex new file mode 100644 index 00000000..c096eb89 --- /dev/null +++ b/sail_latex_mips/valztraceexceptiond1f5e2367606477eb2b33940325e3e87.tex @@ -0,0 +1 @@ +traceException : Exception -> unit \ No newline at end of file diff --git a/sail_latex_mips/valztranslatepca9eb30b515fe139216afcb3a9118ead3.tex b/sail_latex_mips/valztranslatepca9eb30b515fe139216afcb3a9118ead3.tex new file mode 100644 index 00000000..5c185312 --- /dev/null +++ b/sail_latex_mips/valztranslatepca9eb30b515fe139216afcb3a9118ead3.tex @@ -0,0 +1 @@ +TranslatePC : bits(64) -> bits(64) \ No newline at end of file diff --git a/sail_latex_mips/valztruncatea666e28ae0c8ca7327a2b3fcd1ed4ec7.tex b/sail_latex_mips/valztruncatea666e28ae0c8ca7327a2b3fcd1ed4ec7.tex new file mode 100644 index 00000000..75765ea7 --- /dev/null +++ b/sail_latex_mips/valztruncatea666e28ae0c8ca7327a2b3fcd1ed4ec7.tex @@ -0,0 +1 @@ +truncate : forall ('m 'n : Int), ('m >= 0 & 'm <= 'n). (bits('n), int('m)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_mips/valztruncatelsb4d124c6ec672453343dc0b20d295e82d.tex b/sail_latex_mips/valztruncatelsb4d124c6ec672453343dc0b20d295e82d.tex new file mode 100644 index 00000000..0718e5ba --- /dev/null +++ b/sail_latex_mips/valztruncatelsb4d124c6ec672453343dc0b20d295e82d.tex @@ -0,0 +1 @@ +truncateLSB : forall ('m 'n : Int), ('m >= 0 & 'm <= 'n). (bits('n), int('m)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_mips/valzunalignedbytestouched30e9b9e5c4f2d5085ce71a02d1964f0c.tex b/sail_latex_mips/valzunalignedbytestouched30e9b9e5c4f2d5085ce71a02d1964f0c.tex new file mode 100644 index 00000000..171e4ed1 --- /dev/null +++ b/sail_latex_mips/valzunalignedbytestouched30e9b9e5c4f2d5085ce71a02d1964f0c.tex @@ -0,0 +1 @@ +unalignedBytesTouched : (int, WordTypeUnaligned) -> (int, int) \ No newline at end of file diff --git a/sail_latex_mips/valzunrepcap312d66f4391d908cc0a7a87a38e8881a.tex b/sail_latex_mips/valzunrepcap312d66f4391d908cc0a7a87a38e8881a.tex new file mode 100644 index 00000000..13fcebb1 --- /dev/null +++ b/sail_latex_mips/valzunrepcap312d66f4391d908cc0a7a87a38e8881a.tex @@ -0,0 +1 @@ +unrepCap : Capability -> Capability \ No newline at end of file diff --git a/sail_latex_mips/valzunsealcap58689ae49a7317c60147327414a678d2.tex b/sail_latex_mips/valzunsealcap58689ae49a7317c60147327414a678d2.tex new file mode 100644 index 00000000..915a917d --- /dev/null +++ b/sail_latex_mips/valzunsealcap58689ae49a7317c60147327414a678d2.tex @@ -0,0 +1 @@ +unsealCap : Capability -> Capability \ No newline at end of file diff --git a/sail_latex_mips/valzunsigned1010eda2cdd2666cd8fd0ddf82ac526f.tex b/sail_latex_mips/valzunsigned1010eda2cdd2666cd8fd0ddf82ac526f.tex new file mode 100644 index 00000000..2bf99f64 --- /dev/null +++ b/sail_latex_mips/valzunsigned1010eda2cdd2666cd8fd0ddf82ac526f.tex @@ -0,0 +1 @@ +unsigned : forall ('n : Int). bits('n) -> range(0, 2 ^ 'n - 1) \ No newline at end of file diff --git a/sail_latex_mips/valzupdate_subrange_bitsb5ffe862b26310b45a779cd45bbf041e.tex b/sail_latex_mips/valzupdate_subrange_bitsb5ffe862b26310b45a779cd45bbf041e.tex new file mode 100644 index 00000000..7757278d --- /dev/null +++ b/sail_latex_mips/valzupdate_subrange_bitsb5ffe862b26310b45a779cd45bbf041e.tex @@ -0,0 +1,2 @@ +update_subrange_bits : forall ('n 'm 'o : Int), (0 <= 'o & 'o <= 'm & 'm < 'n). + (bits('n), int('m), int('o), bits('m - ('o - 1))) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzupdatebadinstr950852e9ede642484051c5622ba3c67c.tex b/sail_latex_mips/valzupdatebadinstr950852e9ede642484051c5622ba3c67c.tex new file mode 100644 index 00000000..02dd1d5c --- /dev/null +++ b/sail_latex_mips/valzupdatebadinstr950852e9ede642484051c5622ba3c67c.tex @@ -0,0 +1 @@ +updateBadInstr : unit -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzvector_length9ee541b308cdfd9738d44bfb3dff4b46.tex b/sail_latex_mips/valzvector_length9ee541b308cdfd9738d44bfb3dff4b46.tex new file mode 100644 index 00000000..ccbbb261 --- /dev/null +++ b/sail_latex_mips/valzvector_length9ee541b308cdfd9738d44bfb3dff4b46.tex @@ -0,0 +1 @@ +vector_length : forall ('n : Int)('a : Type). vector('n, dec, 'a) -> int('n) \ No newline at end of file diff --git a/sail_latex_mips/valzwgpra4abc6baa21fcdee487f02c739ccf251.tex b/sail_latex_mips/valzwgpra4abc6baa21fcdee487f02c739ccf251.tex new file mode 100644 index 00000000..1274ae0e --- /dev/null +++ b/sail_latex_mips/valzwgpra4abc6baa21fcdee487f02c739ccf251.tex @@ -0,0 +1 @@ +wGPR : (bits(5), bits(64)) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzwordtype_of_num3fb8b8a30f6fb7e01768c7e63da4fa79.tex b/sail_latex_mips/valzwordtype_of_num3fb8b8a30f6fb7e01768c7e63da4fa79.tex new file mode 100644 index 00000000..01e3be75 --- /dev/null +++ b/sail_latex_mips/valzwordtype_of_num3fb8b8a30f6fb7e01768c7e63da4fa79.tex @@ -0,0 +1 @@ +WordType_of_num : forall ('e : Int), (0 <= 'e & 'e <= 3). int('e) -> WordType \ No newline at end of file diff --git a/sail_latex_mips/valzwordtypeunaligned_of_num9534254c2a95ab15ea143c0eb1f767d5.tex b/sail_latex_mips/valzwordtypeunaligned_of_num9534254c2a95ab15ea143c0eb1f767d5.tex new file mode 100644 index 00000000..50f5ae54 --- /dev/null +++ b/sail_latex_mips/valzwordtypeunaligned_of_num9534254c2a95ab15ea143c0eb1f767d5.tex @@ -0,0 +1 @@ +WordTypeUnaligned_of_num : forall ('e : Int), (0 <= 'e & 'e <= 3). int('e) -> WordTypeUnaligned \ No newline at end of file diff --git a/sail_latex_mips/valzwordwidthbyteseabb026e3f94d82320b5d4a77ee9fcc4.tex b/sail_latex_mips/valzwordwidthbyteseabb026e3f94d82320b5d4a77ee9fcc4.tex new file mode 100644 index 00000000..82796cf7 --- /dev/null +++ b/sail_latex_mips/valzwordwidthbyteseabb026e3f94d82320b5d4a77ee9fcc4.tex @@ -0,0 +1 @@ +wordWidthBytes : WordType -> range(1, 8) \ No newline at end of file diff --git a/sail_latex_mips/valzwrite_tag_bool760f89ee258516fba3e938c2e532f5b8.tex b/sail_latex_mips/valzwrite_tag_bool760f89ee258516fba3e938c2e532f5b8.tex new file mode 100644 index 00000000..bffcaaad --- /dev/null +++ b/sail_latex_mips/valzwrite_tag_bool760f89ee258516fba3e938c2e532f5b8.tex @@ -0,0 +1 @@ +write_tag_bool : (bits(64), bool) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzwritecapreg902f20f3d4ba5384b97aa04a7a1756f4.tex b/sail_latex_mips/valzwritecapreg902f20f3d4ba5384b97aa04a7a1756f4.tex new file mode 100644 index 00000000..3d552307 --- /dev/null +++ b/sail_latex_mips/valzwritecapreg902f20f3d4ba5384b97aa04a7a1756f4.tex @@ -0,0 +1 @@ +writeCapReg : (regno, Capability) -> unit \ No newline at end of file diff --git a/sail_latex_mips/valzxor_vecdacd54acc32f073fb01d1c188177bc8c.tex b/sail_latex_mips/valzxor_vecdacd54acc32f073fb01d1c188177bc8c.tex new file mode 100644 index 00000000..6a07449f --- /dev/null +++ b/sail_latex_mips/valzxor_vecdacd54acc32f073fb01d1c188177bc8c.tex @@ -0,0 +1 @@ +xor_vec : forall ('n : Int). (bits('n), bits('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzz8operatorz0za_sz9e046109c9d98ebd1683e514a3e2f3f5d.tex b/sail_latex_mips/valzz8operatorz0za_sz9e046109c9d98ebd1683e514a3e2f3f5d.tex new file mode 100644 index 00000000..13e66d84 --- /dev/null +++ b/sail_latex_mips/valzz8operatorz0za_sz9e046109c9d98ebd1683e514a3e2f3f5d.tex @@ -0,0 +1 @@ +operator *_s : forall ('n : Int). (bits('n), bits('n)) -> bits(2 * 'n) \ No newline at end of file diff --git a/sail_latex_mips/valzz8operatorz0za_uz98194b6fb241100892f8fe90018275deb.tex b/sail_latex_mips/valzz8operatorz0za_uz98194b6fb241100892f8fe90018275deb.tex new file mode 100644 index 00000000..2f1a7183 --- /dev/null +++ b/sail_latex_mips/valzz8operatorz0za_uz98194b6fb241100892f8fe90018275deb.tex @@ -0,0 +1 @@ +operator *_u : forall ('n : Int). (bits('n), bits('n)) -> bits(2 * 'n) \ No newline at end of file diff --git a/sail_latex_mips/valzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex b/sail_latex_mips/valzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex new file mode 100644 index 00000000..4248cb4d --- /dev/null +++ b/sail_latex_mips/valzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex @@ -0,0 +1 @@ +operator <_s : forall ('n : Int), 'n > 0. (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex b/sail_latex_mips/valzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex new file mode 100644 index 00000000..5b0ee02f --- /dev/null +++ b/sail_latex_mips/valzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex @@ -0,0 +1 @@ +operator <_u : forall ('n : Int), 'n >= 0. (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex b/sail_latex_mips/valzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex new file mode 100644 index 00000000..28d0949c --- /dev/null +++ b/sail_latex_mips/valzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex @@ -0,0 +1 @@ +operator >=_s : forall ('n : Int), 'n > 0. (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex b/sail_latex_mips/valzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex new file mode 100644 index 00000000..72d97551 --- /dev/null +++ b/sail_latex_mips/valzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex @@ -0,0 +1 @@ +operator >=_u : forall ('n : Int), 'n >= 0. (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_mips/valzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex b/sail_latex_mips/valzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex new file mode 100644 index 00000000..85e239f5 --- /dev/null +++ b/sail_latex_mips/valzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex @@ -0,0 +1 @@ +operator >>_s : forall ('n 'm : Int). (bits('n), bits('m)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/valzz8operatorz0zqzqz93d1b5248b83463c11188367c0486a3fd.tex b/sail_latex_mips/valzz8operatorz0zqzqz93d1b5248b83463c11188367c0486a3fd.tex new file mode 100644 index 00000000..b2a9d772 --- /dev/null +++ b/sail_latex_mips/valzz8operatorz0zqzqz93d1b5248b83463c11188367c0486a3fd.tex @@ -0,0 +1 @@ +operator ^^ : forall ('n 'm : Int), 'm >= 0. (bits('n), int('m)) -> bits('n * 'm) \ No newline at end of file diff --git a/sail_latex_mips/valzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex b/sail_latex_mips/valzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex new file mode 100644 index 00000000..eb0e9d1a --- /dev/null +++ b/sail_latex_mips/valzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex @@ -0,0 +1 @@ +zeros_implicit : forall ('n : Int), 'n >= 0. (implicit('n), unit) -> bits('n) \ No newline at end of file diff --git a/sail_latex_mips/zGENERATED_FILES_DO_NOT_EDIT b/sail_latex_mips/zGENERATED_FILES_DO_NOT_EDIT new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/0GENERATED_FILES_DO_NOT_EDIT b/sail_latex_riscv/0GENERATED_FILES_DO_NOT_EDIT new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/block7c9393e4ce2c29e4e1dc024db508cec2.sail b/sail_latex_riscv/block7c9393e4ce2c29e4e1dc024db508cec2.sail new file mode 100644 index 00000000..4201c101 --- /dev/null +++ b/sail_latex_riscv/block7c9393e4ce2c29e4e1dc024db508cec2.sail @@ -0,0 +1 @@ +let elsize = shl_int(8, UInt(size)) \ No newline at end of file diff --git a/sail_latex_riscv/commands.tex b/sail_latex_riscv/commands.tex new file mode 100644 index 00000000..551c4a44 --- /dev/null +++ b/sail_latex_riscv/commands.tex @@ -0,0 +1,14476 @@ +\providecommand\saildoclabelled[2]{\phantomsection\label{#1}#2} +\providecommand\saildocval[2]{#1 #2} +\providecommand\saildocfcl[2]{#1 #2} +\providecommand\saildoctype[2]{#1 #2} +\providecommand\saildocfn[2]{#1 #2} +\providecommand\saildocoverload[2]{#1 #2} +\providecommand\saildocabbrev[1]{#1\@} + +\newcommand{\sailRISCVvaledivInt}{\saildoclabelled{sailRISCVzedivzyint}{\saildocval{Euclidean division + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valzediv_int5aaf4d3d5a3d15a7aebaf90d3bfb6650.tex}}}} + +\newcommand{\sailRISCVvalemodInt}{\saildoclabelled{sailRISCVzemodzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzemod_int8e3d74b3b6a72e24e6bd03570d8e21ba.tex}}}} + +\newcommand{\sailRISCVvalabsIntAtom}{\saildoclabelled{sailRISCVzabszyintzyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzabs_int_atom414063313cc5ac5d9a742f9c8a111704.tex}}}} + +\newcommand{\sailRISCVoverloadBabsInt}{\saildoclabelled{sailRISCVoverloadBzabszyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBzabs_intef5fbb521189282054dc80dc7173013d.tex}}}} + +\newcommand{\sailRISCVtypeoption}{\saildoclabelled{sailRISCVtypezoption}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezoptiona3271ef8b6a63c78e6db36dac0ee6547.tex}}}} + +\newcommand{\sailRISCVvalisNone}{\saildoclabelled{sailRISCVziszynone}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzis_nonebebf4558161c4d567fb50f7df9e82374.tex}}}} + +\newcommand{\sailRISCVfnisNone}{\saildoclabelled{sailRISCVfnziszynone}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzis_nonebebf4558161c4d567fb50f7df9e82374.tex}}}} + +\newcommand{\sailRISCVvalisSome}{\saildoclabelled{sailRISCVziszysome}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex}}}} + +\newcommand{\sailRISCVfnisSome}{\saildoclabelled{sailRISCVfnziszysome}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex}}}} + +\newcommand{\sailRISCVvaleqUnit}{\saildoclabelled{sailRISCVzeqzyunit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzeq_unit996f84433ac0995f4aadfca5b68cd358.tex}}}} + +\newcommand{\sailRISCVvaleqBit}{\saildoclabelled{sailRISCVzeqzybit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzeq_bit7182cc37406e2c0d4c1e739a98e248ea.tex}}}} + +\newcommand{\sailRISCVfneqUnit}{\saildoclabelled{sailRISCVfnzeqzyunit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzeq_unit996f84433ac0995f4aadfca5b68cd358.tex}}}} + +\newcommand{\sailRISCVvalnotBool}{\saildoclabelled{sailRISCVznotzybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznot_boole1dd3e44bc87a2a10d8e257004c2d36a.tex}}}} + +\newcommand{\sailRISCVvalandBool}{\saildoclabelled{sailRISCVzandzybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzand_boola4a2cf9ccaa44106300961b15ab20e79.tex}}}} + +\newcommand{\sailRISCVvalandBoolNoFlow}{\saildoclabelled{sailRISCVzandzyboolzynozyflow}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzand_bool_no_flow5d5041fa8ff689136cdc03e3a11eda3a.tex}}}} + +\newcommand{\sailRISCVvalorBool}{\saildoclabelled{sailRISCVzorzybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzor_bool5f07f9d72d4d1495c45a3531c787546a.tex}}}} + +\newcommand{\sailRISCVvaleqInt}{\saildoclabelled{sailRISCVzeqzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzeq_int364a98dbf8a9faa70e666cce41d8c1aa.tex}}}} + +\newcommand{\sailRISCVvaleqBool}{\saildoclabelled{sailRISCVzeqzybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzeq_bool0e93587306381c3f984dc7cea6ae190d.tex}}}} + +\newcommand{\sailRISCVvalneqInt}{\saildoclabelled{sailRISCVzneqzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex}}}} + +\newcommand{\sailRISCVfnneqInt}{\saildoclabelled{sailRISCVfnzneqzyint}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex}}}} + +\newcommand{\sailRISCVvalneqBool}{\saildoclabelled{sailRISCVzneqzybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex}}}} + +\newcommand{\sailRISCVfnneqBool}{\saildoclabelled{sailRISCVfnzneqzybool}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex}}}} + +\newcommand{\sailRISCVvallteqInt}{\saildoclabelled{sailRISCVzlteqzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlteq_intc80d1082e443aa434e39355e493ece1e.tex}}}} + +\newcommand{\sailRISCVvalgteqInt}{\saildoclabelled{sailRISCVzgteqzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgteq_inte32033a8d137f46d187455cff7dbe40e.tex}}}} + +\newcommand{\sailRISCVvalltInt}{\saildoclabelled{sailRISCVzltzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlt_int996a8b8c361a31bed6b5509ca6686e1a.tex}}}} + +\newcommand{\sailRISCVvalgtInt}{\saildoclabelled{sailRISCVzgtzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgt_intef94a8c66f39b1f715cb72941ed95921.tex}}}} + +\newcommand{\sailRISCVoverloadCzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailRISCVoverloadCzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} + +\newcommand{\sailRISCVoverloadDzEightoperatorzZerozOnezJzNine}{\saildoclabelled{sailRISCVoverloadDzz8operatorz0z1zJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex}}}} + +\newcommand{\sailRISCVoverloadEzEightoperatorzZerozUzNine}{\saildoclabelled{sailRISCVoverloadEzz8operatorz0zUz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex}}}} + +\newcommand{\sailRISCVoverloadFzEightoperatorzZerozSixzNine}{\saildoclabelled{sailRISCVoverloadFzz8operatorz0z6z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex}}}} + +\newcommand{\sailRISCVoverloadGzEightoperatorzZerozIzJzNine}{\saildoclabelled{sailRISCVoverloadGzz8operatorz0zIzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex}}}} + +\newcommand{\sailRISCVoverloadHzEightoperatorzZerozIzNine}{\saildoclabelled{sailRISCVoverloadHzz8operatorz0zIz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex}}}} + +\newcommand{\sailRISCVoverloadIzEightoperatorzZerozKzJzNine}{\saildoclabelled{sailRISCVoverloadIzz8operatorz0zKzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex}}}} + +\newcommand{\sailRISCVoverloadJzEightoperatorzZerozKzNine}{\saildoclabelled{sailRISCVoverloadJzz8operatorz0zKz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex}}}} + +\newcommand{\sailRISCVvalId}{\saildoclabelled{sailRISCVzzyzyid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__ided888b8991a27578d5dd72f84db80bce.tex}}}} + +\newcommand{\sailRISCVfnId}{\saildoclabelled{sailRISCVfnzzyzyid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz__ided888b8991a27578d5dd72f84db80bce.tex}}}} + +\newcommand{\sailRISCVoverloadKSizze}{\saildoclabelled{sailRISCVoverloadKzzyzysizze}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex}}}} + +\newcommand{\sailRISCVvalDeref}{\saildoclabelled{sailRISCVzzyzyderef}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__deref1dbc379e24bd1b182e1db755dea8c453.tex}}}} + +\newcommand{\sailRISCVvalBitfieldDeref}{\saildoclabelled{sailRISCVzzyzybitfieldzyderef}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__bitfield_deref5ed587b7c1b91cf82e42f865304262ca.tex}}}} + +\newcommand{\sailRISCVvaladdAtom}{\saildoclabelled{sailRISCVzaddzyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzadd_atomd34efc9e611b6d3b6757e17f4932b12b.tex}}}} + +\newcommand{\sailRISCVvaladdInt}{\saildoclabelled{sailRISCVzaddzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzadd_intb17710be4fd02ace68d83b9dba907034.tex}}}} + +\newcommand{\sailRISCVoverloadLzEightoperatorzZerozBzNine}{\saildoclabelled{sailRISCVoverloadLzz8operatorz0zBz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex}}}} + +\newcommand{\sailRISCVvalsubAtom}{\saildoclabelled{sailRISCVzsubzyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsub_atom328a68dfbab1a07c42d4e7b98eac766f.tex}}}} + +\newcommand{\sailRISCVvalsubInt}{\saildoclabelled{sailRISCVzsubzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsub_intf17f348f33594e77fdc3ef8b6a46b569.tex}}}} + +\newcommand{\sailRISCVoverloadMzEightoperatorzZerozDzNine}{\saildoclabelled{sailRISCVoverloadMzz8operatorz0zDz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex}}}} + +\newcommand{\sailRISCVvalsubNat}{\saildoclabelled{sailRISCVzsubzynat}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsub_nat1e51a6ef44b288dd12f7f69af44dfd3e.tex}}}} + +\newcommand{\sailRISCVvalnegateAtom}{\saildoclabelled{sailRISCVznegatezyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznegate_atomfefdbde89b468d9df54837e864426d70.tex}}}} + +\newcommand{\sailRISCVvalnegateInt}{\saildoclabelled{sailRISCVznegatezyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznegate_int42f776f84c124d77c3e367500082e43f.tex}}}} + +\newcommand{\sailRISCVoverloadNnegate}{\saildoclabelled{sailRISCVoverloadNznegate}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex}}}} + +\newcommand{\sailRISCVvalmultAtom}{\saildoclabelled{sailRISCVzmultzyatom}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmult_atomdbad478b99777b7676dde1f5a7900711.tex}}}} + +\newcommand{\sailRISCVvalmultInt}{\saildoclabelled{sailRISCVzmultzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmult_inte25d1b032a27b461f0eaf0c84be37a2b.tex}}}} + +\newcommand{\sailRISCVoverloadOzEightoperatorzZerozAzNine}{\saildoclabelled{sailRISCVoverloadOzz8operatorz0zAz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex}}}} + +\newcommand{\sailRISCVvalprintInt}{\saildoclabelled{sailRISCVzprintzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprint_intfb625bfb7a4021903513aeb4396bd878.tex}}}} + +\newcommand{\sailRISCVvalprerrInt}{\saildoclabelled{sailRISCVzprerrzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprerr_int00b48f715fbb32df5901801dff63b643.tex}}}} + +\newcommand{\sailRISCVvalShlEight}{\saildoclabelled{sailRISCVzzyshl8}{\saildocval{A common idiom in asl is to take two bits of an opcode and convert in into a variable like + +\lstinputlisting[language=sail]{sail_latex_riscv/block7c9393e4ce2c29e4e1dc024db508cec2.sail}\lstinline{_shl8} ensures that in this case the typechecker knows that the end result will be a value in the set \lstinline`{8, 16, 32, 64}` + +Similarly, we define shifts of 32 and 1 (i.e., powers of two). + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_shl8e01c74b934d4c323501a597baa8e6f73.tex}}}} + +\newcommand{\sailRISCVvalShlThreeTwo}{\saildoclabelled{sailRISCVzzyshl32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_shl32469ae968a52f81e1a28aeacf7e2d496b.tex}}}} + +\newcommand{\sailRISCVvalShlOne}{\saildoclabelled{sailRISCVzzyshl1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_shl1b261f5995acb90d475c10ee0cdbc12ce.tex}}}} + +\newcommand{\sailRISCVvalShlInt}{\saildoclabelled{sailRISCVzzyshlzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_shl_int86f4e1bc3609625860bc16734d7f2614.tex}}}} + +\newcommand{\sailRISCVoverloadPshlInt}{\saildoclabelled{sailRISCVoverloadPzshlzyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPzshl_int4772030e3fc0913189e795ec25e86dc5.tex}}}} + +\newcommand{\sailRISCVvalShrThreeTwo}{\saildoclabelled{sailRISCVzzyshr32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_shr328ec48e4bcaebfdbf5c374b77ca7b535b.tex}}}} + +\newcommand{\sailRISCVvalShrInt}{\saildoclabelled{sailRISCVzzyshrzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_shr_int34025c843d841a08930cb64bf99a1693.tex}}}} + +\newcommand{\sailRISCVoverloadQshrInt}{\saildoclabelled{sailRISCVoverloadQzshrzyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex}}}} + +\newcommand{\sailRISCVvaltdivInt}{\saildoclabelled{sailRISCVztdivzyint}{\saildocval{Truncating division (rounds towards zero) + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valztdiv_int5e119ac7ab9ff04c8877846f345d1159.tex}}}} + +\newcommand{\sailRISCVvalTmodInt}{\saildoclabelled{sailRISCVzzytmodzyint}{\saildocval{Remainder for truncating division (has sign of dividend) + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_tmod_inta2984ba6dbfa10758476d9b3b7f62560.tex}}}} + +\newcommand{\sailRISCVvalTmodIntPositive}{\saildoclabelled{sailRISCVzzytmodzyintzypositive}{\saildocval{If we know the second argument is positive, we know the result is positive + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_tmod_int_positive6f0621d972182279e90a43c082e50c10.tex}}}} + +\newcommand{\sailRISCVoverloadRtmodInt}{\saildoclabelled{sailRISCVoverloadRztmodzyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRztmod_int76b131b53b88df8b201279295eacebbe.tex}}}} + +\newcommand{\sailRISCVvalfdivInt}{\saildoclabelled{sailRISCVzfdivzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex}}}} + +\newcommand{\sailRISCVfnfdivInt}{\saildoclabelled{sailRISCVfnzfdivzyint}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex}}}} + +\newcommand{\sailRISCVvalfmodInt}{\saildoclabelled{sailRISCVzfmodzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfmod_int7e215ca2b888f4e92201959fd40958a5.tex}}}} + +\newcommand{\sailRISCVfnfmodInt}{\saildoclabelled{sailRISCVfnzfmodzyint}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfmod_int7e215ca2b888f4e92201959fd40958a5.tex}}}} + +\newcommand{\sailRISCVvalabsIntPlain}{\saildoclabelled{sailRISCVzabszyintzyplain}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzabs_int_plainb54aa4afeed2c86b519a464eb2e4c77c.tex}}}} + +\newcommand{\sailRISCVoverloadSabsInt}{\saildoclabelled{sailRISCVoverloadSzabszyint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSzabs_intef5fbb521189282054dc80dc7173013d.tex}}}} + +\newcommand{\sailRISCVvaleqString}{\saildoclabelled{sailRISCVzeqzystring}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzeq_string75dfa57c0476ae3f43f8e55ffe51a116.tex}}}} + +\newcommand{\sailRISCVoverloadTzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailRISCVoverloadTzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} + +\newcommand{\sailRISCVvalconcatStr}{\saildoclabelled{sailRISCVzconcatzystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzconcat_str366019c233188ef65ab3d1f977f04112.tex}}}} + +\newcommand{\sailRISCVvaldecStr}{\saildoclabelled{sailRISCVzdeczystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzdec_str7582ccea1482759c248b1f1ac9f6ae63.tex}}}} + +\newcommand{\sailRISCVvalhexStr}{\saildoclabelled{sailRISCVzhexzystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_str47c735e2941ef5c87d4f7502a5e92a2a.tex}}}} + +\newcommand{\sailRISCVvalbitsStr}{\saildoclabelled{sailRISCVzbitszystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbits_strae053d842c21f0867dea1e830d1773cc.tex}}}} + +\newcommand{\sailRISCVvalconcatStrBits}{\saildoclabelled{sailRISCVzconcatzystrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex}}}} + +\newcommand{\sailRISCVfnconcatStrBits}{\saildoclabelled{sailRISCVfnzconcatzystrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex}}}} + +\newcommand{\sailRISCVvalconcatStrDec}{\saildoclabelled{sailRISCVzconcatzystrzydec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex}}}} + +\newcommand{\sailRISCVfnconcatStrDec}{\saildoclabelled{sailRISCVfnzconcatzystrzydec}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex}}}} + +\newcommand{\sailRISCVvalprintEndline}{\saildoclabelled{sailRISCVzprintzyendline}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprint_endline03a43e2779561cb054d0761733c27e9b.tex}}}} + +\newcommand{\sailRISCVvalprerrEndline}{\saildoclabelled{sailRISCVzprerrzyendline}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprerr_endline73ce57fcf6e847727670556577cb2de0.tex}}}} + +\newcommand{\sailRISCVtypebits}{\saildoclabelled{sailRISCVtypezbits}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezbitsa4b31f9b3dc11c921007b665e0d0fce6.tex}}}} + +\newcommand{\sailRISCVvaleqBits}{\saildoclabelled{sailRISCVzeqzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzeq_bits886ce7cf3ec93a28308e8d4e9d63f4be.tex}}}} + +\newcommand{\sailRISCVoverloadUzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailRISCVoverloadUzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} + +\newcommand{\sailRISCVvalneqBits}{\saildoclabelled{sailRISCVzneqzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzneq_bits167748c906c068e62596c88540a84f42.tex}}}} + +\newcommand{\sailRISCVfnneqBits}{\saildoclabelled{sailRISCVfnzneqzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzneq_bits167748c906c068e62596c88540a84f42.tex}}}} + +\newcommand{\sailRISCVoverloadVzEightoperatorzZerozOnezJzNine}{\saildoclabelled{sailRISCVoverloadVzz8operatorz0z1zJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex}}}} + +\newcommand{\sailRISCVvalbitvectorLength}{\saildoclabelled{sailRISCVzbitvectorzylength}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbitvector_lengthcd74a5cced7567d19500671e4b6e1031.tex}}}} + +\newcommand{\sailRISCVvalvectorLength}{\saildoclabelled{sailRISCVzvectorzylength}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzvector_length9ee541b308cdfd9738d44bfb3dff4b46.tex}}}} + +\newcommand{\sailRISCVoverloadWlength}{\saildoclabelled{sailRISCVoverloadWzlength}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWzlength469e3f917f7b24f4691faf3caf842eba.tex}}}} + +\newcommand{\sailRISCVvalcountLeadingZeros}{\saildoclabelled{sailRISCVzcountzyleadingzyzzeros}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcount_leading_zzeros315ae28f559df1d42a7d2ca4cfff2905.tex}}}} + +\newcommand{\sailRISCVvalprintBits}{\saildoclabelled{sailRISCVzprintzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprint_bits30cf225474fbf3e575d7aa83aa309559.tex}}}} + +\newcommand{\sailRISCVvalprerrBits}{\saildoclabelled{sailRISCVzprerrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprerr_bits932899725108ebe483d3226f250f2b92.tex}}}} + +\newcommand{\sailRISCVvalsailSignExtend}{\saildoclabelled{sailRISCVzsailzysignzyextend}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsail_sign_extendb66ac7c1aaedb0cb21bdf07e4518af5e.tex}}}} + +\newcommand{\sailRISCVvalsailZeroExtend}{\saildoclabelled{sailRISCVzsailzyzzerozyextend}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsail_zzero_extend411875c18d3b332113845d17151890c2.tex}}}} + +\newcommand{\sailRISCVvaltruncate}{\saildoclabelled{sailRISCVztruncate}{\saildocval{\lstinline{truncate}\lstinline`(v, n)` truncates \lstinline`v`, keeping only the \emph{least} significant \lstinline`n` bits. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valztruncatea666e28ae0c8ca7327a2b3fcd1ed4ec7.tex}}}} + +\newcommand{\sailRISCVvaltruncateLSB}{\saildoclabelled{sailRISCVztruncateLSB}{\saildocval{\lstinline{truncateLSB}\lstinline`(v, n)` truncates \lstinline`v`, keeping only the \emph{most} significant \lstinline`n` bits. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valztruncatelsb4d124c6ec672453343dc0b20d295e82d.tex}}}} + +\newcommand{\sailRISCVvalsailMask}{\saildoclabelled{sailRISCVzsailzymask}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsail_maske146b73afc824e90813dd8234bfa3053.tex}}}} + +\newcommand{\sailRISCVfnsailMask}{\saildoclabelled{sailRISCVfnzsailzymask}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsail_maske146b73afc824e90813dd8234bfa3053.tex}}}} + +\newcommand{\sailRISCVoverloadXzEightoperatorzZerozQzNine}{\saildoclabelled{sailRISCVoverloadXzz8operatorz0zQz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex}}}} + +\newcommand{\sailRISCVvalbitvectorConcat}{\saildoclabelled{sailRISCVzbitvectorzyconcat}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbitvector_concat6176f8be1468d8779ee8370fd3b4a6e0.tex}}}} + +\newcommand{\sailRISCVoverloadYappend}{\saildoclabelled{sailRISCVoverloadYzappend}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYzappend88575169e0ec1639b6ae3851df999710.tex}}}} + +\newcommand{\sailRISCVvalappendSixFour}{\saildoclabelled{sailRISCVzappendzy64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzappend_6433ef192058d4bf5f092d6f8b6d97f4c4.tex}}}} + +\newcommand{\sailRISCVvalbitvectorAccess}{\saildoclabelled{sailRISCVzbitvectorzyaccess}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbitvector_access8b584ca86770abb6b0da5ef059a02ed9.tex}}}} + +\newcommand{\sailRISCVvalplainVectorAccess}{\saildoclabelled{sailRISCVzplainzyvectorzyaccess}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplain_vector_access792547dd734d4ff2e6078cbb88967469.tex}}}} + +\newcommand{\sailRISCVoverloadZvectorAccess}{\saildoclabelled{sailRISCVoverloadZzvectorzyaccess}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex}}}} + +\newcommand{\sailRISCVvalbitvectorUpdate}{\saildoclabelled{sailRISCVzbitvectorzyupdate}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbitvector_update20826799a1ff3ff40895206db0df14bb.tex}}}} + +\newcommand{\sailRISCVvalplainVectorUpdate}{\saildoclabelled{sailRISCVzplainzyvectorzyupdate}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplain_vector_updateb31d67bfe51b1a6f79983347dfc57da0.tex}}}} + +\newcommand{\sailRISCVoverloadAAvectorUpdate}{\saildoclabelled{sailRISCVoverloadAAzvectorzyupdate}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex}}}} + +\newcommand{\sailRISCVvaladdBits}{\saildoclabelled{sailRISCVzaddzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzadd_bits24373ffc11f289d5bb648df2f4f41b25.tex}}}} + +\newcommand{\sailRISCVvaladdBitsInt}{\saildoclabelled{sailRISCVzaddzybitszyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzadd_bits_inta5424052402522ff4653275c899f7543.tex}}}} + +\newcommand{\sailRISCVoverloadBBzEightoperatorzZerozBzNine}{\saildoclabelled{sailRISCVoverloadBBzz8operatorz0zBz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex}}}} + +\newcommand{\sailRISCVvalsubBits}{\saildoclabelled{sailRISCVzsubzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsub_bitsf0dc4fc3429d45517c523db21af72127.tex}}}} + +\newcommand{\sailRISCVvalnotVec}{\saildoclabelled{sailRISCVznotzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznot_vecfb45897f737be88160f5363827ef4a4b.tex}}}} + +\newcommand{\sailRISCVvalandVec}{\saildoclabelled{sailRISCVzandzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzand_vec99be3fe45d23194b597520c9e407ad35.tex}}}} + +\newcommand{\sailRISCVoverloadCCzEightoperatorzZerozSixzNine}{\saildoclabelled{sailRISCVoverloadCCzz8operatorz0z6z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex}}}} + +\newcommand{\sailRISCVvalorVec}{\saildoclabelled{sailRISCVzorzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzor_vec467c7a3f74be27085fe1b2aa3651ffe7.tex}}}} + +\newcommand{\sailRISCVoverloadDDzEightoperatorzZerozUzNine}{\saildoclabelled{sailRISCVoverloadDDzz8operatorz0zUz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex}}}} + +\newcommand{\sailRISCVvalsubrangeBits}{\saildoclabelled{sailRISCVzsubrangezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsubrange_bits6c497c14df4f4754bd345a6c56ca2aad.tex}}}} + +\newcommand{\sailRISCVoverloadEEvectorSubrange}{\saildoclabelled{sailRISCVoverloadEEzvectorzysubrange}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex}}}} + +\newcommand{\sailRISCVvalupdateSubrangeBits}{\saildoclabelled{sailRISCVzupdatezysubrangezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzupdate_subrange_bitsb5ffe862b26310b45a779cd45bbf041e.tex}}}} + +\newcommand{\sailRISCVoverloadFFvectorUpdateSubrange}{\saildoclabelled{sailRISCVoverloadFFzvectorzyupdatezysubrange}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex}}}} + +\newcommand{\sailRISCVvalsailShiftleft}{\saildoclabelled{sailRISCVzsailzyshiftleft}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsail_shiftlefta7bc10407d10355c4e981688c9926084.tex}}}} + +\newcommand{\sailRISCVvalsailShiftright}{\saildoclabelled{sailRISCVzsailzyshiftright}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsail_shiftrighte403ac5c2740b7767c2bdfe689082562.tex}}}} + +\newcommand{\sailRISCVvalsailArithShiftright}{\saildoclabelled{sailRISCVzsailzyarithzyshiftright}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsail_arith_shiftrighta24f06e92ffcd84e26ed61085c833371.tex}}}} + +\newcommand{\sailRISCVvalsailZeros}{\saildoclabelled{sailRISCVzsailzyzzeros}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsail_zzeros174d4d4928427d9df9fa9749f1df5f96.tex}}}} + +\newcommand{\sailRISCVvalsailOnes}{\saildoclabelled{sailRISCVzsailzyones}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex}}}} + +\newcommand{\sailRISCVfnsailOnes}{\saildoclabelled{sailRISCVfnzsailzyones}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex}}}} + +\newcommand{\sailRISCVvalslice}{\saildoclabelled{sailRISCVzslice}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzslice9979e992fd48f77a2c3fef7fbcce068e.tex}}}} + +\newcommand{\sailRISCVvalreplicateBits}{\saildoclabelled{sailRISCVzreplicatezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzreplicate_bitsb29bdab6bb9437712accf2dc81ea3d3e.tex}}}} + +\newcommand{\sailRISCVvalsliceMask}{\saildoclabelled{sailRISCVzslicezymask}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex}}}} + +\newcommand{\sailRISCVfnsliceMask}{\saildoclabelled{sailRISCVfnzslicezymask}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex}}}} + +\newcommand{\sailRISCVvalgetSliceInt}{\saildoclabelled{sailRISCVzgetzyslicezyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_slice_int3c313e973dc436aff309f66096377164.tex}}}} + +\newcommand{\sailRISCVvalsetSliceInt}{\saildoclabelled{sailRISCVzsetzyslicezyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzset_slice_intf4b6b0ed3d8b3bb2f2e0d7a492959629.tex}}}} + +\newcommand{\sailRISCVvalsetSliceBits}{\saildoclabelled{sailRISCVzsetzyslicezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzset_slice_bits5956200094c551f35973411fcc90a521.tex}}}} + +\newcommand{\sailRISCVvalunsigned}{\saildoclabelled{sailRISCVzunsigned}{\saildocval{converts a bit vector of length $n$ to an integer in the range $0$ to $2^n - 1$. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valzunsigned1010eda2cdd2666cd8fd0ddf82ac526f.tex}}}} + +\newcommand{\sailRISCVvalsigned}{\saildoclabelled{sailRISCVzsigned}{\saildocval{converts a bit vector of length $n$ to an integer in the range $-2^{n-1}$ to $2^{n-1} - 1$ using twos-complement. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsigned36d2317f34f1dacb4e465e6e56b185e6.tex}}}} + +\newcommand{\sailRISCVoverloadGGSizze}{\saildoclabelled{sailRISCVoverloadGGzzyzysizze}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex}}}} + +\newcommand{\sailRISCVtyperegfp}{\saildoclabelled{sailRISCVtypezregfp}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezregfpedcf3a6440b11288a4e07504f1ebdfae.tex}}}} + +\newcommand{\sailRISCVtyperegfps}{\saildoclabelled{sailRISCVtypezregfps}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezregfps6fc0ab735834848cecec1fbd72e56328.tex}}}} + +\newcommand{\sailRISCVtypeniafp}{\saildoclabelled{sailRISCVtypezniafp}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezniafpdcbcae7343979e4fb47e41a0909b121f.tex}}}} + +\newcommand{\sailRISCVtypeniafps}{\saildoclabelled{sailRISCVtypezniafps}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezniafps1c85f5c2a0d9da30d236aad9e6b48b40.tex}}}} + +\newcommand{\sailRISCVtypediafp}{\saildoclabelled{sailRISCVtypezdiafp}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezdiafp900a9a3c892b92c007276686dcd307f6.tex}}}} + +\newcommand{\sailRISCVtypereadKind}{\saildoclabelled{sailRISCVtypezreadzykind}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezread_kindc722f7d2aff68c2bd16feb054ed367f8.tex}}}} + +\newcommand{\sailRISCVvalreadKindOfNum}{\saildoclabelled{sailRISCVzreadzykindzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzread_kind_of_numd8fea9b1331732e205bdd70279e0ba47.tex}}}} + +\newcommand{\sailRISCVfnreadKindOfNum}{\saildoclabelled{sailRISCVfnzreadzykindzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzread_kind_of_numd8fea9b1331732e205bdd70279e0ba47.tex}}}} + +\newcommand{\sailRISCVvalnumOfReadKind}{\saildoclabelled{sailRISCVznumzyofzyreadzykind}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_read_kind9f1d12d5627d7618c1e31c888906fc68.tex}}}} + +\newcommand{\sailRISCVfnnumOfReadKind}{\saildoclabelled{sailRISCVfnznumzyofzyreadzykind}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_read_kind9f1d12d5627d7618c1e31c888906fc68.tex}}}} + +\newcommand{\sailRISCVtypewriteKind}{\saildoclabelled{sailRISCVtypezwritezykind}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezwrite_kindd407cee84c148660ae0b73dee4f0ddc7.tex}}}} + +\newcommand{\sailRISCVvalwriteKindOfNum}{\saildoclabelled{sailRISCVzwritezykindzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwrite_kind_of_num3c6c37285ad605eea3332f170d5b12d9.tex}}}} + +\newcommand{\sailRISCVfnwriteKindOfNum}{\saildoclabelled{sailRISCVfnzwritezykindzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwrite_kind_of_num3c6c37285ad605eea3332f170d5b12d9.tex}}}} + +\newcommand{\sailRISCVvalnumOfWriteKind}{\saildoclabelled{sailRISCVznumzyofzywritezykind}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_write_kind056951dbaa3b47d3c25ba586d7093c91.tex}}}} + +\newcommand{\sailRISCVfnnumOfWriteKind}{\saildoclabelled{sailRISCVfnznumzyofzywritezykind}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_write_kind056951dbaa3b47d3c25ba586d7093c91.tex}}}} + +\newcommand{\sailRISCVtypeaSixFourBarrierDomain}{\saildoclabelled{sailRISCVtypeza64zybarrierzydomain}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typeza64_barrier_domaind28b62adeb08a7dce5456d5fc74d0c80.tex}}}} + +\newcommand{\sailRISCVvalaSixFourBarrierDomainOfNum}{\saildoclabelled{sailRISCVza64zybarrierzydomainzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valza64_barrier_domain_of_num6e122924ff562010f42f288ecc2cdbe3.tex}}}} + +\newcommand{\sailRISCVfnaSixFourBarrierDomainOfNum}{\saildoclabelled{sailRISCVfnza64zybarrierzydomainzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnza64_barrier_domain_of_num6e122924ff562010f42f288ecc2cdbe3.tex}}}} + +\newcommand{\sailRISCVvalnumOfASixFourBarrierDomain}{\saildoclabelled{sailRISCVznumzyofzya64zybarrierzydomain}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_a64_barrier_domainfd9b4ecf6f4c38bf5c7e299b7fb7b219.tex}}}} + +\newcommand{\sailRISCVfnnumOfASixFourBarrierDomain}{\saildoclabelled{sailRISCVfnznumzyofzya64zybarrierzydomain}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_a64_barrier_domainfd9b4ecf6f4c38bf5c7e299b7fb7b219.tex}}}} + +\newcommand{\sailRISCVtypeaSixFourBarrierType}{\saildoclabelled{sailRISCVtypeza64zybarrierzytype}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typeza64_barrier_typec915d041169289864dae061f42a2c131.tex}}}} + +\newcommand{\sailRISCVvalaSixFourBarrierTypeOfNum}{\saildoclabelled{sailRISCVza64zybarrierzytypezyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valza64_barrier_type_of_numc06c55fe3b04f35ecb4741ea01acc85e.tex}}}} + +\newcommand{\sailRISCVfnaSixFourBarrierTypeOfNum}{\saildoclabelled{sailRISCVfnza64zybarrierzytypezyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnza64_barrier_type_of_numc06c55fe3b04f35ecb4741ea01acc85e.tex}}}} + +\newcommand{\sailRISCVvalnumOfASixFourBarrierType}{\saildoclabelled{sailRISCVznumzyofzya64zybarrierzytype}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_a64_barrier_typef15d849f5523574b740454d956b74505.tex}}}} + +\newcommand{\sailRISCVfnnumOfASixFourBarrierType}{\saildoclabelled{sailRISCVfnznumzyofzya64zybarrierzytype}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_a64_barrier_typef15d849f5523574b740454d956b74505.tex}}}} + +\newcommand{\sailRISCVtypebarrierKind}{\saildoclabelled{sailRISCVtypezbarrierzykind}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezbarrier_kind0e1536e14e65f0b7937be9cba7867981.tex}}}} + +\newcommand{\sailRISCVtypetransKind}{\saildoclabelled{sailRISCVtypeztranszykind}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typeztrans_kind8352eb8eb0b209f0054bd957c33bf07d.tex}}}} + +\newcommand{\sailRISCVvaltransKindOfNum}{\saildoclabelled{sailRISCVztranszykindzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztrans_kind_of_num89fdff5348b6925bdad7af7bbcc092d6.tex}}}} + +\newcommand{\sailRISCVfntransKindOfNum}{\saildoclabelled{sailRISCVfnztranszykindzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztrans_kind_of_num89fdff5348b6925bdad7af7bbcc092d6.tex}}}} + +\newcommand{\sailRISCVvalnumOfTransKind}{\saildoclabelled{sailRISCVznumzyofzytranszykind}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_trans_kind7086883ee37c97f3e6858f19cebb2163.tex}}}} + +\newcommand{\sailRISCVfnnumOfTransKind}{\saildoclabelled{sailRISCVfnznumzyofzytranszykind}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_trans_kind7086883ee37c97f3e6858f19cebb2163.tex}}}} + +\newcommand{\sailRISCVtypecacheOpKind}{\saildoclabelled{sailRISCVtypezcachezyopzykind}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcache_op_kind900c2bd360568e5562e384cfad1cfbd4.tex}}}} + +\newcommand{\sailRISCVvalcacheOpKindOfNum}{\saildoclabelled{sailRISCVzcachezyopzykindzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcache_op_kind_of_num612a346f1c1edf9d5bae987ac9d9912c.tex}}}} + +\newcommand{\sailRISCVfncacheOpKindOfNum}{\saildoclabelled{sailRISCVfnzcachezyopzykindzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcache_op_kind_of_num612a346f1c1edf9d5bae987ac9d9912c.tex}}}} + +\newcommand{\sailRISCVvalnumOfCacheOpKind}{\saildoclabelled{sailRISCVznumzyofzycachezyopzykind}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_cache_op_kindbd96e6225a906fea23a868ff35718006.tex}}}} + +\newcommand{\sailRISCVfnnumOfCacheOpKind}{\saildoclabelled{sailRISCVfnznumzyofzycachezyopzykind}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_cache_op_kindbd96e6225a906fea23a868ff35718006.tex}}}} + +\newcommand{\sailRISCVtypeinstructionKind}{\saildoclabelled{sailRISCVtypezinstructionzykind}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezinstruction_kinda0a17f6dfb4c893282fe838bdd846354.tex}}}} + +\newcommand{\sailRISCVvalReadMem}{\saildoclabelled{sailRISCVzzyzyreadzymem}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__read_mem5b50614e040054739d7452238393251d.tex}}}} + +\newcommand{\sailRISCVvalReadMemt}{\saildoclabelled{sailRISCVzzyzyreadzymemt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__read_memt00147dd8cf6dc9809e14fc1395c45ce6.tex}}}} + +\newcommand{\sailRISCVvalWriteMemEa}{\saildoclabelled{sailRISCVzzyzywritezymemzyea}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__write_mem_ea084b77c6ab56479698cd76a013fd7cad.tex}}}} + +\newcommand{\sailRISCVvalWriteMem}{\saildoclabelled{sailRISCVzzyzywritezymem}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__write_mem7fed12b7fc053a5ef3b5be1c753041b9.tex}}}} + +\newcommand{\sailRISCVvalWriteMemt}{\saildoclabelled{sailRISCVzzyzywritezymemt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__write_memte6e713c02b822271b225111a241edb5f.tex}}}} + +\newcommand{\sailRISCVvalExclRes}{\saildoclabelled{sailRISCVzzyzyexclzyres}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__excl_res213a4f8bb9ba5c1a34b50a170a41bba0.tex}}}} + +\newcommand{\sailRISCVvalBarrier}{\saildoclabelled{sailRISCVzzyzybarrier}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__barrier9c91ff87b358aa40ed8f2b1e1d97f44c.tex}}}} + +\newcommand{\sailRISCVvalBranchAnnounce}{\saildoclabelled{sailRISCVzzyzybranchzyannounce}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__branch_announce3f5ec48a7e84580ebc85c9d355048c29.tex}}}} + +\newcommand{\sailRISCVvalCacheMaintenance}{\saildoclabelled{sailRISCVzzyzycachezymaintenance}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__cache_maintenance664ff31aad5ce99f3549048fee01a578.tex}}}} + +\newcommand{\sailRISCVvalInstrAnnounce}{\saildoclabelled{sailRISCVzzyzyinstrzyannounce}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__instr_announce247eaf1a7feec56ee067d896e6f0ee3e.tex}}}} + +\newcommand{\sailRISCVvalstringStartswith}{\saildoclabelled{sailRISCVzstringzystartswith}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzstring_startswith150dcce016e36e283e03e57c7aa7f479.tex}}}} + +\newcommand{\sailRISCVvalstringDrop}{\saildoclabelled{sailRISCVzstringzydrop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzstring_drop09d7231db4951d3343ee0356a8f98d4e.tex}}}} + +\newcommand{\sailRISCVvalstringTake}{\saildoclabelled{sailRISCVzstringzytake}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzstring_takef5fd0689e1a11681ccf5471f34195539.tex}}}} + +\newcommand{\sailRISCVvalstringLength}{\saildoclabelled{sailRISCVzstringzylength}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzstring_length138975cd51f6e879bf061905da0059f9.tex}}}} + +\newcommand{\sailRISCVvalstringAppend}{\saildoclabelled{sailRISCVzstringzyappend}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzstring_appendca8a3ce55684edee6af875f28a1550b0.tex}}}} + +\newcommand{\sailRISCVvaleqAnything}{\saildoclabelled{sailRISCVzeqzyanything}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzeq_anything99dff1d931070d33dac5c755eae24439.tex}}}} + +\newcommand{\sailRISCVoverloadHHzEightoperatorzZerozJzJzNine}{\saildoclabelled{sailRISCVoverloadHHzz8operatorz0zJzJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex}}}} + +\newcommand{\sailRISCVvalregDeref}{\saildoclabelled{sailRISCVzregzyderef}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzreg_deref8bd1d78c61978d7074c7e0e5195e4bf7.tex}}}} + +\newcommand{\sailRISCVvalRegDeref}{\saildoclabelled{sailRISCVzzyregzyderef}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_reg_deref95099334a598a80d1fa0f47df99c8b42.tex}}}} + +\newcommand{\sailRISCVvalanyVectorUpdate}{\saildoclabelled{sailRISCVzanyzyvectorzyupdate}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzany_vector_updatef0077a3dd1846db0e7c8f84fa1a2eed5.tex}}}} + +\newcommand{\sailRISCVoverloadIIvectorUpdate}{\saildoclabelled{sailRISCVoverloadIIzvectorzyupdate}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex}}}} + +\newcommand{\sailRISCVvalupdateSubrange}{\saildoclabelled{sailRISCVzupdatezysubrange}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzupdate_subrangea3cf2a13bfd32a2a89bc44a498800493.tex}}}} + +\newcommand{\sailRISCVvalvectorConcat}{\saildoclabelled{sailRISCVzvectorzyconcat}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzvector_concate0e61f7c9864d8d335d1f5c434546f7c.tex}}}} + +\newcommand{\sailRISCVoverloadJJappend}{\saildoclabelled{sailRISCVoverloadJJzappend}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJzappend88575169e0ec1639b6ae3851df999710.tex}}}} + +\newcommand{\sailRISCVvalnotBit}{\saildoclabelled{sailRISCVznotzybit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznot_bit3b618f3ab6887bbe967eaa12bf52b297.tex}}}} + +\newcommand{\sailRISCVfnnotBit}{\saildoclabelled{sailRISCVfnznotzybit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznot_bit3b618f3ab6887bbe967eaa12bf52b297.tex}}}} + +\newcommand{\sailRISCVoverloadKKzW}{\saildoclabelled{sailRISCVoverloadKKzzW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKzzw805a9067649c7cfeedcb41b57a7e2c86.tex}}}} + +\newcommand{\sailRISCVvalneqVec}{\saildoclabelled{sailRISCVzneqzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzneq_vecefa97ba9877d7fde3cd929d8ec7a401a.tex}}}} + +\newcommand{\sailRISCVfnneqVec}{\saildoclabelled{sailRISCVfnzneqzyvec}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzneq_vecefa97ba9877d7fde3cd929d8ec7a401a.tex}}}} + +\newcommand{\sailRISCVvalneqAnything}{\saildoclabelled{sailRISCVzneqzyanything}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzneq_anythingf220233154ca93d75c0323f604bb8d16.tex}}}} + +\newcommand{\sailRISCVfnneqAnything}{\saildoclabelled{sailRISCVfnzneqzyanything}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzneq_anythingf220233154ca93d75c0323f604bb8d16.tex}}}} + +\newcommand{\sailRISCVoverloadLLzEightoperatorzZerozOnezJzNine}{\saildoclabelled{sailRISCVoverloadLLzz8operatorz0z1zJz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex}}}} + +\newcommand{\sailRISCVoverloadMMzEightoperatorzZerozSixzNine}{\saildoclabelled{sailRISCVoverloadMMzz8operatorz0z6z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex}}}} + +\newcommand{\sailRISCVoverloadNNzEightoperatorzZerozUzNine}{\saildoclabelled{sailRISCVoverloadNNzz8operatorz0zUz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex}}}} + +\newcommand{\sailRISCVvalstringOfInt}{\saildoclabelled{sailRISCVzstringzyofzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzstring_of_int03988e4e2d2976513793427ac823afbe.tex}}}} + +\newcommand{\sailRISCVvalstringOfBits}{\saildoclabelled{sailRISCVzstringzyofzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzstring_of_bits43debe172d2009dbb056cb5252821d62.tex}}}} + +\newcommand{\sailRISCVvalstringOfBit}{\saildoclabelled{sailRISCVzstringzyofzybit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzstring_of_bit7313cdbf7b05129d4977581f9bb14794.tex}}}} + +\newcommand{\sailRISCVfnstringOfBit}{\saildoclabelled{sailRISCVfnzstringzyofzybit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzstring_of_bit7313cdbf7b05129d4977581f9bb14794.tex}}}} + +\newcommand{\sailRISCVoverloadOOBitStr}{\saildoclabelled{sailRISCVoverloadOOzBitStr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOzbitstr0d04da018975c4776e05a9c59c2e380e.tex}}}} + +\newcommand{\sailRISCVvalxorVec}{\saildoclabelled{sailRISCVzxorzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzxor_vecdacd54acc32f073fb01d1c188177bc8c.tex}}}} + +\newcommand{\sailRISCVvalintPower}{\saildoclabelled{sailRISCVzintzypower}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzint_powerb0c5fc1a9fb0852260414607a93aeae6.tex}}}} + +\newcommand{\sailRISCVoverloadPPzEightoperatorzZerozQzNine}{\saildoclabelled{sailRISCVoverloadPPzz8operatorz0zQz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex}}}} + +\newcommand{\sailRISCVvalsubVec}{\saildoclabelled{sailRISCVzsubzyvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsub_vec326e0ba0bb00229be26645e2d44dbd83.tex}}}} + +\newcommand{\sailRISCVvalsubVecInt}{\saildoclabelled{sailRISCVzsubzyveczyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsub_vec_int5e6c04459782b1b8cc706ba2e4c8a435.tex}}}} + +\newcommand{\sailRISCVoverloadQQzEightoperatorzZerozDzNine}{\saildoclabelled{sailRISCVoverloadQQzz8operatorz0zDz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex}}}} + +\newcommand{\sailRISCVvalquotRoundZero}{\saildoclabelled{sailRISCVzquotzyroundzyzzero}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzquot_round_zzeroa8d9d278dc91a14956dfe19d01766403.tex}}}} + +\newcommand{\sailRISCVvalremRoundZero}{\saildoclabelled{sailRISCVzremzyroundzyzzero}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrem_round_zzero90d115d6c3e756b94f7766d1b76fbb83.tex}}}} + +\newcommand{\sailRISCVoverloadRRzEightoperatorzZerozFivezNine}{\saildoclabelled{sailRISCVoverloadRRzz8operatorz0z5z9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex}}}} + +\newcommand{\sailRISCVvalminInt}{\saildoclabelled{sailRISCVzminzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmin_intaf4626ab3b9c2d0b9494d7e8d265dd26.tex}}}} + +\newcommand{\sailRISCVvalmaxInt}{\saildoclabelled{sailRISCVzmaxzyint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmax_inta8f95a0baf723be8373221a893afa8f3.tex}}}} + +\newcommand{\sailRISCVoverloadSSmin}{\saildoclabelled{sailRISCVoverloadSSzmin}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSzmin95ae3c0ebde1421750e6db87bdf74801.tex}}}} + +\newcommand{\sailRISCVoverloadTTmax}{\saildoclabelled{sailRISCVoverloadTTzmax}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTzmax91b641c464c0dc87660499321a356d93.tex}}}} + +\newcommand{\sailRISCVvalpowTwo}{\saildoclabelled{sailRISCVzpow2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpow2e971ce2f9ebb899590551317286dfd1b.tex}}}} + +\newcommand{\sailRISCVvalprint}{\saildoclabelled{sailRISCVzprint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprintc9b8c9c569def1934362480628956c85.tex}}}} + +\newcommand{\sailRISCVvalprintString}{\saildoclabelled{sailRISCVzprintzystring}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprint_string4b7e44eb021c25878c749374ea5657f7.tex}}}} + +\newcommand{\sailRISCVvalprintInstr}{\saildoclabelled{sailRISCVzprintzyinstr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprint_instr59f46726e427ed18b9d5d81c8247a576.tex}}}} + +\newcommand{\sailRISCVvalprintReg}{\saildoclabelled{sailRISCVzprintzyreg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprint_reg1e86a2863e701cf481babd6538033417.tex}}}} + +\newcommand{\sailRISCVvalprintMem}{\saildoclabelled{sailRISCVzprintzymem}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprint_memb6cd54f21a6e2c7a036f86473d516264.tex}}}} + +\newcommand{\sailRISCVvalprintPlatform}{\saildoclabelled{sailRISCVzprintzyplatform}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprint_platform894b0df15559ad78744140d27df61719.tex}}}} + +\newcommand{\sailRISCVvalgetConfigPrintInstr}{\saildoclabelled{sailRISCVzgetzyconfigzyprintzyinstr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_config_print_instrcd725d09d3941c391aadf6b945a364c4.tex}}}} + +\newcommand{\sailRISCVvalgetConfigPrintReg}{\saildoclabelled{sailRISCVzgetzyconfigzyprintzyreg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_config_print_rega14ad214dae5f2d46538a3770abc93e2.tex}}}} + +\newcommand{\sailRISCVvalgetConfigPrintMem}{\saildoclabelled{sailRISCVzgetzyconfigzyprintzymem}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_config_print_memae95e5785b79c4a3f0105a772bf99dca.tex}}}} + +\newcommand{\sailRISCVvalgetConfigPrintPlatform}{\saildoclabelled{sailRISCVzgetzyconfigzyprintzyplatform}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_config_print_platform65eee2fe1a7d52174acea1de4e724e03.tex}}}} + +\newcommand{\sailRISCVfngetConfigPrintInstr}{\saildoclabelled{sailRISCVfnzgetzyconfigzyprintzyinstr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_config_print_instrcd725d09d3941c391aadf6b945a364c4.tex}}}} + +\newcommand{\sailRISCVfngetConfigPrintReg}{\saildoclabelled{sailRISCVfnzgetzyconfigzyprintzyreg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_config_print_rega14ad214dae5f2d46538a3770abc93e2.tex}}}} + +\newcommand{\sailRISCVfngetConfigPrintMem}{\saildoclabelled{sailRISCVfnzgetzyconfigzyprintzymem}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_config_print_memae95e5785b79c4a3f0105a772bf99dca.tex}}}} + +\newcommand{\sailRISCVfngetConfigPrintPlatform}{\saildoclabelled{sailRISCVfnzgetzyconfigzyprintzyplatform}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_config_print_platform65eee2fe1a7d52174acea1de4e724e03.tex}}}} + +\newcommand{\sailRISCVvalEXTS}{\saildoclabelled{sailRISCVzEXTS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzexts8a10d418fac6a2072ef1dfede4580873.tex}}}} + +\newcommand{\sailRISCVvalEXTZ}{\saildoclabelled{sailRISCVzEXTZ}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextzdb77018947d632a113deb15d298290d4.tex}}}} + +\newcommand{\sailRISCVfnEXTS}{\saildoclabelled{sailRISCVfnzEXTS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzexts8a10d418fac6a2072ef1dfede4580873.tex}}}} + +\newcommand{\sailRISCVfnEXTZ}{\saildoclabelled{sailRISCVfnzEXTZ}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzextzdb77018947d632a113deb15d298290d4.tex}}}} + +\newcommand{\sailRISCVvalzzerosImplicit}{\saildoclabelled{sailRISCVzzzeroszyimplicit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex}}}} + +\newcommand{\sailRISCVfnzzerosImplicit}{\saildoclabelled{sailRISCVfnzzzeroszyimplicit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex}}}} + +\newcommand{\sailRISCVoverloadUUzzeros}{\saildoclabelled{sailRISCVoverloadUUzzzeros}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUzzzerosc530711942e216cef3921733c1c5d101.tex}}}} + +\newcommand{\sailRISCVvalones}{\saildoclabelled{sailRISCVzones}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzones26f94136f5db8afd4e9df1e512f7fdc5.tex}}}} + +\newcommand{\sailRISCVfnones}{\saildoclabelled{sailRISCVfnzones}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzones26f94136f5db8afd4e9df1e512f7fdc5.tex}}}} + +\newcommand{\sailRISCVvalboolToBits}{\saildoclabelled{sailRISCVzboolzytozybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex}}}} + +\newcommand{\sailRISCVfnboolToBits}{\saildoclabelled{sailRISCVfnzboolzytozybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex}}}} + +\newcommand{\sailRISCVvalbitToBool}{\saildoclabelled{sailRISCVzbitzytozybool}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex}}}} + +\newcommand{\sailRISCVfnbitToBool}{\saildoclabelled{sailRISCVfnzbitzytozybool}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex}}}} + +\newcommand{\sailRISCVvaltoBits}{\saildoclabelled{sailRISCVztozybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex}}}} + +\newcommand{\sailRISCVfntoBits}{\saildoclabelled{sailRISCVfnztozybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex}}}} + +\newcommand{\sailRISCVvalzEightoperatorzZerozISzNine}{\saildoclabelled{sailRISCVzz8operatorz0zIzysz9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex}}}} + +\newcommand{\sailRISCVvalzEightoperatorzZerozKzJSzNine}{\saildoclabelled{sailRISCVzz8operatorz0zKzJzysz9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex}}}} + +\newcommand{\sailRISCVvalzEightoperatorzZerozIUzNine}{\saildoclabelled{sailRISCVzz8operatorz0zIzyuz9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex}}}} + +\newcommand{\sailRISCVvalzEightoperatorzZerozKzJUzNine}{\saildoclabelled{sailRISCVzz8operatorz0zKzJzyuz9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex}}}} + +\newcommand{\sailRISCVvalzEightoperatorzZerozIzJUzNine}{\saildoclabelled{sailRISCVzz8operatorz0zIzJzyuz9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzz8operatorz0zizj_uz99c310fa9a514922f781c01ba7354f99f.tex}}}} + +\newcommand{\sailRISCVfnzEightoperatorzZerozISzNine}{\saildoclabelled{sailRISCVfnzz8operatorz0zIzysz9}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex}}}} + +\newcommand{\sailRISCVfnzEightoperatorzZerozKzJSzNine}{\saildoclabelled{sailRISCVfnzz8operatorz0zKzJzysz9}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex}}}} + +\newcommand{\sailRISCVfnzEightoperatorzZerozIUzNine}{\saildoclabelled{sailRISCVfnzz8operatorz0zIzyuz9}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex}}}} + +\newcommand{\sailRISCVfnzEightoperatorzZerozKzJUzNine}{\saildoclabelled{sailRISCVfnzz8operatorz0zKzJzyuz9}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex}}}} + +\newcommand{\sailRISCVfnzEightoperatorzZerozIzJUzNine}{\saildoclabelled{sailRISCVfnzz8operatorz0zIzJzyuz9}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzz8operatorz0zizj_uz99c310fa9a514922f781c01ba7354f99f.tex}}}} + +\newcommand{\sailRISCVvalshiftBitsRight}{\saildoclabelled{sailRISCVzshiftzybitszyright}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzshift_bits_right281f5e6a28fe3c92d35fe5c78a0deb41.tex}}}} + +\newcommand{\sailRISCVvalshiftBitsLeft}{\saildoclabelled{sailRISCVzshiftzybitszyleft}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzshift_bits_left0754e8b870e2a3ba46646c35dac7af10.tex}}}} + +\newcommand{\sailRISCVvalshiftl}{\saildoclabelled{sailRISCVzshiftl}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzshiftl7827d0dcac29bd8258f158e7c1e77658.tex}}}} + +\newcommand{\sailRISCVvalshiftr}{\saildoclabelled{sailRISCVzshiftr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzshiftr173b7dba7206ed1b61a12344bdf9182a.tex}}}} + +\newcommand{\sailRISCVoverloadVVzEightoperatorzZerozKzKzNine}{\saildoclabelled{sailRISCVoverloadVVzz8operatorz0zKzKz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex}}}} + +\newcommand{\sailRISCVoverloadWWzEightoperatorzZerozIzIzNine}{\saildoclabelled{sailRISCVoverloadWWzz8operatorz0zIzIz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex}}}} + +\newcommand{\sailRISCVvalshiftRightArithSixFour}{\saildoclabelled{sailRISCVzshiftzyrightzyarith64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzshift_right_arith642d6a56971daae2b1fdb862ebbbaf6a46.tex}}}} + +\newcommand{\sailRISCVfnshiftRightArithSixFour}{\saildoclabelled{sailRISCVfnzshiftzyrightzyarith64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzshift_right_arith642d6a56971daae2b1fdb862ebbbaf6a46.tex}}}} + +\newcommand{\sailRISCVvalshiftRightArithThreeTwo}{\saildoclabelled{sailRISCVzshiftzyrightzyarith32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzshift_right_arith32247e0e7505241d38fca8e6a3bcdfea9e.tex}}}} + +\newcommand{\sailRISCVfnshiftRightArithThreeTwo}{\saildoclabelled{sailRISCVfnzshiftzyrightzyarith32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzshift_right_arith32247e0e7505241d38fca8e6a3bcdfea9e.tex}}}} + +\newcommand{\sailRISCVvalspc}{\saildoclabelled{sailRISCVzspc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzspca574d99b4c3d28e08386a1f673633994.tex}}}} + +\newcommand{\sailRISCVvaloptSpc}{\saildoclabelled{sailRISCVzoptzyspc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzopt_spc4aab1150dfed90f36fea1776963edbf0.tex}}}} + +\newcommand{\sailRISCVvaldefSpc}{\saildoclabelled{sailRISCVzdefzyspc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzdef_spce04ebdaa1e0acd4aa4dd3326642e673e.tex}}}} + +\newcommand{\sailRISCVvaldecimalStringOfBits}{\saildoclabelled{sailRISCVzdecimalzystringzyofzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzdecimal_string_of_bits7da73b6b29137ed7163460292c5440b0.tex}}}} + +\newcommand{\sailRISCVvalhexBits}{\saildoclabelled{sailRISCVzhexzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits6151f0f3396959dd9a279f1e74f7d7ec.tex}}}} + +\newcommand{\sailRISCVvalnLeadingSpaces}{\saildoclabelled{sailRISCVznzyleadingzyspaces}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzn_leading_spaces05ea6c2f03435a60412f4bef062a912a.tex}}}} + +\newcommand{\sailRISCVfnnLeadingSpaces}{\saildoclabelled{sailRISCVfnznzyleadingzyspaces}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzn_leading_spaces05ea6c2f03435a60412f4bef062a912a.tex}}}} + +\newcommand{\sailRISCVvalspcForwards}{\saildoclabelled{sailRISCVzspczyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzspc_forwardsabfa1efbce2d58c6d3e26c86435d3af4.tex}}}} + +\newcommand{\sailRISCVfnspcForwards}{\saildoclabelled{sailRISCVfnzspczyforwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzspc_forwardsabfa1efbce2d58c6d3e26c86435d3af4.tex}}}} + +\newcommand{\sailRISCVvalspcBackwards}{\saildoclabelled{sailRISCVzspczybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzspc_backwardsa712e20ab4070963924d2974cc8aa941.tex}}}} + +\newcommand{\sailRISCVfnspcBackwards}{\saildoclabelled{sailRISCVfnzspczybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzspc_backwardsa712e20ab4070963924d2974cc8aa941.tex}}}} + +\newcommand{\sailRISCVvalspcMatchesPrefix}{\saildoclabelled{sailRISCVzspczymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzspc_matches_prefix38c7965c7edeefb5fb2ccd6915f5bdbb.tex}}}} + +\newcommand{\sailRISCVfnspcMatchesPrefix}{\saildoclabelled{sailRISCVfnzspczymatcheszyprefix}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzspc_matches_prefix38c7965c7edeefb5fb2ccd6915f5bdbb.tex}}}} + +\newcommand{\sailRISCVvaloptSpcForwards}{\saildoclabelled{sailRISCVzoptzyspczyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzopt_spc_forwards395c7cf20c474712cbbb7c80edd24bda.tex}}}} + +\newcommand{\sailRISCVfnoptSpcForwards}{\saildoclabelled{sailRISCVfnzoptzyspczyforwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzopt_spc_forwards395c7cf20c474712cbbb7c80edd24bda.tex}}}} + +\newcommand{\sailRISCVvaloptSpcBackwards}{\saildoclabelled{sailRISCVzoptzyspczybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzopt_spc_backwards68e297450ccdf6f2339325379c27029f.tex}}}} + +\newcommand{\sailRISCVfnoptSpcBackwards}{\saildoclabelled{sailRISCVfnzoptzyspczybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzopt_spc_backwards68e297450ccdf6f2339325379c27029f.tex}}}} + +\newcommand{\sailRISCVvaloptSpcMatchesPrefix}{\saildoclabelled{sailRISCVzoptzyspczymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzopt_spc_matches_prefix495f7798e6650e2ff628a5b7715c161c.tex}}}} + +\newcommand{\sailRISCVfnoptSpcMatchesPrefix}{\saildoclabelled{sailRISCVfnzoptzyspczymatcheszyprefix}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzopt_spc_matches_prefix495f7798e6650e2ff628a5b7715c161c.tex}}}} + +\newcommand{\sailRISCVvaldefSpcForwards}{\saildoclabelled{sailRISCVzdefzyspczyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzdef_spc_forwards4eafa854d5b706686aca12e499e738fa.tex}}}} + +\newcommand{\sailRISCVfndefSpcForwards}{\saildoclabelled{sailRISCVfnzdefzyspczyforwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzdef_spc_forwards4eafa854d5b706686aca12e499e738fa.tex}}}} + +\newcommand{\sailRISCVvaldefSpcBackwards}{\saildoclabelled{sailRISCVzdefzyspczybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzdef_spc_backwardseab568d1f8e592642bb1655eb934a620.tex}}}} + +\newcommand{\sailRISCVfndefSpcBackwards}{\saildoclabelled{sailRISCVfnzdefzyspczybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzdef_spc_backwardseab568d1f8e592642bb1655eb934a620.tex}}}} + +\newcommand{\sailRISCVvaldefSpcMatchesPrefix}{\saildoclabelled{sailRISCVzdefzyspczymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzdef_spc_matches_prefix0e41afd1e8fe11919b3e9439288e00c3.tex}}}} + +\newcommand{\sailRISCVfndefSpcMatchesPrefix}{\saildoclabelled{sailRISCVfnzdefzyspczymatcheszyprefix}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzdef_spc_matches_prefix0e41afd1e8fe11919b3e9439288e00c3.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOne}{\saildoclabelled{sailRISCVzhexzybitszy1}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_1478f9a2bfac5b1844d4822c98afbb89d.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneForwards}{\saildoclabelled{sailRISCVzhexzybitszy1zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_1_forwardsf283099d0fc824606ed0d57afc78de8a.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy1zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_1_forwards_matches95bbf636d6fecebea6adab4fb1b42ac0.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy1zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_1_forwards_matches95bbf636d6fecebea6adab4fb1b42ac0.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy1zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_1_matches_prefixd812208f2aa5a7b3cf37c8de5c575662.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy1zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_1_backwards_matches3d78f15da2768104290b952c286f2f91.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy1zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_1_backwards_matches3d78f15da2768104290b952c286f2f91.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneBackwards}{\saildoclabelled{sailRISCVzhexzybitszy1zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_1_backwards90e5440bb0c40b9363498a8d972dba41.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy1zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_1_backwards90e5440bb0c40b9363498a8d972dba41.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwo}{\saildoclabelled{sailRISCVzhexzybitszy2}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_270bd1024c2f2d5860abcddb1e5cdd513.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoForwards}{\saildoclabelled{sailRISCVzhexzybitszy2zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_2_forwards72b197d3d92a10d7d05fb57812f597ab.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy2zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_2_forwards_matches7ab140c97f69659d3ab1d910b07425fb.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy2zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_2_forwards_matches7ab140c97f69659d3ab1d910b07425fb.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy2zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_2_matches_prefix948a15ea9e341681f6b07cb073ac1114.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy2zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_2_backwards_matches823cb41992ed3a26886d992e75e86734.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy2zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_2_backwards_matches823cb41992ed3a26886d992e75e86734.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoBackwards}{\saildoclabelled{sailRISCVzhexzybitszy2zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_2_backwards18d79d6a578203ebce0993a1703a4245.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy2zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_2_backwards18d79d6a578203ebce0993a1703a4245.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThree}{\saildoclabelled{sailRISCVzhexzybitszy3}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_3aeb691402af5232353b21f4b29231f77.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeForwards}{\saildoclabelled{sailRISCVzhexzybitszy3zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_3_forwards7bd80f2805155aa4c3a7525bb0bfd448.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy3zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_3_forwards_matchese79d3588a48711c3aab539462e1e83ad.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy3zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_3_forwards_matchese79d3588a48711c3aab539462e1e83ad.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy3zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_3_matches_prefix0b670e4346265cc88b71be93bef14dae.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy3zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_3_backwards_matches952f17dffac18d98619e00bc97a700fc.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy3zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_3_backwards_matches952f17dffac18d98619e00bc97a700fc.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeBackwards}{\saildoclabelled{sailRISCVzhexzybitszy3zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_3_backwardsf853f7ad9bfed642772b10dafd6910d1.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy3zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_3_backwardsf853f7ad9bfed642772b10dafd6910d1.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFour}{\saildoclabelled{sailRISCVzhexzybitszy4}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_4cc2b0d5d62eeaf81d463b3beb7b16ede.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFourForwards}{\saildoclabelled{sailRISCVzhexzybitszy4zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_4_forwards17651a29b8d01053a94a764e92e93964.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFourForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy4zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_4_forwards_matchesc9b2af172c13a489fa870acdd673758a.tex}}}} + +\newcommand{\sailRISCVfnhexBitsFourForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy4zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_4_forwards_matchesc9b2af172c13a489fa870acdd673758a.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFourMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy4zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_4_matches_prefix7449c0ebcb161f55de6260595c0db150.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFourBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy4zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_4_backwards_matches798cb282812c7bc9b083a091bb0b23ca.tex}}}} + +\newcommand{\sailRISCVfnhexBitsFourBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy4zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_4_backwards_matches798cb282812c7bc9b083a091bb0b23ca.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFourBackwards}{\saildoclabelled{sailRISCVzhexzybitszy4zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_4_backwardsf22b435ac96c309eec82519c5c010323.tex}}}} + +\newcommand{\sailRISCVfnhexBitsFourBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy4zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_4_backwardsf22b435ac96c309eec82519c5c010323.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFive}{\saildoclabelled{sailRISCVzhexzybitszy5}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_5daa8fabe8bf4a20ba57e93cf91addd75.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFiveForwards}{\saildoclabelled{sailRISCVzhexzybitszy5zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_5_forwards79911e0485d859b00a2fdcba8cff5318.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFiveForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy5zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_5_forwards_matches3e31f036e77b0ee1a3e8312b0067959b.tex}}}} + +\newcommand{\sailRISCVfnhexBitsFiveForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy5zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_5_forwards_matches3e31f036e77b0ee1a3e8312b0067959b.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFiveMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy5zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_5_matches_prefix998186306b8236e178fc5d664bda45c0.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFiveBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy5zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_5_backwards_matchesf675096dc18dd61104842d90f51800a8.tex}}}} + +\newcommand{\sailRISCVfnhexBitsFiveBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy5zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_5_backwards_matchesf675096dc18dd61104842d90f51800a8.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFiveBackwards}{\saildoclabelled{sailRISCVzhexzybitszy5zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_5_backwards79c47a53cbcc5ca893c439296fe2bd3f.tex}}}} + +\newcommand{\sailRISCVfnhexBitsFiveBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy5zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_5_backwards79c47a53cbcc5ca893c439296fe2bd3f.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSix}{\saildoclabelled{sailRISCVzhexzybitszy6}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_61cff7c3b87dd820982f77ae4876bbe56.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSixForwards}{\saildoclabelled{sailRISCVzhexzybitszy6zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_6_forwards3455f13508c617afbe64b39dede36554.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSixForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy6zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_6_forwards_matchescaeea7989719fec9093c81797a7f4155.tex}}}} + +\newcommand{\sailRISCVfnhexBitsSixForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy6zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_6_forwards_matchescaeea7989719fec9093c81797a7f4155.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSixMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy6zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_6_matches_prefixb8878485899ba2293890312e921ac156.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSixBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy6zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_6_backwards_matches4f038823a669140ed233992d9e5ddb69.tex}}}} + +\newcommand{\sailRISCVfnhexBitsSixBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy6zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_6_backwards_matches4f038823a669140ed233992d9e5ddb69.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSixBackwards}{\saildoclabelled{sailRISCVzhexzybitszy6zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_6_backwardsabaf13af56590b164adcda6b4fd1b52f.tex}}}} + +\newcommand{\sailRISCVfnhexBitsSixBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy6zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_6_backwardsabaf13af56590b164adcda6b4fd1b52f.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSeven}{\saildoclabelled{sailRISCVzhexzybitszy7}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_7b8d1ab69e279cfbd7a9d7c59b1171b24.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSevenForwards}{\saildoclabelled{sailRISCVzhexzybitszy7zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_7_forwards9bd105e290f5b2e7d8bb2e10f49c067b.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSevenForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy7zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_7_forwards_matches9d7aa1993e9d141c0950fe9e67734abc.tex}}}} + +\newcommand{\sailRISCVfnhexBitsSevenForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy7zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_7_forwards_matches9d7aa1993e9d141c0950fe9e67734abc.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSevenMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy7zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_7_matches_prefixfe0ccd9dca07ce0b4f7d3176ad3fc10c.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSevenBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy7zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_7_backwards_matchescc985ebeb5f5adedc7e184499a8978db.tex}}}} + +\newcommand{\sailRISCVfnhexBitsSevenBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy7zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_7_backwards_matchescc985ebeb5f5adedc7e184499a8978db.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSevenBackwards}{\saildoclabelled{sailRISCVzhexzybitszy7zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_7_backwards33c217f9145eec45b693f09bca0d89ea.tex}}}} + +\newcommand{\sailRISCVfnhexBitsSevenBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy7zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_7_backwards33c217f9145eec45b693f09bca0d89ea.tex}}}} + +\newcommand{\sailRISCVvalhexBitsEight}{\saildoclabelled{sailRISCVzhexzybitszy8}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_8e02cd45b50bbc73ca04e08e3df697f5d.tex}}}} + +\newcommand{\sailRISCVvalhexBitsEightForwards}{\saildoclabelled{sailRISCVzhexzybitszy8zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_8_forwards168d310ff118fd3c7d7bc80f8de29d67.tex}}}} + +\newcommand{\sailRISCVvalhexBitsEightForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy8zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_8_forwards_matches0746becf5ca996196bfae6048bab9bb1.tex}}}} + +\newcommand{\sailRISCVfnhexBitsEightForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy8zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_8_forwards_matches0746becf5ca996196bfae6048bab9bb1.tex}}}} + +\newcommand{\sailRISCVvalhexBitsEightMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy8zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_8_matches_prefixf713d7df51d74309ab21b6aa029dbeed.tex}}}} + +\newcommand{\sailRISCVvalhexBitsEightBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy8zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_8_backwards_matchesa183109b599ae5e880adc653bde047ba.tex}}}} + +\newcommand{\sailRISCVfnhexBitsEightBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy8zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_8_backwards_matchesa183109b599ae5e880adc653bde047ba.tex}}}} + +\newcommand{\sailRISCVvalhexBitsEightBackwards}{\saildoclabelled{sailRISCVzhexzybitszy8zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_8_backwards8502ba5c5fdfe5404c185ff925d26a02.tex}}}} + +\newcommand{\sailRISCVfnhexBitsEightBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy8zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_8_backwards8502ba5c5fdfe5404c185ff925d26a02.tex}}}} + +\newcommand{\sailRISCVvalhexBitsNine}{\saildoclabelled{sailRISCVzhexzybitszy9}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_9eeceb6bd9aab72270435e4d9e8c5dc4c.tex}}}} + +\newcommand{\sailRISCVvalhexBitsNineForwards}{\saildoclabelled{sailRISCVzhexzybitszy9zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_9_forwards5bc4abb19984f8188c037a8554a3ce15.tex}}}} + +\newcommand{\sailRISCVvalhexBitsNineForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy9zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_9_forwards_matches73ffbf54790f1b1c63b0dc63773cd0c0.tex}}}} + +\newcommand{\sailRISCVfnhexBitsNineForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy9zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_9_forwards_matches73ffbf54790f1b1c63b0dc63773cd0c0.tex}}}} + +\newcommand{\sailRISCVvalhexBitsNineMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy9zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_9_matches_prefix693d173094578fcf50e2fb151d0c156e.tex}}}} + +\newcommand{\sailRISCVvalhexBitsNineBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy9zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_9_backwards_matches34e146fa5f101fa17110f57d272dec69.tex}}}} + +\newcommand{\sailRISCVfnhexBitsNineBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy9zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_9_backwards_matches34e146fa5f101fa17110f57d272dec69.tex}}}} + +\newcommand{\sailRISCVvalhexBitsNineBackwards}{\saildoclabelled{sailRISCVzhexzybitszy9zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_9_backwards90cddf73654805833800c2414c31ab0f.tex}}}} + +\newcommand{\sailRISCVfnhexBitsNineBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy9zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_9_backwards90cddf73654805833800c2414c31ab0f.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneZero}{\saildoclabelled{sailRISCVzhexzybitszy10}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_1001007fc28a3cc2512c7863ca8f700d8b.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneZeroForwards}{\saildoclabelled{sailRISCVzhexzybitszy10zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_10_forwardseca444da7d319d1932fce8e708381d1e.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneZeroForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy10zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_10_forwards_matches5805c03590a8c87ee15c304ac5e14038.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneZeroForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy10zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_10_forwards_matches5805c03590a8c87ee15c304ac5e14038.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneZeroMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy10zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_10_matches_prefix1bc10569a97d5b943c4d0e1bee005436.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneZeroBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy10zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_10_backwards_matches40e05acb0a138e49841d114ad4d36956.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneZeroBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy10zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_10_backwards_matches40e05acb0a138e49841d114ad4d36956.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneZeroBackwards}{\saildoclabelled{sailRISCVzhexzybitszy10zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_10_backwards3ea67a7e3b03c19fc3f62bce5d70adcf.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneZeroBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy10zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_10_backwards3ea67a7e3b03c19fc3f62bce5d70adcf.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneOne}{\saildoclabelled{sailRISCVzhexzybitszy11}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_1196b03eaf6acc67335c0bb71c802e6a22.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneOneForwards}{\saildoclabelled{sailRISCVzhexzybitszy11zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_11_forwardsa103ffbf0ab1e78130e8eca0e504aba5.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneOneForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy11zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_11_forwards_matchesc72e36f9e9259ad52cfd038ae9c0251f.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneOneForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy11zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_11_forwards_matchesc72e36f9e9259ad52cfd038ae9c0251f.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneOneMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy11zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_11_matches_prefix5542021dd19d9d49c8135e0408dda5bf.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneOneBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy11zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_11_backwards_matchesd1ccc1a72470b9d5d21bdc4ac13ff26b.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneOneBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy11zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_11_backwards_matchesd1ccc1a72470b9d5d21bdc4ac13ff26b.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneOneBackwards}{\saildoclabelled{sailRISCVzhexzybitszy11zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_11_backwards2baa8535235545b1d36570cd9bfa54d3.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneOneBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy11zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_11_backwards2baa8535235545b1d36570cd9bfa54d3.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneTwo}{\saildoclabelled{sailRISCVzhexzybitszy12}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_125a4772f29c6286c50b66c991563e61c3.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneTwoForwards}{\saildoclabelled{sailRISCVzhexzybitszy12zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_12_forwardsfead99eab466bc9417dd261cbed56176.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneTwoForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy12zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_12_forwards_matches23afc09f193a32dea040a72b95ec91b2.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneTwoForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy12zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_12_forwards_matches23afc09f193a32dea040a72b95ec91b2.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneTwoMatchesPrefix}{\saildoclabelled{sailRISCVfnzhexzybitszy12zymatcheszyprefix}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_12_matches_prefixc31c0737edfea85e61e2e4a0e4afa0dc.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneTwoBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy12zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_12_backwards_matches6a7e459d92157f0ba9dee2e4c7899300.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneTwoBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy12zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_12_backwards_matches6a7e459d92157f0ba9dee2e4c7899300.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneTwoBackwards}{\saildoclabelled{sailRISCVzhexzybitszy12zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_12_backwards3d80f810c3a0bfaf0d29151a18d72567.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneTwoBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy12zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_12_backwards3d80f810c3a0bfaf0d29151a18d72567.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneThree}{\saildoclabelled{sailRISCVzhexzybitszy13}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_13f2e19b07147e1bc75b3a752515303583.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneThreeForwards}{\saildoclabelled{sailRISCVzhexzybitszy13zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_13_forwards4a6f3d80543dcfc7821c2bf16e534c80.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneThreeForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy13zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_13_forwards_matches24cf47063279787f52ede006100876ff.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneThreeForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy13zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_13_forwards_matches24cf47063279787f52ede006100876ff.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneThreeMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy13zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_13_matches_prefix808dd1e0db4d0e2cbb2964dee566f987.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneThreeBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy13zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_13_backwards_matches3380960c8e44f21f0eeafd0244600ee6.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneThreeBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy13zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_13_backwards_matches3380960c8e44f21f0eeafd0244600ee6.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneThreeBackwards}{\saildoclabelled{sailRISCVzhexzybitszy13zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_13_backwards75db4a8adaa37e62b3ea51d810cbbf3b.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneThreeBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy13zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_13_backwards75db4a8adaa37e62b3ea51d810cbbf3b.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneFour}{\saildoclabelled{sailRISCVzhexzybitszy14}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_147ca431b3e814f7be996cd1b6ec3c0902.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneFourForwards}{\saildoclabelled{sailRISCVzhexzybitszy14zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_14_forwards8f53488826326c38c678631a29ef042b.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneFourForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy14zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_14_forwards_matches229689dc85657ccebc6a0143fb21144e.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneFourForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy14zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_14_forwards_matches229689dc85657ccebc6a0143fb21144e.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneFourMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy14zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_14_matches_prefix43b0d69de97191b01d4d4ad6d99d2952.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneFourBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy14zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_14_backwards_matches7a9acb89282cc5c0ad18d89d22bf3cfa.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneFourBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy14zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_14_backwards_matches7a9acb89282cc5c0ad18d89d22bf3cfa.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneFourBackwards}{\saildoclabelled{sailRISCVzhexzybitszy14zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_14_backwards825f2ad69791fa9a1bb2792ac85efc54.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneFourBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy14zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_14_backwards825f2ad69791fa9a1bb2792ac85efc54.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneFive}{\saildoclabelled{sailRISCVzhexzybitszy15}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_15073380baa5f552c999850321b1ecde51.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneFiveForwards}{\saildoclabelled{sailRISCVzhexzybitszy15zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_15_forwards6c990ff9d54de24c898e16e2e488b179.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneFiveForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy15zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_15_forwards_matches923e93be7d0b466ae08582f59a3c9529.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneFiveForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy15zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_15_forwards_matches923e93be7d0b466ae08582f59a3c9529.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneFiveMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy15zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_15_matches_prefixa2a5a94154c4b4c6efd07c71b5146350.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneFiveBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy15zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_15_backwards_matchesc6cd9235f40d6808371474280c964ff1.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneFiveBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy15zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_15_backwards_matchesc6cd9235f40d6808371474280c964ff1.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneFiveBackwards}{\saildoclabelled{sailRISCVzhexzybitszy15zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_15_backwardscb4ce484e79dc8d005cf2bda729e7867.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneFiveBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy15zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_15_backwardscb4ce484e79dc8d005cf2bda729e7867.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneSix}{\saildoclabelled{sailRISCVzhexzybitszy16}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_167d95ad16536f8aabd412012ac1a3e03f.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneSixForwards}{\saildoclabelled{sailRISCVzhexzybitszy16zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_16_forwards7f61f6684c0758bacebc97ae288552c8.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneSixForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy16zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_16_forwards_matches99127000f54090aaa9f0aeb2c20f4685.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneSixForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy16zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_16_forwards_matches99127000f54090aaa9f0aeb2c20f4685.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneSixMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy16zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_16_matches_prefix38bcd18ff44c77953c7f4f991dfa37b8.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneSixBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy16zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_16_backwards_matches8ff37bbe35e588c9d66f041b5b32d8e0.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneSixBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy16zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_16_backwards_matches8ff37bbe35e588c9d66f041b5b32d8e0.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneSixBackwards}{\saildoclabelled{sailRISCVzhexzybitszy16zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_16_backwards8afef1c1c4af4f381f60fc4dc7267c9c.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneSixBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy16zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_16_backwards8afef1c1c4af4f381f60fc4dc7267c9c.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneSeven}{\saildoclabelled{sailRISCVzhexzybitszy17}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_17d357434a9e9aecc580dae54ef5402fcf.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneSevenForwards}{\saildoclabelled{sailRISCVzhexzybitszy17zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_17_forwards1d1b1aacf0ce8d2f042cb60029feef84.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneSevenForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy17zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_17_forwards_matches45df8bfd52709ac4d9906f538498742e.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneSevenForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy17zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_17_forwards_matches45df8bfd52709ac4d9906f538498742e.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneSevenMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy17zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_17_matches_prefix02c803ee497f2adf656b9a546dc9d148.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneSevenBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy17zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_17_backwards_matchesd594e6fb2cf338d85aa8e3a859821359.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneSevenBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy17zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_17_backwards_matchesd594e6fb2cf338d85aa8e3a859821359.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneSevenBackwards}{\saildoclabelled{sailRISCVzhexzybitszy17zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_17_backwards96076e6b0ee1d8c887acfae20a696145.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneSevenBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy17zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_17_backwards96076e6b0ee1d8c887acfae20a696145.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneEight}{\saildoclabelled{sailRISCVzhexzybitszy18}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_1819473bd89c251dd41ec313d06e46da0e.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneEightForwards}{\saildoclabelled{sailRISCVzhexzybitszy18zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_18_forwards47e61ad2851c0c0e789494a5e30c9e1c.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneEightForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy18zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_18_forwards_matches6e035e739a1d5414f87357bc391d08b3.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneEightForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy18zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_18_forwards_matches6e035e739a1d5414f87357bc391d08b3.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneEightMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy18zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_18_matches_prefix0123403473ed4dd9dbffc716d963c568.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneEightBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy18zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_18_backwards_matches72b528c9dd8e982607b88bd8ab46a37d.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneEightBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy18zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_18_backwards_matches72b528c9dd8e982607b88bd8ab46a37d.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneEightBackwards}{\saildoclabelled{sailRISCVzhexzybitszy18zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_18_backwards0500c1a0187a21072c3255f60243909f.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneEightBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy18zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_18_backwards0500c1a0187a21072c3255f60243909f.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneNine}{\saildoclabelled{sailRISCVzhexzybitszy19}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_1938ed2064ef7ce8152e6dfd8213383d7e.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneNineForwards}{\saildoclabelled{sailRISCVzhexzybitszy19zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_19_forwardsc23db4c1e0ead6b3252ea4464c668ee1.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneNineForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy19zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_19_forwards_matches07c7d804aca651680480475ad9d45b66.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneNineForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy19zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_19_forwards_matches07c7d804aca651680480475ad9d45b66.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneNineMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy19zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_19_matches_prefix28d0e3106abb68242ac4e35ed75b7eea.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneNineBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy19zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_19_backwards_matchesd823f57016d205b9df109966ee967db9.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneNineBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy19zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_19_backwards_matchesd823f57016d205b9df109966ee967db9.tex}}}} + +\newcommand{\sailRISCVvalhexBitsOneNineBackwards}{\saildoclabelled{sailRISCVzhexzybitszy19zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_19_backwards8a1ab4ffc6b6e5e3c0cf6702ec74b710.tex}}}} + +\newcommand{\sailRISCVfnhexBitsOneNineBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy19zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_19_backwards8a1ab4ffc6b6e5e3c0cf6702ec74b710.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoZero}{\saildoclabelled{sailRISCVzhexzybitszy20}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_20073767bf3c4e755df8668de0f192df95.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoZeroForwards}{\saildoclabelled{sailRISCVzhexzybitszy20zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_20_forwards00e9d80df23932a0cd55fe8e4cea5260.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoZeroForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy20zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_20_forwards_matchesde8955f96663b48788095ef74c50f0aa.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoZeroForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy20zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_20_forwards_matchesde8955f96663b48788095ef74c50f0aa.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoZeroMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy20zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_20_matches_prefixdf9ef269745a9eb5e6b479b1935b64ab.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoZeroBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy20zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_20_backwards_matches8c546ae28d487f510dca7fe30ea629c5.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoZeroBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy20zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_20_backwards_matches8c546ae28d487f510dca7fe30ea629c5.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoZeroBackwards}{\saildoclabelled{sailRISCVzhexzybitszy20zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_20_backwardsed333b625b69d435d8e8df1b980d11ef.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoZeroBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy20zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_20_backwardsed333b625b69d435d8e8df1b980d11ef.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoOne}{\saildoclabelled{sailRISCVzhexzybitszy21}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_215a399be0fd96b92fed46a34ed6d97e44.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoOneForwards}{\saildoclabelled{sailRISCVzhexzybitszy21zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_21_forwards5d6372cc66bb45095acb2dbe03a6acfc.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoOneForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy21zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_21_forwards_matches05f5fa78d5ad49b7efae27025b546cb7.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoOneForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy21zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_21_forwards_matches05f5fa78d5ad49b7efae27025b546cb7.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoOneMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy21zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_21_matches_prefix159b58fe3bdaba7ade8041d986b2ecf6.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoOneBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy21zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_21_backwards_matches477a84c0bff49ab6511438197e40d9c3.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoOneBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy21zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_21_backwards_matches477a84c0bff49ab6511438197e40d9c3.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoOneBackwards}{\saildoclabelled{sailRISCVzhexzybitszy21zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_21_backwardsc44f7bb35fd47e4506558a2d7d995f8e.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoOneBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy21zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_21_backwardsc44f7bb35fd47e4506558a2d7d995f8e.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoTwo}{\saildoclabelled{sailRISCVzhexzybitszy22}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_228df71d429e9677759c4b9421597b9624.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoTwoForwards}{\saildoclabelled{sailRISCVzhexzybitszy22zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_22_forwards5f20df76cf594392e558c43103ffc6e4.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoTwoForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy22zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_22_forwards_matches4fe97899c8181992923cd1daaa36d526.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoTwoForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy22zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_22_forwards_matches4fe97899c8181992923cd1daaa36d526.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoTwoMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy22zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_22_matches_prefix1a790a92ddf1d11e5f9d0ff8b4ca8b1c.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoTwoBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy22zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_22_backwards_matchesfd56758d4cd0fd6150ee51afa372c83b.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoTwoBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy22zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_22_backwards_matchesfd56758d4cd0fd6150ee51afa372c83b.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoTwoBackwards}{\saildoclabelled{sailRISCVzhexzybitszy22zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_22_backwardsfbed1dd3d215529ff44a9e8165218968.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoTwoBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy22zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_22_backwardsfbed1dd3d215529ff44a9e8165218968.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoThree}{\saildoclabelled{sailRISCVzhexzybitszy23}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_23418f7302c0b7161a092d463e4d8af7dc.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoThreeForwards}{\saildoclabelled{sailRISCVzhexzybitszy23zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_23_forwardsdd8792f3a53735041dd06c758d6e9f7e.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoThreeForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy23zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_23_forwards_matchesb58b33da7b8d1a86392eabd6cc87b2c3.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoThreeForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy23zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_23_forwards_matchesb58b33da7b8d1a86392eabd6cc87b2c3.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoThreeMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy23zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_23_matches_prefix48403fc7c51b83fad5e40b0f6370b8fa.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoThreeBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy23zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_23_backwards_matchesa97370178cb502dd696426e4a347c318.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoThreeBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy23zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_23_backwards_matchesa97370178cb502dd696426e4a347c318.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoThreeBackwards}{\saildoclabelled{sailRISCVzhexzybitszy23zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_23_backwards2183795dfc2ff2f588be2709c2cd7639.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoThreeBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy23zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_23_backwards2183795dfc2ff2f588be2709c2cd7639.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoFour}{\saildoclabelled{sailRISCVzhexzybitszy24}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_246fe29a7e07e79124e13aa086639a725a.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoFourForwards}{\saildoclabelled{sailRISCVzhexzybitszy24zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_24_forwardsdeaf00c9fe92ade0c2e92648a2b58039.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoFourForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy24zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_24_forwards_matchesf4dd0da48edd6a31433b0bae1bedc1f5.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoFourForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy24zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_24_forwards_matchesf4dd0da48edd6a31433b0bae1bedc1f5.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoFourMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy24zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_24_matches_prefix6ba2f72e46135bdb8c80c62ad4b58e8f.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoFourBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy24zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_24_backwards_matchesb2a483aa8b7cae87c37d98bc8b2a7345.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoFourBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy24zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_24_backwards_matchesb2a483aa8b7cae87c37d98bc8b2a7345.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoFourBackwards}{\saildoclabelled{sailRISCVzhexzybitszy24zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_24_backwardsa48c754c7049ebcb72d1fbba8bcfaadf.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoFourBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy24zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_24_backwardsa48c754c7049ebcb72d1fbba8bcfaadf.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoFive}{\saildoclabelled{sailRISCVzhexzybitszy25}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_25b2fb96ee1c2b78dcefb54132cd9af05a.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoFiveForwards}{\saildoclabelled{sailRISCVzhexzybitszy25zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_25_forwards72bc0d414786f2c38ca3e1ba78cab739.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoFiveForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy25zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_25_forwards_matches6d8831afa1ed150c2dca6afcd8d46fd1.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoFiveForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy25zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_25_forwards_matches6d8831afa1ed150c2dca6afcd8d46fd1.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoFiveMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy25zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_25_matches_prefixa3fd9e9a9ab3f00e09575979dd9a94e8.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoFiveBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy25zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_25_backwards_matchese97e136616a70048191383b2a45471f6.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoFiveBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy25zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_25_backwards_matchese97e136616a70048191383b2a45471f6.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoFiveBackwards}{\saildoclabelled{sailRISCVzhexzybitszy25zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_25_backwardsb4f6ac6cc03e034620b7a4a11a89c5fc.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoFiveBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy25zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_25_backwardsb4f6ac6cc03e034620b7a4a11a89c5fc.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoSix}{\saildoclabelled{sailRISCVzhexzybitszy26}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_26663364c85fd29e21280b999b60cb2a55.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoSixForwards}{\saildoclabelled{sailRISCVzhexzybitszy26zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_26_forwards5a6114b9bf479d01fa3a9e2beec5d91b.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoSixForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy26zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_26_forwards_matchesec5940b6c813530a4c8c509af6c000b6.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoSixForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy26zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_26_forwards_matchesec5940b6c813530a4c8c509af6c000b6.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoSixMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy26zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_26_matches_prefix7b5176f43e479ddf2dec5f4a2011b98f.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoSixBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy26zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_26_backwards_matches0ea73e31736f776e20958f45ec3e81bd.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoSixBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy26zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_26_backwards_matches0ea73e31736f776e20958f45ec3e81bd.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoSixBackwards}{\saildoclabelled{sailRISCVzhexzybitszy26zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_26_backwardsca9980b4fb1beb5e20216094b1b6b352.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoSixBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy26zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_26_backwardsca9980b4fb1beb5e20216094b1b6b352.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoSeven}{\saildoclabelled{sailRISCVzhexzybitszy27}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_27b316c424414b7868c1946d3aa5df4022.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoSevenForwards}{\saildoclabelled{sailRISCVzhexzybitszy27zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_27_forwardsd1cadb067b94f8db9ac21a09b0a9c465.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoSevenForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy27zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_27_forwards_matches6867770d92d07d048cf22050458e9a6f.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoSevenForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy27zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_27_forwards_matches6867770d92d07d048cf22050458e9a6f.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoSevenMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy27zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_27_matches_prefixdc708eca229898ef6aae7c4b60f3b806.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoSevenBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy27zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_27_backwards_matchesc36973ea671b22434d73ad552c3b36f1.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoSevenBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy27zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_27_backwards_matchesc36973ea671b22434d73ad552c3b36f1.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoSevenBackwards}{\saildoclabelled{sailRISCVzhexzybitszy27zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_27_backwards4d49d22a17608696fe779e708d0d5091.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoSevenBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy27zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_27_backwards4d49d22a17608696fe779e708d0d5091.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoEight}{\saildoclabelled{sailRISCVzhexzybitszy28}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_288d4243d5b924b9df9b04ff6f5779762e.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoEightForwards}{\saildoclabelled{sailRISCVzhexzybitszy28zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_28_forwards1cd2299af6ec5f9078eb9063e9f85a94.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoEightForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy28zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_28_forwards_matchesc4d71e8f4caf976479bf0fd50de2a1f7.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoEightForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy28zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_28_forwards_matchesc4d71e8f4caf976479bf0fd50de2a1f7.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoEightMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy28zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_28_matches_prefix70f347867a8aba96b2c10f78f8f7a372.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoEightBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy28zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_28_backwards_matches0baec25715c212015f55f72f54702da4.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoEightBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy28zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_28_backwards_matches0baec25715c212015f55f72f54702da4.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoEightBackwards}{\saildoclabelled{sailRISCVzhexzybitszy28zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_28_backwards2c2d2daf166e3a6a7935d895391a113e.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoEightBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy28zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_28_backwards2c2d2daf166e3a6a7935d895391a113e.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoNine}{\saildoclabelled{sailRISCVzhexzybitszy29}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_29efa82370fcd77919b51fb03d70b237d5.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoNineForwards}{\saildoclabelled{sailRISCVzhexzybitszy29zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_29_forwards25570c63210d57bb228476e7b744cbc0.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoNineForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy29zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_29_forwards_matchesed84d3ffca269bb316dc98b23b11184a.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoNineForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy29zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_29_forwards_matchesed84d3ffca269bb316dc98b23b11184a.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoNineMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy29zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_29_matches_prefix203fecad348616b1e04e6c54168376e2.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoNineBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy29zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_29_backwards_matchese61c62311ca330ee022b0ce689f2bf7a.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoNineBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy29zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_29_backwards_matchese61c62311ca330ee022b0ce689f2bf7a.tex}}}} + +\newcommand{\sailRISCVvalhexBitsTwoNineBackwards}{\saildoclabelled{sailRISCVzhexzybitszy29zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_29_backwards388cf5f0a97b7aadfda6550d7d52cc35.tex}}}} + +\newcommand{\sailRISCVfnhexBitsTwoNineBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy29zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_29_backwards388cf5f0a97b7aadfda6550d7d52cc35.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeZero}{\saildoclabelled{sailRISCVzhexzybitszy30}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_30cc6f2a56c4decf190e17ab7b80196c34.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeZeroForwards}{\saildoclabelled{sailRISCVzhexzybitszy30zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_30_forwardscea5ca246547b759f92507a3787c7a96.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeZeroForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy30zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_30_forwards_matches3630c22b1e1e03c4f0e0de4c42a765db.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeZeroForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy30zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_30_forwards_matches3630c22b1e1e03c4f0e0de4c42a765db.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeZeroMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy30zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_30_matches_prefixbf5a6ef1a55049d8f6c26bfca65564f4.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeZeroBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy30zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_30_backwards_matches55c635ce0a1a3c012b3119662b49178c.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeZeroBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy30zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_30_backwards_matches55c635ce0a1a3c012b3119662b49178c.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeZeroBackwards}{\saildoclabelled{sailRISCVzhexzybitszy30zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_30_backwards3391751afa83c025b48e297fc4113f6e.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeZeroBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy30zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_30_backwards3391751afa83c025b48e297fc4113f6e.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeOne}{\saildoclabelled{sailRISCVzhexzybitszy31}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_314eac40254c178573e1a2e3e8c866b4b9.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeOneForwards}{\saildoclabelled{sailRISCVzhexzybitszy31zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_31_forwards4963ea17f27efca42c2c3b70e3678a1f.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeOneForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy31zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_31_forwards_matches830a8b6e6851a2528701adaae04355bf.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeOneForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy31zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_31_forwards_matches830a8b6e6851a2528701adaae04355bf.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeOneMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy31zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_31_matches_prefixb56aff200a836c2c62dd85dd75e2e301.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeOneBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy31zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_31_backwards_matches68cc0d3844c92f7e0ebe6bcaa48a03ca.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeOneBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy31zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_31_backwards_matches68cc0d3844c92f7e0ebe6bcaa48a03ca.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeOneBackwards}{\saildoclabelled{sailRISCVzhexzybitszy31zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_31_backwards36aadfc7c167e0b19e4147eb55e51cba.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeOneBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy31zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_31_backwards36aadfc7c167e0b19e4147eb55e51cba.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeTwo}{\saildoclabelled{sailRISCVzhexzybitszy32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_3297bfc3853730082de31dbfe87d09e9ff.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeTwoForwards}{\saildoclabelled{sailRISCVzhexzybitszy32zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_32_forwards0b8436c3566927b7a7b6bca8d7dd5251.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeTwoForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy32zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_32_forwards_matches6b2dec12f42cfb341d5a812b57201577.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeTwoForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy32zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_32_forwards_matches6b2dec12f42cfb341d5a812b57201577.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeTwoMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy32zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_32_matches_prefix164ead7d22300ab7799ffb9205a2b7a2.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeTwoBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy32zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_32_backwards_matchesc5862ab9ce54a89fb3d05c1a1e742ba8.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeTwoBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy32zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_32_backwards_matchesc5862ab9ce54a89fb3d05c1a1e742ba8.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeTwoBackwards}{\saildoclabelled{sailRISCVzhexzybitszy32zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_32_backwardse98f8968c64c820f7d6ab0adad242eea.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeTwoBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy32zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_32_backwardse98f8968c64c820f7d6ab0adad242eea.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeThree}{\saildoclabelled{sailRISCVzhexzybitszy33}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_33bf5a1dfcb81a2b69ce2e63f2b8ac8ba4.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeThreeForwards}{\saildoclabelled{sailRISCVzhexzybitszy33zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_33_forwards30b0334f0b6652dcc7d0b51e3609d45f.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeThreeForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy33zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_33_forwards_matches4b4b2c7ba9f6a4dd54548314428e59f6.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeThreeForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy33zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_33_forwards_matches4b4b2c7ba9f6a4dd54548314428e59f6.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeThreeMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy33zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_33_matches_prefixfe32236f637b1e2c06fb0442b85daff6.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeThreeBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy33zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_33_backwards_matchesa0efa80a7912e2204c7a08b11236c3ea.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeThreeBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy33zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_33_backwards_matchesa0efa80a7912e2204c7a08b11236c3ea.tex}}}} + +\newcommand{\sailRISCVvalhexBitsThreeThreeBackwards}{\saildoclabelled{sailRISCVzhexzybitszy33zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_33_backwardscc814f008a05b1129f62004b8fa5c8e5.tex}}}} + +\newcommand{\sailRISCVfnhexBitsThreeThreeBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy33zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_33_backwardscc814f008a05b1129f62004b8fa5c8e5.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFourEight}{\saildoclabelled{sailRISCVzhexzybitszy48}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_48bcd68487a0855653b3f1bd0b77874f47.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFourEightForwards}{\saildoclabelled{sailRISCVzhexzybitszy48zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_48_forwards00cd6bb42ad747a155b252e7b9981df1.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFourEightForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy48zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_48_forwards_matchesf2b53432d5d61a0c6dbc5e249b95d790.tex}}}} + +\newcommand{\sailRISCVfnhexBitsFourEightForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy48zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_48_forwards_matchesf2b53432d5d61a0c6dbc5e249b95d790.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFourEightMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy48zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_48_matches_prefixcaea63593a204f4e52c03e2824ea453e.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFourEightBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy48zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_48_backwards_matches3765c7a672ed4a4188e6adcad2e1769c.tex}}}} + +\newcommand{\sailRISCVfnhexBitsFourEightBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy48zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_48_backwards_matches3765c7a672ed4a4188e6adcad2e1769c.tex}}}} + +\newcommand{\sailRISCVvalhexBitsFourEightBackwards}{\saildoclabelled{sailRISCVzhexzybitszy48zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_48_backwards57285976d132280592935deb245ad737.tex}}}} + +\newcommand{\sailRISCVfnhexBitsFourEightBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy48zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_48_backwards57285976d132280592935deb245ad737.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSixFour}{\saildoclabelled{sailRISCVzhexzybitszy64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_6481d941ae17c8b68343a58c840ecca1cd.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSixFourForwards}{\saildoclabelled{sailRISCVzhexzybitszy64zyforwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_64_forwards7510d79394d351421610c028bea6e7a5.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSixFourForwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy64zyforwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_64_forwards_matches9b4aa7858f48288bd5ee715f31bb0cdb.tex}}}} + +\newcommand{\sailRISCVfnhexBitsSixFourForwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy64zyforwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_64_forwards_matches9b4aa7858f48288bd5ee715f31bb0cdb.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSixFourMatchesPrefix}{\saildoclabelled{sailRISCVzhexzybitszy64zymatcheszyprefix}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_64_matches_prefix72a39a7f0e633af539b7e5e9e8e13575.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSixFourBackwardsMatches}{\saildoclabelled{sailRISCVzhexzybitszy64zybackwardszymatches}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_64_backwards_matches2ac7f320ee670e1403b866f7b48f9b95.tex}}}} + +\newcommand{\sailRISCVfnhexBitsSixFourBackwardsMatches}{\saildoclabelled{sailRISCVfnzhexzybitszy64zybackwardszymatches}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_64_backwards_matches2ac7f320ee670e1403b866f7b48f9b95.tex}}}} + +\newcommand{\sailRISCVvalhexBitsSixFourBackwards}{\saildoclabelled{sailRISCVzhexzybitszy64zybackwards}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhex_bits_64_backwardsef9778c97dfbfdc25f03d089d5788d24.tex}}}} + +\newcommand{\sailRISCVfnhexBitsSixFourBackwards}{\saildoclabelled{sailRISCVfnzhexzybitszy64zybackwards}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhex_bits_64_backwardsef9778c97dfbfdc25f03d089d5788d24.tex}}}} + +\newcommand{\sailRISCVtypexlen}{\saildoclabelled{sailRISCVtypezxlen}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezxlen69b5c0c212b6eef630aa879251a43faf.tex}}}} + +\newcommand{\sailRISCVtypexlenBytes}{\saildoclabelled{sailRISCVtypezxlenzybytes}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezxlen_bytesee19340a9dc2d174c74e7e66789a8ce5.tex}}}} + +\newcommand{\sailRISCVtypexlenbits}{\saildoclabelled{sailRISCVtypezxlenbits}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezxlenbitsf5ff3be63c10995c090bf7946ccc6ec1.tex}}}} + +\newcommand{\sailRISCVtypeflen}{\saildoclabelled{sailRISCVtypezflen}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezflen27ebfaa38e1d50ee3669425f05ac8951.tex}}}} + +\newcommand{\sailRISCVtypeflenBytes}{\saildoclabelled{sailRISCVtypezflenzybytes}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezflen_bytesd7ba48b222b9ef1a7ea6335686de6c81.tex}}}} + +\newcommand{\sailRISCVtypeflenbits}{\saildoclabelled{sailRISCVtypezflenbits}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezflenbits34a10f66673a8dd853aa9dcae8af6905.tex}}}} + +\newcommand{\sailRISCVvalMEMrTag}{\saildoclabelled{sailRISCVzMEMrzytag}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmemr_tag8062b3657c5bfba8d529ea5c413abc36.tex}}}} + +\newcommand{\sailRISCVvalMEMwTag}{\saildoclabelled{sailRISCVzMEMwzytag}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmemw_tag0a1745a5ee5b60705e9e4051c5099882.tex}}}} + +\newcommand{\sailRISCVvalMAX}{\saildoclabelled{sailRISCVzMAX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex}}}} + +\newcommand{\sailRISCVfnMAX}{\saildoclabelled{sailRISCVfnzMAX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex}}}} + +\newcommand{\sailRISCVvalnot}{\saildoclabelled{sailRISCVznot}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznotcbe861867f25b28c34f5ae99957794ed.tex}}}} + +\newcommand{\sailRISCVvalboolToBit}{\saildoclabelled{sailRISCVzboolzytozybit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex}}}} + +\newcommand{\sailRISCVfnboolToBit}{\saildoclabelled{sailRISCVfnzboolzytozybit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex}}}} + +\newcommand{\sailRISCVtypeCPtrCmpOp}{\saildoclabelled{sailRISCVtypezCPtrCmpOp}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcptrcmpopb3b1dde403387930c5431415f0c993e5.tex}}}} + +\newcommand{\sailRISCVvalCPtrCmpOpOfNum}{\saildoclabelled{sailRISCVzCPtrCmpOpzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex}}}} + +\newcommand{\sailRISCVfnCPtrCmpOpOfNum}{\saildoclabelled{sailRISCVfnzCPtrCmpOpzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex}}}} + +\newcommand{\sailRISCVvalnumOfCPtrCmpOp}{\saildoclabelled{sailRISCVznumzyofzyCPtrCmpOp}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex}}}} + +\newcommand{\sailRISCVfnnumOfCPtrCmpOp}{\saildoclabelled{sailRISCVfnznumzyofzyCPtrCmpOp}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex}}}} + +\newcommand{\sailRISCVtypeClearRegSet}{\saildoclabelled{sailRISCVtypezClearRegSet}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezclearregsete5eab3e282a2a338ddb8311b5edbb561.tex}}}} + +\newcommand{\sailRISCVvalClearRegSetOfNum}{\saildoclabelled{sailRISCVzClearRegSetzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex}}}} + +\newcommand{\sailRISCVfnClearRegSetOfNum}{\saildoclabelled{sailRISCVfnzClearRegSetzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex}}}} + +\newcommand{\sailRISCVvalnumOfClearRegSet}{\saildoclabelled{sailRISCVznumzyofzyClearRegSet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_clearregset49e10f200544574f819f7f660071e10b.tex}}}} + +\newcommand{\sailRISCVfnnumOfClearRegSet}{\saildoclabelled{sailRISCVfnznumzyofzyClearRegSet}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_clearregset49e10f200544574f819f7f660071e10b.tex}}}} + +\newcommand{\sailRISCVtypeCapEx}{\saildoclabelled{sailRISCVtypezCapEx}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcapexbc9797bf8ddff0359677ca6657edba93.tex}}}} + +\newcommand{\sailRISCVvalCapExOfNum}{\saildoclabelled{sailRISCVzCapExzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex}}}} + +\newcommand{\sailRISCVfnCapExOfNum}{\saildoclabelled{sailRISCVfnzCapExzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex}}}} + +\newcommand{\sailRISCVvalnumOfCapEx}{\saildoclabelled{sailRISCVznumzyofzyCapEx}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_capexa430f3db535161473e26bac337cc3ffe.tex}}}} + +\newcommand{\sailRISCVfnnumOfCapEx}{\saildoclabelled{sailRISCVfnznumzyofzyCapEx}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_capexa430f3db535161473e26bac337cc3ffe.tex}}}} + +\newcommand{\sailRISCVvalCapExCode}{\saildoclabelled{sailRISCVzCapExCode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcapexcodee065d40e92bb99703db21c8c18bedf11.tex}}}} + +\newcommand{\sailRISCVfnCapExCode}{\saildoclabelled{sailRISCVfnzCapExCode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcapexcodee065d40e92bb99703db21c8c18bedf11.tex}}}} + +\newcommand{\sailRISCVvalstringOfCapex}{\saildoclabelled{sailRISCVzstringzyofzycapex}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex}}}} + +\newcommand{\sailRISCVfnstringOfCapex}{\saildoclabelled{sailRISCVfnzstringzyofzycapex}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex}}}} + +\newcommand{\sailRISCVtypecapregIdx}{\saildoclabelled{sailRISCVtypezcapregzyidx}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcapreg_idx46cb8ec24174ac7dafd6635c5040002d.tex}}}} + +\newcommand{\sailRISCVtypecheriCause}{\saildoclabelled{sailRISCVtypezcherizycause}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcheri_causec1e7f09ff14a785b125a16b7f7b4f4fe.tex}}}} + +\newcommand{\sailRISCVtypescreg}{\saildoclabelled{sailRISCVtypezscreg}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezscreg7666c10c12f9f7ff3cd4397f32a77413.tex}}}} + +\newcommand{\sailRISCVtypecapSizze}{\saildoclabelled{sailRISCVtypezcapzysizze}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcap_sizze1bdaf9cd8fe2936d527bdd4bc7dd72ca.tex}}}} + +\newcommand{\sailRISCVtypelogTwoCapSizze}{\saildoclabelled{sailRISCVtypezlog2zycapzysizze}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezlog2_cap_sizzea1e54166750a789fdd63562b89a8f0d4.tex}}}} + +\newcommand{\sailRISCVtypeCapBits}{\saildoclabelled{sailRISCVtypezCapBits}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcapbits32830b87cefa69a0cdb78ef00d25b781.tex}}}} + +\newcommand{\sailRISCVtypecapOtypeWidth}{\saildoclabelled{sailRISCVtypezcapzyotypezywidth}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcap_otype_widthcbba33421b0d173c367e3bd232817e06.tex}}}} + +\newcommand{\sailRISCVtypecapHpermsWidth}{\saildoclabelled{sailRISCVtypezcapzyhpermszywidth}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcap_hperms_width7a71e6f5d2bdf15a0098752dcdf93274.tex}}}} + +\newcommand{\sailRISCVtypecapUpermsWidth}{\saildoclabelled{sailRISCVtypezcapzyupermszywidth}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcap_uperms_widthf6dfed0942499b0c2d58b90971faca40.tex}}}} + +\newcommand{\sailRISCVtypecapAddrWidth}{\saildoclabelled{sailRISCVtypezcapzyaddrzywidth}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcap_addr_width7d4b25117798a50c5addfe865237309d.tex}}}} + +\newcommand{\sailRISCVtypecapLenWidth}{\saildoclabelled{sailRISCVtypezcapzylenzywidth}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcap_len_width9583637a11dff282b382f15c2de94120.tex}}}} + +\newcommand{\sailRISCVtypecapMantissaWidth}{\saildoclabelled{sailRISCVtypezcapzymantissazywidth}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcap_mantissa_width9664b91a58eac86639a6d61f4c90f63a.tex}}}} + +\newcommand{\sailRISCVtypecapsPerCacheLine}{\saildoclabelled{sailRISCVtypezcapszyperzycachezyline}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcaps_per_cache_line7254e281fd7ea6b3c919ca9a34d729ad.tex}}}} + +\newcommand{\sailRISCVtypeCapAddrInt}{\saildoclabelled{sailRISCVtypezCapAddrInt}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcapaddrintf3dc84d3e8f46c74b19aac7a9fd4f1f2.tex}}}} + +\newcommand{\sailRISCVtypeCapLen}{\saildoclabelled{sailRISCVtypezCapLen}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcaplenf6618af706b03f95ca9741cffae7687d.tex}}}} + +\newcommand{\sailRISCVtypeCapability}{\saildoclabelled{sailRISCVtypezCapability}{\saildoctype{A partially decompressed version of a capability, populated by +capBitsToCapability. E is not present in all formats. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcapability5646515621fe4c3bb7fe8874d1909f0e.tex}}}} + +\newcommand{\sailRISCVvalcapBitsToCapability}{\saildoclabelled{sailRISCVzcapBitsToCapability}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex}}}} + +\newcommand{\sailRISCVfncapBitsToCapability}{\saildoclabelled{sailRISCVfnzcapBitsToCapability}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex}}}} + +\newcommand{\sailRISCVtypememMeta}{\saildoclabelled{sailRISCVtypezmemzymeta}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezmem_metaf5b381cf38597ad4a56a53301483f3c2.tex}}}} + +\newcommand{\sailRISCVtypetagaddrbits}{\saildoclabelled{sailRISCVtypeztagaddrbits}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typeztagaddrbitsc26f5e6e74dd7ca6d16ebef3163d1a53.tex}}}} + +\newcommand{\sailRISCVvaladdrToTagAddr}{\saildoclabelled{sailRISCVzaddrzytozytagzyaddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzaddr_to_tag_addr21cfb55575f4fc24f9ec71484b7d4eb8.tex}}}} + +\newcommand{\sailRISCVfnaddrToTagAddr}{\saildoclabelled{sailRISCVfnzaddrzytozytagzyaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzaddr_to_tag_addr21cfb55575f4fc24f9ec71484b7d4eb8.tex}}}} + +\newcommand{\sailRISCVvaltagAddrToAddr}{\saildoclabelled{sailRISCVztagzyaddrzytozyaddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztag_addr_to_addrec4cd9758dc545430904849bc06af049.tex}}}} + +\newcommand{\sailRISCVfntagAddrToAddr}{\saildoclabelled{sailRISCVfnztagzyaddrzytozyaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztag_addr_to_addrec4cd9758dc545430904849bc06af049.tex}}}} + +\newcommand{\sailRISCVvalWriteRAMMeta}{\saildoclabelled{sailRISCVzzyzyWriteRAMzyMeta}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__writeram_meta071a60a48b7f4ceb27499d72826fb174.tex}}}} + +\newcommand{\sailRISCVfnWriteRAMMeta}{\saildoclabelled{sailRISCVfnzzyzyWriteRAMzyMeta}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz__writeram_meta071a60a48b7f4ceb27499d72826fb174.tex}}}} + +\newcommand{\sailRISCVvalReadRAMMeta}{\saildoclabelled{sailRISCVzzyzyReadRAMzyMeta}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__readram_meta16c05ad578ee799cab7403aa8924f5dd.tex}}}} + +\newcommand{\sailRISCVfnReadRAMMeta}{\saildoclabelled{sailRISCVfnzzyzyReadRAMzyMeta}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz__readram_meta16c05ad578ee799cab7403aa8924f5dd.tex}}}} + +\newcommand{\sailRISCVtypemaxMemAccess}{\saildoclabelled{sailRISCVtypezmaxzymemzyaccess}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezmax_mem_access644b1e3f30ca973c2c87d72a6996dab7.tex}}}} + +\newcommand{\sailRISCVvalwriteRam}{\saildoclabelled{sailRISCVzwritezyram}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwrite_ramaf59f53ca3a497b3b8d64cf319996fb8.tex}}}} + +\newcommand{\sailRISCVfnwriteRam}{\saildoclabelled{sailRISCVfnzwritezyram}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwrite_ramaf59f53ca3a497b3b8d64cf319996fb8.tex}}}} + +\newcommand{\sailRISCVvalwriteRamEa}{\saildoclabelled{sailRISCVzwritezyramzyea}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwrite_ram_ea38ee1d0d3a88b7ca22f44ac1921c34c8.tex}}}} + +\newcommand{\sailRISCVfnwriteRamEa}{\saildoclabelled{sailRISCVfnzwritezyramzyea}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwrite_ram_ea38ee1d0d3a88b7ca22f44ac1921c34c8.tex}}}} + +\newcommand{\sailRISCVvalreadRam}{\saildoclabelled{sailRISCVzreadzyram}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzread_ram020d2ffaf84d982d4588177095c24b8e.tex}}}} + +\newcommand{\sailRISCVfnreadRam}{\saildoclabelled{sailRISCVfnzreadzyram}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzread_ram020d2ffaf84d982d4588177095c24b8e.tex}}}} + +\newcommand{\sailRISCVvalTraceMemoryWrite}{\saildoclabelled{sailRISCVzzyzyTraceMemoryWrite}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__tracememorywrite59b064eac2207f0323d075cfc74a28ea.tex}}}} + +\newcommand{\sailRISCVvalTraceMemoryRead}{\saildoclabelled{sailRISCVzzyzyTraceMemoryRead}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz__tracememoryread11a5e2cc4158cfc2c22e91249b3a83cb.tex}}}} + +\newcommand{\sailRISCVtypecapFlagsWidth}{\saildoclabelled{sailRISCVtypezcapzyflagszywidth}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcap_flags_width335bf4f42772a3e75f4dbee10e086942.tex}}}} + +\newcommand{\sailRISCVtypecapUpermsShift}{\saildoclabelled{sailRISCVtypezcapzyupermszyshift}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcap_uperms_shiftbe2a57515ea08a94424ab7ec6686232b.tex}}}} + +\newcommand{\sailRISCVtypecapPermsWidth}{\saildoclabelled{sailRISCVtypezcapzypermszywidth}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcap_perms_widthf1a97a7ea919ad9f42706f84547f5b1a.tex}}}} + +\newcommand{\sailRISCVtypeCapAddrBits}{\saildoclabelled{sailRISCVtypezCapAddrBits}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcapaddrbitsdbb96675d10b9e9b205f71df6a15d202.tex}}}} + +\newcommand{\sailRISCVtypeCapLenBits}{\saildoclabelled{sailRISCVtypezCapLenBits}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcaplenbits0c88c644020f10b2ca144bfbaba3ec9e.tex}}}} + +\newcommand{\sailRISCVtypeCapPermsBits}{\saildoclabelled{sailRISCVtypezCapPermsBits}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcappermsbits6613dfcf198c86f0eab4b7594494ef02.tex}}}} + +\newcommand{\sailRISCVtypeCapFlagsBits}{\saildoclabelled{sailRISCVtypezCapFlagsBits}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcapflagsbitsc0aea8b13e99ce9586aae1d820edcb88.tex}}}} + +\newcommand{\sailRISCVvalgetCapHardPerms}{\saildoclabelled{sailRISCVzgetCapHardPerms}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex}}}} + +\newcommand{\sailRISCVfngetCapHardPerms}{\saildoclabelled{sailRISCVfnzgetCapHardPerms}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex}}}} + +\newcommand{\sailRISCVvalcapToBits}{\saildoclabelled{sailRISCVzcapToBits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcaptobits025010a6e8c284beecc438f72babcc70.tex}}}} + +\newcommand{\sailRISCVfncapToBits}{\saildoclabelled{sailRISCVfnzcapToBits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcaptobits025010a6e8c284beecc438f72babcc70.tex}}}} + +\newcommand{\sailRISCVvalcapToMemBits}{\saildoclabelled{sailRISCVzcapToMemBits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex}}}} + +\newcommand{\sailRISCVfncapToMemBits}{\saildoclabelled{sailRISCVfnzcapToMemBits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex}}}} + +\newcommand{\sailRISCVvalmemBitsToCapability}{\saildoclabelled{sailRISCVzmemBitsToCapability}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex}}}} + +\newcommand{\sailRISCVfnmemBitsToCapability}{\saildoclabelled{sailRISCVfnzmemBitsToCapability}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex}}}} + +\newcommand{\sailRISCVvalgetCapBoundsBits}{\saildoclabelled{sailRISCVzgetCapBoundsBits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetcapboundsbitscff2a996e27fb45794770bad0b82e1fe.tex}}}} + +\newcommand{\sailRISCVfngetCapBoundsBits}{\saildoclabelled{sailRISCVfnzgetCapBoundsBits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetcapboundsbitscff2a996e27fb45794770bad0b82e1fe.tex}}}} + +\newcommand{\sailRISCVvalgetCapBounds}{\saildoclabelled{sailRISCVzgetCapBounds}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex}}}} + +\newcommand{\sailRISCVfngetCapBounds}{\saildoclabelled{sailRISCVfnzgetCapBounds}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex}}}} + +\newcommand{\sailRISCVvalsetCapBounds}{\saildoclabelled{sailRISCVzsetCapBounds}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex}}}} + +\newcommand{\sailRISCVfnsetCapBounds}{\saildoclabelled{sailRISCVfnzsetCapBounds}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex}}}} + +\newcommand{\sailRISCVvalgetCapPerms}{\saildoclabelled{sailRISCVzgetCapPerms}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetcapperms6aed04c1602f540bb5d604425f922d92.tex}}}} + +\newcommand{\sailRISCVfngetCapPerms}{\saildoclabelled{sailRISCVfnzgetCapPerms}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetcapperms6aed04c1602f540bb5d604425f922d92.tex}}}} + +\newcommand{\sailRISCVvalsetCapPerms}{\saildoclabelled{sailRISCVzsetCapPerms}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex}}}} + +\newcommand{\sailRISCVfnsetCapPerms}{\saildoclabelled{sailRISCVfnzsetCapPerms}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex}}}} + +\newcommand{\sailRISCVvalgetCapFlags}{\saildoclabelled{sailRISCVzgetCapFlags}{\saildocval{Gets the architecture specific capability flags for given capability. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex}}}} + +\newcommand{\sailRISCVfngetCapFlags}{\saildoclabelled{sailRISCVfnzgetCapFlags}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex}}}} + +\newcommand{\sailRISCVvalsetCapFlags}{\saildoclabelled{sailRISCVzsetCapFlags}{\saildocval{\lstinline{setCapFlags}\lstinline`(cap, flags)` sets the architecture specific capability flags on \lstinline`cap` +to \lstinline`flags` and returns the result as new capability. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex}}}} + +\newcommand{\sailRISCVfnsetCapFlags}{\saildoclabelled{sailRISCVfnzsetCapFlags}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex}}}} + +\newcommand{\sailRISCVvalisCapSealed}{\saildoclabelled{sailRISCVzisCapSealed}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valziscapsealeda9077bc28a9d2efcd12e42755a4de536.tex}}}} + +\newcommand{\sailRISCVfnisCapSealed}{\saildoclabelled{sailRISCVfnzisCapSealed}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnziscapsealeda9077bc28a9d2efcd12e42755a4de536.tex}}}} + +\newcommand{\sailRISCVvalhasReservedOType}{\saildoclabelled{sailRISCVzhasReservedOType}{\saildocval{Tests whether the capability has a reserved otype (larger than \hyperref[sailRISCVzmaxzyotype]{\lstinline{max_otype}}). +Note that this includes both sealed (\saildocabbrev{e.g.} sentry) and unsealed (all ones) +otypes. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex}}}} + +\newcommand{\sailRISCVfnhasReservedOType}{\saildoclabelled{sailRISCVfnzhasReservedOType}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex}}}} + +\newcommand{\sailRISCVvalsealCap}{\saildoclabelled{sailRISCVzsealCap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex}}}} + +\newcommand{\sailRISCVfnsealCap}{\saildoclabelled{sailRISCVfnzsealCap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex}}}} + +\newcommand{\sailRISCVvalunsealCap}{\saildoclabelled{sailRISCVzunsealCap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzunsealcap58689ae49a7317c60147327414a678d2.tex}}}} + +\newcommand{\sailRISCVfnunsealCap}{\saildoclabelled{sailRISCVfnzunsealCap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzunsealcap58689ae49a7317c60147327414a678d2.tex}}}} + +\newcommand{\sailRISCVvalgetCapBaseBits}{\saildoclabelled{sailRISCVzgetCapBaseBits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetcapbasebits475f0d31f4d2e3d821fa3069875fc752.tex}}}} + +\newcommand{\sailRISCVfngetCapBaseBits}{\saildoclabelled{sailRISCVfnzgetCapBaseBits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetcapbasebits475f0d31f4d2e3d821fa3069875fc752.tex}}}} + +\newcommand{\sailRISCVvalgetCapBase}{\saildoclabelled{sailRISCVzgetCapBase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex}}}} + +\newcommand{\sailRISCVfngetCapBase}{\saildoclabelled{sailRISCVfnzgetCapBase}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex}}}} + +\newcommand{\sailRISCVvalgetCapTopBits}{\saildoclabelled{sailRISCVzgetCapTopBits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetcaptopbits5ee890f973b03f4c37ec6911afe96449.tex}}}} + +\newcommand{\sailRISCVfngetCapTopBits}{\saildoclabelled{sailRISCVfnzgetCapTopBits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetcaptopbits5ee890f973b03f4c37ec6911afe96449.tex}}}} + +\newcommand{\sailRISCVvalgetCapTop}{\saildoclabelled{sailRISCVzgetCapTop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex}}}} + +\newcommand{\sailRISCVfngetCapTop}{\saildoclabelled{sailRISCVfnzgetCapTop}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex}}}} + +\newcommand{\sailRISCVvalgetCapOffsetBits}{\saildoclabelled{sailRISCVzgetCapOffsetBits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetcapoffsetbits4ee7332151f133f0a8370e45dc0808ca.tex}}}} + +\newcommand{\sailRISCVfngetCapOffsetBits}{\saildoclabelled{sailRISCVfnzgetCapOffsetBits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetcapoffsetbits4ee7332151f133f0a8370e45dc0808ca.tex}}}} + +\newcommand{\sailRISCVvalgetCapOffset}{\saildoclabelled{sailRISCVzgetCapOffset}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex}}}} + +\newcommand{\sailRISCVfngetCapOffset}{\saildoclabelled{sailRISCVfnzgetCapOffset}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex}}}} + +\newcommand{\sailRISCVvalgetCapLength}{\saildoclabelled{sailRISCVzgetCapLength}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex}}}} + +\newcommand{\sailRISCVfngetCapLength}{\saildoclabelled{sailRISCVfnzgetCapLength}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex}}}} + +\newcommand{\sailRISCVvalinCapBounds}{\saildoclabelled{sailRISCVzinCapBounds}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzincapboundsc6e70952d3c6507cf32d75b499b90335.tex}}}} + +\newcommand{\sailRISCVfninCapBounds}{\saildoclabelled{sailRISCVfnzinCapBounds}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzincapboundsc6e70952d3c6507cf32d75b499b90335.tex}}}} + +\newcommand{\sailRISCVvalgetCapCursor}{\saildoclabelled{sailRISCVzgetCapCursor}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex}}}} + +\newcommand{\sailRISCVfngetCapCursor}{\saildoclabelled{sailRISCVfnzgetCapCursor}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex}}}} + +\newcommand{\sailRISCVvalintToCap}{\saildoclabelled{sailRISCVzintzytozycap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzint_to_capf8526cbe276f6bcb8e84d62c62d4f9a1.tex}}}} + +\newcommand{\sailRISCVfnintToCap}{\saildoclabelled{sailRISCVfnzintzytozycap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzint_to_capf8526cbe276f6bcb8e84d62c62d4f9a1.tex}}}} + +\newcommand{\sailRISCVvalinvalidateCap}{\saildoclabelled{sailRISCVzinvalidateCap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinvalidatecap831c5555c31b163a19988faa291f9c20.tex}}}} + +\newcommand{\sailRISCVfninvalidateCap}{\saildoclabelled{sailRISCVfnzinvalidateCap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinvalidatecap831c5555c31b163a19988faa291f9c20.tex}}}} + +\newcommand{\sailRISCVvalcapBoundsEqual}{\saildoclabelled{sailRISCVzcapBoundsEqual}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex}}}} + +\newcommand{\sailRISCVfncapBoundsEqual}{\saildoclabelled{sailRISCVfnzcapBoundsEqual}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex}}}} + +\newcommand{\sailRISCVvalsetCapAddr}{\saildoclabelled{sailRISCVzsetCapAddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex}}}} + +\newcommand{\sailRISCVfnsetCapAddr}{\saildoclabelled{sailRISCVfnzsetCapAddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex}}}} + +\newcommand{\sailRISCVoverloadXXzEightoperatorzZerozKzKzNine}{\saildoclabelled{sailRISCVoverloadXXzz8operatorz0zKzKz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex}}}} + +\newcommand{\sailRISCVoverloadYYzEightoperatorzZerozIzIzNine}{\saildoclabelled{sailRISCVoverloadYYzz8operatorz0zIzIz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex}}}} + +\newcommand{\sailRISCVoverloadZZzEightoperatorzZerozKzKSzNine}{\saildoclabelled{sailRISCVoverloadZZzz8operatorz0zKzKzysz9}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex}}}} + +\newcommand{\sailRISCVvalfastRepCheck}{\saildoclabelled{sailRISCVzfastRepCheck}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfastrepcheck592cc92c49a4599da60647f87c331420.tex}}}} + +\newcommand{\sailRISCVfnfastRepCheck}{\saildoclabelled{sailRISCVfnzfastRepCheck}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfastrepcheck592cc92c49a4599da60647f87c331420.tex}}}} + +\newcommand{\sailRISCVvalsetCapOffset}{\saildoclabelled{sailRISCVzsetCapOffset}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex}}}} + +\newcommand{\sailRISCVfnsetCapOffset}{\saildoclabelled{sailRISCVfnzsetCapOffset}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex}}}} + +\newcommand{\sailRISCVvalsetCapOffsetOrNull}{\saildoclabelled{sailRISCVzsetCapOffsetOrNull}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsetcapoffsetornullc7b6ed6c2844187ec5b671dc1ca3eae0.tex}}}} + +\newcommand{\sailRISCVfnsetCapOffsetOrNull}{\saildoclabelled{sailRISCVfnzsetCapOffsetOrNull}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsetcapoffsetornullc7b6ed6c2844187ec5b671dc1ca3eae0.tex}}}} + +\newcommand{\sailRISCVvalincCapOffset}{\saildoclabelled{sailRISCVzincCapOffset}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinccapoffsetc4735d243650e78b90bacb6efb419260.tex}}}} + +\newcommand{\sailRISCVfnincCapOffset}{\saildoclabelled{sailRISCVfnzincCapOffset}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinccapoffsetc4735d243650e78b90bacb6efb419260.tex}}}} + +\newcommand{\sailRISCVvalcapToString}{\saildoclabelled{sailRISCVzcapToString}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex}}}} + +\newcommand{\sailRISCVfncapToString}{\saildoclabelled{sailRISCVfnzcapToString}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex}}}} + +\newcommand{\sailRISCVvalgetRepresentableAlignmentMask}{\saildoclabelled{sailRISCVzgetRepresentableAlignmentMask}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex}}}} + +\newcommand{\sailRISCVfngetRepresentableAlignmentMask}{\saildoclabelled{sailRISCVfnzgetRepresentableAlignmentMask}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex}}}} + +\newcommand{\sailRISCVvalgetRepresentableLength}{\saildoclabelled{sailRISCVzgetRepresentableLength}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex}}}} + +\newcommand{\sailRISCVfngetRepresentableLength}{\saildoclabelled{sailRISCVfnzgetRepresentableLength}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex}}}} + +\newcommand{\sailRISCVtypeexcCode}{\saildoclabelled{sailRISCVtypezexczycode}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezexc_code41fa41b8abb196633a02f07b51e90738.tex}}}} + +\newcommand{\sailRISCVtypeextPtwLc}{\saildoclabelled{sailRISCVtypezextzyptwzylc}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_ptw_lcbba545a858359524aa6ef05819a4c22a.tex}}}} + +\newcommand{\sailRISCVvalextPtwLcOfNum}{\saildoclabelled{sailRISCVzextzyptwzylczyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_ptw_lc_of_numfefbb86ad247369523da5c5114df83a8.tex}}}} + +\newcommand{\sailRISCVfnextPtwLcOfNum}{\saildoclabelled{sailRISCVfnzextzyptwzylczyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_ptw_lc_of_numfefbb86ad247369523da5c5114df83a8.tex}}}} + +\newcommand{\sailRISCVvalnumOfExtPtwLc}{\saildoclabelled{sailRISCVznumzyofzyextzyptwzylc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_ext_ptw_lcfde46f3a7b817078010b5dc3a4f25be7.tex}}}} + +\newcommand{\sailRISCVfnnumOfExtPtwLc}{\saildoclabelled{sailRISCVfnznumzyofzyextzyptwzylc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_ext_ptw_lcfde46f3a7b817078010b5dc3a4f25be7.tex}}}} + +\newcommand{\sailRISCVtypeextPtwSc}{\saildoclabelled{sailRISCVtypezextzyptwzysc}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_ptw_sccf7d1fb4d0ca02c7aa470f10faacf4b9.tex}}}} + +\newcommand{\sailRISCVvalextPtwScOfNum}{\saildoclabelled{sailRISCVzextzyptwzysczyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_ptw_sc_of_num2137f22f5407b82d12c8574662600e18.tex}}}} + +\newcommand{\sailRISCVfnextPtwScOfNum}{\saildoclabelled{sailRISCVfnzextzyptwzysczyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_ptw_sc_of_num2137f22f5407b82d12c8574662600e18.tex}}}} + +\newcommand{\sailRISCVvalnumOfExtPtwSc}{\saildoclabelled{sailRISCVznumzyofzyextzyptwzysc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_ext_ptw_sc2a22418de077e3289633414d48a30bbe.tex}}}} + +\newcommand{\sailRISCVfnnumOfExtPtwSc}{\saildoclabelled{sailRISCVfnznumzyofzyextzyptwzysc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_ext_ptw_sc2a22418de077e3289633414d48a30bbe.tex}}}} + +\newcommand{\sailRISCVtypeextPtw}{\saildoclabelled{sailRISCVtypezextzyptw}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_ptwde60d7352876746c4773d53f332b5137.tex}}}} + +\newcommand{\sailRISCVvalextPtwLcJoin}{\saildoclabelled{sailRISCVzextzyptwzylczyjoin}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_ptw_lc_joindc735a27ea989374f5eabf813141d337.tex}}}} + +\newcommand{\sailRISCVfnextPtwLcJoin}{\saildoclabelled{sailRISCVfnzextzyptwzylczyjoin}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_ptw_lc_joindc735a27ea989374f5eabf813141d337.tex}}}} + +\newcommand{\sailRISCVvalextPtwScJoin}{\saildoclabelled{sailRISCVzextzyptwzysczyjoin}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_ptw_sc_join88636243b559a2aba809497742e7ce00.tex}}}} + +\newcommand{\sailRISCVfnextPtwScJoin}{\saildoclabelled{sailRISCVfnzextzyptwzysczyjoin}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_ptw_sc_join88636243b559a2aba809497742e7ce00.tex}}}} + +\newcommand{\sailRISCVtypeextPtwFail}{\saildoclabelled{sailRISCVtypezextzyptwzyfail}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_ptw_fail2875647ee1ba483d4a452f6a98fef854.tex}}}} + +\newcommand{\sailRISCVvalextPtwFailOfNum}{\saildoclabelled{sailRISCVzextzyptwzyfailzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_ptw_fail_of_numcc5cb6ad05de49125f246aa8627fb15b.tex}}}} + +\newcommand{\sailRISCVfnextPtwFailOfNum}{\saildoclabelled{sailRISCVfnzextzyptwzyfailzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_ptw_fail_of_numcc5cb6ad05de49125f246aa8627fb15b.tex}}}} + +\newcommand{\sailRISCVvalnumOfExtPtwFail}{\saildoclabelled{sailRISCVznumzyofzyextzyptwzyfail}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_ext_ptw_fail785ab48a0d85159cd76e2d20768c9173.tex}}}} + +\newcommand{\sailRISCVfnnumOfExtPtwFail}{\saildoclabelled{sailRISCVfnznumzyofzyextzyptwzyfail}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_ext_ptw_fail785ab48a0d85159cd76e2d20768c9173.tex}}}} + +\newcommand{\sailRISCVtypeextPtwError}{\saildoclabelled{sailRISCVtypezextzyptwzyerror}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_ptw_error5964337ea2d10baef1f3c2ff9d6e6893.tex}}}} + +\newcommand{\sailRISCVvalextPtwErrorOfNum}{\saildoclabelled{sailRISCVzextzyptwzyerrorzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_ptw_error_of_num6c265a5359168121d0772efe3f31cd45.tex}}}} + +\newcommand{\sailRISCVfnextPtwErrorOfNum}{\saildoclabelled{sailRISCVfnzextzyptwzyerrorzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_ptw_error_of_num6c265a5359168121d0772efe3f31cd45.tex}}}} + +\newcommand{\sailRISCVvalnumOfExtPtwError}{\saildoclabelled{sailRISCVznumzyofzyextzyptwzyerror}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_ext_ptw_error7daeb8fc5a17e215ccad3f2a24541927.tex}}}} + +\newcommand{\sailRISCVfnnumOfExtPtwError}{\saildoclabelled{sailRISCVfnznumzyofzyextzyptwzyerror}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_ext_ptw_error7daeb8fc5a17e215ccad3f2a24541927.tex}}}} + +\newcommand{\sailRISCVtypeextExcType}{\saildoclabelled{sailRISCVtypezextzyexczytype}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_exc_type73c827d8e97122989947956ad800fcf5.tex}}}} + +\newcommand{\sailRISCVvalextExcTypeOfNum}{\saildoclabelled{sailRISCVzextzyexczytypezyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_exc_type_of_numa5807bd3284ecfd6e2edf0e304dee26e.tex}}}} + +\newcommand{\sailRISCVfnextExcTypeOfNum}{\saildoclabelled{sailRISCVfnzextzyexczytypezyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_exc_type_of_numa5807bd3284ecfd6e2edf0e304dee26e.tex}}}} + +\newcommand{\sailRISCVvalextExcTypeToBits}{\saildoclabelled{sailRISCVzextzyexczytypezytozybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_exc_type_to_bitse12334413f8dedca96749d4413e3150b.tex}}}} + +\newcommand{\sailRISCVfnextExcTypeToBits}{\saildoclabelled{sailRISCVfnzextzyexczytypezytozybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_exc_type_to_bitse12334413f8dedca96749d4413e3150b.tex}}}} + +\newcommand{\sailRISCVvalnumOfExtExcType}{\saildoclabelled{sailRISCVznumzyofzyextzyexczytype}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_ext_exc_type79451fb17925bed3ec8d5058c42d301d.tex}}}} + +\newcommand{\sailRISCVfnnumOfExtExcType}{\saildoclabelled{sailRISCVfnznumzyofzyextzyexczytype}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_ext_exc_type79451fb17925bed3ec8d5058c42d301d.tex}}}} + +\newcommand{\sailRISCVvalextExcTypeToStr}{\saildoclabelled{sailRISCVzextzyexczytypezytozystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_exc_type_to_strc4b005a75959aeec9fce26f39219c666.tex}}}} + +\newcommand{\sailRISCVfnextExcTypeToStr}{\saildoclabelled{sailRISCVfnzextzyexczytypezytozystr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_exc_type_to_strc4b005a75959aeec9fce26f39219c666.tex}}}} + +\newcommand{\sailRISCVtypehalf}{\saildoclabelled{sailRISCVtypezhalf}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezhalf6766630885293c014a0c4687f74d88fa.tex}}}} + +\newcommand{\sailRISCVtypeword}{\saildoclabelled{sailRISCVtypezword}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezword9ee2a7d7876193e4985e692f6ae78f08.tex}}}} + +\newcommand{\sailRISCVtyperegidx}{\saildoclabelled{sailRISCVtypezregidx}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezregidxb20ed6db135b3db9440370ddc1897517.tex}}}} + +\newcommand{\sailRISCVtypecregidx}{\saildoclabelled{sailRISCVtypezcregidx}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcregidx93aa5af192dfa10c34a9c84f0c2ce1a1.tex}}}} + +\newcommand{\sailRISCVtypecsreg}{\saildoclabelled{sailRISCVtypezcsreg}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcsreg01b93a287ca075effde1c3cdbc173b4e.tex}}}} + +\newcommand{\sailRISCVtyperegno}{\saildoclabelled{sailRISCVtypezregno}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezregno1c2cd9b00ff5d991528ec5d711c3ace5.tex}}}} + +\newcommand{\sailRISCVvalregidxToRegno}{\saildoclabelled{sailRISCVzregidxzytozyregno}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzregidx_to_regno46c7ee8e863ba355f36bf094aa680714.tex}}}} + +\newcommand{\sailRISCVfnregidxToRegno}{\saildoclabelled{sailRISCVfnzregidxzytozyregno}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzregidx_to_regno46c7ee8e863ba355f36bf094aa680714.tex}}}} + +\newcommand{\sailRISCVvalcregTworegIdx}{\saildoclabelled{sailRISCVzcreg2regzyidx}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcreg2reg_idxe272195325d960d58ce119619a5a1c75.tex}}}} + +\newcommand{\sailRISCVfncregTworegIdx}{\saildoclabelled{sailRISCVfnzcreg2regzyidx}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcreg2reg_idxe272195325d960d58ce119619a5a1c75.tex}}}} + +\newcommand{\sailRISCVtypeopcode}{\saildoclabelled{sailRISCVtypezopcode}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezopcode9a1291b5342e38220790ad44491e6b07.tex}}}} + +\newcommand{\sailRISCVtypeimmOneTwo}{\saildoclabelled{sailRISCVtypezimm12}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezimm12deef2ca6ef7ab7db2c410afab5972c9d.tex}}}} + +\newcommand{\sailRISCVtypeimmTwoZero}{\saildoclabelled{sailRISCVtypezimm20}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezimm20575f3ad0e57a29fe015b13b4df3641d3.tex}}}} + +\newcommand{\sailRISCVtypeamo}{\saildoclabelled{sailRISCVtypezamo}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezamo83bf3a088c1fa727e8019cb088f80417.tex}}}} + +\newcommand{\sailRISCVtypeArchitecture}{\saildoclabelled{sailRISCVtypezArchitecture}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezarchitecture5b5b6aa873a23d1ef07eac267bb6da07.tex}}}} + +\newcommand{\sailRISCVvalArchitectureOfNum}{\saildoclabelled{sailRISCVzArchitecturezyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzarchitecture_of_num798cfe8625bb4fedb9343d4984208b4c.tex}}}} + +\newcommand{\sailRISCVfnArchitectureOfNum}{\saildoclabelled{sailRISCVfnzArchitecturezyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzarchitecture_of_num798cfe8625bb4fedb9343d4984208b4c.tex}}}} + +\newcommand{\sailRISCVvalnumOfArchitecture}{\saildoclabelled{sailRISCVznumzyofzyArchitecture}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_architecture1ae1fee7c4b64fc1c08b7336a9784f4a.tex}}}} + +\newcommand{\sailRISCVfnnumOfArchitecture}{\saildoclabelled{sailRISCVfnznumzyofzyArchitecture}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_architecture1ae1fee7c4b64fc1c08b7336a9784f4a.tex}}}} + +\newcommand{\sailRISCVtypearchXlen}{\saildoclabelled{sailRISCVtypezarchzyxlen}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezarch_xlene776da3b62a5ddb22c2789a29c4f62e0.tex}}}} + +\newcommand{\sailRISCVvalarchitecture}{\saildoclabelled{sailRISCVzarchitecture}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzarchitecture892e99af11725086f28c1c30cefffa9c.tex}}}} + +\newcommand{\sailRISCVfnarchitecture}{\saildoclabelled{sailRISCVfnzarchitecture}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzarchitecture892e99af11725086f28c1c30cefffa9c.tex}}}} + +\newcommand{\sailRISCVvalarchToBits}{\saildoclabelled{sailRISCVzarchzytozybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzarch_to_bits5b82edd15605cd21ec0f9d9dc63af541.tex}}}} + +\newcommand{\sailRISCVfnarchToBits}{\saildoclabelled{sailRISCVfnzarchzytozybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzarch_to_bits5b82edd15605cd21ec0f9d9dc63af541.tex}}}} + +\newcommand{\sailRISCVtypeprivLevel}{\saildoclabelled{sailRISCVtypezprivzylevel}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpriv_leveld5cdc3b186bdc20eb05333efc3cfd01c.tex}}}} + +\newcommand{\sailRISCVtypePrivilege}{\saildoclabelled{sailRISCVtypezPrivilege}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezprivilege9997cec8360c7da9f3608ad36bf538cc.tex}}}} + +\newcommand{\sailRISCVvalPrivilegeOfNum}{\saildoclabelled{sailRISCVzPrivilegezyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprivilege_of_num84ee3b92a1b0c896120347634e28615d.tex}}}} + +\newcommand{\sailRISCVfnPrivilegeOfNum}{\saildoclabelled{sailRISCVfnzPrivilegezyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprivilege_of_num84ee3b92a1b0c896120347634e28615d.tex}}}} + +\newcommand{\sailRISCVvalnumOfPrivilege}{\saildoclabelled{sailRISCVznumzyofzyPrivilege}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_privilege40c636ca569f6d4bb59a57bee3b2742d.tex}}}} + +\newcommand{\sailRISCVfnnumOfPrivilege}{\saildoclabelled{sailRISCVfnznumzyofzyPrivilege}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_privilege40c636ca569f6d4bb59a57bee3b2742d.tex}}}} + +\newcommand{\sailRISCVvalprivLevelToBits}{\saildoclabelled{sailRISCVzprivLevelzytozybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprivlevel_to_bits4b6f72dec94db401093759e81957be6b.tex}}}} + +\newcommand{\sailRISCVfnprivLevelToBits}{\saildoclabelled{sailRISCVfnzprivLevelzytozybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprivlevel_to_bits4b6f72dec94db401093759e81957be6b.tex}}}} + +\newcommand{\sailRISCVvalprivLevelOfBits}{\saildoclabelled{sailRISCVzprivLevelzyofzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprivlevel_of_bitsf8754d7aa9d9aeada7d193ecf64e148c.tex}}}} + +\newcommand{\sailRISCVfnprivLevelOfBits}{\saildoclabelled{sailRISCVfnzprivLevelzyofzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprivlevel_of_bitsf8754d7aa9d9aeada7d193ecf64e148c.tex}}}} + +\newcommand{\sailRISCVvalprivLevelToStr}{\saildoclabelled{sailRISCVzprivLevelzytozystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprivlevel_to_str130b731da9dd60ea89c77efcbbe0d598.tex}}}} + +\newcommand{\sailRISCVfnprivLevelToStr}{\saildoclabelled{sailRISCVfnzprivLevelzytozystr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprivlevel_to_str130b731da9dd60ea89c77efcbbe0d598.tex}}}} + +\newcommand{\sailRISCVoverloadAAAtoStr}{\saildoclabelled{sailRISCVoverloadAAAztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} + +\newcommand{\sailRISCVtypeRetired}{\saildoclabelled{sailRISCVtypezRetired}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezretired3cb36a9311620933468743a8b2d2f6f4.tex}}}} + +\newcommand{\sailRISCVvalRetiredOfNum}{\saildoclabelled{sailRISCVzRetiredzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzretired_of_num68ab3748534f762d814246f11fcf7c77.tex}}}} + +\newcommand{\sailRISCVfnRetiredOfNum}{\saildoclabelled{sailRISCVfnzRetiredzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzretired_of_num68ab3748534f762d814246f11fcf7c77.tex}}}} + +\newcommand{\sailRISCVvalnumOfRetired}{\saildoclabelled{sailRISCVznumzyofzyRetired}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_retiredc5322d8e56eb574c7eb3ebf89e0586af.tex}}}} + +\newcommand{\sailRISCVfnnumOfRetired}{\saildoclabelled{sailRISCVfnznumzyofzyRetired}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_retiredc5322d8e56eb574c7eb3ebf89e0586af.tex}}}} + +\newcommand{\sailRISCVtypeAccessType}{\saildoclabelled{sailRISCVtypezAccessType}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezaccesstype627dc4f8d60f616c352a3659c0dfbd61.tex}}}} + +\newcommand{\sailRISCVtypewordWidth}{\saildoclabelled{sailRISCVtypezwordzywidth}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezword_width15338b31164a0d031656f7f88e6114c8.tex}}}} + +\newcommand{\sailRISCVvalwordWidthOfNum}{\saildoclabelled{sailRISCVzwordzywidthzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzword_width_of_num5022e9594f19a45eb3d8079a7a770a00.tex}}}} + +\newcommand{\sailRISCVfnwordWidthOfNum}{\saildoclabelled{sailRISCVfnzwordzywidthzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzword_width_of_num5022e9594f19a45eb3d8079a7a770a00.tex}}}} + +\newcommand{\sailRISCVvalnumOfWordWidth}{\saildoclabelled{sailRISCVznumzyofzywordzywidth}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_word_width80798ebf687d8b1ac16aea948967912d.tex}}}} + +\newcommand{\sailRISCVfnnumOfWordWidth}{\saildoclabelled{sailRISCVfnznumzyofzywordzywidth}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_word_width80798ebf687d8b1ac16aea948967912d.tex}}}} + +\newcommand{\sailRISCVtypeInterruptType}{\saildoclabelled{sailRISCVtypezInterruptType}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezinterrupttypeea26f192039f815bc5d0d5b058b4fac2.tex}}}} + +\newcommand{\sailRISCVvalInterruptTypeOfNum}{\saildoclabelled{sailRISCVzInterruptTypezyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinterrupttype_of_numbcca70e199dd805ea962d03dd661ceb8.tex}}}} + +\newcommand{\sailRISCVfnInterruptTypeOfNum}{\saildoclabelled{sailRISCVfnzInterruptTypezyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinterrupttype_of_numbcca70e199dd805ea962d03dd661ceb8.tex}}}} + +\newcommand{\sailRISCVvalnumOfInterruptType}{\saildoclabelled{sailRISCVznumzyofzyInterruptType}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_interrupttype186751debed5f5a4e5f875749623071b.tex}}}} + +\newcommand{\sailRISCVfnnumOfInterruptType}{\saildoclabelled{sailRISCVfnznumzyofzyInterruptType}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_interrupttype186751debed5f5a4e5f875749623071b.tex}}}} + +\newcommand{\sailRISCVvalinterruptTypeToBits}{\saildoclabelled{sailRISCVzinterruptTypezytozybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinterrupttype_to_bits80d6193c8205e91dcda1e3a5b6126a81.tex}}}} + +\newcommand{\sailRISCVfninterruptTypeToBits}{\saildoclabelled{sailRISCVfnzinterruptTypezytozybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinterrupttype_to_bits80d6193c8205e91dcda1e3a5b6126a81.tex}}}} + +\newcommand{\sailRISCVtypeExceptionType}{\saildoclabelled{sailRISCVtypezExceptionType}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezexceptiontype8574cf8632bbc8e423ccb2d23e61bdff.tex}}}} + +\newcommand{\sailRISCVvalexceptionTypeToBits}{\saildoclabelled{sailRISCVzexceptionTypezytozybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzexceptiontype_to_bits6edc76877c2677590096c351d9b431f1.tex}}}} + +\newcommand{\sailRISCVfnexceptionTypeToBits}{\saildoclabelled{sailRISCVfnzexceptionTypezytozybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzexceptiontype_to_bits6edc76877c2677590096c351d9b431f1.tex}}}} + +\newcommand{\sailRISCVvalnumOfExceptionType}{\saildoclabelled{sailRISCVznumzyofzyExceptionType}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_exceptiontype13e59fd83201d81140ba0f6bbcbd1a7b.tex}}}} + +\newcommand{\sailRISCVfnnumOfExceptionType}{\saildoclabelled{sailRISCVfnznumzyofzyExceptionType}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_exceptiontype13e59fd83201d81140ba0f6bbcbd1a7b.tex}}}} + +\newcommand{\sailRISCVvalexceptionTypeToStr}{\saildoclabelled{sailRISCVzexceptionTypezytozystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzexceptiontype_to_str566b70f16fdf6ed4d1850ec75465ec4b.tex}}}} + +\newcommand{\sailRISCVfnexceptionTypeToStr}{\saildoclabelled{sailRISCVfnzexceptionTypezytozystr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzexceptiontype_to_str566b70f16fdf6ed4d1850ec75465ec4b.tex}}}} + +\newcommand{\sailRISCVoverloadBBBtoStr}{\saildoclabelled{sailRISCVoverloadBBBztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} + +\newcommand{\sailRISCVtypeexception}{\saildoclabelled{sailRISCVtypezexception}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezexceptionfaa4db8fab65c538edad4222e766a71a.tex}}}} + +\newcommand{\sailRISCVvalnotImplemented}{\saildoclabelled{sailRISCVznotzyimplemented}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznot_implementedde41164205ef21773733c511f05a2946.tex}}}} + +\newcommand{\sailRISCVfnnotImplemented}{\saildoclabelled{sailRISCVfnznotzyimplemented}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznot_implementedde41164205ef21773733c511f05a2946.tex}}}} + +\newcommand{\sailRISCVvalinternalError}{\saildoclabelled{sailRISCVzinternalzyerror}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinternal_error92c3548c19282819d20d44565303aa89.tex}}}} + +\newcommand{\sailRISCVfninternalError}{\saildoclabelled{sailRISCVfnzinternalzyerror}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinternal_error92c3548c19282819d20d44565303aa89.tex}}}} + +\newcommand{\sailRISCVtypetvMode}{\saildoclabelled{sailRISCVtypeztvzymode}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typeztv_modea724d5138c36f1ab6005c9051bd94ea0.tex}}}} + +\newcommand{\sailRISCVtypeTrapVectorMode}{\saildoclabelled{sailRISCVtypezTrapVectorMode}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typeztrapvectormodecc7f1b98e2e9e9062e5f9a94be7a00dd.tex}}}} + +\newcommand{\sailRISCVvalTrapVectorModeOfNum}{\saildoclabelled{sailRISCVzTrapVectorModezyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztrapvectormode_of_num8f2938d16cb187b62f9cdbbb35278d48.tex}}}} + +\newcommand{\sailRISCVfnTrapVectorModeOfNum}{\saildoclabelled{sailRISCVfnzTrapVectorModezyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztrapvectormode_of_num8f2938d16cb187b62f9cdbbb35278d48.tex}}}} + +\newcommand{\sailRISCVvalnumOfTrapVectorMode}{\saildoclabelled{sailRISCVznumzyofzyTrapVectorMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_trapvectormode9673c0ba1b150ae7d0c789bf1ea8f4fe.tex}}}} + +\newcommand{\sailRISCVfnnumOfTrapVectorMode}{\saildoclabelled{sailRISCVfnznumzyofzyTrapVectorMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_trapvectormode9673c0ba1b150ae7d0c789bf1ea8f4fe.tex}}}} + +\newcommand{\sailRISCVvaltrapVectorModeOfBits}{\saildoclabelled{sailRISCVztrapVectorModezyofzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztrapvectormode_of_bits3ab887814163c96ab28aec41cb9b44f6.tex}}}} + +\newcommand{\sailRISCVfntrapVectorModeOfBits}{\saildoclabelled{sailRISCVfnztrapVectorModezyofzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztrapvectormode_of_bits3ab887814163c96ab28aec41cb9b44f6.tex}}}} + +\newcommand{\sailRISCVtypeextStatus}{\saildoclabelled{sailRISCVtypezextzystatus}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_statuscc754716d0653fa6ecbe317b319fb0e7.tex}}}} + +\newcommand{\sailRISCVtypeExtStatus}{\saildoclabelled{sailRISCVtypezExtStatus}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezextstatus48f045aa452fc429aaaaf8df3f7b4a71.tex}}}} + +\newcommand{\sailRISCVvalExtStatusOfNum}{\saildoclabelled{sailRISCVzExtStatuszyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextstatus_of_num31bfbda5f90ad0f3cdbc5a0f1b63da2d.tex}}}} + +\newcommand{\sailRISCVfnExtStatusOfNum}{\saildoclabelled{sailRISCVfnzExtStatuszyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzextstatus_of_num31bfbda5f90ad0f3cdbc5a0f1b63da2d.tex}}}} + +\newcommand{\sailRISCVvalnumOfExtStatus}{\saildoclabelled{sailRISCVznumzyofzyExtStatus}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_extstatus8d29ae3139c8c2d5d4fa7489689b6a41.tex}}}} + +\newcommand{\sailRISCVfnnumOfExtStatus}{\saildoclabelled{sailRISCVfnznumzyofzyExtStatus}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_extstatus8d29ae3139c8c2d5d4fa7489689b6a41.tex}}}} + +\newcommand{\sailRISCVvalextStatusToBits}{\saildoclabelled{sailRISCVzextStatuszytozybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextstatus_to_bits95f7e744a463eb9cfccacc81efa252ae.tex}}}} + +\newcommand{\sailRISCVfnextStatusToBits}{\saildoclabelled{sailRISCVfnzextStatuszytozybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzextstatus_to_bits95f7e744a463eb9cfccacc81efa252ae.tex}}}} + +\newcommand{\sailRISCVvalextStatusOfBits}{\saildoclabelled{sailRISCVzextStatuszyofzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextstatus_of_bits9da79344bfec7cda3e374a5ba6b49e27.tex}}}} + +\newcommand{\sailRISCVfnextStatusOfBits}{\saildoclabelled{sailRISCVfnzextStatuszyofzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzextstatus_of_bits9da79344bfec7cda3e374a5ba6b49e27.tex}}}} + +\newcommand{\sailRISCVtypesatpMode}{\saildoclabelled{sailRISCVtypezsatpzymode}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsatp_mode578b50fd69503e82abb4182613570ec9.tex}}}} + +\newcommand{\sailRISCVtypeSATPMode}{\saildoclabelled{sailRISCVtypezSATPMode}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsatpmodedc53ce733006f254af9d4e33c8ed6401.tex}}}} + +\newcommand{\sailRISCVvalSATPModeOfNum}{\saildoclabelled{sailRISCVzSATPModezyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsatpmode_of_num09ad57622dbe0d0a7b111194f1a36856.tex}}}} + +\newcommand{\sailRISCVfnSATPModeOfNum}{\saildoclabelled{sailRISCVfnzSATPModezyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsatpmode_of_num09ad57622dbe0d0a7b111194f1a36856.tex}}}} + +\newcommand{\sailRISCVvalnumOfSATPMode}{\saildoclabelled{sailRISCVznumzyofzySATPMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_satpmode714998a67cc48d1f59bc52de3d9a052f.tex}}}} + +\newcommand{\sailRISCVfnnumOfSATPMode}{\saildoclabelled{sailRISCVfnznumzyofzySATPMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_satpmode714998a67cc48d1f59bc52de3d9a052f.tex}}}} + +\newcommand{\sailRISCVvalsatpSixFourModeOfBits}{\saildoclabelled{sailRISCVzsatp64Modezyofzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsatp64mode_of_bits11c1e0e3eda64d7361d8ec4950c9f1ea.tex}}}} + +\newcommand{\sailRISCVfnsatpSixFourModeOfBits}{\saildoclabelled{sailRISCVfnzsatp64Modezyofzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsatp64mode_of_bits11c1e0e3eda64d7361d8ec4950c9f1ea.tex}}}} + +\newcommand{\sailRISCVtypecsrRW}{\saildoclabelled{sailRISCVtypezcsrRW}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcsrrwa8d2be180025e67dbbe56d3c5c45b12e.tex}}}} + +\newcommand{\sailRISCVtypeuop}{\saildoclabelled{sailRISCVtypezuop}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezuopd0b3f6267a24e3937a9850ce9ebaa872.tex}}}} + +\newcommand{\sailRISCVvaluopOfNum}{\saildoclabelled{sailRISCVzuopzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzuop_of_num86c5f7f375d0126822beff686eb42370.tex}}}} + +\newcommand{\sailRISCVfnuopOfNum}{\saildoclabelled{sailRISCVfnzuopzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzuop_of_num86c5f7f375d0126822beff686eb42370.tex}}}} + +\newcommand{\sailRISCVvalnumOfUop}{\saildoclabelled{sailRISCVznumzyofzyuop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_uop5155bc57344db1e0852d69264b07f354.tex}}}} + +\newcommand{\sailRISCVfnnumOfUop}{\saildoclabelled{sailRISCVfnznumzyofzyuop}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_uop5155bc57344db1e0852d69264b07f354.tex}}}} + +\newcommand{\sailRISCVtypebop}{\saildoclabelled{sailRISCVtypezbop}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezbop5369d06602ae03217d614193dd3f84fa.tex}}}} + +\newcommand{\sailRISCVvalbopOfNum}{\saildoclabelled{sailRISCVzbopzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbop_of_num74cd9479863c5a21d66fa86ae45f1bd5.tex}}}} + +\newcommand{\sailRISCVfnbopOfNum}{\saildoclabelled{sailRISCVfnzbopzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzbop_of_num74cd9479863c5a21d66fa86ae45f1bd5.tex}}}} + +\newcommand{\sailRISCVvalnumOfBop}{\saildoclabelled{sailRISCVznumzyofzybop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_bop465de2d51df014a233592af62fc5056d.tex}}}} + +\newcommand{\sailRISCVfnnumOfBop}{\saildoclabelled{sailRISCVfnznumzyofzybop}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_bop465de2d51df014a233592af62fc5056d.tex}}}} + +\newcommand{\sailRISCVtypeiop}{\saildoclabelled{sailRISCVtypeziop}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typeziop4f047e83f4bb42a95f028529f28b2b82.tex}}}} + +\newcommand{\sailRISCVvaliopOfNum}{\saildoclabelled{sailRISCVziopzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valziop_of_numd466c8622bc5d10ff829fe51ba16e9a6.tex}}}} + +\newcommand{\sailRISCVfniopOfNum}{\saildoclabelled{sailRISCVfnziopzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnziop_of_numd466c8622bc5d10ff829fe51ba16e9a6.tex}}}} + +\newcommand{\sailRISCVvalnumOfIop}{\saildoclabelled{sailRISCVznumzyofzyiop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_iop7e0f948724eaec1edf1ab6539e332d14.tex}}}} + +\newcommand{\sailRISCVfnnumOfIop}{\saildoclabelled{sailRISCVfnznumzyofzyiop}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_iop7e0f948724eaec1edf1ab6539e332d14.tex}}}} + +\newcommand{\sailRISCVtypesop}{\saildoclabelled{sailRISCVtypezsop}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsop278747973081fc221bd6ffe68d2fa910.tex}}}} + +\newcommand{\sailRISCVvalsopOfNum}{\saildoclabelled{sailRISCVzsopzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsop_of_num788240d3b5d5ef8334c5920b24c291e9.tex}}}} + +\newcommand{\sailRISCVfnsopOfNum}{\saildoclabelled{sailRISCVfnzsopzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsop_of_num788240d3b5d5ef8334c5920b24c291e9.tex}}}} + +\newcommand{\sailRISCVvalnumOfSop}{\saildoclabelled{sailRISCVznumzyofzysop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_sopfa04a24d46338146566ae6e8a80132f0.tex}}}} + +\newcommand{\sailRISCVfnnumOfSop}{\saildoclabelled{sailRISCVfnznumzyofzysop}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_sopfa04a24d46338146566ae6e8a80132f0.tex}}}} + +\newcommand{\sailRISCVtyperop}{\saildoclabelled{sailRISCVtypezrop}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezrop291ca9b0f81265d59b554cd7976da946.tex}}}} + +\newcommand{\sailRISCVvalropOfNum}{\saildoclabelled{sailRISCVzropzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrop_of_numdb49159dd280dafb7370c6477b545c05.tex}}}} + +\newcommand{\sailRISCVfnropOfNum}{\saildoclabelled{sailRISCVfnzropzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrop_of_numdb49159dd280dafb7370c6477b545c05.tex}}}} + +\newcommand{\sailRISCVvalnumOfRop}{\saildoclabelled{sailRISCVznumzyofzyrop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_rop6b1530298b7a57e62b47f86bb5f1b15c.tex}}}} + +\newcommand{\sailRISCVfnnumOfRop}{\saildoclabelled{sailRISCVfnznumzyofzyrop}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_rop6b1530298b7a57e62b47f86bb5f1b15c.tex}}}} + +\newcommand{\sailRISCVtyperopw}{\saildoclabelled{sailRISCVtypezropw}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezropw43e7b9e2c8f71c945acf86b7ec6e0687.tex}}}} + +\newcommand{\sailRISCVvalropwOfNum}{\saildoclabelled{sailRISCVzropwzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzropw_of_numbc49d41e4663ce1e2313189dca74c7f1.tex}}}} + +\newcommand{\sailRISCVfnropwOfNum}{\saildoclabelled{sailRISCVfnzropwzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzropw_of_numbc49d41e4663ce1e2313189dca74c7f1.tex}}}} + +\newcommand{\sailRISCVvalnumOfRopw}{\saildoclabelled{sailRISCVznumzyofzyropw}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_ropw2d1d1b64d2060822876c1a3c1d164870.tex}}}} + +\newcommand{\sailRISCVfnnumOfRopw}{\saildoclabelled{sailRISCVfnznumzyofzyropw}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_ropw2d1d1b64d2060822876c1a3c1d164870.tex}}}} + +\newcommand{\sailRISCVtypesopw}{\saildoclabelled{sailRISCVtypezsopw}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsopw29bbaf9eb4401b2d853623bfd0698c6e.tex}}}} + +\newcommand{\sailRISCVvalsopwOfNum}{\saildoclabelled{sailRISCVzsopwzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsopw_of_num696c7b3c0b6fb9b9c9d699cd0a410ea3.tex}}}} + +\newcommand{\sailRISCVfnsopwOfNum}{\saildoclabelled{sailRISCVfnzsopwzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzsopw_of_num696c7b3c0b6fb9b9c9d699cd0a410ea3.tex}}}} + +\newcommand{\sailRISCVvalnumOfSopw}{\saildoclabelled{sailRISCVznumzyofzysopw}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_sopw352409ee6a8831f827129fc3d78cd4d6.tex}}}} + +\newcommand{\sailRISCVfnnumOfSopw}{\saildoclabelled{sailRISCVfnznumzyofzysopw}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_sopw352409ee6a8831f827129fc3d78cd4d6.tex}}}} + +\newcommand{\sailRISCVtypeamoop}{\saildoclabelled{sailRISCVtypezamoop}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezamoopd600bc1f48968cf6c909a7527f520a98.tex}}}} + +\newcommand{\sailRISCVvalamoopOfNum}{\saildoclabelled{sailRISCVzamoopzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzamoop_of_num66fc14378761bc8bd8137ac63cffe431.tex}}}} + +\newcommand{\sailRISCVfnamoopOfNum}{\saildoclabelled{sailRISCVfnzamoopzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzamoop_of_num66fc14378761bc8bd8137ac63cffe431.tex}}}} + +\newcommand{\sailRISCVvalnumOfAmoop}{\saildoclabelled{sailRISCVznumzyofzyamoop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_amoop3990788e22835bf2e0af928f223c3eba.tex}}}} + +\newcommand{\sailRISCVfnnumOfAmoop}{\saildoclabelled{sailRISCVfnznumzyofzyamoop}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_amoop3990788e22835bf2e0af928f223c3eba.tex}}}} + +\newcommand{\sailRISCVtypecsrop}{\saildoclabelled{sailRISCVtypezcsrop}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcsrop2c5a5cf59f588ba61c955dc544ab5638.tex}}}} + +\newcommand{\sailRISCVvalcsropOfNum}{\saildoclabelled{sailRISCVzcsropzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcsrop_of_numfc0e82db24db14fec87d0613c91892f2.tex}}}} + +\newcommand{\sailRISCVfncsropOfNum}{\saildoclabelled{sailRISCVfnzcsropzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcsrop_of_numfc0e82db24db14fec87d0613c91892f2.tex}}}} + +\newcommand{\sailRISCVvalnumOfCsrop}{\saildoclabelled{sailRISCVznumzyofzycsrop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_csropc21ef48aae10c4abc2e72f7386a31ce9.tex}}}} + +\newcommand{\sailRISCVfnnumOfCsrop}{\saildoclabelled{sailRISCVfnznumzyofzycsrop}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_csropc21ef48aae10c4abc2e72f7386a31ce9.tex}}}} + +\newcommand{\sailRISCVvalsep}{\saildoclabelled{sailRISCVzsep}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsep43dac566d26bd3f7fb9088b8d09ca246.tex}}}} + +\newcommand{\sailRISCVvalboolBits}{\saildoclabelled{sailRISCVzboolzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbool_bitsc0498d89cd314b64ec44bc657a0630ec.tex}}}} + +\newcommand{\sailRISCVvalboolNotBits}{\saildoclabelled{sailRISCVzboolzynotzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbool_not_bits8cc7dc8d8a4bcd7dc0a9851db7a322cc.tex}}}} + +\newcommand{\sailRISCVvalsizzeBits}{\saildoclabelled{sailRISCVzsizzezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsizze_bits40630770cee662892ab899654b7e2f0d.tex}}}} + +\newcommand{\sailRISCVvalsizzeMnemonic}{\saildoclabelled{sailRISCVzsizzezymnemonic}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsizze_mnemonic4114d3c8877e3689368588f52debea7b.tex}}}} + +\newcommand{\sailRISCVvalwordWidthBytes}{\saildoclabelled{sailRISCVzwordzywidthzybytes}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzword_width_bytes3499487c0f03a80d8659fa504a62261f.tex}}}} + +\newcommand{\sailRISCVfnwordWidthBytes}{\saildoclabelled{sailRISCVfnzwordzywidthzybytes}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzword_width_bytes3499487c0f03a80d8659fa504a62261f.tex}}}} + +\newcommand{\sailRISCVtyperegtype}{\saildoclabelled{sailRISCVtypezregtype}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezregtype0be936c0d9e150ad1beff99e08691cf8.tex}}}} + +\newcommand{\sailRISCVvalRegStr}{\saildoclabelled{sailRISCVzRegStr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzregstrf07d744c662238e6879fb1aee407788d.tex}}}} + +\newcommand{\sailRISCVfnRegStr}{\saildoclabelled{sailRISCVfnzRegStr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzregstrf07d744c662238e6879fb1aee407788d.tex}}}} + +\newcommand{\sailRISCVvalregvalFromReg}{\saildoclabelled{sailRISCVzregvalzyfromzyreg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzregval_from_rega072b7983f1f9ac4a9021e76a911b9c9.tex}}}} + +\newcommand{\sailRISCVfnregvalFromReg}{\saildoclabelled{sailRISCVfnzregvalzyfromzyreg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzregval_from_rega072b7983f1f9ac4a9021e76a911b9c9.tex}}}} + +\newcommand{\sailRISCVvalregvalIntoReg}{\saildoclabelled{sailRISCVzregvalzyintozyreg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzregval_into_reg03a5bdeabb3e6169090e6ed21f1a84cb.tex}}}} + +\newcommand{\sailRISCVfnregvalIntoReg}{\saildoclabelled{sailRISCVfnzregvalzyintozyreg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzregval_into_reg03a5bdeabb3e6169090e6ed21f1a84cb.tex}}}} + +\newcommand{\sailRISCVtypefregtype}{\saildoclabelled{sailRISCVtypezfregtype}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezfregtype005522b0120ed9774e1ab7767fd5f4aa.tex}}}} + +\newcommand{\sailRISCVvalFRegStr}{\saildoclabelled{sailRISCVzFRegStr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfregstr48009e974e6089e7ac15bb0f9271a481.tex}}}} + +\newcommand{\sailRISCVfnFRegStr}{\saildoclabelled{sailRISCVfnzFRegStr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfregstr48009e974e6089e7ac15bb0f9271a481.tex}}}} + +\newcommand{\sailRISCVvalfregvalFromFreg}{\saildoclabelled{sailRISCVzfregvalzyfromzyfreg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfregval_from_freg24f4c96a7be559c758c7de5e3dfe669b.tex}}}} + +\newcommand{\sailRISCVfnfregvalFromFreg}{\saildoclabelled{sailRISCVfnzfregvalzyfromzyfreg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfregval_from_freg24f4c96a7be559c758c7de5e3dfe669b.tex}}}} + +\newcommand{\sailRISCVvalfregvalIntoFreg}{\saildoclabelled{sailRISCVzfregvalzyintozyfreg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfregval_into_fregc2bccb9e14fa0e7ca1dec382b998fa46.tex}}}} + +\newcommand{\sailRISCVfnfregvalIntoFreg}{\saildoclabelled{sailRISCVfnzfregvalzyintozyfreg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfregval_into_fregc2bccb9e14fa0e7ca1dec382b998fa46.tex}}}} + +\newcommand{\sailRISCVtyperoundingMode}{\saildoclabelled{sailRISCVtypezroundingzymode}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezrounding_modea8ccd05712e3eb82022c72b8440f235b.tex}}}} + +\newcommand{\sailRISCVvalroundingModeOfNum}{\saildoclabelled{sailRISCVzroundingzymodezyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrounding_mode_of_num6135245be40748c506fabd0190282238.tex}}}} + +\newcommand{\sailRISCVfnroundingModeOfNum}{\saildoclabelled{sailRISCVfnzroundingzymodezyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrounding_mode_of_num6135245be40748c506fabd0190282238.tex}}}} + +\newcommand{\sailRISCVvalnumOfRoundingMode}{\saildoclabelled{sailRISCVznumzyofzyroundingzymode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_rounding_mode41a60e82308e6507de434c7dc6e17db8.tex}}}} + +\newcommand{\sailRISCVfnnumOfRoundingMode}{\saildoclabelled{sailRISCVfnznumzyofzyroundingzymode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_rounding_mode41a60e82308e6507de434c7dc6e17db8.tex}}}} + +\newcommand{\sailRISCVtypefMaddOpS}{\saildoclabelled{sailRISCVtypezfzymaddzyopzyS}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezf_madd_op_sb37be1865406477b64362e39a00e2afe.tex}}}} + +\newcommand{\sailRISCVvalfMaddOpSOfNum}{\saildoclabelled{sailRISCVzfzymaddzyopzySzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_madd_op_s_of_num9bfe1beb29f1f97cf6b7643bd9febe9b.tex}}}} + +\newcommand{\sailRISCVfnfMaddOpSOfNum}{\saildoclabelled{sailRISCVfnzfzymaddzyopzySzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_madd_op_s_of_num9bfe1beb29f1f97cf6b7643bd9febe9b.tex}}}} + +\newcommand{\sailRISCVvalnumOfFMaddOpS}{\saildoclabelled{sailRISCVznumzyofzyfzymaddzyopzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_f_madd_op_s775906828ed91e55055481dedc5d9da4.tex}}}} + +\newcommand{\sailRISCVfnnumOfFMaddOpS}{\saildoclabelled{sailRISCVfnznumzyofzyfzymaddzyopzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_f_madd_op_s775906828ed91e55055481dedc5d9da4.tex}}}} + +\newcommand{\sailRISCVtypefBinRmOpS}{\saildoclabelled{sailRISCVtypezfzybinzyrmzyopzyS}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezf_bin_rm_op_s0fd11305b9d3dfc93e566ad91732c086.tex}}}} + +\newcommand{\sailRISCVvalfBinRmOpSOfNum}{\saildoclabelled{sailRISCVzfzybinzyrmzyopzySzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_bin_rm_op_s_of_num425ba7f76e47ae16326c0417fe340273.tex}}}} + +\newcommand{\sailRISCVfnfBinRmOpSOfNum}{\saildoclabelled{sailRISCVfnzfzybinzyrmzyopzySzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_bin_rm_op_s_of_num425ba7f76e47ae16326c0417fe340273.tex}}}} + +\newcommand{\sailRISCVvalnumOfFBinRmOpS}{\saildoclabelled{sailRISCVznumzyofzyfzybinzyrmzyopzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_f_bin_rm_op_s893f36c63d593d34b1cf67930090a6d2.tex}}}} + +\newcommand{\sailRISCVfnnumOfFBinRmOpS}{\saildoclabelled{sailRISCVfnznumzyofzyfzybinzyrmzyopzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_f_bin_rm_op_s893f36c63d593d34b1cf67930090a6d2.tex}}}} + +\newcommand{\sailRISCVtypefUnRmOpS}{\saildoclabelled{sailRISCVtypezfzyunzyrmzyopzyS}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezf_un_rm_op_sd0ea7b4f9a759adc91555b3055b8016a.tex}}}} + +\newcommand{\sailRISCVvalfUnRmOpSOfNum}{\saildoclabelled{sailRISCVzfzyunzyrmzyopzySzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_un_rm_op_s_of_numcf978158d6a6f45fe1893c4a9c122140.tex}}}} + +\newcommand{\sailRISCVfnfUnRmOpSOfNum}{\saildoclabelled{sailRISCVfnzfzyunzyrmzyopzySzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_un_rm_op_s_of_numcf978158d6a6f45fe1893c4a9c122140.tex}}}} + +\newcommand{\sailRISCVvalnumOfFUnRmOpS}{\saildoclabelled{sailRISCVznumzyofzyfzyunzyrmzyopzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_f_un_rm_op_se915d9a4f61459b98b43ab8bc6055666.tex}}}} + +\newcommand{\sailRISCVfnnumOfFUnRmOpS}{\saildoclabelled{sailRISCVfnznumzyofzyfzyunzyrmzyopzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_f_un_rm_op_se915d9a4f61459b98b43ab8bc6055666.tex}}}} + +\newcommand{\sailRISCVtypefUnOpS}{\saildoclabelled{sailRISCVtypezfzyunzyopzyS}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezf_un_op_s286e536373f63a1fa600b8619060bb26.tex}}}} + +\newcommand{\sailRISCVvalfUnOpSOfNum}{\saildoclabelled{sailRISCVzfzyunzyopzySzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_un_op_s_of_num428b8623c493e45bc273b3e1a0c895e0.tex}}}} + +\newcommand{\sailRISCVfnfUnOpSOfNum}{\saildoclabelled{sailRISCVfnzfzyunzyopzySzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_un_op_s_of_num428b8623c493e45bc273b3e1a0c895e0.tex}}}} + +\newcommand{\sailRISCVvalnumOfFUnOpS}{\saildoclabelled{sailRISCVznumzyofzyfzyunzyopzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_f_un_op_se59a01770756c5c1ccc368187228ef32.tex}}}} + +\newcommand{\sailRISCVfnnumOfFUnOpS}{\saildoclabelled{sailRISCVfnznumzyofzyfzyunzyopzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_f_un_op_se59a01770756c5c1ccc368187228ef32.tex}}}} + +\newcommand{\sailRISCVtypefBinOpS}{\saildoclabelled{sailRISCVtypezfzybinzyopzyS}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezf_bin_op_s70d2d316fdfc1f5fd4d53696fd688829.tex}}}} + +\newcommand{\sailRISCVvalfBinOpSOfNum}{\saildoclabelled{sailRISCVzfzybinzyopzySzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_bin_op_s_of_num66d590442d54517898ad2679db0d80bc.tex}}}} + +\newcommand{\sailRISCVfnfBinOpSOfNum}{\saildoclabelled{sailRISCVfnzfzybinzyopzySzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_bin_op_s_of_num66d590442d54517898ad2679db0d80bc.tex}}}} + +\newcommand{\sailRISCVvalnumOfFBinOpS}{\saildoclabelled{sailRISCVznumzyofzyfzybinzyopzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_f_bin_op_s67646ca4512abf0a4d4b44cd4f5b13ca.tex}}}} + +\newcommand{\sailRISCVfnnumOfFBinOpS}{\saildoclabelled{sailRISCVfnznumzyofzyfzybinzyopzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_f_bin_op_s67646ca4512abf0a4d4b44cd4f5b13ca.tex}}}} + +\newcommand{\sailRISCVtypefMaddOpD}{\saildoclabelled{sailRISCVtypezfzymaddzyopzyD}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezf_madd_op_d3909a9cf5d4cc7f2d6f5dc2a8683ef42.tex}}}} + +\newcommand{\sailRISCVvalfMaddOpDOfNum}{\saildoclabelled{sailRISCVzfzymaddzyopzyDzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_madd_op_d_of_num115462b951eadf3acf4b0a2bb11e801b.tex}}}} + +\newcommand{\sailRISCVfnfMaddOpDOfNum}{\saildoclabelled{sailRISCVfnzfzymaddzyopzyDzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_madd_op_d_of_num115462b951eadf3acf4b0a2bb11e801b.tex}}}} + +\newcommand{\sailRISCVvalnumOfFMaddOpD}{\saildoclabelled{sailRISCVznumzyofzyfzymaddzyopzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_f_madd_op_d37717f7c44daba9b30789132320443ff.tex}}}} + +\newcommand{\sailRISCVfnnumOfFMaddOpD}{\saildoclabelled{sailRISCVfnznumzyofzyfzymaddzyopzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_f_madd_op_d37717f7c44daba9b30789132320443ff.tex}}}} + +\newcommand{\sailRISCVtypefBinRmOpD}{\saildoclabelled{sailRISCVtypezfzybinzyrmzyopzyD}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezf_bin_rm_op_d17db6dd54145474f7e451ccb8f074943.tex}}}} + +\newcommand{\sailRISCVvalfBinRmOpDOfNum}{\saildoclabelled{sailRISCVzfzybinzyrmzyopzyDzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_bin_rm_op_d_of_num4f1c6a877a7fdb6ce5cba8edac489378.tex}}}} + +\newcommand{\sailRISCVfnfBinRmOpDOfNum}{\saildoclabelled{sailRISCVfnzfzybinzyrmzyopzyDzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_bin_rm_op_d_of_num4f1c6a877a7fdb6ce5cba8edac489378.tex}}}} + +\newcommand{\sailRISCVvalnumOfFBinRmOpD}{\saildoclabelled{sailRISCVznumzyofzyfzybinzyrmzyopzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_f_bin_rm_op_dc153c7dd1e01a91df37cddfd46dfd9da.tex}}}} + +\newcommand{\sailRISCVfnnumOfFBinRmOpD}{\saildoclabelled{sailRISCVfnznumzyofzyfzybinzyrmzyopzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_f_bin_rm_op_dc153c7dd1e01a91df37cddfd46dfd9da.tex}}}} + +\newcommand{\sailRISCVtypefUnRmOpD}{\saildoclabelled{sailRISCVtypezfzyunzyrmzyopzyD}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezf_un_rm_op_de2fd51e1e803f0967e3388fb50d06082.tex}}}} + +\newcommand{\sailRISCVvalfUnRmOpDOfNum}{\saildoclabelled{sailRISCVzfzyunzyrmzyopzyDzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_un_rm_op_d_of_num3c7528aaf2a777986f767617d6c66717.tex}}}} + +\newcommand{\sailRISCVfnfUnRmOpDOfNum}{\saildoclabelled{sailRISCVfnzfzyunzyrmzyopzyDzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_un_rm_op_d_of_num3c7528aaf2a777986f767617d6c66717.tex}}}} + +\newcommand{\sailRISCVvalnumOfFUnRmOpD}{\saildoclabelled{sailRISCVznumzyofzyfzyunzyrmzyopzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_f_un_rm_op_d6e3378f59faf04b5d017d7c996a625e0.tex}}}} + +\newcommand{\sailRISCVfnnumOfFUnRmOpD}{\saildoclabelled{sailRISCVfnznumzyofzyfzyunzyrmzyopzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_f_un_rm_op_d6e3378f59faf04b5d017d7c996a625e0.tex}}}} + +\newcommand{\sailRISCVtypefBinOpD}{\saildoclabelled{sailRISCVtypezfzybinzyopzyD}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezf_bin_op_d997af8255aaaca7c24b987d847247564.tex}}}} + +\newcommand{\sailRISCVvalfBinOpDOfNum}{\saildoclabelled{sailRISCVzfzybinzyopzyDzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_bin_op_d_of_num97322de52afcea7a7f630a9ec29b7900.tex}}}} + +\newcommand{\sailRISCVfnfBinOpDOfNum}{\saildoclabelled{sailRISCVfnzfzybinzyopzyDzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_bin_op_d_of_num97322de52afcea7a7f630a9ec29b7900.tex}}}} + +\newcommand{\sailRISCVvalnumOfFBinOpD}{\saildoclabelled{sailRISCVznumzyofzyfzybinzyopzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_f_bin_op_dd209f84b003673fbf65e2d0267de89cd.tex}}}} + +\newcommand{\sailRISCVfnnumOfFBinOpD}{\saildoclabelled{sailRISCVfnznumzyofzyfzybinzyopzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_f_bin_op_dd209f84b003673fbf65e2d0267de89cd.tex}}}} + +\newcommand{\sailRISCVtypefUnOpD}{\saildoclabelled{sailRISCVtypezfzyunzyopzyD}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezf_un_op_d60d5205abfb9c0cba7b1e1dbdf6ad69e.tex}}}} + +\newcommand{\sailRISCVvalfUnOpDOfNum}{\saildoclabelled{sailRISCVzfzyunzyopzyDzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_un_op_d_of_num20c93bb1c359c6ff0f65b3c91dbe8c85.tex}}}} + +\newcommand{\sailRISCVfnfUnOpDOfNum}{\saildoclabelled{sailRISCVfnzfzyunzyopzyDzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_un_op_d_of_num20c93bb1c359c6ff0f65b3c91dbe8c85.tex}}}} + +\newcommand{\sailRISCVvalnumOfFUnOpD}{\saildoclabelled{sailRISCVznumzyofzyfzyunzyopzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_f_un_op_d6d388f339a377c4a985a55a3c728bb8f.tex}}}} + +\newcommand{\sailRISCVfnnumOfFUnOpD}{\saildoclabelled{sailRISCVfnznumzyofzyfzyunzyopzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_f_un_op_d6d388f339a377c4a985a55a3c728bb8f.tex}}}} + +\newcommand{\sailRISCVvalcsrNameMap}{\saildoclabelled{sailRISCVzcsrzynamezymap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcsr_name_map043e1d5f928269d79e6253854765ef21.tex}}}} + +\newcommand{\sailRISCVvalcsrName}{\saildoclabelled{sailRISCVzcsrzyname}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcsr_name355619c0d72f0a56dfaf2d45f4b72967.tex}}}} + +\newcommand{\sailRISCVoverloadCCCtoStr}{\saildoclabelled{sailRISCVoverloadCCCztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} + +\newcommand{\sailRISCVvalextIsCSRDefined}{\saildoclabelled{sailRISCVzextzyiszyCSRzydefined}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVvalextReadCSR}{\saildoclabelled{sailRISCVzextzyreadzyCSR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVvalextWriteCSR}{\saildoclabelled{sailRISCVzextzywritezyCSR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVvalscrNameMap}{\saildoclabelled{sailRISCVzscrzynamezymap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzscr_name_map4b235a67e525de15ab35ff501d369c01.tex}}}} + +\newcommand{\sailRISCVvalscrName}{\saildoclabelled{sailRISCVzscrzyname}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzscr_name18d33d5c24513d7598c403423ce2f8e6.tex}}}} + +\newcommand{\sailRISCVoverloadDDDtoStr}{\saildoclabelled{sailRISCVoverloadDDDztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} + +\newcommand{\sailRISCVtypeextAccessType}{\saildoclabelled{sailRISCVtypezextzyaccesszytype}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_access_type8c60f923ce211fcdc0c77548b866673e.tex}}}} + +\newcommand{\sailRISCVvalextAccessTypeOfNum}{\saildoclabelled{sailRISCVzextzyaccesszytypezyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_access_type_of_num6a15c4e70d2e9820f649a1cc6760e30a.tex}}}} + +\newcommand{\sailRISCVfnextAccessTypeOfNum}{\saildoclabelled{sailRISCVfnzextzyaccesszytypezyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_access_type_of_num6a15c4e70d2e9820f649a1cc6760e30a.tex}}}} + +\newcommand{\sailRISCVvalnumOfExtAccessType}{\saildoclabelled{sailRISCVznumzyofzyextzyaccesszytype}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_ext_access_typea973217ed477a3d18820058dd3b21729.tex}}}} + +\newcommand{\sailRISCVfnnumOfExtAccessType}{\saildoclabelled{sailRISCVfnznumzyofzyextzyaccesszytype}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_ext_access_typea973217ed477a3d18820058dd3b21729.tex}}}} + +\newcommand{\sailRISCVvalaccessTypeToStr}{\saildoclabelled{sailRISCVzaccessTypezytozystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzaccesstype_to_str58f7a46d6b3e326411426e3cf0fe52cf.tex}}}} + +\newcommand{\sailRISCVfnaccessTypeToStr}{\saildoclabelled{sailRISCVfnzaccessTypezytozystr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzaccesstype_to_str58f7a46d6b3e326411426e3cf0fe52cf.tex}}}} + +\newcommand{\sailRISCVoverloadEEEtoStr}{\saildoclabelled{sailRISCVoverloadEEEztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} + +\newcommand{\sailRISCVvalrX}{\saildoclabelled{sailRISCVzrX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrxa8aad9466d0653707390b940aa9282e7.tex}}}} + +\newcommand{\sailRISCVfnrX}{\saildoclabelled{sailRISCVfnzrX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrxa8aad9466d0653707390b940aa9282e7.tex}}}} + +\newcommand{\sailRISCVvalrvfiWX}{\saildoclabelled{sailRISCVzrvfizywX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrvfi_wxed842ecfeb56ef18626194f2f22935f3.tex}}}} + +\newcommand{\sailRISCVfnrvfiWX}{\saildoclabelled{sailRISCVfnzrvfizywX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrvfi_wxed842ecfeb56ef18626194f2f22935f3.tex}}}} + +\newcommand{\sailRISCVvalwX}{\saildoclabelled{sailRISCVzwX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwx0042b1ee0bdb45d47dcb45d5a9461882.tex}}}} + +\newcommand{\sailRISCVfnwX}{\saildoclabelled{sailRISCVfnzwX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwx0042b1ee0bdb45d47dcb45d5a9461882.tex}}}} + +\newcommand{\sailRISCVvalrXBits}{\saildoclabelled{sailRISCVzrXzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrx_bitsba4d35e6c426ac476fdbf36efdd5d0da.tex}}}} + +\newcommand{\sailRISCVfnrXBits}{\saildoclabelled{sailRISCVfnzrXzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrx_bitsba4d35e6c426ac476fdbf36efdd5d0da.tex}}}} + +\newcommand{\sailRISCVvalwXBits}{\saildoclabelled{sailRISCVzwXzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwx_bitseb6ef5be72b31b8cb0f1595602665261.tex}}}} + +\newcommand{\sailRISCVfnwXBits}{\saildoclabelled{sailRISCVfnzwXzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwx_bitseb6ef5be72b31b8cb0f1595602665261.tex}}}} + +\newcommand{\sailRISCVoverloadFFFX}{\saildoclabelled{sailRISCVoverloadFFFzX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFzx1f3c57dd04ac52fd92f3346ca51f00ec.tex}}}} + +\newcommand{\sailRISCVvalregNameAbi}{\saildoclabelled{sailRISCVzregzynamezyabi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzreg_name_abi8c36e923dc671675cb54fb0175878a3f.tex}}}} + +\newcommand{\sailRISCVfnregNameAbi}{\saildoclabelled{sailRISCVfnzregzynamezyabi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzreg_name_abi8c36e923dc671675cb54fb0175878a3f.tex}}}} + +\newcommand{\sailRISCVoverloadGGGtoStr}{\saildoclabelled{sailRISCVoverloadGGGztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} + +\newcommand{\sailRISCVvalregName}{\saildoclabelled{sailRISCVzregzyname}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzreg_namea3a934e14215c11bd841e5d2fb4f53e0.tex}}}} + +\newcommand{\sailRISCVvalcregName}{\saildoclabelled{sailRISCVzcregzyname}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcreg_name8aa7dd2adef25f1d7c38341bff05c8a9.tex}}}} + +\newcommand{\sailRISCVvalinitBaseRegs}{\saildoclabelled{sailRISCVzinitzybasezyregs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinit_base_regs92fa12c31a7794db853235a9147b1c7b.tex}}}} + +\newcommand{\sailRISCVfninitBaseRegs}{\saildoclabelled{sailRISCVfnzinitzybasezyregs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinit_base_regs92fa12c31a7794db853235a9147b1c7b.tex}}}} + +\newcommand{\sailRISCVtypeMisa}{\saildoclabelled{sailRISCVtypezMisa}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezmisaa32c2c216e0702e03f7fa6ac32ade17d.tex}}}} + +\newcommand{\sailRISCVvalMkMisa}{\saildoclabelled{sailRISCVzMkzyMisa}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_misa9e5f00faa0413197c9cc5f0f7791d5b7.tex}}}} + +\newcommand{\sailRISCVfnMkMisa}{\saildoclabelled{sailRISCVfnzMkzyMisa}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_misa9e5f00faa0413197c9cc5f0f7791d5b7.tex}}}} + +\newcommand{\sailRISCVvalGetMisaBits}{\saildoclabelled{sailRISCVzzygetzyMisazybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_bits227fd8e446573e270b2f6ea70e25b072.tex}}}} + +\newcommand{\sailRISCVfnGetMisaBits}{\saildoclabelled{sailRISCVfnzzygetzyMisazybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_bits227fd8e446573e270b2f6ea70e25b072.tex}}}} + +\newcommand{\sailRISCVvalSetMisaBits}{\saildoclabelled{sailRISCVzzysetzyMisazybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_bits8a8c7777988f3569033d87950ad2055d.tex}}}} + +\newcommand{\sailRISCVfnSetMisaBits}{\saildoclabelled{sailRISCVfnzzysetzyMisazybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_bits8a8c7777988f3569033d87950ad2055d.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaBits}{\saildoclabelled{sailRISCVzzyupdatezyMisazybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_bitsf571d9035c480faf7559a6b750d4b5d1.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaBits}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_bitsf571d9035c480faf7559a6b750d4b5d1.tex}}}} + +\newcommand{\sailRISCVoverloadHHHupdateBits}{\saildoclabelled{sailRISCVoverloadHHHzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadIIIModBits}{\saildoclabelled{sailRISCVoverloadIIIzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetMisaMXL}{\saildoclabelled{sailRISCVzzygetzyMisazyMXL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_mxl28cf17010b1a2667fba28101a95eb2ae.tex}}}} + +\newcommand{\sailRISCVfnGetMisaMXL}{\saildoclabelled{sailRISCVfnzzygetzyMisazyMXL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_mxl28cf17010b1a2667fba28101a95eb2ae.tex}}}} + +\newcommand{\sailRISCVvalSetMisaMXL}{\saildoclabelled{sailRISCVzzysetzyMisazyMXL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_mxlfaf2da4a42816291e01fbd0451c6cfc5.tex}}}} + +\newcommand{\sailRISCVfnSetMisaMXL}{\saildoclabelled{sailRISCVfnzzysetzyMisazyMXL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_mxlfaf2da4a42816291e01fbd0451c6cfc5.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaMXL}{\saildoclabelled{sailRISCVzzyupdatezyMisazyMXL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_mxla1af4e187cbc1f82dd5ef946cabac371.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaMXL}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyMXL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_mxla1af4e187cbc1f82dd5ef946cabac371.tex}}}} + +\newcommand{\sailRISCVoverloadJJJupdateMXL}{\saildoclabelled{sailRISCVoverloadJJJzupdatezyMXL}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJzupdate_mxlb5a3c988cbea039f1e178bcd72815821.tex}}}} + +\newcommand{\sailRISCVoverloadKKKModMXL}{\saildoclabelled{sailRISCVoverloadKKKzzymodzyMXL}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKz_mod_mxlaa066cfb7ec1d12283cbb376dd9b1101.tex}}}} + +\newcommand{\sailRISCVvalGetMisaZ}{\saildoclabelled{sailRISCVzzygetzyMisazyZ}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_z0279590775f9ece96e2d9030ddcdfa1d.tex}}}} + +\newcommand{\sailRISCVfnGetMisaZ}{\saildoclabelled{sailRISCVfnzzygetzyMisazyZ}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_z0279590775f9ece96e2d9030ddcdfa1d.tex}}}} + +\newcommand{\sailRISCVvalSetMisaZ}{\saildoclabelled{sailRISCVzzysetzyMisazyZ}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_z0aa6e14567359f53c59523971c522eda.tex}}}} + +\newcommand{\sailRISCVfnSetMisaZ}{\saildoclabelled{sailRISCVfnzzysetzyMisazyZ}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_z0aa6e14567359f53c59523971c522eda.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaZ}{\saildoclabelled{sailRISCVzzyupdatezyMisazyZ}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_z801b78039b962c298e7fc5710e8ae3c4.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaZ}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyZ}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_z801b78039b962c298e7fc5710e8ae3c4.tex}}}} + +\newcommand{\sailRISCVoverloadLLLupdateZ}{\saildoclabelled{sailRISCVoverloadLLLzupdatezyZ}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLzupdate_z526c1a025fbdbfc03ac9334c924737a9.tex}}}} + +\newcommand{\sailRISCVoverloadMMMModZ}{\saildoclabelled{sailRISCVoverloadMMMzzymodzyZ}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMz_mod_za28d358f8525c17052bc8ea6cdba9052.tex}}}} + +\newcommand{\sailRISCVvalGetMisaY}{\saildoclabelled{sailRISCVzzygetzyMisazyY}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_ycb7d2d02e2edfcdcd44bdf6e4764863d.tex}}}} + +\newcommand{\sailRISCVfnGetMisaY}{\saildoclabelled{sailRISCVfnzzygetzyMisazyY}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_ycb7d2d02e2edfcdcd44bdf6e4764863d.tex}}}} + +\newcommand{\sailRISCVvalSetMisaY}{\saildoclabelled{sailRISCVzzysetzyMisazyY}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_y0780ac18d01eba2171fd0f4807b7f5eb.tex}}}} + +\newcommand{\sailRISCVfnSetMisaY}{\saildoclabelled{sailRISCVfnzzysetzyMisazyY}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_y0780ac18d01eba2171fd0f4807b7f5eb.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaY}{\saildoclabelled{sailRISCVzzyupdatezyMisazyY}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_y44689f65180da16f003ee1c86f6b157e.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaY}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyY}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_y44689f65180da16f003ee1c86f6b157e.tex}}}} + +\newcommand{\sailRISCVoverloadNNNupdateY}{\saildoclabelled{sailRISCVoverloadNNNzupdatezyY}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNzupdate_y18932cf4e3dad22b55782b0d44c2a5ed.tex}}}} + +\newcommand{\sailRISCVoverloadOOOModY}{\saildoclabelled{sailRISCVoverloadOOOzzymodzyY}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOz_mod_y4993b5018b9fa96b0a5a3dff5d778b09.tex}}}} + +\newcommand{\sailRISCVvalGetMisaX}{\saildoclabelled{sailRISCVzzygetzyMisazyX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_xd43796eb311a89255d0382867f07ad38.tex}}}} + +\newcommand{\sailRISCVfnGetMisaX}{\saildoclabelled{sailRISCVfnzzygetzyMisazyX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_xd43796eb311a89255d0382867f07ad38.tex}}}} + +\newcommand{\sailRISCVvalSetMisaX}{\saildoclabelled{sailRISCVzzysetzyMisazyX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_x73ca1bfd41ee29a68574f834d43acd6b.tex}}}} + +\newcommand{\sailRISCVfnSetMisaX}{\saildoclabelled{sailRISCVfnzzysetzyMisazyX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_x73ca1bfd41ee29a68574f834d43acd6b.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaX}{\saildoclabelled{sailRISCVzzyupdatezyMisazyX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_x51e71056e58398948e16168b5c3c2df9.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaX}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_x51e71056e58398948e16168b5c3c2df9.tex}}}} + +\newcommand{\sailRISCVoverloadPPPupdateX}{\saildoclabelled{sailRISCVoverloadPPPzupdatezyX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPzupdate_x647abdeca7ac108f059148e19df0452e.tex}}}} + +\newcommand{\sailRISCVoverloadQQQModX}{\saildoclabelled{sailRISCVoverloadQQQzzymodzyX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQz_mod_xc906d7554de3b79cd0cc78501a562587.tex}}}} + +\newcommand{\sailRISCVvalGetMisaW}{\saildoclabelled{sailRISCVzzygetzyMisazyW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_w4b9d3d940363386a3b964f5d156642f8.tex}}}} + +\newcommand{\sailRISCVfnGetMisaW}{\saildoclabelled{sailRISCVfnzzygetzyMisazyW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_w4b9d3d940363386a3b964f5d156642f8.tex}}}} + +\newcommand{\sailRISCVvalSetMisaW}{\saildoclabelled{sailRISCVzzysetzyMisazyW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_wcf078697ae48ea6fcaebfe7fc01e054a.tex}}}} + +\newcommand{\sailRISCVfnSetMisaW}{\saildoclabelled{sailRISCVfnzzysetzyMisazyW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_wcf078697ae48ea6fcaebfe7fc01e054a.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaW}{\saildoclabelled{sailRISCVzzyupdatezyMisazyW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_wd53860d44fba8bd03071c9b2edd62e86.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaW}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_wd53860d44fba8bd03071c9b2edd62e86.tex}}}} + +\newcommand{\sailRISCVoverloadRRRupdateW}{\saildoclabelled{sailRISCVoverloadRRRzupdatezyW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRzupdate_w3209efc3cdd41bbc0810494fad257f06.tex}}}} + +\newcommand{\sailRISCVoverloadSSSModW}{\saildoclabelled{sailRISCVoverloadSSSzzymodzyW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSz_mod_w196183ee717bdd84cd7d5e4b2af0b219.tex}}}} + +\newcommand{\sailRISCVvalGetMisaV}{\saildoclabelled{sailRISCVzzygetzyMisazyV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_v3c3bbe0f72733630524d92db60c14a02.tex}}}} + +\newcommand{\sailRISCVfnGetMisaV}{\saildoclabelled{sailRISCVfnzzygetzyMisazyV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_v3c3bbe0f72733630524d92db60c14a02.tex}}}} + +\newcommand{\sailRISCVvalSetMisaV}{\saildoclabelled{sailRISCVzzysetzyMisazyV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_vd4a716e627db58a7aa372269cb454a1e.tex}}}} + +\newcommand{\sailRISCVfnSetMisaV}{\saildoclabelled{sailRISCVfnzzysetzyMisazyV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_vd4a716e627db58a7aa372269cb454a1e.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaV}{\saildoclabelled{sailRISCVzzyupdatezyMisazyV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_v1a8b5a29274e9567bae2f9671be4372a.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaV}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_v1a8b5a29274e9567bae2f9671be4372a.tex}}}} + +\newcommand{\sailRISCVoverloadTTTupdateV}{\saildoclabelled{sailRISCVoverloadTTTzupdatezyV}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTzupdate_v550d76e01b2aee2bcdcdd8fcb788e6ae.tex}}}} + +\newcommand{\sailRISCVoverloadUUUModV}{\saildoclabelled{sailRISCVoverloadUUUzzymodzyV}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUz_mod_v136fe7ecc31e11f2521faa02b71b57fa.tex}}}} + +\newcommand{\sailRISCVvalGetMisaU}{\saildoclabelled{sailRISCVzzygetzyMisazyU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_u2220c5041e723fd883e5ca3aad46843a.tex}}}} + +\newcommand{\sailRISCVfnGetMisaU}{\saildoclabelled{sailRISCVfnzzygetzyMisazyU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_u2220c5041e723fd883e5ca3aad46843a.tex}}}} + +\newcommand{\sailRISCVvalSetMisaU}{\saildoclabelled{sailRISCVzzysetzyMisazyU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_ub0a56841c43a9fb3c49a6bee644b7362.tex}}}} + +\newcommand{\sailRISCVfnSetMisaU}{\saildoclabelled{sailRISCVfnzzysetzyMisazyU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_ub0a56841c43a9fb3c49a6bee644b7362.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaU}{\saildoclabelled{sailRISCVzzyupdatezyMisazyU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_uac3943ed1944a21d61ef4550883e07f7.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaU}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_uac3943ed1944a21d61ef4550883e07f7.tex}}}} + +\newcommand{\sailRISCVoverloadVVVupdateU}{\saildoclabelled{sailRISCVoverloadVVVzupdatezyU}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVzupdate_uf25457b59a73b45bf964c7ab354d043c.tex}}}} + +\newcommand{\sailRISCVoverloadWWWModU}{\saildoclabelled{sailRISCVoverloadWWWzzymodzyU}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWz_mod_u960ee5decf6c18ea57af0e0387ef7d9c.tex}}}} + +\newcommand{\sailRISCVvalGetMisaT}{\saildoclabelled{sailRISCVzzygetzyMisazyT}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_t964cf69481b883e83863eb9ac05b8d52.tex}}}} + +\newcommand{\sailRISCVfnGetMisaT}{\saildoclabelled{sailRISCVfnzzygetzyMisazyT}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_t964cf69481b883e83863eb9ac05b8d52.tex}}}} + +\newcommand{\sailRISCVvalSetMisaT}{\saildoclabelled{sailRISCVzzysetzyMisazyT}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_tc2c88db403b799714c1a38812acd037c.tex}}}} + +\newcommand{\sailRISCVfnSetMisaT}{\saildoclabelled{sailRISCVfnzzysetzyMisazyT}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_tc2c88db403b799714c1a38812acd037c.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaT}{\saildoclabelled{sailRISCVzzyupdatezyMisazyT}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_tab0b967322f8b3d8c5d8c510963c8722.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaT}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyT}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_tab0b967322f8b3d8c5d8c510963c8722.tex}}}} + +\newcommand{\sailRISCVoverloadXXXupdateT}{\saildoclabelled{sailRISCVoverloadXXXzupdatezyT}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXzupdate_t4387a59a7ca6dbd358923def3d05d452.tex}}}} + +\newcommand{\sailRISCVoverloadYYYModT}{\saildoclabelled{sailRISCVoverloadYYYzzymodzyT}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYz_mod_t20863ac4eec1cefcdefe7f2e08aeb65b.tex}}}} + +\newcommand{\sailRISCVvalGetMisaS}{\saildoclabelled{sailRISCVzzygetzyMisazyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_s8d44106b93832cd46e00cba3d0fd7cc8.tex}}}} + +\newcommand{\sailRISCVfnGetMisaS}{\saildoclabelled{sailRISCVfnzzygetzyMisazyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_s8d44106b93832cd46e00cba3d0fd7cc8.tex}}}} + +\newcommand{\sailRISCVvalSetMisaS}{\saildoclabelled{sailRISCVzzysetzyMisazyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_s4c44d8942646231e0c7666a1590a0a92.tex}}}} + +\newcommand{\sailRISCVfnSetMisaS}{\saildoclabelled{sailRISCVfnzzysetzyMisazyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_s4c44d8942646231e0c7666a1590a0a92.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaS}{\saildoclabelled{sailRISCVzzyupdatezyMisazyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_sa29e6cb2dba70d986fb8ff30487dfbad.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaS}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_sa29e6cb2dba70d986fb8ff30487dfbad.tex}}}} + +\newcommand{\sailRISCVoverloadZZZupdateS}{\saildoclabelled{sailRISCVoverloadZZZzupdatezyS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZzupdate_sa0c87839ffa29da7fb0fae8f4724ad23.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAModS}{\saildoclabelled{sailRISCVoverloadAAAAzzymodzyS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAz_mod_sd4c32983c0a4bd556ddaf553d2e450b6.tex}}}} + +\newcommand{\sailRISCVvalGetMisaR}{\saildoclabelled{sailRISCVzzygetzyMisazyR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_rd0abea1daab407b029000fb4e1d3af0d.tex}}}} + +\newcommand{\sailRISCVfnGetMisaR}{\saildoclabelled{sailRISCVfnzzygetzyMisazyR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_rd0abea1daab407b029000fb4e1d3af0d.tex}}}} + +\newcommand{\sailRISCVvalSetMisaR}{\saildoclabelled{sailRISCVzzysetzyMisazyR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_r2e9e070264ac8e4df4365cbcd9bfec35.tex}}}} + +\newcommand{\sailRISCVfnSetMisaR}{\saildoclabelled{sailRISCVfnzzysetzyMisazyR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_r2e9e070264ac8e4df4365cbcd9bfec35.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaR}{\saildoclabelled{sailRISCVzzyupdatezyMisazyR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_r1f6eba10007c144d1b33e8eff2959c17.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaR}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_r1f6eba10007c144d1b33e8eff2959c17.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBupdateR}{\saildoclabelled{sailRISCVoverloadBBBBzupdatezyR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCModR}{\saildoclabelled{sailRISCVoverloadCCCCzzymodzyR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex}}}} + +\newcommand{\sailRISCVvalGetMisaQ}{\saildoclabelled{sailRISCVzzygetzyMisazyQ}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_q90da1bead4ec3b742728fa054935bbc0.tex}}}} + +\newcommand{\sailRISCVfnGetMisaQ}{\saildoclabelled{sailRISCVfnzzygetzyMisazyQ}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_q90da1bead4ec3b742728fa054935bbc0.tex}}}} + +\newcommand{\sailRISCVvalSetMisaQ}{\saildoclabelled{sailRISCVzzysetzyMisazyQ}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_q0b750236d1f52d9ca63b5ff7f29aeaad.tex}}}} + +\newcommand{\sailRISCVfnSetMisaQ}{\saildoclabelled{sailRISCVfnzzysetzyMisazyQ}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_q0b750236d1f52d9ca63b5ff7f29aeaad.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaQ}{\saildoclabelled{sailRISCVzzyupdatezyMisazyQ}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_q17b883fc2058f678be34555bf03acf4e.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaQ}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyQ}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_q17b883fc2058f678be34555bf03acf4e.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDupdateQ}{\saildoclabelled{sailRISCVoverloadDDDDzupdatezyQ}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDzupdate_q789d0c6855d20e12d058ed6a4170014d.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEModQ}{\saildoclabelled{sailRISCVoverloadEEEEzzymodzyQ}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEz_mod_qba4e572e9225df8e5fc28e66a1a59f8b.tex}}}} + +\newcommand{\sailRISCVvalGetMisaP}{\saildoclabelled{sailRISCVzzygetzyMisazyP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_p728ca41f7e9225442cea7a2d06fda1ba.tex}}}} + +\newcommand{\sailRISCVfnGetMisaP}{\saildoclabelled{sailRISCVfnzzygetzyMisazyP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_p728ca41f7e9225442cea7a2d06fda1ba.tex}}}} + +\newcommand{\sailRISCVvalSetMisaP}{\saildoclabelled{sailRISCVzzysetzyMisazyP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_p0c9c63b8a5952a51bae2365cdbc17092.tex}}}} + +\newcommand{\sailRISCVfnSetMisaP}{\saildoclabelled{sailRISCVfnzzysetzyMisazyP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_p0c9c63b8a5952a51bae2365cdbc17092.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaP}{\saildoclabelled{sailRISCVzzyupdatezyMisazyP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_pc6c8bc56b2633630ff91deb372f972a7.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaP}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_pc6c8bc56b2633630ff91deb372f972a7.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFupdateP}{\saildoclabelled{sailRISCVoverloadFFFFzupdatezyP}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFzupdate_pe6a91f2bcf1dfe547ab54c91e21491d7.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGModP}{\saildoclabelled{sailRISCVoverloadGGGGzzymodzyP}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGz_mod_p2173ed12d76a57820f7a2ec18bdf9649.tex}}}} + +\newcommand{\sailRISCVvalGetMisaO}{\saildoclabelled{sailRISCVzzygetzyMisazyO}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_o286d096661b36149b410863337f15d31.tex}}}} + +\newcommand{\sailRISCVfnGetMisaO}{\saildoclabelled{sailRISCVfnzzygetzyMisazyO}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_o286d096661b36149b410863337f15d31.tex}}}} + +\newcommand{\sailRISCVvalSetMisaO}{\saildoclabelled{sailRISCVzzysetzyMisazyO}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_o6e1ac3382cd1de0c3fbbaf6bbce3e104.tex}}}} + +\newcommand{\sailRISCVfnSetMisaO}{\saildoclabelled{sailRISCVfnzzysetzyMisazyO}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_o6e1ac3382cd1de0c3fbbaf6bbce3e104.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaO}{\saildoclabelled{sailRISCVzzyupdatezyMisazyO}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_obfc0e4a05dbc52b81817844c67df04f7.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaO}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyO}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_obfc0e4a05dbc52b81817844c67df04f7.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHupdateO}{\saildoclabelled{sailRISCVoverloadHHHHzupdatezyO}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHzupdate_o1cf4a63b59c60634f3652ef5713b7f66.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIModO}{\saildoclabelled{sailRISCVoverloadIIIIzzymodzyO}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIz_mod_o90384a06c29bd45bb9fb8e11226e2dcc.tex}}}} + +\newcommand{\sailRISCVvalGetMisaN}{\saildoclabelled{sailRISCVzzygetzyMisazyN}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_n58245b65aecd8d3dded8e5951d67f763.tex}}}} + +\newcommand{\sailRISCVfnGetMisaN}{\saildoclabelled{sailRISCVfnzzygetzyMisazyN}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_n58245b65aecd8d3dded8e5951d67f763.tex}}}} + +\newcommand{\sailRISCVvalSetMisaN}{\saildoclabelled{sailRISCVzzysetzyMisazyN}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_n1bb6db66ab4e88190d63b918228487ea.tex}}}} + +\newcommand{\sailRISCVfnSetMisaN}{\saildoclabelled{sailRISCVfnzzysetzyMisazyN}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_n1bb6db66ab4e88190d63b918228487ea.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaN}{\saildoclabelled{sailRISCVzzyupdatezyMisazyN}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_n83ee893338b4bd792d81b5cf59f2ebce.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaN}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyN}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_n83ee893338b4bd792d81b5cf59f2ebce.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJupdateN}{\saildoclabelled{sailRISCVoverloadJJJJzupdatezyN}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJzupdate_n06ad7e05862f7e6f8616952d94bf0cdf.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKModN}{\saildoclabelled{sailRISCVoverloadKKKKzzymodzyN}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKz_mod_n17a5dd1d9904ad5f32f920b05936d22a.tex}}}} + +\newcommand{\sailRISCVvalGetMisaM}{\saildoclabelled{sailRISCVzzygetzyMisazyM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_meaba66535fc1510348a6e72b1dbef759.tex}}}} + +\newcommand{\sailRISCVfnGetMisaM}{\saildoclabelled{sailRISCVfnzzygetzyMisazyM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_meaba66535fc1510348a6e72b1dbef759.tex}}}} + +\newcommand{\sailRISCVvalSetMisaM}{\saildoclabelled{sailRISCVzzysetzyMisazyM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_m9fc1a0ff196728bb0dbae698e2e8a7e9.tex}}}} + +\newcommand{\sailRISCVfnSetMisaM}{\saildoclabelled{sailRISCVfnzzysetzyMisazyM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_m9fc1a0ff196728bb0dbae698e2e8a7e9.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaM}{\saildoclabelled{sailRISCVzzyupdatezyMisazyM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_m698989b85ca48a2f975a5588f3dc7491.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaM}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_m698989b85ca48a2f975a5588f3dc7491.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLupdateM}{\saildoclabelled{sailRISCVoverloadLLLLzupdatezyM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLzupdate_m412167d0e8698c4d2e3c5386d172d67a.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMModM}{\saildoclabelled{sailRISCVoverloadMMMMzzymodzyM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMz_mod_mec2059285eb3c26fd1e8311b63d5c502.tex}}}} + +\newcommand{\sailRISCVvalGetMisaL}{\saildoclabelled{sailRISCVzzygetzyMisazyL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_lf087e66a72a445f7b73881c1235233c0.tex}}}} + +\newcommand{\sailRISCVfnGetMisaL}{\saildoclabelled{sailRISCVfnzzygetzyMisazyL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_lf087e66a72a445f7b73881c1235233c0.tex}}}} + +\newcommand{\sailRISCVvalSetMisaL}{\saildoclabelled{sailRISCVzzysetzyMisazyL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_lce522273afcdcceb0fff20729aec4ac4.tex}}}} + +\newcommand{\sailRISCVfnSetMisaL}{\saildoclabelled{sailRISCVfnzzysetzyMisazyL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_lce522273afcdcceb0fff20729aec4ac4.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaL}{\saildoclabelled{sailRISCVzzyupdatezyMisazyL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_l26aa92a8b1cde2502fe1736a8838b22e.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaL}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_l26aa92a8b1cde2502fe1736a8838b22e.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNupdateL}{\saildoclabelled{sailRISCVoverloadNNNNzupdatezyL}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNzupdate_l18c2828f8e56660ea058db7889463318.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOModL}{\saildoclabelled{sailRISCVoverloadOOOOzzymodzyL}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOz_mod_lac2bd336f003b6226e212aa9fd493ac8.tex}}}} + +\newcommand{\sailRISCVvalGetMisaK}{\saildoclabelled{sailRISCVzzygetzyMisazyK}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_k16049cc76852c9c8026f567e68a54414.tex}}}} + +\newcommand{\sailRISCVfnGetMisaK}{\saildoclabelled{sailRISCVfnzzygetzyMisazyK}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_k16049cc76852c9c8026f567e68a54414.tex}}}} + +\newcommand{\sailRISCVvalSetMisaK}{\saildoclabelled{sailRISCVzzysetzyMisazyK}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_k32d9915ba6161247dfa2e07599b14f05.tex}}}} + +\newcommand{\sailRISCVfnSetMisaK}{\saildoclabelled{sailRISCVfnzzysetzyMisazyK}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_k32d9915ba6161247dfa2e07599b14f05.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaK}{\saildoclabelled{sailRISCVzzyupdatezyMisazyK}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_kc4683fd490bb981aba37613fc8cdcb37.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaK}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyK}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_kc4683fd490bb981aba37613fc8cdcb37.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPupdateK}{\saildoclabelled{sailRISCVoverloadPPPPzupdatezyK}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPzupdate_k022206cce3b142160f729d7bf95e8a36.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQModK}{\saildoclabelled{sailRISCVoverloadQQQQzzymodzyK}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQz_mod_k2815acab0d1e9758841eb69be2dec6b4.tex}}}} + +\newcommand{\sailRISCVvalGetMisaJ}{\saildoclabelled{sailRISCVzzygetzyMisazyJ}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_j2bd628593035d085073fabfda59a3691.tex}}}} + +\newcommand{\sailRISCVfnGetMisaJ}{\saildoclabelled{sailRISCVfnzzygetzyMisazyJ}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_j2bd628593035d085073fabfda59a3691.tex}}}} + +\newcommand{\sailRISCVvalSetMisaJ}{\saildoclabelled{sailRISCVzzysetzyMisazyJ}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_jf62a4ffaf2eeedcd5ec20654000caf02.tex}}}} + +\newcommand{\sailRISCVfnSetMisaJ}{\saildoclabelled{sailRISCVfnzzysetzyMisazyJ}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_jf62a4ffaf2eeedcd5ec20654000caf02.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaJ}{\saildoclabelled{sailRISCVzzyupdatezyMisazyJ}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_j103955d7d1e9e399dfbb839d275455e0.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaJ}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyJ}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_j103955d7d1e9e399dfbb839d275455e0.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRupdateJ}{\saildoclabelled{sailRISCVoverloadRRRRzupdatezyJ}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRzupdate_j42315d8e5eeed615464c6d7cd92ba743.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSModJ}{\saildoclabelled{sailRISCVoverloadSSSSzzymodzyJ}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSz_mod_j99da9691d0d08dd9802e57459c1a645b.tex}}}} + +\newcommand{\sailRISCVvalGetMisaI}{\saildoclabelled{sailRISCVzzygetzyMisazyI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_ifd11140b556fe14f486f51c949a8637b.tex}}}} + +\newcommand{\sailRISCVfnGetMisaI}{\saildoclabelled{sailRISCVfnzzygetzyMisazyI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_ifd11140b556fe14f486f51c949a8637b.tex}}}} + +\newcommand{\sailRISCVvalSetMisaI}{\saildoclabelled{sailRISCVzzysetzyMisazyI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_i459bf00eda120c5909e07545e00c48c1.tex}}}} + +\newcommand{\sailRISCVfnSetMisaI}{\saildoclabelled{sailRISCVfnzzysetzyMisazyI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_i459bf00eda120c5909e07545e00c48c1.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaI}{\saildoclabelled{sailRISCVzzyupdatezyMisazyI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_i139fa4ff8a9c72a06d7ffebdda92436a.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaI}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_i139fa4ff8a9c72a06d7ffebdda92436a.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTupdateI}{\saildoclabelled{sailRISCVoverloadTTTTzupdatezyI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTzupdate_i23ad4da3401bf9554e20a8c3f705fe00.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUModI}{\saildoclabelled{sailRISCVoverloadUUUUzzymodzyI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUz_mod_i10672a4f5733dfdc7d432fb5c80c7e42.tex}}}} + +\newcommand{\sailRISCVvalGetMisaH}{\saildoclabelled{sailRISCVzzygetzyMisazyH}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_hd877c2daaecfe719a9d7c418c493c805.tex}}}} + +\newcommand{\sailRISCVfnGetMisaH}{\saildoclabelled{sailRISCVfnzzygetzyMisazyH}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_hd877c2daaecfe719a9d7c418c493c805.tex}}}} + +\newcommand{\sailRISCVvalSetMisaH}{\saildoclabelled{sailRISCVzzysetzyMisazyH}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_h7a13933c5ad288a885bba1ccd7aa1003.tex}}}} + +\newcommand{\sailRISCVfnSetMisaH}{\saildoclabelled{sailRISCVfnzzysetzyMisazyH}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_h7a13933c5ad288a885bba1ccd7aa1003.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaH}{\saildoclabelled{sailRISCVzzyupdatezyMisazyH}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_h360ae205342d957f7a624e4c1114fe8f.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaH}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyH}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_h360ae205342d957f7a624e4c1114fe8f.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVupdateH}{\saildoclabelled{sailRISCVoverloadVVVVzupdatezyH}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVzupdate_hae56bacde98340a2d95ba3256bd8ada9.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWModH}{\saildoclabelled{sailRISCVoverloadWWWWzzymodzyH}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWz_mod_h49b48eb0876f788743697a82df15f831.tex}}}} + +\newcommand{\sailRISCVvalGetMisaG}{\saildoclabelled{sailRISCVzzygetzyMisazyG}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_gcfcd286901f53880700e0bb46ee4c493.tex}}}} + +\newcommand{\sailRISCVfnGetMisaG}{\saildoclabelled{sailRISCVfnzzygetzyMisazyG}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_gcfcd286901f53880700e0bb46ee4c493.tex}}}} + +\newcommand{\sailRISCVvalSetMisaG}{\saildoclabelled{sailRISCVzzysetzyMisazyG}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_g7e6256e7a4ea213c35876542280b8601.tex}}}} + +\newcommand{\sailRISCVfnSetMisaG}{\saildoclabelled{sailRISCVfnzzysetzyMisazyG}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_g7e6256e7a4ea213c35876542280b8601.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaG}{\saildoclabelled{sailRISCVzzyupdatezyMisazyG}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_g10edea49b1441082ca8d42e45e1480ab.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaG}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyG}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_g10edea49b1441082ca8d42e45e1480ab.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXupdateG}{\saildoclabelled{sailRISCVoverloadXXXXzupdatezyG}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXzupdate_ga61979e0097ae60f8598f57688dbae8b.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYModG}{\saildoclabelled{sailRISCVoverloadYYYYzzymodzyG}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYz_mod_g521053c016cb3f20bf7b96843a7a2cf4.tex}}}} + +\newcommand{\sailRISCVvalGetMisaF}{\saildoclabelled{sailRISCVzzygetzyMisazyF}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_f684dc9ab9b0a463db4389e87dc7e784f.tex}}}} + +\newcommand{\sailRISCVfnGetMisaF}{\saildoclabelled{sailRISCVfnzzygetzyMisazyF}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_f684dc9ab9b0a463db4389e87dc7e784f.tex}}}} + +\newcommand{\sailRISCVvalSetMisaF}{\saildoclabelled{sailRISCVzzysetzyMisazyF}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_f8c698083198450c6a61ec00abe038c08.tex}}}} + +\newcommand{\sailRISCVfnSetMisaF}{\saildoclabelled{sailRISCVfnzzysetzyMisazyF}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_f8c698083198450c6a61ec00abe038c08.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaF}{\saildoclabelled{sailRISCVzzyupdatezyMisazyF}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_fc88c899133c0200ee42f24494da679a4.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaF}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyF}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_fc88c899133c0200ee42f24494da679a4.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZupdateF}{\saildoclabelled{sailRISCVoverloadZZZZzupdatezyF}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZzupdate_ff24be4e6c534e2f8325e19562655da80.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAModF}{\saildoclabelled{sailRISCVoverloadAAAAAzzymodzyF}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAz_mod_fd77a6e62ab1cfa45a61b48a241cf22f2.tex}}}} + +\newcommand{\sailRISCVvalGetMisaE}{\saildoclabelled{sailRISCVzzygetzyMisazyE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_efde9ad5723fbd21ad73d9649cc491dd4.tex}}}} + +\newcommand{\sailRISCVfnGetMisaE}{\saildoclabelled{sailRISCVfnzzygetzyMisazyE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_efde9ad5723fbd21ad73d9649cc491dd4.tex}}}} + +\newcommand{\sailRISCVvalSetMisaE}{\saildoclabelled{sailRISCVzzysetzyMisazyE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_e36282592c3981fb3312fd0b0b03227bd.tex}}}} + +\newcommand{\sailRISCVfnSetMisaE}{\saildoclabelled{sailRISCVfnzzysetzyMisazyE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_e36282592c3981fb3312fd0b0b03227bd.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaE}{\saildoclabelled{sailRISCVzzyupdatezyMisazyE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_e410ef028122a879e5db0523a611dbfe5.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaE}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_e410ef028122a879e5db0523a611dbfe5.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBupdateE}{\saildoclabelled{sailRISCVoverloadBBBBBzupdatezyE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBzupdate_e5b6e9655311268e198c390cdf59ecba9.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCModE}{\saildoclabelled{sailRISCVoverloadCCCCCzzymodzyE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCz_mod_e788189af4a7082aacc7ac54449a1c6f5.tex}}}} + +\newcommand{\sailRISCVvalGetMisaD}{\saildoclabelled{sailRISCVzzygetzyMisazyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_d254b68e0fd6637680c01aa4da6738280.tex}}}} + +\newcommand{\sailRISCVfnGetMisaD}{\saildoclabelled{sailRISCVfnzzygetzyMisazyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_d254b68e0fd6637680c01aa4da6738280.tex}}}} + +\newcommand{\sailRISCVvalSetMisaD}{\saildoclabelled{sailRISCVzzysetzyMisazyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_dc53b7d60ef59832cce8ea7080073ac39.tex}}}} + +\newcommand{\sailRISCVfnSetMisaD}{\saildoclabelled{sailRISCVfnzzysetzyMisazyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_dc53b7d60ef59832cce8ea7080073ac39.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaD}{\saildoclabelled{sailRISCVzzyupdatezyMisazyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_dae3fb84a048be1ee677eb585143660b4.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaD}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_dae3fb84a048be1ee677eb585143660b4.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDDupdateD}{\saildoclabelled{sailRISCVoverloadDDDDDzupdatezyD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDDzupdate_da9201c8a6710e680d16238f3581a0227.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEEModD}{\saildoclabelled{sailRISCVoverloadEEEEEzzymodzyD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEEz_mod_d8c29507d9735e49d608a373bd2e2c599.tex}}}} + +\newcommand{\sailRISCVvalGetMisaC}{\saildoclabelled{sailRISCVzzygetzyMisazyC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_c79dc24d8a0b99e961dd504cd6b697318.tex}}}} + +\newcommand{\sailRISCVfnGetMisaC}{\saildoclabelled{sailRISCVfnzzygetzyMisazyC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_c79dc24d8a0b99e961dd504cd6b697318.tex}}}} + +\newcommand{\sailRISCVvalSetMisaC}{\saildoclabelled{sailRISCVzzysetzyMisazyC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_cdd88b98e41a5e410ecf7b2bf6be19aa8.tex}}}} + +\newcommand{\sailRISCVfnSetMisaC}{\saildoclabelled{sailRISCVfnzzysetzyMisazyC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_cdd88b98e41a5e410ecf7b2bf6be19aa8.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaC}{\saildoclabelled{sailRISCVzzyupdatezyMisazyC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_c57e3c86e55b96ffdd3750d922289ff67.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaC}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_c57e3c86e55b96ffdd3750d922289ff67.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFFupdateC}{\saildoclabelled{sailRISCVoverloadFFFFFzupdatezyC}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFFzupdate_c58b96a6767db6cbc4e0bfce6023a35b9.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGGModC}{\saildoclabelled{sailRISCVoverloadGGGGGzzymodzyC}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGGz_mod_ceb8c62eaf4804c4722a6c0c552f18d93.tex}}}} + +\newcommand{\sailRISCVvalGetMisaB}{\saildoclabelled{sailRISCVzzygetzyMisazyB}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_b1d772b9d019b6aaad84ed1639e5e0d09.tex}}}} + +\newcommand{\sailRISCVfnGetMisaB}{\saildoclabelled{sailRISCVfnzzygetzyMisazyB}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_b1d772b9d019b6aaad84ed1639e5e0d09.tex}}}} + +\newcommand{\sailRISCVvalSetMisaB}{\saildoclabelled{sailRISCVzzysetzyMisazyB}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_b0a197892362ef80b92b24e457a36fe2e.tex}}}} + +\newcommand{\sailRISCVfnSetMisaB}{\saildoclabelled{sailRISCVfnzzysetzyMisazyB}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_b0a197892362ef80b92b24e457a36fe2e.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaB}{\saildoclabelled{sailRISCVzzyupdatezyMisazyB}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_be5486da384cf1d6bc28f1b8e40ddf4ad.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaB}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyB}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_be5486da384cf1d6bc28f1b8e40ddf4ad.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHHupdateB}{\saildoclabelled{sailRISCVoverloadHHHHHzupdatezyB}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHHzupdate_ba3e6b1d1a0efbd004275eab5c1c3b711.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIIModB}{\saildoclabelled{sailRISCVoverloadIIIIIzzymodzyB}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIIz_mod_bd3b147cd60c14b1c9fafe4194389bcdc.tex}}}} + +\newcommand{\sailRISCVvalGetMisaA}{\saildoclabelled{sailRISCVzzygetzyMisazyA}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_misa_af461bea08dc77aa785842eb918466700.tex}}}} + +\newcommand{\sailRISCVfnGetMisaA}{\saildoclabelled{sailRISCVfnzzygetzyMisazyA}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_misa_af461bea08dc77aa785842eb918466700.tex}}}} + +\newcommand{\sailRISCVvalSetMisaA}{\saildoclabelled{sailRISCVzzysetzyMisazyA}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_misa_af2a884db4759788724edc2e8603b8be4.tex}}}} + +\newcommand{\sailRISCVfnSetMisaA}{\saildoclabelled{sailRISCVfnzzysetzyMisazyA}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_misa_af2a884db4759788724edc2e8603b8be4.tex}}}} + +\newcommand{\sailRISCVvalUpdateMisaA}{\saildoclabelled{sailRISCVzzyupdatezyMisazyA}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_misa_a84a3cc4727896aed6b903b7b0d0caa83.tex}}}} + +\newcommand{\sailRISCVfnUpdateMisaA}{\saildoclabelled{sailRISCVfnzzyupdatezyMisazyA}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_misa_a84a3cc4727896aed6b903b7b0d0caa83.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJJupdateA}{\saildoclabelled{sailRISCVoverloadJJJJJzupdatezyA}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJJzupdate_ab740c1f378b55b3328b2a9f25ff6c1cf.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKKModA}{\saildoclabelled{sailRISCVoverloadKKKKKzzymodzyA}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKKz_mod_a62a6f88676512d98a363811f9f5ba327.tex}}}} + +\newcommand{\sailRISCVvalsysEnableWritableMisa}{\saildoclabelled{sailRISCVzsyszyenablezywritablezymisa}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsys_enable_writable_misa83863aeddc0d69035dc46d6908595d89.tex}}}} + +\newcommand{\sailRISCVvalsysEnableRvc}{\saildoclabelled{sailRISCVzsyszyenablezyrvc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsys_enable_rvc836db920a63cd54b635b109fb85bcb90.tex}}}} + +\newcommand{\sailRISCVvalsysEnableFdext}{\saildoclabelled{sailRISCVzsyszyenablezyfdext}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzsys_enable_fdext3e294bd170189b70567069837e1534c5.tex}}}} + +\newcommand{\sailRISCVvalextVetoDisableC}{\saildoclabelled{sailRISCVzextzyvetozydisablezyC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_veto_disable_cd10c2d1c5077060fa007c1628d7aaa8c.tex}}}} + +\newcommand{\sailRISCVvallegalizzeMisa}{\saildoclabelled{sailRISCVzlegalizzezymisa}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_misad494764bfeb5d382d189645941a1bce6.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeMisa}{\saildoclabelled{sailRISCVfnzlegalizzezymisa}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_misad494764bfeb5d382d189645941a1bce6.tex}}}} + +\newcommand{\sailRISCVvalhaveAtomics}{\saildoclabelled{sailRISCVzhaveAtomics}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhaveatomics63cb703b1e3f955440fac8b850da53f7.tex}}}} + +\newcommand{\sailRISCVfnhaveAtomics}{\saildoclabelled{sailRISCVfnzhaveAtomics}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhaveatomics63cb703b1e3f955440fac8b850da53f7.tex}}}} + +\newcommand{\sailRISCVvalhaveRVC}{\saildoclabelled{sailRISCVzhaveRVC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhavervcd1bab8584f566314057babec4a4bfcce.tex}}}} + +\newcommand{\sailRISCVfnhaveRVC}{\saildoclabelled{sailRISCVfnzhaveRVC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavervcd1bab8584f566314057babec4a4bfcce.tex}}}} + +\newcommand{\sailRISCVvalhaveMulDiv}{\saildoclabelled{sailRISCVzhaveMulDiv}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhavemuldivee13dcf875cf3974336f980d6be89b2a.tex}}}} + +\newcommand{\sailRISCVfnhaveMulDiv}{\saildoclabelled{sailRISCVfnzhaveMulDiv}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavemuldivee13dcf875cf3974336f980d6be89b2a.tex}}}} + +\newcommand{\sailRISCVvalhaveSupMode}{\saildoclabelled{sailRISCVzhaveSupMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhavesupmode3f08edf2b0386d18c650f34868f384db.tex}}}} + +\newcommand{\sailRISCVfnhaveSupMode}{\saildoclabelled{sailRISCVfnzhaveSupMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavesupmode3f08edf2b0386d18c650f34868f384db.tex}}}} + +\newcommand{\sailRISCVvalhaveUsrMode}{\saildoclabelled{sailRISCVzhaveUsrMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhaveusrmode2e520828ead805e9613cc1f88f964861.tex}}}} + +\newcommand{\sailRISCVfnhaveUsrMode}{\saildoclabelled{sailRISCVfnzhaveUsrMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhaveusrmode2e520828ead805e9613cc1f88f964861.tex}}}} + +\newcommand{\sailRISCVvalhaveNExt}{\saildoclabelled{sailRISCVzhaveNExt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhavenext74060caf84942f39cfe17eb66bce56e4.tex}}}} + +\newcommand{\sailRISCVfnhaveNExt}{\saildoclabelled{sailRISCVfnzhaveNExt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavenext74060caf84942f39cfe17eb66bce56e4.tex}}}} + +\newcommand{\sailRISCVtypeMstatus}{\saildoclabelled{sailRISCVtypezMstatus}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezmstatus6adeedf6ca37e8c03608d356a04db81f.tex}}}} + +\newcommand{\sailRISCVvalMkMstatus}{\saildoclabelled{sailRISCVzMkzyMstatus}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_mstatus5db327fc42d9fe4de62eca1e3915bd06.tex}}}} + +\newcommand{\sailRISCVfnMkMstatus}{\saildoclabelled{sailRISCVfnzMkzyMstatus}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_mstatus5db327fc42d9fe4de62eca1e3915bd06.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusBits}{\saildoclabelled{sailRISCVzzygetzyMstatuszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_bits0aa5b9575406d172210cdde6ef45d6cd.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusBits}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_bits0aa5b9575406d172210cdde6ef45d6cd.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusBits}{\saildoclabelled{sailRISCVzzysetzyMstatuszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_bits70d36d4b6b9dcb53e2c6533f6831dfa1.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusBits}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_bits70d36d4b6b9dcb53e2c6533f6831dfa1.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusBits}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_bits62d247fffd2b228018ee801927d13b83.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusBits}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_bits62d247fffd2b228018ee801927d13b83.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLLupdateBits}{\saildoclabelled{sailRISCVoverloadLLLLLzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLLzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMMModBits}{\saildoclabelled{sailRISCVoverloadMMMMMzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMMz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusSD}{\saildoclabelled{sailRISCVzzygetzyMstatuszySD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_sdd1de4e48331a465d1f6bc8b70c10db69.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusSD}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszySD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_sdd1de4e48331a465d1f6bc8b70c10db69.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusSD}{\saildoclabelled{sailRISCVzzysetzyMstatuszySD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_sdd513d7f81bd0e504ac04f4e053f73dea.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusSD}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszySD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_sdd513d7f81bd0e504ac04f4e053f73dea.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusSD}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszySD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_sda4daaeb7cf3d3804c84f8f3adc875435.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusSD}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszySD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_sda4daaeb7cf3d3804c84f8f3adc875435.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNNupdateSD}{\saildoclabelled{sailRISCVoverloadNNNNNzupdatezySD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNNzupdate_sd5d9e90ac938aa12ac2bdb01a3c3d6e92.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOOModSD}{\saildoclabelled{sailRISCVoverloadOOOOOzzymodzySD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOOz_mod_sd1e51a771a9b628b657ecbb1ba7aa8f7c.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusTSR}{\saildoclabelled{sailRISCVzzygetzyMstatuszyTSR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_tsr45a4c5c29b4ca69f189205bb23dbb516.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusTSR}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszyTSR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_tsr45a4c5c29b4ca69f189205bb23dbb516.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusTSR}{\saildoclabelled{sailRISCVzzysetzyMstatuszyTSR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_tsraafd8a43c6d53a07c488b0efb80af394.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusTSR}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszyTSR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_tsraafd8a43c6d53a07c488b0efb80af394.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusTSR}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszyTSR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_tsr911d1e468313451d39d3edd62969f771.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusTSR}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszyTSR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_tsr911d1e468313451d39d3edd62969f771.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPPupdateTSR}{\saildoclabelled{sailRISCVoverloadPPPPPzupdatezyTSR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPPzupdate_tsr6f4c30747be8b86521f24a17848f44f8.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQQModTSR}{\saildoclabelled{sailRISCVoverloadQQQQQzzymodzyTSR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQQz_mod_tsr0f7b8b3a1051c941d7b36c26a6689899.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusTW}{\saildoclabelled{sailRISCVzzygetzyMstatuszyTW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_twdd04977b0ac22974f609e5b00f1a09e9.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusTW}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszyTW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_twdd04977b0ac22974f609e5b00f1a09e9.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusTW}{\saildoclabelled{sailRISCVzzysetzyMstatuszyTW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_tw07f419963ff98d483c7b9ce832c90eb4.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusTW}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszyTW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_tw07f419963ff98d483c7b9ce832c90eb4.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusTW}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszyTW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_tw2d7307276d7507e86718caff9b05aee8.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusTW}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszyTW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_tw2d7307276d7507e86718caff9b05aee8.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRRupdateTW}{\saildoclabelled{sailRISCVoverloadRRRRRzupdatezyTW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRRzupdate_tw5ee4f2da170269d4a859283d302b33bb.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSSModTW}{\saildoclabelled{sailRISCVoverloadSSSSSzzymodzyTW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSSz_mod_twd51a94299168a627db8ea29496d4ea83.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusTVM}{\saildoclabelled{sailRISCVzzygetzyMstatuszyTVM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_tvm0a763585a6834af9f476c5b07d9dcce6.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusTVM}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszyTVM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_tvm0a763585a6834af9f476c5b07d9dcce6.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusTVM}{\saildoclabelled{sailRISCVzzysetzyMstatuszyTVM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_tvmb162bee39ba51b064f3dd93188326775.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusTVM}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszyTVM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_tvmb162bee39ba51b064f3dd93188326775.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusTVM}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszyTVM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_tvmf7d012651ef54cac1cdafef6e0e98a7f.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusTVM}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszyTVM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_tvmf7d012651ef54cac1cdafef6e0e98a7f.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTTupdateTVM}{\saildoclabelled{sailRISCVoverloadTTTTTzupdatezyTVM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTTzupdate_tvm7e1e43bb3e8b7c252211bd33016cce23.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUUModTVM}{\saildoclabelled{sailRISCVoverloadUUUUUzzymodzyTVM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUUz_mod_tvm115bf3a71837868b1ca1b42515d8bf97.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusMXR}{\saildoclabelled{sailRISCVzzygetzyMstatuszyMXR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_mxrc3cb8fda7e9db55ac7c86e5a6c05793f.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusMXR}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszyMXR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_mxrc3cb8fda7e9db55ac7c86e5a6c05793f.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusMXR}{\saildoclabelled{sailRISCVzzysetzyMstatuszyMXR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_mxr7d2c792dc408468b6a36d6dccfe73ce3.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusMXR}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszyMXR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_mxr7d2c792dc408468b6a36d6dccfe73ce3.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusMXR}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszyMXR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_mxr86db170c1ee7edaf7ee350f188d44e71.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusMXR}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszyMXR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_mxr86db170c1ee7edaf7ee350f188d44e71.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVVupdateMXR}{\saildoclabelled{sailRISCVoverloadVVVVVzupdatezyMXR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVVzupdate_mxra54b3693fefa5d6b0301ff08e0ea5a3f.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWWModMXR}{\saildoclabelled{sailRISCVoverloadWWWWWzzymodzyMXR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWWz_mod_mxr626efb0dadf77d402ea180eddd656377.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusSUM}{\saildoclabelled{sailRISCVzzygetzyMstatuszySUM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_sumdf310d1f826fe16b715b86b635711496.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusSUM}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszySUM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_sumdf310d1f826fe16b715b86b635711496.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusSUM}{\saildoclabelled{sailRISCVzzysetzyMstatuszySUM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_sume93a07e55c0ec08fc5f1fff8ec36c08c.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusSUM}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszySUM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_sume93a07e55c0ec08fc5f1fff8ec36c08c.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusSUM}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszySUM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_sumb7a60974e206e5c4db1cb80fdf3bcfe5.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusSUM}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszySUM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_sumb7a60974e206e5c4db1cb80fdf3bcfe5.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXXupdateSUM}{\saildoclabelled{sailRISCVoverloadXXXXXzupdatezySUM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXXzupdate_sum45aaa4f77ddaa1e976bb9719406d8d4d.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYYModSUM}{\saildoclabelled{sailRISCVoverloadYYYYYzzymodzySUM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYYz_mod_sum9c28eec9a0977f334c917bffeb75d7eb.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusMPRV}{\saildoclabelled{sailRISCVzzygetzyMstatuszyMPRV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_mprv4b66922b817797bb81a3c2cdfdeff3e4.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusMPRV}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszyMPRV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_mprv4b66922b817797bb81a3c2cdfdeff3e4.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusMPRV}{\saildoclabelled{sailRISCVzzysetzyMstatuszyMPRV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_mprv7cb39a57c743d887daa45479299eb721.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusMPRV}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszyMPRV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_mprv7cb39a57c743d887daa45479299eb721.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusMPRV}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszyMPRV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_mprv5d1e4d26fc69487fc2e371466a2aefda.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusMPRV}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszyMPRV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_mprv5d1e4d26fc69487fc2e371466a2aefda.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZZupdateMPRV}{\saildoclabelled{sailRISCVoverloadZZZZZzupdatezyMPRV}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZZzupdate_mprv112ef4f0b7ba57dead1dd08473f677fa.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAAModMPRV}{\saildoclabelled{sailRISCVoverloadAAAAAAzzymodzyMPRV}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAAz_mod_mprv5b120c5e51154d4f8a5780bd0310aa4b.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusXS}{\saildoclabelled{sailRISCVzzygetzyMstatuszyXS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_xsb541df8fdc5ba9ddaf95a2890f06b4b1.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusXS}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszyXS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_xsb541df8fdc5ba9ddaf95a2890f06b4b1.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusXS}{\saildoclabelled{sailRISCVzzysetzyMstatuszyXS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_xs13adea89de69c7b934d405e2c5369191.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusXS}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszyXS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_xs13adea89de69c7b934d405e2c5369191.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusXS}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszyXS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_xsa631910853fd5409435e58ed9e2273a3.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusXS}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszyXS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_xsa631910853fd5409435e58ed9e2273a3.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBBupdateXS}{\saildoclabelled{sailRISCVoverloadBBBBBBzupdatezyXS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBBzupdate_xsd577805c39539bb2ca85cd57d24ab51e.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCCModXS}{\saildoclabelled{sailRISCVoverloadCCCCCCzzymodzyXS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCCz_mod_xs4cdc96063571eef4b6f09a5174c4405f.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusFS}{\saildoclabelled{sailRISCVzzygetzyMstatuszyFS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_fs330eb17a3e05d1bdbd6f51377b6d3412.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusFS}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszyFS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_fs330eb17a3e05d1bdbd6f51377b6d3412.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusFS}{\saildoclabelled{sailRISCVzzysetzyMstatuszyFS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_fsf8cc24d417ffb4c08683df543afa5120.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusFS}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszyFS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_fsf8cc24d417ffb4c08683df543afa5120.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusFS}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszyFS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_fsf06a4782f53e6ed8e2818ec43a049e21.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusFS}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszyFS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_fsf06a4782f53e6ed8e2818ec43a049e21.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDDDupdateFS}{\saildoclabelled{sailRISCVoverloadDDDDDDzupdatezyFS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDDDzupdate_fs64e6ca4d39ea47b95fa1da5e3e2e0921.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEEEModFS}{\saildoclabelled{sailRISCVoverloadEEEEEEzzymodzyFS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEEEz_mod_fs91fd3eaccea19c4e4e7d0eef23a6ae9a.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusMPP}{\saildoclabelled{sailRISCVzzygetzyMstatuszyMPP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_mppaf78fafa2a77f2e77dbce07a488444bf.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusMPP}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszyMPP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_mppaf78fafa2a77f2e77dbce07a488444bf.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusMPP}{\saildoclabelled{sailRISCVzzysetzyMstatuszyMPP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_mppaeee0122745c7341c92694423c1d67fa.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusMPP}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszyMPP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_mppaeee0122745c7341c92694423c1d67fa.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusMPP}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszyMPP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_mpp0dfb32efcb28c9f2f9f70f8b7fc4edeb.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusMPP}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszyMPP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_mpp0dfb32efcb28c9f2f9f70f8b7fc4edeb.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFFFupdateMPP}{\saildoclabelled{sailRISCVoverloadFFFFFFzupdatezyMPP}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFFFzupdate_mpp3c9c58e612012b492912dc500a75dc6e.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGGGModMPP}{\saildoclabelled{sailRISCVoverloadGGGGGGzzymodzyMPP}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGGGz_mod_mpp3d9619db1e6f03e1e065c1fea13b6a67.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusSPP}{\saildoclabelled{sailRISCVzzygetzyMstatuszySPP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_spp27a2b01ae2feb0234f716a7027839bbd.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusSPP}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszySPP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_spp27a2b01ae2feb0234f716a7027839bbd.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusSPP}{\saildoclabelled{sailRISCVzzysetzyMstatuszySPP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_sppf813af50b83110182ea2f06174cb1d20.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusSPP}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszySPP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_sppf813af50b83110182ea2f06174cb1d20.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusSPP}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszySPP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_sppfa488292080686e2372e721aece0aca4.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusSPP}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszySPP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_sppfa488292080686e2372e721aece0aca4.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHHHupdateSPP}{\saildoclabelled{sailRISCVoverloadHHHHHHzupdatezySPP}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHHHzupdate_spp8c7dea9e7e0f6e12e0b546be06facdc6.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIIIModSPP}{\saildoclabelled{sailRISCVoverloadIIIIIIzzymodzySPP}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIIIz_mod_spp50ceeb4c06bc3d145fb76bed24fa7e68.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusMPIE}{\saildoclabelled{sailRISCVzzygetzyMstatuszyMPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_mpie70d0deda1607434a8f6fc4a7553fa022.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusMPIE}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszyMPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_mpie70d0deda1607434a8f6fc4a7553fa022.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusMPIE}{\saildoclabelled{sailRISCVzzysetzyMstatuszyMPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_mpieb229e5b0c3cc862190502f8c77503c18.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusMPIE}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszyMPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_mpieb229e5b0c3cc862190502f8c77503c18.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusMPIE}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszyMPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_mpie66bbd7d75ad543a33368f099d66c2ad3.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusMPIE}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszyMPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_mpie66bbd7d75ad543a33368f099d66c2ad3.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJJJupdateMPIE}{\saildoclabelled{sailRISCVoverloadJJJJJJzupdatezyMPIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJJJzupdate_mpiea8e9bf67d46cea99b972f7713503794d.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKKKModMPIE}{\saildoclabelled{sailRISCVoverloadKKKKKKzzymodzyMPIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKKKz_mod_mpief0782a90b79bf243f3b4c31e5bf1eda0.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusSPIE}{\saildoclabelled{sailRISCVzzygetzyMstatuszySPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_spie13e7c8fd06a819c72ff0319a1708039d.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusSPIE}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszySPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_spie13e7c8fd06a819c72ff0319a1708039d.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusSPIE}{\saildoclabelled{sailRISCVzzysetzyMstatuszySPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_spie57764ca3799b0493ec493d655361699e.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusSPIE}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszySPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_spie57764ca3799b0493ec493d655361699e.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusSPIE}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszySPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_spie6da04c490b761f34be7c9f4b5f75dd15.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusSPIE}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszySPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_spie6da04c490b761f34be7c9f4b5f75dd15.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLLLupdateSPIE}{\saildoclabelled{sailRISCVoverloadLLLLLLzupdatezySPIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLLLzupdate_spie94668fa3ad37daf933543298ec02f222.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMMMModSPIE}{\saildoclabelled{sailRISCVoverloadMMMMMMzzymodzySPIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMMMz_mod_spie8a60328109316a4d9a0f7769708c8522.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusUPIE}{\saildoclabelled{sailRISCVzzygetzyMstatuszyUPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_upieb1f082dfe5cc07cf43ceb1a9c5ddd9e4.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusUPIE}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszyUPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_upieb1f082dfe5cc07cf43ceb1a9c5ddd9e4.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusUPIE}{\saildoclabelled{sailRISCVzzysetzyMstatuszyUPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_upie97f5fcc7e74b28a97eb44ae99226200f.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusUPIE}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszyUPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_upie97f5fcc7e74b28a97eb44ae99226200f.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusUPIE}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszyUPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_upie62eccd6c3bcbfbe552e26c27d8c9e73e.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusUPIE}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszyUPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_upie62eccd6c3bcbfbe552e26c27d8c9e73e.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNNNupdateUPIE}{\saildoclabelled{sailRISCVoverloadNNNNNNzupdatezyUPIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNNNzupdate_upiea5ad86a550536087d757a5582d1a8bb9.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOOOModUPIE}{\saildoclabelled{sailRISCVoverloadOOOOOOzzymodzyUPIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOOOz_mod_upie27f56ba53dc72f512e0a128ab616ba83.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusMIE}{\saildoclabelled{sailRISCVzzygetzyMstatuszyMIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_mie663746b59e574a55bd4a0897e80f3213.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusMIE}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszyMIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_mie663746b59e574a55bd4a0897e80f3213.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusMIE}{\saildoclabelled{sailRISCVzzysetzyMstatuszyMIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_mie3ca1abf74b0d93affa2751898f9cdd5b.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusMIE}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszyMIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_mie3ca1abf74b0d93affa2751898f9cdd5b.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusMIE}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszyMIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_mie80faf2146d01111ce6c4739dfadf9c5a.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusMIE}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszyMIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_mie80faf2146d01111ce6c4739dfadf9c5a.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPPPupdateMIE}{\saildoclabelled{sailRISCVoverloadPPPPPPzupdatezyMIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPPPzupdate_mie814cfc4975c3e1f41026c234060b84d3.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQQQModMIE}{\saildoclabelled{sailRISCVoverloadQQQQQQzzymodzyMIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQQQz_mod_mie44478e86e68d533e6e7ad86bf6100f17.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusSIE}{\saildoclabelled{sailRISCVzzygetzyMstatuszySIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_sied77d2cea6c4c5513b90c521245df3f40.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusSIE}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszySIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_sied77d2cea6c4c5513b90c521245df3f40.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusSIE}{\saildoclabelled{sailRISCVzzysetzyMstatuszySIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_sie307ee7865e3a638cfafc30565428356d.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusSIE}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszySIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_sie307ee7865e3a638cfafc30565428356d.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusSIE}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszySIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_sie59e9df0f2de34ad900e35dadcacc511b.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusSIE}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszySIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_sie59e9df0f2de34ad900e35dadcacc511b.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRRRupdateSIE}{\saildoclabelled{sailRISCVoverloadRRRRRRzupdatezySIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRRRzupdate_sie1b2ed07072361c44e9ce7a8ca87b5555.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSSSModSIE}{\saildoclabelled{sailRISCVoverloadSSSSSSzzymodzySIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSSSz_mod_sieea56e4c7d22bb7c198ba004deeb422c9.tex}}}} + +\newcommand{\sailRISCVvalGetMstatusUIE}{\saildoclabelled{sailRISCVzzygetzyMstatuszyUIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mstatus_uie038bd3276e1254d44c8bafbeafa41955.tex}}}} + +\newcommand{\sailRISCVfnGetMstatusUIE}{\saildoclabelled{sailRISCVfnzzygetzyMstatuszyUIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mstatus_uie038bd3276e1254d44c8bafbeafa41955.tex}}}} + +\newcommand{\sailRISCVvalSetMstatusUIE}{\saildoclabelled{sailRISCVzzysetzyMstatuszyUIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mstatus_uieb479c3c10676b772a02256f3db5428da.tex}}}} + +\newcommand{\sailRISCVfnSetMstatusUIE}{\saildoclabelled{sailRISCVfnzzysetzyMstatuszyUIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mstatus_uieb479c3c10676b772a02256f3db5428da.tex}}}} + +\newcommand{\sailRISCVvalUpdateMstatusUIE}{\saildoclabelled{sailRISCVzzyupdatezyMstatuszyUIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mstatus_uie24981f834cc06df1bad9dd31da0f462b.tex}}}} + +\newcommand{\sailRISCVfnUpdateMstatusUIE}{\saildoclabelled{sailRISCVfnzzyupdatezyMstatuszyUIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mstatus_uie24981f834cc06df1bad9dd31da0f462b.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTTTupdateUIE}{\saildoclabelled{sailRISCVoverloadTTTTTTzupdatezyUIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTTTzupdate_uied194e7b32c7c54d35dfc1b602b4b5907.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUUUModUIE}{\saildoclabelled{sailRISCVoverloadUUUUUUzzymodzyUIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUUUz_mod_uie18b8fe18a506d4c612ff106c8cc5fb23.tex}}}} + +\newcommand{\sailRISCVvaleffectivePrivilege}{\saildoclabelled{sailRISCVzeffectivePrivilege}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzeffectiveprivilegeb14beb91b9202c1aefb99c45054bcb23.tex}}}} + +\newcommand{\sailRISCVfneffectivePrivilege}{\saildoclabelled{sailRISCVfnzeffectivePrivilege}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzeffectiveprivilegeb14beb91b9202c1aefb99c45054bcb23.tex}}}} + +\newcommand{\sailRISCVvalgetMstatusSXL}{\saildoclabelled{sailRISCVzgetzymstatuszySXL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_mstatus_sxl360b4b5f8d3130ad7ed7bb536d1d7019.tex}}}} + +\newcommand{\sailRISCVfngetMstatusSXL}{\saildoclabelled{sailRISCVfnzgetzymstatuszySXL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_mstatus_sxl360b4b5f8d3130ad7ed7bb536d1d7019.tex}}}} + +\newcommand{\sailRISCVvalsetMstatusSXL}{\saildoclabelled{sailRISCVzsetzymstatuszySXL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzset_mstatus_sxl3c993e2659d94bb903dbbc607aa47f8c.tex}}}} + +\newcommand{\sailRISCVfnsetMstatusSXL}{\saildoclabelled{sailRISCVfnzsetzymstatuszySXL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzset_mstatus_sxl3c993e2659d94bb903dbbc607aa47f8c.tex}}}} + +\newcommand{\sailRISCVvalgetMstatusUXL}{\saildoclabelled{sailRISCVzgetzymstatuszyUXL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_mstatus_uxl7f41d7b1028a3b1a7e11b635a0524660.tex}}}} + +\newcommand{\sailRISCVfngetMstatusUXL}{\saildoclabelled{sailRISCVfnzgetzymstatuszyUXL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_mstatus_uxl7f41d7b1028a3b1a7e11b635a0524660.tex}}}} + +\newcommand{\sailRISCVvalsetMstatusUXL}{\saildoclabelled{sailRISCVzsetzymstatuszyUXL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzset_mstatus_uxl030f4a70ceca0610271994fbfcb96d4d.tex}}}} + +\newcommand{\sailRISCVfnsetMstatusUXL}{\saildoclabelled{sailRISCVfnzsetzymstatuszyUXL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzset_mstatus_uxl030f4a70ceca0610271994fbfcb96d4d.tex}}}} + +\newcommand{\sailRISCVvallegalizzeMstatus}{\saildoclabelled{sailRISCVzlegalizzezymstatus}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_mstatus99091e0733640797e5a873808232271b.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeMstatus}{\saildoclabelled{sailRISCVfnzlegalizzezymstatus}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_mstatus99091e0733640797e5a873808232271b.tex}}}} + +\newcommand{\sailRISCVvalcurArchitecture}{\saildoclabelled{sailRISCVzcurzyArchitecture}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcur_architecture146db9bbeb421361d412d7f5f7f40511.tex}}}} + +\newcommand{\sailRISCVfncurArchitecture}{\saildoclabelled{sailRISCVfnzcurzyArchitecture}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcur_architecture146db9bbeb421361d412d7f5f7f40511.tex}}}} + +\newcommand{\sailRISCVvalinThreeTwoBitMode}{\saildoclabelled{sailRISCVzin32BitMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzin32bitmode1fa9d4b065e1807e1dff8fc7b86cca8d.tex}}}} + +\newcommand{\sailRISCVfninThreeTwoBitMode}{\saildoclabelled{sailRISCVfnzin32BitMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzin32bitmode1fa9d4b065e1807e1dff8fc7b86cca8d.tex}}}} + +\newcommand{\sailRISCVvalhaveFExt}{\saildoclabelled{sailRISCVzhaveFExt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhavefext496ba4ad5d47088bd723ab96ed6356d0.tex}}}} + +\newcommand{\sailRISCVfnhaveFExt}{\saildoclabelled{sailRISCVfnzhaveFExt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavefext496ba4ad5d47088bd723ab96ed6356d0.tex}}}} + +\newcommand{\sailRISCVvalhaveDExt}{\saildoclabelled{sailRISCVzhaveDExt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhavedextbb6a692871d46f160484ca963a3fffd0.tex}}}} + +\newcommand{\sailRISCVfnhaveDExt}{\saildoclabelled{sailRISCVfnzhaveDExt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavedextbb6a692871d46f160484ca963a3fffd0.tex}}}} + +\newcommand{\sailRISCVtypeMinterrupts}{\saildoclabelled{sailRISCVtypezMinterrupts}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezminterrupts12bbecae04331c3c2bd6fea56af2709c.tex}}}} + +\newcommand{\sailRISCVvalMkMinterrupts}{\saildoclabelled{sailRISCVzMkzyMinterrupts}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_minterruptsaf75f6e1eef17a71d4f11eede706901d.tex}}}} + +\newcommand{\sailRISCVfnMkMinterrupts}{\saildoclabelled{sailRISCVfnzMkzyMinterrupts}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_minterruptsaf75f6e1eef17a71d4f11eede706901d.tex}}}} + +\newcommand{\sailRISCVvalGetMinterruptsBits}{\saildoclabelled{sailRISCVzzygetzyMinterruptszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_minterrupts_bits9861684a481530d5524ef64aad179e28.tex}}}} + +\newcommand{\sailRISCVfnGetMinterruptsBits}{\saildoclabelled{sailRISCVfnzzygetzyMinterruptszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_minterrupts_bits9861684a481530d5524ef64aad179e28.tex}}}} + +\newcommand{\sailRISCVvalSetMinterruptsBits}{\saildoclabelled{sailRISCVzzysetzyMinterruptszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_minterrupts_bits33c9485121287572c28dfb5038fc3d62.tex}}}} + +\newcommand{\sailRISCVfnSetMinterruptsBits}{\saildoclabelled{sailRISCVfnzzysetzyMinterruptszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_minterrupts_bits33c9485121287572c28dfb5038fc3d62.tex}}}} + +\newcommand{\sailRISCVvalUpdateMinterruptsBits}{\saildoclabelled{sailRISCVzzyupdatezyMinterruptszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_minterrupts_bitsd26668b9d73aea27c77c64039eabb63d.tex}}}} + +\newcommand{\sailRISCVfnUpdateMinterruptsBits}{\saildoclabelled{sailRISCVfnzzyupdatezyMinterruptszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_minterrupts_bitsd26668b9d73aea27c77c64039eabb63d.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVVVupdateBits}{\saildoclabelled{sailRISCVoverloadVVVVVVzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVVVzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWWWModBits}{\saildoclabelled{sailRISCVoverloadWWWWWWzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWWWz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetMinterruptsMEI}{\saildoclabelled{sailRISCVzzygetzyMinterruptszyMEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_minterrupts_mei515173f9dd00afe3be3a8f7e3877089a.tex}}}} + +\newcommand{\sailRISCVfnGetMinterruptsMEI}{\saildoclabelled{sailRISCVfnzzygetzyMinterruptszyMEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_minterrupts_mei515173f9dd00afe3be3a8f7e3877089a.tex}}}} + +\newcommand{\sailRISCVvalSetMinterruptsMEI}{\saildoclabelled{sailRISCVzzysetzyMinterruptszyMEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_minterrupts_mei9744cce951b17c7e2932ca8ace0338c4.tex}}}} + +\newcommand{\sailRISCVfnSetMinterruptsMEI}{\saildoclabelled{sailRISCVfnzzysetzyMinterruptszyMEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_minterrupts_mei9744cce951b17c7e2932ca8ace0338c4.tex}}}} + +\newcommand{\sailRISCVvalUpdateMinterruptsMEI}{\saildoclabelled{sailRISCVzzyupdatezyMinterruptszyMEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_minterrupts_mei7bb6606e9f2d34ff0ba0b340c3513751.tex}}}} + +\newcommand{\sailRISCVfnUpdateMinterruptsMEI}{\saildoclabelled{sailRISCVfnzzyupdatezyMinterruptszyMEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_minterrupts_mei7bb6606e9f2d34ff0ba0b340c3513751.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXXXupdateMEI}{\saildoclabelled{sailRISCVoverloadXXXXXXzupdatezyMEI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXXXzupdate_mei397a1d801cdc3d609ba62d313a1c78b6.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYYYModMEI}{\saildoclabelled{sailRISCVoverloadYYYYYYzzymodzyMEI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYYYz_mod_meicf8fd69c57324173193cd468636980ed.tex}}}} + +\newcommand{\sailRISCVvalGetMinterruptsSEI}{\saildoclabelled{sailRISCVzzygetzyMinterruptszySEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_minterrupts_sei6f52e9424a41a0158d2b56253ab8fdd9.tex}}}} + +\newcommand{\sailRISCVfnGetMinterruptsSEI}{\saildoclabelled{sailRISCVfnzzygetzyMinterruptszySEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_minterrupts_sei6f52e9424a41a0158d2b56253ab8fdd9.tex}}}} + +\newcommand{\sailRISCVvalSetMinterruptsSEI}{\saildoclabelled{sailRISCVzzysetzyMinterruptszySEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_minterrupts_seied3b72a76b0168176b36aa09bb08b409.tex}}}} + +\newcommand{\sailRISCVfnSetMinterruptsSEI}{\saildoclabelled{sailRISCVfnzzysetzyMinterruptszySEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_minterrupts_seied3b72a76b0168176b36aa09bb08b409.tex}}}} + +\newcommand{\sailRISCVvalUpdateMinterruptsSEI}{\saildoclabelled{sailRISCVzzyupdatezyMinterruptszySEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_minterrupts_seib6916fd16d950d563a0f6ee65919136c.tex}}}} + +\newcommand{\sailRISCVfnUpdateMinterruptsSEI}{\saildoclabelled{sailRISCVfnzzyupdatezyMinterruptszySEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_minterrupts_seib6916fd16d950d563a0f6ee65919136c.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZZZupdateSEI}{\saildoclabelled{sailRISCVoverloadZZZZZZzupdatezySEI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZZZzupdate_seif1998ef482e23699637a58efcff9cf08.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAAAModSEI}{\saildoclabelled{sailRISCVoverloadAAAAAAAzzymodzySEI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAAAz_mod_sei769b57e17c0057e7ca956b7721915a2e.tex}}}} + +\newcommand{\sailRISCVvalGetMinterruptsUEI}{\saildoclabelled{sailRISCVzzygetzyMinterruptszyUEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_minterrupts_uei0f43bea7cfb1473c624d84e67401f902.tex}}}} + +\newcommand{\sailRISCVfnGetMinterruptsUEI}{\saildoclabelled{sailRISCVfnzzygetzyMinterruptszyUEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_minterrupts_uei0f43bea7cfb1473c624d84e67401f902.tex}}}} + +\newcommand{\sailRISCVvalSetMinterruptsUEI}{\saildoclabelled{sailRISCVzzysetzyMinterruptszyUEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_minterrupts_uei094ebc68e14480c18355d8aa2f610f29.tex}}}} + +\newcommand{\sailRISCVfnSetMinterruptsUEI}{\saildoclabelled{sailRISCVfnzzysetzyMinterruptszyUEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_minterrupts_uei094ebc68e14480c18355d8aa2f610f29.tex}}}} + +\newcommand{\sailRISCVvalUpdateMinterruptsUEI}{\saildoclabelled{sailRISCVzzyupdatezyMinterruptszyUEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_minterrupts_uei72e8cc258b8ba110b65ac0940a170b2c.tex}}}} + +\newcommand{\sailRISCVfnUpdateMinterruptsUEI}{\saildoclabelled{sailRISCVfnzzyupdatezyMinterruptszyUEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_minterrupts_uei72e8cc258b8ba110b65ac0940a170b2c.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBBBupdateUEI}{\saildoclabelled{sailRISCVoverloadBBBBBBBzupdatezyUEI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBBBzupdate_uei8252f0ae84161aa560a37211f39d1461.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCCCModUEI}{\saildoclabelled{sailRISCVoverloadCCCCCCCzzymodzyUEI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCCCz_mod_uei7faef47ef8aacd0d1b2ad1e0530fdf8e.tex}}}} + +\newcommand{\sailRISCVvalGetMinterruptsMTI}{\saildoclabelled{sailRISCVzzygetzyMinterruptszyMTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_minterrupts_mtia5225791c34b1551a9ad789bbc693091.tex}}}} + +\newcommand{\sailRISCVfnGetMinterruptsMTI}{\saildoclabelled{sailRISCVfnzzygetzyMinterruptszyMTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_minterrupts_mtia5225791c34b1551a9ad789bbc693091.tex}}}} + +\newcommand{\sailRISCVvalSetMinterruptsMTI}{\saildoclabelled{sailRISCVzzysetzyMinterruptszyMTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_minterrupts_mtia7bb5032baba4531a4c7bb5fe29eed89.tex}}}} + +\newcommand{\sailRISCVfnSetMinterruptsMTI}{\saildoclabelled{sailRISCVfnzzysetzyMinterruptszyMTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_minterrupts_mtia7bb5032baba4531a4c7bb5fe29eed89.tex}}}} + +\newcommand{\sailRISCVvalUpdateMinterruptsMTI}{\saildoclabelled{sailRISCVzzyupdatezyMinterruptszyMTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_minterrupts_mtic13c165f79b6b9773ec4f922e35a0ebd.tex}}}} + +\newcommand{\sailRISCVfnUpdateMinterruptsMTI}{\saildoclabelled{sailRISCVfnzzyupdatezyMinterruptszyMTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_minterrupts_mtic13c165f79b6b9773ec4f922e35a0ebd.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDDDDupdateMTI}{\saildoclabelled{sailRISCVoverloadDDDDDDDzupdatezyMTI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDDDDzupdate_mtie9a0e80e380d13919203a8a6c5c07d8d.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEEEEModMTI}{\saildoclabelled{sailRISCVoverloadEEEEEEEzzymodzyMTI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEEEEz_mod_mti2df88e254ec8ac5958e47465bf888c25.tex}}}} + +\newcommand{\sailRISCVvalGetMinterruptsSTI}{\saildoclabelled{sailRISCVzzygetzyMinterruptszySTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_minterrupts_stic7fb02b96430cfa9febfe409633700b7.tex}}}} + +\newcommand{\sailRISCVfnGetMinterruptsSTI}{\saildoclabelled{sailRISCVfnzzygetzyMinterruptszySTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_minterrupts_stic7fb02b96430cfa9febfe409633700b7.tex}}}} + +\newcommand{\sailRISCVvalSetMinterruptsSTI}{\saildoclabelled{sailRISCVzzysetzyMinterruptszySTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_minterrupts_sti916655477209971ff8cdb58c26f6ef93.tex}}}} + +\newcommand{\sailRISCVfnSetMinterruptsSTI}{\saildoclabelled{sailRISCVfnzzysetzyMinterruptszySTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_minterrupts_sti916655477209971ff8cdb58c26f6ef93.tex}}}} + +\newcommand{\sailRISCVvalUpdateMinterruptsSTI}{\saildoclabelled{sailRISCVzzyupdatezyMinterruptszySTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_minterrupts_sti2b202ceb3ff9251d1c300cb53ff1c320.tex}}}} + +\newcommand{\sailRISCVfnUpdateMinterruptsSTI}{\saildoclabelled{sailRISCVfnzzyupdatezyMinterruptszySTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_minterrupts_sti2b202ceb3ff9251d1c300cb53ff1c320.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFFFFupdateSTI}{\saildoclabelled{sailRISCVoverloadFFFFFFFzupdatezySTI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFFFFzupdate_stibc2608b6e320f416ad08499be50228f8.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGGGGModSTI}{\saildoclabelled{sailRISCVoverloadGGGGGGGzzymodzySTI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGGGGz_mod_sti42df95a06ca2a120a19277cb17015a3f.tex}}}} + +\newcommand{\sailRISCVvalGetMinterruptsUTI}{\saildoclabelled{sailRISCVzzygetzyMinterruptszyUTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_minterrupts_uti7d38c0c4d8098334626461d0c0734e18.tex}}}} + +\newcommand{\sailRISCVfnGetMinterruptsUTI}{\saildoclabelled{sailRISCVfnzzygetzyMinterruptszyUTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_minterrupts_uti7d38c0c4d8098334626461d0c0734e18.tex}}}} + +\newcommand{\sailRISCVvalSetMinterruptsUTI}{\saildoclabelled{sailRISCVzzysetzyMinterruptszyUTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_minterrupts_utid09c8a6e5f537755c8564dc71a61f188.tex}}}} + +\newcommand{\sailRISCVfnSetMinterruptsUTI}{\saildoclabelled{sailRISCVfnzzysetzyMinterruptszyUTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_minterrupts_utid09c8a6e5f537755c8564dc71a61f188.tex}}}} + +\newcommand{\sailRISCVvalUpdateMinterruptsUTI}{\saildoclabelled{sailRISCVzzyupdatezyMinterruptszyUTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_minterrupts_utiadd0aa7121b36a517ccef2ac029d52ac.tex}}}} + +\newcommand{\sailRISCVfnUpdateMinterruptsUTI}{\saildoclabelled{sailRISCVfnzzyupdatezyMinterruptszyUTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_minterrupts_utiadd0aa7121b36a517ccef2ac029d52ac.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHHHHupdateUTI}{\saildoclabelled{sailRISCVoverloadHHHHHHHzupdatezyUTI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHHHHzupdate_uti7bb127f84633c2b4f4b4de5582168ddf.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIIIIModUTI}{\saildoclabelled{sailRISCVoverloadIIIIIIIzzymodzyUTI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIIIIz_mod_utia23224af950fbe7be4b3db2f7092e6b4.tex}}}} + +\newcommand{\sailRISCVvalGetMinterruptsMSI}{\saildoclabelled{sailRISCVzzygetzyMinterruptszyMSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_minterrupts_msia5cfaf4688d1a0068789c380e6843d0e.tex}}}} + +\newcommand{\sailRISCVfnGetMinterruptsMSI}{\saildoclabelled{sailRISCVfnzzygetzyMinterruptszyMSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_minterrupts_msia5cfaf4688d1a0068789c380e6843d0e.tex}}}} + +\newcommand{\sailRISCVvalSetMinterruptsMSI}{\saildoclabelled{sailRISCVzzysetzyMinterruptszyMSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_minterrupts_msi2f29aeb62fd44e400e4d6811ee58eff4.tex}}}} + +\newcommand{\sailRISCVfnSetMinterruptsMSI}{\saildoclabelled{sailRISCVfnzzysetzyMinterruptszyMSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_minterrupts_msi2f29aeb62fd44e400e4d6811ee58eff4.tex}}}} + +\newcommand{\sailRISCVvalUpdateMinterruptsMSI}{\saildoclabelled{sailRISCVzzyupdatezyMinterruptszyMSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_minterrupts_msib1e866772ecd94b3b9b2c2c19feb2efc.tex}}}} + +\newcommand{\sailRISCVfnUpdateMinterruptsMSI}{\saildoclabelled{sailRISCVfnzzyupdatezyMinterruptszyMSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_minterrupts_msib1e866772ecd94b3b9b2c2c19feb2efc.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJJJJupdateMSI}{\saildoclabelled{sailRISCVoverloadJJJJJJJzupdatezyMSI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJJJJzupdate_msi05b568752ec5efb2935982bb126bbdae.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKKKKModMSI}{\saildoclabelled{sailRISCVoverloadKKKKKKKzzymodzyMSI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKKKKz_mod_msid0d72e986b51e2572e46aebbb9db0de0.tex}}}} + +\newcommand{\sailRISCVvalGetMinterruptsSSI}{\saildoclabelled{sailRISCVzzygetzyMinterruptszySSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_minterrupts_ssi8ebb8da6cffaa81a169231cdfe86edca.tex}}}} + +\newcommand{\sailRISCVfnGetMinterruptsSSI}{\saildoclabelled{sailRISCVfnzzygetzyMinterruptszySSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_minterrupts_ssi8ebb8da6cffaa81a169231cdfe86edca.tex}}}} + +\newcommand{\sailRISCVvalSetMinterruptsSSI}{\saildoclabelled{sailRISCVzzysetzyMinterruptszySSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_minterrupts_ssi862fdaa740d3553d0b00abbad005b654.tex}}}} + +\newcommand{\sailRISCVfnSetMinterruptsSSI}{\saildoclabelled{sailRISCVfnzzysetzyMinterruptszySSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_minterrupts_ssi862fdaa740d3553d0b00abbad005b654.tex}}}} + +\newcommand{\sailRISCVvalUpdateMinterruptsSSI}{\saildoclabelled{sailRISCVzzyupdatezyMinterruptszySSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_minterrupts_ssid8971c54b6d3c79de9fcf8f4e40c9bff.tex}}}} + +\newcommand{\sailRISCVfnUpdateMinterruptsSSI}{\saildoclabelled{sailRISCVfnzzyupdatezyMinterruptszySSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_minterrupts_ssid8971c54b6d3c79de9fcf8f4e40c9bff.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLLLLupdateSSI}{\saildoclabelled{sailRISCVoverloadLLLLLLLzupdatezySSI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLLLLzupdate_ssi5471fd96e5b7a8471f1ef66b598501a9.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMMMMModSSI}{\saildoclabelled{sailRISCVoverloadMMMMMMMzzymodzySSI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMMMMz_mod_ssicb14ae48c26ad162228aa44069530c95.tex}}}} + +\newcommand{\sailRISCVvalGetMinterruptsUSI}{\saildoclabelled{sailRISCVzzygetzyMinterruptszyUSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_minterrupts_usi01d28f9f2001eba94bf8de985b2cc8cd.tex}}}} + +\newcommand{\sailRISCVfnGetMinterruptsUSI}{\saildoclabelled{sailRISCVfnzzygetzyMinterruptszyUSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_minterrupts_usi01d28f9f2001eba94bf8de985b2cc8cd.tex}}}} + +\newcommand{\sailRISCVvalSetMinterruptsUSI}{\saildoclabelled{sailRISCVzzysetzyMinterruptszyUSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_minterrupts_usi073c76e1d0b95c4329e14eefe61bddb2.tex}}}} + +\newcommand{\sailRISCVfnSetMinterruptsUSI}{\saildoclabelled{sailRISCVfnzzysetzyMinterruptszyUSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_minterrupts_usi073c76e1d0b95c4329e14eefe61bddb2.tex}}}} + +\newcommand{\sailRISCVvalUpdateMinterruptsUSI}{\saildoclabelled{sailRISCVzzyupdatezyMinterruptszyUSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_minterrupts_usi77886994f9fcf884ac05c59c57948f29.tex}}}} + +\newcommand{\sailRISCVfnUpdateMinterruptsUSI}{\saildoclabelled{sailRISCVfnzzyupdatezyMinterruptszyUSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_minterrupts_usi77886994f9fcf884ac05c59c57948f29.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNNNNupdateUSI}{\saildoclabelled{sailRISCVoverloadNNNNNNNzupdatezyUSI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNNNNzupdate_usi3c691c58ab628cbd10b9e21b62e0cfc4.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOOOOModUSI}{\saildoclabelled{sailRISCVoverloadOOOOOOOzzymodzyUSI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOOOOz_mod_usif3c3aecb7417cc350ad372adfb40e4d3.tex}}}} + +\newcommand{\sailRISCVvallegalizzeMip}{\saildoclabelled{sailRISCVzlegalizzezymip}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_mip6b35097c942aa7a4220cfbae774dd473.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeMip}{\saildoclabelled{sailRISCVfnzlegalizzezymip}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_mip6b35097c942aa7a4220cfbae774dd473.tex}}}} + +\newcommand{\sailRISCVvallegalizzeMie}{\saildoclabelled{sailRISCVzlegalizzezymie}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_miea3d44a6b9220a2e1cbd134912a2b63af.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeMie}{\saildoclabelled{sailRISCVfnzlegalizzezymie}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_miea3d44a6b9220a2e1cbd134912a2b63af.tex}}}} + +\newcommand{\sailRISCVvallegalizzeMideleg}{\saildoclabelled{sailRISCVzlegalizzezymideleg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_mideleg301fb79c822ffefd5b20e289875da3e4.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeMideleg}{\saildoclabelled{sailRISCVfnzlegalizzezymideleg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_mideleg301fb79c822ffefd5b20e289875da3e4.tex}}}} + +\newcommand{\sailRISCVtypeMedeleg}{\saildoclabelled{sailRISCVtypezMedeleg}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezmedeleg2ea875f42b3c32731b094792df4272ce.tex}}}} + +\newcommand{\sailRISCVvalMkMedeleg}{\saildoclabelled{sailRISCVzMkzyMedeleg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_medeleg3829c83ea6bb677825f964507254a95c.tex}}}} + +\newcommand{\sailRISCVfnMkMedeleg}{\saildoclabelled{sailRISCVfnzMkzyMedeleg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_medeleg3829c83ea6bb677825f964507254a95c.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegBits}{\saildoclabelled{sailRISCVzzygetzyMedelegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_bits254afc4d0ea5cd20737b995ecb86af96.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegBits}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_bits254afc4d0ea5cd20737b995ecb86af96.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegBits}{\saildoclabelled{sailRISCVzzysetzyMedelegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_bitsa5164a346cdd02dcec13d6e5c2839918.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegBits}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_bitsa5164a346cdd02dcec13d6e5c2839918.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegBits}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_bitsf3dc3e6f3f131d1cc6e32b1c37c8cdde.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegBits}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_bitsf3dc3e6f3f131d1cc6e32b1c37c8cdde.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPPPPupdateBits}{\saildoclabelled{sailRISCVoverloadPPPPPPPzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPPPPzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQQQQModBits}{\saildoclabelled{sailRISCVoverloadQQQQQQQzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQQQQz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegSAMOPageFault}{\saildoclabelled{sailRISCVzzygetzyMedelegzySAMOzyPagezyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_samo_page_fault02d4e5d413504e150668b23d70f40d9c.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegSAMOPageFault}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzySAMOzyPagezyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_samo_page_fault02d4e5d413504e150668b23d70f40d9c.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegSAMOPageFault}{\saildoclabelled{sailRISCVzzysetzyMedelegzySAMOzyPagezyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_samo_page_fault3b09cdf77cb2b2817f7c0f833cc758ce.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegSAMOPageFault}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzySAMOzyPagezyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_samo_page_fault3b09cdf77cb2b2817f7c0f833cc758ce.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegSAMOPageFault}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzySAMOzyPagezyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_samo_page_fault0f5a6e51d39c262ed16dd03fd0f6fd33.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegSAMOPageFault}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzySAMOzyPagezyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_samo_page_fault0f5a6e51d39c262ed16dd03fd0f6fd33.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRRRRupdateSAMOPageFault}{\saildoclabelled{sailRISCVoverloadRRRRRRRzupdatezySAMOzyPagezyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRRRRzupdate_samo_page_fault0e0044848164a2453737385b443e2a1d.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSSSSModSAMOPageFault}{\saildoclabelled{sailRISCVoverloadSSSSSSSzzymodzySAMOzyPagezyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSSSSz_mod_samo_page_fault43d7b42a58e066e14279c19346f8aa6e.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegLoadPageFault}{\saildoclabelled{sailRISCVzzygetzyMedelegzyLoadzyPagezyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_load_page_faultcad65281f15a01bca2163ece7e5c6ca2.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegLoadPageFault}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzyLoadzyPagezyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_load_page_faultcad65281f15a01bca2163ece7e5c6ca2.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegLoadPageFault}{\saildoclabelled{sailRISCVzzysetzyMedelegzyLoadzyPagezyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_load_page_fault9d4748d81d2b444605a3e9cebc4943d7.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegLoadPageFault}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzyLoadzyPagezyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_load_page_fault9d4748d81d2b444605a3e9cebc4943d7.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegLoadPageFault}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzyLoadzyPagezyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_load_page_faultf06c6ed3cf5f5fb5c53b68b1755f26be.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegLoadPageFault}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzyLoadzyPagezyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_load_page_faultf06c6ed3cf5f5fb5c53b68b1755f26be.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTTTTupdateLoadPageFault}{\saildoclabelled{sailRISCVoverloadTTTTTTTzupdatezyLoadzyPagezyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTTTTzupdate_load_page_faultf0e55e39dc6672c621900ae1f5aaf5c8.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUUUUModLoadPageFault}{\saildoclabelled{sailRISCVoverloadUUUUUUUzzymodzyLoadzyPagezyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUUUUz_mod_load_page_fault57094f7526c1aa35d9aef0746403aba6.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegFetchPageFault}{\saildoclabelled{sailRISCVzzygetzyMedelegzyFetchzyPagezyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_fetch_page_fault584acc3a0e750181acc1bdc03c42b15c.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegFetchPageFault}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzyFetchzyPagezyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_fetch_page_fault584acc3a0e750181acc1bdc03c42b15c.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegFetchPageFault}{\saildoclabelled{sailRISCVzzysetzyMedelegzyFetchzyPagezyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_fetch_page_faultefe8fe08b8ed5f78322e6a4864364068.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegFetchPageFault}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzyFetchzyPagezyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_fetch_page_faultefe8fe08b8ed5f78322e6a4864364068.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegFetchPageFault}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzyFetchzyPagezyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_fetch_page_faulta2bc84a2cd9018bb44ab5c81423ca187.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegFetchPageFault}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzyFetchzyPagezyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_fetch_page_faulta2bc84a2cd9018bb44ab5c81423ca187.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVVVVupdateFetchPageFault}{\saildoclabelled{sailRISCVoverloadVVVVVVVzupdatezyFetchzyPagezyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVVVVzupdate_fetch_page_fault5db4cf0b8a31dd60d34e3f4575579bf6.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWWWWModFetchPageFault}{\saildoclabelled{sailRISCVoverloadWWWWWWWzzymodzyFetchzyPagezyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWWWWz_mod_fetch_page_faulta754353f965dceb2b48b5c02d38fb070.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegMEnvCall}{\saildoclabelled{sailRISCVzzygetzyMedelegzyMEnvCall}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_menvcalla548a3bce22dd9330ba9f237e8ccd8df.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegMEnvCall}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzyMEnvCall}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_menvcalla548a3bce22dd9330ba9f237e8ccd8df.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegMEnvCall}{\saildoclabelled{sailRISCVzzysetzyMedelegzyMEnvCall}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_menvcall1e30100a01455a75d7aaa14d1ba8b171.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegMEnvCall}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzyMEnvCall}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_menvcall1e30100a01455a75d7aaa14d1ba8b171.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegMEnvCall}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzyMEnvCall}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_menvcall2d8b71da00a8a28b5fb607a33f36612f.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegMEnvCall}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzyMEnvCall}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_menvcall2d8b71da00a8a28b5fb607a33f36612f.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXXXXupdateMEnvCall}{\saildoclabelled{sailRISCVoverloadXXXXXXXzupdatezyMEnvCall}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXXXXzupdate_menvcall5801f983231805c1edca0da644dd7884.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYYYYModMEnvCall}{\saildoclabelled{sailRISCVoverloadYYYYYYYzzymodzyMEnvCall}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYYYYz_mod_menvcall76e08341162761e8373fc048ddccb8c9.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegSEnvCall}{\saildoclabelled{sailRISCVzzygetzyMedelegzySEnvCall}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_senvcall3e8e2ef741b16b80e855ffb13f17850d.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegSEnvCall}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzySEnvCall}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_senvcall3e8e2ef741b16b80e855ffb13f17850d.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegSEnvCall}{\saildoclabelled{sailRISCVzzysetzyMedelegzySEnvCall}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_senvcall9eab904bcf0e2130341264216cb52176.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegSEnvCall}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzySEnvCall}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_senvcall9eab904bcf0e2130341264216cb52176.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegSEnvCall}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzySEnvCall}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_senvcalld3587b88d31060a18775842e14fa2e28.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegSEnvCall}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzySEnvCall}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_senvcalld3587b88d31060a18775842e14fa2e28.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZZZZupdateSEnvCall}{\saildoclabelled{sailRISCVoverloadZZZZZZZzupdatezySEnvCall}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZZZZzupdate_senvcall3c3a7a2242c90957bc2c31d37c79e50a.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAAAAModSEnvCall}{\saildoclabelled{sailRISCVoverloadAAAAAAAAzzymodzySEnvCall}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAAAAz_mod_senvcall87d5357e73e0d0d061971d3b4ae4f615.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegUEnvCall}{\saildoclabelled{sailRISCVzzygetzyMedelegzyUEnvCall}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_uenvcallc38700f20f282265abd49a682cb3711d.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegUEnvCall}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzyUEnvCall}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_uenvcallc38700f20f282265abd49a682cb3711d.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegUEnvCall}{\saildoclabelled{sailRISCVzzysetzyMedelegzyUEnvCall}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_uenvcallb8f205a15af52cac02b9bb0657a52d33.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegUEnvCall}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzyUEnvCall}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_uenvcallb8f205a15af52cac02b9bb0657a52d33.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegUEnvCall}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzyUEnvCall}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_uenvcalle92cde6b912da5ac5a47cd901345bbf9.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegUEnvCall}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzyUEnvCall}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_uenvcalle92cde6b912da5ac5a47cd901345bbf9.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBBBBupdateUEnvCall}{\saildoclabelled{sailRISCVoverloadBBBBBBBBzupdatezyUEnvCall}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBBBBzupdate_uenvcall1a8e9c082fb9f272d5370bee121f426d.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCCCCModUEnvCall}{\saildoclabelled{sailRISCVoverloadCCCCCCCCzzymodzyUEnvCall}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCCCCz_mod_uenvcall837e3a85bd98d15f2f4b32f9230ddef6.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegSAMOAccessFault}{\saildoclabelled{sailRISCVzzygetzyMedelegzySAMOzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_samo_access_faultcb72d93dea2bae751976faa859f64fa9.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegSAMOAccessFault}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzySAMOzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_samo_access_faultcb72d93dea2bae751976faa859f64fa9.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegSAMOAccessFault}{\saildoclabelled{sailRISCVzzysetzyMedelegzySAMOzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_samo_access_fault1dfec566f185ab6cce1059f544290cf1.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegSAMOAccessFault}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzySAMOzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_samo_access_fault1dfec566f185ab6cce1059f544290cf1.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegSAMOAccessFault}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzySAMOzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_samo_access_fault6974daf13df1fa6adbf6f8461fbb31e1.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegSAMOAccessFault}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzySAMOzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_samo_access_fault6974daf13df1fa6adbf6f8461fbb31e1.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDDDDDupdateSAMOAccessFault}{\saildoclabelled{sailRISCVoverloadDDDDDDDDzupdatezySAMOzyAccesszyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDDDDDzupdate_samo_access_faulte622f01b5ab60ce658092d165d64a4f9.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEEEEEModSAMOAccessFault}{\saildoclabelled{sailRISCVoverloadEEEEEEEEzzymodzySAMOzyAccesszyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEEEEEz_mod_samo_access_faultef1cf7b1db2bf21d4e773b1a41ea8eea.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegSAMOAddrAlign}{\saildoclabelled{sailRISCVzzygetzyMedelegzySAMOzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_samo_addr_alignad215ca9df0deef97bdff6842d7f4cb9.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegSAMOAddrAlign}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzySAMOzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_samo_addr_alignad215ca9df0deef97bdff6842d7f4cb9.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegSAMOAddrAlign}{\saildoclabelled{sailRISCVzzysetzyMedelegzySAMOzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_samo_addr_align00c5e4839832dee86f8bfd26cc3f2a80.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegSAMOAddrAlign}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzySAMOzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_samo_addr_align00c5e4839832dee86f8bfd26cc3f2a80.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegSAMOAddrAlign}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzySAMOzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_samo_addr_alignfbf844afddf59029f1bfa6e7730e572d.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegSAMOAddrAlign}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzySAMOzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_samo_addr_alignfbf844afddf59029f1bfa6e7730e572d.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFFFFFupdateSAMOAddrAlign}{\saildoclabelled{sailRISCVoverloadFFFFFFFFzupdatezySAMOzyAddrzyAlign}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFFFFFzupdate_samo_addr_alignb6f17cfe030aff1cf9413eeaa67b67ee.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGGGGGModSAMOAddrAlign}{\saildoclabelled{sailRISCVoverloadGGGGGGGGzzymodzySAMOzyAddrzyAlign}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGGGGGz_mod_samo_addr_align71af067f49a8b506587ec718a5e1b7d2.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegLoadAccessFault}{\saildoclabelled{sailRISCVzzygetzyMedelegzyLoadzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_load_access_fault83f8e20712f80aab31a1decf153c8956.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegLoadAccessFault}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzyLoadzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_load_access_fault83f8e20712f80aab31a1decf153c8956.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegLoadAccessFault}{\saildoclabelled{sailRISCVzzysetzyMedelegzyLoadzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_load_access_fault6e32b99197543196d68c443430ddcd76.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegLoadAccessFault}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzyLoadzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_load_access_fault6e32b99197543196d68c443430ddcd76.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegLoadAccessFault}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzyLoadzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_load_access_faultf83e5fdaf6895717efc1bb0820a40bcc.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegLoadAccessFault}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzyLoadzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_load_access_faultf83e5fdaf6895717efc1bb0820a40bcc.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHHHHHupdateLoadAccessFault}{\saildoclabelled{sailRISCVoverloadHHHHHHHHzupdatezyLoadzyAccesszyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHHHHHzupdate_load_access_faultcc580699ff14ff7930c001851a1463b8.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIIIIIModLoadAccessFault}{\saildoclabelled{sailRISCVoverloadIIIIIIIIzzymodzyLoadzyAccesszyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIIIIIz_mod_load_access_fault185ee80ec13fa3fdeb7c2cd3a76688c9.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegLoadAddrAlign}{\saildoclabelled{sailRISCVzzygetzyMedelegzyLoadzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_load_addr_alignb78e674217d39981dc173fc694981c59.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegLoadAddrAlign}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzyLoadzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_load_addr_alignb78e674217d39981dc173fc694981c59.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegLoadAddrAlign}{\saildoclabelled{sailRISCVzzysetzyMedelegzyLoadzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_load_addr_align477e12d39eacad577451a2c4ce6c5028.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegLoadAddrAlign}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzyLoadzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_load_addr_align477e12d39eacad577451a2c4ce6c5028.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegLoadAddrAlign}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzyLoadzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_load_addr_alignae797c478ddd9ca50ad25f75c4177b59.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegLoadAddrAlign}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzyLoadzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_load_addr_alignae797c478ddd9ca50ad25f75c4177b59.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJJJJJupdateLoadAddrAlign}{\saildoclabelled{sailRISCVoverloadJJJJJJJJzupdatezyLoadzyAddrzyAlign}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJJJJJzupdate_load_addr_aligna304d90cb1ef10e79624a3324854bad0.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKKKKKModLoadAddrAlign}{\saildoclabelled{sailRISCVoverloadKKKKKKKKzzymodzyLoadzyAddrzyAlign}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKKKKKz_mod_load_addr_align34e982fd800fd67969b64a5932439781.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegBreakpoint}{\saildoclabelled{sailRISCVzzygetzyMedelegzyBreakpoint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_breakpointd7558e491e73df703b5f48b45fc459fb.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegBreakpoint}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzyBreakpoint}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_breakpointd7558e491e73df703b5f48b45fc459fb.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegBreakpoint}{\saildoclabelled{sailRISCVzzysetzyMedelegzyBreakpoint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_breakpoint65522090d2dce601562eb82bb71ebd27.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegBreakpoint}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzyBreakpoint}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_breakpoint65522090d2dce601562eb82bb71ebd27.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegBreakpoint}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzyBreakpoint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_breakpointbd84cf9145e5e18dc467f4a838f67957.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegBreakpoint}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzyBreakpoint}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_breakpointbd84cf9145e5e18dc467f4a838f67957.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLLLLLupdateBreakpoint}{\saildoclabelled{sailRISCVoverloadLLLLLLLLzupdatezyBreakpoint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLLLLLzupdate_breakpoint560b5628b33be91263dd76c1c88c6a06.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMMMMMModBreakpoint}{\saildoclabelled{sailRISCVoverloadMMMMMMMMzzymodzyBreakpoint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMMMMMz_mod_breakpointfb455863fb6768bbcbc1b984dbef6360.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegIllegalInstr}{\saildoclabelled{sailRISCVzzygetzyMedelegzyIllegalzyInstr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_illegal_instre418e5763eb05a3ffb4d6c978a1e3ff3.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegIllegalInstr}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzyIllegalzyInstr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_illegal_instre418e5763eb05a3ffb4d6c978a1e3ff3.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegIllegalInstr}{\saildoclabelled{sailRISCVzzysetzyMedelegzyIllegalzyInstr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_illegal_instr0ddff62c362ec255b511a781fc6e9551.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegIllegalInstr}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzyIllegalzyInstr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_illegal_instr0ddff62c362ec255b511a781fc6e9551.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegIllegalInstr}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzyIllegalzyInstr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_illegal_instr1f275bdf5831e7748612e30e7fc1ce66.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegIllegalInstr}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzyIllegalzyInstr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_illegal_instr1f275bdf5831e7748612e30e7fc1ce66.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNNNNNupdateIllegalInstr}{\saildoclabelled{sailRISCVoverloadNNNNNNNNzupdatezyIllegalzyInstr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNNNNNzupdate_illegal_instr455fc8a1f0aa354556519de0f7b2c27b.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOOOOOModIllegalInstr}{\saildoclabelled{sailRISCVoverloadOOOOOOOOzzymodzyIllegalzyInstr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOOOOOz_mod_illegal_instr52b43b228c609c9c311d02dfb920b702.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegFetchAccessFault}{\saildoclabelled{sailRISCVzzygetzyMedelegzyFetchzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_fetch_access_faulte776b2e2dd4e9f7381bf51e711dd1a07.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegFetchAccessFault}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzyFetchzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_fetch_access_faulte776b2e2dd4e9f7381bf51e711dd1a07.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegFetchAccessFault}{\saildoclabelled{sailRISCVzzysetzyMedelegzyFetchzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_fetch_access_fault8b3d91a41393ae3c76d0df3e801928e9.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegFetchAccessFault}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzyFetchzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_fetch_access_fault8b3d91a41393ae3c76d0df3e801928e9.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegFetchAccessFault}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzyFetchzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_fetch_access_fault31fef2dab7b4fcdd2b8d5a549f3df1ee.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegFetchAccessFault}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzyFetchzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_fetch_access_fault31fef2dab7b4fcdd2b8d5a549f3df1ee.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPPPPPupdateFetchAccessFault}{\saildoclabelled{sailRISCVoverloadPPPPPPPPzupdatezyFetchzyAccesszyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPPPPPzupdate_fetch_access_faultf6d3ea38a5b206db76f3d15e6b293e4e.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQQQQQModFetchAccessFault}{\saildoclabelled{sailRISCVoverloadQQQQQQQQzzymodzyFetchzyAccesszyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQQQQQz_mod_fetch_access_fault2d0b00483619a1a634b37492d7e87b39.tex}}}} + +\newcommand{\sailRISCVvalGetMedelegFetchAddrAlign}{\saildoclabelled{sailRISCVzzygetzyMedelegzyFetchzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_medeleg_fetch_addr_aligncd9c88ba625264505b33ace3265d8ea5.tex}}}} + +\newcommand{\sailRISCVfnGetMedelegFetchAddrAlign}{\saildoclabelled{sailRISCVfnzzygetzyMedelegzyFetchzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_medeleg_fetch_addr_aligncd9c88ba625264505b33ace3265d8ea5.tex}}}} + +\newcommand{\sailRISCVvalSetMedelegFetchAddrAlign}{\saildoclabelled{sailRISCVzzysetzyMedelegzyFetchzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_medeleg_fetch_addr_align514673a27e7f896be9dea81dc7662148.tex}}}} + +\newcommand{\sailRISCVfnSetMedelegFetchAddrAlign}{\saildoclabelled{sailRISCVfnzzysetzyMedelegzyFetchzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_medeleg_fetch_addr_align514673a27e7f896be9dea81dc7662148.tex}}}} + +\newcommand{\sailRISCVvalUpdateMedelegFetchAddrAlign}{\saildoclabelled{sailRISCVzzyupdatezyMedelegzyFetchzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_medeleg_fetch_addr_aligna193083f9170990caf0b815723cfe4f5.tex}}}} + +\newcommand{\sailRISCVfnUpdateMedelegFetchAddrAlign}{\saildoclabelled{sailRISCVfnzzyupdatezyMedelegzyFetchzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_medeleg_fetch_addr_aligna193083f9170990caf0b815723cfe4f5.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRRRRRupdateFetchAddrAlign}{\saildoclabelled{sailRISCVoverloadRRRRRRRRzupdatezyFetchzyAddrzyAlign}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRRRRRzupdate_fetch_addr_aligned5113ea584423e01fcb4b2781a3aeab.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSSSSSModFetchAddrAlign}{\saildoclabelled{sailRISCVoverloadSSSSSSSSzzymodzyFetchzyAddrzyAlign}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSSSSSz_mod_fetch_addr_align94e1ec62c225ae16e8fbc401efa25352.tex}}}} + +\newcommand{\sailRISCVvallegalizzeMedeleg}{\saildoclabelled{sailRISCVzlegalizzezymedeleg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_medeleg4472d564e1553d1bbac6c6cbaeff95c9.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeMedeleg}{\saildoclabelled{sailRISCVfnzlegalizzezymedeleg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_medeleg4472d564e1553d1bbac6c6cbaeff95c9.tex}}}} + +\newcommand{\sailRISCVtypeMtvec}{\saildoclabelled{sailRISCVtypezMtvec}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezmtvec31778e1eff09235941858a1d4774e45c.tex}}}} + +\newcommand{\sailRISCVvalMkMtvec}{\saildoclabelled{sailRISCVzMkzyMtvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_mtvec60ead547a4a385f88360115e550b4ab2.tex}}}} + +\newcommand{\sailRISCVfnMkMtvec}{\saildoclabelled{sailRISCVfnzMkzyMtvec}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_mtvec60ead547a4a385f88360115e550b4ab2.tex}}}} + +\newcommand{\sailRISCVvalGetMtvecBits}{\saildoclabelled{sailRISCVzzygetzyMtveczybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mtvec_bitse609b5bdda2049f1b86a85566415ea34.tex}}}} + +\newcommand{\sailRISCVfnGetMtvecBits}{\saildoclabelled{sailRISCVfnzzygetzyMtveczybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mtvec_bitse609b5bdda2049f1b86a85566415ea34.tex}}}} + +\newcommand{\sailRISCVvalSetMtvecBits}{\saildoclabelled{sailRISCVzzysetzyMtveczybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mtvec_bitsbae28d0fb32e4a35886c4c0190acdeb8.tex}}}} + +\newcommand{\sailRISCVfnSetMtvecBits}{\saildoclabelled{sailRISCVfnzzysetzyMtveczybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mtvec_bitsbae28d0fb32e4a35886c4c0190acdeb8.tex}}}} + +\newcommand{\sailRISCVvalUpdateMtvecBits}{\saildoclabelled{sailRISCVzzyupdatezyMtveczybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mtvec_bits158581c836e4cf68e74f750598d54083.tex}}}} + +\newcommand{\sailRISCVfnUpdateMtvecBits}{\saildoclabelled{sailRISCVfnzzyupdatezyMtveczybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mtvec_bits158581c836e4cf68e74f750598d54083.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTTTTTupdateBits}{\saildoclabelled{sailRISCVoverloadTTTTTTTTzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTTTTTzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUUUUUModBits}{\saildoclabelled{sailRISCVoverloadUUUUUUUUzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUUUUUz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetMtvecBase}{\saildoclabelled{sailRISCVzzygetzyMtveczyBase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mtvec_basefad37a1b29dd19f0e36c4f4c971339ee.tex}}}} + +\newcommand{\sailRISCVfnGetMtvecBase}{\saildoclabelled{sailRISCVfnzzygetzyMtveczyBase}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mtvec_basefad37a1b29dd19f0e36c4f4c971339ee.tex}}}} + +\newcommand{\sailRISCVvalSetMtvecBase}{\saildoclabelled{sailRISCVzzysetzyMtveczyBase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mtvec_base86e6903a9eebeb1822f298249988800a.tex}}}} + +\newcommand{\sailRISCVfnSetMtvecBase}{\saildoclabelled{sailRISCVfnzzysetzyMtveczyBase}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mtvec_base86e6903a9eebeb1822f298249988800a.tex}}}} + +\newcommand{\sailRISCVvalUpdateMtvecBase}{\saildoclabelled{sailRISCVzzyupdatezyMtveczyBase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mtvec_base2276531f23752a05146b70a788934e75.tex}}}} + +\newcommand{\sailRISCVfnUpdateMtvecBase}{\saildoclabelled{sailRISCVfnzzyupdatezyMtveczyBase}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mtvec_base2276531f23752a05146b70a788934e75.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVVVVVupdateBase}{\saildoclabelled{sailRISCVoverloadVVVVVVVVzupdatezyBase}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVVVVVzupdate_basef3805d7e016e708f5f63a87f731f0265.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWWWWWModBase}{\saildoclabelled{sailRISCVoverloadWWWWWWWWzzymodzyBase}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWWWWWz_mod_base4044bc65e2dc6a7a9071ee2819432775.tex}}}} + +\newcommand{\sailRISCVvalGetMtvecMode}{\saildoclabelled{sailRISCVzzygetzyMtveczyMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mtvec_modeac4fc90b9c4014235eab8096eeec86f0.tex}}}} + +\newcommand{\sailRISCVfnGetMtvecMode}{\saildoclabelled{sailRISCVfnzzygetzyMtveczyMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mtvec_modeac4fc90b9c4014235eab8096eeec86f0.tex}}}} + +\newcommand{\sailRISCVvalSetMtvecMode}{\saildoclabelled{sailRISCVzzysetzyMtveczyMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mtvec_mode83a05e7666364d3e4e87f1aedc208023.tex}}}} + +\newcommand{\sailRISCVfnSetMtvecMode}{\saildoclabelled{sailRISCVfnzzysetzyMtveczyMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mtvec_mode83a05e7666364d3e4e87f1aedc208023.tex}}}} + +\newcommand{\sailRISCVvalUpdateMtvecMode}{\saildoclabelled{sailRISCVzzyupdatezyMtveczyMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mtvec_moded92fe8c6eb43d3e69a83d0a2b060e3a2.tex}}}} + +\newcommand{\sailRISCVfnUpdateMtvecMode}{\saildoclabelled{sailRISCVfnzzyupdatezyMtveczyMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mtvec_moded92fe8c6eb43d3e69a83d0a2b060e3a2.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXXXXXupdateMode}{\saildoclabelled{sailRISCVoverloadXXXXXXXXzupdatezyMode}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXXXXXzupdate_modea8b179bc2887fad34e9a3f8cefc9cf29.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYYYYYModMode}{\saildoclabelled{sailRISCVoverloadYYYYYYYYzzymodzyMode}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYYYYYz_mod_mode7dda808a114a5634018c73fc24f43140.tex}}}} + +\newcommand{\sailRISCVvallegalizzeTvec}{\saildoclabelled{sailRISCVzlegalizzezytvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_tvec4a108f656cfc40d55dcc9e2cd9614e5c.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeTvec}{\saildoclabelled{sailRISCVfnzlegalizzezytvec}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_tvec4a108f656cfc40d55dcc9e2cd9614e5c.tex}}}} + +\newcommand{\sailRISCVtypeMcause}{\saildoclabelled{sailRISCVtypezMcause}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezmcausea662f8fdb3c01a6efcbdc5abf35af73e.tex}}}} + +\newcommand{\sailRISCVvalMkMcause}{\saildoclabelled{sailRISCVzMkzyMcause}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_mcause0c621c96c15db1b801688d6c698bfddd.tex}}}} + +\newcommand{\sailRISCVfnMkMcause}{\saildoclabelled{sailRISCVfnzMkzyMcause}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_mcause0c621c96c15db1b801688d6c698bfddd.tex}}}} + +\newcommand{\sailRISCVvalGetMcauseBits}{\saildoclabelled{sailRISCVzzygetzyMcausezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mcause_bits74f8f43c07e2abaa1ac3d45b4a2b6ba2.tex}}}} + +\newcommand{\sailRISCVfnGetMcauseBits}{\saildoclabelled{sailRISCVfnzzygetzyMcausezybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mcause_bits74f8f43c07e2abaa1ac3d45b4a2b6ba2.tex}}}} + +\newcommand{\sailRISCVvalSetMcauseBits}{\saildoclabelled{sailRISCVzzysetzyMcausezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mcause_bits80b6d4b61ba8cd659ac54309cbdb9ea7.tex}}}} + +\newcommand{\sailRISCVfnSetMcauseBits}{\saildoclabelled{sailRISCVfnzzysetzyMcausezybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mcause_bits80b6d4b61ba8cd659ac54309cbdb9ea7.tex}}}} + +\newcommand{\sailRISCVvalUpdateMcauseBits}{\saildoclabelled{sailRISCVzzyupdatezyMcausezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mcause_bitsf7e305192beebf30554f7e43f12ae4ed.tex}}}} + +\newcommand{\sailRISCVfnUpdateMcauseBits}{\saildoclabelled{sailRISCVfnzzyupdatezyMcausezybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mcause_bitsf7e305192beebf30554f7e43f12ae4ed.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZZZZZupdateBits}{\saildoclabelled{sailRISCVoverloadZZZZZZZZzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZZZZZzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAAAAAModBits}{\saildoclabelled{sailRISCVoverloadAAAAAAAAAzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAAAAAz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetMcauseIsInterrupt}{\saildoclabelled{sailRISCVzzygetzyMcausezyIsInterrupt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mcause_isinterruptca4d348b8a2eaccd2e92f7ee7d03bee7.tex}}}} + +\newcommand{\sailRISCVfnGetMcauseIsInterrupt}{\saildoclabelled{sailRISCVfnzzygetzyMcausezyIsInterrupt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mcause_isinterruptca4d348b8a2eaccd2e92f7ee7d03bee7.tex}}}} + +\newcommand{\sailRISCVvalSetMcauseIsInterrupt}{\saildoclabelled{sailRISCVzzysetzyMcausezyIsInterrupt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mcause_isinterrupt6acecb43461e553536ef76a71d78c3e7.tex}}}} + +\newcommand{\sailRISCVfnSetMcauseIsInterrupt}{\saildoclabelled{sailRISCVfnzzysetzyMcausezyIsInterrupt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mcause_isinterrupt6acecb43461e553536ef76a71d78c3e7.tex}}}} + +\newcommand{\sailRISCVvalUpdateMcauseIsInterrupt}{\saildoclabelled{sailRISCVzzyupdatezyMcausezyIsInterrupt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mcause_isinterrupt642fe02b577ce4d39155750b612ad77c.tex}}}} + +\newcommand{\sailRISCVfnUpdateMcauseIsInterrupt}{\saildoclabelled{sailRISCVfnzzyupdatezyMcausezyIsInterrupt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mcause_isinterrupt642fe02b577ce4d39155750b612ad77c.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBBBBBupdateIsInterrupt}{\saildoclabelled{sailRISCVoverloadBBBBBBBBBzupdatezyIsInterrupt}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBBBBBzupdate_isinterrupt7cba1e6a14631a642becc8e33e0de341.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCCCCCModIsInterrupt}{\saildoclabelled{sailRISCVoverloadCCCCCCCCCzzymodzyIsInterrupt}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCCCCCz_mod_isinterrupt2bb38c1a3ef90daa70a3b0957628b7d4.tex}}}} + +\newcommand{\sailRISCVvalGetMcauseCause}{\saildoclabelled{sailRISCVzzygetzyMcausezyCause}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_mcause_cause1bdd5398cd23fc4b4f8215c110954e19.tex}}}} + +\newcommand{\sailRISCVfnGetMcauseCause}{\saildoclabelled{sailRISCVfnzzygetzyMcausezyCause}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_mcause_cause1bdd5398cd23fc4b4f8215c110954e19.tex}}}} + +\newcommand{\sailRISCVvalSetMcauseCause}{\saildoclabelled{sailRISCVzzysetzyMcausezyCause}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_mcause_causecce7178eb6a826303b904fd987904cff.tex}}}} + +\newcommand{\sailRISCVfnSetMcauseCause}{\saildoclabelled{sailRISCVfnzzysetzyMcausezyCause}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_mcause_causecce7178eb6a826303b904fd987904cff.tex}}}} + +\newcommand{\sailRISCVvalUpdateMcauseCause}{\saildoclabelled{sailRISCVzzyupdatezyMcausezyCause}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_mcause_cause36f08972c0051221257ac44d915e866d.tex}}}} + +\newcommand{\sailRISCVfnUpdateMcauseCause}{\saildoclabelled{sailRISCVfnzzyupdatezyMcausezyCause}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_mcause_cause36f08972c0051221257ac44d915e866d.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDDDDDDupdateCause}{\saildoclabelled{sailRISCVoverloadDDDDDDDDDzupdatezyCause}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDDDDDDzupdate_cause0e0260fdee4fbd12d08cac973b1bc938.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEEEEEEModCause}{\saildoclabelled{sailRISCVoverloadEEEEEEEEEzzymodzyCause}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEEEEEEz_mod_cause6fb7970fc86ee1af49227b574ab5c281.tex}}}} + +\newcommand{\sailRISCVvaltvecAddr}{\saildoclabelled{sailRISCVztveczyaddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztvec_addrc6c52b287eacbc1aca798406d1b08576.tex}}}} + +\newcommand{\sailRISCVfntvecAddr}{\saildoclabelled{sailRISCVfnztveczyaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztvec_addrc6c52b287eacbc1aca798406d1b08576.tex}}}} + +\newcommand{\sailRISCVvallegalizzeXepc}{\saildoclabelled{sailRISCVzlegalizzezyxepc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_xepc8416dd9133f6232df0898ca0ae2784c2.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeXepc}{\saildoclabelled{sailRISCVfnzlegalizzezyxepc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_xepc8416dd9133f6232df0898ca0ae2784c2.tex}}}} + +\newcommand{\sailRISCVvalpcAlignmentMask}{\saildoclabelled{sailRISCVzpczyalignmentzymask}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpc_alignment_mask1943267c124397815476842d08d3901e.tex}}}} + +\newcommand{\sailRISCVfnpcAlignmentMask}{\saildoclabelled{sailRISCVfnzpczyalignmentzymask}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpc_alignment_mask1943267c124397815476842d08d3901e.tex}}}} + +\newcommand{\sailRISCVtypeCounteren}{\saildoclabelled{sailRISCVtypezCounteren}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcounteren79441db7eb726d320a01493bb921db0e.tex}}}} + +\newcommand{\sailRISCVvalMkCounteren}{\saildoclabelled{sailRISCVzMkzyCounteren}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_counterenf15701a312ca5765a184f9c5e5a93c32.tex}}}} + +\newcommand{\sailRISCVfnMkCounteren}{\saildoclabelled{sailRISCVfnzMkzyCounteren}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_counterenf15701a312ca5765a184f9c5e5a93c32.tex}}}} + +\newcommand{\sailRISCVvalGetCounterenBits}{\saildoclabelled{sailRISCVzzygetzyCounterenzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_counteren_bits63485ab688d4675e7f4e8ef14d9606ff.tex}}}} + +\newcommand{\sailRISCVfnGetCounterenBits}{\saildoclabelled{sailRISCVfnzzygetzyCounterenzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_counteren_bits63485ab688d4675e7f4e8ef14d9606ff.tex}}}} + +\newcommand{\sailRISCVvalSetCounterenBits}{\saildoclabelled{sailRISCVzzysetzyCounterenzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_counteren_bits645facfec852be9a4b81ed364e1460c2.tex}}}} + +\newcommand{\sailRISCVfnSetCounterenBits}{\saildoclabelled{sailRISCVfnzzysetzyCounterenzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_counteren_bits645facfec852be9a4b81ed364e1460c2.tex}}}} + +\newcommand{\sailRISCVvalUpdateCounterenBits}{\saildoclabelled{sailRISCVzzyupdatezyCounterenzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_counteren_bitsab054ba63ba12cbce69135a6de8c9fad.tex}}}} + +\newcommand{\sailRISCVfnUpdateCounterenBits}{\saildoclabelled{sailRISCVfnzzyupdatezyCounterenzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_counteren_bitsab054ba63ba12cbce69135a6de8c9fad.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFFFFFFupdateBits}{\saildoclabelled{sailRISCVoverloadFFFFFFFFFzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFFFFFFzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGGGGGGModBits}{\saildoclabelled{sailRISCVoverloadGGGGGGGGGzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGGGGGGz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetCounterenHPM}{\saildoclabelled{sailRISCVzzygetzyCounterenzyHPM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_counteren_hpm3a5db98081f95347897bc13fea2e569f.tex}}}} + +\newcommand{\sailRISCVfnGetCounterenHPM}{\saildoclabelled{sailRISCVfnzzygetzyCounterenzyHPM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_counteren_hpm3a5db98081f95347897bc13fea2e569f.tex}}}} + +\newcommand{\sailRISCVvalSetCounterenHPM}{\saildoclabelled{sailRISCVzzysetzyCounterenzyHPM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_counteren_hpme0b60e00eab80a2934fe853d7cc21c79.tex}}}} + +\newcommand{\sailRISCVfnSetCounterenHPM}{\saildoclabelled{sailRISCVfnzzysetzyCounterenzyHPM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_counteren_hpme0b60e00eab80a2934fe853d7cc21c79.tex}}}} + +\newcommand{\sailRISCVvalUpdateCounterenHPM}{\saildoclabelled{sailRISCVzzyupdatezyCounterenzyHPM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_counteren_hpma99adbaf80dd358f59495d6ca7717d3b.tex}}}} + +\newcommand{\sailRISCVfnUpdateCounterenHPM}{\saildoclabelled{sailRISCVfnzzyupdatezyCounterenzyHPM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_counteren_hpma99adbaf80dd358f59495d6ca7717d3b.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHHHHHHupdateHPM}{\saildoclabelled{sailRISCVoverloadHHHHHHHHHzupdatezyHPM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHHHHHHzupdate_hpmd00b2501d0195e7ab575a2abf98eb98c.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIIIIIIModHPM}{\saildoclabelled{sailRISCVoverloadIIIIIIIIIzzymodzyHPM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIIIIIIz_mod_hpm583914551c880f3252ab7d2eb7c126a5.tex}}}} + +\newcommand{\sailRISCVvalGetCounterenIR}{\saildoclabelled{sailRISCVzzygetzyCounterenzyIR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_counteren_ir0443e9a01364d655f672be9fb3f334c2.tex}}}} + +\newcommand{\sailRISCVfnGetCounterenIR}{\saildoclabelled{sailRISCVfnzzygetzyCounterenzyIR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_counteren_ir0443e9a01364d655f672be9fb3f334c2.tex}}}} + +\newcommand{\sailRISCVvalSetCounterenIR}{\saildoclabelled{sailRISCVzzysetzyCounterenzyIR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_counteren_irc2c31e7ff83f5b56636c924d61b260d2.tex}}}} + +\newcommand{\sailRISCVfnSetCounterenIR}{\saildoclabelled{sailRISCVfnzzysetzyCounterenzyIR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_counteren_irc2c31e7ff83f5b56636c924d61b260d2.tex}}}} + +\newcommand{\sailRISCVvalUpdateCounterenIR}{\saildoclabelled{sailRISCVzzyupdatezyCounterenzyIR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_counteren_ir66176b4373b2eec827fbf9030a5406d0.tex}}}} + +\newcommand{\sailRISCVfnUpdateCounterenIR}{\saildoclabelled{sailRISCVfnzzyupdatezyCounterenzyIR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_counteren_ir66176b4373b2eec827fbf9030a5406d0.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJJJJJJupdateIR}{\saildoclabelled{sailRISCVoverloadJJJJJJJJJzupdatezyIR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJJJJJJzupdate_ir0515bd19fecd95b93762d149f033240a.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKKKKKKModIR}{\saildoclabelled{sailRISCVoverloadKKKKKKKKKzzymodzyIR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKKKKKKz_mod_ira44a158ed08eebfa24118152fd099692.tex}}}} + +\newcommand{\sailRISCVvalGetCounterenTM}{\saildoclabelled{sailRISCVzzygetzyCounterenzyTM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_counteren_tme8e19db38cbd8e49aa4656434c826c16.tex}}}} + +\newcommand{\sailRISCVfnGetCounterenTM}{\saildoclabelled{sailRISCVfnzzygetzyCounterenzyTM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_counteren_tme8e19db38cbd8e49aa4656434c826c16.tex}}}} + +\newcommand{\sailRISCVvalSetCounterenTM}{\saildoclabelled{sailRISCVzzysetzyCounterenzyTM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_counteren_tmed5ea23cd819bd09590e67c1c76777b7.tex}}}} + +\newcommand{\sailRISCVfnSetCounterenTM}{\saildoclabelled{sailRISCVfnzzysetzyCounterenzyTM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_counteren_tmed5ea23cd819bd09590e67c1c76777b7.tex}}}} + +\newcommand{\sailRISCVvalUpdateCounterenTM}{\saildoclabelled{sailRISCVzzyupdatezyCounterenzyTM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_counteren_tmab580665d1404d6531c604b4b0827504.tex}}}} + +\newcommand{\sailRISCVfnUpdateCounterenTM}{\saildoclabelled{sailRISCVfnzzyupdatezyCounterenzyTM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_counteren_tmab580665d1404d6531c604b4b0827504.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLLLLLLupdateTM}{\saildoclabelled{sailRISCVoverloadLLLLLLLLLzupdatezyTM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLLLLLLzupdate_tm832684a0b7e0412ced303c57d9817272.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMMMMMMModTM}{\saildoclabelled{sailRISCVoverloadMMMMMMMMMzzymodzyTM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMMMMMMz_mod_tm778e52c0329c82ffcc9fd72f0034a61e.tex}}}} + +\newcommand{\sailRISCVvalGetCounterenCY}{\saildoclabelled{sailRISCVzzygetzyCounterenzyCY}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_counteren_cy6e2b3bcf0f631c5bfe1602b7224ac3aa.tex}}}} + +\newcommand{\sailRISCVfnGetCounterenCY}{\saildoclabelled{sailRISCVfnzzygetzyCounterenzyCY}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_counteren_cy6e2b3bcf0f631c5bfe1602b7224ac3aa.tex}}}} + +\newcommand{\sailRISCVvalSetCounterenCY}{\saildoclabelled{sailRISCVzzysetzyCounterenzyCY}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_counteren_cy596db6893acf37ac3bd153f29c01a4f5.tex}}}} + +\newcommand{\sailRISCVfnSetCounterenCY}{\saildoclabelled{sailRISCVfnzzysetzyCounterenzyCY}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_counteren_cy596db6893acf37ac3bd153f29c01a4f5.tex}}}} + +\newcommand{\sailRISCVvalUpdateCounterenCY}{\saildoclabelled{sailRISCVzzyupdatezyCounterenzyCY}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_counteren_cyb4f1e37eac32f7b9365943e5600beec9.tex}}}} + +\newcommand{\sailRISCVfnUpdateCounterenCY}{\saildoclabelled{sailRISCVfnzzyupdatezyCounterenzyCY}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_counteren_cyb4f1e37eac32f7b9365943e5600beec9.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNNNNNNupdateCY}{\saildoclabelled{sailRISCVoverloadNNNNNNNNNzupdatezyCY}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNNNNNNzupdate_cyac1485e867c8bc776a140060ffab1295.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOOOOOOModCY}{\saildoclabelled{sailRISCVoverloadOOOOOOOOOzzymodzyCY}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOOOOOOz_mod_cy5609ca9870deee70dd1ee99cfdfb0c0d.tex}}}} + +\newcommand{\sailRISCVvallegalizzeMcounteren}{\saildoclabelled{sailRISCVzlegalizzezymcounteren}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_mcounteren34ab1d8bf1d636c1c12eb9e0b743229f.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeMcounteren}{\saildoclabelled{sailRISCVfnzlegalizzezymcounteren}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_mcounteren34ab1d8bf1d636c1c12eb9e0b743229f.tex}}}} + +\newcommand{\sailRISCVvallegalizzeScounteren}{\saildoclabelled{sailRISCVzlegalizzezyscounteren}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_scountereneb4feb895f759dc11e62dedd5be1c232.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeScounteren}{\saildoclabelled{sailRISCVfnzlegalizzezyscounteren}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_scountereneb4feb895f759dc11e62dedd5be1c232.tex}}}} + +\newcommand{\sailRISCVtypeCounterin}{\saildoclabelled{sailRISCVtypezCounterin}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezcounterin25158d322f7a7f1b254bff0638245582.tex}}}} + +\newcommand{\sailRISCVvalMkCounterin}{\saildoclabelled{sailRISCVzMkzyCounterin}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_counterin5d7512dddbfaeea7688a2e6a3c88ed68.tex}}}} + +\newcommand{\sailRISCVfnMkCounterin}{\saildoclabelled{sailRISCVfnzMkzyCounterin}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_counterin5d7512dddbfaeea7688a2e6a3c88ed68.tex}}}} + +\newcommand{\sailRISCVvalGetCounterinBits}{\saildoclabelled{sailRISCVzzygetzyCounterinzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_counterin_bits11d3d881d3130628193ac87a6d2fd74a.tex}}}} + +\newcommand{\sailRISCVfnGetCounterinBits}{\saildoclabelled{sailRISCVfnzzygetzyCounterinzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_counterin_bits11d3d881d3130628193ac87a6d2fd74a.tex}}}} + +\newcommand{\sailRISCVvalSetCounterinBits}{\saildoclabelled{sailRISCVzzysetzyCounterinzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_counterin_bits4d906fc122c4b0829e669029457bff46.tex}}}} + +\newcommand{\sailRISCVfnSetCounterinBits}{\saildoclabelled{sailRISCVfnzzysetzyCounterinzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_counterin_bits4d906fc122c4b0829e669029457bff46.tex}}}} + +\newcommand{\sailRISCVvalUpdateCounterinBits}{\saildoclabelled{sailRISCVzzyupdatezyCounterinzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_counterin_bits2487a90cdc32df9b1556a37b4d85fe52.tex}}}} + +\newcommand{\sailRISCVfnUpdateCounterinBits}{\saildoclabelled{sailRISCVfnzzyupdatezyCounterinzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_counterin_bits2487a90cdc32df9b1556a37b4d85fe52.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPPPPPPupdateBits}{\saildoclabelled{sailRISCVoverloadPPPPPPPPPzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPPPPPPzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQQQQQQModBits}{\saildoclabelled{sailRISCVoverloadQQQQQQQQQzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQQQQQQz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetCounterinIR}{\saildoclabelled{sailRISCVzzygetzyCounterinzyIR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_counterin_ira4b70e343466abb62da1c490774a9c7a.tex}}}} + +\newcommand{\sailRISCVfnGetCounterinIR}{\saildoclabelled{sailRISCVfnzzygetzyCounterinzyIR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_counterin_ira4b70e343466abb62da1c490774a9c7a.tex}}}} + +\newcommand{\sailRISCVvalSetCounterinIR}{\saildoclabelled{sailRISCVzzysetzyCounterinzyIR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_counterin_ir7435617becd3df612dd905733de79ab0.tex}}}} + +\newcommand{\sailRISCVfnSetCounterinIR}{\saildoclabelled{sailRISCVfnzzysetzyCounterinzyIR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_counterin_ir7435617becd3df612dd905733de79ab0.tex}}}} + +\newcommand{\sailRISCVvalUpdateCounterinIR}{\saildoclabelled{sailRISCVzzyupdatezyCounterinzyIR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_counterin_ire83041be7a3bb70aa6f359785f4856ef.tex}}}} + +\newcommand{\sailRISCVfnUpdateCounterinIR}{\saildoclabelled{sailRISCVfnzzyupdatezyCounterinzyIR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_counterin_ire83041be7a3bb70aa6f359785f4856ef.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRRRRRRupdateIR}{\saildoclabelled{sailRISCVoverloadRRRRRRRRRzupdatezyIR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRRRRRRzupdate_ir0515bd19fecd95b93762d149f033240a.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSSSSSSModIR}{\saildoclabelled{sailRISCVoverloadSSSSSSSSSzzymodzyIR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSSSSSSz_mod_ira44a158ed08eebfa24118152fd099692.tex}}}} + +\newcommand{\sailRISCVvalGetCounterinCY}{\saildoclabelled{sailRISCVzzygetzyCounterinzyCY}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_counterin_cydc6f1e9f2967dff249969b51399a14ca.tex}}}} + +\newcommand{\sailRISCVfnGetCounterinCY}{\saildoclabelled{sailRISCVfnzzygetzyCounterinzyCY}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_counterin_cydc6f1e9f2967dff249969b51399a14ca.tex}}}} + +\newcommand{\sailRISCVvalSetCounterinCY}{\saildoclabelled{sailRISCVzzysetzyCounterinzyCY}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_counterin_cy2ee6f977ede334731ad36d7afe6e2be4.tex}}}} + +\newcommand{\sailRISCVfnSetCounterinCY}{\saildoclabelled{sailRISCVfnzzysetzyCounterinzyCY}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_counterin_cy2ee6f977ede334731ad36d7afe6e2be4.tex}}}} + +\newcommand{\sailRISCVvalUpdateCounterinCY}{\saildoclabelled{sailRISCVzzyupdatezyCounterinzyCY}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_counterin_cy16506512e1a71f4a75459533622c36ab.tex}}}} + +\newcommand{\sailRISCVfnUpdateCounterinCY}{\saildoclabelled{sailRISCVfnzzyupdatezyCounterinzyCY}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_counterin_cy16506512e1a71f4a75459533622c36ab.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTTTTTTupdateCY}{\saildoclabelled{sailRISCVoverloadTTTTTTTTTzupdatezyCY}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTTTTTTzupdate_cyac1485e867c8bc776a140060ffab1295.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUUUUUUModCY}{\saildoclabelled{sailRISCVoverloadUUUUUUUUUzzymodzyCY}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUUUUUUz_mod_cy5609ca9870deee70dd1ee99cfdfb0c0d.tex}}}} + +\newcommand{\sailRISCVvallegalizzeMcountinhibit}{\saildoclabelled{sailRISCVzlegalizzezymcountinhibit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_mcountinhibit83a4863cf81084082c5c66150150e695.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeMcountinhibit}{\saildoclabelled{sailRISCVfnzlegalizzezymcountinhibit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_mcountinhibit83a4863cf81084082c5c66150150e695.tex}}}} + +\newcommand{\sailRISCVvalretireInstruction}{\saildoclabelled{sailRISCVzretirezyinstruction}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzretire_instructionc9e2e6b25fd8f4e5a96cd82a0dd2a675.tex}}}} + +\newcommand{\sailRISCVfnretireInstruction}{\saildoclabelled{sailRISCVfnzretirezyinstruction}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzretire_instructionc9e2e6b25fd8f4e5a96cd82a0dd2a675.tex}}}} + +\newcommand{\sailRISCVtypeSstatus}{\saildoclabelled{sailRISCVtypezSstatus}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsstatusb3811444f066c3543008d60a23f2fb4b.tex}}}} + +\newcommand{\sailRISCVvalMkSstatus}{\saildoclabelled{sailRISCVzMkzySstatus}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_sstatus103c07d81aa6bb97a5681c36b23d8d7f.tex}}}} + +\newcommand{\sailRISCVfnMkSstatus}{\saildoclabelled{sailRISCVfnzMkzySstatus}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_sstatus103c07d81aa6bb97a5681c36b23d8d7f.tex}}}} + +\newcommand{\sailRISCVvalGetSstatusBits}{\saildoclabelled{sailRISCVzzygetzySstatuszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sstatus_bits47345191d41288d1bd8a7c67bc24ffc6.tex}}}} + +\newcommand{\sailRISCVfnGetSstatusBits}{\saildoclabelled{sailRISCVfnzzygetzySstatuszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sstatus_bits47345191d41288d1bd8a7c67bc24ffc6.tex}}}} + +\newcommand{\sailRISCVvalSetSstatusBits}{\saildoclabelled{sailRISCVzzysetzySstatuszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sstatus_bitsa6c8fba93c0c18f7fc69cd591748cdfa.tex}}}} + +\newcommand{\sailRISCVfnSetSstatusBits}{\saildoclabelled{sailRISCVfnzzysetzySstatuszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sstatus_bitsa6c8fba93c0c18f7fc69cd591748cdfa.tex}}}} + +\newcommand{\sailRISCVvalUpdateSstatusBits}{\saildoclabelled{sailRISCVzzyupdatezySstatuszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sstatus_bits1ba4fa3c8cd21f04fa8e9a269f477a52.tex}}}} + +\newcommand{\sailRISCVfnUpdateSstatusBits}{\saildoclabelled{sailRISCVfnzzyupdatezySstatuszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sstatus_bits1ba4fa3c8cd21f04fa8e9a269f477a52.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVVVVVVupdateBits}{\saildoclabelled{sailRISCVoverloadVVVVVVVVVzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVVVVVVzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWWWWWWModBits}{\saildoclabelled{sailRISCVoverloadWWWWWWWWWzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWWWWWWz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSstatusSD}{\saildoclabelled{sailRISCVzzygetzySstatuszySD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sstatus_sd12bb5cef6bc9eaf62712c3b06c0754ff.tex}}}} + +\newcommand{\sailRISCVfnGetSstatusSD}{\saildoclabelled{sailRISCVfnzzygetzySstatuszySD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sstatus_sd12bb5cef6bc9eaf62712c3b06c0754ff.tex}}}} + +\newcommand{\sailRISCVvalSetSstatusSD}{\saildoclabelled{sailRISCVzzysetzySstatuszySD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sstatus_sdd76fee105151cc55a95224ff72515795.tex}}}} + +\newcommand{\sailRISCVfnSetSstatusSD}{\saildoclabelled{sailRISCVfnzzysetzySstatuszySD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sstatus_sdd76fee105151cc55a95224ff72515795.tex}}}} + +\newcommand{\sailRISCVvalUpdateSstatusSD}{\saildoclabelled{sailRISCVzzyupdatezySstatuszySD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sstatus_sda2846124209293b81711916fe96d61c9.tex}}}} + +\newcommand{\sailRISCVfnUpdateSstatusSD}{\saildoclabelled{sailRISCVfnzzyupdatezySstatuszySD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sstatus_sda2846124209293b81711916fe96d61c9.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXXXXXXupdateSD}{\saildoclabelled{sailRISCVoverloadXXXXXXXXXzupdatezySD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXXXXXXzupdate_sd5d9e90ac938aa12ac2bdb01a3c3d6e92.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYYYYYYModSD}{\saildoclabelled{sailRISCVoverloadYYYYYYYYYzzymodzySD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYYYYYYz_mod_sd1e51a771a9b628b657ecbb1ba7aa8f7c.tex}}}} + +\newcommand{\sailRISCVvalGetSstatusMXR}{\saildoclabelled{sailRISCVzzygetzySstatuszyMXR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sstatus_mxr1ed9764969d17c97d4b45acc9309595b.tex}}}} + +\newcommand{\sailRISCVfnGetSstatusMXR}{\saildoclabelled{sailRISCVfnzzygetzySstatuszyMXR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sstatus_mxr1ed9764969d17c97d4b45acc9309595b.tex}}}} + +\newcommand{\sailRISCVvalSetSstatusMXR}{\saildoclabelled{sailRISCVzzysetzySstatuszyMXR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sstatus_mxra2eba57c040b3e2ec7adb22d3d1de868.tex}}}} + +\newcommand{\sailRISCVfnSetSstatusMXR}{\saildoclabelled{sailRISCVfnzzysetzySstatuszyMXR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sstatus_mxra2eba57c040b3e2ec7adb22d3d1de868.tex}}}} + +\newcommand{\sailRISCVvalUpdateSstatusMXR}{\saildoclabelled{sailRISCVzzyupdatezySstatuszyMXR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sstatus_mxre42b7942f7975353cbe85a0c0e124cdd.tex}}}} + +\newcommand{\sailRISCVfnUpdateSstatusMXR}{\saildoclabelled{sailRISCVfnzzyupdatezySstatuszyMXR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sstatus_mxre42b7942f7975353cbe85a0c0e124cdd.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZZZZZZupdateMXR}{\saildoclabelled{sailRISCVoverloadZZZZZZZZZzupdatezyMXR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZZZZZZzupdate_mxra54b3693fefa5d6b0301ff08e0ea5a3f.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAAAAAAModMXR}{\saildoclabelled{sailRISCVoverloadAAAAAAAAAAzzymodzyMXR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAAAAAAz_mod_mxr626efb0dadf77d402ea180eddd656377.tex}}}} + +\newcommand{\sailRISCVvalGetSstatusSUM}{\saildoclabelled{sailRISCVzzygetzySstatuszySUM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sstatus_sumfd7d657ad527ac995d1fbf0ded8ce3f5.tex}}}} + +\newcommand{\sailRISCVfnGetSstatusSUM}{\saildoclabelled{sailRISCVfnzzygetzySstatuszySUM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sstatus_sumfd7d657ad527ac995d1fbf0ded8ce3f5.tex}}}} + +\newcommand{\sailRISCVvalSetSstatusSUM}{\saildoclabelled{sailRISCVzzysetzySstatuszySUM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sstatus_sumd6e6c88b359702301526305ad3ae0775.tex}}}} + +\newcommand{\sailRISCVfnSetSstatusSUM}{\saildoclabelled{sailRISCVfnzzysetzySstatuszySUM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sstatus_sumd6e6c88b359702301526305ad3ae0775.tex}}}} + +\newcommand{\sailRISCVvalUpdateSstatusSUM}{\saildoclabelled{sailRISCVzzyupdatezySstatuszySUM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sstatus_sum0cb0974a1d97890dd07f5d0a8a0e2a1f.tex}}}} + +\newcommand{\sailRISCVfnUpdateSstatusSUM}{\saildoclabelled{sailRISCVfnzzyupdatezySstatuszySUM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sstatus_sum0cb0974a1d97890dd07f5d0a8a0e2a1f.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBBBBBBupdateSUM}{\saildoclabelled{sailRISCVoverloadBBBBBBBBBBzupdatezySUM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBBBBBBzupdate_sum45aaa4f77ddaa1e976bb9719406d8d4d.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCCCCCCModSUM}{\saildoclabelled{sailRISCVoverloadCCCCCCCCCCzzymodzySUM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCCCCCCz_mod_sum9c28eec9a0977f334c917bffeb75d7eb.tex}}}} + +\newcommand{\sailRISCVvalGetSstatusXS}{\saildoclabelled{sailRISCVzzygetzySstatuszyXS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sstatus_xs83df09eb63f5261e086c2a1e7e0f1c7a.tex}}}} + +\newcommand{\sailRISCVfnGetSstatusXS}{\saildoclabelled{sailRISCVfnzzygetzySstatuszyXS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sstatus_xs83df09eb63f5261e086c2a1e7e0f1c7a.tex}}}} + +\newcommand{\sailRISCVvalSetSstatusXS}{\saildoclabelled{sailRISCVzzysetzySstatuszyXS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sstatus_xs051efb5955770c941a701fd96e8879a7.tex}}}} + +\newcommand{\sailRISCVfnSetSstatusXS}{\saildoclabelled{sailRISCVfnzzysetzySstatuszyXS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sstatus_xs051efb5955770c941a701fd96e8879a7.tex}}}} + +\newcommand{\sailRISCVvalUpdateSstatusXS}{\saildoclabelled{sailRISCVzzyupdatezySstatuszyXS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sstatus_xs8ed6c14d8c84fed994d5b6f62a6f95ff.tex}}}} + +\newcommand{\sailRISCVfnUpdateSstatusXS}{\saildoclabelled{sailRISCVfnzzyupdatezySstatuszyXS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sstatus_xs8ed6c14d8c84fed994d5b6f62a6f95ff.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDDDDDDDupdateXS}{\saildoclabelled{sailRISCVoverloadDDDDDDDDDDzupdatezyXS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDDDDDDDzupdate_xsd577805c39539bb2ca85cd57d24ab51e.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEEEEEEEModXS}{\saildoclabelled{sailRISCVoverloadEEEEEEEEEEzzymodzyXS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEEEEEEEz_mod_xs4cdc96063571eef4b6f09a5174c4405f.tex}}}} + +\newcommand{\sailRISCVvalGetSstatusFS}{\saildoclabelled{sailRISCVzzygetzySstatuszyFS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sstatus_fs1460ce74aab98835a1244cb2459d0b77.tex}}}} + +\newcommand{\sailRISCVfnGetSstatusFS}{\saildoclabelled{sailRISCVfnzzygetzySstatuszyFS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sstatus_fs1460ce74aab98835a1244cb2459d0b77.tex}}}} + +\newcommand{\sailRISCVvalSetSstatusFS}{\saildoclabelled{sailRISCVzzysetzySstatuszyFS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sstatus_fse0f398b51eea363e05016843c2c595a4.tex}}}} + +\newcommand{\sailRISCVfnSetSstatusFS}{\saildoclabelled{sailRISCVfnzzysetzySstatuszyFS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sstatus_fse0f398b51eea363e05016843c2c595a4.tex}}}} + +\newcommand{\sailRISCVvalUpdateSstatusFS}{\saildoclabelled{sailRISCVzzyupdatezySstatuszyFS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sstatus_fs5ae270f58355a8043214a3e56ea4ecb9.tex}}}} + +\newcommand{\sailRISCVfnUpdateSstatusFS}{\saildoclabelled{sailRISCVfnzzyupdatezySstatuszyFS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sstatus_fs5ae270f58355a8043214a3e56ea4ecb9.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFFFFFFFupdateFS}{\saildoclabelled{sailRISCVoverloadFFFFFFFFFFzupdatezyFS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFFFFFFFzupdate_fs64e6ca4d39ea47b95fa1da5e3e2e0921.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGGGGGGGModFS}{\saildoclabelled{sailRISCVoverloadGGGGGGGGGGzzymodzyFS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGGGGGGGz_mod_fs91fd3eaccea19c4e4e7d0eef23a6ae9a.tex}}}} + +\newcommand{\sailRISCVvalGetSstatusSPP}{\saildoclabelled{sailRISCVzzygetzySstatuszySPP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sstatus_spp7cc37e9faad99d47707d2a3ed85339cb.tex}}}} + +\newcommand{\sailRISCVfnGetSstatusSPP}{\saildoclabelled{sailRISCVfnzzygetzySstatuszySPP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sstatus_spp7cc37e9faad99d47707d2a3ed85339cb.tex}}}} + +\newcommand{\sailRISCVvalSetSstatusSPP}{\saildoclabelled{sailRISCVzzysetzySstatuszySPP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sstatus_spp8d87600dabd1a0a5c7d063db6e618a28.tex}}}} + +\newcommand{\sailRISCVfnSetSstatusSPP}{\saildoclabelled{sailRISCVfnzzysetzySstatuszySPP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sstatus_spp8d87600dabd1a0a5c7d063db6e618a28.tex}}}} + +\newcommand{\sailRISCVvalUpdateSstatusSPP}{\saildoclabelled{sailRISCVzzyupdatezySstatuszySPP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sstatus_spp6bca059909e0ea5d1dca7a5f6a4c496d.tex}}}} + +\newcommand{\sailRISCVfnUpdateSstatusSPP}{\saildoclabelled{sailRISCVfnzzyupdatezySstatuszySPP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sstatus_spp6bca059909e0ea5d1dca7a5f6a4c496d.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHHHHHHHupdateSPP}{\saildoclabelled{sailRISCVoverloadHHHHHHHHHHzupdatezySPP}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHHHHHHHzupdate_spp8c7dea9e7e0f6e12e0b546be06facdc6.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIIIIIIIModSPP}{\saildoclabelled{sailRISCVoverloadIIIIIIIIIIzzymodzySPP}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIIIIIIIz_mod_spp50ceeb4c06bc3d145fb76bed24fa7e68.tex}}}} + +\newcommand{\sailRISCVvalGetSstatusSPIE}{\saildoclabelled{sailRISCVzzygetzySstatuszySPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sstatus_spie72f0239373389161757a30610914f136.tex}}}} + +\newcommand{\sailRISCVfnGetSstatusSPIE}{\saildoclabelled{sailRISCVfnzzygetzySstatuszySPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sstatus_spie72f0239373389161757a30610914f136.tex}}}} + +\newcommand{\sailRISCVvalSetSstatusSPIE}{\saildoclabelled{sailRISCVzzysetzySstatuszySPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sstatus_spie739993a605bcb322c2dbdf0ca5ddd2bc.tex}}}} + +\newcommand{\sailRISCVfnSetSstatusSPIE}{\saildoclabelled{sailRISCVfnzzysetzySstatuszySPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sstatus_spie739993a605bcb322c2dbdf0ca5ddd2bc.tex}}}} + +\newcommand{\sailRISCVvalUpdateSstatusSPIE}{\saildoclabelled{sailRISCVzzyupdatezySstatuszySPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sstatus_spiea58b5496b1efe334d89b66e4df1f6a37.tex}}}} + +\newcommand{\sailRISCVfnUpdateSstatusSPIE}{\saildoclabelled{sailRISCVfnzzyupdatezySstatuszySPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sstatus_spiea58b5496b1efe334d89b66e4df1f6a37.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJJJJJJJupdateSPIE}{\saildoclabelled{sailRISCVoverloadJJJJJJJJJJzupdatezySPIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJJJJJJJzupdate_spie94668fa3ad37daf933543298ec02f222.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKKKKKKKModSPIE}{\saildoclabelled{sailRISCVoverloadKKKKKKKKKKzzymodzySPIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKKKKKKKz_mod_spie8a60328109316a4d9a0f7769708c8522.tex}}}} + +\newcommand{\sailRISCVvalGetSstatusUPIE}{\saildoclabelled{sailRISCVzzygetzySstatuszyUPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sstatus_upie1fbaa84eb888e534ff854d4d873dff79.tex}}}} + +\newcommand{\sailRISCVfnGetSstatusUPIE}{\saildoclabelled{sailRISCVfnzzygetzySstatuszyUPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sstatus_upie1fbaa84eb888e534ff854d4d873dff79.tex}}}} + +\newcommand{\sailRISCVvalSetSstatusUPIE}{\saildoclabelled{sailRISCVzzysetzySstatuszyUPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sstatus_upiec20707b779f0d69be936cc46a8acab83.tex}}}} + +\newcommand{\sailRISCVfnSetSstatusUPIE}{\saildoclabelled{sailRISCVfnzzysetzySstatuszyUPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sstatus_upiec20707b779f0d69be936cc46a8acab83.tex}}}} + +\newcommand{\sailRISCVvalUpdateSstatusUPIE}{\saildoclabelled{sailRISCVzzyupdatezySstatuszyUPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sstatus_upie90c90f6e3ef912c0267408b59aaaec07.tex}}}} + +\newcommand{\sailRISCVfnUpdateSstatusUPIE}{\saildoclabelled{sailRISCVfnzzyupdatezySstatuszyUPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sstatus_upie90c90f6e3ef912c0267408b59aaaec07.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLLLLLLLupdateUPIE}{\saildoclabelled{sailRISCVoverloadLLLLLLLLLLzupdatezyUPIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLLLLLLLzupdate_upiea5ad86a550536087d757a5582d1a8bb9.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMMMMMMMModUPIE}{\saildoclabelled{sailRISCVoverloadMMMMMMMMMMzzymodzyUPIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMMMMMMMz_mod_upie27f56ba53dc72f512e0a128ab616ba83.tex}}}} + +\newcommand{\sailRISCVvalGetSstatusSIE}{\saildoclabelled{sailRISCVzzygetzySstatuszySIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sstatus_sie9e01f0fa9797876074411f8310096e19.tex}}}} + +\newcommand{\sailRISCVfnGetSstatusSIE}{\saildoclabelled{sailRISCVfnzzygetzySstatuszySIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sstatus_sie9e01f0fa9797876074411f8310096e19.tex}}}} + +\newcommand{\sailRISCVvalSetSstatusSIE}{\saildoclabelled{sailRISCVzzysetzySstatuszySIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sstatus_siead9f271cff4bf9d22da8464c4d1ca3b4.tex}}}} + +\newcommand{\sailRISCVfnSetSstatusSIE}{\saildoclabelled{sailRISCVfnzzysetzySstatuszySIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sstatus_siead9f271cff4bf9d22da8464c4d1ca3b4.tex}}}} + +\newcommand{\sailRISCVvalUpdateSstatusSIE}{\saildoclabelled{sailRISCVzzyupdatezySstatuszySIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sstatus_siea3c5fb4c611f7dacc262fcbe33a89902.tex}}}} + +\newcommand{\sailRISCVfnUpdateSstatusSIE}{\saildoclabelled{sailRISCVfnzzyupdatezySstatuszySIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sstatus_siea3c5fb4c611f7dacc262fcbe33a89902.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNNNNNNNupdateSIE}{\saildoclabelled{sailRISCVoverloadNNNNNNNNNNzupdatezySIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNNNNNNNzupdate_sie1b2ed07072361c44e9ce7a8ca87b5555.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOOOOOOOModSIE}{\saildoclabelled{sailRISCVoverloadOOOOOOOOOOzzymodzySIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOOOOOOOz_mod_sieea56e4c7d22bb7c198ba004deeb422c9.tex}}}} + +\newcommand{\sailRISCVvalGetSstatusUIE}{\saildoclabelled{sailRISCVzzygetzySstatuszyUIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sstatus_uie5a504087d59c8a2af6de9c1f7a14b612.tex}}}} + +\newcommand{\sailRISCVfnGetSstatusUIE}{\saildoclabelled{sailRISCVfnzzygetzySstatuszyUIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sstatus_uie5a504087d59c8a2af6de9c1f7a14b612.tex}}}} + +\newcommand{\sailRISCVvalSetSstatusUIE}{\saildoclabelled{sailRISCVzzysetzySstatuszyUIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sstatus_uie05848044f6bfa6902b92558093153733.tex}}}} + +\newcommand{\sailRISCVfnSetSstatusUIE}{\saildoclabelled{sailRISCVfnzzysetzySstatuszyUIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sstatus_uie05848044f6bfa6902b92558093153733.tex}}}} + +\newcommand{\sailRISCVvalUpdateSstatusUIE}{\saildoclabelled{sailRISCVzzyupdatezySstatuszyUIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sstatus_uie0de3308b00b5fa027c405d5ba7ea56a8.tex}}}} + +\newcommand{\sailRISCVfnUpdateSstatusUIE}{\saildoclabelled{sailRISCVfnzzyupdatezySstatuszyUIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sstatus_uie0de3308b00b5fa027c405d5ba7ea56a8.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPPPPPPPupdateUIE}{\saildoclabelled{sailRISCVoverloadPPPPPPPPPPzupdatezyUIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPPPPPPPzupdate_uied194e7b32c7c54d35dfc1b602b4b5907.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQQQQQQQModUIE}{\saildoclabelled{sailRISCVoverloadQQQQQQQQQQzzymodzyUIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQQQQQQQz_mod_uie18b8fe18a506d4c612ff106c8cc5fb23.tex}}}} + +\newcommand{\sailRISCVvalgetSstatusUXL}{\saildoclabelled{sailRISCVzgetzysstatuszyUXL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_sstatus_uxl1156c19b76a50f309373d09741dbfe73.tex}}}} + +\newcommand{\sailRISCVfngetSstatusUXL}{\saildoclabelled{sailRISCVfnzgetzysstatuszyUXL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_sstatus_uxl1156c19b76a50f309373d09741dbfe73.tex}}}} + +\newcommand{\sailRISCVvalsetSstatusUXL}{\saildoclabelled{sailRISCVzsetzysstatuszyUXL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzset_sstatus_uxl4d602a7109609248f9b54c8c905b4ad0.tex}}}} + +\newcommand{\sailRISCVfnsetSstatusUXL}{\saildoclabelled{sailRISCVfnzsetzysstatuszyUXL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzset_sstatus_uxl4d602a7109609248f9b54c8c905b4ad0.tex}}}} + +\newcommand{\sailRISCVvallowerMstatus}{\saildoclabelled{sailRISCVzlowerzymstatus}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlower_mstatuse71dfbedf80129bee76a841456768dd1.tex}}}} + +\newcommand{\sailRISCVfnlowerMstatus}{\saildoclabelled{sailRISCVfnzlowerzymstatus}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlower_mstatuse71dfbedf80129bee76a841456768dd1.tex}}}} + +\newcommand{\sailRISCVvalliftSstatus}{\saildoclabelled{sailRISCVzliftzysstatus}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlift_sstatus8b6865e3f513094f03fd5bfc83d2ed77.tex}}}} + +\newcommand{\sailRISCVfnliftSstatus}{\saildoclabelled{sailRISCVfnzliftzysstatus}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlift_sstatus8b6865e3f513094f03fd5bfc83d2ed77.tex}}}} + +\newcommand{\sailRISCVvallegalizzeSstatus}{\saildoclabelled{sailRISCVzlegalizzezysstatus}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_sstatus6838bd21db8615a2ed1602fc6dd7f8da.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeSstatus}{\saildoclabelled{sailRISCVfnzlegalizzezysstatus}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_sstatus6838bd21db8615a2ed1602fc6dd7f8da.tex}}}} + +\newcommand{\sailRISCVtypeSedeleg}{\saildoclabelled{sailRISCVtypezSedeleg}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsedeleg261f8092f9d360d308a10bcbcc83c5f6.tex}}}} + +\newcommand{\sailRISCVvalMkSedeleg}{\saildoclabelled{sailRISCVzMkzySedeleg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_sedeleg222d7d880065c377c672b48be0312b58.tex}}}} + +\newcommand{\sailRISCVfnMkSedeleg}{\saildoclabelled{sailRISCVfnzMkzySedeleg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_sedeleg222d7d880065c377c672b48be0312b58.tex}}}} + +\newcommand{\sailRISCVvalGetSedelegBits}{\saildoclabelled{sailRISCVzzygetzySedelegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sedeleg_bitsf6b9b215e547db1e045ee7ddfb1f2f7a.tex}}}} + +\newcommand{\sailRISCVfnGetSedelegBits}{\saildoclabelled{sailRISCVfnzzygetzySedelegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sedeleg_bitsf6b9b215e547db1e045ee7ddfb1f2f7a.tex}}}} + +\newcommand{\sailRISCVvalSetSedelegBits}{\saildoclabelled{sailRISCVzzysetzySedelegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sedeleg_bitsa2dbd669d717e67fa0750d9be9a12cee.tex}}}} + +\newcommand{\sailRISCVfnSetSedelegBits}{\saildoclabelled{sailRISCVfnzzysetzySedelegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sedeleg_bitsa2dbd669d717e67fa0750d9be9a12cee.tex}}}} + +\newcommand{\sailRISCVvalUpdateSedelegBits}{\saildoclabelled{sailRISCVzzyupdatezySedelegzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sedeleg_bits2cf1d3152200555a4daa2092a724ca06.tex}}}} + +\newcommand{\sailRISCVfnUpdateSedelegBits}{\saildoclabelled{sailRISCVfnzzyupdatezySedelegzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sedeleg_bits2cf1d3152200555a4daa2092a724ca06.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRRRRRRRupdateBits}{\saildoclabelled{sailRISCVoverloadRRRRRRRRRRzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRRRRRRRzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSSSSSSSModBits}{\saildoclabelled{sailRISCVoverloadSSSSSSSSSSzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSSSSSSSz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSedelegUEnvCall}{\saildoclabelled{sailRISCVzzygetzySedelegzyUEnvCall}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sedeleg_uenvcall9adf65053b570cbc347b25630db85fa1.tex}}}} + +\newcommand{\sailRISCVfnGetSedelegUEnvCall}{\saildoclabelled{sailRISCVfnzzygetzySedelegzyUEnvCall}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sedeleg_uenvcall9adf65053b570cbc347b25630db85fa1.tex}}}} + +\newcommand{\sailRISCVvalSetSedelegUEnvCall}{\saildoclabelled{sailRISCVzzysetzySedelegzyUEnvCall}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sedeleg_uenvcall80b0a54fdfebf30e056fa7c713788315.tex}}}} + +\newcommand{\sailRISCVfnSetSedelegUEnvCall}{\saildoclabelled{sailRISCVfnzzysetzySedelegzyUEnvCall}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sedeleg_uenvcall80b0a54fdfebf30e056fa7c713788315.tex}}}} + +\newcommand{\sailRISCVvalUpdateSedelegUEnvCall}{\saildoclabelled{sailRISCVzzyupdatezySedelegzyUEnvCall}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sedeleg_uenvcall0461d2c07b3055bf1fc4d0b3ea5739ef.tex}}}} + +\newcommand{\sailRISCVfnUpdateSedelegUEnvCall}{\saildoclabelled{sailRISCVfnzzyupdatezySedelegzyUEnvCall}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sedeleg_uenvcall0461d2c07b3055bf1fc4d0b3ea5739ef.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTTTTTTTupdateUEnvCall}{\saildoclabelled{sailRISCVoverloadTTTTTTTTTTzupdatezyUEnvCall}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTTTTTTTzupdate_uenvcall1a8e9c082fb9f272d5370bee121f426d.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUUUUUUUModUEnvCall}{\saildoclabelled{sailRISCVoverloadUUUUUUUUUUzzymodzyUEnvCall}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUUUUUUUz_mod_uenvcall837e3a85bd98d15f2f4b32f9230ddef6.tex}}}} + +\newcommand{\sailRISCVvalGetSedelegSAMOAccessFault}{\saildoclabelled{sailRISCVzzygetzySedelegzySAMOzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sedeleg_samo_access_fault3592b648b74f292f7582352512f54c43.tex}}}} + +\newcommand{\sailRISCVfnGetSedelegSAMOAccessFault}{\saildoclabelled{sailRISCVfnzzygetzySedelegzySAMOzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sedeleg_samo_access_fault3592b648b74f292f7582352512f54c43.tex}}}} + +\newcommand{\sailRISCVvalSetSedelegSAMOAccessFault}{\saildoclabelled{sailRISCVzzysetzySedelegzySAMOzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sedeleg_samo_access_fault9cc04f455b39e7c1866c125033bf2f03.tex}}}} + +\newcommand{\sailRISCVfnSetSedelegSAMOAccessFault}{\saildoclabelled{sailRISCVfnzzysetzySedelegzySAMOzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sedeleg_samo_access_fault9cc04f455b39e7c1866c125033bf2f03.tex}}}} + +\newcommand{\sailRISCVvalUpdateSedelegSAMOAccessFault}{\saildoclabelled{sailRISCVzzyupdatezySedelegzySAMOzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sedeleg_samo_access_fault9638c0015422d7509a2a078d70f56ba2.tex}}}} + +\newcommand{\sailRISCVfnUpdateSedelegSAMOAccessFault}{\saildoclabelled{sailRISCVfnzzyupdatezySedelegzySAMOzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sedeleg_samo_access_fault9638c0015422d7509a2a078d70f56ba2.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVVVVVVVupdateSAMOAccessFault}{\saildoclabelled{sailRISCVoverloadVVVVVVVVVVzupdatezySAMOzyAccesszyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVVVVVVVzupdate_samo_access_faulte622f01b5ab60ce658092d165d64a4f9.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWWWWWWWModSAMOAccessFault}{\saildoclabelled{sailRISCVoverloadWWWWWWWWWWzzymodzySAMOzyAccesszyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWWWWWWWz_mod_samo_access_faultef1cf7b1db2bf21d4e773b1a41ea8eea.tex}}}} + +\newcommand{\sailRISCVvalGetSedelegSAMOAddrAlign}{\saildoclabelled{sailRISCVzzygetzySedelegzySAMOzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sedeleg_samo_addr_align20af8fdcd584bdebc6b45b3bf763ab61.tex}}}} + +\newcommand{\sailRISCVfnGetSedelegSAMOAddrAlign}{\saildoclabelled{sailRISCVfnzzygetzySedelegzySAMOzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sedeleg_samo_addr_align20af8fdcd584bdebc6b45b3bf763ab61.tex}}}} + +\newcommand{\sailRISCVvalSetSedelegSAMOAddrAlign}{\saildoclabelled{sailRISCVzzysetzySedelegzySAMOzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sedeleg_samo_addr_align9567cfb032fb426d3c4292d506d6a9d2.tex}}}} + +\newcommand{\sailRISCVfnSetSedelegSAMOAddrAlign}{\saildoclabelled{sailRISCVfnzzysetzySedelegzySAMOzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sedeleg_samo_addr_align9567cfb032fb426d3c4292d506d6a9d2.tex}}}} + +\newcommand{\sailRISCVvalUpdateSedelegSAMOAddrAlign}{\saildoclabelled{sailRISCVzzyupdatezySedelegzySAMOzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sedeleg_samo_addr_align39928f0de9fb23d2068681efa4f6e746.tex}}}} + +\newcommand{\sailRISCVfnUpdateSedelegSAMOAddrAlign}{\saildoclabelled{sailRISCVfnzzyupdatezySedelegzySAMOzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sedeleg_samo_addr_align39928f0de9fb23d2068681efa4f6e746.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXXXXXXXupdateSAMOAddrAlign}{\saildoclabelled{sailRISCVoverloadXXXXXXXXXXzupdatezySAMOzyAddrzyAlign}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXXXXXXXzupdate_samo_addr_alignb6f17cfe030aff1cf9413eeaa67b67ee.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYYYYYYYModSAMOAddrAlign}{\saildoclabelled{sailRISCVoverloadYYYYYYYYYYzzymodzySAMOzyAddrzyAlign}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYYYYYYYz_mod_samo_addr_align71af067f49a8b506587ec718a5e1b7d2.tex}}}} + +\newcommand{\sailRISCVvalGetSedelegLoadAccessFault}{\saildoclabelled{sailRISCVzzygetzySedelegzyLoadzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sedeleg_load_access_faultac09796aa8cbf3a86b1fed3ecd8f3c88.tex}}}} + +\newcommand{\sailRISCVfnGetSedelegLoadAccessFault}{\saildoclabelled{sailRISCVfnzzygetzySedelegzyLoadzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sedeleg_load_access_faultac09796aa8cbf3a86b1fed3ecd8f3c88.tex}}}} + +\newcommand{\sailRISCVvalSetSedelegLoadAccessFault}{\saildoclabelled{sailRISCVzzysetzySedelegzyLoadzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sedeleg_load_access_fault3dcfaa698c0c375f65a901a1c187a93b.tex}}}} + +\newcommand{\sailRISCVfnSetSedelegLoadAccessFault}{\saildoclabelled{sailRISCVfnzzysetzySedelegzyLoadzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sedeleg_load_access_fault3dcfaa698c0c375f65a901a1c187a93b.tex}}}} + +\newcommand{\sailRISCVvalUpdateSedelegLoadAccessFault}{\saildoclabelled{sailRISCVzzyupdatezySedelegzyLoadzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sedeleg_load_access_fault6594e15b80693a22fb20ab7451df6720.tex}}}} + +\newcommand{\sailRISCVfnUpdateSedelegLoadAccessFault}{\saildoclabelled{sailRISCVfnzzyupdatezySedelegzyLoadzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sedeleg_load_access_fault6594e15b80693a22fb20ab7451df6720.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZZZZZZZupdateLoadAccessFault}{\saildoclabelled{sailRISCVoverloadZZZZZZZZZZzupdatezyLoadzyAccesszyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZZZZZZZzupdate_load_access_faultcc580699ff14ff7930c001851a1463b8.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAAAAAAAModLoadAccessFault}{\saildoclabelled{sailRISCVoverloadAAAAAAAAAAAzzymodzyLoadzyAccesszyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAAAAAAAz_mod_load_access_fault185ee80ec13fa3fdeb7c2cd3a76688c9.tex}}}} + +\newcommand{\sailRISCVvalGetSedelegLoadAddrAlign}{\saildoclabelled{sailRISCVzzygetzySedelegzyLoadzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sedeleg_load_addr_aligna36eb31e7e82330db9574602098e9a62.tex}}}} + +\newcommand{\sailRISCVfnGetSedelegLoadAddrAlign}{\saildoclabelled{sailRISCVfnzzygetzySedelegzyLoadzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sedeleg_load_addr_aligna36eb31e7e82330db9574602098e9a62.tex}}}} + +\newcommand{\sailRISCVvalSetSedelegLoadAddrAlign}{\saildoclabelled{sailRISCVzzysetzySedelegzyLoadzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sedeleg_load_addr_align3845e25f6585eadcab3b640d7c9d0c9a.tex}}}} + +\newcommand{\sailRISCVfnSetSedelegLoadAddrAlign}{\saildoclabelled{sailRISCVfnzzysetzySedelegzyLoadzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sedeleg_load_addr_align3845e25f6585eadcab3b640d7c9d0c9a.tex}}}} + +\newcommand{\sailRISCVvalUpdateSedelegLoadAddrAlign}{\saildoclabelled{sailRISCVzzyupdatezySedelegzyLoadzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sedeleg_load_addr_alignddc26fe8167315620c0f5b98d7cf6b8d.tex}}}} + +\newcommand{\sailRISCVfnUpdateSedelegLoadAddrAlign}{\saildoclabelled{sailRISCVfnzzyupdatezySedelegzyLoadzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sedeleg_load_addr_alignddc26fe8167315620c0f5b98d7cf6b8d.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBBBBBBBupdateLoadAddrAlign}{\saildoclabelled{sailRISCVoverloadBBBBBBBBBBBzupdatezyLoadzyAddrzyAlign}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBBBBBBBzupdate_load_addr_aligna304d90cb1ef10e79624a3324854bad0.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCCCCCCCModLoadAddrAlign}{\saildoclabelled{sailRISCVoverloadCCCCCCCCCCCzzymodzyLoadzyAddrzyAlign}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCCCCCCCz_mod_load_addr_align34e982fd800fd67969b64a5932439781.tex}}}} + +\newcommand{\sailRISCVvalGetSedelegBreakpoint}{\saildoclabelled{sailRISCVzzygetzySedelegzyBreakpoint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sedeleg_breakpointc77d25240c231ee118b1655024dfeea6.tex}}}} + +\newcommand{\sailRISCVfnGetSedelegBreakpoint}{\saildoclabelled{sailRISCVfnzzygetzySedelegzyBreakpoint}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sedeleg_breakpointc77d25240c231ee118b1655024dfeea6.tex}}}} + +\newcommand{\sailRISCVvalSetSedelegBreakpoint}{\saildoclabelled{sailRISCVzzysetzySedelegzyBreakpoint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sedeleg_breakpoint2acb469996a4630099a56b45b59c2861.tex}}}} + +\newcommand{\sailRISCVfnSetSedelegBreakpoint}{\saildoclabelled{sailRISCVfnzzysetzySedelegzyBreakpoint}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sedeleg_breakpoint2acb469996a4630099a56b45b59c2861.tex}}}} + +\newcommand{\sailRISCVvalUpdateSedelegBreakpoint}{\saildoclabelled{sailRISCVzzyupdatezySedelegzyBreakpoint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sedeleg_breakpoint4d1939da47af81029ca375f5c1c080e4.tex}}}} + +\newcommand{\sailRISCVfnUpdateSedelegBreakpoint}{\saildoclabelled{sailRISCVfnzzyupdatezySedelegzyBreakpoint}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sedeleg_breakpoint4d1939da47af81029ca375f5c1c080e4.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDDDDDDDDupdateBreakpoint}{\saildoclabelled{sailRISCVoverloadDDDDDDDDDDDzupdatezyBreakpoint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDDDDDDDDzupdate_breakpoint560b5628b33be91263dd76c1c88c6a06.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEEEEEEEEModBreakpoint}{\saildoclabelled{sailRISCVoverloadEEEEEEEEEEEzzymodzyBreakpoint}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEEEEEEEEz_mod_breakpointfb455863fb6768bbcbc1b984dbef6360.tex}}}} + +\newcommand{\sailRISCVvalGetSedelegIllegalInstr}{\saildoclabelled{sailRISCVzzygetzySedelegzyIllegalzyInstr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sedeleg_illegal_instrb6d9314c6ab6f5e95202046d9dfe0756.tex}}}} + +\newcommand{\sailRISCVfnGetSedelegIllegalInstr}{\saildoclabelled{sailRISCVfnzzygetzySedelegzyIllegalzyInstr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sedeleg_illegal_instrb6d9314c6ab6f5e95202046d9dfe0756.tex}}}} + +\newcommand{\sailRISCVvalSetSedelegIllegalInstr}{\saildoclabelled{sailRISCVzzysetzySedelegzyIllegalzyInstr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sedeleg_illegal_instrd248f17962068c21c567c4bc40790c19.tex}}}} + +\newcommand{\sailRISCVfnSetSedelegIllegalInstr}{\saildoclabelled{sailRISCVfnzzysetzySedelegzyIllegalzyInstr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sedeleg_illegal_instrd248f17962068c21c567c4bc40790c19.tex}}}} + +\newcommand{\sailRISCVvalUpdateSedelegIllegalInstr}{\saildoclabelled{sailRISCVzzyupdatezySedelegzyIllegalzyInstr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sedeleg_illegal_instr9f8eba51e2ce66c712c8a83a69cb47a0.tex}}}} + +\newcommand{\sailRISCVfnUpdateSedelegIllegalInstr}{\saildoclabelled{sailRISCVfnzzyupdatezySedelegzyIllegalzyInstr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sedeleg_illegal_instr9f8eba51e2ce66c712c8a83a69cb47a0.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFFFFFFFFupdateIllegalInstr}{\saildoclabelled{sailRISCVoverloadFFFFFFFFFFFzupdatezyIllegalzyInstr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFFFFFFFFzupdate_illegal_instr455fc8a1f0aa354556519de0f7b2c27b.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGGGGGGGGModIllegalInstr}{\saildoclabelled{sailRISCVoverloadGGGGGGGGGGGzzymodzyIllegalzyInstr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGGGGGGGGz_mod_illegal_instr52b43b228c609c9c311d02dfb920b702.tex}}}} + +\newcommand{\sailRISCVvalGetSedelegFetchAccessFault}{\saildoclabelled{sailRISCVzzygetzySedelegzyFetchzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sedeleg_fetch_access_faultf8861e3f9e14da4d59e7ab55d00a289b.tex}}}} + +\newcommand{\sailRISCVfnGetSedelegFetchAccessFault}{\saildoclabelled{sailRISCVfnzzygetzySedelegzyFetchzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sedeleg_fetch_access_faultf8861e3f9e14da4d59e7ab55d00a289b.tex}}}} + +\newcommand{\sailRISCVvalSetSedelegFetchAccessFault}{\saildoclabelled{sailRISCVzzysetzySedelegzyFetchzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sedeleg_fetch_access_fault193173c32591a593674fa8e5c0a550fc.tex}}}} + +\newcommand{\sailRISCVfnSetSedelegFetchAccessFault}{\saildoclabelled{sailRISCVfnzzysetzySedelegzyFetchzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sedeleg_fetch_access_fault193173c32591a593674fa8e5c0a550fc.tex}}}} + +\newcommand{\sailRISCVvalUpdateSedelegFetchAccessFault}{\saildoclabelled{sailRISCVzzyupdatezySedelegzyFetchzyAccesszyFault}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sedeleg_fetch_access_faultda711a3adc64706197c584b3f07a0e63.tex}}}} + +\newcommand{\sailRISCVfnUpdateSedelegFetchAccessFault}{\saildoclabelled{sailRISCVfnzzyupdatezySedelegzyFetchzyAccesszyFault}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sedeleg_fetch_access_faultda711a3adc64706197c584b3f07a0e63.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHHHHHHHHupdateFetchAccessFault}{\saildoclabelled{sailRISCVoverloadHHHHHHHHHHHzupdatezyFetchzyAccesszyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHHHHHHHHzupdate_fetch_access_faultf6d3ea38a5b206db76f3d15e6b293e4e.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIIIIIIIIModFetchAccessFault}{\saildoclabelled{sailRISCVoverloadIIIIIIIIIIIzzymodzyFetchzyAccesszyFault}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIIIIIIIIz_mod_fetch_access_fault2d0b00483619a1a634b37492d7e87b39.tex}}}} + +\newcommand{\sailRISCVvalGetSedelegFetchAddrAlign}{\saildoclabelled{sailRISCVzzygetzySedelegzyFetchzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sedeleg_fetch_addr_alignee0f20da19f67b8d187355d5547984ca.tex}}}} + +\newcommand{\sailRISCVfnGetSedelegFetchAddrAlign}{\saildoclabelled{sailRISCVfnzzygetzySedelegzyFetchzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sedeleg_fetch_addr_alignee0f20da19f67b8d187355d5547984ca.tex}}}} + +\newcommand{\sailRISCVvalSetSedelegFetchAddrAlign}{\saildoclabelled{sailRISCVzzysetzySedelegzyFetchzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sedeleg_fetch_addr_aligna2669337b650c15def12b3457ae83d4f.tex}}}} + +\newcommand{\sailRISCVfnSetSedelegFetchAddrAlign}{\saildoclabelled{sailRISCVfnzzysetzySedelegzyFetchzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sedeleg_fetch_addr_aligna2669337b650c15def12b3457ae83d4f.tex}}}} + +\newcommand{\sailRISCVvalUpdateSedelegFetchAddrAlign}{\saildoclabelled{sailRISCVzzyupdatezySedelegzyFetchzyAddrzyAlign}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sedeleg_fetch_addr_align57e1b55e0654637983d88a45a3d27115.tex}}}} + +\newcommand{\sailRISCVfnUpdateSedelegFetchAddrAlign}{\saildoclabelled{sailRISCVfnzzyupdatezySedelegzyFetchzyAddrzyAlign}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sedeleg_fetch_addr_align57e1b55e0654637983d88a45a3d27115.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJJJJJJJJupdateFetchAddrAlign}{\saildoclabelled{sailRISCVoverloadJJJJJJJJJJJzupdatezyFetchzyAddrzyAlign}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJJJJJJJJzupdate_fetch_addr_aligned5113ea584423e01fcb4b2781a3aeab.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKKKKKKKKModFetchAddrAlign}{\saildoclabelled{sailRISCVoverloadKKKKKKKKKKKzzymodzyFetchzyAddrzyAlign}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKKKKKKKKz_mod_fetch_addr_align94e1ec62c225ae16e8fbc401efa25352.tex}}}} + +\newcommand{\sailRISCVvallegalizzeSedeleg}{\saildoclabelled{sailRISCVzlegalizzezysedeleg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_sedelegd33e4c93e76af1c9ae6a7795974dbcc3.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeSedeleg}{\saildoclabelled{sailRISCVfnzlegalizzezysedeleg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_sedelegd33e4c93e76af1c9ae6a7795974dbcc3.tex}}}} + +\newcommand{\sailRISCVtypeSinterrupts}{\saildoclabelled{sailRISCVtypezSinterrupts}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsinterrupts37e2ae8cbcb085a9455d8333ab820af3.tex}}}} + +\newcommand{\sailRISCVvalMkSinterrupts}{\saildoclabelled{sailRISCVzMkzySinterrupts}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_sinterrupts50ead85256a5e42901dcc54cd50f0280.tex}}}} + +\newcommand{\sailRISCVfnMkSinterrupts}{\saildoclabelled{sailRISCVfnzMkzySinterrupts}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_sinterrupts50ead85256a5e42901dcc54cd50f0280.tex}}}} + +\newcommand{\sailRISCVvalGetSinterruptsBits}{\saildoclabelled{sailRISCVzzygetzySinterruptszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sinterrupts_bits890ab2f21b741ac095ede551b06b14b0.tex}}}} + +\newcommand{\sailRISCVfnGetSinterruptsBits}{\saildoclabelled{sailRISCVfnzzygetzySinterruptszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sinterrupts_bits890ab2f21b741ac095ede551b06b14b0.tex}}}} + +\newcommand{\sailRISCVvalSetSinterruptsBits}{\saildoclabelled{sailRISCVzzysetzySinterruptszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sinterrupts_bits11d675c3310ec7be4b053dce213f9e13.tex}}}} + +\newcommand{\sailRISCVfnSetSinterruptsBits}{\saildoclabelled{sailRISCVfnzzysetzySinterruptszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sinterrupts_bits11d675c3310ec7be4b053dce213f9e13.tex}}}} + +\newcommand{\sailRISCVvalUpdateSinterruptsBits}{\saildoclabelled{sailRISCVzzyupdatezySinterruptszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sinterrupts_bitsb82a5eaca518d7033ee5b65b76de6fc3.tex}}}} + +\newcommand{\sailRISCVfnUpdateSinterruptsBits}{\saildoclabelled{sailRISCVfnzzyupdatezySinterruptszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sinterrupts_bitsb82a5eaca518d7033ee5b65b76de6fc3.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLLLLLLLLupdateBits}{\saildoclabelled{sailRISCVoverloadLLLLLLLLLLLzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLLLLLLLLzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMMMMMMMMModBits}{\saildoclabelled{sailRISCVoverloadMMMMMMMMMMMzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMMMMMMMMz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSinterruptsSEI}{\saildoclabelled{sailRISCVzzygetzySinterruptszySEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sinterrupts_sei5458488d503712b6667d489b56acd5e1.tex}}}} + +\newcommand{\sailRISCVfnGetSinterruptsSEI}{\saildoclabelled{sailRISCVfnzzygetzySinterruptszySEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sinterrupts_sei5458488d503712b6667d489b56acd5e1.tex}}}} + +\newcommand{\sailRISCVvalSetSinterruptsSEI}{\saildoclabelled{sailRISCVzzysetzySinterruptszySEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sinterrupts_seid1a27b6ed01fc08d7ed92e7473ca0c67.tex}}}} + +\newcommand{\sailRISCVfnSetSinterruptsSEI}{\saildoclabelled{sailRISCVfnzzysetzySinterruptszySEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sinterrupts_seid1a27b6ed01fc08d7ed92e7473ca0c67.tex}}}} + +\newcommand{\sailRISCVvalUpdateSinterruptsSEI}{\saildoclabelled{sailRISCVzzyupdatezySinterruptszySEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sinterrupts_seidfae2f173d12134865a23f8b06b92d56.tex}}}} + +\newcommand{\sailRISCVfnUpdateSinterruptsSEI}{\saildoclabelled{sailRISCVfnzzyupdatezySinterruptszySEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sinterrupts_seidfae2f173d12134865a23f8b06b92d56.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNNNNNNNNupdateSEI}{\saildoclabelled{sailRISCVoverloadNNNNNNNNNNNzupdatezySEI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNNNNNNNNzupdate_seif1998ef482e23699637a58efcff9cf08.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOOOOOOOOModSEI}{\saildoclabelled{sailRISCVoverloadOOOOOOOOOOOzzymodzySEI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOOOOOOOOz_mod_sei769b57e17c0057e7ca956b7721915a2e.tex}}}} + +\newcommand{\sailRISCVvalGetSinterruptsUEI}{\saildoclabelled{sailRISCVzzygetzySinterruptszyUEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sinterrupts_uei29ec1fbe91082e4eaef04b2891fe1177.tex}}}} + +\newcommand{\sailRISCVfnGetSinterruptsUEI}{\saildoclabelled{sailRISCVfnzzygetzySinterruptszyUEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sinterrupts_uei29ec1fbe91082e4eaef04b2891fe1177.tex}}}} + +\newcommand{\sailRISCVvalSetSinterruptsUEI}{\saildoclabelled{sailRISCVzzysetzySinterruptszyUEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sinterrupts_ueid6db53e4645f60442d748c9717159555.tex}}}} + +\newcommand{\sailRISCVfnSetSinterruptsUEI}{\saildoclabelled{sailRISCVfnzzysetzySinterruptszyUEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sinterrupts_ueid6db53e4645f60442d748c9717159555.tex}}}} + +\newcommand{\sailRISCVvalUpdateSinterruptsUEI}{\saildoclabelled{sailRISCVzzyupdatezySinterruptszyUEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sinterrupts_uei4e9add8c9d8edc1f50674d5eb879d669.tex}}}} + +\newcommand{\sailRISCVfnUpdateSinterruptsUEI}{\saildoclabelled{sailRISCVfnzzyupdatezySinterruptszyUEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sinterrupts_uei4e9add8c9d8edc1f50674d5eb879d669.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPPPPPPPPupdateUEI}{\saildoclabelled{sailRISCVoverloadPPPPPPPPPPPzupdatezyUEI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPPPPPPPPzupdate_uei8252f0ae84161aa560a37211f39d1461.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQQQQQQQQModUEI}{\saildoclabelled{sailRISCVoverloadQQQQQQQQQQQzzymodzyUEI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQQQQQQQQz_mod_uei7faef47ef8aacd0d1b2ad1e0530fdf8e.tex}}}} + +\newcommand{\sailRISCVvalGetSinterruptsSTI}{\saildoclabelled{sailRISCVzzygetzySinterruptszySTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sinterrupts_sti9ba6390e5ddbefa9f37ab560c671354e.tex}}}} + +\newcommand{\sailRISCVfnGetSinterruptsSTI}{\saildoclabelled{sailRISCVfnzzygetzySinterruptszySTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sinterrupts_sti9ba6390e5ddbefa9f37ab560c671354e.tex}}}} + +\newcommand{\sailRISCVvalSetSinterruptsSTI}{\saildoclabelled{sailRISCVzzysetzySinterruptszySTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sinterrupts_sti6ee1684f0baef5e2b4c1b77cfad5548a.tex}}}} + +\newcommand{\sailRISCVfnSetSinterruptsSTI}{\saildoclabelled{sailRISCVfnzzysetzySinterruptszySTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sinterrupts_sti6ee1684f0baef5e2b4c1b77cfad5548a.tex}}}} + +\newcommand{\sailRISCVvalUpdateSinterruptsSTI}{\saildoclabelled{sailRISCVzzyupdatezySinterruptszySTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sinterrupts_sti3fd7347767c86ca33481e1dbc90ce93c.tex}}}} + +\newcommand{\sailRISCVfnUpdateSinterruptsSTI}{\saildoclabelled{sailRISCVfnzzyupdatezySinterruptszySTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sinterrupts_sti3fd7347767c86ca33481e1dbc90ce93c.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRRRRRRRRupdateSTI}{\saildoclabelled{sailRISCVoverloadRRRRRRRRRRRzupdatezySTI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRRRRRRRRzupdate_stibc2608b6e320f416ad08499be50228f8.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSSSSSSSSModSTI}{\saildoclabelled{sailRISCVoverloadSSSSSSSSSSSzzymodzySTI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSSSSSSSSz_mod_sti42df95a06ca2a120a19277cb17015a3f.tex}}}} + +\newcommand{\sailRISCVvalGetSinterruptsUTI}{\saildoclabelled{sailRISCVzzygetzySinterruptszyUTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sinterrupts_utiecf1d7ffb74e287dbae46219d8f856cb.tex}}}} + +\newcommand{\sailRISCVfnGetSinterruptsUTI}{\saildoclabelled{sailRISCVfnzzygetzySinterruptszyUTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sinterrupts_utiecf1d7ffb74e287dbae46219d8f856cb.tex}}}} + +\newcommand{\sailRISCVvalSetSinterruptsUTI}{\saildoclabelled{sailRISCVzzysetzySinterruptszyUTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sinterrupts_utid6108a193d51614aeb91d29cae7b52d4.tex}}}} + +\newcommand{\sailRISCVfnSetSinterruptsUTI}{\saildoclabelled{sailRISCVfnzzysetzySinterruptszyUTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sinterrupts_utid6108a193d51614aeb91d29cae7b52d4.tex}}}} + +\newcommand{\sailRISCVvalUpdateSinterruptsUTI}{\saildoclabelled{sailRISCVzzyupdatezySinterruptszyUTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sinterrupts_uti76436fc7f8e1e46117a090613db49900.tex}}}} + +\newcommand{\sailRISCVfnUpdateSinterruptsUTI}{\saildoclabelled{sailRISCVfnzzyupdatezySinterruptszyUTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sinterrupts_uti76436fc7f8e1e46117a090613db49900.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTTTTTTTTupdateUTI}{\saildoclabelled{sailRISCVoverloadTTTTTTTTTTTzupdatezyUTI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTTTTTTTTzupdate_uti7bb127f84633c2b4f4b4de5582168ddf.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUUUUUUUUModUTI}{\saildoclabelled{sailRISCVoverloadUUUUUUUUUUUzzymodzyUTI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUUUUUUUUz_mod_utia23224af950fbe7be4b3db2f7092e6b4.tex}}}} + +\newcommand{\sailRISCVvalGetSinterruptsSSI}{\saildoclabelled{sailRISCVzzygetzySinterruptszySSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sinterrupts_ssi240024e06c4365a8f0ed4ba1b36afb6c.tex}}}} + +\newcommand{\sailRISCVfnGetSinterruptsSSI}{\saildoclabelled{sailRISCVfnzzygetzySinterruptszySSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sinterrupts_ssi240024e06c4365a8f0ed4ba1b36afb6c.tex}}}} + +\newcommand{\sailRISCVvalSetSinterruptsSSI}{\saildoclabelled{sailRISCVzzysetzySinterruptszySSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sinterrupts_ssi34d088bb8c03bd9774e94278832e9c78.tex}}}} + +\newcommand{\sailRISCVfnSetSinterruptsSSI}{\saildoclabelled{sailRISCVfnzzysetzySinterruptszySSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sinterrupts_ssi34d088bb8c03bd9774e94278832e9c78.tex}}}} + +\newcommand{\sailRISCVvalUpdateSinterruptsSSI}{\saildoclabelled{sailRISCVzzyupdatezySinterruptszySSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sinterrupts_ssi41e461cfb1d80cf6497915184ac067fe.tex}}}} + +\newcommand{\sailRISCVfnUpdateSinterruptsSSI}{\saildoclabelled{sailRISCVfnzzyupdatezySinterruptszySSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sinterrupts_ssi41e461cfb1d80cf6497915184ac067fe.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVVVVVVVVupdateSSI}{\saildoclabelled{sailRISCVoverloadVVVVVVVVVVVzupdatezySSI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVVVVVVVVzupdate_ssi5471fd96e5b7a8471f1ef66b598501a9.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWWWWWWWWModSSI}{\saildoclabelled{sailRISCVoverloadWWWWWWWWWWWzzymodzySSI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWWWWWWWWz_mod_ssicb14ae48c26ad162228aa44069530c95.tex}}}} + +\newcommand{\sailRISCVvalGetSinterruptsUSI}{\saildoclabelled{sailRISCVzzygetzySinterruptszyUSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sinterrupts_usidbf3fbc5878b2118ded205939499c8c9.tex}}}} + +\newcommand{\sailRISCVfnGetSinterruptsUSI}{\saildoclabelled{sailRISCVfnzzygetzySinterruptszyUSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sinterrupts_usidbf3fbc5878b2118ded205939499c8c9.tex}}}} + +\newcommand{\sailRISCVvalSetSinterruptsUSI}{\saildoclabelled{sailRISCVzzysetzySinterruptszyUSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sinterrupts_usi4837f15564ed5aede9a0c1c6ed9d89c6.tex}}}} + +\newcommand{\sailRISCVfnSetSinterruptsUSI}{\saildoclabelled{sailRISCVfnzzysetzySinterruptszyUSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sinterrupts_usi4837f15564ed5aede9a0c1c6ed9d89c6.tex}}}} + +\newcommand{\sailRISCVvalUpdateSinterruptsUSI}{\saildoclabelled{sailRISCVzzyupdatezySinterruptszyUSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sinterrupts_usia415b4e062e30257cfefa06256955512.tex}}}} + +\newcommand{\sailRISCVfnUpdateSinterruptsUSI}{\saildoclabelled{sailRISCVfnzzyupdatezySinterruptszyUSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sinterrupts_usia415b4e062e30257cfefa06256955512.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXXXXXXXXupdateUSI}{\saildoclabelled{sailRISCVoverloadXXXXXXXXXXXzupdatezyUSI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXXXXXXXXzupdate_usi3c691c58ab628cbd10b9e21b62e0cfc4.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYYYYYYYYModUSI}{\saildoclabelled{sailRISCVoverloadYYYYYYYYYYYzzymodzyUSI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYYYYYYYYz_mod_usif3c3aecb7417cc350ad372adfb40e4d3.tex}}}} + +\newcommand{\sailRISCVvallowerMip}{\saildoclabelled{sailRISCVzlowerzymip}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlower_mip782f0e78d1db1ca14e49fae5b84aab3a.tex}}}} + +\newcommand{\sailRISCVfnlowerMip}{\saildoclabelled{sailRISCVfnzlowerzymip}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlower_mip782f0e78d1db1ca14e49fae5b84aab3a.tex}}}} + +\newcommand{\sailRISCVvallowerMie}{\saildoclabelled{sailRISCVzlowerzymie}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlower_mie31369302ff2457befa23f7f9d54a6b02.tex}}}} + +\newcommand{\sailRISCVfnlowerMie}{\saildoclabelled{sailRISCVfnzlowerzymie}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlower_mie31369302ff2457befa23f7f9d54a6b02.tex}}}} + +\newcommand{\sailRISCVvalliftSip}{\saildoclabelled{sailRISCVzliftzysip}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlift_sip492375a8cff775f29029156b44dfe1bf.tex}}}} + +\newcommand{\sailRISCVfnliftSip}{\saildoclabelled{sailRISCVfnzliftzysip}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlift_sip492375a8cff775f29029156b44dfe1bf.tex}}}} + +\newcommand{\sailRISCVvallegalizzeSip}{\saildoclabelled{sailRISCVzlegalizzezysip}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_sip8870e10af087ca0981c61bf7bdfe8175.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeSip}{\saildoclabelled{sailRISCVfnzlegalizzezysip}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_sip8870e10af087ca0981c61bf7bdfe8175.tex}}}} + +\newcommand{\sailRISCVvalliftSie}{\saildoclabelled{sailRISCVzliftzysie}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlift_sie0866dcb30be948749bf6a401d4f6594e.tex}}}} + +\newcommand{\sailRISCVfnliftSie}{\saildoclabelled{sailRISCVfnzliftzysie}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlift_sie0866dcb30be948749bf6a401d4f6594e.tex}}}} + +\newcommand{\sailRISCVvallegalizzeSie}{\saildoclabelled{sailRISCVzlegalizzezysie}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_sie49baa5a30e7d5365e2d6c1dc23c7686d.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeSie}{\saildoclabelled{sailRISCVfnzlegalizzezysie}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_sie49baa5a30e7d5365e2d6c1dc23c7686d.tex}}}} + +\newcommand{\sailRISCVtypeSatpSixFour}{\saildoclabelled{sailRISCVtypezSatp64}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsatp64bc81c51aa01ca27913d2b0a8ed23d481.tex}}}} + +\newcommand{\sailRISCVvalMkSatpSixFour}{\saildoclabelled{sailRISCVzMkzySatp64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_satp64329969f3c15112d031d796680dc02dba.tex}}}} + +\newcommand{\sailRISCVfnMkSatpSixFour}{\saildoclabelled{sailRISCVfnzMkzySatp64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_satp64329969f3c15112d031d796680dc02dba.tex}}}} + +\newcommand{\sailRISCVvalGetSatpSixFourBits}{\saildoclabelled{sailRISCVzzygetzySatp64zybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_satp64_bitsdb6de00ddfe8eefd1a814354aac4a548.tex}}}} + +\newcommand{\sailRISCVfnGetSatpSixFourBits}{\saildoclabelled{sailRISCVfnzzygetzySatp64zybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_satp64_bitsdb6de00ddfe8eefd1a814354aac4a548.tex}}}} + +\newcommand{\sailRISCVvalSetSatpSixFourBits}{\saildoclabelled{sailRISCVzzysetzySatp64zybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_satp64_bits1ef37f6f328908e0dfa046d4c516d3b7.tex}}}} + +\newcommand{\sailRISCVfnSetSatpSixFourBits}{\saildoclabelled{sailRISCVfnzzysetzySatp64zybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_satp64_bits1ef37f6f328908e0dfa046d4c516d3b7.tex}}}} + +\newcommand{\sailRISCVvalUpdateSatpSixFourBits}{\saildoclabelled{sailRISCVzzyupdatezySatp64zybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_satp64_bits2b386da295e07d09d86a4906f50a6dcf.tex}}}} + +\newcommand{\sailRISCVfnUpdateSatpSixFourBits}{\saildoclabelled{sailRISCVfnzzyupdatezySatp64zybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_satp64_bits2b386da295e07d09d86a4906f50a6dcf.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZZZZZZZZupdateBits}{\saildoclabelled{sailRISCVoverloadZZZZZZZZZZZzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZZZZZZZZzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAAAAAAAAModBits}{\saildoclabelled{sailRISCVoverloadAAAAAAAAAAAAzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAAAAAAAAz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSatpSixFourMode}{\saildoclabelled{sailRISCVzzygetzySatp64zyMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_satp64_mode5542c94fbfcb40171b429bef968a7954.tex}}}} + +\newcommand{\sailRISCVfnGetSatpSixFourMode}{\saildoclabelled{sailRISCVfnzzygetzySatp64zyMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_satp64_mode5542c94fbfcb40171b429bef968a7954.tex}}}} + +\newcommand{\sailRISCVvalSetSatpSixFourMode}{\saildoclabelled{sailRISCVzzysetzySatp64zyMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_satp64_modedd62965c996bac9cb96fa44094dbf974.tex}}}} + +\newcommand{\sailRISCVfnSetSatpSixFourMode}{\saildoclabelled{sailRISCVfnzzysetzySatp64zyMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_satp64_modedd62965c996bac9cb96fa44094dbf974.tex}}}} + +\newcommand{\sailRISCVvalUpdateSatpSixFourMode}{\saildoclabelled{sailRISCVzzyupdatezySatp64zyMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_satp64_modef6a327a4e9deddb4a58d5af1293fb1e4.tex}}}} + +\newcommand{\sailRISCVfnUpdateSatpSixFourMode}{\saildoclabelled{sailRISCVfnzzyupdatezySatp64zyMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_satp64_modef6a327a4e9deddb4a58d5af1293fb1e4.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBBBBBBBBupdateMode}{\saildoclabelled{sailRISCVoverloadBBBBBBBBBBBBzupdatezyMode}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBBBBBBBBzupdate_modea8b179bc2887fad34e9a3f8cefc9cf29.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCCCCCCCCModMode}{\saildoclabelled{sailRISCVoverloadCCCCCCCCCCCCzzymodzyMode}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCCCCCCCCz_mod_mode7dda808a114a5634018c73fc24f43140.tex}}}} + +\newcommand{\sailRISCVvalGetSatpSixFourAsid}{\saildoclabelled{sailRISCVzzygetzySatp64zyAsid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_satp64_asid5a55ab259b6bd85453ad8708a0fb485a.tex}}}} + +\newcommand{\sailRISCVfnGetSatpSixFourAsid}{\saildoclabelled{sailRISCVfnzzygetzySatp64zyAsid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_satp64_asid5a55ab259b6bd85453ad8708a0fb485a.tex}}}} + +\newcommand{\sailRISCVvalSetSatpSixFourAsid}{\saildoclabelled{sailRISCVzzysetzySatp64zyAsid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_satp64_asid2ddaf59d37788d7a3a27cef76891dfb8.tex}}}} + +\newcommand{\sailRISCVfnSetSatpSixFourAsid}{\saildoclabelled{sailRISCVfnzzysetzySatp64zyAsid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_satp64_asid2ddaf59d37788d7a3a27cef76891dfb8.tex}}}} + +\newcommand{\sailRISCVvalUpdateSatpSixFourAsid}{\saildoclabelled{sailRISCVzzyupdatezySatp64zyAsid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_satp64_asid4587433548bd071c272c301c9b049f40.tex}}}} + +\newcommand{\sailRISCVfnUpdateSatpSixFourAsid}{\saildoclabelled{sailRISCVfnzzyupdatezySatp64zyAsid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_satp64_asid4587433548bd071c272c301c9b049f40.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDDDDDDDDDupdateAsid}{\saildoclabelled{sailRISCVoverloadDDDDDDDDDDDDzupdatezyAsid}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDDDDDDDDDzupdate_asid5cc334067dcbe9c9a4eb59266b7b5404.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEEEEEEEEEModAsid}{\saildoclabelled{sailRISCVoverloadEEEEEEEEEEEEzzymodzyAsid}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEEEEEEEEEz_mod_asid55036e3f51de771bc07215ff1caec750.tex}}}} + +\newcommand{\sailRISCVvalGetSatpSixFourPPN}{\saildoclabelled{sailRISCVzzygetzySatp64zyPPN}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_satp64_ppn5c0b704bfa56e2113c29e0d13f46b734.tex}}}} + +\newcommand{\sailRISCVfnGetSatpSixFourPPN}{\saildoclabelled{sailRISCVfnzzygetzySatp64zyPPN}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_satp64_ppn5c0b704bfa56e2113c29e0d13f46b734.tex}}}} + +\newcommand{\sailRISCVvalSetSatpSixFourPPN}{\saildoclabelled{sailRISCVzzysetzySatp64zyPPN}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_satp64_ppn31d9614063b4541d68753b5e3090b133.tex}}}} + +\newcommand{\sailRISCVfnSetSatpSixFourPPN}{\saildoclabelled{sailRISCVfnzzysetzySatp64zyPPN}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_satp64_ppn31d9614063b4541d68753b5e3090b133.tex}}}} + +\newcommand{\sailRISCVvalUpdateSatpSixFourPPN}{\saildoclabelled{sailRISCVzzyupdatezySatp64zyPPN}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_satp64_ppne5381a5ff516a83023a3ab6b001812ea.tex}}}} + +\newcommand{\sailRISCVfnUpdateSatpSixFourPPN}{\saildoclabelled{sailRISCVfnzzyupdatezySatp64zyPPN}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_satp64_ppne5381a5ff516a83023a3ab6b001812ea.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFFFFFFFFFupdatePPN}{\saildoclabelled{sailRISCVoverloadFFFFFFFFFFFFzupdatezyPPN}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFFFFFFFFFzupdate_ppn97bb9a526eb6125397ee215b375879df.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGGGGGGGGGModPPN}{\saildoclabelled{sailRISCVoverloadGGGGGGGGGGGGzzymodzyPPN}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGGGGGGGGGz_mod_ppne431ce60abd1029c297cc5814bcb183d.tex}}}} + +\newcommand{\sailRISCVvallegalizzeSatpSixFour}{\saildoclabelled{sailRISCVzlegalizzezysatp64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_satp64c07dfcb94af8010eb535b5f77fbb8614.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeSatpSixFour}{\saildoclabelled{sailRISCVfnzlegalizzezysatp64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_satp64c07dfcb94af8010eb535b5f77fbb8614.tex}}}} + +\newcommand{\sailRISCVtypeSatpThreeTwo}{\saildoclabelled{sailRISCVtypezSatp32}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsatp321d6ed78cf9005ac8e6444a423cd6e618.tex}}}} + +\newcommand{\sailRISCVvalMkSatpThreeTwo}{\saildoclabelled{sailRISCVzMkzySatp32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_satp322e54e0b7f463382f08c680a0164f0a0d.tex}}}} + +\newcommand{\sailRISCVfnMkSatpThreeTwo}{\saildoclabelled{sailRISCVfnzMkzySatp32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_satp322e54e0b7f463382f08c680a0164f0a0d.tex}}}} + +\newcommand{\sailRISCVvalGetSatpThreeTwoBits}{\saildoclabelled{sailRISCVzzygetzySatp32zybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_satp32_bits4ef2050c8a62cb83e3a3f48d91f2a8d8.tex}}}} + +\newcommand{\sailRISCVfnGetSatpThreeTwoBits}{\saildoclabelled{sailRISCVfnzzygetzySatp32zybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_satp32_bits4ef2050c8a62cb83e3a3f48d91f2a8d8.tex}}}} + +\newcommand{\sailRISCVvalSetSatpThreeTwoBits}{\saildoclabelled{sailRISCVzzysetzySatp32zybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_satp32_bits1d19cd20b80cea73ba6dc6c4919c83bd.tex}}}} + +\newcommand{\sailRISCVfnSetSatpThreeTwoBits}{\saildoclabelled{sailRISCVfnzzysetzySatp32zybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_satp32_bits1d19cd20b80cea73ba6dc6c4919c83bd.tex}}}} + +\newcommand{\sailRISCVvalUpdateSatpThreeTwoBits}{\saildoclabelled{sailRISCVzzyupdatezySatp32zybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_satp32_bits040735762104e2eb7ee468b2c73a3376.tex}}}} + +\newcommand{\sailRISCVfnUpdateSatpThreeTwoBits}{\saildoclabelled{sailRISCVfnzzyupdatezySatp32zybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_satp32_bits040735762104e2eb7ee468b2c73a3376.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHHHHHHHHHupdateBits}{\saildoclabelled{sailRISCVoverloadHHHHHHHHHHHHzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHHHHHHHHHzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIIIIIIIIIModBits}{\saildoclabelled{sailRISCVoverloadIIIIIIIIIIIIzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIIIIIIIIIz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSatpThreeTwoMode}{\saildoclabelled{sailRISCVzzygetzySatp32zyMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_satp32_modeb053b6b63fe63dd46382110a8b594bfd.tex}}}} + +\newcommand{\sailRISCVfnGetSatpThreeTwoMode}{\saildoclabelled{sailRISCVfnzzygetzySatp32zyMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_satp32_modeb053b6b63fe63dd46382110a8b594bfd.tex}}}} + +\newcommand{\sailRISCVvalSetSatpThreeTwoMode}{\saildoclabelled{sailRISCVzzysetzySatp32zyMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_satp32_mode92a8ae476bd67a0a5ff16c383b2067ca.tex}}}} + +\newcommand{\sailRISCVfnSetSatpThreeTwoMode}{\saildoclabelled{sailRISCVfnzzysetzySatp32zyMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_satp32_mode92a8ae476bd67a0a5ff16c383b2067ca.tex}}}} + +\newcommand{\sailRISCVvalUpdateSatpThreeTwoMode}{\saildoclabelled{sailRISCVzzyupdatezySatp32zyMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_satp32_modeeff3936a1c725a7de10614f5e8bbdc94.tex}}}} + +\newcommand{\sailRISCVfnUpdateSatpThreeTwoMode}{\saildoclabelled{sailRISCVfnzzyupdatezySatp32zyMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_satp32_modeeff3936a1c725a7de10614f5e8bbdc94.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJJJJJJJJJupdateMode}{\saildoclabelled{sailRISCVoverloadJJJJJJJJJJJJzupdatezyMode}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJJJJJJJJJzupdate_modea8b179bc2887fad34e9a3f8cefc9cf29.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKKKKKKKKKModMode}{\saildoclabelled{sailRISCVoverloadKKKKKKKKKKKKzzymodzyMode}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKKKKKKKKKz_mod_mode7dda808a114a5634018c73fc24f43140.tex}}}} + +\newcommand{\sailRISCVvalGetSatpThreeTwoAsid}{\saildoclabelled{sailRISCVzzygetzySatp32zyAsid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_satp32_asid79b89125e014e4824b79940178c13320.tex}}}} + +\newcommand{\sailRISCVfnGetSatpThreeTwoAsid}{\saildoclabelled{sailRISCVfnzzygetzySatp32zyAsid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_satp32_asid79b89125e014e4824b79940178c13320.tex}}}} + +\newcommand{\sailRISCVvalSetSatpThreeTwoAsid}{\saildoclabelled{sailRISCVzzysetzySatp32zyAsid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_satp32_asid1e472f8b9d87ee7ce4dc47786138f7af.tex}}}} + +\newcommand{\sailRISCVfnSetSatpThreeTwoAsid}{\saildoclabelled{sailRISCVfnzzysetzySatp32zyAsid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_satp32_asid1e472f8b9d87ee7ce4dc47786138f7af.tex}}}} + +\newcommand{\sailRISCVvalUpdateSatpThreeTwoAsid}{\saildoclabelled{sailRISCVzzyupdatezySatp32zyAsid}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_satp32_asid4a10333ee9adcd6b560d2b22f799b1c2.tex}}}} + +\newcommand{\sailRISCVfnUpdateSatpThreeTwoAsid}{\saildoclabelled{sailRISCVfnzzyupdatezySatp32zyAsid}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_satp32_asid4a10333ee9adcd6b560d2b22f799b1c2.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLLLLLLLLLupdateAsid}{\saildoclabelled{sailRISCVoverloadLLLLLLLLLLLLzupdatezyAsid}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLLLLLLLLLzupdate_asid5cc334067dcbe9c9a4eb59266b7b5404.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMMMMMMMMMModAsid}{\saildoclabelled{sailRISCVoverloadMMMMMMMMMMMMzzymodzyAsid}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMMMMMMMMMz_mod_asid55036e3f51de771bc07215ff1caec750.tex}}}} + +\newcommand{\sailRISCVvalGetSatpThreeTwoPPN}{\saildoclabelled{sailRISCVzzygetzySatp32zyPPN}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_satp32_ppn09e489a7e17eb50d41a060c4cfdf4452.tex}}}} + +\newcommand{\sailRISCVfnGetSatpThreeTwoPPN}{\saildoclabelled{sailRISCVfnzzygetzySatp32zyPPN}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_satp32_ppn09e489a7e17eb50d41a060c4cfdf4452.tex}}}} + +\newcommand{\sailRISCVvalSetSatpThreeTwoPPN}{\saildoclabelled{sailRISCVzzysetzySatp32zyPPN}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_satp32_ppne026770b9c95405e7d420506a450e1f8.tex}}}} + +\newcommand{\sailRISCVfnSetSatpThreeTwoPPN}{\saildoclabelled{sailRISCVfnzzysetzySatp32zyPPN}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_satp32_ppne026770b9c95405e7d420506a450e1f8.tex}}}} + +\newcommand{\sailRISCVvalUpdateSatpThreeTwoPPN}{\saildoclabelled{sailRISCVzzyupdatezySatp32zyPPN}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_satp32_ppnfdc6c798de82ace5c37372a64d41dbd8.tex}}}} + +\newcommand{\sailRISCVfnUpdateSatpThreeTwoPPN}{\saildoclabelled{sailRISCVfnzzyupdatezySatp32zyPPN}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_satp32_ppnfdc6c798de82ace5c37372a64d41dbd8.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNNNNNNNNNupdatePPN}{\saildoclabelled{sailRISCVoverloadNNNNNNNNNNNNzupdatezyPPN}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNNNNNNNNNzupdate_ppn97bb9a526eb6125397ee215b375879df.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOOOOOOOOOModPPN}{\saildoclabelled{sailRISCVoverloadOOOOOOOOOOOOzzymodzyPPN}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOOOOOOOOOz_mod_ppne431ce60abd1029c297cc5814bcb183d.tex}}}} + +\newcommand{\sailRISCVvallegalizzeSatpThreeTwo}{\saildoclabelled{sailRISCVzlegalizzezysatp32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_satp32b15f7b0d2d9380033f3e1b09fe370a61.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeSatpThreeTwo}{\saildoclabelled{sailRISCVfnzlegalizzezysatp32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_satp32b15f7b0d2d9380033f3e1b09fe370a61.tex}}}} + +\newcommand{\sailRISCVtypePmpAddrMatchType}{\saildoclabelled{sailRISCVtypezPmpAddrMatchType}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpmpaddrmatchtype51c8a34448b8f2bea86b1b88c958b458.tex}}}} + +\newcommand{\sailRISCVvalPmpAddrMatchTypeOfNum}{\saildoclabelled{sailRISCVzPmpAddrMatchTypezyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpaddrmatchtype_of_num05d549dd7f3bf4d35f3c38ea6a015bf3.tex}}}} + +\newcommand{\sailRISCVfnPmpAddrMatchTypeOfNum}{\saildoclabelled{sailRISCVfnzPmpAddrMatchTypezyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpaddrmatchtype_of_num05d549dd7f3bf4d35f3c38ea6a015bf3.tex}}}} + +\newcommand{\sailRISCVvalnumOfPmpAddrMatchType}{\saildoclabelled{sailRISCVznumzyofzyPmpAddrMatchType}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_pmpaddrmatchtypee330d16c3db664232af948049b8edeb9.tex}}}} + +\newcommand{\sailRISCVfnnumOfPmpAddrMatchType}{\saildoclabelled{sailRISCVfnznumzyofzyPmpAddrMatchType}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_pmpaddrmatchtypee330d16c3db664232af948049b8edeb9.tex}}}} + +\newcommand{\sailRISCVvalpmpAddrMatchTypeOfBits}{\saildoclabelled{sailRISCVzpmpAddrMatchTypezyofzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpaddrmatchtype_of_bits8b4e245ce3d01f111a1f89404623ac98.tex}}}} + +\newcommand{\sailRISCVfnpmpAddrMatchTypeOfBits}{\saildoclabelled{sailRISCVfnzpmpAddrMatchTypezyofzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpaddrmatchtype_of_bits8b4e245ce3d01f111a1f89404623ac98.tex}}}} + +\newcommand{\sailRISCVvalpmpAddrMatchTypeToBits}{\saildoclabelled{sailRISCVzpmpAddrMatchTypezytozybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpaddrmatchtype_to_bitsd16d593c276e8bc21809612105ac8913.tex}}}} + +\newcommand{\sailRISCVfnpmpAddrMatchTypeToBits}{\saildoclabelled{sailRISCVfnzpmpAddrMatchTypezytozybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpaddrmatchtype_to_bitsd16d593c276e8bc21809612105ac8913.tex}}}} + +\newcommand{\sailRISCVtypePmpcfgEnt}{\saildoclabelled{sailRISCVtypezPmpcfgzyent}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpmpcfg_entf1f5c95dff6dbc5296f79013fd3eda09.tex}}}} + +\newcommand{\sailRISCVvalMkPmpcfgEnt}{\saildoclabelled{sailRISCVzMkzyPmpcfgzyent}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_pmpcfg_ent3c5800ef8bd6fce928dfecddb43bbdaf.tex}}}} + +\newcommand{\sailRISCVfnMkPmpcfgEnt}{\saildoclabelled{sailRISCVfnzMkzyPmpcfgzyent}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_pmpcfg_ent3c5800ef8bd6fce928dfecddb43bbdaf.tex}}}} + +\newcommand{\sailRISCVvalGetPmpcfgEntBits}{\saildoclabelled{sailRISCVzzygetzyPmpcfgzyentzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pmpcfg_ent_bits548ab0717907b301f5b9c16399b10032.tex}}}} + +\newcommand{\sailRISCVfnGetPmpcfgEntBits}{\saildoclabelled{sailRISCVfnzzygetzyPmpcfgzyentzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pmpcfg_ent_bits548ab0717907b301f5b9c16399b10032.tex}}}} + +\newcommand{\sailRISCVvalSetPmpcfgEntBits}{\saildoclabelled{sailRISCVzzysetzyPmpcfgzyentzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pmpcfg_ent_bits594540475f6835a77bc55f1853c82f34.tex}}}} + +\newcommand{\sailRISCVfnSetPmpcfgEntBits}{\saildoclabelled{sailRISCVfnzzysetzyPmpcfgzyentzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pmpcfg_ent_bits594540475f6835a77bc55f1853c82f34.tex}}}} + +\newcommand{\sailRISCVvalUpdatePmpcfgEntBits}{\saildoclabelled{sailRISCVzzyupdatezyPmpcfgzyentzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pmpcfg_ent_bits6dc08fac70bb607f44a679981ff8591f.tex}}}} + +\newcommand{\sailRISCVfnUpdatePmpcfgEntBits}{\saildoclabelled{sailRISCVfnzzyupdatezyPmpcfgzyentzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pmpcfg_ent_bits6dc08fac70bb607f44a679981ff8591f.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPPPPPPPPPupdateBits}{\saildoclabelled{sailRISCVoverloadPPPPPPPPPPPPzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPPPPPPPPPzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQQQQQQQQQModBits}{\saildoclabelled{sailRISCVoverloadQQQQQQQQQQQQzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQQQQQQQQQz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetPmpcfgEntL}{\saildoclabelled{sailRISCVzzygetzyPmpcfgzyentzyL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pmpcfg_ent_l809319223a792af7a0eb5574371df331.tex}}}} + +\newcommand{\sailRISCVfnGetPmpcfgEntL}{\saildoclabelled{sailRISCVfnzzygetzyPmpcfgzyentzyL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pmpcfg_ent_l809319223a792af7a0eb5574371df331.tex}}}} + +\newcommand{\sailRISCVvalSetPmpcfgEntL}{\saildoclabelled{sailRISCVzzysetzyPmpcfgzyentzyL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pmpcfg_ent_l3838182dc02b8ff73f27360aa88f7580.tex}}}} + +\newcommand{\sailRISCVfnSetPmpcfgEntL}{\saildoclabelled{sailRISCVfnzzysetzyPmpcfgzyentzyL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pmpcfg_ent_l3838182dc02b8ff73f27360aa88f7580.tex}}}} + +\newcommand{\sailRISCVvalUpdatePmpcfgEntL}{\saildoclabelled{sailRISCVzzyupdatezyPmpcfgzyentzyL}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pmpcfg_ent_lb0e2b34db62383c5c6ef62efd629c305.tex}}}} + +\newcommand{\sailRISCVfnUpdatePmpcfgEntL}{\saildoclabelled{sailRISCVfnzzyupdatezyPmpcfgzyentzyL}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pmpcfg_ent_lb0e2b34db62383c5c6ef62efd629c305.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRRRRRRRRRupdateL}{\saildoclabelled{sailRISCVoverloadRRRRRRRRRRRRzupdatezyL}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRRRRRRRRRzupdate_l18c2828f8e56660ea058db7889463318.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSSSSSSSSSModL}{\saildoclabelled{sailRISCVoverloadSSSSSSSSSSSSzzymodzyL}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSSSSSSSSSz_mod_lac2bd336f003b6226e212aa9fd493ac8.tex}}}} + +\newcommand{\sailRISCVvalGetPmpcfgEntA}{\saildoclabelled{sailRISCVzzygetzyPmpcfgzyentzyA}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pmpcfg_ent_a91770fb51fbff6c4cb08646293fdf39f.tex}}}} + +\newcommand{\sailRISCVfnGetPmpcfgEntA}{\saildoclabelled{sailRISCVfnzzygetzyPmpcfgzyentzyA}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pmpcfg_ent_a91770fb51fbff6c4cb08646293fdf39f.tex}}}} + +\newcommand{\sailRISCVvalSetPmpcfgEntA}{\saildoclabelled{sailRISCVzzysetzyPmpcfgzyentzyA}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pmpcfg_ent_a9693fd9f223e2207b066d9000b8199c1.tex}}}} + +\newcommand{\sailRISCVfnSetPmpcfgEntA}{\saildoclabelled{sailRISCVfnzzysetzyPmpcfgzyentzyA}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pmpcfg_ent_a9693fd9f223e2207b066d9000b8199c1.tex}}}} + +\newcommand{\sailRISCVvalUpdatePmpcfgEntA}{\saildoclabelled{sailRISCVzzyupdatezyPmpcfgzyentzyA}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pmpcfg_ent_adadbb540a1c6bab1c55bd9a61e3b9e0a.tex}}}} + +\newcommand{\sailRISCVfnUpdatePmpcfgEntA}{\saildoclabelled{sailRISCVfnzzyupdatezyPmpcfgzyentzyA}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pmpcfg_ent_adadbb540a1c6bab1c55bd9a61e3b9e0a.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTTTTTTTTTupdateA}{\saildoclabelled{sailRISCVoverloadTTTTTTTTTTTTzupdatezyA}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTTTTTTTTTzupdate_ab740c1f378b55b3328b2a9f25ff6c1cf.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUUUUUUUUUModA}{\saildoclabelled{sailRISCVoverloadUUUUUUUUUUUUzzymodzyA}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUUUUUUUUUz_mod_a62a6f88676512d98a363811f9f5ba327.tex}}}} + +\newcommand{\sailRISCVvalGetPmpcfgEntX}{\saildoclabelled{sailRISCVzzygetzyPmpcfgzyentzyX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pmpcfg_ent_x7298f9632eb08a3009a272d71e240aee.tex}}}} + +\newcommand{\sailRISCVfnGetPmpcfgEntX}{\saildoclabelled{sailRISCVfnzzygetzyPmpcfgzyentzyX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pmpcfg_ent_x7298f9632eb08a3009a272d71e240aee.tex}}}} + +\newcommand{\sailRISCVvalSetPmpcfgEntX}{\saildoclabelled{sailRISCVzzysetzyPmpcfgzyentzyX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pmpcfg_ent_x673f5396d42ee8881cf0e4a176b53225.tex}}}} + +\newcommand{\sailRISCVfnSetPmpcfgEntX}{\saildoclabelled{sailRISCVfnzzysetzyPmpcfgzyentzyX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pmpcfg_ent_x673f5396d42ee8881cf0e4a176b53225.tex}}}} + +\newcommand{\sailRISCVvalUpdatePmpcfgEntX}{\saildoclabelled{sailRISCVzzyupdatezyPmpcfgzyentzyX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pmpcfg_ent_x097e4626d7a8cfe0234214857e298c86.tex}}}} + +\newcommand{\sailRISCVfnUpdatePmpcfgEntX}{\saildoclabelled{sailRISCVfnzzyupdatezyPmpcfgzyentzyX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pmpcfg_ent_x097e4626d7a8cfe0234214857e298c86.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVVVVVVVVVupdateX}{\saildoclabelled{sailRISCVoverloadVVVVVVVVVVVVzupdatezyX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVVVVVVVVVzupdate_x647abdeca7ac108f059148e19df0452e.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWWWWWWWWWModX}{\saildoclabelled{sailRISCVoverloadWWWWWWWWWWWWzzymodzyX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWWWWWWWWWz_mod_xc906d7554de3b79cd0cc78501a562587.tex}}}} + +\newcommand{\sailRISCVvalGetPmpcfgEntW}{\saildoclabelled{sailRISCVzzygetzyPmpcfgzyentzyW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pmpcfg_ent_w9a2773642113e6c2af77db6f82354b24.tex}}}} + +\newcommand{\sailRISCVfnGetPmpcfgEntW}{\saildoclabelled{sailRISCVfnzzygetzyPmpcfgzyentzyW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pmpcfg_ent_w9a2773642113e6c2af77db6f82354b24.tex}}}} + +\newcommand{\sailRISCVvalSetPmpcfgEntW}{\saildoclabelled{sailRISCVzzysetzyPmpcfgzyentzyW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pmpcfg_ent_wce1529faf12026bc7cc93760d4dd2183.tex}}}} + +\newcommand{\sailRISCVfnSetPmpcfgEntW}{\saildoclabelled{sailRISCVfnzzysetzyPmpcfgzyentzyW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pmpcfg_ent_wce1529faf12026bc7cc93760d4dd2183.tex}}}} + +\newcommand{\sailRISCVvalUpdatePmpcfgEntW}{\saildoclabelled{sailRISCVzzyupdatezyPmpcfgzyentzyW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pmpcfg_ent_w74feb7c9463c0ec331329f44cf100d0f.tex}}}} + +\newcommand{\sailRISCVfnUpdatePmpcfgEntW}{\saildoclabelled{sailRISCVfnzzyupdatezyPmpcfgzyentzyW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pmpcfg_ent_w74feb7c9463c0ec331329f44cf100d0f.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXXXXXXXXXupdateW}{\saildoclabelled{sailRISCVoverloadXXXXXXXXXXXXzupdatezyW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXXXXXXXXXzupdate_w3209efc3cdd41bbc0810494fad257f06.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYYYYYYYYYModW}{\saildoclabelled{sailRISCVoverloadYYYYYYYYYYYYzzymodzyW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYYYYYYYYYz_mod_w196183ee717bdd84cd7d5e4b2af0b219.tex}}}} + +\newcommand{\sailRISCVvalGetPmpcfgEntR}{\saildoclabelled{sailRISCVzzygetzyPmpcfgzyentzyR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pmpcfg_ent_r2cdcfc9666bd2e243c0c9c0473f345d2.tex}}}} + +\newcommand{\sailRISCVfnGetPmpcfgEntR}{\saildoclabelled{sailRISCVfnzzygetzyPmpcfgzyentzyR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pmpcfg_ent_r2cdcfc9666bd2e243c0c9c0473f345d2.tex}}}} + +\newcommand{\sailRISCVvalSetPmpcfgEntR}{\saildoclabelled{sailRISCVzzysetzyPmpcfgzyentzyR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pmpcfg_ent_re7495d5157c5145daf88a430c7faa2ea.tex}}}} + +\newcommand{\sailRISCVfnSetPmpcfgEntR}{\saildoclabelled{sailRISCVfnzzysetzyPmpcfgzyentzyR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pmpcfg_ent_re7495d5157c5145daf88a430c7faa2ea.tex}}}} + +\newcommand{\sailRISCVvalUpdatePmpcfgEntR}{\saildoclabelled{sailRISCVzzyupdatezyPmpcfgzyentzyR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pmpcfg_ent_r2c785198293c46ff7260dc7a32aa6331.tex}}}} + +\newcommand{\sailRISCVfnUpdatePmpcfgEntR}{\saildoclabelled{sailRISCVfnzzyupdatezyPmpcfgzyentzyR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pmpcfg_ent_r2c785198293c46ff7260dc7a32aa6331.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZZZZZZZZZupdateR}{\saildoclabelled{sailRISCVoverloadZZZZZZZZZZZZzupdatezyR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZZZZZZZZZzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAAAAAAAAAModR}{\saildoclabelled{sailRISCVoverloadAAAAAAAAAAAAAzzymodzyR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAAAAAAAAAz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex}}}} + +\newcommand{\sailRISCVvalpmpReadCfgReg}{\saildoclabelled{sailRISCVzpmpReadCfgReg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpreadcfgreg4f212865b80d1cf6286c5525466852bb.tex}}}} + +\newcommand{\sailRISCVfnpmpReadCfgReg}{\saildoclabelled{sailRISCVfnzpmpReadCfgReg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpreadcfgreg4f212865b80d1cf6286c5525466852bb.tex}}}} + +\newcommand{\sailRISCVvalpmpLocked}{\saildoclabelled{sailRISCVzpmpLocked}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmplocked32d6273cc49a9c7a22cf1a063f7a3d9b.tex}}}} + +\newcommand{\sailRISCVfnpmpLocked}{\saildoclabelled{sailRISCVfnzpmpLocked}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmplocked32d6273cc49a9c7a22cf1a063f7a3d9b.tex}}}} + +\newcommand{\sailRISCVvalpmpTORLocked}{\saildoclabelled{sailRISCVzpmpTORLocked}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmptorlockedc6616187f2e2905a9fb7c4ac60d52920.tex}}}} + +\newcommand{\sailRISCVfnpmpTORLocked}{\saildoclabelled{sailRISCVfnzpmpTORLocked}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmptorlockedc6616187f2e2905a9fb7c4ac60d52920.tex}}}} + +\newcommand{\sailRISCVvalpmpWriteCfg}{\saildoclabelled{sailRISCVzpmpWriteCfg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpwritecfg2cde3ea402426e32bb50a4bc91e0c983.tex}}}} + +\newcommand{\sailRISCVfnpmpWriteCfg}{\saildoclabelled{sailRISCVfnzpmpWriteCfg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpwritecfg2cde3ea402426e32bb50a4bc91e0c983.tex}}}} + +\newcommand{\sailRISCVvalpmpWriteCfgReg}{\saildoclabelled{sailRISCVzpmpWriteCfgReg}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpwritecfgregf08572520295a822ab88e05e223953db.tex}}}} + +\newcommand{\sailRISCVfnpmpWriteCfgReg}{\saildoclabelled{sailRISCVfnzpmpWriteCfgReg}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpwritecfgregf08572520295a822ab88e05e223953db.tex}}}} + +\newcommand{\sailRISCVvalpmpWriteAddr}{\saildoclabelled{sailRISCVzpmpWriteAddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpwriteaddr35a89b2e3be238e40992648bdf6c2e4c.tex}}}} + +\newcommand{\sailRISCVfnpmpWriteAddr}{\saildoclabelled{sailRISCVfnzpmpWriteAddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpwriteaddr35a89b2e3be238e40992648bdf6c2e4c.tex}}}} + +\newcommand{\sailRISCVtypepmpAddrRange}{\saildoclabelled{sailRISCVtypezpmpzyaddrzyrange}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpmp_addr_range0c14af966e97978e2e0bea3825363bf8.tex}}}} + +\newcommand{\sailRISCVvalpmpAddrRangeA}{\saildoclabelled{sailRISCVzpmpAddrRange}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpaddrranged0e482997ef7d22fddc89c097e038f0d.tex}}}} + +\newcommand{\sailRISCVfnpmpAddrRangeA}{\saildoclabelled{sailRISCVfnzpmpAddrRange}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpaddrranged0e482997ef7d22fddc89c097e038f0d.tex}}}} + +\newcommand{\sailRISCVvalpmpCheckRWX}{\saildoclabelled{sailRISCVzpmpCheckRWX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpcheckrwx6a81da10e740c25fedddbe430f079b7d.tex}}}} + +\newcommand{\sailRISCVfnpmpCheckRWX}{\saildoclabelled{sailRISCVfnzpmpCheckRWX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpcheckrwx6a81da10e740c25fedddbe430f079b7d.tex}}}} + +\newcommand{\sailRISCVvalpmpCheckPerms}{\saildoclabelled{sailRISCVzpmpCheckPerms}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpcheckperms43a47caab37d2bebaa37cc41235e7387.tex}}}} + +\newcommand{\sailRISCVfnpmpCheckPerms}{\saildoclabelled{sailRISCVfnzpmpCheckPerms}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpcheckperms43a47caab37d2bebaa37cc41235e7387.tex}}}} + +\newcommand{\sailRISCVtypepmpAddrMatch}{\saildoclabelled{sailRISCVtypezpmpAddrMatch}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpmpaddrmatch1b3d520a29cdf5ebe0ae194fe06ab693.tex}}}} + +\newcommand{\sailRISCVvalpmpAddrMatchOfNum}{\saildoclabelled{sailRISCVzpmpAddrMatchzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpaddrmatch_of_num92a36380d4ab664cee1f4ee0143e390f.tex}}}} + +\newcommand{\sailRISCVfnpmpAddrMatchOfNum}{\saildoclabelled{sailRISCVfnzpmpAddrMatchzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpaddrmatch_of_num92a36380d4ab664cee1f4ee0143e390f.tex}}}} + +\newcommand{\sailRISCVvalnumOfPmpAddrMatch}{\saildoclabelled{sailRISCVznumzyofzypmpAddrMatch}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_pmpaddrmatch6db470099c3f03581d51f40437610a39.tex}}}} + +\newcommand{\sailRISCVfnnumOfPmpAddrMatch}{\saildoclabelled{sailRISCVfnznumzyofzypmpAddrMatch}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_pmpaddrmatch6db470099c3f03581d51f40437610a39.tex}}}} + +\newcommand{\sailRISCVvalpmpMatchAddr}{\saildoclabelled{sailRISCVzpmpMatchAddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpmatchaddr4db797384cb60b665d5b05ce2f54ea2f.tex}}}} + +\newcommand{\sailRISCVfnpmpMatchAddr}{\saildoclabelled{sailRISCVfnzpmpMatchAddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpmatchaddr4db797384cb60b665d5b05ce2f54ea2f.tex}}}} + +\newcommand{\sailRISCVtypepmpMatch}{\saildoclabelled{sailRISCVtypezpmpMatch}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpmpmatch43c06bad055792d6d43e48c69738fa97.tex}}}} + +\newcommand{\sailRISCVvalpmpMatchOfNum}{\saildoclabelled{sailRISCVzpmpMatchzyofzynum}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpmatch_of_num271d71ea451fba2032d2e5ea441d9f49.tex}}}} + +\newcommand{\sailRISCVfnpmpMatchOfNum}{\saildoclabelled{sailRISCVfnzpmpMatchzyofzynum}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpmatch_of_num271d71ea451fba2032d2e5ea441d9f49.tex}}}} + +\newcommand{\sailRISCVvalnumOfPmpMatch}{\saildoclabelled{sailRISCVznumzyofzypmpMatch}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznum_of_pmpmatch3a839a54108c809c88766e9119a0bce5.tex}}}} + +\newcommand{\sailRISCVfnnumOfPmpMatch}{\saildoclabelled{sailRISCVfnznumzyofzypmpMatch}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznum_of_pmpmatch3a839a54108c809c88766e9119a0bce5.tex}}}} + +\newcommand{\sailRISCVvalpmpMatchEntry}{\saildoclabelled{sailRISCVzpmpMatchEntry}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpmatchentryb540666374b1cccee76fe8eb4dc7362f.tex}}}} + +\newcommand{\sailRISCVfnpmpMatchEntry}{\saildoclabelled{sailRISCVfnzpmpMatchEntry}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpmatchentryb540666374b1cccee76fe8eb4dc7362f.tex}}}} + +\newcommand{\sailRISCVvalpmpCheck}{\saildoclabelled{sailRISCVzpmpCheck}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmpcheck818accaacf804d4474fe874d5c97929a.tex}}}} + +\newcommand{\sailRISCVfnpmpCheck}{\saildoclabelled{sailRISCVfnzpmpCheck}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmpcheck818accaacf804d4474fe874d5c97929a.tex}}}} + +\newcommand{\sailRISCVvalinitPmp}{\saildoclabelled{sailRISCVzinitzypmp}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinit_pmp10ae24a767d242e86512a2c1a55970ef.tex}}}} + +\newcommand{\sailRISCVfninitPmp}{\saildoclabelled{sailRISCVfnzinitzypmp}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinit_pmp10ae24a767d242e86512a2c1a55970ef.tex}}}} + +\newcommand{\sailRISCVtypeccsr}{\saildoclabelled{sailRISCVtypezccsr}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezccsrebba1b25012128c604b97c41d5de5508.tex}}}} + +\newcommand{\sailRISCVvalMkCcsr}{\saildoclabelled{sailRISCVzMkzyccsr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_ccsre3234e42694bb21773ea7b0780c04af8.tex}}}} + +\newcommand{\sailRISCVfnMkCcsr}{\saildoclabelled{sailRISCVfnzMkzyccsr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_ccsre3234e42694bb21773ea7b0780c04af8.tex}}}} + +\newcommand{\sailRISCVvalGetCcsrBits}{\saildoclabelled{sailRISCVzzygetzyccsrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_ccsr_bitsa5bf4f91be070c5e733b7c8dcd21079f.tex}}}} + +\newcommand{\sailRISCVfnGetCcsrBits}{\saildoclabelled{sailRISCVfnzzygetzyccsrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_ccsr_bitsa5bf4f91be070c5e733b7c8dcd21079f.tex}}}} + +\newcommand{\sailRISCVvalSetCcsrBits}{\saildoclabelled{sailRISCVzzysetzyccsrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_ccsr_bits3806e9d0f8a05e576c1382f4734c757e.tex}}}} + +\newcommand{\sailRISCVfnSetCcsrBits}{\saildoclabelled{sailRISCVfnzzysetzyccsrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_ccsr_bits3806e9d0f8a05e576c1382f4734c757e.tex}}}} + +\newcommand{\sailRISCVvalUpdateCcsrBits}{\saildoclabelled{sailRISCVzzyupdatezyccsrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_ccsr_bitscab95b9f107541973f0ca10985835467.tex}}}} + +\newcommand{\sailRISCVfnUpdateCcsrBits}{\saildoclabelled{sailRISCVfnzzyupdatezyccsrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_ccsr_bitscab95b9f107541973f0ca10985835467.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBBBBBBBBBupdateBits}{\saildoclabelled{sailRISCVoverloadBBBBBBBBBBBBBzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBBBBBBBBBzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCCCCCCCCCModBits}{\saildoclabelled{sailRISCVoverloadCCCCCCCCCCCCCzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCCCCCCCCCz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetCcsrCapIdx}{\saildoclabelled{sailRISCVzzygetzyccsrzycapzyidx}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_ccsr_cap_idx07f5b7d982282306c072600892773224.tex}}}} + +\newcommand{\sailRISCVfnGetCcsrCapIdx}{\saildoclabelled{sailRISCVfnzzygetzyccsrzycapzyidx}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_ccsr_cap_idx07f5b7d982282306c072600892773224.tex}}}} + +\newcommand{\sailRISCVvalSetCcsrCapIdx}{\saildoclabelled{sailRISCVzzysetzyccsrzycapzyidx}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_ccsr_cap_idxf1dab003746059638583e08318dd0939.tex}}}} + +\newcommand{\sailRISCVfnSetCcsrCapIdx}{\saildoclabelled{sailRISCVfnzzysetzyccsrzycapzyidx}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_ccsr_cap_idxf1dab003746059638583e08318dd0939.tex}}}} + +\newcommand{\sailRISCVvalUpdateCcsrCapIdx}{\saildoclabelled{sailRISCVzzyupdatezyccsrzycapzyidx}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_ccsr_cap_idxcf97e2a26597f29b63eaa57befa11cea.tex}}}} + +\newcommand{\sailRISCVfnUpdateCcsrCapIdx}{\saildoclabelled{sailRISCVfnzzyupdatezyccsrzycapzyidx}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_ccsr_cap_idxcf97e2a26597f29b63eaa57befa11cea.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDDDDDDDDDDupdateCapIdx}{\saildoclabelled{sailRISCVoverloadDDDDDDDDDDDDDzupdatezycapzyidx}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDDDDDDDDDDzupdate_cap_idxe77ade3df0db97f2d0c7e159a697bce8.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEEEEEEEEEEModCapIdx}{\saildoclabelled{sailRISCVoverloadEEEEEEEEEEEEEzzymodzycapzyidx}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEEEEEEEEEEz_mod_cap_idx2aa9e57d92bb9ee2c5c8636b1e91e4b8.tex}}}} + +\newcommand{\sailRISCVvalGetCcsrCause}{\saildoclabelled{sailRISCVzzygetzyccsrzycause}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_ccsr_caused575f504e43b5c4f705e1e76299969a8.tex}}}} + +\newcommand{\sailRISCVfnGetCcsrCause}{\saildoclabelled{sailRISCVfnzzygetzyccsrzycause}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_ccsr_caused575f504e43b5c4f705e1e76299969a8.tex}}}} + +\newcommand{\sailRISCVvalSetCcsrCause}{\saildoclabelled{sailRISCVzzysetzyccsrzycause}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_ccsr_causea61c64eff6f93cf534fa898aaa26f2b0.tex}}}} + +\newcommand{\sailRISCVfnSetCcsrCause}{\saildoclabelled{sailRISCVfnzzysetzyccsrzycause}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_ccsr_causea61c64eff6f93cf534fa898aaa26f2b0.tex}}}} + +\newcommand{\sailRISCVvalUpdateCcsrCause}{\saildoclabelled{sailRISCVzzyupdatezyccsrzycause}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_ccsr_causecd8b7254c686be403e4e906a346f4642.tex}}}} + +\newcommand{\sailRISCVfnUpdateCcsrCause}{\saildoclabelled{sailRISCVfnzzyupdatezyccsrzycause}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_ccsr_causecd8b7254c686be403e4e906a346f4642.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFFFFFFFFFFupdateCauseA}{\saildoclabelled{sailRISCVoverloadFFFFFFFFFFFFFzupdatezycause}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFFFFFFFFFFzupdate_cause68e022ebb6a1524860ca61573bc7f0b3.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGGGGGGGGGGModCauseA}{\saildoclabelled{sailRISCVoverloadGGGGGGGGGGGGGzzymodzycause}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGGGGGGGGGGz_mod_causeb77ad00e2fa7ea0bcdf939ce8b0035af.tex}}}} + +\newcommand{\sailRISCVvalGetCcsrD}{\saildoclabelled{sailRISCVzzygetzyccsrzyd}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_ccsr_d5cb2dcaceb4937b225b4475484d2bf2d.tex}}}} + +\newcommand{\sailRISCVfnGetCcsrD}{\saildoclabelled{sailRISCVfnzzygetzyccsrzyd}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_ccsr_d5cb2dcaceb4937b225b4475484d2bf2d.tex}}}} + +\newcommand{\sailRISCVvalSetCcsrD}{\saildoclabelled{sailRISCVzzysetzyccsrzyd}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_ccsr_db32b59142df24c8fe9016263b659269d.tex}}}} + +\newcommand{\sailRISCVfnSetCcsrD}{\saildoclabelled{sailRISCVfnzzysetzyccsrzyd}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_ccsr_db32b59142df24c8fe9016263b659269d.tex}}}} + +\newcommand{\sailRISCVvalUpdateCcsrD}{\saildoclabelled{sailRISCVzzyupdatezyccsrzyd}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_ccsr_dad4c6c7e8973232b0249a9b870dab8b8.tex}}}} + +\newcommand{\sailRISCVfnUpdateCcsrD}{\saildoclabelled{sailRISCVfnzzyupdatezyccsrzyd}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_ccsr_dad4c6c7e8973232b0249a9b870dab8b8.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHHHHHHHHHHupdateDA}{\saildoclabelled{sailRISCVoverloadHHHHHHHHHHHHHzupdatezyd}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHHHHHHHHHHzupdate_d57d9225616475e802ecec210f39b5b9d.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIIIIIIIIIIModDA}{\saildoclabelled{sailRISCVoverloadIIIIIIIIIIIIIzzymodzyd}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIIIIIIIIIIz_mod_db168473f6dc9a1201d80a180a02bc64a.tex}}}} + +\newcommand{\sailRISCVvalGetCcsrE}{\saildoclabelled{sailRISCVzzygetzyccsrzye}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_ccsr_e6d359c132221ee638d3b99e5bb880b1c.tex}}}} + +\newcommand{\sailRISCVfnGetCcsrE}{\saildoclabelled{sailRISCVfnzzygetzyccsrzye}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_ccsr_e6d359c132221ee638d3b99e5bb880b1c.tex}}}} + +\newcommand{\sailRISCVvalSetCcsrE}{\saildoclabelled{sailRISCVzzysetzyccsrzye}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_ccsr_e1c0d679cfed0abc1454ed21db9246e96.tex}}}} + +\newcommand{\sailRISCVfnSetCcsrE}{\saildoclabelled{sailRISCVfnzzysetzyccsrzye}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_ccsr_e1c0d679cfed0abc1454ed21db9246e96.tex}}}} + +\newcommand{\sailRISCVvalUpdateCcsrE}{\saildoclabelled{sailRISCVzzyupdatezyccsrzye}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_ccsr_e79adbf3ff342d3a9fc182dd2dd614be3.tex}}}} + +\newcommand{\sailRISCVfnUpdateCcsrE}{\saildoclabelled{sailRISCVfnzzyupdatezyccsrzye}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_ccsr_e79adbf3ff342d3a9fc182dd2dd614be3.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJJJJJJJJJJupdateEA}{\saildoclabelled{sailRISCVoverloadJJJJJJJJJJJJJzupdatezye}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJJJJJJJJJJzupdate_e7a63b7e30669139ab9225922027a87d0.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKKKKKKKKKKModEA}{\saildoclabelled{sailRISCVoverloadKKKKKKKKKKKKKzzymodzye}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKKKKKKKKKKz_mod_ed8b4db91b378334a887e790f3939603e.tex}}}} + +\newcommand{\sailRISCVvallegalizzeCcsr}{\saildoclabelled{sailRISCVzlegalizzezyccsr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_ccsr8248d36ab83d1808c1e3e0b64d88c1cf.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeCcsr}{\saildoclabelled{sailRISCVfnzlegalizzezyccsr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_ccsr8248d36ab83d1808c1e3e0b64d88c1cf.tex}}}} + +\newcommand{\sailRISCVvalminInstructionBytes}{\saildoclabelled{sailRISCVzminzyinstructionzybytes}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmin_instruction_bytesb10dab453fbe2e946cf3f20de7511e71.tex}}}} + +\newcommand{\sailRISCVfnminInstructionBytes}{\saildoclabelled{sailRISCVfnzminzyinstructionzybytes}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmin_instruction_bytesb10dab453fbe2e946cf3f20de7511e71.tex}}}} + +\newcommand{\sailRISCVvalhaveXcheri}{\saildoclabelled{sailRISCVzhaveXcheri}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhavexcheri36112408abb05cceef19a84af1e5a22a.tex}}}} + +\newcommand{\sailRISCVfnhaveXcheri}{\saildoclabelled{sailRISCVfnzhaveXcheri}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhavexcheri36112408abb05cceef19a84af1e5a22a.tex}}}} + +\newcommand{\sailRISCVvallegalizzeTcc}{\saildoclabelled{sailRISCVzlegalizzezytcc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_tccfd2d2ccb3d791b05f6d62114b5036cb9.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeTcc}{\saildoclabelled{sailRISCVfnzlegalizzezytcc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_tccfd2d2ccb3d791b05f6d62114b5036cb9.tex}}}} + +\newcommand{\sailRISCVvallegalizzeEpcc}{\saildoclabelled{sailRISCVzlegalizzezyepcc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_epccfd09ccf016c22f97fa9a6b5dfba65e84.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeEpcc}{\saildoclabelled{sailRISCVfnzlegalizzezyepcc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_epccfd09ccf016c22f97fa9a6b5dfba65e84.tex}}}} + +\newcommand{\sailRISCVvalrC}{\saildoclabelled{sailRISCVzrC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrcda9d82cd736deb89a37d9ca089373805.tex}}}} + +\newcommand{\sailRISCVfnrC}{\saildoclabelled{sailRISCVfnzrC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrcda9d82cd736deb89a37d9ca089373805.tex}}}} + +\newcommand{\sailRISCVvalwC}{\saildoclabelled{sailRISCVzwC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwc721d52ce2fe818d0148aaf1d5b6e2bec.tex}}}} + +\newcommand{\sailRISCVfnwC}{\saildoclabelled{sailRISCVfnzwC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwc721d52ce2fe818d0148aaf1d5b6e2bec.tex}}}} + +\newcommand{\sailRISCVvalrCBits}{\saildoclabelled{sailRISCVzrCzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrc_bits18d7e232c147203cdc9c7cd0ffbe7ec0.tex}}}} + +\newcommand{\sailRISCVfnrCBits}{\saildoclabelled{sailRISCVfnzrCzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrc_bits18d7e232c147203cdc9c7cd0ffbe7ec0.tex}}}} + +\newcommand{\sailRISCVvalwCBits}{\saildoclabelled{sailRISCVzwCzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwc_bitsb8b2d4f53308d4bb8d154a1f6664d336.tex}}}} + +\newcommand{\sailRISCVfnwCBits}{\saildoclabelled{sailRISCVfnzwCzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwc_bitsb8b2d4f53308d4bb8d154a1f6664d336.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLLLLLLLLLLC}{\saildoclabelled{sailRISCVoverloadLLLLLLLLLLLLLzC}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLLLLLLLLLLzc15f67105dab436b80b9241d87d1f8e9d.tex}}}} + +\newcommand{\sailRISCVvalextInitRegs}{\saildoclabelled{sailRISCVzextzyinitzyregs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_init_regs1d9ff00ce58fd5712eb26190e338015a.tex}}}} + +\newcommand{\sailRISCVfnextInitRegs}{\saildoclabelled{sailRISCVfnzextzyinitzyregs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_init_regs1d9ff00ce58fd5712eb26190e338015a.tex}}}} + +\newcommand{\sailRISCVvalextRvfiInit}{\saildoclabelled{sailRISCVzextzyrvfizyinit}{\saildocval{This function is called after above when running rvfi and allows the model +to be initialised differently. For RVFI we initialise cap regs to default +instead of null. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_rvfi_init925272b6b4282430111c3e89a50f1e0b.tex}}}} + +\newcommand{\sailRISCVfnextRvfiInit}{\saildoclabelled{sailRISCVfnzextzyrvfizyinit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_rvfi_init925272b6b4282430111c3e89a50f1e0b.tex}}}} + +\newcommand{\sailRISCVvalcapRegNameAbi}{\saildoclabelled{sailRISCVzcapzyregzynamezyabi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcap_reg_name_abi719d69842e8a63e886ffe0791675d4e0.tex}}}} + +\newcommand{\sailRISCVfncapRegNameAbi}{\saildoclabelled{sailRISCVfnzcapzyregzynamezyabi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcap_reg_name_abi719d69842e8a63e886ffe0791675d4e0.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMMMMMMMMMMtoStr}{\saildoclabelled{sailRISCVoverloadMMMMMMMMMMMMMztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMMMMMMMMMMzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} + +\newcommand{\sailRISCVvalcapRegName}{\saildoclabelled{sailRISCVzcapzyregzyname}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcap_reg_name2541adc6dad121efe53209371c0fbc68.tex}}}} + +\newcommand{\sailRISCVvalcapCregName}{\saildoclabelled{sailRISCVzcapzycregzyname}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcap_creg_nameb745905c258c936ba7a6eafe4633359f.tex}}}} + +\newcommand{\sailRISCVvalgetArchPc}{\saildoclabelled{sailRISCVzgetzyarchzypc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_arch_pc874e1e50a5765cd3e317d37fa710a52d.tex}}}} + +\newcommand{\sailRISCVfngetArchPc}{\saildoclabelled{sailRISCVfnzgetzyarchzypc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_arch_pc874e1e50a5765cd3e317d37fa710a52d.tex}}}} + +\newcommand{\sailRISCVvalgetNextPc}{\saildoclabelled{sailRISCVzgetzynextzypc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_next_pc52098782da35f914abcd4b708363813b.tex}}}} + +\newcommand{\sailRISCVfngetNextPc}{\saildoclabelled{sailRISCVfnzgetzynextzypc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_next_pc52098782da35f914abcd4b708363813b.tex}}}} + +\newcommand{\sailRISCVvalsetNextPc}{\saildoclabelled{sailRISCVzsetzynextzypc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzset_next_pc4a8ca0d1733a6630871f9f58d4ea2e08.tex}}}} + +\newcommand{\sailRISCVfnsetNextPc}{\saildoclabelled{sailRISCVfnzsetzynextzypc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzset_next_pc4a8ca0d1733a6630871f9f58d4ea2e08.tex}}}} + +\newcommand{\sailRISCVvaltickPc}{\saildoclabelled{sailRISCVztickzypc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztick_pc459868e2ecb79c51cd3817471ae33696.tex}}}} + +\newcommand{\sailRISCVfntickPc}{\saildoclabelled{sailRISCVfnztickzypc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztick_pc459868e2ecb79c51cd3817471ae33696.tex}}}} + +\newcommand{\sailRISCVtypeUstatus}{\saildoclabelled{sailRISCVtypezUstatus}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezustatusea9ad819ad5ad1c26e0977e4f7a545d6.tex}}}} + +\newcommand{\sailRISCVvalMkUstatus}{\saildoclabelled{sailRISCVzMkzyUstatus}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_ustatus6494ac5e1dcede8689e33b27d65d3204.tex}}}} + +\newcommand{\sailRISCVfnMkUstatus}{\saildoclabelled{sailRISCVfnzMkzyUstatus}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_ustatus6494ac5e1dcede8689e33b27d65d3204.tex}}}} + +\newcommand{\sailRISCVvalGetUstatusBits}{\saildoclabelled{sailRISCVzzygetzyUstatuszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_ustatus_bits230116890e8a3e29f1d043be407c7237.tex}}}} + +\newcommand{\sailRISCVfnGetUstatusBits}{\saildoclabelled{sailRISCVfnzzygetzyUstatuszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_ustatus_bits230116890e8a3e29f1d043be407c7237.tex}}}} + +\newcommand{\sailRISCVvalSetUstatusBits}{\saildoclabelled{sailRISCVzzysetzyUstatuszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_ustatus_bits30b27147d374fd2bd7fadc954e833c3f.tex}}}} + +\newcommand{\sailRISCVfnSetUstatusBits}{\saildoclabelled{sailRISCVfnzzysetzyUstatuszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_ustatus_bits30b27147d374fd2bd7fadc954e833c3f.tex}}}} + +\newcommand{\sailRISCVvalUpdateUstatusBits}{\saildoclabelled{sailRISCVzzyupdatezyUstatuszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_ustatus_bits58fc869676c24d63b7324b3ddc882d14.tex}}}} + +\newcommand{\sailRISCVfnUpdateUstatusBits}{\saildoclabelled{sailRISCVfnzzyupdatezyUstatuszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_ustatus_bits58fc869676c24d63b7324b3ddc882d14.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNNNNNNNNNNupdateBits}{\saildoclabelled{sailRISCVoverloadNNNNNNNNNNNNNzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNNNNNNNNNNzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOOOOOOOOOOModBits}{\saildoclabelled{sailRISCVoverloadOOOOOOOOOOOOOzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOOOOOOOOOOz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetUstatusUPIE}{\saildoclabelled{sailRISCVzzygetzyUstatuszyUPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_ustatus_upiec1c1afe6b971883383e700b3ef0f0b35.tex}}}} + +\newcommand{\sailRISCVfnGetUstatusUPIE}{\saildoclabelled{sailRISCVfnzzygetzyUstatuszyUPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_ustatus_upiec1c1afe6b971883383e700b3ef0f0b35.tex}}}} + +\newcommand{\sailRISCVvalSetUstatusUPIE}{\saildoclabelled{sailRISCVzzysetzyUstatuszyUPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_ustatus_upie36655d5ae32856b4d8e9eefbf763af27.tex}}}} + +\newcommand{\sailRISCVfnSetUstatusUPIE}{\saildoclabelled{sailRISCVfnzzysetzyUstatuszyUPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_ustatus_upie36655d5ae32856b4d8e9eefbf763af27.tex}}}} + +\newcommand{\sailRISCVvalUpdateUstatusUPIE}{\saildoclabelled{sailRISCVzzyupdatezyUstatuszyUPIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_ustatus_upie620a46996c155948c916224ee8c0d297.tex}}}} + +\newcommand{\sailRISCVfnUpdateUstatusUPIE}{\saildoclabelled{sailRISCVfnzzyupdatezyUstatuszyUPIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_ustatus_upie620a46996c155948c916224ee8c0d297.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPPPPPPPPPPupdateUPIE}{\saildoclabelled{sailRISCVoverloadPPPPPPPPPPPPPzupdatezyUPIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPPPPPPPPPPzupdate_upiea5ad86a550536087d757a5582d1a8bb9.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQQQQQQQQQQModUPIE}{\saildoclabelled{sailRISCVoverloadQQQQQQQQQQQQQzzymodzyUPIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQQQQQQQQQQz_mod_upie27f56ba53dc72f512e0a128ab616ba83.tex}}}} + +\newcommand{\sailRISCVvalGetUstatusUIE}{\saildoclabelled{sailRISCVzzygetzyUstatuszyUIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_ustatus_uie443e8ee7d068af4b9b66e7cbf42dd57e.tex}}}} + +\newcommand{\sailRISCVfnGetUstatusUIE}{\saildoclabelled{sailRISCVfnzzygetzyUstatuszyUIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_ustatus_uie443e8ee7d068af4b9b66e7cbf42dd57e.tex}}}} + +\newcommand{\sailRISCVvalSetUstatusUIE}{\saildoclabelled{sailRISCVzzysetzyUstatuszyUIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_ustatus_uied66ad7f688ead51a86b377a82d67ff47.tex}}}} + +\newcommand{\sailRISCVfnSetUstatusUIE}{\saildoclabelled{sailRISCVfnzzysetzyUstatuszyUIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_ustatus_uied66ad7f688ead51a86b377a82d67ff47.tex}}}} + +\newcommand{\sailRISCVvalUpdateUstatusUIE}{\saildoclabelled{sailRISCVzzyupdatezyUstatuszyUIE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_ustatus_uie937a13d13f328a695bd490140941d1ad.tex}}}} + +\newcommand{\sailRISCVfnUpdateUstatusUIE}{\saildoclabelled{sailRISCVfnzzyupdatezyUstatuszyUIE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_ustatus_uie937a13d13f328a695bd490140941d1ad.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRRRRRRRRRRupdateUIE}{\saildoclabelled{sailRISCVoverloadRRRRRRRRRRRRRzupdatezyUIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRRRRRRRRRRzupdate_uied194e7b32c7c54d35dfc1b602b4b5907.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSSSSSSSSSSModUIE}{\saildoclabelled{sailRISCVoverloadSSSSSSSSSSSSSzzymodzyUIE}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSSSSSSSSSSz_mod_uie18b8fe18a506d4c612ff106c8cc5fb23.tex}}}} + +\newcommand{\sailRISCVvallowerSstatus}{\saildoclabelled{sailRISCVzlowerzysstatus}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlower_sstatusee8227db3ac1f80e02871989d3ac7837.tex}}}} + +\newcommand{\sailRISCVfnlowerSstatus}{\saildoclabelled{sailRISCVfnzlowerzysstatus}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlower_sstatusee8227db3ac1f80e02871989d3ac7837.tex}}}} + +\newcommand{\sailRISCVvalliftUstatus}{\saildoclabelled{sailRISCVzliftzyustatus}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlift_ustatus9f7d2e2291fdb3a746dca97290479c47.tex}}}} + +\newcommand{\sailRISCVfnliftUstatus}{\saildoclabelled{sailRISCVfnzliftzyustatus}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlift_ustatus9f7d2e2291fdb3a746dca97290479c47.tex}}}} + +\newcommand{\sailRISCVvallegalizzeUstatus}{\saildoclabelled{sailRISCVzlegalizzezyustatus}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_ustatusae91980d0571269b3dd8a4a779cb06c6.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeUstatus}{\saildoclabelled{sailRISCVfnzlegalizzezyustatus}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_ustatusae91980d0571269b3dd8a4a779cb06c6.tex}}}} + +\newcommand{\sailRISCVtypeUinterrupts}{\saildoclabelled{sailRISCVtypezUinterrupts}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezuinterrupts1427c63818d0a5c9cb26ba06e84f503f.tex}}}} + +\newcommand{\sailRISCVvalMkUinterrupts}{\saildoclabelled{sailRISCVzMkzyUinterrupts}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_uinterrupts22955e59610459ed7c6ad97089d22498.tex}}}} + +\newcommand{\sailRISCVfnMkUinterrupts}{\saildoclabelled{sailRISCVfnzMkzyUinterrupts}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_uinterrupts22955e59610459ed7c6ad97089d22498.tex}}}} + +\newcommand{\sailRISCVvalGetUinterruptsBits}{\saildoclabelled{sailRISCVzzygetzyUinterruptszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_uinterrupts_bits0b7d0f2f07976b876318898e01847c70.tex}}}} + +\newcommand{\sailRISCVfnGetUinterruptsBits}{\saildoclabelled{sailRISCVfnzzygetzyUinterruptszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_uinterrupts_bits0b7d0f2f07976b876318898e01847c70.tex}}}} + +\newcommand{\sailRISCVvalSetUinterruptsBits}{\saildoclabelled{sailRISCVzzysetzyUinterruptszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_uinterrupts_bits727060290947315f91798504a8e1220d.tex}}}} + +\newcommand{\sailRISCVfnSetUinterruptsBits}{\saildoclabelled{sailRISCVfnzzysetzyUinterruptszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_uinterrupts_bits727060290947315f91798504a8e1220d.tex}}}} + +\newcommand{\sailRISCVvalUpdateUinterruptsBits}{\saildoclabelled{sailRISCVzzyupdatezyUinterruptszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_uinterrupts_bits9c553d2ae4d62c448e09c704b0d8bba7.tex}}}} + +\newcommand{\sailRISCVfnUpdateUinterruptsBits}{\saildoclabelled{sailRISCVfnzzyupdatezyUinterruptszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_uinterrupts_bits9c553d2ae4d62c448e09c704b0d8bba7.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTTTTTTTTTTupdateBits}{\saildoclabelled{sailRISCVoverloadTTTTTTTTTTTTTzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTTTTTTTTTTzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUUUUUUUUUUModBits}{\saildoclabelled{sailRISCVoverloadUUUUUUUUUUUUUzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUUUUUUUUUUz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetUinterruptsUEI}{\saildoclabelled{sailRISCVzzygetzyUinterruptszyUEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_uinterrupts_uei6c329ab1295c95ff6f49fe4076feabea.tex}}}} + +\newcommand{\sailRISCVfnGetUinterruptsUEI}{\saildoclabelled{sailRISCVfnzzygetzyUinterruptszyUEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_uinterrupts_uei6c329ab1295c95ff6f49fe4076feabea.tex}}}} + +\newcommand{\sailRISCVvalSetUinterruptsUEI}{\saildoclabelled{sailRISCVzzysetzyUinterruptszyUEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_uinterrupts_uei6395a09166c9287c4cbab9ca7e87e0bd.tex}}}} + +\newcommand{\sailRISCVfnSetUinterruptsUEI}{\saildoclabelled{sailRISCVfnzzysetzyUinterruptszyUEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_uinterrupts_uei6395a09166c9287c4cbab9ca7e87e0bd.tex}}}} + +\newcommand{\sailRISCVvalUpdateUinterruptsUEI}{\saildoclabelled{sailRISCVzzyupdatezyUinterruptszyUEI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_uinterrupts_ueib05aa22b4bb2fffd287cb5a502f86a7d.tex}}}} + +\newcommand{\sailRISCVfnUpdateUinterruptsUEI}{\saildoclabelled{sailRISCVfnzzyupdatezyUinterruptszyUEI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_uinterrupts_ueib05aa22b4bb2fffd287cb5a502f86a7d.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVVVVVVVVVVupdateUEI}{\saildoclabelled{sailRISCVoverloadVVVVVVVVVVVVVzupdatezyUEI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVVVVVVVVVVzupdate_uei8252f0ae84161aa560a37211f39d1461.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWWWWWWWWWWModUEI}{\saildoclabelled{sailRISCVoverloadWWWWWWWWWWWWWzzymodzyUEI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWWWWWWWWWWz_mod_uei7faef47ef8aacd0d1b2ad1e0530fdf8e.tex}}}} + +\newcommand{\sailRISCVvalGetUinterruptsUTI}{\saildoclabelled{sailRISCVzzygetzyUinterruptszyUTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_uinterrupts_uti4f7a1e53cab567fa843f7436769357a0.tex}}}} + +\newcommand{\sailRISCVfnGetUinterruptsUTI}{\saildoclabelled{sailRISCVfnzzygetzyUinterruptszyUTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_uinterrupts_uti4f7a1e53cab567fa843f7436769357a0.tex}}}} + +\newcommand{\sailRISCVvalSetUinterruptsUTI}{\saildoclabelled{sailRISCVzzysetzyUinterruptszyUTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_uinterrupts_uti74ee6b037b2bfa28007515ce9e1e9566.tex}}}} + +\newcommand{\sailRISCVfnSetUinterruptsUTI}{\saildoclabelled{sailRISCVfnzzysetzyUinterruptszyUTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_uinterrupts_uti74ee6b037b2bfa28007515ce9e1e9566.tex}}}} + +\newcommand{\sailRISCVvalUpdateUinterruptsUTI}{\saildoclabelled{sailRISCVzzyupdatezyUinterruptszyUTI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_uinterrupts_uti881f938d0d5ebb68be2d1bcc7637dc77.tex}}}} + +\newcommand{\sailRISCVfnUpdateUinterruptsUTI}{\saildoclabelled{sailRISCVfnzzyupdatezyUinterruptszyUTI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_uinterrupts_uti881f938d0d5ebb68be2d1bcc7637dc77.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXXXXXXXXXXupdateUTI}{\saildoclabelled{sailRISCVoverloadXXXXXXXXXXXXXzupdatezyUTI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXXXXXXXXXXzupdate_uti7bb127f84633c2b4f4b4de5582168ddf.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYYYYYYYYYYModUTI}{\saildoclabelled{sailRISCVoverloadYYYYYYYYYYYYYzzymodzyUTI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYYYYYYYYYYz_mod_utia23224af950fbe7be4b3db2f7092e6b4.tex}}}} + +\newcommand{\sailRISCVvalGetUinterruptsUSI}{\saildoclabelled{sailRISCVzzygetzyUinterruptszyUSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_uinterrupts_usi1b085056d929d854a848f905b87c060b.tex}}}} + +\newcommand{\sailRISCVfnGetUinterruptsUSI}{\saildoclabelled{sailRISCVfnzzygetzyUinterruptszyUSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_uinterrupts_usi1b085056d929d854a848f905b87c060b.tex}}}} + +\newcommand{\sailRISCVvalSetUinterruptsUSI}{\saildoclabelled{sailRISCVzzysetzyUinterruptszyUSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_uinterrupts_usi8050a61e8750bb4582bb9dda39b65457.tex}}}} + +\newcommand{\sailRISCVfnSetUinterruptsUSI}{\saildoclabelled{sailRISCVfnzzysetzyUinterruptszyUSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_uinterrupts_usi8050a61e8750bb4582bb9dda39b65457.tex}}}} + +\newcommand{\sailRISCVvalUpdateUinterruptsUSI}{\saildoclabelled{sailRISCVzzyupdatezyUinterruptszyUSI}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_uinterrupts_usi1ec1151a92f98583f7c0c3cb9f03ca01.tex}}}} + +\newcommand{\sailRISCVfnUpdateUinterruptsUSI}{\saildoclabelled{sailRISCVfnzzyupdatezyUinterruptszyUSI}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_uinterrupts_usi1ec1151a92f98583f7c0c3cb9f03ca01.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZZZZZZZZZZupdateUSI}{\saildoclabelled{sailRISCVoverloadZZZZZZZZZZZZZzupdatezyUSI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZZZZZZZZZZzupdate_usi3c691c58ab628cbd10b9e21b62e0cfc4.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAAAAAAAAAAModUSI}{\saildoclabelled{sailRISCVoverloadAAAAAAAAAAAAAAzzymodzyUSI}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAAAAAAAAAAz_mod_usif3c3aecb7417cc350ad372adfb40e4d3.tex}}}} + +\newcommand{\sailRISCVvallowerSip}{\saildoclabelled{sailRISCVzlowerzysip}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlower_sipfb2971a9ef35ea1e2a4c00f905ec894c.tex}}}} + +\newcommand{\sailRISCVfnlowerSip}{\saildoclabelled{sailRISCVfnzlowerzysip}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlower_sipfb2971a9ef35ea1e2a4c00f905ec894c.tex}}}} + +\newcommand{\sailRISCVvallowerSie}{\saildoclabelled{sailRISCVzlowerzysie}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlower_siea6b1bfe3227230c0b4c5a544f98a7636.tex}}}} + +\newcommand{\sailRISCVfnlowerSie}{\saildoclabelled{sailRISCVfnzlowerzysie}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlower_siea6b1bfe3227230c0b4c5a544f98a7636.tex}}}} + +\newcommand{\sailRISCVvalliftUip}{\saildoclabelled{sailRISCVzliftzyuip}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlift_uipc541c535c8821c63ef55fd81254b1078.tex}}}} + +\newcommand{\sailRISCVfnliftUip}{\saildoclabelled{sailRISCVfnzliftzyuip}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlift_uipc541c535c8821c63ef55fd81254b1078.tex}}}} + +\newcommand{\sailRISCVvallegalizzeUip}{\saildoclabelled{sailRISCVzlegalizzezyuip}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_uipc8133dbe8104c4fd25f4a3933fa30bbb.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeUip}{\saildoclabelled{sailRISCVfnzlegalizzezyuip}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_uipc8133dbe8104c4fd25f4a3933fa30bbb.tex}}}} + +\newcommand{\sailRISCVvalliftUie}{\saildoclabelled{sailRISCVzliftzyuie}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlift_uied44a5d7049b27cdb894913f74634a628.tex}}}} + +\newcommand{\sailRISCVfnliftUie}{\saildoclabelled{sailRISCVfnzliftzyuie}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlift_uied44a5d7049b27cdb894913f74634a628.tex}}}} + +\newcommand{\sailRISCVvallegalizzeUie}{\saildoclabelled{sailRISCVzlegalizzezyuie}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_uie26bad63954765d654a99bf56da523d30.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeUie}{\saildoclabelled{sailRISCVfnzlegalizzezyuie}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_uie26bad63954765d654a99bf56da523d30.tex}}}} + +\newcommand{\sailRISCVtypeextException}{\saildoclabelled{sailRISCVtypezextzyexception}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_exception91bbea5dcedef746789e1dfa97cb264d.tex}}}} + +\newcommand{\sailRISCVvalhandleTrapExtension}{\saildoclabelled{sailRISCVzhandlezytrapzyextension}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_trap_extension9480b0ad72ce05ffcdcc27185eb4525c.tex}}}} + +\newcommand{\sailRISCVfnhandleTrapExtension}{\saildoclabelled{sailRISCVfnzhandlezytrapzyextension}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_trap_extension9480b0ad72ce05ffcdcc27185eb4525c.tex}}}} + +\newcommand{\sailRISCVvalprepareTrapVector}{\saildoclabelled{sailRISCVzpreparezytrapzyvector}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprepare_trap_vector90a104f40adfa987d74a613f4061790f.tex}}}} + +\newcommand{\sailRISCVfnprepareTrapVector}{\saildoclabelled{sailRISCVfnzpreparezytrapzyvector}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprepare_trap_vector90a104f40adfa987d74a613f4061790f.tex}}}} + +\newcommand{\sailRISCVvalgetXretTarget}{\saildoclabelled{sailRISCVzgetzyxretzytarget}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_xret_target26ce66652c1cd67f2e91b685c1d44e62.tex}}}} + +\newcommand{\sailRISCVfngetXretTarget}{\saildoclabelled{sailRISCVfnzgetzyxretzytarget}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_xret_target26ce66652c1cd67f2e91b685c1d44e62.tex}}}} + +\newcommand{\sailRISCVvalsetXretTarget}{\saildoclabelled{sailRISCVzsetzyxretzytarget}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzset_xret_target81095db6e6bb6da6b746ed406dccd45e.tex}}}} + +\newcommand{\sailRISCVfnsetXretTarget}{\saildoclabelled{sailRISCVfnzsetzyxretzytarget}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzset_xret_target81095db6e6bb6da6b746ed406dccd45e.tex}}}} + +\newcommand{\sailRISCVvalprepareXretTarget}{\saildoclabelled{sailRISCVzpreparezyxretzytarget}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprepare_xret_target77691a306ebd6df5d988335f19693ba0.tex}}}} + +\newcommand{\sailRISCVfnprepareXretTarget}{\saildoclabelled{sailRISCVfnzpreparezyxretzytarget}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprepare_xret_target77691a306ebd6df5d988335f19693ba0.tex}}}} + +\newcommand{\sailRISCVvalgetMtvec}{\saildoclabelled{sailRISCVzgetzymtvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_mtvec134cdc828faab7bf9f19733fba43da2f.tex}}}} + +\newcommand{\sailRISCVfngetMtvec}{\saildoclabelled{sailRISCVfnzgetzymtvec}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_mtvec134cdc828faab7bf9f19733fba43da2f.tex}}}} + +\newcommand{\sailRISCVvalgetStvec}{\saildoclabelled{sailRISCVzgetzystvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_stvec8e871a236060976d6c548af2b67478db.tex}}}} + +\newcommand{\sailRISCVfngetStvec}{\saildoclabelled{sailRISCVfnzgetzystvec}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_stvec8e871a236060976d6c548af2b67478db.tex}}}} + +\newcommand{\sailRISCVvalgetUtvec}{\saildoclabelled{sailRISCVzgetzyutvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_utvec375b7b6fc923ff7174c10f9b93b1b2cf.tex}}}} + +\newcommand{\sailRISCVfngetUtvec}{\saildoclabelled{sailRISCVfnzgetzyutvec}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_utvec375b7b6fc923ff7174c10f9b93b1b2cf.tex}}}} + +\newcommand{\sailRISCVvalsetMtvec}{\saildoclabelled{sailRISCVzsetzymtvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzset_mtvec628ceb1975fa7b69631fcc224f1bbbc0.tex}}}} + +\newcommand{\sailRISCVfnsetMtvec}{\saildoclabelled{sailRISCVfnzsetzymtvec}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzset_mtvec628ceb1975fa7b69631fcc224f1bbbc0.tex}}}} + +\newcommand{\sailRISCVvalsetStvec}{\saildoclabelled{sailRISCVzsetzystvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzset_stvec0d8dcc20a4d9dd912d52b9252d2370a7.tex}}}} + +\newcommand{\sailRISCVfnsetStvec}{\saildoclabelled{sailRISCVfnzsetzystvec}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzset_stvec0d8dcc20a4d9dd912d52b9252d2370a7.tex}}}} + +\newcommand{\sailRISCVvalsetUtvec}{\saildoclabelled{sailRISCVzsetzyutvec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzset_utvec4e028b19c2b4db0c1c1a0a48f1c4a330.tex}}}} + +\newcommand{\sailRISCVfnsetUtvec}{\saildoclabelled{sailRISCVfnzsetzyutvec}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzset_utvec4e028b19c2b4db0c1c1a0a48f1c4a330.tex}}}} + +\newcommand{\sailRISCVtypesyncException}{\saildoclabelled{sailRISCVtypezsynczyexception}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsync_exceptionf6f925de3b34f9256b962854b6415d97.tex}}}} + +\newcommand{\sailRISCVtypebitsRm}{\saildoclabelled{sailRISCVtypezbitszyrm}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezbits_rm5b1f0169c0e4579bf2dcf98ba6079158.tex}}}} + +\newcommand{\sailRISCVtypebitsFflags}{\saildoclabelled{sailRISCVtypezbitszyfflags}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezbits_fflagsed9b9763ebe260174539e00fd7a0a522.tex}}}} + +\newcommand{\sailRISCVtypebitsS}{\saildoclabelled{sailRISCVtypezbitszyS}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezbits_s528d05a73240052d43e6da2026f5b50f.tex}}}} + +\newcommand{\sailRISCVtypebitsD}{\saildoclabelled{sailRISCVtypezbitszyD}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezbits_db59c6343f76a23d300748dc232dd81da.tex}}}} + +\newcommand{\sailRISCVtypebitsW}{\saildoclabelled{sailRISCVtypezbitszyW}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezbits_wcd34ca70f55b1c3a8eca237a0b2e5a5b.tex}}}} + +\newcommand{\sailRISCVtypebitsWU}{\saildoclabelled{sailRISCVtypezbitszyWU}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezbits_wud57fbe06e562e34a1f66b7832875f761.tex}}}} + +\newcommand{\sailRISCVtypebitsL}{\saildoclabelled{sailRISCVtypezbitszyL}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezbits_l07cb308b5e4f91b7017ab58409d32070.tex}}}} + +\newcommand{\sailRISCVtypebitsLU}{\saildoclabelled{sailRISCVtypezbitszyLU}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezbits_lu3ab4327e3a12cfe46ba2eb7149190854.tex}}}} + +\newcommand{\sailRISCVvalupdateSoftfloatFflags}{\saildoclabelled{sailRISCVzupdatezysoftfloatzyfflags}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzupdate_softfloat_fflagsc33a686e24584b0b748b2ae8f801c505.tex}}}} + +\newcommand{\sailRISCVfnupdateSoftfloatFflags}{\saildoclabelled{sailRISCVfnzupdatezysoftfloatzyfflags}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzupdate_softfloat_fflagsc33a686e24584b0b748b2ae8f801c505.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoAdd}{\saildoclabelled{sailRISCVzexternzyf32Add}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32add6570d62f364513d11456621384cd41a4.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoAdd}{\saildoclabelled{sailRISCVzriscvzyf32Add}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32add558e9569237c3f82255e78eba6e4d963.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoAdd}{\saildoclabelled{sailRISCVfnzriscvzyf32Add}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32add558e9569237c3f82255e78eba6e4d963.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoSub}{\saildoclabelled{sailRISCVzexternzyf32Sub}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32sub46595a3cbe22b28fcde81c3635052d96.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoSub}{\saildoclabelled{sailRISCVzriscvzyf32Sub}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32sub247ea008998dd84d9a3c22db11127bea.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoSub}{\saildoclabelled{sailRISCVfnzriscvzyf32Sub}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32sub247ea008998dd84d9a3c22db11127bea.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoMul}{\saildoclabelled{sailRISCVzexternzyf32Mul}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32mul3fa5520c02f9481c619db6b9185fc991.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoMul}{\saildoclabelled{sailRISCVzriscvzyf32Mul}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32mulc9ec954a141b4f26110e9e3c2b42b73c.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoMul}{\saildoclabelled{sailRISCVfnzriscvzyf32Mul}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32mulc9ec954a141b4f26110e9e3c2b42b73c.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoDiv}{\saildoclabelled{sailRISCVzexternzyf32Div}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32diva3f93b8d1944c9eb5853444ef6275b73.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoDiv}{\saildoclabelled{sailRISCVzriscvzyf32Div}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32div86cc53dd9bb61e6f44380c708e0673ca.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoDiv}{\saildoclabelled{sailRISCVfnzriscvzyf32Div}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32div86cc53dd9bb61e6f44380c708e0673ca.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourAdd}{\saildoclabelled{sailRISCVzexternzyf64Add}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64addeb106f14f2c0905dadf390a0565da932.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourAdd}{\saildoclabelled{sailRISCVzriscvzyf64Add}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64add33e6272fa354fe4e7b1963d6545bc4f7.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourAdd}{\saildoclabelled{sailRISCVfnzriscvzyf64Add}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64add33e6272fa354fe4e7b1963d6545bc4f7.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourSub}{\saildoclabelled{sailRISCVzexternzyf64Sub}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64subd720cdc7595c5e294f7877ef74876c27.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourSub}{\saildoclabelled{sailRISCVzriscvzyf64Sub}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64sub64a17c7e3b243ed3af4bc99790d41a9f.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourSub}{\saildoclabelled{sailRISCVfnzriscvzyf64Sub}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64sub64a17c7e3b243ed3af4bc99790d41a9f.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourMul}{\saildoclabelled{sailRISCVzexternzyf64Mul}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64mulf814ecd2e3d0ed473f76dcca74bd1c73.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourMul}{\saildoclabelled{sailRISCVzriscvzyf64Mul}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64mul1bf597fee8433219c830072b7c0b998e.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourMul}{\saildoclabelled{sailRISCVfnzriscvzyf64Mul}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64mul1bf597fee8433219c830072b7c0b998e.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourDiv}{\saildoclabelled{sailRISCVzexternzyf64Div}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64div5b9c0428c30d14b1844b77539325cd9e.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourDiv}{\saildoclabelled{sailRISCVzriscvzyf64Div}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64divecc62207bb7fa437fcf66a19597ada83.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourDiv}{\saildoclabelled{sailRISCVfnzriscvzyf64Div}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64divecc62207bb7fa437fcf66a19597ada83.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoMulAdd}{\saildoclabelled{sailRISCVzexternzyf32MulAdd}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32muladd83ecaa2576af176cb966151d8adbd0ae.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoMulAdd}{\saildoclabelled{sailRISCVzriscvzyf32MulAdd}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32muladdc6b7d5aa910c0cf67022d34e7a745cd8.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoMulAdd}{\saildoclabelled{sailRISCVfnzriscvzyf32MulAdd}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32muladdc6b7d5aa910c0cf67022d34e7a745cd8.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourMulAdd}{\saildoclabelled{sailRISCVzexternzyf64MulAdd}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64muladd15243cc8731c3e0a2ef0ef7f3ed15e68.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourMulAdd}{\saildoclabelled{sailRISCVzriscvzyf64MulAdd}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64muladdf20eb35780f2858aa3087b34aba2250a.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourMulAdd}{\saildoclabelled{sailRISCVfnzriscvzyf64MulAdd}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64muladdf20eb35780f2858aa3087b34aba2250a.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoSqrt}{\saildoclabelled{sailRISCVzexternzyf32Sqrt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32sqrtf11b42be8c2478d6f003de6a9af154f6.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoSqrt}{\saildoclabelled{sailRISCVzriscvzyf32Sqrt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32sqrtd0c4078227e28f52a7984b6a7f89ce8a.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoSqrt}{\saildoclabelled{sailRISCVfnzriscvzyf32Sqrt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32sqrtd0c4078227e28f52a7984b6a7f89ce8a.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourSqrt}{\saildoclabelled{sailRISCVzexternzyf64Sqrt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64sqrta3145a122395bda30fb542d678fd4539.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourSqrt}{\saildoclabelled{sailRISCVzriscvzyf64Sqrt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64sqrta506b6089ecf799deb21b124eaf60f0c.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourSqrt}{\saildoclabelled{sailRISCVfnzriscvzyf64Sqrt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64sqrta506b6089ecf799deb21b124eaf60f0c.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoToIThreeTwo}{\saildoclabelled{sailRISCVzexternzyf32ToI32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32toi326cf4b3bab68206b610e134ff8908ca89.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoToIThreeTwo}{\saildoclabelled{sailRISCVzriscvzyf32ToI32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32toi32b5d471852e14b8b79d2ad8fd065ac832.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoToIThreeTwo}{\saildoclabelled{sailRISCVfnzriscvzyf32ToI32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32toi32b5d471852e14b8b79d2ad8fd065ac832.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoToUiThreeTwo}{\saildoclabelled{sailRISCVzexternzyf32ToUi32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32toui3254cab07407e1a29139940b162c1c3d28.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoToUiThreeTwo}{\saildoclabelled{sailRISCVzriscvzyf32ToUi32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32toui329abf292f8a5b1458fd639f0b62a9b052.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoToUiThreeTwo}{\saildoclabelled{sailRISCVfnzriscvzyf32ToUi32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32toui329abf292f8a5b1458fd639f0b62a9b052.tex}}}} + +\newcommand{\sailRISCVvalexternIThreeTwoToFThreeTwo}{\saildoclabelled{sailRISCVzexternzyi32ToF32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_i32tof32928758eb5e1cef38c85f3df1f2fa8faa.tex}}}} + +\newcommand{\sailRISCVvalriscvIThreeTwoToFThreeTwo}{\saildoclabelled{sailRISCVzriscvzyi32ToF32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_i32tof32262d900b5276fc61cfada0a2c080dd00.tex}}}} + +\newcommand{\sailRISCVfnriscvIThreeTwoToFThreeTwo}{\saildoclabelled{sailRISCVfnzriscvzyi32ToF32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_i32tof32262d900b5276fc61cfada0a2c080dd00.tex}}}} + +\newcommand{\sailRISCVvalexternUiThreeTwoToFThreeTwo}{\saildoclabelled{sailRISCVzexternzyui32ToF32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_ui32tof320d34a36731fc04f9878fe858410678ad.tex}}}} + +\newcommand{\sailRISCVvalriscvUiThreeTwoToFThreeTwo}{\saildoclabelled{sailRISCVzriscvzyui32ToF32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_ui32tof3277c5e2e314e991c265ecd083fea05bf0.tex}}}} + +\newcommand{\sailRISCVfnriscvUiThreeTwoToFThreeTwo}{\saildoclabelled{sailRISCVfnzriscvzyui32ToF32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_ui32tof3277c5e2e314e991c265ecd083fea05bf0.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoToISixFour}{\saildoclabelled{sailRISCVzexternzyf32ToI64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32toi640b3f54fe8e434e95ad11bc87f4692a8c.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoToISixFour}{\saildoclabelled{sailRISCVzriscvzyf32ToI64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32toi640208fd5f6c45fde93d3e7c63a2825d81.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoToISixFour}{\saildoclabelled{sailRISCVfnzriscvzyf32ToI64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32toi640208fd5f6c45fde93d3e7c63a2825d81.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoToUiSixFour}{\saildoclabelled{sailRISCVzexternzyf32ToUi64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32toui6494114a44e0de80b91ab99de5cb70ae02.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoToUiSixFour}{\saildoclabelled{sailRISCVzriscvzyf32ToUi64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32toui6423479b6a7ca0f54a5c926da7d7620403.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoToUiSixFour}{\saildoclabelled{sailRISCVfnzriscvzyf32ToUi64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32toui6423479b6a7ca0f54a5c926da7d7620403.tex}}}} + +\newcommand{\sailRISCVvalexternISixFourToFThreeTwo}{\saildoclabelled{sailRISCVzexternzyi64ToF32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_i64tof3238824aafa28223d09bd70270bcc53a19.tex}}}} + +\newcommand{\sailRISCVvalriscvISixFourToFThreeTwo}{\saildoclabelled{sailRISCVzriscvzyi64ToF32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_i64tof329ea93669bfe183b3595b128f97eb0d64.tex}}}} + +\newcommand{\sailRISCVfnriscvISixFourToFThreeTwo}{\saildoclabelled{sailRISCVfnzriscvzyi64ToF32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_i64tof329ea93669bfe183b3595b128f97eb0d64.tex}}}} + +\newcommand{\sailRISCVvalexternUiSixFourToFThreeTwo}{\saildoclabelled{sailRISCVzexternzyui64ToF32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_ui64tof3222147d78d464deaed8427dd5e9a1f97d.tex}}}} + +\newcommand{\sailRISCVvalriscvUiSixFourToFThreeTwo}{\saildoclabelled{sailRISCVzriscvzyui64ToF32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_ui64tof32006c37b85131ebfdf4c65a0ecf2d321b.tex}}}} + +\newcommand{\sailRISCVfnriscvUiSixFourToFThreeTwo}{\saildoclabelled{sailRISCVfnzriscvzyui64ToF32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_ui64tof32006c37b85131ebfdf4c65a0ecf2d321b.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourToIThreeTwo}{\saildoclabelled{sailRISCVzexternzyf64ToI32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64toi328ccd500b2d8a0508350bd93919a71172.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourToIThreeTwo}{\saildoclabelled{sailRISCVzriscvzyf64ToI32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64toi32390e064989835e074118b56d834e6d48.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourToIThreeTwo}{\saildoclabelled{sailRISCVfnzriscvzyf64ToI32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64toi32390e064989835e074118b56d834e6d48.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourToUiThreeTwo}{\saildoclabelled{sailRISCVzexternzyf64ToUi32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64toui3201aa4791323c1c065734b1b292dfc483.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourToUiThreeTwo}{\saildoclabelled{sailRISCVzriscvzyf64ToUi32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64toui32df8698a76aef244e4d021f6db07ed8aa.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourToUiThreeTwo}{\saildoclabelled{sailRISCVfnzriscvzyf64ToUi32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64toui32df8698a76aef244e4d021f6db07ed8aa.tex}}}} + +\newcommand{\sailRISCVvalexternIThreeTwoToFSixFour}{\saildoclabelled{sailRISCVzexternzyi32ToF64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_i32tof64fd00956ce74e2f05bee6c0c09b2fe4e9.tex}}}} + +\newcommand{\sailRISCVvalriscvIThreeTwoToFSixFour}{\saildoclabelled{sailRISCVzriscvzyi32ToF64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_i32tof64e97e000de9456cb796f52f30b64c9715.tex}}}} + +\newcommand{\sailRISCVfnriscvIThreeTwoToFSixFour}{\saildoclabelled{sailRISCVfnzriscvzyi32ToF64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_i32tof64e97e000de9456cb796f52f30b64c9715.tex}}}} + +\newcommand{\sailRISCVvalexternUiThreeTwoToFSixFour}{\saildoclabelled{sailRISCVzexternzyui32ToF64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_ui32tof64e2fa1dc20fc15cc4e3898f79cd2790c4.tex}}}} + +\newcommand{\sailRISCVvalriscvUiThreeTwoToFSixFour}{\saildoclabelled{sailRISCVzriscvzyui32ToF64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_ui32tof6485dd2d5d0818e64745a16c8bd2e6f3ad.tex}}}} + +\newcommand{\sailRISCVfnriscvUiThreeTwoToFSixFour}{\saildoclabelled{sailRISCVfnzriscvzyui32ToF64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_ui32tof6485dd2d5d0818e64745a16c8bd2e6f3ad.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourToISixFour}{\saildoclabelled{sailRISCVzexternzyf64ToI64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64toi641dd890d7fbf7a24774c052a9c246250f.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourToISixFour}{\saildoclabelled{sailRISCVzriscvzyf64ToI64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64toi64b279b582ab789b7d76bd4628cf864db9.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourToISixFour}{\saildoclabelled{sailRISCVfnzriscvzyf64ToI64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64toi64b279b582ab789b7d76bd4628cf864db9.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourToUiSixFour}{\saildoclabelled{sailRISCVzexternzyf64ToUi64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64toui64941713ad89e209a4feb9e7b47c7194bb.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourToUiSixFour}{\saildoclabelled{sailRISCVzriscvzyf64ToUi64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64toui64a8c06df736f513b3e5ec73bfb9385733.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourToUiSixFour}{\saildoclabelled{sailRISCVfnzriscvzyf64ToUi64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64toui64a8c06df736f513b3e5ec73bfb9385733.tex}}}} + +\newcommand{\sailRISCVvalexternISixFourToFSixFour}{\saildoclabelled{sailRISCVzexternzyi64ToF64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_i64tof64aed9270eafe2e670b0a96825020ff419.tex}}}} + +\newcommand{\sailRISCVvalriscvISixFourToFSixFour}{\saildoclabelled{sailRISCVzriscvzyi64ToF64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_i64tof645552b730328b5e488a5469c4d60ba48e.tex}}}} + +\newcommand{\sailRISCVfnriscvISixFourToFSixFour}{\saildoclabelled{sailRISCVfnzriscvzyi64ToF64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_i64tof645552b730328b5e488a5469c4d60ba48e.tex}}}} + +\newcommand{\sailRISCVvalexternUiSixFourToFSixFour}{\saildoclabelled{sailRISCVzexternzyui64ToF64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_ui64tof64b071761b350c914c21ca717b7ff70706.tex}}}} + +\newcommand{\sailRISCVvalriscvUiSixFourToFSixFour}{\saildoclabelled{sailRISCVzriscvzyui64ToF64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_ui64tof647831c3694f6a0849ff1899ade6b08220.tex}}}} + +\newcommand{\sailRISCVfnriscvUiSixFourToFSixFour}{\saildoclabelled{sailRISCVfnzriscvzyui64ToF64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_ui64tof647831c3694f6a0849ff1899ade6b08220.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoToFSixFour}{\saildoclabelled{sailRISCVzexternzyf32ToF64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32tof64195ee529424460f0ea430364e6969b58.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoToFSixFour}{\saildoclabelled{sailRISCVzriscvzyf32ToF64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32tof6463cfa807ac39aea5d45f7cb4ee2d9248.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoToFSixFour}{\saildoclabelled{sailRISCVfnzriscvzyf32ToF64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32tof6463cfa807ac39aea5d45f7cb4ee2d9248.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourToFThreeTwo}{\saildoclabelled{sailRISCVzexternzyf64ToF32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64tof329e6bdb39c58bf46aad8078a255a69675.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourToFThreeTwo}{\saildoclabelled{sailRISCVzriscvzyf64ToF32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64tof326b35917fadbed27b5d3cecd2f8762d01.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourToFThreeTwo}{\saildoclabelled{sailRISCVfnzriscvzyf64ToF32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64tof326b35917fadbed27b5d3cecd2f8762d01.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoLt}{\saildoclabelled{sailRISCVzexternzyf32Lt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32lt76345a6740b5e66e208ded2a17434c50.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoLt}{\saildoclabelled{sailRISCVzriscvzyf32Lt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32lt4e30f0abd945d0950f5c75c3397e58b8.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoLt}{\saildoclabelled{sailRISCVfnzriscvzyf32Lt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32lt4e30f0abd945d0950f5c75c3397e58b8.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoLe}{\saildoclabelled{sailRISCVzexternzyf32Le}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32le97e1d493296eff955b8dd2b74525e2ad.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoLe}{\saildoclabelled{sailRISCVzriscvzyf32Le}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32le5580a4448a4b6b5ef89a7a80b6f5e23a.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoLe}{\saildoclabelled{sailRISCVfnzriscvzyf32Le}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32le5580a4448a4b6b5ef89a7a80b6f5e23a.tex}}}} + +\newcommand{\sailRISCVvalexternFThreeTwoEq}{\saildoclabelled{sailRISCVzexternzyf32Eq}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f32eq1152b8b8a8d02d885ad3651e36443f8b.tex}}}} + +\newcommand{\sailRISCVvalriscvFThreeTwoEq}{\saildoclabelled{sailRISCVzriscvzyf32Eq}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f32eqbb5f45f4706cd2893dcaf9d3d15d7b11.tex}}}} + +\newcommand{\sailRISCVfnriscvFThreeTwoEq}{\saildoclabelled{sailRISCVfnzriscvzyf32Eq}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f32eqbb5f45f4706cd2893dcaf9d3d15d7b11.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourLt}{\saildoclabelled{sailRISCVzexternzyf64Lt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64lt9068248c1389b86f906917568fb33729.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourLt}{\saildoclabelled{sailRISCVzriscvzyf64Lt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64lt7fe1cae2d039f2771557eafe4cff0d62.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourLt}{\saildoclabelled{sailRISCVfnzriscvzyf64Lt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64lt7fe1cae2d039f2771557eafe4cff0d62.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourLe}{\saildoclabelled{sailRISCVzexternzyf64Le}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64le607de75fdc830000d71db4eee82f8025.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourLe}{\saildoclabelled{sailRISCVzriscvzyf64Le}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64leedff2d39af8855d31503064db9e49593.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourLe}{\saildoclabelled{sailRISCVfnzriscvzyf64Le}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64leedff2d39af8855d31503064db9e49593.tex}}}} + +\newcommand{\sailRISCVvalexternFSixFourEq}{\saildoclabelled{sailRISCVzexternzyf64Eq}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextern_f64eqb2180e00de7f0745336b1c04e9ead3f3.tex}}}} + +\newcommand{\sailRISCVvalriscvFSixFourEq}{\saildoclabelled{sailRISCVzriscvzyf64Eq}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzriscv_f64eq911a3686fab30a7dbcecd0d21d7bc788.tex}}}} + +\newcommand{\sailRISCVfnriscvFSixFourEq}{\saildoclabelled{sailRISCVfnzriscvzyf64Eq}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzriscv_f64eq911a3686fab30a7dbcecd0d21d7bc788.tex}}}} + +\newcommand{\sailRISCVvaldirtyFdContext}{\saildoclabelled{sailRISCVzdirtyzyfdzycontext}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzdirty_fd_context8f0fcc8b7745d7294388295307af4058.tex}}}} + +\newcommand{\sailRISCVfndirtyFdContext}{\saildoclabelled{sailRISCVfnzdirtyzyfdzycontext}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzdirty_fd_context8f0fcc8b7745d7294388295307af4058.tex}}}} + +\newcommand{\sailRISCVvalrF}{\saildoclabelled{sailRISCVzrF}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrff2ed1bbacd3ac737af7186c6d8884885.tex}}}} + +\newcommand{\sailRISCVfnrF}{\saildoclabelled{sailRISCVfnzrF}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrff2ed1bbacd3ac737af7186c6d8884885.tex}}}} + +\newcommand{\sailRISCVvalwF}{\saildoclabelled{sailRISCVzwF}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwfd3e403dd75784ce7e0cfdf609e32706e.tex}}}} + +\newcommand{\sailRISCVfnwF}{\saildoclabelled{sailRISCVfnzwF}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwfd3e403dd75784ce7e0cfdf609e32706e.tex}}}} + +\newcommand{\sailRISCVvalrFBits}{\saildoclabelled{sailRISCVzrFzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrf_bits63ac239a90c8d4bdc4ca1b8375c08531.tex}}}} + +\newcommand{\sailRISCVfnrFBits}{\saildoclabelled{sailRISCVfnzrFzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrf_bits63ac239a90c8d4bdc4ca1b8375c08531.tex}}}} + +\newcommand{\sailRISCVvalwFBits}{\saildoclabelled{sailRISCVzwFzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwf_bits141c8aafc4ef81f118d39a00d8a5249d.tex}}}} + +\newcommand{\sailRISCVfnwFBits}{\saildoclabelled{sailRISCVfnzwFzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwf_bits141c8aafc4ef81f118d39a00d8a5249d.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBBBBBBBBBBF}{\saildoclabelled{sailRISCVoverloadBBBBBBBBBBBBBBzF}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBBBBBBBBBBzf71805d10b9ea2a56437652aba0daf9bf.tex}}}} + +\newcommand{\sailRISCVvalfregNameAbi}{\saildoclabelled{sailRISCVzfregzynamezyabi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfreg_name_abi149ff973f4a58e634d652021d3e44de0.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCCCCCCCCCCtoStr}{\saildoclabelled{sailRISCVoverloadCCCCCCCCCCCCCCztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCCCCCCCCCCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} + +\newcommand{\sailRISCVvalfregName}{\saildoclabelled{sailRISCVzfregzyname}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfreg_name4ac4601cc383d5edd878a00fc0bde952.tex}}}} + +\newcommand{\sailRISCVvalinitFdextRegs}{\saildoclabelled{sailRISCVzinitzyfdextzyregs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinit_fdext_regs66a16bff324f831ac63cd022934bcc14.tex}}}} + +\newcommand{\sailRISCVfninitFdextRegs}{\saildoclabelled{sailRISCVfnzinitzyfdextzyregs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinit_fdext_regs66a16bff324f831ac63cd022934bcc14.tex}}}} + +\newcommand{\sailRISCVtypeFcsr}{\saildoclabelled{sailRISCVtypezFcsr}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezfcsrb3f3a19258d9652856cfe0e745b7acf3.tex}}}} + +\newcommand{\sailRISCVvalMkFcsr}{\saildoclabelled{sailRISCVzMkzyFcsr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_fcsr9657e355ebbcf62f95e4a48aa5de149a.tex}}}} + +\newcommand{\sailRISCVfnMkFcsr}{\saildoclabelled{sailRISCVfnzMkzyFcsr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_fcsr9657e355ebbcf62f95e4a48aa5de149a.tex}}}} + +\newcommand{\sailRISCVvalGetFcsrBits}{\saildoclabelled{sailRISCVzzygetzyFcsrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_fcsr_bits38eb65790eec4fcba3d93a546d99637e.tex}}}} + +\newcommand{\sailRISCVfnGetFcsrBits}{\saildoclabelled{sailRISCVfnzzygetzyFcsrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_fcsr_bits38eb65790eec4fcba3d93a546d99637e.tex}}}} + +\newcommand{\sailRISCVvalSetFcsrBits}{\saildoclabelled{sailRISCVzzysetzyFcsrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_fcsr_bits14808d6e9585f49863a62ef97cfccc18.tex}}}} + +\newcommand{\sailRISCVfnSetFcsrBits}{\saildoclabelled{sailRISCVfnzzysetzyFcsrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_fcsr_bits14808d6e9585f49863a62ef97cfccc18.tex}}}} + +\newcommand{\sailRISCVvalUpdateFcsrBits}{\saildoclabelled{sailRISCVzzyupdatezyFcsrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_fcsr_bitsd93593273c229b56f42c5419848120a5.tex}}}} + +\newcommand{\sailRISCVfnUpdateFcsrBits}{\saildoclabelled{sailRISCVfnzzyupdatezyFcsrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_fcsr_bitsd93593273c229b56f42c5419848120a5.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDDDDDDDDDDDupdateBits}{\saildoclabelled{sailRISCVoverloadDDDDDDDDDDDDDDzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDDDDDDDDDDDzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEEEEEEEEEEEModBits}{\saildoclabelled{sailRISCVoverloadEEEEEEEEEEEEEEzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEEEEEEEEEEEz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetFcsrFRM}{\saildoclabelled{sailRISCVzzygetzyFcsrzyFRM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_fcsr_frmc585de536fb10558f0653a1315c2301e.tex}}}} + +\newcommand{\sailRISCVfnGetFcsrFRM}{\saildoclabelled{sailRISCVfnzzygetzyFcsrzyFRM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_fcsr_frmc585de536fb10558f0653a1315c2301e.tex}}}} + +\newcommand{\sailRISCVvalSetFcsrFRM}{\saildoclabelled{sailRISCVzzysetzyFcsrzyFRM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_fcsr_frmadaccc6e48224bd13dc49815c7dca973.tex}}}} + +\newcommand{\sailRISCVfnSetFcsrFRM}{\saildoclabelled{sailRISCVfnzzysetzyFcsrzyFRM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_fcsr_frmadaccc6e48224bd13dc49815c7dca973.tex}}}} + +\newcommand{\sailRISCVvalUpdateFcsrFRM}{\saildoclabelled{sailRISCVzzyupdatezyFcsrzyFRM}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_fcsr_frmdde96c8b780c41e6aa00deb4160779be.tex}}}} + +\newcommand{\sailRISCVfnUpdateFcsrFRM}{\saildoclabelled{sailRISCVfnzzyupdatezyFcsrzyFRM}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_fcsr_frmdde96c8b780c41e6aa00deb4160779be.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFFFFFFFFFFFupdateFRM}{\saildoclabelled{sailRISCVoverloadFFFFFFFFFFFFFFzupdatezyFRM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFFFFFFFFFFFzupdate_frm523f62f4860983773adf9a52ee1eea5c.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGGGGGGGGGGGModFRM}{\saildoclabelled{sailRISCVoverloadGGGGGGGGGGGGGGzzymodzyFRM}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGGGGGGGGGGGz_mod_frmd6735957b64e7c0e8f6762761df1daef.tex}}}} + +\newcommand{\sailRISCVvalGetFcsrFFLAGS}{\saildoclabelled{sailRISCVzzygetzyFcsrzyFFLAGS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_fcsr_fflagse7920eae191e6251650c82768d152824.tex}}}} + +\newcommand{\sailRISCVfnGetFcsrFFLAGS}{\saildoclabelled{sailRISCVfnzzygetzyFcsrzyFFLAGS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_fcsr_fflagse7920eae191e6251650c82768d152824.tex}}}} + +\newcommand{\sailRISCVvalSetFcsrFFLAGS}{\saildoclabelled{sailRISCVzzysetzyFcsrzyFFLAGS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_fcsr_fflagsd8192cedf9e30718ca38134692e797b3.tex}}}} + +\newcommand{\sailRISCVfnSetFcsrFFLAGS}{\saildoclabelled{sailRISCVfnzzysetzyFcsrzyFFLAGS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_fcsr_fflagsd8192cedf9e30718ca38134692e797b3.tex}}}} + +\newcommand{\sailRISCVvalUpdateFcsrFFLAGS}{\saildoclabelled{sailRISCVzzyupdatezyFcsrzyFFLAGS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_fcsr_fflags358f6ae3cab298c0e35ab7d81a328b5f.tex}}}} + +\newcommand{\sailRISCVfnUpdateFcsrFFLAGS}{\saildoclabelled{sailRISCVfnzzyupdatezyFcsrzyFFLAGS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_fcsr_fflags358f6ae3cab298c0e35ab7d81a328b5f.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHHHHHHHHHHHupdateFFLAGS}{\saildoclabelled{sailRISCVoverloadHHHHHHHHHHHHHHzupdatezyFFLAGS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHHHHHHHHHHHzupdate_fflags40cb509aa136e461ae0ef1ffa4627b5a.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIIIIIIIIIIIModFFLAGS}{\saildoclabelled{sailRISCVoverloadIIIIIIIIIIIIIIzzymodzyFFLAGS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIIIIIIIIIIIz_mod_fflags96236e6dd2fda3eab086581987046fc9.tex}}}} + +\newcommand{\sailRISCVvalextWriteFcsr}{\saildoclabelled{sailRISCVzextzywritezyfcsr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_write_fcsr8225c20959aaf9205d48c42ffe341a87.tex}}}} + +\newcommand{\sailRISCVfnextWriteFcsr}{\saildoclabelled{sailRISCVfnzextzywritezyfcsr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_write_fcsr8225c20959aaf9205d48c42ffe341a87.tex}}}} + +\newcommand{\sailRISCVvalwriteFflags}{\saildoclabelled{sailRISCVzwritezyfflags}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwrite_fflagsf7610eb4597d886b515ad9553608a8d7.tex}}}} + +\newcommand{\sailRISCVfnwriteFflags}{\saildoclabelled{sailRISCVfnzwritezyfflags}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwrite_fflagsf7610eb4597d886b515ad9553608a8d7.tex}}}} + +\newcommand{\sailRISCVvalaccrueFflags}{\saildoclabelled{sailRISCVzaccruezyfflags}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzaccrue_fflags6f6e494f89bde56691f40e88b063e194.tex}}}} + +\newcommand{\sailRISCVfnaccrueFflags}{\saildoclabelled{sailRISCVfnzaccruezyfflags}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzaccrue_fflags6f6e494f89bde56691f40e88b063e194.tex}}}} + +\newcommand{\sailRISCVfncsrName}{\saildoclabelled{sailRISCVfnzcsrzyname}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcsr_name355619c0d72f0a56dfaf2d45f4b72967.tex}}}} + +\newcommand{\sailRISCVfclhaveUsrModeextIsCSRDefined}{\saildoclabelled{sailRISCVfclhaveUsrModezextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclhaveUsrModezext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclandBoolextIsCSRDefined}{\saildoclabelled{sailRISCVfclandBoolzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclandBoolzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclorBoolextIsCSRDefined}{\saildoclabelled{sailRISCVfclorBoolzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclorBoolzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclandBoolAextIsCSRDefined}{\saildoclabelled{sailRISCVfclandBoolAzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclandBoolAzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclandBoolBextIsCSRDefined}{\saildoclabelled{sailRISCVfclandBoolBzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclandBoolBzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclandBoolCextIsCSRDefined}{\saildoclabelled{sailRISCVfclandBoolCzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclandBoolCzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclandBoolDextIsCSRDefined}{\saildoclabelled{sailRISCVfclandBoolDzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclandBoolDzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclandBoolEextIsCSRDefined}{\saildoclabelled{sailRISCVfclandBoolEzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclandBoolEzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclandBoolFextIsCSRDefined}{\saildoclabelled{sailRISCVfclandBoolFzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclandBoolFzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclandBoolGextIsCSRDefined}{\saildoclabelled{sailRISCVfclandBoolGzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclandBoolGzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclandBoolHextIsCSRDefined}{\saildoclabelled{sailRISCVfclandBoolHzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclandBoolHzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclorBoolAextIsCSRDefined}{\saildoclabelled{sailRISCVfclorBoolAzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclorBoolAzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclorBoolBextIsCSRDefined}{\saildoclabelled{sailRISCVfclorBoolBzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclorBoolBzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclorBoolCextIsCSRDefined}{\saildoclabelled{sailRISCVfclorBoolCzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclorBoolCzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + +\newcommand{\sailRISCVfclextIsCSRDefined}{\saildoclabelled{sailRISCVfclzextzyiszyCSRzydefined}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex}}}} + + + +\newcommand{\sailRISCVfclGetCcsrBitsuccsrextReadCSR}{\saildoclabelled{sailRISCVfclGetCcsrBitsuccsrzextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclGetCcsrBitsuccsrzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfclGetCcsrBitssccsrextReadCSR}{\saildoclabelled{sailRISCVfclGetCcsrBitssccsrzextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclGetCcsrBitssccsrzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfclGetCcsrBitsmccsrextReadCSR}{\saildoclabelled{sailRISCVfclGetCcsrBitsmccsrzextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclGetCcsrBitsmccsrzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfclGetUstatusBitslowerSstatuslowerMstatusmstatusextReadCSR}{\saildoclabelled{sailRISCVfclGetUstatusBitslowerSstatuslowerMstatusmstatuszextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclGetUstatusBitslowerSstatuslowerMstatusmstatuszext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfclGetUinterruptsBitslowerSieextReadCSR}{\saildoclabelled{sailRISCVfclGetUinterruptsBitslowerSiezextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclGetUinterruptsBitslowerSiezext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfclgetUtvecextReadCSR}{\saildoclabelled{sailRISCVfclgetUtveczextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclgetUtveczext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfcluscratchextReadCSR}{\saildoclabelled{sailRISCVfcluscratchzextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fcluscratchzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfclandVecextReadCSR}{\saildoclabelled{sailRISCVfclandVeczextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclandVeczext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfclGetMcauseBitsucauseextReadCSR}{\saildoclabelled{sailRISCVfclGetMcauseBitsucausezextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclGetMcauseBitsucausezext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfclutvalextReadCSR}{\saildoclabelled{sailRISCVfclutvalzextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclutvalzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfclGetUinterruptsBitslowerSipextReadCSR}{\saildoclabelled{sailRISCVfclGetUinterruptsBitslowerSipzextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclGetUinterruptsBitslowerSipzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfclEXTZextReadCSR}{\saildoclabelled{sailRISCVfclEXTZzextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclEXTZzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfclEXTZAextReadCSR}{\saildoclabelled{sailRISCVfclEXTZAzextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclEXTZAzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfclEXTZBextReadCSR}{\saildoclabelled{sailRISCVfclEXTZBzextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclEXTZBzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + +\newcommand{\sailRISCVfclNoneextReadCSR}{\saildoclabelled{sailRISCVfclNonezextzyreadzyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclNonezext_read_csr8af202f75b7d6e7536c08d920bd54264.tex}}}} + + + +\newcommand{\sailRISCVfclextWriteCSR}{\saildoclabelled{sailRISCVfclzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclAextWriteCSR}{\saildoclabelled{sailRISCVfclAzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclAzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclBextWriteCSR}{\saildoclabelled{sailRISCVfclBzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclBzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclCextWriteCSR}{\saildoclabelled{sailRISCVfclCzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclDextWriteCSR}{\saildoclabelled{sailRISCVfclDzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclDzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclEextWriteCSR}{\saildoclabelled{sailRISCVfclEzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclEzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclFextWriteCSR}{\saildoclabelled{sailRISCVfclFzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclGextWriteCSR}{\saildoclabelled{sailRISCVfclGzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclGzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclHextWriteCSR}{\saildoclabelled{sailRISCVfclHzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclHzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclIextWriteCSR}{\saildoclabelled{sailRISCVfclIzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclIzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclJextWriteCSR}{\saildoclabelled{sailRISCVfclJzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclJzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclKextWriteCSR}{\saildoclabelled{sailRISCVfclKzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclKzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclLextWriteCSR}{\saildoclabelled{sailRISCVfclLzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclLzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclMextWriteCSR}{\saildoclabelled{sailRISCVfclMzextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclMzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + +\newcommand{\sailRISCVfclNoneextWriteCSR}{\saildoclabelled{sailRISCVfclNonezextzywritezyCSR}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclNonezext_write_csrea3e63f4d0be7079660a260c43b112cd.tex}}}} + + + +\newcommand{\sailRISCVvalcsrAccess}{\saildoclabelled{sailRISCVzcsrAccess}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcsraccess68432d7ad570023367f89beb42b653aa.tex}}}} + +\newcommand{\sailRISCVfncsrAccess}{\saildoclabelled{sailRISCVfnzcsrAccess}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcsraccess68432d7ad570023367f89beb42b653aa.tex}}}} + +\newcommand{\sailRISCVvalcsrPriv}{\saildoclabelled{sailRISCVzcsrPriv}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcsrprivc196a9e4f8a034a73a295c0ac67907ed.tex}}}} + +\newcommand{\sailRISCVfncsrPriv}{\saildoclabelled{sailRISCVfnzcsrPriv}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcsrprivc196a9e4f8a034a73a295c0ac67907ed.tex}}}} + +\newcommand{\sailRISCVvalisCSRDefined}{\saildoclabelled{sailRISCVziszyCSRzydefined}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzis_csr_definedcd68bcdc8a87dceb6e3521cc036a67d0.tex}}}} + +\newcommand{\sailRISCVfnisCSRDefined}{\saildoclabelled{sailRISCVfnziszyCSRzydefined}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzis_csr_definedcd68bcdc8a87dceb6e3521cc036a67d0.tex}}}} + +\newcommand{\sailRISCVvalcheckCSRAccess}{\saildoclabelled{sailRISCVzcheckzyCSRzyaccess}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcheck_csr_access77b52cf2ed56bd5489c2fcc29e6efff7.tex}}}} + +\newcommand{\sailRISCVfncheckCSRAccess}{\saildoclabelled{sailRISCVfnzcheckzyCSRzyaccess}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcheck_csr_access77b52cf2ed56bd5489c2fcc29e6efff7.tex}}}} + +\newcommand{\sailRISCVvalcheckTVMSATP}{\saildoclabelled{sailRISCVzcheckzyTVMzySATP}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcheck_tvm_satp8e66c1c4a67c389d24c42619a3634b21.tex}}}} + +\newcommand{\sailRISCVfncheckTVMSATP}{\saildoclabelled{sailRISCVfnzcheckzyTVMzySATP}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcheck_tvm_satp8e66c1c4a67c389d24c42619a3634b21.tex}}}} + +\newcommand{\sailRISCVvalcheckCounteren}{\saildoclabelled{sailRISCVzcheckzyCounteren}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcheck_counteren24e3081662742c5feea4ad876dc0a51c.tex}}}} + +\newcommand{\sailRISCVfncheckCounteren}{\saildoclabelled{sailRISCVfnzcheckzyCounteren}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcheck_counteren24e3081662742c5feea4ad876dc0a51c.tex}}}} + +\newcommand{\sailRISCVvalcheckCSR}{\saildoclabelled{sailRISCVzcheckzyCSR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcheck_csr588ba7a7f36d1f6476f0b3640406ee0a.tex}}}} + +\newcommand{\sailRISCVfncheckCSR}{\saildoclabelled{sailRISCVfnzcheckzyCSR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcheck_csr588ba7a7f36d1f6476f0b3640406ee0a.tex}}}} + +\newcommand{\sailRISCVvalspeculateConditional}{\saildoclabelled{sailRISCVzspeculatezyconditional}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzspeculate_conditionalc9cfcf9f8fbedbbbb1846b896e477d5c.tex}}}} + +\newcommand{\sailRISCVvalloadReservation}{\saildoclabelled{sailRISCVzloadzyreservation}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzload_reservationca254f1d85cbf90f1662b9f77f637106.tex}}}} + +\newcommand{\sailRISCVvalmatchReservation}{\saildoclabelled{sailRISCVzmatchzyreservation}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmatch_reservationedafe654d6b1fee1b351613706caf96e.tex}}}} + +\newcommand{\sailRISCVvalcancelReservation}{\saildoclabelled{sailRISCVzcancelzyreservation}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcancel_reservationf12c9af3ed835ad5be485ac1fad8d56f.tex}}}} + +\newcommand{\sailRISCVvalexceptionDelegatee}{\saildoclabelled{sailRISCVzexceptionzydelegatee}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzexception_delegateefb7e9252abe9f7e50e2f06577208c695.tex}}}} + +\newcommand{\sailRISCVfnexceptionDelegatee}{\saildoclabelled{sailRISCVfnzexceptionzydelegatee}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzexception_delegateefb7e9252abe9f7e50e2f06577208c695.tex}}}} + +\newcommand{\sailRISCVvalfindPendingInterrupt}{\saildoclabelled{sailRISCVzfindPendingInterrupt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfindpendinginterrupt0ed4e5cc6469ca27b20724b51027ab4c.tex}}}} + +\newcommand{\sailRISCVfnfindPendingInterrupt}{\saildoclabelled{sailRISCVfnzfindPendingInterrupt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfindpendinginterrupt0ed4e5cc6469ca27b20724b51027ab4c.tex}}}} + +\newcommand{\sailRISCVtypeinterruptSet}{\saildoclabelled{sailRISCVtypezinterruptzyset}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezinterrupt_set44973ef906c7020fc165399cdb4dc72c.tex}}}} + +\newcommand{\sailRISCVvalprocessPending}{\saildoclabelled{sailRISCVzprocessPending}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprocesspendingf31f33d163f06483630c9da88eafecaa.tex}}}} + +\newcommand{\sailRISCVfnprocessPending}{\saildoclabelled{sailRISCVfnzprocessPending}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprocesspendingf31f33d163f06483630c9da88eafecaa.tex}}}} + +\newcommand{\sailRISCVvalgetPendingSet}{\saildoclabelled{sailRISCVzgetPendingSet}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgetpendingsetfe7aa2453fb185b904f0c1c2ec773ed8.tex}}}} + +\newcommand{\sailRISCVfngetPendingSet}{\saildoclabelled{sailRISCVfnzgetPendingSet}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgetpendingsetfe7aa2453fb185b904f0c1c2ec773ed8.tex}}}} + +\newcommand{\sailRISCVvaldispatchInterrupt}{\saildoclabelled{sailRISCVzdispatchInterrupt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzdispatchinterruptaf83562ba97e1882252696fd8999b3e7.tex}}}} + +\newcommand{\sailRISCVfndispatchInterrupt}{\saildoclabelled{sailRISCVfnzdispatchInterrupt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzdispatchinterruptaf83562ba97e1882252696fd8999b3e7.tex}}}} + +\newcommand{\sailRISCVtypectlResult}{\saildoclabelled{sailRISCVtypezctlzyresult}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezctl_result052149e0767cf8ed055fce7a562f2c3c.tex}}}} + +\newcommand{\sailRISCVvaltval}{\saildoclabelled{sailRISCVztval}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztval0ee7d37a987a82754891fc591aec5852.tex}}}} + +\newcommand{\sailRISCVfntval}{\saildoclabelled{sailRISCVfnztval}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztval0ee7d37a987a82754891fc591aec5852.tex}}}} + +\newcommand{\sailRISCVvalrvfiTrap}{\saildoclabelled{sailRISCVzrvfizytrap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrvfi_trap0d0ddd87deff120444aa8feac182c6ce.tex}}}} + +\newcommand{\sailRISCVfnrvfiTrap}{\saildoclabelled{sailRISCVfnzrvfizytrap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrvfi_trap0d0ddd87deff120444aa8feac182c6ce.tex}}}} + +\newcommand{\sailRISCVvaltrapHandler}{\saildoclabelled{sailRISCVztrapzyhandler}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztrap_handler0acf2ac9f6239ac64448b463d4df9cf4.tex}}}} + +\newcommand{\sailRISCVfntrapHandler}{\saildoclabelled{sailRISCVfnztrapzyhandler}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztrap_handler0acf2ac9f6239ac64448b463d4df9cf4.tex}}}} + +\newcommand{\sailRISCVvalexceptionHandler}{\saildoclabelled{sailRISCVzexceptionzyhandler}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzexception_handlerf03729146a8718cee62ce35044e16202.tex}}}} + +\newcommand{\sailRISCVfnexceptionHandler}{\saildoclabelled{sailRISCVfnzexceptionzyhandler}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzexception_handlerf03729146a8718cee62ce35044e16202.tex}}}} + +\newcommand{\sailRISCVvalhandleMemException}{\saildoclabelled{sailRISCVzhandlezymemzyexception}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_mem_exceptionec2a0168c4f7affdb0652fb9992ac72e.tex}}}} + +\newcommand{\sailRISCVfnhandleMemException}{\saildoclabelled{sailRISCVfnzhandlezymemzyexception}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_mem_exceptionec2a0168c4f7affdb0652fb9992ac72e.tex}}}} + +\newcommand{\sailRISCVvalhandleException}{\saildoclabelled{sailRISCVzhandlezyexception}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_exception5b7a94266182a8a2ef0291c83b256387.tex}}}} + +\newcommand{\sailRISCVfnhandleException}{\saildoclabelled{sailRISCVfnzhandlezyexception}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_exception5b7a94266182a8a2ef0291c83b256387.tex}}}} + +\newcommand{\sailRISCVvalhandleInterrupt}{\saildoclabelled{sailRISCVzhandlezyinterrupt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_interrupt9048a02caa891e49449f7a1f3f4e9ee4.tex}}}} + +\newcommand{\sailRISCVfnhandleInterrupt}{\saildoclabelled{sailRISCVfnzhandlezyinterrupt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_interrupt9048a02caa891e49449f7a1f3f4e9ee4.tex}}}} + +\newcommand{\sailRISCVvalinitSys}{\saildoclabelled{sailRISCVzinitzysys}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinit_sysc92898d1b2b72595dd36bce10e6a67fb.tex}}}} + +\newcommand{\sailRISCVfninitSys}{\saildoclabelled{sailRISCVfnzinitzysys}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinit_sysc92898d1b2b72595dd36bce10e6a67fb.tex}}}} + +\newcommand{\sailRISCVtypeMemoryOpResult}{\saildoclabelled{sailRISCVtypezMemoryOpResult}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezmemoryopresult3416532231724086920f553567ecf72c.tex}}}} + +\newcommand{\sailRISCVvalMemoryOpResultAddMeta}{\saildoclabelled{sailRISCVzMemoryOpResultzyaddzymeta}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmemoryopresult_add_meta6f4337fb08e42f593b3375a2d1083593.tex}}}} + +\newcommand{\sailRISCVfnMemoryOpResultAddMeta}{\saildoclabelled{sailRISCVfnzMemoryOpResultzyaddzymeta}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmemoryopresult_add_meta6f4337fb08e42f593b3375a2d1083593.tex}}}} + +\newcommand{\sailRISCVvalMemoryOpResultDropMeta}{\saildoclabelled{sailRISCVzMemoryOpResultzydropzymeta}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmemoryopresult_drop_metafa9388b5fdd8fbe880aa4e686c59bab1.tex}}}} + +\newcommand{\sailRISCVfnMemoryOpResultDropMeta}{\saildoclabelled{sailRISCVfnzMemoryOpResultzydropzymeta}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmemoryopresult_drop_metafa9388b5fdd8fbe880aa4e686c59bab1.tex}}}} + +\newcommand{\sailRISCVtypeExtFetchAddrCheck}{\saildoclabelled{sailRISCVtypezExtzyFetchAddrzyCheck}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_fetchaddr_checkea47f0986744ae6c29753d54694485fe.tex}}}} + +\newcommand{\sailRISCVtypeExtControlAddrCheck}{\saildoclabelled{sailRISCVtypezExtzyControlAddrzyCheck}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_controladdr_checka9d6f41abcba03f32cc75e65e808a059.tex}}}} + +\newcommand{\sailRISCVtypeExtDataAddrCheck}{\saildoclabelled{sailRISCVtypezExtzyDataAddrzyCheck}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_dataaddr_checkae2f55c86bbc0d35297825ba44134f12.tex}}}} + +\newcommand{\sailRISCVvalhandleCheriCapException}{\saildoclabelled{sailRISCVzhandlezycherizycapzyexception}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_cheri_cap_exceptionc1ff083ca6d0a739fb48243e22ff4898.tex}}}} + +\newcommand{\sailRISCVfnhandleCheriCapException}{\saildoclabelled{sailRISCVfnzhandlezycherizycapzyexception}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_cheri_cap_exceptionc1ff083ca6d0a739fb48243e22ff4898.tex}}}} + +\newcommand{\sailRISCVvalhandleCheriRegException}{\saildoclabelled{sailRISCVzhandlezycherizyregzyexception}{\saildocval{Causes the processor to raise a capability exception by writing the given +capability exception cause and register number to the xccsr register then +signalling an exception. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_cheri_reg_exceptionfad1b48ae08f4eb90d02a5d75771c894.tex}}}} + +\newcommand{\sailRISCVfnhandleCheriRegException}{\saildoclabelled{sailRISCVfnzhandlezycherizyregzyexception}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_cheri_reg_exceptionfad1b48ae08f4eb90d02a5d75771c894.tex}}}} + +\newcommand{\sailRISCVvalhandleCheriPccException}{\saildoclabelled{sailRISCVzhandlezycherizypcczyexception}{\saildocval{Is as \hyperref[sailRISCVzhandlezycherizycapzyexception]{\lstinline{handle_cheri_cap_exception}} except that the capability register +number uses the special value 0x10 indicating the PCC register. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_cheri_pcc_exception3ca0178a61c5394ac2c49197cedda1c1.tex}}}} + +\newcommand{\sailRISCVfnhandleCheriPccException}{\saildoclabelled{sailRISCVfnzhandlezycherizypcczyexception}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_cheri_pcc_exception3ca0178a61c5394ac2c49197cedda1c1.tex}}}} + +\newcommand{\sailRISCVvalpccAccessSystemRegs}{\saildoclabelled{sailRISCVzpcczyaccesszysystemzyregs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex}}}} + +\newcommand{\sailRISCVfnpccAccessSystemRegs}{\saildoclabelled{sailRISCVfnzpcczyaccesszysystemzyregs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex}}}} + +\newcommand{\sailRISCVtypeextFetchAddrError}{\saildoclabelled{sailRISCVtypezextzyfetchzyaddrzyerror}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_fetch_addr_error77c89145df888a86f60f8c4b402dc719.tex}}}} + +\newcommand{\sailRISCVvalextFetchCheckPc}{\saildoclabelled{sailRISCVzextzyfetchzycheckzypc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_fetch_check_pc2e82f09c4f4da5465b70e5f9e6f48b77.tex}}}} + +\newcommand{\sailRISCVfnextFetchCheckPc}{\saildoclabelled{sailRISCVfnzextzyfetchzycheckzypc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_fetch_check_pc2e82f09c4f4da5465b70e5f9e6f48b77.tex}}}} + +\newcommand{\sailRISCVvalextHandleFetchCheckError}{\saildoclabelled{sailRISCVzextzyhandlezyfetchzycheckzyerror}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_handle_fetch_check_error1c773c1438a4c5dcc256df216f0a1aa9.tex}}}} + +\newcommand{\sailRISCVfnextHandleFetchCheckError}{\saildoclabelled{sailRISCVfnzextzyhandlezyfetchzycheckzyerror}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_handle_fetch_check_error1c773c1438a4c5dcc256df216f0a1aa9.tex}}}} + +\newcommand{\sailRISCVtypeextControlAddrError}{\saildoclabelled{sailRISCVtypezextzycontrolzyaddrzyerror}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_control_addr_error30fe954fdccd9382175241e7b6137d82.tex}}}} + +\newcommand{\sailRISCVvalextControlCheckAddr}{\saildoclabelled{sailRISCVzextzycontrolzycheckzyaddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_control_check_addr2d404fc3390578d569e3f547f0d18fce.tex}}}} + +\newcommand{\sailRISCVfnextControlCheckAddr}{\saildoclabelled{sailRISCVfnzextzycontrolzycheckzyaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_control_check_addr2d404fc3390578d569e3f547f0d18fce.tex}}}} + +\newcommand{\sailRISCVvalextControlCheckPc}{\saildoclabelled{sailRISCVzextzycontrolzycheckzypc}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_control_check_pc92c2579f955b827738ac1e5c79b85839.tex}}}} + +\newcommand{\sailRISCVfnextControlCheckPc}{\saildoclabelled{sailRISCVfnzextzycontrolzycheckzypc}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_control_check_pc92c2579f955b827738ac1e5c79b85839.tex}}}} + +\newcommand{\sailRISCVvalextHandleControlCheckError}{\saildoclabelled{sailRISCVzextzyhandlezycontrolzycheckzyerror}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_handle_control_check_error7b80ca54e4133f98238aa5f1371bfc1f.tex}}}} + +\newcommand{\sailRISCVfnextHandleControlCheckError}{\saildoclabelled{sailRISCVfnzextzyhandlezycontrolzycheckzyerror}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_handle_control_check_error7b80ca54e4133f98238aa5f1371bfc1f.tex}}}} + +\newcommand{\sailRISCVtypeextDataAddrError}{\saildoclabelled{sailRISCVtypezextzydatazyaddrzyerror}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_data_addr_errora4f74a5b44e1f0d7e46bc0f33c466dea.tex}}}} + +\newcommand{\sailRISCVvalgetCheriModeCapAddr}{\saildoclabelled{sailRISCVzgetzycherizymodezycapzyaddr}{\saildocval{For given base register and offset returns, depending on current capability +mode flag, a bounding capability, effective address, and capreg\_idx (for use +in cap cause). + +}{\lstinputlisting[language=sail]{sail_latex_riscv/valzget_cheri_mode_cap_addr267a231c94a9ae3cf08d67cb43590a2e.tex}}}} + +\newcommand{\sailRISCVfngetCheriModeCapAddr}{\saildoclabelled{sailRISCVfnzgetzycherizymodezycapzyaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzget_cheri_mode_cap_addr267a231c94a9ae3cf08d67cb43590a2e.tex}}}} + +\newcommand{\sailRISCVvalextDataGetAddr}{\saildoclabelled{sailRISCVzextzydatazygetzyaddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_data_get_addra719d6978c6003ef3b6e2e57ccbf64b8.tex}}}} + +\newcommand{\sailRISCVfnextDataGetAddr}{\saildoclabelled{sailRISCVfnzextzydatazygetzyaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_data_get_addra719d6978c6003ef3b6e2e57ccbf64b8.tex}}}} + +\newcommand{\sailRISCVvalextHandleDataCheckError}{\saildoclabelled{sailRISCVzextzyhandlezydatazycheckzyerror}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_handle_data_check_errorad2507fc7050fbd24451608767d75b73.tex}}}} + +\newcommand{\sailRISCVfnextHandleDataCheckError}{\saildoclabelled{sailRISCVfnzextzyhandlezydatazycheckzyerror}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_handle_data_check_errorad2507fc7050fbd24451608767d75b73.tex}}}} + +\newcommand{\sailRISCVvalextCheckXretPriv}{\saildoclabelled{sailRISCVzextzycheckzyxretzypriv}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_check_xret_priv92677d070503a361c4ac308adba53957.tex}}}} + +\newcommand{\sailRISCVfnextCheckXretPriv}{\saildoclabelled{sailRISCVfnzextzycheckzyxretzypriv}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_check_xret_priv92677d070503a361c4ac308adba53957.tex}}}} + +\newcommand{\sailRISCVvalextFailXretPriv}{\saildoclabelled{sailRISCVzextzyfailzyxretzypriv}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_fail_xret_priva071b88d32f48ad8e720a4cae916da8b.tex}}}} + +\newcommand{\sailRISCVfnextFailXretPriv}{\saildoclabelled{sailRISCVfnzextzyfailzyxretzypriv}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_fail_xret_priva071b88d32f48ad8e720a4cae916da8b.tex}}}} + +\newcommand{\sailRISCVvalextCheckCSR}{\saildoclabelled{sailRISCVzextzycheckzyCSR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_check_csreef82c82c124fe04d74fc6fd8219bb68.tex}}}} + +\newcommand{\sailRISCVfnextCheckCSR}{\saildoclabelled{sailRISCVfnzextzycheckzyCSR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_check_csreef82c82c124fe04d74fc6fd8219bb68.tex}}}} + +\newcommand{\sailRISCVvalextCheckCSRFail}{\saildoclabelled{sailRISCVzextzycheckzyCSRzyfail}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_check_csr_fail991cc4645a62a48eb645391d3988288a.tex}}}} + +\newcommand{\sailRISCVfnextCheckCSRFail}{\saildoclabelled{sailRISCVfnzextzycheckzyCSRzyfail}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_check_csr_fail991cc4645a62a48eb645391d3988288a.tex}}}} + +\newcommand{\sailRISCVfnextVetoDisableC}{\saildoclabelled{sailRISCVfnzextzyvetozydisablezyC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_veto_disable_cd10c2d1c5077060fa007c1628d7aaa8c.tex}}}} + +\newcommand{\sailRISCVvalelfTohost}{\saildoclabelled{sailRISCVzelfzytohost}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzelf_tohost30cafcd41bc201ebfe5bbd0510aa0b7c.tex}}}} + +\newcommand{\sailRISCVvalelfEntry}{\saildoclabelled{sailRISCVzelfzyentry}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzelf_entry2a366da786fa7f56d47732b2fddb2821.tex}}}} + +\newcommand{\sailRISCVvalplatRamBase}{\saildoclabelled{sailRISCVzplatzyramzybase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_ram_base0d7614688445a7408614bad359843641.tex}}}} + +\newcommand{\sailRISCVvalplatRamSizze}{\saildoclabelled{sailRISCVzplatzyramzysizze}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_ram_sizze3e389712a74fd397e22555e7f548f008.tex}}}} + +\newcommand{\sailRISCVvalplatEnablePmp}{\saildoclabelled{sailRISCVzplatzyenablezypmp}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_enable_pmpe3a19dd2b08d4a89664077b8a1cf0844.tex}}}} + +\newcommand{\sailRISCVvalplatEnableDirtyUpdate}{\saildoclabelled{sailRISCVzplatzyenablezydirtyzyupdate}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_enable_dirty_update0b255805eb9610b556493bfe506416f2.tex}}}} + +\newcommand{\sailRISCVvalplatEnableMisalignedAccess}{\saildoclabelled{sailRISCVzplatzyenablezymisalignedzyaccess}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_enable_misaligned_accesscb4191568185cb3901b1944164f65f6e.tex}}}} + +\newcommand{\sailRISCVvalplatMtvalHasIllegalInstBits}{\saildoclabelled{sailRISCVzplatzymtvalzyhaszyillegalzyinstzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_mtval_has_illegal_inst_bits49cda37cfdfffb5c464c6333bb83f0b0.tex}}}} + +\newcommand{\sailRISCVvalplatRomBase}{\saildoclabelled{sailRISCVzplatzyromzybase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_rom_basebdbb354c7f3bb238fa08300023cbf0b5.tex}}}} + +\newcommand{\sailRISCVvalplatRomSizze}{\saildoclabelled{sailRISCVzplatzyromzysizze}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_rom_sizze563dbbc4d715886f76fbde684ac8a500.tex}}}} + +\newcommand{\sailRISCVvalplatClintBase}{\saildoclabelled{sailRISCVzplatzyclintzybase}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_clint_base0196a3035036838f7fe4f78d61a1f9d8.tex}}}} + +\newcommand{\sailRISCVvalplatClintSizze}{\saildoclabelled{sailRISCVzplatzyclintzysizze}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_clint_sizze8fb2ec94310f08d19d4c7c0476f57919.tex}}}} + +\newcommand{\sailRISCVvalplatHtifTohost}{\saildoclabelled{sailRISCVzplatzyhtifzytohost}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_htif_tohostf9ba2e7ae67de81976fbefc0304b89d1.tex}}}} + +\newcommand{\sailRISCVfnplatHtifTohost}{\saildoclabelled{sailRISCVfnzplatzyhtifzytohost}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzplat_htif_tohostf9ba2e7ae67de81976fbefc0304b89d1.tex}}}} + +\newcommand{\sailRISCVvalphysMemSegments}{\saildoclabelled{sailRISCVzphyszymemzysegments}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzphys_mem_segments83ff72aa5aa998a329fa30de106aa0a7.tex}}}} + +\newcommand{\sailRISCVfnphysMemSegments}{\saildoclabelled{sailRISCVfnzphyszymemzysegments}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzphys_mem_segments83ff72aa5aa998a329fa30de106aa0a7.tex}}}} + +\newcommand{\sailRISCVvalwithinPhysMem}{\saildoclabelled{sailRISCVzwithinzyphyszymem}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwithin_phys_mem5b6233a64f93394cb594812a945dcbb2.tex}}}} + +\newcommand{\sailRISCVfnwithinPhysMem}{\saildoclabelled{sailRISCVfnzwithinzyphyszymem}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwithin_phys_mem5b6233a64f93394cb594812a945dcbb2.tex}}}} + +\newcommand{\sailRISCVvalwithinClint}{\saildoclabelled{sailRISCVzwithinzyclint}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwithin_clintc139e042afc9910b6edf55c2c70f2e80.tex}}}} + +\newcommand{\sailRISCVfnwithinClint}{\saildoclabelled{sailRISCVfnzwithinzyclint}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwithin_clintc139e042afc9910b6edf55c2c70f2e80.tex}}}} + +\newcommand{\sailRISCVvalwithinHtifWritable}{\saildoclabelled{sailRISCVzwithinzyhtifzywritable}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwithin_htif_writablec356d0ea372a60437fdf28745e5e9ae3.tex}}}} + +\newcommand{\sailRISCVfnwithinHtifWritable}{\saildoclabelled{sailRISCVfnzwithinzyhtifzywritable}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwithin_htif_writablec356d0ea372a60437fdf28745e5e9ae3.tex}}}} + +\newcommand{\sailRISCVvalwithinHtifReadable}{\saildoclabelled{sailRISCVzwithinzyhtifzyreadable}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwithin_htif_readable2f6131e40985c12d9270943521113c33.tex}}}} + +\newcommand{\sailRISCVfnwithinHtifReadable}{\saildoclabelled{sailRISCVfnzwithinzyhtifzyreadable}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwithin_htif_readable2f6131e40985c12d9270943521113c33.tex}}}} + +\newcommand{\sailRISCVvalplatInsnsPerTick}{\saildoclabelled{sailRISCVzplatzyinsnszyperzytick}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_insns_per_tick0a43cf4e39e3447031fdc4fb6c22d20e.tex}}}} + +\newcommand{\sailRISCVvalclintLoad}{\saildoclabelled{sailRISCVzclintzyload}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzclint_load21de915eadac54aac5354dd7bcbb8d32.tex}}}} + +\newcommand{\sailRISCVfnclintLoad}{\saildoclabelled{sailRISCVfnzclintzyload}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzclint_load21de915eadac54aac5354dd7bcbb8d32.tex}}}} + +\newcommand{\sailRISCVvalclintDispatch}{\saildoclabelled{sailRISCVzclintzydispatch}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzclint_dispatch8f07ea27f21c1842cfbd7abdf66f1da6.tex}}}} + +\newcommand{\sailRISCVfnclintDispatch}{\saildoclabelled{sailRISCVfnzclintzydispatch}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzclint_dispatch8f07ea27f21c1842cfbd7abdf66f1da6.tex}}}} + +\newcommand{\sailRISCVvalclintStore}{\saildoclabelled{sailRISCVzclintzystore}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzclint_store5ac6a4caa2fe222e7b924cd9a27ec52f.tex}}}} + +\newcommand{\sailRISCVfnclintStore}{\saildoclabelled{sailRISCVfnzclintzystore}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzclint_store5ac6a4caa2fe222e7b924cd9a27ec52f.tex}}}} + +\newcommand{\sailRISCVvaltickClock}{\saildoclabelled{sailRISCVztickzyclock}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztick_clocka855f1c53aa2515a7a67cd69b5b3d663.tex}}}} + +\newcommand{\sailRISCVfntickClock}{\saildoclabelled{sailRISCVfnztickzyclock}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztick_clocka855f1c53aa2515a7a67cd69b5b3d663.tex}}}} + +\newcommand{\sailRISCVvalplatTermWrite}{\saildoclabelled{sailRISCVzplatzytermzywrite}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_term_write036fbb8469eac6f64f37bf65565a5f02.tex}}}} + +\newcommand{\sailRISCVvalplatTermRead}{\saildoclabelled{sailRISCVzplatzytermzyread}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplat_term_readbc174c8d489d235edca54e912406e103.tex}}}} + +\newcommand{\sailRISCVtypehtifCmd}{\saildoclabelled{sailRISCVtypezhtifzycmd}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezhtif_cmd11bed6786969720c8c78224801520c9a.tex}}}} + +\newcommand{\sailRISCVvalMkHtifCmd}{\saildoclabelled{sailRISCVzMkzyhtifzycmd}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_htif_cmde6729ad1ed1b5a3925de51048804de68.tex}}}} + +\newcommand{\sailRISCVfnMkHtifCmd}{\saildoclabelled{sailRISCVfnzMkzyhtifzycmd}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_htif_cmde6729ad1ed1b5a3925de51048804de68.tex}}}} + +\newcommand{\sailRISCVvalGetHtifCmdBits}{\saildoclabelled{sailRISCVzzygetzyhtifzycmdzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_htif_cmd_bits1eb71429743386e681784c96e268deaf.tex}}}} + +\newcommand{\sailRISCVfnGetHtifCmdBits}{\saildoclabelled{sailRISCVfnzzygetzyhtifzycmdzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_htif_cmd_bits1eb71429743386e681784c96e268deaf.tex}}}} + +\newcommand{\sailRISCVvalSetHtifCmdBits}{\saildoclabelled{sailRISCVzzysetzyhtifzycmdzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_htif_cmd_bits689a1226135e157ab73f85b4e32f7b0e.tex}}}} + +\newcommand{\sailRISCVfnSetHtifCmdBits}{\saildoclabelled{sailRISCVfnzzysetzyhtifzycmdzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_htif_cmd_bits689a1226135e157ab73f85b4e32f7b0e.tex}}}} + +\newcommand{\sailRISCVvalUpdateHtifCmdBits}{\saildoclabelled{sailRISCVzzyupdatezyhtifzycmdzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_htif_cmd_bitsf4016ddf8b504ce2ad50554db668de5e.tex}}}} + +\newcommand{\sailRISCVfnUpdateHtifCmdBits}{\saildoclabelled{sailRISCVfnzzyupdatezyhtifzycmdzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_htif_cmd_bitsf4016ddf8b504ce2ad50554db668de5e.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJJJJJJJJJJJupdateBits}{\saildoclabelled{sailRISCVoverloadJJJJJJJJJJJJJJzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJJJJJJJJJJJzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKKKKKKKKKKKModBits}{\saildoclabelled{sailRISCVoverloadKKKKKKKKKKKKKKzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKKKKKKKKKKKz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetHtifCmdDevice}{\saildoclabelled{sailRISCVzzygetzyhtifzycmdzydevice}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_htif_cmd_device49a4f976524fe1bb4129d075a7e50cb3.tex}}}} + +\newcommand{\sailRISCVfnGetHtifCmdDevice}{\saildoclabelled{sailRISCVfnzzygetzyhtifzycmdzydevice}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_htif_cmd_device49a4f976524fe1bb4129d075a7e50cb3.tex}}}} + +\newcommand{\sailRISCVvalSetHtifCmdDevice}{\saildoclabelled{sailRISCVzzysetzyhtifzycmdzydevice}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_htif_cmd_deviceca3d219cd020878f1e936d65dadd246c.tex}}}} + +\newcommand{\sailRISCVfnSetHtifCmdDevice}{\saildoclabelled{sailRISCVfnzzysetzyhtifzycmdzydevice}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_htif_cmd_deviceca3d219cd020878f1e936d65dadd246c.tex}}}} + +\newcommand{\sailRISCVvalUpdateHtifCmdDevice}{\saildoclabelled{sailRISCVzzyupdatezyhtifzycmdzydevice}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_htif_cmd_device37d8d93e2615eb16246d9d3624507e12.tex}}}} + +\newcommand{\sailRISCVfnUpdateHtifCmdDevice}{\saildoclabelled{sailRISCVfnzzyupdatezyhtifzycmdzydevice}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_htif_cmd_device37d8d93e2615eb16246d9d3624507e12.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLLLLLLLLLLLupdateDevice}{\saildoclabelled{sailRISCVoverloadLLLLLLLLLLLLLLzupdatezydevice}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLLLLLLLLLLLzupdate_device133872281fc83dcb5df6232f6344d8c0.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMMMMMMMMMMMModDevice}{\saildoclabelled{sailRISCVoverloadMMMMMMMMMMMMMMzzymodzydevice}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMMMMMMMMMMMz_mod_deviced59eb8a2803361d08f70d5dfe4de57a2.tex}}}} + +\newcommand{\sailRISCVvalGetHtifCmdCmd}{\saildoclabelled{sailRISCVzzygetzyhtifzycmdzycmd}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_htif_cmd_cmd819958801f753cde6a79cea6d1060596.tex}}}} + +\newcommand{\sailRISCVfnGetHtifCmdCmd}{\saildoclabelled{sailRISCVfnzzygetzyhtifzycmdzycmd}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_htif_cmd_cmd819958801f753cde6a79cea6d1060596.tex}}}} + +\newcommand{\sailRISCVvalSetHtifCmdCmd}{\saildoclabelled{sailRISCVzzysetzyhtifzycmdzycmd}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_htif_cmd_cmd0433aa4c5b2a4721f8f44a87e408d238.tex}}}} + +\newcommand{\sailRISCVfnSetHtifCmdCmd}{\saildoclabelled{sailRISCVfnzzysetzyhtifzycmdzycmd}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_htif_cmd_cmd0433aa4c5b2a4721f8f44a87e408d238.tex}}}} + +\newcommand{\sailRISCVvalUpdateHtifCmdCmd}{\saildoclabelled{sailRISCVzzyupdatezyhtifzycmdzycmd}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_htif_cmd_cmd6ec3dd793a5d6eea4a6de9c247ff1ed7.tex}}}} + +\newcommand{\sailRISCVfnUpdateHtifCmdCmd}{\saildoclabelled{sailRISCVfnzzyupdatezyhtifzycmdzycmd}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_htif_cmd_cmd6ec3dd793a5d6eea4a6de9c247ff1ed7.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNNNNNNNNNNNupdateCmd}{\saildoclabelled{sailRISCVoverloadNNNNNNNNNNNNNNzupdatezycmd}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNNNNNNNNNNNzupdate_cmdfa3836cfddf11c618c06ae9d2b47cd43.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOOOOOOOOOOOModCmd}{\saildoclabelled{sailRISCVoverloadOOOOOOOOOOOOOOzzymodzycmd}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOOOOOOOOOOOz_mod_cmda78881afb278208f2e0a03703f92acc3.tex}}}} + +\newcommand{\sailRISCVvalGetHtifCmdPayload}{\saildoclabelled{sailRISCVzzygetzyhtifzycmdzypayload}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_htif_cmd_payload61085de7e39b8efa3ae178ccc88eb7d5.tex}}}} + +\newcommand{\sailRISCVfnGetHtifCmdPayload}{\saildoclabelled{sailRISCVfnzzygetzyhtifzycmdzypayload}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_htif_cmd_payload61085de7e39b8efa3ae178ccc88eb7d5.tex}}}} + +\newcommand{\sailRISCVvalSetHtifCmdPayload}{\saildoclabelled{sailRISCVzzysetzyhtifzycmdzypayload}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_htif_cmd_payload54f16ea011075a1e7c5afa0c27e684a6.tex}}}} + +\newcommand{\sailRISCVfnSetHtifCmdPayload}{\saildoclabelled{sailRISCVfnzzysetzyhtifzycmdzypayload}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_htif_cmd_payload54f16ea011075a1e7c5afa0c27e684a6.tex}}}} + +\newcommand{\sailRISCVvalUpdateHtifCmdPayload}{\saildoclabelled{sailRISCVzzyupdatezyhtifzycmdzypayload}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_htif_cmd_payloadf8c76e11f35c2157b590a60e4678b1cc.tex}}}} + +\newcommand{\sailRISCVfnUpdateHtifCmdPayload}{\saildoclabelled{sailRISCVfnzzyupdatezyhtifzycmdzypayload}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_htif_cmd_payloadf8c76e11f35c2157b590a60e4678b1cc.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPPPPPPPPPPPupdatePayload}{\saildoclabelled{sailRISCVoverloadPPPPPPPPPPPPPPzupdatezypayload}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPPPPPPPPPPPzupdate_payload1cd3e49aac00ade7b567c8c5fce6bd11.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQQQQQQQQQQQModPayload}{\saildoclabelled{sailRISCVoverloadQQQQQQQQQQQQQQzzymodzypayload}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQQQQQQQQQQQz_mod_payload7f7d1a64858e00d9a581ddd7341ee771.tex}}}} + +\newcommand{\sailRISCVvalhtifLoad}{\saildoclabelled{sailRISCVzhtifzyload}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhtif_load7bc11b4853a5dae019f61722a0a6d6d7.tex}}}} + +\newcommand{\sailRISCVfnhtifLoad}{\saildoclabelled{sailRISCVfnzhtifzyload}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhtif_load7bc11b4853a5dae019f61722a0a6d6d7.tex}}}} + +\newcommand{\sailRISCVvalhtifStore}{\saildoclabelled{sailRISCVzhtifzystore}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhtif_storeab9d062182e5f884583204ccd435221d.tex}}}} + +\newcommand{\sailRISCVfnhtifStore}{\saildoclabelled{sailRISCVfnzhtifzystore}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhtif_storeab9d062182e5f884583204ccd435221d.tex}}}} + +\newcommand{\sailRISCVvalhtifTick}{\saildoclabelled{sailRISCVzhtifzytick}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhtif_tick227711b74637bcd9c79730b4942f90fb.tex}}}} + +\newcommand{\sailRISCVfnhtifTick}{\saildoclabelled{sailRISCVfnzhtifzytick}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhtif_tick227711b74637bcd9c79730b4942f90fb.tex}}}} + +\newcommand{\sailRISCVvalwithinMmioReadable}{\saildoclabelled{sailRISCVzwithinzymmiozyreadable}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwithin_mmio_readable2afaf2bf016b6ead5a5708ec8508d184.tex}}}} + +\newcommand{\sailRISCVfnwithinMmioReadable}{\saildoclabelled{sailRISCVfnzwithinzymmiozyreadable}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwithin_mmio_readable2afaf2bf016b6ead5a5708ec8508d184.tex}}}} + +\newcommand{\sailRISCVvalwithinMmioWritable}{\saildoclabelled{sailRISCVzwithinzymmiozywritable}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwithin_mmio_writable310089204ce2d4e6a33811b1982373ad.tex}}}} + +\newcommand{\sailRISCVfnwithinMmioWritable}{\saildoclabelled{sailRISCVfnzwithinzymmiozywritable}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwithin_mmio_writable310089204ce2d4e6a33811b1982373ad.tex}}}} + +\newcommand{\sailRISCVvalmmioRead}{\saildoclabelled{sailRISCVzmmiozyread}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmmio_read910c976398a0cf73e8b4d12641a665c1.tex}}}} + +\newcommand{\sailRISCVfnmmioRead}{\saildoclabelled{sailRISCVfnzmmiozyread}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmmio_read910c976398a0cf73e8b4d12641a665c1.tex}}}} + +\newcommand{\sailRISCVvalmmioWrite}{\saildoclabelled{sailRISCVzmmiozywrite}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmmio_writec1bd5fc64a027d200e43ae1730320ed7.tex}}}} + +\newcommand{\sailRISCVfnmmioWrite}{\saildoclabelled{sailRISCVfnzmmiozywrite}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmmio_writec1bd5fc64a027d200e43ae1730320ed7.tex}}}} + +\newcommand{\sailRISCVvalinitPlatform}{\saildoclabelled{sailRISCVzinitzyplatform}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinit_platform487cad4292d23a20d6a3d0b81157a250.tex}}}} + +\newcommand{\sailRISCVfninitPlatform}{\saildoclabelled{sailRISCVfnzinitzyplatform}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinit_platform487cad4292d23a20d6a3d0b81157a250.tex}}}} + +\newcommand{\sailRISCVvaltickPlatform}{\saildoclabelled{sailRISCVztickzyplatform}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztick_platformc49251d76e66d78fce3dd1f18a27869c.tex}}}} + +\newcommand{\sailRISCVfntickPlatform}{\saildoclabelled{sailRISCVfnztickzyplatform}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztick_platformc49251d76e66d78fce3dd1f18a27869c.tex}}}} + +\newcommand{\sailRISCVvalhandleIllegal}{\saildoclabelled{sailRISCVzhandlezyillegal}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_illegal5907526c9d8e4989ca440b67ea4948c3.tex}}}} + +\newcommand{\sailRISCVfnhandleIllegal}{\saildoclabelled{sailRISCVfnzhandlezyillegal}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_illegal5907526c9d8e4989ca440b67ea4948c3.tex}}}} + +\newcommand{\sailRISCVvalplatformWfi}{\saildoclabelled{sailRISCVzplatformzywfi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzplatform_wfi377b23f6619d58844892f179f2934ac6.tex}}}} + +\newcommand{\sailRISCVfnplatformWfi}{\saildoclabelled{sailRISCVfnzplatformzywfi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzplatform_wfi377b23f6619d58844892f179f2934ac6.tex}}}} + +\newcommand{\sailRISCVvalisAlignedAddr}{\saildoclabelled{sailRISCVziszyalignedzyaddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzis_aligned_addr6fae0ea13237382ac6720d04123fd943.tex}}}} + +\newcommand{\sailRISCVfnisAlignedAddr}{\saildoclabelled{sailRISCVfnziszyalignedzyaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzis_aligned_addr6fae0ea13237382ac6720d04123fd943.tex}}}} + +\newcommand{\sailRISCVvalreadKindOfFlags}{\saildoclabelled{sailRISCVzreadzykindzyofzyflags}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzread_kind_of_flagsbdfde0c548450764d5ed916ca1cb98ac.tex}}}} + +\newcommand{\sailRISCVfnreadKindOfFlags}{\saildoclabelled{sailRISCVfnzreadzykindzyofzyflags}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzread_kind_of_flagsbdfde0c548450764d5ed916ca1cb98ac.tex}}}} + +\newcommand{\sailRISCVvalphysMemRead}{\saildoclabelled{sailRISCVzphyszymemzyread}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzphys_mem_readdcad862ae3a42c22bfc78bad8e3328db.tex}}}} + +\newcommand{\sailRISCVfnphysMemRead}{\saildoclabelled{sailRISCVfnzphyszymemzyread}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzphys_mem_readdcad862ae3a42c22bfc78bad8e3328db.tex}}}} + +\newcommand{\sailRISCVvalcheckedMemRead}{\saildoclabelled{sailRISCVzcheckedzymemzyread}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzchecked_mem_read46a92fcd62c31279edfc3bc18c424fa0.tex}}}} + +\newcommand{\sailRISCVfncheckedMemRead}{\saildoclabelled{sailRISCVfnzcheckedzymemzyread}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzchecked_mem_read46a92fcd62c31279edfc3bc18c424fa0.tex}}}} + +\newcommand{\sailRISCVvalpmpMemRead}{\saildoclabelled{sailRISCVzpmpzymemzyread}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmp_mem_readc45533831bda1c394396c536ba168b7a.tex}}}} + +\newcommand{\sailRISCVfnpmpMemRead}{\saildoclabelled{sailRISCVfnzpmpzymemzyread}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmp_mem_readc45533831bda1c394396c536ba168b7a.tex}}}} + +\newcommand{\sailRISCVvalrvfiRead}{\saildoclabelled{sailRISCVzrvfizyread}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrvfi_readaee7411fcd70e67f9e6d2f7f9f563435.tex}}}} + +\newcommand{\sailRISCVfnrvfiRead}{\saildoclabelled{sailRISCVfnzrvfizyread}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrvfi_readaee7411fcd70e67f9e6d2f7f9f563435.tex}}}} + +\newcommand{\sailRISCVvalmemRead}{\saildoclabelled{sailRISCVzmemzyread}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmem_readbc59b9b8e622af015b97ceb8dcd5c69e.tex}}}} + +\newcommand{\sailRISCVvalmemReadMeta}{\saildoclabelled{sailRISCVzmemzyreadzymeta}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmem_read_metaa66233a97620233d3f80f4bf1a13c232.tex}}}} + +\newcommand{\sailRISCVfnmemReadMeta}{\saildoclabelled{sailRISCVfnzmemzyreadzymeta}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmem_read_metaa66233a97620233d3f80f4bf1a13c232.tex}}}} + +\newcommand{\sailRISCVfnmemRead}{\saildoclabelled{sailRISCVfnzmemzyread}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmem_readbc59b9b8e622af015b97ceb8dcd5c69e.tex}}}} + +\newcommand{\sailRISCVvalmemWriteEa}{\saildoclabelled{sailRISCVzmemzywritezyea}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmem_write_eaf1486ee81ccf925e874de8977b0270e9.tex}}}} + +\newcommand{\sailRISCVfnmemWriteEa}{\saildoclabelled{sailRISCVfnzmemzywritezyea}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmem_write_eaf1486ee81ccf925e874de8977b0270e9.tex}}}} + +\newcommand{\sailRISCVvalrvfiWrite}{\saildoclabelled{sailRISCVzrvfizywrite}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex}}}} + +\newcommand{\sailRISCVfnrvfiWrite}{\saildoclabelled{sailRISCVfnzrvfizywrite}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex}}}} + +\newcommand{\sailRISCVvalphysMemWrite}{\saildoclabelled{sailRISCVzphyszymemzywrite}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzphys_mem_writefae7815adda192bed56129eba4b7bb01.tex}}}} + +\newcommand{\sailRISCVfnphysMemWrite}{\saildoclabelled{sailRISCVfnzphyszymemzywrite}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzphys_mem_writefae7815adda192bed56129eba4b7bb01.tex}}}} + +\newcommand{\sailRISCVvalcheckedMemWrite}{\saildoclabelled{sailRISCVzcheckedzymemzywrite}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzchecked_mem_write765e0693788c9f4b01c2243ece39909e.tex}}}} + +\newcommand{\sailRISCVfncheckedMemWrite}{\saildoclabelled{sailRISCVfnzcheckedzymemzywrite}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzchecked_mem_write765e0693788c9f4b01c2243ece39909e.tex}}}} + +\newcommand{\sailRISCVvalpmpMemWrite}{\saildoclabelled{sailRISCVzpmpzymemzywrite}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzpmp_mem_write4ae53a6de2384826cc3e765eccd350e8.tex}}}} + +\newcommand{\sailRISCVfnpmpMemWrite}{\saildoclabelled{sailRISCVfnzpmpzymemzywrite}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzpmp_mem_write4ae53a6de2384826cc3e765eccd350e8.tex}}}} + +\newcommand{\sailRISCVvalmemWriteValueMeta}{\saildoclabelled{sailRISCVzmemzywritezyvaluezymeta}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmem_write_value_meta586f37dd78d9b5be2a948e83778e6186.tex}}}} + +\newcommand{\sailRISCVfnmemWriteValueMeta}{\saildoclabelled{sailRISCVfnzmemzywritezyvaluezymeta}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmem_write_value_meta586f37dd78d9b5be2a948e83778e6186.tex}}}} + +\newcommand{\sailRISCVvalmemWriteValue}{\saildoclabelled{sailRISCVzmemzywritezyvalue}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmem_write_valuec32f59efd2dcb7ea78ea4c9778bdf2e1.tex}}}} + +\newcommand{\sailRISCVfnmemWriteValue}{\saildoclabelled{sailRISCVfnzmemzywritezyvalue}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmem_write_valuec32f59efd2dcb7ea78ea4c9778bdf2e1.tex}}}} + +\newcommand{\sailRISCVvalmemReadCap}{\saildoclabelled{sailRISCVzmemzyreadzycap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmem_read_cap518c2935d72d61e3ceee2abb80c9fce5.tex}}}} + +\newcommand{\sailRISCVfnmemReadCap}{\saildoclabelled{sailRISCVfnzmemzyreadzycap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmem_read_cap518c2935d72d61e3ceee2abb80c9fce5.tex}}}} + +\newcommand{\sailRISCVvalmemWriteEaCap}{\saildoclabelled{sailRISCVzmemzywritezyeazycap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmem_write_ea_capaa2cfa0cf86165d13bd79024ad44b71d.tex}}}} + +\newcommand{\sailRISCVfnmemWriteEaCap}{\saildoclabelled{sailRISCVfnzmemzywritezyeazycap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmem_write_ea_capaa2cfa0cf86165d13bd79024ad44b71d.tex}}}} + +\newcommand{\sailRISCVvalmemWriteCap}{\saildoclabelled{sailRISCVzmemzywritezycap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmem_write_cap1a1d6143df72b48afdcbdae2e99e77f4.tex}}}} + +\newcommand{\sailRISCVfnmemWriteCap}{\saildoclabelled{sailRISCVfnzmemzywritezycap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmem_write_cap1a1d6143df72b48afdcbdae2e99e77f4.tex}}}} + +\newcommand{\sailRISCVtypepteAttribs}{\saildoclabelled{sailRISCVtypezpteAttribs}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpteattribs7d3296aef3ee8195982b63fe09ada4c1.tex}}}} + +\newcommand{\sailRISCVtypePTEBits}{\saildoclabelled{sailRISCVtypezPTEzyBits}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpte_bits8fb42d02184f92f56f1b4720e0954290.tex}}}} + +\newcommand{\sailRISCVvalMkPTEBits}{\saildoclabelled{sailRISCVzMkzyPTEzyBits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_pte_bits2f40a3dc189d8feaf027fdaa7cd0c939.tex}}}} + +\newcommand{\sailRISCVfnMkPTEBits}{\saildoclabelled{sailRISCVfnzMkzyPTEzyBits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_pte_bits2f40a3dc189d8feaf027fdaa7cd0c939.tex}}}} + +\newcommand{\sailRISCVvalGetPTEBitsBits}{\saildoclabelled{sailRISCVzzygetzyPTEzyBitszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pte_bits_bits6cd7748e02dfe09da9dd53f24f9ac073.tex}}}} + +\newcommand{\sailRISCVfnGetPTEBitsBits}{\saildoclabelled{sailRISCVfnzzygetzyPTEzyBitszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pte_bits_bits6cd7748e02dfe09da9dd53f24f9ac073.tex}}}} + +\newcommand{\sailRISCVvalSetPTEBitsBits}{\saildoclabelled{sailRISCVzzysetzyPTEzyBitszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pte_bits_bits6d0635987f7718a8a39cf3033064c503.tex}}}} + +\newcommand{\sailRISCVfnSetPTEBitsBits}{\saildoclabelled{sailRISCVfnzzysetzyPTEzyBitszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pte_bits_bits6d0635987f7718a8a39cf3033064c503.tex}}}} + +\newcommand{\sailRISCVvalUpdatePTEBitsBits}{\saildoclabelled{sailRISCVzzyupdatezyPTEzyBitszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pte_bits_bits103014768edd92dc714fb7a033a0405f.tex}}}} + +\newcommand{\sailRISCVfnUpdatePTEBitsBits}{\saildoclabelled{sailRISCVfnzzyupdatezyPTEzyBitszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pte_bits_bits103014768edd92dc714fb7a033a0405f.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRRRRRRRRRRRupdateBits}{\saildoclabelled{sailRISCVoverloadRRRRRRRRRRRRRRzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRRRRRRRRRRRzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSSSSSSSSSSSModBits}{\saildoclabelled{sailRISCVoverloadSSSSSSSSSSSSSSzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSSSSSSSSSSSz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetPTEBitsD}{\saildoclabelled{sailRISCVzzygetzyPTEzyBitszyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pte_bits_d1ee6a89af287b35ae0a1cf2945b86d59.tex}}}} + +\newcommand{\sailRISCVfnGetPTEBitsD}{\saildoclabelled{sailRISCVfnzzygetzyPTEzyBitszyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pte_bits_d1ee6a89af287b35ae0a1cf2945b86d59.tex}}}} + +\newcommand{\sailRISCVvalSetPTEBitsD}{\saildoclabelled{sailRISCVzzysetzyPTEzyBitszyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pte_bits_d91bbe4815197f856eaded6975a2b164b.tex}}}} + +\newcommand{\sailRISCVfnSetPTEBitsD}{\saildoclabelled{sailRISCVfnzzysetzyPTEzyBitszyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pte_bits_d91bbe4815197f856eaded6975a2b164b.tex}}}} + +\newcommand{\sailRISCVvalUpdatePTEBitsD}{\saildoclabelled{sailRISCVzzyupdatezyPTEzyBitszyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pte_bits_d0702d6e9e8c79296c17be6a87f7d2bcb.tex}}}} + +\newcommand{\sailRISCVfnUpdatePTEBitsD}{\saildoclabelled{sailRISCVfnzzyupdatezyPTEzyBitszyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pte_bits_d0702d6e9e8c79296c17be6a87f7d2bcb.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTTTTTTTTTTTupdateD}{\saildoclabelled{sailRISCVoverloadTTTTTTTTTTTTTTzupdatezyD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTTTTTTTTTTTzupdate_da9201c8a6710e680d16238f3581a0227.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUUUUUUUUUUUModD}{\saildoclabelled{sailRISCVoverloadUUUUUUUUUUUUUUzzymodzyD}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUUUUUUUUUUUz_mod_d8c29507d9735e49d608a373bd2e2c599.tex}}}} + +\newcommand{\sailRISCVvalGetPTEBitsA}{\saildoclabelled{sailRISCVzzygetzyPTEzyBitszyA}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pte_bits_adca5243c2ba1646df88e501938973569.tex}}}} + +\newcommand{\sailRISCVfnGetPTEBitsA}{\saildoclabelled{sailRISCVfnzzygetzyPTEzyBitszyA}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pte_bits_adca5243c2ba1646df88e501938973569.tex}}}} + +\newcommand{\sailRISCVvalSetPTEBitsA}{\saildoclabelled{sailRISCVzzysetzyPTEzyBitszyA}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pte_bits_aac67ea7f6b10ab3673728f748f93c292.tex}}}} + +\newcommand{\sailRISCVfnSetPTEBitsA}{\saildoclabelled{sailRISCVfnzzysetzyPTEzyBitszyA}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pte_bits_aac67ea7f6b10ab3673728f748f93c292.tex}}}} + +\newcommand{\sailRISCVvalUpdatePTEBitsA}{\saildoclabelled{sailRISCVzzyupdatezyPTEzyBitszyA}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pte_bits_a3004f24784d29ad77e6bb0801c41e98e.tex}}}} + +\newcommand{\sailRISCVfnUpdatePTEBitsA}{\saildoclabelled{sailRISCVfnzzyupdatezyPTEzyBitszyA}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pte_bits_a3004f24784d29ad77e6bb0801c41e98e.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVVVVVVVVVVVupdateA}{\saildoclabelled{sailRISCVoverloadVVVVVVVVVVVVVVzupdatezyA}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVVVVVVVVVVVzupdate_ab740c1f378b55b3328b2a9f25ff6c1cf.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWWWWWWWWWWWModA}{\saildoclabelled{sailRISCVoverloadWWWWWWWWWWWWWWzzymodzyA}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWWWWWWWWWWWz_mod_a62a6f88676512d98a363811f9f5ba327.tex}}}} + +\newcommand{\sailRISCVvalGetPTEBitsG}{\saildoclabelled{sailRISCVzzygetzyPTEzyBitszyG}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pte_bits_g072ec08934990455850facd53f018b89.tex}}}} + +\newcommand{\sailRISCVfnGetPTEBitsG}{\saildoclabelled{sailRISCVfnzzygetzyPTEzyBitszyG}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pte_bits_g072ec08934990455850facd53f018b89.tex}}}} + +\newcommand{\sailRISCVvalSetPTEBitsG}{\saildoclabelled{sailRISCVzzysetzyPTEzyBitszyG}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pte_bits_g31ff87423c27525881946540eb3368f0.tex}}}} + +\newcommand{\sailRISCVfnSetPTEBitsG}{\saildoclabelled{sailRISCVfnzzysetzyPTEzyBitszyG}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pte_bits_g31ff87423c27525881946540eb3368f0.tex}}}} + +\newcommand{\sailRISCVvalUpdatePTEBitsG}{\saildoclabelled{sailRISCVzzyupdatezyPTEzyBitszyG}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pte_bits_g7f8aa128b55e6f52846f32adb9e9a045.tex}}}} + +\newcommand{\sailRISCVfnUpdatePTEBitsG}{\saildoclabelled{sailRISCVfnzzyupdatezyPTEzyBitszyG}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pte_bits_g7f8aa128b55e6f52846f32adb9e9a045.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXXXXXXXXXXXupdateG}{\saildoclabelled{sailRISCVoverloadXXXXXXXXXXXXXXzupdatezyG}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXXXXXXXXXXXzupdate_ga61979e0097ae60f8598f57688dbae8b.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYYYYYYYYYYYModG}{\saildoclabelled{sailRISCVoverloadYYYYYYYYYYYYYYzzymodzyG}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYYYYYYYYYYYz_mod_g521053c016cb3f20bf7b96843a7a2cf4.tex}}}} + +\newcommand{\sailRISCVvalGetPTEBitsU}{\saildoclabelled{sailRISCVzzygetzyPTEzyBitszyU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pte_bits_u300741c1239ab0c65dc451f1700b52d8.tex}}}} + +\newcommand{\sailRISCVfnGetPTEBitsU}{\saildoclabelled{sailRISCVfnzzygetzyPTEzyBitszyU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pte_bits_u300741c1239ab0c65dc451f1700b52d8.tex}}}} + +\newcommand{\sailRISCVvalSetPTEBitsU}{\saildoclabelled{sailRISCVzzysetzyPTEzyBitszyU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pte_bits_u7152ad61970d5f3617d43634186dfaf6.tex}}}} + +\newcommand{\sailRISCVfnSetPTEBitsU}{\saildoclabelled{sailRISCVfnzzysetzyPTEzyBitszyU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pte_bits_u7152ad61970d5f3617d43634186dfaf6.tex}}}} + +\newcommand{\sailRISCVvalUpdatePTEBitsU}{\saildoclabelled{sailRISCVzzyupdatezyPTEzyBitszyU}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pte_bits_u977bcbc754c6423b417ff582c0113450.tex}}}} + +\newcommand{\sailRISCVfnUpdatePTEBitsU}{\saildoclabelled{sailRISCVfnzzyupdatezyPTEzyBitszyU}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pte_bits_u977bcbc754c6423b417ff582c0113450.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZZZZZZZZZZZupdateU}{\saildoclabelled{sailRISCVoverloadZZZZZZZZZZZZZZzupdatezyU}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZZZZZZZZZZZzupdate_uf25457b59a73b45bf964c7ab354d043c.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAAAAAAAAAAAModU}{\saildoclabelled{sailRISCVoverloadAAAAAAAAAAAAAAAzzymodzyU}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAAAAAAAAAAAz_mod_u960ee5decf6c18ea57af0e0387ef7d9c.tex}}}} + +\newcommand{\sailRISCVvalGetPTEBitsX}{\saildoclabelled{sailRISCVzzygetzyPTEzyBitszyX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pte_bits_x1b94d5b50779d8431b6a164038524c85.tex}}}} + +\newcommand{\sailRISCVfnGetPTEBitsX}{\saildoclabelled{sailRISCVfnzzygetzyPTEzyBitszyX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pte_bits_x1b94d5b50779d8431b6a164038524c85.tex}}}} + +\newcommand{\sailRISCVvalSetPTEBitsX}{\saildoclabelled{sailRISCVzzysetzyPTEzyBitszyX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pte_bits_xd8616f420b73ae2b89e310bf44d3a11a.tex}}}} + +\newcommand{\sailRISCVfnSetPTEBitsX}{\saildoclabelled{sailRISCVfnzzysetzyPTEzyBitszyX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pte_bits_xd8616f420b73ae2b89e310bf44d3a11a.tex}}}} + +\newcommand{\sailRISCVvalUpdatePTEBitsX}{\saildoclabelled{sailRISCVzzyupdatezyPTEzyBitszyX}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pte_bits_xe681f15474cf63965beb076cc7920964.tex}}}} + +\newcommand{\sailRISCVfnUpdatePTEBitsX}{\saildoclabelled{sailRISCVfnzzyupdatezyPTEzyBitszyX}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pte_bits_xe681f15474cf63965beb076cc7920964.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBBBBBBBBBBBupdateX}{\saildoclabelled{sailRISCVoverloadBBBBBBBBBBBBBBBzupdatezyX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBBBBBBBBBBBzupdate_x647abdeca7ac108f059148e19df0452e.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCCCCCCCCCCCModX}{\saildoclabelled{sailRISCVoverloadCCCCCCCCCCCCCCCzzymodzyX}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCCCCCCCCCCCz_mod_xc906d7554de3b79cd0cc78501a562587.tex}}}} + +\newcommand{\sailRISCVvalGetPTEBitsW}{\saildoclabelled{sailRISCVzzygetzyPTEzyBitszyW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pte_bits_w1d621d1d07d6e1ee0c6cbdd6eff9e867.tex}}}} + +\newcommand{\sailRISCVfnGetPTEBitsW}{\saildoclabelled{sailRISCVfnzzygetzyPTEzyBitszyW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pte_bits_w1d621d1d07d6e1ee0c6cbdd6eff9e867.tex}}}} + +\newcommand{\sailRISCVvalSetPTEBitsW}{\saildoclabelled{sailRISCVzzysetzyPTEzyBitszyW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pte_bits_w6af9664f46a96e5953a99351ac9f2eec.tex}}}} + +\newcommand{\sailRISCVfnSetPTEBitsW}{\saildoclabelled{sailRISCVfnzzysetzyPTEzyBitszyW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pte_bits_w6af9664f46a96e5953a99351ac9f2eec.tex}}}} + +\newcommand{\sailRISCVvalUpdatePTEBitsW}{\saildoclabelled{sailRISCVzzyupdatezyPTEzyBitszyW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pte_bits_w18528f50b9477178a61c7f8ca1c44e05.tex}}}} + +\newcommand{\sailRISCVfnUpdatePTEBitsW}{\saildoclabelled{sailRISCVfnzzyupdatezyPTEzyBitszyW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pte_bits_w18528f50b9477178a61c7f8ca1c44e05.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDDDDDDDDDDDDupdateW}{\saildoclabelled{sailRISCVoverloadDDDDDDDDDDDDDDDzupdatezyW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDDDDDDDDDDDDzupdate_w3209efc3cdd41bbc0810494fad257f06.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEEEEEEEEEEEEModW}{\saildoclabelled{sailRISCVoverloadEEEEEEEEEEEEEEEzzymodzyW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEEEEEEEEEEEEz_mod_w196183ee717bdd84cd7d5e4b2af0b219.tex}}}} + +\newcommand{\sailRISCVvalGetPTEBitsR}{\saildoclabelled{sailRISCVzzygetzyPTEzyBitszyR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pte_bits_r3a52c7a77cb754fb6a6eb55405de30cd.tex}}}} + +\newcommand{\sailRISCVfnGetPTEBitsR}{\saildoclabelled{sailRISCVfnzzygetzyPTEzyBitszyR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pte_bits_r3a52c7a77cb754fb6a6eb55405de30cd.tex}}}} + +\newcommand{\sailRISCVvalSetPTEBitsR}{\saildoclabelled{sailRISCVzzysetzyPTEzyBitszyR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pte_bits_r7ddb8623ba4795fb0437583737d032bc.tex}}}} + +\newcommand{\sailRISCVfnSetPTEBitsR}{\saildoclabelled{sailRISCVfnzzysetzyPTEzyBitszyR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pte_bits_r7ddb8623ba4795fb0437583737d032bc.tex}}}} + +\newcommand{\sailRISCVvalUpdatePTEBitsR}{\saildoclabelled{sailRISCVzzyupdatezyPTEzyBitszyR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pte_bits_r320dc9e678d3a436f17fb038197c377c.tex}}}} + +\newcommand{\sailRISCVfnUpdatePTEBitsR}{\saildoclabelled{sailRISCVfnzzyupdatezyPTEzyBitszyR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pte_bits_r320dc9e678d3a436f17fb038197c377c.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFFFFFFFFFFFFupdateR}{\saildoclabelled{sailRISCVoverloadFFFFFFFFFFFFFFFzupdatezyR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFFFFFFFFFFFFzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGGGGGGGGGGGGModR}{\saildoclabelled{sailRISCVoverloadGGGGGGGGGGGGGGGzzymodzyR}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGGGGGGGGGGGGz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex}}}} + +\newcommand{\sailRISCVvalGetPTEBitsV}{\saildoclabelled{sailRISCVzzygetzyPTEzyBitszyV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_pte_bits_vb582fda618233a0ee7948c90600227f6.tex}}}} + +\newcommand{\sailRISCVfnGetPTEBitsV}{\saildoclabelled{sailRISCVfnzzygetzyPTEzyBitszyV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_pte_bits_vb582fda618233a0ee7948c90600227f6.tex}}}} + +\newcommand{\sailRISCVvalSetPTEBitsV}{\saildoclabelled{sailRISCVzzysetzyPTEzyBitszyV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_pte_bits_ve9a7a4a2a11bf5683da07253607039cb.tex}}}} + +\newcommand{\sailRISCVfnSetPTEBitsV}{\saildoclabelled{sailRISCVfnzzysetzyPTEzyBitszyV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_pte_bits_ve9a7a4a2a11bf5683da07253607039cb.tex}}}} + +\newcommand{\sailRISCVvalUpdatePTEBitsV}{\saildoclabelled{sailRISCVzzyupdatezyPTEzyBitszyV}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_pte_bits_vf1ed439c0a93204c0e278d68fd72351c.tex}}}} + +\newcommand{\sailRISCVfnUpdatePTEBitsV}{\saildoclabelled{sailRISCVfnzzyupdatezyPTEzyBitszyV}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_pte_bits_vf1ed439c0a93204c0e278d68fd72351c.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHHHHHHHHHHHHupdateV}{\saildoclabelled{sailRISCVoverloadHHHHHHHHHHHHHHHzupdatezyV}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHHHHHHHHHHHHzupdate_v550d76e01b2aee2bcdcdd8fcb788e6ae.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIIIIIIIIIIIIModV}{\saildoclabelled{sailRISCVoverloadIIIIIIIIIIIIIIIzzymodzyV}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIIIIIIIIIIIIz_mod_v136fe7ecc31e11f2521faa02b71b57fa.tex}}}} + +\newcommand{\sailRISCVtypeextPte}{\saildoclabelled{sailRISCVtypezextPte}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezextpte08291a23c157d4bccbd0a79786be8e37.tex}}}} + +\newcommand{\sailRISCVtypeExtPTEBits}{\saildoclabelled{sailRISCVtypezExtzyPTEzyBits}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezext_pte_bitsa7158098bccf12e34e307673a27a3abd.tex}}}} + +\newcommand{\sailRISCVvalMkExtPTEBits}{\saildoclabelled{sailRISCVzMkzyExtzyPTEzyBits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_ext_pte_bitsc4519926cf8a81ebbc7a7489bdaaf1ef.tex}}}} + +\newcommand{\sailRISCVfnMkExtPTEBits}{\saildoclabelled{sailRISCVfnzMkzyExtzyPTEzyBits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_ext_pte_bitsc4519926cf8a81ebbc7a7489bdaaf1ef.tex}}}} + +\newcommand{\sailRISCVvalGetExtPTEBitsBits}{\saildoclabelled{sailRISCVzzygetzyExtzyPTEzyBitszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_ext_pte_bits_bits65e7ce08656cda27553d43325a4acc17.tex}}}} + +\newcommand{\sailRISCVfnGetExtPTEBitsBits}{\saildoclabelled{sailRISCVfnzzygetzyExtzyPTEzyBitszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_ext_pte_bits_bits65e7ce08656cda27553d43325a4acc17.tex}}}} + +\newcommand{\sailRISCVvalSetExtPTEBitsBits}{\saildoclabelled{sailRISCVzzysetzyExtzyPTEzyBitszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_ext_pte_bits_bitsa761c9ca2c6e788009a6f80b588af6be.tex}}}} + +\newcommand{\sailRISCVfnSetExtPTEBitsBits}{\saildoclabelled{sailRISCVfnzzysetzyExtzyPTEzyBitszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_ext_pte_bits_bitsa761c9ca2c6e788009a6f80b588af6be.tex}}}} + +\newcommand{\sailRISCVvalUpdateExtPTEBitsBits}{\saildoclabelled{sailRISCVzzyupdatezyExtzyPTEzyBitszybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_ext_pte_bits_bits5b635310b9455d491454822f0311285b.tex}}}} + +\newcommand{\sailRISCVfnUpdateExtPTEBitsBits}{\saildoclabelled{sailRISCVfnzzyupdatezyExtzyPTEzyBitszybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_ext_pte_bits_bits5b635310b9455d491454822f0311285b.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJJJJJJJJJJJJupdateBits}{\saildoclabelled{sailRISCVoverloadJJJJJJJJJJJJJJJzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJJJJJJJJJJJJzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKKKKKKKKKKKKModBits}{\saildoclabelled{sailRISCVoverloadKKKKKKKKKKKKKKKzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKKKKKKKKKKKKz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetExtPTEBitsCapWrite}{\saildoclabelled{sailRISCVzzygetzyExtzyPTEzyBitszyCapWrite}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_ext_pte_bits_capwrite0baac5a6f85e40fbdac28ee04067e65c.tex}}}} + +\newcommand{\sailRISCVfnGetExtPTEBitsCapWrite}{\saildoclabelled{sailRISCVfnzzygetzyExtzyPTEzyBitszyCapWrite}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_ext_pte_bits_capwrite0baac5a6f85e40fbdac28ee04067e65c.tex}}}} + +\newcommand{\sailRISCVvalSetExtPTEBitsCapWrite}{\saildoclabelled{sailRISCVzzysetzyExtzyPTEzyBitszyCapWrite}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_ext_pte_bits_capwriteccb693fb16cf80f8b094a130c168d1f7.tex}}}} + +\newcommand{\sailRISCVfnSetExtPTEBitsCapWrite}{\saildoclabelled{sailRISCVfnzzysetzyExtzyPTEzyBitszyCapWrite}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_ext_pte_bits_capwriteccb693fb16cf80f8b094a130c168d1f7.tex}}}} + +\newcommand{\sailRISCVvalUpdateExtPTEBitsCapWrite}{\saildoclabelled{sailRISCVzzyupdatezyExtzyPTEzyBitszyCapWrite}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_ext_pte_bits_capwritedcd59d2d59ab5341029d35f94ab8d27f.tex}}}} + +\newcommand{\sailRISCVfnUpdateExtPTEBitsCapWrite}{\saildoclabelled{sailRISCVfnzzyupdatezyExtzyPTEzyBitszyCapWrite}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_ext_pte_bits_capwritedcd59d2d59ab5341029d35f94ab8d27f.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLLLLLLLLLLLLupdateCapWrite}{\saildoclabelled{sailRISCVoverloadLLLLLLLLLLLLLLLzupdatezyCapWrite}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLLLLLLLLLLLLzupdate_capwritec85de060c1310bedb36952771a329406.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMMMMMMMMMMMMModCapWrite}{\saildoclabelled{sailRISCVoverloadMMMMMMMMMMMMMMMzzymodzyCapWrite}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMMMMMMMMMMMMz_mod_capwritee4dbda0d648b2ccd05f17d2dddd34537.tex}}}} + +\newcommand{\sailRISCVvalGetExtPTEBitsCapRead}{\saildoclabelled{sailRISCVzzygetzyExtzyPTEzyBitszyCapRead}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_ext_pte_bits_capread333ce4aba2e72cd3f2c792b515f6703a.tex}}}} + +\newcommand{\sailRISCVfnGetExtPTEBitsCapRead}{\saildoclabelled{sailRISCVfnzzygetzyExtzyPTEzyBitszyCapRead}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_ext_pte_bits_capread333ce4aba2e72cd3f2c792b515f6703a.tex}}}} + +\newcommand{\sailRISCVvalSetExtPTEBitsCapRead}{\saildoclabelled{sailRISCVzzysetzyExtzyPTEzyBitszyCapRead}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_ext_pte_bits_capreadfba293dd04ef2251e165147b0523320d.tex}}}} + +\newcommand{\sailRISCVfnSetExtPTEBitsCapRead}{\saildoclabelled{sailRISCVfnzzysetzyExtzyPTEzyBitszyCapRead}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_ext_pte_bits_capreadfba293dd04ef2251e165147b0523320d.tex}}}} + +\newcommand{\sailRISCVvalUpdateExtPTEBitsCapRead}{\saildoclabelled{sailRISCVzzyupdatezyExtzyPTEzyBitszyCapRead}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_ext_pte_bits_capreadb593f0e07fbd2201e626b373cddf00e2.tex}}}} + +\newcommand{\sailRISCVfnUpdateExtPTEBitsCapRead}{\saildoclabelled{sailRISCVfnzzyupdatezyExtzyPTEzyBitszyCapRead}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_ext_pte_bits_capreadb593f0e07fbd2201e626b373cddf00e2.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNNNNNNNNNNNNupdateCapRead}{\saildoclabelled{sailRISCVoverloadNNNNNNNNNNNNNNNzupdatezyCapRead}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNNNNNNNNNNNNzupdate_capread56ae6dad86051d18043217916904fc13.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOOOOOOOOOOOOModCapRead}{\saildoclabelled{sailRISCVoverloadOOOOOOOOOOOOOOOzzymodzyCapRead}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOOOOOOOOOOOOz_mod_capread786e2e18dc372ac62966150177d60d05.tex}}}} + +\newcommand{\sailRISCVvalisPTEPtr}{\saildoclabelled{sailRISCVzisPTEPtr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzispteptrba43877f6dc42c078f937aa41c879446.tex}}}} + +\newcommand{\sailRISCVfnisPTEPtr}{\saildoclabelled{sailRISCVfnzisPTEPtr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzispteptrba43877f6dc42c078f937aa41c879446.tex}}}} + +\newcommand{\sailRISCVvalisInvalidPTE}{\saildoclabelled{sailRISCVzisInvalidPTE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzisinvalidpte046e5b8d20df2f7ed228312986edeed3.tex}}}} + +\newcommand{\sailRISCVfnisInvalidPTE}{\saildoclabelled{sailRISCVfnzisInvalidPTE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzisinvalidpte046e5b8d20df2f7ed228312986edeed3.tex}}}} + +\newcommand{\sailRISCVtypePTECheck}{\saildoclabelled{sailRISCVtypezPTEzyCheck}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpte_checke4890d6be3f8a927bdcbd51b1a5be9d3.tex}}}} + +\newcommand{\sailRISCVvalcheckPTEPermission}{\saildoclabelled{sailRISCVzcheckPTEPermission}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcheckptepermissione94004ed8067442121c54ab1b95848d0.tex}}}} + +\newcommand{\sailRISCVfncheckPTEPermission}{\saildoclabelled{sailRISCVfnzcheckPTEPermission}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcheckptepermissione94004ed8067442121c54ab1b95848d0.tex}}}} + +\newcommand{\sailRISCVvalupdatePTEBits}{\saildoclabelled{sailRISCVzupdatezyPTEzyBits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzupdate_pte_bitsd84d357c2799412dbae43ca95464282b.tex}}}} + +\newcommand{\sailRISCVfnupdatePTEBits}{\saildoclabelled{sailRISCVfnzupdatezyPTEzyBits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzupdate_pte_bitsd84d357c2799412dbae43ca95464282b.tex}}}} + +\newcommand{\sailRISCVtypePTWError}{\saildoclabelled{sailRISCVtypezPTWzyError}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezptw_errore6acdb6d9897199828c918d43d6e0475.tex}}}} + +\newcommand{\sailRISCVvalptwErrorToStr}{\saildoclabelled{sailRISCVzptwzyerrorzytozystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzptw_error_to_stra1d14633b5815718af0734f3fe6896fb.tex}}}} + +\newcommand{\sailRISCVfnptwErrorToStr}{\saildoclabelled{sailRISCVfnzptwzyerrorzytozystr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzptw_error_to_stra1d14633b5815718af0734f3fe6896fb.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPPPPPPPPPPPPtoStr}{\saildoclabelled{sailRISCVoverloadPPPPPPPPPPPPPPPztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPPPPPPPPPPPPzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} + +\newcommand{\sailRISCVvalextGetPtwError}{\saildoclabelled{sailRISCVzextzygetzyptwzyerror}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_get_ptw_errorb38503fe4519ddae4ed13f9933d3c0a5.tex}}}} + +\newcommand{\sailRISCVfnextGetPtwError}{\saildoclabelled{sailRISCVfnzextzygetzyptwzyerror}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_get_ptw_errorb38503fe4519ddae4ed13f9933d3c0a5.tex}}}} + +\newcommand{\sailRISCVvaltranslationException}{\saildoclabelled{sailRISCVztranslationException}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztranslationexceptionbd47ba58dcb6fcc0be14f6efdd551ad8.tex}}}} + +\newcommand{\sailRISCVfntranslationException}{\saildoclabelled{sailRISCVfnztranslationException}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztranslationexceptionbd47ba58dcb6fcc0be14f6efdd551ad8.tex}}}} + +\newcommand{\sailRISCVtypevaddrThreeTwo}{\saildoclabelled{sailRISCVtypezvaddr32}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezvaddr321f5ce490361ac653dc4efb96fb3a4c98.tex}}}} + +\newcommand{\sailRISCVtypepaddrThreeTwo}{\saildoclabelled{sailRISCVtypezpaddr32}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpaddr326acc54e31f94adeb46900dacee685a4f.tex}}}} + +\newcommand{\sailRISCVtypepteThreeTwo}{\saildoclabelled{sailRISCVtypezpte32}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpte3289880ebfd8a537e73fa0b03b58db09a5.tex}}}} + +\newcommand{\sailRISCVtypeasidThreeTwo}{\saildoclabelled{sailRISCVtypezasid32}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezasid322158fcb044d3d182ba538bfe0883c5fc.tex}}}} + +\newcommand{\sailRISCVvalcurAsidThreeTwo}{\saildoclabelled{sailRISCVzcurAsid32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcurasid32f5f0e43e5813461351dff485d90e4aa4.tex}}}} + +\newcommand{\sailRISCVfncurAsidThreeTwo}{\saildoclabelled{sailRISCVfnzcurAsid32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcurasid32f5f0e43e5813461351dff485d90e4aa4.tex}}}} + +\newcommand{\sailRISCVvalcurPTBThreeTwo}{\saildoclabelled{sailRISCVzcurPTB32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcurptb320f32995fafcf5ebca7eeda72aee3f74f.tex}}}} + +\newcommand{\sailRISCVfncurPTBThreeTwo}{\saildoclabelled{sailRISCVfnzcurPTB32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcurptb320f32995fafcf5ebca7eeda72aee3f74f.tex}}}} + +\newcommand{\sailRISCVtypeSVThreeTwoVaddr}{\saildoclabelled{sailRISCVtypezSV32zyVaddr}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsv32_vaddre98811ac62644b6d3e91ca2d91e5afb3.tex}}}} + +\newcommand{\sailRISCVvalMkSVThreeTwoVaddr}{\saildoclabelled{sailRISCVzMkzySV32zyVaddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_sv32_vaddrd462eac178a4cd9186df0d708de0cabf.tex}}}} + +\newcommand{\sailRISCVfnMkSVThreeTwoVaddr}{\saildoclabelled{sailRISCVfnzMkzySV32zyVaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_sv32_vaddrd462eac178a4cd9186df0d708de0cabf.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeTwoVaddrBits}{\saildoclabelled{sailRISCVzzygetzySV32zyVaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv32_vaddr_bits0caf929432208e7079ae87374085c96f.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeTwoVaddrBits}{\saildoclabelled{sailRISCVfnzzygetzySV32zyVaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv32_vaddr_bits0caf929432208e7079ae87374085c96f.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeTwoVaddrBits}{\saildoclabelled{sailRISCVzzysetzySV32zyVaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv32_vaddr_bits598a6533ea70614d0d53c8cea8eced8e.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeTwoVaddrBits}{\saildoclabelled{sailRISCVfnzzysetzySV32zyVaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv32_vaddr_bits598a6533ea70614d0d53c8cea8eced8e.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeTwoVaddrBits}{\saildoclabelled{sailRISCVzzyupdatezySV32zyVaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv32_vaddr_bitsc681e87f3f4d859da7fee6d71d8b62c6.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeTwoVaddrBits}{\saildoclabelled{sailRISCVfnzzyupdatezySV32zyVaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv32_vaddr_bitsc681e87f3f4d859da7fee6d71d8b62c6.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQQQQQQQQQQQQupdateBits}{\saildoclabelled{sailRISCVoverloadQQQQQQQQQQQQQQQzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQQQQQQQQQQQQzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRRRRRRRRRRRRModBits}{\saildoclabelled{sailRISCVoverloadRRRRRRRRRRRRRRRzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRRRRRRRRRRRRz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeTwoVaddrVPNi}{\saildoclabelled{sailRISCVzzygetzySV32zyVaddrzyVPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv32_vaddr_vpniab523206431fb7d5db154d45287e96ba.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeTwoVaddrVPNi}{\saildoclabelled{sailRISCVfnzzygetzySV32zyVaddrzyVPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv32_vaddr_vpniab523206431fb7d5db154d45287e96ba.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeTwoVaddrVPNi}{\saildoclabelled{sailRISCVzzysetzySV32zyVaddrzyVPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv32_vaddr_vpnib8665127c6a283f2aacb5e3825422f5f.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeTwoVaddrVPNi}{\saildoclabelled{sailRISCVfnzzysetzySV32zyVaddrzyVPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv32_vaddr_vpnib8665127c6a283f2aacb5e3825422f5f.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeTwoVaddrVPNi}{\saildoclabelled{sailRISCVzzyupdatezySV32zyVaddrzyVPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv32_vaddr_vpnif3d232fd203d42def1af1b10dd8639df.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeTwoVaddrVPNi}{\saildoclabelled{sailRISCVfnzzyupdatezySV32zyVaddrzyVPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv32_vaddr_vpnif3d232fd203d42def1af1b10dd8639df.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSSSSSSSSSSSSupdateVPNi}{\saildoclabelled{sailRISCVoverloadSSSSSSSSSSSSSSSzupdatezyVPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSSSSSSSSSSSSzupdate_vpni561962844c1733722e96cd548b134172.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTTTTTTTTTTTTModVPNi}{\saildoclabelled{sailRISCVoverloadTTTTTTTTTTTTTTTzzymodzyVPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTTTTTTTTTTTTz_mod_vpni3dea7adc47f37ae733dae17ca8f9a4fe.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeTwoVaddrPgOfs}{\saildoclabelled{sailRISCVzzygetzySV32zyVaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv32_vaddr_pgofsdbfd9837672881608e9b05eff50b2e99.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeTwoVaddrPgOfs}{\saildoclabelled{sailRISCVfnzzygetzySV32zyVaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv32_vaddr_pgofsdbfd9837672881608e9b05eff50b2e99.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeTwoVaddrPgOfs}{\saildoclabelled{sailRISCVzzysetzySV32zyVaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv32_vaddr_pgofse1f36d8f721e1df38bd5c772d609bd45.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeTwoVaddrPgOfs}{\saildoclabelled{sailRISCVfnzzysetzySV32zyVaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv32_vaddr_pgofse1f36d8f721e1df38bd5c772d609bd45.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeTwoVaddrPgOfs}{\saildoclabelled{sailRISCVzzyupdatezySV32zyVaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv32_vaddr_pgofs4d5270a8a6277991b4da2a32d070beba.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeTwoVaddrPgOfs}{\saildoclabelled{sailRISCVfnzzyupdatezySV32zyVaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv32_vaddr_pgofs4d5270a8a6277991b4da2a32d070beba.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUUUUUUUUUUUUupdatePgOfs}{\saildoclabelled{sailRISCVoverloadUUUUUUUUUUUUUUUzupdatezyPgOfs}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUUUUUUUUUUUUzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVVVVVVVVVVVVModPgOfs}{\saildoclabelled{sailRISCVoverloadVVVVVVVVVVVVVVVzzymodzyPgOfs}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVVVVVVVVVVVVz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex}}}} + +\newcommand{\sailRISCVtypeSVThreeTwoPaddr}{\saildoclabelled{sailRISCVtypezSV32zyPaddr}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsv32_paddr9f5cfa9b0e96f55368dd46c5e00148a5.tex}}}} + +\newcommand{\sailRISCVvalMkSVThreeTwoPaddr}{\saildoclabelled{sailRISCVzMkzySV32zyPaddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_sv32_paddr38cec8bc7eb5a8f367e53058939b7ee9.tex}}}} + +\newcommand{\sailRISCVfnMkSVThreeTwoPaddr}{\saildoclabelled{sailRISCVfnzMkzySV32zyPaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_sv32_paddr38cec8bc7eb5a8f367e53058939b7ee9.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeTwoPaddrBits}{\saildoclabelled{sailRISCVzzygetzySV32zyPaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv32_paddr_bitsc60ef4da8b2834c670d1e63afd2220ae.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeTwoPaddrBits}{\saildoclabelled{sailRISCVfnzzygetzySV32zyPaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv32_paddr_bitsc60ef4da8b2834c670d1e63afd2220ae.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeTwoPaddrBits}{\saildoclabelled{sailRISCVzzysetzySV32zyPaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv32_paddr_bits7ac5072e9a9d0f202a9169b342d1027c.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeTwoPaddrBits}{\saildoclabelled{sailRISCVfnzzysetzySV32zyPaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv32_paddr_bits7ac5072e9a9d0f202a9169b342d1027c.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeTwoPaddrBits}{\saildoclabelled{sailRISCVzzyupdatezySV32zyPaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv32_paddr_bits471b1f564b9f112d8202c1386e4a2c40.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeTwoPaddrBits}{\saildoclabelled{sailRISCVfnzzyupdatezySV32zyPaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv32_paddr_bits471b1f564b9f112d8202c1386e4a2c40.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWWWWWWWWWWWWupdateBits}{\saildoclabelled{sailRISCVoverloadWWWWWWWWWWWWWWWzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWWWWWWWWWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXXXXXXXXXXXXModBits}{\saildoclabelled{sailRISCVoverloadXXXXXXXXXXXXXXXzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXXXXXXXXXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeTwoPaddrPPNi}{\saildoclabelled{sailRISCVzzygetzySV32zyPaddrzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv32_paddr_ppni1504c6497d4791cfe4234a5cc0365252.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeTwoPaddrPPNi}{\saildoclabelled{sailRISCVfnzzygetzySV32zyPaddrzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv32_paddr_ppni1504c6497d4791cfe4234a5cc0365252.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeTwoPaddrPPNi}{\saildoclabelled{sailRISCVzzysetzySV32zyPaddrzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv32_paddr_ppni94a2cc32ea73c50cb5cac893287046f5.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeTwoPaddrPPNi}{\saildoclabelled{sailRISCVfnzzysetzySV32zyPaddrzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv32_paddr_ppni94a2cc32ea73c50cb5cac893287046f5.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeTwoPaddrPPNi}{\saildoclabelled{sailRISCVzzyupdatezySV32zyPaddrzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv32_paddr_ppnic2e893ade647c24a430ebfdfc1376233.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeTwoPaddrPPNi}{\saildoclabelled{sailRISCVfnzzyupdatezySV32zyPaddrzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv32_paddr_ppnic2e893ade647c24a430ebfdfc1376233.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYYYYYYYYYYYYupdatePPNi}{\saildoclabelled{sailRISCVoverloadYYYYYYYYYYYYYYYzupdatezyPPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYYYYYYYYYYYYzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZZZZZZZZZZZZModPPNi}{\saildoclabelled{sailRISCVoverloadZZZZZZZZZZZZZZZzzymodzyPPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZZZZZZZZZZZZz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeTwoPaddrPgOfs}{\saildoclabelled{sailRISCVzzygetzySV32zyPaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv32_paddr_pgofs835ba010b40a7fd02d4a61e2ab2de4b4.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeTwoPaddrPgOfs}{\saildoclabelled{sailRISCVfnzzygetzySV32zyPaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv32_paddr_pgofs835ba010b40a7fd02d4a61e2ab2de4b4.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeTwoPaddrPgOfs}{\saildoclabelled{sailRISCVzzysetzySV32zyPaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv32_paddr_pgofsab302689c37e31253a4e6531b82c42ab.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeTwoPaddrPgOfs}{\saildoclabelled{sailRISCVfnzzysetzySV32zyPaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv32_paddr_pgofsab302689c37e31253a4e6531b82c42ab.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeTwoPaddrPgOfs}{\saildoclabelled{sailRISCVzzyupdatezySV32zyPaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv32_paddr_pgofsece69bfc0ddb3bbee82163605c655cd8.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeTwoPaddrPgOfs}{\saildoclabelled{sailRISCVfnzzyupdatezySV32zyPaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv32_paddr_pgofsece69bfc0ddb3bbee82163605c655cd8.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAAAAAAAAAAAAupdatePgOfs}{\saildoclabelled{sailRISCVoverloadAAAAAAAAAAAAAAAAzupdatezyPgOfs}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAAAAAAAAAAAAzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBBBBBBBBBBBBModPgOfs}{\saildoclabelled{sailRISCVoverloadBBBBBBBBBBBBBBBBzzymodzyPgOfs}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBBBBBBBBBBBBz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex}}}} + +\newcommand{\sailRISCVtypeSVThreeTwoPTE}{\saildoclabelled{sailRISCVtypezSV32zyPTE}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsv32_pte054d26e26929f0189a30c1313f7f54e1.tex}}}} + +\newcommand{\sailRISCVvalMkSVThreeTwoPTE}{\saildoclabelled{sailRISCVzMkzySV32zyPTE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_sv32_pte36c66a6cb6c5db181eeea4960a6a2882.tex}}}} + +\newcommand{\sailRISCVfnMkSVThreeTwoPTE}{\saildoclabelled{sailRISCVfnzMkzySV32zyPTE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_sv32_pte36c66a6cb6c5db181eeea4960a6a2882.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeTwoPTEBits}{\saildoclabelled{sailRISCVzzygetzySV32zyPTEzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv32_pte_bits184b603cf04702f500c26a3f44a95bce.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeTwoPTEBits}{\saildoclabelled{sailRISCVfnzzygetzySV32zyPTEzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv32_pte_bits184b603cf04702f500c26a3f44a95bce.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeTwoPTEBits}{\saildoclabelled{sailRISCVzzysetzySV32zyPTEzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv32_pte_bitsaf6e5291a5df8cafbd0f8c816eb211d7.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeTwoPTEBits}{\saildoclabelled{sailRISCVfnzzysetzySV32zyPTEzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv32_pte_bitsaf6e5291a5df8cafbd0f8c816eb211d7.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeTwoPTEBits}{\saildoclabelled{sailRISCVzzyupdatezySV32zyPTEzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv32_pte_bits6ed5ef3d3bdb39782740d15add28a8ca.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeTwoPTEBits}{\saildoclabelled{sailRISCVfnzzyupdatezySV32zyPTEzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv32_pte_bits6ed5ef3d3bdb39782740d15add28a8ca.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCCCCCCCCCCCCupdateBits}{\saildoclabelled{sailRISCVoverloadCCCCCCCCCCCCCCCCzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCCCCCCCCCCCCzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDDDDDDDDDDDDDModBits}{\saildoclabelled{sailRISCVoverloadDDDDDDDDDDDDDDDDzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDDDDDDDDDDDDDz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeTwoPTEPPNi}{\saildoclabelled{sailRISCVzzygetzySV32zyPTEzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv32_pte_ppni0d6471170f5c73c025591b74f4c1fe5e.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeTwoPTEPPNi}{\saildoclabelled{sailRISCVfnzzygetzySV32zyPTEzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv32_pte_ppni0d6471170f5c73c025591b74f4c1fe5e.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeTwoPTEPPNi}{\saildoclabelled{sailRISCVzzysetzySV32zyPTEzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv32_pte_ppnifab6de1238f9a347277b22b09cad438b.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeTwoPTEPPNi}{\saildoclabelled{sailRISCVfnzzysetzySV32zyPTEzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv32_pte_ppnifab6de1238f9a347277b22b09cad438b.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeTwoPTEPPNi}{\saildoclabelled{sailRISCVzzyupdatezySV32zyPTEzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv32_pte_ppni21f940c0d0da732c90fb464f03b30e8e.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeTwoPTEPPNi}{\saildoclabelled{sailRISCVfnzzyupdatezySV32zyPTEzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv32_pte_ppni21f940c0d0da732c90fb464f03b30e8e.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEEEEEEEEEEEEEupdatePPNi}{\saildoclabelled{sailRISCVoverloadEEEEEEEEEEEEEEEEzupdatezyPPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEEEEEEEEEEEEEzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFFFFFFFFFFFFFModPPNi}{\saildoclabelled{sailRISCVoverloadFFFFFFFFFFFFFFFFzzymodzyPPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFFFFFFFFFFFFFz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeTwoPTERSW}{\saildoclabelled{sailRISCVzzygetzySV32zyPTEzyRSW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv32_pte_rswe20144b93e162ff3dff60d8ea711bcfe.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeTwoPTERSW}{\saildoclabelled{sailRISCVfnzzygetzySV32zyPTEzyRSW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv32_pte_rswe20144b93e162ff3dff60d8ea711bcfe.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeTwoPTERSW}{\saildoclabelled{sailRISCVzzysetzySV32zyPTEzyRSW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv32_pte_rsw8ae54b55d6031c4f79807b3714efee6a.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeTwoPTERSW}{\saildoclabelled{sailRISCVfnzzysetzySV32zyPTEzyRSW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv32_pte_rsw8ae54b55d6031c4f79807b3714efee6a.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeTwoPTERSW}{\saildoclabelled{sailRISCVzzyupdatezySV32zyPTEzyRSW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv32_pte_rsw2127473fcefd5043f7339af205217e28.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeTwoPTERSW}{\saildoclabelled{sailRISCVfnzzyupdatezySV32zyPTEzyRSW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv32_pte_rsw2127473fcefd5043f7339af205217e28.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGGGGGGGGGGGGGupdateRSW}{\saildoclabelled{sailRISCVoverloadGGGGGGGGGGGGGGGGzupdatezyRSW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGGGGGGGGGGGGGzupdate_rsw7e773e2fdd93d70f9490f8401b97d4e9.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHHHHHHHHHHHHHModRSW}{\saildoclabelled{sailRISCVoverloadHHHHHHHHHHHHHHHHzzymodzyRSW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHHHHHHHHHHHHHz_mod_rswf4989a734cfde890cb5a1c8d3b4e6798.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeTwoPTEBITS}{\saildoclabelled{sailRISCVzzygetzySV32zyPTEzyBITS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv32_pte_bitse339fd2b2bd11b8fd6c71664018dafca.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeTwoPTEBITS}{\saildoclabelled{sailRISCVfnzzygetzySV32zyPTEzyBITS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv32_pte_bitse339fd2b2bd11b8fd6c71664018dafca.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeTwoPTEBITS}{\saildoclabelled{sailRISCVzzysetzySV32zyPTEzyBITS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv32_pte_bits4f565be9958b1f59ab14509c2773579f.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeTwoPTEBITS}{\saildoclabelled{sailRISCVfnzzysetzySV32zyPTEzyBITS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv32_pte_bits4f565be9958b1f59ab14509c2773579f.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeTwoPTEBITS}{\saildoclabelled{sailRISCVzzyupdatezySV32zyPTEzyBITS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv32_pte_bits55ab6942a6f92e27c0aaaffec4bc5b75.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeTwoPTEBITS}{\saildoclabelled{sailRISCVfnzzyupdatezySV32zyPTEzyBITS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv32_pte_bits55ab6942a6f92e27c0aaaffec4bc5b75.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIIIIIIIIIIIIIupdateBITS}{\saildoclabelled{sailRISCVoverloadIIIIIIIIIIIIIIIIzupdatezyBITS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIIIIIIIIIIIIIzupdate_bits5a3f6688b4b8427544fc33354e84149f.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJJJJJJJJJJJJJModBITS}{\saildoclabelled{sailRISCVoverloadJJJJJJJJJJJJJJJJzzymodzyBITS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJJJJJJJJJJJJJz_mod_bits60455a5b4231baf7b82d860f6efc2682.tex}}}} + +\newcommand{\sailRISCVtypepaddrSixFour}{\saildoclabelled{sailRISCVtypezpaddr64}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpaddr64f58cecb2121bad03c9e64da6cd15339b.tex}}}} + +\newcommand{\sailRISCVtypepteSixFour}{\saildoclabelled{sailRISCVtypezpte64}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpte6458e3ea8a5bd698d68e67a410a526fd60.tex}}}} + +\newcommand{\sailRISCVtypeasidSixFour}{\saildoclabelled{sailRISCVtypezasid64}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezasid64774ad52daab98e87d2a0c714473b041f.tex}}}} + +\newcommand{\sailRISCVvalcurAsidSixFour}{\saildoclabelled{sailRISCVzcurAsid64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcurasid64b2c4a622c945e46b0aea25ce9a07740f.tex}}}} + +\newcommand{\sailRISCVfncurAsidSixFour}{\saildoclabelled{sailRISCVfnzcurAsid64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcurasid64b2c4a622c945e46b0aea25ce9a07740f.tex}}}} + +\newcommand{\sailRISCVvalcurPTBSixFour}{\saildoclabelled{sailRISCVzcurPTB64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcurptb6479eaa1d344e911b626ff56a8856bcd50.tex}}}} + +\newcommand{\sailRISCVfncurPTBSixFour}{\saildoclabelled{sailRISCVfnzcurPTB64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcurptb6479eaa1d344e911b626ff56a8856bcd50.tex}}}} + +\newcommand{\sailRISCVtypevaddrThreeNine}{\saildoclabelled{sailRISCVtypezvaddr39}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezvaddr39d9a5d0d949c4cbbbc71c053903cf73cb.tex}}}} + +\newcommand{\sailRISCVtypeSVThreeNineVaddr}{\saildoclabelled{sailRISCVtypezSV39zyVaddr}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsv39_vaddr9f1c1a92c2c683b5b23ddacf71051c03.tex}}}} + +\newcommand{\sailRISCVvalMkSVThreeNineVaddr}{\saildoclabelled{sailRISCVzMkzySV39zyVaddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_sv39_vaddr6221e811d934736591eeb06d6df3537c.tex}}}} + +\newcommand{\sailRISCVfnMkSVThreeNineVaddr}{\saildoclabelled{sailRISCVfnzMkzySV39zyVaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_sv39_vaddr6221e811d934736591eeb06d6df3537c.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeNineVaddrBits}{\saildoclabelled{sailRISCVzzygetzySV39zyVaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv39_vaddr_bits364185505ec9c15373ab9c1464724954.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeNineVaddrBits}{\saildoclabelled{sailRISCVfnzzygetzySV39zyVaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv39_vaddr_bits364185505ec9c15373ab9c1464724954.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeNineVaddrBits}{\saildoclabelled{sailRISCVzzysetzySV39zyVaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv39_vaddr_bits9dda733adeb14d86c90ae7719235d0bc.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeNineVaddrBits}{\saildoclabelled{sailRISCVfnzzysetzySV39zyVaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv39_vaddr_bits9dda733adeb14d86c90ae7719235d0bc.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeNineVaddrBits}{\saildoclabelled{sailRISCVzzyupdatezySV39zyVaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv39_vaddr_bits9b5c877641996c39232fdaa69695b175.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeNineVaddrBits}{\saildoclabelled{sailRISCVfnzzyupdatezySV39zyVaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv39_vaddr_bits9b5c877641996c39232fdaa69695b175.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKKKKKKKKKKKKKupdateBits}{\saildoclabelled{sailRISCVoverloadKKKKKKKKKKKKKKKKzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKKKKKKKKKKKKKzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLLLLLLLLLLLLLModBits}{\saildoclabelled{sailRISCVoverloadLLLLLLLLLLLLLLLLzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLLLLLLLLLLLLLz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeNineVaddrVPNi}{\saildoclabelled{sailRISCVzzygetzySV39zyVaddrzyVPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv39_vaddr_vpni21781895f7de6beeab4c3b9429948ba9.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeNineVaddrVPNi}{\saildoclabelled{sailRISCVfnzzygetzySV39zyVaddrzyVPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv39_vaddr_vpni21781895f7de6beeab4c3b9429948ba9.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeNineVaddrVPNi}{\saildoclabelled{sailRISCVzzysetzySV39zyVaddrzyVPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv39_vaddr_vpni862fded28960b086e268044e94d900bd.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeNineVaddrVPNi}{\saildoclabelled{sailRISCVfnzzysetzySV39zyVaddrzyVPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv39_vaddr_vpni862fded28960b086e268044e94d900bd.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeNineVaddrVPNi}{\saildoclabelled{sailRISCVzzyupdatezySV39zyVaddrzyVPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv39_vaddr_vpnibc20f5f41da77bf31c390df8cd865198.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeNineVaddrVPNi}{\saildoclabelled{sailRISCVfnzzyupdatezySV39zyVaddrzyVPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv39_vaddr_vpnibc20f5f41da77bf31c390df8cd865198.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMMMMMMMMMMMMMupdateVPNi}{\saildoclabelled{sailRISCVoverloadMMMMMMMMMMMMMMMMzupdatezyVPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMMMMMMMMMMMMMzupdate_vpni561962844c1733722e96cd548b134172.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNNNNNNNNNNNNNModVPNi}{\saildoclabelled{sailRISCVoverloadNNNNNNNNNNNNNNNNzzymodzyVPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNNNNNNNNNNNNNz_mod_vpni3dea7adc47f37ae733dae17ca8f9a4fe.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeNineVaddrPgOfs}{\saildoclabelled{sailRISCVzzygetzySV39zyVaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv39_vaddr_pgofs4e8b61f46949b7eec961a817eeb9caf2.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeNineVaddrPgOfs}{\saildoclabelled{sailRISCVfnzzygetzySV39zyVaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv39_vaddr_pgofs4e8b61f46949b7eec961a817eeb9caf2.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeNineVaddrPgOfs}{\saildoclabelled{sailRISCVzzysetzySV39zyVaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv39_vaddr_pgofs10da37447f07e7766bd99c3f4712450e.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeNineVaddrPgOfs}{\saildoclabelled{sailRISCVfnzzysetzySV39zyVaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv39_vaddr_pgofs10da37447f07e7766bd99c3f4712450e.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeNineVaddrPgOfs}{\saildoclabelled{sailRISCVzzyupdatezySV39zyVaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv39_vaddr_pgofs2203553b5bf9afd58276a7958197b4c6.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeNineVaddrPgOfs}{\saildoclabelled{sailRISCVfnzzyupdatezySV39zyVaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv39_vaddr_pgofs2203553b5bf9afd58276a7958197b4c6.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOOOOOOOOOOOOOupdatePgOfs}{\saildoclabelled{sailRISCVoverloadOOOOOOOOOOOOOOOOzupdatezyPgOfs}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOOOOOOOOOOOOOzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPPPPPPPPPPPPPModPgOfs}{\saildoclabelled{sailRISCVoverloadPPPPPPPPPPPPPPPPzzymodzyPgOfs}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPPPPPPPPPPPPPz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex}}}} + +\newcommand{\sailRISCVtypeSVThreeNinePaddr}{\saildoclabelled{sailRISCVtypezSV39zyPaddr}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsv39_paddr8e7ac2ddc4a718336a4f3894cdd91edd.tex}}}} + +\newcommand{\sailRISCVvalMkSVThreeNinePaddr}{\saildoclabelled{sailRISCVzMkzySV39zyPaddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_sv39_paddr9839b2830ababd96b40ec4ed4e215f85.tex}}}} + +\newcommand{\sailRISCVfnMkSVThreeNinePaddr}{\saildoclabelled{sailRISCVfnzMkzySV39zyPaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_sv39_paddr9839b2830ababd96b40ec4ed4e215f85.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeNinePaddrBits}{\saildoclabelled{sailRISCVzzygetzySV39zyPaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv39_paddr_bits834b4f44fc6e69ffd391c9b6237cce2b.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeNinePaddrBits}{\saildoclabelled{sailRISCVfnzzygetzySV39zyPaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv39_paddr_bits834b4f44fc6e69ffd391c9b6237cce2b.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeNinePaddrBits}{\saildoclabelled{sailRISCVzzysetzySV39zyPaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv39_paddr_bits3ec2652094be77813b00186e0c009ce4.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeNinePaddrBits}{\saildoclabelled{sailRISCVfnzzysetzySV39zyPaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv39_paddr_bits3ec2652094be77813b00186e0c009ce4.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeNinePaddrBits}{\saildoclabelled{sailRISCVzzyupdatezySV39zyPaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv39_paddr_bits95d51c315963bb06758677d399020d4c.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeNinePaddrBits}{\saildoclabelled{sailRISCVfnzzyupdatezySV39zyPaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv39_paddr_bits95d51c315963bb06758677d399020d4c.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQQQQQQQQQQQQQupdateBits}{\saildoclabelled{sailRISCVoverloadQQQQQQQQQQQQQQQQzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQQQQQQQQQQQQQzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRRRRRRRRRRRRRModBits}{\saildoclabelled{sailRISCVoverloadRRRRRRRRRRRRRRRRzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRRRRRRRRRRRRRz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeNinePaddrPPNi}{\saildoclabelled{sailRISCVzzygetzySV39zyPaddrzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv39_paddr_ppnie78045a960397b424c97285aca9dd29b.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeNinePaddrPPNi}{\saildoclabelled{sailRISCVfnzzygetzySV39zyPaddrzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv39_paddr_ppnie78045a960397b424c97285aca9dd29b.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeNinePaddrPPNi}{\saildoclabelled{sailRISCVzzysetzySV39zyPaddrzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv39_paddr_ppni179def635ee83e4cac60b403fcd2e376.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeNinePaddrPPNi}{\saildoclabelled{sailRISCVfnzzysetzySV39zyPaddrzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv39_paddr_ppni179def635ee83e4cac60b403fcd2e376.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeNinePaddrPPNi}{\saildoclabelled{sailRISCVzzyupdatezySV39zyPaddrzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv39_paddr_ppni64a04f2f491820010df9118b96fe3bb1.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeNinePaddrPPNi}{\saildoclabelled{sailRISCVfnzzyupdatezySV39zyPaddrzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv39_paddr_ppni64a04f2f491820010df9118b96fe3bb1.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSSSSSSSSSSSSSupdatePPNi}{\saildoclabelled{sailRISCVoverloadSSSSSSSSSSSSSSSSzupdatezyPPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSSSSSSSSSSSSSzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTTTTTTTTTTTTTModPPNi}{\saildoclabelled{sailRISCVoverloadTTTTTTTTTTTTTTTTzzymodzyPPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTTTTTTTTTTTTTz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeNinePaddrPgOfs}{\saildoclabelled{sailRISCVzzygetzySV39zyPaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv39_paddr_pgofsb92f2e38ca030595309ba60289cfc67e.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeNinePaddrPgOfs}{\saildoclabelled{sailRISCVfnzzygetzySV39zyPaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv39_paddr_pgofsb92f2e38ca030595309ba60289cfc67e.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeNinePaddrPgOfs}{\saildoclabelled{sailRISCVzzysetzySV39zyPaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv39_paddr_pgofscbde8c5af7576e92ba5fca9143abbb66.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeNinePaddrPgOfs}{\saildoclabelled{sailRISCVfnzzysetzySV39zyPaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv39_paddr_pgofscbde8c5af7576e92ba5fca9143abbb66.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeNinePaddrPgOfs}{\saildoclabelled{sailRISCVzzyupdatezySV39zyPaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv39_paddr_pgofs92e3fd4a4ef641b9bd4695bcb4e6865d.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeNinePaddrPgOfs}{\saildoclabelled{sailRISCVfnzzyupdatezySV39zyPaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv39_paddr_pgofs92e3fd4a4ef641b9bd4695bcb4e6865d.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUUUUUUUUUUUUUupdatePgOfs}{\saildoclabelled{sailRISCVoverloadUUUUUUUUUUUUUUUUzupdatezyPgOfs}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUUUUUUUUUUUUUzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVVVVVVVVVVVVVModPgOfs}{\saildoclabelled{sailRISCVoverloadVVVVVVVVVVVVVVVVzzymodzyPgOfs}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVVVVVVVVVVVVVz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex}}}} + +\newcommand{\sailRISCVtypeSVThreeNinePTE}{\saildoclabelled{sailRISCVtypezSV39zyPTE}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsv39_ptea9e6dd73ae92b5be63b2a7edb5ccc8a3.tex}}}} + +\newcommand{\sailRISCVvalMkSVThreeNinePTE}{\saildoclabelled{sailRISCVzMkzySV39zyPTE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_sv39_pte72f20a67de4a391e796c728a1b1411bf.tex}}}} + +\newcommand{\sailRISCVfnMkSVThreeNinePTE}{\saildoclabelled{sailRISCVfnzMkzySV39zyPTE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_sv39_pte72f20a67de4a391e796c728a1b1411bf.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeNinePTEBits}{\saildoclabelled{sailRISCVzzygetzySV39zyPTEzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv39_pte_bits0a004475205374ae82c050106619c089.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeNinePTEBits}{\saildoclabelled{sailRISCVfnzzygetzySV39zyPTEzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv39_pte_bits0a004475205374ae82c050106619c089.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeNinePTEBits}{\saildoclabelled{sailRISCVzzysetzySV39zyPTEzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv39_pte_bitsde1d8d06cbfb62b5b9924a167cdc23ec.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeNinePTEBits}{\saildoclabelled{sailRISCVfnzzysetzySV39zyPTEzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv39_pte_bitsde1d8d06cbfb62b5b9924a167cdc23ec.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeNinePTEBits}{\saildoclabelled{sailRISCVzzyupdatezySV39zyPTEzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv39_pte_bitsf70d63d10d4409523d5b20cddef1d791.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeNinePTEBits}{\saildoclabelled{sailRISCVfnzzyupdatezySV39zyPTEzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv39_pte_bitsf70d63d10d4409523d5b20cddef1d791.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWWWWWWWWWWWWWupdateBits}{\saildoclabelled{sailRISCVoverloadWWWWWWWWWWWWWWWWzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWWWWWWWWWWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXXXXXXXXXXXXXModBits}{\saildoclabelled{sailRISCVoverloadXXXXXXXXXXXXXXXXzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXXXXXXXXXXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeNinePTEExt}{\saildoclabelled{sailRISCVzzygetzySV39zyPTEzyExt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv39_pte_ext400fef25828eab6cdcb38e7e7fd21c72.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeNinePTEExt}{\saildoclabelled{sailRISCVfnzzygetzySV39zyPTEzyExt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv39_pte_ext400fef25828eab6cdcb38e7e7fd21c72.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeNinePTEExt}{\saildoclabelled{sailRISCVzzysetzySV39zyPTEzyExt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv39_pte_ext579db3d4726a0e68687d2bef859f8658.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeNinePTEExt}{\saildoclabelled{sailRISCVfnzzysetzySV39zyPTEzyExt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv39_pte_ext579db3d4726a0e68687d2bef859f8658.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeNinePTEExt}{\saildoclabelled{sailRISCVzzyupdatezySV39zyPTEzyExt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv39_pte_ext7389da76692695bdeeaa0a6612d2ddf3.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeNinePTEExt}{\saildoclabelled{sailRISCVfnzzyupdatezySV39zyPTEzyExt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv39_pte_ext7389da76692695bdeeaa0a6612d2ddf3.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYYYYYYYYYYYYYupdateExt}{\saildoclabelled{sailRISCVoverloadYYYYYYYYYYYYYYYYzupdatezyExt}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYYYYYYYYYYYYYzupdate_ext4723b679799a58fbdda2ba5058faef53.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZZZZZZZZZZZZZModExt}{\saildoclabelled{sailRISCVoverloadZZZZZZZZZZZZZZZZzzymodzyExt}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZZZZZZZZZZZZZz_mod_extee31bbe7b534e72c2dacd0c25ba837ba.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeNinePTEPPNi}{\saildoclabelled{sailRISCVzzygetzySV39zyPTEzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv39_pte_ppni426489f4764a5d0ade3e9346a0b394c7.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeNinePTEPPNi}{\saildoclabelled{sailRISCVfnzzygetzySV39zyPTEzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv39_pte_ppni426489f4764a5d0ade3e9346a0b394c7.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeNinePTEPPNi}{\saildoclabelled{sailRISCVzzysetzySV39zyPTEzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv39_pte_ppnif74fb7c03da31075e81899e241f18909.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeNinePTEPPNi}{\saildoclabelled{sailRISCVfnzzysetzySV39zyPTEzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv39_pte_ppnif74fb7c03da31075e81899e241f18909.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeNinePTEPPNi}{\saildoclabelled{sailRISCVzzyupdatezySV39zyPTEzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv39_pte_ppni4bb75edea91e119f5e4b777a201ca7de.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeNinePTEPPNi}{\saildoclabelled{sailRISCVfnzzyupdatezySV39zyPTEzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv39_pte_ppni4bb75edea91e119f5e4b777a201ca7de.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAAAAAAAAAAAAAupdatePPNi}{\saildoclabelled{sailRISCVoverloadAAAAAAAAAAAAAAAAAzupdatezyPPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAAAAAAAAAAAAAzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBBBBBBBBBBBBBModPPNi}{\saildoclabelled{sailRISCVoverloadBBBBBBBBBBBBBBBBBzzymodzyPPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBBBBBBBBBBBBBz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeNinePTERSW}{\saildoclabelled{sailRISCVzzygetzySV39zyPTEzyRSW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv39_pte_rswb7f6ce3a77a6a7a556a5530cded759fa.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeNinePTERSW}{\saildoclabelled{sailRISCVfnzzygetzySV39zyPTEzyRSW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv39_pte_rswb7f6ce3a77a6a7a556a5530cded759fa.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeNinePTERSW}{\saildoclabelled{sailRISCVzzysetzySV39zyPTEzyRSW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv39_pte_rsw9dcf0d2943fb66aef30725a715b1c011.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeNinePTERSW}{\saildoclabelled{sailRISCVfnzzysetzySV39zyPTEzyRSW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv39_pte_rsw9dcf0d2943fb66aef30725a715b1c011.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeNinePTERSW}{\saildoclabelled{sailRISCVzzyupdatezySV39zyPTEzyRSW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv39_pte_rsw7d745d7147024b1db9a0ab778ae3aa90.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeNinePTERSW}{\saildoclabelled{sailRISCVfnzzyupdatezySV39zyPTEzyRSW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv39_pte_rsw7d745d7147024b1db9a0ab778ae3aa90.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCCCCCCCCCCCCCupdateRSW}{\saildoclabelled{sailRISCVoverloadCCCCCCCCCCCCCCCCCzupdatezyRSW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCCCCCCCCCCCCCzupdate_rsw7e773e2fdd93d70f9490f8401b97d4e9.tex}}}} + +\newcommand{\sailRISCVoverloadDDDDDDDDDDDDDDDDDModRSW}{\saildoclabelled{sailRISCVoverloadDDDDDDDDDDDDDDDDDzzymodzyRSW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadDDDDDDDDDDDDDDDDDz_mod_rswf4989a734cfde890cb5a1c8d3b4e6798.tex}}}} + +\newcommand{\sailRISCVvalGetSVThreeNinePTEBITS}{\saildoclabelled{sailRISCVzzygetzySV39zyPTEzyBITS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv39_pte_bits2894d61e8f7557590f0240a44dc9dca4.tex}}}} + +\newcommand{\sailRISCVfnGetSVThreeNinePTEBITS}{\saildoclabelled{sailRISCVfnzzygetzySV39zyPTEzyBITS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv39_pte_bits2894d61e8f7557590f0240a44dc9dca4.tex}}}} + +\newcommand{\sailRISCVvalSetSVThreeNinePTEBITS}{\saildoclabelled{sailRISCVzzysetzySV39zyPTEzyBITS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv39_pte_bitse9589b312fc9f713a1d54dadb5f0e45d.tex}}}} + +\newcommand{\sailRISCVfnSetSVThreeNinePTEBITS}{\saildoclabelled{sailRISCVfnzzysetzySV39zyPTEzyBITS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv39_pte_bitse9589b312fc9f713a1d54dadb5f0e45d.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVThreeNinePTEBITS}{\saildoclabelled{sailRISCVzzyupdatezySV39zyPTEzyBITS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv39_pte_bits3f8498b470f391c57cca777dadcbfb2e.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVThreeNinePTEBITS}{\saildoclabelled{sailRISCVfnzzyupdatezySV39zyPTEzyBITS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv39_pte_bits3f8498b470f391c57cca777dadcbfb2e.tex}}}} + +\newcommand{\sailRISCVoverloadEEEEEEEEEEEEEEEEEupdateBITS}{\saildoclabelled{sailRISCVoverloadEEEEEEEEEEEEEEEEEzupdatezyBITS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadEEEEEEEEEEEEEEEEEzupdate_bits5a3f6688b4b8427544fc33354e84149f.tex}}}} + +\newcommand{\sailRISCVoverloadFFFFFFFFFFFFFFFFFModBITS}{\saildoclabelled{sailRISCVoverloadFFFFFFFFFFFFFFFFFzzymodzyBITS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadFFFFFFFFFFFFFFFFFz_mod_bits60455a5b4231baf7b82d860f6efc2682.tex}}}} + +\newcommand{\sailRISCVtypevaddrFourEight}{\saildoclabelled{sailRISCVtypezvaddr48}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezvaddr4805a60a23d20e81c5ff9e6a5609aea22f.tex}}}} + +\newcommand{\sailRISCVtypepteFourEight}{\saildoclabelled{sailRISCVtypezpte48}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezpte48f7bf6ee72ef0ed2c1101c9e605f2f127.tex}}}} + +\newcommand{\sailRISCVtypeSVFourEightVaddr}{\saildoclabelled{sailRISCVtypezSV48zyVaddr}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsv48_vaddrd3fdeb6a4cba35ed677a6112bb677bc2.tex}}}} + +\newcommand{\sailRISCVvalMkSVFourEightVaddr}{\saildoclabelled{sailRISCVzMkzySV48zyVaddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_sv48_vaddr1a3eef2a9372d3cb53334a8a4bf1eaf9.tex}}}} + +\newcommand{\sailRISCVfnMkSVFourEightVaddr}{\saildoclabelled{sailRISCVfnzMkzySV48zyVaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_sv48_vaddr1a3eef2a9372d3cb53334a8a4bf1eaf9.tex}}}} + +\newcommand{\sailRISCVvalGetSVFourEightVaddrBits}{\saildoclabelled{sailRISCVzzygetzySV48zyVaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv48_vaddr_bits2beaae5ea8854498717f33a471bb5c12.tex}}}} + +\newcommand{\sailRISCVfnGetSVFourEightVaddrBits}{\saildoclabelled{sailRISCVfnzzygetzySV48zyVaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv48_vaddr_bits2beaae5ea8854498717f33a471bb5c12.tex}}}} + +\newcommand{\sailRISCVvalSetSVFourEightVaddrBits}{\saildoclabelled{sailRISCVzzysetzySV48zyVaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv48_vaddr_bitsd37e2d8f1c88cf733caeb08edd844785.tex}}}} + +\newcommand{\sailRISCVfnSetSVFourEightVaddrBits}{\saildoclabelled{sailRISCVfnzzysetzySV48zyVaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv48_vaddr_bitsd37e2d8f1c88cf733caeb08edd844785.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVFourEightVaddrBits}{\saildoclabelled{sailRISCVzzyupdatezySV48zyVaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv48_vaddr_bits591ffccf87e6224a472977f7dbf4b171.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVFourEightVaddrBits}{\saildoclabelled{sailRISCVfnzzyupdatezySV48zyVaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv48_vaddr_bits591ffccf87e6224a472977f7dbf4b171.tex}}}} + +\newcommand{\sailRISCVoverloadGGGGGGGGGGGGGGGGGupdateBits}{\saildoclabelled{sailRISCVoverloadGGGGGGGGGGGGGGGGGzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadGGGGGGGGGGGGGGGGGzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadHHHHHHHHHHHHHHHHHModBits}{\saildoclabelled{sailRISCVoverloadHHHHHHHHHHHHHHHHHzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadHHHHHHHHHHHHHHHHHz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSVFourEightVaddrVPNi}{\saildoclabelled{sailRISCVzzygetzySV48zyVaddrzyVPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv48_vaddr_vpnibe8fbceb3423612d8be18c52f74da3d9.tex}}}} + +\newcommand{\sailRISCVfnGetSVFourEightVaddrVPNi}{\saildoclabelled{sailRISCVfnzzygetzySV48zyVaddrzyVPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv48_vaddr_vpnibe8fbceb3423612d8be18c52f74da3d9.tex}}}} + +\newcommand{\sailRISCVvalSetSVFourEightVaddrVPNi}{\saildoclabelled{sailRISCVzzysetzySV48zyVaddrzyVPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv48_vaddr_vpni49c5d04a526f6722627d07f53e7f09dc.tex}}}} + +\newcommand{\sailRISCVfnSetSVFourEightVaddrVPNi}{\saildoclabelled{sailRISCVfnzzysetzySV48zyVaddrzyVPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv48_vaddr_vpni49c5d04a526f6722627d07f53e7f09dc.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVFourEightVaddrVPNi}{\saildoclabelled{sailRISCVzzyupdatezySV48zyVaddrzyVPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv48_vaddr_vpni9035d832e2b055cf87646fbf4511fccb.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVFourEightVaddrVPNi}{\saildoclabelled{sailRISCVfnzzyupdatezySV48zyVaddrzyVPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv48_vaddr_vpni9035d832e2b055cf87646fbf4511fccb.tex}}}} + +\newcommand{\sailRISCVoverloadIIIIIIIIIIIIIIIIIupdateVPNi}{\saildoclabelled{sailRISCVoverloadIIIIIIIIIIIIIIIIIzupdatezyVPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadIIIIIIIIIIIIIIIIIzupdate_vpni561962844c1733722e96cd548b134172.tex}}}} + +\newcommand{\sailRISCVoverloadJJJJJJJJJJJJJJJJJModVPNi}{\saildoclabelled{sailRISCVoverloadJJJJJJJJJJJJJJJJJzzymodzyVPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadJJJJJJJJJJJJJJJJJz_mod_vpni3dea7adc47f37ae733dae17ca8f9a4fe.tex}}}} + +\newcommand{\sailRISCVvalGetSVFourEightVaddrPgOfs}{\saildoclabelled{sailRISCVzzygetzySV48zyVaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv48_vaddr_pgofsb1f1b723984e85436ebf972d3c0794b0.tex}}}} + +\newcommand{\sailRISCVfnGetSVFourEightVaddrPgOfs}{\saildoclabelled{sailRISCVfnzzygetzySV48zyVaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv48_vaddr_pgofsb1f1b723984e85436ebf972d3c0794b0.tex}}}} + +\newcommand{\sailRISCVvalSetSVFourEightVaddrPgOfs}{\saildoclabelled{sailRISCVzzysetzySV48zyVaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv48_vaddr_pgofsed661e13958cf27c80315e6cd60b8a36.tex}}}} + +\newcommand{\sailRISCVfnSetSVFourEightVaddrPgOfs}{\saildoclabelled{sailRISCVfnzzysetzySV48zyVaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv48_vaddr_pgofsed661e13958cf27c80315e6cd60b8a36.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVFourEightVaddrPgOfs}{\saildoclabelled{sailRISCVzzyupdatezySV48zyVaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv48_vaddr_pgofs474bdc293738ab8c86555518304df3b0.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVFourEightVaddrPgOfs}{\saildoclabelled{sailRISCVfnzzyupdatezySV48zyVaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv48_vaddr_pgofs474bdc293738ab8c86555518304df3b0.tex}}}} + +\newcommand{\sailRISCVoverloadKKKKKKKKKKKKKKKKKupdatePgOfs}{\saildoclabelled{sailRISCVoverloadKKKKKKKKKKKKKKKKKzupdatezyPgOfs}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadKKKKKKKKKKKKKKKKKzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex}}}} + +\newcommand{\sailRISCVoverloadLLLLLLLLLLLLLLLLLModPgOfs}{\saildoclabelled{sailRISCVoverloadLLLLLLLLLLLLLLLLLzzymodzyPgOfs}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadLLLLLLLLLLLLLLLLLz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex}}}} + +\newcommand{\sailRISCVtypeSVFourEightPaddr}{\saildoclabelled{sailRISCVtypezSV48zyPaddr}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsv48_paddrb31db8c73707db172008fed5607c9247.tex}}}} + +\newcommand{\sailRISCVvalMkSVFourEightPaddr}{\saildoclabelled{sailRISCVzMkzySV48zyPaddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_sv48_paddr2e91c2bf0030c89b31d06021ef3c01eb.tex}}}} + +\newcommand{\sailRISCVfnMkSVFourEightPaddr}{\saildoclabelled{sailRISCVfnzMkzySV48zyPaddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_sv48_paddr2e91c2bf0030c89b31d06021ef3c01eb.tex}}}} + +\newcommand{\sailRISCVvalGetSVFourEightPaddrBits}{\saildoclabelled{sailRISCVzzygetzySV48zyPaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv48_paddr_bits254b25d43747ddb1b15788364bb3ff6f.tex}}}} + +\newcommand{\sailRISCVfnGetSVFourEightPaddrBits}{\saildoclabelled{sailRISCVfnzzygetzySV48zyPaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv48_paddr_bits254b25d43747ddb1b15788364bb3ff6f.tex}}}} + +\newcommand{\sailRISCVvalSetSVFourEightPaddrBits}{\saildoclabelled{sailRISCVzzysetzySV48zyPaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv48_paddr_bits50513db01891b630792f1d6a843c784b.tex}}}} + +\newcommand{\sailRISCVfnSetSVFourEightPaddrBits}{\saildoclabelled{sailRISCVfnzzysetzySV48zyPaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv48_paddr_bits50513db01891b630792f1d6a843c784b.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVFourEightPaddrBits}{\saildoclabelled{sailRISCVzzyupdatezySV48zyPaddrzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv48_paddr_bitsd392e84dd67a8ca48490ef502cca7bd9.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVFourEightPaddrBits}{\saildoclabelled{sailRISCVfnzzyupdatezySV48zyPaddrzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv48_paddr_bitsd392e84dd67a8ca48490ef502cca7bd9.tex}}}} + +\newcommand{\sailRISCVoverloadMMMMMMMMMMMMMMMMMupdateBits}{\saildoclabelled{sailRISCVoverloadMMMMMMMMMMMMMMMMMzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadMMMMMMMMMMMMMMMMMzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadNNNNNNNNNNNNNNNNNModBits}{\saildoclabelled{sailRISCVoverloadNNNNNNNNNNNNNNNNNzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadNNNNNNNNNNNNNNNNNz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSVFourEightPaddrPPNi}{\saildoclabelled{sailRISCVzzygetzySV48zyPaddrzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv48_paddr_ppni9c768f41f1a5703418c459280b46b7c6.tex}}}} + +\newcommand{\sailRISCVfnGetSVFourEightPaddrPPNi}{\saildoclabelled{sailRISCVfnzzygetzySV48zyPaddrzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv48_paddr_ppni9c768f41f1a5703418c459280b46b7c6.tex}}}} + +\newcommand{\sailRISCVvalSetSVFourEightPaddrPPNi}{\saildoclabelled{sailRISCVzzysetzySV48zyPaddrzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv48_paddr_ppni6d70c043fcdc253e5c9daadde935dc78.tex}}}} + +\newcommand{\sailRISCVfnSetSVFourEightPaddrPPNi}{\saildoclabelled{sailRISCVfnzzysetzySV48zyPaddrzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv48_paddr_ppni6d70c043fcdc253e5c9daadde935dc78.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVFourEightPaddrPPNi}{\saildoclabelled{sailRISCVzzyupdatezySV48zyPaddrzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv48_paddr_ppni3e4b50484e79dc7761373bc124441fd0.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVFourEightPaddrPPNi}{\saildoclabelled{sailRISCVfnzzyupdatezySV48zyPaddrzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv48_paddr_ppni3e4b50484e79dc7761373bc124441fd0.tex}}}} + +\newcommand{\sailRISCVoverloadOOOOOOOOOOOOOOOOOupdatePPNi}{\saildoclabelled{sailRISCVoverloadOOOOOOOOOOOOOOOOOzupdatezyPPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadOOOOOOOOOOOOOOOOOzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex}}}} + +\newcommand{\sailRISCVoverloadPPPPPPPPPPPPPPPPPModPPNi}{\saildoclabelled{sailRISCVoverloadPPPPPPPPPPPPPPPPPzzymodzyPPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadPPPPPPPPPPPPPPPPPz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex}}}} + +\newcommand{\sailRISCVvalGetSVFourEightPaddrPgOfs}{\saildoclabelled{sailRISCVzzygetzySV48zyPaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv48_paddr_pgofs7fbf559e6e9712930b86b30c8364e938.tex}}}} + +\newcommand{\sailRISCVfnGetSVFourEightPaddrPgOfs}{\saildoclabelled{sailRISCVfnzzygetzySV48zyPaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv48_paddr_pgofs7fbf559e6e9712930b86b30c8364e938.tex}}}} + +\newcommand{\sailRISCVvalSetSVFourEightPaddrPgOfs}{\saildoclabelled{sailRISCVzzysetzySV48zyPaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv48_paddr_pgofs562f79909d47d2b0eba8ebce320e03c4.tex}}}} + +\newcommand{\sailRISCVfnSetSVFourEightPaddrPgOfs}{\saildoclabelled{sailRISCVfnzzysetzySV48zyPaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv48_paddr_pgofs562f79909d47d2b0eba8ebce320e03c4.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVFourEightPaddrPgOfs}{\saildoclabelled{sailRISCVzzyupdatezySV48zyPaddrzyPgOfs}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv48_paddr_pgofsd71fa33c7b6f3543d0d9b5dc2d8380f5.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVFourEightPaddrPgOfs}{\saildoclabelled{sailRISCVfnzzyupdatezySV48zyPaddrzyPgOfs}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv48_paddr_pgofsd71fa33c7b6f3543d0d9b5dc2d8380f5.tex}}}} + +\newcommand{\sailRISCVoverloadQQQQQQQQQQQQQQQQQupdatePgOfs}{\saildoclabelled{sailRISCVoverloadQQQQQQQQQQQQQQQQQzupdatezyPgOfs}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadQQQQQQQQQQQQQQQQQzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex}}}} + +\newcommand{\sailRISCVoverloadRRRRRRRRRRRRRRRRRModPgOfs}{\saildoclabelled{sailRISCVoverloadRRRRRRRRRRRRRRRRRzzymodzyPgOfs}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadRRRRRRRRRRRRRRRRRz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex}}}} + +\newcommand{\sailRISCVtypeSVFourEightPTE}{\saildoclabelled{sailRISCVtypezSV48zyPTE}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezsv48_pte3a2f757f22affd3d18dd7c046956b713.tex}}}} + +\newcommand{\sailRISCVvalMkSVFourEightPTE}{\saildoclabelled{sailRISCVzMkzySV48zyPTE}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmk_sv48_pte98d38b79a0d0a08a23bc295e90c40a75.tex}}}} + +\newcommand{\sailRISCVfnMkSVFourEightPTE}{\saildoclabelled{sailRISCVfnzMkzySV48zyPTE}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmk_sv48_pte98d38b79a0d0a08a23bc295e90c40a75.tex}}}} + +\newcommand{\sailRISCVvalGetSVFourEightPTEBits}{\saildoclabelled{sailRISCVzzygetzySV48zyPTEzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv48_pte_bitsb58b3209e52ef5413579ee91bdf5b83d.tex}}}} + +\newcommand{\sailRISCVfnGetSVFourEightPTEBits}{\saildoclabelled{sailRISCVfnzzygetzySV48zyPTEzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv48_pte_bitsb58b3209e52ef5413579ee91bdf5b83d.tex}}}} + +\newcommand{\sailRISCVvalSetSVFourEightPTEBits}{\saildoclabelled{sailRISCVzzysetzySV48zyPTEzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv48_pte_bits0b444a773ec492c3163a73656822756d.tex}}}} + +\newcommand{\sailRISCVfnSetSVFourEightPTEBits}{\saildoclabelled{sailRISCVfnzzysetzySV48zyPTEzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv48_pte_bits0b444a773ec492c3163a73656822756d.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVFourEightPTEBits}{\saildoclabelled{sailRISCVzzyupdatezySV48zyPTEzybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv48_pte_bits0a6df26df13de159300f6127a4b286db.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVFourEightPTEBits}{\saildoclabelled{sailRISCVfnzzyupdatezySV48zyPTEzybits}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv48_pte_bits0a6df26df13de159300f6127a4b286db.tex}}}} + +\newcommand{\sailRISCVoverloadSSSSSSSSSSSSSSSSSupdateBits}{\saildoclabelled{sailRISCVoverloadSSSSSSSSSSSSSSSSSzupdatezybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadSSSSSSSSSSSSSSSSSzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex}}}} + +\newcommand{\sailRISCVoverloadTTTTTTTTTTTTTTTTTModBits}{\saildoclabelled{sailRISCVoverloadTTTTTTTTTTTTTTTTTzzymodzybits}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadTTTTTTTTTTTTTTTTTz_mod_bits34655d348b672c050c646beeecebb43d.tex}}}} + +\newcommand{\sailRISCVvalGetSVFourEightPTEExt}{\saildoclabelled{sailRISCVzzygetzySV48zyPTEzyExt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv48_pte_ext9e4ca3d27e7c17dad6458361686784bb.tex}}}} + +\newcommand{\sailRISCVfnGetSVFourEightPTEExt}{\saildoclabelled{sailRISCVfnzzygetzySV48zyPTEzyExt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv48_pte_ext9e4ca3d27e7c17dad6458361686784bb.tex}}}} + +\newcommand{\sailRISCVvalSetSVFourEightPTEExt}{\saildoclabelled{sailRISCVzzysetzySV48zyPTEzyExt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv48_pte_ext6ca7bfb443ac18c8ef730a785a66e223.tex}}}} + +\newcommand{\sailRISCVfnSetSVFourEightPTEExt}{\saildoclabelled{sailRISCVfnzzysetzySV48zyPTEzyExt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv48_pte_ext6ca7bfb443ac18c8ef730a785a66e223.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVFourEightPTEExt}{\saildoclabelled{sailRISCVzzyupdatezySV48zyPTEzyExt}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv48_pte_ext35aecfa61e536a6e82b25c27b17d2b27.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVFourEightPTEExt}{\saildoclabelled{sailRISCVfnzzyupdatezySV48zyPTEzyExt}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv48_pte_ext35aecfa61e536a6e82b25c27b17d2b27.tex}}}} + +\newcommand{\sailRISCVoverloadUUUUUUUUUUUUUUUUUupdateExt}{\saildoclabelled{sailRISCVoverloadUUUUUUUUUUUUUUUUUzupdatezyExt}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadUUUUUUUUUUUUUUUUUzupdate_ext4723b679799a58fbdda2ba5058faef53.tex}}}} + +\newcommand{\sailRISCVoverloadVVVVVVVVVVVVVVVVVModExt}{\saildoclabelled{sailRISCVoverloadVVVVVVVVVVVVVVVVVzzymodzyExt}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadVVVVVVVVVVVVVVVVVz_mod_extee31bbe7b534e72c2dacd0c25ba837ba.tex}}}} + +\newcommand{\sailRISCVvalGetSVFourEightPTEPPNi}{\saildoclabelled{sailRISCVzzygetzySV48zyPTEzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv48_pte_ppni308a2407b318a165e64cac46fe1d2d0b.tex}}}} + +\newcommand{\sailRISCVfnGetSVFourEightPTEPPNi}{\saildoclabelled{sailRISCVfnzzygetzySV48zyPTEzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv48_pte_ppni308a2407b318a165e64cac46fe1d2d0b.tex}}}} + +\newcommand{\sailRISCVvalSetSVFourEightPTEPPNi}{\saildoclabelled{sailRISCVzzysetzySV48zyPTEzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv48_pte_ppnif14b23da9aa27f230829cd1afd9a766b.tex}}}} + +\newcommand{\sailRISCVfnSetSVFourEightPTEPPNi}{\saildoclabelled{sailRISCVfnzzysetzySV48zyPTEzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv48_pte_ppnif14b23da9aa27f230829cd1afd9a766b.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVFourEightPTEPPNi}{\saildoclabelled{sailRISCVzzyupdatezySV48zyPTEzyPPNi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv48_pte_ppni151ef3d95182ce7f10853d377fa591b3.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVFourEightPTEPPNi}{\saildoclabelled{sailRISCVfnzzyupdatezySV48zyPTEzyPPNi}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv48_pte_ppni151ef3d95182ce7f10853d377fa591b3.tex}}}} + +\newcommand{\sailRISCVoverloadWWWWWWWWWWWWWWWWWupdatePPNi}{\saildoclabelled{sailRISCVoverloadWWWWWWWWWWWWWWWWWzupdatezyPPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadWWWWWWWWWWWWWWWWWzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex}}}} + +\newcommand{\sailRISCVoverloadXXXXXXXXXXXXXXXXXModPPNi}{\saildoclabelled{sailRISCVoverloadXXXXXXXXXXXXXXXXXzzymodzyPPNi}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadXXXXXXXXXXXXXXXXXz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex}}}} + +\newcommand{\sailRISCVvalGetSVFourEightPTERSW}{\saildoclabelled{sailRISCVzzygetzySV48zyPTEzyRSW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv48_pte_rsw44e860cbd993f79b4ea9ef51b7de8885.tex}}}} + +\newcommand{\sailRISCVfnGetSVFourEightPTERSW}{\saildoclabelled{sailRISCVfnzzygetzySV48zyPTEzyRSW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv48_pte_rsw44e860cbd993f79b4ea9ef51b7de8885.tex}}}} + +\newcommand{\sailRISCVvalSetSVFourEightPTERSW}{\saildoclabelled{sailRISCVzzysetzySV48zyPTEzyRSW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv48_pte_rswc91c2908d341bbe5216582c940bf7837.tex}}}} + +\newcommand{\sailRISCVfnSetSVFourEightPTERSW}{\saildoclabelled{sailRISCVfnzzysetzySV48zyPTEzyRSW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv48_pte_rswc91c2908d341bbe5216582c940bf7837.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVFourEightPTERSW}{\saildoclabelled{sailRISCVzzyupdatezySV48zyPTEzyRSW}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv48_pte_rsw6c601ebf0d644b711cbbe304a5538b5e.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVFourEightPTERSW}{\saildoclabelled{sailRISCVfnzzyupdatezySV48zyPTEzyRSW}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv48_pte_rsw6c601ebf0d644b711cbbe304a5538b5e.tex}}}} + +\newcommand{\sailRISCVoverloadYYYYYYYYYYYYYYYYYupdateRSW}{\saildoclabelled{sailRISCVoverloadYYYYYYYYYYYYYYYYYzupdatezyRSW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadYYYYYYYYYYYYYYYYYzupdate_rsw7e773e2fdd93d70f9490f8401b97d4e9.tex}}}} + +\newcommand{\sailRISCVoverloadZZZZZZZZZZZZZZZZZModRSW}{\saildoclabelled{sailRISCVoverloadZZZZZZZZZZZZZZZZZzzymodzyRSW}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadZZZZZZZZZZZZZZZZZz_mod_rswf4989a734cfde890cb5a1c8d3b4e6798.tex}}}} + +\newcommand{\sailRISCVvalGetSVFourEightPTEBITS}{\saildoclabelled{sailRISCVzzygetzySV48zyPTEzyBITS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_get_sv48_pte_bits3cedec2ea70a0849ea60d8d346d0f936.tex}}}} + +\newcommand{\sailRISCVfnGetSVFourEightPTEBITS}{\saildoclabelled{sailRISCVfnzzygetzySV48zyPTEzyBITS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_get_sv48_pte_bits3cedec2ea70a0849ea60d8d346d0f936.tex}}}} + +\newcommand{\sailRISCVvalSetSVFourEightPTEBITS}{\saildoclabelled{sailRISCVzzysetzySV48zyPTEzyBITS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_set_sv48_pte_bitsad0cc90eccc969a6500100c935bee630.tex}}}} + +\newcommand{\sailRISCVfnSetSVFourEightPTEBITS}{\saildoclabelled{sailRISCVfnzzysetzySV48zyPTEzyBITS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_set_sv48_pte_bitsad0cc90eccc969a6500100c935bee630.tex}}}} + +\newcommand{\sailRISCVvalUpdateSVFourEightPTEBITS}{\saildoclabelled{sailRISCVzzyupdatezySV48zyPTEzyBITS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valz_update_sv48_pte_bits5dd960679bb9cad63f93bb029f042c00.tex}}}} + +\newcommand{\sailRISCVfnUpdateSVFourEightPTEBITS}{\saildoclabelled{sailRISCVfnzzyupdatezySV48zyPTEzyBITS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnz_update_sv48_pte_bits5dd960679bb9cad63f93bb029f042c00.tex}}}} + +\newcommand{\sailRISCVoverloadAAAAAAAAAAAAAAAAAAupdateBITS}{\saildoclabelled{sailRISCVoverloadAAAAAAAAAAAAAAAAAAzupdatezyBITS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadAAAAAAAAAAAAAAAAAAzupdate_bits5a3f6688b4b8427544fc33354e84149f.tex}}}} + +\newcommand{\sailRISCVoverloadBBBBBBBBBBBBBBBBBBModBITS}{\saildoclabelled{sailRISCVoverloadBBBBBBBBBBBBBBBBBBzzymodzyBITS}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadBBBBBBBBBBBBBBBBBBz_mod_bits60455a5b4231baf7b82d860f6efc2682.tex}}}} + +\newcommand{\sailRISCVtypePTWResult}{\saildoclabelled{sailRISCVtypezPTWzyResult}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezptw_result387dae5ea1a379e54bc31c478988b63d.tex}}}} + +\newcommand{\sailRISCVtypeTRResult}{\saildoclabelled{sailRISCVtypezTRzyResult}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typeztr_result3a5e84bc36b624bd12e1a801e779c4c4.tex}}}} + +\newcommand{\sailRISCVtypeTLBEntry}{\saildoclabelled{sailRISCVtypezTLBzyEntry}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typeztlb_entryd6a3e312d7372e7db4df8f6c3707b5fa.tex}}}} + +\newcommand{\sailRISCVvalmakeTLBEntry}{\saildoclabelled{sailRISCVzmakezyTLBzyEntry}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmake_tlb_entry6b22aedb2f264f70f3e1bd2d5dd6f057.tex}}}} + +\newcommand{\sailRISCVfnmakeTLBEntry}{\saildoclabelled{sailRISCVfnzmakezyTLBzyEntry}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmake_tlb_entry6b22aedb2f264f70f3e1bd2d5dd6f057.tex}}}} + +\newcommand{\sailRISCVvalmatchTLBEntry}{\saildoclabelled{sailRISCVzmatchzyTLBzyEntry}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmatch_tlb_entry15cb314356c461bfc7d1b30f45fecb98.tex}}}} + +\newcommand{\sailRISCVfnmatchTLBEntry}{\saildoclabelled{sailRISCVfnzmatchzyTLBzyEntry}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzmatch_tlb_entry15cb314356c461bfc7d1b30f45fecb98.tex}}}} + +\newcommand{\sailRISCVvalflushTLBEntry}{\saildoclabelled{sailRISCVzflushzyTLBzyEntry}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzflush_tlb_entry8073b262f27cbbda50ac10a3cc21c463.tex}}}} + +\newcommand{\sailRISCVfnflushTLBEntry}{\saildoclabelled{sailRISCVfnzflushzyTLBzyEntry}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzflush_tlb_entry8073b262f27cbbda50ac10a3cc21c463.tex}}}} + +\newcommand{\sailRISCVvalwalkThreeNine}{\saildoclabelled{sailRISCVzwalk39}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwalk398233e1f75321f48773213830a045bfac.tex}}}} + +\newcommand{\sailRISCVfnwalkThreeNine}{\saildoclabelled{sailRISCVfnzwalk39}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwalk398233e1f75321f48773213830a045bfac.tex}}}} + +\newcommand{\sailRISCVtypeTLBThreeNineEntry}{\saildoclabelled{sailRISCVtypezTLB39zyEntry}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typeztlb39_entrya6d01947ae0af49073403c37a147bc7a.tex}}}} + +\newcommand{\sailRISCVvallookupTLBThreeNine}{\saildoclabelled{sailRISCVzlookupzyTLB39}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlookup_tlb39701cebd3fa43ee6815ecaa975a199f5b.tex}}}} + +\newcommand{\sailRISCVfnlookupTLBThreeNine}{\saildoclabelled{sailRISCVfnzlookupzyTLB39}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlookup_tlb39701cebd3fa43ee6815ecaa975a199f5b.tex}}}} + +\newcommand{\sailRISCVvaladdToTLBThreeNine}{\saildoclabelled{sailRISCVzaddzytozyTLB39}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzadd_to_tlb39f45d8d071e2986dede49d7c2109cd4f5.tex}}}} + +\newcommand{\sailRISCVfnaddToTLBThreeNine}{\saildoclabelled{sailRISCVfnzaddzytozyTLB39}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzadd_to_tlb39f45d8d071e2986dede49d7c2109cd4f5.tex}}}} + +\newcommand{\sailRISCVvalwriteTLBThreeNine}{\saildoclabelled{sailRISCVzwritezyTLB39}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwrite_tlb39d07866694d7288e6a3cb2ac08a58c288.tex}}}} + +\newcommand{\sailRISCVfnwriteTLBThreeNine}{\saildoclabelled{sailRISCVfnzwritezyTLB39}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwrite_tlb39d07866694d7288e6a3cb2ac08a58c288.tex}}}} + +\newcommand{\sailRISCVvalflushTLBThreeNine}{\saildoclabelled{sailRISCVzflushzyTLB39}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzflush_tlb39155d346596461ed0e3ab611745b6738a.tex}}}} + +\newcommand{\sailRISCVfnflushTLBThreeNine}{\saildoclabelled{sailRISCVfnzflushzyTLB39}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzflush_tlb39155d346596461ed0e3ab611745b6738a.tex}}}} + +\newcommand{\sailRISCVvaltranslateThreeNine}{\saildoclabelled{sailRISCVztranslate39}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztranslate39daa42428c4ec23bd5def028158b476c6.tex}}}} + +\newcommand{\sailRISCVfntranslateThreeNine}{\saildoclabelled{sailRISCVfnztranslate39}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztranslate39daa42428c4ec23bd5def028158b476c6.tex}}}} + +\newcommand{\sailRISCVvalinitVmemSvThreeNine}{\saildoclabelled{sailRISCVzinitzyvmemzysv39}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinit_vmem_sv390a83d23f548fedfc48c542ac764df587.tex}}}} + +\newcommand{\sailRISCVfninitVmemSvThreeNine}{\saildoclabelled{sailRISCVfnzinitzyvmemzysv39}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinit_vmem_sv390a83d23f548fedfc48c542ac764df587.tex}}}} + +\newcommand{\sailRISCVvalwalkFourEight}{\saildoclabelled{sailRISCVzwalk48}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwalk486c4033235ca01e713873e89320a939ac.tex}}}} + +\newcommand{\sailRISCVfnwalkFourEight}{\saildoclabelled{sailRISCVfnzwalk48}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwalk486c4033235ca01e713873e89320a939ac.tex}}}} + +\newcommand{\sailRISCVtypeTLBFourEightEntry}{\saildoclabelled{sailRISCVtypezTLB48zyEntry}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typeztlb48_entry26abc9d10a3e265edd1da0902c832cee.tex}}}} + +\newcommand{\sailRISCVvallookupTLBFourEight}{\saildoclabelled{sailRISCVzlookupzyTLB48}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlookup_tlb481be2085cbc29568c5c522b87bd854b70.tex}}}} + +\newcommand{\sailRISCVfnlookupTLBFourEight}{\saildoclabelled{sailRISCVfnzlookupzyTLB48}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlookup_tlb481be2085cbc29568c5c522b87bd854b70.tex}}}} + +\newcommand{\sailRISCVvaladdToTLBFourEight}{\saildoclabelled{sailRISCVzaddzytozyTLB48}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzadd_to_tlb48a08cb99b91f9c80121525cc743b92593.tex}}}} + +\newcommand{\sailRISCVfnaddToTLBFourEight}{\saildoclabelled{sailRISCVfnzaddzytozyTLB48}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzadd_to_tlb48a08cb99b91f9c80121525cc743b92593.tex}}}} + +\newcommand{\sailRISCVvalwriteTLBFourEight}{\saildoclabelled{sailRISCVzwritezyTLB48}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwrite_tlb48c2deeba6fb9156609619ba23dcc84e5a.tex}}}} + +\newcommand{\sailRISCVfnwriteTLBFourEight}{\saildoclabelled{sailRISCVfnzwritezyTLB48}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwrite_tlb48c2deeba6fb9156609619ba23dcc84e5a.tex}}}} + +\newcommand{\sailRISCVvalflushTLBFourEight}{\saildoclabelled{sailRISCVzflushzyTLB48}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzflush_tlb482377e6a21b0e61c1f15d8ef64c6ac044.tex}}}} + +\newcommand{\sailRISCVfnflushTLBFourEight}{\saildoclabelled{sailRISCVfnzflushzyTLB48}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzflush_tlb482377e6a21b0e61c1f15d8ef64c6ac044.tex}}}} + +\newcommand{\sailRISCVvaltranslateFourEight}{\saildoclabelled{sailRISCVztranslate48}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztranslate488637bc30f662c37b22a80c3d053c14e5.tex}}}} + +\newcommand{\sailRISCVfntranslateFourEight}{\saildoclabelled{sailRISCVfnztranslate48}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztranslate488637bc30f662c37b22a80c3d053c14e5.tex}}}} + +\newcommand{\sailRISCVvalinitVmemSvFourEight}{\saildoclabelled{sailRISCVzinitzyvmemzysv48}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinit_vmem_sv487afaa3d38e7e9ff21a6cbfad52504311.tex}}}} + +\newcommand{\sailRISCVfninitVmemSvFourEight}{\saildoclabelled{sailRISCVfnzinitzyvmemzysv48}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinit_vmem_sv487afaa3d38e7e9ff21a6cbfad52504311.tex}}}} + +\newcommand{\sailRISCVvallegalizzeSatp}{\saildoclabelled{sailRISCVzlegalizzezysatp}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlegalizze_satp1fbfb541ef401311caafca983cb812d6.tex}}}} + +\newcommand{\sailRISCVfnlegalizzeSatp}{\saildoclabelled{sailRISCVfnzlegalizzezysatp}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlegalizze_satp1fbfb541ef401311caafca983cb812d6.tex}}}} + +\newcommand{\sailRISCVvalisValidSvThreeNineAddr}{\saildoclabelled{sailRISCVzisValidSv39Addr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzisvalidsv39addr6225e53e2f01610f83ab9bea1f3201bf.tex}}}} + +\newcommand{\sailRISCVfnisValidSvThreeNineAddr}{\saildoclabelled{sailRISCVfnzisValidSv39Addr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzisvalidsv39addr6225e53e2f01610f83ab9bea1f3201bf.tex}}}} + +\newcommand{\sailRISCVvalisValidSvFourEightAddr}{\saildoclabelled{sailRISCVzisValidSv48Addr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzisvalidsv48addr5c09db742963fd3c2cd1457f6411e837.tex}}}} + +\newcommand{\sailRISCVfnisValidSvFourEightAddr}{\saildoclabelled{sailRISCVfnzisValidSv48Addr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzisvalidsv48addr5c09db742963fd3c2cd1457f6411e837.tex}}}} + +\newcommand{\sailRISCVvaltranslationMode}{\saildoclabelled{sailRISCVztranslationMode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztranslationmode51f0fd652f39ec2f6d4c16847f0d4345.tex}}}} + +\newcommand{\sailRISCVfntranslationMode}{\saildoclabelled{sailRISCVfnztranslationMode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztranslationmode51f0fd652f39ec2f6d4c16847f0d4345.tex}}}} + +\newcommand{\sailRISCVvaltranslateAddr}{\saildoclabelled{sailRISCVztranslateAddr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valztranslateaddr7dc6bd4ea43d006224000f7b68f6a187.tex}}}} + +\newcommand{\sailRISCVfntranslateAddr}{\saildoclabelled{sailRISCVfnztranslateAddr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnztranslateaddr7dc6bd4ea43d006224000f7b68f6a187.tex}}}} + +\newcommand{\sailRISCVvalflushTLB}{\saildoclabelled{sailRISCVzflushzyTLB}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzflush_tlbf2c831dee428b5971141e383ef962e36.tex}}}} + +\newcommand{\sailRISCVfnflushTLB}{\saildoclabelled{sailRISCVfnzflushzyTLB}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzflush_tlbf2c831dee428b5971141e383ef962e36.tex}}}} + +\newcommand{\sailRISCVvalinitVmem}{\saildoclabelled{sailRISCVzinitzyvmem}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinit_vmem811d98ebf1d4d536d0e4070a3b67fe03.tex}}}} + +\newcommand{\sailRISCVfninitVmem}{\saildoclabelled{sailRISCVfnzinitzyvmem}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinit_vmem811d98ebf1d4d536d0e4070a3b67fe03.tex}}}} + +\newcommand{\sailRISCVtypeast}{\saildoclabelled{sailRISCVtypezast}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezast6bb070d12e82e4887160cdfd016230c8.tex}}}} + +\newcommand{\sailRISCVvalexecute}{\saildoclabelled{sailRISCVzexecute}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVvalassembly}{\saildoclabelled{sailRISCVzassembly}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzassembly6c256353098ca1294b0a3873338d670c.tex}}}} + +\newcommand{\sailRISCVvalencdec}{\saildoclabelled{sailRISCVzencdec}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzencdeca7ceb0009f9b533ad47d2b69e8881c04.tex}}}} + +\newcommand{\sailRISCVvalencdecCompressed}{\saildoclabelled{sailRISCVzencdeczycompressed}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzencdec_compressed480f14a33b2969971592c7ca63bcfde9.tex}}}} + +\newcommand{\sailRISCVvalencdecUop}{\saildoclabelled{sailRISCVzencdeczyuop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzencdec_uop0feeafb72397448d1e686117bd04bd8d.tex}}}} + +\newcommand{\sailRISCVvalutypeMnemonic}{\saildoclabelled{sailRISCVzutypezymnemonic}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzutype_mnemonic5740211feaadc8d830fd698383ea27eb.tex}}}} + +\newcommand{\sailRISCVvalencdecBop}{\saildoclabelled{sailRISCVzencdeczybop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzencdec_bop37935afdc8fb9d403964a671d7b8ef6f.tex}}}} + +\newcommand{\sailRISCVvalbtypeMnemonic}{\saildoclabelled{sailRISCVzbtypezymnemonic}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbtype_mnemonicee542cf061481e1e2c0e4ec1302a928b.tex}}}} + +\newcommand{\sailRISCVvalencdecIop}{\saildoclabelled{sailRISCVzencdeczyiop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzencdec_iopdc6254ab3f3dfdad4df376ed9499c048.tex}}}} + +\newcommand{\sailRISCVvalitypeMnemonic}{\saildoclabelled{sailRISCVzitypezymnemonic}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzitype_mnemonicb2266da97e58b5824550ef451a0000db.tex}}}} + +\newcommand{\sailRISCVvalencdecSop}{\saildoclabelled{sailRISCVzencdeczysop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzencdec_sop073a7abc17ca60aa3455773907eb78c7.tex}}}} + +\newcommand{\sailRISCVvalshiftiopMnemonic}{\saildoclabelled{sailRISCVzshiftiopzymnemonic}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzshiftiop_mnemonicbeafdfe24bd90ed73f232559498ac819.tex}}}} + +\newcommand{\sailRISCVvalrtypeMnemonic}{\saildoclabelled{sailRISCVzrtypezymnemonic}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrtype_mnemonic539b9ad883876e5c6be9237e5c98ffbb.tex}}}} + +\newcommand{\sailRISCVvalextendValue}{\saildoclabelled{sailRISCVzextendzyvalue}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzextend_value8ddb26f3f92f6848beaff0fbcaa992f6.tex}}}} + +\newcommand{\sailRISCVfnextendValue}{\saildoclabelled{sailRISCVfnzextendzyvalue}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzextend_value8ddb26f3f92f6848beaff0fbcaa992f6.tex}}}} + +\newcommand{\sailRISCVvalprocessLoad}{\saildoclabelled{sailRISCVzprocesszyload}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprocess_load7d9288eb90dd41d1aa3c47eda679c483.tex}}}} + +\newcommand{\sailRISCVfnprocessLoad}{\saildoclabelled{sailRISCVfnzprocesszyload}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprocess_load7d9288eb90dd41d1aa3c47eda679c483.tex}}}} + +\newcommand{\sailRISCVvalcheckMisaligned}{\saildoclabelled{sailRISCVzcheckzymisaligned}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcheck_misaligned6730e75ccee79325a38a992b6314fd91.tex}}}} + +\newcommand{\sailRISCVfncheckMisaligned}{\saildoclabelled{sailRISCVfnzcheckzymisaligned}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcheck_misaligned6730e75ccee79325a38a992b6314fd91.tex}}}} + +\newcommand{\sailRISCVvalmaybeAq}{\saildoclabelled{sailRISCVzmaybezyaq}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmaybe_aq7807a00a0c8e402132f155781a4acc6b.tex}}}} + +\newcommand{\sailRISCVvalmaybeRl}{\saildoclabelled{sailRISCVzmaybezyrl}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmaybe_rl471fbde2d5b588b1be3bdbcbad1b5b40.tex}}}} + +\newcommand{\sailRISCVvalmaybeU}{\saildoclabelled{sailRISCVzmaybezyu}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmaybe_u271e5e54fd4c9b9e611d3ad0e98a3503.tex}}}} + +\newcommand{\sailRISCVvalshiftwMnemonic}{\saildoclabelled{sailRISCVzshiftwzymnemonic}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzshiftw_mnemonice823d8fe4e9165665d0ca244aa353baa.tex}}}} + +\newcommand{\sailRISCVvalrtypewMnemonic}{\saildoclabelled{sailRISCVzrtypewzymnemonic}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzrtypew_mnemonic72f42d5e018398fdfceb25edf2e10caf.tex}}}} + +\newcommand{\sailRISCVvalshiftiwopMnemonic}{\saildoclabelled{sailRISCVzshiftiwopzymnemonic}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzshiftiwop_mnemonic59f60b5dc1f36ebc6fe3d32d9df1d608.tex}}}} + +\newcommand{\sailRISCVvalbitMaybeR}{\saildoclabelled{sailRISCVzbitzymaybezyr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbit_maybe_r1c52279a1272ff324e99d5b1b65881cd.tex}}}} + +\newcommand{\sailRISCVvalbitMaybeW}{\saildoclabelled{sailRISCVzbitzymaybezyw}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbit_maybe_w6d81c7531ae5006f39930eecd7114080.tex}}}} + +\newcommand{\sailRISCVvalbitMaybeI}{\saildoclabelled{sailRISCVzbitzymaybezyi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbit_maybe_iea1ce4e78632791b6873db323516744a.tex}}}} + +\newcommand{\sailRISCVvalbitMaybeO}{\saildoclabelled{sailRISCVzbitzymaybezyo}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzbit_maybe_oa643ed77970ec3375ca02eb2a3d6d7e3.tex}}}} + +\newcommand{\sailRISCVvalfenceBits}{\saildoclabelled{sailRISCVzfencezybits}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfence_bits39f0871d2c2e4d36bb4622567377397d.tex}}}} + +\newcommand{\sailRISCVvalaqrlStr}{\saildoclabelled{sailRISCVzaqrlzystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzaqrl_str43f7a950ecb4ae033c3d54ba744ac285.tex}}}} + +\newcommand{\sailRISCVfnaqrlStr}{\saildoclabelled{sailRISCVfnzaqrlzystr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzaqrl_str43f7a950ecb4ae033c3d54ba744ac285.tex}}}} + +\newcommand{\sailRISCVvallrscWidthStr}{\saildoclabelled{sailRISCVzlrsczywidthzystr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzlrsc_width_str1a32b7e5b18a83477d13203cd0eca601.tex}}}} + +\newcommand{\sailRISCVfnlrscWidthStr}{\saildoclabelled{sailRISCVfnzlrsczywidthzystr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzlrsc_width_str1a32b7e5b18a83477d13203cd0eca601.tex}}}} + +\newcommand{\sailRISCVvalprocessLoadres}{\saildoclabelled{sailRISCVzprocesszyloadres}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprocess_loadres3acadfd67bd540642036cf41405a27c0.tex}}}} + +\newcommand{\sailRISCVfnprocessLoadres}{\saildoclabelled{sailRISCVfnzprocesszyloadres}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprocess_loadres3acadfd67bd540642036cf41405a27c0.tex}}}} + +\newcommand{\sailRISCVvalencdecAmoop}{\saildoclabelled{sailRISCVzencdeczyamoop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzencdec_amoopad56ea38f11b2d2533d3cea1e6e89079.tex}}}} + +\newcommand{\sailRISCVvalamoMnemonic}{\saildoclabelled{sailRISCVzamozymnemonic}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzamo_mnemonicac3b9dc5cf93b937e8a5514efa62f568.tex}}}} + +\newcommand{\sailRISCVvalencdecMulOp}{\saildoclabelled{sailRISCVzencdeczymulzyop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzencdec_mul_op4fddc1c61135e80f6618dd3c6fca770c.tex}}}} + +\newcommand{\sailRISCVvalmulMnemonic}{\saildoclabelled{sailRISCVzmulzymnemonic}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmul_mnemonic8e8a5c0cf101d49d6656287f35956c53.tex}}}} + +\newcommand{\sailRISCVvalmaybeNotU}{\saildoclabelled{sailRISCVzmaybezynotzyu}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmaybe_not_ud1aa0681e785549479247e44134e0663.tex}}}} + +\newcommand{\sailRISCVvalencdecCsrop}{\saildoclabelled{sailRISCVzencdeczycsrop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzencdec_csrop402749395fac229088b2e6f6e6206c72.tex}}}} + +\newcommand{\sailRISCVvalreadCSR}{\saildoclabelled{sailRISCVzreadCSR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzreadcsr1a9ed1f2dac4690038fbe34a4617edca.tex}}}} + +\newcommand{\sailRISCVfnreadCSR}{\saildoclabelled{sailRISCVfnzreadCSR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzreadcsr1a9ed1f2dac4690038fbe34a4617edca.tex}}}} + +\newcommand{\sailRISCVvalwriteCSR}{\saildoclabelled{sailRISCVzwriteCSR}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzwritecsr7af48520171f4dd0cd06c1b6876196a7.tex}}}} + +\newcommand{\sailRISCVfnwriteCSR}{\saildoclabelled{sailRISCVfnzwriteCSR}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzwritecsr7af48520171f4dd0cd06c1b6876196a7.tex}}}} + +\newcommand{\sailRISCVvalmaybeI}{\saildoclabelled{sailRISCVzmaybezyi}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzmaybe_i65644ebcc11e5b25fca853fb9aeea917.tex}}}} + +\newcommand{\sailRISCVvalcsrMnemonic}{\saildoclabelled{sailRISCVzcsrzymnemonic}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcsr_mnemonic3a1dd26f3ac0095deadcf2bffb0adbc8.tex}}}} + +\newcommand{\sailRISCVvalencdecRoundingMode}{\saildoclabelled{sailRISCVzencdeczyroundingzymode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzencdec_rounding_mode4e9de2b381b2971c0047c4587dc1aeff.tex}}}} + +\newcommand{\sailRISCVvalfrmMnemonic}{\saildoclabelled{sailRISCVzfrmzymnemonic}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfrm_mnemonic1efa3419adbb7f3793e39728661edbd6.tex}}}} + +\newcommand{\sailRISCVvalselectInstrOrFcsrRm}{\saildoclabelled{sailRISCVzselectzyinstrzyorzyfcsrzyrm}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzselect_instr_or_fcsr_rm8a489b01095486a7dc41b6fb5b17b9a7.tex}}}} + +\newcommand{\sailRISCVfnselectInstrOrFcsrRm}{\saildoclabelled{sailRISCVfnzselectzyinstrzyorzyfcsrzyrm}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzselect_instr_or_fcsr_rm8a489b01095486a7dc41b6fb5b17b9a7.tex}}}} + +\newcommand{\sailRISCVvalnxFlag}{\saildoclabelled{sailRISCVznxFlag}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznxflaga9ef0edc4edc03b79abaa230aaad20a6.tex}}}} + +\newcommand{\sailRISCVfnnxFlag}{\saildoclabelled{sailRISCVfnznxFlag}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznxflaga9ef0edc4edc03b79abaa230aaad20a6.tex}}}} + +\newcommand{\sailRISCVvalufFlag}{\saildoclabelled{sailRISCVzufFlag}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzufflagb3d552180ae10d9ed1b23a8e10ad2e9c.tex}}}} + +\newcommand{\sailRISCVfnufFlag}{\saildoclabelled{sailRISCVfnzufFlag}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzufflagb3d552180ae10d9ed1b23a8e10ad2e9c.tex}}}} + +\newcommand{\sailRISCVvalofFlag}{\saildoclabelled{sailRISCVzofFlag}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzofflag1be1156688e569fa940a9118708be17d.tex}}}} + +\newcommand{\sailRISCVfnofFlag}{\saildoclabelled{sailRISCVfnzofFlag}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzofflag1be1156688e569fa940a9118708be17d.tex}}}} + +\newcommand{\sailRISCVvaldzzFlag}{\saildoclabelled{sailRISCVzdzzFlag}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzdzzflagcea95ae2581be09607c095ea1558f21b.tex}}}} + +\newcommand{\sailRISCVfndzzFlag}{\saildoclabelled{sailRISCVfnzdzzFlag}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzdzzflagcea95ae2581be09607c095ea1558f21b.tex}}}} + +\newcommand{\sailRISCVvalnvFlag}{\saildoclabelled{sailRISCVznvFlag}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznvflag96f5e3b2efdbb80ea87eb99f361ac158.tex}}}} + +\newcommand{\sailRISCVfnnvFlag}{\saildoclabelled{sailRISCVfnznvFlag}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznvflag96f5e3b2efdbb80ea87eb99f361ac158.tex}}}} + +\newcommand{\sailRISCVvalfsplitS}{\saildoclabelled{sailRISCVzfsplitzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfsplit_s587b8f3a581d4f6ab15969163c75b5ff.tex}}}} + +\newcommand{\sailRISCVfnfsplitS}{\saildoclabelled{sailRISCVfnzfsplitzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfsplit_s587b8f3a581d4f6ab15969163c75b5ff.tex}}}} + +\newcommand{\sailRISCVvalfmakeS}{\saildoclabelled{sailRISCVzfmakezyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfmake_sf09ffe3c3e52a17eb1e248d73c150f66.tex}}}} + +\newcommand{\sailRISCVfnfmakeS}{\saildoclabelled{sailRISCVfnzfmakezyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfmake_sf09ffe3c3e52a17eb1e248d73c150f66.tex}}}} + +\newcommand{\sailRISCVvalcanonicalNaNS}{\saildoclabelled{sailRISCVzcanonicalzyNaNzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcanonical_nan_s21045df28a8988e296d9749590d92369.tex}}}} + +\newcommand{\sailRISCVfncanonicalNaNS}{\saildoclabelled{sailRISCVfnzcanonicalzyNaNzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcanonical_nan_s21045df28a8988e296d9749590d92369.tex}}}} + +\newcommand{\sailRISCVvalfIsNegInfS}{\saildoclabelled{sailRISCVzfzyiszynegzyinfzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_neg_inf_sf1e927a0ea24a891ce2c85c8d22d9613.tex}}}} + +\newcommand{\sailRISCVfnfIsNegInfS}{\saildoclabelled{sailRISCVfnzfzyiszynegzyinfzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_neg_inf_sf1e927a0ea24a891ce2c85c8d22d9613.tex}}}} + +\newcommand{\sailRISCVvalfIsNegNormS}{\saildoclabelled{sailRISCVzfzyiszynegzynormzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_neg_norm_s8bfccfb981e547ad5f5c42e4a17c2a1f.tex}}}} + +\newcommand{\sailRISCVfnfIsNegNormS}{\saildoclabelled{sailRISCVfnzfzyiszynegzynormzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_neg_norm_s8bfccfb981e547ad5f5c42e4a17c2a1f.tex}}}} + +\newcommand{\sailRISCVvalfIsNegSubnormS}{\saildoclabelled{sailRISCVzfzyiszynegzysubnormzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_neg_subnorm_sd8c8d47f6284f9e99142031238418d6e.tex}}}} + +\newcommand{\sailRISCVfnfIsNegSubnormS}{\saildoclabelled{sailRISCVfnzfzyiszynegzysubnormzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_neg_subnorm_sd8c8d47f6284f9e99142031238418d6e.tex}}}} + +\newcommand{\sailRISCVvalfIsNegZeroS}{\saildoclabelled{sailRISCVzfzyiszynegzyzzerozyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_neg_zzero_s01b2d7b1def55db2428888908b29c669.tex}}}} + +\newcommand{\sailRISCVfnfIsNegZeroS}{\saildoclabelled{sailRISCVfnzfzyiszynegzyzzerozyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_neg_zzero_s01b2d7b1def55db2428888908b29c669.tex}}}} + +\newcommand{\sailRISCVvalfIsPosZeroS}{\saildoclabelled{sailRISCVzfzyiszyposzyzzerozyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_pos_zzero_s92eacf7245b38cd8fbe2b7411cc24794.tex}}}} + +\newcommand{\sailRISCVfnfIsPosZeroS}{\saildoclabelled{sailRISCVfnzfzyiszyposzyzzerozyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_pos_zzero_s92eacf7245b38cd8fbe2b7411cc24794.tex}}}} + +\newcommand{\sailRISCVvalfIsPosSubnormS}{\saildoclabelled{sailRISCVzfzyiszyposzysubnormzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_pos_subnorm_s4efdacb98629e85ea864b456e8377a98.tex}}}} + +\newcommand{\sailRISCVfnfIsPosSubnormS}{\saildoclabelled{sailRISCVfnzfzyiszyposzysubnormzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_pos_subnorm_s4efdacb98629e85ea864b456e8377a98.tex}}}} + +\newcommand{\sailRISCVvalfIsPosNormS}{\saildoclabelled{sailRISCVzfzyiszyposzynormzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_pos_norm_s19872015fda671aa1dca05b90a2680c4.tex}}}} + +\newcommand{\sailRISCVfnfIsPosNormS}{\saildoclabelled{sailRISCVfnzfzyiszyposzynormzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_pos_norm_s19872015fda671aa1dca05b90a2680c4.tex}}}} + +\newcommand{\sailRISCVvalfIsPosInfS}{\saildoclabelled{sailRISCVzfzyiszyposzyinfzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_pos_inf_sf714fc249168edfd360262aca5e55c4d.tex}}}} + +\newcommand{\sailRISCVfnfIsPosInfS}{\saildoclabelled{sailRISCVfnzfzyiszyposzyinfzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_pos_inf_sf714fc249168edfd360262aca5e55c4d.tex}}}} + +\newcommand{\sailRISCVvalfIsSNaNS}{\saildoclabelled{sailRISCVzfzyiszySNaNzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_snan_s4f74c8b27b066b5e2d6856d63c0d8113.tex}}}} + +\newcommand{\sailRISCVfnfIsSNaNS}{\saildoclabelled{sailRISCVfnzfzyiszySNaNzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_snan_s4f74c8b27b066b5e2d6856d63c0d8113.tex}}}} + +\newcommand{\sailRISCVvalfIsQNaNS}{\saildoclabelled{sailRISCVzfzyiszyQNaNzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_qnan_s36343ea7477dd88c6d9f512ad8587fd3.tex}}}} + +\newcommand{\sailRISCVfnfIsQNaNS}{\saildoclabelled{sailRISCVfnzfzyiszyQNaNzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_qnan_s36343ea7477dd88c6d9f512ad8587fd3.tex}}}} + +\newcommand{\sailRISCVvalfIsNaNS}{\saildoclabelled{sailRISCVzfzyiszyNaNzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_nan_s0d165c8ab9495379c496e3667f21236f.tex}}}} + +\newcommand{\sailRISCVfnfIsNaNS}{\saildoclabelled{sailRISCVfnzfzyiszyNaNzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_nan_s0d165c8ab9495379c496e3667f21236f.tex}}}} + +\newcommand{\sailRISCVvalnegateS}{\saildoclabelled{sailRISCVznegatezyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznegate_s602acdc6547e76adb79aa6072014fa3e.tex}}}} + +\newcommand{\sailRISCVfnnegateS}{\saildoclabelled{sailRISCVfnznegatezyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznegate_s602acdc6547e76adb79aa6072014fa3e.tex}}}} + +\newcommand{\sailRISCVvalfeqQuietS}{\saildoclabelled{sailRISCVzfeqzyquietzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfeq_quiet_saed522b017dd40dd277d80aee28e4fe9.tex}}}} + +\newcommand{\sailRISCVfnfeqQuietS}{\saildoclabelled{sailRISCVfnzfeqzyquietzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfeq_quiet_saed522b017dd40dd277d80aee28e4fe9.tex}}}} + +\newcommand{\sailRISCVvalfltS}{\saildoclabelled{sailRISCVzfltzyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzflt_sb42cf5853deeee1a9c0ed2ff1e36a52b.tex}}}} + +\newcommand{\sailRISCVfnfltS}{\saildoclabelled{sailRISCVfnzfltzyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzflt_sb42cf5853deeee1a9c0ed2ff1e36a52b.tex}}}} + +\newcommand{\sailRISCVvalfleS}{\saildoclabelled{sailRISCVzflezyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfle_s93e035a8ca13e7d64b965c7c750ae56d.tex}}}} + +\newcommand{\sailRISCVfnfleS}{\saildoclabelled{sailRISCVfnzflezyS}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfle_s93e035a8ca13e7d64b965c7c750ae56d.tex}}}} + +\newcommand{\sailRISCVvalnanBox}{\saildoclabelled{sailRISCVznanzybox}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex}}}} + +\newcommand{\sailRISCVfnnanBox}{\saildoclabelled{sailRISCVfnznanzybox}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex}}}} + +\newcommand{\sailRISCVvalnanUnbox}{\saildoclabelled{sailRISCVznanzyunbox}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznan_unbox6971c840905d637f635a4793907fe38e.tex}}}} + +\newcommand{\sailRISCVfnnanUnbox}{\saildoclabelled{sailRISCVfnznanzyunbox}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznan_unbox6971c840905d637f635a4793907fe38e.tex}}}} + +\newcommand{\sailRISCVvalisRVThreeTwoFOrRVSixFourF}{\saildoclabelled{sailRISCVziszyRV32FzyorzyRV64F}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzis_rv32f_or_rv64f0479eeacd8ff6d333014b8d2bd493bf0.tex}}}} + +\newcommand{\sailRISCVfnisRVThreeTwoFOrRVSixFourF}{\saildoclabelled{sailRISCVfnziszyRV32FzyorzyRV64F}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzis_rv32f_or_rv64f0479eeacd8ff6d333014b8d2bd493bf0.tex}}}} + +\newcommand{\sailRISCVvalisRVSixFourF}{\saildoclabelled{sailRISCVziszyRV64F}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzis_rv64f294d3f4a32a15e369d15c34498a07034.tex}}}} + +\newcommand{\sailRISCVfnisRVSixFourF}{\saildoclabelled{sailRISCVfnziszyRV64F}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzis_rv64f294d3f4a32a15e369d15c34498a07034.tex}}}} + +\newcommand{\sailRISCVvalisRVThreeTwoDOrRVSixFourD}{\saildoclabelled{sailRISCVziszyRV32DzyorzyRV64D}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzis_rv32d_or_rv64d3518fa18b37b3eaa9c4945d112044e98.tex}}}} + +\newcommand{\sailRISCVfnisRVThreeTwoDOrRVSixFourD}{\saildoclabelled{sailRISCVfnziszyRV32DzyorzyRV64D}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzis_rv32d_or_rv64d3518fa18b37b3eaa9c4945d112044e98.tex}}}} + +\newcommand{\sailRISCVvalisRVSixFourD}{\saildoclabelled{sailRISCVziszyRV64D}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzis_rv64d2ec4297accd40afbaf8305bfa55a08ef.tex}}}} + +\newcommand{\sailRISCVfnisRVSixFourD}{\saildoclabelled{sailRISCVfnziszyRV64D}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzis_rv64d2ec4297accd40afbaf8305bfa55a08ef.tex}}}} + +\newcommand{\sailRISCVvalprocessFloadSixFour}{\saildoclabelled{sailRISCVzprocesszyfload64}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprocess_fload64aaf81fa4052296eb2993198993f6472c.tex}}}} + +\newcommand{\sailRISCVfnprocessFloadSixFour}{\saildoclabelled{sailRISCVfnzprocesszyfload64}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprocess_fload64aaf81fa4052296eb2993198993f6472c.tex}}}} + +\newcommand{\sailRISCVvalprocessFloadThreeTwo}{\saildoclabelled{sailRISCVzprocesszyfload32}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprocess_fload322b1b2657ee5e1571b2af7b0d3a6631b7.tex}}}} + +\newcommand{\sailRISCVfnprocessFloadThreeTwo}{\saildoclabelled{sailRISCVfnzprocesszyfload32}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprocess_fload322b1b2657ee5e1571b2af7b0d3a6631b7.tex}}}} + +\newcommand{\sailRISCVvalprocessFstore}{\saildoclabelled{sailRISCVzprocesszyfstore}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprocess_fstoree9440c013cfdcc23312bc61d5762f1d1.tex}}}} + +\newcommand{\sailRISCVfnprocessFstore}{\saildoclabelled{sailRISCVfnzprocesszyfstore}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprocess_fstoree9440c013cfdcc23312bc61d5762f1d1.tex}}}} + +\newcommand{\sailRISCVvalfMaddTypeMnemonicS}{\saildoclabelled{sailRISCVzfzymaddzytypezymnemoniczyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_madd_type_mnemonic_se8cab142783011d68d65bf9f55ceaf5f.tex}}}} + +\newcommand{\sailRISCVvalfBinRmTypeMnemonicS}{\saildoclabelled{sailRISCVzfzybinzyrmzytypezymnemoniczyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_bin_rm_type_mnemonic_s2d0dda4f6d202d3b11b80b4a78a91df1.tex}}}} + +\newcommand{\sailRISCVvalfUnRmTypeMnemonicS}{\saildoclabelled{sailRISCVzfzyunzyrmzytypezymnemoniczyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_un_rm_type_mnemonic_s24ea00e2ecedf00b96871ba799645a81.tex}}}} + +\newcommand{\sailRISCVvalfBinTypeMnemonicS}{\saildoclabelled{sailRISCVzfzybinzytypezymnemoniczyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_bin_type_mnemonic_s7707fb27bf62e8e8783b4425caefe10c.tex}}}} + +\newcommand{\sailRISCVvalfUnTypeMnemonicS}{\saildoclabelled{sailRISCVzfzyunzytypezymnemoniczyS}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_un_type_mnemonic_s68f8c6b309ddb2dc8d9cab3341f41b29.tex}}}} + +\newcommand{\sailRISCVvalfsplitD}{\saildoclabelled{sailRISCVzfsplitzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfsplit_d774cb8ca3d70fb4590f5725c3fd93ad0.tex}}}} + +\newcommand{\sailRISCVfnfsplitD}{\saildoclabelled{sailRISCVfnzfsplitzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfsplit_d774cb8ca3d70fb4590f5725c3fd93ad0.tex}}}} + +\newcommand{\sailRISCVvalfmakeD}{\saildoclabelled{sailRISCVzfmakezyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfmake_de1abf4e676ae7d02ecd6d0037a7d77ee.tex}}}} + +\newcommand{\sailRISCVfnfmakeD}{\saildoclabelled{sailRISCVfnzfmakezyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfmake_de1abf4e676ae7d02ecd6d0037a7d77ee.tex}}}} + +\newcommand{\sailRISCVvalcanonicalNaND}{\saildoclabelled{sailRISCVzcanonicalzyNaNzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcanonical_nan_d7d468e933fb666b50bdf56e90272edf5.tex}}}} + +\newcommand{\sailRISCVfncanonicalNaND}{\saildoclabelled{sailRISCVfnzcanonicalzyNaNzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcanonical_nan_d7d468e933fb666b50bdf56e90272edf5.tex}}}} + +\newcommand{\sailRISCVvalfIsNegInfD}{\saildoclabelled{sailRISCVzfzyiszynegzyinfzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_neg_inf_d3f44c40462ec32ab41b8fa4dc4e6f998.tex}}}} + +\newcommand{\sailRISCVfnfIsNegInfD}{\saildoclabelled{sailRISCVfnzfzyiszynegzyinfzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_neg_inf_d3f44c40462ec32ab41b8fa4dc4e6f998.tex}}}} + +\newcommand{\sailRISCVvalfIsNegNormD}{\saildoclabelled{sailRISCVzfzyiszynegzynormzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_neg_norm_d9b9e067af3304bb1fae5d1501327fd53.tex}}}} + +\newcommand{\sailRISCVfnfIsNegNormD}{\saildoclabelled{sailRISCVfnzfzyiszynegzynormzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_neg_norm_d9b9e067af3304bb1fae5d1501327fd53.tex}}}} + +\newcommand{\sailRISCVvalfIsNegSubnormD}{\saildoclabelled{sailRISCVzfzyiszynegzysubnormzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_neg_subnorm_d808d9c9ea664491fe0b23b650d1e996c.tex}}}} + +\newcommand{\sailRISCVfnfIsNegSubnormD}{\saildoclabelled{sailRISCVfnzfzyiszynegzysubnormzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_neg_subnorm_d808d9c9ea664491fe0b23b650d1e996c.tex}}}} + +\newcommand{\sailRISCVvalfIsNegZeroD}{\saildoclabelled{sailRISCVzfzyiszynegzyzzerozyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_neg_zzero_d7855947d702bd41cc96dbb033e17918f.tex}}}} + +\newcommand{\sailRISCVfnfIsNegZeroD}{\saildoclabelled{sailRISCVfnzfzyiszynegzyzzerozyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_neg_zzero_d7855947d702bd41cc96dbb033e17918f.tex}}}} + +\newcommand{\sailRISCVvalfIsPosZeroD}{\saildoclabelled{sailRISCVzfzyiszyposzyzzerozyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_pos_zzero_d7e379cb7f8f90c1af7e79d78e2a86f37.tex}}}} + +\newcommand{\sailRISCVfnfIsPosZeroD}{\saildoclabelled{sailRISCVfnzfzyiszyposzyzzerozyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_pos_zzero_d7e379cb7f8f90c1af7e79d78e2a86f37.tex}}}} + +\newcommand{\sailRISCVvalfIsPosSubnormD}{\saildoclabelled{sailRISCVzfzyiszyposzysubnormzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_pos_subnorm_d7e83f87299dae2035e33b7c97dd6be45.tex}}}} + +\newcommand{\sailRISCVfnfIsPosSubnormD}{\saildoclabelled{sailRISCVfnzfzyiszyposzysubnormzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_pos_subnorm_d7e83f87299dae2035e33b7c97dd6be45.tex}}}} + +\newcommand{\sailRISCVvalfIsPosNormD}{\saildoclabelled{sailRISCVzfzyiszyposzynormzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_pos_norm_d6611be4e31c69209487c037c5336c370.tex}}}} + +\newcommand{\sailRISCVfnfIsPosNormD}{\saildoclabelled{sailRISCVfnzfzyiszyposzynormzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_pos_norm_d6611be4e31c69209487c037c5336c370.tex}}}} + +\newcommand{\sailRISCVvalfIsPosInfD}{\saildoclabelled{sailRISCVzfzyiszyposzyinfzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_pos_inf_ddc033c6bfe555dfe790113dec0ddb7e3.tex}}}} + +\newcommand{\sailRISCVfnfIsPosInfD}{\saildoclabelled{sailRISCVfnzfzyiszyposzyinfzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_pos_inf_ddc033c6bfe555dfe790113dec0ddb7e3.tex}}}} + +\newcommand{\sailRISCVvalfIsSNaND}{\saildoclabelled{sailRISCVzfzyiszySNaNzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_snan_d3e7f4d132d4d3fe4846581a123c48b56.tex}}}} + +\newcommand{\sailRISCVfnfIsSNaND}{\saildoclabelled{sailRISCVfnzfzyiszySNaNzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_snan_d3e7f4d132d4d3fe4846581a123c48b56.tex}}}} + +\newcommand{\sailRISCVvalfIsQNaND}{\saildoclabelled{sailRISCVzfzyiszyQNaNzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_qnan_d5bbb21fc7537d62baacf94741f71226d.tex}}}} + +\newcommand{\sailRISCVfnfIsQNaND}{\saildoclabelled{sailRISCVfnzfzyiszyQNaNzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_qnan_d5bbb21fc7537d62baacf94741f71226d.tex}}}} + +\newcommand{\sailRISCVvalfIsNaND}{\saildoclabelled{sailRISCVzfzyiszyNaNzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_is_nan_d970e43a6bafb89b645fab556a4ad623c.tex}}}} + +\newcommand{\sailRISCVfnfIsNaND}{\saildoclabelled{sailRISCVfnzfzyiszyNaNzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzf_is_nan_d970e43a6bafb89b645fab556a4ad623c.tex}}}} + +\newcommand{\sailRISCVvalnegateD}{\saildoclabelled{sailRISCVznegatezyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valznegate_dc9622c2a4f7fec13696be94bec5ae96c.tex}}}} + +\newcommand{\sailRISCVfnnegateD}{\saildoclabelled{sailRISCVfnznegatezyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnznegate_dc9622c2a4f7fec13696be94bec5ae96c.tex}}}} + +\newcommand{\sailRISCVvalfeqQuietD}{\saildoclabelled{sailRISCVzfeqzyquietzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfeq_quiet_d0b6b5eb435e8b9c9bcf3b77e16fff044.tex}}}} + +\newcommand{\sailRISCVfnfeqQuietD}{\saildoclabelled{sailRISCVfnzfeqzyquietzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfeq_quiet_d0b6b5eb435e8b9c9bcf3b77e16fff044.tex}}}} + +\newcommand{\sailRISCVvalfltD}{\saildoclabelled{sailRISCVzfltzyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzflt_dc45e113a7fb9ece6e62166679b975f44.tex}}}} + +\newcommand{\sailRISCVfnfltD}{\saildoclabelled{sailRISCVfnzfltzyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzflt_dc45e113a7fb9ece6e62166679b975f44.tex}}}} + +\newcommand{\sailRISCVvalfleD}{\saildoclabelled{sailRISCVzflezyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfle_dc504d6eb55e9a730eda7235ae654dd1c.tex}}}} + +\newcommand{\sailRISCVfnfleD}{\saildoclabelled{sailRISCVfnzflezyD}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfle_dc504d6eb55e9a730eda7235ae654dd1c.tex}}}} + +\newcommand{\sailRISCVvalfMaddTypeMnemonicD}{\saildoclabelled{sailRISCVzfzymaddzytypezymnemoniczyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_madd_type_mnemonic_de10f87b5527cad531eb1f3e055843354.tex}}}} + +\newcommand{\sailRISCVvalfBinRmTypeMnemonicD}{\saildoclabelled{sailRISCVzfzybinzyrmzytypezymnemoniczyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_bin_rm_type_mnemonic_deb9e3f6f9179ea4b09697f358f9f6a0b.tex}}}} + +\newcommand{\sailRISCVvalfUnRmTypeMnemonicD}{\saildoclabelled{sailRISCVzfzyunzyrmzytypezymnemoniczyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_un_rm_type_mnemonic_d4a9ba98f21ea36db9609bd6233749d86.tex}}}} + +\newcommand{\sailRISCVvalfBinTypeMnemonicD}{\saildoclabelled{sailRISCVzfzybinzytypezymnemoniczyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_bin_type_mnemonic_d4c3459a461182e50755d18d2795fe9de.tex}}}} + +\newcommand{\sailRISCVvalfUnTypeMnemonicD}{\saildoclabelled{sailRISCVzfzyunzytypezymnemoniczyD}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzf_un_type_mnemonic_d67aa9b49056aabdddaa065ba03ecbadb.tex}}}} + +\newcommand{\sailRISCVvalhandleLoadDataViaCap}{\saildoclabelled{sailRISCVzhandlezyloadzydatazyviazycap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_load_data_via_capf2827ba9c795213ba1703c9ae04ec80e.tex}}}} + +\newcommand{\sailRISCVfnhandleLoadDataViaCap}{\saildoclabelled{sailRISCVfnzhandlezyloadzydatazyviazycap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_load_data_via_capf2827ba9c795213ba1703c9ae04ec80e.tex}}}} + +\newcommand{\sailRISCVvalhandleLoadCapViaCap}{\saildoclabelled{sailRISCVzhandlezyloadzycapzyviazycap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_load_cap_via_capc983c32af845a3dec84f2d1241c33390.tex}}}} + +\newcommand{\sailRISCVfnhandleLoadCapViaCap}{\saildoclabelled{sailRISCVfnzhandlezyloadzycapzyviazycap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_load_cap_via_capc983c32af845a3dec84f2d1241c33390.tex}}}} + +\newcommand{\sailRISCVvalcheckResMisaligned}{\saildoclabelled{sailRISCVzcheckzyreszymisaligned}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzcheck_res_misalignede05ad7adc37fbdff34459806aaddc074.tex}}}} + +\newcommand{\sailRISCVfncheckResMisaligned}{\saildoclabelled{sailRISCVfnzcheckzyreszymisaligned}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzcheck_res_misalignede05ad7adc37fbdff34459806aaddc074.tex}}}} + +\newcommand{\sailRISCVvalhandleLoadresDataViaCap}{\saildoclabelled{sailRISCVzhandlezyloadreszydatazyviazycap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_loadres_data_via_cap08189f30ce7dd627d16d9228026d4005.tex}}}} + +\newcommand{\sailRISCVfnhandleLoadresDataViaCap}{\saildoclabelled{sailRISCVfnzhandlezyloadreszydatazyviazycap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_loadres_data_via_cap08189f30ce7dd627d16d9228026d4005.tex}}}} + +\newcommand{\sailRISCVvalhandleLoadresCapViaCap}{\saildoclabelled{sailRISCVzhandlezyloadreszycapzyviazycap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_loadres_cap_via_capcff54276a28e84c26d372dc8f545b3f0.tex}}}} + +\newcommand{\sailRISCVfnhandleLoadresCapViaCap}{\saildoclabelled{sailRISCVfnzhandlezyloadreszycapzyviazycap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_loadres_cap_via_capcff54276a28e84c26d372dc8f545b3f0.tex}}}} + +\newcommand{\sailRISCVvalhandleStoreDataViaCap}{\saildoclabelled{sailRISCVzhandlezystorezydatazyviazycap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_store_data_via_capa375706a8b6644ee610b608c6152f081.tex}}}} + +\newcommand{\sailRISCVfnhandleStoreDataViaCap}{\saildoclabelled{sailRISCVfnzhandlezystorezydatazyviazycap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_store_data_via_capa375706a8b6644ee610b608c6152f081.tex}}}} + +\newcommand{\sailRISCVvalhandleStoreCapViaCap}{\saildoclabelled{sailRISCVzhandlezystorezycapzyviazycap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_store_cap_via_cap4d789b2f59a39e53239d073296e45c38.tex}}}} + +\newcommand{\sailRISCVfnhandleStoreCapViaCap}{\saildoclabelled{sailRISCVfnzhandlezystorezycapzyviazycap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_store_cap_via_cap4d789b2f59a39e53239d073296e45c38.tex}}}} + +\newcommand{\sailRISCVvalhandleStoreCondDataViaCap}{\saildoclabelled{sailRISCVzhandlezystorezycondzydatazyviazycap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_store_cond_data_via_cap90bf472704e0e0e2072d2afbb0123121.tex}}}} + +\newcommand{\sailRISCVfnhandleStoreCondDataViaCap}{\saildoclabelled{sailRISCVfnzhandlezystorezycondzydatazyviazycap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_store_cond_data_via_cap90bf472704e0e0e2072d2afbb0123121.tex}}}} + +\newcommand{\sailRISCVvalhandleStoreCondCapViaCap}{\saildoclabelled{sailRISCVzhandlezystorezycondzycapzyviazycap}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzhandle_store_cond_cap_via_capdfc2c7d93322ab0a720ded29c24438b2.tex}}}} + +\newcommand{\sailRISCVfnhandleStoreCondCapViaCap}{\saildoclabelled{sailRISCVfnzhandlezystorezycondzycapzyviazycap}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzhandle_store_cond_cap_via_capdfc2c7d93322ab0a720ded29c24438b2.tex}}}} + +\newcommand{\sailRISCVfclUTYPEexecute}{\saildoclabelled{sailRISCVfclUTYPEzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclUTYPEzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclRISCVUnderscoreJALexecute}{\saildoclabelled{sailRISCVfclRISCVUnderscoreJALzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclRISCVUnderscoreJALzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclBTYPEexecute}{\saildoclabelled{sailRISCVfclBTYPEzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclBTYPEzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclITYPEexecute}{\saildoclabelled{sailRISCVfclITYPEzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclITYPEzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclSHIFTIOPexecute}{\saildoclabelled{sailRISCVfclSHIFTIOPzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclSHIFTIOPzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclRTYPEexecute}{\saildoclabelled{sailRISCVfclRTYPEzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclRTYPEzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclLOADexecute}{\saildoclabelled{sailRISCVfclLOADzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclLOADzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclSTOREexecute}{\saildoclabelled{sailRISCVfclSTOREzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclSTOREzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclADDIWexecute}{\saildoclabelled{sailRISCVfclADDIWzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclADDIWzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclSHIFTWexecute}{\saildoclabelled{sailRISCVfclSHIFTWzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclSHIFTWzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclRTYPEWexecute}{\saildoclabelled{sailRISCVfclRTYPEWzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclRTYPEWzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclSHIFTIWOPexecute}{\saildoclabelled{sailRISCVfclSHIFTIWOPzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclSHIFTIWOPzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFENCEexecute}{\saildoclabelled{sailRISCVfclFENCEzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFENCEzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFENCEUnderscoreTSOexecute}{\saildoclabelled{sailRISCVfclFENCEUnderscoreTSOzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFENCEUnderscoreTSOzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFENCEIexecute}{\saildoclabelled{sailRISCVfclFENCEIzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFENCEIzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclECALLexecute}{\saildoclabelled{sailRISCVfclECALLzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclECALLzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclMRETexecute}{\saildoclabelled{sailRISCVfclMRETzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclMRETzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclSRETexecute}{\saildoclabelled{sailRISCVfclSRETzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclSRETzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclEBREAKexecute}{\saildoclabelled{sailRISCVfclEBREAKzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclEBREAKzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclWFIexecute}{\saildoclabelled{sailRISCVfclWFIzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclWFIzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclSFENCEUnderscoreVMAexecute}{\saildoclabelled{sailRISCVfclSFENCEUnderscoreVMAzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclSFENCEUnderscoreVMAzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclLOADRESexecute}{\saildoclabelled{sailRISCVfclLOADRESzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclLOADRESzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclSTORECONexecute}{\saildoclabelled{sailRISCVfclSTORECONzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclSTORECONzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclAMOexecute}{\saildoclabelled{sailRISCVfclAMOzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclAMOzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreNOPexecute}{\saildoclabelled{sailRISCVfclCUnderscoreNOPzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreNOPzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreADDIFourSPNexecute}{\saildoclabelled{sailRISCVfclCUnderscoreADDIFourSPNzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreADDIFourSPNzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreLWexecute}{\saildoclabelled{sailRISCVfclCUnderscoreLWzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreLWzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreLDexecute}{\saildoclabelled{sailRISCVfclCUnderscoreLDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreLDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreSWexecute}{\saildoclabelled{sailRISCVfclCUnderscoreSWzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreSWzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreSDexecute}{\saildoclabelled{sailRISCVfclCUnderscoreSDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreSDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreADDIexecute}{\saildoclabelled{sailRISCVfclCUnderscoreADDIzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreADDIzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreJALexecute}{\saildoclabelled{sailRISCVfclCUnderscoreJALzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreJALzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreADDIWexecute}{\saildoclabelled{sailRISCVfclCUnderscoreADDIWzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreADDIWzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreLIexecute}{\saildoclabelled{sailRISCVfclCUnderscoreLIzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreLIzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreADDIOneSixSPexecute}{\saildoclabelled{sailRISCVfclCUnderscoreADDIOneSixSPzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreADDIOneSixSPzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreLUIexecute}{\saildoclabelled{sailRISCVfclCUnderscoreLUIzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreLUIzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreSRLIexecute}{\saildoclabelled{sailRISCVfclCUnderscoreSRLIzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreSRLIzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreSRAIexecute}{\saildoclabelled{sailRISCVfclCUnderscoreSRAIzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreSRAIzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreANDIexecute}{\saildoclabelled{sailRISCVfclCUnderscoreANDIzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreANDIzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreSUBexecute}{\saildoclabelled{sailRISCVfclCUnderscoreSUBzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreSUBzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreXORexecute}{\saildoclabelled{sailRISCVfclCUnderscoreXORzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreXORzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreORexecute}{\saildoclabelled{sailRISCVfclCUnderscoreORzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreORzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreANDexecute}{\saildoclabelled{sailRISCVfclCUnderscoreANDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreANDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreSUBWexecute}{\saildoclabelled{sailRISCVfclCUnderscoreSUBWzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreSUBWzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreADDWexecute}{\saildoclabelled{sailRISCVfclCUnderscoreADDWzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreADDWzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreJexecute}{\saildoclabelled{sailRISCVfclCUnderscoreJzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreJzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreBEQZexecute}{\saildoclabelled{sailRISCVfclCUnderscoreBEQZzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreBEQZzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreBNEZexecute}{\saildoclabelled{sailRISCVfclCUnderscoreBNEZzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreBNEZzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreSLLIexecute}{\saildoclabelled{sailRISCVfclCUnderscoreSLLIzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreSLLIzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreLWSPexecute}{\saildoclabelled{sailRISCVfclCUnderscoreLWSPzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreLWSPzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreLDSPexecute}{\saildoclabelled{sailRISCVfclCUnderscoreLDSPzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreLDSPzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreSWSPexecute}{\saildoclabelled{sailRISCVfclCUnderscoreSWSPzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreSWSPzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreSDSPexecute}{\saildoclabelled{sailRISCVfclCUnderscoreSDSPzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreSDSPzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreJRexecute}{\saildoclabelled{sailRISCVfclCUnderscoreJRzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreJRzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreJALRexecute}{\saildoclabelled{sailRISCVfclCUnderscoreJALRzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreJALRzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreMVexecute}{\saildoclabelled{sailRISCVfclCUnderscoreMVzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreMVzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreEBREAKexecute}{\saildoclabelled{sailRISCVfclCUnderscoreEBREAKzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreEBREAKzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreADDexecute}{\saildoclabelled{sailRISCVfclCUnderscoreADDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreADDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclMULexecute}{\saildoclabelled{sailRISCVfclMULzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclMULzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclDIVexecute}{\saildoclabelled{sailRISCVfclDIVzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclDIVzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclREMexecute}{\saildoclabelled{sailRISCVfclREMzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclREMzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclMULWexecute}{\saildoclabelled{sailRISCVfclMULWzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclMULWzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclDIVWexecute}{\saildoclabelled{sailRISCVfclDIVWzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclDIVWzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclREMWexecute}{\saildoclabelled{sailRISCVfclREMWzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclREMWzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCSRexecute}{\saildoclabelled{sailRISCVfclCSRzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCSRzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclLOADUnderscoreFPexecute}{\saildoclabelled{sailRISCVfclLOADUnderscoreFPzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclLOADUnderscoreFPzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclSTOREUnderscoreFPexecute}{\saildoclabelled{sailRISCVfclSTOREUnderscoreFPzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclSTOREUnderscoreFPzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreMADDUnderscoreTYPEUnderscoreSexecute}{\saildoclabelled{sailRISCVfclFUnderscoreMADDUnderscoreTYPEUnderscoreSzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreMADDUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreRMUnderscoreTYPEUnderscoreSexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreRMUnderscoreTYPEUnderscoreSzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreRMUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSAexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSAzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSAzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSBexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSBzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSBzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSCexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSCzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSDexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSEexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSEzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSEzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSFexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSFzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSFzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSGexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSGzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSGzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSHexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSHzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSHzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSAexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSAzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSAzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSBexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSBzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSBzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSCexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSCzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSDexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSEexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSEzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSEzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSFexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSFzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSFzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSGexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreSGzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSGzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreTYPEUnderscoreSexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreTYPEUnderscoreSzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreTYPEUnderscoreSAexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreTYPEUnderscoreSAzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreSAzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreTYPEUnderscoreSBexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreTYPEUnderscoreSBzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreSBzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreMADDUnderscoreTYPEUnderscoreDexecute}{\saildoclabelled{sailRISCVfclFUnderscoreMADDUnderscoreTYPEUnderscoreDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreMADDUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreRMUnderscoreTYPEUnderscoreDexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreRMUnderscoreTYPEUnderscoreDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreRMUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDAexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDAzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDAzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDBexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDBzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDBzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDCexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDCzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDDexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDEexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDEzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDEzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDFexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDFzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDFzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDGexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDGzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDGzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDHexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDHzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDHzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDIexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDIzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDIzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDJexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDJzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDJzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDAexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDAzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDAzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDBexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDBzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDBzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDCexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDCzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDDexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDEexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDEzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDEzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDFexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDFzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDFzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDGexecute}{\saildoclabelled{sailRISCVfclFUnderscoreBINUnderscoreTYPEUnderscoreDGzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDGzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreTYPEUnderscoreDexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreTYPEUnderscoreDzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreTYPEUnderscoreDAexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreTYPEUnderscoreDAzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreDAzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFUnderscoreUNUnderscoreTYPEUnderscoreDBexecute}{\saildoclabelled{sailRISCVfclFUnderscoreUNUnderscoreTYPEUnderscoreDBzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreDBzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCGetPermexecute}{\saildoclabelled{sailRISCVfclCGetPermzexecute}{\saildocfcl{The least significant \hyperref[sailRISCVzcapzyhpermszywidth]{\lstinline{cap_hperms_width}} bits of integer register \emph{rd} are +set equal to the \textbf{perms} field of capability register \emph{cs1}; bits +\hyperref[sailRISCVzcapzyupermszyshift]{\lstinline{cap_uperms_shift}} to \hyperref[sailRISCVzcapzyupermszyshift]{\lstinline{cap_uperms_shift}}+\hyperref[sailRISCVzcapzyupermszywidth]{\lstinline{cap_uperms_width}}-1 of \emph{rd} are set +equal to the \textbf{uperms} field of \emph{cs1}. +The other bits of \emph{rd} are set to zero. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCGetPermzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCGetFlagsexecute}{\saildoclabelled{sailRISCVfclCGetFlagszexecute}{\saildocfcl{Integer register \emph{rd} is set equal to the zero-extended \textbf{flags} field of +capability register \emph{cs1}. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCGetFlagszexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCGetTypeexecute}{\saildoclabelled{sailRISCVfclCGetTypezexecute}{\saildocfcl{Integer register \emph{rd} is set equal to the \textbf{otype} field of capability +register \emph{cs1}. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCGetTypezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCGetBaseexecute}{\saildoclabelled{sailRISCVfclCGetBasezexecute}{\saildocfcl{Integer register \emph{rd} is set equal to the \textbf{base} field of capability +register \emph{cs1}. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCGetBasezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCGetOffsetexecute}{\saildoclabelled{sailRISCVfclCGetOffsetzexecute}{\saildocfcl{Integer register \emph{rd} is set equal to the \textbf{offset} field of capability +register \emph{cs1}. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCGetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCGetLenexecute}{\saildoclabelled{sailRISCVfclCGetLenzexecute}{\saildocfcl{Integer register \emph{rd} is set equal to the \textbf{length} field of capability +register \emph{cs1}. + +\subsection*{Notes} + + +\begin{itemize} +\item Due to the compressed representation of capabilities, the actual length + of capabilities can be $2^{\hyperref[sailRISCVzxlen]{{xlen}}}$; \hyperref[sailRISCVzCGetLen]{\lstinline{CGetLen}} will return the + maximum value of $2^{\hyperref[sailRISCVzxlen]{{xlen}}}-1$ in this case. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCGetLenzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCGetTagexecute}{\saildoclabelled{sailRISCVfclCGetTagzexecute}{\saildocfcl{The low bit of integer register \emph{rd} is set to the \textbf{tag} field of \emph{cs1}. +All other bits of \emph{rd} are cleared. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCGetTagzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCGetSealedexecute}{\saildoclabelled{sailRISCVfclCGetSealedzexecute}{\saildocfcl{The low bit of integer register \emph{rd} is set to 0 if \emph{cs1} is unsealed +and to 1 otherwise. +All other bits of \emph{rd} are cleared. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCGetSealedzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCGetAddrexecute}{\saildoclabelled{sailRISCVfclCGetAddrzexecute}{\saildocfcl{Integer register \emph{rd} is set equal to the \textbf{address} field of capability +register \emph{cs1}. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCGetAddrzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCSpecialRWexecute}{\saildoclabelled{sailRISCVfclCSpecialRWzexecute}{\saildocfcl{Capability register \emph{cd} is set equal to special capability register \emph{scr}, +and \emph{scr} is set equal to capability register \emph{cs1} if \emph{cs1} is not \textbf{C0}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{scr} does not exist. +\item \emph{scr} is read-only and \emph{cs1} is not \textbf{C0}. +\item \emph{scr} is only accessible to a higher privilege mode. +\item \emph{scr} requires \textbf{Permit\_Access\_System\_Registers} and that is not + granted by \textbf{PCC}.\textbf{perms}. +\end{itemize} + + +\subsection*{Notes} + + +\begin{itemize} +\item Writing \textbf{NULL} to a special capability register cannot be done with \textbf{C0} + as that only performs a read. An alternative implementation would allocate + a separate two-operand CSpecialR instruction and interpret \emph{cs1} being + \textbf{C0} as a write of \textbf{NULL} if the need to use a temporary capability + register proves to be overly problematic for software. For U-mode + transitions to domains without \textbf{Permit\_Access\_System\_Registers} only + \textbf{DDC} should need clearing, which can be done with \hyperref[sailRISCVzCClear]{\lstinline{CClear}}. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCSpecialRWzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCAndPermexecute}{\saildoclabelled{sailRISCVfclCAndPermzexecute}{\saildocfcl{Capability register \emph{cd} is replaced with the contents of capability +register \emph{cs1} with the \textbf{perms} field set to the bitwise and of its +previous value and bits 0 to \hyperref[sailRISCVzcapzyhpermszywidth]{\lstinline{cap_hperms_width}}-1 of integer register \emph{rs2} +and the \textbf{uperms} field set to the bitwise and of its previous value and +bits \hyperref[sailRISCVzcapzyupermszyshift]{\lstinline{cap_uperms_shift}} to \hyperref[sailRISCVzcapzyupermszyshift]{\lstinline{cap_uperms_shift}}+\hyperref[sailRISCVzcapzyupermszywidth]{\lstinline{cap_uperms_width}}-1 of \emph{rs2}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1}.\textbf{tag} is set and \emph{cs1} is sealed. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCAndPermzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCSetFlagsexecute}{\saildoclabelled{sailRISCVfclCSetFlagszexecute}{\saildocfcl{Capability register \emph{cd} is replaced with the contents of capability +register \emph{cs1} with the \textbf{flags} field set to bits 0 to \hyperref[sailRISCVzcapzyflagszywidth]{\lstinline{cap_flags_width}}-1 +of integer register \emph{rs2}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is set and \emph{cs1} is sealed. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCSetFlagszexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCToPtrexecute}{\saildoclabelled{sailRISCVfclCToPtrzexecute}{\saildocfcl{If the \textbf{tag} field of capability register \emph{cs1} is not set then integer +register \emph{rd} is set to 0, otherwise integer register \emph{rd} is set to +\emph{cs1}.\textbf{address} $-$ \emph{cs2}.\textbf{base}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs2}.\textbf{tag} is unset. +\item \emph{cs1}.\textbf{tag} is set and \emph{cs1} is sealed. +\end{itemize} + + +\subsection*{Notes} + + +\begin{itemize} +\item \emph{cs2} being sealed will not cause an exception to be raised. This is for + further study. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCToPtrzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCSubexecute}{\saildoclabelled{sailRISCVfclCSubzexecute}{\saildocfcl{Integer register \emph{rd} is set equal to (\emph{cs1}.\textbf{address} $-$ +\emph{cs2}.\textbf{address}) $\bmod~2^{\hyperref[sailRISCVzxlen]{{xlen}}}$. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCSubzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCIncOffsetexecute}{\saildoclabelled{sailRISCVfclCIncOffsetzexecute}{\saildocfcl{Capability register \emph{cd} is set equal to capability register \emph{cs1} with its +\textbf{address} replaced with \emph{cs1}.\textbf{address} $+$ \emph{rs2}. +If the resulting capability cannot be represented exactly, then \emph{cd}.\textbf{tag} +is cleared. The remaining capability fields are set to what the in-memory +representation of \emph{cs1} with the address set to \emph{cs1}.\textbf{address} $+$ \emph{rs2} +decodes to. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is set and \emph{cs1} is sealed. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCIncOffsetzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCIncOffsetImmediateexecute}{\saildoclabelled{sailRISCVfclCIncOffsetImmediatezexecute}{\saildocfcl{Capability register \emph{cd} is set equal to capability register \emph{cs1} with its +\textbf{address} replaced with \emph{cs1}.\textbf{address} $+$ \emph{imm}. +If the resulting capability cannot be represented exactly, then \emph{cd}.\textbf{tag} +is cleared. The remaining capability fields are set to what the in-memory +representation of \emph{cs1} with the address set to \emph{cs1}.\textbf{address} $+$ \emph{imm} +decodes to. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is set and \emph{cs1} is sealed. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCIncOffsetImmediatezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCSetOffsetexecute}{\saildoclabelled{sailRISCVfclCSetOffsetzexecute}{\saildocfcl{Capability register \emph{cd} is set equal to capability register \emph{cs1} with its +\textbf{offset} replaced with \emph{cs1}.\textbf{offset} $+$ \emph{rs2}. +If the resulting capability cannot be represented exactly, then \emph{cd}.\textbf{tag} +is cleared. The remaining capability fields are set to what the in-memory +representation of \emph{cs1} with the address set to \emph{cd}.\textbf{address} decodes to. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is set and \emph{cs1} is sealed. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCSetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCSetAddrexecute}{\saildoclabelled{sailRISCVfclCSetAddrzexecute}{\saildocfcl{Capability register \emph{cd} is set equal to capability register \emph{cs1} with its +\textbf{address} replaced with \emph{rs2}. +If the resulting capability cannot be represented exactly, then \emph{cd}.\textbf{tag} +is cleared. The remaining capability fields are set to what the in-memory +representation of \emph{cs1} with the address set to \emph{rs2} decodes to. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is set and \emph{cs1} is sealed. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCSetAddrzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCSetBoundsexecute}{\saildoclabelled{sailRISCVfclCSetBoundszexecute}{\saildocfcl{Capability register \emph{cd} is set to capability register \emph{cs1} with its +\textbf{base} field replaced with \emph{cs1}.\textbf{address} and its \textbf{length} field +replaced with integer register \emph{rs2}. If the resulting capability cannot be +represented exactly the \textbf{base} will be rounded down and the \textbf{length} +will be rounded up by the smallest amount needed to form a representable +capability covering the requested bounds, and will never exceed the bounds +of \emph{cs1}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed. +\item \emph{cs1}.\textbf{address} $\lt$ \emph{cs1}.\textbf{base}. +\item \emph{cs1}.\textbf{address} $+$ \emph{rs2} $\gt$ \emph{cs1}.\textbf{top}. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCSetBoundszexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCSetBoundsImmediateexecute}{\saildoclabelled{sailRISCVfclCSetBoundsImmediatezexecute}{\saildocfcl{Capability register \emph{cd} is set to capability register \emph{cs1} with its +\textbf{base} field replaced with \emph{cs1}.\textbf{address} and its \textbf{length} field +replaced with \emph{uimm}. If the resulting capability cannot be represented +exactly the \textbf{base} will be rounded down and the \textbf{length} will be rounded +up by the smallest amount needed to form a representable capability covering +the requested bounds, and will never exceed the bounds of \emph{cs1}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed. +\item \emph{cs1}.\textbf{address} $\lt$ \emph{cs1}.\textbf{base}. +\item \emph{cs1}.\textbf{address} $+$ \emph{uimm} $\gt$ \emph{cs1}.\textbf{top}. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCSetBoundsImmediatezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCSetBoundsExactexecute}{\saildoclabelled{sailRISCVfclCSetBoundsExactzexecute}{\saildocfcl{Capability register \emph{cd} is set to capability register \emph{cs1} with its +\textbf{base} field replaced with \emph{cs1}.\textbf{address} and its \textbf{length} field +replaced with integer register \emph{rs2}. Unlike \hyperref[sailRISCVzCSetBounds]{\lstinline{CSetBounds}}, this instruction +will trap if the resulting capability cannot be represented exactly. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed. +\item \emph{cs1}.\textbf{address} $\lt$ \emph{cs1}.\textbf{base}. +\item \emph{cs1}.\textbf{address} $+$ \emph{rs2} $\gt$ \emph{cs1}.\textbf{top}. +\item The resulting capability cannot be represented exactly. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCSetBoundsExactzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCClearTagexecute}{\saildoclabelled{sailRISCVfclCClearTagzexecute}{\saildocfcl{Capability register \emph{cd} is replaced with the contents of \emph{cs1}, with +the \textbf{tag} field cleared. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCClearTagzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCMoveexecute}{\saildoclabelled{sailRISCVfclCMovezexecute}{\saildocfcl{Capability register \emph{cd} is replaced with the contents of \emph{cs1}. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCMovezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclClearexecute}{\saildoclabelled{sailRISCVfclClearzexecute}{\saildocfcl{Integer registers 8 $\times$ \emph{q} $+$ \emph{i} are each set to 0 if the \emph{i}th bit +of \emph{m} is set. This instruction is only present on implementations with a +split register file. On implementations with a merged register file the +functionality of this instruction is covered by \hyperref[sailRISCVzCClear]{\lstinline{CClear}}. + +\subsection*{Notes} + + +\begin{itemize} +\item This instruction is designed to accelerate the register clearing that is + required for secure domain transitions. It is expected that it can be + implemented efficiently in hardware using a single `valid' bit per + register that is cleared by this instruction and set on any subsequent + write to the register. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclClearzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCClearexecute}{\saildoclabelled{sailRISCVfclCClearzexecute}{\saildocfcl{Capability registers 8 $\times$ \emph{q} $+$ \emph{i} are each set to \textbf{NULL} if the +\emph{i}th bit of \emph{m} is set, with the exception that the 0th bit of \emph{m} refers +to \textbf{DDC} when \emph{q} is 0, rather than \textbf{C0}. + +\subsection*{Notes} + + +\begin{itemize} +\item This instruction is designed to accelerate the register clearing that is + required for secure domain transitions. It is expected that it can be + implemented efficiently in hardware using a single `valid' bit per + register that is cleared by this instruction and set on any subsequent + write to the register. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCClearzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclFPClearexecute}{\saildoclabelled{sailRISCVfclFPClearzexecute}{\saildocfcl{Floating-point registers 8 $\times$ \emph{q} $+$ \emph{i} are each set to 0 if the +\emph{i}th bit of \emph{m} is set. + +\subsection*{Notes} + + +\begin{itemize} +\item This instruction is designed to accelerate the register clearing that is + required for secure domain transitions. It is expected that it can be + implemented efficiently in hardware using a single `valid' bit per + register that is cleared by this instruction and set on any subsequent + write to the register. + + +\item The 0 value written is FLEN bits wide, the largest supported by the + implementation, such that the in-memory representation of the register is + 0, rather than a NaN-boxed narrower value. + + +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclFPClearzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCFromPtrexecute}{\saildoclabelled{sailRISCVfclCFromPtrzexecute}{\saildocfcl{If the value of integer register \emph{rs2} is 0 then capability register \emph{cd} is +set to \textbf{NULL}. Otherwise capability register \emph{cd} is set to capability +register \emph{cs1} with its \textbf{offset} replaced with \emph{rs2}. If the resulting +capability cannot be represented exactly, then \emph{cd}.\textbf{tag} is cleared. The +remaining capability fields are set to what the in-memory representation of +\emph{cs1} with the address set to \emph{cd}.\textbf{address} decodes to. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is set. +\item \emph{cs1} is sealed. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCFromPtrzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCBuildCapexecute}{\saildoclabelled{sailRISCVfclCBuildCapzexecute}{\saildocfcl{Capability register \emph{cd} is set equal to capability register \emph{cs1} with its +\textbf{base}, \textbf{length}, \textbf{address}, \textbf{perms}, \textbf{uperms} and \textbf{flags} +replaced with the corresponding fields in capability register \emph{cs2}. If +\emph{cs2} is a sentry then \emph{cd} is also sealed as a sentry. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed. +\item \emph{cs2}.\textbf{base} $\lt$ \emph{cs1}.\textbf{base} +\item \emph{cs2}.\textbf{top} $\gt$ \emph{cs1}.\textbf{top} +\item \emph{cs2}.\textbf{base} $\gt$ \emph{cs2}.\textbf{top} +\item \emph{cs2}.\textbf{perms} grants a permission that is not granted by + \emph{cs1}.\textbf{perms}. +\item \emph{cs2}.\textbf{uperms} grants a permission that is not granted by + \emph{cs1}.\textbf{uperms}. +\end{itemize} + + +\subsection*{Notes} + + +\begin{itemize} +\item Implementations may instead choose to set \emph{cd} to \emph{cs2} with its \textbf{tag} + set after performing all checks, but the specification derives the result + from \emph{cs1} in order to convey the provenance associated with this + operation. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCBuildCapzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCCopyTypeexecute}{\saildoclabelled{sailRISCVfclCCopyTypezexecute}{\saildocfcl{If the \textbf{otype} field of capability register \emph{cs2} is not a reserved value +then capability register \emph{cd} is replaced with the contents of capability +register \emph{cs1} with the \textbf{address} set to \emph{cs2}.\textbf{otype}. Otherwise +capability register \emph{cd} is replaced with the \textbf{NULL} capability with its +\textbf{address} set to \emph{cs2}.\textbf{otype}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed. +\item \emph{cs2}.\textbf{otype} $\lt$ \emph{cs1}.\textbf{base}. +\item \emph{cs2}.\textbf{otype} $\ge$ \emph{cs1}.\textbf{top}. +\end{itemize} + + +\subsection*{Notes} + + +\begin{itemize} +\item Reserved otypes always get turned into derived-from-\textbf{NULL} capabilities, + regardless of the authority given in \emph{cs1}, as, at the moment, all + reserved otypes are constructed using ambiently-available actions. + \hyperref[sailRISCVzCCSeal]{\lstinline{CCSeal}} knows how to work with these. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCCopyTypezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCRRLexecute}{\saildoclabelled{sailRISCVfclCRRLzexecute}{\saildocfcl{Integer register \emph{rd} is set to the smallest value greater or equal to \emph{rs1} +that can be used as a length to set exact bounds on a capability that has a +suitably aligned base (as obtained with the help of \hyperref[sailRISCVzCRAM]{\lstinline{CRAM}}). + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCRRLzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCRAMexecute}{\saildoclabelled{sailRISCVfclCRAMzexecute}{\saildocfcl{Integer register \emph{rd} is set to a mask that can be used to round addresses +down to to a value that is sufficiently aligned to set exact bounds for the +nearest representable length of \emph{rs1} (as obtained by \hyperref[sailRISCVzCRRL]{\lstinline{CRRL}}). + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCRAMzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCTestSubsetexecute}{\saildoclabelled{sailRISCVfclCTestSubsetzexecute}{\saildocfcl{Integer register \emph{rd} is set to 1 if the \textbf{tag} fields of capability +registers \emph{cs1} and \emph{cs2} are the same and the bounds and permissions of +\emph{cs2} are a subset of those of \emph{cs1}. + +\subsection*{Notes} + + +\begin{itemize} +\item The operand order for this instruction is reversed compared with the + normal RISC-V comparison instructions, but this may be changed in future. + + +\item The \textbf{otype} field is ignored for this instruction, but an alternative + implementation might wish to consider capabilities with distinct + \textbf{otype}s as unordered as is done for the \textbf{tag} field. + + +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCTestSubsetzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCSEQXexecute}{\saildoclabelled{sailRISCVfclCSEQXzexecute}{\saildocfcl{Integer register \emph{rd} is set to 1 if the \textbf{tag} fields and in-memory +representations of capability registers \emph{cs1} and \emph{cs2} are identical, +including any reserved encoding bits, otherwise it is set to 0. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCSEQXzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCSealexecute}{\saildoclabelled{sailRISCVfclCSealzexecute}{\saildocfcl{Capability register \emph{cd} is replaced with capability register \emph{cs1}, and is +sealed with \textbf{otype} equal to the \textbf{address} field of capability register +\emph{cs2}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs2}.\textbf{tag} is not set. +\item \emph{cs1}.\textbf{sealed} is set. +\item \emph{cs2}.\textbf{sealed} is set. +\item \emph{cs2}.\textbf{perms} does not grant \textbf{Permit\_Seal}. +\item \emph{cs2}.\textbf{address} $\lt$ \emph{cs2}.\textbf{base}. +\item \emph{cs2}.\textbf{address} $\ge$ \emph{cs2}.\textbf{top}. +\item \emph{cs2}.\textbf{address} $\gt$ \hyperref[sailRISCVzmaxzyotype]{\lstinline{max_otype}}. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCSealzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCCSealexecute}{\saildoclabelled{sailRISCVfclCCSealzexecute}{\saildocfcl{Capability register \emph{cd} is replaced with capability register \emph{cs1}, and is +conditionally sealed with \textbf{otype} equal to the \textbf{address} field of +capability register \emph{cs2}. The conditions under which the input is passed +through unaltered are intended to permit a fast branchless rederivation +sequence with multiple sealing authorities with a single \hyperref[sailRISCVzCBuildCap]{\lstinline{CBuildCap}} and a +set of \hyperref[sailRISCVzCCopyType]{\lstinline{CCopyType}} and \hyperref[sailRISCVzCCSeal]{\lstinline{CCSeal}} pairs when swapping capabilities in from +disk. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs2}.\textbf{sealed} is set. +\item \emph{cs2}.\textbf{perms} does not grant \textbf{Permit\_Seal}. +\item \emph{cs2}.\textbf{address} $\gt$ \hyperref[sailRISCVzmaxzyotype]{\lstinline{max_otype}}. +\end{itemize} + + +\subsection*{Notes} + + +\begin{itemize} +\item Since the intent is that this is used for rederiving swapped-out + capabilities, the expectation is that this whole sequence is guarded by a + check on whether the \textbf{tag} field of the capability was valid, and so any + invalid capability input in \emph{cs1} will cause a trap. + + +\item If the input to be conditionally sealed is already sealed it is passed + through before any futher checks are made. This allows multiple \hyperref[sailRISCVzCCSeal]{\lstinline{CCSeal}}s + in a chain, any of which can be the one to seal the initial input. The + intent is that all of these \hyperref[sailRISCVzCCSeal]{\lstinline{CCSeal}}s' authorities will have been produced + by \hyperref[sailRISCVzCCopyType]{\lstinline{CCopyType}}s of the same input (i.e., they will all attempt to seal to + the same type), but that's not, strictly, required. Sealed capabilities + with a reserved \textbf{otype} are also constructed directly by \hyperref[sailRISCVzCBuildCap]{\lstinline{CBuildCap}}. + + +\item To avoid the need to branch on whether the original capability was sealed, + attempts to seal with the reserved unsealed \textbf{otype} will leave the + capability unmodified rather than trap. + + +\item To avoid the need to check which is the correct authority, any sealing + request where the \textbf{address} of capability register \emph{cs2} is out of + bounds will leave the capability unmodified rather than trap, as will + attempts to seal with an invalid capability since it may have become + unrepresentable but be within its reinterpreted bounds. + + +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCCSealzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnsealexecute}{\saildoclabelled{sailRISCVfclCUnsealzexecute}{\saildocfcl{Capability register \emph{cd} is replaced with capability register \emph{cs1} and is +unsealed, using capability register \emph{cs2} as the authority for the unsealing +operation. If \emph{cs2}.\textbf{perms} does not grant \textbf{Global} then \emph{cd}.\textbf{perms} +is stripped of \textbf{Global}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs2}.\textbf{tag} is not set. +\item \emph{cs1} is not sealed. +\item \emph{cs2} is sealed. +\item \emph{cs1}.\textbf{otype} is reserved. +\item \emph{cs1}.\textbf{address} $\ne$ \emph{cs1}.\textbf{otype}. +\item \emph{cs2}.\textbf{perms} does not grant \textbf{Permit\_Unseal}. +\item \emph{cs2}.\textbf{address} $\lt$ \emph{cs2}.\textbf{base}. +\item \emph{cs2}.\textbf{address} $\ge$ \emph{cs2}.\textbf{top}. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnsealzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCSealEntryexecute}{\saildoclabelled{sailRISCVfclCSealEntryzexecute}{\saildocfcl{Capability register \emph{cd} is replaced with capability register \emph{cs1} and +sealed as a sentry. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Execute}. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCSealEntryzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCInvokeexecute}{\saildoclabelled{sailRISCVfclCInvokezexecute}{\saildocfcl{\textbf{PCC} is set equal to capability register \emph{cs1} and unsealed with the 0th +bit of its \textbf{address} set to 0, whilst \textbf{C31} is set equal to capability +register \emph{cs2} and unsealed. This provides a constrained form of +non-monotonicity, allowing for fast jumps between protection domains, with +\emph{cs1} providing the target domain's code and \emph{cs2} providing the target +domain's data. The capabilities must have a matching \textbf{otype} to ensure the +right data is provided for the given jump target. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs2}.\textbf{tag} is not set. +\item \emph{cs1}.\textbf{otype} is reserved. +\item \emph{cs2}.\textbf{otype} is reserved. +\item \emph{cs1}.\textbf{otype} $\ne$ \emph{cs2}.\textbf{otype}. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_CInvoke}. +\item \emph{cs2}.\textbf{perms} does not grant \textbf{Permit\_CInvoke}. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Execute}. +\item \emph{cs2}.\textbf{perms} grants \textbf{Permit\_Execute}. +\item \emph{cs1}.\textbf{address} $\lt$ \emph{cs1}.\textbf{base}. +\item \emph{cs1}.\textbf{address} $+$ min\_instruction\_bytes $\gt$ \emph{cs1}.\textbf{top}. +\item \emph{cs1}.\textbf{base} is unaligned. +\item \emph{cs1}.\textbf{address} is unaligned, ignoring bit 0. +\end{itemize} + + +\subsection*{Notes} + + +\begin{itemize} +\item From the point of view of security, this needs to be an atomic operation + (i.e. the caller cannot decide to just do some of it, because partial + execution could put the system into an insecure state). From a hardware + perspective, more complex domain-transition implementations (e.g., to + implement function-call semantics or message passing) may need to perform + multiple memory reads and writes, which might take multiple cycles and + complicate control logic. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCInvokezexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCJALRexecute}{\saildoclabelled{sailRISCVfclCJALRzexecute}{\saildocfcl{Capability register \emph{cd} is replaced with the next instruction's \textbf{PCC} and +sealed as a sentry. \textbf{PCC} is replaced with the value of capability +register \emph{cs1} with the 0th bit of its \textbf{address} set to 0 and is unsealed +if it is a sentry. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed and is not a sentry. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Execute}. +\item \emph{cs1}.\textbf{address} $\lt$ \emph{cs1}.\textbf{base}. +\item \emph{cs1}.\textbf{address} $+$ min\_instruction\_bytes $\gt$ \emph{cs1}.\textbf{top}. +\item \emph{cs1}.\textbf{base} is unaligned. +\item \emph{cs1}.\textbf{address} is unaligned, ignoring bit 0. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCJALRzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclLoadDataDDCexecute}{\saildoclabelled{sailRISCVfclLoadDataDDCzexecute}{\saildocfcl{Integer register \emph{rd} is replaced with the signed or unsigned byte, +halfword, word or doubleword located in memory at \textbf{DDC}.\textbf{address} $+$ +\emph{rs1}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \textbf{DDC}.\textbf{tag} is not set. +\item \textbf{DDC} is sealed. +\item \textbf{DDC}.\textbf{perms} does not grant \textbf{Permit\_Load}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $\lt$ \textbf{DDC}.\textbf{base}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $+$ \emph{size} $\gt$ \textbf{DDC}.\textbf{top}. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclLoadDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclLoadDataCapexecute}{\saildoclabelled{sailRISCVfclLoadDataCapzexecute}{\saildocfcl{Integer register \emph{rd} is replaced with the signed or unsigned byte, +halfword, word or doubleword located in memory at \emph{cs1}.\textbf{address}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Load}. +\item \emph{cs1}.\textbf{address} $\lt$ \emph{cs1}.\textbf{base}. +\item \emph{cs1}.\textbf{address} $+$ \emph{size} $\gt$ \emph{cs1}.\textbf{top}. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclLoadDataCapzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclLoadCapDDCexecute}{\saildoclabelled{sailRISCVfclLoadCapDDCzexecute}{\saildocfcl{Capability register \emph{cd} is replaced with the capability located in memory +at \textbf{DDC}.\textbf{address} $+$ \emph{rs1}, and if \textbf{DDC}.\textbf{perms} does not grant +\textbf{Permit\_Load\_Capability} then \emph{cd}.\textbf{tag} is cleared. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \textbf{DDC}.\textbf{tag} is not set. +\item \textbf{DDC} is sealed. +\item \textbf{DDC}.\textbf{perms} does not grant \textbf{Permit\_Load}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $\lt$ \textbf{DDC}.\textbf{base}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $+$ \textbf{CLEN} $/$ 8 $\gt$ \textbf{DDC}.\textbf{top}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} is unaligned, regardless of whether the + implementation supports unaligned data accesses. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclLoadCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclLoadCapCapexecute}{\saildoclabelled{sailRISCVfclLoadCapCapzexecute}{\saildocfcl{Capability register \emph{cd} is replaced with the capability located in memory +at \emph{cs1}.\textbf{address}, and if \emph{cs1}.\textbf{perms} does not grant +\textbf{Permit\_Load\_Capability} then \emph{cd}.\textbf{tag} is cleared. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Load}. +\item \emph{cs1}.\textbf{address} $\lt$ \emph{cs1}.\textbf{base}. +\item \emph{cs1}.\textbf{address} $+$ \textbf{CLEN} $/$ 8 $\gt$ \emph{cs1}.\textbf{top}. +\item \emph{cs1}.\textbf{address} is unaligned, regardless of whether the implementation + supports unaligned data accesses. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclLoadCapCapzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCLoadTagsexecute}{\saildoclabelled{sailRISCVfclCLoadTagszexecute}{\saildocfcl{Integer register \emph{rd} is replaced with the tags of the capabilities located +in memory at and above \emph{cs1}.\textbf{address}. The 0th bit corresponds to the +first capability in memory. The result is coherent with other processors, as +if the corresponding data words had also been loaded. The number of tags +loaded is implementation-defined; typical implementations are expected to +return the tags held in an L1 cache line, and so we use the constant +\hyperref[sailRISCVzcapszyperzycachezyline]{\lstinline{caps_per_cache_line}}. The number of tags loaded must be a power of two, at +least 1, and no more than \textbf{XLEN}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed. +\item \emph{cs1}.\textbf{perms} does not grant both \textbf{Permit\_Load} and + \textbf{Permit\_Load\_Capability}. +\item \emph{cs1}.\textbf{address} $\lt$ \emph{cs1}.\textbf{base}. +\item \emph{cs1}.\textbf{address} $+$ \hyperref[sailRISCVzcapszyperzycachezyline]{\lstinline{caps_per_cache_line}} $\times$ \textbf{CLEN} $/$ 8 + $\gt$ \emph{cs1}.\textbf{top}. +\item \emph{cs1}.\textbf{address} is unaligned. +\item The page table entry for \emph{cs1}.\textbf{address} would cause the tag to be + cleared. +\end{itemize} + + +\subsection*{Notes} + + +\begin{itemize} +\item In order to reduce DRAM traffic, implementations may choose to load only + the tags and not the corresponding data, and may wish to not evict other + cache lines by treating it as a non-temporal/streaming load. + + +\item Software can easily discover the number of tags loaded by an + implementation by storing a series of \textbf{XLEN} capabilities to an aligned + array and performing a \hyperref[sailRISCVzCLoadTags]{\lstinline{CLoadTags}} operation. This need only be done once. + + +\item For heterogeneous multi-core or multi-processor systems, all cores must + return the same number of tags, which will often be based on the smallest + cache line size in the system. + + +\item Unlike \hyperref[sailRISCVzLC]{\lstinline{LC}}, this instuction traps if tags will always be unset due to + lacking \textbf{Permit\_Load\_Capability} or page table entry permissions, since + that is likely indicative of a software bug that could lead to temporal + safety vulnerabilities if capabilities are erroneously missed. + + +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCLoadTagszexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclLoadResDataDDCexecute}{\saildoclabelled{sailRISCVfclLoadResDataDDCzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclLoadResDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclLoadResCapDDCexecute}{\saildoclabelled{sailRISCVfclLoadResCapDDCzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclLoadResCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclLoadResCapexecute}{\saildoclabelled{sailRISCVfclLoadResCapzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclLoadResCapzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclLoadResCapCapexecute}{\saildoclabelled{sailRISCVfclLoadResCapCapzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclLoadResCapCapzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclStoreDataDDCexecute}{\saildoclabelled{sailRISCVfclStoreDataDDCzexecute}{\saildocfcl{The byte, halfword, word or doubleword located in memory at +\textbf{DDC}.\textbf{address} $+$ \emph{rs1} is replaced with integer register \emph{rs2}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \textbf{DDC}.\textbf{tag} is not set. +\item \textbf{DDC} is sealed. +\item \textbf{DDC}.\textbf{perms} does not grant \textbf{Permit\_Store}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $\lt$ \textbf{DDC}.\textbf{base}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $+$ \emph{size} $\gt$ \textbf{DDC}.\textbf{top}. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclStoreDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclStoreDataCapexecute}{\saildoclabelled{sailRISCVfclStoreDataCapzexecute}{\saildocfcl{The byte, halfword, word or doubleword located in memory at +\emph{cs1}.\textbf{address} is replaced with integer register \emph{rs2}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Store}. +\item \emph{cs1}.\textbf{address} $\lt$ \emph{cs1}.\textbf{base}. +\item \emph{cs1}.\textbf{address} $+$ \emph{size} $\gt$ \emph{cs1}.\textbf{top}. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclStoreDataCapzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclStoreCapDDCexecute}{\saildoclabelled{sailRISCVfclStoreCapDDCzexecute}{\saildocfcl{The capability located in memory at \textbf{DDC}.\textbf{address} $+$ \emph{rs1} is +replaced with capability register \emph{cs2}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \textbf{DDC}.\textbf{tag} is not set. +\item \textbf{DDC} is sealed. +\item \textbf{DDC}.\textbf{perms} does not grant \textbf{Permit\_Store}. +\item \textbf{DDC}.\textbf{perms} does not grant \textbf{Permit\_Store\_Capability} and + \emph{cs2}.\textbf{tag} is set. +\item \textbf{DDC}.\textbf{perms} does not grant \textbf{Permit\_Store\_Local\_Capability}, + \emph{cs2}.\textbf{tag} is set and \emph{cs2}.\textbf{perms} does not grant \textbf{Global}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $\lt$ \textbf{DDC}.\textbf{base}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $+$ \textbf{CLEN} $/$ 8 $\gt$ \textbf{DDC}.\textbf{top}. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclStoreCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclStoreCapCapexecute}{\saildoclabelled{sailRISCVfclStoreCapCapzexecute}{\saildocfcl{The capability located in memory at \emph{cs1}.\textbf{address} is replaced with +capability register \emph{cs2}. + +\subsection*{Exceptions} + + +An exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Store}. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Store\_Capability} and + \emph{cs2}.\textbf{tag} is set. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Store\_Local\_Capability}, + \emph{cs2}.\textbf{tag} is set and \emph{cs2}.\textbf{perms} does not grant \textbf{Global}. +\item \emph{cs1}.\textbf{address} $\lt$ \emph{cs1}.\textbf{base}. +\item \emph{cs1}.\textbf{address} $+$ \textbf{CLEN} $\gt$ \emph{cs1}.\textbf{top}. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclStoreCapCapzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclAUIPCCexecute}{\saildoclabelled{sailRISCVfclAUIPCCzexecute}{\saildocfcl{Capability register \emph{cd} is replaced with the contents of \textbf{PCC}, with the +\textbf{address} replaced with \textbf{PCC}.\textbf{address} $+$ \emph{imm} $\times$ 4096. + +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclAUIPCCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclLoadCapImmexecute}{\saildoclabelled{sailRISCVfclLoadCapImmzexecute}{\saildocfcl{In integer mode, capability register \emph{cd} is replaced with the capability +located in memory at \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $+$ \emph{imm}, and if +\textbf{DDC}.\textbf{perms} does not grant \textbf{Permit\_Load\_Capability} then +\emph{cd}.\textbf{tag} is cleared. In capability mode, capability register \emph{cd} is +replaced with the capability located in memory at \emph{cs1}.\textbf{address} $+$ +\emph{imm}, and if \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Load\_Capability} then +\emph{cd}.\textbf{tag} is cleared. + +\subsection*{Exceptions} + + +In integer mode, an exception is raised if: + +\begin{itemize} +\item \textbf{DDC}.\textbf{tag} is not set. +\item \textbf{DDC} is sealed. +\item \textbf{DDC}.\textbf{perms} does not grant \textbf{Permit\_Load}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $+$ \emph{imm} $\lt$ \textbf{DDC}.\textbf{base}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $+$ \emph{imm} $+$ \textbf{CLEN} $/$ 8 $\gt$ + \textbf{DDC}.\textbf{top}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $+$ \emph{imm} is unaligned, regardless of + whether the implementation supports unaligned data accesses. +\end{itemize} + + +In capability mode, an exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Load}. +\item \emph{cs1}.\textbf{address} $+$ \emph{imm} $\lt$ \emph{cs1}.\textbf{base}. +\item \emph{cs1}.\textbf{address} $+$ \emph{imm} $+$ \textbf{CLEN} $/$ 8 $\gt$ \emph{cs1}.\textbf{top}. +\item \emph{cs1}.\textbf{address} $+$ \emph{imm} is unaligned, regardless of whether the + implementation supports unaligned data accesses. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclLoadCapImmzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclStoreCapImmexecute}{\saildoclabelled{sailRISCVfclStoreCapImmzexecute}{\saildocfcl{In integer mode, the capability located in memory at \textbf{DDC}.\textbf{address} $+$ +\emph{rs1} $+$ \emph{imm} is replaced with capability register \emph{cs2}. In capability +mode, the capability located in memory at \emph{cs1}.\textbf{address} $+$ \emph{imm} is +replaced with capability register \emph{cs2}. + +\subsection*{Exceptions} + + +In integer mode, an exception is raised if: + +\begin{itemize} +\item \textbf{DDC}.\textbf{tag} is not set. +\item \textbf{DDC} is sealed. +\item \textbf{DDC}.\textbf{perms} does not grant \textbf{Permit\_Store}. +\item \textbf{DDC}.\textbf{perms} does not grant \textbf{Permit\_Store\_Capability} and + \emph{cs2}.\textbf{tag} is set. +\item \textbf{DDC}.\textbf{perms} does not grant \textbf{Permit\_Store\_Local\_Capability}, + \emph{cs2}.\textbf{tag} is set and \emph{cs2}.\textbf{perms} does not grant \textbf{Global}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $+$ \emph{imm} $\lt$ \textbf{DDC}.\textbf{base}. +\item \textbf{DDC}.\textbf{address} $+$ \emph{rs1} $+$ \emph{imm} $+$ \textbf{CLEN} $/$ 8 $\gt$ + \textbf{DDC}.\textbf{top}. +\end{itemize} + + +In capability mode, an exception is raised if: + +\begin{itemize} +\item \emph{cs1}.\textbf{tag} is not set. +\item \emph{cs1} is sealed. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Store}. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Store\_Capability} and + \emph{cs2}.\textbf{tag} is set. +\item \emph{cs1}.\textbf{perms} does not grant \textbf{Permit\_Store\_Local\_Capability}, + \emph{cs2}.\textbf{tag} is set and \emph{cs2}.\textbf{perms} does not grant \textbf{Global}. +\item \emph{cs1}.\textbf{address} $+$ \emph{imm} $\lt$ \emph{cs1}.\textbf{base}. +\item \emph{cs1}.\textbf{address} $+$ \emph{imm} $+$ \textbf{CLEN} $/$ 8 $\gt$ \emph{cs1}.\textbf{top}. +\end{itemize} +}{\lstinputlisting[language=sail]{sail_latex_riscv/fclStoreCapImmzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclStoreCondDataDDCexecute}{\saildoclabelled{sailRISCVfclStoreCondDataDDCzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclStoreCondDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclStoreCondCapDDCexecute}{\saildoclabelled{sailRISCVfclStoreCondCapDDCzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclStoreCondCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclStoreCondCapexecute}{\saildoclabelled{sailRISCVfclStoreCondCapzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclStoreCondCapzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclStoreCondCapCapexecute}{\saildoclabelled{sailRISCVfclStoreCondCapCapzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclStoreCondCapCapzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclRISCVUnderscoreJALRexecute}{\saildoclabelled{sailRISCVfclRISCVUnderscoreJALRzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclRISCVUnderscoreJALRzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclILLEGALexecute}{\saildoclabelled{sailRISCVfclILLEGALzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclILLEGALzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + +\newcommand{\sailRISCVfclCUnderscoreILLEGALexecute}{\saildoclabelled{sailRISCVfclCUnderscoreILLEGALzexecute}{\saildocfcl{}{\lstinputlisting[language=sail]{sail_latex_riscv/fclCUnderscoreILLEGALzexecute33a689e3a631b9b905b85461d3814943.tex}}}} + + + +\newcommand{\sailRISCVvalprintInsn}{\saildoclabelled{sailRISCVzprintzyinsn}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzprint_insn34adb9871c343ddeeb08d9e768ad4c92.tex}}}} + +\newcommand{\sailRISCVfnprintInsn}{\saildoclabelled{sailRISCVfnzprintzyinsn}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzprint_insn34adb9871c343ddeeb08d9e768ad4c92.tex}}}} + +\newcommand{\sailRISCVoverloadCCCCCCCCCCCCCCCCCCtoStr}{\saildoclabelled{sailRISCVoverloadCCCCCCCCCCCCCCCCCCztozystr}{\saildocoverload{}{\lstinputlisting[language=sail]{sail_latex_riscv/overloadCCCCCCCCCCCCCCCCCCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex}}}} + +\newcommand{\sailRISCVvaldecode}{\saildoclabelled{sailRISCVzdecode}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailRISCVfndecode}{\saildoclabelled{sailRISCVfnzdecode}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzdecodec2b8e713fb767e340b7b488fdcba3aab.tex}}}} + +\newcommand{\sailRISCVvaldecodeCompressed}{\saildoclabelled{sailRISCVzdecodeCompressed}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzdecodecompresseda0c5feab498dd29a69efe0353146e981.tex}}}} + +\newcommand{\sailRISCVfndecodeCompressed}{\saildoclabelled{sailRISCVfnzdecodeCompressed}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzdecodecompresseda0c5feab498dd29a69efe0353146e981.tex}}}} + +\newcommand{\sailRISCVtypeFetchResult}{\saildoclabelled{sailRISCVtypezFetchResult}{\saildoctype{}{\lstinputlisting[language=sail]{sail_latex_riscv/typezfetchresult170a566bc6b6cd6bbb373e14725091ab.tex}}}} + +\newcommand{\sailRISCVvalextInit}{\saildoclabelled{sailRISCVzextzyinit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_initaf8e3807fa5c1bbef01331f40e0f99a4.tex}}}} + +\newcommand{\sailRISCVfnextInit}{\saildoclabelled{sailRISCVfnzextzyinit}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_initaf8e3807fa5c1bbef01331f40e0f99a4.tex}}}} + +\newcommand{\sailRISCVvalextFetchHook}{\saildoclabelled{sailRISCVzextzyfetchzyhook}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_fetch_hookb78ddd15c7be769c4a0783ef122b9767.tex}}}} + +\newcommand{\sailRISCVfnextFetchHook}{\saildoclabelled{sailRISCVfnzextzyfetchzyhook}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_fetch_hookb78ddd15c7be769c4a0783ef122b9767.tex}}}} + +\newcommand{\sailRISCVvalextPreStepHook}{\saildoclabelled{sailRISCVzextzyprezystepzyhook}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_pre_step_hookbaa423b1418b5f3048ae14ba522eabb5.tex}}}} + +\newcommand{\sailRISCVfnextPreStepHook}{\saildoclabelled{sailRISCVfnzextzyprezystepzyhook}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_pre_step_hookbaa423b1418b5f3048ae14ba522eabb5.tex}}}} + +\newcommand{\sailRISCVvalextPostStepHook}{\saildoclabelled{sailRISCVzextzypostzystepzyhook}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_post_step_hook12041b61939f7dc96fabf0eb4cecd40e.tex}}}} + +\newcommand{\sailRISCVfnextPostStepHook}{\saildoclabelled{sailRISCVfnzextzypostzystepzyhook}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_post_step_hook12041b61939f7dc96fabf0eb4cecd40e.tex}}}} + +\newcommand{\sailRISCVvalextPostDecodeHook}{\saildoclabelled{sailRISCVzextzypostzydecodezyhook}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzext_post_decode_hook0ea81b52fdd64a9c28fe27bce7cc93bb.tex}}}} + +\newcommand{\sailRISCVfnextPostDecodeHook}{\saildoclabelled{sailRISCVfnzextzypostzydecodezyhook}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzext_post_decode_hook0ea81b52fdd64a9c28fe27bce7cc93bb.tex}}}} + +\newcommand{\sailRISCVvalisRVC}{\saildoclabelled{sailRISCVzisRVC}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzisrvcd64dda5fc24513d78f480d3583dee004.tex}}}} + +\newcommand{\sailRISCVfnisRVC}{\saildoclabelled{sailRISCVfnzisRVC}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzisrvcd64dda5fc24513d78f480d3583dee004.tex}}}} + +\newcommand{\sailRISCVvalfetch}{\saildoclabelled{sailRISCVzfetch}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzfetch5e1d71b1ad15beedbd2dacb5ddbcd2b6.tex}}}} + +\newcommand{\sailRISCVfnfetch}{\saildoclabelled{sailRISCVfnzfetch}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzfetch5e1d71b1ad15beedbd2dacb5ddbcd2b6.tex}}}} + +\newcommand{\sailRISCVvalstep}{\saildoclabelled{sailRISCVzstep}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzstepb001f84c8bf78b78b44b98d2b7f1f7d7.tex}}}} + +\newcommand{\sailRISCVfnstep}{\saildoclabelled{sailRISCVfnzstep}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzstepb001f84c8bf78b78b44b98d2b7f1f7d7.tex}}}} + +\newcommand{\sailRISCVvalloop}{\saildoclabelled{sailRISCVzloop}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzloop939222c31aec6e03415219d7c5a4ee7a.tex}}}} + +\newcommand{\sailRISCVfnloop}{\saildoclabelled{sailRISCVfnzloop}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzloop939222c31aec6e03415219d7c5a4ee7a.tex}}}} + +\newcommand{\sailRISCVvalinitModel}{\saildoclabelled{sailRISCVzinitzymodel}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinit_model2343c87c630c8dc589bf21c69bd047d3.tex}}}} + +\newcommand{\sailRISCVfninitModel}{\saildoclabelled{sailRISCVfnzinitzymodel}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinit_model2343c87c630c8dc589bf21c69bd047d3.tex}}}} + +\newcommand{\sailRISCVvalGPRstr}{\saildoclabelled{sailRISCVzGPRstr}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzgprstr8a694e087c131a3070bde7e75ad3a570.tex}}}} + +\newcommand{\sailRISCVfnGPRstr}{\saildoclabelled{sailRISCVfnzGPRstr}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzgprstr8a694e087c131a3070bde7e75ad3a570.tex}}}} + +\newcommand{\sailRISCVvalinitialAnalysis}{\saildoclabelled{sailRISCVzinitialzyanalysis}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzinitial_analysis58ef2bf9252095b4ead796191551d1ec.tex}}}} + +\newcommand{\sailRISCVfninitialAnalysis}{\saildoclabelled{sailRISCVfnzinitialzyanalysis}{\saildocfn{}{\lstinputlisting[language=sail]{sail_latex_riscv/fnzinitial_analysis58ef2bf9252095b4ead796191551d1ec.tex}}}} + +\newcommand{\sailRISCVval}[1]{ + \ifstrequal{#1}{Architecture\_of\_num}{\sailRISCVvalArchitectureOfNum}{}% + \ifstrequal{#1}{CPtrCmpOp\_of\_num}{\sailRISCVvalCPtrCmpOpOfNum}{}% + \ifstrequal{#1}{CapExCode}{\sailRISCVvalCapExCode}{}% + \ifstrequal{#1}{CapEx\_of\_num}{\sailRISCVvalCapExOfNum}{}% + \ifstrequal{#1}{ClearRegSet\_of\_num}{\sailRISCVvalClearRegSetOfNum}{}% + \ifstrequal{#1}{EXTS}{\sailRISCVvalEXTS}{}% + \ifstrequal{#1}{EXTZ}{\sailRISCVvalEXTZ}{}% + \ifstrequal{#1}{ExtStatus\_of\_num}{\sailRISCVvalExtStatusOfNum}{}% + \ifstrequal{#1}{FRegStr}{\sailRISCVvalFRegStr}{}% + \ifstrequal{#1}{GPRstr}{\sailRISCVvalGPRstr}{}% + \ifstrequal{#1}{InterruptType\_of\_num}{\sailRISCVvalInterruptTypeOfNum}{}% + \ifstrequal{#1}{MAX}{\sailRISCVvalMAX}{}% + \ifstrequal{#1}{MEMr\_tag}{\sailRISCVvalMEMrTag}{}% + \ifstrequal{#1}{MEMw\_tag}{\sailRISCVvalMEMwTag}{}% + \ifstrequal{#1}{MemoryOpResult\_add\_meta}{\sailRISCVvalMemoryOpResultAddMeta}{}% + \ifstrequal{#1}{MemoryOpResult\_drop\_meta}{\sailRISCVvalMemoryOpResultDropMeta}{}% + \ifstrequal{#1}{Mk\_Counteren}{\sailRISCVvalMkCounteren}{}% + \ifstrequal{#1}{Mk\_Counterin}{\sailRISCVvalMkCounterin}{}% + \ifstrequal{#1}{Mk\_Ext\_PTE\_Bits}{\sailRISCVvalMkExtPTEBits}{}% + \ifstrequal{#1}{Mk\_Fcsr}{\sailRISCVvalMkFcsr}{}% + \ifstrequal{#1}{Mk\_Mcause}{\sailRISCVvalMkMcause}{}% + \ifstrequal{#1}{Mk\_Medeleg}{\sailRISCVvalMkMedeleg}{}% + \ifstrequal{#1}{Mk\_Minterrupts}{\sailRISCVvalMkMinterrupts}{}% + \ifstrequal{#1}{Mk\_Misa}{\sailRISCVvalMkMisa}{}% + \ifstrequal{#1}{Mk\_Mstatus}{\sailRISCVvalMkMstatus}{}% + \ifstrequal{#1}{Mk\_Mtvec}{\sailRISCVvalMkMtvec}{}% + \ifstrequal{#1}{Mk\_PTE\_Bits}{\sailRISCVvalMkPTEBits}{}% + \ifstrequal{#1}{Mk\_Pmpcfg\_ent}{\sailRISCVvalMkPmpcfgEnt}{}% + \ifstrequal{#1}{Mk\_SV32\_PTE}{\sailRISCVvalMkSVThreeTwoPTE}{}% + \ifstrequal{#1}{Mk\_SV32\_Paddr}{\sailRISCVvalMkSVThreeTwoPaddr}{}% + \ifstrequal{#1}{Mk\_SV32\_Vaddr}{\sailRISCVvalMkSVThreeTwoVaddr}{}% + \ifstrequal{#1}{Mk\_SV39\_PTE}{\sailRISCVvalMkSVThreeNinePTE}{}% + \ifstrequal{#1}{Mk\_SV39\_Paddr}{\sailRISCVvalMkSVThreeNinePaddr}{}% + \ifstrequal{#1}{Mk\_SV39\_Vaddr}{\sailRISCVvalMkSVThreeNineVaddr}{}% + \ifstrequal{#1}{Mk\_SV48\_PTE}{\sailRISCVvalMkSVFourEightPTE}{}% + \ifstrequal{#1}{Mk\_SV48\_Paddr}{\sailRISCVvalMkSVFourEightPaddr}{}% + \ifstrequal{#1}{Mk\_SV48\_Vaddr}{\sailRISCVvalMkSVFourEightVaddr}{}% + \ifstrequal{#1}{Mk\_Satp32}{\sailRISCVvalMkSatpThreeTwo}{}% + \ifstrequal{#1}{Mk\_Satp64}{\sailRISCVvalMkSatpSixFour}{}% + \ifstrequal{#1}{Mk\_Sedeleg}{\sailRISCVvalMkSedeleg}{}% + \ifstrequal{#1}{Mk\_Sinterrupts}{\sailRISCVvalMkSinterrupts}{}% + \ifstrequal{#1}{Mk\_Sstatus}{\sailRISCVvalMkSstatus}{}% + \ifstrequal{#1}{Mk\_Uinterrupts}{\sailRISCVvalMkUinterrupts}{}% + \ifstrequal{#1}{Mk\_Ustatus}{\sailRISCVvalMkUstatus}{}% + \ifstrequal{#1}{Mk\_ccsr}{\sailRISCVvalMkCcsr}{}% + \ifstrequal{#1}{Mk\_htif\_cmd}{\sailRISCVvalMkHtifCmd}{}% + \ifstrequal{#1}{PmpAddrMatchType\_of\_num}{\sailRISCVvalPmpAddrMatchTypeOfNum}{}% + \ifstrequal{#1}{Privilege\_of\_num}{\sailRISCVvalPrivilegeOfNum}{}% + \ifstrequal{#1}{RegStr}{\sailRISCVvalRegStr}{}% + \ifstrequal{#1}{Retired\_of\_num}{\sailRISCVvalRetiredOfNum}{}% + \ifstrequal{#1}{SATPMode\_of\_num}{\sailRISCVvalSATPModeOfNum}{}% + \ifstrequal{#1}{TrapVectorMode\_of\_num}{\sailRISCVvalTrapVectorModeOfNum}{}% + \ifstrequal{#1}{\_\_ReadRAM\_Meta}{\sailRISCVvalReadRAMMeta}{}% + \ifstrequal{#1}{\_\_TraceMemoryRead}{\sailRISCVvalTraceMemoryRead}{}% + \ifstrequal{#1}{\_\_TraceMemoryWrite}{\sailRISCVvalTraceMemoryWrite}{}% + \ifstrequal{#1}{\_\_WriteRAM\_Meta}{\sailRISCVvalWriteRAMMeta}{}% + \ifstrequal{#1}{\_\_barrier}{\sailRISCVvalBarrier}{}% + \ifstrequal{#1}{\_\_bitfield\_deref}{\sailRISCVvalBitfieldDeref}{}% + \ifstrequal{#1}{\_\_branch\_announce}{\sailRISCVvalBranchAnnounce}{}% + \ifstrequal{#1}{\_\_cache\_maintenance}{\sailRISCVvalCacheMaintenance}{}% + \ifstrequal{#1}{\_\_deref}{\sailRISCVvalDeref}{}% + \ifstrequal{#1}{\_\_excl\_res}{\sailRISCVvalExclRes}{}% + \ifstrequal{#1}{\_\_id}{\sailRISCVvalId}{}% + \ifstrequal{#1}{\_\_instr\_announce}{\sailRISCVvalInstrAnnounce}{}% + \ifstrequal{#1}{\_\_read\_mem}{\sailRISCVvalReadMem}{}% + \ifstrequal{#1}{\_\_read\_memt}{\sailRISCVvalReadMemt}{}% + \ifstrequal{#1}{\_\_write\_mem}{\sailRISCVvalWriteMem}{}% + \ifstrequal{#1}{\_\_write\_mem\_ea}{\sailRISCVvalWriteMemEa}{}% + \ifstrequal{#1}{\_\_write\_memt}{\sailRISCVvalWriteMemt}{}% + \ifstrequal{#1}{\_get\_Counteren\_CY}{\sailRISCVvalGetCounterenCY}{}% + \ifstrequal{#1}{\_get\_Counteren\_HPM}{\sailRISCVvalGetCounterenHPM}{}% + \ifstrequal{#1}{\_get\_Counteren\_IR}{\sailRISCVvalGetCounterenIR}{}% + \ifstrequal{#1}{\_get\_Counteren\_TM}{\sailRISCVvalGetCounterenTM}{}% + \ifstrequal{#1}{\_get\_Counteren\_bits}{\sailRISCVvalGetCounterenBits}{}% + \ifstrequal{#1}{\_get\_Counterin\_CY}{\sailRISCVvalGetCounterinCY}{}% + \ifstrequal{#1}{\_get\_Counterin\_IR}{\sailRISCVvalGetCounterinIR}{}% + \ifstrequal{#1}{\_get\_Counterin\_bits}{\sailRISCVvalGetCounterinBits}{}% + \ifstrequal{#1}{\_get\_Ext\_PTE\_Bits\_CapRead}{\sailRISCVvalGetExtPTEBitsCapRead}{}% + \ifstrequal{#1}{\_get\_Ext\_PTE\_Bits\_CapWrite}{\sailRISCVvalGetExtPTEBitsCapWrite}{}% + \ifstrequal{#1}{\_get\_Ext\_PTE\_Bits\_bits}{\sailRISCVvalGetExtPTEBitsBits}{}% + \ifstrequal{#1}{\_get\_Fcsr\_FFLAGS}{\sailRISCVvalGetFcsrFFLAGS}{}% + \ifstrequal{#1}{\_get\_Fcsr\_FRM}{\sailRISCVvalGetFcsrFRM}{}% + \ifstrequal{#1}{\_get\_Fcsr\_bits}{\sailRISCVvalGetFcsrBits}{}% + \ifstrequal{#1}{\_get\_Mcause\_Cause}{\sailRISCVvalGetMcauseCause}{}% + \ifstrequal{#1}{\_get\_Mcause\_IsInterrupt}{\sailRISCVvalGetMcauseIsInterrupt}{}% + \ifstrequal{#1}{\_get\_Mcause\_bits}{\sailRISCVvalGetMcauseBits}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Breakpoint}{\sailRISCVvalGetMedelegBreakpoint}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Fetch\_Access\_Fault}{\sailRISCVvalGetMedelegFetchAccessFault}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Fetch\_Addr\_Align}{\sailRISCVvalGetMedelegFetchAddrAlign}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Fetch\_Page\_Fault}{\sailRISCVvalGetMedelegFetchPageFault}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Illegal\_Instr}{\sailRISCVvalGetMedelegIllegalInstr}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Load\_Access\_Fault}{\sailRISCVvalGetMedelegLoadAccessFault}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Load\_Addr\_Align}{\sailRISCVvalGetMedelegLoadAddrAlign}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Load\_Page\_Fault}{\sailRISCVvalGetMedelegLoadPageFault}{}% + \ifstrequal{#1}{\_get\_Medeleg\_MEnvCall}{\sailRISCVvalGetMedelegMEnvCall}{}% + \ifstrequal{#1}{\_get\_Medeleg\_SAMO\_Access\_Fault}{\sailRISCVvalGetMedelegSAMOAccessFault}{}% + \ifstrequal{#1}{\_get\_Medeleg\_SAMO\_Addr\_Align}{\sailRISCVvalGetMedelegSAMOAddrAlign}{}% + \ifstrequal{#1}{\_get\_Medeleg\_SAMO\_Page\_Fault}{\sailRISCVvalGetMedelegSAMOPageFault}{}% + \ifstrequal{#1}{\_get\_Medeleg\_SEnvCall}{\sailRISCVvalGetMedelegSEnvCall}{}% + \ifstrequal{#1}{\_get\_Medeleg\_UEnvCall}{\sailRISCVvalGetMedelegUEnvCall}{}% + \ifstrequal{#1}{\_get\_Medeleg\_bits}{\sailRISCVvalGetMedelegBits}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_MEI}{\sailRISCVvalGetMinterruptsMEI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_MSI}{\sailRISCVvalGetMinterruptsMSI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_MTI}{\sailRISCVvalGetMinterruptsMTI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_SEI}{\sailRISCVvalGetMinterruptsSEI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_SSI}{\sailRISCVvalGetMinterruptsSSI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_STI}{\sailRISCVvalGetMinterruptsSTI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_UEI}{\sailRISCVvalGetMinterruptsUEI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_USI}{\sailRISCVvalGetMinterruptsUSI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_UTI}{\sailRISCVvalGetMinterruptsUTI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_bits}{\sailRISCVvalGetMinterruptsBits}{}% + \ifstrequal{#1}{\_get\_Misa\_A}{\sailRISCVvalGetMisaA}{}% + \ifstrequal{#1}{\_get\_Misa\_B}{\sailRISCVvalGetMisaB}{}% + \ifstrequal{#1}{\_get\_Misa\_C}{\sailRISCVvalGetMisaC}{}% + \ifstrequal{#1}{\_get\_Misa\_D}{\sailRISCVvalGetMisaD}{}% + \ifstrequal{#1}{\_get\_Misa\_E}{\sailRISCVvalGetMisaE}{}% + \ifstrequal{#1}{\_get\_Misa\_F}{\sailRISCVvalGetMisaF}{}% + \ifstrequal{#1}{\_get\_Misa\_G}{\sailRISCVvalGetMisaG}{}% + \ifstrequal{#1}{\_get\_Misa\_H}{\sailRISCVvalGetMisaH}{}% + \ifstrequal{#1}{\_get\_Misa\_I}{\sailRISCVvalGetMisaI}{}% + \ifstrequal{#1}{\_get\_Misa\_J}{\sailRISCVvalGetMisaJ}{}% + \ifstrequal{#1}{\_get\_Misa\_K}{\sailRISCVvalGetMisaK}{}% + \ifstrequal{#1}{\_get\_Misa\_L}{\sailRISCVvalGetMisaL}{}% + \ifstrequal{#1}{\_get\_Misa\_M}{\sailRISCVvalGetMisaM}{}% + \ifstrequal{#1}{\_get\_Misa\_MXL}{\sailRISCVvalGetMisaMXL}{}% + \ifstrequal{#1}{\_get\_Misa\_N}{\sailRISCVvalGetMisaN}{}% + \ifstrequal{#1}{\_get\_Misa\_O}{\sailRISCVvalGetMisaO}{}% + \ifstrequal{#1}{\_get\_Misa\_P}{\sailRISCVvalGetMisaP}{}% + \ifstrequal{#1}{\_get\_Misa\_Q}{\sailRISCVvalGetMisaQ}{}% + \ifstrequal{#1}{\_get\_Misa\_R}{\sailRISCVvalGetMisaR}{}% + \ifstrequal{#1}{\_get\_Misa\_S}{\sailRISCVvalGetMisaS}{}% + \ifstrequal{#1}{\_get\_Misa\_T}{\sailRISCVvalGetMisaT}{}% + \ifstrequal{#1}{\_get\_Misa\_U}{\sailRISCVvalGetMisaU}{}% + \ifstrequal{#1}{\_get\_Misa\_V}{\sailRISCVvalGetMisaV}{}% + \ifstrequal{#1}{\_get\_Misa\_W}{\sailRISCVvalGetMisaW}{}% + \ifstrequal{#1}{\_get\_Misa\_X}{\sailRISCVvalGetMisaX}{}% + \ifstrequal{#1}{\_get\_Misa\_Y}{\sailRISCVvalGetMisaY}{}% + \ifstrequal{#1}{\_get\_Misa\_Z}{\sailRISCVvalGetMisaZ}{}% + \ifstrequal{#1}{\_get\_Misa\_bits}{\sailRISCVvalGetMisaBits}{}% + \ifstrequal{#1}{\_get\_Mstatus\_FS}{\sailRISCVvalGetMstatusFS}{}% + \ifstrequal{#1}{\_get\_Mstatus\_MIE}{\sailRISCVvalGetMstatusMIE}{}% + \ifstrequal{#1}{\_get\_Mstatus\_MPIE}{\sailRISCVvalGetMstatusMPIE}{}% + \ifstrequal{#1}{\_get\_Mstatus\_MPP}{\sailRISCVvalGetMstatusMPP}{}% + \ifstrequal{#1}{\_get\_Mstatus\_MPRV}{\sailRISCVvalGetMstatusMPRV}{}% + \ifstrequal{#1}{\_get\_Mstatus\_MXR}{\sailRISCVvalGetMstatusMXR}{}% + \ifstrequal{#1}{\_get\_Mstatus\_SD}{\sailRISCVvalGetMstatusSD}{}% + \ifstrequal{#1}{\_get\_Mstatus\_SIE}{\sailRISCVvalGetMstatusSIE}{}% + \ifstrequal{#1}{\_get\_Mstatus\_SPIE}{\sailRISCVvalGetMstatusSPIE}{}% + \ifstrequal{#1}{\_get\_Mstatus\_SPP}{\sailRISCVvalGetMstatusSPP}{}% + \ifstrequal{#1}{\_get\_Mstatus\_SUM}{\sailRISCVvalGetMstatusSUM}{}% + \ifstrequal{#1}{\_get\_Mstatus\_TSR}{\sailRISCVvalGetMstatusTSR}{}% + \ifstrequal{#1}{\_get\_Mstatus\_TVM}{\sailRISCVvalGetMstatusTVM}{}% + \ifstrequal{#1}{\_get\_Mstatus\_TW}{\sailRISCVvalGetMstatusTW}{}% + \ifstrequal{#1}{\_get\_Mstatus\_UIE}{\sailRISCVvalGetMstatusUIE}{}% + \ifstrequal{#1}{\_get\_Mstatus\_UPIE}{\sailRISCVvalGetMstatusUPIE}{}% + \ifstrequal{#1}{\_get\_Mstatus\_XS}{\sailRISCVvalGetMstatusXS}{}% + \ifstrequal{#1}{\_get\_Mstatus\_bits}{\sailRISCVvalGetMstatusBits}{}% + \ifstrequal{#1}{\_get\_Mtvec\_Base}{\sailRISCVvalGetMtvecBase}{}% + \ifstrequal{#1}{\_get\_Mtvec\_Mode}{\sailRISCVvalGetMtvecMode}{}% + \ifstrequal{#1}{\_get\_Mtvec\_bits}{\sailRISCVvalGetMtvecBits}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_A}{\sailRISCVvalGetPTEBitsA}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_D}{\sailRISCVvalGetPTEBitsD}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_G}{\sailRISCVvalGetPTEBitsG}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_R}{\sailRISCVvalGetPTEBitsR}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_U}{\sailRISCVvalGetPTEBitsU}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_V}{\sailRISCVvalGetPTEBitsV}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_W}{\sailRISCVvalGetPTEBitsW}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_X}{\sailRISCVvalGetPTEBitsX}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_bits}{\sailRISCVvalGetPTEBitsBits}{}% + \ifstrequal{#1}{\_get\_Pmpcfg\_ent\_A}{\sailRISCVvalGetPmpcfgEntA}{}% + \ifstrequal{#1}{\_get\_Pmpcfg\_ent\_L}{\sailRISCVvalGetPmpcfgEntL}{}% + \ifstrequal{#1}{\_get\_Pmpcfg\_ent\_R}{\sailRISCVvalGetPmpcfgEntR}{}% + \ifstrequal{#1}{\_get\_Pmpcfg\_ent\_W}{\sailRISCVvalGetPmpcfgEntW}{}% + \ifstrequal{#1}{\_get\_Pmpcfg\_ent\_X}{\sailRISCVvalGetPmpcfgEntX}{}% + \ifstrequal{#1}{\_get\_Pmpcfg\_ent\_bits}{\sailRISCVvalGetPmpcfgEntBits}{}% + \ifstrequal{#1}{\_get\_SV32\_PTE\_BITS}{\sailRISCVvalGetSVThreeTwoPTEBITS}{}% + \ifstrequal{#1}{\_get\_SV32\_PTE\_PPNi}{\sailRISCVvalGetSVThreeTwoPTEPPNi}{}% + \ifstrequal{#1}{\_get\_SV32\_PTE\_RSW}{\sailRISCVvalGetSVThreeTwoPTERSW}{}% + \ifstrequal{#1}{\_get\_SV32\_PTE\_bits}{\sailRISCVvalGetSVThreeTwoPTEBits}{}% + \ifstrequal{#1}{\_get\_SV32\_Paddr\_PPNi}{\sailRISCVvalGetSVThreeTwoPaddrPPNi}{}% + \ifstrequal{#1}{\_get\_SV32\_Paddr\_PgOfs}{\sailRISCVvalGetSVThreeTwoPaddrPgOfs}{}% + \ifstrequal{#1}{\_get\_SV32\_Paddr\_bits}{\sailRISCVvalGetSVThreeTwoPaddrBits}{}% + \ifstrequal{#1}{\_get\_SV32\_Vaddr\_PgOfs}{\sailRISCVvalGetSVThreeTwoVaddrPgOfs}{}% + \ifstrequal{#1}{\_get\_SV32\_Vaddr\_VPNi}{\sailRISCVvalGetSVThreeTwoVaddrVPNi}{}% + \ifstrequal{#1}{\_get\_SV32\_Vaddr\_bits}{\sailRISCVvalGetSVThreeTwoVaddrBits}{}% + \ifstrequal{#1}{\_get\_SV39\_PTE\_BITS}{\sailRISCVvalGetSVThreeNinePTEBITS}{}% + \ifstrequal{#1}{\_get\_SV39\_PTE\_Ext}{\sailRISCVvalGetSVThreeNinePTEExt}{}% + \ifstrequal{#1}{\_get\_SV39\_PTE\_PPNi}{\sailRISCVvalGetSVThreeNinePTEPPNi}{}% + \ifstrequal{#1}{\_get\_SV39\_PTE\_RSW}{\sailRISCVvalGetSVThreeNinePTERSW}{}% + \ifstrequal{#1}{\_get\_SV39\_PTE\_bits}{\sailRISCVvalGetSVThreeNinePTEBits}{}% + \ifstrequal{#1}{\_get\_SV39\_Paddr\_PPNi}{\sailRISCVvalGetSVThreeNinePaddrPPNi}{}% + \ifstrequal{#1}{\_get\_SV39\_Paddr\_PgOfs}{\sailRISCVvalGetSVThreeNinePaddrPgOfs}{}% + \ifstrequal{#1}{\_get\_SV39\_Paddr\_bits}{\sailRISCVvalGetSVThreeNinePaddrBits}{}% + \ifstrequal{#1}{\_get\_SV39\_Vaddr\_PgOfs}{\sailRISCVvalGetSVThreeNineVaddrPgOfs}{}% + \ifstrequal{#1}{\_get\_SV39\_Vaddr\_VPNi}{\sailRISCVvalGetSVThreeNineVaddrVPNi}{}% + \ifstrequal{#1}{\_get\_SV39\_Vaddr\_bits}{\sailRISCVvalGetSVThreeNineVaddrBits}{}% + \ifstrequal{#1}{\_get\_SV48\_PTE\_BITS}{\sailRISCVvalGetSVFourEightPTEBITS}{}% + \ifstrequal{#1}{\_get\_SV48\_PTE\_Ext}{\sailRISCVvalGetSVFourEightPTEExt}{}% + \ifstrequal{#1}{\_get\_SV48\_PTE\_PPNi}{\sailRISCVvalGetSVFourEightPTEPPNi}{}% + \ifstrequal{#1}{\_get\_SV48\_PTE\_RSW}{\sailRISCVvalGetSVFourEightPTERSW}{}% + \ifstrequal{#1}{\_get\_SV48\_PTE\_bits}{\sailRISCVvalGetSVFourEightPTEBits}{}% + \ifstrequal{#1}{\_get\_SV48\_Paddr\_PPNi}{\sailRISCVvalGetSVFourEightPaddrPPNi}{}% + \ifstrequal{#1}{\_get\_SV48\_Paddr\_PgOfs}{\sailRISCVvalGetSVFourEightPaddrPgOfs}{}% + \ifstrequal{#1}{\_get\_SV48\_Paddr\_bits}{\sailRISCVvalGetSVFourEightPaddrBits}{}% + \ifstrequal{#1}{\_get\_SV48\_Vaddr\_PgOfs}{\sailRISCVvalGetSVFourEightVaddrPgOfs}{}% + \ifstrequal{#1}{\_get\_SV48\_Vaddr\_VPNi}{\sailRISCVvalGetSVFourEightVaddrVPNi}{}% + \ifstrequal{#1}{\_get\_SV48\_Vaddr\_bits}{\sailRISCVvalGetSVFourEightVaddrBits}{}% + \ifstrequal{#1}{\_get\_Satp32\_Asid}{\sailRISCVvalGetSatpThreeTwoAsid}{}% + \ifstrequal{#1}{\_get\_Satp32\_Mode}{\sailRISCVvalGetSatpThreeTwoMode}{}% + \ifstrequal{#1}{\_get\_Satp32\_PPN}{\sailRISCVvalGetSatpThreeTwoPPN}{}% + \ifstrequal{#1}{\_get\_Satp32\_bits}{\sailRISCVvalGetSatpThreeTwoBits}{}% + \ifstrequal{#1}{\_get\_Satp64\_Asid}{\sailRISCVvalGetSatpSixFourAsid}{}% + \ifstrequal{#1}{\_get\_Satp64\_Mode}{\sailRISCVvalGetSatpSixFourMode}{}% + \ifstrequal{#1}{\_get\_Satp64\_PPN}{\sailRISCVvalGetSatpSixFourPPN}{}% + \ifstrequal{#1}{\_get\_Satp64\_bits}{\sailRISCVvalGetSatpSixFourBits}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_Breakpoint}{\sailRISCVvalGetSedelegBreakpoint}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_Fetch\_Access\_Fault}{\sailRISCVvalGetSedelegFetchAccessFault}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_Fetch\_Addr\_Align}{\sailRISCVvalGetSedelegFetchAddrAlign}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_Illegal\_Instr}{\sailRISCVvalGetSedelegIllegalInstr}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_Load\_Access\_Fault}{\sailRISCVvalGetSedelegLoadAccessFault}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_Load\_Addr\_Align}{\sailRISCVvalGetSedelegLoadAddrAlign}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_SAMO\_Access\_Fault}{\sailRISCVvalGetSedelegSAMOAccessFault}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_SAMO\_Addr\_Align}{\sailRISCVvalGetSedelegSAMOAddrAlign}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_UEnvCall}{\sailRISCVvalGetSedelegUEnvCall}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_bits}{\sailRISCVvalGetSedelegBits}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_SEI}{\sailRISCVvalGetSinterruptsSEI}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_SSI}{\sailRISCVvalGetSinterruptsSSI}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_STI}{\sailRISCVvalGetSinterruptsSTI}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_UEI}{\sailRISCVvalGetSinterruptsUEI}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_USI}{\sailRISCVvalGetSinterruptsUSI}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_UTI}{\sailRISCVvalGetSinterruptsUTI}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_bits}{\sailRISCVvalGetSinterruptsBits}{}% + \ifstrequal{#1}{\_get\_Sstatus\_FS}{\sailRISCVvalGetSstatusFS}{}% + \ifstrequal{#1}{\_get\_Sstatus\_MXR}{\sailRISCVvalGetSstatusMXR}{}% + \ifstrequal{#1}{\_get\_Sstatus\_SD}{\sailRISCVvalGetSstatusSD}{}% + \ifstrequal{#1}{\_get\_Sstatus\_SIE}{\sailRISCVvalGetSstatusSIE}{}% + \ifstrequal{#1}{\_get\_Sstatus\_SPIE}{\sailRISCVvalGetSstatusSPIE}{}% + \ifstrequal{#1}{\_get\_Sstatus\_SPP}{\sailRISCVvalGetSstatusSPP}{}% + \ifstrequal{#1}{\_get\_Sstatus\_SUM}{\sailRISCVvalGetSstatusSUM}{}% + \ifstrequal{#1}{\_get\_Sstatus\_UIE}{\sailRISCVvalGetSstatusUIE}{}% + \ifstrequal{#1}{\_get\_Sstatus\_UPIE}{\sailRISCVvalGetSstatusUPIE}{}% + \ifstrequal{#1}{\_get\_Sstatus\_XS}{\sailRISCVvalGetSstatusXS}{}% + \ifstrequal{#1}{\_get\_Sstatus\_bits}{\sailRISCVvalGetSstatusBits}{}% + \ifstrequal{#1}{\_get\_Uinterrupts\_UEI}{\sailRISCVvalGetUinterruptsUEI}{}% + \ifstrequal{#1}{\_get\_Uinterrupts\_USI}{\sailRISCVvalGetUinterruptsUSI}{}% + \ifstrequal{#1}{\_get\_Uinterrupts\_UTI}{\sailRISCVvalGetUinterruptsUTI}{}% + \ifstrequal{#1}{\_get\_Uinterrupts\_bits}{\sailRISCVvalGetUinterruptsBits}{}% + \ifstrequal{#1}{\_get\_Ustatus\_UIE}{\sailRISCVvalGetUstatusUIE}{}% + \ifstrequal{#1}{\_get\_Ustatus\_UPIE}{\sailRISCVvalGetUstatusUPIE}{}% + \ifstrequal{#1}{\_get\_Ustatus\_bits}{\sailRISCVvalGetUstatusBits}{}% + \ifstrequal{#1}{\_get\_ccsr\_bits}{\sailRISCVvalGetCcsrBits}{}% + \ifstrequal{#1}{\_get\_ccsr\_cap\_idx}{\sailRISCVvalGetCcsrCapIdx}{}% + \ifstrequal{#1}{\_get\_ccsr\_cause}{\sailRISCVvalGetCcsrCause}{}% + \ifstrequal{#1}{\_get\_ccsr\_d}{\sailRISCVvalGetCcsrD}{}% + \ifstrequal{#1}{\_get\_ccsr\_e}{\sailRISCVvalGetCcsrE}{}% + \ifstrequal{#1}{\_get\_htif\_cmd\_bits}{\sailRISCVvalGetHtifCmdBits}{}% + \ifstrequal{#1}{\_get\_htif\_cmd\_cmd}{\sailRISCVvalGetHtifCmdCmd}{}% + \ifstrequal{#1}{\_get\_htif\_cmd\_device}{\sailRISCVvalGetHtifCmdDevice}{}% + \ifstrequal{#1}{\_get\_htif\_cmd\_payload}{\sailRISCVvalGetHtifCmdPayload}{}% + \ifstrequal{#1}{\_reg\_deref}{\sailRISCVvalRegDeref}{}% + \ifstrequal{#1}{\_set\_Counteren\_CY}{\sailRISCVvalSetCounterenCY}{}% + \ifstrequal{#1}{\_set\_Counteren\_HPM}{\sailRISCVvalSetCounterenHPM}{}% + \ifstrequal{#1}{\_set\_Counteren\_IR}{\sailRISCVvalSetCounterenIR}{}% + \ifstrequal{#1}{\_set\_Counteren\_TM}{\sailRISCVvalSetCounterenTM}{}% + \ifstrequal{#1}{\_set\_Counteren\_bits}{\sailRISCVvalSetCounterenBits}{}% + \ifstrequal{#1}{\_set\_Counterin\_CY}{\sailRISCVvalSetCounterinCY}{}% + \ifstrequal{#1}{\_set\_Counterin\_IR}{\sailRISCVvalSetCounterinIR}{}% + \ifstrequal{#1}{\_set\_Counterin\_bits}{\sailRISCVvalSetCounterinBits}{}% + \ifstrequal{#1}{\_set\_Ext\_PTE\_Bits\_CapRead}{\sailRISCVvalSetExtPTEBitsCapRead}{}% + \ifstrequal{#1}{\_set\_Ext\_PTE\_Bits\_CapWrite}{\sailRISCVvalSetExtPTEBitsCapWrite}{}% + \ifstrequal{#1}{\_set\_Ext\_PTE\_Bits\_bits}{\sailRISCVvalSetExtPTEBitsBits}{}% + \ifstrequal{#1}{\_set\_Fcsr\_FFLAGS}{\sailRISCVvalSetFcsrFFLAGS}{}% + \ifstrequal{#1}{\_set\_Fcsr\_FRM}{\sailRISCVvalSetFcsrFRM}{}% + \ifstrequal{#1}{\_set\_Fcsr\_bits}{\sailRISCVvalSetFcsrBits}{}% + \ifstrequal{#1}{\_set\_Mcause\_Cause}{\sailRISCVvalSetMcauseCause}{}% + \ifstrequal{#1}{\_set\_Mcause\_IsInterrupt}{\sailRISCVvalSetMcauseIsInterrupt}{}% + \ifstrequal{#1}{\_set\_Mcause\_bits}{\sailRISCVvalSetMcauseBits}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Breakpoint}{\sailRISCVvalSetMedelegBreakpoint}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Fetch\_Access\_Fault}{\sailRISCVvalSetMedelegFetchAccessFault}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Fetch\_Addr\_Align}{\sailRISCVvalSetMedelegFetchAddrAlign}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Fetch\_Page\_Fault}{\sailRISCVvalSetMedelegFetchPageFault}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Illegal\_Instr}{\sailRISCVvalSetMedelegIllegalInstr}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Load\_Access\_Fault}{\sailRISCVvalSetMedelegLoadAccessFault}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Load\_Addr\_Align}{\sailRISCVvalSetMedelegLoadAddrAlign}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Load\_Page\_Fault}{\sailRISCVvalSetMedelegLoadPageFault}{}% + \ifstrequal{#1}{\_set\_Medeleg\_MEnvCall}{\sailRISCVvalSetMedelegMEnvCall}{}% + \ifstrequal{#1}{\_set\_Medeleg\_SAMO\_Access\_Fault}{\sailRISCVvalSetMedelegSAMOAccessFault}{}% + \ifstrequal{#1}{\_set\_Medeleg\_SAMO\_Addr\_Align}{\sailRISCVvalSetMedelegSAMOAddrAlign}{}% + \ifstrequal{#1}{\_set\_Medeleg\_SAMO\_Page\_Fault}{\sailRISCVvalSetMedelegSAMOPageFault}{}% + \ifstrequal{#1}{\_set\_Medeleg\_SEnvCall}{\sailRISCVvalSetMedelegSEnvCall}{}% + \ifstrequal{#1}{\_set\_Medeleg\_UEnvCall}{\sailRISCVvalSetMedelegUEnvCall}{}% + \ifstrequal{#1}{\_set\_Medeleg\_bits}{\sailRISCVvalSetMedelegBits}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_MEI}{\sailRISCVvalSetMinterruptsMEI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_MSI}{\sailRISCVvalSetMinterruptsMSI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_MTI}{\sailRISCVvalSetMinterruptsMTI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_SEI}{\sailRISCVvalSetMinterruptsSEI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_SSI}{\sailRISCVvalSetMinterruptsSSI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_STI}{\sailRISCVvalSetMinterruptsSTI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_UEI}{\sailRISCVvalSetMinterruptsUEI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_USI}{\sailRISCVvalSetMinterruptsUSI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_UTI}{\sailRISCVvalSetMinterruptsUTI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_bits}{\sailRISCVvalSetMinterruptsBits}{}% + \ifstrequal{#1}{\_set\_Misa\_A}{\sailRISCVvalSetMisaA}{}% + \ifstrequal{#1}{\_set\_Misa\_B}{\sailRISCVvalSetMisaB}{}% + \ifstrequal{#1}{\_set\_Misa\_C}{\sailRISCVvalSetMisaC}{}% + \ifstrequal{#1}{\_set\_Misa\_D}{\sailRISCVvalSetMisaD}{}% + \ifstrequal{#1}{\_set\_Misa\_E}{\sailRISCVvalSetMisaE}{}% + \ifstrequal{#1}{\_set\_Misa\_F}{\sailRISCVvalSetMisaF}{}% + \ifstrequal{#1}{\_set\_Misa\_G}{\sailRISCVvalSetMisaG}{}% + \ifstrequal{#1}{\_set\_Misa\_H}{\sailRISCVvalSetMisaH}{}% + \ifstrequal{#1}{\_set\_Misa\_I}{\sailRISCVvalSetMisaI}{}% + \ifstrequal{#1}{\_set\_Misa\_J}{\sailRISCVvalSetMisaJ}{}% + \ifstrequal{#1}{\_set\_Misa\_K}{\sailRISCVvalSetMisaK}{}% + \ifstrequal{#1}{\_set\_Misa\_L}{\sailRISCVvalSetMisaL}{}% + \ifstrequal{#1}{\_set\_Misa\_M}{\sailRISCVvalSetMisaM}{}% + \ifstrequal{#1}{\_set\_Misa\_MXL}{\sailRISCVvalSetMisaMXL}{}% + \ifstrequal{#1}{\_set\_Misa\_N}{\sailRISCVvalSetMisaN}{}% + \ifstrequal{#1}{\_set\_Misa\_O}{\sailRISCVvalSetMisaO}{}% + \ifstrequal{#1}{\_set\_Misa\_P}{\sailRISCVvalSetMisaP}{}% + \ifstrequal{#1}{\_set\_Misa\_Q}{\sailRISCVvalSetMisaQ}{}% + \ifstrequal{#1}{\_set\_Misa\_R}{\sailRISCVvalSetMisaR}{}% + \ifstrequal{#1}{\_set\_Misa\_S}{\sailRISCVvalSetMisaS}{}% + \ifstrequal{#1}{\_set\_Misa\_T}{\sailRISCVvalSetMisaT}{}% + \ifstrequal{#1}{\_set\_Misa\_U}{\sailRISCVvalSetMisaU}{}% + \ifstrequal{#1}{\_set\_Misa\_V}{\sailRISCVvalSetMisaV}{}% + \ifstrequal{#1}{\_set\_Misa\_W}{\sailRISCVvalSetMisaW}{}% + \ifstrequal{#1}{\_set\_Misa\_X}{\sailRISCVvalSetMisaX}{}% + \ifstrequal{#1}{\_set\_Misa\_Y}{\sailRISCVvalSetMisaY}{}% + \ifstrequal{#1}{\_set\_Misa\_Z}{\sailRISCVvalSetMisaZ}{}% + \ifstrequal{#1}{\_set\_Misa\_bits}{\sailRISCVvalSetMisaBits}{}% + \ifstrequal{#1}{\_set\_Mstatus\_FS}{\sailRISCVvalSetMstatusFS}{}% + \ifstrequal{#1}{\_set\_Mstatus\_MIE}{\sailRISCVvalSetMstatusMIE}{}% + \ifstrequal{#1}{\_set\_Mstatus\_MPIE}{\sailRISCVvalSetMstatusMPIE}{}% + \ifstrequal{#1}{\_set\_Mstatus\_MPP}{\sailRISCVvalSetMstatusMPP}{}% + \ifstrequal{#1}{\_set\_Mstatus\_MPRV}{\sailRISCVvalSetMstatusMPRV}{}% + \ifstrequal{#1}{\_set\_Mstatus\_MXR}{\sailRISCVvalSetMstatusMXR}{}% + \ifstrequal{#1}{\_set\_Mstatus\_SD}{\sailRISCVvalSetMstatusSD}{}% + \ifstrequal{#1}{\_set\_Mstatus\_SIE}{\sailRISCVvalSetMstatusSIE}{}% + \ifstrequal{#1}{\_set\_Mstatus\_SPIE}{\sailRISCVvalSetMstatusSPIE}{}% + \ifstrequal{#1}{\_set\_Mstatus\_SPP}{\sailRISCVvalSetMstatusSPP}{}% + \ifstrequal{#1}{\_set\_Mstatus\_SUM}{\sailRISCVvalSetMstatusSUM}{}% + \ifstrequal{#1}{\_set\_Mstatus\_TSR}{\sailRISCVvalSetMstatusTSR}{}% + \ifstrequal{#1}{\_set\_Mstatus\_TVM}{\sailRISCVvalSetMstatusTVM}{}% + \ifstrequal{#1}{\_set\_Mstatus\_TW}{\sailRISCVvalSetMstatusTW}{}% + \ifstrequal{#1}{\_set\_Mstatus\_UIE}{\sailRISCVvalSetMstatusUIE}{}% + \ifstrequal{#1}{\_set\_Mstatus\_UPIE}{\sailRISCVvalSetMstatusUPIE}{}% + \ifstrequal{#1}{\_set\_Mstatus\_XS}{\sailRISCVvalSetMstatusXS}{}% + \ifstrequal{#1}{\_set\_Mstatus\_bits}{\sailRISCVvalSetMstatusBits}{}% + \ifstrequal{#1}{\_set\_Mtvec\_Base}{\sailRISCVvalSetMtvecBase}{}% + \ifstrequal{#1}{\_set\_Mtvec\_Mode}{\sailRISCVvalSetMtvecMode}{}% + \ifstrequal{#1}{\_set\_Mtvec\_bits}{\sailRISCVvalSetMtvecBits}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_A}{\sailRISCVvalSetPTEBitsA}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_D}{\sailRISCVvalSetPTEBitsD}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_G}{\sailRISCVvalSetPTEBitsG}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_R}{\sailRISCVvalSetPTEBitsR}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_U}{\sailRISCVvalSetPTEBitsU}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_V}{\sailRISCVvalSetPTEBitsV}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_W}{\sailRISCVvalSetPTEBitsW}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_X}{\sailRISCVvalSetPTEBitsX}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_bits}{\sailRISCVvalSetPTEBitsBits}{}% + \ifstrequal{#1}{\_set\_Pmpcfg\_ent\_A}{\sailRISCVvalSetPmpcfgEntA}{}% + \ifstrequal{#1}{\_set\_Pmpcfg\_ent\_L}{\sailRISCVvalSetPmpcfgEntL}{}% + \ifstrequal{#1}{\_set\_Pmpcfg\_ent\_R}{\sailRISCVvalSetPmpcfgEntR}{}% + \ifstrequal{#1}{\_set\_Pmpcfg\_ent\_W}{\sailRISCVvalSetPmpcfgEntW}{}% + \ifstrequal{#1}{\_set\_Pmpcfg\_ent\_X}{\sailRISCVvalSetPmpcfgEntX}{}% + \ifstrequal{#1}{\_set\_Pmpcfg\_ent\_bits}{\sailRISCVvalSetPmpcfgEntBits}{}% + \ifstrequal{#1}{\_set\_SV32\_PTE\_BITS}{\sailRISCVvalSetSVThreeTwoPTEBITS}{}% + \ifstrequal{#1}{\_set\_SV32\_PTE\_PPNi}{\sailRISCVvalSetSVThreeTwoPTEPPNi}{}% + \ifstrequal{#1}{\_set\_SV32\_PTE\_RSW}{\sailRISCVvalSetSVThreeTwoPTERSW}{}% + \ifstrequal{#1}{\_set\_SV32\_PTE\_bits}{\sailRISCVvalSetSVThreeTwoPTEBits}{}% + \ifstrequal{#1}{\_set\_SV32\_Paddr\_PPNi}{\sailRISCVvalSetSVThreeTwoPaddrPPNi}{}% + \ifstrequal{#1}{\_set\_SV32\_Paddr\_PgOfs}{\sailRISCVvalSetSVThreeTwoPaddrPgOfs}{}% + \ifstrequal{#1}{\_set\_SV32\_Paddr\_bits}{\sailRISCVvalSetSVThreeTwoPaddrBits}{}% + \ifstrequal{#1}{\_set\_SV32\_Vaddr\_PgOfs}{\sailRISCVvalSetSVThreeTwoVaddrPgOfs}{}% + \ifstrequal{#1}{\_set\_SV32\_Vaddr\_VPNi}{\sailRISCVvalSetSVThreeTwoVaddrVPNi}{}% + \ifstrequal{#1}{\_set\_SV32\_Vaddr\_bits}{\sailRISCVvalSetSVThreeTwoVaddrBits}{}% + \ifstrequal{#1}{\_set\_SV39\_PTE\_BITS}{\sailRISCVvalSetSVThreeNinePTEBITS}{}% + \ifstrequal{#1}{\_set\_SV39\_PTE\_Ext}{\sailRISCVvalSetSVThreeNinePTEExt}{}% + \ifstrequal{#1}{\_set\_SV39\_PTE\_PPNi}{\sailRISCVvalSetSVThreeNinePTEPPNi}{}% + \ifstrequal{#1}{\_set\_SV39\_PTE\_RSW}{\sailRISCVvalSetSVThreeNinePTERSW}{}% + \ifstrequal{#1}{\_set\_SV39\_PTE\_bits}{\sailRISCVvalSetSVThreeNinePTEBits}{}% + \ifstrequal{#1}{\_set\_SV39\_Paddr\_PPNi}{\sailRISCVvalSetSVThreeNinePaddrPPNi}{}% + \ifstrequal{#1}{\_set\_SV39\_Paddr\_PgOfs}{\sailRISCVvalSetSVThreeNinePaddrPgOfs}{}% + \ifstrequal{#1}{\_set\_SV39\_Paddr\_bits}{\sailRISCVvalSetSVThreeNinePaddrBits}{}% + \ifstrequal{#1}{\_set\_SV39\_Vaddr\_PgOfs}{\sailRISCVvalSetSVThreeNineVaddrPgOfs}{}% + \ifstrequal{#1}{\_set\_SV39\_Vaddr\_VPNi}{\sailRISCVvalSetSVThreeNineVaddrVPNi}{}% + \ifstrequal{#1}{\_set\_SV39\_Vaddr\_bits}{\sailRISCVvalSetSVThreeNineVaddrBits}{}% + \ifstrequal{#1}{\_set\_SV48\_PTE\_BITS}{\sailRISCVvalSetSVFourEightPTEBITS}{}% + \ifstrequal{#1}{\_set\_SV48\_PTE\_Ext}{\sailRISCVvalSetSVFourEightPTEExt}{}% + \ifstrequal{#1}{\_set\_SV48\_PTE\_PPNi}{\sailRISCVvalSetSVFourEightPTEPPNi}{}% + \ifstrequal{#1}{\_set\_SV48\_PTE\_RSW}{\sailRISCVvalSetSVFourEightPTERSW}{}% + \ifstrequal{#1}{\_set\_SV48\_PTE\_bits}{\sailRISCVvalSetSVFourEightPTEBits}{}% + \ifstrequal{#1}{\_set\_SV48\_Paddr\_PPNi}{\sailRISCVvalSetSVFourEightPaddrPPNi}{}% + \ifstrequal{#1}{\_set\_SV48\_Paddr\_PgOfs}{\sailRISCVvalSetSVFourEightPaddrPgOfs}{}% + \ifstrequal{#1}{\_set\_SV48\_Paddr\_bits}{\sailRISCVvalSetSVFourEightPaddrBits}{}% + \ifstrequal{#1}{\_set\_SV48\_Vaddr\_PgOfs}{\sailRISCVvalSetSVFourEightVaddrPgOfs}{}% + \ifstrequal{#1}{\_set\_SV48\_Vaddr\_VPNi}{\sailRISCVvalSetSVFourEightVaddrVPNi}{}% + \ifstrequal{#1}{\_set\_SV48\_Vaddr\_bits}{\sailRISCVvalSetSVFourEightVaddrBits}{}% + \ifstrequal{#1}{\_set\_Satp32\_Asid}{\sailRISCVvalSetSatpThreeTwoAsid}{}% + \ifstrequal{#1}{\_set\_Satp32\_Mode}{\sailRISCVvalSetSatpThreeTwoMode}{}% + \ifstrequal{#1}{\_set\_Satp32\_PPN}{\sailRISCVvalSetSatpThreeTwoPPN}{}% + \ifstrequal{#1}{\_set\_Satp32\_bits}{\sailRISCVvalSetSatpThreeTwoBits}{}% + \ifstrequal{#1}{\_set\_Satp64\_Asid}{\sailRISCVvalSetSatpSixFourAsid}{}% + \ifstrequal{#1}{\_set\_Satp64\_Mode}{\sailRISCVvalSetSatpSixFourMode}{}% + \ifstrequal{#1}{\_set\_Satp64\_PPN}{\sailRISCVvalSetSatpSixFourPPN}{}% + \ifstrequal{#1}{\_set\_Satp64\_bits}{\sailRISCVvalSetSatpSixFourBits}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_Breakpoint}{\sailRISCVvalSetSedelegBreakpoint}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_Fetch\_Access\_Fault}{\sailRISCVvalSetSedelegFetchAccessFault}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_Fetch\_Addr\_Align}{\sailRISCVvalSetSedelegFetchAddrAlign}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_Illegal\_Instr}{\sailRISCVvalSetSedelegIllegalInstr}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_Load\_Access\_Fault}{\sailRISCVvalSetSedelegLoadAccessFault}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_Load\_Addr\_Align}{\sailRISCVvalSetSedelegLoadAddrAlign}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_SAMO\_Access\_Fault}{\sailRISCVvalSetSedelegSAMOAccessFault}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_SAMO\_Addr\_Align}{\sailRISCVvalSetSedelegSAMOAddrAlign}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_UEnvCall}{\sailRISCVvalSetSedelegUEnvCall}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_bits}{\sailRISCVvalSetSedelegBits}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_SEI}{\sailRISCVvalSetSinterruptsSEI}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_SSI}{\sailRISCVvalSetSinterruptsSSI}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_STI}{\sailRISCVvalSetSinterruptsSTI}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_UEI}{\sailRISCVvalSetSinterruptsUEI}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_USI}{\sailRISCVvalSetSinterruptsUSI}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_UTI}{\sailRISCVvalSetSinterruptsUTI}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_bits}{\sailRISCVvalSetSinterruptsBits}{}% + \ifstrequal{#1}{\_set\_Sstatus\_FS}{\sailRISCVvalSetSstatusFS}{}% + \ifstrequal{#1}{\_set\_Sstatus\_MXR}{\sailRISCVvalSetSstatusMXR}{}% + \ifstrequal{#1}{\_set\_Sstatus\_SD}{\sailRISCVvalSetSstatusSD}{}% + \ifstrequal{#1}{\_set\_Sstatus\_SIE}{\sailRISCVvalSetSstatusSIE}{}% + \ifstrequal{#1}{\_set\_Sstatus\_SPIE}{\sailRISCVvalSetSstatusSPIE}{}% + \ifstrequal{#1}{\_set\_Sstatus\_SPP}{\sailRISCVvalSetSstatusSPP}{}% + \ifstrequal{#1}{\_set\_Sstatus\_SUM}{\sailRISCVvalSetSstatusSUM}{}% + \ifstrequal{#1}{\_set\_Sstatus\_UIE}{\sailRISCVvalSetSstatusUIE}{}% + \ifstrequal{#1}{\_set\_Sstatus\_UPIE}{\sailRISCVvalSetSstatusUPIE}{}% + \ifstrequal{#1}{\_set\_Sstatus\_XS}{\sailRISCVvalSetSstatusXS}{}% + \ifstrequal{#1}{\_set\_Sstatus\_bits}{\sailRISCVvalSetSstatusBits}{}% + \ifstrequal{#1}{\_set\_Uinterrupts\_UEI}{\sailRISCVvalSetUinterruptsUEI}{}% + \ifstrequal{#1}{\_set\_Uinterrupts\_USI}{\sailRISCVvalSetUinterruptsUSI}{}% + \ifstrequal{#1}{\_set\_Uinterrupts\_UTI}{\sailRISCVvalSetUinterruptsUTI}{}% + \ifstrequal{#1}{\_set\_Uinterrupts\_bits}{\sailRISCVvalSetUinterruptsBits}{}% + \ifstrequal{#1}{\_set\_Ustatus\_UIE}{\sailRISCVvalSetUstatusUIE}{}% + \ifstrequal{#1}{\_set\_Ustatus\_UPIE}{\sailRISCVvalSetUstatusUPIE}{}% + \ifstrequal{#1}{\_set\_Ustatus\_bits}{\sailRISCVvalSetUstatusBits}{}% + \ifstrequal{#1}{\_set\_ccsr\_bits}{\sailRISCVvalSetCcsrBits}{}% + \ifstrequal{#1}{\_set\_ccsr\_cap\_idx}{\sailRISCVvalSetCcsrCapIdx}{}% + \ifstrequal{#1}{\_set\_ccsr\_cause}{\sailRISCVvalSetCcsrCause}{}% + \ifstrequal{#1}{\_set\_ccsr\_d}{\sailRISCVvalSetCcsrD}{}% + \ifstrequal{#1}{\_set\_ccsr\_e}{\sailRISCVvalSetCcsrE}{}% + \ifstrequal{#1}{\_set\_htif\_cmd\_bits}{\sailRISCVvalSetHtifCmdBits}{}% + \ifstrequal{#1}{\_set\_htif\_cmd\_cmd}{\sailRISCVvalSetHtifCmdCmd}{}% + \ifstrequal{#1}{\_set\_htif\_cmd\_device}{\sailRISCVvalSetHtifCmdDevice}{}% + \ifstrequal{#1}{\_set\_htif\_cmd\_payload}{\sailRISCVvalSetHtifCmdPayload}{}% + \ifstrequal{#1}{\_shl1}{\sailRISCVvalShlOne}{}% + \ifstrequal{#1}{\_shl32}{\sailRISCVvalShlThreeTwo}{}% + \ifstrequal{#1}{\_shl8}{\sailRISCVvalShlEight}{}% + \ifstrequal{#1}{\_shl\_int}{\sailRISCVvalShlInt}{}% + \ifstrequal{#1}{\_shr32}{\sailRISCVvalShrThreeTwo}{}% + \ifstrequal{#1}{\_shr\_int}{\sailRISCVvalShrInt}{}% + \ifstrequal{#1}{\_tmod\_int}{\sailRISCVvalTmodInt}{}% + \ifstrequal{#1}{\_tmod\_int\_positive}{\sailRISCVvalTmodIntPositive}{}% + \ifstrequal{#1}{\_update\_Counteren\_CY}{\sailRISCVvalUpdateCounterenCY}{}% + \ifstrequal{#1}{\_update\_Counteren\_HPM}{\sailRISCVvalUpdateCounterenHPM}{}% + \ifstrequal{#1}{\_update\_Counteren\_IR}{\sailRISCVvalUpdateCounterenIR}{}% + \ifstrequal{#1}{\_update\_Counteren\_TM}{\sailRISCVvalUpdateCounterenTM}{}% + \ifstrequal{#1}{\_update\_Counteren\_bits}{\sailRISCVvalUpdateCounterenBits}{}% + \ifstrequal{#1}{\_update\_Counterin\_CY}{\sailRISCVvalUpdateCounterinCY}{}% + \ifstrequal{#1}{\_update\_Counterin\_IR}{\sailRISCVvalUpdateCounterinIR}{}% + \ifstrequal{#1}{\_update\_Counterin\_bits}{\sailRISCVvalUpdateCounterinBits}{}% + \ifstrequal{#1}{\_update\_Ext\_PTE\_Bits\_CapRead}{\sailRISCVvalUpdateExtPTEBitsCapRead}{}% + \ifstrequal{#1}{\_update\_Ext\_PTE\_Bits\_CapWrite}{\sailRISCVvalUpdateExtPTEBitsCapWrite}{}% + \ifstrequal{#1}{\_update\_Ext\_PTE\_Bits\_bits}{\sailRISCVvalUpdateExtPTEBitsBits}{}% + \ifstrequal{#1}{\_update\_Fcsr\_FFLAGS}{\sailRISCVvalUpdateFcsrFFLAGS}{}% + \ifstrequal{#1}{\_update\_Fcsr\_FRM}{\sailRISCVvalUpdateFcsrFRM}{}% + \ifstrequal{#1}{\_update\_Fcsr\_bits}{\sailRISCVvalUpdateFcsrBits}{}% + \ifstrequal{#1}{\_update\_Mcause\_Cause}{\sailRISCVvalUpdateMcauseCause}{}% + \ifstrequal{#1}{\_update\_Mcause\_IsInterrupt}{\sailRISCVvalUpdateMcauseIsInterrupt}{}% + \ifstrequal{#1}{\_update\_Mcause\_bits}{\sailRISCVvalUpdateMcauseBits}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Breakpoint}{\sailRISCVvalUpdateMedelegBreakpoint}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Fetch\_Access\_Fault}{\sailRISCVvalUpdateMedelegFetchAccessFault}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Fetch\_Addr\_Align}{\sailRISCVvalUpdateMedelegFetchAddrAlign}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Fetch\_Page\_Fault}{\sailRISCVvalUpdateMedelegFetchPageFault}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Illegal\_Instr}{\sailRISCVvalUpdateMedelegIllegalInstr}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Load\_Access\_Fault}{\sailRISCVvalUpdateMedelegLoadAccessFault}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Load\_Addr\_Align}{\sailRISCVvalUpdateMedelegLoadAddrAlign}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Load\_Page\_Fault}{\sailRISCVvalUpdateMedelegLoadPageFault}{}% + \ifstrequal{#1}{\_update\_Medeleg\_MEnvCall}{\sailRISCVvalUpdateMedelegMEnvCall}{}% + \ifstrequal{#1}{\_update\_Medeleg\_SAMO\_Access\_Fault}{\sailRISCVvalUpdateMedelegSAMOAccessFault}{}% + \ifstrequal{#1}{\_update\_Medeleg\_SAMO\_Addr\_Align}{\sailRISCVvalUpdateMedelegSAMOAddrAlign}{}% + \ifstrequal{#1}{\_update\_Medeleg\_SAMO\_Page\_Fault}{\sailRISCVvalUpdateMedelegSAMOPageFault}{}% + \ifstrequal{#1}{\_update\_Medeleg\_SEnvCall}{\sailRISCVvalUpdateMedelegSEnvCall}{}% + \ifstrequal{#1}{\_update\_Medeleg\_UEnvCall}{\sailRISCVvalUpdateMedelegUEnvCall}{}% + \ifstrequal{#1}{\_update\_Medeleg\_bits}{\sailRISCVvalUpdateMedelegBits}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_MEI}{\sailRISCVvalUpdateMinterruptsMEI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_MSI}{\sailRISCVvalUpdateMinterruptsMSI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_MTI}{\sailRISCVvalUpdateMinterruptsMTI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_SEI}{\sailRISCVvalUpdateMinterruptsSEI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_SSI}{\sailRISCVvalUpdateMinterruptsSSI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_STI}{\sailRISCVvalUpdateMinterruptsSTI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_UEI}{\sailRISCVvalUpdateMinterruptsUEI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_USI}{\sailRISCVvalUpdateMinterruptsUSI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_UTI}{\sailRISCVvalUpdateMinterruptsUTI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_bits}{\sailRISCVvalUpdateMinterruptsBits}{}% + \ifstrequal{#1}{\_update\_Misa\_A}{\sailRISCVvalUpdateMisaA}{}% + \ifstrequal{#1}{\_update\_Misa\_B}{\sailRISCVvalUpdateMisaB}{}% + \ifstrequal{#1}{\_update\_Misa\_C}{\sailRISCVvalUpdateMisaC}{}% + \ifstrequal{#1}{\_update\_Misa\_D}{\sailRISCVvalUpdateMisaD}{}% + \ifstrequal{#1}{\_update\_Misa\_E}{\sailRISCVvalUpdateMisaE}{}% + \ifstrequal{#1}{\_update\_Misa\_F}{\sailRISCVvalUpdateMisaF}{}% + \ifstrequal{#1}{\_update\_Misa\_G}{\sailRISCVvalUpdateMisaG}{}% + \ifstrequal{#1}{\_update\_Misa\_H}{\sailRISCVvalUpdateMisaH}{}% + \ifstrequal{#1}{\_update\_Misa\_I}{\sailRISCVvalUpdateMisaI}{}% + \ifstrequal{#1}{\_update\_Misa\_J}{\sailRISCVvalUpdateMisaJ}{}% + \ifstrequal{#1}{\_update\_Misa\_K}{\sailRISCVvalUpdateMisaK}{}% + \ifstrequal{#1}{\_update\_Misa\_L}{\sailRISCVvalUpdateMisaL}{}% + \ifstrequal{#1}{\_update\_Misa\_M}{\sailRISCVvalUpdateMisaM}{}% + \ifstrequal{#1}{\_update\_Misa\_MXL}{\sailRISCVvalUpdateMisaMXL}{}% + \ifstrequal{#1}{\_update\_Misa\_N}{\sailRISCVvalUpdateMisaN}{}% + \ifstrequal{#1}{\_update\_Misa\_O}{\sailRISCVvalUpdateMisaO}{}% + \ifstrequal{#1}{\_update\_Misa\_P}{\sailRISCVvalUpdateMisaP}{}% + \ifstrequal{#1}{\_update\_Misa\_Q}{\sailRISCVvalUpdateMisaQ}{}% + \ifstrequal{#1}{\_update\_Misa\_R}{\sailRISCVvalUpdateMisaR}{}% + \ifstrequal{#1}{\_update\_Misa\_S}{\sailRISCVvalUpdateMisaS}{}% + \ifstrequal{#1}{\_update\_Misa\_T}{\sailRISCVvalUpdateMisaT}{}% + \ifstrequal{#1}{\_update\_Misa\_U}{\sailRISCVvalUpdateMisaU}{}% + \ifstrequal{#1}{\_update\_Misa\_V}{\sailRISCVvalUpdateMisaV}{}% + \ifstrequal{#1}{\_update\_Misa\_W}{\sailRISCVvalUpdateMisaW}{}% + \ifstrequal{#1}{\_update\_Misa\_X}{\sailRISCVvalUpdateMisaX}{}% + \ifstrequal{#1}{\_update\_Misa\_Y}{\sailRISCVvalUpdateMisaY}{}% + \ifstrequal{#1}{\_update\_Misa\_Z}{\sailRISCVvalUpdateMisaZ}{}% + \ifstrequal{#1}{\_update\_Misa\_bits}{\sailRISCVvalUpdateMisaBits}{}% + \ifstrequal{#1}{\_update\_Mstatus\_FS}{\sailRISCVvalUpdateMstatusFS}{}% + \ifstrequal{#1}{\_update\_Mstatus\_MIE}{\sailRISCVvalUpdateMstatusMIE}{}% + \ifstrequal{#1}{\_update\_Mstatus\_MPIE}{\sailRISCVvalUpdateMstatusMPIE}{}% + \ifstrequal{#1}{\_update\_Mstatus\_MPP}{\sailRISCVvalUpdateMstatusMPP}{}% + \ifstrequal{#1}{\_update\_Mstatus\_MPRV}{\sailRISCVvalUpdateMstatusMPRV}{}% + \ifstrequal{#1}{\_update\_Mstatus\_MXR}{\sailRISCVvalUpdateMstatusMXR}{}% + \ifstrequal{#1}{\_update\_Mstatus\_SD}{\sailRISCVvalUpdateMstatusSD}{}% + \ifstrequal{#1}{\_update\_Mstatus\_SIE}{\sailRISCVvalUpdateMstatusSIE}{}% + \ifstrequal{#1}{\_update\_Mstatus\_SPIE}{\sailRISCVvalUpdateMstatusSPIE}{}% + \ifstrequal{#1}{\_update\_Mstatus\_SPP}{\sailRISCVvalUpdateMstatusSPP}{}% + \ifstrequal{#1}{\_update\_Mstatus\_SUM}{\sailRISCVvalUpdateMstatusSUM}{}% + \ifstrequal{#1}{\_update\_Mstatus\_TSR}{\sailRISCVvalUpdateMstatusTSR}{}% + \ifstrequal{#1}{\_update\_Mstatus\_TVM}{\sailRISCVvalUpdateMstatusTVM}{}% + \ifstrequal{#1}{\_update\_Mstatus\_TW}{\sailRISCVvalUpdateMstatusTW}{}% + \ifstrequal{#1}{\_update\_Mstatus\_UIE}{\sailRISCVvalUpdateMstatusUIE}{}% + \ifstrequal{#1}{\_update\_Mstatus\_UPIE}{\sailRISCVvalUpdateMstatusUPIE}{}% + \ifstrequal{#1}{\_update\_Mstatus\_XS}{\sailRISCVvalUpdateMstatusXS}{}% + \ifstrequal{#1}{\_update\_Mstatus\_bits}{\sailRISCVvalUpdateMstatusBits}{}% + \ifstrequal{#1}{\_update\_Mtvec\_Base}{\sailRISCVvalUpdateMtvecBase}{}% + \ifstrequal{#1}{\_update\_Mtvec\_Mode}{\sailRISCVvalUpdateMtvecMode}{}% + \ifstrequal{#1}{\_update\_Mtvec\_bits}{\sailRISCVvalUpdateMtvecBits}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_A}{\sailRISCVvalUpdatePTEBitsA}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_D}{\sailRISCVvalUpdatePTEBitsD}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_G}{\sailRISCVvalUpdatePTEBitsG}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_R}{\sailRISCVvalUpdatePTEBitsR}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_U}{\sailRISCVvalUpdatePTEBitsU}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_V}{\sailRISCVvalUpdatePTEBitsV}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_W}{\sailRISCVvalUpdatePTEBitsW}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_X}{\sailRISCVvalUpdatePTEBitsX}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_bits}{\sailRISCVvalUpdatePTEBitsBits}{}% + \ifstrequal{#1}{\_update\_Pmpcfg\_ent\_A}{\sailRISCVvalUpdatePmpcfgEntA}{}% + \ifstrequal{#1}{\_update\_Pmpcfg\_ent\_L}{\sailRISCVvalUpdatePmpcfgEntL}{}% + \ifstrequal{#1}{\_update\_Pmpcfg\_ent\_R}{\sailRISCVvalUpdatePmpcfgEntR}{}% + \ifstrequal{#1}{\_update\_Pmpcfg\_ent\_W}{\sailRISCVvalUpdatePmpcfgEntW}{}% + \ifstrequal{#1}{\_update\_Pmpcfg\_ent\_X}{\sailRISCVvalUpdatePmpcfgEntX}{}% + \ifstrequal{#1}{\_update\_Pmpcfg\_ent\_bits}{\sailRISCVvalUpdatePmpcfgEntBits}{}% + \ifstrequal{#1}{\_update\_SV32\_PTE\_BITS}{\sailRISCVvalUpdateSVThreeTwoPTEBITS}{}% + \ifstrequal{#1}{\_update\_SV32\_PTE\_PPNi}{\sailRISCVvalUpdateSVThreeTwoPTEPPNi}{}% + \ifstrequal{#1}{\_update\_SV32\_PTE\_RSW}{\sailRISCVvalUpdateSVThreeTwoPTERSW}{}% + \ifstrequal{#1}{\_update\_SV32\_PTE\_bits}{\sailRISCVvalUpdateSVThreeTwoPTEBits}{}% + \ifstrequal{#1}{\_update\_SV32\_Paddr\_PPNi}{\sailRISCVvalUpdateSVThreeTwoPaddrPPNi}{}% + \ifstrequal{#1}{\_update\_SV32\_Paddr\_PgOfs}{\sailRISCVvalUpdateSVThreeTwoPaddrPgOfs}{}% + \ifstrequal{#1}{\_update\_SV32\_Paddr\_bits}{\sailRISCVvalUpdateSVThreeTwoPaddrBits}{}% + \ifstrequal{#1}{\_update\_SV32\_Vaddr\_PgOfs}{\sailRISCVvalUpdateSVThreeTwoVaddrPgOfs}{}% + \ifstrequal{#1}{\_update\_SV32\_Vaddr\_VPNi}{\sailRISCVvalUpdateSVThreeTwoVaddrVPNi}{}% + \ifstrequal{#1}{\_update\_SV32\_Vaddr\_bits}{\sailRISCVvalUpdateSVThreeTwoVaddrBits}{}% + \ifstrequal{#1}{\_update\_SV39\_PTE\_BITS}{\sailRISCVvalUpdateSVThreeNinePTEBITS}{}% + \ifstrequal{#1}{\_update\_SV39\_PTE\_Ext}{\sailRISCVvalUpdateSVThreeNinePTEExt}{}% + \ifstrequal{#1}{\_update\_SV39\_PTE\_PPNi}{\sailRISCVvalUpdateSVThreeNinePTEPPNi}{}% + \ifstrequal{#1}{\_update\_SV39\_PTE\_RSW}{\sailRISCVvalUpdateSVThreeNinePTERSW}{}% + \ifstrequal{#1}{\_update\_SV39\_PTE\_bits}{\sailRISCVvalUpdateSVThreeNinePTEBits}{}% + \ifstrequal{#1}{\_update\_SV39\_Paddr\_PPNi}{\sailRISCVvalUpdateSVThreeNinePaddrPPNi}{}% + \ifstrequal{#1}{\_update\_SV39\_Paddr\_PgOfs}{\sailRISCVvalUpdateSVThreeNinePaddrPgOfs}{}% + \ifstrequal{#1}{\_update\_SV39\_Paddr\_bits}{\sailRISCVvalUpdateSVThreeNinePaddrBits}{}% + \ifstrequal{#1}{\_update\_SV39\_Vaddr\_PgOfs}{\sailRISCVvalUpdateSVThreeNineVaddrPgOfs}{}% + \ifstrequal{#1}{\_update\_SV39\_Vaddr\_VPNi}{\sailRISCVvalUpdateSVThreeNineVaddrVPNi}{}% + \ifstrequal{#1}{\_update\_SV39\_Vaddr\_bits}{\sailRISCVvalUpdateSVThreeNineVaddrBits}{}% + \ifstrequal{#1}{\_update\_SV48\_PTE\_BITS}{\sailRISCVvalUpdateSVFourEightPTEBITS}{}% + \ifstrequal{#1}{\_update\_SV48\_PTE\_Ext}{\sailRISCVvalUpdateSVFourEightPTEExt}{}% + \ifstrequal{#1}{\_update\_SV48\_PTE\_PPNi}{\sailRISCVvalUpdateSVFourEightPTEPPNi}{}% + \ifstrequal{#1}{\_update\_SV48\_PTE\_RSW}{\sailRISCVvalUpdateSVFourEightPTERSW}{}% + \ifstrequal{#1}{\_update\_SV48\_PTE\_bits}{\sailRISCVvalUpdateSVFourEightPTEBits}{}% + \ifstrequal{#1}{\_update\_SV48\_Paddr\_PPNi}{\sailRISCVvalUpdateSVFourEightPaddrPPNi}{}% + \ifstrequal{#1}{\_update\_SV48\_Paddr\_PgOfs}{\sailRISCVvalUpdateSVFourEightPaddrPgOfs}{}% + \ifstrequal{#1}{\_update\_SV48\_Paddr\_bits}{\sailRISCVvalUpdateSVFourEightPaddrBits}{}% + \ifstrequal{#1}{\_update\_SV48\_Vaddr\_PgOfs}{\sailRISCVvalUpdateSVFourEightVaddrPgOfs}{}% + \ifstrequal{#1}{\_update\_SV48\_Vaddr\_VPNi}{\sailRISCVvalUpdateSVFourEightVaddrVPNi}{}% + \ifstrequal{#1}{\_update\_SV48\_Vaddr\_bits}{\sailRISCVvalUpdateSVFourEightVaddrBits}{}% + \ifstrequal{#1}{\_update\_Satp32\_Asid}{\sailRISCVvalUpdateSatpThreeTwoAsid}{}% + \ifstrequal{#1}{\_update\_Satp32\_Mode}{\sailRISCVvalUpdateSatpThreeTwoMode}{}% + \ifstrequal{#1}{\_update\_Satp32\_PPN}{\sailRISCVvalUpdateSatpThreeTwoPPN}{}% + \ifstrequal{#1}{\_update\_Satp32\_bits}{\sailRISCVvalUpdateSatpThreeTwoBits}{}% + \ifstrequal{#1}{\_update\_Satp64\_Asid}{\sailRISCVvalUpdateSatpSixFourAsid}{}% + \ifstrequal{#1}{\_update\_Satp64\_Mode}{\sailRISCVvalUpdateSatpSixFourMode}{}% + \ifstrequal{#1}{\_update\_Satp64\_PPN}{\sailRISCVvalUpdateSatpSixFourPPN}{}% + \ifstrequal{#1}{\_update\_Satp64\_bits}{\sailRISCVvalUpdateSatpSixFourBits}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_Breakpoint}{\sailRISCVvalUpdateSedelegBreakpoint}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_Fetch\_Access\_Fault}{\sailRISCVvalUpdateSedelegFetchAccessFault}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_Fetch\_Addr\_Align}{\sailRISCVvalUpdateSedelegFetchAddrAlign}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_Illegal\_Instr}{\sailRISCVvalUpdateSedelegIllegalInstr}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_Load\_Access\_Fault}{\sailRISCVvalUpdateSedelegLoadAccessFault}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_Load\_Addr\_Align}{\sailRISCVvalUpdateSedelegLoadAddrAlign}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_SAMO\_Access\_Fault}{\sailRISCVvalUpdateSedelegSAMOAccessFault}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_SAMO\_Addr\_Align}{\sailRISCVvalUpdateSedelegSAMOAddrAlign}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_UEnvCall}{\sailRISCVvalUpdateSedelegUEnvCall}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_bits}{\sailRISCVvalUpdateSedelegBits}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_SEI}{\sailRISCVvalUpdateSinterruptsSEI}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_SSI}{\sailRISCVvalUpdateSinterruptsSSI}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_STI}{\sailRISCVvalUpdateSinterruptsSTI}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_UEI}{\sailRISCVvalUpdateSinterruptsUEI}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_USI}{\sailRISCVvalUpdateSinterruptsUSI}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_UTI}{\sailRISCVvalUpdateSinterruptsUTI}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_bits}{\sailRISCVvalUpdateSinterruptsBits}{}% + \ifstrequal{#1}{\_update\_Sstatus\_FS}{\sailRISCVvalUpdateSstatusFS}{}% + \ifstrequal{#1}{\_update\_Sstatus\_MXR}{\sailRISCVvalUpdateSstatusMXR}{}% + \ifstrequal{#1}{\_update\_Sstatus\_SD}{\sailRISCVvalUpdateSstatusSD}{}% + \ifstrequal{#1}{\_update\_Sstatus\_SIE}{\sailRISCVvalUpdateSstatusSIE}{}% + \ifstrequal{#1}{\_update\_Sstatus\_SPIE}{\sailRISCVvalUpdateSstatusSPIE}{}% + \ifstrequal{#1}{\_update\_Sstatus\_SPP}{\sailRISCVvalUpdateSstatusSPP}{}% + \ifstrequal{#1}{\_update\_Sstatus\_SUM}{\sailRISCVvalUpdateSstatusSUM}{}% + \ifstrequal{#1}{\_update\_Sstatus\_UIE}{\sailRISCVvalUpdateSstatusUIE}{}% + \ifstrequal{#1}{\_update\_Sstatus\_UPIE}{\sailRISCVvalUpdateSstatusUPIE}{}% + \ifstrequal{#1}{\_update\_Sstatus\_XS}{\sailRISCVvalUpdateSstatusXS}{}% + \ifstrequal{#1}{\_update\_Sstatus\_bits}{\sailRISCVvalUpdateSstatusBits}{}% + \ifstrequal{#1}{\_update\_Uinterrupts\_UEI}{\sailRISCVvalUpdateUinterruptsUEI}{}% + \ifstrequal{#1}{\_update\_Uinterrupts\_USI}{\sailRISCVvalUpdateUinterruptsUSI}{}% + \ifstrequal{#1}{\_update\_Uinterrupts\_UTI}{\sailRISCVvalUpdateUinterruptsUTI}{}% + \ifstrequal{#1}{\_update\_Uinterrupts\_bits}{\sailRISCVvalUpdateUinterruptsBits}{}% + \ifstrequal{#1}{\_update\_Ustatus\_UIE}{\sailRISCVvalUpdateUstatusUIE}{}% + \ifstrequal{#1}{\_update\_Ustatus\_UPIE}{\sailRISCVvalUpdateUstatusUPIE}{}% + \ifstrequal{#1}{\_update\_Ustatus\_bits}{\sailRISCVvalUpdateUstatusBits}{}% + \ifstrequal{#1}{\_update\_ccsr\_bits}{\sailRISCVvalUpdateCcsrBits}{}% + \ifstrequal{#1}{\_update\_ccsr\_cap\_idx}{\sailRISCVvalUpdateCcsrCapIdx}{}% + \ifstrequal{#1}{\_update\_ccsr\_cause}{\sailRISCVvalUpdateCcsrCause}{}% + \ifstrequal{#1}{\_update\_ccsr\_d}{\sailRISCVvalUpdateCcsrD}{}% + \ifstrequal{#1}{\_update\_ccsr\_e}{\sailRISCVvalUpdateCcsrE}{}% + \ifstrequal{#1}{\_update\_htif\_cmd\_bits}{\sailRISCVvalUpdateHtifCmdBits}{}% + \ifstrequal{#1}{\_update\_htif\_cmd\_cmd}{\sailRISCVvalUpdateHtifCmdCmd}{}% + \ifstrequal{#1}{\_update\_htif\_cmd\_device}{\sailRISCVvalUpdateHtifCmdDevice}{}% + \ifstrequal{#1}{\_update\_htif\_cmd\_payload}{\sailRISCVvalUpdateHtifCmdPayload}{}% + \ifstrequal{#1}{a64\_barrier\_domain\_of\_num}{\sailRISCVvalaSixFourBarrierDomainOfNum}{}% + \ifstrequal{#1}{a64\_barrier\_type\_of\_num}{\sailRISCVvalaSixFourBarrierTypeOfNum}{}% + \ifstrequal{#1}{abs\_int\_atom}{\sailRISCVvalabsIntAtom}{}% + \ifstrequal{#1}{abs\_int\_plain}{\sailRISCVvalabsIntPlain}{}% + \ifstrequal{#1}{accessType\_to\_str}{\sailRISCVvalaccessTypeToStr}{}% + \ifstrequal{#1}{accrue\_fflags}{\sailRISCVvalaccrueFflags}{}% + \ifstrequal{#1}{add\_atom}{\sailRISCVvaladdAtom}{}% + \ifstrequal{#1}{add\_bits}{\sailRISCVvaladdBits}{}% + \ifstrequal{#1}{add\_bits\_int}{\sailRISCVvaladdBitsInt}{}% + \ifstrequal{#1}{add\_int}{\sailRISCVvaladdInt}{}% + \ifstrequal{#1}{add\_to\_TLB39}{\sailRISCVvaladdToTLBThreeNine}{}% + \ifstrequal{#1}{add\_to\_TLB48}{\sailRISCVvaladdToTLBFourEight}{}% + \ifstrequal{#1}{addr\_to\_tag\_addr}{\sailRISCVvaladdrToTagAddr}{}% + \ifstrequal{#1}{amo\_mnemonic}{\sailRISCVvalamoMnemonic}{}% + \ifstrequal{#1}{amoop\_of\_num}{\sailRISCVvalamoopOfNum}{}% + \ifstrequal{#1}{and\_bool}{\sailRISCVvalandBool}{}% + \ifstrequal{#1}{and\_bool\_no\_flow}{\sailRISCVvalandBoolNoFlow}{}% + \ifstrequal{#1}{and\_vec}{\sailRISCVvalandVec}{}% + \ifstrequal{#1}{any\_vector\_update}{\sailRISCVvalanyVectorUpdate}{}% + \ifstrequal{#1}{append\_64}{\sailRISCVvalappendSixFour}{}% + \ifstrequal{#1}{aqrl\_str}{\sailRISCVvalaqrlStr}{}% + \ifstrequal{#1}{arch\_to\_bits}{\sailRISCVvalarchToBits}{}% + \ifstrequal{#1}{architecture}{\sailRISCVvalarchitecture}{}% + \ifstrequal{#1}{assembly}{\sailRISCVvalassembly}{}% + \ifstrequal{#1}{bit\_maybe\_i}{\sailRISCVvalbitMaybeI}{}% + \ifstrequal{#1}{bit\_maybe\_o}{\sailRISCVvalbitMaybeO}{}% + \ifstrequal{#1}{bit\_maybe\_r}{\sailRISCVvalbitMaybeR}{}% + \ifstrequal{#1}{bit\_maybe\_w}{\sailRISCVvalbitMaybeW}{}% + \ifstrequal{#1}{bit\_to\_bool}{\sailRISCVvalbitToBool}{}% + \ifstrequal{#1}{bits\_str}{\sailRISCVvalbitsStr}{}% + \ifstrequal{#1}{bitvector\_access}{\sailRISCVvalbitvectorAccess}{}% + \ifstrequal{#1}{bitvector\_concat}{\sailRISCVvalbitvectorConcat}{}% + \ifstrequal{#1}{bitvector\_length}{\sailRISCVvalbitvectorLength}{}% + \ifstrequal{#1}{bitvector\_update}{\sailRISCVvalbitvectorUpdate}{}% + \ifstrequal{#1}{bool\_bits}{\sailRISCVvalboolBits}{}% + \ifstrequal{#1}{bool\_not\_bits}{\sailRISCVvalboolNotBits}{}% + \ifstrequal{#1}{bool\_to\_bit}{\sailRISCVvalboolToBit}{}% + \ifstrequal{#1}{bool\_to\_bits}{\sailRISCVvalboolToBits}{}% + \ifstrequal{#1}{bop\_of\_num}{\sailRISCVvalbopOfNum}{}% + \ifstrequal{#1}{btype\_mnemonic}{\sailRISCVvalbtypeMnemonic}{}% + \ifstrequal{#1}{cache\_op\_kind\_of\_num}{\sailRISCVvalcacheOpKindOfNum}{}% + \ifstrequal{#1}{cancel\_reservation}{\sailRISCVvalcancelReservation}{}% + \ifstrequal{#1}{canonical\_NaN\_D}{\sailRISCVvalcanonicalNaND}{}% + \ifstrequal{#1}{canonical\_NaN\_S}{\sailRISCVvalcanonicalNaNS}{}% + \ifstrequal{#1}{capBitsToCapability}{\sailRISCVvalcapBitsToCapability}{}% + \ifstrequal{#1}{capBoundsEqual}{\sailRISCVvalcapBoundsEqual}{}% + \ifstrequal{#1}{capToBits}{\sailRISCVvalcapToBits}{}% + \ifstrequal{#1}{capToMemBits}{\sailRISCVvalcapToMemBits}{}% + \ifstrequal{#1}{capToString}{\sailRISCVvalcapToString}{}% + \ifstrequal{#1}{cap\_creg\_name}{\sailRISCVvalcapCregName}{}% + \ifstrequal{#1}{cap\_reg\_name}{\sailRISCVvalcapRegName}{}% + \ifstrequal{#1}{cap\_reg\_name\_abi}{\sailRISCVvalcapRegNameAbi}{}% + \ifstrequal{#1}{checkPTEPermission}{\sailRISCVvalcheckPTEPermission}{}% + \ifstrequal{#1}{check\_CSR}{\sailRISCVvalcheckCSR}{}% + \ifstrequal{#1}{check\_CSR\_access}{\sailRISCVvalcheckCSRAccess}{}% + \ifstrequal{#1}{check\_Counteren}{\sailRISCVvalcheckCounteren}{}% + \ifstrequal{#1}{check\_TVM\_SATP}{\sailRISCVvalcheckTVMSATP}{}% + \ifstrequal{#1}{check\_misaligned}{\sailRISCVvalcheckMisaligned}{}% + \ifstrequal{#1}{check\_res\_misaligned}{\sailRISCVvalcheckResMisaligned}{}% + \ifstrequal{#1}{checked\_mem\_read}{\sailRISCVvalcheckedMemRead}{}% + \ifstrequal{#1}{checked\_mem\_write}{\sailRISCVvalcheckedMemWrite}{}% + \ifstrequal{#1}{clint\_dispatch}{\sailRISCVvalclintDispatch}{}% + \ifstrequal{#1}{clint\_load}{\sailRISCVvalclintLoad}{}% + \ifstrequal{#1}{clint\_store}{\sailRISCVvalclintStore}{}% + \ifstrequal{#1}{concat\_str}{\sailRISCVvalconcatStr}{}% + \ifstrequal{#1}{concat\_str\_bits}{\sailRISCVvalconcatStrBits}{}% + \ifstrequal{#1}{concat\_str\_dec}{\sailRISCVvalconcatStrDec}{}% + \ifstrequal{#1}{count\_leading\_zeros}{\sailRISCVvalcountLeadingZeros}{}% + \ifstrequal{#1}{creg2reg\_idx}{\sailRISCVvalcregTworegIdx}{}% + \ifstrequal{#1}{creg\_name}{\sailRISCVvalcregName}{}% + \ifstrequal{#1}{csrAccess}{\sailRISCVvalcsrAccess}{}% + \ifstrequal{#1}{csrPriv}{\sailRISCVvalcsrPriv}{}% + \ifstrequal{#1}{csr\_mnemonic}{\sailRISCVvalcsrMnemonic}{}% + \ifstrequal{#1}{csr\_name}{\sailRISCVvalcsrName}{}% + \ifstrequal{#1}{csr\_name\_map}{\sailRISCVvalcsrNameMap}{}% + \ifstrequal{#1}{csrop\_of\_num}{\sailRISCVvalcsropOfNum}{}% + \ifstrequal{#1}{curAsid32}{\sailRISCVvalcurAsidThreeTwo}{}% + \ifstrequal{#1}{curAsid64}{\sailRISCVvalcurAsidSixFour}{}% + \ifstrequal{#1}{curPTB32}{\sailRISCVvalcurPTBThreeTwo}{}% + \ifstrequal{#1}{curPTB64}{\sailRISCVvalcurPTBSixFour}{}% + \ifstrequal{#1}{cur\_Architecture}{\sailRISCVvalcurArchitecture}{}% + \ifstrequal{#1}{dec\_str}{\sailRISCVvaldecStr}{}% + \ifstrequal{#1}{decimal\_string\_of\_bits}{\sailRISCVvaldecimalStringOfBits}{}% + \ifstrequal{#1}{decode}{\sailRISCVvaldecode}{}% + \ifstrequal{#1}{decodeCompressed}{\sailRISCVvaldecodeCompressed}{}% + \ifstrequal{#1}{def\_spc}{\sailRISCVvaldefSpc}{}% + \ifstrequal{#1}{def\_spc\_backwards}{\sailRISCVvaldefSpcBackwards}{}% + \ifstrequal{#1}{def\_spc\_forwards}{\sailRISCVvaldefSpcForwards}{}% + \ifstrequal{#1}{def\_spc\_matches\_prefix}{\sailRISCVvaldefSpcMatchesPrefix}{}% + \ifstrequal{#1}{dirty\_fd\_context}{\sailRISCVvaldirtyFdContext}{}% + \ifstrequal{#1}{dispatchInterrupt}{\sailRISCVvaldispatchInterrupt}{}% + \ifstrequal{#1}{dzFlag}{\sailRISCVvaldzzFlag}{}% + \ifstrequal{#1}{ediv\_int}{\sailRISCVvaledivInt}{}% + \ifstrequal{#1}{effectivePrivilege}{\sailRISCVvaleffectivePrivilege}{}% + \ifstrequal{#1}{elf\_entry}{\sailRISCVvalelfEntry}{}% + \ifstrequal{#1}{elf\_tohost}{\sailRISCVvalelfTohost}{}% + \ifstrequal{#1}{emod\_int}{\sailRISCVvalemodInt}{}% + \ifstrequal{#1}{encdec}{\sailRISCVvalencdec}{}% + \ifstrequal{#1}{encdec\_amoop}{\sailRISCVvalencdecAmoop}{}% + \ifstrequal{#1}{encdec\_bop}{\sailRISCVvalencdecBop}{}% + \ifstrequal{#1}{encdec\_compressed}{\sailRISCVvalencdecCompressed}{}% + \ifstrequal{#1}{encdec\_csrop}{\sailRISCVvalencdecCsrop}{}% + \ifstrequal{#1}{encdec\_iop}{\sailRISCVvalencdecIop}{}% + \ifstrequal{#1}{encdec\_mul\_op}{\sailRISCVvalencdecMulOp}{}% + \ifstrequal{#1}{encdec\_rounding\_mode}{\sailRISCVvalencdecRoundingMode}{}% + \ifstrequal{#1}{encdec\_sop}{\sailRISCVvalencdecSop}{}% + \ifstrequal{#1}{encdec\_uop}{\sailRISCVvalencdecUop}{}% + \ifstrequal{#1}{eq\_anything}{\sailRISCVvaleqAnything}{}% + \ifstrequal{#1}{eq\_bit}{\sailRISCVvaleqBit}{}% + \ifstrequal{#1}{eq\_bits}{\sailRISCVvaleqBits}{}% + \ifstrequal{#1}{eq\_bool}{\sailRISCVvaleqBool}{}% + \ifstrequal{#1}{eq\_int}{\sailRISCVvaleqInt}{}% + \ifstrequal{#1}{eq\_string}{\sailRISCVvaleqString}{}% + \ifstrequal{#1}{eq\_unit}{\sailRISCVvaleqUnit}{}% + \ifstrequal{#1}{exceptionType\_to\_bits}{\sailRISCVvalexceptionTypeToBits}{}% + \ifstrequal{#1}{exceptionType\_to\_str}{\sailRISCVvalexceptionTypeToStr}{}% + \ifstrequal{#1}{exception\_delegatee}{\sailRISCVvalexceptionDelegatee}{}% + \ifstrequal{#1}{exception\_handler}{\sailRISCVvalexceptionHandler}{}% + \ifstrequal{#1}{execute}{\sailRISCVvalexecute}{}% + \ifstrequal{#1}{extStatus\_of\_bits}{\sailRISCVvalextStatusOfBits}{}% + \ifstrequal{#1}{extStatus\_to\_bits}{\sailRISCVvalextStatusToBits}{}% + \ifstrequal{#1}{ext\_access\_type\_of\_num}{\sailRISCVvalextAccessTypeOfNum}{}% + \ifstrequal{#1}{ext\_check\_CSR}{\sailRISCVvalextCheckCSR}{}% + \ifstrequal{#1}{ext\_check\_CSR\_fail}{\sailRISCVvalextCheckCSRFail}{}% + \ifstrequal{#1}{ext\_check\_xret\_priv}{\sailRISCVvalextCheckXretPriv}{}% + \ifstrequal{#1}{ext\_control\_check\_addr}{\sailRISCVvalextControlCheckAddr}{}% + \ifstrequal{#1}{ext\_control\_check\_pc}{\sailRISCVvalextControlCheckPc}{}% + \ifstrequal{#1}{ext\_data\_get\_addr}{\sailRISCVvalextDataGetAddr}{}% + \ifstrequal{#1}{ext\_exc\_type\_of\_num}{\sailRISCVvalextExcTypeOfNum}{}% + \ifstrequal{#1}{ext\_exc\_type\_to\_bits}{\sailRISCVvalextExcTypeToBits}{}% + \ifstrequal{#1}{ext\_exc\_type\_to\_str}{\sailRISCVvalextExcTypeToStr}{}% + \ifstrequal{#1}{ext\_fail\_xret\_priv}{\sailRISCVvalextFailXretPriv}{}% + \ifstrequal{#1}{ext\_fetch\_check\_pc}{\sailRISCVvalextFetchCheckPc}{}% + \ifstrequal{#1}{ext\_fetch\_hook}{\sailRISCVvalextFetchHook}{}% + \ifstrequal{#1}{ext\_get\_ptw\_error}{\sailRISCVvalextGetPtwError}{}% + \ifstrequal{#1}{ext\_handle\_control\_check\_error}{\sailRISCVvalextHandleControlCheckError}{}% + \ifstrequal{#1}{ext\_handle\_data\_check\_error}{\sailRISCVvalextHandleDataCheckError}{}% + \ifstrequal{#1}{ext\_handle\_fetch\_check\_error}{\sailRISCVvalextHandleFetchCheckError}{}% + \ifstrequal{#1}{ext\_init}{\sailRISCVvalextInit}{}% + \ifstrequal{#1}{ext\_init\_regs}{\sailRISCVvalextInitRegs}{}% + \ifstrequal{#1}{ext\_is\_CSR\_defined}{\sailRISCVvalextIsCSRDefined}{}% + \ifstrequal{#1}{ext\_post\_decode\_hook}{\sailRISCVvalextPostDecodeHook}{}% + \ifstrequal{#1}{ext\_post\_step\_hook}{\sailRISCVvalextPostStepHook}{}% + \ifstrequal{#1}{ext\_pre\_step\_hook}{\sailRISCVvalextPreStepHook}{}% + \ifstrequal{#1}{ext\_ptw\_error\_of\_num}{\sailRISCVvalextPtwErrorOfNum}{}% + \ifstrequal{#1}{ext\_ptw\_fail\_of\_num}{\sailRISCVvalextPtwFailOfNum}{}% + \ifstrequal{#1}{ext\_ptw\_lc\_join}{\sailRISCVvalextPtwLcJoin}{}% + \ifstrequal{#1}{ext\_ptw\_lc\_of\_num}{\sailRISCVvalextPtwLcOfNum}{}% + \ifstrequal{#1}{ext\_ptw\_sc\_join}{\sailRISCVvalextPtwScJoin}{}% + \ifstrequal{#1}{ext\_ptw\_sc\_of\_num}{\sailRISCVvalextPtwScOfNum}{}% + \ifstrequal{#1}{ext\_read\_CSR}{\sailRISCVvalextReadCSR}{}% + \ifstrequal{#1}{ext\_rvfi\_init}{\sailRISCVvalextRvfiInit}{}% + \ifstrequal{#1}{ext\_veto\_disable\_C}{\sailRISCVvalextVetoDisableC}{}% + \ifstrequal{#1}{ext\_write\_CSR}{\sailRISCVvalextWriteCSR}{}% + \ifstrequal{#1}{ext\_write\_fcsr}{\sailRISCVvalextWriteFcsr}{}% + \ifstrequal{#1}{extend\_value}{\sailRISCVvalextendValue}{}% + \ifstrequal{#1}{extern\_f32Add}{\sailRISCVvalexternFThreeTwoAdd}{}% + \ifstrequal{#1}{extern\_f32Div}{\sailRISCVvalexternFThreeTwoDiv}{}% + \ifstrequal{#1}{extern\_f32Eq}{\sailRISCVvalexternFThreeTwoEq}{}% + \ifstrequal{#1}{extern\_f32Le}{\sailRISCVvalexternFThreeTwoLe}{}% + \ifstrequal{#1}{extern\_f32Lt}{\sailRISCVvalexternFThreeTwoLt}{}% + \ifstrequal{#1}{extern\_f32Mul}{\sailRISCVvalexternFThreeTwoMul}{}% + \ifstrequal{#1}{extern\_f32MulAdd}{\sailRISCVvalexternFThreeTwoMulAdd}{}% + \ifstrequal{#1}{extern\_f32Sqrt}{\sailRISCVvalexternFThreeTwoSqrt}{}% + \ifstrequal{#1}{extern\_f32Sub}{\sailRISCVvalexternFThreeTwoSub}{}% + \ifstrequal{#1}{extern\_f32ToF64}{\sailRISCVvalexternFThreeTwoToFSixFour}{}% + \ifstrequal{#1}{extern\_f32ToI32}{\sailRISCVvalexternFThreeTwoToIThreeTwo}{}% + \ifstrequal{#1}{extern\_f32ToI64}{\sailRISCVvalexternFThreeTwoToISixFour}{}% + \ifstrequal{#1}{extern\_f32ToUi32}{\sailRISCVvalexternFThreeTwoToUiThreeTwo}{}% + \ifstrequal{#1}{extern\_f32ToUi64}{\sailRISCVvalexternFThreeTwoToUiSixFour}{}% + \ifstrequal{#1}{extern\_f64Add}{\sailRISCVvalexternFSixFourAdd}{}% + \ifstrequal{#1}{extern\_f64Div}{\sailRISCVvalexternFSixFourDiv}{}% + \ifstrequal{#1}{extern\_f64Eq}{\sailRISCVvalexternFSixFourEq}{}% + \ifstrequal{#1}{extern\_f64Le}{\sailRISCVvalexternFSixFourLe}{}% + \ifstrequal{#1}{extern\_f64Lt}{\sailRISCVvalexternFSixFourLt}{}% + \ifstrequal{#1}{extern\_f64Mul}{\sailRISCVvalexternFSixFourMul}{}% + \ifstrequal{#1}{extern\_f64MulAdd}{\sailRISCVvalexternFSixFourMulAdd}{}% + \ifstrequal{#1}{extern\_f64Sqrt}{\sailRISCVvalexternFSixFourSqrt}{}% + \ifstrequal{#1}{extern\_f64Sub}{\sailRISCVvalexternFSixFourSub}{}% + \ifstrequal{#1}{extern\_f64ToF32}{\sailRISCVvalexternFSixFourToFThreeTwo}{}% + \ifstrequal{#1}{extern\_f64ToI32}{\sailRISCVvalexternFSixFourToIThreeTwo}{}% + \ifstrequal{#1}{extern\_f64ToI64}{\sailRISCVvalexternFSixFourToISixFour}{}% + \ifstrequal{#1}{extern\_f64ToUi32}{\sailRISCVvalexternFSixFourToUiThreeTwo}{}% + \ifstrequal{#1}{extern\_f64ToUi64}{\sailRISCVvalexternFSixFourToUiSixFour}{}% + \ifstrequal{#1}{extern\_i32ToF32}{\sailRISCVvalexternIThreeTwoToFThreeTwo}{}% + \ifstrequal{#1}{extern\_i32ToF64}{\sailRISCVvalexternIThreeTwoToFSixFour}{}% + \ifstrequal{#1}{extern\_i64ToF32}{\sailRISCVvalexternISixFourToFThreeTwo}{}% + \ifstrequal{#1}{extern\_i64ToF64}{\sailRISCVvalexternISixFourToFSixFour}{}% + \ifstrequal{#1}{extern\_ui32ToF32}{\sailRISCVvalexternUiThreeTwoToFThreeTwo}{}% + \ifstrequal{#1}{extern\_ui32ToF64}{\sailRISCVvalexternUiThreeTwoToFSixFour}{}% + \ifstrequal{#1}{extern\_ui64ToF32}{\sailRISCVvalexternUiSixFourToFThreeTwo}{}% + \ifstrequal{#1}{extern\_ui64ToF64}{\sailRISCVvalexternUiSixFourToFSixFour}{}% + \ifstrequal{#1}{f\_bin\_op\_D\_of\_num}{\sailRISCVvalfBinOpDOfNum}{}% + \ifstrequal{#1}{f\_bin\_op\_S\_of\_num}{\sailRISCVvalfBinOpSOfNum}{}% + \ifstrequal{#1}{f\_bin\_rm\_op\_D\_of\_num}{\sailRISCVvalfBinRmOpDOfNum}{}% + \ifstrequal{#1}{f\_bin\_rm\_op\_S\_of\_num}{\sailRISCVvalfBinRmOpSOfNum}{}% + \ifstrequal{#1}{f\_bin\_rm\_type\_mnemonic\_D}{\sailRISCVvalfBinRmTypeMnemonicD}{}% + \ifstrequal{#1}{f\_bin\_rm\_type\_mnemonic\_S}{\sailRISCVvalfBinRmTypeMnemonicS}{}% + \ifstrequal{#1}{f\_bin\_type\_mnemonic\_D}{\sailRISCVvalfBinTypeMnemonicD}{}% + \ifstrequal{#1}{f\_bin\_type\_mnemonic\_S}{\sailRISCVvalfBinTypeMnemonicS}{}% + \ifstrequal{#1}{f\_is\_NaN\_D}{\sailRISCVvalfIsNaND}{}% + \ifstrequal{#1}{f\_is\_NaN\_S}{\sailRISCVvalfIsNaNS}{}% + \ifstrequal{#1}{f\_is\_QNaN\_D}{\sailRISCVvalfIsQNaND}{}% + \ifstrequal{#1}{f\_is\_QNaN\_S}{\sailRISCVvalfIsQNaNS}{}% + \ifstrequal{#1}{f\_is\_SNaN\_D}{\sailRISCVvalfIsSNaND}{}% + \ifstrequal{#1}{f\_is\_SNaN\_S}{\sailRISCVvalfIsSNaNS}{}% + \ifstrequal{#1}{f\_is\_neg\_inf\_D}{\sailRISCVvalfIsNegInfD}{}% + \ifstrequal{#1}{f\_is\_neg\_inf\_S}{\sailRISCVvalfIsNegInfS}{}% + \ifstrequal{#1}{f\_is\_neg\_norm\_D}{\sailRISCVvalfIsNegNormD}{}% + \ifstrequal{#1}{f\_is\_neg\_norm\_S}{\sailRISCVvalfIsNegNormS}{}% + \ifstrequal{#1}{f\_is\_neg\_subnorm\_D}{\sailRISCVvalfIsNegSubnormD}{}% + \ifstrequal{#1}{f\_is\_neg\_subnorm\_S}{\sailRISCVvalfIsNegSubnormS}{}% + \ifstrequal{#1}{f\_is\_neg\_zero\_D}{\sailRISCVvalfIsNegZeroD}{}% + \ifstrequal{#1}{f\_is\_neg\_zero\_S}{\sailRISCVvalfIsNegZeroS}{}% + \ifstrequal{#1}{f\_is\_pos\_inf\_D}{\sailRISCVvalfIsPosInfD}{}% + \ifstrequal{#1}{f\_is\_pos\_inf\_S}{\sailRISCVvalfIsPosInfS}{}% + \ifstrequal{#1}{f\_is\_pos\_norm\_D}{\sailRISCVvalfIsPosNormD}{}% + \ifstrequal{#1}{f\_is\_pos\_norm\_S}{\sailRISCVvalfIsPosNormS}{}% + \ifstrequal{#1}{f\_is\_pos\_subnorm\_D}{\sailRISCVvalfIsPosSubnormD}{}% + \ifstrequal{#1}{f\_is\_pos\_subnorm\_S}{\sailRISCVvalfIsPosSubnormS}{}% + \ifstrequal{#1}{f\_is\_pos\_zero\_D}{\sailRISCVvalfIsPosZeroD}{}% + \ifstrequal{#1}{f\_is\_pos\_zero\_S}{\sailRISCVvalfIsPosZeroS}{}% + \ifstrequal{#1}{f\_madd\_op\_D\_of\_num}{\sailRISCVvalfMaddOpDOfNum}{}% + \ifstrequal{#1}{f\_madd\_op\_S\_of\_num}{\sailRISCVvalfMaddOpSOfNum}{}% + \ifstrequal{#1}{f\_madd\_type\_mnemonic\_D}{\sailRISCVvalfMaddTypeMnemonicD}{}% + \ifstrequal{#1}{f\_madd\_type\_mnemonic\_S}{\sailRISCVvalfMaddTypeMnemonicS}{}% + \ifstrequal{#1}{f\_un\_op\_D\_of\_num}{\sailRISCVvalfUnOpDOfNum}{}% + \ifstrequal{#1}{f\_un\_op\_S\_of\_num}{\sailRISCVvalfUnOpSOfNum}{}% + \ifstrequal{#1}{f\_un\_rm\_op\_D\_of\_num}{\sailRISCVvalfUnRmOpDOfNum}{}% + \ifstrequal{#1}{f\_un\_rm\_op\_S\_of\_num}{\sailRISCVvalfUnRmOpSOfNum}{}% + \ifstrequal{#1}{f\_un\_rm\_type\_mnemonic\_D}{\sailRISCVvalfUnRmTypeMnemonicD}{}% + \ifstrequal{#1}{f\_un\_rm\_type\_mnemonic\_S}{\sailRISCVvalfUnRmTypeMnemonicS}{}% + \ifstrequal{#1}{f\_un\_type\_mnemonic\_D}{\sailRISCVvalfUnTypeMnemonicD}{}% + \ifstrequal{#1}{f\_un\_type\_mnemonic\_S}{\sailRISCVvalfUnTypeMnemonicS}{}% + \ifstrequal{#1}{fastRepCheck}{\sailRISCVvalfastRepCheck}{}% + \ifstrequal{#1}{fdiv\_int}{\sailRISCVvalfdivInt}{}% + \ifstrequal{#1}{fence\_bits}{\sailRISCVvalfenceBits}{}% + \ifstrequal{#1}{feq\_quiet\_D}{\sailRISCVvalfeqQuietD}{}% + \ifstrequal{#1}{feq\_quiet\_S}{\sailRISCVvalfeqQuietS}{}% + \ifstrequal{#1}{fetch}{\sailRISCVvalfetch}{}% + \ifstrequal{#1}{findPendingInterrupt}{\sailRISCVvalfindPendingInterrupt}{}% + \ifstrequal{#1}{fle\_D}{\sailRISCVvalfleD}{}% + \ifstrequal{#1}{fle\_S}{\sailRISCVvalfleS}{}% + \ifstrequal{#1}{flt\_D}{\sailRISCVvalfltD}{}% + \ifstrequal{#1}{flt\_S}{\sailRISCVvalfltS}{}% + \ifstrequal{#1}{flush\_TLB}{\sailRISCVvalflushTLB}{}% + \ifstrequal{#1}{flush\_TLB39}{\sailRISCVvalflushTLBThreeNine}{}% + \ifstrequal{#1}{flush\_TLB48}{\sailRISCVvalflushTLBFourEight}{}% + \ifstrequal{#1}{flush\_TLB\_Entry}{\sailRISCVvalflushTLBEntry}{}% + \ifstrequal{#1}{fmake\_D}{\sailRISCVvalfmakeD}{}% + \ifstrequal{#1}{fmake\_S}{\sailRISCVvalfmakeS}{}% + \ifstrequal{#1}{fmod\_int}{\sailRISCVvalfmodInt}{}% + \ifstrequal{#1}{freg\_name}{\sailRISCVvalfregName}{}% + \ifstrequal{#1}{freg\_name\_abi}{\sailRISCVvalfregNameAbi}{}% + \ifstrequal{#1}{fregval\_from\_freg}{\sailRISCVvalfregvalFromFreg}{}% + \ifstrequal{#1}{fregval\_into\_freg}{\sailRISCVvalfregvalIntoFreg}{}% + \ifstrequal{#1}{frm\_mnemonic}{\sailRISCVvalfrmMnemonic}{}% + \ifstrequal{#1}{fsplit\_D}{\sailRISCVvalfsplitD}{}% + \ifstrequal{#1}{fsplit\_S}{\sailRISCVvalfsplitS}{}% + \ifstrequal{#1}{getCapBase}{\sailRISCVvalgetCapBase}{}% + \ifstrequal{#1}{getCapBaseBits}{\sailRISCVvalgetCapBaseBits}{}% + \ifstrequal{#1}{getCapBounds}{\sailRISCVvalgetCapBounds}{}% + \ifstrequal{#1}{getCapBoundsBits}{\sailRISCVvalgetCapBoundsBits}{}% + \ifstrequal{#1}{getCapCursor}{\sailRISCVvalgetCapCursor}{}% + \ifstrequal{#1}{getCapFlags}{\sailRISCVvalgetCapFlags}{}% + \ifstrequal{#1}{getCapHardPerms}{\sailRISCVvalgetCapHardPerms}{}% + \ifstrequal{#1}{getCapLength}{\sailRISCVvalgetCapLength}{}% + \ifstrequal{#1}{getCapOffset}{\sailRISCVvalgetCapOffset}{}% + \ifstrequal{#1}{getCapOffsetBits}{\sailRISCVvalgetCapOffsetBits}{}% + \ifstrequal{#1}{getCapPerms}{\sailRISCVvalgetCapPerms}{}% + \ifstrequal{#1}{getCapTop}{\sailRISCVvalgetCapTop}{}% + \ifstrequal{#1}{getCapTopBits}{\sailRISCVvalgetCapTopBits}{}% + \ifstrequal{#1}{getPendingSet}{\sailRISCVvalgetPendingSet}{}% + \ifstrequal{#1}{getRepresentableAlignmentMask}{\sailRISCVvalgetRepresentableAlignmentMask}{}% + \ifstrequal{#1}{getRepresentableLength}{\sailRISCVvalgetRepresentableLength}{}% + \ifstrequal{#1}{get\_arch\_pc}{\sailRISCVvalgetArchPc}{}% + \ifstrequal{#1}{get\_cheri\_mode\_cap\_addr}{\sailRISCVvalgetCheriModeCapAddr}{}% + \ifstrequal{#1}{get\_config\_print\_instr}{\sailRISCVvalgetConfigPrintInstr}{}% + \ifstrequal{#1}{get\_config\_print\_mem}{\sailRISCVvalgetConfigPrintMem}{}% + \ifstrequal{#1}{get\_config\_print\_platform}{\sailRISCVvalgetConfigPrintPlatform}{}% + \ifstrequal{#1}{get\_config\_print\_reg}{\sailRISCVvalgetConfigPrintReg}{}% + \ifstrequal{#1}{get\_mstatus\_SXL}{\sailRISCVvalgetMstatusSXL}{}% + \ifstrequal{#1}{get\_mstatus\_UXL}{\sailRISCVvalgetMstatusUXL}{}% + \ifstrequal{#1}{get\_mtvec}{\sailRISCVvalgetMtvec}{}% + \ifstrequal{#1}{get\_next\_pc}{\sailRISCVvalgetNextPc}{}% + \ifstrequal{#1}{get\_slice\_int}{\sailRISCVvalgetSliceInt}{}% + \ifstrequal{#1}{get\_sstatus\_UXL}{\sailRISCVvalgetSstatusUXL}{}% + \ifstrequal{#1}{get\_stvec}{\sailRISCVvalgetStvec}{}% + \ifstrequal{#1}{get\_utvec}{\sailRISCVvalgetUtvec}{}% + \ifstrequal{#1}{get\_xret\_target}{\sailRISCVvalgetXretTarget}{}% + \ifstrequal{#1}{gt\_int}{\sailRISCVvalgtInt}{}% + \ifstrequal{#1}{gteq\_int}{\sailRISCVvalgteqInt}{}% + \ifstrequal{#1}{handle\_cheri\_cap\_exception}{\sailRISCVvalhandleCheriCapException}{}% + \ifstrequal{#1}{handle\_cheri\_pcc\_exception}{\sailRISCVvalhandleCheriPccException}{}% + \ifstrequal{#1}{handle\_cheri\_reg\_exception}{\sailRISCVvalhandleCheriRegException}{}% + \ifstrequal{#1}{handle\_exception}{\sailRISCVvalhandleException}{}% + \ifstrequal{#1}{handle\_illegal}{\sailRISCVvalhandleIllegal}{}% + \ifstrequal{#1}{handle\_interrupt}{\sailRISCVvalhandleInterrupt}{}% + \ifstrequal{#1}{handle\_load\_cap\_via\_cap}{\sailRISCVvalhandleLoadCapViaCap}{}% + \ifstrequal{#1}{handle\_load\_data\_via\_cap}{\sailRISCVvalhandleLoadDataViaCap}{}% + \ifstrequal{#1}{handle\_loadres\_cap\_via\_cap}{\sailRISCVvalhandleLoadresCapViaCap}{}% + \ifstrequal{#1}{handle\_loadres\_data\_via\_cap}{\sailRISCVvalhandleLoadresDataViaCap}{}% + \ifstrequal{#1}{handle\_mem\_exception}{\sailRISCVvalhandleMemException}{}% + \ifstrequal{#1}{handle\_store\_cap\_via\_cap}{\sailRISCVvalhandleStoreCapViaCap}{}% + \ifstrequal{#1}{handle\_store\_cond\_cap\_via\_cap}{\sailRISCVvalhandleStoreCondCapViaCap}{}% + \ifstrequal{#1}{handle\_store\_cond\_data\_via\_cap}{\sailRISCVvalhandleStoreCondDataViaCap}{}% + \ifstrequal{#1}{handle\_store\_data\_via\_cap}{\sailRISCVvalhandleStoreDataViaCap}{}% + \ifstrequal{#1}{handle\_trap\_extension}{\sailRISCVvalhandleTrapExtension}{}% + \ifstrequal{#1}{hasReservedOType}{\sailRISCVvalhasReservedOType}{}% + \ifstrequal{#1}{haveAtomics}{\sailRISCVvalhaveAtomics}{}% + \ifstrequal{#1}{haveDExt}{\sailRISCVvalhaveDExt}{}% + \ifstrequal{#1}{haveFExt}{\sailRISCVvalhaveFExt}{}% + \ifstrequal{#1}{haveMulDiv}{\sailRISCVvalhaveMulDiv}{}% + \ifstrequal{#1}{haveNExt}{\sailRISCVvalhaveNExt}{}% + \ifstrequal{#1}{haveRVC}{\sailRISCVvalhaveRVC}{}% + \ifstrequal{#1}{haveSupMode}{\sailRISCVvalhaveSupMode}{}% + \ifstrequal{#1}{haveUsrMode}{\sailRISCVvalhaveUsrMode}{}% + \ifstrequal{#1}{haveXcheri}{\sailRISCVvalhaveXcheri}{}% + \ifstrequal{#1}{hex\_bits}{\sailRISCVvalhexBits}{}% + \ifstrequal{#1}{hex\_bits\_1}{\sailRISCVvalhexBitsOne}{}% + \ifstrequal{#1}{hex\_bits\_10}{\sailRISCVvalhexBitsOneZero}{}% + \ifstrequal{#1}{hex\_bits\_10\_backwards}{\sailRISCVvalhexBitsOneZeroBackwards}{}% + \ifstrequal{#1}{hex\_bits\_10\_backwards\_matches}{\sailRISCVvalhexBitsOneZeroBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_10\_forwards}{\sailRISCVvalhexBitsOneZeroForwards}{}% + \ifstrequal{#1}{hex\_bits\_10\_forwards\_matches}{\sailRISCVvalhexBitsOneZeroForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_10\_matches\_prefix}{\sailRISCVvalhexBitsOneZeroMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_11}{\sailRISCVvalhexBitsOneOne}{}% + \ifstrequal{#1}{hex\_bits\_11\_backwards}{\sailRISCVvalhexBitsOneOneBackwards}{}% + \ifstrequal{#1}{hex\_bits\_11\_backwards\_matches}{\sailRISCVvalhexBitsOneOneBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_11\_forwards}{\sailRISCVvalhexBitsOneOneForwards}{}% + \ifstrequal{#1}{hex\_bits\_11\_forwards\_matches}{\sailRISCVvalhexBitsOneOneForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_11\_matches\_prefix}{\sailRISCVvalhexBitsOneOneMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_12}{\sailRISCVvalhexBitsOneTwo}{}% + \ifstrequal{#1}{hex\_bits\_12\_backwards}{\sailRISCVvalhexBitsOneTwoBackwards}{}% + \ifstrequal{#1}{hex\_bits\_12\_backwards\_matches}{\sailRISCVvalhexBitsOneTwoBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_12\_forwards}{\sailRISCVvalhexBitsOneTwoForwards}{}% + \ifstrequal{#1}{hex\_bits\_12\_forwards\_matches}{\sailRISCVvalhexBitsOneTwoForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_13}{\sailRISCVvalhexBitsOneThree}{}% + \ifstrequal{#1}{hex\_bits\_13\_backwards}{\sailRISCVvalhexBitsOneThreeBackwards}{}% + \ifstrequal{#1}{hex\_bits\_13\_backwards\_matches}{\sailRISCVvalhexBitsOneThreeBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_13\_forwards}{\sailRISCVvalhexBitsOneThreeForwards}{}% + \ifstrequal{#1}{hex\_bits\_13\_forwards\_matches}{\sailRISCVvalhexBitsOneThreeForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_13\_matches\_prefix}{\sailRISCVvalhexBitsOneThreeMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_14}{\sailRISCVvalhexBitsOneFour}{}% + \ifstrequal{#1}{hex\_bits\_14\_backwards}{\sailRISCVvalhexBitsOneFourBackwards}{}% + \ifstrequal{#1}{hex\_bits\_14\_backwards\_matches}{\sailRISCVvalhexBitsOneFourBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_14\_forwards}{\sailRISCVvalhexBitsOneFourForwards}{}% + \ifstrequal{#1}{hex\_bits\_14\_forwards\_matches}{\sailRISCVvalhexBitsOneFourForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_14\_matches\_prefix}{\sailRISCVvalhexBitsOneFourMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_15}{\sailRISCVvalhexBitsOneFive}{}% + \ifstrequal{#1}{hex\_bits\_15\_backwards}{\sailRISCVvalhexBitsOneFiveBackwards}{}% + \ifstrequal{#1}{hex\_bits\_15\_backwards\_matches}{\sailRISCVvalhexBitsOneFiveBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_15\_forwards}{\sailRISCVvalhexBitsOneFiveForwards}{}% + \ifstrequal{#1}{hex\_bits\_15\_forwards\_matches}{\sailRISCVvalhexBitsOneFiveForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_15\_matches\_prefix}{\sailRISCVvalhexBitsOneFiveMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_16}{\sailRISCVvalhexBitsOneSix}{}% + \ifstrequal{#1}{hex\_bits\_16\_backwards}{\sailRISCVvalhexBitsOneSixBackwards}{}% + \ifstrequal{#1}{hex\_bits\_16\_backwards\_matches}{\sailRISCVvalhexBitsOneSixBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_16\_forwards}{\sailRISCVvalhexBitsOneSixForwards}{}% + \ifstrequal{#1}{hex\_bits\_16\_forwards\_matches}{\sailRISCVvalhexBitsOneSixForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_16\_matches\_prefix}{\sailRISCVvalhexBitsOneSixMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_17}{\sailRISCVvalhexBitsOneSeven}{}% + \ifstrequal{#1}{hex\_bits\_17\_backwards}{\sailRISCVvalhexBitsOneSevenBackwards}{}% + \ifstrequal{#1}{hex\_bits\_17\_backwards\_matches}{\sailRISCVvalhexBitsOneSevenBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_17\_forwards}{\sailRISCVvalhexBitsOneSevenForwards}{}% + \ifstrequal{#1}{hex\_bits\_17\_forwards\_matches}{\sailRISCVvalhexBitsOneSevenForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_17\_matches\_prefix}{\sailRISCVvalhexBitsOneSevenMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_18}{\sailRISCVvalhexBitsOneEight}{}% + \ifstrequal{#1}{hex\_bits\_18\_backwards}{\sailRISCVvalhexBitsOneEightBackwards}{}% + \ifstrequal{#1}{hex\_bits\_18\_backwards\_matches}{\sailRISCVvalhexBitsOneEightBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_18\_forwards}{\sailRISCVvalhexBitsOneEightForwards}{}% + \ifstrequal{#1}{hex\_bits\_18\_forwards\_matches}{\sailRISCVvalhexBitsOneEightForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_18\_matches\_prefix}{\sailRISCVvalhexBitsOneEightMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_19}{\sailRISCVvalhexBitsOneNine}{}% + \ifstrequal{#1}{hex\_bits\_19\_backwards}{\sailRISCVvalhexBitsOneNineBackwards}{}% + \ifstrequal{#1}{hex\_bits\_19\_backwards\_matches}{\sailRISCVvalhexBitsOneNineBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_19\_forwards}{\sailRISCVvalhexBitsOneNineForwards}{}% + \ifstrequal{#1}{hex\_bits\_19\_forwards\_matches}{\sailRISCVvalhexBitsOneNineForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_19\_matches\_prefix}{\sailRISCVvalhexBitsOneNineMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_1\_backwards}{\sailRISCVvalhexBitsOneBackwards}{}% + \ifstrequal{#1}{hex\_bits\_1\_backwards\_matches}{\sailRISCVvalhexBitsOneBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_1\_forwards}{\sailRISCVvalhexBitsOneForwards}{}% + \ifstrequal{#1}{hex\_bits\_1\_forwards\_matches}{\sailRISCVvalhexBitsOneForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_1\_matches\_prefix}{\sailRISCVvalhexBitsOneMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_2}{\sailRISCVvalhexBitsTwo}{}% + \ifstrequal{#1}{hex\_bits\_20}{\sailRISCVvalhexBitsTwoZero}{}% + \ifstrequal{#1}{hex\_bits\_20\_backwards}{\sailRISCVvalhexBitsTwoZeroBackwards}{}% + \ifstrequal{#1}{hex\_bits\_20\_backwards\_matches}{\sailRISCVvalhexBitsTwoZeroBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_20\_forwards}{\sailRISCVvalhexBitsTwoZeroForwards}{}% + \ifstrequal{#1}{hex\_bits\_20\_forwards\_matches}{\sailRISCVvalhexBitsTwoZeroForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_20\_matches\_prefix}{\sailRISCVvalhexBitsTwoZeroMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_21}{\sailRISCVvalhexBitsTwoOne}{}% + \ifstrequal{#1}{hex\_bits\_21\_backwards}{\sailRISCVvalhexBitsTwoOneBackwards}{}% + \ifstrequal{#1}{hex\_bits\_21\_backwards\_matches}{\sailRISCVvalhexBitsTwoOneBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_21\_forwards}{\sailRISCVvalhexBitsTwoOneForwards}{}% + \ifstrequal{#1}{hex\_bits\_21\_forwards\_matches}{\sailRISCVvalhexBitsTwoOneForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_21\_matches\_prefix}{\sailRISCVvalhexBitsTwoOneMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_22}{\sailRISCVvalhexBitsTwoTwo}{}% + \ifstrequal{#1}{hex\_bits\_22\_backwards}{\sailRISCVvalhexBitsTwoTwoBackwards}{}% + \ifstrequal{#1}{hex\_bits\_22\_backwards\_matches}{\sailRISCVvalhexBitsTwoTwoBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_22\_forwards}{\sailRISCVvalhexBitsTwoTwoForwards}{}% + \ifstrequal{#1}{hex\_bits\_22\_forwards\_matches}{\sailRISCVvalhexBitsTwoTwoForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_22\_matches\_prefix}{\sailRISCVvalhexBitsTwoTwoMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_23}{\sailRISCVvalhexBitsTwoThree}{}% + \ifstrequal{#1}{hex\_bits\_23\_backwards}{\sailRISCVvalhexBitsTwoThreeBackwards}{}% + \ifstrequal{#1}{hex\_bits\_23\_backwards\_matches}{\sailRISCVvalhexBitsTwoThreeBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_23\_forwards}{\sailRISCVvalhexBitsTwoThreeForwards}{}% + \ifstrequal{#1}{hex\_bits\_23\_forwards\_matches}{\sailRISCVvalhexBitsTwoThreeForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_23\_matches\_prefix}{\sailRISCVvalhexBitsTwoThreeMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_24}{\sailRISCVvalhexBitsTwoFour}{}% + \ifstrequal{#1}{hex\_bits\_24\_backwards}{\sailRISCVvalhexBitsTwoFourBackwards}{}% + \ifstrequal{#1}{hex\_bits\_24\_backwards\_matches}{\sailRISCVvalhexBitsTwoFourBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_24\_forwards}{\sailRISCVvalhexBitsTwoFourForwards}{}% + \ifstrequal{#1}{hex\_bits\_24\_forwards\_matches}{\sailRISCVvalhexBitsTwoFourForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_24\_matches\_prefix}{\sailRISCVvalhexBitsTwoFourMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_25}{\sailRISCVvalhexBitsTwoFive}{}% + \ifstrequal{#1}{hex\_bits\_25\_backwards}{\sailRISCVvalhexBitsTwoFiveBackwards}{}% + \ifstrequal{#1}{hex\_bits\_25\_backwards\_matches}{\sailRISCVvalhexBitsTwoFiveBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_25\_forwards}{\sailRISCVvalhexBitsTwoFiveForwards}{}% + \ifstrequal{#1}{hex\_bits\_25\_forwards\_matches}{\sailRISCVvalhexBitsTwoFiveForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_25\_matches\_prefix}{\sailRISCVvalhexBitsTwoFiveMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_26}{\sailRISCVvalhexBitsTwoSix}{}% + \ifstrequal{#1}{hex\_bits\_26\_backwards}{\sailRISCVvalhexBitsTwoSixBackwards}{}% + \ifstrequal{#1}{hex\_bits\_26\_backwards\_matches}{\sailRISCVvalhexBitsTwoSixBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_26\_forwards}{\sailRISCVvalhexBitsTwoSixForwards}{}% + \ifstrequal{#1}{hex\_bits\_26\_forwards\_matches}{\sailRISCVvalhexBitsTwoSixForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_26\_matches\_prefix}{\sailRISCVvalhexBitsTwoSixMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_27}{\sailRISCVvalhexBitsTwoSeven}{}% + \ifstrequal{#1}{hex\_bits\_27\_backwards}{\sailRISCVvalhexBitsTwoSevenBackwards}{}% + \ifstrequal{#1}{hex\_bits\_27\_backwards\_matches}{\sailRISCVvalhexBitsTwoSevenBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_27\_forwards}{\sailRISCVvalhexBitsTwoSevenForwards}{}% + \ifstrequal{#1}{hex\_bits\_27\_forwards\_matches}{\sailRISCVvalhexBitsTwoSevenForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_27\_matches\_prefix}{\sailRISCVvalhexBitsTwoSevenMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_28}{\sailRISCVvalhexBitsTwoEight}{}% + \ifstrequal{#1}{hex\_bits\_28\_backwards}{\sailRISCVvalhexBitsTwoEightBackwards}{}% + \ifstrequal{#1}{hex\_bits\_28\_backwards\_matches}{\sailRISCVvalhexBitsTwoEightBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_28\_forwards}{\sailRISCVvalhexBitsTwoEightForwards}{}% + \ifstrequal{#1}{hex\_bits\_28\_forwards\_matches}{\sailRISCVvalhexBitsTwoEightForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_28\_matches\_prefix}{\sailRISCVvalhexBitsTwoEightMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_29}{\sailRISCVvalhexBitsTwoNine}{}% + \ifstrequal{#1}{hex\_bits\_29\_backwards}{\sailRISCVvalhexBitsTwoNineBackwards}{}% + \ifstrequal{#1}{hex\_bits\_29\_backwards\_matches}{\sailRISCVvalhexBitsTwoNineBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_29\_forwards}{\sailRISCVvalhexBitsTwoNineForwards}{}% + \ifstrequal{#1}{hex\_bits\_29\_forwards\_matches}{\sailRISCVvalhexBitsTwoNineForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_29\_matches\_prefix}{\sailRISCVvalhexBitsTwoNineMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_2\_backwards}{\sailRISCVvalhexBitsTwoBackwards}{}% + \ifstrequal{#1}{hex\_bits\_2\_backwards\_matches}{\sailRISCVvalhexBitsTwoBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_2\_forwards}{\sailRISCVvalhexBitsTwoForwards}{}% + \ifstrequal{#1}{hex\_bits\_2\_forwards\_matches}{\sailRISCVvalhexBitsTwoForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_2\_matches\_prefix}{\sailRISCVvalhexBitsTwoMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_3}{\sailRISCVvalhexBitsThree}{}% + \ifstrequal{#1}{hex\_bits\_30}{\sailRISCVvalhexBitsThreeZero}{}% + \ifstrequal{#1}{hex\_bits\_30\_backwards}{\sailRISCVvalhexBitsThreeZeroBackwards}{}% + \ifstrequal{#1}{hex\_bits\_30\_backwards\_matches}{\sailRISCVvalhexBitsThreeZeroBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_30\_forwards}{\sailRISCVvalhexBitsThreeZeroForwards}{}% + \ifstrequal{#1}{hex\_bits\_30\_forwards\_matches}{\sailRISCVvalhexBitsThreeZeroForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_30\_matches\_prefix}{\sailRISCVvalhexBitsThreeZeroMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_31}{\sailRISCVvalhexBitsThreeOne}{}% + \ifstrequal{#1}{hex\_bits\_31\_backwards}{\sailRISCVvalhexBitsThreeOneBackwards}{}% + \ifstrequal{#1}{hex\_bits\_31\_backwards\_matches}{\sailRISCVvalhexBitsThreeOneBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_31\_forwards}{\sailRISCVvalhexBitsThreeOneForwards}{}% + \ifstrequal{#1}{hex\_bits\_31\_forwards\_matches}{\sailRISCVvalhexBitsThreeOneForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_31\_matches\_prefix}{\sailRISCVvalhexBitsThreeOneMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_32}{\sailRISCVvalhexBitsThreeTwo}{}% + \ifstrequal{#1}{hex\_bits\_32\_backwards}{\sailRISCVvalhexBitsThreeTwoBackwards}{}% + \ifstrequal{#1}{hex\_bits\_32\_backwards\_matches}{\sailRISCVvalhexBitsThreeTwoBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_32\_forwards}{\sailRISCVvalhexBitsThreeTwoForwards}{}% + \ifstrequal{#1}{hex\_bits\_32\_forwards\_matches}{\sailRISCVvalhexBitsThreeTwoForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_32\_matches\_prefix}{\sailRISCVvalhexBitsThreeTwoMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_33}{\sailRISCVvalhexBitsThreeThree}{}% + \ifstrequal{#1}{hex\_bits\_33\_backwards}{\sailRISCVvalhexBitsThreeThreeBackwards}{}% + \ifstrequal{#1}{hex\_bits\_33\_backwards\_matches}{\sailRISCVvalhexBitsThreeThreeBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_33\_forwards}{\sailRISCVvalhexBitsThreeThreeForwards}{}% + \ifstrequal{#1}{hex\_bits\_33\_forwards\_matches}{\sailRISCVvalhexBitsThreeThreeForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_33\_matches\_prefix}{\sailRISCVvalhexBitsThreeThreeMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_3\_backwards}{\sailRISCVvalhexBitsThreeBackwards}{}% + \ifstrequal{#1}{hex\_bits\_3\_backwards\_matches}{\sailRISCVvalhexBitsThreeBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_3\_forwards}{\sailRISCVvalhexBitsThreeForwards}{}% + \ifstrequal{#1}{hex\_bits\_3\_forwards\_matches}{\sailRISCVvalhexBitsThreeForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_3\_matches\_prefix}{\sailRISCVvalhexBitsThreeMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_4}{\sailRISCVvalhexBitsFour}{}% + \ifstrequal{#1}{hex\_bits\_48}{\sailRISCVvalhexBitsFourEight}{}% + \ifstrequal{#1}{hex\_bits\_48\_backwards}{\sailRISCVvalhexBitsFourEightBackwards}{}% + \ifstrequal{#1}{hex\_bits\_48\_backwards\_matches}{\sailRISCVvalhexBitsFourEightBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_48\_forwards}{\sailRISCVvalhexBitsFourEightForwards}{}% + \ifstrequal{#1}{hex\_bits\_48\_forwards\_matches}{\sailRISCVvalhexBitsFourEightForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_48\_matches\_prefix}{\sailRISCVvalhexBitsFourEightMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_4\_backwards}{\sailRISCVvalhexBitsFourBackwards}{}% + \ifstrequal{#1}{hex\_bits\_4\_backwards\_matches}{\sailRISCVvalhexBitsFourBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_4\_forwards}{\sailRISCVvalhexBitsFourForwards}{}% + \ifstrequal{#1}{hex\_bits\_4\_forwards\_matches}{\sailRISCVvalhexBitsFourForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_4\_matches\_prefix}{\sailRISCVvalhexBitsFourMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_5}{\sailRISCVvalhexBitsFive}{}% + \ifstrequal{#1}{hex\_bits\_5\_backwards}{\sailRISCVvalhexBitsFiveBackwards}{}% + \ifstrequal{#1}{hex\_bits\_5\_backwards\_matches}{\sailRISCVvalhexBitsFiveBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_5\_forwards}{\sailRISCVvalhexBitsFiveForwards}{}% + \ifstrequal{#1}{hex\_bits\_5\_forwards\_matches}{\sailRISCVvalhexBitsFiveForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_5\_matches\_prefix}{\sailRISCVvalhexBitsFiveMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_6}{\sailRISCVvalhexBitsSix}{}% + \ifstrequal{#1}{hex\_bits\_64}{\sailRISCVvalhexBitsSixFour}{}% + \ifstrequal{#1}{hex\_bits\_64\_backwards}{\sailRISCVvalhexBitsSixFourBackwards}{}% + \ifstrequal{#1}{hex\_bits\_64\_backwards\_matches}{\sailRISCVvalhexBitsSixFourBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_64\_forwards}{\sailRISCVvalhexBitsSixFourForwards}{}% + \ifstrequal{#1}{hex\_bits\_64\_forwards\_matches}{\sailRISCVvalhexBitsSixFourForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_64\_matches\_prefix}{\sailRISCVvalhexBitsSixFourMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_6\_backwards}{\sailRISCVvalhexBitsSixBackwards}{}% + \ifstrequal{#1}{hex\_bits\_6\_backwards\_matches}{\sailRISCVvalhexBitsSixBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_6\_forwards}{\sailRISCVvalhexBitsSixForwards}{}% + \ifstrequal{#1}{hex\_bits\_6\_forwards\_matches}{\sailRISCVvalhexBitsSixForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_6\_matches\_prefix}{\sailRISCVvalhexBitsSixMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_7}{\sailRISCVvalhexBitsSeven}{}% + \ifstrequal{#1}{hex\_bits\_7\_backwards}{\sailRISCVvalhexBitsSevenBackwards}{}% + \ifstrequal{#1}{hex\_bits\_7\_backwards\_matches}{\sailRISCVvalhexBitsSevenBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_7\_forwards}{\sailRISCVvalhexBitsSevenForwards}{}% + \ifstrequal{#1}{hex\_bits\_7\_forwards\_matches}{\sailRISCVvalhexBitsSevenForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_7\_matches\_prefix}{\sailRISCVvalhexBitsSevenMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_8}{\sailRISCVvalhexBitsEight}{}% + \ifstrequal{#1}{hex\_bits\_8\_backwards}{\sailRISCVvalhexBitsEightBackwards}{}% + \ifstrequal{#1}{hex\_bits\_8\_backwards\_matches}{\sailRISCVvalhexBitsEightBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_8\_forwards}{\sailRISCVvalhexBitsEightForwards}{}% + \ifstrequal{#1}{hex\_bits\_8\_forwards\_matches}{\sailRISCVvalhexBitsEightForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_8\_matches\_prefix}{\sailRISCVvalhexBitsEightMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_9}{\sailRISCVvalhexBitsNine}{}% + \ifstrequal{#1}{hex\_bits\_9\_backwards}{\sailRISCVvalhexBitsNineBackwards}{}% + \ifstrequal{#1}{hex\_bits\_9\_backwards\_matches}{\sailRISCVvalhexBitsNineBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_9\_forwards}{\sailRISCVvalhexBitsNineForwards}{}% + \ifstrequal{#1}{hex\_bits\_9\_forwards\_matches}{\sailRISCVvalhexBitsNineForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_9\_matches\_prefix}{\sailRISCVvalhexBitsNineMatchesPrefix}{}% + \ifstrequal{#1}{hex\_str}{\sailRISCVvalhexStr}{}% + \ifstrequal{#1}{htif\_load}{\sailRISCVvalhtifLoad}{}% + \ifstrequal{#1}{htif\_store}{\sailRISCVvalhtifStore}{}% + \ifstrequal{#1}{htif\_tick}{\sailRISCVvalhtifTick}{}% + \ifstrequal{#1}{in32BitMode}{\sailRISCVvalinThreeTwoBitMode}{}% + \ifstrequal{#1}{inCapBounds}{\sailRISCVvalinCapBounds}{}% + \ifstrequal{#1}{incCapOffset}{\sailRISCVvalincCapOffset}{}% + \ifstrequal{#1}{init\_base\_regs}{\sailRISCVvalinitBaseRegs}{}% + \ifstrequal{#1}{init\_fdext\_regs}{\sailRISCVvalinitFdextRegs}{}% + \ifstrequal{#1}{init\_model}{\sailRISCVvalinitModel}{}% + \ifstrequal{#1}{init\_platform}{\sailRISCVvalinitPlatform}{}% + \ifstrequal{#1}{init\_pmp}{\sailRISCVvalinitPmp}{}% + \ifstrequal{#1}{init\_sys}{\sailRISCVvalinitSys}{}% + \ifstrequal{#1}{init\_vmem}{\sailRISCVvalinitVmem}{}% + \ifstrequal{#1}{init\_vmem\_sv39}{\sailRISCVvalinitVmemSvThreeNine}{}% + \ifstrequal{#1}{init\_vmem\_sv48}{\sailRISCVvalinitVmemSvFourEight}{}% + \ifstrequal{#1}{initial\_analysis}{\sailRISCVvalinitialAnalysis}{}% + \ifstrequal{#1}{int\_power}{\sailRISCVvalintPower}{}% + \ifstrequal{#1}{int\_to\_cap}{\sailRISCVvalintToCap}{}% + \ifstrequal{#1}{internal\_error}{\sailRISCVvalinternalError}{}% + \ifstrequal{#1}{interruptType\_to\_bits}{\sailRISCVvalinterruptTypeToBits}{}% + \ifstrequal{#1}{invalidateCap}{\sailRISCVvalinvalidateCap}{}% + \ifstrequal{#1}{iop\_of\_num}{\sailRISCVvaliopOfNum}{}% + \ifstrequal{#1}{isCapSealed}{\sailRISCVvalisCapSealed}{}% + \ifstrequal{#1}{isInvalidPTE}{\sailRISCVvalisInvalidPTE}{}% + \ifstrequal{#1}{isPTEPtr}{\sailRISCVvalisPTEPtr}{}% + \ifstrequal{#1}{isRVC}{\sailRISCVvalisRVC}{}% + \ifstrequal{#1}{isValidSv39Addr}{\sailRISCVvalisValidSvThreeNineAddr}{}% + \ifstrequal{#1}{isValidSv48Addr}{\sailRISCVvalisValidSvFourEightAddr}{}% + \ifstrequal{#1}{is\_CSR\_defined}{\sailRISCVvalisCSRDefined}{}% + \ifstrequal{#1}{is\_RV32D\_or\_RV64D}{\sailRISCVvalisRVThreeTwoDOrRVSixFourD}{}% + \ifstrequal{#1}{is\_RV32F\_or\_RV64F}{\sailRISCVvalisRVThreeTwoFOrRVSixFourF}{}% + \ifstrequal{#1}{is\_RV64D}{\sailRISCVvalisRVSixFourD}{}% + \ifstrequal{#1}{is\_RV64F}{\sailRISCVvalisRVSixFourF}{}% + \ifstrequal{#1}{is\_aligned\_addr}{\sailRISCVvalisAlignedAddr}{}% + \ifstrequal{#1}{is\_none}{\sailRISCVvalisNone}{}% + \ifstrequal{#1}{is\_some}{\sailRISCVvalisSome}{}% + \ifstrequal{#1}{itype\_mnemonic}{\sailRISCVvalitypeMnemonic}{}% + \ifstrequal{#1}{legalize\_ccsr}{\sailRISCVvallegalizzeCcsr}{}% + \ifstrequal{#1}{legalize\_epcc}{\sailRISCVvallegalizzeEpcc}{}% + \ifstrequal{#1}{legalize\_mcounteren}{\sailRISCVvallegalizzeMcounteren}{}% + \ifstrequal{#1}{legalize\_mcountinhibit}{\sailRISCVvallegalizzeMcountinhibit}{}% + \ifstrequal{#1}{legalize\_medeleg}{\sailRISCVvallegalizzeMedeleg}{}% + \ifstrequal{#1}{legalize\_mideleg}{\sailRISCVvallegalizzeMideleg}{}% + \ifstrequal{#1}{legalize\_mie}{\sailRISCVvallegalizzeMie}{}% + \ifstrequal{#1}{legalize\_mip}{\sailRISCVvallegalizzeMip}{}% + \ifstrequal{#1}{legalize\_misa}{\sailRISCVvallegalizzeMisa}{}% + \ifstrequal{#1}{legalize\_mstatus}{\sailRISCVvallegalizzeMstatus}{}% + \ifstrequal{#1}{legalize\_satp}{\sailRISCVvallegalizzeSatp}{}% + \ifstrequal{#1}{legalize\_satp32}{\sailRISCVvallegalizzeSatpThreeTwo}{}% + \ifstrequal{#1}{legalize\_satp64}{\sailRISCVvallegalizzeSatpSixFour}{}% + \ifstrequal{#1}{legalize\_scounteren}{\sailRISCVvallegalizzeScounteren}{}% + \ifstrequal{#1}{legalize\_sedeleg}{\sailRISCVvallegalizzeSedeleg}{}% + \ifstrequal{#1}{legalize\_sie}{\sailRISCVvallegalizzeSie}{}% + \ifstrequal{#1}{legalize\_sip}{\sailRISCVvallegalizzeSip}{}% + \ifstrequal{#1}{legalize\_sstatus}{\sailRISCVvallegalizzeSstatus}{}% + \ifstrequal{#1}{legalize\_tcc}{\sailRISCVvallegalizzeTcc}{}% + \ifstrequal{#1}{legalize\_tvec}{\sailRISCVvallegalizzeTvec}{}% + \ifstrequal{#1}{legalize\_uie}{\sailRISCVvallegalizzeUie}{}% + \ifstrequal{#1}{legalize\_uip}{\sailRISCVvallegalizzeUip}{}% + \ifstrequal{#1}{legalize\_ustatus}{\sailRISCVvallegalizzeUstatus}{}% + \ifstrequal{#1}{legalize\_xepc}{\sailRISCVvallegalizzeXepc}{}% + \ifstrequal{#1}{lift\_sie}{\sailRISCVvalliftSie}{}% + \ifstrequal{#1}{lift\_sip}{\sailRISCVvalliftSip}{}% + \ifstrequal{#1}{lift\_sstatus}{\sailRISCVvalliftSstatus}{}% + \ifstrequal{#1}{lift\_uie}{\sailRISCVvalliftUie}{}% + \ifstrequal{#1}{lift\_uip}{\sailRISCVvalliftUip}{}% + \ifstrequal{#1}{lift\_ustatus}{\sailRISCVvalliftUstatus}{}% + \ifstrequal{#1}{load\_reservation}{\sailRISCVvalloadReservation}{}% + \ifstrequal{#1}{lookup\_TLB39}{\sailRISCVvallookupTLBThreeNine}{}% + \ifstrequal{#1}{lookup\_TLB48}{\sailRISCVvallookupTLBFourEight}{}% + \ifstrequal{#1}{loop}{\sailRISCVvalloop}{}% + \ifstrequal{#1}{lower\_mie}{\sailRISCVvallowerMie}{}% + \ifstrequal{#1}{lower\_mip}{\sailRISCVvallowerMip}{}% + \ifstrequal{#1}{lower\_mstatus}{\sailRISCVvallowerMstatus}{}% + \ifstrequal{#1}{lower\_sie}{\sailRISCVvallowerSie}{}% + \ifstrequal{#1}{lower\_sip}{\sailRISCVvallowerSip}{}% + \ifstrequal{#1}{lower\_sstatus}{\sailRISCVvallowerSstatus}{}% + \ifstrequal{#1}{lrsc\_width\_str}{\sailRISCVvallrscWidthStr}{}% + \ifstrequal{#1}{lt\_int}{\sailRISCVvalltInt}{}% + \ifstrequal{#1}{lteq\_int}{\sailRISCVvallteqInt}{}% + \ifstrequal{#1}{make\_TLB\_Entry}{\sailRISCVvalmakeTLBEntry}{}% + \ifstrequal{#1}{match\_TLB\_Entry}{\sailRISCVvalmatchTLBEntry}{}% + \ifstrequal{#1}{match\_reservation}{\sailRISCVvalmatchReservation}{}% + \ifstrequal{#1}{max\_int}{\sailRISCVvalmaxInt}{}% + \ifstrequal{#1}{maybe\_aq}{\sailRISCVvalmaybeAq}{}% + \ifstrequal{#1}{maybe\_i}{\sailRISCVvalmaybeI}{}% + \ifstrequal{#1}{maybe\_not\_u}{\sailRISCVvalmaybeNotU}{}% + \ifstrequal{#1}{maybe\_rl}{\sailRISCVvalmaybeRl}{}% + \ifstrequal{#1}{maybe\_u}{\sailRISCVvalmaybeU}{}% + \ifstrequal{#1}{memBitsToCapability}{\sailRISCVvalmemBitsToCapability}{}% + \ifstrequal{#1}{mem\_read}{\sailRISCVvalmemRead}{}% + \ifstrequal{#1}{mem\_read\_cap}{\sailRISCVvalmemReadCap}{}% + \ifstrequal{#1}{mem\_read\_meta}{\sailRISCVvalmemReadMeta}{}% + \ifstrequal{#1}{mem\_write\_cap}{\sailRISCVvalmemWriteCap}{}% + \ifstrequal{#1}{mem\_write\_ea}{\sailRISCVvalmemWriteEa}{}% + \ifstrequal{#1}{mem\_write\_ea\_cap}{\sailRISCVvalmemWriteEaCap}{}% + \ifstrequal{#1}{mem\_write\_value}{\sailRISCVvalmemWriteValue}{}% + \ifstrequal{#1}{mem\_write\_value\_meta}{\sailRISCVvalmemWriteValueMeta}{}% + \ifstrequal{#1}{min\_instruction\_bytes}{\sailRISCVvalminInstructionBytes}{}% + \ifstrequal{#1}{min\_int}{\sailRISCVvalminInt}{}% + \ifstrequal{#1}{mmio\_read}{\sailRISCVvalmmioRead}{}% + \ifstrequal{#1}{mmio\_write}{\sailRISCVvalmmioWrite}{}% + \ifstrequal{#1}{mul\_mnemonic}{\sailRISCVvalmulMnemonic}{}% + \ifstrequal{#1}{mult\_atom}{\sailRISCVvalmultAtom}{}% + \ifstrequal{#1}{mult\_int}{\sailRISCVvalmultInt}{}% + \ifstrequal{#1}{n\_leading\_spaces}{\sailRISCVvalnLeadingSpaces}{}% + \ifstrequal{#1}{nan\_box}{\sailRISCVvalnanBox}{}% + \ifstrequal{#1}{nan\_unbox}{\sailRISCVvalnanUnbox}{}% + \ifstrequal{#1}{negate\_D}{\sailRISCVvalnegateD}{}% + \ifstrequal{#1}{negate\_S}{\sailRISCVvalnegateS}{}% + \ifstrequal{#1}{negate\_atom}{\sailRISCVvalnegateAtom}{}% + \ifstrequal{#1}{negate\_int}{\sailRISCVvalnegateInt}{}% + \ifstrequal{#1}{neq\_anything}{\sailRISCVvalneqAnything}{}% + \ifstrequal{#1}{neq\_bits}{\sailRISCVvalneqBits}{}% + \ifstrequal{#1}{neq\_bool}{\sailRISCVvalneqBool}{}% + \ifstrequal{#1}{neq\_int}{\sailRISCVvalneqInt}{}% + \ifstrequal{#1}{neq\_vec}{\sailRISCVvalneqVec}{}% + \ifstrequal{#1}{not}{\sailRISCVvalnot}{}% + \ifstrequal{#1}{not\_bit}{\sailRISCVvalnotBit}{}% + \ifstrequal{#1}{not\_bool}{\sailRISCVvalnotBool}{}% + \ifstrequal{#1}{not\_implemented}{\sailRISCVvalnotImplemented}{}% + \ifstrequal{#1}{not\_vec}{\sailRISCVvalnotVec}{}% + \ifstrequal{#1}{num\_of\_Architecture}{\sailRISCVvalnumOfArchitecture}{}% + \ifstrequal{#1}{num\_of\_CPtrCmpOp}{\sailRISCVvalnumOfCPtrCmpOp}{}% + \ifstrequal{#1}{num\_of\_CapEx}{\sailRISCVvalnumOfCapEx}{}% + \ifstrequal{#1}{num\_of\_ClearRegSet}{\sailRISCVvalnumOfClearRegSet}{}% + \ifstrequal{#1}{num\_of\_ExceptionType}{\sailRISCVvalnumOfExceptionType}{}% + \ifstrequal{#1}{num\_of\_ExtStatus}{\sailRISCVvalnumOfExtStatus}{}% + \ifstrequal{#1}{num\_of\_InterruptType}{\sailRISCVvalnumOfInterruptType}{}% + \ifstrequal{#1}{num\_of\_PmpAddrMatchType}{\sailRISCVvalnumOfPmpAddrMatchType}{}% + \ifstrequal{#1}{num\_of\_Privilege}{\sailRISCVvalnumOfPrivilege}{}% + \ifstrequal{#1}{num\_of\_Retired}{\sailRISCVvalnumOfRetired}{}% + \ifstrequal{#1}{num\_of\_SATPMode}{\sailRISCVvalnumOfSATPMode}{}% + \ifstrequal{#1}{num\_of\_TrapVectorMode}{\sailRISCVvalnumOfTrapVectorMode}{}% + \ifstrequal{#1}{num\_of\_a64\_barrier\_domain}{\sailRISCVvalnumOfASixFourBarrierDomain}{}% + \ifstrequal{#1}{num\_of\_a64\_barrier\_type}{\sailRISCVvalnumOfASixFourBarrierType}{}% + \ifstrequal{#1}{num\_of\_amoop}{\sailRISCVvalnumOfAmoop}{}% + \ifstrequal{#1}{num\_of\_bop}{\sailRISCVvalnumOfBop}{}% + \ifstrequal{#1}{num\_of\_cache\_op\_kind}{\sailRISCVvalnumOfCacheOpKind}{}% + \ifstrequal{#1}{num\_of\_csrop}{\sailRISCVvalnumOfCsrop}{}% + \ifstrequal{#1}{num\_of\_ext\_access\_type}{\sailRISCVvalnumOfExtAccessType}{}% + \ifstrequal{#1}{num\_of\_ext\_exc\_type}{\sailRISCVvalnumOfExtExcType}{}% + \ifstrequal{#1}{num\_of\_ext\_ptw\_error}{\sailRISCVvalnumOfExtPtwError}{}% + \ifstrequal{#1}{num\_of\_ext\_ptw\_fail}{\sailRISCVvalnumOfExtPtwFail}{}% + \ifstrequal{#1}{num\_of\_ext\_ptw\_lc}{\sailRISCVvalnumOfExtPtwLc}{}% + \ifstrequal{#1}{num\_of\_ext\_ptw\_sc}{\sailRISCVvalnumOfExtPtwSc}{}% + \ifstrequal{#1}{num\_of\_f\_bin\_op\_D}{\sailRISCVvalnumOfFBinOpD}{}% + \ifstrequal{#1}{num\_of\_f\_bin\_op\_S}{\sailRISCVvalnumOfFBinOpS}{}% + \ifstrequal{#1}{num\_of\_f\_bin\_rm\_op\_D}{\sailRISCVvalnumOfFBinRmOpD}{}% + \ifstrequal{#1}{num\_of\_f\_bin\_rm\_op\_S}{\sailRISCVvalnumOfFBinRmOpS}{}% + \ifstrequal{#1}{num\_of\_f\_madd\_op\_D}{\sailRISCVvalnumOfFMaddOpD}{}% + \ifstrequal{#1}{num\_of\_f\_madd\_op\_S}{\sailRISCVvalnumOfFMaddOpS}{}% + \ifstrequal{#1}{num\_of\_f\_un\_op\_D}{\sailRISCVvalnumOfFUnOpD}{}% + \ifstrequal{#1}{num\_of\_f\_un\_op\_S}{\sailRISCVvalnumOfFUnOpS}{}% + \ifstrequal{#1}{num\_of\_f\_un\_rm\_op\_D}{\sailRISCVvalnumOfFUnRmOpD}{}% + \ifstrequal{#1}{num\_of\_f\_un\_rm\_op\_S}{\sailRISCVvalnumOfFUnRmOpS}{}% + \ifstrequal{#1}{num\_of\_iop}{\sailRISCVvalnumOfIop}{}% + \ifstrequal{#1}{num\_of\_pmpAddrMatch}{\sailRISCVvalnumOfPmpAddrMatch}{}% + \ifstrequal{#1}{num\_of\_pmpMatch}{\sailRISCVvalnumOfPmpMatch}{}% + \ifstrequal{#1}{num\_of\_read\_kind}{\sailRISCVvalnumOfReadKind}{}% + \ifstrequal{#1}{num\_of\_rop}{\sailRISCVvalnumOfRop}{}% + \ifstrequal{#1}{num\_of\_ropw}{\sailRISCVvalnumOfRopw}{}% + \ifstrequal{#1}{num\_of\_rounding\_mode}{\sailRISCVvalnumOfRoundingMode}{}% + \ifstrequal{#1}{num\_of\_sop}{\sailRISCVvalnumOfSop}{}% + \ifstrequal{#1}{num\_of\_sopw}{\sailRISCVvalnumOfSopw}{}% + \ifstrequal{#1}{num\_of\_trans\_kind}{\sailRISCVvalnumOfTransKind}{}% + \ifstrequal{#1}{num\_of\_uop}{\sailRISCVvalnumOfUop}{}% + \ifstrequal{#1}{num\_of\_word\_width}{\sailRISCVvalnumOfWordWidth}{}% + \ifstrequal{#1}{num\_of\_write\_kind}{\sailRISCVvalnumOfWriteKind}{}% + \ifstrequal{#1}{nvFlag}{\sailRISCVvalnvFlag}{}% + \ifstrequal{#1}{nxFlag}{\sailRISCVvalnxFlag}{}% + \ifstrequal{#1}{ofFlag}{\sailRISCVvalofFlag}{}% + \ifstrequal{#1}{ones}{\sailRISCVvalones}{}% + \ifstrequal{#1}{opt\_spc}{\sailRISCVvaloptSpc}{}% + \ifstrequal{#1}{opt\_spc\_backwards}{\sailRISCVvaloptSpcBackwards}{}% + \ifstrequal{#1}{opt\_spc\_forwards}{\sailRISCVvaloptSpcForwards}{}% + \ifstrequal{#1}{opt\_spc\_matches\_prefix}{\sailRISCVvaloptSpcMatchesPrefix}{}% + \ifstrequal{#1}{or\_bool}{\sailRISCVvalorBool}{}% + \ifstrequal{#1}{or\_vec}{\sailRISCVvalorVec}{}% + \ifstrequal{#1}{pc\_alignment\_mask}{\sailRISCVvalpcAlignmentMask}{}% + \ifstrequal{#1}{pcc\_access\_system\_regs}{\sailRISCVvalpccAccessSystemRegs}{}% + \ifstrequal{#1}{phys\_mem\_read}{\sailRISCVvalphysMemRead}{}% + \ifstrequal{#1}{phys\_mem\_segments}{\sailRISCVvalphysMemSegments}{}% + \ifstrequal{#1}{phys\_mem\_write}{\sailRISCVvalphysMemWrite}{}% + \ifstrequal{#1}{plain\_vector\_access}{\sailRISCVvalplainVectorAccess}{}% + \ifstrequal{#1}{plain\_vector\_update}{\sailRISCVvalplainVectorUpdate}{}% + \ifstrequal{#1}{plat\_clint\_base}{\sailRISCVvalplatClintBase}{}% + \ifstrequal{#1}{plat\_clint\_size}{\sailRISCVvalplatClintSizze}{}% + \ifstrequal{#1}{plat\_enable\_dirty\_update}{\sailRISCVvalplatEnableDirtyUpdate}{}% + \ifstrequal{#1}{plat\_enable\_misaligned\_access}{\sailRISCVvalplatEnableMisalignedAccess}{}% + \ifstrequal{#1}{plat\_enable\_pmp}{\sailRISCVvalplatEnablePmp}{}% + \ifstrequal{#1}{plat\_htif\_tohost}{\sailRISCVvalplatHtifTohost}{}% + \ifstrequal{#1}{plat\_insns\_per\_tick}{\sailRISCVvalplatInsnsPerTick}{}% + \ifstrequal{#1}{plat\_mtval\_has\_illegal\_inst\_bits}{\sailRISCVvalplatMtvalHasIllegalInstBits}{}% + \ifstrequal{#1}{plat\_ram\_base}{\sailRISCVvalplatRamBase}{}% + \ifstrequal{#1}{plat\_ram\_size}{\sailRISCVvalplatRamSizze}{}% + \ifstrequal{#1}{plat\_rom\_base}{\sailRISCVvalplatRomBase}{}% + \ifstrequal{#1}{plat\_rom\_size}{\sailRISCVvalplatRomSizze}{}% + \ifstrequal{#1}{plat\_term\_read}{\sailRISCVvalplatTermRead}{}% + \ifstrequal{#1}{plat\_term\_write}{\sailRISCVvalplatTermWrite}{}% + \ifstrequal{#1}{platform\_wfi}{\sailRISCVvalplatformWfi}{}% + \ifstrequal{#1}{pmpAddrMatchType\_of\_bits}{\sailRISCVvalpmpAddrMatchTypeOfBits}{}% + \ifstrequal{#1}{pmpAddrMatchType\_to\_bits}{\sailRISCVvalpmpAddrMatchTypeToBits}{}% + \ifstrequal{#1}{pmpAddrMatch\_of\_num}{\sailRISCVvalpmpAddrMatchOfNum}{}% + \ifstrequal{#1}{pmpAddrRange}{\sailRISCVvalpmpAddrRangeA}{}% + \ifstrequal{#1}{pmpCheck}{\sailRISCVvalpmpCheck}{}% + \ifstrequal{#1}{pmpCheckPerms}{\sailRISCVvalpmpCheckPerms}{}% + \ifstrequal{#1}{pmpCheckRWX}{\sailRISCVvalpmpCheckRWX}{}% + \ifstrequal{#1}{pmpLocked}{\sailRISCVvalpmpLocked}{}% + \ifstrequal{#1}{pmpMatchAddr}{\sailRISCVvalpmpMatchAddr}{}% + \ifstrequal{#1}{pmpMatchEntry}{\sailRISCVvalpmpMatchEntry}{}% + \ifstrequal{#1}{pmpMatch\_of\_num}{\sailRISCVvalpmpMatchOfNum}{}% + \ifstrequal{#1}{pmpReadCfgReg}{\sailRISCVvalpmpReadCfgReg}{}% + \ifstrequal{#1}{pmpTORLocked}{\sailRISCVvalpmpTORLocked}{}% + \ifstrequal{#1}{pmpWriteAddr}{\sailRISCVvalpmpWriteAddr}{}% + \ifstrequal{#1}{pmpWriteCfg}{\sailRISCVvalpmpWriteCfg}{}% + \ifstrequal{#1}{pmpWriteCfgReg}{\sailRISCVvalpmpWriteCfgReg}{}% + \ifstrequal{#1}{pmp\_mem\_read}{\sailRISCVvalpmpMemRead}{}% + \ifstrequal{#1}{pmp\_mem\_write}{\sailRISCVvalpmpMemWrite}{}% + \ifstrequal{#1}{pow2}{\sailRISCVvalpowTwo}{}% + \ifstrequal{#1}{prepare\_trap\_vector}{\sailRISCVvalprepareTrapVector}{}% + \ifstrequal{#1}{prepare\_xret\_target}{\sailRISCVvalprepareXretTarget}{}% + \ifstrequal{#1}{prerr\_bits}{\sailRISCVvalprerrBits}{}% + \ifstrequal{#1}{prerr\_endline}{\sailRISCVvalprerrEndline}{}% + \ifstrequal{#1}{prerr\_int}{\sailRISCVvalprerrInt}{}% + \ifstrequal{#1}{print}{\sailRISCVvalprint}{}% + \ifstrequal{#1}{print\_bits}{\sailRISCVvalprintBits}{}% + \ifstrequal{#1}{print\_endline}{\sailRISCVvalprintEndline}{}% + \ifstrequal{#1}{print\_insn}{\sailRISCVvalprintInsn}{}% + \ifstrequal{#1}{print\_instr}{\sailRISCVvalprintInstr}{}% + \ifstrequal{#1}{print\_int}{\sailRISCVvalprintInt}{}% + \ifstrequal{#1}{print\_mem}{\sailRISCVvalprintMem}{}% + \ifstrequal{#1}{print\_platform}{\sailRISCVvalprintPlatform}{}% + \ifstrequal{#1}{print\_reg}{\sailRISCVvalprintReg}{}% + \ifstrequal{#1}{print\_string}{\sailRISCVvalprintString}{}% + \ifstrequal{#1}{privLevel\_of\_bits}{\sailRISCVvalprivLevelOfBits}{}% + \ifstrequal{#1}{privLevel\_to\_bits}{\sailRISCVvalprivLevelToBits}{}% + \ifstrequal{#1}{privLevel\_to\_str}{\sailRISCVvalprivLevelToStr}{}% + \ifstrequal{#1}{processPending}{\sailRISCVvalprocessPending}{}% + \ifstrequal{#1}{process\_fload32}{\sailRISCVvalprocessFloadThreeTwo}{}% + \ifstrequal{#1}{process\_fload64}{\sailRISCVvalprocessFloadSixFour}{}% + \ifstrequal{#1}{process\_fstore}{\sailRISCVvalprocessFstore}{}% + \ifstrequal{#1}{process\_load}{\sailRISCVvalprocessLoad}{}% + \ifstrequal{#1}{process\_loadres}{\sailRISCVvalprocessLoadres}{}% + \ifstrequal{#1}{ptw\_error\_to\_str}{\sailRISCVvalptwErrorToStr}{}% + \ifstrequal{#1}{quot\_round\_zero}{\sailRISCVvalquotRoundZero}{}% + \ifstrequal{#1}{rC}{\sailRISCVvalrC}{}% + \ifstrequal{#1}{rC\_bits}{\sailRISCVvalrCBits}{}% + \ifstrequal{#1}{rF}{\sailRISCVvalrF}{}% + \ifstrequal{#1}{rF\_bits}{\sailRISCVvalrFBits}{}% + \ifstrequal{#1}{rX}{\sailRISCVvalrX}{}% + \ifstrequal{#1}{rX\_bits}{\sailRISCVvalrXBits}{}% + \ifstrequal{#1}{readCSR}{\sailRISCVvalreadCSR}{}% + \ifstrequal{#1}{read\_kind\_of\_flags}{\sailRISCVvalreadKindOfFlags}{}% + \ifstrequal{#1}{read\_kind\_of\_num}{\sailRISCVvalreadKindOfNum}{}% + \ifstrequal{#1}{read\_ram}{\sailRISCVvalreadRam}{}% + \ifstrequal{#1}{reg\_deref}{\sailRISCVvalregDeref}{}% + \ifstrequal{#1}{reg\_name}{\sailRISCVvalregName}{}% + \ifstrequal{#1}{reg\_name\_abi}{\sailRISCVvalregNameAbi}{}% + \ifstrequal{#1}{regidx\_to\_regno}{\sailRISCVvalregidxToRegno}{}% + \ifstrequal{#1}{regval\_from\_reg}{\sailRISCVvalregvalFromReg}{}% + \ifstrequal{#1}{regval\_into\_reg}{\sailRISCVvalregvalIntoReg}{}% + \ifstrequal{#1}{rem\_round\_zero}{\sailRISCVvalremRoundZero}{}% + \ifstrequal{#1}{replicate\_bits}{\sailRISCVvalreplicateBits}{}% + \ifstrequal{#1}{retire\_instruction}{\sailRISCVvalretireInstruction}{}% + \ifstrequal{#1}{riscv\_f32Add}{\sailRISCVvalriscvFThreeTwoAdd}{}% + \ifstrequal{#1}{riscv\_f32Div}{\sailRISCVvalriscvFThreeTwoDiv}{}% + \ifstrequal{#1}{riscv\_f32Eq}{\sailRISCVvalriscvFThreeTwoEq}{}% + \ifstrequal{#1}{riscv\_f32Le}{\sailRISCVvalriscvFThreeTwoLe}{}% + \ifstrequal{#1}{riscv\_f32Lt}{\sailRISCVvalriscvFThreeTwoLt}{}% + \ifstrequal{#1}{riscv\_f32Mul}{\sailRISCVvalriscvFThreeTwoMul}{}% + \ifstrequal{#1}{riscv\_f32MulAdd}{\sailRISCVvalriscvFThreeTwoMulAdd}{}% + \ifstrequal{#1}{riscv\_f32Sqrt}{\sailRISCVvalriscvFThreeTwoSqrt}{}% + \ifstrequal{#1}{riscv\_f32Sub}{\sailRISCVvalriscvFThreeTwoSub}{}% + \ifstrequal{#1}{riscv\_f32ToF64}{\sailRISCVvalriscvFThreeTwoToFSixFour}{}% + \ifstrequal{#1}{riscv\_f32ToI32}{\sailRISCVvalriscvFThreeTwoToIThreeTwo}{}% + \ifstrequal{#1}{riscv\_f32ToI64}{\sailRISCVvalriscvFThreeTwoToISixFour}{}% + \ifstrequal{#1}{riscv\_f32ToUi32}{\sailRISCVvalriscvFThreeTwoToUiThreeTwo}{}% + \ifstrequal{#1}{riscv\_f32ToUi64}{\sailRISCVvalriscvFThreeTwoToUiSixFour}{}% + \ifstrequal{#1}{riscv\_f64Add}{\sailRISCVvalriscvFSixFourAdd}{}% + \ifstrequal{#1}{riscv\_f64Div}{\sailRISCVvalriscvFSixFourDiv}{}% + \ifstrequal{#1}{riscv\_f64Eq}{\sailRISCVvalriscvFSixFourEq}{}% + \ifstrequal{#1}{riscv\_f64Le}{\sailRISCVvalriscvFSixFourLe}{}% + \ifstrequal{#1}{riscv\_f64Lt}{\sailRISCVvalriscvFSixFourLt}{}% + \ifstrequal{#1}{riscv\_f64Mul}{\sailRISCVvalriscvFSixFourMul}{}% + \ifstrequal{#1}{riscv\_f64MulAdd}{\sailRISCVvalriscvFSixFourMulAdd}{}% + \ifstrequal{#1}{riscv\_f64Sqrt}{\sailRISCVvalriscvFSixFourSqrt}{}% + \ifstrequal{#1}{riscv\_f64Sub}{\sailRISCVvalriscvFSixFourSub}{}% + \ifstrequal{#1}{riscv\_f64ToF32}{\sailRISCVvalriscvFSixFourToFThreeTwo}{}% + \ifstrequal{#1}{riscv\_f64ToI32}{\sailRISCVvalriscvFSixFourToIThreeTwo}{}% + \ifstrequal{#1}{riscv\_f64ToI64}{\sailRISCVvalriscvFSixFourToISixFour}{}% + \ifstrequal{#1}{riscv\_f64ToUi32}{\sailRISCVvalriscvFSixFourToUiThreeTwo}{}% + \ifstrequal{#1}{riscv\_f64ToUi64}{\sailRISCVvalriscvFSixFourToUiSixFour}{}% + \ifstrequal{#1}{riscv\_i32ToF32}{\sailRISCVvalriscvIThreeTwoToFThreeTwo}{}% + \ifstrequal{#1}{riscv\_i32ToF64}{\sailRISCVvalriscvIThreeTwoToFSixFour}{}% + \ifstrequal{#1}{riscv\_i64ToF32}{\sailRISCVvalriscvISixFourToFThreeTwo}{}% + \ifstrequal{#1}{riscv\_i64ToF64}{\sailRISCVvalriscvISixFourToFSixFour}{}% + \ifstrequal{#1}{riscv\_ui32ToF32}{\sailRISCVvalriscvUiThreeTwoToFThreeTwo}{}% + \ifstrequal{#1}{riscv\_ui32ToF64}{\sailRISCVvalriscvUiThreeTwoToFSixFour}{}% + \ifstrequal{#1}{riscv\_ui64ToF32}{\sailRISCVvalriscvUiSixFourToFThreeTwo}{}% + \ifstrequal{#1}{riscv\_ui64ToF64}{\sailRISCVvalriscvUiSixFourToFSixFour}{}% + \ifstrequal{#1}{rop\_of\_num}{\sailRISCVvalropOfNum}{}% + \ifstrequal{#1}{ropw\_of\_num}{\sailRISCVvalropwOfNum}{}% + \ifstrequal{#1}{rounding\_mode\_of\_num}{\sailRISCVvalroundingModeOfNum}{}% + \ifstrequal{#1}{rtype\_mnemonic}{\sailRISCVvalrtypeMnemonic}{}% + \ifstrequal{#1}{rtypew\_mnemonic}{\sailRISCVvalrtypewMnemonic}{}% + \ifstrequal{#1}{rvfi\_read}{\sailRISCVvalrvfiRead}{}% + \ifstrequal{#1}{rvfi\_trap}{\sailRISCVvalrvfiTrap}{}% + \ifstrequal{#1}{rvfi\_wX}{\sailRISCVvalrvfiWX}{}% + \ifstrequal{#1}{rvfi\_write}{\sailRISCVvalrvfiWrite}{}% + \ifstrequal{#1}{sail\_arith\_shiftright}{\sailRISCVvalsailArithShiftright}{}% + \ifstrequal{#1}{sail\_mask}{\sailRISCVvalsailMask}{}% + \ifstrequal{#1}{sail\_ones}{\sailRISCVvalsailOnes}{}% + \ifstrequal{#1}{sail\_shiftleft}{\sailRISCVvalsailShiftleft}{}% + \ifstrequal{#1}{sail\_shiftright}{\sailRISCVvalsailShiftright}{}% + \ifstrequal{#1}{sail\_sign\_extend}{\sailRISCVvalsailSignExtend}{}% + \ifstrequal{#1}{sail\_zero\_extend}{\sailRISCVvalsailZeroExtend}{}% + \ifstrequal{#1}{sail\_zeros}{\sailRISCVvalsailZeros}{}% + \ifstrequal{#1}{satp64Mode\_of\_bits}{\sailRISCVvalsatpSixFourModeOfBits}{}% + \ifstrequal{#1}{scr\_name}{\sailRISCVvalscrName}{}% + \ifstrequal{#1}{scr\_name\_map}{\sailRISCVvalscrNameMap}{}% + \ifstrequal{#1}{sealCap}{\sailRISCVvalsealCap}{}% + \ifstrequal{#1}{select\_instr\_or\_fcsr\_rm}{\sailRISCVvalselectInstrOrFcsrRm}{}% + \ifstrequal{#1}{sep}{\sailRISCVvalsep}{}% + \ifstrequal{#1}{setCapAddr}{\sailRISCVvalsetCapAddr}{}% + \ifstrequal{#1}{setCapBounds}{\sailRISCVvalsetCapBounds}{}% + \ifstrequal{#1}{setCapFlags}{\sailRISCVvalsetCapFlags}{}% + \ifstrequal{#1}{setCapOffset}{\sailRISCVvalsetCapOffset}{}% + \ifstrequal{#1}{setCapOffsetOrNull}{\sailRISCVvalsetCapOffsetOrNull}{}% + \ifstrequal{#1}{setCapPerms}{\sailRISCVvalsetCapPerms}{}% + \ifstrequal{#1}{set\_mstatus\_SXL}{\sailRISCVvalsetMstatusSXL}{}% + \ifstrequal{#1}{set\_mstatus\_UXL}{\sailRISCVvalsetMstatusUXL}{}% + \ifstrequal{#1}{set\_mtvec}{\sailRISCVvalsetMtvec}{}% + \ifstrequal{#1}{set\_next\_pc}{\sailRISCVvalsetNextPc}{}% + \ifstrequal{#1}{set\_slice\_bits}{\sailRISCVvalsetSliceBits}{}% + \ifstrequal{#1}{set\_slice\_int}{\sailRISCVvalsetSliceInt}{}% + \ifstrequal{#1}{set\_sstatus\_UXL}{\sailRISCVvalsetSstatusUXL}{}% + \ifstrequal{#1}{set\_stvec}{\sailRISCVvalsetStvec}{}% + \ifstrequal{#1}{set\_utvec}{\sailRISCVvalsetUtvec}{}% + \ifstrequal{#1}{set\_xret\_target}{\sailRISCVvalsetXretTarget}{}% + \ifstrequal{#1}{shift\_bits\_left}{\sailRISCVvalshiftBitsLeft}{}% + \ifstrequal{#1}{shift\_bits\_right}{\sailRISCVvalshiftBitsRight}{}% + \ifstrequal{#1}{shift\_right\_arith32}{\sailRISCVvalshiftRightArithThreeTwo}{}% + \ifstrequal{#1}{shift\_right\_arith64}{\sailRISCVvalshiftRightArithSixFour}{}% + \ifstrequal{#1}{shiftiop\_mnemonic}{\sailRISCVvalshiftiopMnemonic}{}% + \ifstrequal{#1}{shiftiwop\_mnemonic}{\sailRISCVvalshiftiwopMnemonic}{}% + \ifstrequal{#1}{shiftl}{\sailRISCVvalshiftl}{}% + \ifstrequal{#1}{shiftr}{\sailRISCVvalshiftr}{}% + \ifstrequal{#1}{shiftw\_mnemonic}{\sailRISCVvalshiftwMnemonic}{}% + \ifstrequal{#1}{signed}{\sailRISCVvalsigned}{}% + \ifstrequal{#1}{size\_bits}{\sailRISCVvalsizzeBits}{}% + \ifstrequal{#1}{size\_mnemonic}{\sailRISCVvalsizzeMnemonic}{}% + \ifstrequal{#1}{slice}{\sailRISCVvalslice}{}% + \ifstrequal{#1}{slice\_mask}{\sailRISCVvalsliceMask}{}% + \ifstrequal{#1}{sop\_of\_num}{\sailRISCVvalsopOfNum}{}% + \ifstrequal{#1}{sopw\_of\_num}{\sailRISCVvalsopwOfNum}{}% + \ifstrequal{#1}{spc}{\sailRISCVvalspc}{}% + \ifstrequal{#1}{spc\_backwards}{\sailRISCVvalspcBackwards}{}% + \ifstrequal{#1}{spc\_forwards}{\sailRISCVvalspcForwards}{}% + \ifstrequal{#1}{spc\_matches\_prefix}{\sailRISCVvalspcMatchesPrefix}{}% + \ifstrequal{#1}{speculate\_conditional}{\sailRISCVvalspeculateConditional}{}% + \ifstrequal{#1}{step}{\sailRISCVvalstep}{}% + \ifstrequal{#1}{string\_append}{\sailRISCVvalstringAppend}{}% + \ifstrequal{#1}{string\_drop}{\sailRISCVvalstringDrop}{}% + \ifstrequal{#1}{string\_length}{\sailRISCVvalstringLength}{}% + \ifstrequal{#1}{string\_of\_bit}{\sailRISCVvalstringOfBit}{}% + \ifstrequal{#1}{string\_of\_bits}{\sailRISCVvalstringOfBits}{}% + \ifstrequal{#1}{string\_of\_capex}{\sailRISCVvalstringOfCapex}{}% + \ifstrequal{#1}{string\_of\_int}{\sailRISCVvalstringOfInt}{}% + \ifstrequal{#1}{string\_startswith}{\sailRISCVvalstringStartswith}{}% + \ifstrequal{#1}{string\_take}{\sailRISCVvalstringTake}{}% + \ifstrequal{#1}{sub\_atom}{\sailRISCVvalsubAtom}{}% + \ifstrequal{#1}{sub\_bits}{\sailRISCVvalsubBits}{}% + \ifstrequal{#1}{sub\_int}{\sailRISCVvalsubInt}{}% + \ifstrequal{#1}{sub\_nat}{\sailRISCVvalsubNat}{}% + \ifstrequal{#1}{sub\_vec}{\sailRISCVvalsubVec}{}% + \ifstrequal{#1}{sub\_vec\_int}{\sailRISCVvalsubVecInt}{}% + \ifstrequal{#1}{subrange\_bits}{\sailRISCVvalsubrangeBits}{}% + \ifstrequal{#1}{sys\_enable\_fdext}{\sailRISCVvalsysEnableFdext}{}% + \ifstrequal{#1}{sys\_enable\_rvc}{\sailRISCVvalsysEnableRvc}{}% + \ifstrequal{#1}{sys\_enable\_writable\_misa}{\sailRISCVvalsysEnableWritableMisa}{}% + \ifstrequal{#1}{tag\_addr\_to\_addr}{\sailRISCVvaltagAddrToAddr}{}% + \ifstrequal{#1}{tdiv\_int}{\sailRISCVvaltdivInt}{}% + \ifstrequal{#1}{tick\_clock}{\sailRISCVvaltickClock}{}% + \ifstrequal{#1}{tick\_pc}{\sailRISCVvaltickPc}{}% + \ifstrequal{#1}{tick\_platform}{\sailRISCVvaltickPlatform}{}% + \ifstrequal{#1}{to\_bits}{\sailRISCVvaltoBits}{}% + \ifstrequal{#1}{trans\_kind\_of\_num}{\sailRISCVvaltransKindOfNum}{}% + \ifstrequal{#1}{translate39}{\sailRISCVvaltranslateThreeNine}{}% + \ifstrequal{#1}{translate48}{\sailRISCVvaltranslateFourEight}{}% + \ifstrequal{#1}{translateAddr}{\sailRISCVvaltranslateAddr}{}% + \ifstrequal{#1}{translationException}{\sailRISCVvaltranslationException}{}% + \ifstrequal{#1}{translationMode}{\sailRISCVvaltranslationMode}{}% + \ifstrequal{#1}{trapVectorMode\_of\_bits}{\sailRISCVvaltrapVectorModeOfBits}{}% + \ifstrequal{#1}{trap\_handler}{\sailRISCVvaltrapHandler}{}% + \ifstrequal{#1}{truncate}{\sailRISCVvaltruncate}{}% + \ifstrequal{#1}{truncateLSB}{\sailRISCVvaltruncateLSB}{}% + \ifstrequal{#1}{tval}{\sailRISCVvaltval}{}% + \ifstrequal{#1}{tvec\_addr}{\sailRISCVvaltvecAddr}{}% + \ifstrequal{#1}{ufFlag}{\sailRISCVvalufFlag}{}% + \ifstrequal{#1}{unsealCap}{\sailRISCVvalunsealCap}{}% + \ifstrequal{#1}{unsigned}{\sailRISCVvalunsigned}{}% + \ifstrequal{#1}{uop\_of\_num}{\sailRISCVvaluopOfNum}{}% + \ifstrequal{#1}{update\_PTE\_Bits}{\sailRISCVvalupdatePTEBits}{}% + \ifstrequal{#1}{update\_softfloat\_fflags}{\sailRISCVvalupdateSoftfloatFflags}{}% + \ifstrequal{#1}{update\_subrange}{\sailRISCVvalupdateSubrange}{}% + \ifstrequal{#1}{update\_subrange\_bits}{\sailRISCVvalupdateSubrangeBits}{}% + \ifstrequal{#1}{utype\_mnemonic}{\sailRISCVvalutypeMnemonic}{}% + \ifstrequal{#1}{vector\_concat}{\sailRISCVvalvectorConcat}{}% + \ifstrequal{#1}{vector\_length}{\sailRISCVvalvectorLength}{}% + \ifstrequal{#1}{wC}{\sailRISCVvalwC}{}% + \ifstrequal{#1}{wC\_bits}{\sailRISCVvalwCBits}{}% + \ifstrequal{#1}{wF}{\sailRISCVvalwF}{}% + \ifstrequal{#1}{wF\_bits}{\sailRISCVvalwFBits}{}% + \ifstrequal{#1}{wX}{\sailRISCVvalwX}{}% + \ifstrequal{#1}{wX\_bits}{\sailRISCVvalwXBits}{}% + \ifstrequal{#1}{walk39}{\sailRISCVvalwalkThreeNine}{}% + \ifstrequal{#1}{walk48}{\sailRISCVvalwalkFourEight}{}% + \ifstrequal{#1}{within\_clint}{\sailRISCVvalwithinClint}{}% + \ifstrequal{#1}{within\_htif\_readable}{\sailRISCVvalwithinHtifReadable}{}% + \ifstrequal{#1}{within\_htif\_writable}{\sailRISCVvalwithinHtifWritable}{}% + \ifstrequal{#1}{within\_mmio\_readable}{\sailRISCVvalwithinMmioReadable}{}% + \ifstrequal{#1}{within\_mmio\_writable}{\sailRISCVvalwithinMmioWritable}{}% + \ifstrequal{#1}{within\_phys\_mem}{\sailRISCVvalwithinPhysMem}{}% + \ifstrequal{#1}{word\_width\_bytes}{\sailRISCVvalwordWidthBytes}{}% + \ifstrequal{#1}{word\_width\_of\_num}{\sailRISCVvalwordWidthOfNum}{}% + \ifstrequal{#1}{writeCSR}{\sailRISCVvalwriteCSR}{}% + \ifstrequal{#1}{write\_TLB39}{\sailRISCVvalwriteTLBThreeNine}{}% + \ifstrequal{#1}{write\_TLB48}{\sailRISCVvalwriteTLBFourEight}{}% + \ifstrequal{#1}{write\_fflags}{\sailRISCVvalwriteFflags}{}% + \ifstrequal{#1}{write\_kind\_of\_num}{\sailRISCVvalwriteKindOfNum}{}% + \ifstrequal{#1}{write\_ram}{\sailRISCVvalwriteRam}{}% + \ifstrequal{#1}{write\_ram\_ea}{\sailRISCVvalwriteRamEa}{}% + \ifstrequal{#1}{xor\_vec}{\sailRISCVvalxorVec}{}% + \ifstrequal{#1}{zeros\_implicit}{\sailRISCVvalzzerosImplicit}{}% + \ifstrequal{#1}{(operator $>$=\_u)}{\sailRISCVvalzEightoperatorzZerozIzJUzNine}{}% + \ifstrequal{#1}{(operator $>$\_s)}{\sailRISCVvalzEightoperatorzZerozISzNine}{}% + \ifstrequal{#1}{(operator $>$\_u)}{\sailRISCVvalzEightoperatorzZerozIUzNine}{}% + \ifstrequal{#1}{(operator $$>$$=\_s)}{\sailRISCVvalzEightoperatorzZerozKzJSzNine}{}% + \ifstrequal{#1}{(operator $$>$$=\_u)}{\sailRISCVvalzEightoperatorzZerozKzJUzNine}{}} + +\newcommand{\sailRISCVrefval}[2]{ + \ifstrequal{#1}{Architecture_of_num}{\hyperref[sailRISCVzArchitecturezyofzynum]{#2}}{}% + \ifstrequal{#1}{CPtrCmpOp_of_num}{\hyperref[sailRISCVzCPtrCmpOpzyofzynum]{#2}}{}% + \ifstrequal{#1}{CapExCode}{\hyperref[sailRISCVzCapExCode]{#2}}{}% + \ifstrequal{#1}{CapEx_of_num}{\hyperref[sailRISCVzCapExzyofzynum]{#2}}{}% + \ifstrequal{#1}{ClearRegSet_of_num}{\hyperref[sailRISCVzClearRegSetzyofzynum]{#2}}{}% + \ifstrequal{#1}{EXTS}{\hyperref[sailRISCVzEXTS]{#2}}{}% + \ifstrequal{#1}{EXTZ}{\hyperref[sailRISCVzEXTZ]{#2}}{}% + \ifstrequal{#1}{ExtStatus_of_num}{\hyperref[sailRISCVzExtStatuszyofzynum]{#2}}{}% + \ifstrequal{#1}{FRegStr}{\hyperref[sailRISCVzFRegStr]{#2}}{}% + \ifstrequal{#1}{GPRstr}{\hyperref[sailRISCVzGPRstr]{#2}}{}% + \ifstrequal{#1}{InterruptType_of_num}{\hyperref[sailRISCVzInterruptTypezyofzynum]{#2}}{}% + \ifstrequal{#1}{MAX}{\hyperref[sailRISCVzMAX]{#2}}{}% + \ifstrequal{#1}{MEMr_tag}{\hyperref[sailRISCVzMEMrzytag]{#2}}{}% + \ifstrequal{#1}{MEMw_tag}{\hyperref[sailRISCVzMEMwzytag]{#2}}{}% + \ifstrequal{#1}{MemoryOpResult_add_meta}{\hyperref[sailRISCVzMemoryOpResultzyaddzymeta]{#2}}{}% + \ifstrequal{#1}{MemoryOpResult_drop_meta}{\hyperref[sailRISCVzMemoryOpResultzydropzymeta]{#2}}{}% + \ifstrequal{#1}{Mk_Counteren}{\hyperref[sailRISCVzMkzyCounteren]{#2}}{}% + \ifstrequal{#1}{Mk_Counterin}{\hyperref[sailRISCVzMkzyCounterin]{#2}}{}% + \ifstrequal{#1}{Mk_Ext_PTE_Bits}{\hyperref[sailRISCVzMkzyExtzyPTEzyBits]{#2}}{}% + \ifstrequal{#1}{Mk_Fcsr}{\hyperref[sailRISCVzMkzyFcsr]{#2}}{}% + \ifstrequal{#1}{Mk_Mcause}{\hyperref[sailRISCVzMkzyMcause]{#2}}{}% + \ifstrequal{#1}{Mk_Medeleg}{\hyperref[sailRISCVzMkzyMedeleg]{#2}}{}% + \ifstrequal{#1}{Mk_Minterrupts}{\hyperref[sailRISCVzMkzyMinterrupts]{#2}}{}% + \ifstrequal{#1}{Mk_Misa}{\hyperref[sailRISCVzMkzyMisa]{#2}}{}% + \ifstrequal{#1}{Mk_Mstatus}{\hyperref[sailRISCVzMkzyMstatus]{#2}}{}% + \ifstrequal{#1}{Mk_Mtvec}{\hyperref[sailRISCVzMkzyMtvec]{#2}}{}% + \ifstrequal{#1}{Mk_PTE_Bits}{\hyperref[sailRISCVzMkzyPTEzyBits]{#2}}{}% + \ifstrequal{#1}{Mk_Pmpcfg_ent}{\hyperref[sailRISCVzMkzyPmpcfgzyent]{#2}}{}% + \ifstrequal{#1}{Mk_SV32_PTE}{\hyperref[sailRISCVzMkzySV32zyPTE]{#2}}{}% + \ifstrequal{#1}{Mk_SV32_Paddr}{\hyperref[sailRISCVzMkzySV32zyPaddr]{#2}}{}% + \ifstrequal{#1}{Mk_SV32_Vaddr}{\hyperref[sailRISCVzMkzySV32zyVaddr]{#2}}{}% + \ifstrequal{#1}{Mk_SV39_PTE}{\hyperref[sailRISCVzMkzySV39zyPTE]{#2}}{}% + \ifstrequal{#1}{Mk_SV39_Paddr}{\hyperref[sailRISCVzMkzySV39zyPaddr]{#2}}{}% + \ifstrequal{#1}{Mk_SV39_Vaddr}{\hyperref[sailRISCVzMkzySV39zyVaddr]{#2}}{}% + \ifstrequal{#1}{Mk_SV48_PTE}{\hyperref[sailRISCVzMkzySV48zyPTE]{#2}}{}% + \ifstrequal{#1}{Mk_SV48_Paddr}{\hyperref[sailRISCVzMkzySV48zyPaddr]{#2}}{}% + \ifstrequal{#1}{Mk_SV48_Vaddr}{\hyperref[sailRISCVzMkzySV48zyVaddr]{#2}}{}% + \ifstrequal{#1}{Mk_Satp32}{\hyperref[sailRISCVzMkzySatp32]{#2}}{}% + \ifstrequal{#1}{Mk_Satp64}{\hyperref[sailRISCVzMkzySatp64]{#2}}{}% + \ifstrequal{#1}{Mk_Sedeleg}{\hyperref[sailRISCVzMkzySedeleg]{#2}}{}% + \ifstrequal{#1}{Mk_Sinterrupts}{\hyperref[sailRISCVzMkzySinterrupts]{#2}}{}% + \ifstrequal{#1}{Mk_Sstatus}{\hyperref[sailRISCVzMkzySstatus]{#2}}{}% + \ifstrequal{#1}{Mk_Uinterrupts}{\hyperref[sailRISCVzMkzyUinterrupts]{#2}}{}% + \ifstrequal{#1}{Mk_Ustatus}{\hyperref[sailRISCVzMkzyUstatus]{#2}}{}% + \ifstrequal{#1}{Mk_ccsr}{\hyperref[sailRISCVzMkzyccsr]{#2}}{}% + \ifstrequal{#1}{Mk_htif_cmd}{\hyperref[sailRISCVzMkzyhtifzycmd]{#2}}{}% + \ifstrequal{#1}{PmpAddrMatchType_of_num}{\hyperref[sailRISCVzPmpAddrMatchTypezyofzynum]{#2}}{}% + \ifstrequal{#1}{Privilege_of_num}{\hyperref[sailRISCVzPrivilegezyofzynum]{#2}}{}% + \ifstrequal{#1}{RegStr}{\hyperref[sailRISCVzRegStr]{#2}}{}% + \ifstrequal{#1}{Retired_of_num}{\hyperref[sailRISCVzRetiredzyofzynum]{#2}}{}% + \ifstrequal{#1}{SATPMode_of_num}{\hyperref[sailRISCVzSATPModezyofzynum]{#2}}{}% + \ifstrequal{#1}{TrapVectorMode_of_num}{\hyperref[sailRISCVzTrapVectorModezyofzynum]{#2}}{}% + \ifstrequal{#1}{__ReadRAM_Meta}{\hyperref[sailRISCVzzyzyReadRAMzyMeta]{#2}}{}% + \ifstrequal{#1}{__TraceMemoryRead}{\hyperref[sailRISCVzzyzyTraceMemoryRead]{#2}}{}% + \ifstrequal{#1}{__TraceMemoryWrite}{\hyperref[sailRISCVzzyzyTraceMemoryWrite]{#2}}{}% + \ifstrequal{#1}{__WriteRAM_Meta}{\hyperref[sailRISCVzzyzyWriteRAMzyMeta]{#2}}{}% + \ifstrequal{#1}{__barrier}{\hyperref[sailRISCVzzyzybarrier]{#2}}{}% + \ifstrequal{#1}{__bitfield_deref}{\hyperref[sailRISCVzzyzybitfieldzyderef]{#2}}{}% + \ifstrequal{#1}{__branch_announce}{\hyperref[sailRISCVzzyzybranchzyannounce]{#2}}{}% + \ifstrequal{#1}{__cache_maintenance}{\hyperref[sailRISCVzzyzycachezymaintenance]{#2}}{}% + \ifstrequal{#1}{__deref}{\hyperref[sailRISCVzzyzyderef]{#2}}{}% + \ifstrequal{#1}{__excl_res}{\hyperref[sailRISCVzzyzyexclzyres]{#2}}{}% + \ifstrequal{#1}{__id}{\hyperref[sailRISCVzzyzyid]{#2}}{}% + \ifstrequal{#1}{__instr_announce}{\hyperref[sailRISCVzzyzyinstrzyannounce]{#2}}{}% + \ifstrequal{#1}{__read_mem}{\hyperref[sailRISCVzzyzyreadzymem]{#2}}{}% + \ifstrequal{#1}{__read_memt}{\hyperref[sailRISCVzzyzyreadzymemt]{#2}}{}% + \ifstrequal{#1}{__write_mem}{\hyperref[sailRISCVzzyzywritezymem]{#2}}{}% + \ifstrequal{#1}{__write_mem_ea}{\hyperref[sailRISCVzzyzywritezymemzyea]{#2}}{}% + \ifstrequal{#1}{__write_memt}{\hyperref[sailRISCVzzyzywritezymemt]{#2}}{}% + \ifstrequal{#1}{_get_Counteren_CY}{\hyperref[sailRISCVzzygetzyCounterenzyCY]{#2}}{}% + \ifstrequal{#1}{_get_Counteren_HPM}{\hyperref[sailRISCVzzygetzyCounterenzyHPM]{#2}}{}% + \ifstrequal{#1}{_get_Counteren_IR}{\hyperref[sailRISCVzzygetzyCounterenzyIR]{#2}}{}% + \ifstrequal{#1}{_get_Counteren_TM}{\hyperref[sailRISCVzzygetzyCounterenzyTM]{#2}}{}% + \ifstrequal{#1}{_get_Counteren_bits}{\hyperref[sailRISCVzzygetzyCounterenzybits]{#2}}{}% + \ifstrequal{#1}{_get_Counterin_CY}{\hyperref[sailRISCVzzygetzyCounterinzyCY]{#2}}{}% + \ifstrequal{#1}{_get_Counterin_IR}{\hyperref[sailRISCVzzygetzyCounterinzyIR]{#2}}{}% + \ifstrequal{#1}{_get_Counterin_bits}{\hyperref[sailRISCVzzygetzyCounterinzybits]{#2}}{}% + \ifstrequal{#1}{_get_Ext_PTE_Bits_CapRead}{\hyperref[sailRISCVzzygetzyExtzyPTEzyBitszyCapRead]{#2}}{}% + \ifstrequal{#1}{_get_Ext_PTE_Bits_CapWrite}{\hyperref[sailRISCVzzygetzyExtzyPTEzyBitszyCapWrite]{#2}}{}% + \ifstrequal{#1}{_get_Ext_PTE_Bits_bits}{\hyperref[sailRISCVzzygetzyExtzyPTEzyBitszybits]{#2}}{}% + \ifstrequal{#1}{_get_Fcsr_FFLAGS}{\hyperref[sailRISCVzzygetzyFcsrzyFFLAGS]{#2}}{}% + \ifstrequal{#1}{_get_Fcsr_FRM}{\hyperref[sailRISCVzzygetzyFcsrzyFRM]{#2}}{}% + \ifstrequal{#1}{_get_Fcsr_bits}{\hyperref[sailRISCVzzygetzyFcsrzybits]{#2}}{}% + \ifstrequal{#1}{_get_Mcause_Cause}{\hyperref[sailRISCVzzygetzyMcausezyCause]{#2}}{}% + \ifstrequal{#1}{_get_Mcause_IsInterrupt}{\hyperref[sailRISCVzzygetzyMcausezyIsInterrupt]{#2}}{}% + \ifstrequal{#1}{_get_Mcause_bits}{\hyperref[sailRISCVzzygetzyMcausezybits]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_Breakpoint}{\hyperref[sailRISCVzzygetzyMedelegzyBreakpoint]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_Fetch_Access_Fault}{\hyperref[sailRISCVzzygetzyMedelegzyFetchzyAccesszyFault]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_Fetch_Addr_Align}{\hyperref[sailRISCVzzygetzyMedelegzyFetchzyAddrzyAlign]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_Fetch_Page_Fault}{\hyperref[sailRISCVzzygetzyMedelegzyFetchzyPagezyFault]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_Illegal_Instr}{\hyperref[sailRISCVzzygetzyMedelegzyIllegalzyInstr]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_Load_Access_Fault}{\hyperref[sailRISCVzzygetzyMedelegzyLoadzyAccesszyFault]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_Load_Addr_Align}{\hyperref[sailRISCVzzygetzyMedelegzyLoadzyAddrzyAlign]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_Load_Page_Fault}{\hyperref[sailRISCVzzygetzyMedelegzyLoadzyPagezyFault]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_MEnvCall}{\hyperref[sailRISCVzzygetzyMedelegzyMEnvCall]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_SAMO_Access_Fault}{\hyperref[sailRISCVzzygetzyMedelegzySAMOzyAccesszyFault]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_SAMO_Addr_Align}{\hyperref[sailRISCVzzygetzyMedelegzySAMOzyAddrzyAlign]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_SAMO_Page_Fault}{\hyperref[sailRISCVzzygetzyMedelegzySAMOzyPagezyFault]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_SEnvCall}{\hyperref[sailRISCVzzygetzyMedelegzySEnvCall]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_UEnvCall}{\hyperref[sailRISCVzzygetzyMedelegzyUEnvCall]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_bits}{\hyperref[sailRISCVzzygetzyMedelegzybits]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_MEI}{\hyperref[sailRISCVzzygetzyMinterruptszyMEI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_MSI}{\hyperref[sailRISCVzzygetzyMinterruptszyMSI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_MTI}{\hyperref[sailRISCVzzygetzyMinterruptszyMTI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_SEI}{\hyperref[sailRISCVzzygetzyMinterruptszySEI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_SSI}{\hyperref[sailRISCVzzygetzyMinterruptszySSI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_STI}{\hyperref[sailRISCVzzygetzyMinterruptszySTI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_UEI}{\hyperref[sailRISCVzzygetzyMinterruptszyUEI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_USI}{\hyperref[sailRISCVzzygetzyMinterruptszyUSI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_UTI}{\hyperref[sailRISCVzzygetzyMinterruptszyUTI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_bits}{\hyperref[sailRISCVzzygetzyMinterruptszybits]{#2}}{}% + \ifstrequal{#1}{_get_Misa_A}{\hyperref[sailRISCVzzygetzyMisazyA]{#2}}{}% + \ifstrequal{#1}{_get_Misa_B}{\hyperref[sailRISCVzzygetzyMisazyB]{#2}}{}% + \ifstrequal{#1}{_get_Misa_C}{\hyperref[sailRISCVzzygetzyMisazyC]{#2}}{}% + \ifstrequal{#1}{_get_Misa_D}{\hyperref[sailRISCVzzygetzyMisazyD]{#2}}{}% + \ifstrequal{#1}{_get_Misa_E}{\hyperref[sailRISCVzzygetzyMisazyE]{#2}}{}% + \ifstrequal{#1}{_get_Misa_F}{\hyperref[sailRISCVzzygetzyMisazyF]{#2}}{}% + \ifstrequal{#1}{_get_Misa_G}{\hyperref[sailRISCVzzygetzyMisazyG]{#2}}{}% + \ifstrequal{#1}{_get_Misa_H}{\hyperref[sailRISCVzzygetzyMisazyH]{#2}}{}% + \ifstrequal{#1}{_get_Misa_I}{\hyperref[sailRISCVzzygetzyMisazyI]{#2}}{}% + \ifstrequal{#1}{_get_Misa_J}{\hyperref[sailRISCVzzygetzyMisazyJ]{#2}}{}% + \ifstrequal{#1}{_get_Misa_K}{\hyperref[sailRISCVzzygetzyMisazyK]{#2}}{}% + \ifstrequal{#1}{_get_Misa_L}{\hyperref[sailRISCVzzygetzyMisazyL]{#2}}{}% + \ifstrequal{#1}{_get_Misa_M}{\hyperref[sailRISCVzzygetzyMisazyM]{#2}}{}% + \ifstrequal{#1}{_get_Misa_MXL}{\hyperref[sailRISCVzzygetzyMisazyMXL]{#2}}{}% + \ifstrequal{#1}{_get_Misa_N}{\hyperref[sailRISCVzzygetzyMisazyN]{#2}}{}% + \ifstrequal{#1}{_get_Misa_O}{\hyperref[sailRISCVzzygetzyMisazyO]{#2}}{}% + \ifstrequal{#1}{_get_Misa_P}{\hyperref[sailRISCVzzygetzyMisazyP]{#2}}{}% + \ifstrequal{#1}{_get_Misa_Q}{\hyperref[sailRISCVzzygetzyMisazyQ]{#2}}{}% + \ifstrequal{#1}{_get_Misa_R}{\hyperref[sailRISCVzzygetzyMisazyR]{#2}}{}% + \ifstrequal{#1}{_get_Misa_S}{\hyperref[sailRISCVzzygetzyMisazyS]{#2}}{}% + \ifstrequal{#1}{_get_Misa_T}{\hyperref[sailRISCVzzygetzyMisazyT]{#2}}{}% + \ifstrequal{#1}{_get_Misa_U}{\hyperref[sailRISCVzzygetzyMisazyU]{#2}}{}% + \ifstrequal{#1}{_get_Misa_V}{\hyperref[sailRISCVzzygetzyMisazyV]{#2}}{}% + \ifstrequal{#1}{_get_Misa_W}{\hyperref[sailRISCVzzygetzyMisazyW]{#2}}{}% + \ifstrequal{#1}{_get_Misa_X}{\hyperref[sailRISCVzzygetzyMisazyX]{#2}}{}% + \ifstrequal{#1}{_get_Misa_Y}{\hyperref[sailRISCVzzygetzyMisazyY]{#2}}{}% + \ifstrequal{#1}{_get_Misa_Z}{\hyperref[sailRISCVzzygetzyMisazyZ]{#2}}{}% + \ifstrequal{#1}{_get_Misa_bits}{\hyperref[sailRISCVzzygetzyMisazybits]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_FS}{\hyperref[sailRISCVzzygetzyMstatuszyFS]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_MIE}{\hyperref[sailRISCVzzygetzyMstatuszyMIE]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_MPIE}{\hyperref[sailRISCVzzygetzyMstatuszyMPIE]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_MPP}{\hyperref[sailRISCVzzygetzyMstatuszyMPP]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_MPRV}{\hyperref[sailRISCVzzygetzyMstatuszyMPRV]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_MXR}{\hyperref[sailRISCVzzygetzyMstatuszyMXR]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_SD}{\hyperref[sailRISCVzzygetzyMstatuszySD]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_SIE}{\hyperref[sailRISCVzzygetzyMstatuszySIE]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_SPIE}{\hyperref[sailRISCVzzygetzyMstatuszySPIE]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_SPP}{\hyperref[sailRISCVzzygetzyMstatuszySPP]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_SUM}{\hyperref[sailRISCVzzygetzyMstatuszySUM]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_TSR}{\hyperref[sailRISCVzzygetzyMstatuszyTSR]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_TVM}{\hyperref[sailRISCVzzygetzyMstatuszyTVM]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_TW}{\hyperref[sailRISCVzzygetzyMstatuszyTW]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_UIE}{\hyperref[sailRISCVzzygetzyMstatuszyUIE]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_UPIE}{\hyperref[sailRISCVzzygetzyMstatuszyUPIE]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_XS}{\hyperref[sailRISCVzzygetzyMstatuszyXS]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_bits}{\hyperref[sailRISCVzzygetzyMstatuszybits]{#2}}{}% + \ifstrequal{#1}{_get_Mtvec_Base}{\hyperref[sailRISCVzzygetzyMtveczyBase]{#2}}{}% + \ifstrequal{#1}{_get_Mtvec_Mode}{\hyperref[sailRISCVzzygetzyMtveczyMode]{#2}}{}% + \ifstrequal{#1}{_get_Mtvec_bits}{\hyperref[sailRISCVzzygetzyMtveczybits]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_A}{\hyperref[sailRISCVzzygetzyPTEzyBitszyA]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_D}{\hyperref[sailRISCVzzygetzyPTEzyBitszyD]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_G}{\hyperref[sailRISCVzzygetzyPTEzyBitszyG]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_R}{\hyperref[sailRISCVzzygetzyPTEzyBitszyR]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_U}{\hyperref[sailRISCVzzygetzyPTEzyBitszyU]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_V}{\hyperref[sailRISCVzzygetzyPTEzyBitszyV]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_W}{\hyperref[sailRISCVzzygetzyPTEzyBitszyW]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_X}{\hyperref[sailRISCVzzygetzyPTEzyBitszyX]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_bits}{\hyperref[sailRISCVzzygetzyPTEzyBitszybits]{#2}}{}% + \ifstrequal{#1}{_get_Pmpcfg_ent_A}{\hyperref[sailRISCVzzygetzyPmpcfgzyentzyA]{#2}}{}% + \ifstrequal{#1}{_get_Pmpcfg_ent_L}{\hyperref[sailRISCVzzygetzyPmpcfgzyentzyL]{#2}}{}% + \ifstrequal{#1}{_get_Pmpcfg_ent_R}{\hyperref[sailRISCVzzygetzyPmpcfgzyentzyR]{#2}}{}% + \ifstrequal{#1}{_get_Pmpcfg_ent_W}{\hyperref[sailRISCVzzygetzyPmpcfgzyentzyW]{#2}}{}% + \ifstrequal{#1}{_get_Pmpcfg_ent_X}{\hyperref[sailRISCVzzygetzyPmpcfgzyentzyX]{#2}}{}% + \ifstrequal{#1}{_get_Pmpcfg_ent_bits}{\hyperref[sailRISCVzzygetzyPmpcfgzyentzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV32_PTE_BITS}{\hyperref[sailRISCVzzygetzySV32zyPTEzyBITS]{#2}}{}% + \ifstrequal{#1}{_get_SV32_PTE_PPNi}{\hyperref[sailRISCVzzygetzySV32zyPTEzyPPNi]{#2}}{}% + \ifstrequal{#1}{_get_SV32_PTE_RSW}{\hyperref[sailRISCVzzygetzySV32zyPTEzyRSW]{#2}}{}% + \ifstrequal{#1}{_get_SV32_PTE_bits}{\hyperref[sailRISCVzzygetzySV32zyPTEzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV32_Paddr_PPNi}{\hyperref[sailRISCVzzygetzySV32zyPaddrzyPPNi]{#2}}{}% + \ifstrequal{#1}{_get_SV32_Paddr_PgOfs}{\hyperref[sailRISCVzzygetzySV32zyPaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_get_SV32_Paddr_bits}{\hyperref[sailRISCVzzygetzySV32zyPaddrzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV32_Vaddr_PgOfs}{\hyperref[sailRISCVzzygetzySV32zyVaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_get_SV32_Vaddr_VPNi}{\hyperref[sailRISCVzzygetzySV32zyVaddrzyVPNi]{#2}}{}% + \ifstrequal{#1}{_get_SV32_Vaddr_bits}{\hyperref[sailRISCVzzygetzySV32zyVaddrzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV39_PTE_BITS}{\hyperref[sailRISCVzzygetzySV39zyPTEzyBITS]{#2}}{}% + \ifstrequal{#1}{_get_SV39_PTE_Ext}{\hyperref[sailRISCVzzygetzySV39zyPTEzyExt]{#2}}{}% + \ifstrequal{#1}{_get_SV39_PTE_PPNi}{\hyperref[sailRISCVzzygetzySV39zyPTEzyPPNi]{#2}}{}% + \ifstrequal{#1}{_get_SV39_PTE_RSW}{\hyperref[sailRISCVzzygetzySV39zyPTEzyRSW]{#2}}{}% + \ifstrequal{#1}{_get_SV39_PTE_bits}{\hyperref[sailRISCVzzygetzySV39zyPTEzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV39_Paddr_PPNi}{\hyperref[sailRISCVzzygetzySV39zyPaddrzyPPNi]{#2}}{}% + \ifstrequal{#1}{_get_SV39_Paddr_PgOfs}{\hyperref[sailRISCVzzygetzySV39zyPaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_get_SV39_Paddr_bits}{\hyperref[sailRISCVzzygetzySV39zyPaddrzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV39_Vaddr_PgOfs}{\hyperref[sailRISCVzzygetzySV39zyVaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_get_SV39_Vaddr_VPNi}{\hyperref[sailRISCVzzygetzySV39zyVaddrzyVPNi]{#2}}{}% + \ifstrequal{#1}{_get_SV39_Vaddr_bits}{\hyperref[sailRISCVzzygetzySV39zyVaddrzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV48_PTE_BITS}{\hyperref[sailRISCVzzygetzySV48zyPTEzyBITS]{#2}}{}% + \ifstrequal{#1}{_get_SV48_PTE_Ext}{\hyperref[sailRISCVzzygetzySV48zyPTEzyExt]{#2}}{}% + \ifstrequal{#1}{_get_SV48_PTE_PPNi}{\hyperref[sailRISCVzzygetzySV48zyPTEzyPPNi]{#2}}{}% + \ifstrequal{#1}{_get_SV48_PTE_RSW}{\hyperref[sailRISCVzzygetzySV48zyPTEzyRSW]{#2}}{}% + \ifstrequal{#1}{_get_SV48_PTE_bits}{\hyperref[sailRISCVzzygetzySV48zyPTEzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV48_Paddr_PPNi}{\hyperref[sailRISCVzzygetzySV48zyPaddrzyPPNi]{#2}}{}% + \ifstrequal{#1}{_get_SV48_Paddr_PgOfs}{\hyperref[sailRISCVzzygetzySV48zyPaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_get_SV48_Paddr_bits}{\hyperref[sailRISCVzzygetzySV48zyPaddrzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV48_Vaddr_PgOfs}{\hyperref[sailRISCVzzygetzySV48zyVaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_get_SV48_Vaddr_VPNi}{\hyperref[sailRISCVzzygetzySV48zyVaddrzyVPNi]{#2}}{}% + \ifstrequal{#1}{_get_SV48_Vaddr_bits}{\hyperref[sailRISCVzzygetzySV48zyVaddrzybits]{#2}}{}% + \ifstrequal{#1}{_get_Satp32_Asid}{\hyperref[sailRISCVzzygetzySatp32zyAsid]{#2}}{}% + \ifstrequal{#1}{_get_Satp32_Mode}{\hyperref[sailRISCVzzygetzySatp32zyMode]{#2}}{}% + \ifstrequal{#1}{_get_Satp32_PPN}{\hyperref[sailRISCVzzygetzySatp32zyPPN]{#2}}{}% + \ifstrequal{#1}{_get_Satp32_bits}{\hyperref[sailRISCVzzygetzySatp32zybits]{#2}}{}% + \ifstrequal{#1}{_get_Satp64_Asid}{\hyperref[sailRISCVzzygetzySatp64zyAsid]{#2}}{}% + \ifstrequal{#1}{_get_Satp64_Mode}{\hyperref[sailRISCVzzygetzySatp64zyMode]{#2}}{}% + \ifstrequal{#1}{_get_Satp64_PPN}{\hyperref[sailRISCVzzygetzySatp64zyPPN]{#2}}{}% + \ifstrequal{#1}{_get_Satp64_bits}{\hyperref[sailRISCVzzygetzySatp64zybits]{#2}}{}% + \ifstrequal{#1}{_get_Sedeleg_Breakpoint}{\hyperref[sailRISCVzzygetzySedelegzyBreakpoint]{#2}}{}% + \ifstrequal{#1}{_get_Sedeleg_Fetch_Access_Fault}{\hyperref[sailRISCVzzygetzySedelegzyFetchzyAccesszyFault]{#2}}{}% + \ifstrequal{#1}{_get_Sedeleg_Fetch_Addr_Align}{\hyperref[sailRISCVzzygetzySedelegzyFetchzyAddrzyAlign]{#2}}{}% + \ifstrequal{#1}{_get_Sedeleg_Illegal_Instr}{\hyperref[sailRISCVzzygetzySedelegzyIllegalzyInstr]{#2}}{}% + \ifstrequal{#1}{_get_Sedeleg_Load_Access_Fault}{\hyperref[sailRISCVzzygetzySedelegzyLoadzyAccesszyFault]{#2}}{}% + \ifstrequal{#1}{_get_Sedeleg_Load_Addr_Align}{\hyperref[sailRISCVzzygetzySedelegzyLoadzyAddrzyAlign]{#2}}{}% + \ifstrequal{#1}{_get_Sedeleg_SAMO_Access_Fault}{\hyperref[sailRISCVzzygetzySedelegzySAMOzyAccesszyFault]{#2}}{}% + \ifstrequal{#1}{_get_Sedeleg_SAMO_Addr_Align}{\hyperref[sailRISCVzzygetzySedelegzySAMOzyAddrzyAlign]{#2}}{}% + \ifstrequal{#1}{_get_Sedeleg_UEnvCall}{\hyperref[sailRISCVzzygetzySedelegzyUEnvCall]{#2}}{}% + \ifstrequal{#1}{_get_Sedeleg_bits}{\hyperref[sailRISCVzzygetzySedelegzybits]{#2}}{}% + \ifstrequal{#1}{_get_Sinterrupts_SEI}{\hyperref[sailRISCVzzygetzySinterruptszySEI]{#2}}{}% + \ifstrequal{#1}{_get_Sinterrupts_SSI}{\hyperref[sailRISCVzzygetzySinterruptszySSI]{#2}}{}% + \ifstrequal{#1}{_get_Sinterrupts_STI}{\hyperref[sailRISCVzzygetzySinterruptszySTI]{#2}}{}% + \ifstrequal{#1}{_get_Sinterrupts_UEI}{\hyperref[sailRISCVzzygetzySinterruptszyUEI]{#2}}{}% + \ifstrequal{#1}{_get_Sinterrupts_USI}{\hyperref[sailRISCVzzygetzySinterruptszyUSI]{#2}}{}% + \ifstrequal{#1}{_get_Sinterrupts_UTI}{\hyperref[sailRISCVzzygetzySinterruptszyUTI]{#2}}{}% + \ifstrequal{#1}{_get_Sinterrupts_bits}{\hyperref[sailRISCVzzygetzySinterruptszybits]{#2}}{}% + \ifstrequal{#1}{_get_Sstatus_FS}{\hyperref[sailRISCVzzygetzySstatuszyFS]{#2}}{}% + \ifstrequal{#1}{_get_Sstatus_MXR}{\hyperref[sailRISCVzzygetzySstatuszyMXR]{#2}}{}% + \ifstrequal{#1}{_get_Sstatus_SD}{\hyperref[sailRISCVzzygetzySstatuszySD]{#2}}{}% + \ifstrequal{#1}{_get_Sstatus_SIE}{\hyperref[sailRISCVzzygetzySstatuszySIE]{#2}}{}% + \ifstrequal{#1}{_get_Sstatus_SPIE}{\hyperref[sailRISCVzzygetzySstatuszySPIE]{#2}}{}% + \ifstrequal{#1}{_get_Sstatus_SPP}{\hyperref[sailRISCVzzygetzySstatuszySPP]{#2}}{}% + \ifstrequal{#1}{_get_Sstatus_SUM}{\hyperref[sailRISCVzzygetzySstatuszySUM]{#2}}{}% + \ifstrequal{#1}{_get_Sstatus_UIE}{\hyperref[sailRISCVzzygetzySstatuszyUIE]{#2}}{}% + \ifstrequal{#1}{_get_Sstatus_UPIE}{\hyperref[sailRISCVzzygetzySstatuszyUPIE]{#2}}{}% + \ifstrequal{#1}{_get_Sstatus_XS}{\hyperref[sailRISCVzzygetzySstatuszyXS]{#2}}{}% + \ifstrequal{#1}{_get_Sstatus_bits}{\hyperref[sailRISCVzzygetzySstatuszybits]{#2}}{}% + \ifstrequal{#1}{_get_Uinterrupts_UEI}{\hyperref[sailRISCVzzygetzyUinterruptszyUEI]{#2}}{}% + \ifstrequal{#1}{_get_Uinterrupts_USI}{\hyperref[sailRISCVzzygetzyUinterruptszyUSI]{#2}}{}% + \ifstrequal{#1}{_get_Uinterrupts_UTI}{\hyperref[sailRISCVzzygetzyUinterruptszyUTI]{#2}}{}% + \ifstrequal{#1}{_get_Uinterrupts_bits}{\hyperref[sailRISCVzzygetzyUinterruptszybits]{#2}}{}% + \ifstrequal{#1}{_get_Ustatus_UIE}{\hyperref[sailRISCVzzygetzyUstatuszyUIE]{#2}}{}% + \ifstrequal{#1}{_get_Ustatus_UPIE}{\hyperref[sailRISCVzzygetzyUstatuszyUPIE]{#2}}{}% + \ifstrequal{#1}{_get_Ustatus_bits}{\hyperref[sailRISCVzzygetzyUstatuszybits]{#2}}{}% + \ifstrequal{#1}{_get_ccsr_bits}{\hyperref[sailRISCVzzygetzyccsrzybits]{#2}}{}% + \ifstrequal{#1}{_get_ccsr_cap_idx}{\hyperref[sailRISCVzzygetzyccsrzycapzyidx]{#2}}{}% + \ifstrequal{#1}{_get_ccsr_cause}{\hyperref[sailRISCVzzygetzyccsrzycause]{#2}}{}% + \ifstrequal{#1}{_get_ccsr_d}{\hyperref[sailRISCVzzygetzyccsrzyd]{#2}}{}% + \ifstrequal{#1}{_get_ccsr_e}{\hyperref[sailRISCVzzygetzyccsrzye]{#2}}{}% + \ifstrequal{#1}{_get_htif_cmd_bits}{\hyperref[sailRISCVzzygetzyhtifzycmdzybits]{#2}}{}% + \ifstrequal{#1}{_get_htif_cmd_cmd}{\hyperref[sailRISCVzzygetzyhtifzycmdzycmd]{#2}}{}% + \ifstrequal{#1}{_get_htif_cmd_device}{\hyperref[sailRISCVzzygetzyhtifzycmdzydevice]{#2}}{}% + \ifstrequal{#1}{_get_htif_cmd_payload}{\hyperref[sailRISCVzzygetzyhtifzycmdzypayload]{#2}}{}% + \ifstrequal{#1}{_reg_deref}{\hyperref[sailRISCVzzyregzyderef]{#2}}{}% + \ifstrequal{#1}{_set_Counteren_CY}{\hyperref[sailRISCVzzysetzyCounterenzyCY]{#2}}{}% + \ifstrequal{#1}{_set_Counteren_HPM}{\hyperref[sailRISCVzzysetzyCounterenzyHPM]{#2}}{}% + \ifstrequal{#1}{_set_Counteren_IR}{\hyperref[sailRISCVzzysetzyCounterenzyIR]{#2}}{}% + \ifstrequal{#1}{_set_Counteren_TM}{\hyperref[sailRISCVzzysetzyCounterenzyTM]{#2}}{}% + \ifstrequal{#1}{_set_Counteren_bits}{\hyperref[sailRISCVzzysetzyCounterenzybits]{#2}}{}% + \ifstrequal{#1}{_set_Counterin_CY}{\hyperref[sailRISCVzzysetzyCounterinzyCY]{#2}}{}% + \ifstrequal{#1}{_set_Counterin_IR}{\hyperref[sailRISCVzzysetzyCounterinzyIR]{#2}}{}% + \ifstrequal{#1}{_set_Counterin_bits}{\hyperref[sailRISCVzzysetzyCounterinzybits]{#2}}{}% + \ifstrequal{#1}{_set_Ext_PTE_Bits_CapRead}{\hyperref[sailRISCVzzysetzyExtzyPTEzyBitszyCapRead]{#2}}{}% + \ifstrequal{#1}{_set_Ext_PTE_Bits_CapWrite}{\hyperref[sailRISCVzzysetzyExtzyPTEzyBitszyCapWrite]{#2}}{}% + \ifstrequal{#1}{_set_Ext_PTE_Bits_bits}{\hyperref[sailRISCVzzysetzyExtzyPTEzyBitszybits]{#2}}{}% + \ifstrequal{#1}{_set_Fcsr_FFLAGS}{\hyperref[sailRISCVzzysetzyFcsrzyFFLAGS]{#2}}{}% + \ifstrequal{#1}{_set_Fcsr_FRM}{\hyperref[sailRISCVzzysetzyFcsrzyFRM]{#2}}{}% + \ifstrequal{#1}{_set_Fcsr_bits}{\hyperref[sailRISCVzzysetzyFcsrzybits]{#2}}{}% + \ifstrequal{#1}{_set_Mcause_Cause}{\hyperref[sailRISCVzzysetzyMcausezyCause]{#2}}{}% + \ifstrequal{#1}{_set_Mcause_IsInterrupt}{\hyperref[sailRISCVzzysetzyMcausezyIsInterrupt]{#2}}{}% + \ifstrequal{#1}{_set_Mcause_bits}{\hyperref[sailRISCVzzysetzyMcausezybits]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_Breakpoint}{\hyperref[sailRISCVzzysetzyMedelegzyBreakpoint]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_Fetch_Access_Fault}{\hyperref[sailRISCVzzysetzyMedelegzyFetchzyAccesszyFault]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_Fetch_Addr_Align}{\hyperref[sailRISCVzzysetzyMedelegzyFetchzyAddrzyAlign]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_Fetch_Page_Fault}{\hyperref[sailRISCVzzysetzyMedelegzyFetchzyPagezyFault]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_Illegal_Instr}{\hyperref[sailRISCVzzysetzyMedelegzyIllegalzyInstr]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_Load_Access_Fault}{\hyperref[sailRISCVzzysetzyMedelegzyLoadzyAccesszyFault]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_Load_Addr_Align}{\hyperref[sailRISCVzzysetzyMedelegzyLoadzyAddrzyAlign]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_Load_Page_Fault}{\hyperref[sailRISCVzzysetzyMedelegzyLoadzyPagezyFault]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_MEnvCall}{\hyperref[sailRISCVzzysetzyMedelegzyMEnvCall]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_SAMO_Access_Fault}{\hyperref[sailRISCVzzysetzyMedelegzySAMOzyAccesszyFault]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_SAMO_Addr_Align}{\hyperref[sailRISCVzzysetzyMedelegzySAMOzyAddrzyAlign]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_SAMO_Page_Fault}{\hyperref[sailRISCVzzysetzyMedelegzySAMOzyPagezyFault]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_SEnvCall}{\hyperref[sailRISCVzzysetzyMedelegzySEnvCall]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_UEnvCall}{\hyperref[sailRISCVzzysetzyMedelegzyUEnvCall]{#2}}{}% + \ifstrequal{#1}{_set_Medeleg_bits}{\hyperref[sailRISCVzzysetzyMedelegzybits]{#2}}{}% + \ifstrequal{#1}{_set_Minterrupts_MEI}{\hyperref[sailRISCVzzysetzyMinterruptszyMEI]{#2}}{}% + \ifstrequal{#1}{_set_Minterrupts_MSI}{\hyperref[sailRISCVzzysetzyMinterruptszyMSI]{#2}}{}% + \ifstrequal{#1}{_set_Minterrupts_MTI}{\hyperref[sailRISCVzzysetzyMinterruptszyMTI]{#2}}{}% + \ifstrequal{#1}{_set_Minterrupts_SEI}{\hyperref[sailRISCVzzysetzyMinterruptszySEI]{#2}}{}% + \ifstrequal{#1}{_set_Minterrupts_SSI}{\hyperref[sailRISCVzzysetzyMinterruptszySSI]{#2}}{}% + \ifstrequal{#1}{_set_Minterrupts_STI}{\hyperref[sailRISCVzzysetzyMinterruptszySTI]{#2}}{}% + \ifstrequal{#1}{_set_Minterrupts_UEI}{\hyperref[sailRISCVzzysetzyMinterruptszyUEI]{#2}}{}% + \ifstrequal{#1}{_set_Minterrupts_USI}{\hyperref[sailRISCVzzysetzyMinterruptszyUSI]{#2}}{}% + \ifstrequal{#1}{_set_Minterrupts_UTI}{\hyperref[sailRISCVzzysetzyMinterruptszyUTI]{#2}}{}% + \ifstrequal{#1}{_set_Minterrupts_bits}{\hyperref[sailRISCVzzysetzyMinterruptszybits]{#2}}{}% + \ifstrequal{#1}{_set_Misa_A}{\hyperref[sailRISCVzzysetzyMisazyA]{#2}}{}% + \ifstrequal{#1}{_set_Misa_B}{\hyperref[sailRISCVzzysetzyMisazyB]{#2}}{}% + \ifstrequal{#1}{_set_Misa_C}{\hyperref[sailRISCVzzysetzyMisazyC]{#2}}{}% + \ifstrequal{#1}{_set_Misa_D}{\hyperref[sailRISCVzzysetzyMisazyD]{#2}}{}% + \ifstrequal{#1}{_set_Misa_E}{\hyperref[sailRISCVzzysetzyMisazyE]{#2}}{}% + \ifstrequal{#1}{_set_Misa_F}{\hyperref[sailRISCVzzysetzyMisazyF]{#2}}{}% + \ifstrequal{#1}{_set_Misa_G}{\hyperref[sailRISCVzzysetzyMisazyG]{#2}}{}% + \ifstrequal{#1}{_set_Misa_H}{\hyperref[sailRISCVzzysetzyMisazyH]{#2}}{}% + \ifstrequal{#1}{_set_Misa_I}{\hyperref[sailRISCVzzysetzyMisazyI]{#2}}{}% + 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\ifstrequal{#1}{_set_Misa_V}{\hyperref[sailRISCVzzysetzyMisazyV]{#2}}{}% + \ifstrequal{#1}{_set_Misa_W}{\hyperref[sailRISCVzzysetzyMisazyW]{#2}}{}% + \ifstrequal{#1}{_set_Misa_X}{\hyperref[sailRISCVzzysetzyMisazyX]{#2}}{}% + \ifstrequal{#1}{_set_Misa_Y}{\hyperref[sailRISCVzzysetzyMisazyY]{#2}}{}% + \ifstrequal{#1}{_set_Misa_Z}{\hyperref[sailRISCVzzysetzyMisazyZ]{#2}}{}% + \ifstrequal{#1}{_set_Misa_bits}{\hyperref[sailRISCVzzysetzyMisazybits]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_FS}{\hyperref[sailRISCVzzysetzyMstatuszyFS]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_MIE}{\hyperref[sailRISCVzzysetzyMstatuszyMIE]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_MPIE}{\hyperref[sailRISCVzzysetzyMstatuszyMPIE]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_MPP}{\hyperref[sailRISCVzzysetzyMstatuszyMPP]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_MPRV}{\hyperref[sailRISCVzzysetzyMstatuszyMPRV]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_MXR}{\hyperref[sailRISCVzzysetzyMstatuszyMXR]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_SD}{\hyperref[sailRISCVzzysetzyMstatuszySD]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_SIE}{\hyperref[sailRISCVzzysetzyMstatuszySIE]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_SPIE}{\hyperref[sailRISCVzzysetzyMstatuszySPIE]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_SPP}{\hyperref[sailRISCVzzysetzyMstatuszySPP]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_SUM}{\hyperref[sailRISCVzzysetzyMstatuszySUM]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_TSR}{\hyperref[sailRISCVzzysetzyMstatuszyTSR]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_TVM}{\hyperref[sailRISCVzzysetzyMstatuszyTVM]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_TW}{\hyperref[sailRISCVzzysetzyMstatuszyTW]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_UIE}{\hyperref[sailRISCVzzysetzyMstatuszyUIE]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_UPIE}{\hyperref[sailRISCVzzysetzyMstatuszyUPIE]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_XS}{\hyperref[sailRISCVzzysetzyMstatuszyXS]{#2}}{}% + \ifstrequal{#1}{_set_Mstatus_bits}{\hyperref[sailRISCVzzysetzyMstatuszybits]{#2}}{}% + \ifstrequal{#1}{_set_Mtvec_Base}{\hyperref[sailRISCVzzysetzyMtveczyBase]{#2}}{}% + \ifstrequal{#1}{_set_Mtvec_Mode}{\hyperref[sailRISCVzzysetzyMtveczyMode]{#2}}{}% + \ifstrequal{#1}{_set_Mtvec_bits}{\hyperref[sailRISCVzzysetzyMtveczybits]{#2}}{}% + \ifstrequal{#1}{_set_PTE_Bits_A}{\hyperref[sailRISCVzzysetzyPTEzyBitszyA]{#2}}{}% + \ifstrequal{#1}{_set_PTE_Bits_D}{\hyperref[sailRISCVzzysetzyPTEzyBitszyD]{#2}}{}% + \ifstrequal{#1}{_set_PTE_Bits_G}{\hyperref[sailRISCVzzysetzyPTEzyBitszyG]{#2}}{}% + \ifstrequal{#1}{_set_PTE_Bits_R}{\hyperref[sailRISCVzzysetzyPTEzyBitszyR]{#2}}{}% + \ifstrequal{#1}{_set_PTE_Bits_U}{\hyperref[sailRISCVzzysetzyPTEzyBitszyU]{#2}}{}% + \ifstrequal{#1}{_set_PTE_Bits_V}{\hyperref[sailRISCVzzysetzyPTEzyBitszyV]{#2}}{}% + \ifstrequal{#1}{_set_PTE_Bits_W}{\hyperref[sailRISCVzzysetzyPTEzyBitszyW]{#2}}{}% + \ifstrequal{#1}{_set_PTE_Bits_X}{\hyperref[sailRISCVzzysetzyPTEzyBitszyX]{#2}}{}% + \ifstrequal{#1}{_set_PTE_Bits_bits}{\hyperref[sailRISCVzzysetzyPTEzyBitszybits]{#2}}{}% + \ifstrequal{#1}{_set_Pmpcfg_ent_A}{\hyperref[sailRISCVzzysetzyPmpcfgzyentzyA]{#2}}{}% + \ifstrequal{#1}{_set_Pmpcfg_ent_L}{\hyperref[sailRISCVzzysetzyPmpcfgzyentzyL]{#2}}{}% + \ifstrequal{#1}{_set_Pmpcfg_ent_R}{\hyperref[sailRISCVzzysetzyPmpcfgzyentzyR]{#2}}{}% + \ifstrequal{#1}{_set_Pmpcfg_ent_W}{\hyperref[sailRISCVzzysetzyPmpcfgzyentzyW]{#2}}{}% + \ifstrequal{#1}{_set_Pmpcfg_ent_X}{\hyperref[sailRISCVzzysetzyPmpcfgzyentzyX]{#2}}{}% + \ifstrequal{#1}{_set_Pmpcfg_ent_bits}{\hyperref[sailRISCVzzysetzyPmpcfgzyentzybits]{#2}}{}% + \ifstrequal{#1}{_set_SV32_PTE_BITS}{\hyperref[sailRISCVzzysetzySV32zyPTEzyBITS]{#2}}{}% + \ifstrequal{#1}{_set_SV32_PTE_PPNi}{\hyperref[sailRISCVzzysetzySV32zyPTEzyPPNi]{#2}}{}% + \ifstrequal{#1}{_set_SV32_PTE_RSW}{\hyperref[sailRISCVzzysetzySV32zyPTEzyRSW]{#2}}{}% + \ifstrequal{#1}{_set_SV32_PTE_bits}{\hyperref[sailRISCVzzysetzySV32zyPTEzybits]{#2}}{}% + \ifstrequal{#1}{_set_SV32_Paddr_PPNi}{\hyperref[sailRISCVzzysetzySV32zyPaddrzyPPNi]{#2}}{}% + \ifstrequal{#1}{_set_SV32_Paddr_PgOfs}{\hyperref[sailRISCVzzysetzySV32zyPaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_set_SV32_Paddr_bits}{\hyperref[sailRISCVzzysetzySV32zyPaddrzybits]{#2}}{}% + \ifstrequal{#1}{_set_SV32_Vaddr_PgOfs}{\hyperref[sailRISCVzzysetzySV32zyVaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_set_SV32_Vaddr_VPNi}{\hyperref[sailRISCVzzysetzySV32zyVaddrzyVPNi]{#2}}{}% + \ifstrequal{#1}{_set_SV32_Vaddr_bits}{\hyperref[sailRISCVzzysetzySV32zyVaddrzybits]{#2}}{}% + \ifstrequal{#1}{_set_SV39_PTE_BITS}{\hyperref[sailRISCVzzysetzySV39zyPTEzyBITS]{#2}}{}% + \ifstrequal{#1}{_set_SV39_PTE_Ext}{\hyperref[sailRISCVzzysetzySV39zyPTEzyExt]{#2}}{}% + \ifstrequal{#1}{_set_SV39_PTE_PPNi}{\hyperref[sailRISCVzzysetzySV39zyPTEzyPPNi]{#2}}{}% + \ifstrequal{#1}{_set_SV39_PTE_RSW}{\hyperref[sailRISCVzzysetzySV39zyPTEzyRSW]{#2}}{}% + \ifstrequal{#1}{_set_SV39_PTE_bits}{\hyperref[sailRISCVzzysetzySV39zyPTEzybits]{#2}}{}% + \ifstrequal{#1}{_set_SV39_Paddr_PPNi}{\hyperref[sailRISCVzzysetzySV39zyPaddrzyPPNi]{#2}}{}% + \ifstrequal{#1}{_set_SV39_Paddr_PgOfs}{\hyperref[sailRISCVzzysetzySV39zyPaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_set_SV39_Paddr_bits}{\hyperref[sailRISCVzzysetzySV39zyPaddrzybits]{#2}}{}% + \ifstrequal{#1}{_set_SV39_Vaddr_PgOfs}{\hyperref[sailRISCVzzysetzySV39zyVaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_set_SV39_Vaddr_VPNi}{\hyperref[sailRISCVzzysetzySV39zyVaddrzyVPNi]{#2}}{}% + \ifstrequal{#1}{_set_SV39_Vaddr_bits}{\hyperref[sailRISCVzzysetzySV39zyVaddrzybits]{#2}}{}% + \ifstrequal{#1}{_set_SV48_PTE_BITS}{\hyperref[sailRISCVzzysetzySV48zyPTEzyBITS]{#2}}{}% + \ifstrequal{#1}{_set_SV48_PTE_Ext}{\hyperref[sailRISCVzzysetzySV48zyPTEzyExt]{#2}}{}% + \ifstrequal{#1}{_set_SV48_PTE_PPNi}{\hyperref[sailRISCVzzysetzySV48zyPTEzyPPNi]{#2}}{}% + \ifstrequal{#1}{_set_SV48_PTE_RSW}{\hyperref[sailRISCVzzysetzySV48zyPTEzyRSW]{#2}}{}% + \ifstrequal{#1}{_set_SV48_PTE_bits}{\hyperref[sailRISCVzzysetzySV48zyPTEzybits]{#2}}{}% + \ifstrequal{#1}{_set_SV48_Paddr_PPNi}{\hyperref[sailRISCVzzysetzySV48zyPaddrzyPPNi]{#2}}{}% + \ifstrequal{#1}{_set_SV48_Paddr_PgOfs}{\hyperref[sailRISCVzzysetzySV48zyPaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_set_SV48_Paddr_bits}{\hyperref[sailRISCVzzysetzySV48zyPaddrzybits]{#2}}{}% + \ifstrequal{#1}{_set_SV48_Vaddr_PgOfs}{\hyperref[sailRISCVzzysetzySV48zyVaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_set_SV48_Vaddr_VPNi}{\hyperref[sailRISCVzzysetzySV48zyVaddrzyVPNi]{#2}}{}% + \ifstrequal{#1}{_set_SV48_Vaddr_bits}{\hyperref[sailRISCVzzysetzySV48zyVaddrzybits]{#2}}{}% + \ifstrequal{#1}{_set_Satp32_Asid}{\hyperref[sailRISCVzzysetzySatp32zyAsid]{#2}}{}% + \ifstrequal{#1}{_set_Satp32_Mode}{\hyperref[sailRISCVzzysetzySatp32zyMode]{#2}}{}% + \ifstrequal{#1}{_set_Satp32_PPN}{\hyperref[sailRISCVzzysetzySatp32zyPPN]{#2}}{}% + \ifstrequal{#1}{_set_Satp32_bits}{\hyperref[sailRISCVzzysetzySatp32zybits]{#2}}{}% + \ifstrequal{#1}{_set_Satp64_Asid}{\hyperref[sailRISCVzzysetzySatp64zyAsid]{#2}}{}% + \ifstrequal{#1}{_set_Satp64_Mode}{\hyperref[sailRISCVzzysetzySatp64zyMode]{#2}}{}% + \ifstrequal{#1}{_set_Satp64_PPN}{\hyperref[sailRISCVzzysetzySatp64zyPPN]{#2}}{}% + \ifstrequal{#1}{_set_Satp64_bits}{\hyperref[sailRISCVzzysetzySatp64zybits]{#2}}{}% + \ifstrequal{#1}{_set_Sedeleg_Breakpoint}{\hyperref[sailRISCVzzysetzySedelegzyBreakpoint]{#2}}{}% + \ifstrequal{#1}{_set_Sedeleg_Fetch_Access_Fault}{\hyperref[sailRISCVzzysetzySedelegzyFetchzyAccesszyFault]{#2}}{}% + \ifstrequal{#1}{_set_Sedeleg_Fetch_Addr_Align}{\hyperref[sailRISCVzzysetzySedelegzyFetchzyAddrzyAlign]{#2}}{}% + \ifstrequal{#1}{_set_Sedeleg_Illegal_Instr}{\hyperref[sailRISCVzzysetzySedelegzyIllegalzyInstr]{#2}}{}% + \ifstrequal{#1}{_set_Sedeleg_Load_Access_Fault}{\hyperref[sailRISCVzzysetzySedelegzyLoadzyAccesszyFault]{#2}}{}% + \ifstrequal{#1}{_set_Sedeleg_Load_Addr_Align}{\hyperref[sailRISCVzzysetzySedelegzyLoadzyAddrzyAlign]{#2}}{}% + \ifstrequal{#1}{_set_Sedeleg_SAMO_Access_Fault}{\hyperref[sailRISCVzzysetzySedelegzySAMOzyAccesszyFault]{#2}}{}% + \ifstrequal{#1}{_set_Sedeleg_SAMO_Addr_Align}{\hyperref[sailRISCVzzysetzySedelegzySAMOzyAddrzyAlign]{#2}}{}% + \ifstrequal{#1}{_set_Sedeleg_UEnvCall}{\hyperref[sailRISCVzzysetzySedelegzyUEnvCall]{#2}}{}% + \ifstrequal{#1}{_set_Sedeleg_bits}{\hyperref[sailRISCVzzysetzySedelegzybits]{#2}}{}% + \ifstrequal{#1}{_set_Sinterrupts_SEI}{\hyperref[sailRISCVzzysetzySinterruptszySEI]{#2}}{}% + \ifstrequal{#1}{_set_Sinterrupts_SSI}{\hyperref[sailRISCVzzysetzySinterruptszySSI]{#2}}{}% + \ifstrequal{#1}{_set_Sinterrupts_STI}{\hyperref[sailRISCVzzysetzySinterruptszySTI]{#2}}{}% + \ifstrequal{#1}{_set_Sinterrupts_UEI}{\hyperref[sailRISCVzzysetzySinterruptszyUEI]{#2}}{}% + \ifstrequal{#1}{_set_Sinterrupts_USI}{\hyperref[sailRISCVzzysetzySinterruptszyUSI]{#2}}{}% + \ifstrequal{#1}{_set_Sinterrupts_UTI}{\hyperref[sailRISCVzzysetzySinterruptszyUTI]{#2}}{}% + \ifstrequal{#1}{_set_Sinterrupts_bits}{\hyperref[sailRISCVzzysetzySinterruptszybits]{#2}}{}% + \ifstrequal{#1}{_set_Sstatus_FS}{\hyperref[sailRISCVzzysetzySstatuszyFS]{#2}}{}% + \ifstrequal{#1}{_set_Sstatus_MXR}{\hyperref[sailRISCVzzysetzySstatuszyMXR]{#2}}{}% + \ifstrequal{#1}{_set_Sstatus_SD}{\hyperref[sailRISCVzzysetzySstatuszySD]{#2}}{}% + \ifstrequal{#1}{_set_Sstatus_SIE}{\hyperref[sailRISCVzzysetzySstatuszySIE]{#2}}{}% + \ifstrequal{#1}{_set_Sstatus_SPIE}{\hyperref[sailRISCVzzysetzySstatuszySPIE]{#2}}{}% + \ifstrequal{#1}{_set_Sstatus_SPP}{\hyperref[sailRISCVzzysetzySstatuszySPP]{#2}}{}% + \ifstrequal{#1}{_set_Sstatus_SUM}{\hyperref[sailRISCVzzysetzySstatuszySUM]{#2}}{}% + \ifstrequal{#1}{_set_Sstatus_UIE}{\hyperref[sailRISCVzzysetzySstatuszyUIE]{#2}}{}% + \ifstrequal{#1}{_set_Sstatus_UPIE}{\hyperref[sailRISCVzzysetzySstatuszyUPIE]{#2}}{}% + \ifstrequal{#1}{_set_Sstatus_XS}{\hyperref[sailRISCVzzysetzySstatuszyXS]{#2}}{}% + \ifstrequal{#1}{_set_Sstatus_bits}{\hyperref[sailRISCVzzysetzySstatuszybits]{#2}}{}% + \ifstrequal{#1}{_set_Uinterrupts_UEI}{\hyperref[sailRISCVzzysetzyUinterruptszyUEI]{#2}}{}% + \ifstrequal{#1}{_set_Uinterrupts_USI}{\hyperref[sailRISCVzzysetzyUinterruptszyUSI]{#2}}{}% + \ifstrequal{#1}{_set_Uinterrupts_UTI}{\hyperref[sailRISCVzzysetzyUinterruptszyUTI]{#2}}{}% + \ifstrequal{#1}{_set_Uinterrupts_bits}{\hyperref[sailRISCVzzysetzyUinterruptszybits]{#2}}{}% + \ifstrequal{#1}{_set_Ustatus_UIE}{\hyperref[sailRISCVzzysetzyUstatuszyUIE]{#2}}{}% + \ifstrequal{#1}{_set_Ustatus_UPIE}{\hyperref[sailRISCVzzysetzyUstatuszyUPIE]{#2}}{}% + \ifstrequal{#1}{_set_Ustatus_bits}{\hyperref[sailRISCVzzysetzyUstatuszybits]{#2}}{}% + \ifstrequal{#1}{_set_ccsr_bits}{\hyperref[sailRISCVzzysetzyccsrzybits]{#2}}{}% + \ifstrequal{#1}{_set_ccsr_cap_idx}{\hyperref[sailRISCVzzysetzyccsrzycapzyidx]{#2}}{}% + \ifstrequal{#1}{_set_ccsr_cause}{\hyperref[sailRISCVzzysetzyccsrzycause]{#2}}{}% + \ifstrequal{#1}{_set_ccsr_d}{\hyperref[sailRISCVzzysetzyccsrzyd]{#2}}{}% + \ifstrequal{#1}{_set_ccsr_e}{\hyperref[sailRISCVzzysetzyccsrzye]{#2}}{}% + \ifstrequal{#1}{_set_htif_cmd_bits}{\hyperref[sailRISCVzzysetzyhtifzycmdzybits]{#2}}{}% + \ifstrequal{#1}{_set_htif_cmd_cmd}{\hyperref[sailRISCVzzysetzyhtifzycmdzycmd]{#2}}{}% + \ifstrequal{#1}{_set_htif_cmd_device}{\hyperref[sailRISCVzzysetzyhtifzycmdzydevice]{#2}}{}% + \ifstrequal{#1}{_set_htif_cmd_payload}{\hyperref[sailRISCVzzysetzyhtifzycmdzypayload]{#2}}{}% + \ifstrequal{#1}{_shl1}{\hyperref[sailRISCVzzyshl1]{#2}}{}% + \ifstrequal{#1}{_shl32}{\hyperref[sailRISCVzzyshl32]{#2}}{}% + \ifstrequal{#1}{_shl8}{\hyperref[sailRISCVzzyshl8]{#2}}{}% + \ifstrequal{#1}{_shl_int}{\hyperref[sailRISCVzzyshlzyint]{#2}}{}% + \ifstrequal{#1}{_shr32}{\hyperref[sailRISCVzzyshr32]{#2}}{}% + \ifstrequal{#1}{_shr_int}{\hyperref[sailRISCVzzyshrzyint]{#2}}{}% + \ifstrequal{#1}{_tmod_int}{\hyperref[sailRISCVzzytmodzyint]{#2}}{}% + \ifstrequal{#1}{_tmod_int_positive}{\hyperref[sailRISCVzzytmodzyintzypositive]{#2}}{}% + \ifstrequal{#1}{_update_Counteren_CY}{\hyperref[sailRISCVzzyupdatezyCounterenzyCY]{#2}}{}% + \ifstrequal{#1}{_update_Counteren_HPM}{\hyperref[sailRISCVzzyupdatezyCounterenzyHPM]{#2}}{}% + \ifstrequal{#1}{_update_Counteren_IR}{\hyperref[sailRISCVzzyupdatezyCounterenzyIR]{#2}}{}% + \ifstrequal{#1}{_update_Counteren_TM}{\hyperref[sailRISCVzzyupdatezyCounterenzyTM]{#2}}{}% + \ifstrequal{#1}{_update_Counteren_bits}{\hyperref[sailRISCVzzyupdatezyCounterenzybits]{#2}}{}% + \ifstrequal{#1}{_update_Counterin_CY}{\hyperref[sailRISCVzzyupdatezyCounterinzyCY]{#2}}{}% + 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\ifstrequal{#1}{f_bin_op_S_of_num}{\hyperref[sailRISCVzfzybinzyopzySzyofzynum]{#2}}{}% + \ifstrequal{#1}{f_bin_rm_op_D_of_num}{\hyperref[sailRISCVzfzybinzyrmzyopzyDzyofzynum]{#2}}{}% + \ifstrequal{#1}{f_bin_rm_op_S_of_num}{\hyperref[sailRISCVzfzybinzyrmzyopzySzyofzynum]{#2}}{}% + \ifstrequal{#1}{f_bin_rm_type_mnemonic_D}{\hyperref[sailRISCVzfzybinzyrmzytypezymnemoniczyD]{#2}}{}% + \ifstrequal{#1}{f_bin_rm_type_mnemonic_S}{\hyperref[sailRISCVzfzybinzyrmzytypezymnemoniczyS]{#2}}{}% + \ifstrequal{#1}{f_bin_type_mnemonic_D}{\hyperref[sailRISCVzfzybinzytypezymnemoniczyD]{#2}}{}% + \ifstrequal{#1}{f_bin_type_mnemonic_S}{\hyperref[sailRISCVzfzybinzytypezymnemoniczyS]{#2}}{}% + \ifstrequal{#1}{f_is_NaN_D}{\hyperref[sailRISCVzfzyiszyNaNzyD]{#2}}{}% + \ifstrequal{#1}{f_is_NaN_S}{\hyperref[sailRISCVzfzyiszyNaNzyS]{#2}}{}% + \ifstrequal{#1}{f_is_QNaN_D}{\hyperref[sailRISCVzfzyiszyQNaNzyD]{#2}}{}% + \ifstrequal{#1}{f_is_QNaN_S}{\hyperref[sailRISCVzfzyiszyQNaNzyS]{#2}}{}% + \ifstrequal{#1}{f_is_SNaN_D}{\hyperref[sailRISCVzfzyiszySNaNzyD]{#2}}{}% + \ifstrequal{#1}{f_is_SNaN_S}{\hyperref[sailRISCVzfzyiszySNaNzyS]{#2}}{}% + \ifstrequal{#1}{f_is_neg_inf_D}{\hyperref[sailRISCVzfzyiszynegzyinfzyD]{#2}}{}% + \ifstrequal{#1}{f_is_neg_inf_S}{\hyperref[sailRISCVzfzyiszynegzyinfzyS]{#2}}{}% + \ifstrequal{#1}{f_is_neg_norm_D}{\hyperref[sailRISCVzfzyiszynegzynormzyD]{#2}}{}% + \ifstrequal{#1}{f_is_neg_norm_S}{\hyperref[sailRISCVzfzyiszynegzynormzyS]{#2}}{}% + \ifstrequal{#1}{f_is_neg_subnorm_D}{\hyperref[sailRISCVzfzyiszynegzysubnormzyD]{#2}}{}% + \ifstrequal{#1}{f_is_neg_subnorm_S}{\hyperref[sailRISCVzfzyiszynegzysubnormzyS]{#2}}{}% + \ifstrequal{#1}{f_is_neg_zero_D}{\hyperref[sailRISCVzfzyiszynegzyzzerozyD]{#2}}{}% + \ifstrequal{#1}{f_is_neg_zero_S}{\hyperref[sailRISCVzfzyiszynegzyzzerozyS]{#2}}{}% + \ifstrequal{#1}{f_is_pos_inf_D}{\hyperref[sailRISCVzfzyiszyposzyinfzyD]{#2}}{}% + \ifstrequal{#1}{f_is_pos_inf_S}{\hyperref[sailRISCVzfzyiszyposzyinfzyS]{#2}}{}% + \ifstrequal{#1}{f_is_pos_norm_D}{\hyperref[sailRISCVzfzyiszyposzynormzyD]{#2}}{}% + \ifstrequal{#1}{f_is_pos_norm_S}{\hyperref[sailRISCVzfzyiszyposzynormzyS]{#2}}{}% + \ifstrequal{#1}{f_is_pos_subnorm_D}{\hyperref[sailRISCVzfzyiszyposzysubnormzyD]{#2}}{}% + \ifstrequal{#1}{f_is_pos_subnorm_S}{\hyperref[sailRISCVzfzyiszyposzysubnormzyS]{#2}}{}% + \ifstrequal{#1}{f_is_pos_zero_D}{\hyperref[sailRISCVzfzyiszyposzyzzerozyD]{#2}}{}% + \ifstrequal{#1}{f_is_pos_zero_S}{\hyperref[sailRISCVzfzyiszyposzyzzerozyS]{#2}}{}% + \ifstrequal{#1}{f_madd_op_D_of_num}{\hyperref[sailRISCVzfzymaddzyopzyDzyofzynum]{#2}}{}% + \ifstrequal{#1}{f_madd_op_S_of_num}{\hyperref[sailRISCVzfzymaddzyopzySzyofzynum]{#2}}{}% + \ifstrequal{#1}{f_madd_type_mnemonic_D}{\hyperref[sailRISCVzfzymaddzytypezymnemoniczyD]{#2}}{}% + \ifstrequal{#1}{f_madd_type_mnemonic_S}{\hyperref[sailRISCVzfzymaddzytypezymnemoniczyS]{#2}}{}% + \ifstrequal{#1}{f_un_op_D_of_num}{\hyperref[sailRISCVzfzyunzyopzyDzyofzynum]{#2}}{}% + \ifstrequal{#1}{f_un_op_S_of_num}{\hyperref[sailRISCVzfzyunzyopzySzyofzynum]{#2}}{}% + \ifstrequal{#1}{f_un_rm_op_D_of_num}{\hyperref[sailRISCVzfzyunzyrmzyopzyDzyofzynum]{#2}}{}% + \ifstrequal{#1}{f_un_rm_op_S_of_num}{\hyperref[sailRISCVzfzyunzyrmzyopzySzyofzynum]{#2}}{}% + \ifstrequal{#1}{f_un_rm_type_mnemonic_D}{\hyperref[sailRISCVzfzyunzyrmzytypezymnemoniczyD]{#2}}{}% + \ifstrequal{#1}{f_un_rm_type_mnemonic_S}{\hyperref[sailRISCVzfzyunzyrmzytypezymnemoniczyS]{#2}}{}% + \ifstrequal{#1}{f_un_type_mnemonic_D}{\hyperref[sailRISCVzfzyunzytypezymnemoniczyD]{#2}}{}% + \ifstrequal{#1}{f_un_type_mnemonic_S}{\hyperref[sailRISCVzfzyunzytypezymnemoniczyS]{#2}}{}% + \ifstrequal{#1}{fastRepCheck}{\hyperref[sailRISCVzfastRepCheck]{#2}}{}% + \ifstrequal{#1}{fdiv_int}{\hyperref[sailRISCVzfdivzyint]{#2}}{}% + \ifstrequal{#1}{fence_bits}{\hyperref[sailRISCVzfencezybits]{#2}}{}% + \ifstrequal{#1}{feq_quiet_D}{\hyperref[sailRISCVzfeqzyquietzyD]{#2}}{}% + \ifstrequal{#1}{feq_quiet_S}{\hyperref[sailRISCVzfeqzyquietzyS]{#2}}{}% + \ifstrequal{#1}{fetch}{\hyperref[sailRISCVzfetch]{#2}}{}% + \ifstrequal{#1}{findPendingInterrupt}{\hyperref[sailRISCVzfindPendingInterrupt]{#2}}{}% + \ifstrequal{#1}{fle_D}{\hyperref[sailRISCVzflezyD]{#2}}{}% + \ifstrequal{#1}{fle_S}{\hyperref[sailRISCVzflezyS]{#2}}{}% + \ifstrequal{#1}{flt_D}{\hyperref[sailRISCVzfltzyD]{#2}}{}% + \ifstrequal{#1}{flt_S}{\hyperref[sailRISCVzfltzyS]{#2}}{}% + \ifstrequal{#1}{flush_TLB}{\hyperref[sailRISCVzflushzyTLB]{#2}}{}% + \ifstrequal{#1}{flush_TLB39}{\hyperref[sailRISCVzflushzyTLB39]{#2}}{}% + \ifstrequal{#1}{flush_TLB48}{\hyperref[sailRISCVzflushzyTLB48]{#2}}{}% + \ifstrequal{#1}{flush_TLB_Entry}{\hyperref[sailRISCVzflushzyTLBzyEntry]{#2}}{}% + \ifstrequal{#1}{fmake_D}{\hyperref[sailRISCVzfmakezyD]{#2}}{}% + \ifstrequal{#1}{fmake_S}{\hyperref[sailRISCVzfmakezyS]{#2}}{}% + \ifstrequal{#1}{fmod_int}{\hyperref[sailRISCVzfmodzyint]{#2}}{}% + \ifstrequal{#1}{freg_name}{\hyperref[sailRISCVzfregzyname]{#2}}{}% + \ifstrequal{#1}{freg_name_abi}{\hyperref[sailRISCVzfregzynamezyabi]{#2}}{}% + \ifstrequal{#1}{fregval_from_freg}{\hyperref[sailRISCVzfregvalzyfromzyfreg]{#2}}{}% + \ifstrequal{#1}{fregval_into_freg}{\hyperref[sailRISCVzfregvalzyintozyfreg]{#2}}{}% + \ifstrequal{#1}{frm_mnemonic}{\hyperref[sailRISCVzfrmzymnemonic]{#2}}{}% + \ifstrequal{#1}{fsplit_D}{\hyperref[sailRISCVzfsplitzyD]{#2}}{}% + \ifstrequal{#1}{fsplit_S}{\hyperref[sailRISCVzfsplitzyS]{#2}}{}% + \ifstrequal{#1}{getCapBase}{\hyperref[sailRISCVzgetCapBase]{#2}}{}% + \ifstrequal{#1}{getCapBaseBits}{\hyperref[sailRISCVzgetCapBaseBits]{#2}}{}% + \ifstrequal{#1}{getCapBounds}{\hyperref[sailRISCVzgetCapBounds]{#2}}{}% + \ifstrequal{#1}{getCapBoundsBits}{\hyperref[sailRISCVzgetCapBoundsBits]{#2}}{}% + \ifstrequal{#1}{getCapCursor}{\hyperref[sailRISCVzgetCapCursor]{#2}}{}% + \ifstrequal{#1}{getCapFlags}{\hyperref[sailRISCVzgetCapFlags]{#2}}{}% + \ifstrequal{#1}{getCapHardPerms}{\hyperref[sailRISCVzgetCapHardPerms]{#2}}{}% + \ifstrequal{#1}{getCapLength}{\hyperref[sailRISCVzgetCapLength]{#2}}{}% + \ifstrequal{#1}{getCapOffset}{\hyperref[sailRISCVzgetCapOffset]{#2}}{}% + \ifstrequal{#1}{getCapOffsetBits}{\hyperref[sailRISCVzgetCapOffsetBits]{#2}}{}% + \ifstrequal{#1}{getCapPerms}{\hyperref[sailRISCVzgetCapPerms]{#2}}{}% + \ifstrequal{#1}{getCapTop}{\hyperref[sailRISCVzgetCapTop]{#2}}{}% + \ifstrequal{#1}{getCapTopBits}{\hyperref[sailRISCVzgetCapTopBits]{#2}}{}% + \ifstrequal{#1}{getPendingSet}{\hyperref[sailRISCVzgetPendingSet]{#2}}{}% + \ifstrequal{#1}{getRepresentableAlignmentMask}{\hyperref[sailRISCVzgetRepresentableAlignmentMask]{#2}}{}% + \ifstrequal{#1}{getRepresentableLength}{\hyperref[sailRISCVzgetRepresentableLength]{#2}}{}% + \ifstrequal{#1}{get_arch_pc}{\hyperref[sailRISCVzgetzyarchzypc]{#2}}{}% + \ifstrequal{#1}{get_cheri_mode_cap_addr}{\hyperref[sailRISCVzgetzycherizymodezycapzyaddr]{#2}}{}% + \ifstrequal{#1}{get_config_print_instr}{\hyperref[sailRISCVzgetzyconfigzyprintzyinstr]{#2}}{}% + \ifstrequal{#1}{get_config_print_mem}{\hyperref[sailRISCVzgetzyconfigzyprintzymem]{#2}}{}% + \ifstrequal{#1}{get_config_print_platform}{\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{#2}}{}% + \ifstrequal{#1}{get_config_print_reg}{\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{#2}}{}% + \ifstrequal{#1}{get_mstatus_SXL}{\hyperref[sailRISCVzgetzymstatuszySXL]{#2}}{}% + \ifstrequal{#1}{get_mstatus_UXL}{\hyperref[sailRISCVzgetzymstatuszyUXL]{#2}}{}% + \ifstrequal{#1}{get_mtvec}{\hyperref[sailRISCVzgetzymtvec]{#2}}{}% + \ifstrequal{#1}{get_next_pc}{\hyperref[sailRISCVzgetzynextzypc]{#2}}{}% + \ifstrequal{#1}{get_slice_int}{\hyperref[sailRISCVzgetzyslicezyint]{#2}}{}% + \ifstrequal{#1}{get_sstatus_UXL}{\hyperref[sailRISCVzgetzysstatuszyUXL]{#2}}{}% + \ifstrequal{#1}{get_stvec}{\hyperref[sailRISCVzgetzystvec]{#2}}{}% + \ifstrequal{#1}{get_utvec}{\hyperref[sailRISCVzgetzyutvec]{#2}}{}% + \ifstrequal{#1}{get_xret_target}{\hyperref[sailRISCVzgetzyxretzytarget]{#2}}{}% + \ifstrequal{#1}{gt_int}{\hyperref[sailRISCVzgtzyint]{#2}}{}% + \ifstrequal{#1}{gteq_int}{\hyperref[sailRISCVzgteqzyint]{#2}}{}% + \ifstrequal{#1}{handle_cheri_cap_exception}{\hyperref[sailRISCVzhandlezycherizycapzyexception]{#2}}{}% + \ifstrequal{#1}{handle_cheri_pcc_exception}{\hyperref[sailRISCVzhandlezycherizypcczyexception]{#2}}{}% + \ifstrequal{#1}{handle_cheri_reg_exception}{\hyperref[sailRISCVzhandlezycherizyregzyexception]{#2}}{}% + \ifstrequal{#1}{handle_exception}{\hyperref[sailRISCVzhandlezyexception]{#2}}{}% + \ifstrequal{#1}{handle_illegal}{\hyperref[sailRISCVzhandlezyillegal]{#2}}{}% + \ifstrequal{#1}{handle_interrupt}{\hyperref[sailRISCVzhandlezyinterrupt]{#2}}{}% + \ifstrequal{#1}{handle_load_cap_via_cap}{\hyperref[sailRISCVzhandlezyloadzycapzyviazycap]{#2}}{}% + \ifstrequal{#1}{handle_load_data_via_cap}{\hyperref[sailRISCVzhandlezyloadzydatazyviazycap]{#2}}{}% + \ifstrequal{#1}{handle_loadres_cap_via_cap}{\hyperref[sailRISCVzhandlezyloadreszycapzyviazycap]{#2}}{}% + \ifstrequal{#1}{handle_loadres_data_via_cap}{\hyperref[sailRISCVzhandlezyloadreszydatazyviazycap]{#2}}{}% + \ifstrequal{#1}{handle_mem_exception}{\hyperref[sailRISCVzhandlezymemzyexception]{#2}}{}% + \ifstrequal{#1}{handle_store_cap_via_cap}{\hyperref[sailRISCVzhandlezystorezycapzyviazycap]{#2}}{}% + \ifstrequal{#1}{handle_store_cond_cap_via_cap}{\hyperref[sailRISCVzhandlezystorezycondzycapzyviazycap]{#2}}{}% + \ifstrequal{#1}{handle_store_cond_data_via_cap}{\hyperref[sailRISCVzhandlezystorezycondzydatazyviazycap]{#2}}{}% + \ifstrequal{#1}{handle_store_data_via_cap}{\hyperref[sailRISCVzhandlezystorezydatazyviazycap]{#2}}{}% + \ifstrequal{#1}{handle_trap_extension}{\hyperref[sailRISCVzhandlezytrapzyextension]{#2}}{}% + \ifstrequal{#1}{hasReservedOType}{\hyperref[sailRISCVzhasReservedOType]{#2}}{}% + \ifstrequal{#1}{haveAtomics}{\hyperref[sailRISCVzhaveAtomics]{#2}}{}% + \ifstrequal{#1}{haveDExt}{\hyperref[sailRISCVzhaveDExt]{#2}}{}% + \ifstrequal{#1}{haveFExt}{\hyperref[sailRISCVzhaveFExt]{#2}}{}% + \ifstrequal{#1}{haveMulDiv}{\hyperref[sailRISCVzhaveMulDiv]{#2}}{}% + \ifstrequal{#1}{haveNExt}{\hyperref[sailRISCVzhaveNExt]{#2}}{}% + \ifstrequal{#1}{haveRVC}{\hyperref[sailRISCVzhaveRVC]{#2}}{}% + \ifstrequal{#1}{haveSupMode}{\hyperref[sailRISCVzhaveSupMode]{#2}}{}% + \ifstrequal{#1}{haveUsrMode}{\hyperref[sailRISCVzhaveUsrMode]{#2}}{}% + \ifstrequal{#1}{haveXcheri}{\hyperref[sailRISCVzhaveXcheri]{#2}}{}% + \ifstrequal{#1}{hex_bits}{\hyperref[sailRISCVzhexzybits]{#2}}{}% + \ifstrequal{#1}{hex_bits_1}{\hyperref[sailRISCVzhexzybitszy1]{#2}}{}% + \ifstrequal{#1}{hex_bits_10}{\hyperref[sailRISCVzhexzybitszy10]{#2}}{}% + \ifstrequal{#1}{hex_bits_10_backwards}{\hyperref[sailRISCVzhexzybitszy10zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_10_backwards_matches}{\hyperref[sailRISCVzhexzybitszy10zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_10_forwards}{\hyperref[sailRISCVzhexzybitszy10zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_10_forwards_matches}{\hyperref[sailRISCVzhexzybitszy10zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_10_matches_prefix}{\hyperref[sailRISCVzhexzybitszy10zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_11}{\hyperref[sailRISCVzhexzybitszy11]{#2}}{}% + \ifstrequal{#1}{hex_bits_11_backwards}{\hyperref[sailRISCVzhexzybitszy11zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_11_backwards_matches}{\hyperref[sailRISCVzhexzybitszy11zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_11_forwards}{\hyperref[sailRISCVzhexzybitszy11zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_11_forwards_matches}{\hyperref[sailRISCVzhexzybitszy11zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_11_matches_prefix}{\hyperref[sailRISCVzhexzybitszy11zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_12}{\hyperref[sailRISCVzhexzybitszy12]{#2}}{}% + \ifstrequal{#1}{hex_bits_12_backwards}{\hyperref[sailRISCVzhexzybitszy12zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_12_backwards_matches}{\hyperref[sailRISCVzhexzybitszy12zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_12_forwards}{\hyperref[sailRISCVzhexzybitszy12zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_12_forwards_matches}{\hyperref[sailRISCVzhexzybitszy12zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_13}{\hyperref[sailRISCVzhexzybitszy13]{#2}}{}% + \ifstrequal{#1}{hex_bits_13_backwards}{\hyperref[sailRISCVzhexzybitszy13zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_13_backwards_matches}{\hyperref[sailRISCVzhexzybitszy13zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_13_forwards}{\hyperref[sailRISCVzhexzybitszy13zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_13_forwards_matches}{\hyperref[sailRISCVzhexzybitszy13zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_13_matches_prefix}{\hyperref[sailRISCVzhexzybitszy13zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_14}{\hyperref[sailRISCVzhexzybitszy14]{#2}}{}% + \ifstrequal{#1}{hex_bits_14_backwards}{\hyperref[sailRISCVzhexzybitszy14zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_14_backwards_matches}{\hyperref[sailRISCVzhexzybitszy14zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_14_forwards}{\hyperref[sailRISCVzhexzybitszy14zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_14_forwards_matches}{\hyperref[sailRISCVzhexzybitszy14zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_14_matches_prefix}{\hyperref[sailRISCVzhexzybitszy14zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_15}{\hyperref[sailRISCVzhexzybitszy15]{#2}}{}% + \ifstrequal{#1}{hex_bits_15_backwards}{\hyperref[sailRISCVzhexzybitszy15zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_15_backwards_matches}{\hyperref[sailRISCVzhexzybitszy15zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_15_forwards}{\hyperref[sailRISCVzhexzybitszy15zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_15_forwards_matches}{\hyperref[sailRISCVzhexzybitszy15zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_15_matches_prefix}{\hyperref[sailRISCVzhexzybitszy15zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_16}{\hyperref[sailRISCVzhexzybitszy16]{#2}}{}% + \ifstrequal{#1}{hex_bits_16_backwards}{\hyperref[sailRISCVzhexzybitszy16zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_16_backwards_matches}{\hyperref[sailRISCVzhexzybitszy16zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_16_forwards}{\hyperref[sailRISCVzhexzybitszy16zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_16_forwards_matches}{\hyperref[sailRISCVzhexzybitszy16zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_16_matches_prefix}{\hyperref[sailRISCVzhexzybitszy16zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_17}{\hyperref[sailRISCVzhexzybitszy17]{#2}}{}% + \ifstrequal{#1}{hex_bits_17_backwards}{\hyperref[sailRISCVzhexzybitszy17zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_17_backwards_matches}{\hyperref[sailRISCVzhexzybitszy17zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_17_forwards}{\hyperref[sailRISCVzhexzybitszy17zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_17_forwards_matches}{\hyperref[sailRISCVzhexzybitszy17zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_17_matches_prefix}{\hyperref[sailRISCVzhexzybitszy17zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_18}{\hyperref[sailRISCVzhexzybitszy18]{#2}}{}% + \ifstrequal{#1}{hex_bits_18_backwards}{\hyperref[sailRISCVzhexzybitszy18zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_18_backwards_matches}{\hyperref[sailRISCVzhexzybitszy18zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_18_forwards}{\hyperref[sailRISCVzhexzybitszy18zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_18_forwards_matches}{\hyperref[sailRISCVzhexzybitszy18zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_18_matches_prefix}{\hyperref[sailRISCVzhexzybitszy18zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_19}{\hyperref[sailRISCVzhexzybitszy19]{#2}}{}% + \ifstrequal{#1}{hex_bits_19_backwards}{\hyperref[sailRISCVzhexzybitszy19zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_19_backwards_matches}{\hyperref[sailRISCVzhexzybitszy19zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_19_forwards}{\hyperref[sailRISCVzhexzybitszy19zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_19_forwards_matches}{\hyperref[sailRISCVzhexzybitszy19zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_19_matches_prefix}{\hyperref[sailRISCVzhexzybitszy19zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_1_backwards}{\hyperref[sailRISCVzhexzybitszy1zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_1_backwards_matches}{\hyperref[sailRISCVzhexzybitszy1zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_1_forwards}{\hyperref[sailRISCVzhexzybitszy1zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_1_forwards_matches}{\hyperref[sailRISCVzhexzybitszy1zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_1_matches_prefix}{\hyperref[sailRISCVzhexzybitszy1zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_2}{\hyperref[sailRISCVzhexzybitszy2]{#2}}{}% + \ifstrequal{#1}{hex_bits_20}{\hyperref[sailRISCVzhexzybitszy20]{#2}}{}% + \ifstrequal{#1}{hex_bits_20_backwards}{\hyperref[sailRISCVzhexzybitszy20zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_20_backwards_matches}{\hyperref[sailRISCVzhexzybitszy20zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_20_forwards}{\hyperref[sailRISCVzhexzybitszy20zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_20_forwards_matches}{\hyperref[sailRISCVzhexzybitszy20zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_20_matches_prefix}{\hyperref[sailRISCVzhexzybitszy20zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_21}{\hyperref[sailRISCVzhexzybitszy21]{#2}}{}% + \ifstrequal{#1}{hex_bits_21_backwards}{\hyperref[sailRISCVzhexzybitszy21zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_21_backwards_matches}{\hyperref[sailRISCVzhexzybitszy21zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_21_forwards}{\hyperref[sailRISCVzhexzybitszy21zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_21_forwards_matches}{\hyperref[sailRISCVzhexzybitszy21zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_21_matches_prefix}{\hyperref[sailRISCVzhexzybitszy21zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_22}{\hyperref[sailRISCVzhexzybitszy22]{#2}}{}% + \ifstrequal{#1}{hex_bits_22_backwards}{\hyperref[sailRISCVzhexzybitszy22zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_22_backwards_matches}{\hyperref[sailRISCVzhexzybitszy22zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_22_forwards}{\hyperref[sailRISCVzhexzybitszy22zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_22_forwards_matches}{\hyperref[sailRISCVzhexzybitszy22zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_22_matches_prefix}{\hyperref[sailRISCVzhexzybitszy22zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_23}{\hyperref[sailRISCVzhexzybitszy23]{#2}}{}% + \ifstrequal{#1}{hex_bits_23_backwards}{\hyperref[sailRISCVzhexzybitszy23zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_23_backwards_matches}{\hyperref[sailRISCVzhexzybitszy23zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_23_forwards}{\hyperref[sailRISCVzhexzybitszy23zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_23_forwards_matches}{\hyperref[sailRISCVzhexzybitszy23zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_23_matches_prefix}{\hyperref[sailRISCVzhexzybitszy23zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_24}{\hyperref[sailRISCVzhexzybitszy24]{#2}}{}% + \ifstrequal{#1}{hex_bits_24_backwards}{\hyperref[sailRISCVzhexzybitszy24zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_24_backwards_matches}{\hyperref[sailRISCVzhexzybitszy24zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_24_forwards}{\hyperref[sailRISCVzhexzybitszy24zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_24_forwards_matches}{\hyperref[sailRISCVzhexzybitszy24zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_24_matches_prefix}{\hyperref[sailRISCVzhexzybitszy24zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_25}{\hyperref[sailRISCVzhexzybitszy25]{#2}}{}% + \ifstrequal{#1}{hex_bits_25_backwards}{\hyperref[sailRISCVzhexzybitszy25zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_25_backwards_matches}{\hyperref[sailRISCVzhexzybitszy25zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_25_forwards}{\hyperref[sailRISCVzhexzybitszy25zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_25_forwards_matches}{\hyperref[sailRISCVzhexzybitszy25zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_25_matches_prefix}{\hyperref[sailRISCVzhexzybitszy25zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_26}{\hyperref[sailRISCVzhexzybitszy26]{#2}}{}% + \ifstrequal{#1}{hex_bits_26_backwards}{\hyperref[sailRISCVzhexzybitszy26zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_26_backwards_matches}{\hyperref[sailRISCVzhexzybitszy26zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_26_forwards}{\hyperref[sailRISCVzhexzybitszy26zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_26_forwards_matches}{\hyperref[sailRISCVzhexzybitszy26zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_26_matches_prefix}{\hyperref[sailRISCVzhexzybitszy26zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_27}{\hyperref[sailRISCVzhexzybitszy27]{#2}}{}% + \ifstrequal{#1}{hex_bits_27_backwards}{\hyperref[sailRISCVzhexzybitszy27zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_27_backwards_matches}{\hyperref[sailRISCVzhexzybitszy27zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_27_forwards}{\hyperref[sailRISCVzhexzybitszy27zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_27_forwards_matches}{\hyperref[sailRISCVzhexzybitszy27zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_27_matches_prefix}{\hyperref[sailRISCVzhexzybitszy27zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_28}{\hyperref[sailRISCVzhexzybitszy28]{#2}}{}% + \ifstrequal{#1}{hex_bits_28_backwards}{\hyperref[sailRISCVzhexzybitszy28zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_28_backwards_matches}{\hyperref[sailRISCVzhexzybitszy28zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_28_forwards}{\hyperref[sailRISCVzhexzybitszy28zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_28_forwards_matches}{\hyperref[sailRISCVzhexzybitszy28zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_28_matches_prefix}{\hyperref[sailRISCVzhexzybitszy28zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_29}{\hyperref[sailRISCVzhexzybitszy29]{#2}}{}% + \ifstrequal{#1}{hex_bits_29_backwards}{\hyperref[sailRISCVzhexzybitszy29zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_29_backwards_matches}{\hyperref[sailRISCVzhexzybitszy29zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_29_forwards}{\hyperref[sailRISCVzhexzybitszy29zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_29_forwards_matches}{\hyperref[sailRISCVzhexzybitszy29zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_29_matches_prefix}{\hyperref[sailRISCVzhexzybitszy29zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_2_backwards}{\hyperref[sailRISCVzhexzybitszy2zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_2_backwards_matches}{\hyperref[sailRISCVzhexzybitszy2zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_2_forwards}{\hyperref[sailRISCVzhexzybitszy2zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_2_forwards_matches}{\hyperref[sailRISCVzhexzybitszy2zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_2_matches_prefix}{\hyperref[sailRISCVzhexzybitszy2zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_3}{\hyperref[sailRISCVzhexzybitszy3]{#2}}{}% + \ifstrequal{#1}{hex_bits_30}{\hyperref[sailRISCVzhexzybitszy30]{#2}}{}% + \ifstrequal{#1}{hex_bits_30_backwards}{\hyperref[sailRISCVzhexzybitszy30zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_30_backwards_matches}{\hyperref[sailRISCVzhexzybitszy30zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_30_forwards}{\hyperref[sailRISCVzhexzybitszy30zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_30_forwards_matches}{\hyperref[sailRISCVzhexzybitszy30zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_30_matches_prefix}{\hyperref[sailRISCVzhexzybitszy30zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_31}{\hyperref[sailRISCVzhexzybitszy31]{#2}}{}% + \ifstrequal{#1}{hex_bits_31_backwards}{\hyperref[sailRISCVzhexzybitszy31zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_31_backwards_matches}{\hyperref[sailRISCVzhexzybitszy31zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_31_forwards}{\hyperref[sailRISCVzhexzybitszy31zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_31_forwards_matches}{\hyperref[sailRISCVzhexzybitszy31zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_31_matches_prefix}{\hyperref[sailRISCVzhexzybitszy31zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_32}{\hyperref[sailRISCVzhexzybitszy32]{#2}}{}% + \ifstrequal{#1}{hex_bits_32_backwards}{\hyperref[sailRISCVzhexzybitszy32zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_32_backwards_matches}{\hyperref[sailRISCVzhexzybitszy32zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_32_forwards}{\hyperref[sailRISCVzhexzybitszy32zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_32_forwards_matches}{\hyperref[sailRISCVzhexzybitszy32zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_32_matches_prefix}{\hyperref[sailRISCVzhexzybitszy32zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_33}{\hyperref[sailRISCVzhexzybitszy33]{#2}}{}% + \ifstrequal{#1}{hex_bits_33_backwards}{\hyperref[sailRISCVzhexzybitszy33zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_33_backwards_matches}{\hyperref[sailRISCVzhexzybitszy33zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_33_forwards}{\hyperref[sailRISCVzhexzybitszy33zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_33_forwards_matches}{\hyperref[sailRISCVzhexzybitszy33zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_33_matches_prefix}{\hyperref[sailRISCVzhexzybitszy33zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_3_backwards}{\hyperref[sailRISCVzhexzybitszy3zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_3_backwards_matches}{\hyperref[sailRISCVzhexzybitszy3zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_3_forwards}{\hyperref[sailRISCVzhexzybitszy3zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_3_forwards_matches}{\hyperref[sailRISCVzhexzybitszy3zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_3_matches_prefix}{\hyperref[sailRISCVzhexzybitszy3zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_4}{\hyperref[sailRISCVzhexzybitszy4]{#2}}{}% + \ifstrequal{#1}{hex_bits_48}{\hyperref[sailRISCVzhexzybitszy48]{#2}}{}% + \ifstrequal{#1}{hex_bits_48_backwards}{\hyperref[sailRISCVzhexzybitszy48zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_48_backwards_matches}{\hyperref[sailRISCVzhexzybitszy48zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_48_forwards}{\hyperref[sailRISCVzhexzybitszy48zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_48_forwards_matches}{\hyperref[sailRISCVzhexzybitszy48zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_48_matches_prefix}{\hyperref[sailRISCVzhexzybitszy48zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_4_backwards}{\hyperref[sailRISCVzhexzybitszy4zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_4_backwards_matches}{\hyperref[sailRISCVzhexzybitszy4zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_4_forwards}{\hyperref[sailRISCVzhexzybitszy4zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_4_forwards_matches}{\hyperref[sailRISCVzhexzybitszy4zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_4_matches_prefix}{\hyperref[sailRISCVzhexzybitszy4zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_5}{\hyperref[sailRISCVzhexzybitszy5]{#2}}{}% + \ifstrequal{#1}{hex_bits_5_backwards}{\hyperref[sailRISCVzhexzybitszy5zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_5_backwards_matches}{\hyperref[sailRISCVzhexzybitszy5zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_5_forwards}{\hyperref[sailRISCVzhexzybitszy5zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_5_forwards_matches}{\hyperref[sailRISCVzhexzybitszy5zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_5_matches_prefix}{\hyperref[sailRISCVzhexzybitszy5zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_6}{\hyperref[sailRISCVzhexzybitszy6]{#2}}{}% + \ifstrequal{#1}{hex_bits_64}{\hyperref[sailRISCVzhexzybitszy64]{#2}}{}% + \ifstrequal{#1}{hex_bits_64_backwards}{\hyperref[sailRISCVzhexzybitszy64zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_64_backwards_matches}{\hyperref[sailRISCVzhexzybitszy64zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_64_forwards}{\hyperref[sailRISCVzhexzybitszy64zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_64_forwards_matches}{\hyperref[sailRISCVzhexzybitszy64zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_64_matches_prefix}{\hyperref[sailRISCVzhexzybitszy64zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_6_backwards}{\hyperref[sailRISCVzhexzybitszy6zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_6_backwards_matches}{\hyperref[sailRISCVzhexzybitszy6zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_6_forwards}{\hyperref[sailRISCVzhexzybitszy6zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_6_forwards_matches}{\hyperref[sailRISCVzhexzybitszy6zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_6_matches_prefix}{\hyperref[sailRISCVzhexzybitszy6zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_7}{\hyperref[sailRISCVzhexzybitszy7]{#2}}{}% + \ifstrequal{#1}{hex_bits_7_backwards}{\hyperref[sailRISCVzhexzybitszy7zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_7_backwards_matches}{\hyperref[sailRISCVzhexzybitszy7zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_7_forwards}{\hyperref[sailRISCVzhexzybitszy7zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_7_forwards_matches}{\hyperref[sailRISCVzhexzybitszy7zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_7_matches_prefix}{\hyperref[sailRISCVzhexzybitszy7zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_8}{\hyperref[sailRISCVzhexzybitszy8]{#2}}{}% + \ifstrequal{#1}{hex_bits_8_backwards}{\hyperref[sailRISCVzhexzybitszy8zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_8_backwards_matches}{\hyperref[sailRISCVzhexzybitszy8zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_8_forwards}{\hyperref[sailRISCVzhexzybitszy8zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_8_forwards_matches}{\hyperref[sailRISCVzhexzybitszy8zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_8_matches_prefix}{\hyperref[sailRISCVzhexzybitszy8zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_bits_9}{\hyperref[sailRISCVzhexzybitszy9]{#2}}{}% + \ifstrequal{#1}{hex_bits_9_backwards}{\hyperref[sailRISCVzhexzybitszy9zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_9_backwards_matches}{\hyperref[sailRISCVzhexzybitszy9zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_9_forwards}{\hyperref[sailRISCVzhexzybitszy9zyforwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_9_forwards_matches}{\hyperref[sailRISCVzhexzybitszy9zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_9_matches_prefix}{\hyperref[sailRISCVzhexzybitszy9zymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{hex_str}{\hyperref[sailRISCVzhexzystr]{#2}}{}% + \ifstrequal{#1}{htif_load}{\hyperref[sailRISCVzhtifzyload]{#2}}{}% + \ifstrequal{#1}{htif_store}{\hyperref[sailRISCVzhtifzystore]{#2}}{}% + \ifstrequal{#1}{htif_tick}{\hyperref[sailRISCVzhtifzytick]{#2}}{}% + \ifstrequal{#1}{in32BitMode}{\hyperref[sailRISCVzin32BitMode]{#2}}{}% + \ifstrequal{#1}{inCapBounds}{\hyperref[sailRISCVzinCapBounds]{#2}}{}% + \ifstrequal{#1}{incCapOffset}{\hyperref[sailRISCVzincCapOffset]{#2}}{}% + \ifstrequal{#1}{init_base_regs}{\hyperref[sailRISCVzinitzybasezyregs]{#2}}{}% + \ifstrequal{#1}{init_fdext_regs}{\hyperref[sailRISCVzinitzyfdextzyregs]{#2}}{}% + \ifstrequal{#1}{init_model}{\hyperref[sailRISCVzinitzymodel]{#2}}{}% + \ifstrequal{#1}{init_platform}{\hyperref[sailRISCVzinitzyplatform]{#2}}{}% + \ifstrequal{#1}{init_pmp}{\hyperref[sailRISCVzinitzypmp]{#2}}{}% + \ifstrequal{#1}{init_sys}{\hyperref[sailRISCVzinitzysys]{#2}}{}% + \ifstrequal{#1}{init_vmem}{\hyperref[sailRISCVzinitzyvmem]{#2}}{}% + \ifstrequal{#1}{init_vmem_sv39}{\hyperref[sailRISCVzinitzyvmemzysv39]{#2}}{}% + \ifstrequal{#1}{init_vmem_sv48}{\hyperref[sailRISCVzinitzyvmemzysv48]{#2}}{}% + \ifstrequal{#1}{initial_analysis}{\hyperref[sailRISCVzinitialzyanalysis]{#2}}{}% + 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\ifstrequal{#1}{print}{\hyperref[sailRISCVzprint]{#2}}{}% + \ifstrequal{#1}{print_bits}{\hyperref[sailRISCVzprintzybits]{#2}}{}% + \ifstrequal{#1}{print_endline}{\hyperref[sailRISCVzprintzyendline]{#2}}{}% + \ifstrequal{#1}{print_insn}{\hyperref[sailRISCVzprintzyinsn]{#2}}{}% + \ifstrequal{#1}{print_instr}{\hyperref[sailRISCVzprintzyinstr]{#2}}{}% + \ifstrequal{#1}{print_int}{\hyperref[sailRISCVzprintzyint]{#2}}{}% + \ifstrequal{#1}{print_mem}{\hyperref[sailRISCVzprintzymem]{#2}}{}% + \ifstrequal{#1}{print_platform}{\hyperref[sailRISCVzprintzyplatform]{#2}}{}% + \ifstrequal{#1}{print_reg}{\hyperref[sailRISCVzprintzyreg]{#2}}{}% + \ifstrequal{#1}{print_string}{\hyperref[sailRISCVzprintzystring]{#2}}{}% + \ifstrequal{#1}{privLevel_of_bits}{\hyperref[sailRISCVzprivLevelzyofzybits]{#2}}{}% + \ifstrequal{#1}{privLevel_to_bits}{\hyperref[sailRISCVzprivLevelzytozybits]{#2}}{}% + \ifstrequal{#1}{privLevel_to_str}{\hyperref[sailRISCVzprivLevelzytozystr]{#2}}{}% + \ifstrequal{#1}{processPending}{\hyperref[sailRISCVzprocessPending]{#2}}{}% + \ifstrequal{#1}{process_fload32}{\hyperref[sailRISCVzprocesszyfload32]{#2}}{}% + \ifstrequal{#1}{process_fload64}{\hyperref[sailRISCVzprocesszyfload64]{#2}}{}% + \ifstrequal{#1}{process_fstore}{\hyperref[sailRISCVzprocesszyfstore]{#2}}{}% + \ifstrequal{#1}{process_load}{\hyperref[sailRISCVzprocesszyload]{#2}}{}% + \ifstrequal{#1}{process_loadres}{\hyperref[sailRISCVzprocesszyloadres]{#2}}{}% + \ifstrequal{#1}{ptw_error_to_str}{\hyperref[sailRISCVzptwzyerrorzytozystr]{#2}}{}% + \ifstrequal{#1}{quot_round_zero}{\hyperref[sailRISCVzquotzyroundzyzzero]{#2}}{}% + \ifstrequal{#1}{rC}{\hyperref[sailRISCVzrC]{#2}}{}% + \ifstrequal{#1}{rC_bits}{\hyperref[sailRISCVzrCzybits]{#2}}{}% + \ifstrequal{#1}{rF}{\hyperref[sailRISCVzrF]{#2}}{}% + \ifstrequal{#1}{rF_bits}{\hyperref[sailRISCVzrFzybits]{#2}}{}% + \ifstrequal{#1}{rX}{\hyperref[sailRISCVzrX]{#2}}{}% + \ifstrequal{#1}{rX_bits}{\hyperref[sailRISCVzrXzybits]{#2}}{}% + \ifstrequal{#1}{readCSR}{\hyperref[sailRISCVzreadCSR]{#2}}{}% + \ifstrequal{#1}{read_kind_of_flags}{\hyperref[sailRISCVzreadzykindzyofzyflags]{#2}}{}% + \ifstrequal{#1}{read_kind_of_num}{\hyperref[sailRISCVzreadzykindzyofzynum]{#2}}{}% + \ifstrequal{#1}{read_ram}{\hyperref[sailRISCVzreadzyram]{#2}}{}% + \ifstrequal{#1}{reg_deref}{\hyperref[sailRISCVzregzyderef]{#2}}{}% + \ifstrequal{#1}{reg_name}{\hyperref[sailRISCVzregzyname]{#2}}{}% + \ifstrequal{#1}{reg_name_abi}{\hyperref[sailRISCVzregzynamezyabi]{#2}}{}% + \ifstrequal{#1}{regidx_to_regno}{\hyperref[sailRISCVzregidxzytozyregno]{#2}}{}% + \ifstrequal{#1}{regval_from_reg}{\hyperref[sailRISCVzregvalzyfromzyreg]{#2}}{}% + \ifstrequal{#1}{regval_into_reg}{\hyperref[sailRISCVzregvalzyintozyreg]{#2}}{}% + \ifstrequal{#1}{rem_round_zero}{\hyperref[sailRISCVzremzyroundzyzzero]{#2}}{}% + \ifstrequal{#1}{replicate_bits}{\hyperref[sailRISCVzreplicatezybits]{#2}}{}% + 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\ifstrequal{#1}{riscv_f64ToI64}{\hyperref[sailRISCVzriscvzyf64ToI64]{#2}}{}% + \ifstrequal{#1}{riscv_f64ToUi32}{\hyperref[sailRISCVzriscvzyf64ToUi32]{#2}}{}% + \ifstrequal{#1}{riscv_f64ToUi64}{\hyperref[sailRISCVzriscvzyf64ToUi64]{#2}}{}% + \ifstrequal{#1}{riscv_i32ToF32}{\hyperref[sailRISCVzriscvzyi32ToF32]{#2}}{}% + \ifstrequal{#1}{riscv_i32ToF64}{\hyperref[sailRISCVzriscvzyi32ToF64]{#2}}{}% + \ifstrequal{#1}{riscv_i64ToF32}{\hyperref[sailRISCVzriscvzyi64ToF32]{#2}}{}% + \ifstrequal{#1}{riscv_i64ToF64}{\hyperref[sailRISCVzriscvzyi64ToF64]{#2}}{}% + \ifstrequal{#1}{riscv_ui32ToF32}{\hyperref[sailRISCVzriscvzyui32ToF32]{#2}}{}% + \ifstrequal{#1}{riscv_ui32ToF64}{\hyperref[sailRISCVzriscvzyui32ToF64]{#2}}{}% + \ifstrequal{#1}{riscv_ui64ToF32}{\hyperref[sailRISCVzriscvzyui64ToF32]{#2}}{}% + \ifstrequal{#1}{riscv_ui64ToF64}{\hyperref[sailRISCVzriscvzyui64ToF64]{#2}}{}% + \ifstrequal{#1}{rop_of_num}{\hyperref[sailRISCVzropzyofzynum]{#2}}{}% + \ifstrequal{#1}{ropw_of_num}{\hyperref[sailRISCVzropwzyofzynum]{#2}}{}% + \ifstrequal{#1}{rounding_mode_of_num}{\hyperref[sailRISCVzroundingzymodezyofzynum]{#2}}{}% + \ifstrequal{#1}{rtype_mnemonic}{\hyperref[sailRISCVzrtypezymnemonic]{#2}}{}% + \ifstrequal{#1}{rtypew_mnemonic}{\hyperref[sailRISCVzrtypewzymnemonic]{#2}}{}% + \ifstrequal{#1}{rvfi_read}{\hyperref[sailRISCVzrvfizyread]{#2}}{}% + \ifstrequal{#1}{rvfi_trap}{\hyperref[sailRISCVzrvfizytrap]{#2}}{}% + \ifstrequal{#1}{rvfi_wX}{\hyperref[sailRISCVzrvfizywX]{#2}}{}% + \ifstrequal{#1}{rvfi_write}{\hyperref[sailRISCVzrvfizywrite]{#2}}{}% + \ifstrequal{#1}{sail_arith_shiftright}{\hyperref[sailRISCVzsailzyarithzyshiftright]{#2}}{}% + \ifstrequal{#1}{sail_mask}{\hyperref[sailRISCVzsailzymask]{#2}}{}% + \ifstrequal{#1}{sail_ones}{\hyperref[sailRISCVzsailzyones]{#2}}{}% + \ifstrequal{#1}{sail_shiftleft}{\hyperref[sailRISCVzsailzyshiftleft]{#2}}{}% + \ifstrequal{#1}{sail_shiftright}{\hyperref[sailRISCVzsailzyshiftright]{#2}}{}% + \ifstrequal{#1}{sail_sign_extend}{\hyperref[sailRISCVzsailzysignzyextend]{#2}}{}% + \ifstrequal{#1}{sail_zero_extend}{\hyperref[sailRISCVzsailzyzzerozyextend]{#2}}{}% + \ifstrequal{#1}{sail_zeros}{\hyperref[sailRISCVzsailzyzzeros]{#2}}{}% + \ifstrequal{#1}{satp64Mode_of_bits}{\hyperref[sailRISCVzsatp64Modezyofzybits]{#2}}{}% + \ifstrequal{#1}{scr_name}{\hyperref[sailRISCVzscrzyname]{#2}}{}% + \ifstrequal{#1}{scr_name_map}{\hyperref[sailRISCVzscrzynamezymap]{#2}}{}% + \ifstrequal{#1}{sealCap}{\hyperref[sailRISCVzsealCap]{#2}}{}% + \ifstrequal{#1}{select_instr_or_fcsr_rm}{\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{#2}}{}% + \ifstrequal{#1}{sep}{\hyperref[sailRISCVzsep]{#2}}{}% + \ifstrequal{#1}{setCapAddr}{\hyperref[sailRISCVzsetCapAddr]{#2}}{}% + \ifstrequal{#1}{setCapBounds}{\hyperref[sailRISCVzsetCapBounds]{#2}}{}% + \ifstrequal{#1}{setCapFlags}{\hyperref[sailRISCVzsetCapFlags]{#2}}{}% + \ifstrequal{#1}{setCapOffset}{\hyperref[sailRISCVzsetCapOffset]{#2}}{}% + \ifstrequal{#1}{setCapOffsetOrNull}{\hyperref[sailRISCVzsetCapOffsetOrNull]{#2}}{}% + \ifstrequal{#1}{setCapPerms}{\hyperref[sailRISCVzsetCapPerms]{#2}}{}% + \ifstrequal{#1}{set_mstatus_SXL}{\hyperref[sailRISCVzsetzymstatuszySXL]{#2}}{}% + \ifstrequal{#1}{set_mstatus_UXL}{\hyperref[sailRISCVzsetzymstatuszyUXL]{#2}}{}% + \ifstrequal{#1}{set_mtvec}{\hyperref[sailRISCVzsetzymtvec]{#2}}{}% + \ifstrequal{#1}{set_next_pc}{\hyperref[sailRISCVzsetzynextzypc]{#2}}{}% + \ifstrequal{#1}{set_slice_bits}{\hyperref[sailRISCVzsetzyslicezybits]{#2}}{}% + \ifstrequal{#1}{set_slice_int}{\hyperref[sailRISCVzsetzyslicezyint]{#2}}{}% + \ifstrequal{#1}{set_sstatus_UXL}{\hyperref[sailRISCVzsetzysstatuszyUXL]{#2}}{}% + \ifstrequal{#1}{set_stvec}{\hyperref[sailRISCVzsetzystvec]{#2}}{}% + \ifstrequal{#1}{set_utvec}{\hyperref[sailRISCVzsetzyutvec]{#2}}{}% + \ifstrequal{#1}{set_xret_target}{\hyperref[sailRISCVzsetzyxretzytarget]{#2}}{}% + \ifstrequal{#1}{shift_bits_left}{\hyperref[sailRISCVzshiftzybitszyleft]{#2}}{}% + \ifstrequal{#1}{shift_bits_right}{\hyperref[sailRISCVzshiftzybitszyright]{#2}}{}% + \ifstrequal{#1}{shift_right_arith32}{\hyperref[sailRISCVzshiftzyrightzyarith32]{#2}}{}% + \ifstrequal{#1}{shift_right_arith64}{\hyperref[sailRISCVzshiftzyrightzyarith64]{#2}}{}% + \ifstrequal{#1}{shiftiop_mnemonic}{\hyperref[sailRISCVzshiftiopzymnemonic]{#2}}{}% + \ifstrequal{#1}{shiftiwop_mnemonic}{\hyperref[sailRISCVzshiftiwopzymnemonic]{#2}}{}% + \ifstrequal{#1}{shiftl}{\hyperref[sailRISCVzshiftl]{#2}}{}% + \ifstrequal{#1}{shiftr}{\hyperref[sailRISCVzshiftr]{#2}}{}% + \ifstrequal{#1}{shiftw_mnemonic}{\hyperref[sailRISCVzshiftwzymnemonic]{#2}}{}% + \ifstrequal{#1}{signed}{\hyperref[sailRISCVzsigned]{#2}}{}% + \ifstrequal{#1}{size_bits}{\hyperref[sailRISCVzsizzezybits]{#2}}{}% + \ifstrequal{#1}{size_mnemonic}{\hyperref[sailRISCVzsizzezymnemonic]{#2}}{}% + \ifstrequal{#1}{slice}{\hyperref[sailRISCVzslice]{#2}}{}% + \ifstrequal{#1}{slice_mask}{\hyperref[sailRISCVzslicezymask]{#2}}{}% + \ifstrequal{#1}{sop_of_num}{\hyperref[sailRISCVzsopzyofzynum]{#2}}{}% + \ifstrequal{#1}{sopw_of_num}{\hyperref[sailRISCVzsopwzyofzynum]{#2}}{}% + \ifstrequal{#1}{spc}{\hyperref[sailRISCVzspc]{#2}}{}% + \ifstrequal{#1}{spc_backwards}{\hyperref[sailRISCVzspczybackwards]{#2}}{}% + \ifstrequal{#1}{spc_forwards}{\hyperref[sailRISCVzspczyforwards]{#2}}{}% + \ifstrequal{#1}{spc_matches_prefix}{\hyperref[sailRISCVzspczymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{speculate_conditional}{\hyperref[sailRISCVzspeculatezyconditional]{#2}}{}% + \ifstrequal{#1}{step}{\hyperref[sailRISCVzstep]{#2}}{}% + \ifstrequal{#1}{string_append}{\hyperref[sailRISCVzstringzyappend]{#2}}{}% + \ifstrequal{#1}{string_drop}{\hyperref[sailRISCVzstringzydrop]{#2}}{}% + \ifstrequal{#1}{string_length}{\hyperref[sailRISCVzstringzylength]{#2}}{}% + \ifstrequal{#1}{string_of_bit}{\hyperref[sailRISCVzstringzyofzybit]{#2}}{}% + \ifstrequal{#1}{string_of_bits}{\hyperref[sailRISCVzstringzyofzybits]{#2}}{}% + \ifstrequal{#1}{string_of_capex}{\hyperref[sailRISCVzstringzyofzycapex]{#2}}{}% + \ifstrequal{#1}{string_of_int}{\hyperref[sailRISCVzstringzyofzyint]{#2}}{}% + \ifstrequal{#1}{string_startswith}{\hyperref[sailRISCVzstringzystartswith]{#2}}{}% + \ifstrequal{#1}{string_take}{\hyperref[sailRISCVzstringzytake]{#2}}{}% + \ifstrequal{#1}{sub_atom}{\hyperref[sailRISCVzsubzyatom]{#2}}{}% + \ifstrequal{#1}{sub_bits}{\hyperref[sailRISCVzsubzybits]{#2}}{}% + \ifstrequal{#1}{sub_int}{\hyperref[sailRISCVzsubzyint]{#2}}{}% + \ifstrequal{#1}{sub_nat}{\hyperref[sailRISCVzsubzynat]{#2}}{}% + \ifstrequal{#1}{sub_vec}{\hyperref[sailRISCVzsubzyvec]{#2}}{}% + \ifstrequal{#1}{sub_vec_int}{\hyperref[sailRISCVzsubzyveczyint]{#2}}{}% + \ifstrequal{#1}{subrange_bits}{\hyperref[sailRISCVzsubrangezybits]{#2}}{}% + \ifstrequal{#1}{sys_enable_fdext}{\hyperref[sailRISCVzsyszyenablezyfdext]{#2}}{}% + \ifstrequal{#1}{sys_enable_rvc}{\hyperref[sailRISCVzsyszyenablezyrvc]{#2}}{}% + \ifstrequal{#1}{sys_enable_writable_misa}{\hyperref[sailRISCVzsyszyenablezywritablezymisa]{#2}}{}% + \ifstrequal{#1}{tag_addr_to_addr}{\hyperref[sailRISCVztagzyaddrzytozyaddr]{#2}}{}% + \ifstrequal{#1}{tdiv_int}{\hyperref[sailRISCVztdivzyint]{#2}}{}% + \ifstrequal{#1}{tick_clock}{\hyperref[sailRISCVztickzyclock]{#2}}{}% + \ifstrequal{#1}{tick_pc}{\hyperref[sailRISCVztickzypc]{#2}}{}% + \ifstrequal{#1}{tick_platform}{\hyperref[sailRISCVztickzyplatform]{#2}}{}% + \ifstrequal{#1}{to_bits}{\hyperref[sailRISCVztozybits]{#2}}{}% + \ifstrequal{#1}{trans_kind_of_num}{\hyperref[sailRISCVztranszykindzyofzynum]{#2}}{}% + \ifstrequal{#1}{translate39}{\hyperref[sailRISCVztranslate39]{#2}}{}% + \ifstrequal{#1}{translate48}{\hyperref[sailRISCVztranslate48]{#2}}{}% + \ifstrequal{#1}{translateAddr}{\hyperref[sailRISCVztranslateAddr]{#2}}{}% + \ifstrequal{#1}{translationException}{\hyperref[sailRISCVztranslationException]{#2}}{}% + \ifstrequal{#1}{translationMode}{\hyperref[sailRISCVztranslationMode]{#2}}{}% + \ifstrequal{#1}{trapVectorMode_of_bits}{\hyperref[sailRISCVztrapVectorModezyofzybits]{#2}}{}% + \ifstrequal{#1}{trap_handler}{\hyperref[sailRISCVztrapzyhandler]{#2}}{}% + \ifstrequal{#1}{truncate}{\hyperref[sailRISCVztruncate]{#2}}{}% + \ifstrequal{#1}{truncateLSB}{\hyperref[sailRISCVztruncateLSB]{#2}}{}% + \ifstrequal{#1}{tval}{\hyperref[sailRISCVztval]{#2}}{}% + \ifstrequal{#1}{tvec_addr}{\hyperref[sailRISCVztveczyaddr]{#2}}{}% + \ifstrequal{#1}{ufFlag}{\hyperref[sailRISCVzufFlag]{#2}}{}% + \ifstrequal{#1}{unsealCap}{\hyperref[sailRISCVzunsealCap]{#2}}{}% + \ifstrequal{#1}{unsigned}{\hyperref[sailRISCVzunsigned]{#2}}{}% + \ifstrequal{#1}{uop_of_num}{\hyperref[sailRISCVzuopzyofzynum]{#2}}{}% + \ifstrequal{#1}{update_PTE_Bits}{\hyperref[sailRISCVzupdatezyPTEzyBits]{#2}}{}% + \ifstrequal{#1}{update_softfloat_fflags}{\hyperref[sailRISCVzupdatezysoftfloatzyfflags]{#2}}{}% + \ifstrequal{#1}{update_subrange}{\hyperref[sailRISCVzupdatezysubrange]{#2}}{}% + \ifstrequal{#1}{update_subrange_bits}{\hyperref[sailRISCVzupdatezysubrangezybits]{#2}}{}% + \ifstrequal{#1}{utype_mnemonic}{\hyperref[sailRISCVzutypezymnemonic]{#2}}{}% + \ifstrequal{#1}{vector_concat}{\hyperref[sailRISCVzvectorzyconcat]{#2}}{}% + \ifstrequal{#1}{vector_length}{\hyperref[sailRISCVzvectorzylength]{#2}}{}% + \ifstrequal{#1}{wC}{\hyperref[sailRISCVzwC]{#2}}{}% + \ifstrequal{#1}{wC_bits}{\hyperref[sailRISCVzwCzybits]{#2}}{}% + \ifstrequal{#1}{wF}{\hyperref[sailRISCVzwF]{#2}}{}% + \ifstrequal{#1}{wF_bits}{\hyperref[sailRISCVzwFzybits]{#2}}{}% + \ifstrequal{#1}{wX}{\hyperref[sailRISCVzwX]{#2}}{}% + \ifstrequal{#1}{wX_bits}{\hyperref[sailRISCVzwXzybits]{#2}}{}% + \ifstrequal{#1}{walk39}{\hyperref[sailRISCVzwalk39]{#2}}{}% + \ifstrequal{#1}{walk48}{\hyperref[sailRISCVzwalk48]{#2}}{}% + \ifstrequal{#1}{within_clint}{\hyperref[sailRISCVzwithinzyclint]{#2}}{}% + \ifstrequal{#1}{within_htif_readable}{\hyperref[sailRISCVzwithinzyhtifzyreadable]{#2}}{}% + \ifstrequal{#1}{within_htif_writable}{\hyperref[sailRISCVzwithinzyhtifzywritable]{#2}}{}% + \ifstrequal{#1}{within_mmio_readable}{\hyperref[sailRISCVzwithinzymmiozyreadable]{#2}}{}% + \ifstrequal{#1}{within_mmio_writable}{\hyperref[sailRISCVzwithinzymmiozywritable]{#2}}{}% + \ifstrequal{#1}{within_phys_mem}{\hyperref[sailRISCVzwithinzyphyszymem]{#2}}{}% + \ifstrequal{#1}{word_width_bytes}{\hyperref[sailRISCVzwordzywidthzybytes]{#2}}{}% + \ifstrequal{#1}{word_width_of_num}{\hyperref[sailRISCVzwordzywidthzyofzynum]{#2}}{}% + \ifstrequal{#1}{writeCSR}{\hyperref[sailRISCVzwriteCSR]{#2}}{}% + \ifstrequal{#1}{write_TLB39}{\hyperref[sailRISCVzwritezyTLB39]{#2}}{}% + \ifstrequal{#1}{write_TLB48}{\hyperref[sailRISCVzwritezyTLB48]{#2}}{}% + \ifstrequal{#1}{write_fflags}{\hyperref[sailRISCVzwritezyfflags]{#2}}{}% + \ifstrequal{#1}{write_kind_of_num}{\hyperref[sailRISCVzwritezykindzyofzynum]{#2}}{}% + \ifstrequal{#1}{write_ram}{\hyperref[sailRISCVzwritezyram]{#2}}{}% + \ifstrequal{#1}{write_ram_ea}{\hyperref[sailRISCVzwritezyramzyea]{#2}}{}% + \ifstrequal{#1}{xor_vec}{\hyperref[sailRISCVzxorzyvec]{#2}}{}% + \ifstrequal{#1}{zeros_implicit}{\hyperref[sailRISCVzzzeroszyimplicit]{#2}}{}% + \ifstrequal{#1}{(operator <=_u)}{\hyperref[sailRISCVzz8operatorz0zIzJzyuz9]{#2}}{}% + \ifstrequal{#1}{(operator <_s)}{\hyperref[sailRISCVzz8operatorz0zIzysz9]{#2}}{}% + \ifstrequal{#1}{(operator <_u)}{\hyperref[sailRISCVzz8operatorz0zIzyuz9]{#2}}{}% + \ifstrequal{#1}{(operator >=_s)}{\hyperref[sailRISCVzz8operatorz0zKzJzysz9]{#2}}{}% + \ifstrequal{#1}{(operator >=_u)}{\hyperref[sailRISCVzz8operatorz0zKzJzyuz9]{#2}}{}} + +\newcommand{\sailRISCVfn}[1]{ + \ifstrequal{#1}{Architecture\_of\_num}{\sailRISCVfnArchitectureOfNum}{}% + \ifstrequal{#1}{CPtrCmpOp\_of\_num}{\sailRISCVfnCPtrCmpOpOfNum}{}% + \ifstrequal{#1}{CapExCode}{\sailRISCVfnCapExCode}{}% + \ifstrequal{#1}{CapEx\_of\_num}{\sailRISCVfnCapExOfNum}{}% + \ifstrequal{#1}{ClearRegSet\_of\_num}{\sailRISCVfnClearRegSetOfNum}{}% + \ifstrequal{#1}{EXTS}{\sailRISCVfnEXTS}{}% + \ifstrequal{#1}{EXTZ}{\sailRISCVfnEXTZ}{}% + \ifstrequal{#1}{ExtStatus\_of\_num}{\sailRISCVfnExtStatusOfNum}{}% + \ifstrequal{#1}{FRegStr}{\sailRISCVfnFRegStr}{}% + \ifstrequal{#1}{GPRstr}{\sailRISCVfnGPRstr}{}% + \ifstrequal{#1}{InterruptType\_of\_num}{\sailRISCVfnInterruptTypeOfNum}{}% + \ifstrequal{#1}{MAX}{\sailRISCVfnMAX}{}% + \ifstrequal{#1}{MemoryOpResult\_add\_meta}{\sailRISCVfnMemoryOpResultAddMeta}{}% + \ifstrequal{#1}{MemoryOpResult\_drop\_meta}{\sailRISCVfnMemoryOpResultDropMeta}{}% + \ifstrequal{#1}{Mk\_Counteren}{\sailRISCVfnMkCounteren}{}% + \ifstrequal{#1}{Mk\_Counterin}{\sailRISCVfnMkCounterin}{}% + \ifstrequal{#1}{Mk\_Ext\_PTE\_Bits}{\sailRISCVfnMkExtPTEBits}{}% + \ifstrequal{#1}{Mk\_Fcsr}{\sailRISCVfnMkFcsr}{}% + \ifstrequal{#1}{Mk\_Mcause}{\sailRISCVfnMkMcause}{}% + \ifstrequal{#1}{Mk\_Medeleg}{\sailRISCVfnMkMedeleg}{}% + \ifstrequal{#1}{Mk\_Minterrupts}{\sailRISCVfnMkMinterrupts}{}% + \ifstrequal{#1}{Mk\_Misa}{\sailRISCVfnMkMisa}{}% + \ifstrequal{#1}{Mk\_Mstatus}{\sailRISCVfnMkMstatus}{}% + \ifstrequal{#1}{Mk\_Mtvec}{\sailRISCVfnMkMtvec}{}% + \ifstrequal{#1}{Mk\_PTE\_Bits}{\sailRISCVfnMkPTEBits}{}% + \ifstrequal{#1}{Mk\_Pmpcfg\_ent}{\sailRISCVfnMkPmpcfgEnt}{}% + \ifstrequal{#1}{Mk\_SV32\_PTE}{\sailRISCVfnMkSVThreeTwoPTE}{}% + \ifstrequal{#1}{Mk\_SV32\_Paddr}{\sailRISCVfnMkSVThreeTwoPaddr}{}% + \ifstrequal{#1}{Mk\_SV32\_Vaddr}{\sailRISCVfnMkSVThreeTwoVaddr}{}% + \ifstrequal{#1}{Mk\_SV39\_PTE}{\sailRISCVfnMkSVThreeNinePTE}{}% + \ifstrequal{#1}{Mk\_SV39\_Paddr}{\sailRISCVfnMkSVThreeNinePaddr}{}% + \ifstrequal{#1}{Mk\_SV39\_Vaddr}{\sailRISCVfnMkSVThreeNineVaddr}{}% + \ifstrequal{#1}{Mk\_SV48\_PTE}{\sailRISCVfnMkSVFourEightPTE}{}% + \ifstrequal{#1}{Mk\_SV48\_Paddr}{\sailRISCVfnMkSVFourEightPaddr}{}% + \ifstrequal{#1}{Mk\_SV48\_Vaddr}{\sailRISCVfnMkSVFourEightVaddr}{}% + \ifstrequal{#1}{Mk\_Satp32}{\sailRISCVfnMkSatpThreeTwo}{}% + \ifstrequal{#1}{Mk\_Satp64}{\sailRISCVfnMkSatpSixFour}{}% + \ifstrequal{#1}{Mk\_Sedeleg}{\sailRISCVfnMkSedeleg}{}% + \ifstrequal{#1}{Mk\_Sinterrupts}{\sailRISCVfnMkSinterrupts}{}% + \ifstrequal{#1}{Mk\_Sstatus}{\sailRISCVfnMkSstatus}{}% + \ifstrequal{#1}{Mk\_Uinterrupts}{\sailRISCVfnMkUinterrupts}{}% + \ifstrequal{#1}{Mk\_Ustatus}{\sailRISCVfnMkUstatus}{}% + \ifstrequal{#1}{Mk\_ccsr}{\sailRISCVfnMkCcsr}{}% + \ifstrequal{#1}{Mk\_htif\_cmd}{\sailRISCVfnMkHtifCmd}{}% + \ifstrequal{#1}{PmpAddrMatchType\_of\_num}{\sailRISCVfnPmpAddrMatchTypeOfNum}{}% + \ifstrequal{#1}{Privilege\_of\_num}{\sailRISCVfnPrivilegeOfNum}{}% + \ifstrequal{#1}{RegStr}{\sailRISCVfnRegStr}{}% + \ifstrequal{#1}{Retired\_of\_num}{\sailRISCVfnRetiredOfNum}{}% + \ifstrequal{#1}{SATPMode\_of\_num}{\sailRISCVfnSATPModeOfNum}{}% + \ifstrequal{#1}{TrapVectorMode\_of\_num}{\sailRISCVfnTrapVectorModeOfNum}{}% + \ifstrequal{#1}{\_\_ReadRAM\_Meta}{\sailRISCVfnReadRAMMeta}{}% + \ifstrequal{#1}{\_\_WriteRAM\_Meta}{\sailRISCVfnWriteRAMMeta}{}% + \ifstrequal{#1}{\_\_id}{\sailRISCVfnId}{}% + \ifstrequal{#1}{\_get\_Counteren\_CY}{\sailRISCVfnGetCounterenCY}{}% + \ifstrequal{#1}{\_get\_Counteren\_HPM}{\sailRISCVfnGetCounterenHPM}{}% + \ifstrequal{#1}{\_get\_Counteren\_IR}{\sailRISCVfnGetCounterenIR}{}% + \ifstrequal{#1}{\_get\_Counteren\_TM}{\sailRISCVfnGetCounterenTM}{}% + \ifstrequal{#1}{\_get\_Counteren\_bits}{\sailRISCVfnGetCounterenBits}{}% + \ifstrequal{#1}{\_get\_Counterin\_CY}{\sailRISCVfnGetCounterinCY}{}% + \ifstrequal{#1}{\_get\_Counterin\_IR}{\sailRISCVfnGetCounterinIR}{}% + \ifstrequal{#1}{\_get\_Counterin\_bits}{\sailRISCVfnGetCounterinBits}{}% + \ifstrequal{#1}{\_get\_Ext\_PTE\_Bits\_CapRead}{\sailRISCVfnGetExtPTEBitsCapRead}{}% + \ifstrequal{#1}{\_get\_Ext\_PTE\_Bits\_CapWrite}{\sailRISCVfnGetExtPTEBitsCapWrite}{}% + \ifstrequal{#1}{\_get\_Ext\_PTE\_Bits\_bits}{\sailRISCVfnGetExtPTEBitsBits}{}% + \ifstrequal{#1}{\_get\_Fcsr\_FFLAGS}{\sailRISCVfnGetFcsrFFLAGS}{}% + \ifstrequal{#1}{\_get\_Fcsr\_FRM}{\sailRISCVfnGetFcsrFRM}{}% + \ifstrequal{#1}{\_get\_Fcsr\_bits}{\sailRISCVfnGetFcsrBits}{}% + \ifstrequal{#1}{\_get\_Mcause\_Cause}{\sailRISCVfnGetMcauseCause}{}% + \ifstrequal{#1}{\_get\_Mcause\_IsInterrupt}{\sailRISCVfnGetMcauseIsInterrupt}{}% + \ifstrequal{#1}{\_get\_Mcause\_bits}{\sailRISCVfnGetMcauseBits}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Breakpoint}{\sailRISCVfnGetMedelegBreakpoint}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Fetch\_Access\_Fault}{\sailRISCVfnGetMedelegFetchAccessFault}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Fetch\_Addr\_Align}{\sailRISCVfnGetMedelegFetchAddrAlign}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Fetch\_Page\_Fault}{\sailRISCVfnGetMedelegFetchPageFault}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Illegal\_Instr}{\sailRISCVfnGetMedelegIllegalInstr}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Load\_Access\_Fault}{\sailRISCVfnGetMedelegLoadAccessFault}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Load\_Addr\_Align}{\sailRISCVfnGetMedelegLoadAddrAlign}{}% + \ifstrequal{#1}{\_get\_Medeleg\_Load\_Page\_Fault}{\sailRISCVfnGetMedelegLoadPageFault}{}% + \ifstrequal{#1}{\_get\_Medeleg\_MEnvCall}{\sailRISCVfnGetMedelegMEnvCall}{}% + \ifstrequal{#1}{\_get\_Medeleg\_SAMO\_Access\_Fault}{\sailRISCVfnGetMedelegSAMOAccessFault}{}% + \ifstrequal{#1}{\_get\_Medeleg\_SAMO\_Addr\_Align}{\sailRISCVfnGetMedelegSAMOAddrAlign}{}% + \ifstrequal{#1}{\_get\_Medeleg\_SAMO\_Page\_Fault}{\sailRISCVfnGetMedelegSAMOPageFault}{}% + \ifstrequal{#1}{\_get\_Medeleg\_SEnvCall}{\sailRISCVfnGetMedelegSEnvCall}{}% + \ifstrequal{#1}{\_get\_Medeleg\_UEnvCall}{\sailRISCVfnGetMedelegUEnvCall}{}% + \ifstrequal{#1}{\_get\_Medeleg\_bits}{\sailRISCVfnGetMedelegBits}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_MEI}{\sailRISCVfnGetMinterruptsMEI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_MSI}{\sailRISCVfnGetMinterruptsMSI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_MTI}{\sailRISCVfnGetMinterruptsMTI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_SEI}{\sailRISCVfnGetMinterruptsSEI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_SSI}{\sailRISCVfnGetMinterruptsSSI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_STI}{\sailRISCVfnGetMinterruptsSTI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_UEI}{\sailRISCVfnGetMinterruptsUEI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_USI}{\sailRISCVfnGetMinterruptsUSI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_UTI}{\sailRISCVfnGetMinterruptsUTI}{}% + \ifstrequal{#1}{\_get\_Minterrupts\_bits}{\sailRISCVfnGetMinterruptsBits}{}% + \ifstrequal{#1}{\_get\_Misa\_A}{\sailRISCVfnGetMisaA}{}% + \ifstrequal{#1}{\_get\_Misa\_B}{\sailRISCVfnGetMisaB}{}% + \ifstrequal{#1}{\_get\_Misa\_C}{\sailRISCVfnGetMisaC}{}% + \ifstrequal{#1}{\_get\_Misa\_D}{\sailRISCVfnGetMisaD}{}% + \ifstrequal{#1}{\_get\_Misa\_E}{\sailRISCVfnGetMisaE}{}% + \ifstrequal{#1}{\_get\_Misa\_F}{\sailRISCVfnGetMisaF}{}% + \ifstrequal{#1}{\_get\_Misa\_G}{\sailRISCVfnGetMisaG}{}% + \ifstrequal{#1}{\_get\_Misa\_H}{\sailRISCVfnGetMisaH}{}% + \ifstrequal{#1}{\_get\_Misa\_I}{\sailRISCVfnGetMisaI}{}% + \ifstrequal{#1}{\_get\_Misa\_J}{\sailRISCVfnGetMisaJ}{}% + \ifstrequal{#1}{\_get\_Misa\_K}{\sailRISCVfnGetMisaK}{}% + \ifstrequal{#1}{\_get\_Misa\_L}{\sailRISCVfnGetMisaL}{}% + \ifstrequal{#1}{\_get\_Misa\_M}{\sailRISCVfnGetMisaM}{}% + \ifstrequal{#1}{\_get\_Misa\_MXL}{\sailRISCVfnGetMisaMXL}{}% + \ifstrequal{#1}{\_get\_Misa\_N}{\sailRISCVfnGetMisaN}{}% + \ifstrequal{#1}{\_get\_Misa\_O}{\sailRISCVfnGetMisaO}{}% + \ifstrequal{#1}{\_get\_Misa\_P}{\sailRISCVfnGetMisaP}{}% + \ifstrequal{#1}{\_get\_Misa\_Q}{\sailRISCVfnGetMisaQ}{}% + \ifstrequal{#1}{\_get\_Misa\_R}{\sailRISCVfnGetMisaR}{}% + \ifstrequal{#1}{\_get\_Misa\_S}{\sailRISCVfnGetMisaS}{}% + \ifstrequal{#1}{\_get\_Misa\_T}{\sailRISCVfnGetMisaT}{}% + \ifstrequal{#1}{\_get\_Misa\_U}{\sailRISCVfnGetMisaU}{}% + \ifstrequal{#1}{\_get\_Misa\_V}{\sailRISCVfnGetMisaV}{}% + \ifstrequal{#1}{\_get\_Misa\_W}{\sailRISCVfnGetMisaW}{}% + \ifstrequal{#1}{\_get\_Misa\_X}{\sailRISCVfnGetMisaX}{}% + \ifstrequal{#1}{\_get\_Misa\_Y}{\sailRISCVfnGetMisaY}{}% + \ifstrequal{#1}{\_get\_Misa\_Z}{\sailRISCVfnGetMisaZ}{}% + \ifstrequal{#1}{\_get\_Misa\_bits}{\sailRISCVfnGetMisaBits}{}% + \ifstrequal{#1}{\_get\_Mstatus\_FS}{\sailRISCVfnGetMstatusFS}{}% + \ifstrequal{#1}{\_get\_Mstatus\_MIE}{\sailRISCVfnGetMstatusMIE}{}% + \ifstrequal{#1}{\_get\_Mstatus\_MPIE}{\sailRISCVfnGetMstatusMPIE}{}% + \ifstrequal{#1}{\_get\_Mstatus\_MPP}{\sailRISCVfnGetMstatusMPP}{}% + \ifstrequal{#1}{\_get\_Mstatus\_MPRV}{\sailRISCVfnGetMstatusMPRV}{}% + \ifstrequal{#1}{\_get\_Mstatus\_MXR}{\sailRISCVfnGetMstatusMXR}{}% + \ifstrequal{#1}{\_get\_Mstatus\_SD}{\sailRISCVfnGetMstatusSD}{}% + \ifstrequal{#1}{\_get\_Mstatus\_SIE}{\sailRISCVfnGetMstatusSIE}{}% + \ifstrequal{#1}{\_get\_Mstatus\_SPIE}{\sailRISCVfnGetMstatusSPIE}{}% + \ifstrequal{#1}{\_get\_Mstatus\_SPP}{\sailRISCVfnGetMstatusSPP}{}% + \ifstrequal{#1}{\_get\_Mstatus\_SUM}{\sailRISCVfnGetMstatusSUM}{}% + \ifstrequal{#1}{\_get\_Mstatus\_TSR}{\sailRISCVfnGetMstatusTSR}{}% + \ifstrequal{#1}{\_get\_Mstatus\_TVM}{\sailRISCVfnGetMstatusTVM}{}% + \ifstrequal{#1}{\_get\_Mstatus\_TW}{\sailRISCVfnGetMstatusTW}{}% + \ifstrequal{#1}{\_get\_Mstatus\_UIE}{\sailRISCVfnGetMstatusUIE}{}% + \ifstrequal{#1}{\_get\_Mstatus\_UPIE}{\sailRISCVfnGetMstatusUPIE}{}% + \ifstrequal{#1}{\_get\_Mstatus\_XS}{\sailRISCVfnGetMstatusXS}{}% + \ifstrequal{#1}{\_get\_Mstatus\_bits}{\sailRISCVfnGetMstatusBits}{}% + \ifstrequal{#1}{\_get\_Mtvec\_Base}{\sailRISCVfnGetMtvecBase}{}% + \ifstrequal{#1}{\_get\_Mtvec\_Mode}{\sailRISCVfnGetMtvecMode}{}% + \ifstrequal{#1}{\_get\_Mtvec\_bits}{\sailRISCVfnGetMtvecBits}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_A}{\sailRISCVfnGetPTEBitsA}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_D}{\sailRISCVfnGetPTEBitsD}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_G}{\sailRISCVfnGetPTEBitsG}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_R}{\sailRISCVfnGetPTEBitsR}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_U}{\sailRISCVfnGetPTEBitsU}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_V}{\sailRISCVfnGetPTEBitsV}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_W}{\sailRISCVfnGetPTEBitsW}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_X}{\sailRISCVfnGetPTEBitsX}{}% + \ifstrequal{#1}{\_get\_PTE\_Bits\_bits}{\sailRISCVfnGetPTEBitsBits}{}% + \ifstrequal{#1}{\_get\_Pmpcfg\_ent\_A}{\sailRISCVfnGetPmpcfgEntA}{}% + \ifstrequal{#1}{\_get\_Pmpcfg\_ent\_L}{\sailRISCVfnGetPmpcfgEntL}{}% + \ifstrequal{#1}{\_get\_Pmpcfg\_ent\_R}{\sailRISCVfnGetPmpcfgEntR}{}% + \ifstrequal{#1}{\_get\_Pmpcfg\_ent\_W}{\sailRISCVfnGetPmpcfgEntW}{}% + \ifstrequal{#1}{\_get\_Pmpcfg\_ent\_X}{\sailRISCVfnGetPmpcfgEntX}{}% + \ifstrequal{#1}{\_get\_Pmpcfg\_ent\_bits}{\sailRISCVfnGetPmpcfgEntBits}{}% + \ifstrequal{#1}{\_get\_SV32\_PTE\_BITS}{\sailRISCVfnGetSVThreeTwoPTEBITS}{}% + \ifstrequal{#1}{\_get\_SV32\_PTE\_PPNi}{\sailRISCVfnGetSVThreeTwoPTEPPNi}{}% + \ifstrequal{#1}{\_get\_SV32\_PTE\_RSW}{\sailRISCVfnGetSVThreeTwoPTERSW}{}% + \ifstrequal{#1}{\_get\_SV32\_PTE\_bits}{\sailRISCVfnGetSVThreeTwoPTEBits}{}% + \ifstrequal{#1}{\_get\_SV32\_Paddr\_PPNi}{\sailRISCVfnGetSVThreeTwoPaddrPPNi}{}% + \ifstrequal{#1}{\_get\_SV32\_Paddr\_PgOfs}{\sailRISCVfnGetSVThreeTwoPaddrPgOfs}{}% + \ifstrequal{#1}{\_get\_SV32\_Paddr\_bits}{\sailRISCVfnGetSVThreeTwoPaddrBits}{}% + \ifstrequal{#1}{\_get\_SV32\_Vaddr\_PgOfs}{\sailRISCVfnGetSVThreeTwoVaddrPgOfs}{}% + \ifstrequal{#1}{\_get\_SV32\_Vaddr\_VPNi}{\sailRISCVfnGetSVThreeTwoVaddrVPNi}{}% + \ifstrequal{#1}{\_get\_SV32\_Vaddr\_bits}{\sailRISCVfnGetSVThreeTwoVaddrBits}{}% + \ifstrequal{#1}{\_get\_SV39\_PTE\_BITS}{\sailRISCVfnGetSVThreeNinePTEBITS}{}% + \ifstrequal{#1}{\_get\_SV39\_PTE\_Ext}{\sailRISCVfnGetSVThreeNinePTEExt}{}% + \ifstrequal{#1}{\_get\_SV39\_PTE\_PPNi}{\sailRISCVfnGetSVThreeNinePTEPPNi}{}% + \ifstrequal{#1}{\_get\_SV39\_PTE\_RSW}{\sailRISCVfnGetSVThreeNinePTERSW}{}% + \ifstrequal{#1}{\_get\_SV39\_PTE\_bits}{\sailRISCVfnGetSVThreeNinePTEBits}{}% + \ifstrequal{#1}{\_get\_SV39\_Paddr\_PPNi}{\sailRISCVfnGetSVThreeNinePaddrPPNi}{}% + \ifstrequal{#1}{\_get\_SV39\_Paddr\_PgOfs}{\sailRISCVfnGetSVThreeNinePaddrPgOfs}{}% + \ifstrequal{#1}{\_get\_SV39\_Paddr\_bits}{\sailRISCVfnGetSVThreeNinePaddrBits}{}% + \ifstrequal{#1}{\_get\_SV39\_Vaddr\_PgOfs}{\sailRISCVfnGetSVThreeNineVaddrPgOfs}{}% + \ifstrequal{#1}{\_get\_SV39\_Vaddr\_VPNi}{\sailRISCVfnGetSVThreeNineVaddrVPNi}{}% + \ifstrequal{#1}{\_get\_SV39\_Vaddr\_bits}{\sailRISCVfnGetSVThreeNineVaddrBits}{}% + \ifstrequal{#1}{\_get\_SV48\_PTE\_BITS}{\sailRISCVfnGetSVFourEightPTEBITS}{}% + \ifstrequal{#1}{\_get\_SV48\_PTE\_Ext}{\sailRISCVfnGetSVFourEightPTEExt}{}% + \ifstrequal{#1}{\_get\_SV48\_PTE\_PPNi}{\sailRISCVfnGetSVFourEightPTEPPNi}{}% + \ifstrequal{#1}{\_get\_SV48\_PTE\_RSW}{\sailRISCVfnGetSVFourEightPTERSW}{}% + \ifstrequal{#1}{\_get\_SV48\_PTE\_bits}{\sailRISCVfnGetSVFourEightPTEBits}{}% + \ifstrequal{#1}{\_get\_SV48\_Paddr\_PPNi}{\sailRISCVfnGetSVFourEightPaddrPPNi}{}% + \ifstrequal{#1}{\_get\_SV48\_Paddr\_PgOfs}{\sailRISCVfnGetSVFourEightPaddrPgOfs}{}% + \ifstrequal{#1}{\_get\_SV48\_Paddr\_bits}{\sailRISCVfnGetSVFourEightPaddrBits}{}% + \ifstrequal{#1}{\_get\_SV48\_Vaddr\_PgOfs}{\sailRISCVfnGetSVFourEightVaddrPgOfs}{}% + \ifstrequal{#1}{\_get\_SV48\_Vaddr\_VPNi}{\sailRISCVfnGetSVFourEightVaddrVPNi}{}% + \ifstrequal{#1}{\_get\_SV48\_Vaddr\_bits}{\sailRISCVfnGetSVFourEightVaddrBits}{}% + \ifstrequal{#1}{\_get\_Satp32\_Asid}{\sailRISCVfnGetSatpThreeTwoAsid}{}% + \ifstrequal{#1}{\_get\_Satp32\_Mode}{\sailRISCVfnGetSatpThreeTwoMode}{}% + \ifstrequal{#1}{\_get\_Satp32\_PPN}{\sailRISCVfnGetSatpThreeTwoPPN}{}% + \ifstrequal{#1}{\_get\_Satp32\_bits}{\sailRISCVfnGetSatpThreeTwoBits}{}% + \ifstrequal{#1}{\_get\_Satp64\_Asid}{\sailRISCVfnGetSatpSixFourAsid}{}% + \ifstrequal{#1}{\_get\_Satp64\_Mode}{\sailRISCVfnGetSatpSixFourMode}{}% + \ifstrequal{#1}{\_get\_Satp64\_PPN}{\sailRISCVfnGetSatpSixFourPPN}{}% + \ifstrequal{#1}{\_get\_Satp64\_bits}{\sailRISCVfnGetSatpSixFourBits}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_Breakpoint}{\sailRISCVfnGetSedelegBreakpoint}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_Fetch\_Access\_Fault}{\sailRISCVfnGetSedelegFetchAccessFault}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_Fetch\_Addr\_Align}{\sailRISCVfnGetSedelegFetchAddrAlign}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_Illegal\_Instr}{\sailRISCVfnGetSedelegIllegalInstr}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_Load\_Access\_Fault}{\sailRISCVfnGetSedelegLoadAccessFault}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_Load\_Addr\_Align}{\sailRISCVfnGetSedelegLoadAddrAlign}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_SAMO\_Access\_Fault}{\sailRISCVfnGetSedelegSAMOAccessFault}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_SAMO\_Addr\_Align}{\sailRISCVfnGetSedelegSAMOAddrAlign}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_UEnvCall}{\sailRISCVfnGetSedelegUEnvCall}{}% + \ifstrequal{#1}{\_get\_Sedeleg\_bits}{\sailRISCVfnGetSedelegBits}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_SEI}{\sailRISCVfnGetSinterruptsSEI}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_SSI}{\sailRISCVfnGetSinterruptsSSI}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_STI}{\sailRISCVfnGetSinterruptsSTI}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_UEI}{\sailRISCVfnGetSinterruptsUEI}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_USI}{\sailRISCVfnGetSinterruptsUSI}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_UTI}{\sailRISCVfnGetSinterruptsUTI}{}% + \ifstrequal{#1}{\_get\_Sinterrupts\_bits}{\sailRISCVfnGetSinterruptsBits}{}% + \ifstrequal{#1}{\_get\_Sstatus\_FS}{\sailRISCVfnGetSstatusFS}{}% + \ifstrequal{#1}{\_get\_Sstatus\_MXR}{\sailRISCVfnGetSstatusMXR}{}% + \ifstrequal{#1}{\_get\_Sstatus\_SD}{\sailRISCVfnGetSstatusSD}{}% + \ifstrequal{#1}{\_get\_Sstatus\_SIE}{\sailRISCVfnGetSstatusSIE}{}% + \ifstrequal{#1}{\_get\_Sstatus\_SPIE}{\sailRISCVfnGetSstatusSPIE}{}% + \ifstrequal{#1}{\_get\_Sstatus\_SPP}{\sailRISCVfnGetSstatusSPP}{}% + \ifstrequal{#1}{\_get\_Sstatus\_SUM}{\sailRISCVfnGetSstatusSUM}{}% + \ifstrequal{#1}{\_get\_Sstatus\_UIE}{\sailRISCVfnGetSstatusUIE}{}% + \ifstrequal{#1}{\_get\_Sstatus\_UPIE}{\sailRISCVfnGetSstatusUPIE}{}% + \ifstrequal{#1}{\_get\_Sstatus\_XS}{\sailRISCVfnGetSstatusXS}{}% + \ifstrequal{#1}{\_get\_Sstatus\_bits}{\sailRISCVfnGetSstatusBits}{}% + \ifstrequal{#1}{\_get\_Uinterrupts\_UEI}{\sailRISCVfnGetUinterruptsUEI}{}% + \ifstrequal{#1}{\_get\_Uinterrupts\_USI}{\sailRISCVfnGetUinterruptsUSI}{}% + \ifstrequal{#1}{\_get\_Uinterrupts\_UTI}{\sailRISCVfnGetUinterruptsUTI}{}% + \ifstrequal{#1}{\_get\_Uinterrupts\_bits}{\sailRISCVfnGetUinterruptsBits}{}% + \ifstrequal{#1}{\_get\_Ustatus\_UIE}{\sailRISCVfnGetUstatusUIE}{}% + \ifstrequal{#1}{\_get\_Ustatus\_UPIE}{\sailRISCVfnGetUstatusUPIE}{}% + \ifstrequal{#1}{\_get\_Ustatus\_bits}{\sailRISCVfnGetUstatusBits}{}% + \ifstrequal{#1}{\_get\_ccsr\_bits}{\sailRISCVfnGetCcsrBits}{}% + \ifstrequal{#1}{\_get\_ccsr\_cap\_idx}{\sailRISCVfnGetCcsrCapIdx}{}% + \ifstrequal{#1}{\_get\_ccsr\_cause}{\sailRISCVfnGetCcsrCause}{}% + \ifstrequal{#1}{\_get\_ccsr\_d}{\sailRISCVfnGetCcsrD}{}% + \ifstrequal{#1}{\_get\_ccsr\_e}{\sailRISCVfnGetCcsrE}{}% + \ifstrequal{#1}{\_get\_htif\_cmd\_bits}{\sailRISCVfnGetHtifCmdBits}{}% + \ifstrequal{#1}{\_get\_htif\_cmd\_cmd}{\sailRISCVfnGetHtifCmdCmd}{}% + \ifstrequal{#1}{\_get\_htif\_cmd\_device}{\sailRISCVfnGetHtifCmdDevice}{}% + \ifstrequal{#1}{\_get\_htif\_cmd\_payload}{\sailRISCVfnGetHtifCmdPayload}{}% + \ifstrequal{#1}{\_set\_Counteren\_CY}{\sailRISCVfnSetCounterenCY}{}% + \ifstrequal{#1}{\_set\_Counteren\_HPM}{\sailRISCVfnSetCounterenHPM}{}% + \ifstrequal{#1}{\_set\_Counteren\_IR}{\sailRISCVfnSetCounterenIR}{}% + \ifstrequal{#1}{\_set\_Counteren\_TM}{\sailRISCVfnSetCounterenTM}{}% + \ifstrequal{#1}{\_set\_Counteren\_bits}{\sailRISCVfnSetCounterenBits}{}% + \ifstrequal{#1}{\_set\_Counterin\_CY}{\sailRISCVfnSetCounterinCY}{}% + \ifstrequal{#1}{\_set\_Counterin\_IR}{\sailRISCVfnSetCounterinIR}{}% + \ifstrequal{#1}{\_set\_Counterin\_bits}{\sailRISCVfnSetCounterinBits}{}% + \ifstrequal{#1}{\_set\_Ext\_PTE\_Bits\_CapRead}{\sailRISCVfnSetExtPTEBitsCapRead}{}% + \ifstrequal{#1}{\_set\_Ext\_PTE\_Bits\_CapWrite}{\sailRISCVfnSetExtPTEBitsCapWrite}{}% + \ifstrequal{#1}{\_set\_Ext\_PTE\_Bits\_bits}{\sailRISCVfnSetExtPTEBitsBits}{}% + \ifstrequal{#1}{\_set\_Fcsr\_FFLAGS}{\sailRISCVfnSetFcsrFFLAGS}{}% + \ifstrequal{#1}{\_set\_Fcsr\_FRM}{\sailRISCVfnSetFcsrFRM}{}% + \ifstrequal{#1}{\_set\_Fcsr\_bits}{\sailRISCVfnSetFcsrBits}{}% + \ifstrequal{#1}{\_set\_Mcause\_Cause}{\sailRISCVfnSetMcauseCause}{}% + \ifstrequal{#1}{\_set\_Mcause\_IsInterrupt}{\sailRISCVfnSetMcauseIsInterrupt}{}% + \ifstrequal{#1}{\_set\_Mcause\_bits}{\sailRISCVfnSetMcauseBits}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Breakpoint}{\sailRISCVfnSetMedelegBreakpoint}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Fetch\_Access\_Fault}{\sailRISCVfnSetMedelegFetchAccessFault}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Fetch\_Addr\_Align}{\sailRISCVfnSetMedelegFetchAddrAlign}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Fetch\_Page\_Fault}{\sailRISCVfnSetMedelegFetchPageFault}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Illegal\_Instr}{\sailRISCVfnSetMedelegIllegalInstr}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Load\_Access\_Fault}{\sailRISCVfnSetMedelegLoadAccessFault}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Load\_Addr\_Align}{\sailRISCVfnSetMedelegLoadAddrAlign}{}% + \ifstrequal{#1}{\_set\_Medeleg\_Load\_Page\_Fault}{\sailRISCVfnSetMedelegLoadPageFault}{}% + \ifstrequal{#1}{\_set\_Medeleg\_MEnvCall}{\sailRISCVfnSetMedelegMEnvCall}{}% + \ifstrequal{#1}{\_set\_Medeleg\_SAMO\_Access\_Fault}{\sailRISCVfnSetMedelegSAMOAccessFault}{}% + \ifstrequal{#1}{\_set\_Medeleg\_SAMO\_Addr\_Align}{\sailRISCVfnSetMedelegSAMOAddrAlign}{}% + \ifstrequal{#1}{\_set\_Medeleg\_SAMO\_Page\_Fault}{\sailRISCVfnSetMedelegSAMOPageFault}{}% + \ifstrequal{#1}{\_set\_Medeleg\_SEnvCall}{\sailRISCVfnSetMedelegSEnvCall}{}% + \ifstrequal{#1}{\_set\_Medeleg\_UEnvCall}{\sailRISCVfnSetMedelegUEnvCall}{}% + \ifstrequal{#1}{\_set\_Medeleg\_bits}{\sailRISCVfnSetMedelegBits}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_MEI}{\sailRISCVfnSetMinterruptsMEI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_MSI}{\sailRISCVfnSetMinterruptsMSI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_MTI}{\sailRISCVfnSetMinterruptsMTI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_SEI}{\sailRISCVfnSetMinterruptsSEI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_SSI}{\sailRISCVfnSetMinterruptsSSI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_STI}{\sailRISCVfnSetMinterruptsSTI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_UEI}{\sailRISCVfnSetMinterruptsUEI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_USI}{\sailRISCVfnSetMinterruptsUSI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_UTI}{\sailRISCVfnSetMinterruptsUTI}{}% + \ifstrequal{#1}{\_set\_Minterrupts\_bits}{\sailRISCVfnSetMinterruptsBits}{}% + \ifstrequal{#1}{\_set\_Misa\_A}{\sailRISCVfnSetMisaA}{}% + \ifstrequal{#1}{\_set\_Misa\_B}{\sailRISCVfnSetMisaB}{}% + \ifstrequal{#1}{\_set\_Misa\_C}{\sailRISCVfnSetMisaC}{}% + \ifstrequal{#1}{\_set\_Misa\_D}{\sailRISCVfnSetMisaD}{}% + \ifstrequal{#1}{\_set\_Misa\_E}{\sailRISCVfnSetMisaE}{}% + \ifstrequal{#1}{\_set\_Misa\_F}{\sailRISCVfnSetMisaF}{}% + \ifstrequal{#1}{\_set\_Misa\_G}{\sailRISCVfnSetMisaG}{}% + \ifstrequal{#1}{\_set\_Misa\_H}{\sailRISCVfnSetMisaH}{}% + \ifstrequal{#1}{\_set\_Misa\_I}{\sailRISCVfnSetMisaI}{}% + \ifstrequal{#1}{\_set\_Misa\_J}{\sailRISCVfnSetMisaJ}{}% + \ifstrequal{#1}{\_set\_Misa\_K}{\sailRISCVfnSetMisaK}{}% + \ifstrequal{#1}{\_set\_Misa\_L}{\sailRISCVfnSetMisaL}{}% + \ifstrequal{#1}{\_set\_Misa\_M}{\sailRISCVfnSetMisaM}{}% + \ifstrequal{#1}{\_set\_Misa\_MXL}{\sailRISCVfnSetMisaMXL}{}% + \ifstrequal{#1}{\_set\_Misa\_N}{\sailRISCVfnSetMisaN}{}% + \ifstrequal{#1}{\_set\_Misa\_O}{\sailRISCVfnSetMisaO}{}% + \ifstrequal{#1}{\_set\_Misa\_P}{\sailRISCVfnSetMisaP}{}% + \ifstrequal{#1}{\_set\_Misa\_Q}{\sailRISCVfnSetMisaQ}{}% + \ifstrequal{#1}{\_set\_Misa\_R}{\sailRISCVfnSetMisaR}{}% + \ifstrequal{#1}{\_set\_Misa\_S}{\sailRISCVfnSetMisaS}{}% + \ifstrequal{#1}{\_set\_Misa\_T}{\sailRISCVfnSetMisaT}{}% + \ifstrequal{#1}{\_set\_Misa\_U}{\sailRISCVfnSetMisaU}{}% + \ifstrequal{#1}{\_set\_Misa\_V}{\sailRISCVfnSetMisaV}{}% + \ifstrequal{#1}{\_set\_Misa\_W}{\sailRISCVfnSetMisaW}{}% + \ifstrequal{#1}{\_set\_Misa\_X}{\sailRISCVfnSetMisaX}{}% + \ifstrequal{#1}{\_set\_Misa\_Y}{\sailRISCVfnSetMisaY}{}% + \ifstrequal{#1}{\_set\_Misa\_Z}{\sailRISCVfnSetMisaZ}{}% + \ifstrequal{#1}{\_set\_Misa\_bits}{\sailRISCVfnSetMisaBits}{}% + \ifstrequal{#1}{\_set\_Mstatus\_FS}{\sailRISCVfnSetMstatusFS}{}% + \ifstrequal{#1}{\_set\_Mstatus\_MIE}{\sailRISCVfnSetMstatusMIE}{}% + \ifstrequal{#1}{\_set\_Mstatus\_MPIE}{\sailRISCVfnSetMstatusMPIE}{}% + \ifstrequal{#1}{\_set\_Mstatus\_MPP}{\sailRISCVfnSetMstatusMPP}{}% + \ifstrequal{#1}{\_set\_Mstatus\_MPRV}{\sailRISCVfnSetMstatusMPRV}{}% + \ifstrequal{#1}{\_set\_Mstatus\_MXR}{\sailRISCVfnSetMstatusMXR}{}% + \ifstrequal{#1}{\_set\_Mstatus\_SD}{\sailRISCVfnSetMstatusSD}{}% + \ifstrequal{#1}{\_set\_Mstatus\_SIE}{\sailRISCVfnSetMstatusSIE}{}% + \ifstrequal{#1}{\_set\_Mstatus\_SPIE}{\sailRISCVfnSetMstatusSPIE}{}% + \ifstrequal{#1}{\_set\_Mstatus\_SPP}{\sailRISCVfnSetMstatusSPP}{}% + \ifstrequal{#1}{\_set\_Mstatus\_SUM}{\sailRISCVfnSetMstatusSUM}{}% + \ifstrequal{#1}{\_set\_Mstatus\_TSR}{\sailRISCVfnSetMstatusTSR}{}% + \ifstrequal{#1}{\_set\_Mstatus\_TVM}{\sailRISCVfnSetMstatusTVM}{}% + \ifstrequal{#1}{\_set\_Mstatus\_TW}{\sailRISCVfnSetMstatusTW}{}% + \ifstrequal{#1}{\_set\_Mstatus\_UIE}{\sailRISCVfnSetMstatusUIE}{}% + \ifstrequal{#1}{\_set\_Mstatus\_UPIE}{\sailRISCVfnSetMstatusUPIE}{}% + \ifstrequal{#1}{\_set\_Mstatus\_XS}{\sailRISCVfnSetMstatusXS}{}% + \ifstrequal{#1}{\_set\_Mstatus\_bits}{\sailRISCVfnSetMstatusBits}{}% + \ifstrequal{#1}{\_set\_Mtvec\_Base}{\sailRISCVfnSetMtvecBase}{}% + \ifstrequal{#1}{\_set\_Mtvec\_Mode}{\sailRISCVfnSetMtvecMode}{}% + \ifstrequal{#1}{\_set\_Mtvec\_bits}{\sailRISCVfnSetMtvecBits}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_A}{\sailRISCVfnSetPTEBitsA}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_D}{\sailRISCVfnSetPTEBitsD}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_G}{\sailRISCVfnSetPTEBitsG}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_R}{\sailRISCVfnSetPTEBitsR}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_U}{\sailRISCVfnSetPTEBitsU}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_V}{\sailRISCVfnSetPTEBitsV}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_W}{\sailRISCVfnSetPTEBitsW}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_X}{\sailRISCVfnSetPTEBitsX}{}% + \ifstrequal{#1}{\_set\_PTE\_Bits\_bits}{\sailRISCVfnSetPTEBitsBits}{}% + \ifstrequal{#1}{\_set\_Pmpcfg\_ent\_A}{\sailRISCVfnSetPmpcfgEntA}{}% + \ifstrequal{#1}{\_set\_Pmpcfg\_ent\_L}{\sailRISCVfnSetPmpcfgEntL}{}% + \ifstrequal{#1}{\_set\_Pmpcfg\_ent\_R}{\sailRISCVfnSetPmpcfgEntR}{}% + \ifstrequal{#1}{\_set\_Pmpcfg\_ent\_W}{\sailRISCVfnSetPmpcfgEntW}{}% + \ifstrequal{#1}{\_set\_Pmpcfg\_ent\_X}{\sailRISCVfnSetPmpcfgEntX}{}% + \ifstrequal{#1}{\_set\_Pmpcfg\_ent\_bits}{\sailRISCVfnSetPmpcfgEntBits}{}% + \ifstrequal{#1}{\_set\_SV32\_PTE\_BITS}{\sailRISCVfnSetSVThreeTwoPTEBITS}{}% + \ifstrequal{#1}{\_set\_SV32\_PTE\_PPNi}{\sailRISCVfnSetSVThreeTwoPTEPPNi}{}% + \ifstrequal{#1}{\_set\_SV32\_PTE\_RSW}{\sailRISCVfnSetSVThreeTwoPTERSW}{}% + \ifstrequal{#1}{\_set\_SV32\_PTE\_bits}{\sailRISCVfnSetSVThreeTwoPTEBits}{}% + \ifstrequal{#1}{\_set\_SV32\_Paddr\_PPNi}{\sailRISCVfnSetSVThreeTwoPaddrPPNi}{}% + \ifstrequal{#1}{\_set\_SV32\_Paddr\_PgOfs}{\sailRISCVfnSetSVThreeTwoPaddrPgOfs}{}% + \ifstrequal{#1}{\_set\_SV32\_Paddr\_bits}{\sailRISCVfnSetSVThreeTwoPaddrBits}{}% + \ifstrequal{#1}{\_set\_SV32\_Vaddr\_PgOfs}{\sailRISCVfnSetSVThreeTwoVaddrPgOfs}{}% + \ifstrequal{#1}{\_set\_SV32\_Vaddr\_VPNi}{\sailRISCVfnSetSVThreeTwoVaddrVPNi}{}% + \ifstrequal{#1}{\_set\_SV32\_Vaddr\_bits}{\sailRISCVfnSetSVThreeTwoVaddrBits}{}% + \ifstrequal{#1}{\_set\_SV39\_PTE\_BITS}{\sailRISCVfnSetSVThreeNinePTEBITS}{}% + \ifstrequal{#1}{\_set\_SV39\_PTE\_Ext}{\sailRISCVfnSetSVThreeNinePTEExt}{}% + \ifstrequal{#1}{\_set\_SV39\_PTE\_PPNi}{\sailRISCVfnSetSVThreeNinePTEPPNi}{}% + \ifstrequal{#1}{\_set\_SV39\_PTE\_RSW}{\sailRISCVfnSetSVThreeNinePTERSW}{}% + \ifstrequal{#1}{\_set\_SV39\_PTE\_bits}{\sailRISCVfnSetSVThreeNinePTEBits}{}% + \ifstrequal{#1}{\_set\_SV39\_Paddr\_PPNi}{\sailRISCVfnSetSVThreeNinePaddrPPNi}{}% + \ifstrequal{#1}{\_set\_SV39\_Paddr\_PgOfs}{\sailRISCVfnSetSVThreeNinePaddrPgOfs}{}% + \ifstrequal{#1}{\_set\_SV39\_Paddr\_bits}{\sailRISCVfnSetSVThreeNinePaddrBits}{}% + \ifstrequal{#1}{\_set\_SV39\_Vaddr\_PgOfs}{\sailRISCVfnSetSVThreeNineVaddrPgOfs}{}% + \ifstrequal{#1}{\_set\_SV39\_Vaddr\_VPNi}{\sailRISCVfnSetSVThreeNineVaddrVPNi}{}% + \ifstrequal{#1}{\_set\_SV39\_Vaddr\_bits}{\sailRISCVfnSetSVThreeNineVaddrBits}{}% + \ifstrequal{#1}{\_set\_SV48\_PTE\_BITS}{\sailRISCVfnSetSVFourEightPTEBITS}{}% + \ifstrequal{#1}{\_set\_SV48\_PTE\_Ext}{\sailRISCVfnSetSVFourEightPTEExt}{}% + \ifstrequal{#1}{\_set\_SV48\_PTE\_PPNi}{\sailRISCVfnSetSVFourEightPTEPPNi}{}% + \ifstrequal{#1}{\_set\_SV48\_PTE\_RSW}{\sailRISCVfnSetSVFourEightPTERSW}{}% + \ifstrequal{#1}{\_set\_SV48\_PTE\_bits}{\sailRISCVfnSetSVFourEightPTEBits}{}% + \ifstrequal{#1}{\_set\_SV48\_Paddr\_PPNi}{\sailRISCVfnSetSVFourEightPaddrPPNi}{}% + \ifstrequal{#1}{\_set\_SV48\_Paddr\_PgOfs}{\sailRISCVfnSetSVFourEightPaddrPgOfs}{}% + \ifstrequal{#1}{\_set\_SV48\_Paddr\_bits}{\sailRISCVfnSetSVFourEightPaddrBits}{}% + \ifstrequal{#1}{\_set\_SV48\_Vaddr\_PgOfs}{\sailRISCVfnSetSVFourEightVaddrPgOfs}{}% + \ifstrequal{#1}{\_set\_SV48\_Vaddr\_VPNi}{\sailRISCVfnSetSVFourEightVaddrVPNi}{}% + \ifstrequal{#1}{\_set\_SV48\_Vaddr\_bits}{\sailRISCVfnSetSVFourEightVaddrBits}{}% + \ifstrequal{#1}{\_set\_Satp32\_Asid}{\sailRISCVfnSetSatpThreeTwoAsid}{}% + \ifstrequal{#1}{\_set\_Satp32\_Mode}{\sailRISCVfnSetSatpThreeTwoMode}{}% + \ifstrequal{#1}{\_set\_Satp32\_PPN}{\sailRISCVfnSetSatpThreeTwoPPN}{}% + \ifstrequal{#1}{\_set\_Satp32\_bits}{\sailRISCVfnSetSatpThreeTwoBits}{}% + \ifstrequal{#1}{\_set\_Satp64\_Asid}{\sailRISCVfnSetSatpSixFourAsid}{}% + \ifstrequal{#1}{\_set\_Satp64\_Mode}{\sailRISCVfnSetSatpSixFourMode}{}% + \ifstrequal{#1}{\_set\_Satp64\_PPN}{\sailRISCVfnSetSatpSixFourPPN}{}% + \ifstrequal{#1}{\_set\_Satp64\_bits}{\sailRISCVfnSetSatpSixFourBits}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_Breakpoint}{\sailRISCVfnSetSedelegBreakpoint}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_Fetch\_Access\_Fault}{\sailRISCVfnSetSedelegFetchAccessFault}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_Fetch\_Addr\_Align}{\sailRISCVfnSetSedelegFetchAddrAlign}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_Illegal\_Instr}{\sailRISCVfnSetSedelegIllegalInstr}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_Load\_Access\_Fault}{\sailRISCVfnSetSedelegLoadAccessFault}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_Load\_Addr\_Align}{\sailRISCVfnSetSedelegLoadAddrAlign}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_SAMO\_Access\_Fault}{\sailRISCVfnSetSedelegSAMOAccessFault}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_SAMO\_Addr\_Align}{\sailRISCVfnSetSedelegSAMOAddrAlign}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_UEnvCall}{\sailRISCVfnSetSedelegUEnvCall}{}% + \ifstrequal{#1}{\_set\_Sedeleg\_bits}{\sailRISCVfnSetSedelegBits}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_SEI}{\sailRISCVfnSetSinterruptsSEI}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_SSI}{\sailRISCVfnSetSinterruptsSSI}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_STI}{\sailRISCVfnSetSinterruptsSTI}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_UEI}{\sailRISCVfnSetSinterruptsUEI}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_USI}{\sailRISCVfnSetSinterruptsUSI}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_UTI}{\sailRISCVfnSetSinterruptsUTI}{}% + \ifstrequal{#1}{\_set\_Sinterrupts\_bits}{\sailRISCVfnSetSinterruptsBits}{}% + \ifstrequal{#1}{\_set\_Sstatus\_FS}{\sailRISCVfnSetSstatusFS}{}% + \ifstrequal{#1}{\_set\_Sstatus\_MXR}{\sailRISCVfnSetSstatusMXR}{}% + \ifstrequal{#1}{\_set\_Sstatus\_SD}{\sailRISCVfnSetSstatusSD}{}% + \ifstrequal{#1}{\_set\_Sstatus\_SIE}{\sailRISCVfnSetSstatusSIE}{}% + \ifstrequal{#1}{\_set\_Sstatus\_SPIE}{\sailRISCVfnSetSstatusSPIE}{}% + \ifstrequal{#1}{\_set\_Sstatus\_SPP}{\sailRISCVfnSetSstatusSPP}{}% + \ifstrequal{#1}{\_set\_Sstatus\_SUM}{\sailRISCVfnSetSstatusSUM}{}% + \ifstrequal{#1}{\_set\_Sstatus\_UIE}{\sailRISCVfnSetSstatusUIE}{}% + \ifstrequal{#1}{\_set\_Sstatus\_UPIE}{\sailRISCVfnSetSstatusUPIE}{}% + \ifstrequal{#1}{\_set\_Sstatus\_XS}{\sailRISCVfnSetSstatusXS}{}% + \ifstrequal{#1}{\_set\_Sstatus\_bits}{\sailRISCVfnSetSstatusBits}{}% + \ifstrequal{#1}{\_set\_Uinterrupts\_UEI}{\sailRISCVfnSetUinterruptsUEI}{}% + \ifstrequal{#1}{\_set\_Uinterrupts\_USI}{\sailRISCVfnSetUinterruptsUSI}{}% + \ifstrequal{#1}{\_set\_Uinterrupts\_UTI}{\sailRISCVfnSetUinterruptsUTI}{}% + \ifstrequal{#1}{\_set\_Uinterrupts\_bits}{\sailRISCVfnSetUinterruptsBits}{}% + \ifstrequal{#1}{\_set\_Ustatus\_UIE}{\sailRISCVfnSetUstatusUIE}{}% + \ifstrequal{#1}{\_set\_Ustatus\_UPIE}{\sailRISCVfnSetUstatusUPIE}{}% + \ifstrequal{#1}{\_set\_Ustatus\_bits}{\sailRISCVfnSetUstatusBits}{}% + \ifstrequal{#1}{\_set\_ccsr\_bits}{\sailRISCVfnSetCcsrBits}{}% + \ifstrequal{#1}{\_set\_ccsr\_cap\_idx}{\sailRISCVfnSetCcsrCapIdx}{}% + \ifstrequal{#1}{\_set\_ccsr\_cause}{\sailRISCVfnSetCcsrCause}{}% + \ifstrequal{#1}{\_set\_ccsr\_d}{\sailRISCVfnSetCcsrD}{}% + \ifstrequal{#1}{\_set\_ccsr\_e}{\sailRISCVfnSetCcsrE}{}% + \ifstrequal{#1}{\_set\_htif\_cmd\_bits}{\sailRISCVfnSetHtifCmdBits}{}% + \ifstrequal{#1}{\_set\_htif\_cmd\_cmd}{\sailRISCVfnSetHtifCmdCmd}{}% + \ifstrequal{#1}{\_set\_htif\_cmd\_device}{\sailRISCVfnSetHtifCmdDevice}{}% + \ifstrequal{#1}{\_set\_htif\_cmd\_payload}{\sailRISCVfnSetHtifCmdPayload}{}% + \ifstrequal{#1}{\_update\_Counteren\_CY}{\sailRISCVfnUpdateCounterenCY}{}% + \ifstrequal{#1}{\_update\_Counteren\_HPM}{\sailRISCVfnUpdateCounterenHPM}{}% + \ifstrequal{#1}{\_update\_Counteren\_IR}{\sailRISCVfnUpdateCounterenIR}{}% + \ifstrequal{#1}{\_update\_Counteren\_TM}{\sailRISCVfnUpdateCounterenTM}{}% + \ifstrequal{#1}{\_update\_Counteren\_bits}{\sailRISCVfnUpdateCounterenBits}{}% + \ifstrequal{#1}{\_update\_Counterin\_CY}{\sailRISCVfnUpdateCounterinCY}{}% + \ifstrequal{#1}{\_update\_Counterin\_IR}{\sailRISCVfnUpdateCounterinIR}{}% + \ifstrequal{#1}{\_update\_Counterin\_bits}{\sailRISCVfnUpdateCounterinBits}{}% + \ifstrequal{#1}{\_update\_Ext\_PTE\_Bits\_CapRead}{\sailRISCVfnUpdateExtPTEBitsCapRead}{}% + \ifstrequal{#1}{\_update\_Ext\_PTE\_Bits\_CapWrite}{\sailRISCVfnUpdateExtPTEBitsCapWrite}{}% + \ifstrequal{#1}{\_update\_Ext\_PTE\_Bits\_bits}{\sailRISCVfnUpdateExtPTEBitsBits}{}% + \ifstrequal{#1}{\_update\_Fcsr\_FFLAGS}{\sailRISCVfnUpdateFcsrFFLAGS}{}% + \ifstrequal{#1}{\_update\_Fcsr\_FRM}{\sailRISCVfnUpdateFcsrFRM}{}% + \ifstrequal{#1}{\_update\_Fcsr\_bits}{\sailRISCVfnUpdateFcsrBits}{}% + \ifstrequal{#1}{\_update\_Mcause\_Cause}{\sailRISCVfnUpdateMcauseCause}{}% + \ifstrequal{#1}{\_update\_Mcause\_IsInterrupt}{\sailRISCVfnUpdateMcauseIsInterrupt}{}% + \ifstrequal{#1}{\_update\_Mcause\_bits}{\sailRISCVfnUpdateMcauseBits}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Breakpoint}{\sailRISCVfnUpdateMedelegBreakpoint}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Fetch\_Access\_Fault}{\sailRISCVfnUpdateMedelegFetchAccessFault}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Fetch\_Addr\_Align}{\sailRISCVfnUpdateMedelegFetchAddrAlign}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Fetch\_Page\_Fault}{\sailRISCVfnUpdateMedelegFetchPageFault}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Illegal\_Instr}{\sailRISCVfnUpdateMedelegIllegalInstr}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Load\_Access\_Fault}{\sailRISCVfnUpdateMedelegLoadAccessFault}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Load\_Addr\_Align}{\sailRISCVfnUpdateMedelegLoadAddrAlign}{}% + \ifstrequal{#1}{\_update\_Medeleg\_Load\_Page\_Fault}{\sailRISCVfnUpdateMedelegLoadPageFault}{}% + \ifstrequal{#1}{\_update\_Medeleg\_MEnvCall}{\sailRISCVfnUpdateMedelegMEnvCall}{}% + \ifstrequal{#1}{\_update\_Medeleg\_SAMO\_Access\_Fault}{\sailRISCVfnUpdateMedelegSAMOAccessFault}{}% + \ifstrequal{#1}{\_update\_Medeleg\_SAMO\_Addr\_Align}{\sailRISCVfnUpdateMedelegSAMOAddrAlign}{}% + \ifstrequal{#1}{\_update\_Medeleg\_SAMO\_Page\_Fault}{\sailRISCVfnUpdateMedelegSAMOPageFault}{}% + \ifstrequal{#1}{\_update\_Medeleg\_SEnvCall}{\sailRISCVfnUpdateMedelegSEnvCall}{}% + \ifstrequal{#1}{\_update\_Medeleg\_UEnvCall}{\sailRISCVfnUpdateMedelegUEnvCall}{}% + \ifstrequal{#1}{\_update\_Medeleg\_bits}{\sailRISCVfnUpdateMedelegBits}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_MEI}{\sailRISCVfnUpdateMinterruptsMEI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_MSI}{\sailRISCVfnUpdateMinterruptsMSI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_MTI}{\sailRISCVfnUpdateMinterruptsMTI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_SEI}{\sailRISCVfnUpdateMinterruptsSEI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_SSI}{\sailRISCVfnUpdateMinterruptsSSI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_STI}{\sailRISCVfnUpdateMinterruptsSTI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_UEI}{\sailRISCVfnUpdateMinterruptsUEI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_USI}{\sailRISCVfnUpdateMinterruptsUSI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_UTI}{\sailRISCVfnUpdateMinterruptsUTI}{}% + \ifstrequal{#1}{\_update\_Minterrupts\_bits}{\sailRISCVfnUpdateMinterruptsBits}{}% + \ifstrequal{#1}{\_update\_Misa\_A}{\sailRISCVfnUpdateMisaA}{}% + \ifstrequal{#1}{\_update\_Misa\_B}{\sailRISCVfnUpdateMisaB}{}% + \ifstrequal{#1}{\_update\_Misa\_C}{\sailRISCVfnUpdateMisaC}{}% + \ifstrequal{#1}{\_update\_Misa\_D}{\sailRISCVfnUpdateMisaD}{}% + \ifstrequal{#1}{\_update\_Misa\_E}{\sailRISCVfnUpdateMisaE}{}% + \ifstrequal{#1}{\_update\_Misa\_F}{\sailRISCVfnUpdateMisaF}{}% + \ifstrequal{#1}{\_update\_Misa\_G}{\sailRISCVfnUpdateMisaG}{}% + \ifstrequal{#1}{\_update\_Misa\_H}{\sailRISCVfnUpdateMisaH}{}% + \ifstrequal{#1}{\_update\_Misa\_I}{\sailRISCVfnUpdateMisaI}{}% + \ifstrequal{#1}{\_update\_Misa\_J}{\sailRISCVfnUpdateMisaJ}{}% + \ifstrequal{#1}{\_update\_Misa\_K}{\sailRISCVfnUpdateMisaK}{}% + \ifstrequal{#1}{\_update\_Misa\_L}{\sailRISCVfnUpdateMisaL}{}% + \ifstrequal{#1}{\_update\_Misa\_M}{\sailRISCVfnUpdateMisaM}{}% + \ifstrequal{#1}{\_update\_Misa\_MXL}{\sailRISCVfnUpdateMisaMXL}{}% + \ifstrequal{#1}{\_update\_Misa\_N}{\sailRISCVfnUpdateMisaN}{}% + \ifstrequal{#1}{\_update\_Misa\_O}{\sailRISCVfnUpdateMisaO}{}% + \ifstrequal{#1}{\_update\_Misa\_P}{\sailRISCVfnUpdateMisaP}{}% + \ifstrequal{#1}{\_update\_Misa\_Q}{\sailRISCVfnUpdateMisaQ}{}% + \ifstrequal{#1}{\_update\_Misa\_R}{\sailRISCVfnUpdateMisaR}{}% + \ifstrequal{#1}{\_update\_Misa\_S}{\sailRISCVfnUpdateMisaS}{}% + \ifstrequal{#1}{\_update\_Misa\_T}{\sailRISCVfnUpdateMisaT}{}% + \ifstrequal{#1}{\_update\_Misa\_U}{\sailRISCVfnUpdateMisaU}{}% + \ifstrequal{#1}{\_update\_Misa\_V}{\sailRISCVfnUpdateMisaV}{}% + \ifstrequal{#1}{\_update\_Misa\_W}{\sailRISCVfnUpdateMisaW}{}% + \ifstrequal{#1}{\_update\_Misa\_X}{\sailRISCVfnUpdateMisaX}{}% + \ifstrequal{#1}{\_update\_Misa\_Y}{\sailRISCVfnUpdateMisaY}{}% + \ifstrequal{#1}{\_update\_Misa\_Z}{\sailRISCVfnUpdateMisaZ}{}% + \ifstrequal{#1}{\_update\_Misa\_bits}{\sailRISCVfnUpdateMisaBits}{}% + \ifstrequal{#1}{\_update\_Mstatus\_FS}{\sailRISCVfnUpdateMstatusFS}{}% + \ifstrequal{#1}{\_update\_Mstatus\_MIE}{\sailRISCVfnUpdateMstatusMIE}{}% + \ifstrequal{#1}{\_update\_Mstatus\_MPIE}{\sailRISCVfnUpdateMstatusMPIE}{}% + \ifstrequal{#1}{\_update\_Mstatus\_MPP}{\sailRISCVfnUpdateMstatusMPP}{}% + \ifstrequal{#1}{\_update\_Mstatus\_MPRV}{\sailRISCVfnUpdateMstatusMPRV}{}% + \ifstrequal{#1}{\_update\_Mstatus\_MXR}{\sailRISCVfnUpdateMstatusMXR}{}% + \ifstrequal{#1}{\_update\_Mstatus\_SD}{\sailRISCVfnUpdateMstatusSD}{}% + \ifstrequal{#1}{\_update\_Mstatus\_SIE}{\sailRISCVfnUpdateMstatusSIE}{}% + \ifstrequal{#1}{\_update\_Mstatus\_SPIE}{\sailRISCVfnUpdateMstatusSPIE}{}% + \ifstrequal{#1}{\_update\_Mstatus\_SPP}{\sailRISCVfnUpdateMstatusSPP}{}% + \ifstrequal{#1}{\_update\_Mstatus\_SUM}{\sailRISCVfnUpdateMstatusSUM}{}% + \ifstrequal{#1}{\_update\_Mstatus\_TSR}{\sailRISCVfnUpdateMstatusTSR}{}% + \ifstrequal{#1}{\_update\_Mstatus\_TVM}{\sailRISCVfnUpdateMstatusTVM}{}% + \ifstrequal{#1}{\_update\_Mstatus\_TW}{\sailRISCVfnUpdateMstatusTW}{}% + \ifstrequal{#1}{\_update\_Mstatus\_UIE}{\sailRISCVfnUpdateMstatusUIE}{}% + \ifstrequal{#1}{\_update\_Mstatus\_UPIE}{\sailRISCVfnUpdateMstatusUPIE}{}% + \ifstrequal{#1}{\_update\_Mstatus\_XS}{\sailRISCVfnUpdateMstatusXS}{}% + \ifstrequal{#1}{\_update\_Mstatus\_bits}{\sailRISCVfnUpdateMstatusBits}{}% + \ifstrequal{#1}{\_update\_Mtvec\_Base}{\sailRISCVfnUpdateMtvecBase}{}% + \ifstrequal{#1}{\_update\_Mtvec\_Mode}{\sailRISCVfnUpdateMtvecMode}{}% + \ifstrequal{#1}{\_update\_Mtvec\_bits}{\sailRISCVfnUpdateMtvecBits}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_A}{\sailRISCVfnUpdatePTEBitsA}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_D}{\sailRISCVfnUpdatePTEBitsD}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_G}{\sailRISCVfnUpdatePTEBitsG}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_R}{\sailRISCVfnUpdatePTEBitsR}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_U}{\sailRISCVfnUpdatePTEBitsU}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_V}{\sailRISCVfnUpdatePTEBitsV}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_W}{\sailRISCVfnUpdatePTEBitsW}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_X}{\sailRISCVfnUpdatePTEBitsX}{}% + \ifstrequal{#1}{\_update\_PTE\_Bits\_bits}{\sailRISCVfnUpdatePTEBitsBits}{}% + \ifstrequal{#1}{\_update\_Pmpcfg\_ent\_A}{\sailRISCVfnUpdatePmpcfgEntA}{}% + \ifstrequal{#1}{\_update\_Pmpcfg\_ent\_L}{\sailRISCVfnUpdatePmpcfgEntL}{}% + \ifstrequal{#1}{\_update\_Pmpcfg\_ent\_R}{\sailRISCVfnUpdatePmpcfgEntR}{}% + \ifstrequal{#1}{\_update\_Pmpcfg\_ent\_W}{\sailRISCVfnUpdatePmpcfgEntW}{}% + \ifstrequal{#1}{\_update\_Pmpcfg\_ent\_X}{\sailRISCVfnUpdatePmpcfgEntX}{}% + \ifstrequal{#1}{\_update\_Pmpcfg\_ent\_bits}{\sailRISCVfnUpdatePmpcfgEntBits}{}% + \ifstrequal{#1}{\_update\_SV32\_PTE\_BITS}{\sailRISCVfnUpdateSVThreeTwoPTEBITS}{}% + \ifstrequal{#1}{\_update\_SV32\_PTE\_PPNi}{\sailRISCVfnUpdateSVThreeTwoPTEPPNi}{}% + \ifstrequal{#1}{\_update\_SV32\_PTE\_RSW}{\sailRISCVfnUpdateSVThreeTwoPTERSW}{}% + \ifstrequal{#1}{\_update\_SV32\_PTE\_bits}{\sailRISCVfnUpdateSVThreeTwoPTEBits}{}% + \ifstrequal{#1}{\_update\_SV32\_Paddr\_PPNi}{\sailRISCVfnUpdateSVThreeTwoPaddrPPNi}{}% + \ifstrequal{#1}{\_update\_SV32\_Paddr\_PgOfs}{\sailRISCVfnUpdateSVThreeTwoPaddrPgOfs}{}% + \ifstrequal{#1}{\_update\_SV32\_Paddr\_bits}{\sailRISCVfnUpdateSVThreeTwoPaddrBits}{}% + \ifstrequal{#1}{\_update\_SV32\_Vaddr\_PgOfs}{\sailRISCVfnUpdateSVThreeTwoVaddrPgOfs}{}% + \ifstrequal{#1}{\_update\_SV32\_Vaddr\_VPNi}{\sailRISCVfnUpdateSVThreeTwoVaddrVPNi}{}% + \ifstrequal{#1}{\_update\_SV32\_Vaddr\_bits}{\sailRISCVfnUpdateSVThreeTwoVaddrBits}{}% + \ifstrequal{#1}{\_update\_SV39\_PTE\_BITS}{\sailRISCVfnUpdateSVThreeNinePTEBITS}{}% + \ifstrequal{#1}{\_update\_SV39\_PTE\_Ext}{\sailRISCVfnUpdateSVThreeNinePTEExt}{}% + \ifstrequal{#1}{\_update\_SV39\_PTE\_PPNi}{\sailRISCVfnUpdateSVThreeNinePTEPPNi}{}% + \ifstrequal{#1}{\_update\_SV39\_PTE\_RSW}{\sailRISCVfnUpdateSVThreeNinePTERSW}{}% + \ifstrequal{#1}{\_update\_SV39\_PTE\_bits}{\sailRISCVfnUpdateSVThreeNinePTEBits}{}% + \ifstrequal{#1}{\_update\_SV39\_Paddr\_PPNi}{\sailRISCVfnUpdateSVThreeNinePaddrPPNi}{}% + \ifstrequal{#1}{\_update\_SV39\_Paddr\_PgOfs}{\sailRISCVfnUpdateSVThreeNinePaddrPgOfs}{}% + \ifstrequal{#1}{\_update\_SV39\_Paddr\_bits}{\sailRISCVfnUpdateSVThreeNinePaddrBits}{}% + \ifstrequal{#1}{\_update\_SV39\_Vaddr\_PgOfs}{\sailRISCVfnUpdateSVThreeNineVaddrPgOfs}{}% + \ifstrequal{#1}{\_update\_SV39\_Vaddr\_VPNi}{\sailRISCVfnUpdateSVThreeNineVaddrVPNi}{}% + \ifstrequal{#1}{\_update\_SV39\_Vaddr\_bits}{\sailRISCVfnUpdateSVThreeNineVaddrBits}{}% + \ifstrequal{#1}{\_update\_SV48\_PTE\_BITS}{\sailRISCVfnUpdateSVFourEightPTEBITS}{}% + \ifstrequal{#1}{\_update\_SV48\_PTE\_Ext}{\sailRISCVfnUpdateSVFourEightPTEExt}{}% + \ifstrequal{#1}{\_update\_SV48\_PTE\_PPNi}{\sailRISCVfnUpdateSVFourEightPTEPPNi}{}% + \ifstrequal{#1}{\_update\_SV48\_PTE\_RSW}{\sailRISCVfnUpdateSVFourEightPTERSW}{}% + \ifstrequal{#1}{\_update\_SV48\_PTE\_bits}{\sailRISCVfnUpdateSVFourEightPTEBits}{}% + \ifstrequal{#1}{\_update\_SV48\_Paddr\_PPNi}{\sailRISCVfnUpdateSVFourEightPaddrPPNi}{}% + \ifstrequal{#1}{\_update\_SV48\_Paddr\_PgOfs}{\sailRISCVfnUpdateSVFourEightPaddrPgOfs}{}% + \ifstrequal{#1}{\_update\_SV48\_Paddr\_bits}{\sailRISCVfnUpdateSVFourEightPaddrBits}{}% + \ifstrequal{#1}{\_update\_SV48\_Vaddr\_PgOfs}{\sailRISCVfnUpdateSVFourEightVaddrPgOfs}{}% + \ifstrequal{#1}{\_update\_SV48\_Vaddr\_VPNi}{\sailRISCVfnUpdateSVFourEightVaddrVPNi}{}% + \ifstrequal{#1}{\_update\_SV48\_Vaddr\_bits}{\sailRISCVfnUpdateSVFourEightVaddrBits}{}% + \ifstrequal{#1}{\_update\_Satp32\_Asid}{\sailRISCVfnUpdateSatpThreeTwoAsid}{}% + \ifstrequal{#1}{\_update\_Satp32\_Mode}{\sailRISCVfnUpdateSatpThreeTwoMode}{}% + \ifstrequal{#1}{\_update\_Satp32\_PPN}{\sailRISCVfnUpdateSatpThreeTwoPPN}{}% + \ifstrequal{#1}{\_update\_Satp32\_bits}{\sailRISCVfnUpdateSatpThreeTwoBits}{}% + \ifstrequal{#1}{\_update\_Satp64\_Asid}{\sailRISCVfnUpdateSatpSixFourAsid}{}% + \ifstrequal{#1}{\_update\_Satp64\_Mode}{\sailRISCVfnUpdateSatpSixFourMode}{}% + \ifstrequal{#1}{\_update\_Satp64\_PPN}{\sailRISCVfnUpdateSatpSixFourPPN}{}% + \ifstrequal{#1}{\_update\_Satp64\_bits}{\sailRISCVfnUpdateSatpSixFourBits}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_Breakpoint}{\sailRISCVfnUpdateSedelegBreakpoint}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_Fetch\_Access\_Fault}{\sailRISCVfnUpdateSedelegFetchAccessFault}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_Fetch\_Addr\_Align}{\sailRISCVfnUpdateSedelegFetchAddrAlign}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_Illegal\_Instr}{\sailRISCVfnUpdateSedelegIllegalInstr}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_Load\_Access\_Fault}{\sailRISCVfnUpdateSedelegLoadAccessFault}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_Load\_Addr\_Align}{\sailRISCVfnUpdateSedelegLoadAddrAlign}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_SAMO\_Access\_Fault}{\sailRISCVfnUpdateSedelegSAMOAccessFault}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_SAMO\_Addr\_Align}{\sailRISCVfnUpdateSedelegSAMOAddrAlign}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_UEnvCall}{\sailRISCVfnUpdateSedelegUEnvCall}{}% + \ifstrequal{#1}{\_update\_Sedeleg\_bits}{\sailRISCVfnUpdateSedelegBits}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_SEI}{\sailRISCVfnUpdateSinterruptsSEI}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_SSI}{\sailRISCVfnUpdateSinterruptsSSI}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_STI}{\sailRISCVfnUpdateSinterruptsSTI}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_UEI}{\sailRISCVfnUpdateSinterruptsUEI}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_USI}{\sailRISCVfnUpdateSinterruptsUSI}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_UTI}{\sailRISCVfnUpdateSinterruptsUTI}{}% + \ifstrequal{#1}{\_update\_Sinterrupts\_bits}{\sailRISCVfnUpdateSinterruptsBits}{}% + \ifstrequal{#1}{\_update\_Sstatus\_FS}{\sailRISCVfnUpdateSstatusFS}{}% + \ifstrequal{#1}{\_update\_Sstatus\_MXR}{\sailRISCVfnUpdateSstatusMXR}{}% + \ifstrequal{#1}{\_update\_Sstatus\_SD}{\sailRISCVfnUpdateSstatusSD}{}% + \ifstrequal{#1}{\_update\_Sstatus\_SIE}{\sailRISCVfnUpdateSstatusSIE}{}% + \ifstrequal{#1}{\_update\_Sstatus\_SPIE}{\sailRISCVfnUpdateSstatusSPIE}{}% + \ifstrequal{#1}{\_update\_Sstatus\_SPP}{\sailRISCVfnUpdateSstatusSPP}{}% + \ifstrequal{#1}{\_update\_Sstatus\_SUM}{\sailRISCVfnUpdateSstatusSUM}{}% + \ifstrequal{#1}{\_update\_Sstatus\_UIE}{\sailRISCVfnUpdateSstatusUIE}{}% + \ifstrequal{#1}{\_update\_Sstatus\_UPIE}{\sailRISCVfnUpdateSstatusUPIE}{}% + \ifstrequal{#1}{\_update\_Sstatus\_XS}{\sailRISCVfnUpdateSstatusXS}{}% + \ifstrequal{#1}{\_update\_Sstatus\_bits}{\sailRISCVfnUpdateSstatusBits}{}% + \ifstrequal{#1}{\_update\_Uinterrupts\_UEI}{\sailRISCVfnUpdateUinterruptsUEI}{}% + \ifstrequal{#1}{\_update\_Uinterrupts\_USI}{\sailRISCVfnUpdateUinterruptsUSI}{}% + \ifstrequal{#1}{\_update\_Uinterrupts\_UTI}{\sailRISCVfnUpdateUinterruptsUTI}{}% + \ifstrequal{#1}{\_update\_Uinterrupts\_bits}{\sailRISCVfnUpdateUinterruptsBits}{}% + \ifstrequal{#1}{\_update\_Ustatus\_UIE}{\sailRISCVfnUpdateUstatusUIE}{}% + \ifstrequal{#1}{\_update\_Ustatus\_UPIE}{\sailRISCVfnUpdateUstatusUPIE}{}% + \ifstrequal{#1}{\_update\_Ustatus\_bits}{\sailRISCVfnUpdateUstatusBits}{}% + \ifstrequal{#1}{\_update\_ccsr\_bits}{\sailRISCVfnUpdateCcsrBits}{}% + \ifstrequal{#1}{\_update\_ccsr\_cap\_idx}{\sailRISCVfnUpdateCcsrCapIdx}{}% + \ifstrequal{#1}{\_update\_ccsr\_cause}{\sailRISCVfnUpdateCcsrCause}{}% + \ifstrequal{#1}{\_update\_ccsr\_d}{\sailRISCVfnUpdateCcsrD}{}% + \ifstrequal{#1}{\_update\_ccsr\_e}{\sailRISCVfnUpdateCcsrE}{}% + \ifstrequal{#1}{\_update\_htif\_cmd\_bits}{\sailRISCVfnUpdateHtifCmdBits}{}% + \ifstrequal{#1}{\_update\_htif\_cmd\_cmd}{\sailRISCVfnUpdateHtifCmdCmd}{}% + \ifstrequal{#1}{\_update\_htif\_cmd\_device}{\sailRISCVfnUpdateHtifCmdDevice}{}% + \ifstrequal{#1}{\_update\_htif\_cmd\_payload}{\sailRISCVfnUpdateHtifCmdPayload}{}% + \ifstrequal{#1}{a64\_barrier\_domain\_of\_num}{\sailRISCVfnaSixFourBarrierDomainOfNum}{}% + \ifstrequal{#1}{a64\_barrier\_type\_of\_num}{\sailRISCVfnaSixFourBarrierTypeOfNum}{}% + \ifstrequal{#1}{accessType\_to\_str}{\sailRISCVfnaccessTypeToStr}{}% + \ifstrequal{#1}{accrue\_fflags}{\sailRISCVfnaccrueFflags}{}% + \ifstrequal{#1}{add\_to\_TLB39}{\sailRISCVfnaddToTLBThreeNine}{}% + \ifstrequal{#1}{add\_to\_TLB48}{\sailRISCVfnaddToTLBFourEight}{}% + \ifstrequal{#1}{addr\_to\_tag\_addr}{\sailRISCVfnaddrToTagAddr}{}% + \ifstrequal{#1}{amoop\_of\_num}{\sailRISCVfnamoopOfNum}{}% + \ifstrequal{#1}{aqrl\_str}{\sailRISCVfnaqrlStr}{}% + \ifstrequal{#1}{arch\_to\_bits}{\sailRISCVfnarchToBits}{}% + \ifstrequal{#1}{architecture}{\sailRISCVfnarchitecture}{}% + \ifstrequal{#1}{bit\_to\_bool}{\sailRISCVfnbitToBool}{}% + \ifstrequal{#1}{bool\_to\_bit}{\sailRISCVfnboolToBit}{}% + \ifstrequal{#1}{bool\_to\_bits}{\sailRISCVfnboolToBits}{}% + \ifstrequal{#1}{bop\_of\_num}{\sailRISCVfnbopOfNum}{}% + \ifstrequal{#1}{cache\_op\_kind\_of\_num}{\sailRISCVfncacheOpKindOfNum}{}% + \ifstrequal{#1}{canonical\_NaN\_D}{\sailRISCVfncanonicalNaND}{}% + \ifstrequal{#1}{canonical\_NaN\_S}{\sailRISCVfncanonicalNaNS}{}% + \ifstrequal{#1}{capBitsToCapability}{\sailRISCVfncapBitsToCapability}{}% + \ifstrequal{#1}{capBoundsEqual}{\sailRISCVfncapBoundsEqual}{}% + \ifstrequal{#1}{capToBits}{\sailRISCVfncapToBits}{}% + \ifstrequal{#1}{capToMemBits}{\sailRISCVfncapToMemBits}{}% + \ifstrequal{#1}{capToString}{\sailRISCVfncapToString}{}% + \ifstrequal{#1}{cap\_reg\_name\_abi}{\sailRISCVfncapRegNameAbi}{}% + \ifstrequal{#1}{checkPTEPermission}{\sailRISCVfncheckPTEPermission}{}% + \ifstrequal{#1}{check\_CSR}{\sailRISCVfncheckCSR}{}% + \ifstrequal{#1}{check\_CSR\_access}{\sailRISCVfncheckCSRAccess}{}% + \ifstrequal{#1}{check\_Counteren}{\sailRISCVfncheckCounteren}{}% + \ifstrequal{#1}{check\_TVM\_SATP}{\sailRISCVfncheckTVMSATP}{}% + \ifstrequal{#1}{check\_misaligned}{\sailRISCVfncheckMisaligned}{}% + \ifstrequal{#1}{check\_res\_misaligned}{\sailRISCVfncheckResMisaligned}{}% + \ifstrequal{#1}{checked\_mem\_read}{\sailRISCVfncheckedMemRead}{}% + \ifstrequal{#1}{checked\_mem\_write}{\sailRISCVfncheckedMemWrite}{}% + \ifstrequal{#1}{clint\_dispatch}{\sailRISCVfnclintDispatch}{}% + \ifstrequal{#1}{clint\_load}{\sailRISCVfnclintLoad}{}% + \ifstrequal{#1}{clint\_store}{\sailRISCVfnclintStore}{}% + \ifstrequal{#1}{concat\_str\_bits}{\sailRISCVfnconcatStrBits}{}% + \ifstrequal{#1}{concat\_str\_dec}{\sailRISCVfnconcatStrDec}{}% + \ifstrequal{#1}{creg2reg\_idx}{\sailRISCVfncregTworegIdx}{}% + \ifstrequal{#1}{csrAccess}{\sailRISCVfncsrAccess}{}% + \ifstrequal{#1}{csrPriv}{\sailRISCVfncsrPriv}{}% + \ifstrequal{#1}{csr\_name}{\sailRISCVfncsrName}{}% + \ifstrequal{#1}{csrop\_of\_num}{\sailRISCVfncsropOfNum}{}% + \ifstrequal{#1}{curAsid32}{\sailRISCVfncurAsidThreeTwo}{}% + \ifstrequal{#1}{curAsid64}{\sailRISCVfncurAsidSixFour}{}% + \ifstrequal{#1}{curPTB32}{\sailRISCVfncurPTBThreeTwo}{}% + \ifstrequal{#1}{curPTB64}{\sailRISCVfncurPTBSixFour}{}% + \ifstrequal{#1}{cur\_Architecture}{\sailRISCVfncurArchitecture}{}% + \ifstrequal{#1}{decode}{\sailRISCVfndecode}{}% + \ifstrequal{#1}{decodeCompressed}{\sailRISCVfndecodeCompressed}{}% + \ifstrequal{#1}{def\_spc\_backwards}{\sailRISCVfndefSpcBackwards}{}% + \ifstrequal{#1}{def\_spc\_forwards}{\sailRISCVfndefSpcForwards}{}% + \ifstrequal{#1}{def\_spc\_matches\_prefix}{\sailRISCVfndefSpcMatchesPrefix}{}% + \ifstrequal{#1}{dirty\_fd\_context}{\sailRISCVfndirtyFdContext}{}% + \ifstrequal{#1}{dispatchInterrupt}{\sailRISCVfndispatchInterrupt}{}% + \ifstrequal{#1}{dzFlag}{\sailRISCVfndzzFlag}{}% + \ifstrequal{#1}{effectivePrivilege}{\sailRISCVfneffectivePrivilege}{}% + \ifstrequal{#1}{eq\_unit}{\sailRISCVfneqUnit}{}% + \ifstrequal{#1}{exceptionType\_to\_bits}{\sailRISCVfnexceptionTypeToBits}{}% + \ifstrequal{#1}{exceptionType\_to\_str}{\sailRISCVfnexceptionTypeToStr}{}% + \ifstrequal{#1}{exception\_delegatee}{\sailRISCVfnexceptionDelegatee}{}% + \ifstrequal{#1}{exception\_handler}{\sailRISCVfnexceptionHandler}{}% + \ifstrequal{#1}{extStatus\_of\_bits}{\sailRISCVfnextStatusOfBits}{}% + \ifstrequal{#1}{extStatus\_to\_bits}{\sailRISCVfnextStatusToBits}{}% + \ifstrequal{#1}{ext\_access\_type\_of\_num}{\sailRISCVfnextAccessTypeOfNum}{}% + \ifstrequal{#1}{ext\_check\_CSR}{\sailRISCVfnextCheckCSR}{}% + \ifstrequal{#1}{ext\_check\_CSR\_fail}{\sailRISCVfnextCheckCSRFail}{}% + \ifstrequal{#1}{ext\_check\_xret\_priv}{\sailRISCVfnextCheckXretPriv}{}% + \ifstrequal{#1}{ext\_control\_check\_addr}{\sailRISCVfnextControlCheckAddr}{}% + \ifstrequal{#1}{ext\_control\_check\_pc}{\sailRISCVfnextControlCheckPc}{}% + \ifstrequal{#1}{ext\_data\_get\_addr}{\sailRISCVfnextDataGetAddr}{}% + \ifstrequal{#1}{ext\_exc\_type\_of\_num}{\sailRISCVfnextExcTypeOfNum}{}% + \ifstrequal{#1}{ext\_exc\_type\_to\_bits}{\sailRISCVfnextExcTypeToBits}{}% + \ifstrequal{#1}{ext\_exc\_type\_to\_str}{\sailRISCVfnextExcTypeToStr}{}% + \ifstrequal{#1}{ext\_fail\_xret\_priv}{\sailRISCVfnextFailXretPriv}{}% + \ifstrequal{#1}{ext\_fetch\_check\_pc}{\sailRISCVfnextFetchCheckPc}{}% + \ifstrequal{#1}{ext\_fetch\_hook}{\sailRISCVfnextFetchHook}{}% + \ifstrequal{#1}{ext\_get\_ptw\_error}{\sailRISCVfnextGetPtwError}{}% + \ifstrequal{#1}{ext\_handle\_control\_check\_error}{\sailRISCVfnextHandleControlCheckError}{}% + \ifstrequal{#1}{ext\_handle\_data\_check\_error}{\sailRISCVfnextHandleDataCheckError}{}% + \ifstrequal{#1}{ext\_handle\_fetch\_check\_error}{\sailRISCVfnextHandleFetchCheckError}{}% + \ifstrequal{#1}{ext\_init}{\sailRISCVfnextInit}{}% + \ifstrequal{#1}{ext\_init\_regs}{\sailRISCVfnextInitRegs}{}% + \ifstrequal{#1}{ext\_post\_decode\_hook}{\sailRISCVfnextPostDecodeHook}{}% + \ifstrequal{#1}{ext\_post\_step\_hook}{\sailRISCVfnextPostStepHook}{}% + \ifstrequal{#1}{ext\_pre\_step\_hook}{\sailRISCVfnextPreStepHook}{}% + \ifstrequal{#1}{ext\_ptw\_error\_of\_num}{\sailRISCVfnextPtwErrorOfNum}{}% + \ifstrequal{#1}{ext\_ptw\_fail\_of\_num}{\sailRISCVfnextPtwFailOfNum}{}% + \ifstrequal{#1}{ext\_ptw\_lc\_join}{\sailRISCVfnextPtwLcJoin}{}% + \ifstrequal{#1}{ext\_ptw\_lc\_of\_num}{\sailRISCVfnextPtwLcOfNum}{}% + \ifstrequal{#1}{ext\_ptw\_sc\_join}{\sailRISCVfnextPtwScJoin}{}% + \ifstrequal{#1}{ext\_ptw\_sc\_of\_num}{\sailRISCVfnextPtwScOfNum}{}% + \ifstrequal{#1}{ext\_rvfi\_init}{\sailRISCVfnextRvfiInit}{}% + \ifstrequal{#1}{ext\_veto\_disable\_C}{\sailRISCVfnextVetoDisableC}{}% + \ifstrequal{#1}{ext\_write\_fcsr}{\sailRISCVfnextWriteFcsr}{}% + \ifstrequal{#1}{extend\_value}{\sailRISCVfnextendValue}{}% + \ifstrequal{#1}{f\_bin\_op\_D\_of\_num}{\sailRISCVfnfBinOpDOfNum}{}% + \ifstrequal{#1}{f\_bin\_op\_S\_of\_num}{\sailRISCVfnfBinOpSOfNum}{}% + \ifstrequal{#1}{f\_bin\_rm\_op\_D\_of\_num}{\sailRISCVfnfBinRmOpDOfNum}{}% + \ifstrequal{#1}{f\_bin\_rm\_op\_S\_of\_num}{\sailRISCVfnfBinRmOpSOfNum}{}% + \ifstrequal{#1}{f\_is\_NaN\_D}{\sailRISCVfnfIsNaND}{}% + \ifstrequal{#1}{f\_is\_NaN\_S}{\sailRISCVfnfIsNaNS}{}% + \ifstrequal{#1}{f\_is\_QNaN\_D}{\sailRISCVfnfIsQNaND}{}% + \ifstrequal{#1}{f\_is\_QNaN\_S}{\sailRISCVfnfIsQNaNS}{}% + \ifstrequal{#1}{f\_is\_SNaN\_D}{\sailRISCVfnfIsSNaND}{}% + \ifstrequal{#1}{f\_is\_SNaN\_S}{\sailRISCVfnfIsSNaNS}{}% + \ifstrequal{#1}{f\_is\_neg\_inf\_D}{\sailRISCVfnfIsNegInfD}{}% + \ifstrequal{#1}{f\_is\_neg\_inf\_S}{\sailRISCVfnfIsNegInfS}{}% + \ifstrequal{#1}{f\_is\_neg\_norm\_D}{\sailRISCVfnfIsNegNormD}{}% + \ifstrequal{#1}{f\_is\_neg\_norm\_S}{\sailRISCVfnfIsNegNormS}{}% + \ifstrequal{#1}{f\_is\_neg\_subnorm\_D}{\sailRISCVfnfIsNegSubnormD}{}% + \ifstrequal{#1}{f\_is\_neg\_subnorm\_S}{\sailRISCVfnfIsNegSubnormS}{}% + \ifstrequal{#1}{f\_is\_neg\_zero\_D}{\sailRISCVfnfIsNegZeroD}{}% + \ifstrequal{#1}{f\_is\_neg\_zero\_S}{\sailRISCVfnfIsNegZeroS}{}% + \ifstrequal{#1}{f\_is\_pos\_inf\_D}{\sailRISCVfnfIsPosInfD}{}% + \ifstrequal{#1}{f\_is\_pos\_inf\_S}{\sailRISCVfnfIsPosInfS}{}% + \ifstrequal{#1}{f\_is\_pos\_norm\_D}{\sailRISCVfnfIsPosNormD}{}% + \ifstrequal{#1}{f\_is\_pos\_norm\_S}{\sailRISCVfnfIsPosNormS}{}% + \ifstrequal{#1}{f\_is\_pos\_subnorm\_D}{\sailRISCVfnfIsPosSubnormD}{}% + \ifstrequal{#1}{f\_is\_pos\_subnorm\_S}{\sailRISCVfnfIsPosSubnormS}{}% + \ifstrequal{#1}{f\_is\_pos\_zero\_D}{\sailRISCVfnfIsPosZeroD}{}% + \ifstrequal{#1}{f\_is\_pos\_zero\_S}{\sailRISCVfnfIsPosZeroS}{}% + \ifstrequal{#1}{f\_madd\_op\_D\_of\_num}{\sailRISCVfnfMaddOpDOfNum}{}% + \ifstrequal{#1}{f\_madd\_op\_S\_of\_num}{\sailRISCVfnfMaddOpSOfNum}{}% + \ifstrequal{#1}{f\_un\_op\_D\_of\_num}{\sailRISCVfnfUnOpDOfNum}{}% + \ifstrequal{#1}{f\_un\_op\_S\_of\_num}{\sailRISCVfnfUnOpSOfNum}{}% + \ifstrequal{#1}{f\_un\_rm\_op\_D\_of\_num}{\sailRISCVfnfUnRmOpDOfNum}{}% + \ifstrequal{#1}{f\_un\_rm\_op\_S\_of\_num}{\sailRISCVfnfUnRmOpSOfNum}{}% + \ifstrequal{#1}{fastRepCheck}{\sailRISCVfnfastRepCheck}{}% + \ifstrequal{#1}{fdiv\_int}{\sailRISCVfnfdivInt}{}% + \ifstrequal{#1}{feq\_quiet\_D}{\sailRISCVfnfeqQuietD}{}% + \ifstrequal{#1}{feq\_quiet\_S}{\sailRISCVfnfeqQuietS}{}% + \ifstrequal{#1}{fetch}{\sailRISCVfnfetch}{}% + \ifstrequal{#1}{findPendingInterrupt}{\sailRISCVfnfindPendingInterrupt}{}% + \ifstrequal{#1}{fle\_D}{\sailRISCVfnfleD}{}% + \ifstrequal{#1}{fle\_S}{\sailRISCVfnfleS}{}% + \ifstrequal{#1}{flt\_D}{\sailRISCVfnfltD}{}% + \ifstrequal{#1}{flt\_S}{\sailRISCVfnfltS}{}% + \ifstrequal{#1}{flush\_TLB}{\sailRISCVfnflushTLB}{}% + \ifstrequal{#1}{flush\_TLB39}{\sailRISCVfnflushTLBThreeNine}{}% + \ifstrequal{#1}{flush\_TLB48}{\sailRISCVfnflushTLBFourEight}{}% + \ifstrequal{#1}{flush\_TLB\_Entry}{\sailRISCVfnflushTLBEntry}{}% + \ifstrequal{#1}{fmake\_D}{\sailRISCVfnfmakeD}{}% + \ifstrequal{#1}{fmake\_S}{\sailRISCVfnfmakeS}{}% + \ifstrequal{#1}{fmod\_int}{\sailRISCVfnfmodInt}{}% + \ifstrequal{#1}{fregval\_from\_freg}{\sailRISCVfnfregvalFromFreg}{}% + \ifstrequal{#1}{fregval\_into\_freg}{\sailRISCVfnfregvalIntoFreg}{}% + \ifstrequal{#1}{fsplit\_D}{\sailRISCVfnfsplitD}{}% + \ifstrequal{#1}{fsplit\_S}{\sailRISCVfnfsplitS}{}% + \ifstrequal{#1}{getCapBase}{\sailRISCVfngetCapBase}{}% + \ifstrequal{#1}{getCapBaseBits}{\sailRISCVfngetCapBaseBits}{}% + \ifstrequal{#1}{getCapBounds}{\sailRISCVfngetCapBounds}{}% + \ifstrequal{#1}{getCapBoundsBits}{\sailRISCVfngetCapBoundsBits}{}% + \ifstrequal{#1}{getCapCursor}{\sailRISCVfngetCapCursor}{}% + \ifstrequal{#1}{getCapFlags}{\sailRISCVfngetCapFlags}{}% + \ifstrequal{#1}{getCapHardPerms}{\sailRISCVfngetCapHardPerms}{}% + \ifstrequal{#1}{getCapLength}{\sailRISCVfngetCapLength}{}% + \ifstrequal{#1}{getCapOffset}{\sailRISCVfngetCapOffset}{}% + \ifstrequal{#1}{getCapOffsetBits}{\sailRISCVfngetCapOffsetBits}{}% + \ifstrequal{#1}{getCapPerms}{\sailRISCVfngetCapPerms}{}% + \ifstrequal{#1}{getCapTop}{\sailRISCVfngetCapTop}{}% + \ifstrequal{#1}{getCapTopBits}{\sailRISCVfngetCapTopBits}{}% + \ifstrequal{#1}{getPendingSet}{\sailRISCVfngetPendingSet}{}% + \ifstrequal{#1}{getRepresentableAlignmentMask}{\sailRISCVfngetRepresentableAlignmentMask}{}% + \ifstrequal{#1}{getRepresentableLength}{\sailRISCVfngetRepresentableLength}{}% + \ifstrequal{#1}{get\_arch\_pc}{\sailRISCVfngetArchPc}{}% + \ifstrequal{#1}{get\_cheri\_mode\_cap\_addr}{\sailRISCVfngetCheriModeCapAddr}{}% + \ifstrequal{#1}{get\_config\_print\_instr}{\sailRISCVfngetConfigPrintInstr}{}% + \ifstrequal{#1}{get\_config\_print\_mem}{\sailRISCVfngetConfigPrintMem}{}% + \ifstrequal{#1}{get\_config\_print\_platform}{\sailRISCVfngetConfigPrintPlatform}{}% + \ifstrequal{#1}{get\_config\_print\_reg}{\sailRISCVfngetConfigPrintReg}{}% + \ifstrequal{#1}{get\_mstatus\_SXL}{\sailRISCVfngetMstatusSXL}{}% + \ifstrequal{#1}{get\_mstatus\_UXL}{\sailRISCVfngetMstatusUXL}{}% + \ifstrequal{#1}{get\_mtvec}{\sailRISCVfngetMtvec}{}% + \ifstrequal{#1}{get\_next\_pc}{\sailRISCVfngetNextPc}{}% + \ifstrequal{#1}{get\_sstatus\_UXL}{\sailRISCVfngetSstatusUXL}{}% + \ifstrequal{#1}{get\_stvec}{\sailRISCVfngetStvec}{}% + \ifstrequal{#1}{get\_utvec}{\sailRISCVfngetUtvec}{}% + \ifstrequal{#1}{get\_xret\_target}{\sailRISCVfngetXretTarget}{}% + \ifstrequal{#1}{handle\_cheri\_cap\_exception}{\sailRISCVfnhandleCheriCapException}{}% + \ifstrequal{#1}{handle\_cheri\_pcc\_exception}{\sailRISCVfnhandleCheriPccException}{}% + \ifstrequal{#1}{handle\_cheri\_reg\_exception}{\sailRISCVfnhandleCheriRegException}{}% + \ifstrequal{#1}{handle\_exception}{\sailRISCVfnhandleException}{}% + \ifstrequal{#1}{handle\_illegal}{\sailRISCVfnhandleIllegal}{}% + \ifstrequal{#1}{handle\_interrupt}{\sailRISCVfnhandleInterrupt}{}% + \ifstrequal{#1}{handle\_load\_cap\_via\_cap}{\sailRISCVfnhandleLoadCapViaCap}{}% + \ifstrequal{#1}{handle\_load\_data\_via\_cap}{\sailRISCVfnhandleLoadDataViaCap}{}% + \ifstrequal{#1}{handle\_loadres\_cap\_via\_cap}{\sailRISCVfnhandleLoadresCapViaCap}{}% + \ifstrequal{#1}{handle\_loadres\_data\_via\_cap}{\sailRISCVfnhandleLoadresDataViaCap}{}% + \ifstrequal{#1}{handle\_mem\_exception}{\sailRISCVfnhandleMemException}{}% + \ifstrequal{#1}{handle\_store\_cap\_via\_cap}{\sailRISCVfnhandleStoreCapViaCap}{}% + \ifstrequal{#1}{handle\_store\_cond\_cap\_via\_cap}{\sailRISCVfnhandleStoreCondCapViaCap}{}% + \ifstrequal{#1}{handle\_store\_cond\_data\_via\_cap}{\sailRISCVfnhandleStoreCondDataViaCap}{}% + \ifstrequal{#1}{handle\_store\_data\_via\_cap}{\sailRISCVfnhandleStoreDataViaCap}{}% + \ifstrequal{#1}{handle\_trap\_extension}{\sailRISCVfnhandleTrapExtension}{}% + \ifstrequal{#1}{hasReservedOType}{\sailRISCVfnhasReservedOType}{}% + \ifstrequal{#1}{haveAtomics}{\sailRISCVfnhaveAtomics}{}% + \ifstrequal{#1}{haveDExt}{\sailRISCVfnhaveDExt}{}% + \ifstrequal{#1}{haveFExt}{\sailRISCVfnhaveFExt}{}% + \ifstrequal{#1}{haveMulDiv}{\sailRISCVfnhaveMulDiv}{}% + \ifstrequal{#1}{haveNExt}{\sailRISCVfnhaveNExt}{}% + \ifstrequal{#1}{haveRVC}{\sailRISCVfnhaveRVC}{}% + \ifstrequal{#1}{haveSupMode}{\sailRISCVfnhaveSupMode}{}% + \ifstrequal{#1}{haveUsrMode}{\sailRISCVfnhaveUsrMode}{}% + \ifstrequal{#1}{haveXcheri}{\sailRISCVfnhaveXcheri}{}% + \ifstrequal{#1}{hex\_bits\_10\_backwards}{\sailRISCVfnhexBitsOneZeroBackwards}{}% + \ifstrequal{#1}{hex\_bits\_10\_backwards\_matches}{\sailRISCVfnhexBitsOneZeroBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_10\_forwards\_matches}{\sailRISCVfnhexBitsOneZeroForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_11\_backwards}{\sailRISCVfnhexBitsOneOneBackwards}{}% + \ifstrequal{#1}{hex\_bits\_11\_backwards\_matches}{\sailRISCVfnhexBitsOneOneBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_11\_forwards\_matches}{\sailRISCVfnhexBitsOneOneForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_12\_backwards}{\sailRISCVfnhexBitsOneTwoBackwards}{}% + \ifstrequal{#1}{hex\_bits\_12\_backwards\_matches}{\sailRISCVfnhexBitsOneTwoBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_12\_forwards\_matches}{\sailRISCVfnhexBitsOneTwoForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_12\_matches\_prefix}{\sailRISCVfnhexBitsOneTwoMatchesPrefix}{}% + \ifstrequal{#1}{hex\_bits\_13\_backwards}{\sailRISCVfnhexBitsOneThreeBackwards}{}% + \ifstrequal{#1}{hex\_bits\_13\_backwards\_matches}{\sailRISCVfnhexBitsOneThreeBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_13\_forwards\_matches}{\sailRISCVfnhexBitsOneThreeForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_14\_backwards}{\sailRISCVfnhexBitsOneFourBackwards}{}% + \ifstrequal{#1}{hex\_bits\_14\_backwards\_matches}{\sailRISCVfnhexBitsOneFourBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_14\_forwards\_matches}{\sailRISCVfnhexBitsOneFourForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_15\_backwards}{\sailRISCVfnhexBitsOneFiveBackwards}{}% + \ifstrequal{#1}{hex\_bits\_15\_backwards\_matches}{\sailRISCVfnhexBitsOneFiveBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_15\_forwards\_matches}{\sailRISCVfnhexBitsOneFiveForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_16\_backwards}{\sailRISCVfnhexBitsOneSixBackwards}{}% + \ifstrequal{#1}{hex\_bits\_16\_backwards\_matches}{\sailRISCVfnhexBitsOneSixBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_16\_forwards\_matches}{\sailRISCVfnhexBitsOneSixForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_17\_backwards}{\sailRISCVfnhexBitsOneSevenBackwards}{}% + \ifstrequal{#1}{hex\_bits\_17\_backwards\_matches}{\sailRISCVfnhexBitsOneSevenBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_17\_forwards\_matches}{\sailRISCVfnhexBitsOneSevenForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_18\_backwards}{\sailRISCVfnhexBitsOneEightBackwards}{}% + \ifstrequal{#1}{hex\_bits\_18\_backwards\_matches}{\sailRISCVfnhexBitsOneEightBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_18\_forwards\_matches}{\sailRISCVfnhexBitsOneEightForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_19\_backwards}{\sailRISCVfnhexBitsOneNineBackwards}{}% + \ifstrequal{#1}{hex\_bits\_19\_backwards\_matches}{\sailRISCVfnhexBitsOneNineBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_19\_forwards\_matches}{\sailRISCVfnhexBitsOneNineForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_1\_backwards}{\sailRISCVfnhexBitsOneBackwards}{}% + \ifstrequal{#1}{hex\_bits\_1\_backwards\_matches}{\sailRISCVfnhexBitsOneBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_1\_forwards\_matches}{\sailRISCVfnhexBitsOneForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_20\_backwards}{\sailRISCVfnhexBitsTwoZeroBackwards}{}% + \ifstrequal{#1}{hex\_bits\_20\_backwards\_matches}{\sailRISCVfnhexBitsTwoZeroBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_20\_forwards\_matches}{\sailRISCVfnhexBitsTwoZeroForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_21\_backwards}{\sailRISCVfnhexBitsTwoOneBackwards}{}% + \ifstrequal{#1}{hex\_bits\_21\_backwards\_matches}{\sailRISCVfnhexBitsTwoOneBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_21\_forwards\_matches}{\sailRISCVfnhexBitsTwoOneForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_22\_backwards}{\sailRISCVfnhexBitsTwoTwoBackwards}{}% + \ifstrequal{#1}{hex\_bits\_22\_backwards\_matches}{\sailRISCVfnhexBitsTwoTwoBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_22\_forwards\_matches}{\sailRISCVfnhexBitsTwoTwoForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_23\_backwards}{\sailRISCVfnhexBitsTwoThreeBackwards}{}% + \ifstrequal{#1}{hex\_bits\_23\_backwards\_matches}{\sailRISCVfnhexBitsTwoThreeBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_23\_forwards\_matches}{\sailRISCVfnhexBitsTwoThreeForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_24\_backwards}{\sailRISCVfnhexBitsTwoFourBackwards}{}% + \ifstrequal{#1}{hex\_bits\_24\_backwards\_matches}{\sailRISCVfnhexBitsTwoFourBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_24\_forwards\_matches}{\sailRISCVfnhexBitsTwoFourForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_25\_backwards}{\sailRISCVfnhexBitsTwoFiveBackwards}{}% + \ifstrequal{#1}{hex\_bits\_25\_backwards\_matches}{\sailRISCVfnhexBitsTwoFiveBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_25\_forwards\_matches}{\sailRISCVfnhexBitsTwoFiveForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_26\_backwards}{\sailRISCVfnhexBitsTwoSixBackwards}{}% + \ifstrequal{#1}{hex\_bits\_26\_backwards\_matches}{\sailRISCVfnhexBitsTwoSixBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_26\_forwards\_matches}{\sailRISCVfnhexBitsTwoSixForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_27\_backwards}{\sailRISCVfnhexBitsTwoSevenBackwards}{}% + \ifstrequal{#1}{hex\_bits\_27\_backwards\_matches}{\sailRISCVfnhexBitsTwoSevenBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_27\_forwards\_matches}{\sailRISCVfnhexBitsTwoSevenForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_28\_backwards}{\sailRISCVfnhexBitsTwoEightBackwards}{}% + \ifstrequal{#1}{hex\_bits\_28\_backwards\_matches}{\sailRISCVfnhexBitsTwoEightBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_28\_forwards\_matches}{\sailRISCVfnhexBitsTwoEightForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_29\_backwards}{\sailRISCVfnhexBitsTwoNineBackwards}{}% + \ifstrequal{#1}{hex\_bits\_29\_backwards\_matches}{\sailRISCVfnhexBitsTwoNineBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_29\_forwards\_matches}{\sailRISCVfnhexBitsTwoNineForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_2\_backwards}{\sailRISCVfnhexBitsTwoBackwards}{}% + \ifstrequal{#1}{hex\_bits\_2\_backwards\_matches}{\sailRISCVfnhexBitsTwoBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_2\_forwards\_matches}{\sailRISCVfnhexBitsTwoForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_30\_backwards}{\sailRISCVfnhexBitsThreeZeroBackwards}{}% + \ifstrequal{#1}{hex\_bits\_30\_backwards\_matches}{\sailRISCVfnhexBitsThreeZeroBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_30\_forwards\_matches}{\sailRISCVfnhexBitsThreeZeroForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_31\_backwards}{\sailRISCVfnhexBitsThreeOneBackwards}{}% + \ifstrequal{#1}{hex\_bits\_31\_backwards\_matches}{\sailRISCVfnhexBitsThreeOneBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_31\_forwards\_matches}{\sailRISCVfnhexBitsThreeOneForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_32\_backwards}{\sailRISCVfnhexBitsThreeTwoBackwards}{}% + \ifstrequal{#1}{hex\_bits\_32\_backwards\_matches}{\sailRISCVfnhexBitsThreeTwoBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_32\_forwards\_matches}{\sailRISCVfnhexBitsThreeTwoForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_33\_backwards}{\sailRISCVfnhexBitsThreeThreeBackwards}{}% + \ifstrequal{#1}{hex\_bits\_33\_backwards\_matches}{\sailRISCVfnhexBitsThreeThreeBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_33\_forwards\_matches}{\sailRISCVfnhexBitsThreeThreeForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_3\_backwards}{\sailRISCVfnhexBitsThreeBackwards}{}% + \ifstrequal{#1}{hex\_bits\_3\_backwards\_matches}{\sailRISCVfnhexBitsThreeBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_3\_forwards\_matches}{\sailRISCVfnhexBitsThreeForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_48\_backwards}{\sailRISCVfnhexBitsFourEightBackwards}{}% + \ifstrequal{#1}{hex\_bits\_48\_backwards\_matches}{\sailRISCVfnhexBitsFourEightBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_48\_forwards\_matches}{\sailRISCVfnhexBitsFourEightForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_4\_backwards}{\sailRISCVfnhexBitsFourBackwards}{}% + \ifstrequal{#1}{hex\_bits\_4\_backwards\_matches}{\sailRISCVfnhexBitsFourBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_4\_forwards\_matches}{\sailRISCVfnhexBitsFourForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_5\_backwards}{\sailRISCVfnhexBitsFiveBackwards}{}% + \ifstrequal{#1}{hex\_bits\_5\_backwards\_matches}{\sailRISCVfnhexBitsFiveBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_5\_forwards\_matches}{\sailRISCVfnhexBitsFiveForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_64\_backwards}{\sailRISCVfnhexBitsSixFourBackwards}{}% + \ifstrequal{#1}{hex\_bits\_64\_backwards\_matches}{\sailRISCVfnhexBitsSixFourBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_64\_forwards\_matches}{\sailRISCVfnhexBitsSixFourForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_6\_backwards}{\sailRISCVfnhexBitsSixBackwards}{}% + \ifstrequal{#1}{hex\_bits\_6\_backwards\_matches}{\sailRISCVfnhexBitsSixBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_6\_forwards\_matches}{\sailRISCVfnhexBitsSixForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_7\_backwards}{\sailRISCVfnhexBitsSevenBackwards}{}% + \ifstrequal{#1}{hex\_bits\_7\_backwards\_matches}{\sailRISCVfnhexBitsSevenBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_7\_forwards\_matches}{\sailRISCVfnhexBitsSevenForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_8\_backwards}{\sailRISCVfnhexBitsEightBackwards}{}% + \ifstrequal{#1}{hex\_bits\_8\_backwards\_matches}{\sailRISCVfnhexBitsEightBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_8\_forwards\_matches}{\sailRISCVfnhexBitsEightForwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_9\_backwards}{\sailRISCVfnhexBitsNineBackwards}{}% + \ifstrequal{#1}{hex\_bits\_9\_backwards\_matches}{\sailRISCVfnhexBitsNineBackwardsMatches}{}% + \ifstrequal{#1}{hex\_bits\_9\_forwards\_matches}{\sailRISCVfnhexBitsNineForwardsMatches}{}% + \ifstrequal{#1}{htif\_load}{\sailRISCVfnhtifLoad}{}% + \ifstrequal{#1}{htif\_store}{\sailRISCVfnhtifStore}{}% + \ifstrequal{#1}{htif\_tick}{\sailRISCVfnhtifTick}{}% + \ifstrequal{#1}{in32BitMode}{\sailRISCVfninThreeTwoBitMode}{}% + \ifstrequal{#1}{inCapBounds}{\sailRISCVfninCapBounds}{}% + \ifstrequal{#1}{incCapOffset}{\sailRISCVfnincCapOffset}{}% + \ifstrequal{#1}{init\_base\_regs}{\sailRISCVfninitBaseRegs}{}% + \ifstrequal{#1}{init\_fdext\_regs}{\sailRISCVfninitFdextRegs}{}% + \ifstrequal{#1}{init\_model}{\sailRISCVfninitModel}{}% + \ifstrequal{#1}{init\_platform}{\sailRISCVfninitPlatform}{}% + \ifstrequal{#1}{init\_pmp}{\sailRISCVfninitPmp}{}% + \ifstrequal{#1}{init\_sys}{\sailRISCVfninitSys}{}% + \ifstrequal{#1}{init\_vmem}{\sailRISCVfninitVmem}{}% + \ifstrequal{#1}{init\_vmem\_sv39}{\sailRISCVfninitVmemSvThreeNine}{}% + \ifstrequal{#1}{init\_vmem\_sv48}{\sailRISCVfninitVmemSvFourEight}{}% + \ifstrequal{#1}{initial\_analysis}{\sailRISCVfninitialAnalysis}{}% + \ifstrequal{#1}{int\_to\_cap}{\sailRISCVfnintToCap}{}% + \ifstrequal{#1}{internal\_error}{\sailRISCVfninternalError}{}% + \ifstrequal{#1}{interruptType\_to\_bits}{\sailRISCVfninterruptTypeToBits}{}% + \ifstrequal{#1}{invalidateCap}{\sailRISCVfninvalidateCap}{}% + \ifstrequal{#1}{iop\_of\_num}{\sailRISCVfniopOfNum}{}% + \ifstrequal{#1}{isCapSealed}{\sailRISCVfnisCapSealed}{}% + \ifstrequal{#1}{isInvalidPTE}{\sailRISCVfnisInvalidPTE}{}% + \ifstrequal{#1}{isPTEPtr}{\sailRISCVfnisPTEPtr}{}% + \ifstrequal{#1}{isRVC}{\sailRISCVfnisRVC}{}% + \ifstrequal{#1}{isValidSv39Addr}{\sailRISCVfnisValidSvThreeNineAddr}{}% + \ifstrequal{#1}{isValidSv48Addr}{\sailRISCVfnisValidSvFourEightAddr}{}% + \ifstrequal{#1}{is\_CSR\_defined}{\sailRISCVfnisCSRDefined}{}% + \ifstrequal{#1}{is\_RV32D\_or\_RV64D}{\sailRISCVfnisRVThreeTwoDOrRVSixFourD}{}% + \ifstrequal{#1}{is\_RV32F\_or\_RV64F}{\sailRISCVfnisRVThreeTwoFOrRVSixFourF}{}% + \ifstrequal{#1}{is\_RV64D}{\sailRISCVfnisRVSixFourD}{}% + \ifstrequal{#1}{is\_RV64F}{\sailRISCVfnisRVSixFourF}{}% + \ifstrequal{#1}{is\_aligned\_addr}{\sailRISCVfnisAlignedAddr}{}% + \ifstrequal{#1}{is\_none}{\sailRISCVfnisNone}{}% + \ifstrequal{#1}{is\_some}{\sailRISCVfnisSome}{}% + \ifstrequal{#1}{legalize\_ccsr}{\sailRISCVfnlegalizzeCcsr}{}% + \ifstrequal{#1}{legalize\_epcc}{\sailRISCVfnlegalizzeEpcc}{}% + \ifstrequal{#1}{legalize\_mcounteren}{\sailRISCVfnlegalizzeMcounteren}{}% + \ifstrequal{#1}{legalize\_mcountinhibit}{\sailRISCVfnlegalizzeMcountinhibit}{}% + \ifstrequal{#1}{legalize\_medeleg}{\sailRISCVfnlegalizzeMedeleg}{}% + \ifstrequal{#1}{legalize\_mideleg}{\sailRISCVfnlegalizzeMideleg}{}% + \ifstrequal{#1}{legalize\_mie}{\sailRISCVfnlegalizzeMie}{}% + \ifstrequal{#1}{legalize\_mip}{\sailRISCVfnlegalizzeMip}{}% + \ifstrequal{#1}{legalize\_misa}{\sailRISCVfnlegalizzeMisa}{}% + \ifstrequal{#1}{legalize\_mstatus}{\sailRISCVfnlegalizzeMstatus}{}% + \ifstrequal{#1}{legalize\_satp}{\sailRISCVfnlegalizzeSatp}{}% + \ifstrequal{#1}{legalize\_satp32}{\sailRISCVfnlegalizzeSatpThreeTwo}{}% + \ifstrequal{#1}{legalize\_satp64}{\sailRISCVfnlegalizzeSatpSixFour}{}% + \ifstrequal{#1}{legalize\_scounteren}{\sailRISCVfnlegalizzeScounteren}{}% + \ifstrequal{#1}{legalize\_sedeleg}{\sailRISCVfnlegalizzeSedeleg}{}% + \ifstrequal{#1}{legalize\_sie}{\sailRISCVfnlegalizzeSie}{}% + \ifstrequal{#1}{legalize\_sip}{\sailRISCVfnlegalizzeSip}{}% + \ifstrequal{#1}{legalize\_sstatus}{\sailRISCVfnlegalizzeSstatus}{}% + \ifstrequal{#1}{legalize\_tcc}{\sailRISCVfnlegalizzeTcc}{}% + \ifstrequal{#1}{legalize\_tvec}{\sailRISCVfnlegalizzeTvec}{}% + \ifstrequal{#1}{legalize\_uie}{\sailRISCVfnlegalizzeUie}{}% + \ifstrequal{#1}{legalize\_uip}{\sailRISCVfnlegalizzeUip}{}% + \ifstrequal{#1}{legalize\_ustatus}{\sailRISCVfnlegalizzeUstatus}{}% + \ifstrequal{#1}{legalize\_xepc}{\sailRISCVfnlegalizzeXepc}{}% + \ifstrequal{#1}{lift\_sie}{\sailRISCVfnliftSie}{}% + \ifstrequal{#1}{lift\_sip}{\sailRISCVfnliftSip}{}% + \ifstrequal{#1}{lift\_sstatus}{\sailRISCVfnliftSstatus}{}% + \ifstrequal{#1}{lift\_uie}{\sailRISCVfnliftUie}{}% + \ifstrequal{#1}{lift\_uip}{\sailRISCVfnliftUip}{}% + \ifstrequal{#1}{lift\_ustatus}{\sailRISCVfnliftUstatus}{}% + \ifstrequal{#1}{lookup\_TLB39}{\sailRISCVfnlookupTLBThreeNine}{}% + \ifstrequal{#1}{lookup\_TLB48}{\sailRISCVfnlookupTLBFourEight}{}% + \ifstrequal{#1}{loop}{\sailRISCVfnloop}{}% + \ifstrequal{#1}{lower\_mie}{\sailRISCVfnlowerMie}{}% + \ifstrequal{#1}{lower\_mip}{\sailRISCVfnlowerMip}{}% + \ifstrequal{#1}{lower\_mstatus}{\sailRISCVfnlowerMstatus}{}% + \ifstrequal{#1}{lower\_sie}{\sailRISCVfnlowerSie}{}% + \ifstrequal{#1}{lower\_sip}{\sailRISCVfnlowerSip}{}% + \ifstrequal{#1}{lower\_sstatus}{\sailRISCVfnlowerSstatus}{}% + \ifstrequal{#1}{lrsc\_width\_str}{\sailRISCVfnlrscWidthStr}{}% + \ifstrequal{#1}{make\_TLB\_Entry}{\sailRISCVfnmakeTLBEntry}{}% + \ifstrequal{#1}{match\_TLB\_Entry}{\sailRISCVfnmatchTLBEntry}{}% + \ifstrequal{#1}{memBitsToCapability}{\sailRISCVfnmemBitsToCapability}{}% + \ifstrequal{#1}{mem\_read}{\sailRISCVfnmemRead}{}% + \ifstrequal{#1}{mem\_read\_cap}{\sailRISCVfnmemReadCap}{}% + \ifstrequal{#1}{mem\_read\_meta}{\sailRISCVfnmemReadMeta}{}% + \ifstrequal{#1}{mem\_write\_cap}{\sailRISCVfnmemWriteCap}{}% + \ifstrequal{#1}{mem\_write\_ea}{\sailRISCVfnmemWriteEa}{}% + \ifstrequal{#1}{mem\_write\_ea\_cap}{\sailRISCVfnmemWriteEaCap}{}% + \ifstrequal{#1}{mem\_write\_value}{\sailRISCVfnmemWriteValue}{}% + \ifstrequal{#1}{mem\_write\_value\_meta}{\sailRISCVfnmemWriteValueMeta}{}% + \ifstrequal{#1}{min\_instruction\_bytes}{\sailRISCVfnminInstructionBytes}{}% + \ifstrequal{#1}{mmio\_read}{\sailRISCVfnmmioRead}{}% + \ifstrequal{#1}{mmio\_write}{\sailRISCVfnmmioWrite}{}% + \ifstrequal{#1}{n\_leading\_spaces}{\sailRISCVfnnLeadingSpaces}{}% + \ifstrequal{#1}{nan\_box}{\sailRISCVfnnanBox}{}% + \ifstrequal{#1}{nan\_unbox}{\sailRISCVfnnanUnbox}{}% + \ifstrequal{#1}{negate\_D}{\sailRISCVfnnegateD}{}% + \ifstrequal{#1}{negate\_S}{\sailRISCVfnnegateS}{}% + \ifstrequal{#1}{neq\_anything}{\sailRISCVfnneqAnything}{}% + \ifstrequal{#1}{neq\_bits}{\sailRISCVfnneqBits}{}% + \ifstrequal{#1}{neq\_bool}{\sailRISCVfnneqBool}{}% + \ifstrequal{#1}{neq\_int}{\sailRISCVfnneqInt}{}% + \ifstrequal{#1}{neq\_vec}{\sailRISCVfnneqVec}{}% + \ifstrequal{#1}{not\_bit}{\sailRISCVfnnotBit}{}% + \ifstrequal{#1}{not\_implemented}{\sailRISCVfnnotImplemented}{}% + \ifstrequal{#1}{num\_of\_Architecture}{\sailRISCVfnnumOfArchitecture}{}% + \ifstrequal{#1}{num\_of\_CPtrCmpOp}{\sailRISCVfnnumOfCPtrCmpOp}{}% + \ifstrequal{#1}{num\_of\_CapEx}{\sailRISCVfnnumOfCapEx}{}% + \ifstrequal{#1}{num\_of\_ClearRegSet}{\sailRISCVfnnumOfClearRegSet}{}% + \ifstrequal{#1}{num\_of\_ExceptionType}{\sailRISCVfnnumOfExceptionType}{}% + \ifstrequal{#1}{num\_of\_ExtStatus}{\sailRISCVfnnumOfExtStatus}{}% + \ifstrequal{#1}{num\_of\_InterruptType}{\sailRISCVfnnumOfInterruptType}{}% + \ifstrequal{#1}{num\_of\_PmpAddrMatchType}{\sailRISCVfnnumOfPmpAddrMatchType}{}% + \ifstrequal{#1}{num\_of\_Privilege}{\sailRISCVfnnumOfPrivilege}{}% + \ifstrequal{#1}{num\_of\_Retired}{\sailRISCVfnnumOfRetired}{}% + \ifstrequal{#1}{num\_of\_SATPMode}{\sailRISCVfnnumOfSATPMode}{}% + \ifstrequal{#1}{num\_of\_TrapVectorMode}{\sailRISCVfnnumOfTrapVectorMode}{}% + \ifstrequal{#1}{num\_of\_a64\_barrier\_domain}{\sailRISCVfnnumOfASixFourBarrierDomain}{}% + \ifstrequal{#1}{num\_of\_a64\_barrier\_type}{\sailRISCVfnnumOfASixFourBarrierType}{}% + \ifstrequal{#1}{num\_of\_amoop}{\sailRISCVfnnumOfAmoop}{}% + \ifstrequal{#1}{num\_of\_bop}{\sailRISCVfnnumOfBop}{}% + \ifstrequal{#1}{num\_of\_cache\_op\_kind}{\sailRISCVfnnumOfCacheOpKind}{}% + \ifstrequal{#1}{num\_of\_csrop}{\sailRISCVfnnumOfCsrop}{}% + \ifstrequal{#1}{num\_of\_ext\_access\_type}{\sailRISCVfnnumOfExtAccessType}{}% + \ifstrequal{#1}{num\_of\_ext\_exc\_type}{\sailRISCVfnnumOfExtExcType}{}% + \ifstrequal{#1}{num\_of\_ext\_ptw\_error}{\sailRISCVfnnumOfExtPtwError}{}% + \ifstrequal{#1}{num\_of\_ext\_ptw\_fail}{\sailRISCVfnnumOfExtPtwFail}{}% + \ifstrequal{#1}{num\_of\_ext\_ptw\_lc}{\sailRISCVfnnumOfExtPtwLc}{}% + \ifstrequal{#1}{num\_of\_ext\_ptw\_sc}{\sailRISCVfnnumOfExtPtwSc}{}% + \ifstrequal{#1}{num\_of\_f\_bin\_op\_D}{\sailRISCVfnnumOfFBinOpD}{}% + \ifstrequal{#1}{num\_of\_f\_bin\_op\_S}{\sailRISCVfnnumOfFBinOpS}{}% + \ifstrequal{#1}{num\_of\_f\_bin\_rm\_op\_D}{\sailRISCVfnnumOfFBinRmOpD}{}% + \ifstrequal{#1}{num\_of\_f\_bin\_rm\_op\_S}{\sailRISCVfnnumOfFBinRmOpS}{}% + \ifstrequal{#1}{num\_of\_f\_madd\_op\_D}{\sailRISCVfnnumOfFMaddOpD}{}% + \ifstrequal{#1}{num\_of\_f\_madd\_op\_S}{\sailRISCVfnnumOfFMaddOpS}{}% + \ifstrequal{#1}{num\_of\_f\_un\_op\_D}{\sailRISCVfnnumOfFUnOpD}{}% + \ifstrequal{#1}{num\_of\_f\_un\_op\_S}{\sailRISCVfnnumOfFUnOpS}{}% + \ifstrequal{#1}{num\_of\_f\_un\_rm\_op\_D}{\sailRISCVfnnumOfFUnRmOpD}{}% + \ifstrequal{#1}{num\_of\_f\_un\_rm\_op\_S}{\sailRISCVfnnumOfFUnRmOpS}{}% + \ifstrequal{#1}{num\_of\_iop}{\sailRISCVfnnumOfIop}{}% + \ifstrequal{#1}{num\_of\_pmpAddrMatch}{\sailRISCVfnnumOfPmpAddrMatch}{}% + \ifstrequal{#1}{num\_of\_pmpMatch}{\sailRISCVfnnumOfPmpMatch}{}% + \ifstrequal{#1}{num\_of\_read\_kind}{\sailRISCVfnnumOfReadKind}{}% + \ifstrequal{#1}{num\_of\_rop}{\sailRISCVfnnumOfRop}{}% + \ifstrequal{#1}{num\_of\_ropw}{\sailRISCVfnnumOfRopw}{}% + \ifstrequal{#1}{num\_of\_rounding\_mode}{\sailRISCVfnnumOfRoundingMode}{}% + \ifstrequal{#1}{num\_of\_sop}{\sailRISCVfnnumOfSop}{}% + \ifstrequal{#1}{num\_of\_sopw}{\sailRISCVfnnumOfSopw}{}% + \ifstrequal{#1}{num\_of\_trans\_kind}{\sailRISCVfnnumOfTransKind}{}% + \ifstrequal{#1}{num\_of\_uop}{\sailRISCVfnnumOfUop}{}% + \ifstrequal{#1}{num\_of\_word\_width}{\sailRISCVfnnumOfWordWidth}{}% + \ifstrequal{#1}{num\_of\_write\_kind}{\sailRISCVfnnumOfWriteKind}{}% + \ifstrequal{#1}{nvFlag}{\sailRISCVfnnvFlag}{}% + \ifstrequal{#1}{nxFlag}{\sailRISCVfnnxFlag}{}% + \ifstrequal{#1}{ofFlag}{\sailRISCVfnofFlag}{}% + \ifstrequal{#1}{ones}{\sailRISCVfnones}{}% + \ifstrequal{#1}{opt\_spc\_backwards}{\sailRISCVfnoptSpcBackwards}{}% + \ifstrequal{#1}{opt\_spc\_forwards}{\sailRISCVfnoptSpcForwards}{}% + \ifstrequal{#1}{opt\_spc\_matches\_prefix}{\sailRISCVfnoptSpcMatchesPrefix}{}% + \ifstrequal{#1}{pc\_alignment\_mask}{\sailRISCVfnpcAlignmentMask}{}% + \ifstrequal{#1}{pcc\_access\_system\_regs}{\sailRISCVfnpccAccessSystemRegs}{}% + \ifstrequal{#1}{phys\_mem\_read}{\sailRISCVfnphysMemRead}{}% + \ifstrequal{#1}{phys\_mem\_segments}{\sailRISCVfnphysMemSegments}{}% + \ifstrequal{#1}{phys\_mem\_write}{\sailRISCVfnphysMemWrite}{}% + \ifstrequal{#1}{plat\_htif\_tohost}{\sailRISCVfnplatHtifTohost}{}% + \ifstrequal{#1}{platform\_wfi}{\sailRISCVfnplatformWfi}{}% + \ifstrequal{#1}{pmpAddrMatchType\_of\_bits}{\sailRISCVfnpmpAddrMatchTypeOfBits}{}% + \ifstrequal{#1}{pmpAddrMatchType\_to\_bits}{\sailRISCVfnpmpAddrMatchTypeToBits}{}% + \ifstrequal{#1}{pmpAddrMatch\_of\_num}{\sailRISCVfnpmpAddrMatchOfNum}{}% + \ifstrequal{#1}{pmpAddrRange}{\sailRISCVfnpmpAddrRangeA}{}% + \ifstrequal{#1}{pmpCheck}{\sailRISCVfnpmpCheck}{}% + \ifstrequal{#1}{pmpCheckPerms}{\sailRISCVfnpmpCheckPerms}{}% + \ifstrequal{#1}{pmpCheckRWX}{\sailRISCVfnpmpCheckRWX}{}% + \ifstrequal{#1}{pmpLocked}{\sailRISCVfnpmpLocked}{}% + \ifstrequal{#1}{pmpMatchAddr}{\sailRISCVfnpmpMatchAddr}{}% + \ifstrequal{#1}{pmpMatchEntry}{\sailRISCVfnpmpMatchEntry}{}% + \ifstrequal{#1}{pmpMatch\_of\_num}{\sailRISCVfnpmpMatchOfNum}{}% + \ifstrequal{#1}{pmpReadCfgReg}{\sailRISCVfnpmpReadCfgReg}{}% + \ifstrequal{#1}{pmpTORLocked}{\sailRISCVfnpmpTORLocked}{}% + \ifstrequal{#1}{pmpWriteAddr}{\sailRISCVfnpmpWriteAddr}{}% + \ifstrequal{#1}{pmpWriteCfg}{\sailRISCVfnpmpWriteCfg}{}% + \ifstrequal{#1}{pmpWriteCfgReg}{\sailRISCVfnpmpWriteCfgReg}{}% + \ifstrequal{#1}{pmp\_mem\_read}{\sailRISCVfnpmpMemRead}{}% + \ifstrequal{#1}{pmp\_mem\_write}{\sailRISCVfnpmpMemWrite}{}% + \ifstrequal{#1}{prepare\_trap\_vector}{\sailRISCVfnprepareTrapVector}{}% + \ifstrequal{#1}{prepare\_xret\_target}{\sailRISCVfnprepareXretTarget}{}% + \ifstrequal{#1}{print\_insn}{\sailRISCVfnprintInsn}{}% + \ifstrequal{#1}{privLevel\_of\_bits}{\sailRISCVfnprivLevelOfBits}{}% + \ifstrequal{#1}{privLevel\_to\_bits}{\sailRISCVfnprivLevelToBits}{}% + \ifstrequal{#1}{privLevel\_to\_str}{\sailRISCVfnprivLevelToStr}{}% + \ifstrequal{#1}{processPending}{\sailRISCVfnprocessPending}{}% + \ifstrequal{#1}{process\_fload32}{\sailRISCVfnprocessFloadThreeTwo}{}% + \ifstrequal{#1}{process\_fload64}{\sailRISCVfnprocessFloadSixFour}{}% + \ifstrequal{#1}{process\_fstore}{\sailRISCVfnprocessFstore}{}% + \ifstrequal{#1}{process\_load}{\sailRISCVfnprocessLoad}{}% + \ifstrequal{#1}{process\_loadres}{\sailRISCVfnprocessLoadres}{}% + \ifstrequal{#1}{ptw\_error\_to\_str}{\sailRISCVfnptwErrorToStr}{}% + \ifstrequal{#1}{rC}{\sailRISCVfnrC}{}% + \ifstrequal{#1}{rC\_bits}{\sailRISCVfnrCBits}{}% + \ifstrequal{#1}{rF}{\sailRISCVfnrF}{}% + \ifstrequal{#1}{rF\_bits}{\sailRISCVfnrFBits}{}% + \ifstrequal{#1}{rX}{\sailRISCVfnrX}{}% + \ifstrequal{#1}{rX\_bits}{\sailRISCVfnrXBits}{}% + \ifstrequal{#1}{readCSR}{\sailRISCVfnreadCSR}{}% + \ifstrequal{#1}{read\_kind\_of\_flags}{\sailRISCVfnreadKindOfFlags}{}% + \ifstrequal{#1}{read\_kind\_of\_num}{\sailRISCVfnreadKindOfNum}{}% + \ifstrequal{#1}{read\_ram}{\sailRISCVfnreadRam}{}% + \ifstrequal{#1}{reg\_name\_abi}{\sailRISCVfnregNameAbi}{}% + \ifstrequal{#1}{regidx\_to\_regno}{\sailRISCVfnregidxToRegno}{}% + \ifstrequal{#1}{regval\_from\_reg}{\sailRISCVfnregvalFromReg}{}% + \ifstrequal{#1}{regval\_into\_reg}{\sailRISCVfnregvalIntoReg}{}% + \ifstrequal{#1}{retire\_instruction}{\sailRISCVfnretireInstruction}{}% + \ifstrequal{#1}{riscv\_f32Add}{\sailRISCVfnriscvFThreeTwoAdd}{}% + \ifstrequal{#1}{riscv\_f32Div}{\sailRISCVfnriscvFThreeTwoDiv}{}% + \ifstrequal{#1}{riscv\_f32Eq}{\sailRISCVfnriscvFThreeTwoEq}{}% + \ifstrequal{#1}{riscv\_f32Le}{\sailRISCVfnriscvFThreeTwoLe}{}% + \ifstrequal{#1}{riscv\_f32Lt}{\sailRISCVfnriscvFThreeTwoLt}{}% + \ifstrequal{#1}{riscv\_f32Mul}{\sailRISCVfnriscvFThreeTwoMul}{}% + \ifstrequal{#1}{riscv\_f32MulAdd}{\sailRISCVfnriscvFThreeTwoMulAdd}{}% + \ifstrequal{#1}{riscv\_f32Sqrt}{\sailRISCVfnriscvFThreeTwoSqrt}{}% + \ifstrequal{#1}{riscv\_f32Sub}{\sailRISCVfnriscvFThreeTwoSub}{}% + \ifstrequal{#1}{riscv\_f32ToF64}{\sailRISCVfnriscvFThreeTwoToFSixFour}{}% + \ifstrequal{#1}{riscv\_f32ToI32}{\sailRISCVfnriscvFThreeTwoToIThreeTwo}{}% + \ifstrequal{#1}{riscv\_f32ToI64}{\sailRISCVfnriscvFThreeTwoToISixFour}{}% + \ifstrequal{#1}{riscv\_f32ToUi32}{\sailRISCVfnriscvFThreeTwoToUiThreeTwo}{}% + \ifstrequal{#1}{riscv\_f32ToUi64}{\sailRISCVfnriscvFThreeTwoToUiSixFour}{}% + \ifstrequal{#1}{riscv\_f64Add}{\sailRISCVfnriscvFSixFourAdd}{}% + \ifstrequal{#1}{riscv\_f64Div}{\sailRISCVfnriscvFSixFourDiv}{}% + \ifstrequal{#1}{riscv\_f64Eq}{\sailRISCVfnriscvFSixFourEq}{}% + \ifstrequal{#1}{riscv\_f64Le}{\sailRISCVfnriscvFSixFourLe}{}% + \ifstrequal{#1}{riscv\_f64Lt}{\sailRISCVfnriscvFSixFourLt}{}% + \ifstrequal{#1}{riscv\_f64Mul}{\sailRISCVfnriscvFSixFourMul}{}% + \ifstrequal{#1}{riscv\_f64MulAdd}{\sailRISCVfnriscvFSixFourMulAdd}{}% + \ifstrequal{#1}{riscv\_f64Sqrt}{\sailRISCVfnriscvFSixFourSqrt}{}% + \ifstrequal{#1}{riscv\_f64Sub}{\sailRISCVfnriscvFSixFourSub}{}% + \ifstrequal{#1}{riscv\_f64ToF32}{\sailRISCVfnriscvFSixFourToFThreeTwo}{}% + \ifstrequal{#1}{riscv\_f64ToI32}{\sailRISCVfnriscvFSixFourToIThreeTwo}{}% + \ifstrequal{#1}{riscv\_f64ToI64}{\sailRISCVfnriscvFSixFourToISixFour}{}% + \ifstrequal{#1}{riscv\_f64ToUi32}{\sailRISCVfnriscvFSixFourToUiThreeTwo}{}% + \ifstrequal{#1}{riscv\_f64ToUi64}{\sailRISCVfnriscvFSixFourToUiSixFour}{}% + \ifstrequal{#1}{riscv\_i32ToF32}{\sailRISCVfnriscvIThreeTwoToFThreeTwo}{}% + \ifstrequal{#1}{riscv\_i32ToF64}{\sailRISCVfnriscvIThreeTwoToFSixFour}{}% + \ifstrequal{#1}{riscv\_i64ToF32}{\sailRISCVfnriscvISixFourToFThreeTwo}{}% + \ifstrequal{#1}{riscv\_i64ToF64}{\sailRISCVfnriscvISixFourToFSixFour}{}% + \ifstrequal{#1}{riscv\_ui32ToF32}{\sailRISCVfnriscvUiThreeTwoToFThreeTwo}{}% + \ifstrequal{#1}{riscv\_ui32ToF64}{\sailRISCVfnriscvUiThreeTwoToFSixFour}{}% + \ifstrequal{#1}{riscv\_ui64ToF32}{\sailRISCVfnriscvUiSixFourToFThreeTwo}{}% + \ifstrequal{#1}{riscv\_ui64ToF64}{\sailRISCVfnriscvUiSixFourToFSixFour}{}% + \ifstrequal{#1}{rop\_of\_num}{\sailRISCVfnropOfNum}{}% + \ifstrequal{#1}{ropw\_of\_num}{\sailRISCVfnropwOfNum}{}% + \ifstrequal{#1}{rounding\_mode\_of\_num}{\sailRISCVfnroundingModeOfNum}{}% + \ifstrequal{#1}{rvfi\_read}{\sailRISCVfnrvfiRead}{}% + \ifstrequal{#1}{rvfi\_trap}{\sailRISCVfnrvfiTrap}{}% + \ifstrequal{#1}{rvfi\_wX}{\sailRISCVfnrvfiWX}{}% + \ifstrequal{#1}{rvfi\_write}{\sailRISCVfnrvfiWrite}{}% + \ifstrequal{#1}{sail\_mask}{\sailRISCVfnsailMask}{}% + \ifstrequal{#1}{sail\_ones}{\sailRISCVfnsailOnes}{}% + \ifstrequal{#1}{satp64Mode\_of\_bits}{\sailRISCVfnsatpSixFourModeOfBits}{}% + \ifstrequal{#1}{sealCap}{\sailRISCVfnsealCap}{}% + \ifstrequal{#1}{select\_instr\_or\_fcsr\_rm}{\sailRISCVfnselectInstrOrFcsrRm}{}% + \ifstrequal{#1}{setCapAddr}{\sailRISCVfnsetCapAddr}{}% + \ifstrequal{#1}{setCapBounds}{\sailRISCVfnsetCapBounds}{}% + \ifstrequal{#1}{setCapFlags}{\sailRISCVfnsetCapFlags}{}% + \ifstrequal{#1}{setCapOffset}{\sailRISCVfnsetCapOffset}{}% + \ifstrequal{#1}{setCapOffsetOrNull}{\sailRISCVfnsetCapOffsetOrNull}{}% + \ifstrequal{#1}{setCapPerms}{\sailRISCVfnsetCapPerms}{}% + \ifstrequal{#1}{set\_mstatus\_SXL}{\sailRISCVfnsetMstatusSXL}{}% + \ifstrequal{#1}{set\_mstatus\_UXL}{\sailRISCVfnsetMstatusUXL}{}% + \ifstrequal{#1}{set\_mtvec}{\sailRISCVfnsetMtvec}{}% + \ifstrequal{#1}{set\_next\_pc}{\sailRISCVfnsetNextPc}{}% + \ifstrequal{#1}{set\_sstatus\_UXL}{\sailRISCVfnsetSstatusUXL}{}% + \ifstrequal{#1}{set\_stvec}{\sailRISCVfnsetStvec}{}% + \ifstrequal{#1}{set\_utvec}{\sailRISCVfnsetUtvec}{}% + \ifstrequal{#1}{set\_xret\_target}{\sailRISCVfnsetXretTarget}{}% + \ifstrequal{#1}{shift\_right\_arith32}{\sailRISCVfnshiftRightArithThreeTwo}{}% + \ifstrequal{#1}{shift\_right\_arith64}{\sailRISCVfnshiftRightArithSixFour}{}% + \ifstrequal{#1}{slice\_mask}{\sailRISCVfnsliceMask}{}% + \ifstrequal{#1}{sop\_of\_num}{\sailRISCVfnsopOfNum}{}% + \ifstrequal{#1}{sopw\_of\_num}{\sailRISCVfnsopwOfNum}{}% + \ifstrequal{#1}{spc\_backwards}{\sailRISCVfnspcBackwards}{}% + \ifstrequal{#1}{spc\_forwards}{\sailRISCVfnspcForwards}{}% + \ifstrequal{#1}{spc\_matches\_prefix}{\sailRISCVfnspcMatchesPrefix}{}% + \ifstrequal{#1}{step}{\sailRISCVfnstep}{}% + \ifstrequal{#1}{string\_of\_bit}{\sailRISCVfnstringOfBit}{}% + \ifstrequal{#1}{string\_of\_capex}{\sailRISCVfnstringOfCapex}{}% + \ifstrequal{#1}{tag\_addr\_to\_addr}{\sailRISCVfntagAddrToAddr}{}% + \ifstrequal{#1}{tick\_clock}{\sailRISCVfntickClock}{}% + \ifstrequal{#1}{tick\_pc}{\sailRISCVfntickPc}{}% + \ifstrequal{#1}{tick\_platform}{\sailRISCVfntickPlatform}{}% + \ifstrequal{#1}{to\_bits}{\sailRISCVfntoBits}{}% + \ifstrequal{#1}{trans\_kind\_of\_num}{\sailRISCVfntransKindOfNum}{}% + \ifstrequal{#1}{translate39}{\sailRISCVfntranslateThreeNine}{}% + \ifstrequal{#1}{translate48}{\sailRISCVfntranslateFourEight}{}% + \ifstrequal{#1}{translateAddr}{\sailRISCVfntranslateAddr}{}% + \ifstrequal{#1}{translationException}{\sailRISCVfntranslationException}{}% + \ifstrequal{#1}{translationMode}{\sailRISCVfntranslationMode}{}% + \ifstrequal{#1}{trapVectorMode\_of\_bits}{\sailRISCVfntrapVectorModeOfBits}{}% + \ifstrequal{#1}{trap\_handler}{\sailRISCVfntrapHandler}{}% + \ifstrequal{#1}{tval}{\sailRISCVfntval}{}% + \ifstrequal{#1}{tvec\_addr}{\sailRISCVfntvecAddr}{}% + \ifstrequal{#1}{ufFlag}{\sailRISCVfnufFlag}{}% + \ifstrequal{#1}{unsealCap}{\sailRISCVfnunsealCap}{}% + \ifstrequal{#1}{uop\_of\_num}{\sailRISCVfnuopOfNum}{}% + \ifstrequal{#1}{update\_PTE\_Bits}{\sailRISCVfnupdatePTEBits}{}% + \ifstrequal{#1}{update\_softfloat\_fflags}{\sailRISCVfnupdateSoftfloatFflags}{}% + \ifstrequal{#1}{wC}{\sailRISCVfnwC}{}% + \ifstrequal{#1}{wC\_bits}{\sailRISCVfnwCBits}{}% + \ifstrequal{#1}{wF}{\sailRISCVfnwF}{}% + \ifstrequal{#1}{wF\_bits}{\sailRISCVfnwFBits}{}% + \ifstrequal{#1}{wX}{\sailRISCVfnwX}{}% + \ifstrequal{#1}{wX\_bits}{\sailRISCVfnwXBits}{}% + \ifstrequal{#1}{walk39}{\sailRISCVfnwalkThreeNine}{}% + \ifstrequal{#1}{walk48}{\sailRISCVfnwalkFourEight}{}% + \ifstrequal{#1}{within\_clint}{\sailRISCVfnwithinClint}{}% + \ifstrequal{#1}{within\_htif\_readable}{\sailRISCVfnwithinHtifReadable}{}% + \ifstrequal{#1}{within\_htif\_writable}{\sailRISCVfnwithinHtifWritable}{}% + \ifstrequal{#1}{within\_mmio\_readable}{\sailRISCVfnwithinMmioReadable}{}% + \ifstrequal{#1}{within\_mmio\_writable}{\sailRISCVfnwithinMmioWritable}{}% + \ifstrequal{#1}{within\_phys\_mem}{\sailRISCVfnwithinPhysMem}{}% + \ifstrequal{#1}{word\_width\_bytes}{\sailRISCVfnwordWidthBytes}{}% + \ifstrequal{#1}{word\_width\_of\_num}{\sailRISCVfnwordWidthOfNum}{}% + \ifstrequal{#1}{writeCSR}{\sailRISCVfnwriteCSR}{}% + \ifstrequal{#1}{write\_TLB39}{\sailRISCVfnwriteTLBThreeNine}{}% + \ifstrequal{#1}{write\_TLB48}{\sailRISCVfnwriteTLBFourEight}{}% + \ifstrequal{#1}{write\_fflags}{\sailRISCVfnwriteFflags}{}% + \ifstrequal{#1}{write\_kind\_of\_num}{\sailRISCVfnwriteKindOfNum}{}% + \ifstrequal{#1}{write\_ram}{\sailRISCVfnwriteRam}{}% + \ifstrequal{#1}{write\_ram\_ea}{\sailRISCVfnwriteRamEa}{}% + \ifstrequal{#1}{zeros\_implicit}{\sailRISCVfnzzerosImplicit}{}% + \ifstrequal{#1}{(operator $>$=\_u)}{\sailRISCVfnzEightoperatorzZerozIzJUzNine}{}% + \ifstrequal{#1}{(operator $>$\_s)}{\sailRISCVfnzEightoperatorzZerozISzNine}{}% + \ifstrequal{#1}{(operator $>$\_u)}{\sailRISCVfnzEightoperatorzZerozIUzNine}{}% + \ifstrequal{#1}{(operator $$>$$=\_s)}{\sailRISCVfnzEightoperatorzZerozKzJSzNine}{}% + \ifstrequal{#1}{(operator $$>$$=\_u)}{\sailRISCVfnzEightoperatorzZerozKzJUzNine}{}} + +\newcommand{\sailRISCVreffn}[2]{ + \ifstrequal{#1}{Architecture_of_num}{\hyperref[sailRISCVfnzArchitecturezyofzynum]{#2}}{}% + \ifstrequal{#1}{CPtrCmpOp_of_num}{\hyperref[sailRISCVfnzCPtrCmpOpzyofzynum]{#2}}{}% + \ifstrequal{#1}{CapExCode}{\hyperref[sailRISCVfnzCapExCode]{#2}}{}% + \ifstrequal{#1}{CapEx_of_num}{\hyperref[sailRISCVfnzCapExzyofzynum]{#2}}{}% + \ifstrequal{#1}{ClearRegSet_of_num}{\hyperref[sailRISCVfnzClearRegSetzyofzynum]{#2}}{}% + \ifstrequal{#1}{EXTS}{\hyperref[sailRISCVfnzEXTS]{#2}}{}% + \ifstrequal{#1}{EXTZ}{\hyperref[sailRISCVfnzEXTZ]{#2}}{}% + \ifstrequal{#1}{ExtStatus_of_num}{\hyperref[sailRISCVfnzExtStatuszyofzynum]{#2}}{}% + \ifstrequal{#1}{FRegStr}{\hyperref[sailRISCVfnzFRegStr]{#2}}{}% + \ifstrequal{#1}{GPRstr}{\hyperref[sailRISCVfnzGPRstr]{#2}}{}% + \ifstrequal{#1}{InterruptType_of_num}{\hyperref[sailRISCVfnzInterruptTypezyofzynum]{#2}}{}% + \ifstrequal{#1}{MAX}{\hyperref[sailRISCVfnzMAX]{#2}}{}% + \ifstrequal{#1}{MemoryOpResult_add_meta}{\hyperref[sailRISCVfnzMemoryOpResultzyaddzymeta]{#2}}{}% + \ifstrequal{#1}{MemoryOpResult_drop_meta}{\hyperref[sailRISCVfnzMemoryOpResultzydropzymeta]{#2}}{}% + \ifstrequal{#1}{Mk_Counteren}{\hyperref[sailRISCVfnzMkzyCounteren]{#2}}{}% + \ifstrequal{#1}{Mk_Counterin}{\hyperref[sailRISCVfnzMkzyCounterin]{#2}}{}% + \ifstrequal{#1}{Mk_Ext_PTE_Bits}{\hyperref[sailRISCVfnzMkzyExtzyPTEzyBits]{#2}}{}% + \ifstrequal{#1}{Mk_Fcsr}{\hyperref[sailRISCVfnzMkzyFcsr]{#2}}{}% + \ifstrequal{#1}{Mk_Mcause}{\hyperref[sailRISCVfnzMkzyMcause]{#2}}{}% + \ifstrequal{#1}{Mk_Medeleg}{\hyperref[sailRISCVfnzMkzyMedeleg]{#2}}{}% + \ifstrequal{#1}{Mk_Minterrupts}{\hyperref[sailRISCVfnzMkzyMinterrupts]{#2}}{}% + \ifstrequal{#1}{Mk_Misa}{\hyperref[sailRISCVfnzMkzyMisa]{#2}}{}% + \ifstrequal{#1}{Mk_Mstatus}{\hyperref[sailRISCVfnzMkzyMstatus]{#2}}{}% + \ifstrequal{#1}{Mk_Mtvec}{\hyperref[sailRISCVfnzMkzyMtvec]{#2}}{}% + \ifstrequal{#1}{Mk_PTE_Bits}{\hyperref[sailRISCVfnzMkzyPTEzyBits]{#2}}{}% + \ifstrequal{#1}{Mk_Pmpcfg_ent}{\hyperref[sailRISCVfnzMkzyPmpcfgzyent]{#2}}{}% + \ifstrequal{#1}{Mk_SV32_PTE}{\hyperref[sailRISCVfnzMkzySV32zyPTE]{#2}}{}% + \ifstrequal{#1}{Mk_SV32_Paddr}{\hyperref[sailRISCVfnzMkzySV32zyPaddr]{#2}}{}% + \ifstrequal{#1}{Mk_SV32_Vaddr}{\hyperref[sailRISCVfnzMkzySV32zyVaddr]{#2}}{}% + \ifstrequal{#1}{Mk_SV39_PTE}{\hyperref[sailRISCVfnzMkzySV39zyPTE]{#2}}{}% + \ifstrequal{#1}{Mk_SV39_Paddr}{\hyperref[sailRISCVfnzMkzySV39zyPaddr]{#2}}{}% + \ifstrequal{#1}{Mk_SV39_Vaddr}{\hyperref[sailRISCVfnzMkzySV39zyVaddr]{#2}}{}% + \ifstrequal{#1}{Mk_SV48_PTE}{\hyperref[sailRISCVfnzMkzySV48zyPTE]{#2}}{}% + \ifstrequal{#1}{Mk_SV48_Paddr}{\hyperref[sailRISCVfnzMkzySV48zyPaddr]{#2}}{}% + \ifstrequal{#1}{Mk_SV48_Vaddr}{\hyperref[sailRISCVfnzMkzySV48zyVaddr]{#2}}{}% + \ifstrequal{#1}{Mk_Satp32}{\hyperref[sailRISCVfnzMkzySatp32]{#2}}{}% + \ifstrequal{#1}{Mk_Satp64}{\hyperref[sailRISCVfnzMkzySatp64]{#2}}{}% + \ifstrequal{#1}{Mk_Sedeleg}{\hyperref[sailRISCVfnzMkzySedeleg]{#2}}{}% + \ifstrequal{#1}{Mk_Sinterrupts}{\hyperref[sailRISCVfnzMkzySinterrupts]{#2}}{}% + \ifstrequal{#1}{Mk_Sstatus}{\hyperref[sailRISCVfnzMkzySstatus]{#2}}{}% + \ifstrequal{#1}{Mk_Uinterrupts}{\hyperref[sailRISCVfnzMkzyUinterrupts]{#2}}{}% + \ifstrequal{#1}{Mk_Ustatus}{\hyperref[sailRISCVfnzMkzyUstatus]{#2}}{}% + \ifstrequal{#1}{Mk_ccsr}{\hyperref[sailRISCVfnzMkzyccsr]{#2}}{}% + \ifstrequal{#1}{Mk_htif_cmd}{\hyperref[sailRISCVfnzMkzyhtifzycmd]{#2}}{}% + \ifstrequal{#1}{PmpAddrMatchType_of_num}{\hyperref[sailRISCVfnzPmpAddrMatchTypezyofzynum]{#2}}{}% + \ifstrequal{#1}{Privilege_of_num}{\hyperref[sailRISCVfnzPrivilegezyofzynum]{#2}}{}% + \ifstrequal{#1}{RegStr}{\hyperref[sailRISCVfnzRegStr]{#2}}{}% + \ifstrequal{#1}{Retired_of_num}{\hyperref[sailRISCVfnzRetiredzyofzynum]{#2}}{}% + \ifstrequal{#1}{SATPMode_of_num}{\hyperref[sailRISCVfnzSATPModezyofzynum]{#2}}{}% + \ifstrequal{#1}{TrapVectorMode_of_num}{\hyperref[sailRISCVfnzTrapVectorModezyofzynum]{#2}}{}% + \ifstrequal{#1}{__ReadRAM_Meta}{\hyperref[sailRISCVfnzzyzyReadRAMzyMeta]{#2}}{}% + \ifstrequal{#1}{__WriteRAM_Meta}{\hyperref[sailRISCVfnzzyzyWriteRAMzyMeta]{#2}}{}% + \ifstrequal{#1}{__id}{\hyperref[sailRISCVfnzzyzyid]{#2}}{}% + \ifstrequal{#1}{_get_Counteren_CY}{\hyperref[sailRISCVfnzzygetzyCounterenzyCY]{#2}}{}% + \ifstrequal{#1}{_get_Counteren_HPM}{\hyperref[sailRISCVfnzzygetzyCounterenzyHPM]{#2}}{}% + \ifstrequal{#1}{_get_Counteren_IR}{\hyperref[sailRISCVfnzzygetzyCounterenzyIR]{#2}}{}% + \ifstrequal{#1}{_get_Counteren_TM}{\hyperref[sailRISCVfnzzygetzyCounterenzyTM]{#2}}{}% + \ifstrequal{#1}{_get_Counteren_bits}{\hyperref[sailRISCVfnzzygetzyCounterenzybits]{#2}}{}% + \ifstrequal{#1}{_get_Counterin_CY}{\hyperref[sailRISCVfnzzygetzyCounterinzyCY]{#2}}{}% + \ifstrequal{#1}{_get_Counterin_IR}{\hyperref[sailRISCVfnzzygetzyCounterinzyIR]{#2}}{}% + \ifstrequal{#1}{_get_Counterin_bits}{\hyperref[sailRISCVfnzzygetzyCounterinzybits]{#2}}{}% + \ifstrequal{#1}{_get_Ext_PTE_Bits_CapRead}{\hyperref[sailRISCVfnzzygetzyExtzyPTEzyBitszyCapRead]{#2}}{}% + \ifstrequal{#1}{_get_Ext_PTE_Bits_CapWrite}{\hyperref[sailRISCVfnzzygetzyExtzyPTEzyBitszyCapWrite]{#2}}{}% + \ifstrequal{#1}{_get_Ext_PTE_Bits_bits}{\hyperref[sailRISCVfnzzygetzyExtzyPTEzyBitszybits]{#2}}{}% + \ifstrequal{#1}{_get_Fcsr_FFLAGS}{\hyperref[sailRISCVfnzzygetzyFcsrzyFFLAGS]{#2}}{}% + \ifstrequal{#1}{_get_Fcsr_FRM}{\hyperref[sailRISCVfnzzygetzyFcsrzyFRM]{#2}}{}% + \ifstrequal{#1}{_get_Fcsr_bits}{\hyperref[sailRISCVfnzzygetzyFcsrzybits]{#2}}{}% + \ifstrequal{#1}{_get_Mcause_Cause}{\hyperref[sailRISCVfnzzygetzyMcausezyCause]{#2}}{}% + \ifstrequal{#1}{_get_Mcause_IsInterrupt}{\hyperref[sailRISCVfnzzygetzyMcausezyIsInterrupt]{#2}}{}% + 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\ifstrequal{#1}{_get_Medeleg_MEnvCall}{\hyperref[sailRISCVfnzzygetzyMedelegzyMEnvCall]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_SAMO_Access_Fault}{\hyperref[sailRISCVfnzzygetzyMedelegzySAMOzyAccesszyFault]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_SAMO_Addr_Align}{\hyperref[sailRISCVfnzzygetzyMedelegzySAMOzyAddrzyAlign]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_SAMO_Page_Fault}{\hyperref[sailRISCVfnzzygetzyMedelegzySAMOzyPagezyFault]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_SEnvCall}{\hyperref[sailRISCVfnzzygetzyMedelegzySEnvCall]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_UEnvCall}{\hyperref[sailRISCVfnzzygetzyMedelegzyUEnvCall]{#2}}{}% + \ifstrequal{#1}{_get_Medeleg_bits}{\hyperref[sailRISCVfnzzygetzyMedelegzybits]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_MEI}{\hyperref[sailRISCVfnzzygetzyMinterruptszyMEI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_MSI}{\hyperref[sailRISCVfnzzygetzyMinterruptszyMSI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_MTI}{\hyperref[sailRISCVfnzzygetzyMinterruptszyMTI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_SEI}{\hyperref[sailRISCVfnzzygetzyMinterruptszySEI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_SSI}{\hyperref[sailRISCVfnzzygetzyMinterruptszySSI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_STI}{\hyperref[sailRISCVfnzzygetzyMinterruptszySTI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_UEI}{\hyperref[sailRISCVfnzzygetzyMinterruptszyUEI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_USI}{\hyperref[sailRISCVfnzzygetzyMinterruptszyUSI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_UTI}{\hyperref[sailRISCVfnzzygetzyMinterruptszyUTI]{#2}}{}% + \ifstrequal{#1}{_get_Minterrupts_bits}{\hyperref[sailRISCVfnzzygetzyMinterruptszybits]{#2}}{}% + \ifstrequal{#1}{_get_Misa_A}{\hyperref[sailRISCVfnzzygetzyMisazyA]{#2}}{}% + \ifstrequal{#1}{_get_Misa_B}{\hyperref[sailRISCVfnzzygetzyMisazyB]{#2}}{}% + \ifstrequal{#1}{_get_Misa_C}{\hyperref[sailRISCVfnzzygetzyMisazyC]{#2}}{}% + \ifstrequal{#1}{_get_Misa_D}{\hyperref[sailRISCVfnzzygetzyMisazyD]{#2}}{}% + \ifstrequal{#1}{_get_Misa_E}{\hyperref[sailRISCVfnzzygetzyMisazyE]{#2}}{}% + \ifstrequal{#1}{_get_Misa_F}{\hyperref[sailRISCVfnzzygetzyMisazyF]{#2}}{}% + \ifstrequal{#1}{_get_Misa_G}{\hyperref[sailRISCVfnzzygetzyMisazyG]{#2}}{}% + \ifstrequal{#1}{_get_Misa_H}{\hyperref[sailRISCVfnzzygetzyMisazyH]{#2}}{}% + \ifstrequal{#1}{_get_Misa_I}{\hyperref[sailRISCVfnzzygetzyMisazyI]{#2}}{}% + \ifstrequal{#1}{_get_Misa_J}{\hyperref[sailRISCVfnzzygetzyMisazyJ]{#2}}{}% + \ifstrequal{#1}{_get_Misa_K}{\hyperref[sailRISCVfnzzygetzyMisazyK]{#2}}{}% + \ifstrequal{#1}{_get_Misa_L}{\hyperref[sailRISCVfnzzygetzyMisazyL]{#2}}{}% + \ifstrequal{#1}{_get_Misa_M}{\hyperref[sailRISCVfnzzygetzyMisazyM]{#2}}{}% + \ifstrequal{#1}{_get_Misa_MXL}{\hyperref[sailRISCVfnzzygetzyMisazyMXL]{#2}}{}% + \ifstrequal{#1}{_get_Misa_N}{\hyperref[sailRISCVfnzzygetzyMisazyN]{#2}}{}% + \ifstrequal{#1}{_get_Misa_O}{\hyperref[sailRISCVfnzzygetzyMisazyO]{#2}}{}% + \ifstrequal{#1}{_get_Misa_P}{\hyperref[sailRISCVfnzzygetzyMisazyP]{#2}}{}% + \ifstrequal{#1}{_get_Misa_Q}{\hyperref[sailRISCVfnzzygetzyMisazyQ]{#2}}{}% + \ifstrequal{#1}{_get_Misa_R}{\hyperref[sailRISCVfnzzygetzyMisazyR]{#2}}{}% + \ifstrequal{#1}{_get_Misa_S}{\hyperref[sailRISCVfnzzygetzyMisazyS]{#2}}{}% + \ifstrequal{#1}{_get_Misa_T}{\hyperref[sailRISCVfnzzygetzyMisazyT]{#2}}{}% + \ifstrequal{#1}{_get_Misa_U}{\hyperref[sailRISCVfnzzygetzyMisazyU]{#2}}{}% + \ifstrequal{#1}{_get_Misa_V}{\hyperref[sailRISCVfnzzygetzyMisazyV]{#2}}{}% + \ifstrequal{#1}{_get_Misa_W}{\hyperref[sailRISCVfnzzygetzyMisazyW]{#2}}{}% + \ifstrequal{#1}{_get_Misa_X}{\hyperref[sailRISCVfnzzygetzyMisazyX]{#2}}{}% + \ifstrequal{#1}{_get_Misa_Y}{\hyperref[sailRISCVfnzzygetzyMisazyY]{#2}}{}% + \ifstrequal{#1}{_get_Misa_Z}{\hyperref[sailRISCVfnzzygetzyMisazyZ]{#2}}{}% + \ifstrequal{#1}{_get_Misa_bits}{\hyperref[sailRISCVfnzzygetzyMisazybits]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_FS}{\hyperref[sailRISCVfnzzygetzyMstatuszyFS]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_MIE}{\hyperref[sailRISCVfnzzygetzyMstatuszyMIE]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_MPIE}{\hyperref[sailRISCVfnzzygetzyMstatuszyMPIE]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_MPP}{\hyperref[sailRISCVfnzzygetzyMstatuszyMPP]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_MPRV}{\hyperref[sailRISCVfnzzygetzyMstatuszyMPRV]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_MXR}{\hyperref[sailRISCVfnzzygetzyMstatuszyMXR]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_SD}{\hyperref[sailRISCVfnzzygetzyMstatuszySD]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_SIE}{\hyperref[sailRISCVfnzzygetzyMstatuszySIE]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_SPIE}{\hyperref[sailRISCVfnzzygetzyMstatuszySPIE]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_SPP}{\hyperref[sailRISCVfnzzygetzyMstatuszySPP]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_SUM}{\hyperref[sailRISCVfnzzygetzyMstatuszySUM]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_TSR}{\hyperref[sailRISCVfnzzygetzyMstatuszyTSR]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_TVM}{\hyperref[sailRISCVfnzzygetzyMstatuszyTVM]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_TW}{\hyperref[sailRISCVfnzzygetzyMstatuszyTW]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_UIE}{\hyperref[sailRISCVfnzzygetzyMstatuszyUIE]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_UPIE}{\hyperref[sailRISCVfnzzygetzyMstatuszyUPIE]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_XS}{\hyperref[sailRISCVfnzzygetzyMstatuszyXS]{#2}}{}% + \ifstrequal{#1}{_get_Mstatus_bits}{\hyperref[sailRISCVfnzzygetzyMstatuszybits]{#2}}{}% + \ifstrequal{#1}{_get_Mtvec_Base}{\hyperref[sailRISCVfnzzygetzyMtveczyBase]{#2}}{}% + \ifstrequal{#1}{_get_Mtvec_Mode}{\hyperref[sailRISCVfnzzygetzyMtveczyMode]{#2}}{}% + \ifstrequal{#1}{_get_Mtvec_bits}{\hyperref[sailRISCVfnzzygetzyMtveczybits]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_A}{\hyperref[sailRISCVfnzzygetzyPTEzyBitszyA]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_D}{\hyperref[sailRISCVfnzzygetzyPTEzyBitszyD]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_G}{\hyperref[sailRISCVfnzzygetzyPTEzyBitszyG]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_R}{\hyperref[sailRISCVfnzzygetzyPTEzyBitszyR]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_U}{\hyperref[sailRISCVfnzzygetzyPTEzyBitszyU]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_V}{\hyperref[sailRISCVfnzzygetzyPTEzyBitszyV]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_W}{\hyperref[sailRISCVfnzzygetzyPTEzyBitszyW]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_X}{\hyperref[sailRISCVfnzzygetzyPTEzyBitszyX]{#2}}{}% + \ifstrequal{#1}{_get_PTE_Bits_bits}{\hyperref[sailRISCVfnzzygetzyPTEzyBitszybits]{#2}}{}% + \ifstrequal{#1}{_get_Pmpcfg_ent_A}{\hyperref[sailRISCVfnzzygetzyPmpcfgzyentzyA]{#2}}{}% + \ifstrequal{#1}{_get_Pmpcfg_ent_L}{\hyperref[sailRISCVfnzzygetzyPmpcfgzyentzyL]{#2}}{}% + \ifstrequal{#1}{_get_Pmpcfg_ent_R}{\hyperref[sailRISCVfnzzygetzyPmpcfgzyentzyR]{#2}}{}% + \ifstrequal{#1}{_get_Pmpcfg_ent_W}{\hyperref[sailRISCVfnzzygetzyPmpcfgzyentzyW]{#2}}{}% + \ifstrequal{#1}{_get_Pmpcfg_ent_X}{\hyperref[sailRISCVfnzzygetzyPmpcfgzyentzyX]{#2}}{}% + \ifstrequal{#1}{_get_Pmpcfg_ent_bits}{\hyperref[sailRISCVfnzzygetzyPmpcfgzyentzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV32_PTE_BITS}{\hyperref[sailRISCVfnzzygetzySV32zyPTEzyBITS]{#2}}{}% + \ifstrequal{#1}{_get_SV32_PTE_PPNi}{\hyperref[sailRISCVfnzzygetzySV32zyPTEzyPPNi]{#2}}{}% + \ifstrequal{#1}{_get_SV32_PTE_RSW}{\hyperref[sailRISCVfnzzygetzySV32zyPTEzyRSW]{#2}}{}% + \ifstrequal{#1}{_get_SV32_PTE_bits}{\hyperref[sailRISCVfnzzygetzySV32zyPTEzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV32_Paddr_PPNi}{\hyperref[sailRISCVfnzzygetzySV32zyPaddrzyPPNi]{#2}}{}% + \ifstrequal{#1}{_get_SV32_Paddr_PgOfs}{\hyperref[sailRISCVfnzzygetzySV32zyPaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_get_SV32_Paddr_bits}{\hyperref[sailRISCVfnzzygetzySV32zyPaddrzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV32_Vaddr_PgOfs}{\hyperref[sailRISCVfnzzygetzySV32zyVaddrzyPgOfs]{#2}}{}% + \ifstrequal{#1}{_get_SV32_Vaddr_VPNi}{\hyperref[sailRISCVfnzzygetzySV32zyVaddrzyVPNi]{#2}}{}% + \ifstrequal{#1}{_get_SV32_Vaddr_bits}{\hyperref[sailRISCVfnzzygetzySV32zyVaddrzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV39_PTE_BITS}{\hyperref[sailRISCVfnzzygetzySV39zyPTEzyBITS]{#2}}{}% + \ifstrequal{#1}{_get_SV39_PTE_Ext}{\hyperref[sailRISCVfnzzygetzySV39zyPTEzyExt]{#2}}{}% + \ifstrequal{#1}{_get_SV39_PTE_PPNi}{\hyperref[sailRISCVfnzzygetzySV39zyPTEzyPPNi]{#2}}{}% + \ifstrequal{#1}{_get_SV39_PTE_RSW}{\hyperref[sailRISCVfnzzygetzySV39zyPTEzyRSW]{#2}}{}% + \ifstrequal{#1}{_get_SV39_PTE_bits}{\hyperref[sailRISCVfnzzygetzySV39zyPTEzybits]{#2}}{}% + \ifstrequal{#1}{_get_SV39_Paddr_PPNi}{\hyperref[sailRISCVfnzzygetzySV39zyPaddrzyPPNi]{#2}}{}% + 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\ifstrequal{#1}{hex_bits_25_backwards}{\hyperref[sailRISCVfnzhexzybitszy25zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_25_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy25zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_25_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy25zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_26_backwards}{\hyperref[sailRISCVfnzhexzybitszy26zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_26_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy26zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_26_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy26zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_27_backwards}{\hyperref[sailRISCVfnzhexzybitszy27zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_27_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy27zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_27_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy27zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_28_backwards}{\hyperref[sailRISCVfnzhexzybitszy28zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_28_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy28zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_28_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy28zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_29_backwards}{\hyperref[sailRISCVfnzhexzybitszy29zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_29_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy29zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_29_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy29zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_2_backwards}{\hyperref[sailRISCVfnzhexzybitszy2zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_2_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy2zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_2_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy2zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_30_backwards}{\hyperref[sailRISCVfnzhexzybitszy30zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_30_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy30zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_30_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy30zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_31_backwards}{\hyperref[sailRISCVfnzhexzybitszy31zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_31_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy31zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_31_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy31zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_32_backwards}{\hyperref[sailRISCVfnzhexzybitszy32zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_32_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy32zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_32_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy32zyforwardszymatches]{#2}}{}% + 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\ifstrequal{#1}{hex_bits_4_backwards}{\hyperref[sailRISCVfnzhexzybitszy4zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_4_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy4zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_4_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy4zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_5_backwards}{\hyperref[sailRISCVfnzhexzybitszy5zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_5_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy5zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_5_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy5zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_64_backwards}{\hyperref[sailRISCVfnzhexzybitszy64zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_64_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy64zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_64_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy64zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_6_backwards}{\hyperref[sailRISCVfnzhexzybitszy6zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_6_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy6zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_6_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy6zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_7_backwards}{\hyperref[sailRISCVfnzhexzybitszy7zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_7_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy7zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_7_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy7zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_8_backwards}{\hyperref[sailRISCVfnzhexzybitszy8zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_8_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy8zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_8_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy8zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_9_backwards}{\hyperref[sailRISCVfnzhexzybitszy9zybackwards]{#2}}{}% + \ifstrequal{#1}{hex_bits_9_backwards_matches}{\hyperref[sailRISCVfnzhexzybitszy9zybackwardszymatches]{#2}}{}% + \ifstrequal{#1}{hex_bits_9_forwards_matches}{\hyperref[sailRISCVfnzhexzybitszy9zyforwardszymatches]{#2}}{}% + \ifstrequal{#1}{htif_load}{\hyperref[sailRISCVfnzhtifzyload]{#2}}{}% + \ifstrequal{#1}{htif_store}{\hyperref[sailRISCVfnzhtifzystore]{#2}}{}% + \ifstrequal{#1}{htif_tick}{\hyperref[sailRISCVfnzhtifzytick]{#2}}{}% + \ifstrequal{#1}{in32BitMode}{\hyperref[sailRISCVfnzin32BitMode]{#2}}{}% + \ifstrequal{#1}{inCapBounds}{\hyperref[sailRISCVfnzinCapBounds]{#2}}{}% + \ifstrequal{#1}{incCapOffset}{\hyperref[sailRISCVfnzincCapOffset]{#2}}{}% + \ifstrequal{#1}{init_base_regs}{\hyperref[sailRISCVfnzinitzybasezyregs]{#2}}{}% + \ifstrequal{#1}{init_fdext_regs}{\hyperref[sailRISCVfnzinitzyfdextzyregs]{#2}}{}% + \ifstrequal{#1}{init_model}{\hyperref[sailRISCVfnzinitzymodel]{#2}}{}% + \ifstrequal{#1}{init_platform}{\hyperref[sailRISCVfnzinitzyplatform]{#2}}{}% + \ifstrequal{#1}{init_pmp}{\hyperref[sailRISCVfnzinitzypmp]{#2}}{}% + \ifstrequal{#1}{init_sys}{\hyperref[sailRISCVfnzinitzysys]{#2}}{}% + \ifstrequal{#1}{init_vmem}{\hyperref[sailRISCVfnzinitzyvmem]{#2}}{}% + \ifstrequal{#1}{init_vmem_sv39}{\hyperref[sailRISCVfnzinitzyvmemzysv39]{#2}}{}% + \ifstrequal{#1}{init_vmem_sv48}{\hyperref[sailRISCVfnzinitzyvmemzysv48]{#2}}{}% + \ifstrequal{#1}{initial_analysis}{\hyperref[sailRISCVfnzinitialzyanalysis]{#2}}{}% + \ifstrequal{#1}{int_to_cap}{\hyperref[sailRISCVfnzintzytozycap]{#2}}{}% + \ifstrequal{#1}{internal_error}{\hyperref[sailRISCVfnzinternalzyerror]{#2}}{}% + \ifstrequal{#1}{interruptType_to_bits}{\hyperref[sailRISCVfnzinterruptTypezytozybits]{#2}}{}% + \ifstrequal{#1}{invalidateCap}{\hyperref[sailRISCVfnzinvalidateCap]{#2}}{}% + \ifstrequal{#1}{iop_of_num}{\hyperref[sailRISCVfnziopzyofzynum]{#2}}{}% + \ifstrequal{#1}{isCapSealed}{\hyperref[sailRISCVfnzisCapSealed]{#2}}{}% + \ifstrequal{#1}{isInvalidPTE}{\hyperref[sailRISCVfnzisInvalidPTE]{#2}}{}% + \ifstrequal{#1}{isPTEPtr}{\hyperref[sailRISCVfnzisPTEPtr]{#2}}{}% + \ifstrequal{#1}{isRVC}{\hyperref[sailRISCVfnzisRVC]{#2}}{}% + \ifstrequal{#1}{isValidSv39Addr}{\hyperref[sailRISCVfnzisValidSv39Addr]{#2}}{}% + \ifstrequal{#1}{isValidSv48Addr}{\hyperref[sailRISCVfnzisValidSv48Addr]{#2}}{}% + \ifstrequal{#1}{is_CSR_defined}{\hyperref[sailRISCVfnziszyCSRzydefined]{#2}}{}% + \ifstrequal{#1}{is_RV32D_or_RV64D}{\hyperref[sailRISCVfnziszyRV32DzyorzyRV64D]{#2}}{}% + \ifstrequal{#1}{is_RV32F_or_RV64F}{\hyperref[sailRISCVfnziszyRV32FzyorzyRV64F]{#2}}{}% + \ifstrequal{#1}{is_RV64D}{\hyperref[sailRISCVfnziszyRV64D]{#2}}{}% + \ifstrequal{#1}{is_RV64F}{\hyperref[sailRISCVfnziszyRV64F]{#2}}{}% + \ifstrequal{#1}{is_aligned_addr}{\hyperref[sailRISCVfnziszyalignedzyaddr]{#2}}{}% + \ifstrequal{#1}{is_none}{\hyperref[sailRISCVfnziszynone]{#2}}{}% + \ifstrequal{#1}{is_some}{\hyperref[sailRISCVfnziszysome]{#2}}{}% + \ifstrequal{#1}{legalize_ccsr}{\hyperref[sailRISCVfnzlegalizzezyccsr]{#2}}{}% + \ifstrequal{#1}{legalize_epcc}{\hyperref[sailRISCVfnzlegalizzezyepcc]{#2}}{}% + \ifstrequal{#1}{legalize_mcounteren}{\hyperref[sailRISCVfnzlegalizzezymcounteren]{#2}}{}% + \ifstrequal{#1}{legalize_mcountinhibit}{\hyperref[sailRISCVfnzlegalizzezymcountinhibit]{#2}}{}% + \ifstrequal{#1}{legalize_medeleg}{\hyperref[sailRISCVfnzlegalizzezymedeleg]{#2}}{}% + \ifstrequal{#1}{legalize_mideleg}{\hyperref[sailRISCVfnzlegalizzezymideleg]{#2}}{}% + \ifstrequal{#1}{legalize_mie}{\hyperref[sailRISCVfnzlegalizzezymie]{#2}}{}% + \ifstrequal{#1}{legalize_mip}{\hyperref[sailRISCVfnzlegalizzezymip]{#2}}{}% + \ifstrequal{#1}{legalize_misa}{\hyperref[sailRISCVfnzlegalizzezymisa]{#2}}{}% + \ifstrequal{#1}{legalize_mstatus}{\hyperref[sailRISCVfnzlegalizzezymstatus]{#2}}{}% + \ifstrequal{#1}{legalize_satp}{\hyperref[sailRISCVfnzlegalizzezysatp]{#2}}{}% + \ifstrequal{#1}{legalize_satp32}{\hyperref[sailRISCVfnzlegalizzezysatp32]{#2}}{}% + \ifstrequal{#1}{legalize_satp64}{\hyperref[sailRISCVfnzlegalizzezysatp64]{#2}}{}% + \ifstrequal{#1}{legalize_scounteren}{\hyperref[sailRISCVfnzlegalizzezyscounteren]{#2}}{}% + \ifstrequal{#1}{legalize_sedeleg}{\hyperref[sailRISCVfnzlegalizzezysedeleg]{#2}}{}% + \ifstrequal{#1}{legalize_sie}{\hyperref[sailRISCVfnzlegalizzezysie]{#2}}{}% + \ifstrequal{#1}{legalize_sip}{\hyperref[sailRISCVfnzlegalizzezysip]{#2}}{}% + \ifstrequal{#1}{legalize_sstatus}{\hyperref[sailRISCVfnzlegalizzezysstatus]{#2}}{}% + \ifstrequal{#1}{legalize_tcc}{\hyperref[sailRISCVfnzlegalizzezytcc]{#2}}{}% + \ifstrequal{#1}{legalize_tvec}{\hyperref[sailRISCVfnzlegalizzezytvec]{#2}}{}% + \ifstrequal{#1}{legalize_uie}{\hyperref[sailRISCVfnzlegalizzezyuie]{#2}}{}% + \ifstrequal{#1}{legalize_uip}{\hyperref[sailRISCVfnzlegalizzezyuip]{#2}}{}% + \ifstrequal{#1}{legalize_ustatus}{\hyperref[sailRISCVfnzlegalizzezyustatus]{#2}}{}% + \ifstrequal{#1}{legalize_xepc}{\hyperref[sailRISCVfnzlegalizzezyxepc]{#2}}{}% + \ifstrequal{#1}{lift_sie}{\hyperref[sailRISCVfnzliftzysie]{#2}}{}% + \ifstrequal{#1}{lift_sip}{\hyperref[sailRISCVfnzliftzysip]{#2}}{}% + \ifstrequal{#1}{lift_sstatus}{\hyperref[sailRISCVfnzliftzysstatus]{#2}}{}% + \ifstrequal{#1}{lift_uie}{\hyperref[sailRISCVfnzliftzyuie]{#2}}{}% + \ifstrequal{#1}{lift_uip}{\hyperref[sailRISCVfnzliftzyuip]{#2}}{}% + \ifstrequal{#1}{lift_ustatus}{\hyperref[sailRISCVfnzliftzyustatus]{#2}}{}% + \ifstrequal{#1}{lookup_TLB39}{\hyperref[sailRISCVfnzlookupzyTLB39]{#2}}{}% + \ifstrequal{#1}{lookup_TLB48}{\hyperref[sailRISCVfnzlookupzyTLB48]{#2}}{}% + \ifstrequal{#1}{loop}{\hyperref[sailRISCVfnzloop]{#2}}{}% + \ifstrequal{#1}{lower_mie}{\hyperref[sailRISCVfnzlowerzymie]{#2}}{}% + \ifstrequal{#1}{lower_mip}{\hyperref[sailRISCVfnzlowerzymip]{#2}}{}% + \ifstrequal{#1}{lower_mstatus}{\hyperref[sailRISCVfnzlowerzymstatus]{#2}}{}% + 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\ifstrequal{#1}{mem_write_ea_cap}{\hyperref[sailRISCVfnzmemzywritezyeazycap]{#2}}{}% + \ifstrequal{#1}{mem_write_value}{\hyperref[sailRISCVfnzmemzywritezyvalue]{#2}}{}% + \ifstrequal{#1}{mem_write_value_meta}{\hyperref[sailRISCVfnzmemzywritezyvaluezymeta]{#2}}{}% + \ifstrequal{#1}{min_instruction_bytes}{\hyperref[sailRISCVfnzminzyinstructionzybytes]{#2}}{}% + \ifstrequal{#1}{mmio_read}{\hyperref[sailRISCVfnzmmiozyread]{#2}}{}% + \ifstrequal{#1}{mmio_write}{\hyperref[sailRISCVfnzmmiozywrite]{#2}}{}% + \ifstrequal{#1}{n_leading_spaces}{\hyperref[sailRISCVfnznzyleadingzyspaces]{#2}}{}% + \ifstrequal{#1}{nan_box}{\hyperref[sailRISCVfnznanzybox]{#2}}{}% + \ifstrequal{#1}{nan_unbox}{\hyperref[sailRISCVfnznanzyunbox]{#2}}{}% + \ifstrequal{#1}{negate_D}{\hyperref[sailRISCVfnznegatezyD]{#2}}{}% + \ifstrequal{#1}{negate_S}{\hyperref[sailRISCVfnznegatezyS]{#2}}{}% + \ifstrequal{#1}{neq_anything}{\hyperref[sailRISCVfnzneqzyanything]{#2}}{}% + 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\ifstrequal{#1}{num_of_rop}{\hyperref[sailRISCVfnznumzyofzyrop]{#2}}{}% + \ifstrequal{#1}{num_of_ropw}{\hyperref[sailRISCVfnznumzyofzyropw]{#2}}{}% + \ifstrequal{#1}{num_of_rounding_mode}{\hyperref[sailRISCVfnznumzyofzyroundingzymode]{#2}}{}% + \ifstrequal{#1}{num_of_sop}{\hyperref[sailRISCVfnznumzyofzysop]{#2}}{}% + \ifstrequal{#1}{num_of_sopw}{\hyperref[sailRISCVfnznumzyofzysopw]{#2}}{}% + \ifstrequal{#1}{num_of_trans_kind}{\hyperref[sailRISCVfnznumzyofzytranszykind]{#2}}{}% + \ifstrequal{#1}{num_of_uop}{\hyperref[sailRISCVfnznumzyofzyuop]{#2}}{}% + \ifstrequal{#1}{num_of_word_width}{\hyperref[sailRISCVfnznumzyofzywordzywidth]{#2}}{}% + \ifstrequal{#1}{num_of_write_kind}{\hyperref[sailRISCVfnznumzyofzywritezykind]{#2}}{}% + \ifstrequal{#1}{nvFlag}{\hyperref[sailRISCVfnznvFlag]{#2}}{}% + \ifstrequal{#1}{nxFlag}{\hyperref[sailRISCVfnznxFlag]{#2}}{}% + \ifstrequal{#1}{ofFlag}{\hyperref[sailRISCVfnzofFlag]{#2}}{}% + \ifstrequal{#1}{ones}{\hyperref[sailRISCVfnzones]{#2}}{}% + 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\ifstrequal{#1}{process_fload32}{\hyperref[sailRISCVfnzprocesszyfload32]{#2}}{}% + \ifstrequal{#1}{process_fload64}{\hyperref[sailRISCVfnzprocesszyfload64]{#2}}{}% + \ifstrequal{#1}{process_fstore}{\hyperref[sailRISCVfnzprocesszyfstore]{#2}}{}% + \ifstrequal{#1}{process_load}{\hyperref[sailRISCVfnzprocesszyload]{#2}}{}% + \ifstrequal{#1}{process_loadres}{\hyperref[sailRISCVfnzprocesszyloadres]{#2}}{}% + \ifstrequal{#1}{ptw_error_to_str}{\hyperref[sailRISCVfnzptwzyerrorzytozystr]{#2}}{}% + \ifstrequal{#1}{rC}{\hyperref[sailRISCVfnzrC]{#2}}{}% + \ifstrequal{#1}{rC_bits}{\hyperref[sailRISCVfnzrCzybits]{#2}}{}% + \ifstrequal{#1}{rF}{\hyperref[sailRISCVfnzrF]{#2}}{}% + \ifstrequal{#1}{rF_bits}{\hyperref[sailRISCVfnzrFzybits]{#2}}{}% + \ifstrequal{#1}{rX}{\hyperref[sailRISCVfnzrX]{#2}}{}% + \ifstrequal{#1}{rX_bits}{\hyperref[sailRISCVfnzrXzybits]{#2}}{}% + \ifstrequal{#1}{readCSR}{\hyperref[sailRISCVfnzreadCSR]{#2}}{}% + \ifstrequal{#1}{read_kind_of_flags}{\hyperref[sailRISCVfnzreadzykindzyofzyflags]{#2}}{}% + \ifstrequal{#1}{read_kind_of_num}{\hyperref[sailRISCVfnzreadzykindzyofzynum]{#2}}{}% + \ifstrequal{#1}{read_ram}{\hyperref[sailRISCVfnzreadzyram]{#2}}{}% + \ifstrequal{#1}{reg_name_abi}{\hyperref[sailRISCVfnzregzynamezyabi]{#2}}{}% + \ifstrequal{#1}{regidx_to_regno}{\hyperref[sailRISCVfnzregidxzytozyregno]{#2}}{}% + \ifstrequal{#1}{regval_from_reg}{\hyperref[sailRISCVfnzregvalzyfromzyreg]{#2}}{}% + \ifstrequal{#1}{regval_into_reg}{\hyperref[sailRISCVfnzregvalzyintozyreg]{#2}}{}% + \ifstrequal{#1}{retire_instruction}{\hyperref[sailRISCVfnzretirezyinstruction]{#2}}{}% + \ifstrequal{#1}{riscv_f32Add}{\hyperref[sailRISCVfnzriscvzyf32Add]{#2}}{}% + \ifstrequal{#1}{riscv_f32Div}{\hyperref[sailRISCVfnzriscvzyf32Div]{#2}}{}% + \ifstrequal{#1}{riscv_f32Eq}{\hyperref[sailRISCVfnzriscvzyf32Eq]{#2}}{}% + \ifstrequal{#1}{riscv_f32Le}{\hyperref[sailRISCVfnzriscvzyf32Le]{#2}}{}% + \ifstrequal{#1}{riscv_f32Lt}{\hyperref[sailRISCVfnzriscvzyf32Lt]{#2}}{}% + \ifstrequal{#1}{riscv_f32Mul}{\hyperref[sailRISCVfnzriscvzyf32Mul]{#2}}{}% + \ifstrequal{#1}{riscv_f32MulAdd}{\hyperref[sailRISCVfnzriscvzyf32MulAdd]{#2}}{}% + \ifstrequal{#1}{riscv_f32Sqrt}{\hyperref[sailRISCVfnzriscvzyf32Sqrt]{#2}}{}% + \ifstrequal{#1}{riscv_f32Sub}{\hyperref[sailRISCVfnzriscvzyf32Sub]{#2}}{}% + \ifstrequal{#1}{riscv_f32ToF64}{\hyperref[sailRISCVfnzriscvzyf32ToF64]{#2}}{}% + \ifstrequal{#1}{riscv_f32ToI32}{\hyperref[sailRISCVfnzriscvzyf32ToI32]{#2}}{}% + \ifstrequal{#1}{riscv_f32ToI64}{\hyperref[sailRISCVfnzriscvzyf32ToI64]{#2}}{}% + \ifstrequal{#1}{riscv_f32ToUi32}{\hyperref[sailRISCVfnzriscvzyf32ToUi32]{#2}}{}% + \ifstrequal{#1}{riscv_f32ToUi64}{\hyperref[sailRISCVfnzriscvzyf32ToUi64]{#2}}{}% + \ifstrequal{#1}{riscv_f64Add}{\hyperref[sailRISCVfnzriscvzyf64Add]{#2}}{}% + \ifstrequal{#1}{riscv_f64Div}{\hyperref[sailRISCVfnzriscvzyf64Div]{#2}}{}% + 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\ifstrequal{#1}{rvfi_trap}{\hyperref[sailRISCVfnzrvfizytrap]{#2}}{}% + \ifstrequal{#1}{rvfi_wX}{\hyperref[sailRISCVfnzrvfizywX]{#2}}{}% + \ifstrequal{#1}{rvfi_write}{\hyperref[sailRISCVfnzrvfizywrite]{#2}}{}% + \ifstrequal{#1}{sail_mask}{\hyperref[sailRISCVfnzsailzymask]{#2}}{}% + \ifstrequal{#1}{sail_ones}{\hyperref[sailRISCVfnzsailzyones]{#2}}{}% + \ifstrequal{#1}{satp64Mode_of_bits}{\hyperref[sailRISCVfnzsatp64Modezyofzybits]{#2}}{}% + \ifstrequal{#1}{sealCap}{\hyperref[sailRISCVfnzsealCap]{#2}}{}% + \ifstrequal{#1}{select_instr_or_fcsr_rm}{\hyperref[sailRISCVfnzselectzyinstrzyorzyfcsrzyrm]{#2}}{}% + \ifstrequal{#1}{setCapAddr}{\hyperref[sailRISCVfnzsetCapAddr]{#2}}{}% + \ifstrequal{#1}{setCapBounds}{\hyperref[sailRISCVfnzsetCapBounds]{#2}}{}% + \ifstrequal{#1}{setCapFlags}{\hyperref[sailRISCVfnzsetCapFlags]{#2}}{}% + \ifstrequal{#1}{setCapOffset}{\hyperref[sailRISCVfnzsetCapOffset]{#2}}{}% + \ifstrequal{#1}{setCapOffsetOrNull}{\hyperref[sailRISCVfnzsetCapOffsetOrNull]{#2}}{}% + \ifstrequal{#1}{setCapPerms}{\hyperref[sailRISCVfnzsetCapPerms]{#2}}{}% + \ifstrequal{#1}{set_mstatus_SXL}{\hyperref[sailRISCVfnzsetzymstatuszySXL]{#2}}{}% + \ifstrequal{#1}{set_mstatus_UXL}{\hyperref[sailRISCVfnzsetzymstatuszyUXL]{#2}}{}% + \ifstrequal{#1}{set_mtvec}{\hyperref[sailRISCVfnzsetzymtvec]{#2}}{}% + \ifstrequal{#1}{set_next_pc}{\hyperref[sailRISCVfnzsetzynextzypc]{#2}}{}% + \ifstrequal{#1}{set_sstatus_UXL}{\hyperref[sailRISCVfnzsetzysstatuszyUXL]{#2}}{}% + \ifstrequal{#1}{set_stvec}{\hyperref[sailRISCVfnzsetzystvec]{#2}}{}% + \ifstrequal{#1}{set_utvec}{\hyperref[sailRISCVfnzsetzyutvec]{#2}}{}% + \ifstrequal{#1}{set_xret_target}{\hyperref[sailRISCVfnzsetzyxretzytarget]{#2}}{}% + \ifstrequal{#1}{shift_right_arith32}{\hyperref[sailRISCVfnzshiftzyrightzyarith32]{#2}}{}% + \ifstrequal{#1}{shift_right_arith64}{\hyperref[sailRISCVfnzshiftzyrightzyarith64]{#2}}{}% + \ifstrequal{#1}{slice_mask}{\hyperref[sailRISCVfnzslicezymask]{#2}}{}% + \ifstrequal{#1}{sop_of_num}{\hyperref[sailRISCVfnzsopzyofzynum]{#2}}{}% + \ifstrequal{#1}{sopw_of_num}{\hyperref[sailRISCVfnzsopwzyofzynum]{#2}}{}% + \ifstrequal{#1}{spc_backwards}{\hyperref[sailRISCVfnzspczybackwards]{#2}}{}% + \ifstrequal{#1}{spc_forwards}{\hyperref[sailRISCVfnzspczyforwards]{#2}}{}% + \ifstrequal{#1}{spc_matches_prefix}{\hyperref[sailRISCVfnzspczymatcheszyprefix]{#2}}{}% + \ifstrequal{#1}{step}{\hyperref[sailRISCVfnzstep]{#2}}{}% + \ifstrequal{#1}{string_of_bit}{\hyperref[sailRISCVfnzstringzyofzybit]{#2}}{}% + \ifstrequal{#1}{string_of_capex}{\hyperref[sailRISCVfnzstringzyofzycapex]{#2}}{}% + \ifstrequal{#1}{tag_addr_to_addr}{\hyperref[sailRISCVfnztagzyaddrzytozyaddr]{#2}}{}% + \ifstrequal{#1}{tick_clock}{\hyperref[sailRISCVfnztickzyclock]{#2}}{}% + \ifstrequal{#1}{tick_pc}{\hyperref[sailRISCVfnztickzypc]{#2}}{}% + \ifstrequal{#1}{tick_platform}{\hyperref[sailRISCVfnztickzyplatform]{#2}}{}% + \ifstrequal{#1}{to_bits}{\hyperref[sailRISCVfnztozybits]{#2}}{}% + \ifstrequal{#1}{trans_kind_of_num}{\hyperref[sailRISCVfnztranszykindzyofzynum]{#2}}{}% + \ifstrequal{#1}{translate39}{\hyperref[sailRISCVfnztranslate39]{#2}}{}% + \ifstrequal{#1}{translate48}{\hyperref[sailRISCVfnztranslate48]{#2}}{}% + \ifstrequal{#1}{translateAddr}{\hyperref[sailRISCVfnztranslateAddr]{#2}}{}% + \ifstrequal{#1}{translationException}{\hyperref[sailRISCVfnztranslationException]{#2}}{}% + \ifstrequal{#1}{translationMode}{\hyperref[sailRISCVfnztranslationMode]{#2}}{}% + \ifstrequal{#1}{trapVectorMode_of_bits}{\hyperref[sailRISCVfnztrapVectorModezyofzybits]{#2}}{}% + \ifstrequal{#1}{trap_handler}{\hyperref[sailRISCVfnztrapzyhandler]{#2}}{}% + \ifstrequal{#1}{tval}{\hyperref[sailRISCVfnztval]{#2}}{}% + \ifstrequal{#1}{tvec_addr}{\hyperref[sailRISCVfnztveczyaddr]{#2}}{}% + \ifstrequal{#1}{ufFlag}{\hyperref[sailRISCVfnzufFlag]{#2}}{}% + \ifstrequal{#1}{unsealCap}{\hyperref[sailRISCVfnzunsealCap]{#2}}{}% + \ifstrequal{#1}{uop_of_num}{\hyperref[sailRISCVfnzuopzyofzynum]{#2}}{}% + \ifstrequal{#1}{update_PTE_Bits}{\hyperref[sailRISCVfnzupdatezyPTEzyBits]{#2}}{}% + \ifstrequal{#1}{update_softfloat_fflags}{\hyperref[sailRISCVfnzupdatezysoftfloatzyfflags]{#2}}{}% + \ifstrequal{#1}{wC}{\hyperref[sailRISCVfnzwC]{#2}}{}% + \ifstrequal{#1}{wC_bits}{\hyperref[sailRISCVfnzwCzybits]{#2}}{}% + \ifstrequal{#1}{wF}{\hyperref[sailRISCVfnzwF]{#2}}{}% + \ifstrequal{#1}{wF_bits}{\hyperref[sailRISCVfnzwFzybits]{#2}}{}% + \ifstrequal{#1}{wX}{\hyperref[sailRISCVfnzwX]{#2}}{}% + \ifstrequal{#1}{wX_bits}{\hyperref[sailRISCVfnzwXzybits]{#2}}{}% + \ifstrequal{#1}{walk39}{\hyperref[sailRISCVfnzwalk39]{#2}}{}% + \ifstrequal{#1}{walk48}{\hyperref[sailRISCVfnzwalk48]{#2}}{}% + \ifstrequal{#1}{within_clint}{\hyperref[sailRISCVfnzwithinzyclint]{#2}}{}% + \ifstrequal{#1}{within_htif_readable}{\hyperref[sailRISCVfnzwithinzyhtifzyreadable]{#2}}{}% + \ifstrequal{#1}{within_htif_writable}{\hyperref[sailRISCVfnzwithinzyhtifzywritable]{#2}}{}% + \ifstrequal{#1}{within_mmio_readable}{\hyperref[sailRISCVfnzwithinzymmiozyreadable]{#2}}{}% + \ifstrequal{#1}{within_mmio_writable}{\hyperref[sailRISCVfnzwithinzymmiozywritable]{#2}}{}% + \ifstrequal{#1}{within_phys_mem}{\hyperref[sailRISCVfnzwithinzyphyszymem]{#2}}{}% + \ifstrequal{#1}{word_width_bytes}{\hyperref[sailRISCVfnzwordzywidthzybytes]{#2}}{}% + \ifstrequal{#1}{word_width_of_num}{\hyperref[sailRISCVfnzwordzywidthzyofzynum]{#2}}{}% + \ifstrequal{#1}{writeCSR}{\hyperref[sailRISCVfnzwriteCSR]{#2}}{}% + \ifstrequal{#1}{write_TLB39}{\hyperref[sailRISCVfnzwritezyTLB39]{#2}}{}% + \ifstrequal{#1}{write_TLB48}{\hyperref[sailRISCVfnzwritezyTLB48]{#2}}{}% + \ifstrequal{#1}{write_fflags}{\hyperref[sailRISCVfnzwritezyfflags]{#2}}{}% + \ifstrequal{#1}{write_kind_of_num}{\hyperref[sailRISCVfnzwritezykindzyofzynum]{#2}}{}% + \ifstrequal{#1}{write_ram}{\hyperref[sailRISCVfnzwritezyram]{#2}}{}% + \ifstrequal{#1}{write_ram_ea}{\hyperref[sailRISCVfnzwritezyramzyea]{#2}}{}% + \ifstrequal{#1}{zeros_implicit}{\hyperref[sailRISCVfnzzzeroszyimplicit]{#2}}{}% + \ifstrequal{#1}{(operator <=_u)}{\hyperref[sailRISCVfnzz8operatorz0zIzJzyuz9]{#2}}{}% + \ifstrequal{#1}{(operator <_s)}{\hyperref[sailRISCVfnzz8operatorz0zIzysz9]{#2}}{}% + \ifstrequal{#1}{(operator <_u)}{\hyperref[sailRISCVfnzz8operatorz0zIzyuz9]{#2}}{}% + \ifstrequal{#1}{(operator >=_s)}{\hyperref[sailRISCVfnzz8operatorz0zKzJzysz9]{#2}}{}% + \ifstrequal{#1}{(operator >=_u)}{\hyperref[sailRISCVfnzz8operatorz0zKzJzyuz9]{#2}}{}} + +\newcommand{\sailRISCVtype}[1]{ + \ifstrequal{#1}{AccessType}{\sailRISCVtypeAccessType}{}% + \ifstrequal{#1}{Architecture}{\sailRISCVtypeArchitecture}{}% + \ifstrequal{#1}{CPtrCmpOp}{\sailRISCVtypeCPtrCmpOp}{}% + \ifstrequal{#1}{CapAddrBits}{\sailRISCVtypeCapAddrBits}{}% + \ifstrequal{#1}{CapAddrInt}{\sailRISCVtypeCapAddrInt}{}% + \ifstrequal{#1}{CapBits}{\sailRISCVtypeCapBits}{}% + \ifstrequal{#1}{CapEx}{\sailRISCVtypeCapEx}{}% + \ifstrequal{#1}{CapFlagsBits}{\sailRISCVtypeCapFlagsBits}{}% + \ifstrequal{#1}{CapLen}{\sailRISCVtypeCapLen}{}% + \ifstrequal{#1}{CapLenBits}{\sailRISCVtypeCapLenBits}{}% + \ifstrequal{#1}{CapPermsBits}{\sailRISCVtypeCapPermsBits}{}% + \ifstrequal{#1}{Capability}{\sailRISCVtypeCapability}{}% + \ifstrequal{#1}{ClearRegSet}{\sailRISCVtypeClearRegSet}{}% + \ifstrequal{#1}{Counteren}{\sailRISCVtypeCounteren}{}% + \ifstrequal{#1}{Counterin}{\sailRISCVtypeCounterin}{}% + \ifstrequal{#1}{ExceptionType}{\sailRISCVtypeExceptionType}{}% + \ifstrequal{#1}{ExtStatus}{\sailRISCVtypeExtStatus}{}% + \ifstrequal{#1}{Ext\_ControlAddr\_Check}{\sailRISCVtypeExtControlAddrCheck}{}% + \ifstrequal{#1}{Ext\_DataAddr\_Check}{\sailRISCVtypeExtDataAddrCheck}{}% + \ifstrequal{#1}{Ext\_FetchAddr\_Check}{\sailRISCVtypeExtFetchAddrCheck}{}% + \ifstrequal{#1}{Ext\_PTE\_Bits}{\sailRISCVtypeExtPTEBits}{}% + \ifstrequal{#1}{Fcsr}{\sailRISCVtypeFcsr}{}% + \ifstrequal{#1}{FetchResult}{\sailRISCVtypeFetchResult}{}% + \ifstrequal{#1}{InterruptType}{\sailRISCVtypeInterruptType}{}% + \ifstrequal{#1}{Mcause}{\sailRISCVtypeMcause}{}% + \ifstrequal{#1}{Medeleg}{\sailRISCVtypeMedeleg}{}% + \ifstrequal{#1}{MemoryOpResult}{\sailRISCVtypeMemoryOpResult}{}% + \ifstrequal{#1}{Minterrupts}{\sailRISCVtypeMinterrupts}{}% + \ifstrequal{#1}{Misa}{\sailRISCVtypeMisa}{}% + \ifstrequal{#1}{Mstatus}{\sailRISCVtypeMstatus}{}% + \ifstrequal{#1}{Mtvec}{\sailRISCVtypeMtvec}{}% + \ifstrequal{#1}{PTE\_Bits}{\sailRISCVtypePTEBits}{}% + \ifstrequal{#1}{PTE\_Check}{\sailRISCVtypePTECheck}{}% + \ifstrequal{#1}{PTW\_Error}{\sailRISCVtypePTWError}{}% + \ifstrequal{#1}{PTW\_Result}{\sailRISCVtypePTWResult}{}% + \ifstrequal{#1}{PmpAddrMatchType}{\sailRISCVtypePmpAddrMatchType}{}% + \ifstrequal{#1}{Pmpcfg\_ent}{\sailRISCVtypePmpcfgEnt}{}% + \ifstrequal{#1}{Privilege}{\sailRISCVtypePrivilege}{}% + \ifstrequal{#1}{Retired}{\sailRISCVtypeRetired}{}% + \ifstrequal{#1}{SATPMode}{\sailRISCVtypeSATPMode}{}% + \ifstrequal{#1}{SV32\_PTE}{\sailRISCVtypeSVThreeTwoPTE}{}% + \ifstrequal{#1}{SV32\_Paddr}{\sailRISCVtypeSVThreeTwoPaddr}{}% + \ifstrequal{#1}{SV32\_Vaddr}{\sailRISCVtypeSVThreeTwoVaddr}{}% + \ifstrequal{#1}{SV39\_PTE}{\sailRISCVtypeSVThreeNinePTE}{}% + \ifstrequal{#1}{SV39\_Paddr}{\sailRISCVtypeSVThreeNinePaddr}{}% + \ifstrequal{#1}{SV39\_Vaddr}{\sailRISCVtypeSVThreeNineVaddr}{}% + \ifstrequal{#1}{SV48\_PTE}{\sailRISCVtypeSVFourEightPTE}{}% + \ifstrequal{#1}{SV48\_Paddr}{\sailRISCVtypeSVFourEightPaddr}{}% + \ifstrequal{#1}{SV48\_Vaddr}{\sailRISCVtypeSVFourEightVaddr}{}% + \ifstrequal{#1}{Satp32}{\sailRISCVtypeSatpThreeTwo}{}% + \ifstrequal{#1}{Satp64}{\sailRISCVtypeSatpSixFour}{}% + \ifstrequal{#1}{Sedeleg}{\sailRISCVtypeSedeleg}{}% + \ifstrequal{#1}{Sinterrupts}{\sailRISCVtypeSinterrupts}{}% + \ifstrequal{#1}{Sstatus}{\sailRISCVtypeSstatus}{}% + \ifstrequal{#1}{TLB39\_Entry}{\sailRISCVtypeTLBThreeNineEntry}{}% + \ifstrequal{#1}{TLB48\_Entry}{\sailRISCVtypeTLBFourEightEntry}{}% + \ifstrequal{#1}{TLB\_Entry}{\sailRISCVtypeTLBEntry}{}% + \ifstrequal{#1}{TR\_Result}{\sailRISCVtypeTRResult}{}% + \ifstrequal{#1}{TrapVectorMode}{\sailRISCVtypeTrapVectorMode}{}% + \ifstrequal{#1}{Uinterrupts}{\sailRISCVtypeUinterrupts}{}% + \ifstrequal{#1}{Ustatus}{\sailRISCVtypeUstatus}{}% + \ifstrequal{#1}{a64\_barrier\_domain}{\sailRISCVtypeaSixFourBarrierDomain}{}% + \ifstrequal{#1}{a64\_barrier\_type}{\sailRISCVtypeaSixFourBarrierType}{}% + \ifstrequal{#1}{amo}{\sailRISCVtypeamo}{}% + \ifstrequal{#1}{amoop}{\sailRISCVtypeamoop}{}% + \ifstrequal{#1}{arch\_xlen}{\sailRISCVtypearchXlen}{}% + \ifstrequal{#1}{asid32}{\sailRISCVtypeasidThreeTwo}{}% + \ifstrequal{#1}{asid64}{\sailRISCVtypeasidSixFour}{}% + \ifstrequal{#1}{ast}{\sailRISCVtypeast}{}% + \ifstrequal{#1}{barrier\_kind}{\sailRISCVtypebarrierKind}{}% + \ifstrequal{#1}{bits}{\sailRISCVtypebits}{}% + \ifstrequal{#1}{bits\_D}{\sailRISCVtypebitsD}{}% + \ifstrequal{#1}{bits\_L}{\sailRISCVtypebitsL}{}% + \ifstrequal{#1}{bits\_LU}{\sailRISCVtypebitsLU}{}% + \ifstrequal{#1}{bits\_S}{\sailRISCVtypebitsS}{}% + \ifstrequal{#1}{bits\_W}{\sailRISCVtypebitsW}{}% + \ifstrequal{#1}{bits\_WU}{\sailRISCVtypebitsWU}{}% + \ifstrequal{#1}{bits\_fflags}{\sailRISCVtypebitsFflags}{}% + \ifstrequal{#1}{bits\_rm}{\sailRISCVtypebitsRm}{}% + \ifstrequal{#1}{bop}{\sailRISCVtypebop}{}% + \ifstrequal{#1}{cache\_op\_kind}{\sailRISCVtypecacheOpKind}{}% + \ifstrequal{#1}{cap\_addr\_width}{\sailRISCVtypecapAddrWidth}{}% + \ifstrequal{#1}{cap\_flags\_width}{\sailRISCVtypecapFlagsWidth}{}% + \ifstrequal{#1}{cap\_hperms\_width}{\sailRISCVtypecapHpermsWidth}{}% + \ifstrequal{#1}{cap\_len\_width}{\sailRISCVtypecapLenWidth}{}% + \ifstrequal{#1}{cap\_mantissa\_width}{\sailRISCVtypecapMantissaWidth}{}% + \ifstrequal{#1}{cap\_otype\_width}{\sailRISCVtypecapOtypeWidth}{}% + \ifstrequal{#1}{cap\_perms\_width}{\sailRISCVtypecapPermsWidth}{}% + \ifstrequal{#1}{cap\_size}{\sailRISCVtypecapSizze}{}% + \ifstrequal{#1}{cap\_uperms\_shift}{\sailRISCVtypecapUpermsShift}{}% + \ifstrequal{#1}{cap\_uperms\_width}{\sailRISCVtypecapUpermsWidth}{}% + \ifstrequal{#1}{capreg\_idx}{\sailRISCVtypecapregIdx}{}% + \ifstrequal{#1}{caps\_per\_cache\_line}{\sailRISCVtypecapsPerCacheLine}{}% + \ifstrequal{#1}{ccsr}{\sailRISCVtypeccsr}{}% + \ifstrequal{#1}{cheri\_cause}{\sailRISCVtypecheriCause}{}% + \ifstrequal{#1}{cregidx}{\sailRISCVtypecregidx}{}% + \ifstrequal{#1}{csrRW}{\sailRISCVtypecsrRW}{}% + \ifstrequal{#1}{csreg}{\sailRISCVtypecsreg}{}% + \ifstrequal{#1}{csrop}{\sailRISCVtypecsrop}{}% + \ifstrequal{#1}{ctl\_result}{\sailRISCVtypectlResult}{}% + \ifstrequal{#1}{diafp}{\sailRISCVtypediafp}{}% + \ifstrequal{#1}{exc\_code}{\sailRISCVtypeexcCode}{}% + \ifstrequal{#1}{exception}{\sailRISCVtypeexception}{}% + \ifstrequal{#1}{extPte}{\sailRISCVtypeextPte}{}% + \ifstrequal{#1}{ext\_access\_type}{\sailRISCVtypeextAccessType}{}% + \ifstrequal{#1}{ext\_control\_addr\_error}{\sailRISCVtypeextControlAddrError}{}% + \ifstrequal{#1}{ext\_data\_addr\_error}{\sailRISCVtypeextDataAddrError}{}% + \ifstrequal{#1}{ext\_exc\_type}{\sailRISCVtypeextExcType}{}% + \ifstrequal{#1}{ext\_exception}{\sailRISCVtypeextException}{}% + \ifstrequal{#1}{ext\_fetch\_addr\_error}{\sailRISCVtypeextFetchAddrError}{}% + \ifstrequal{#1}{ext\_ptw}{\sailRISCVtypeextPtw}{}% + \ifstrequal{#1}{ext\_ptw\_error}{\sailRISCVtypeextPtwError}{}% + \ifstrequal{#1}{ext\_ptw\_fail}{\sailRISCVtypeextPtwFail}{}% + \ifstrequal{#1}{ext\_ptw\_lc}{\sailRISCVtypeextPtwLc}{}% + \ifstrequal{#1}{ext\_ptw\_sc}{\sailRISCVtypeextPtwSc}{}% + \ifstrequal{#1}{ext\_status}{\sailRISCVtypeextStatus}{}% + \ifstrequal{#1}{f\_bin\_op\_D}{\sailRISCVtypefBinOpD}{}% + \ifstrequal{#1}{f\_bin\_op\_S}{\sailRISCVtypefBinOpS}{}% + \ifstrequal{#1}{f\_bin\_rm\_op\_D}{\sailRISCVtypefBinRmOpD}{}% + \ifstrequal{#1}{f\_bin\_rm\_op\_S}{\sailRISCVtypefBinRmOpS}{}% + \ifstrequal{#1}{f\_madd\_op\_D}{\sailRISCVtypefMaddOpD}{}% + \ifstrequal{#1}{f\_madd\_op\_S}{\sailRISCVtypefMaddOpS}{}% + \ifstrequal{#1}{f\_un\_op\_D}{\sailRISCVtypefUnOpD}{}% + \ifstrequal{#1}{f\_un\_op\_S}{\sailRISCVtypefUnOpS}{}% + \ifstrequal{#1}{f\_un\_rm\_op\_D}{\sailRISCVtypefUnRmOpD}{}% + \ifstrequal{#1}{f\_un\_rm\_op\_S}{\sailRISCVtypefUnRmOpS}{}% + \ifstrequal{#1}{flen}{\sailRISCVtypeflen}{}% + \ifstrequal{#1}{flen\_bytes}{\sailRISCVtypeflenBytes}{}% + \ifstrequal{#1}{flenbits}{\sailRISCVtypeflenbits}{}% + \ifstrequal{#1}{fregtype}{\sailRISCVtypefregtype}{}% + \ifstrequal{#1}{half}{\sailRISCVtypehalf}{}% + \ifstrequal{#1}{htif\_cmd}{\sailRISCVtypehtifCmd}{}% + \ifstrequal{#1}{imm12}{\sailRISCVtypeimmOneTwo}{}% + \ifstrequal{#1}{imm20}{\sailRISCVtypeimmTwoZero}{}% + \ifstrequal{#1}{instruction\_kind}{\sailRISCVtypeinstructionKind}{}% + \ifstrequal{#1}{interrupt\_set}{\sailRISCVtypeinterruptSet}{}% + \ifstrequal{#1}{iop}{\sailRISCVtypeiop}{}% + \ifstrequal{#1}{log2\_cap\_size}{\sailRISCVtypelogTwoCapSizze}{}% + \ifstrequal{#1}{max\_mem\_access}{\sailRISCVtypemaxMemAccess}{}% + \ifstrequal{#1}{mem\_meta}{\sailRISCVtypememMeta}{}% + \ifstrequal{#1}{niafp}{\sailRISCVtypeniafp}{}% + \ifstrequal{#1}{niafps}{\sailRISCVtypeniafps}{}% + \ifstrequal{#1}{opcode}{\sailRISCVtypeopcode}{}% + \ifstrequal{#1}{option}{\sailRISCVtypeoption}{}% + \ifstrequal{#1}{paddr32}{\sailRISCVtypepaddrThreeTwo}{}% + \ifstrequal{#1}{paddr64}{\sailRISCVtypepaddrSixFour}{}% + \ifstrequal{#1}{pmpAddrMatch}{\sailRISCVtypepmpAddrMatch}{}% + \ifstrequal{#1}{pmpMatch}{\sailRISCVtypepmpMatch}{}% + \ifstrequal{#1}{pmp\_addr\_range}{\sailRISCVtypepmpAddrRange}{}% + \ifstrequal{#1}{priv\_level}{\sailRISCVtypeprivLevel}{}% + \ifstrequal{#1}{pte32}{\sailRISCVtypepteThreeTwo}{}% + \ifstrequal{#1}{pte48}{\sailRISCVtypepteFourEight}{}% + \ifstrequal{#1}{pte64}{\sailRISCVtypepteSixFour}{}% + \ifstrequal{#1}{pteAttribs}{\sailRISCVtypepteAttribs}{}% + \ifstrequal{#1}{read\_kind}{\sailRISCVtypereadKind}{}% + \ifstrequal{#1}{regfp}{\sailRISCVtyperegfp}{}% + \ifstrequal{#1}{regfps}{\sailRISCVtyperegfps}{}% + \ifstrequal{#1}{regidx}{\sailRISCVtyperegidx}{}% + \ifstrequal{#1}{regno}{\sailRISCVtyperegno}{}% + \ifstrequal{#1}{regtype}{\sailRISCVtyperegtype}{}% + \ifstrequal{#1}{rop}{\sailRISCVtyperop}{}% + \ifstrequal{#1}{ropw}{\sailRISCVtyperopw}{}% + \ifstrequal{#1}{rounding\_mode}{\sailRISCVtyperoundingMode}{}% + \ifstrequal{#1}{satp\_mode}{\sailRISCVtypesatpMode}{}% + \ifstrequal{#1}{screg}{\sailRISCVtypescreg}{}% + \ifstrequal{#1}{sop}{\sailRISCVtypesop}{}% + \ifstrequal{#1}{sopw}{\sailRISCVtypesopw}{}% + \ifstrequal{#1}{sync\_exception}{\sailRISCVtypesyncException}{}% + \ifstrequal{#1}{tagaddrbits}{\sailRISCVtypetagaddrbits}{}% + \ifstrequal{#1}{trans\_kind}{\sailRISCVtypetransKind}{}% + \ifstrequal{#1}{tv\_mode}{\sailRISCVtypetvMode}{}% + \ifstrequal{#1}{uop}{\sailRISCVtypeuop}{}% + \ifstrequal{#1}{vaddr32}{\sailRISCVtypevaddrThreeTwo}{}% + \ifstrequal{#1}{vaddr39}{\sailRISCVtypevaddrThreeNine}{}% + \ifstrequal{#1}{vaddr48}{\sailRISCVtypevaddrFourEight}{}% + \ifstrequal{#1}{word}{\sailRISCVtypeword}{}% + \ifstrequal{#1}{word\_width}{\sailRISCVtypewordWidth}{}% + \ifstrequal{#1}{write\_kind}{\sailRISCVtypewriteKind}{}% + \ifstrequal{#1}{xlen}{\sailRISCVtypexlen}{}% + \ifstrequal{#1}{xlen\_bytes}{\sailRISCVtypexlenBytes}{}% + \ifstrequal{#1}{xlenbits}{\sailRISCVtypexlenbits}{}} + +\newcommand{\sailRISCVreftype}[2]{ + \ifstrequal{#1}{AccessType}{\hyperref[sailRISCVtypezAccessType]{#2}}{}% + \ifstrequal{#1}{Architecture}{\hyperref[sailRISCVtypezArchitecture]{#2}}{}% + \ifstrequal{#1}{CPtrCmpOp}{\hyperref[sailRISCVtypezCPtrCmpOp]{#2}}{}% + \ifstrequal{#1}{CapAddrBits}{\hyperref[sailRISCVtypezCapAddrBits]{#2}}{}% + \ifstrequal{#1}{CapAddrInt}{\hyperref[sailRISCVtypezCapAddrInt]{#2}}{}% + \ifstrequal{#1}{CapBits}{\hyperref[sailRISCVtypezCapBits]{#2}}{}% + \ifstrequal{#1}{CapEx}{\hyperref[sailRISCVtypezCapEx]{#2}}{}% + \ifstrequal{#1}{CapFlagsBits}{\hyperref[sailRISCVtypezCapFlagsBits]{#2}}{}% + \ifstrequal{#1}{CapLen}{\hyperref[sailRISCVtypezCapLen]{#2}}{}% + \ifstrequal{#1}{CapLenBits}{\hyperref[sailRISCVtypezCapLenBits]{#2}}{}% + \ifstrequal{#1}{CapPermsBits}{\hyperref[sailRISCVtypezCapPermsBits]{#2}}{}% + \ifstrequal{#1}{Capability}{\hyperref[sailRISCVtypezCapability]{#2}}{}% + \ifstrequal{#1}{ClearRegSet}{\hyperref[sailRISCVtypezClearRegSet]{#2}}{}% + \ifstrequal{#1}{Counteren}{\hyperref[sailRISCVtypezCounteren]{#2}}{}% + \ifstrequal{#1}{Counterin}{\hyperref[sailRISCVtypezCounterin]{#2}}{}% + \ifstrequal{#1}{ExceptionType}{\hyperref[sailRISCVtypezExceptionType]{#2}}{}% + \ifstrequal{#1}{ExtStatus}{\hyperref[sailRISCVtypezExtStatus]{#2}}{}% + \ifstrequal{#1}{Ext_ControlAddr_Check}{\hyperref[sailRISCVtypezExtzyControlAddrzyCheck]{#2}}{}% + \ifstrequal{#1}{Ext_DataAddr_Check}{\hyperref[sailRISCVtypezExtzyDataAddrzyCheck]{#2}}{}% + \ifstrequal{#1}{Ext_FetchAddr_Check}{\hyperref[sailRISCVtypezExtzyFetchAddrzyCheck]{#2}}{}% + \ifstrequal{#1}{Ext_PTE_Bits}{\hyperref[sailRISCVtypezExtzyPTEzyBits]{#2}}{}% + \ifstrequal{#1}{Fcsr}{\hyperref[sailRISCVtypezFcsr]{#2}}{}% + \ifstrequal{#1}{FetchResult}{\hyperref[sailRISCVtypezFetchResult]{#2}}{}% + \ifstrequal{#1}{InterruptType}{\hyperref[sailRISCVtypezInterruptType]{#2}}{}% + \ifstrequal{#1}{Mcause}{\hyperref[sailRISCVtypezMcause]{#2}}{}% + \ifstrequal{#1}{Medeleg}{\hyperref[sailRISCVtypezMedeleg]{#2}}{}% + \ifstrequal{#1}{MemoryOpResult}{\hyperref[sailRISCVtypezMemoryOpResult]{#2}}{}% + \ifstrequal{#1}{Minterrupts}{\hyperref[sailRISCVtypezMinterrupts]{#2}}{}% + \ifstrequal{#1}{Misa}{\hyperref[sailRISCVtypezMisa]{#2}}{}% + \ifstrequal{#1}{Mstatus}{\hyperref[sailRISCVtypezMstatus]{#2}}{}% + \ifstrequal{#1}{Mtvec}{\hyperref[sailRISCVtypezMtvec]{#2}}{}% + \ifstrequal{#1}{PTE_Bits}{\hyperref[sailRISCVtypezPTEzyBits]{#2}}{}% + \ifstrequal{#1}{PTE_Check}{\hyperref[sailRISCVtypezPTEzyCheck]{#2}}{}% + \ifstrequal{#1}{PTW_Error}{\hyperref[sailRISCVtypezPTWzyError]{#2}}{}% + \ifstrequal{#1}{PTW_Result}{\hyperref[sailRISCVtypezPTWzyResult]{#2}}{}% + \ifstrequal{#1}{PmpAddrMatchType}{\hyperref[sailRISCVtypezPmpAddrMatchType]{#2}}{}% + \ifstrequal{#1}{Pmpcfg_ent}{\hyperref[sailRISCVtypezPmpcfgzyent]{#2}}{}% + \ifstrequal{#1}{Privilege}{\hyperref[sailRISCVtypezPrivilege]{#2}}{}% + \ifstrequal{#1}{Retired}{\hyperref[sailRISCVtypezRetired]{#2}}{}% + \ifstrequal{#1}{SATPMode}{\hyperref[sailRISCVtypezSATPMode]{#2}}{}% + \ifstrequal{#1}{SV32_PTE}{\hyperref[sailRISCVtypezSV32zyPTE]{#2}}{}% + \ifstrequal{#1}{SV32_Paddr}{\hyperref[sailRISCVtypezSV32zyPaddr]{#2}}{}% + \ifstrequal{#1}{SV32_Vaddr}{\hyperref[sailRISCVtypezSV32zyVaddr]{#2}}{}% + \ifstrequal{#1}{SV39_PTE}{\hyperref[sailRISCVtypezSV39zyPTE]{#2}}{}% + \ifstrequal{#1}{SV39_Paddr}{\hyperref[sailRISCVtypezSV39zyPaddr]{#2}}{}% + \ifstrequal{#1}{SV39_Vaddr}{\hyperref[sailRISCVtypezSV39zyVaddr]{#2}}{}% + \ifstrequal{#1}{SV48_PTE}{\hyperref[sailRISCVtypezSV48zyPTE]{#2}}{}% + \ifstrequal{#1}{SV48_Paddr}{\hyperref[sailRISCVtypezSV48zyPaddr]{#2}}{}% + \ifstrequal{#1}{SV48_Vaddr}{\hyperref[sailRISCVtypezSV48zyVaddr]{#2}}{}% + \ifstrequal{#1}{Satp32}{\hyperref[sailRISCVtypezSatp32]{#2}}{}% + \ifstrequal{#1}{Satp64}{\hyperref[sailRISCVtypezSatp64]{#2}}{}% + \ifstrequal{#1}{Sedeleg}{\hyperref[sailRISCVtypezSedeleg]{#2}}{}% + \ifstrequal{#1}{Sinterrupts}{\hyperref[sailRISCVtypezSinterrupts]{#2}}{}% + \ifstrequal{#1}{Sstatus}{\hyperref[sailRISCVtypezSstatus]{#2}}{}% + \ifstrequal{#1}{TLB39_Entry}{\hyperref[sailRISCVtypezTLB39zyEntry]{#2}}{}% + \ifstrequal{#1}{TLB48_Entry}{\hyperref[sailRISCVtypezTLB48zyEntry]{#2}}{}% + \ifstrequal{#1}{TLB_Entry}{\hyperref[sailRISCVtypezTLBzyEntry]{#2}}{}% + \ifstrequal{#1}{TR_Result}{\hyperref[sailRISCVtypezTRzyResult]{#2}}{}% + \ifstrequal{#1}{TrapVectorMode}{\hyperref[sailRISCVtypezTrapVectorMode]{#2}}{}% + \ifstrequal{#1}{Uinterrupts}{\hyperref[sailRISCVtypezUinterrupts]{#2}}{}% + \ifstrequal{#1}{Ustatus}{\hyperref[sailRISCVtypezUstatus]{#2}}{}% + \ifstrequal{#1}{a64_barrier_domain}{\hyperref[sailRISCVtypeza64zybarrierzydomain]{#2}}{}% + \ifstrequal{#1}{a64_barrier_type}{\hyperref[sailRISCVtypeza64zybarrierzytype]{#2}}{}% + \ifstrequal{#1}{amo}{\hyperref[sailRISCVtypezamo]{#2}}{}% + \ifstrequal{#1}{amoop}{\hyperref[sailRISCVtypezamoop]{#2}}{}% + \ifstrequal{#1}{arch_xlen}{\hyperref[sailRISCVtypezarchzyxlen]{#2}}{}% + \ifstrequal{#1}{asid32}{\hyperref[sailRISCVtypezasid32]{#2}}{}% + \ifstrequal{#1}{asid64}{\hyperref[sailRISCVtypezasid64]{#2}}{}% + \ifstrequal{#1}{ast}{\hyperref[sailRISCVtypezast]{#2}}{}% + \ifstrequal{#1}{barrier_kind}{\hyperref[sailRISCVtypezbarrierzykind]{#2}}{}% + \ifstrequal{#1}{bits}{\hyperref[sailRISCVtypezbits]{#2}}{}% + \ifstrequal{#1}{bits_D}{\hyperref[sailRISCVtypezbitszyD]{#2}}{}% + \ifstrequal{#1}{bits_L}{\hyperref[sailRISCVtypezbitszyL]{#2}}{}% + \ifstrequal{#1}{bits_LU}{\hyperref[sailRISCVtypezbitszyLU]{#2}}{}% + \ifstrequal{#1}{bits_S}{\hyperref[sailRISCVtypezbitszyS]{#2}}{}% + \ifstrequal{#1}{bits_W}{\hyperref[sailRISCVtypezbitszyW]{#2}}{}% + \ifstrequal{#1}{bits_WU}{\hyperref[sailRISCVtypezbitszyWU]{#2}}{}% + \ifstrequal{#1}{bits_fflags}{\hyperref[sailRISCVtypezbitszyfflags]{#2}}{}% + \ifstrequal{#1}{bits_rm}{\hyperref[sailRISCVtypezbitszyrm]{#2}}{}% + \ifstrequal{#1}{bop}{\hyperref[sailRISCVtypezbop]{#2}}{}% + \ifstrequal{#1}{cache_op_kind}{\hyperref[sailRISCVtypezcachezyopzykind]{#2}}{}% + \ifstrequal{#1}{cap_addr_width}{\hyperref[sailRISCVtypezcapzyaddrzywidth]{#2}}{}% + \ifstrequal{#1}{cap_flags_width}{\hyperref[sailRISCVtypezcapzyflagszywidth]{#2}}{}% + \ifstrequal{#1}{cap_hperms_width}{\hyperref[sailRISCVtypezcapzyhpermszywidth]{#2}}{}% + \ifstrequal{#1}{cap_len_width}{\hyperref[sailRISCVtypezcapzylenzywidth]{#2}}{}% + \ifstrequal{#1}{cap_mantissa_width}{\hyperref[sailRISCVtypezcapzymantissazywidth]{#2}}{}% + \ifstrequal{#1}{cap_otype_width}{\hyperref[sailRISCVtypezcapzyotypezywidth]{#2}}{}% + \ifstrequal{#1}{cap_perms_width}{\hyperref[sailRISCVtypezcapzypermszywidth]{#2}}{}% + \ifstrequal{#1}{cap_size}{\hyperref[sailRISCVtypezcapzysizze]{#2}}{}% + \ifstrequal{#1}{cap_uperms_shift}{\hyperref[sailRISCVtypezcapzyupermszyshift]{#2}}{}% + \ifstrequal{#1}{cap_uperms_width}{\hyperref[sailRISCVtypezcapzyupermszywidth]{#2}}{}% + \ifstrequal{#1}{capreg_idx}{\hyperref[sailRISCVtypezcapregzyidx]{#2}}{}% + \ifstrequal{#1}{caps_per_cache_line}{\hyperref[sailRISCVtypezcapszyperzycachezyline]{#2}}{}% + \ifstrequal{#1}{ccsr}{\hyperref[sailRISCVtypezccsr]{#2}}{}% + \ifstrequal{#1}{cheri_cause}{\hyperref[sailRISCVtypezcherizycause]{#2}}{}% + \ifstrequal{#1}{cregidx}{\hyperref[sailRISCVtypezcregidx]{#2}}{}% + \ifstrequal{#1}{csrRW}{\hyperref[sailRISCVtypezcsrRW]{#2}}{}% + \ifstrequal{#1}{csreg}{\hyperref[sailRISCVtypezcsreg]{#2}}{}% + \ifstrequal{#1}{csrop}{\hyperref[sailRISCVtypezcsrop]{#2}}{}% + \ifstrequal{#1}{ctl_result}{\hyperref[sailRISCVtypezctlzyresult]{#2}}{}% + \ifstrequal{#1}{diafp}{\hyperref[sailRISCVtypezdiafp]{#2}}{}% + \ifstrequal{#1}{exc_code}{\hyperref[sailRISCVtypezexczycode]{#2}}{}% + \ifstrequal{#1}{exception}{\hyperref[sailRISCVtypezexception]{#2}}{}% + \ifstrequal{#1}{extPte}{\hyperref[sailRISCVtypezextPte]{#2}}{}% + \ifstrequal{#1}{ext_access_type}{\hyperref[sailRISCVtypezextzyaccesszytype]{#2}}{}% + \ifstrequal{#1}{ext_control_addr_error}{\hyperref[sailRISCVtypezextzycontrolzyaddrzyerror]{#2}}{}% + \ifstrequal{#1}{ext_data_addr_error}{\hyperref[sailRISCVtypezextzydatazyaddrzyerror]{#2}}{}% + \ifstrequal{#1}{ext_exc_type}{\hyperref[sailRISCVtypezextzyexczytype]{#2}}{}% + \ifstrequal{#1}{ext_exception}{\hyperref[sailRISCVtypezextzyexception]{#2}}{}% + \ifstrequal{#1}{ext_fetch_addr_error}{\hyperref[sailRISCVtypezextzyfetchzyaddrzyerror]{#2}}{}% + \ifstrequal{#1}{ext_ptw}{\hyperref[sailRISCVtypezextzyptw]{#2}}{}% + \ifstrequal{#1}{ext_ptw_error}{\hyperref[sailRISCVtypezextzyptwzyerror]{#2}}{}% + \ifstrequal{#1}{ext_ptw_fail}{\hyperref[sailRISCVtypezextzyptwzyfail]{#2}}{}% + \ifstrequal{#1}{ext_ptw_lc}{\hyperref[sailRISCVtypezextzyptwzylc]{#2}}{}% + \ifstrequal{#1}{ext_ptw_sc}{\hyperref[sailRISCVtypezextzyptwzysc]{#2}}{}% + \ifstrequal{#1}{ext_status}{\hyperref[sailRISCVtypezextzystatus]{#2}}{}% + \ifstrequal{#1}{f_bin_op_D}{\hyperref[sailRISCVtypezfzybinzyopzyD]{#2}}{}% + \ifstrequal{#1}{f_bin_op_S}{\hyperref[sailRISCVtypezfzybinzyopzyS]{#2}}{}% + \ifstrequal{#1}{f_bin_rm_op_D}{\hyperref[sailRISCVtypezfzybinzyrmzyopzyD]{#2}}{}% + \ifstrequal{#1}{f_bin_rm_op_S}{\hyperref[sailRISCVtypezfzybinzyrmzyopzyS]{#2}}{}% + \ifstrequal{#1}{f_madd_op_D}{\hyperref[sailRISCVtypezfzymaddzyopzyD]{#2}}{}% + \ifstrequal{#1}{f_madd_op_S}{\hyperref[sailRISCVtypezfzymaddzyopzyS]{#2}}{}% + \ifstrequal{#1}{f_un_op_D}{\hyperref[sailRISCVtypezfzyunzyopzyD]{#2}}{}% + \ifstrequal{#1}{f_un_op_S}{\hyperref[sailRISCVtypezfzyunzyopzyS]{#2}}{}% + \ifstrequal{#1}{f_un_rm_op_D}{\hyperref[sailRISCVtypezfzyunzyrmzyopzyD]{#2}}{}% + \ifstrequal{#1}{f_un_rm_op_S}{\hyperref[sailRISCVtypezfzyunzyrmzyopzyS]{#2}}{}% + \ifstrequal{#1}{flen}{\hyperref[sailRISCVtypezflen]{#2}}{}% + \ifstrequal{#1}{flen_bytes}{\hyperref[sailRISCVtypezflenzybytes]{#2}}{}% + \ifstrequal{#1}{flenbits}{\hyperref[sailRISCVtypezflenbits]{#2}}{}% + \ifstrequal{#1}{fregtype}{\hyperref[sailRISCVtypezfregtype]{#2}}{}% + \ifstrequal{#1}{half}{\hyperref[sailRISCVtypezhalf]{#2}}{}% + \ifstrequal{#1}{htif_cmd}{\hyperref[sailRISCVtypezhtifzycmd]{#2}}{}% + \ifstrequal{#1}{imm12}{\hyperref[sailRISCVtypezimm12]{#2}}{}% + \ifstrequal{#1}{imm20}{\hyperref[sailRISCVtypezimm20]{#2}}{}% + \ifstrequal{#1}{instruction_kind}{\hyperref[sailRISCVtypezinstructionzykind]{#2}}{}% + \ifstrequal{#1}{interrupt_set}{\hyperref[sailRISCVtypezinterruptzyset]{#2}}{}% + \ifstrequal{#1}{iop}{\hyperref[sailRISCVtypeziop]{#2}}{}% + \ifstrequal{#1}{log2_cap_size}{\hyperref[sailRISCVtypezlog2zycapzysizze]{#2}}{}% + \ifstrequal{#1}{max_mem_access}{\hyperref[sailRISCVtypezmaxzymemzyaccess]{#2}}{}% + \ifstrequal{#1}{mem_meta}{\hyperref[sailRISCVtypezmemzymeta]{#2}}{}% + \ifstrequal{#1}{niafp}{\hyperref[sailRISCVtypezniafp]{#2}}{}% + \ifstrequal{#1}{niafps}{\hyperref[sailRISCVtypezniafps]{#2}}{}% + \ifstrequal{#1}{opcode}{\hyperref[sailRISCVtypezopcode]{#2}}{}% + \ifstrequal{#1}{option}{\hyperref[sailRISCVtypezoption]{#2}}{}% + \ifstrequal{#1}{paddr32}{\hyperref[sailRISCVtypezpaddr32]{#2}}{}% + \ifstrequal{#1}{paddr64}{\hyperref[sailRISCVtypezpaddr64]{#2}}{}% + \ifstrequal{#1}{pmpAddrMatch}{\hyperref[sailRISCVtypezpmpAddrMatch]{#2}}{}% + \ifstrequal{#1}{pmpMatch}{\hyperref[sailRISCVtypezpmpMatch]{#2}}{}% + \ifstrequal{#1}{pmp_addr_range}{\hyperref[sailRISCVtypezpmpzyaddrzyrange]{#2}}{}% + \ifstrequal{#1}{priv_level}{\hyperref[sailRISCVtypezprivzylevel]{#2}}{}% + \ifstrequal{#1}{pte32}{\hyperref[sailRISCVtypezpte32]{#2}}{}% + \ifstrequal{#1}{pte48}{\hyperref[sailRISCVtypezpte48]{#2}}{}% + \ifstrequal{#1}{pte64}{\hyperref[sailRISCVtypezpte64]{#2}}{}% + \ifstrequal{#1}{pteAttribs}{\hyperref[sailRISCVtypezpteAttribs]{#2}}{}% + \ifstrequal{#1}{read_kind}{\hyperref[sailRISCVtypezreadzykind]{#2}}{}% + \ifstrequal{#1}{regfp}{\hyperref[sailRISCVtypezregfp]{#2}}{}% + \ifstrequal{#1}{regfps}{\hyperref[sailRISCVtypezregfps]{#2}}{}% + \ifstrequal{#1}{regidx}{\hyperref[sailRISCVtypezregidx]{#2}}{}% + \ifstrequal{#1}{regno}{\hyperref[sailRISCVtypezregno]{#2}}{}% + \ifstrequal{#1}{regtype}{\hyperref[sailRISCVtypezregtype]{#2}}{}% + \ifstrequal{#1}{rop}{\hyperref[sailRISCVtypezrop]{#2}}{}% + \ifstrequal{#1}{ropw}{\hyperref[sailRISCVtypezropw]{#2}}{}% + \ifstrequal{#1}{rounding_mode}{\hyperref[sailRISCVtypezroundingzymode]{#2}}{}% + \ifstrequal{#1}{satp_mode}{\hyperref[sailRISCVtypezsatpzymode]{#2}}{}% + \ifstrequal{#1}{screg}{\hyperref[sailRISCVtypezscreg]{#2}}{}% + \ifstrequal{#1}{sop}{\hyperref[sailRISCVtypezsop]{#2}}{}% + \ifstrequal{#1}{sopw}{\hyperref[sailRISCVtypezsopw]{#2}}{}% + \ifstrequal{#1}{sync_exception}{\hyperref[sailRISCVtypezsynczyexception]{#2}}{}% + \ifstrequal{#1}{tagaddrbits}{\hyperref[sailRISCVtypeztagaddrbits]{#2}}{}% + \ifstrequal{#1}{trans_kind}{\hyperref[sailRISCVtypeztranszykind]{#2}}{}% + \ifstrequal{#1}{tv_mode}{\hyperref[sailRISCVtypeztvzymode]{#2}}{}% + \ifstrequal{#1}{uop}{\hyperref[sailRISCVtypezuop]{#2}}{}% + \ifstrequal{#1}{vaddr32}{\hyperref[sailRISCVtypezvaddr32]{#2}}{}% + \ifstrequal{#1}{vaddr39}{\hyperref[sailRISCVtypezvaddr39]{#2}}{}% + \ifstrequal{#1}{vaddr48}{\hyperref[sailRISCVtypezvaddr48]{#2}}{}% + \ifstrequal{#1}{word}{\hyperref[sailRISCVtypezword]{#2}}{}% + \ifstrequal{#1}{word_width}{\hyperref[sailRISCVtypezwordzywidth]{#2}}{}% + \ifstrequal{#1}{write_kind}{\hyperref[sailRISCVtypezwritezykind]{#2}}{}% + \ifstrequal{#1}{xlen}{\hyperref[sailRISCVtypezxlen]{#2}}{}% + \ifstrequal{#1}{xlen_bytes}{\hyperref[sailRISCVtypezxlenzybytes]{#2}}{}% + \ifstrequal{#1}{xlenbits}{\hyperref[sailRISCVtypezxlenbits]{#2}}{}} diff --git a/sail_latex_riscv/fclADDIWzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclADDIWzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d2bd8d0d --- /dev/null +++ b/sail_latex_riscv/fclADDIWzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let result : xlenbits = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm) + #\hyperref[sailRISCVzX]{X}#(rs1); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTS]{EXTS}#(result[31..0]); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclAMOzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclAMOzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..bc2d3f13 --- /dev/null +++ b/sail_latex_riscv/fclAMOzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,79 @@ +if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { + /* Get the address, #\hyperref[sailRISCVzX]{X}#(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match #\hyperref[sailRISCVzextzydatazygetzyaddr]{ext\_data\_get\_addr}#(rs1, #\hyperref[sailRISCVzzzeros]{zeros}#(), #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Data, Data), width) { + #\hyperref[sailRISCVzExtzyDataAddrzyError]{Ext\_DataAddr\_Error}#(e) => { #\hyperref[sailRISCVzextzyhandlezydatazycheckzyerror]{ext\_handle\_data\_check\_error}#(e); RETIRE_FAIL }, + #\hyperref[sailRISCVzExtzyDataAddrzyOK]{Ext\_DataAddr\_OK}#(vaddr) => { + match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddr, #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Data, Data)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, _) => { + let eares : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(unit) = match (width, sizeof(xlen)) { + (WORD, _) => #\hyperref[sailRISCVzmemzywritezyea]{mem\_write\_ea}#(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => #\hyperref[sailRISCVzmemzywritezyea]{mem\_write\_ea}#(addr, 8, aq & rl, rl, true), + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("AMO expected WORD or DOUBLE") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + WORD => if is_unsigned then #\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzX]{X}#(rs2)[31..0]) else #\hyperref[sailRISCVzEXTS]{EXTS}#(#\hyperref[sailRISCVzX]{X}#(rs2)[31..0]), + DOUBLE => #\hyperref[sailRISCVzX]{X}#(rs2), + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("AMO expected WORD or DOUBLE") + }; + match (eares) { + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(addr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(_) => { + let mval : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(xlenbits) = match (width, sizeof(xlen)) { + (WORD, _) => #\hyperref[sailRISCVzextendzyvalue]{extend\_value}#(is_unsigned, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => #\hyperref[sailRISCVzextendzyvalue]{extend\_value}#(is_unsigned, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Data, Data), addr, 8, aq, aq & rl, true)), + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("AMO expected WORD or DOUBLE") + }; + match (mval) { + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(addr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using #\hyperref[sailRISCVztozybits]{to\_bits}#(). + */ + AMOMIN => #\hyperref[sailRISCVztozybits]{to\_bits}#(sizeof(xlen), #\hyperref[sailRISCVzmin]{min}#(#\hyperref[sailRISCVzsigned]{signed}#(rs2_val), #\hyperref[sailRISCVzsigned]{signed}#(loaded))), + AMOMAX => #\hyperref[sailRISCVztozybits]{to\_bits}#(sizeof(xlen), #\hyperref[sailRISCVzmax]{max}#(#\hyperref[sailRISCVzsigned]{signed}#(rs2_val), #\hyperref[sailRISCVzsigned]{signed}#(loaded))), + AMOMINU => #\hyperref[sailRISCVztozybits]{to\_bits}#(sizeof(xlen), #\hyperref[sailRISCVzmin]{min}#(#\hyperref[sailRISCVzunsigned]{unsigned}#(rs2_val), #\hyperref[sailRISCVzunsigned]{unsigned}#(loaded))), + AMOMAXU => #\hyperref[sailRISCVztozybits]{to\_bits}#(sizeof(xlen), #\hyperref[sailRISCVzmax]{max}#(#\hyperref[sailRISCVzunsigned]{unsigned}#(rs2_val), #\hyperref[sailRISCVzunsigned]{unsigned}#(loaded))) + }; + let rval : xlenbits = match width { + WORD => #\hyperref[sailRISCVzEXTS]{EXTS}#(loaded[31..0]), + DOUBLE => loaded, + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("AMO expected WORD or DOUBLE") + }; + let wval : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(bool) = match (width, sizeof(xlen)) { + (WORD, _) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 8, result, aq & rl, rl, true), + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("AMO expected WORD or DOUBLE") + }; + match (wval) { + #\hyperref[sailRISCVzMemValue]{MemValue}#(true) => { #\hyperref[sailRISCVzX]{X}#(rd) = rval; RETIRE_SUCCESS }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(false) => { #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("AMO got false from mem_write_value") }, + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(addr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclAUIPCCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclAUIPCCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..515b5907 --- /dev/null +++ b/sail_latex_riscv/fclAUIPCCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,7 @@ +let off : xlenbits = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm @ 0x000); +let (representable, newCap) = #\hyperref[sailRISCVzsetCapAddr]{setCapAddr}#(PCC, PC + off); +if representable then + #\hyperref[sailRISCVzC]{C}#(cd) = newCap +else + #\hyperref[sailRISCVzC]{C}#(cd) = #\hyperref[sailRISCVzinvalidateCap]{invalidateCap}#(newCap); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclAzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclAzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..69d49597 --- /dev/null +++ b/sail_latex_riscv/fclAzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}# (0x9C0, value) = { sccsr = #\hyperref[sailRISCVzlegalizzezyccsr]{legalize\_ccsr}#(sccsr, value); #\hyperref[sailRISCVzSome]{Some}#(sccsr.#\hyperref[sailRISCVzbits]{bits}#()) } diff --git a/sail_latex_riscv/fclBTYPEzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclBTYPEzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..ce6240c1 --- /dev/null +++ b/sail_latex_riscv/fclBTYPEzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,29 @@ +let rs1_val = #\hyperref[sailRISCVzX]{X}#(rs1); +let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); +let taken : bool = match op { + RISCV_BEQ => rs1_val == rs2_val, + RISCV_BNE => rs1_val != rs2_val, + RISCV_BLT => rs1_val <_s rs2_val, + RISCV_BGE => rs1_val >=_s rs2_val, + RISCV_BLTU => rs1_val <_u rs2_val, + RISCV_BGEU => rs1_val >=_u rs2_val +}; +let t : xlenbits = PC + #\hyperref[sailRISCVzEXTS]{EXTS}#(imm); +if taken then { + /* Extensions get the first checks on the prospective target address. */ + match #\hyperref[sailRISCVzextzycontrolzycheckzypc]{ext\_control\_check\_pc}#(t) { + #\hyperref[sailRISCVzExtzyControlAddrzyError]{Ext\_ControlAddr\_Error}#(e) => { + #\hyperref[sailRISCVzextzyhandlezycontrolzycheckzyerror]{ext\_handle\_control\_check\_error}#(e); + RETIRE_FAIL + }, + #\hyperref[sailRISCVzExtzyControlAddrzyOK]{Ext\_ControlAddr\_OK}#(target) => { + if #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(target[1]) & (~ (#\hyperref[sailRISCVzhaveRVC]{haveRVC}#())) then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(target, #\hyperref[sailRISCVzEzyFetchzyAddrzyAlign]{E\_Fetch\_Addr\_Align}#()); + RETIRE_FAIL; + } else { + #\hyperref[sailRISCVzsetzynextzypc]{set\_next\_pc}#(target); + RETIRE_SUCCESS + } + } + } +} else RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclBzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclBzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..a2116ff2 --- /dev/null +++ b/sail_latex_riscv/fclBzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}# (0xBC0, value) = { mccsr = #\hyperref[sailRISCVzlegalizzezyccsr]{legalize\_ccsr}#(mccsr, value); #\hyperref[sailRISCVzSome]{Some}#(mccsr.#\hyperref[sailRISCVzbits]{bits}#()) } diff --git a/sail_latex_riscv/fclCAndPermzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCAndPermzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..c89c3188 --- /dev/null +++ b/sail_latex_riscv/fclCAndPermzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,15 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); +if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else { + let perms = #\hyperref[sailRISCVzgetCapPerms]{getCapPerms}#(cs1_val); + let mask = #\hyperref[sailRISCVztruncate]{truncate}#(rs2_val, cap_perms_width); + let newCap = #\hyperref[sailRISCVzsetCapPerms]{setCapPerms}#(cs1_val, (perms & mask)); + #\hyperref[sailRISCVzC]{C}#(cd) = newCap; + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCBuildCapzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCBuildCapzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..eaa220ec --- /dev/null +++ b/sail_latex_riscv/fclCBuildCapzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,37 @@ +let cs1_val = if #\hyperref[sailRISCVzunsigned]{unsigned}#(cs1) == 0 then DDC else #\hyperref[sailRISCVzC]{C}#(cs1); +let cs2_val = #\hyperref[sailRISCVzC]{C}#(cs2); +let (cs1_base, cs1_top) = #\hyperref[sailRISCVzgetCapBounds]{getCapBounds}#(cs1_val); +let (cs2_base, cs2_top) = #\hyperref[sailRISCVzgetCapBounds]{getCapBounds}#(cs2_val); +let cs1_perms = #\hyperref[sailRISCVzgetCapPerms]{getCapPerms}#(cs1_val); +let cs2_perms = #\hyperref[sailRISCVzgetCapPerms]{getCapPerms}#(cs2_val); +let cs2_flags = #\hyperref[sailRISCVzgetCapFlags]{getCapFlags}#(cs2_val); +if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else if cs2_base < cs1_base then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); + RETIRE_FAIL +} else if cs2_top > cs1_top then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); + RETIRE_FAIL +} else if cs2_base > cs2_top then { /* check for length < 0 - possible because cs2 might be untagged */ + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs2); + RETIRE_FAIL +} else if (cs2_perms & cs1_perms) != cs2_perms then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_UserDefViolation, cs1); + RETIRE_FAIL +} else { + let (exact, cd1) = #\hyperref[sailRISCVzsetCapBounds]{setCapBounds}#(cs1_val, #\hyperref[sailRISCVztozybits]{to\_bits}#(cap_addr_width, cs2_base), #\hyperref[sailRISCVztozybits]{to\_bits}#(cap_len_width, cs2_top)); + let (representable, cd2) = #\hyperref[sailRISCVzsetCapOffset]{setCapOffset}#(cd1, #\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(cs2_val)); + let cd3 = #\hyperref[sailRISCVzsetCapPerms]{setCapPerms}#(cd2, cs2_perms); + let cd4 = #\hyperref[sailRISCVzsetCapFlags]{setCapFlags}#(cd3, cs2_flags); + let cd5 = if #\hyperref[sailRISCVzsigned]{signed}#(cs2_val.otype) == otype_sentry then #\hyperref[sailRISCVzsealCap]{sealCap}#(cd4, #\hyperref[sailRISCVztozybits]{to\_bits}#(cap_otype_width, otype_sentry)) else cd4; + { + assert(exact, "CBuildCap: setCapBounds was not exact"); /* base and top came from cs2 originally so will be exact */ + #\hyperref[sailRISCVzC]{C}#(cd) = cd5; + RETIRE_SUCCESS + } +} diff --git a/sail_latex_riscv/fclCCSealzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCCSealzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..1ba6332e --- /dev/null +++ b/sail_latex_riscv/fclCCSealzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,36 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let cs2_val = #\hyperref[sailRISCVzC]{C}#(cs2); +let cs2_cursor = #\hyperref[sailRISCVzgetCapCursor]{getCapCursor}#(cs2_val); +let (cs2_base, cs2_top) = #\hyperref[sailRISCVzgetCapBounds]{getCapBounds}#(cs2_val); +if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs2_val.tag) then { + /* CCopyType may not have been able to represent the result */ + #\hyperref[sailRISCVzC]{C}#(cd) = cs1_val; + RETIRE_SUCCESS +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzC]{C}#(cd) = cs1_val; + RETIRE_SUCCESS +} else if cs2_cursor < cs2_base then { + #\hyperref[sailRISCVzC]{C}#(cd) = cs1_val; + RETIRE_SUCCESS +} else if cs2_cursor >= cs2_top then { + #\hyperref[sailRISCVzC]{C}#(cd) = cs1_val; + RETIRE_SUCCESS +} else if #\hyperref[sailRISCVzsigned]{signed}#(cs2_val.address) == otype_unsealed then { + #\hyperref[sailRISCVzC]{C}#(cd) = cs1_val; + RETIRE_SUCCESS +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs2_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs2); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs2_val.permit_seal) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_PermitSealViolation, cs2); + RETIRE_FAIL +} else if cs2_cursor > max_otype then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs2); + RETIRE_FAIL +} else { + #\hyperref[sailRISCVzC]{C}#(cd) = #\hyperref[sailRISCVzsealCap]{sealCap}#(cs1_val, #\hyperref[sailRISCVztozybits]{to\_bits}#(cap_otype_width, cs2_cursor)); + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCClearTagzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCClearTagzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..c6d7cef5 --- /dev/null +++ b/sail_latex_riscv/fclCClearTagzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +#\hyperref[sailRISCVzC]{C}#(cd) = {cs1_val with tag=false}; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCClearzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCClearzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..3f8e0f24 --- /dev/null +++ b/sail_latex_riscv/fclCClearzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let q_u = #\hyperref[sailRISCVzunsigned]{unsigned}#(q); +foreach (i from 0 to 7) + if m[i] == bitone then + if q_u == 0 & i == 0 then + DDC = null_cap + else + #\hyperref[sailRISCVzC]{C}#(8 * q_u + i) = null_cap; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCCopyTypezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCCopyTypezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..3540f54f --- /dev/null +++ b/sail_latex_riscv/fclCCopyTypezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,25 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let cs2_val = #\hyperref[sailRISCVzC]{C}#(cs2); +let (cs1_base, cs1_top) = #\hyperref[sailRISCVzgetCapBounds]{getCapBounds}#(cs1_val); +let cs2_otype = #\hyperref[sailRISCVzunsigned]{unsigned}#(cs2_val.otype); +if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzhasReservedOType]{hasReservedOType}#(cs2_val) then { + #\hyperref[sailRISCVzC]{C}#(cd) = #\hyperref[sailRISCVzintzytozycap]{int\_to\_cap}#(#\hyperref[sailRISCVzEXTS]{EXTS}#(cs2_val.otype)); + RETIRE_SUCCESS +} else if cs2_otype < cs1_base then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); + RETIRE_FAIL +} else if cs2_otype >= cs1_top then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); + RETIRE_FAIL +} else { + let (success, cap) = #\hyperref[sailRISCVzsetCapAddr]{setCapAddr}#(cs1_val, #\hyperref[sailRISCVztozybits]{to\_bits}#(cap_addr_width, cs2_otype)); + assert(success, "CopyType: offset is in bounds so should be representable"); + #\hyperref[sailRISCVzC]{C}#(cd) = cap; + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCFromPtrzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCFromPtrzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..83371e1c --- /dev/null +++ b/sail_latex_riscv/fclCFromPtrzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,19 @@ +let cs1_val = if #\hyperref[sailRISCVzunsigned]{unsigned}#(cs1) == 0 then DDC else #\hyperref[sailRISCVzC]{C}#(cs1); +let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); +if rs2_val == #\hyperref[sailRISCVzzzeros]{zeros}#() then { + #\hyperref[sailRISCVzC]{C}#(cd) = null_cap; + RETIRE_SUCCESS +} else if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else { + let (success, newCap) = #\hyperref[sailRISCVzsetCapOffset]{setCapOffset}#(cs1_val, rs2_val); + if success then + #\hyperref[sailRISCVzC]{C}#(cd) = newCap + else + #\hyperref[sailRISCVzC]{C}#(cd) = #\hyperref[sailRISCVzinvalidateCap]{invalidateCap}#(newCap); + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCGetAddrzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCGetAddrzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..5587f283 --- /dev/null +++ b/sail_latex_riscv/fclCGetAddrzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let capVal = #\hyperref[sailRISCVzC]{C}#(cs1); +#\hyperref[sailRISCVzX]{X}#(rd) = capVal.address; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCGetBasezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCGetBasezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..5bf162d5 --- /dev/null +++ b/sail_latex_riscv/fclCGetBasezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let capVal = #\hyperref[sailRISCVzC]{C}#(cs1); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(capVal); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCGetFlagszexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCGetFlagszexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..0a70a033 --- /dev/null +++ b/sail_latex_riscv/fclCGetFlagszexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let capVal = #\hyperref[sailRISCVzC]{C}#(cs1); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzgetCapFlags]{getCapFlags}#(capVal)); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCGetLenzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCGetLenzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..7bcfa927 --- /dev/null +++ b/sail_latex_riscv/fclCGetLenzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +let capVal = #\hyperref[sailRISCVzC]{C}#(cs1); +let len = #\hyperref[sailRISCVzgetCapLength]{getCapLength}#(capVal); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVztozybits]{to\_bits}#(sizeof(xlen), if len > MAX_ADDR then MAX_ADDR else len); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCGetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCGetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..46c2297a --- /dev/null +++ b/sail_latex_riscv/fclCGetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let capVal = #\hyperref[sailRISCVzC]{C}#(cs1); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(capVal); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCGetPermzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCGetPermzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..b2cfe987 --- /dev/null +++ b/sail_latex_riscv/fclCGetPermzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let capVal = #\hyperref[sailRISCVzC]{C}#(cs1); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzgetCapPerms]{getCapPerms}#(capVal)); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCGetSealedzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCGetSealedzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e51cd6ec --- /dev/null +++ b/sail_latex_riscv/fclCGetSealedzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let capVal = #\hyperref[sailRISCVzC]{C}#(cs1); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(#\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(capVal))); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCGetTagzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCGetTagzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..4164afa5 --- /dev/null +++ b/sail_latex_riscv/fclCGetTagzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let capVal = #\hyperref[sailRISCVzC]{C}#(cs1); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(capVal.tag)); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCGetTypezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCGetTypezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..8bd3e0b3 --- /dev/null +++ b/sail_latex_riscv/fclCGetTypezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,5 @@ +let capVal = #\hyperref[sailRISCVzC]{C}#(cs1); +#\hyperref[sailRISCVzX]{X}#(rd) = if #\hyperref[sailRISCVzhasReservedOType]{hasReservedOType}#(capVal) + then #\hyperref[sailRISCVzEXTS]{EXTS}#(capVal.otype) + else #\hyperref[sailRISCVzEXTZ]{EXTZ}#(capVal.otype); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCIncOffsetImmediatezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCIncOffsetImmediatezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e301c318 --- /dev/null +++ b/sail_latex_riscv/fclCIncOffsetImmediatezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,13 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let immBits : xlenbits = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm); +if cs1_val.tag & #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else { + let (success, newCap) = #\hyperref[sailRISCVzincCapOffset]{incCapOffset}#(cs1_val, immBits); + if success then + #\hyperref[sailRISCVzC]{C}#(cd) = newCap + else + #\hyperref[sailRISCVzC]{C}#(cd) = #\hyperref[sailRISCVzinvalidateCap]{invalidateCap}#(newCap); + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCIncOffsetzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCIncOffsetzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..2df5550c --- /dev/null +++ b/sail_latex_riscv/fclCIncOffsetzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,13 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); +if cs1_val.tag & #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else { + let (success, newCap) = #\hyperref[sailRISCVzincCapOffset]{incCapOffset}#(cs1_val, rs2_val); + if success then + #\hyperref[sailRISCVzC]{C}#(cd) = newCap + else + #\hyperref[sailRISCVzC]{C}#(cd) = #\hyperref[sailRISCVzinvalidateCap]{invalidateCap}#(newCap); + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCInvokezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCInvokezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..7619bfe9 --- /dev/null +++ b/sail_latex_riscv/fclCInvokezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,46 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let cs2_val = #\hyperref[sailRISCVzC]{C}#(cs2); +let newPC = [cs1_val.address with 0 = bitzero]; /* clear bit zero as for RISCV JALR */ +let newPCCBase = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(cs1_val); +if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs2_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs2); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzhasReservedOType]{hasReservedOType}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzhasReservedOType]{hasReservedOType}#(cs2_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs2); + RETIRE_FAIL +} else if cs1_val.otype != cs2_val.otype then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TypeViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs1_val.permit_cinvoke) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_PermitCInvokeViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs2_val.permit_cinvoke) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_PermitCInvokeViolation, cs2); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs1_val.permit_execute) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_PermitExecuteViolation, cs1); + RETIRE_FAIL +} else if cs2_val.permit_execute then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_PermitExecuteViolation, cs2); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(cs1_val, newPC, #\hyperref[sailRISCVzminzyinstructionzybytes]{min\_instruction\_bytes}#())) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); + RETIRE_FAIL +} else if newPCCBase[0] == bitone | (newPCCBase[1] == bitone & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#())) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_UnalignedBase, cs1); + RETIRE_FAIL +} else if newPC[1] == bitone & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#()) then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(newPC, #\hyperref[sailRISCVzEzyFetchzyAddrzyAlign]{E\_Fetch\_Addr\_Align}#()); + RETIRE_FAIL +} else { + #\hyperref[sailRISCVzC]{C}#(31) = #\hyperref[sailRISCVzunsealCap]{unsealCap}#(cs2_val); + nextPC = newPC; + nextPCC = #\hyperref[sailRISCVzunsealCap]{unsealCap}#(cs1_val); + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCJALRzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCJALRzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..61215ab7 --- /dev/null +++ b/sail_latex_riscv/fclCJALRzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,30 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let newPC = [cs1_val.address with 0 = bitzero]; /* clear bit zero as for RISCV JALR */ +let newPCCBase = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(cs1_val); +if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) & (#\hyperref[sailRISCVzsigned]{signed}#(cs1_val.otype) != otype_sentry) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs1_val.permit_execute) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_PermitExecuteViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(cs1_val, newPC, #\hyperref[sailRISCVzminzyinstructionzybytes]{min\_instruction\_bytes}#())) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); + RETIRE_FAIL +} else if newPCCBase[0] == bitone | (newPCCBase[1] == bitone & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#())) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_UnalignedBase, cs1); + RETIRE_FAIL +} else if newPC[1] == bitone & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#()) then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(newPC, #\hyperref[sailRISCVzEzyFetchzyAddrzyAlign]{E\_Fetch\_Addr\_Align}#()); + RETIRE_FAIL +} else { + let (success, linkCap) = #\hyperref[sailRISCVzsetCapAddr]{setCapAddr}#(PCC, nextPC); /* Note that nextPC accounts for compressed instrucitons */ + assert(success, "Link cap should always be representable."); + assert(#\hyperref[sailRISCVznot]{not}# (#\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(linkCap)), "Link cap should always be unsealed"); + #\hyperref[sailRISCVzC]{C}#(cd) = #\hyperref[sailRISCVzsealCap]{sealCap}#(linkCap, #\hyperref[sailRISCVztozybits]{to\_bits}#(cap_otype_width, otype_sentry)); + nextPC = newPC; + nextPCC = #\hyperref[sailRISCVzunsealCap]{unsealCap}#(cs1_val); + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCLoadTagszexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCLoadTagszexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d790fb80 --- /dev/null +++ b/sail_latex_riscv/fclCLoadTagszexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,52 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let vaddr = cs1_val.address; +let aq : bool = false; +let rl : bool = false; +if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs1_val.permit_load) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_PermitLoadViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs1_val.permit_load_cap) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_PermitLoadCapViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(cs1_val, vaddr, caps_per_cache_line * cap_size)) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (#\hyperref[sailRISCVzunsigned]{unsigned}#(vaddr) % (caps_per_cache_line * cap_size) == 0) then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, #\hyperref[sailRISCVzEzyLoadzyAddrzyAlign]{E\_Load\_Addr\_Align}#()); + RETIRE_FAIL +} else match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddr, #\hyperref[sailRISCVzRead]{Read}#(Cap)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(_), _) => { #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("unexpected cheri exception for tags load") }, + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, ptw_info) => { + if ptw_info.ptw_lc != PTW_LC_OK then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, #\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(EXC_LOAD_CAP_PAGE_FAULT)); + RETIRE_FAIL + } else { + mtags : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(#\hyperref[sailRISCVzbits]{bits}#(caps_per_cache_line)) = #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzzzeros]{zeros}#()); + + foreach (i from 0 #\hyperref[sailRISCVzto]{to}# (caps_per_cache_line - 1)) { + match mtags { + #\hyperref[sailRISCVzMemException]{MemException}#(_) => (), + #\hyperref[sailRISCVzMemValue]{MemValue}#(tags) => { + match #\hyperref[sailRISCVzmemzyreadzycap]{mem\_read\_cap}#(addr + i * cap_size, aq, rl, false) { + #\hyperref[sailRISCVzMemException]{MemException}#(e) => mtags = #\hyperref[sailRISCVzMemException]{MemException}#(e), + #\hyperref[sailRISCVzMemValue]{MemValue}#(v) => + mtags = #\hyperref[sailRISCVzMemValue]{MemValue}#([tags with i = #\hyperref[sailRISCVzboolzytozybit]{bool\_to\_bit}#(v.tag)]) + } + } + } + }; + + match mtags { + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(v) => { #\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(v); RETIRE_SUCCESS } + } + } + } +} diff --git a/sail_latex_riscv/fclCMovezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCMovezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..cf8ad331 --- /dev/null +++ b/sail_latex_riscv/fclCMovezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +#\hyperref[sailRISCVzC]{C}#(cd) = #\hyperref[sailRISCVzC]{C}#(cs1); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCRAMzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCRAMzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..c46461c7 --- /dev/null +++ b/sail_latex_riscv/fclCRAMzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let len = #\hyperref[sailRISCVzX]{X}#(rs1); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzgetRepresentableAlignmentMask]{getRepresentableAlignmentMask}#(len); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCRRLzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCRRLzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..446f9317 --- /dev/null +++ b/sail_latex_riscv/fclCRRLzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let len = #\hyperref[sailRISCVzX]{X}#(rs1); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzgetRepresentableLength]{getRepresentableLength}#(len); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCSEQXzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCSEQXzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..c4f25276 --- /dev/null +++ b/sail_latex_riscv/fclCSEQXzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let cs2_val = #\hyperref[sailRISCVzC]{C}#(cs2); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cs1_val == cs2_val)); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCSRzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCSRzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..f79cbaff --- /dev/null +++ b/sail_latex_riscv/fclCSRzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,22 @@ +let rs1_val : xlenbits = if is_imm then #\hyperref[sailRISCVzEXTZ]{EXTZ}#(rs1) else #\hyperref[sailRISCVzX]{X}#(rs1); +let isWrite : bool = match op { + CSRRW => true, + _ => if is_imm then #\hyperref[sailRISCVzunsigned]{unsigned}#(rs1_val) != 0 else #\hyperref[sailRISCVzunsigned]{unsigned}#(rs1) != 0 +}; +if ~ (#\hyperref[sailRISCVzcheckzyCSR]{check\_CSR}#(csr, cur_privilege, isWrite)) +then { #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); RETIRE_FAIL } +else if ~ (#\hyperref[sailRISCVzextzycheckzyCSR]{ext\_check\_CSR}#(csr, cur_privilege, isWrite)) +then { #\hyperref[sailRISCVzextzycheckzyCSRzyfail]{ext\_check\_CSR\_fail}#(); RETIRE_FAIL } +else { + let csr_val = #\hyperref[sailRISCVzreadCSR]{readCSR}#(csr); /* could have side-effects, so technically shouldn't perform for CSRW[I] with rd == 0 */ + if isWrite then { + let new_val : xlenbits = match op { + CSRRW => rs1_val, + CSRRS => csr_val | rs1_val, + CSRRC => csr_val & ~(rs1_val) + }; + #\hyperref[sailRISCVzwriteCSR]{writeCSR}#(csr, new_val) + }; + #\hyperref[sailRISCVzX]{X}#(rd) = csr_val; + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCSealEntryzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCSealEntryzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..473f0352 --- /dev/null +++ b/sail_latex_riscv/fclCSealEntryzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if (#\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val)) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs1_val.permit_execute) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_PermitExecuteViolation, cs1); + RETIRE_FAIL +} else { + #\hyperref[sailRISCVzC]{C}#(cd) = #\hyperref[sailRISCVzsealCap]{sealCap}#(cs1_val, #\hyperref[sailRISCVztozybits]{to\_bits}#(cap_otype_width, otype_sentry)); + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCSealzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCSealzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..3c26c367 --- /dev/null +++ b/sail_latex_riscv/fclCSealzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,32 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let cs2_val = #\hyperref[sailRISCVzC]{C}#(cs2); +let cs2_cursor = #\hyperref[sailRISCVzgetCapCursor]{getCapCursor}#(cs2_val); +let (cs2_base, cs2_top) = #\hyperref[sailRISCVzgetCapBounds]{getCapBounds}#(cs2_val); +if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs2_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs2); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs2_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs2); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs2_val.permit_seal) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_PermitSealViolation, cs2); + RETIRE_FAIL +} else if cs2_cursor < cs2_base then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs2); + RETIRE_FAIL +} else if cs2_cursor >= cs2_top then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs2); + RETIRE_FAIL +} else if cs2_cursor > max_otype then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs2); + RETIRE_FAIL +} else { + #\hyperref[sailRISCVzC]{C}#(cd) = #\hyperref[sailRISCVzsealCap]{sealCap}#(cs1_val, #\hyperref[sailRISCVztozybits]{to\_bits}#(cap_otype_width, cs2_cursor)); + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCSetAddrzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCSetAddrzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..0c1ca64b --- /dev/null +++ b/sail_latex_riscv/fclCSetAddrzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,13 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); +if cs1_val.tag & #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else { + let (representable, newCap) = #\hyperref[sailRISCVzsetCapAddr]{setCapAddr}#(cs1_val, rs2_val); + if representable then + #\hyperref[sailRISCVzC]{C}#(cd) = newCap + else + #\hyperref[sailRISCVzC]{C}#(cd) = #\hyperref[sailRISCVzinvalidateCap]{invalidateCap}#(newCap); + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCSetBoundsExactzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCSetBoundsExactzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..5cd9ca7b --- /dev/null +++ b/sail_latex_riscv/fclCSetBoundsExactzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,23 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); +let newBase = cs1_val.address; +let newTop : CapLenBits = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(newBase) + #\hyperref[sailRISCVzEXTZ]{EXTZ}#(rs2_val); +if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(cs1_val, newBase, #\hyperref[sailRISCVzunsigned]{unsigned}#(rs2_val))) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); + RETIRE_FAIL +} else { + let (exact, newCap) = #\hyperref[sailRISCVzsetCapBounds]{setCapBounds}#(cs1_val, newBase, newTop); + if #\hyperref[sailRISCVznot]{not}# (exact) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_InexactBounds, cs1); + RETIRE_FAIL + } else { + #\hyperref[sailRISCVzC]{C}#(cd) = newCap; + RETIRE_SUCCESS + } +} diff --git a/sail_latex_riscv/fclCSetBoundsImmediatezexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCSetBoundsImmediatezexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..481d4153 --- /dev/null +++ b/sail_latex_riscv/fclCSetBoundsImmediatezexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,17 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let newBase = cs1_val.address; +let newTop : CapLenBits = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(newBase) + #\hyperref[sailRISCVzEXTZ]{EXTZ}#(uimm); +if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(cs1_val, newBase, #\hyperref[sailRISCVzunsigned]{unsigned}#(uimm))) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); + RETIRE_FAIL +} else { + let (_, newCap) = #\hyperref[sailRISCVzsetCapBounds]{setCapBounds}#(cs1_val, newBase, newTop); + #\hyperref[sailRISCVzC]{C}#(cd) = newCap; /* ignore exact */ + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCSetBoundszexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCSetBoundszexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..9c319ae6 --- /dev/null +++ b/sail_latex_riscv/fclCSetBoundszexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,18 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); +let newBase = cs1_val.address; +let newTop : CapLenBits = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(newBase) + #\hyperref[sailRISCVzEXTZ]{EXTZ}#(rs2_val); +if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(cs1_val, newBase, #\hyperref[sailRISCVzunsigned]{unsigned}#(rs2_val))) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs1); + RETIRE_FAIL +} else { + let (_, newCap) = #\hyperref[sailRISCVzsetCapBounds]{setCapBounds}#(cs1_val, newBase, newTop); + #\hyperref[sailRISCVzC]{C}#(cd) = newCap; /* ignore exact */ + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCSetFlagszexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCSetFlagszexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..27bfb4bc --- /dev/null +++ b/sail_latex_riscv/fclCSetFlagszexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,10 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); +if cs1_val.tag & #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else { + let newCap = #\hyperref[sailRISCVzsetCapFlags]{setCapFlags}#(cs1_val, #\hyperref[sailRISCVztruncate]{truncate}#(rs2_val, cap_flags_width)); + #\hyperref[sailRISCVzC]{C}#(cd) = newCap; + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCSetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCSetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..aba49601 --- /dev/null +++ b/sail_latex_riscv/fclCSetOffsetzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,13 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); +if cs1_val.tag & #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else { + let (success, newCap) = #\hyperref[sailRISCVzsetCapOffset]{setCapOffset}#(cs1_val, rs2_val); + if success then + #\hyperref[sailRISCVzC]{C}#(cd) = newCap + else + #\hyperref[sailRISCVzC]{C}#(cd) = #\hyperref[sailRISCVzinvalidateCap]{invalidateCap}#(newCap); + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCSpecialRWzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCSpecialRWzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d4cd5630 --- /dev/null +++ b/sail_latex_riscv/fclCSpecialRWzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,68 @@ +let (specialExists, ro, priv, needASR) : (bool, bool, Privilege, bool) = match #\hyperref[sailRISCVzunsigned]{unsigned}#(scr) { + 0 => (true, true, User, false), + 1 => (true, false, User, false), + 4 if #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() => (true, false, User, true), + 5 if #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() => (true, false, User, true), + 6 if #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() => (true, false, User, true), + 7 if #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() => (true, false, User, true), + 12 if #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() => (true, false, Supervisor, true), + 13 if #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() => (true, false, Supervisor, true), + 14 if #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() => (true, false, Supervisor, true), + 15 if #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() => (true, false, Supervisor, true), + 28 => (true, false, Machine, true), + 29 => (true, false, Machine, true), + 30 => (true, false, Machine, true), + 31 => (true, false, Machine, true), + _ => (false, true, Machine, true) +}; +if (#\hyperref[sailRISCVznot]{not}#(specialExists) | + ro & cs1 != #\hyperref[sailRISCVzzzeros]{zeros}#() | + (#\hyperref[sailRISCVzprivLevelzytozybits]{privLevel\_to\_bits}#(cur_privilege) <_u #\hyperref[sailRISCVzprivLevelzytozybits]{privLevel\_to\_bits}#(priv))) then { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} else if (needASR & #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}#())) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_AccessSystemRegsViolation, 0b1 @ scr); + RETIRE_FAIL +} else { + let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); + #\hyperref[sailRISCVzC]{C}#(cd) = match #\hyperref[sailRISCVzunsigned]{unsigned}#(scr) { + 0 => { + let (success, pcc) = #\hyperref[sailRISCVzsetCapAddr]{setCapAddr}#(PCC, PC); + assert (success, "PCC with offset PC should always be representable"); + pcc + }, + 1 => DDC, + 4 => UTCC, + 5 => UTDC, + 6 => UScratchC, + 7 => #\hyperref[sailRISCVzlegalizzezyepcc]{legalize\_epcc}#(UEPCC), + 12 => STCC, + 13 => STDC, + 14 => SScratchC, + 15 => #\hyperref[sailRISCVzlegalizzezyepcc]{legalize\_epcc}#(SEPCC), + 28 => MTCC, + 29 => MTDC, + 30 => MScratchC, + 31 => #\hyperref[sailRISCVzlegalizzezyepcc]{legalize\_epcc}#(MEPCC), + _ => {assert(false, "unreachable"); undefined} + }; + if (cs1 != #\hyperref[sailRISCVzzzeros]{zeros}#()) then { + match #\hyperref[sailRISCVzunsigned]{unsigned}#(scr) { + 1 => DDC = cs1_val, + 4 => UTCC = #\hyperref[sailRISCVzlegalizzezytcc]{legalize\_tcc}#(UTCC, cs1_val), + 5 => UTDC = cs1_val, + 6 => UScratchC = cs1_val, + 7 => UEPCC = cs1_val, + 12 => STCC = #\hyperref[sailRISCVzlegalizzezytcc]{legalize\_tcc}#(STCC, cs1_val), + 13 => STDC = cs1_val, + 14 => SScratchC = cs1_val, + 15 => SEPCC = cs1_val, + 28 => MTCC = #\hyperref[sailRISCVzlegalizzezytcc]{legalize\_tcc}#(MTCC, cs1_val), + 29 => MTDC = cs1_val, + 30 => MScratchC = cs1_val, + 31 => MEPCC = cs1_val, + _ => assert(false, "unreachable") + } + }; + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCSubzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCSubzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..b4acbe28 --- /dev/null +++ b/sail_latex_riscv/fclCSubzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +let cs2_val = #\hyperref[sailRISCVzC]{C}#(cs2); +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +#\hyperref[sailRISCVzX]{X}#(rd) = cs1_val.address - cs2_val.address; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCTestSubsetzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCTestSubsetzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..fa0f3c9c --- /dev/null +++ b/sail_latex_riscv/fclCTestSubsetzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,18 @@ +let cs1_val = if #\hyperref[sailRISCVzunsigned]{unsigned}#(cs1) == 0 then DDC else #\hyperref[sailRISCVzC]{C}#(cs1); +let cs2_val = #\hyperref[sailRISCVzC]{C}#(cs2); +let (cs2_base, cs2_top) = #\hyperref[sailRISCVzgetCapBounds]{getCapBounds}#(cs2_val); +let (cs1_base, cs1_top) = #\hyperref[sailRISCVzgetCapBounds]{getCapBounds}#(cs1_val); +let cs2_perms = #\hyperref[sailRISCVzgetCapPerms]{getCapPerms}#(cs2_val); +let cs1_perms = #\hyperref[sailRISCVzgetCapPerms]{getCapPerms}#(cs1_val); +let result = if cs1_val.tag != cs2_val.tag then + 0b0 + else if cs2_base < cs1_base then + 0b0 + else if cs2_top > cs1_top then + 0b0 + else if (cs2_perms & cs1_perms) != cs2_perms then + 0b0 + else + 0b1; +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(result); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCToPtrzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCToPtrzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..a8e19fd8 --- /dev/null +++ b/sail_latex_riscv/fclCToPtrzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,16 @@ +let cs2_val = if #\hyperref[sailRISCVzunsigned]{unsigned}#(cs2) == 0 then DDC else #\hyperref[sailRISCVzC]{C}#(cs2); +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +if #\hyperref[sailRISCVznot]{not}# (cs2_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs2); + RETIRE_FAIL +} else if cs1_val.tag & #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else { + /* Note: returning zero for untagged values breaks magic constants such as SIG_IGN */ + #\hyperref[sailRISCVzX]{X}#(rd) = if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then + #\hyperref[sailRISCVzzzeros]{zeros}#() + else + cs1_val.address - #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(cs2_val); + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclCUnderscoreADDIFourSPNzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreADDIFourSPNzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..1a58e023 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreADDIFourSPNzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let imm : #\hyperref[sailRISCVzbits]{bits}#(12) = (0b00 @ nzimm @ 0b00); +let rd = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rdc); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzITYPE]{ITYPE}#(imm, sp, rd, RISCV_ADDI)) diff --git a/sail_latex_riscv/fclCUnderscoreADDIOneSixSPzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreADDIOneSixSPzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..3381ed25 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreADDIOneSixSPzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +let imm : #\hyperref[sailRISCVzbits]{bits}#(12) = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm @ 0x0); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzITYPE]{ITYPE}#(imm, sp, sp, RISCV_ADDI)) diff --git a/sail_latex_riscv/fclCUnderscoreADDIWzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreADDIWzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclCUnderscoreADDIzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreADDIzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..008b7033 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreADDIzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +let imm : #\hyperref[sailRISCVzbits]{bits}#(12) = #\hyperref[sailRISCVzEXTS]{EXTS}#(nzi); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzITYPE]{ITYPE}#(imm, rsd, rsd, RISCV_ADDI)) diff --git a/sail_latex_riscv/fclCUnderscoreADDWzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreADDWzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..74fa492c --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreADDWzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let rsd = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsd); +let rs2 = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rs2); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzRTYPEW]{RTYPEW}#(rs2, rsd, rsd, RISCV_ADDW)) diff --git a/sail_latex_riscv/fclCUnderscoreADDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreADDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclCUnderscoreANDIzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreANDIzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..adf92512 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreANDIzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +let rsd = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsd); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzITYPE]{ITYPE}#(#\hyperref[sailRISCVzEXTS]{EXTS}#(imm), rsd, rsd, RISCV_ANDI)) diff --git a/sail_latex_riscv/fclCUnderscoreANDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreANDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..37bf85d4 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreANDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let rsd = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsd); +let rs2 = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rs2); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzRTYPE]{RTYPE}#(rs2, rsd, rsd, RISCV_AND)) diff --git a/sail_latex_riscv/fclCUnderscoreBEQZzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreBEQZzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclCUnderscoreBNEZzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreBNEZzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclCUnderscoreEBREAKzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreEBREAKzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclCUnderscoreILLEGALzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreILLEGALzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclCUnderscoreJALRzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreJALRzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclCUnderscoreJALzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreJALzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclCUnderscoreJRzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreJRzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclCUnderscoreJzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreJzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclCUnderscoreLDSPzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreLDSPzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..3ef7ece6 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreLDSPzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +let imm : #\hyperref[sailRISCVzbits]{bits}#(12) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(uimm @ 0b000); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzLOAD]{LOAD}#(imm, sp, rd, false, DOUBLE, false, false)) diff --git a/sail_latex_riscv/fclCUnderscoreLDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreLDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..394779dc --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreLDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +let imm : #\hyperref[sailRISCVzbits]{bits}#(12) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(uimm @ 0b000); +let rd = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rdc); +let rs = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsc); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzLOAD]{LOAD}#(imm, rs, rd, false, DOUBLE, false, false)) diff --git a/sail_latex_riscv/fclCUnderscoreLIzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreLIzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..5adc4676 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreLIzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +let imm : #\hyperref[sailRISCVzbits]{bits}#(12) = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzITYPE]{ITYPE}#(imm, zreg, rd, RISCV_ADDI)) diff --git a/sail_latex_riscv/fclCUnderscoreLUIzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreLUIzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..bb3e95bf --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreLUIzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +let res : #\hyperref[sailRISCVzbits]{bits}#(20) = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzUTYPE]{UTYPE}#(res, rd, RISCV_LUI)) diff --git a/sail_latex_riscv/fclCUnderscoreLWSPzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreLWSPzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..6c8c4bd8 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreLWSPzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +let imm : #\hyperref[sailRISCVzbits]{bits}#(12) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(uimm @ 0b00); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzLOAD]{LOAD}#(imm, sp, rd, false, WORD, false, false)) diff --git a/sail_latex_riscv/fclCUnderscoreLWzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreLWzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..714068a8 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreLWzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +let imm : #\hyperref[sailRISCVzbits]{bits}#(12) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(uimm @ 0b00); +let rd = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rdc); +let rs = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsc); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzLOAD]{LOAD}#(imm, rs, rd, false, WORD, false, false)) diff --git a/sail_latex_riscv/fclCUnderscoreMVzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreMVzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclCUnderscoreNOPzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreNOPzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclCUnderscoreORzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreORzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..fea17481 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreORzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let rsd = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsd); +let rs2 = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rs2); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzRTYPE]{RTYPE}#(rs2, rsd, rsd, RISCV_OR)) diff --git a/sail_latex_riscv/fclCUnderscoreSDSPzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreSDSPzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..310d1d4a --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreSDSPzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +let imm : #\hyperref[sailRISCVzbits]{bits}#(12) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(uimm @ 0b000); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzSTORE]{STORE}#(imm, rs2, sp, DOUBLE, false, false)) diff --git a/sail_latex_riscv/fclCUnderscoreSDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreSDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..2cefc699 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreSDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +let imm : #\hyperref[sailRISCVzbits]{bits}#(12) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(uimm @ 0b000); +let rs1 = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsc1); +let rs2 = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsc2); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzSTORE]{STORE}#(imm, rs2, rs1, DOUBLE, false, false)) diff --git a/sail_latex_riscv/fclCUnderscoreSLLIzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreSLLIzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclCUnderscoreSRAIzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreSRAIzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..10f90d1e --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreSRAIzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +let rsd = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsd); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzSHIFTIOP]{SHIFTIOP}#(shamt, rsd, rsd, RISCV_SRAI)) diff --git a/sail_latex_riscv/fclCUnderscoreSRLIzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreSRLIzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..a7c343d8 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreSRLIzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +let rsd = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsd); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzSHIFTIOP]{SHIFTIOP}#(shamt, rsd, rsd, RISCV_SRLI)) diff --git a/sail_latex_riscv/fclCUnderscoreSUBWzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreSUBWzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..7001fbf4 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreSUBWzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let rsd = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsd); +let rs2 = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rs2); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzRTYPEW]{RTYPEW}#(rs2, rsd, rsd, RISCV_SUBW)) diff --git a/sail_latex_riscv/fclCUnderscoreSUBzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreSUBzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..9e35db02 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreSUBzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let rsd = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsd); +let rs2 = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rs2); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzRTYPE]{RTYPE}#(rs2, rsd, rsd, RISCV_SUB)) diff --git a/sail_latex_riscv/fclCUnderscoreSWSPzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreSWSPzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..80b18c95 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreSWSPzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +let imm : #\hyperref[sailRISCVzbits]{bits}#(12) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(uimm @ 0b00); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzSTORE]{STORE}#(imm, rs2, sp, WORD, false, false)) diff --git a/sail_latex_riscv/fclCUnderscoreSWzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreSWzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..8fb73b89 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreSWzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +let imm : #\hyperref[sailRISCVzbits]{bits}#(12) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(uimm @ 0b00); +let rs1 = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsc1); +let rs2 = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsc2); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzSTORE]{STORE}#(imm, rs2, rs1, WORD, false, false)) diff --git a/sail_latex_riscv/fclCUnderscoreXORzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnderscoreXORzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..bc099499 --- /dev/null +++ b/sail_latex_riscv/fclCUnderscoreXORzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let rsd = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rsd); +let rs2 = #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(rs2); +#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzRTYPE]{RTYPE}#(rs2, rsd, rsd, RISCV_XOR)) diff --git a/sail_latex_riscv/fclCUnsealzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclCUnsealzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..87d9d2bc --- /dev/null +++ b/sail_latex_riscv/fclCUnsealzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,36 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let cs2_val = #\hyperref[sailRISCVzC]{C}#(cs2); +let cs2_cursor = #\hyperref[sailRISCVzgetCapCursor]{getCapCursor}#(cs2_val); +let (cs2_base, cs2_top) = #\hyperref[sailRISCVzgetCapBounds]{getCapBounds}#(cs2_val); +if #\hyperref[sailRISCVznot]{not}# (cs1_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs2_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TagViolation, cs2); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (#\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs1_val)) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs1); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cs2_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_SealViolation, cs2); + RETIRE_FAIL +} else if #\hyperref[sailRISCVzhasReservedOType]{hasReservedOType}#(cs1_val) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TypeViolation, cs1); + RETIRE_FAIL +} else if cs2_cursor != #\hyperref[sailRISCVzunsigned]{unsigned}#(cs1_val.otype) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_TypeViolation, cs2); + RETIRE_FAIL +} else if #\hyperref[sailRISCVznot]{not}# (cs2_val.permit_unseal) then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_PermitUnsealViolation, cs2); + RETIRE_FAIL +} else if cs2_cursor < cs2_base then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs2); + RETIRE_FAIL +} else if cs2_cursor >= cs2_top then { + #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(CapEx_LengthViolation, cs2); + RETIRE_FAIL +} else { + let new_global = cs1_val.global & cs2_val.global; + #\hyperref[sailRISCVzC]{C}#(cd) = {#\hyperref[sailRISCVzunsealCap]{unsealCap}#(cs1_val) with global=new_global}; + RETIRE_SUCCESS +} diff --git a/sail_latex_riscv/fclClearzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclClearzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..33987df4 --- /dev/null +++ b/sail_latex_riscv/fclClearzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,5 @@ +let q_u = #\hyperref[sailRISCVzunsigned]{unsigned}#(q); +foreach (i from 0 to 7) + if m[i] == bitone then + #\hyperref[sailRISCVzX]{X}#(8 * q_u + i) = #\hyperref[sailRISCVzzzeros]{zeros}#(); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclCzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclCzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..5faff1cb --- /dev/null +++ b/sail_latex_riscv/fclCzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}#(0x000, value) = { mstatus = #\hyperref[sailRISCVzlegalizzezyustatus]{legalize\_ustatus}#(mstatus, value); #\hyperref[sailRISCVzSome]{Some}#(mstatus.#\hyperref[sailRISCVzbits]{bits}#()) } diff --git a/sail_latex_riscv/fclDIVWzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclDIVWzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..46216b91 --- /dev/null +++ b/sail_latex_riscv/fclDIVWzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +if #\hyperref[sailRISCVzhaveMulDiv]{haveMulDiv}#() then { + let rs1_val = #\hyperref[sailRISCVzX]{X}#(rs1)[31..0]; + let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2)[31..0]; + let rs1_int : int = if s then #\hyperref[sailRISCVzsigned]{signed}#(rs1_val) else #\hyperref[sailRISCVzunsigned]{unsigned}#(rs1_val); + let rs2_int : int = if s then #\hyperref[sailRISCVzsigned]{signed}#(rs2_val) else #\hyperref[sailRISCVzunsigned]{unsigned}#(rs2_val); + let q : int = if rs2_int == 0 then -1 else #\hyperref[sailRISCVzquotzyroundzyzzero]{quot\_round\_zero}#(rs1_int, rs2_int); + /* check for signed overflow */ + let q': int = if s & q > (2 ^ 31 - 1) then (0 - 2^31) else q; + #\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTS]{EXTS}#(#\hyperref[sailRISCVztozybits]{to\_bits}#(32, q')); + RETIRE_SUCCESS +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclDIVzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclDIVzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..f80a0d2f --- /dev/null +++ b/sail_latex_riscv/fclDIVzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +if #\hyperref[sailRISCVzhaveMulDiv]{haveMulDiv}#() then { + let rs1_val = #\hyperref[sailRISCVzX]{X}#(rs1); + let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); + let rs1_int : int = if s then #\hyperref[sailRISCVzsigned]{signed}#(rs1_val) else #\hyperref[sailRISCVzunsigned]{unsigned}#(rs1_val); + let rs2_int : int = if s then #\hyperref[sailRISCVzsigned]{signed}#(rs2_val) else #\hyperref[sailRISCVzunsigned]{unsigned}#(rs2_val); + let q : int = if rs2_int == 0 then -1 else #\hyperref[sailRISCVzquotzyroundzyzzero]{quot\_round\_zero}#(rs1_int, rs2_int); + /* check for signed overflow */ + let q': int = if s & q > xlen_max_signed then xlen_min_signed else q; + #\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVztozybits]{to\_bits}#(sizeof(xlen), q'); + RETIRE_SUCCESS +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclDzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclDzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..d8b2f8cc --- /dev/null +++ b/sail_latex_riscv/fclDzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1,3 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}#(0x004, value) = { let sie = #\hyperref[sailRISCVzlegalizzezyuie]{legalize\_uie}#(#\hyperref[sailRISCVzlowerzymie]{lower\_mie}#(mie, mideleg), sideleg, value); + mie = #\hyperref[sailRISCVzliftzysie]{lift\_sie}#(mie, mideleg, sie); + #\hyperref[sailRISCVzSome]{Some}#(mie.#\hyperref[sailRISCVzbits]{bits}#()) } diff --git a/sail_latex_riscv/fclEBREAKzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclEBREAKzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..1c3d4432 --- /dev/null +++ b/sail_latex_riscv/fclEBREAKzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,2 @@ +#\hyperref[sailRISCVzhandlezyexception]{handle\_exception}#(#\hyperref[sailRISCVzEzyBreakpoint]{E\_Breakpoint}#()); +RETIRE_FAIL diff --git a/sail_latex_riscv/fclECALLzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclECALLzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..2fe15ca1 --- /dev/null +++ b/sail_latex_riscv/fclECALLzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,10 @@ +let t : sync_exception = + struct { trap = match (cur_privilege) { + User => #\hyperref[sailRISCVzEzyUzyEnvCall]{E\_U\_EnvCall}#(), + Supervisor => #\hyperref[sailRISCVzEzySzyEnvCall]{E\_S\_EnvCall}#(), + Machine => #\hyperref[sailRISCVzEzyMzyEnvCall]{E\_M\_EnvCall}#() + }, + excinfo = (#\hyperref[sailRISCVzNone]{None}#() : #\hyperref[sailRISCVzoption]{option}#(xlenbits)), + ext = #\hyperref[sailRISCVzNone]{None}#() }; +#\hyperref[sailRISCVzsetzynextzypc]{set\_next\_pc}#(#\hyperref[sailRISCVzexceptionzyhandler]{exception\_handler}#(cur_privilege, #\hyperref[sailRISCVzCTLzyTRAP]{CTL\_TRAP}#(t), PC)); +RETIRE_FAIL diff --git a/sail_latex_riscv/fclEXTZAzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclEXTZAzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..cb0d1d4e --- /dev/null +++ b/sail_latex_riscv/fclEXTZAzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}# (0x002) = #\hyperref[sailRISCVzSome]{Some}# (#\hyperref[sailRISCVzEXTZ]{EXTZ}# (fcsr.#\hyperref[sailRISCVzFRM]{FRM}#())) diff --git a/sail_latex_riscv/fclEXTZBzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclEXTZBzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..e4537817 --- /dev/null +++ b/sail_latex_riscv/fclEXTZBzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}# (0x003) = #\hyperref[sailRISCVzSome]{Some}# (#\hyperref[sailRISCVzEXTZ]{EXTZ}# (fcsr.#\hyperref[sailRISCVzbits]{bits}#())) diff --git a/sail_latex_riscv/fclEXTZzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclEXTZzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..83eda765 --- /dev/null +++ b/sail_latex_riscv/fclEXTZzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}# (0x001) = #\hyperref[sailRISCVzSome]{Some}# (#\hyperref[sailRISCVzEXTZ]{EXTZ}# (fcsr.#\hyperref[sailRISCVzFFLAGS]{FFLAGS}#())) diff --git a/sail_latex_riscv/fclEzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclEzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..d3a74843 --- /dev/null +++ b/sail_latex_riscv/fclEzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}#(0x005, value) = { #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzsetzyutvec]{set\_utvec}#(value)) } diff --git a/sail_latex_riscv/fclFENCEIzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFENCEIzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclFENCEUnderscoreTSOzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFENCEUnderscoreTSOzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..a63aa8a9 --- /dev/null +++ b/sail_latex_riscv/fclFENCEUnderscoreTSOzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +match (pred, succ) { + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11) => #\hyperref[sailRISCVzzyzybarrier]{\_\_barrier}#(#\hyperref[sailRISCVzBarrierzyRISCVzytso]{Barrier\_RISCV\_tso}#()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b00, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b00) => (), + + _ => { #\hyperref[sailRISCVzprint]{print}#("FIXME: unsupported fence"); + () } +}; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFENCEzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFENCEzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..0ee08753 --- /dev/null +++ b/sail_latex_riscv/fclFENCEzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,17 @@ +match (pred, succ) { + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11) => #\hyperref[sailRISCVzzyzybarrier]{\_\_barrier}#(#\hyperref[sailRISCVzBarrierzyRISCVzyrwzyrw]{Barrier\_RISCV\_rw\_rw}#()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b10, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11) => #\hyperref[sailRISCVzzyzybarrier]{\_\_barrier}#(#\hyperref[sailRISCVzBarrierzyRISCVzyrzyrw]{Barrier\_RISCV\_r\_rw}#()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b10, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b10) => #\hyperref[sailRISCVzzyzybarrier]{\_\_barrier}#(#\hyperref[sailRISCVzBarrierzyRISCVzyrzyr]{Barrier\_RISCV\_r\_r}#()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b01) => #\hyperref[sailRISCVzzyzybarrier]{\_\_barrier}#(#\hyperref[sailRISCVzBarrierzyRISCVzyrwzyw]{Barrier\_RISCV\_rw\_w}#()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b01, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b01) => #\hyperref[sailRISCVzzyzybarrier]{\_\_barrier}#(#\hyperref[sailRISCVzBarrierzyRISCVzywzyw]{Barrier\_RISCV\_w\_w}#()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b01, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11) => #\hyperref[sailRISCVzzyzybarrier]{\_\_barrier}#(#\hyperref[sailRISCVzBarrierzyRISCVzywzyrw]{Barrier\_RISCV\_w\_rw}#()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b10) => #\hyperref[sailRISCVzzyzybarrier]{\_\_barrier}#(#\hyperref[sailRISCVzBarrierzyRISCVzyrwzyr]{Barrier\_RISCV\_rw\_r}#()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b10, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b01) => #\hyperref[sailRISCVzzyzybarrier]{\_\_barrier}#(#\hyperref[sailRISCVzBarrierzyRISCVzyrzyw]{Barrier\_RISCV\_r\_w}#()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b01, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b10) => #\hyperref[sailRISCVzzyzybarrier]{\_\_barrier}#(#\hyperref[sailRISCVzBarrierzyRISCVzywzyr]{Barrier\_RISCV\_w\_r}#()), + + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b00, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b00) => (), + + _ => { #\hyperref[sailRISCVzprint]{print}#("FIXME: unsupported fence"); + () } +}; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFPClearzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFPClearzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d1a1dc10 --- /dev/null +++ b/sail_latex_riscv/fclFPClearzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,9 @@ +if #\hyperref[sailRISCVzhaveFExt]{haveFExt}#() then { + foreach (i from 0 to 7) + if m[i] == bitone then + #\hyperref[sailRISCVzF]{F}#(8 * #\hyperref[sailRISCVzunsigned]{unsigned}#(q) + i) = #\hyperref[sailRISCVzzzeros]{zeros}#(); + RETIRE_SUCCESS +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreRMUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreRMUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e9a61524 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreRMUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,12 @@ +let rs1_val_64b = #\hyperref[sailRISCVzF]{F}#(rs1); +let rs2_val_64b = #\hyperref[sailRISCVzF]{F}#(rs2); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); +let (fflags, rd_val_64b) : (#\hyperref[sailRISCVzbits]{bits}#(5), #\hyperref[sailRISCVzbits]{bits}#(64)) = match op { + FADD_D => #\hyperref[sailRISCVzriscvzyf64Add]{riscv\_f64Add}# (rm_3b, rs1_val_64b, rs2_val_64b), + FSUB_D => #\hyperref[sailRISCVzriscvzyf64Sub]{riscv\_f64Sub}# (rm_3b, rs1_val_64b, rs2_val_64b), + FMUL_D => #\hyperref[sailRISCVzriscvzyf64Mul]{riscv\_f64Mul}# (rm_3b, rs1_val_64b, rs2_val_64b), + FDIV_D => #\hyperref[sailRISCVzriscvzyf64Div]{riscv\_f64Div}# (rm_3b, rs1_val_64b, rs2_val_64b) +}; +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_64b; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreRMUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreRMUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..ae5ebefe --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreRMUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,12 @@ +let rs1_val_32b = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rs2_val_32b = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs2)); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); +let (fflags, rd_val_32b) : (#\hyperref[sailRISCVzbits]{bits}#(5), #\hyperref[sailRISCVzbits]{bits}#(32)) = match op { + FADD_S => #\hyperref[sailRISCVzriscvzyf32Add]{riscv\_f32Add}# (rm_3b, rs1_val_32b, rs2_val_32b), + FSUB_S => #\hyperref[sailRISCVzriscvzyf32Sub]{riscv\_f32Sub}# (rm_3b, rs1_val_32b, rs2_val_32b), + FMUL_S => #\hyperref[sailRISCVzriscvzyf32Mul]{riscv\_f32Mul}# (rm_3b, rs1_val_32b, rs2_val_32b), + FDIV_S => #\hyperref[sailRISCVzriscvzyf32Div]{riscv\_f32Div}# (rm_3b, rs1_val_32b, rs2_val_32b) +}; +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_32b); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDAzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDAzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..58c176dc --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDAzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rs2_val_D = #\hyperref[sailRISCVzF]{F}#(rs2); +let (s1, e1, m1) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (rs1_val_D); +let (s2, e2, m2) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (rs2_val_D); +let rd_val_D = #\hyperref[sailRISCVzfmakezyD]{fmake\_D}# (0b1 ^ s2, e1, m1); + +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_D; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDBzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDBzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..7c57135d --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDBzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rs2_val_D = #\hyperref[sailRISCVzF]{F}#(rs2); +let (s1, e1, m1) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (rs1_val_D); +let (s2, e2, m2) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (rs2_val_D); +let rd_val_D = #\hyperref[sailRISCVzfmakezyD]{fmake\_D}# (s1 ^ s2, e1, m1); + +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_D; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..a29ddaf8 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,17 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rs2_val_D = #\hyperref[sailRISCVzF]{F}#(rs2); + +let is_quiet = true; +let (rs1_lt_rs2, fflags) = #\hyperref[sailRISCVzflezyD]{fle\_D}# (rs1_val_D, rs2_val_D, is_quiet); + +let rd_val_D = if (#\hyperref[sailRISCVzfzyiszyNaNzyD]{f\_is\_NaN\_D}#(rs1_val_D) & #\hyperref[sailRISCVzfzyiszyNaNzyD]{f\_is\_NaN\_D}#(rs2_val_D)) then #\hyperref[sailRISCVzcanonicalzyNaNzyD]{canonical\_NaN\_D}#() + else if #\hyperref[sailRISCVzfzyiszyNaNzyD]{f\_is\_NaN\_D}#(rs1_val_D) then rs2_val_D + else if #\hyperref[sailRISCVzfzyiszyNaNzyD]{f\_is\_NaN\_D}#(rs2_val_D) then rs1_val_D + else if (#\hyperref[sailRISCVzfzyiszynegzyzzerozyD]{f\_is\_neg\_zero\_D}#(rs1_val_D) & #\hyperref[sailRISCVzfzyiszyposzyzzerozyD]{f\_is\_pos\_zero\_D}#(rs2_val_D)) then rs1_val_D + else if (#\hyperref[sailRISCVzfzyiszynegzyzzerozyD]{f\_is\_neg\_zero\_D}#(rs2_val_D) & #\hyperref[sailRISCVzfzyiszyposzyzzerozyD]{f\_is\_pos\_zero\_D}#(rs1_val_D)) then rs2_val_D + else if rs1_lt_rs2 then rs1_val_D + else /* (not rs1_lt_rs2) */ rs2_val_D; + +#\hyperref[sailRISCVzaccruezyfflags]{accrue\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_D; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..0770f673 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,17 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rs2_val_D = #\hyperref[sailRISCVzF]{F}#(rs2); + +let is_quiet = true; +let (rs2_lt_rs1, fflags) = #\hyperref[sailRISCVzflezyD]{fle\_D}# (rs2_val_D, rs1_val_D, is_quiet); + +let rd_val_D = if (#\hyperref[sailRISCVzfzyiszyNaNzyD]{f\_is\_NaN\_D}#(rs1_val_D) & #\hyperref[sailRISCVzfzyiszyNaNzyD]{f\_is\_NaN\_D}#(rs2_val_D)) then #\hyperref[sailRISCVzcanonicalzyNaNzyD]{canonical\_NaN\_D}#() + else if #\hyperref[sailRISCVzfzyiszyNaNzyD]{f\_is\_NaN\_D}#(rs1_val_D) then rs2_val_D + else if #\hyperref[sailRISCVzfzyiszyNaNzyD]{f\_is\_NaN\_D}#(rs2_val_D) then rs1_val_D + else if (#\hyperref[sailRISCVzfzyiszynegzyzzerozyD]{f\_is\_neg\_zero\_D}#(rs1_val_D) & #\hyperref[sailRISCVzfzyiszyposzyzzerozyD]{f\_is\_pos\_zero\_D}#(rs2_val_D)) then rs2_val_D + else if (#\hyperref[sailRISCVzfzyiszynegzyzzerozyD]{f\_is\_neg\_zero\_D}#(rs2_val_D) & #\hyperref[sailRISCVzfzyiszyposzyzzerozyD]{f\_is\_pos\_zero\_D}#(rs1_val_D)) then rs1_val_D + else if rs2_lt_rs1 then rs1_val_D + else /* (not rs2_lt_rs1) */ rs2_val_D; + +#\hyperref[sailRISCVzaccruezyfflags]{accrue\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_D; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDEzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDEzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..677fe651 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDEzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,9 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rs2_val_D = #\hyperref[sailRISCVzF]{F}#(rs2); + +let (fflags, rd_val) : (bits_fflags, bits_LU) = + #\hyperref[sailRISCVzriscvzyf64Eq]{riscv\_f64Eq}# (rs1_val_D, rs2_val_D); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzX]{X}#(rd) = rd_val; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDFzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDFzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..59f75671 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDFzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,9 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rs2_val_D = #\hyperref[sailRISCVzF]{F}#(rs2); + +let (fflags, rd_val) : (bits_fflags, bits_LU) = + #\hyperref[sailRISCVzriscvzyf64Lt]{riscv\_f64Lt}# (rs1_val_D, rs2_val_D); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzX]{X}#(rd) = rd_val; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDGzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDGzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..3230e20b --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDGzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,9 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rs2_val_D = #\hyperref[sailRISCVzF]{F}#(rs2); + +let (fflags, rd_val) : (bits_fflags, bits_LU) = + #\hyperref[sailRISCVzriscvzyf64Le]{riscv\_f64Le}# (rs1_val_D, rs2_val_D); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzX]{X}#(rd) = rd_val; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..af0c39ff --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rs2_val_D = #\hyperref[sailRISCVzF]{F}#(rs2); +let (s1, e1, m1) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (rs1_val_D); +let (s2, e2, m2) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (rs2_val_D); +let rd_val_D = #\hyperref[sailRISCVzfmakezyD]{fmake\_D}# (s2, e1, m1); + +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_D; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSAzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSAzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..0b8450d4 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSAzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rs2_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs2)); +let (s1, e1, m1) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (rs1_val_S); +let (s2, e2, m2) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (rs2_val_S); +let rd_val_S = #\hyperref[sailRISCVzfmakezyS]{fmake\_S}# (0b1 ^ s2, e1, m1); + +#\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_S); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSBzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSBzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..2c16e504 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSBzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rs2_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs2)); +let (s1, e1, m1) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (rs1_val_S); +let (s2, e2, m2) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (rs2_val_S); +let rd_val_S = #\hyperref[sailRISCVzfmakezyS]{fmake\_S}# (s1 ^ s2, e1, m1); + +#\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_S); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..b0a6ca14 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,17 @@ +let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rs2_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs2)); + +let is_quiet = true; +let (rs1_lt_rs2, fflags) = #\hyperref[sailRISCVzflezyS]{fle\_S}# (rs1_val_S, rs2_val_S, is_quiet); + +let rd_val_S = if (#\hyperref[sailRISCVzfzyiszyNaNzyS]{f\_is\_NaN\_S}#(rs1_val_S) & #\hyperref[sailRISCVzfzyiszyNaNzyS]{f\_is\_NaN\_S}#(rs2_val_S)) then #\hyperref[sailRISCVzcanonicalzyNaNzyS]{canonical\_NaN\_S}#() + else if #\hyperref[sailRISCVzfzyiszyNaNzyS]{f\_is\_NaN\_S}#(rs1_val_S) then rs2_val_S + else if #\hyperref[sailRISCVzfzyiszyNaNzyS]{f\_is\_NaN\_S}#(rs2_val_S) then rs1_val_S + else if (#\hyperref[sailRISCVzfzyiszynegzyzzerozyS]{f\_is\_neg\_zero\_S}#(rs1_val_S) & #\hyperref[sailRISCVzfzyiszyposzyzzerozyS]{f\_is\_pos\_zero\_S}#(rs2_val_S)) then rs1_val_S + else if (#\hyperref[sailRISCVzfzyiszynegzyzzerozyS]{f\_is\_neg\_zero\_S}#(rs2_val_S) & #\hyperref[sailRISCVzfzyiszyposzyzzerozyS]{f\_is\_pos\_zero\_S}#(rs1_val_S)) then rs2_val_S + else if rs1_lt_rs2 then rs1_val_S + else /* (not rs1_lt_rs2) */ rs2_val_S; + +#\hyperref[sailRISCVzaccruezyfflags]{accrue\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_S); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..46ea4b66 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,17 @@ +let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rs2_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs2)); + +let is_quiet = true; +let (rs2_lt_rs1, fflags) = #\hyperref[sailRISCVzflezyS]{fle\_S}# (rs2_val_S, rs1_val_S, is_quiet); + +let rd_val_S = if (#\hyperref[sailRISCVzfzyiszyNaNzyS]{f\_is\_NaN\_S}#(rs1_val_S) & #\hyperref[sailRISCVzfzyiszyNaNzyS]{f\_is\_NaN\_S}#(rs2_val_S)) then #\hyperref[sailRISCVzcanonicalzyNaNzyS]{canonical\_NaN\_S}#() + else if #\hyperref[sailRISCVzfzyiszyNaNzyS]{f\_is\_NaN\_S}#(rs1_val_S) then rs2_val_S + else if #\hyperref[sailRISCVzfzyiszyNaNzyS]{f\_is\_NaN\_S}#(rs2_val_S) then rs1_val_S + else if (#\hyperref[sailRISCVzfzyiszynegzyzzerozyS]{f\_is\_neg\_zero\_S}#(rs1_val_S) & #\hyperref[sailRISCVzfzyiszyposzyzzerozyS]{f\_is\_pos\_zero\_S}#(rs2_val_S)) then rs2_val_S + else if (#\hyperref[sailRISCVzfzyiszynegzyzzerozyS]{f\_is\_neg\_zero\_S}#(rs2_val_S) & #\hyperref[sailRISCVzfzyiszyposzyzzerozyS]{f\_is\_pos\_zero\_S}#(rs1_val_S)) then rs1_val_S + else if rs2_lt_rs1 then rs1_val_S + else /* (not rs2_lt_rs1) */ rs2_val_S; + +#\hyperref[sailRISCVzaccruezyfflags]{accrue\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_S); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSEzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSEzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..8b95f836 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSEzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,9 @@ +let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rs2_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs2)); + +let (fflags, rd_val) : (bits_fflags, bits_WU) = + #\hyperref[sailRISCVzriscvzyf32Eq]{riscv\_f32Eq}# (rs1_val_S, rs2_val_S); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(rd_val); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSFzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSFzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..3da89385 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSFzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,9 @@ +let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rs2_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs2)); + +let (fflags, rd_val) : (bits_fflags, bits_WU) = + #\hyperref[sailRISCVzriscvzyf32Lt]{riscv\_f32Lt}# (rs1_val_S, rs2_val_S); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(rd_val); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSGzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSGzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..1ec9a0f0 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSGzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,9 @@ +let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rs2_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs2)); + +let (fflags, rd_val) : (bits_fflags, bits_WU) = + #\hyperref[sailRISCVzriscvzyf32Le]{riscv\_f32Le}# (rs1_val_S, rs2_val_S); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(rd_val); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..b05cc5fe --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreBINUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rs2_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs2)); +let (s1, e1, m1) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (rs1_val_S); +let (s2, e2, m2) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (rs2_val_S); +let rd_val_S = #\hyperref[sailRISCVzfmakezyS]{fmake\_S}# (s2, e1, m1); + +#\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_S); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreMADDUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreMADDUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..f2869cf4 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreMADDUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +let rs1_val_64b = #\hyperref[sailRISCVzF]{F}#(rs1); +let rs2_val_64b = #\hyperref[sailRISCVzF]{F}#(rs2); +let rs3_val_64b = #\hyperref[sailRISCVzF]{F}#(rs3); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); +let (fflags, rd_val_64b) : (#\hyperref[sailRISCVzbits]{bits}#(5), #\hyperref[sailRISCVzbits]{bits}#(64)) = + match op { + FMADD_D => #\hyperref[sailRISCVzriscvzyf64MulAdd]{riscv\_f64MulAdd}# (rm_3b, rs1_val_64b, rs2_val_64b, rs3_val_64b), + FMSUB_D => #\hyperref[sailRISCVzriscvzyf64MulAdd]{riscv\_f64MulAdd}# (rm_3b, rs1_val_64b, rs2_val_64b, #\hyperref[sailRISCVznegatezyD]{negate\_D}# (rs3_val_64b)), + FNMSUB_D => #\hyperref[sailRISCVzriscvzyf64MulAdd]{riscv\_f64MulAdd}# (rm_3b, #\hyperref[sailRISCVznegatezyD]{negate\_D}# (rs1_val_64b), rs2_val_64b, rs3_val_64b), + FNMADD_D => #\hyperref[sailRISCVzriscvzyf64MulAdd]{riscv\_f64MulAdd}# (rm_3b, #\hyperref[sailRISCVznegatezyD]{negate\_D}# (rs1_val_64b), rs2_val_64b, #\hyperref[sailRISCVznegatezyD]{negate\_D}# (rs3_val_64b)) + }; +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_64b; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreMADDUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreMADDUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..be3b7ebf --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreMADDUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +let rs1_val_32b = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rs2_val_32b = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs2)); +let rs3_val_32b = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs3)); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); +let (fflags, rd_val_32b) : (#\hyperref[sailRISCVzbits]{bits}#(5), #\hyperref[sailRISCVzbits]{bits}#(32)) = + match op { + FMADD_S => #\hyperref[sailRISCVzriscvzyf32MulAdd]{riscv\_f32MulAdd}# (rm_3b, rs1_val_32b, rs2_val_32b, rs3_val_32b), + FMSUB_S => #\hyperref[sailRISCVzriscvzyf32MulAdd]{riscv\_f32MulAdd}# (rm_3b, rs1_val_32b, rs2_val_32b, #\hyperref[sailRISCVznegatezyS]{negate\_S}# (rs3_val_32b)), + FNMSUB_S => #\hyperref[sailRISCVzriscvzyf32MulAdd]{riscv\_f32MulAdd}# (rm_3b, #\hyperref[sailRISCVznegatezyS]{negate\_S}# (rs1_val_32b), rs2_val_32b, rs3_val_32b), + FNMADD_S => #\hyperref[sailRISCVzriscvzyf32MulAdd]{riscv\_f32MulAdd}# (rm_3b, #\hyperref[sailRISCVznegatezyS]{negate\_S}# (rs1_val_32b), rs2_val_32b, #\hyperref[sailRISCVznegatezyS]{negate\_S}# (rs3_val_32b)) + }; +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_32b); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDAzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDAzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..3ecc1967 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDAzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_W) = #\hyperref[sailRISCVzriscvzyf64ToI32]{riscv\_f64ToI32}# (rm_3b, rs1_val_D); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTS]{EXTS}# (rd_val_W); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDBzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDBzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..3545afaf --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDBzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_WU) = #\hyperref[sailRISCVzriscvzyf64ToUi32]{riscv\_f64ToUi32}# (rm_3b, rs1_val_D); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTS]{EXTS}# (rd_val_WU); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..bb00cb27 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_W = #\hyperref[sailRISCVzX]{X}#(rs1) [31..0]; +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_D) = #\hyperref[sailRISCVzriscvzyi32ToF64]{riscv\_i32ToF64}# (rm_3b, rs1_val_W); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_D; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..a3ebd2cd --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_WU = #\hyperref[sailRISCVzX]{X}#(rs1) [31..0]; +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_D) = #\hyperref[sailRISCVzriscvzyui32ToF64]{riscv\_ui32ToF64}# (rm_3b, rs1_val_WU); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_D; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDEzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDEzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..cabe56ba --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDEzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_S) = #\hyperref[sailRISCVzriscvzyf64ToF32]{riscv\_f64ToF32}# (rm_3b, rs1_val_D); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_S); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDFzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDFzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..ce303ff2 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDFzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_D) = #\hyperref[sailRISCVzriscvzyf32ToF64]{riscv\_f32ToF64}# (rm_3b, rs1_val_S); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_D; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDGzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDGzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..c6506fe1 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDGzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_L) = #\hyperref[sailRISCVzriscvzyf64ToI64]{riscv\_f64ToI64}# (rm_3b, rs1_val_D); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzX]{X}#(rd) = rd_val_L; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDHzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDHzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..afb76fe5 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDHzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_LU) = #\hyperref[sailRISCVzriscvzyf64ToUi64]{riscv\_f64ToUi64}# (rm_3b, rs1_val_D); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzX]{X}#(rd) = rd_val_LU; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDIzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDIzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..601d24e6 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDIzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_L = #\hyperref[sailRISCVzX]{X}#(rs1); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_D) = #\hyperref[sailRISCVzriscvzyi64ToF64]{riscv\_i64ToF64}# (rm_3b, rs1_val_L); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_D; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDJzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDJzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..1bb34801 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDJzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_LU = #\hyperref[sailRISCVzX]{X}#(rs1); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_D) = #\hyperref[sailRISCVzriscvzyui64ToF64]{riscv\_ui64ToF64}# (rm_3b, rs1_val_LU); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_D; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..eb501e5a --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_D) = #\hyperref[sailRISCVzriscvzyf64Sqrt]{riscv\_f64Sqrt}# (rm_3b, rs1_val_D); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_D; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSAzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSAzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..acdab79f --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSAzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_W) = #\hyperref[sailRISCVzriscvzyf32ToI32]{riscv\_f32ToI32}# (rm_3b, rs1_val_S); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTS]{EXTS}# (rd_val_W); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSBzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSBzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..6eb34161 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSBzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_WU) = #\hyperref[sailRISCVzriscvzyf32ToUi32]{riscv\_f32ToUi32}# (rm_3b, rs1_val_S); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTS]{EXTS}# (rd_val_WU); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d286c956 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_W = #\hyperref[sailRISCVzX]{X}#(rs1) [31..0]; +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_S) = #\hyperref[sailRISCVzriscvzyi32ToF32]{riscv\_i32ToF32}# (rm_3b, rs1_val_W); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_S); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d32d5794 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_WU = #\hyperref[sailRISCVzX]{X}#(rs1) [31..0]; +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_S) = #\hyperref[sailRISCVzriscvzyui32ToF32]{riscv\_ui32ToF32}# (rm_3b, rs1_val_WU); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_S); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSEzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSEzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..3789af46 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSEzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +if sizeof(flen) == 64 +then { + let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); + let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + + let (fflags, rd_val_L) = #\hyperref[sailRISCVzriscvzyf32ToI64]{riscv\_f32ToI64}# (rm_3b, rs1_val_S); + + #\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); + #\hyperref[sailRISCVzX]{X}#(rd) = rd_val_L; + RETIRE_SUCCESS +} else { + /* this would not decode on RV32 */ + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSFzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSFzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..7b7bf6be --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSFzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +if sizeof(flen) == 64 +then { + let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); + let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + + let (fflags, rd_val_LU) = #\hyperref[sailRISCVzriscvzyf32ToUi64]{riscv\_f32ToUi64}# (rm_3b, rs1_val_S); + + #\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); + #\hyperref[sailRISCVzX]{X}#(rd) = rd_val_LU; + RETIRE_SUCCESS +} else { + /* this would not decode on RV32 */ + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSGzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSGzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..5c274b62 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSGzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +if sizeof(flen) == 64 +then { + let rs1_val_L = #\hyperref[sailRISCVzX]{X}#(rs1); + let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + + let (fflags, rd_val_S) = #\hyperref[sailRISCVzriscvzyi64ToF32]{riscv\_i64ToF32}# (rm_3b, rs1_val_L); + + #\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); + #\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_S); + RETIRE_SUCCESS +} else { + /* this would not decode on RV32 */ + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSHzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSHzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..4ec98a91 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSHzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +if sizeof(flen) == 64 +then { + let rs1_val_LU = #\hyperref[sailRISCVzX]{X}#(rs1); + let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + + let (fflags, rd_val_S) = #\hyperref[sailRISCVzriscvzyui64ToF32]{riscv\_ui64ToF32}# (rm_3b, rs1_val_LU); + + #\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); + #\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_S); + RETIRE_SUCCESS +} else { + /* this would not decode on RV32 */ + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..a53aa92f --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreRMUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); +let rm_3b = #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (#\hyperref[sailRISCVzselectzyinstrzyorzyfcsrzyrm]{select\_instr\_or\_fcsr\_rm}# (rm)); + +let (fflags, rd_val_S) = #\hyperref[sailRISCVzriscvzyf32Sqrt]{riscv\_f32Sqrt}# (rm_3b, rs1_val_S); + +#\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags); +#\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_S); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreDAzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreDAzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..dd8df4a7 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreDAzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); +let rd_val_X = rs1_val_D; +#\hyperref[sailRISCVzX]{X}#(rd) = rd_val_X; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreDBzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreDBzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d577d043 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreDBzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +let rs1_val_X = #\hyperref[sailRISCVzX]{X}#(rs1); +let rd_val_D = rs1_val_X; +#\hyperref[sailRISCVzF]{F}#(rd) = rd_val_D; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..6e5a3ef3 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreDzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,17 @@ +let rs1_val_D = #\hyperref[sailRISCVzF]{F}#(rs1); + +let rd_val_10b : #\hyperref[sailRISCVzbits]{bits}# (10) = + if #\hyperref[sailRISCVzfzyiszynegzyinfzyD]{f\_is\_neg\_inf\_D}# (rs1_val_D) then 0b_00_0000_0001 + else if #\hyperref[sailRISCVzfzyiszynegzynormzyD]{f\_is\_neg\_norm\_D}# (rs1_val_D) then 0b_00_0000_0010 + else if #\hyperref[sailRISCVzfzyiszynegzysubnormzyD]{f\_is\_neg\_subnorm\_D}# (rs1_val_D) then 0b_00_0000_0100 + else if #\hyperref[sailRISCVzfzyiszynegzyzzerozyD]{f\_is\_neg\_zero\_D}# (rs1_val_D) then 0b_00_0000_1000 + else if #\hyperref[sailRISCVzfzyiszyposzyzzerozyD]{f\_is\_pos\_zero\_D}# (rs1_val_D) then 0b_00_0001_0000 + else if #\hyperref[sailRISCVzfzyiszyposzysubnormzyD]{f\_is\_pos\_subnorm\_D}# (rs1_val_D) then 0b_00_0010_0000 + else if #\hyperref[sailRISCVzfzyiszyposzynormzyD]{f\_is\_pos\_norm\_D}# (rs1_val_D) then 0b_00_0100_0000 + else if #\hyperref[sailRISCVzfzyiszyposzyinfzyD]{f\_is\_pos\_inf\_D}# (rs1_val_D) then 0b_00_1000_0000 + else if #\hyperref[sailRISCVzfzyiszySNaNzyD]{f\_is\_SNaN\_D}# (rs1_val_D) then 0b_01_0000_0000 + else if #\hyperref[sailRISCVzfzyiszyQNaNzyD]{f\_is\_QNaN\_D}# (rs1_val_D) then 0b_10_0000_0000 + else #\hyperref[sailRISCVzzzeros]{zeros}#(); + +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}# (rd_val_10b); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreSAzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreSAzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..785df4a4 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreSAzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +let rs1_val_S = #\hyperref[sailRISCVzF]{F}#(rs1)[31..0]; +let rd_val_X : xlenbits = #\hyperref[sailRISCVzEXTS]{EXTS}#(rs1_val_S); +#\hyperref[sailRISCVzX]{X}#(rd) = rd_val_X; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreSBzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreSBzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..c9b41cb9 --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreSBzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,4 @@ +let rs1_val_X = #\hyperref[sailRISCVzX]{X}#(rs1); +let rd_val_S = rs1_val_X [31..0]; +#\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}# (rd_val_S); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..fd28c25f --- /dev/null +++ b/sail_latex_riscv/fclFUnderscoreUNUnderscoreTYPEUnderscoreSzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,17 @@ +let rs1_val_S = #\hyperref[sailRISCVznanzyunbox]{nan\_unbox}# (#\hyperref[sailRISCVzF]{F}#(rs1)); + +let rd_val_10b : #\hyperref[sailRISCVzbits]{bits}# (10) = + if #\hyperref[sailRISCVzfzyiszynegzyinfzyS]{f\_is\_neg\_inf\_S}# (rs1_val_S) then 0b_00_0000_0001 + else if #\hyperref[sailRISCVzfzyiszynegzynormzyS]{f\_is\_neg\_norm\_S}# (rs1_val_S) then 0b_00_0000_0010 + else if #\hyperref[sailRISCVzfzyiszynegzysubnormzyS]{f\_is\_neg\_subnorm\_S}# (rs1_val_S) then 0b_00_0000_0100 + else if #\hyperref[sailRISCVzfzyiszynegzyzzerozyS]{f\_is\_neg\_zero\_S}# (rs1_val_S) then 0b_00_0000_1000 + else if #\hyperref[sailRISCVzfzyiszyposzyzzerozyS]{f\_is\_pos\_zero\_S}# (rs1_val_S) then 0b_00_0001_0000 + else if #\hyperref[sailRISCVzfzyiszyposzysubnormzyS]{f\_is\_pos\_subnorm\_S}# (rs1_val_S) then 0b_00_0010_0000 + else if #\hyperref[sailRISCVzfzyiszyposzynormzyS]{f\_is\_pos\_norm\_S}# (rs1_val_S) then 0b_00_0100_0000 + else if #\hyperref[sailRISCVzfzyiszyposzyinfzyS]{f\_is\_pos\_inf\_S}# (rs1_val_S) then 0b_00_1000_0000 + else if #\hyperref[sailRISCVzfzyiszySNaNzyS]{f\_is\_SNaN\_S}# (rs1_val_S) then 0b_01_0000_0000 + else if #\hyperref[sailRISCVzfzyiszyQNaNzyS]{f\_is\_QNaN\_S}# (rs1_val_S) then 0b_10_0000_0000 + else #\hyperref[sailRISCVzzzeros]{zeros}#(); + +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}# (rd_val_10b); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclFzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclFzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..6ea2e81d --- /dev/null +++ b/sail_latex_riscv/fclFzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}#(0x040, value) = { uscratch = value; #\hyperref[sailRISCVzSome]{Some}#(uscratch) } diff --git a/sail_latex_riscv/fclGetCcsrBitsmccsrzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclGetCcsrBitsmccsrzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..9d83386c --- /dev/null +++ b/sail_latex_riscv/fclGetCcsrBitsmccsrzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}# (0xBC0) = #\hyperref[sailRISCVzSome]{Some}#(mccsr.#\hyperref[sailRISCVzbits]{bits}#()) diff --git a/sail_latex_riscv/fclGetCcsrBitssccsrzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclGetCcsrBitssccsrzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..f4d02669 --- /dev/null +++ b/sail_latex_riscv/fclGetCcsrBitssccsrzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}# (0x9C0) = #\hyperref[sailRISCVzSome]{Some}#(sccsr.#\hyperref[sailRISCVzbits]{bits}#()) diff --git a/sail_latex_riscv/fclGetCcsrBitsuccsrzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclGetCcsrBitsuccsrzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..b5fc016c --- /dev/null +++ b/sail_latex_riscv/fclGetCcsrBitsuccsrzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}# (0x8C0) = #\hyperref[sailRISCVzSome]{Some}#(uccsr.#\hyperref[sailRISCVzbits]{bits}#()) diff --git a/sail_latex_riscv/fclGetMcauseBitsucausezext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclGetMcauseBitsucausezext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..dfced63f --- /dev/null +++ b/sail_latex_riscv/fclGetMcauseBitsucausezext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}#(0x042) = #\hyperref[sailRISCVzSome]{Some}#(ucause.#\hyperref[sailRISCVzbits]{bits}#()) diff --git a/sail_latex_riscv/fclGetUinterruptsBitslowerSiezext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclGetUinterruptsBitslowerSiezext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..77fde6d4 --- /dev/null +++ b/sail_latex_riscv/fclGetUinterruptsBitslowerSiezext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}#(0x004) = #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzlowerzysie]{lower\_sie}#(#\hyperref[sailRISCVzlowerzymie]{lower\_mie}#(mie, mideleg), sideleg).#\hyperref[sailRISCVzbits]{bits}#()) diff --git a/sail_latex_riscv/fclGetUinterruptsBitslowerSipzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclGetUinterruptsBitslowerSipzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..9d3a6951 --- /dev/null +++ b/sail_latex_riscv/fclGetUinterruptsBitslowerSipzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}#(0x044) = #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzlowerzysip]{lower\_sip}#(#\hyperref[sailRISCVzlowerzymip]{lower\_mip}#(mip, mideleg), sideleg).#\hyperref[sailRISCVzbits]{bits}#()) diff --git a/sail_latex_riscv/fclGetUstatusBitslowerSstatuslowerMstatusmstatuszext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclGetUstatusBitslowerSstatuslowerMstatusmstatuszext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..f28468c1 --- /dev/null +++ b/sail_latex_riscv/fclGetUstatusBitslowerSstatuslowerMstatusmstatuszext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}#(0x000) = #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzlowerzysstatus]{lower\_sstatus}#(#\hyperref[sailRISCVzlowerzymstatus]{lower\_mstatus}#(mstatus)).#\hyperref[sailRISCVzbits]{bits}#()) diff --git a/sail_latex_riscv/fclGzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclGzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..29a03da9 --- /dev/null +++ b/sail_latex_riscv/fclGzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}#(0x041, value) = { #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzsetzyxretzytarget]{set\_xret\_target}#(User, value)) } diff --git a/sail_latex_riscv/fclHzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclHzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..c89da4b5 --- /dev/null +++ b/sail_latex_riscv/fclHzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}#(0x042, value) = { ucause->#\hyperref[sailRISCVzbits]{bits}#() = value; #\hyperref[sailRISCVzSome]{Some}#(ucause.#\hyperref[sailRISCVzbits]{bits}#()) } diff --git a/sail_latex_riscv/fclILLEGALzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclILLEGALzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e69de29b diff --git a/sail_latex_riscv/fclITYPEzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclITYPEzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..aa74fd06 --- /dev/null +++ b/sail_latex_riscv/fclITYPEzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,12 @@ +let rs1_val = #\hyperref[sailRISCVzX]{X}#(rs1); +let immext : xlenbits = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm); +let result : xlenbits = match op { + RISCV_ADDI => rs1_val + immext, + RISCV_SLTI => #\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(rs1_val <_s immext)), + RISCV_SLTIU => #\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(rs1_val <_u immext)), + RISCV_ANDI => rs1_val & immext, + RISCV_ORI => rs1_val | immext, + RISCV_XORI => rs1_val ^ immext +}; +#\hyperref[sailRISCVzX]{X}#(rd) = result; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclIzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclIzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..c65b9e45 --- /dev/null +++ b/sail_latex_riscv/fclIzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}#(0x043, value) = { utval = value; #\hyperref[sailRISCVzSome]{Some}#(utval) } diff --git a/sail_latex_riscv/fclJzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclJzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..ccb82cde --- /dev/null +++ b/sail_latex_riscv/fclJzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1,3 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}#(0x044, value) = { let sip = #\hyperref[sailRISCVzlegalizzezyuip]{legalize\_uip}#(#\hyperref[sailRISCVzlowerzymip]{lower\_mip}#(mip, mideleg), sideleg, value); + mip = #\hyperref[sailRISCVzliftzysip]{lift\_sip}#(mip, mideleg, sip); + #\hyperref[sailRISCVzSome]{Some}#(mip.#\hyperref[sailRISCVzbits]{bits}#()) } diff --git a/sail_latex_riscv/fclKzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclKzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..5b676891 --- /dev/null +++ b/sail_latex_riscv/fclKzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}# (0x001, value) = { #\hyperref[sailRISCVzextzywritezyfcsr]{ext\_write\_fcsr}# (fcsr.#\hyperref[sailRISCVzFRM]{FRM}#(), value [4..0]); #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(fcsr.#\hyperref[sailRISCVzFFLAGS]{FFLAGS}#())) } diff --git a/sail_latex_riscv/fclLOADRESzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLOADRESzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..6587d109 --- /dev/null +++ b/sail_latex_riscv/fclLOADRESzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,37 @@ +if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { + /* Get the address, #\hyperref[sailRISCVzX]{X}#(rs1) (no offset). + * Extensions might perform additional checks on address validity. + */ + match #\hyperref[sailRISCVzextzydatazygetzyaddr]{ext\_data\_get\_addr}#(rs1, #\hyperref[sailRISCVzzzeros]{zeros}#(), #\hyperref[sailRISCVzRead]{Read}#(Data), width) { + #\hyperref[sailRISCVzExtzyDataAddrzyError]{Ext\_DataAddr\_Error}#(e) => { #\hyperref[sailRISCVzextzyhandlezydatazycheckzyerror]{ext\_handle\_data\_check\_error}#(e); RETIRE_FAIL }, + #\hyperref[sailRISCVzExtzyDataAddrzyOK]{Ext\_DataAddr\_OK}#(vaddr) => { + let aligned : bool = + /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt + * to treat them as valid here; otherwise we'd need to throw an internal_error. + */ + match width { + BYTE => true, + HALF => vaddr[0..0] == 0b0, + WORD => vaddr[1..0] == 0b00, + DOUBLE => vaddr[2..0] == 0b000 + }; + /* "LR faults like a normal load, even though it's in the AMO major opcode space." + * - Andrew Waterman, isa-dev, 10 Jul 2018. + */ + if (~ (aligned)) + then { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, #\hyperref[sailRISCVzEzyLoadzyAddrzyAlign]{E\_Load\_Addr\_Align}#()); RETIRE_FAIL } + else match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddr, #\hyperref[sailRISCVzRead]{Read}#(Data)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, _) => + match (width, sizeof(xlen)) { + (WORD, _) => #\hyperref[sailRISCVzprocesszyloadres]{process\_loadres}#(rd, vaddr, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), addr, 4, aq, rl, true), false), + (DOUBLE, 64) => #\hyperref[sailRISCVzprocesszyloadres]{process\_loadres}#(rd, vaddr, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), addr, 8, aq, rl, true), false), + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("LOADRES expected WORD or DOUBLE") + } + } + } + } +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclLOADUnderscoreFPzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLOADUnderscoreFPzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..ec36d95d --- /dev/null +++ b/sail_latex_riscv/fclLOADUnderscoreFPzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,23 @@ +let offset : xlenbits = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm); +/* Get the address, #\hyperref[sailRISCVzX]{X}#(rs1) + offset. + Some extensions perform additional checks on address validity. */ +match #\hyperref[sailRISCVzextzydatazygetzyaddr]{ext\_data\_get\_addr}#(rs1, offset, #\hyperref[sailRISCVzRead]{Read}#(Data), width) { + #\hyperref[sailRISCVzExtzyDataAddrzyError]{Ext\_DataAddr\_Error}#(e) => { #\hyperref[sailRISCVzextzyhandlezydatazycheckzyerror]{ext\_handle\_data\_check\_error}#(e); RETIRE_FAIL }, + #\hyperref[sailRISCVzExtzyDataAddrzyOK]{Ext\_DataAddr\_OK}#(vaddr) => + if #\hyperref[sailRISCVzcheckzymisaligned]{check\_misaligned}#(vaddr, width) + then { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, #\hyperref[sailRISCVzEzyLoadzyAddrzyAlign]{E\_Load\_Addr\_Align}#()); RETIRE_FAIL } + else match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddr, #\hyperref[sailRISCVzRead]{Read}#(Data)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, _) => { + let (aq, rl, res) = (false, false, false); + match (width, sizeof(xlen)) { + (BYTE, _) => { #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); RETIRE_FAIL }, + (HALF, _) => { #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); RETIRE_FAIL }, + (WORD, _) => + #\hyperref[sailRISCVzprocesszyfload32]{process\_fload32}#(rd, vaddr, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), addr, 4, aq, rl, res)), + (DOUBLE, 64) => + #\hyperref[sailRISCVzprocesszyfload64]{process\_fload64}#(rd, vaddr, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), addr, 8, aq, rl, res)) + } + } + } +} diff --git a/sail_latex_riscv/fclLOADzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLOADzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..f051f153 --- /dev/null +++ b/sail_latex_riscv/fclLOADzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,23 @@ +let offset : xlenbits = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm); +/* Get the address, #\hyperref[sailRISCVzX]{X}#(rs1) + offset. + Some extensions perform additional checks on address validity. */ +match #\hyperref[sailRISCVzextzydatazygetzyaddr]{ext\_data\_get\_addr}#(rs1, offset, #\hyperref[sailRISCVzRead]{Read}#(Data), width) { + #\hyperref[sailRISCVzExtzyDataAddrzyError]{Ext\_DataAddr\_Error}#(e) => { #\hyperref[sailRISCVzextzyhandlezydatazycheckzyerror]{ext\_handle\_data\_check\_error}#(e); RETIRE_FAIL }, + #\hyperref[sailRISCVzExtzyDataAddrzyOK]{Ext\_DataAddr\_OK}#(vaddr) => + if #\hyperref[sailRISCVzcheckzymisaligned]{check\_misaligned}#(vaddr, width) + then { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, #\hyperref[sailRISCVzEzyLoadzyAddrzyAlign]{E\_Load\_Addr\_Align}#()); RETIRE_FAIL } + else match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddr, #\hyperref[sailRISCVzRead]{Read}#(Data)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(paddr, _) => + match (width, sizeof(xlen)) { + (BYTE, _) => + #\hyperref[sailRISCVzprocesszyload]{process\_load}#(rd, vaddr, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), paddr, 1, aq, rl, false), is_unsigned), + (HALF, _) => + #\hyperref[sailRISCVzprocesszyload]{process\_load}#(rd, vaddr, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), paddr, 2, aq, rl, false), is_unsigned), + (WORD, _) => + #\hyperref[sailRISCVzprocesszyload]{process\_load}#(rd, vaddr, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), paddr, 4, aq, rl, false), is_unsigned), + (DOUBLE, 64) => + #\hyperref[sailRISCVzprocesszyload]{process\_load}#(rd, vaddr, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), paddr, 8, aq, rl, false), is_unsigned) + } + } +} diff --git a/sail_latex_riscv/fclLoadCapCapzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLoadCapCapzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..68f81154 --- /dev/null +++ b/sail_latex_riscv/fclLoadCapCapzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let vaddr = cs1_val.address; +#\hyperref[sailRISCVzhandlezyloadzycapzyviazycap]{handle\_load\_cap\_via\_cap}#(cd, 0b0 @ cs1, cs1_val, vaddr) diff --git a/sail_latex_riscv/fclLoadCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLoadCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..2b986eae --- /dev/null +++ b/sail_latex_riscv/fclLoadCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let ddc_val = DDC; +let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); +#\hyperref[sailRISCVzhandlezyloadzycapzyviazycap]{handle\_load\_cap\_via\_cap}#(cd, DDC_IDX, ddc_val, vaddr) diff --git a/sail_latex_riscv/fclLoadCapImmzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLoadCapImmzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..b74a0909 --- /dev/null +++ b/sail_latex_riscv/fclLoadCapImmzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let offset : xlenbits = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm); +let (auth_val, vaddr, auth_idx) = #\hyperref[sailRISCVzgetzycherizymodezycapzyaddr]{get\_cheri\_mode\_cap\_addr}#(rs1_cs1, offset); +#\hyperref[sailRISCVzhandlezyloadzycapzyviazycap]{handle\_load\_cap\_via\_cap}#(cd, auth_idx, auth_val, vaddr) diff --git a/sail_latex_riscv/fclLoadDataCapzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLoadDataCapzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..17bb551d --- /dev/null +++ b/sail_latex_riscv/fclLoadDataCapzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let vaddr = cs1_val.address; +#\hyperref[sailRISCVzhandlezyloadzydatazyviazycap]{handle\_load\_data\_via\_cap}#(rd, 0b0 @ cs1, cs1_val, vaddr, is_unsigned, width) diff --git a/sail_latex_riscv/fclLoadDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLoadDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..b9832bd7 --- /dev/null +++ b/sail_latex_riscv/fclLoadDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let ddc_val = DDC; +let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); +#\hyperref[sailRISCVzhandlezyloadzydatazyviazycap]{handle\_load\_data\_via\_cap}#(rd, DDC_IDX, ddc_val, vaddr, is_unsigned, width) diff --git a/sail_latex_riscv/fclLoadResCapCapzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLoadResCapCapzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..981a69b6 --- /dev/null +++ b/sail_latex_riscv/fclLoadResCapCapzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { + let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); + let vaddr = cs1_val.address + #\hyperref[sailRISCVzX]{X}#(cs1); + #\hyperref[sailRISCVzhandlezyloadreszycapzyviazycap]{handle\_loadres\_cap\_via\_cap}#(cd, 0b0 @ cs1, cs1_val, vaddr) +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclLoadResCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLoadResCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..9baceedd --- /dev/null +++ b/sail_latex_riscv/fclLoadResCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { + let ddc_val = DDC; + let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); + #\hyperref[sailRISCVzhandlezyloadreszycapzyviazycap]{handle\_loadres\_cap\_via\_cap}#(cd, DDC_IDX, ddc_val, vaddr) +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclLoadResCapzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLoadResCapzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..27ef4818 --- /dev/null +++ b/sail_latex_riscv/fclLoadResCapzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { + let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); + let vaddr = cs1_val.address; + #\hyperref[sailRISCVzhandlezyloadreszydatazyviazycap]{handle\_loadres\_data\_via\_cap}#(rd, 0b0 @ cs1, cs1_val, vaddr, width) +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclLoadResDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclLoadResDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..1c7a5edb --- /dev/null +++ b/sail_latex_riscv/fclLoadResDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { + let ddc_val = DDC; + let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); + #\hyperref[sailRISCVzhandlezyloadreszydatazyviazycap]{handle\_loadres\_data\_via\_cap}#(rd, DDC_IDX, ddc_val, vaddr, width) +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclLzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclLzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..594467a8 --- /dev/null +++ b/sail_latex_riscv/fclLzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}# (0x002, value) = { #\hyperref[sailRISCVzextzywritezyfcsr]{ext\_write\_fcsr}# (value [2..0], fcsr.#\hyperref[sailRISCVzFFLAGS]{FFLAGS}#()); #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(fcsr.#\hyperref[sailRISCVzFRM]{FRM}#())) } diff --git a/sail_latex_riscv/fclMRETzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclMRETzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..112cf56a --- /dev/null +++ b/sail_latex_riscv/fclMRETzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,6 @@ +if cur_privilege != Machine +then #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#() +else if ~(#\hyperref[sailRISCVzextzycheckzyxretzypriv]{ext\_check\_xret\_priv}# (Machine)) +then #\hyperref[sailRISCVzextzyfailzyxretzypriv]{ext\_fail\_xret\_priv}# () +else #\hyperref[sailRISCVzsetzynextzypc]{set\_next\_pc}#(#\hyperref[sailRISCVzexceptionzyhandler]{exception\_handler}#(cur_privilege, #\hyperref[sailRISCVzCTLzyMRET]{CTL\_MRET}#(), PC)); +RETIRE_FAIL diff --git a/sail_latex_riscv/fclMULWzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclMULWzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..689eb158 --- /dev/null +++ b/sail_latex_riscv/fclMULWzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +if #\hyperref[sailRISCVzhaveMulDiv]{haveMulDiv}#() then { + let rs1_val = #\hyperref[sailRISCVzX]{X}#(rs1)[31..0]; + let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2)[31..0]; + let rs1_int : int = #\hyperref[sailRISCVzsigned]{signed}#(rs1_val); + let rs2_int : int = #\hyperref[sailRISCVzsigned]{signed}#(rs2_val); + /* to_bits requires expansion to 64 bits followed by truncation */ + let result32 = #\hyperref[sailRISCVztozybits]{to\_bits}#(64, rs1_int * rs2_int)[31..0]; + let result : xlenbits = #\hyperref[sailRISCVzEXTS]{EXTS}#(result32); + #\hyperref[sailRISCVzX]{X}#(rd) = result; + RETIRE_SUCCESS +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclMULzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclMULzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..a8be8d97 --- /dev/null +++ b/sail_latex_riscv/fclMULzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,15 @@ +if #\hyperref[sailRISCVzhaveMulDiv]{haveMulDiv}#() then { + let rs1_val = #\hyperref[sailRISCVzX]{X}#(rs1); + let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); + let rs1_int : int = if signed1 then #\hyperref[sailRISCVzsigned]{signed}#(rs1_val) else #\hyperref[sailRISCVzunsigned]{unsigned}#(rs1_val); + let rs2_int : int = if signed2 then #\hyperref[sailRISCVzsigned]{signed}#(rs2_val) else #\hyperref[sailRISCVzunsigned]{unsigned}#(rs2_val); + let result_wide = #\hyperref[sailRISCVztozybits]{to\_bits}#(2 * sizeof(xlen), rs1_int * rs2_int); + let result = if high + then result_wide[(2 * sizeof(xlen) - 1) .. sizeof(xlen)] + else result_wide[(sizeof(xlen) - 1) .. 0]; + #\hyperref[sailRISCVzX]{X}#(rd) = result; + RETIRE_SUCCESS +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclMzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclMzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..971c23cc --- /dev/null +++ b/sail_latex_riscv/fclMzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}# (0x003, value) = { #\hyperref[sailRISCVzextzywritezyfcsr]{ext\_write\_fcsr}# (value [7..5], value [4..0]); #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(fcsr.#\hyperref[sailRISCVzbits]{bits}#())) } diff --git a/sail_latex_riscv/fclNonezext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclNonezext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..158fb268 --- /dev/null +++ b/sail_latex_riscv/fclNonezext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause ext_read_CSR _ = #\hyperref[sailRISCVzNone]{None}#() diff --git a/sail_latex_riscv/fclNonezext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclNonezext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..c0739369 --- /dev/null +++ b/sail_latex_riscv/fclNonezext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}# (_, _) = #\hyperref[sailRISCVzNone]{None}#() diff --git a/sail_latex_riscv/fclREMWzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclREMWzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..23313093 --- /dev/null +++ b/sail_latex_riscv/fclREMWzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,13 @@ +if #\hyperref[sailRISCVzhaveMulDiv]{haveMulDiv}#() then { + let rs1_val = #\hyperref[sailRISCVzX]{X}#(rs1)[31..0]; + let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2)[31..0]; + let rs1_int : int = if s then #\hyperref[sailRISCVzsigned]{signed}#(rs1_val) else #\hyperref[sailRISCVzunsigned]{unsigned}#(rs1_val); + let rs2_int : int = if s then #\hyperref[sailRISCVzsigned]{signed}#(rs2_val) else #\hyperref[sailRISCVzunsigned]{unsigned}#(rs2_val); + let r : int = if rs2_int == 0 then rs1_int else #\hyperref[sailRISCVzremzyroundzyzzero]{rem\_round\_zero}#(rs1_int, rs2_int); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + #\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTS]{EXTS}#(#\hyperref[sailRISCVztozybits]{to\_bits}#(32, r)); + RETIRE_SUCCESS +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclREMzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclREMzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..b1aaef72 --- /dev/null +++ b/sail_latex_riscv/fclREMzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,13 @@ +if #\hyperref[sailRISCVzhaveMulDiv]{haveMulDiv}#() then { + let rs1_val = #\hyperref[sailRISCVzX]{X}#(rs1); + let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); + let rs1_int : int = if s then #\hyperref[sailRISCVzsigned]{signed}#(rs1_val) else #\hyperref[sailRISCVzunsigned]{unsigned}#(rs1_val); + let rs2_int : int = if s then #\hyperref[sailRISCVzsigned]{signed}#(rs2_val) else #\hyperref[sailRISCVzunsigned]{unsigned}#(rs2_val); + let r : int = if rs2_int == 0 then rs1_int else #\hyperref[sailRISCVzremzyroundzyzzero]{rem\_round\_zero}#(rs1_int, rs2_int); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + #\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVztozybits]{to\_bits}#(sizeof(xlen), r); + RETIRE_SUCCESS +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclRISCVUnderscoreJALRzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclRISCVUnderscoreJALRzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..fb944164 --- /dev/null +++ b/sail_latex_riscv/fclRISCVUnderscoreJALRzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,25 @@ +/* For the sequential model, the memory-model definition doesn't work directly + * if rs1 = rd. We would effectively have to keep a regfile for reads and another for + * writes, and swap on instruction completion. This could perhaps be optimized in + * some manner, but for now, we just keep a reordered definition to improve simulator + * performance. + */ +let t : xlenbits = #\hyperref[sailRISCVzX]{X}#(rs1) + #\hyperref[sailRISCVzEXTS]{EXTS}#(imm); +/* Extensions get the first checks on the prospective target address. */ +match #\hyperref[sailRISCVzextzycontrolzycheckzyaddr]{ext\_control\_check\_addr}#(t) { + #\hyperref[sailRISCVzExtzyControlAddrzyError]{Ext\_ControlAddr\_Error}#(e) => { + #\hyperref[sailRISCVzextzyhandlezycontrolzycheckzyerror]{ext\_handle\_control\_check\_error}#(e); + RETIRE_FAIL + }, + #\hyperref[sailRISCVzExtzyControlAddrzyOK]{Ext\_ControlAddr\_OK}#(addr) => { + let target = [addr with 0 = bitzero]; /* clear addr[0] */ + if #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(target[1]) & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#()) then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(target, #\hyperref[sailRISCVzEzyFetchzyAddrzyAlign]{E\_Fetch\_Addr\_Align}#()); + RETIRE_FAIL + } else { + #\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzgetzynextzypc]{get\_next\_pc}#(); + #\hyperref[sailRISCVzsetzynextzypc]{set\_next\_pc}#(target); + RETIRE_SUCCESS + } + } +} diff --git a/sail_latex_riscv/fclRISCVUnderscoreJALzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclRISCVUnderscoreJALzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..e6f480e8 --- /dev/null +++ b/sail_latex_riscv/fclRISCVUnderscoreJALzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,20 @@ +let t : xlenbits = PC + #\hyperref[sailRISCVzEXTS]{EXTS}#(imm); +/* Extensions get the first checks on the prospective target address. */ +match #\hyperref[sailRISCVzextzycontrolzycheckzypc]{ext\_control\_check\_pc}#(t) { + #\hyperref[sailRISCVzExtzyControlAddrzyError]{Ext\_ControlAddr\_Error}#(e) => { + #\hyperref[sailRISCVzextzyhandlezycontrolzycheckzyerror]{ext\_handle\_control\_check\_error}#(e); + RETIRE_FAIL + }, + #\hyperref[sailRISCVzExtzyControlAddrzyOK]{Ext\_ControlAddr\_OK}#(target) => { + /* Perform standard alignment check */ + if #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(target[1]) & (~ (#\hyperref[sailRISCVzhaveRVC]{haveRVC}#())) + then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(target, #\hyperref[sailRISCVzEzyFetchzyAddrzyAlign]{E\_Fetch\_Addr\_Align}#()); + RETIRE_FAIL + } else { + #\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzgetzynextzypc]{get\_next\_pc}#(); + #\hyperref[sailRISCVzsetzynextzypc]{set\_next\_pc}#(target); + RETIRE_SUCCESS + } + } +} diff --git a/sail_latex_riscv/fclRTYPEWzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclRTYPEWzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..afdc7d61 --- /dev/null +++ b/sail_latex_riscv/fclRTYPEWzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,11 @@ +let rs1_val = (#\hyperref[sailRISCVzX]{X}#(rs1))[31..0]; +let rs2_val = (#\hyperref[sailRISCVzX]{X}#(rs2))[31..0]; +let result : #\hyperref[sailRISCVzbits]{bits}#(32) = match op { + RISCV_ADDW => rs1_val + rs2_val, + RISCV_SUBW => rs1_val - rs2_val, + RISCV_SLLW => rs1_val << (rs2_val[4..0]), + RISCV_SRLW => rs1_val >> (rs2_val[4..0]), + RISCV_SRAW => #\hyperref[sailRISCVzshiftzyrightzyarith32]{shift\_right\_arith32}#(rs1_val, rs2_val[4..0]) +}; +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTS]{EXTS}#(result); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclRTYPEzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclRTYPEzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..932331eb --- /dev/null +++ b/sail_latex_riscv/fclRTYPEzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,22 @@ +let rs1_val = #\hyperref[sailRISCVzX]{X}#(rs1); +let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); +let result : xlenbits = match op { + RISCV_ADD => rs1_val + rs2_val, + RISCV_SLT => #\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(rs1_val <_s rs2_val)), + RISCV_SLTU => #\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(rs1_val <_u rs2_val)), + RISCV_AND => rs1_val & rs2_val, + RISCV_OR => rs1_val | rs2_val, + RISCV_XOR => rs1_val ^ rs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then rs1_val << (rs2_val[4..0]) + else rs1_val << (rs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then rs1_val >> (rs2_val[4..0]) + else rs1_val >> (rs2_val[5..0]), + RISCV_SUB => rs1_val - rs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then #\hyperref[sailRISCVzshiftzyrightzyarith32]{shift\_right\_arith32}#(rs1_val, rs2_val[4..0]) + else #\hyperref[sailRISCVzshiftzyrightzyarith64]{shift\_right\_arith64}#(rs1_val, rs2_val[5..0]) +}; +#\hyperref[sailRISCVzX]{X}#(rd) = result; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclSFENCEUnderscoreVMAzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclSFENCEUnderscoreVMAzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..8bae634e --- /dev/null +++ b/sail_latex_riscv/fclSFENCEUnderscoreVMAzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,11 @@ +let addr : #\hyperref[sailRISCVzoption]{option}#(xlenbits) = if rs1 == 0b00000 then #\hyperref[sailRISCVzNone]{None}#() else #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzX]{X}#(rs1)); +let asid : #\hyperref[sailRISCVzoption]{option}#(xlenbits) = if rs2 == 0b00000 then #\hyperref[sailRISCVzNone]{None}#() else #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzX]{X}#(rs2)); +match cur_privilege { + User => { #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); RETIRE_FAIL }, + Supervisor => match (#\hyperref[sailRISCVzarchitecture]{architecture}#(#\hyperref[sailRISCVzgetzymstatuszySXL]{get\_mstatus\_SXL}#(mstatus)), mstatus.#\hyperref[sailRISCVzTVM]{TVM}#()) { + (#\hyperref[sailRISCVzSome]{Some}#(_), 0b1) => { #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); RETIRE_FAIL }, + (#\hyperref[sailRISCVzSome]{Some}#(_), 0b0) => { #\hyperref[sailRISCVzflushzyTLB]{flush\_TLB}#(asid, addr); RETIRE_SUCCESS }, + (_, _) => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("unimplemented sfence architecture") + }, + Machine => { #\hyperref[sailRISCVzflushzyTLB]{flush\_TLB}#(asid, addr); RETIRE_SUCCESS } +} diff --git a/sail_latex_riscv/fclSHIFTIOPzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclSHIFTIOPzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..ff79bc43 --- /dev/null +++ b/sail_latex_riscv/fclSHIFTIOPzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,15 @@ +let rs1_val = #\hyperref[sailRISCVzX]{X}#(rs1); +/* the decoder guard should ensure that shamt[5] = 0 for RV32 */ +let result : xlenbits = match op { + RISCV_SLLI => if sizeof(xlen) == 32 + then rs1_val << shamt[4..0] + else rs1_val << shamt, + RISCV_SRLI => if sizeof(xlen) == 32 + then rs1_val >> shamt[4..0] + else rs1_val >> shamt, + RISCV_SRAI => if sizeof(xlen) == 32 + then #\hyperref[sailRISCVzshiftzyrightzyarith32]{shift\_right\_arith32}#(rs1_val, shamt[4..0]) + else #\hyperref[sailRISCVzshiftzyrightzyarith64]{shift\_right\_arith64}#(rs1_val, shamt) +}; +#\hyperref[sailRISCVzX]{X}#(rd) = result; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclSHIFTIWOPzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclSHIFTIWOPzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..f3b1949e --- /dev/null +++ b/sail_latex_riscv/fclSHIFTIWOPzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val = #\hyperref[sailRISCVzX]{X}#(rs1); +let result : #\hyperref[sailRISCVzbits]{bits}#(32) = match op { + RISCV_SLLIW => rs1_val[31..0] << shamt, + RISCV_SRLIW => rs1_val[31..0] >> shamt, + RISCV_SRAIW => #\hyperref[sailRISCVzshiftzyrightzyarith32]{shift\_right\_arith32}#(rs1_val[31..0], shamt) +}; +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTS]{EXTS}#(result); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclSHIFTWzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclSHIFTWzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d3cb6d31 --- /dev/null +++ b/sail_latex_riscv/fclSHIFTWzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,8 @@ +let rs1_val = (#\hyperref[sailRISCVzX]{X}#(rs1))[31..0]; +let result : #\hyperref[sailRISCVzbits]{bits}#(32) = match op { + RISCV_SLLI => rs1_val << shamt, + RISCV_SRLI => rs1_val >> shamt, + RISCV_SRAI => #\hyperref[sailRISCVzshiftzyrightzyarith32]{shift\_right\_arith32}#(rs1_val, shamt) +}; +#\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTS]{EXTS}#(result); +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclSRETzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclSRETzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..c3e3071e --- /dev/null +++ b/sail_latex_riscv/fclSRETzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,11 @@ +let sret_illegal : bool = match cur_privilege { + User => true, + Supervisor => ~ (#\hyperref[sailRISCVzhaveSupMode]{haveSupMode}# ()) | mstatus.#\hyperref[sailRISCVzTSR]{TSR}#() == 0b1, + Machine => ~ (#\hyperref[sailRISCVzhaveSupMode]{haveSupMode}# ()) +}; +if sret_illegal +then #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#() +else if ~(#\hyperref[sailRISCVzextzycheckzyxretzypriv]{ext\_check\_xret\_priv}# (Supervisor)) +then #\hyperref[sailRISCVzextzyfailzyxretzypriv]{ext\_fail\_xret\_priv}# () +else #\hyperref[sailRISCVzsetzynextzypc]{set\_next\_pc}#(#\hyperref[sailRISCVzexceptionzyhandler]{exception\_handler}#(cur_privilege, #\hyperref[sailRISCVzCTLzySRET]{CTL\_SRET}#(), PC)); +RETIRE_FAIL diff --git a/sail_latex_riscv/fclSTORECONzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclSTORECONzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..b67d724a --- /dev/null +++ b/sail_latex_riscv/fclSTORECONzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,69 @@ +if #\hyperref[sailRISCVzspeculatezyconditional]{speculate\_conditional}# () == false then { + /* should only happen in rmem + * rmem: allow SC to fail very early + */ + #\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1); RETIRE_SUCCESS +} else { + if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { + /* normal non-rmem case + * rmem: SC is allowed to #\hyperref[sailRISCVzsucceed]{succeed}# (but might fail later) + */ + /* Get the address, #\hyperref[sailRISCVzX]{X}#(rs1) (no offset). + * Extensions might perform additional checks on address validity. + */ + match #\hyperref[sailRISCVzextzydatazygetzyaddr]{ext\_data\_get\_addr}#(rs1, #\hyperref[sailRISCVzzzeros]{zeros}#(), #\hyperref[sailRISCVzWrite]{Write}#(Data), width) { + #\hyperref[sailRISCVzExtzyDataAddrzyError]{Ext\_DataAddr\_Error}#(e) => { #\hyperref[sailRISCVzextzyhandlezydatazycheckzyerror]{ext\_handle\_data\_check\_error}#(e); RETIRE_FAIL }, + #\hyperref[sailRISCVzExtzyDataAddrzyOK]{Ext\_DataAddr\_OK}#(vaddr) => { + let aligned : bool = + /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt + * to treat them as valid here; otherwise we'd need to throw an internal_error. + */ + match width { + BYTE => true, + HALF => vaddr[0..0] == 0b0, + WORD => vaddr[1..0] == 0b00, + DOUBLE => vaddr[2..0] == 0b000 + }; + if (~ (aligned)) + then { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, #\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#()); RETIRE_FAIL } + else { + if #\hyperref[sailRISCVzmatchzyreservation]{match\_reservation}#(vaddr) == false then { + /* cannot happen in rmem */ + #\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1); #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); RETIRE_SUCCESS + } else { + match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddr, #\hyperref[sailRISCVzWrite]{Write}#(Data)) { /* Write and ReadWrite are equivalent here: + * both result in a SAMO exception */ + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, _) => { + let eares : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(unit) = match (width, sizeof(xlen)) { + (WORD, _) => #\hyperref[sailRISCVzmemzywritezyea]{mem\_write\_ea}#(addr, 4, aq, rl, true), + (DOUBLE, 64) => #\hyperref[sailRISCVzmemzywritezyea]{mem\_write\_ea}#(addr, 8, aq, rl, true), + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("STORECON expected word or double") + }; + match (eares) { + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(addr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(_) => { + rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); + let res : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(bool) = match (width, sizeof(xlen)) { + (WORD, _) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 4, rs2_val[31..0], aq, rl, true), + (DOUBLE, 64) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 8, rs2_val, aq, rl, true), + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("STORECON expected word or double") + }; + match (res) { + #\hyperref[sailRISCVzMemValue]{MemValue}#(true) => { #\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); RETIRE_SUCCESS }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(false) => { #\hyperref[sailRISCVzX]{X}#(rd) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1); #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); RETIRE_SUCCESS }, + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(addr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL + } +} diff --git a/sail_latex_riscv/fclSTOREUnderscoreFPzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclSTOREUnderscoreFPzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..50bb1089 --- /dev/null +++ b/sail_latex_riscv/fclSTOREUnderscoreFPzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,33 @@ +let offset : xlenbits = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm); +let (aq, rl, con) = (false, false, false); +/* Get the address, #\hyperref[sailRISCVzX]{X}#(rs1) + offset. + Some extensions perform additional checks on address validity. */ +match #\hyperref[sailRISCVzextzydatazygetzyaddr]{ext\_data\_get\_addr}#(rs1, offset, #\hyperref[sailRISCVzWrite]{Write}#(Data), width) { + #\hyperref[sailRISCVzExtzyDataAddrzyError]{Ext\_DataAddr\_Error}#(e) => { #\hyperref[sailRISCVzextzyhandlezydatazycheckzyerror]{ext\_handle\_data\_check\_error}#(e); RETIRE_FAIL }, + #\hyperref[sailRISCVzExtzyDataAddrzyOK]{Ext\_DataAddr\_OK}#(vaddr) => + if #\hyperref[sailRISCVzcheckzymisaligned]{check\_misaligned}#(vaddr, width) + then { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, #\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#()); RETIRE_FAIL } + else match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddr, #\hyperref[sailRISCVzWrite]{Write}#(Data)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, _) => { + let eares : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(unit) = match width { + BYTE => #\hyperref[sailRISCVzMemValue]{MemValue}# () /* bogus placeholder for illegal size */, + HALF => #\hyperref[sailRISCVzMemValue]{MemValue}# () /* bogus placeholder for illegal size */, + WORD => #\hyperref[sailRISCVzmemzywritezyea]{mem\_write\_ea}#(addr, 4, aq, rl, false), + DOUBLE => #\hyperref[sailRISCVzmemzywritezyea]{mem\_write\_ea}#(addr, 8, aq, rl, false) + }; + match (eares) { + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(addr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(_) => { + let rs2_val = #\hyperref[sailRISCVzF]{F}#(rs2); + match (width, sizeof(xlen)) { + (BYTE, _) => { #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); RETIRE_FAIL }, + (HALF, _) => { #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); RETIRE_FAIL }, + (WORD, _) => #\hyperref[sailRISCVzprocesszyfstore]{process\_fstore}# (vaddr, #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 4, rs2_val[31..0], aq, rl, con)), + (DOUBLE, 64) => #\hyperref[sailRISCVzprocesszyfstore]{process\_fstore}# (vaddr, #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 8, rs2_val, aq, rl, con)) + }; + } + } + } + } +} diff --git a/sail_latex_riscv/fclSTOREzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclSTOREzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..b4079968 --- /dev/null +++ b/sail_latex_riscv/fclSTOREzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,37 @@ +let offset : xlenbits = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm); +/* Get the address, #\hyperref[sailRISCVzX]{X}#(rs1) + offset. + Some extensions perform additional checks on address validity. */ +match #\hyperref[sailRISCVzextzydatazygetzyaddr]{ext\_data\_get\_addr}#(rs1, offset, #\hyperref[sailRISCVzWrite]{Write}#(Data), width) { + #\hyperref[sailRISCVzExtzyDataAddrzyError]{Ext\_DataAddr\_Error}#(e) => { #\hyperref[sailRISCVzextzyhandlezydatazycheckzyerror]{ext\_handle\_data\_check\_error}#(e); RETIRE_FAIL }, + #\hyperref[sailRISCVzExtzyDataAddrzyOK]{Ext\_DataAddr\_OK}#(vaddr) => + if #\hyperref[sailRISCVzcheckzymisaligned]{check\_misaligned}#(vaddr, width) + then { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, #\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#()); RETIRE_FAIL } + else match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddr, #\hyperref[sailRISCVzWrite]{Write}#(Data)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(paddr, _) => { + let eares : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(unit) = match width { + BYTE => #\hyperref[sailRISCVzmemzywritezyea]{mem\_write\_ea}#(paddr, 1, aq, rl, false), + HALF => #\hyperref[sailRISCVzmemzywritezyea]{mem\_write\_ea}#(paddr, 2, aq, rl, false), + WORD => #\hyperref[sailRISCVzmemzywritezyea]{mem\_write\_ea}#(paddr, 4, aq, rl, false), + DOUBLE => #\hyperref[sailRISCVzmemzywritezyea]{mem\_write\_ea}#(paddr, 8, aq, rl, false) + }; + match (eares) { + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(_) => { + let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); + let res : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(paddr, 1, rs2_val[7..0], aq, rl, false), + (HALF, _) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(paddr, 2, rs2_val[15..0], aq, rl, false), + (WORD, _) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(paddr, 4, rs2_val[31..0], aq, rl, false), + (DOUBLE, 64) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(paddr, 8, rs2_val, aq, rl, false) + }; + match (res) { + #\hyperref[sailRISCVzMemValue]{MemValue}#(true) => RETIRE_SUCCESS, + #\hyperref[sailRISCVzMemValue]{MemValue}#(false) => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("store got false from mem_write_value"), + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, e); RETIRE_FAIL } + } + } + } + } + } +} diff --git a/sail_latex_riscv/fclStoreCapCapzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclStoreCapCapzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..eda649ff --- /dev/null +++ b/sail_latex_riscv/fclStoreCapCapzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let vaddr = cs1_val.address; +#\hyperref[sailRISCVzhandlezystorezycapzyviazycap]{handle\_store\_cap\_via\_cap}#(cs2, 0b0 @ cs1, cs1_val, vaddr) diff --git a/sail_latex_riscv/fclStoreCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclStoreCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..872c7e3e --- /dev/null +++ b/sail_latex_riscv/fclStoreCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let ddc_val = DDC; +let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); +#\hyperref[sailRISCVzhandlezystorezycapzyviazycap]{handle\_store\_cap\_via\_cap}#(cs2, DDC_IDX, ddc_val, vaddr) diff --git a/sail_latex_riscv/fclStoreCapImmzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclStoreCapImmzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..1a1552b4 --- /dev/null +++ b/sail_latex_riscv/fclStoreCapImmzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let offset : xlenbits = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm); +let (auth_val, vaddr, auth_idx) = #\hyperref[sailRISCVzgetzycherizymodezycapzyaddr]{get\_cheri\_mode\_cap\_addr}#(rs1_cs1, offset); +#\hyperref[sailRISCVzhandlezystorezycapzyviazycap]{handle\_store\_cap\_via\_cap}#(cs2, auth_idx, auth_val, vaddr) diff --git a/sail_latex_riscv/fclStoreCondCapCapzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclStoreCondCapCapzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..f1ba3a25 --- /dev/null +++ b/sail_latex_riscv/fclStoreCondCapCapzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +if #\hyperref[sailRISCVzspeculatezyconditional]{speculate\_conditional}# () == false then { + /* should only happen in rmem + * rmem: allow SC to fail very early + */ + #\hyperref[sailRISCVzC]{C}#(cs2) = #\hyperref[sailRISCVzintzytozycap]{int\_to\_cap}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1)); + RETIRE_SUCCESS +} else if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { + let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); + let vaddr = cs1_val.address; + #\hyperref[sailRISCVzhandlezystorezycondzycapzyviazycap]{handle\_store\_cond\_cap\_via\_cap}#(cs2, 0b0 @ cs1, cs1_val, vaddr) +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclStoreCondCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclStoreCondCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..3cea7a36 --- /dev/null +++ b/sail_latex_riscv/fclStoreCondCapDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +if #\hyperref[sailRISCVzspeculatezyconditional]{speculate\_conditional}# () == false then { + /* should only happen in rmem + * rmem: allow SC to fail very early + */ + #\hyperref[sailRISCVzC]{C}#(cs2) = #\hyperref[sailRISCVzintzytozycap]{int\_to\_cap}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1)); + RETIRE_SUCCESS +} else if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { + let ddc_val = DDC; + let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); + #\hyperref[sailRISCVzhandlezystorezycondzycapzyviazycap]{handle\_store\_cond\_cap\_via\_cap}#(cs2, DDC_IDX, ddc_val, vaddr) +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclStoreCondCapzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclStoreCondCapzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..9a6a5ffc --- /dev/null +++ b/sail_latex_riscv/fclStoreCondCapzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +if #\hyperref[sailRISCVzspeculatezyconditional]{speculate\_conditional}# () == false then { + /* should only happen in rmem + * rmem: allow SC to fail very early + */ + #\hyperref[sailRISCVzX]{X}#(rs2) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1); + RETIRE_SUCCESS +} else if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { + let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); + let vaddr = cs1_val.address; + #\hyperref[sailRISCVzhandlezystorezycondzydatazyviazycap]{handle\_store\_cond\_data\_via\_cap}#(rs2, 0b0 @ cs1, cs1_val, vaddr, width) +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclStoreCondDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclStoreCondDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..4d341708 --- /dev/null +++ b/sail_latex_riscv/fclStoreCondDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,14 @@ +if #\hyperref[sailRISCVzspeculatezyconditional]{speculate\_conditional}# () == false then { + /* should only happen in rmem + * rmem: allow SC to fail very early + */ + #\hyperref[sailRISCVzX]{X}#(rs2) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1); + RETIRE_SUCCESS +} else if #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() then { + let ddc_val = DDC; + let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); + #\hyperref[sailRISCVzhandlezystorezycondzydatazyviazycap]{handle\_store\_cond\_data\_via\_cap}#(rs2, DDC_IDX, ddc_val, vaddr, width) +} else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + RETIRE_FAIL +} diff --git a/sail_latex_riscv/fclStoreDataCapzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclStoreDataCapzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..b034fe4f --- /dev/null +++ b/sail_latex_riscv/fclStoreDataCapzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let cs1_val = #\hyperref[sailRISCVzC]{C}#(cs1); +let vaddr = cs1_val.address; +#\hyperref[sailRISCVzhandlezystorezydatazyviazycap]{handle\_store\_data\_via\_cap}#(rs2, 0b0 @ cs1, cs1_val, vaddr, width) diff --git a/sail_latex_riscv/fclStoreDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclStoreDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..6f69313b --- /dev/null +++ b/sail_latex_riscv/fclStoreDataDDCzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,3 @@ +let ddc_val = DDC; +let vaddr = ddc_val.address + #\hyperref[sailRISCVzX]{X}#(rs1); +#\hyperref[sailRISCVzhandlezystorezydatazyviazycap]{handle\_store\_data\_via\_cap}#(rs2, DDC_IDX, ddc_val, vaddr, width) diff --git a/sail_latex_riscv/fclUTYPEzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclUTYPEzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..f4257ae3 --- /dev/null +++ b/sail_latex_riscv/fclUTYPEzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,7 @@ +let off : xlenbits = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm @ 0x000); +let ret : xlenbits = match op { + RISCV_LUI => off, + RISCV_AUIPC => #\hyperref[sailRISCVzgetzyarchzypc]{get\_arch\_pc}#() + off +}; +#\hyperref[sailRISCVzX]{X}#(rd) = ret; +RETIRE_SUCCESS diff --git a/sail_latex_riscv/fclWFIzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/fclWFIzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..41a2d7f8 --- /dev/null +++ b/sail_latex_riscv/fclWFIzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1,6 @@ +match cur_privilege { + Machine => { #\hyperref[sailRISCVzplatformzywfi]{platform\_wfi}#(); RETIRE_SUCCESS }, + Supervisor => if mstatus.#\hyperref[sailRISCVzTW]{TW}#() == 0b1 + then { #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); RETIRE_FAIL } + else { #\hyperref[sailRISCVzplatformzywfi]{platform\_wfi}#(); RETIRE_SUCCESS }, + User => { #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); RETIRE_FAIL } diff --git a/sail_latex_riscv/fclandBoolAzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclandBoolAzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..6e29e65e --- /dev/null +++ b/sail_latex_riscv/fclandBoolAzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}#(0x000, _) = #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() & #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() // ustatus diff --git a/sail_latex_riscv/fclandBoolBzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclandBoolBzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..bdb4ed09 --- /dev/null +++ b/sail_latex_riscv/fclandBoolBzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}#(0x004, _) = #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() & #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() // uie diff --git a/sail_latex_riscv/fclandBoolCzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclandBoolCzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..eff3bca1 --- /dev/null +++ b/sail_latex_riscv/fclandBoolCzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}#(0x005, _) = #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() & #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() // utvec diff --git a/sail_latex_riscv/fclandBoolDzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclandBoolDzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..609c239c --- /dev/null +++ b/sail_latex_riscv/fclandBoolDzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}#(0x040, _) = #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() & #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() // uscratch diff --git a/sail_latex_riscv/fclandBoolEzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclandBoolEzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..b1d67c9a --- /dev/null +++ b/sail_latex_riscv/fclandBoolEzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}#(0x041, _) = #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() & #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() // uepc diff --git a/sail_latex_riscv/fclandBoolFzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclandBoolFzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..57eb4246 --- /dev/null +++ b/sail_latex_riscv/fclandBoolFzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}#(0x042, _) = #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() & #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() // ucause diff --git a/sail_latex_riscv/fclandBoolGzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclandBoolGzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..52113a64 --- /dev/null +++ b/sail_latex_riscv/fclandBoolGzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}#(0x043, _) = #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() & #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() // utval diff --git a/sail_latex_riscv/fclandBoolHzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclandBoolHzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..69075163 --- /dev/null +++ b/sail_latex_riscv/fclandBoolHzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}#(0x044, _) = #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() & #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() // uip diff --git a/sail_latex_riscv/fclandBoolzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclandBoolzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..fbf4aa41 --- /dev/null +++ b/sail_latex_riscv/fclandBoolzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}# (0x9C0, p) = #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (p == Machine | p == Supervisor) // sccsr diff --git a/sail_latex_riscv/fclandVeczext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclandVeczext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..e2d7bd29 --- /dev/null +++ b/sail_latex_riscv/fclandVeczext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}#(0x041) = #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzgetzyxretzytarget]{get\_xret\_target}#(User) & #\hyperref[sailRISCVzpczyalignmentzymask]{pc\_alignment\_mask}#()) diff --git a/sail_latex_riscv/fclgetUtveczext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclgetUtveczext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..79a24ea7 --- /dev/null +++ b/sail_latex_riscv/fclgetUtveczext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}#(0x005) = #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzgetzyutvec]{get\_utvec}#()) diff --git a/sail_latex_riscv/fclhaveUsrModezext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclhaveUsrModezext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..1a1df795 --- /dev/null +++ b/sail_latex_riscv/fclhaveUsrModezext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}# (0x8C0, p) = #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() // uccsr diff --git a/sail_latex_riscv/fclorBoolAzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclorBoolAzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..3a03b301 --- /dev/null +++ b/sail_latex_riscv/fclorBoolAzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}# (0x001, _) = #\hyperref[sailRISCVzhaveFExt]{haveFExt}#() | #\hyperref[sailRISCVzhaveDExt]{haveDExt}#() diff --git a/sail_latex_riscv/fclorBoolBzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclorBoolBzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..63855f0c --- /dev/null +++ b/sail_latex_riscv/fclorBoolBzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}# (0x002, _) = #\hyperref[sailRISCVzhaveFExt]{haveFExt}#() | #\hyperref[sailRISCVzhaveDExt]{haveDExt}#() diff --git a/sail_latex_riscv/fclorBoolCzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclorBoolCzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..49fe846a --- /dev/null +++ b/sail_latex_riscv/fclorBoolCzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}# (0x003, _) = #\hyperref[sailRISCVzhaveFExt]{haveFExt}#() | #\hyperref[sailRISCVzhaveDExt]{haveDExt}#() diff --git a/sail_latex_riscv/fclorBoolzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclorBoolzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..fd69ecb4 --- /dev/null +++ b/sail_latex_riscv/fclorBoolzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}# (0xBC0, p) = p == Machine | p == Supervisor // mccsr diff --git a/sail_latex_riscv/fcluscratchzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fcluscratchzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..6a979d30 --- /dev/null +++ b/sail_latex_riscv/fcluscratchzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}#(0x040) = #\hyperref[sailRISCVzSome]{Some}#(uscratch) diff --git a/sail_latex_riscv/fclutvalzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/fclutvalzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..5fd766f6 --- /dev/null +++ b/sail_latex_riscv/fclutvalzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}#(0x043) = #\hyperref[sailRISCVzSome]{Some}#(utval) diff --git a/sail_latex_riscv/fclzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/fclzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..adcadea1 --- /dev/null +++ b/sail_latex_riscv/fclzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}#(_, _) = false diff --git a/sail_latex_riscv/fclzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/fclzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..4e8a8fb9 --- /dev/null +++ b/sail_latex_riscv/fclzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +function clause #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}# (0x8C0, value) = { uccsr = #\hyperref[sailRISCVzlegalizzezyccsr]{legalize\_ccsr}#(uccsr, value); #\hyperref[sailRISCVzSome]{Some}#(uccsr.#\hyperref[sailRISCVzbits]{bits}#()) } diff --git a/sail_latex_riscv/fnz__ided888b8991a27578d5dd72f84db80bce.tex b/sail_latex_riscv/fnz__ided888b8991a27578d5dd72f84db80bce.tex new file mode 100644 index 00000000..ed8afda1 --- /dev/null +++ b/sail_latex_riscv/fnz__ided888b8991a27578d5dd72f84db80bce.tex @@ -0,0 +1 @@ +function __id forall 'n. (x: #\hyperref[sailRISCVzint]{int}#('n)) -> #\hyperref[sailRISCVzint]{int}#('n) = x diff --git a/sail_latex_riscv/fnz__readram_meta16c05ad578ee799cab7403aa8924f5dd.tex b/sail_latex_riscv/fnz__readram_meta16c05ad578ee799cab7403aa8924f5dd.tex new file mode 100644 index 00000000..7a8aa29b --- /dev/null +++ b/sail_latex_riscv/fnz__readram_meta16c05ad578ee799cab7403aa8924f5dd.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzzyzyReadRAMzyMeta]{\_\_ReadRAM\_Meta}#(addr, width) = { + let tag_addr = #\hyperref[sailRISCVzaddrzytozytagzyaddr]{addr\_to\_tag\_addr}#(addr); + let tag = #\hyperref[sailRISCVzMEMrzytag]{MEMr\_tag}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(tag_addr)); + if #\hyperref[sailRISCVzgetzyconfigzyprintzymem]{get\_config\_print\_mem}#() then + #\hyperref[sailRISCVzprintzymem]{print\_mem}#("tag[R," ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVztagzyaddrzytozyaddr]{tag\_addr\_to\_addr}#(tag_addr)) ^ "] -> " ^ (if tag then "1" else "0")); + tag +} diff --git a/sail_latex_riscv/fnz__writeram_meta071a60a48b7f4ceb27499d72826fb174.tex b/sail_latex_riscv/fnz__writeram_meta071a60a48b7f4ceb27499d72826fb174.tex new file mode 100644 index 00000000..7dda9d25 --- /dev/null +++ b/sail_latex_riscv/fnz__writeram_meta071a60a48b7f4ceb27499d72826fb174.tex @@ -0,0 +1,16 @@ +function #\hyperref[sailRISCVzzyzyWriteRAMzyMeta]{\_\_WriteRAM\_Meta}#(addr, width, tag) = { + let tag_addr = #\hyperref[sailRISCVzaddrzytozytagzyaddr]{addr\_to\_tag\_addr}#(addr); + if #\hyperref[sailRISCVzgetzyconfigzyprintzymem]{get\_config\_print\_mem}#() then + #\hyperref[sailRISCVzprintzymem]{print\_mem}#("tag[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVztagzyaddrzytozyaddr]{tag\_addr\_to\_addr}#(tag_addr)) ^ "] <- " ^ (if tag then "1" else "0")); + #\hyperref[sailRISCVzMEMwzytag]{MEMw\_tag}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(tag_addr), tag); + /* If the write crosses a cap_size alignment boundary then we need + * to write the tag for the subsequent region. Writes greater than + * cap_size that might span more than two regions are not supported. + */ + let tag_addr2 = #\hyperref[sailRISCVzaddrzytozytagzyaddr]{addr\_to\_tag\_addr}#(addr + width - 1); + if tag_addr != tag_addr2 then { + if #\hyperref[sailRISCVzgetzyconfigzyprintzymem]{get\_config\_print\_mem}#() then + #\hyperref[sailRISCVzprintzymem]{print\_mem}#("tag[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVztagzyaddrzytozyaddr]{tag\_addr\_to\_addr}#(tag_addr2)) ^ "] <- " ^ (if tag then "1" else "0")); + #\hyperref[sailRISCVzMEMwzytag]{MEMw\_tag}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(tag_addr2), tag); + } +} diff --git a/sail_latex_riscv/fnz_get_ccsr_bitsa5bf4f91be070c5e733b7c8dcd21079f.tex b/sail_latex_riscv/fnz_get_ccsr_bitsa5bf4f91be070c5e733b7c8dcd21079f.tex new file mode 100644 index 00000000..a88569da --- /dev/null +++ b/sail_latex_riscv/fnz_get_ccsr_bitsa5bf4f91be070c5e733b7c8dcd21079f.tex @@ -0,0 +1 @@ +function _get_ccsr_bits v = subrange_bits(v.ccsr_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_ccsr_cap_idx07f5b7d982282306c072600892773224.tex b/sail_latex_riscv/fnz_get_ccsr_cap_idx07f5b7d982282306c072600892773224.tex new file mode 100644 index 00000000..b3e5f530 --- /dev/null +++ b/sail_latex_riscv/fnz_get_ccsr_cap_idx07f5b7d982282306c072600892773224.tex @@ -0,0 +1 @@ +function _get_ccsr_cap_idx v = subrange_bits(v.ccsr_chunk_0, 15, 10) diff --git a/sail_latex_riscv/fnz_get_ccsr_caused575f504e43b5c4f705e1e76299969a8.tex b/sail_latex_riscv/fnz_get_ccsr_caused575f504e43b5c4f705e1e76299969a8.tex new file mode 100644 index 00000000..2fba9037 --- /dev/null +++ b/sail_latex_riscv/fnz_get_ccsr_caused575f504e43b5c4f705e1e76299969a8.tex @@ -0,0 +1 @@ +function _get_ccsr_cause v = subrange_bits(v.ccsr_chunk_0, 9, 5) diff --git a/sail_latex_riscv/fnz_get_ccsr_d5cb2dcaceb4937b225b4475484d2bf2d.tex b/sail_latex_riscv/fnz_get_ccsr_d5cb2dcaceb4937b225b4475484d2bf2d.tex new file mode 100644 index 00000000..345a8fcf --- /dev/null +++ b/sail_latex_riscv/fnz_get_ccsr_d5cb2dcaceb4937b225b4475484d2bf2d.tex @@ -0,0 +1 @@ +function _get_ccsr_d v = subrange_bits(v.ccsr_chunk_0, 1, 1) diff --git a/sail_latex_riscv/fnz_get_ccsr_e6d359c132221ee638d3b99e5bb880b1c.tex b/sail_latex_riscv/fnz_get_ccsr_e6d359c132221ee638d3b99e5bb880b1c.tex new file mode 100644 index 00000000..ae5e18ad --- /dev/null +++ b/sail_latex_riscv/fnz_get_ccsr_e6d359c132221ee638d3b99e5bb880b1c.tex @@ -0,0 +1 @@ +function _get_ccsr_e v = subrange_bits(v.ccsr_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_counteren_bits63485ab688d4675e7f4e8ef14d9606ff.tex b/sail_latex_riscv/fnz_get_counteren_bits63485ab688d4675e7f4e8ef14d9606ff.tex new file mode 100644 index 00000000..29994689 --- /dev/null +++ b/sail_latex_riscv/fnz_get_counteren_bits63485ab688d4675e7f4e8ef14d9606ff.tex @@ -0,0 +1 @@ +function _get_Counteren_bits v = subrange_bits(v.Counteren_chunk_0, 31, 0) diff --git a/sail_latex_riscv/fnz_get_counteren_cy6e2b3bcf0f631c5bfe1602b7224ac3aa.tex b/sail_latex_riscv/fnz_get_counteren_cy6e2b3bcf0f631c5bfe1602b7224ac3aa.tex new file mode 100644 index 00000000..32eb00f6 --- /dev/null +++ b/sail_latex_riscv/fnz_get_counteren_cy6e2b3bcf0f631c5bfe1602b7224ac3aa.tex @@ -0,0 +1 @@ +function _get_Counteren_CY v = subrange_bits(v.Counteren_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_counteren_hpm3a5db98081f95347897bc13fea2e569f.tex b/sail_latex_riscv/fnz_get_counteren_hpm3a5db98081f95347897bc13fea2e569f.tex new file mode 100644 index 00000000..59d6673f --- /dev/null +++ b/sail_latex_riscv/fnz_get_counteren_hpm3a5db98081f95347897bc13fea2e569f.tex @@ -0,0 +1 @@ +function _get_Counteren_HPM v = subrange_bits(v.Counteren_chunk_0, 31, 3) diff --git a/sail_latex_riscv/fnz_get_counteren_ir0443e9a01364d655f672be9fb3f334c2.tex b/sail_latex_riscv/fnz_get_counteren_ir0443e9a01364d655f672be9fb3f334c2.tex new file mode 100644 index 00000000..64045c7b --- /dev/null +++ b/sail_latex_riscv/fnz_get_counteren_ir0443e9a01364d655f672be9fb3f334c2.tex @@ -0,0 +1 @@ +function _get_Counteren_IR v = subrange_bits(v.Counteren_chunk_0, 2, 2) diff --git a/sail_latex_riscv/fnz_get_counteren_tme8e19db38cbd8e49aa4656434c826c16.tex b/sail_latex_riscv/fnz_get_counteren_tme8e19db38cbd8e49aa4656434c826c16.tex new file mode 100644 index 00000000..1ff8e039 --- /dev/null +++ b/sail_latex_riscv/fnz_get_counteren_tme8e19db38cbd8e49aa4656434c826c16.tex @@ -0,0 +1 @@ +function _get_Counteren_TM v = subrange_bits(v.Counteren_chunk_0, 1, 1) diff --git a/sail_latex_riscv/fnz_get_counterin_bits11d3d881d3130628193ac87a6d2fd74a.tex b/sail_latex_riscv/fnz_get_counterin_bits11d3d881d3130628193ac87a6d2fd74a.tex new file mode 100644 index 00000000..63f3369c --- /dev/null +++ b/sail_latex_riscv/fnz_get_counterin_bits11d3d881d3130628193ac87a6d2fd74a.tex @@ -0,0 +1 @@ +function _get_Counterin_bits v = subrange_bits(v.Counterin_chunk_0, 31, 0) diff --git a/sail_latex_riscv/fnz_get_counterin_cydc6f1e9f2967dff249969b51399a14ca.tex b/sail_latex_riscv/fnz_get_counterin_cydc6f1e9f2967dff249969b51399a14ca.tex new file mode 100644 index 00000000..ca602cf5 --- /dev/null +++ b/sail_latex_riscv/fnz_get_counterin_cydc6f1e9f2967dff249969b51399a14ca.tex @@ -0,0 +1 @@ +function _get_Counterin_CY v = subrange_bits(v.Counterin_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_counterin_ira4b70e343466abb62da1c490774a9c7a.tex b/sail_latex_riscv/fnz_get_counterin_ira4b70e343466abb62da1c490774a9c7a.tex new file mode 100644 index 00000000..928c5db0 --- /dev/null +++ b/sail_latex_riscv/fnz_get_counterin_ira4b70e343466abb62da1c490774a9c7a.tex @@ -0,0 +1 @@ +function _get_Counterin_IR v = subrange_bits(v.Counterin_chunk_0, 2, 2) diff --git a/sail_latex_riscv/fnz_get_ext_pte_bits_bits65e7ce08656cda27553d43325a4acc17.tex b/sail_latex_riscv/fnz_get_ext_pte_bits_bits65e7ce08656cda27553d43325a4acc17.tex new file mode 100644 index 00000000..ba25819e --- /dev/null +++ b/sail_latex_riscv/fnz_get_ext_pte_bits_bits65e7ce08656cda27553d43325a4acc17.tex @@ -0,0 +1 @@ +function _get_Ext_PTE_Bits_bits v = subrange_bits(v.Ext_PTE_Bits_chunk_0, 9, 0) diff --git a/sail_latex_riscv/fnz_get_ext_pte_bits_capread333ce4aba2e72cd3f2c792b515f6703a.tex b/sail_latex_riscv/fnz_get_ext_pte_bits_capread333ce4aba2e72cd3f2c792b515f6703a.tex new file mode 100644 index 00000000..c295c1f2 --- /dev/null +++ b/sail_latex_riscv/fnz_get_ext_pte_bits_capread333ce4aba2e72cd3f2c792b515f6703a.tex @@ -0,0 +1 @@ +function _get_Ext_PTE_Bits_CapRead v = subrange_bits(v.Ext_PTE_Bits_chunk_0, 8, 8) diff --git a/sail_latex_riscv/fnz_get_ext_pte_bits_capwrite0baac5a6f85e40fbdac28ee04067e65c.tex b/sail_latex_riscv/fnz_get_ext_pte_bits_capwrite0baac5a6f85e40fbdac28ee04067e65c.tex new file mode 100644 index 00000000..dddcd50d --- /dev/null +++ b/sail_latex_riscv/fnz_get_ext_pte_bits_capwrite0baac5a6f85e40fbdac28ee04067e65c.tex @@ -0,0 +1 @@ +function _get_Ext_PTE_Bits_CapWrite v = subrange_bits(v.Ext_PTE_Bits_chunk_0, 9, 9) diff --git a/sail_latex_riscv/fnz_get_fcsr_bits38eb65790eec4fcba3d93a546d99637e.tex b/sail_latex_riscv/fnz_get_fcsr_bits38eb65790eec4fcba3d93a546d99637e.tex new file mode 100644 index 00000000..70c9cb21 --- /dev/null +++ b/sail_latex_riscv/fnz_get_fcsr_bits38eb65790eec4fcba3d93a546d99637e.tex @@ -0,0 +1 @@ +function _get_Fcsr_bits v = subrange_bits(v.Fcsr_chunk_0, 31, 0) diff --git a/sail_latex_riscv/fnz_get_fcsr_fflagse7920eae191e6251650c82768d152824.tex b/sail_latex_riscv/fnz_get_fcsr_fflagse7920eae191e6251650c82768d152824.tex new file mode 100644 index 00000000..6ec255fd --- /dev/null +++ b/sail_latex_riscv/fnz_get_fcsr_fflagse7920eae191e6251650c82768d152824.tex @@ -0,0 +1 @@ +function _get_Fcsr_FFLAGS v = subrange_bits(v.Fcsr_chunk_0, 4, 0) diff --git a/sail_latex_riscv/fnz_get_fcsr_frmc585de536fb10558f0653a1315c2301e.tex b/sail_latex_riscv/fnz_get_fcsr_frmc585de536fb10558f0653a1315c2301e.tex new file mode 100644 index 00000000..f7dec97b --- /dev/null +++ b/sail_latex_riscv/fnz_get_fcsr_frmc585de536fb10558f0653a1315c2301e.tex @@ -0,0 +1 @@ +function _get_Fcsr_FRM v = subrange_bits(v.Fcsr_chunk_0, 7, 5) diff --git a/sail_latex_riscv/fnz_get_htif_cmd_bits1eb71429743386e681784c96e268deaf.tex b/sail_latex_riscv/fnz_get_htif_cmd_bits1eb71429743386e681784c96e268deaf.tex new file mode 100644 index 00000000..903b8cda --- /dev/null +++ b/sail_latex_riscv/fnz_get_htif_cmd_bits1eb71429743386e681784c96e268deaf.tex @@ -0,0 +1 @@ +function _get_htif_cmd_bits v = subrange_bits(v.htif_cmd_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_htif_cmd_cmd819958801f753cde6a79cea6d1060596.tex b/sail_latex_riscv/fnz_get_htif_cmd_cmd819958801f753cde6a79cea6d1060596.tex new file mode 100644 index 00000000..a8cfc206 --- /dev/null +++ b/sail_latex_riscv/fnz_get_htif_cmd_cmd819958801f753cde6a79cea6d1060596.tex @@ -0,0 +1 @@ +function _get_htif_cmd_cmd v = subrange_bits(v.htif_cmd_chunk_0, 55, 48) diff --git a/sail_latex_riscv/fnz_get_htif_cmd_device49a4f976524fe1bb4129d075a7e50cb3.tex b/sail_latex_riscv/fnz_get_htif_cmd_device49a4f976524fe1bb4129d075a7e50cb3.tex new file mode 100644 index 00000000..210e238f --- /dev/null +++ b/sail_latex_riscv/fnz_get_htif_cmd_device49a4f976524fe1bb4129d075a7e50cb3.tex @@ -0,0 +1 @@ +function _get_htif_cmd_device v = subrange_bits(v.htif_cmd_chunk_0, 63, 56) diff --git a/sail_latex_riscv/fnz_get_htif_cmd_payload61085de7e39b8efa3ae178ccc88eb7d5.tex b/sail_latex_riscv/fnz_get_htif_cmd_payload61085de7e39b8efa3ae178ccc88eb7d5.tex new file mode 100644 index 00000000..b333a398 --- /dev/null +++ b/sail_latex_riscv/fnz_get_htif_cmd_payload61085de7e39b8efa3ae178ccc88eb7d5.tex @@ -0,0 +1 @@ +function _get_htif_cmd_payload v = subrange_bits(v.htif_cmd_chunk_0, 47, 0) diff --git a/sail_latex_riscv/fnz_get_mcause_bits74f8f43c07e2abaa1ac3d45b4a2b6ba2.tex b/sail_latex_riscv/fnz_get_mcause_bits74f8f43c07e2abaa1ac3d45b4a2b6ba2.tex new file mode 100644 index 00000000..1e2a7966 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mcause_bits74f8f43c07e2abaa1ac3d45b4a2b6ba2.tex @@ -0,0 +1 @@ +function _get_Mcause_bits v = subrange_bits(v.Mcause_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_mcause_cause1bdd5398cd23fc4b4f8215c110954e19.tex b/sail_latex_riscv/fnz_get_mcause_cause1bdd5398cd23fc4b4f8215c110954e19.tex new file mode 100644 index 00000000..5e5ff5c7 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mcause_cause1bdd5398cd23fc4b4f8215c110954e19.tex @@ -0,0 +1 @@ +function _get_Mcause_Cause v = subrange_bits(v.Mcause_chunk_0, 62, 0) diff --git a/sail_latex_riscv/fnz_get_mcause_isinterruptca4d348b8a2eaccd2e92f7ee7d03bee7.tex b/sail_latex_riscv/fnz_get_mcause_isinterruptca4d348b8a2eaccd2e92f7ee7d03bee7.tex new file mode 100644 index 00000000..2b5e959d --- /dev/null +++ b/sail_latex_riscv/fnz_get_mcause_isinterruptca4d348b8a2eaccd2e92f7ee7d03bee7.tex @@ -0,0 +1 @@ +function _get_Mcause_IsInterrupt v = subrange_bits(v.Mcause_chunk_0, 63, 63) diff --git a/sail_latex_riscv/fnz_get_medeleg_bits254afc4d0ea5cd20737b995ecb86af96.tex b/sail_latex_riscv/fnz_get_medeleg_bits254afc4d0ea5cd20737b995ecb86af96.tex new file mode 100644 index 00000000..2fc039e8 --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_bits254afc4d0ea5cd20737b995ecb86af96.tex @@ -0,0 +1 @@ +function _get_Medeleg_bits v = subrange_bits(v.Medeleg_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_medeleg_breakpointd7558e491e73df703b5f48b45fc459fb.tex b/sail_latex_riscv/fnz_get_medeleg_breakpointd7558e491e73df703b5f48b45fc459fb.tex new file mode 100644 index 00000000..7ba4a6bd --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_breakpointd7558e491e73df703b5f48b45fc459fb.tex @@ -0,0 +1 @@ +function _get_Medeleg_Breakpoint v = subrange_bits(v.Medeleg_chunk_0, 3, 3) diff --git a/sail_latex_riscv/fnz_get_medeleg_fetch_access_faulte776b2e2dd4e9f7381bf51e711dd1a07.tex b/sail_latex_riscv/fnz_get_medeleg_fetch_access_faulte776b2e2dd4e9f7381bf51e711dd1a07.tex new file mode 100644 index 00000000..b44d18fc --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_fetch_access_faulte776b2e2dd4e9f7381bf51e711dd1a07.tex @@ -0,0 +1 @@ +function _get_Medeleg_Fetch_Access_Fault v = subrange_bits(v.Medeleg_chunk_0, 1, 1) diff --git a/sail_latex_riscv/fnz_get_medeleg_fetch_addr_aligncd9c88ba625264505b33ace3265d8ea5.tex b/sail_latex_riscv/fnz_get_medeleg_fetch_addr_aligncd9c88ba625264505b33ace3265d8ea5.tex new file mode 100644 index 00000000..c1baa497 --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_fetch_addr_aligncd9c88ba625264505b33ace3265d8ea5.tex @@ -0,0 +1 @@ +function _get_Medeleg_Fetch_Addr_Align v = subrange_bits(v.Medeleg_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_medeleg_fetch_page_fault584acc3a0e750181acc1bdc03c42b15c.tex b/sail_latex_riscv/fnz_get_medeleg_fetch_page_fault584acc3a0e750181acc1bdc03c42b15c.tex new file mode 100644 index 00000000..2bebb6f1 --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_fetch_page_fault584acc3a0e750181acc1bdc03c42b15c.tex @@ -0,0 +1 @@ +function _get_Medeleg_Fetch_Page_Fault v = subrange_bits(v.Medeleg_chunk_0, 12, 12) diff --git a/sail_latex_riscv/fnz_get_medeleg_illegal_instre418e5763eb05a3ffb4d6c978a1e3ff3.tex b/sail_latex_riscv/fnz_get_medeleg_illegal_instre418e5763eb05a3ffb4d6c978a1e3ff3.tex new file mode 100644 index 00000000..81a130cd --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_illegal_instre418e5763eb05a3ffb4d6c978a1e3ff3.tex @@ -0,0 +1 @@ +function _get_Medeleg_Illegal_Instr v = subrange_bits(v.Medeleg_chunk_0, 2, 2) diff --git a/sail_latex_riscv/fnz_get_medeleg_load_access_fault83f8e20712f80aab31a1decf153c8956.tex b/sail_latex_riscv/fnz_get_medeleg_load_access_fault83f8e20712f80aab31a1decf153c8956.tex new file mode 100644 index 00000000..eb7dc2fb --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_load_access_fault83f8e20712f80aab31a1decf153c8956.tex @@ -0,0 +1 @@ +function _get_Medeleg_Load_Access_Fault v = subrange_bits(v.Medeleg_chunk_0, 5, 5) diff --git a/sail_latex_riscv/fnz_get_medeleg_load_addr_alignb78e674217d39981dc173fc694981c59.tex b/sail_latex_riscv/fnz_get_medeleg_load_addr_alignb78e674217d39981dc173fc694981c59.tex new file mode 100644 index 00000000..f3ed40e4 --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_load_addr_alignb78e674217d39981dc173fc694981c59.tex @@ -0,0 +1 @@ +function _get_Medeleg_Load_Addr_Align v = subrange_bits(v.Medeleg_chunk_0, 4, 4) diff --git a/sail_latex_riscv/fnz_get_medeleg_load_page_faultcad65281f15a01bca2163ece7e5c6ca2.tex b/sail_latex_riscv/fnz_get_medeleg_load_page_faultcad65281f15a01bca2163ece7e5c6ca2.tex new file mode 100644 index 00000000..3cd4f4d0 --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_load_page_faultcad65281f15a01bca2163ece7e5c6ca2.tex @@ -0,0 +1 @@ +function _get_Medeleg_Load_Page_Fault v = subrange_bits(v.Medeleg_chunk_0, 13, 13) diff --git a/sail_latex_riscv/fnz_get_medeleg_menvcalla548a3bce22dd9330ba9f237e8ccd8df.tex b/sail_latex_riscv/fnz_get_medeleg_menvcalla548a3bce22dd9330ba9f237e8ccd8df.tex new file mode 100644 index 00000000..e56e466b --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_menvcalla548a3bce22dd9330ba9f237e8ccd8df.tex @@ -0,0 +1 @@ +function _get_Medeleg_MEnvCall v = subrange_bits(v.Medeleg_chunk_0, 10, 10) diff --git a/sail_latex_riscv/fnz_get_medeleg_samo_access_faultcb72d93dea2bae751976faa859f64fa9.tex b/sail_latex_riscv/fnz_get_medeleg_samo_access_faultcb72d93dea2bae751976faa859f64fa9.tex new file mode 100644 index 00000000..27c5adda --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_samo_access_faultcb72d93dea2bae751976faa859f64fa9.tex @@ -0,0 +1 @@ +function _get_Medeleg_SAMO_Access_Fault v = subrange_bits(v.Medeleg_chunk_0, 7, 7) diff --git a/sail_latex_riscv/fnz_get_medeleg_samo_addr_alignad215ca9df0deef97bdff6842d7f4cb9.tex b/sail_latex_riscv/fnz_get_medeleg_samo_addr_alignad215ca9df0deef97bdff6842d7f4cb9.tex new file mode 100644 index 00000000..5b3a5c24 --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_samo_addr_alignad215ca9df0deef97bdff6842d7f4cb9.tex @@ -0,0 +1 @@ +function _get_Medeleg_SAMO_Addr_Align v = subrange_bits(v.Medeleg_chunk_0, 6, 6) diff --git a/sail_latex_riscv/fnz_get_medeleg_samo_page_fault02d4e5d413504e150668b23d70f40d9c.tex b/sail_latex_riscv/fnz_get_medeleg_samo_page_fault02d4e5d413504e150668b23d70f40d9c.tex new file mode 100644 index 00000000..3e3a2a5a --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_samo_page_fault02d4e5d413504e150668b23d70f40d9c.tex @@ -0,0 +1 @@ +function _get_Medeleg_SAMO_Page_Fault v = subrange_bits(v.Medeleg_chunk_0, 15, 15) diff --git a/sail_latex_riscv/fnz_get_medeleg_senvcall3e8e2ef741b16b80e855ffb13f17850d.tex b/sail_latex_riscv/fnz_get_medeleg_senvcall3e8e2ef741b16b80e855ffb13f17850d.tex new file mode 100644 index 00000000..8e3d9499 --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_senvcall3e8e2ef741b16b80e855ffb13f17850d.tex @@ -0,0 +1 @@ +function _get_Medeleg_SEnvCall v = subrange_bits(v.Medeleg_chunk_0, 9, 9) diff --git a/sail_latex_riscv/fnz_get_medeleg_uenvcallc38700f20f282265abd49a682cb3711d.tex b/sail_latex_riscv/fnz_get_medeleg_uenvcallc38700f20f282265abd49a682cb3711d.tex new file mode 100644 index 00000000..4e29c7dd --- /dev/null +++ b/sail_latex_riscv/fnz_get_medeleg_uenvcallc38700f20f282265abd49a682cb3711d.tex @@ -0,0 +1 @@ +function _get_Medeleg_UEnvCall v = subrange_bits(v.Medeleg_chunk_0, 8, 8) diff --git a/sail_latex_riscv/fnz_get_minterrupts_bits9861684a481530d5524ef64aad179e28.tex b/sail_latex_riscv/fnz_get_minterrupts_bits9861684a481530d5524ef64aad179e28.tex new file mode 100644 index 00000000..e5ecc4ff --- /dev/null +++ b/sail_latex_riscv/fnz_get_minterrupts_bits9861684a481530d5524ef64aad179e28.tex @@ -0,0 +1 @@ +function _get_Minterrupts_bits v = subrange_bits(v.Minterrupts_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_minterrupts_mei515173f9dd00afe3be3a8f7e3877089a.tex b/sail_latex_riscv/fnz_get_minterrupts_mei515173f9dd00afe3be3a8f7e3877089a.tex new file mode 100644 index 00000000..6629f9b7 --- /dev/null +++ b/sail_latex_riscv/fnz_get_minterrupts_mei515173f9dd00afe3be3a8f7e3877089a.tex @@ -0,0 +1 @@ +function _get_Minterrupts_MEI v = subrange_bits(v.Minterrupts_chunk_0, 11, 11) diff --git a/sail_latex_riscv/fnz_get_minterrupts_msia5cfaf4688d1a0068789c380e6843d0e.tex b/sail_latex_riscv/fnz_get_minterrupts_msia5cfaf4688d1a0068789c380e6843d0e.tex new file mode 100644 index 00000000..8b5a9ec0 --- /dev/null +++ b/sail_latex_riscv/fnz_get_minterrupts_msia5cfaf4688d1a0068789c380e6843d0e.tex @@ -0,0 +1 @@ +function _get_Minterrupts_MSI v = subrange_bits(v.Minterrupts_chunk_0, 3, 3) diff --git a/sail_latex_riscv/fnz_get_minterrupts_mtia5225791c34b1551a9ad789bbc693091.tex b/sail_latex_riscv/fnz_get_minterrupts_mtia5225791c34b1551a9ad789bbc693091.tex new file mode 100644 index 00000000..8d7ffdd9 --- /dev/null +++ b/sail_latex_riscv/fnz_get_minterrupts_mtia5225791c34b1551a9ad789bbc693091.tex @@ -0,0 +1 @@ +function _get_Minterrupts_MTI v = subrange_bits(v.Minterrupts_chunk_0, 7, 7) diff --git a/sail_latex_riscv/fnz_get_minterrupts_sei6f52e9424a41a0158d2b56253ab8fdd9.tex b/sail_latex_riscv/fnz_get_minterrupts_sei6f52e9424a41a0158d2b56253ab8fdd9.tex new file mode 100644 index 00000000..5295f0a7 --- /dev/null +++ b/sail_latex_riscv/fnz_get_minterrupts_sei6f52e9424a41a0158d2b56253ab8fdd9.tex @@ -0,0 +1 @@ +function _get_Minterrupts_SEI v = subrange_bits(v.Minterrupts_chunk_0, 9, 9) diff --git a/sail_latex_riscv/fnz_get_minterrupts_ssi8ebb8da6cffaa81a169231cdfe86edca.tex b/sail_latex_riscv/fnz_get_minterrupts_ssi8ebb8da6cffaa81a169231cdfe86edca.tex new file mode 100644 index 00000000..5d19ad95 --- /dev/null +++ b/sail_latex_riscv/fnz_get_minterrupts_ssi8ebb8da6cffaa81a169231cdfe86edca.tex @@ -0,0 +1 @@ +function _get_Minterrupts_SSI v = subrange_bits(v.Minterrupts_chunk_0, 1, 1) diff --git a/sail_latex_riscv/fnz_get_minterrupts_stic7fb02b96430cfa9febfe409633700b7.tex b/sail_latex_riscv/fnz_get_minterrupts_stic7fb02b96430cfa9febfe409633700b7.tex new file mode 100644 index 00000000..ff75db37 --- /dev/null +++ b/sail_latex_riscv/fnz_get_minterrupts_stic7fb02b96430cfa9febfe409633700b7.tex @@ -0,0 +1 @@ +function _get_Minterrupts_STI v = subrange_bits(v.Minterrupts_chunk_0, 5, 5) diff --git a/sail_latex_riscv/fnz_get_minterrupts_uei0f43bea7cfb1473c624d84e67401f902.tex b/sail_latex_riscv/fnz_get_minterrupts_uei0f43bea7cfb1473c624d84e67401f902.tex new file mode 100644 index 00000000..a2a89798 --- /dev/null +++ b/sail_latex_riscv/fnz_get_minterrupts_uei0f43bea7cfb1473c624d84e67401f902.tex @@ -0,0 +1 @@ +function _get_Minterrupts_UEI v = subrange_bits(v.Minterrupts_chunk_0, 8, 8) diff --git a/sail_latex_riscv/fnz_get_minterrupts_usi01d28f9f2001eba94bf8de985b2cc8cd.tex b/sail_latex_riscv/fnz_get_minterrupts_usi01d28f9f2001eba94bf8de985b2cc8cd.tex new file mode 100644 index 00000000..ef6dfa9b --- /dev/null +++ b/sail_latex_riscv/fnz_get_minterrupts_usi01d28f9f2001eba94bf8de985b2cc8cd.tex @@ -0,0 +1 @@ +function _get_Minterrupts_USI v = subrange_bits(v.Minterrupts_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_minterrupts_uti7d38c0c4d8098334626461d0c0734e18.tex b/sail_latex_riscv/fnz_get_minterrupts_uti7d38c0c4d8098334626461d0c0734e18.tex new file mode 100644 index 00000000..81f0483a --- /dev/null +++ b/sail_latex_riscv/fnz_get_minterrupts_uti7d38c0c4d8098334626461d0c0734e18.tex @@ -0,0 +1 @@ +function _get_Minterrupts_UTI v = subrange_bits(v.Minterrupts_chunk_0, 4, 4) diff --git a/sail_latex_riscv/fnz_get_misa_af461bea08dc77aa785842eb918466700.tex b/sail_latex_riscv/fnz_get_misa_af461bea08dc77aa785842eb918466700.tex new file mode 100644 index 00000000..ff3afa89 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_af461bea08dc77aa785842eb918466700.tex @@ -0,0 +1 @@ +function _get_Misa_A v = subrange_bits(v.Misa_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_misa_b1d772b9d019b6aaad84ed1639e5e0d09.tex b/sail_latex_riscv/fnz_get_misa_b1d772b9d019b6aaad84ed1639e5e0d09.tex new file mode 100644 index 00000000..6de316c1 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_b1d772b9d019b6aaad84ed1639e5e0d09.tex @@ -0,0 +1 @@ +function _get_Misa_B v = subrange_bits(v.Misa_chunk_0, 1, 1) diff --git a/sail_latex_riscv/fnz_get_misa_bits227fd8e446573e270b2f6ea70e25b072.tex b/sail_latex_riscv/fnz_get_misa_bits227fd8e446573e270b2f6ea70e25b072.tex new file mode 100644 index 00000000..38f44fae --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_bits227fd8e446573e270b2f6ea70e25b072.tex @@ -0,0 +1 @@ +function _get_Misa_bits v = subrange_bits(v.Misa_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_misa_c79dc24d8a0b99e961dd504cd6b697318.tex b/sail_latex_riscv/fnz_get_misa_c79dc24d8a0b99e961dd504cd6b697318.tex new file mode 100644 index 00000000..3c576ff7 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_c79dc24d8a0b99e961dd504cd6b697318.tex @@ -0,0 +1 @@ +function _get_Misa_C v = subrange_bits(v.Misa_chunk_0, 2, 2) diff --git a/sail_latex_riscv/fnz_get_misa_d254b68e0fd6637680c01aa4da6738280.tex b/sail_latex_riscv/fnz_get_misa_d254b68e0fd6637680c01aa4da6738280.tex new file mode 100644 index 00000000..ac9960d9 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_d254b68e0fd6637680c01aa4da6738280.tex @@ -0,0 +1 @@ +function _get_Misa_D v = subrange_bits(v.Misa_chunk_0, 3, 3) diff --git a/sail_latex_riscv/fnz_get_misa_efde9ad5723fbd21ad73d9649cc491dd4.tex b/sail_latex_riscv/fnz_get_misa_efde9ad5723fbd21ad73d9649cc491dd4.tex new file mode 100644 index 00000000..c039a9fd --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_efde9ad5723fbd21ad73d9649cc491dd4.tex @@ -0,0 +1 @@ +function _get_Misa_E v = subrange_bits(v.Misa_chunk_0, 4, 4) diff --git a/sail_latex_riscv/fnz_get_misa_f684dc9ab9b0a463db4389e87dc7e784f.tex b/sail_latex_riscv/fnz_get_misa_f684dc9ab9b0a463db4389e87dc7e784f.tex new file mode 100644 index 00000000..a9d1a5e3 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_f684dc9ab9b0a463db4389e87dc7e784f.tex @@ -0,0 +1 @@ +function _get_Misa_F v = subrange_bits(v.Misa_chunk_0, 5, 5) diff --git a/sail_latex_riscv/fnz_get_misa_gcfcd286901f53880700e0bb46ee4c493.tex b/sail_latex_riscv/fnz_get_misa_gcfcd286901f53880700e0bb46ee4c493.tex new file mode 100644 index 00000000..02a0e931 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_gcfcd286901f53880700e0bb46ee4c493.tex @@ -0,0 +1 @@ +function _get_Misa_G v = subrange_bits(v.Misa_chunk_0, 6, 6) diff --git a/sail_latex_riscv/fnz_get_misa_hd877c2daaecfe719a9d7c418c493c805.tex b/sail_latex_riscv/fnz_get_misa_hd877c2daaecfe719a9d7c418c493c805.tex new file mode 100644 index 00000000..09a72749 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_hd877c2daaecfe719a9d7c418c493c805.tex @@ -0,0 +1 @@ +function _get_Misa_H v = subrange_bits(v.Misa_chunk_0, 7, 7) diff --git a/sail_latex_riscv/fnz_get_misa_ifd11140b556fe14f486f51c949a8637b.tex b/sail_latex_riscv/fnz_get_misa_ifd11140b556fe14f486f51c949a8637b.tex new file mode 100644 index 00000000..735b4ea0 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_ifd11140b556fe14f486f51c949a8637b.tex @@ -0,0 +1 @@ +function _get_Misa_I v = subrange_bits(v.Misa_chunk_0, 8, 8) diff --git a/sail_latex_riscv/fnz_get_misa_j2bd628593035d085073fabfda59a3691.tex b/sail_latex_riscv/fnz_get_misa_j2bd628593035d085073fabfda59a3691.tex new file mode 100644 index 00000000..fd60a831 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_j2bd628593035d085073fabfda59a3691.tex @@ -0,0 +1 @@ +function _get_Misa_J v = subrange_bits(v.Misa_chunk_0, 9, 9) diff --git a/sail_latex_riscv/fnz_get_misa_k16049cc76852c9c8026f567e68a54414.tex b/sail_latex_riscv/fnz_get_misa_k16049cc76852c9c8026f567e68a54414.tex new file mode 100644 index 00000000..ac393b0b --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_k16049cc76852c9c8026f567e68a54414.tex @@ -0,0 +1 @@ +function _get_Misa_K v = subrange_bits(v.Misa_chunk_0, 10, 10) diff --git a/sail_latex_riscv/fnz_get_misa_lf087e66a72a445f7b73881c1235233c0.tex b/sail_latex_riscv/fnz_get_misa_lf087e66a72a445f7b73881c1235233c0.tex new file mode 100644 index 00000000..504b0e14 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_lf087e66a72a445f7b73881c1235233c0.tex @@ -0,0 +1 @@ +function _get_Misa_L v = subrange_bits(v.Misa_chunk_0, 11, 11) diff --git a/sail_latex_riscv/fnz_get_misa_meaba66535fc1510348a6e72b1dbef759.tex b/sail_latex_riscv/fnz_get_misa_meaba66535fc1510348a6e72b1dbef759.tex new file mode 100644 index 00000000..5dcd2680 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_meaba66535fc1510348a6e72b1dbef759.tex @@ -0,0 +1 @@ +function _get_Misa_M v = subrange_bits(v.Misa_chunk_0, 12, 12) diff --git a/sail_latex_riscv/fnz_get_misa_mxl28cf17010b1a2667fba28101a95eb2ae.tex b/sail_latex_riscv/fnz_get_misa_mxl28cf17010b1a2667fba28101a95eb2ae.tex new file mode 100644 index 00000000..2a8d3e8d --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_mxl28cf17010b1a2667fba28101a95eb2ae.tex @@ -0,0 +1 @@ +function _get_Misa_MXL v = subrange_bits(v.Misa_chunk_0, 63, 62) diff --git a/sail_latex_riscv/fnz_get_misa_n58245b65aecd8d3dded8e5951d67f763.tex b/sail_latex_riscv/fnz_get_misa_n58245b65aecd8d3dded8e5951d67f763.tex new file mode 100644 index 00000000..795f96e3 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_n58245b65aecd8d3dded8e5951d67f763.tex @@ -0,0 +1 @@ +function _get_Misa_N v = subrange_bits(v.Misa_chunk_0, 13, 13) diff --git a/sail_latex_riscv/fnz_get_misa_o286d096661b36149b410863337f15d31.tex b/sail_latex_riscv/fnz_get_misa_o286d096661b36149b410863337f15d31.tex new file mode 100644 index 00000000..400458ee --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_o286d096661b36149b410863337f15d31.tex @@ -0,0 +1 @@ +function _get_Misa_O v = subrange_bits(v.Misa_chunk_0, 14, 14) diff --git a/sail_latex_riscv/fnz_get_misa_p728ca41f7e9225442cea7a2d06fda1ba.tex b/sail_latex_riscv/fnz_get_misa_p728ca41f7e9225442cea7a2d06fda1ba.tex new file mode 100644 index 00000000..a8ddb5fa --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_p728ca41f7e9225442cea7a2d06fda1ba.tex @@ -0,0 +1 @@ +function _get_Misa_P v = subrange_bits(v.Misa_chunk_0, 15, 15) diff --git a/sail_latex_riscv/fnz_get_misa_q90da1bead4ec3b742728fa054935bbc0.tex b/sail_latex_riscv/fnz_get_misa_q90da1bead4ec3b742728fa054935bbc0.tex new file mode 100644 index 00000000..5177d673 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_q90da1bead4ec3b742728fa054935bbc0.tex @@ -0,0 +1 @@ +function _get_Misa_Q v = subrange_bits(v.Misa_chunk_0, 16, 16) diff --git a/sail_latex_riscv/fnz_get_misa_rd0abea1daab407b029000fb4e1d3af0d.tex b/sail_latex_riscv/fnz_get_misa_rd0abea1daab407b029000fb4e1d3af0d.tex new file mode 100644 index 00000000..cbe42565 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_rd0abea1daab407b029000fb4e1d3af0d.tex @@ -0,0 +1 @@ +function _get_Misa_R v = subrange_bits(v.Misa_chunk_0, 17, 17) diff --git a/sail_latex_riscv/fnz_get_misa_s8d44106b93832cd46e00cba3d0fd7cc8.tex b/sail_latex_riscv/fnz_get_misa_s8d44106b93832cd46e00cba3d0fd7cc8.tex new file mode 100644 index 00000000..d089f0d6 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_s8d44106b93832cd46e00cba3d0fd7cc8.tex @@ -0,0 +1 @@ +function _get_Misa_S v = subrange_bits(v.Misa_chunk_0, 18, 18) diff --git a/sail_latex_riscv/fnz_get_misa_t964cf69481b883e83863eb9ac05b8d52.tex b/sail_latex_riscv/fnz_get_misa_t964cf69481b883e83863eb9ac05b8d52.tex new file mode 100644 index 00000000..7114fa23 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_t964cf69481b883e83863eb9ac05b8d52.tex @@ -0,0 +1 @@ +function _get_Misa_T v = subrange_bits(v.Misa_chunk_0, 19, 19) diff --git a/sail_latex_riscv/fnz_get_misa_u2220c5041e723fd883e5ca3aad46843a.tex b/sail_latex_riscv/fnz_get_misa_u2220c5041e723fd883e5ca3aad46843a.tex new file mode 100644 index 00000000..2d6cc6c6 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_u2220c5041e723fd883e5ca3aad46843a.tex @@ -0,0 +1 @@ +function _get_Misa_U v = subrange_bits(v.Misa_chunk_0, 20, 20) diff --git a/sail_latex_riscv/fnz_get_misa_v3c3bbe0f72733630524d92db60c14a02.tex b/sail_latex_riscv/fnz_get_misa_v3c3bbe0f72733630524d92db60c14a02.tex new file mode 100644 index 00000000..08b208b0 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_v3c3bbe0f72733630524d92db60c14a02.tex @@ -0,0 +1 @@ +function _get_Misa_V v = subrange_bits(v.Misa_chunk_0, 21, 21) diff --git a/sail_latex_riscv/fnz_get_misa_w4b9d3d940363386a3b964f5d156642f8.tex b/sail_latex_riscv/fnz_get_misa_w4b9d3d940363386a3b964f5d156642f8.tex new file mode 100644 index 00000000..a606c97b --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_w4b9d3d940363386a3b964f5d156642f8.tex @@ -0,0 +1 @@ +function _get_Misa_W v = subrange_bits(v.Misa_chunk_0, 22, 22) diff --git a/sail_latex_riscv/fnz_get_misa_xd43796eb311a89255d0382867f07ad38.tex b/sail_latex_riscv/fnz_get_misa_xd43796eb311a89255d0382867f07ad38.tex new file mode 100644 index 00000000..93f7e75b --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_xd43796eb311a89255d0382867f07ad38.tex @@ -0,0 +1 @@ +function _get_Misa_X v = subrange_bits(v.Misa_chunk_0, 23, 23) diff --git a/sail_latex_riscv/fnz_get_misa_ycb7d2d02e2edfcdcd44bdf6e4764863d.tex b/sail_latex_riscv/fnz_get_misa_ycb7d2d02e2edfcdcd44bdf6e4764863d.tex new file mode 100644 index 00000000..341cefd8 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_ycb7d2d02e2edfcdcd44bdf6e4764863d.tex @@ -0,0 +1 @@ +function _get_Misa_Y v = subrange_bits(v.Misa_chunk_0, 24, 24) diff --git a/sail_latex_riscv/fnz_get_misa_z0279590775f9ece96e2d9030ddcdfa1d.tex b/sail_latex_riscv/fnz_get_misa_z0279590775f9ece96e2d9030ddcdfa1d.tex new file mode 100644 index 00000000..cfcf9155 --- /dev/null +++ b/sail_latex_riscv/fnz_get_misa_z0279590775f9ece96e2d9030ddcdfa1d.tex @@ -0,0 +1 @@ +function _get_Misa_Z v = subrange_bits(v.Misa_chunk_0, 25, 25) diff --git a/sail_latex_riscv/fnz_get_mstatus_bits0aa5b9575406d172210cdde6ef45d6cd.tex b/sail_latex_riscv/fnz_get_mstatus_bits0aa5b9575406d172210cdde6ef45d6cd.tex new file mode 100644 index 00000000..c7a127fa --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_bits0aa5b9575406d172210cdde6ef45d6cd.tex @@ -0,0 +1 @@ +function _get_Mstatus_bits v = subrange_bits(v.Mstatus_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_mstatus_fs330eb17a3e05d1bdbd6f51377b6d3412.tex b/sail_latex_riscv/fnz_get_mstatus_fs330eb17a3e05d1bdbd6f51377b6d3412.tex new file mode 100644 index 00000000..49f5f0e2 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_fs330eb17a3e05d1bdbd6f51377b6d3412.tex @@ -0,0 +1 @@ +function _get_Mstatus_FS v = subrange_bits(v.Mstatus_chunk_0, 14, 13) diff --git a/sail_latex_riscv/fnz_get_mstatus_mie663746b59e574a55bd4a0897e80f3213.tex b/sail_latex_riscv/fnz_get_mstatus_mie663746b59e574a55bd4a0897e80f3213.tex new file mode 100644 index 00000000..ba765ae9 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_mie663746b59e574a55bd4a0897e80f3213.tex @@ -0,0 +1 @@ +function _get_Mstatus_MIE v = subrange_bits(v.Mstatus_chunk_0, 3, 3) diff --git a/sail_latex_riscv/fnz_get_mstatus_mpie70d0deda1607434a8f6fc4a7553fa022.tex b/sail_latex_riscv/fnz_get_mstatus_mpie70d0deda1607434a8f6fc4a7553fa022.tex new file mode 100644 index 00000000..cafd9008 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_mpie70d0deda1607434a8f6fc4a7553fa022.tex @@ -0,0 +1 @@ +function _get_Mstatus_MPIE v = subrange_bits(v.Mstatus_chunk_0, 7, 7) diff --git a/sail_latex_riscv/fnz_get_mstatus_mppaf78fafa2a77f2e77dbce07a488444bf.tex b/sail_latex_riscv/fnz_get_mstatus_mppaf78fafa2a77f2e77dbce07a488444bf.tex new file mode 100644 index 00000000..1ac5c50b --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_mppaf78fafa2a77f2e77dbce07a488444bf.tex @@ -0,0 +1 @@ +function _get_Mstatus_MPP v = subrange_bits(v.Mstatus_chunk_0, 12, 11) diff --git a/sail_latex_riscv/fnz_get_mstatus_mprv4b66922b817797bb81a3c2cdfdeff3e4.tex b/sail_latex_riscv/fnz_get_mstatus_mprv4b66922b817797bb81a3c2cdfdeff3e4.tex new file mode 100644 index 00000000..e93fd651 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_mprv4b66922b817797bb81a3c2cdfdeff3e4.tex @@ -0,0 +1 @@ +function _get_Mstatus_MPRV v = subrange_bits(v.Mstatus_chunk_0, 17, 17) diff --git a/sail_latex_riscv/fnz_get_mstatus_mxrc3cb8fda7e9db55ac7c86e5a6c05793f.tex b/sail_latex_riscv/fnz_get_mstatus_mxrc3cb8fda7e9db55ac7c86e5a6c05793f.tex new file mode 100644 index 00000000..b5ebe239 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_mxrc3cb8fda7e9db55ac7c86e5a6c05793f.tex @@ -0,0 +1 @@ +function _get_Mstatus_MXR v = subrange_bits(v.Mstatus_chunk_0, 19, 19) diff --git a/sail_latex_riscv/fnz_get_mstatus_sdd1de4e48331a465d1f6bc8b70c10db69.tex b/sail_latex_riscv/fnz_get_mstatus_sdd1de4e48331a465d1f6bc8b70c10db69.tex new file mode 100644 index 00000000..6c275a86 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_sdd1de4e48331a465d1f6bc8b70c10db69.tex @@ -0,0 +1 @@ +function _get_Mstatus_SD v = subrange_bits(v.Mstatus_chunk_0, 63, 63) diff --git a/sail_latex_riscv/fnz_get_mstatus_sied77d2cea6c4c5513b90c521245df3f40.tex b/sail_latex_riscv/fnz_get_mstatus_sied77d2cea6c4c5513b90c521245df3f40.tex new file mode 100644 index 00000000..9804b102 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_sied77d2cea6c4c5513b90c521245df3f40.tex @@ -0,0 +1 @@ +function _get_Mstatus_SIE v = subrange_bits(v.Mstatus_chunk_0, 1, 1) diff --git a/sail_latex_riscv/fnz_get_mstatus_spie13e7c8fd06a819c72ff0319a1708039d.tex b/sail_latex_riscv/fnz_get_mstatus_spie13e7c8fd06a819c72ff0319a1708039d.tex new file mode 100644 index 00000000..d196484c --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_spie13e7c8fd06a819c72ff0319a1708039d.tex @@ -0,0 +1 @@ +function _get_Mstatus_SPIE v = subrange_bits(v.Mstatus_chunk_0, 5, 5) diff --git a/sail_latex_riscv/fnz_get_mstatus_spp27a2b01ae2feb0234f716a7027839bbd.tex b/sail_latex_riscv/fnz_get_mstatus_spp27a2b01ae2feb0234f716a7027839bbd.tex new file mode 100644 index 00000000..ce1c1b19 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_spp27a2b01ae2feb0234f716a7027839bbd.tex @@ -0,0 +1 @@ +function _get_Mstatus_SPP v = subrange_bits(v.Mstatus_chunk_0, 8, 8) diff --git a/sail_latex_riscv/fnz_get_mstatus_sumdf310d1f826fe16b715b86b635711496.tex b/sail_latex_riscv/fnz_get_mstatus_sumdf310d1f826fe16b715b86b635711496.tex new file mode 100644 index 00000000..003104db --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_sumdf310d1f826fe16b715b86b635711496.tex @@ -0,0 +1 @@ +function _get_Mstatus_SUM v = subrange_bits(v.Mstatus_chunk_0, 18, 18) diff --git a/sail_latex_riscv/fnz_get_mstatus_tsr45a4c5c29b4ca69f189205bb23dbb516.tex b/sail_latex_riscv/fnz_get_mstatus_tsr45a4c5c29b4ca69f189205bb23dbb516.tex new file mode 100644 index 00000000..b8599692 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_tsr45a4c5c29b4ca69f189205bb23dbb516.tex @@ -0,0 +1 @@ +function _get_Mstatus_TSR v = subrange_bits(v.Mstatus_chunk_0, 22, 22) diff --git a/sail_latex_riscv/fnz_get_mstatus_tvm0a763585a6834af9f476c5b07d9dcce6.tex b/sail_latex_riscv/fnz_get_mstatus_tvm0a763585a6834af9f476c5b07d9dcce6.tex new file mode 100644 index 00000000..7f9f51a3 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_tvm0a763585a6834af9f476c5b07d9dcce6.tex @@ -0,0 +1 @@ +function _get_Mstatus_TVM v = subrange_bits(v.Mstatus_chunk_0, 20, 20) diff --git a/sail_latex_riscv/fnz_get_mstatus_twdd04977b0ac22974f609e5b00f1a09e9.tex b/sail_latex_riscv/fnz_get_mstatus_twdd04977b0ac22974f609e5b00f1a09e9.tex new file mode 100644 index 00000000..d8d2106d --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_twdd04977b0ac22974f609e5b00f1a09e9.tex @@ -0,0 +1 @@ +function _get_Mstatus_TW v = subrange_bits(v.Mstatus_chunk_0, 21, 21) diff --git a/sail_latex_riscv/fnz_get_mstatus_uie038bd3276e1254d44c8bafbeafa41955.tex b/sail_latex_riscv/fnz_get_mstatus_uie038bd3276e1254d44c8bafbeafa41955.tex new file mode 100644 index 00000000..e4483d84 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_uie038bd3276e1254d44c8bafbeafa41955.tex @@ -0,0 +1 @@ +function _get_Mstatus_UIE v = subrange_bits(v.Mstatus_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_mstatus_upieb1f082dfe5cc07cf43ceb1a9c5ddd9e4.tex b/sail_latex_riscv/fnz_get_mstatus_upieb1f082dfe5cc07cf43ceb1a9c5ddd9e4.tex new file mode 100644 index 00000000..abba7907 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_upieb1f082dfe5cc07cf43ceb1a9c5ddd9e4.tex @@ -0,0 +1 @@ +function _get_Mstatus_UPIE v = subrange_bits(v.Mstatus_chunk_0, 4, 4) diff --git a/sail_latex_riscv/fnz_get_mstatus_xsb541df8fdc5ba9ddaf95a2890f06b4b1.tex b/sail_latex_riscv/fnz_get_mstatus_xsb541df8fdc5ba9ddaf95a2890f06b4b1.tex new file mode 100644 index 00000000..2c221b61 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mstatus_xsb541df8fdc5ba9ddaf95a2890f06b4b1.tex @@ -0,0 +1 @@ +function _get_Mstatus_XS v = subrange_bits(v.Mstatus_chunk_0, 16, 15) diff --git a/sail_latex_riscv/fnz_get_mtvec_basefad37a1b29dd19f0e36c4f4c971339ee.tex b/sail_latex_riscv/fnz_get_mtvec_basefad37a1b29dd19f0e36c4f4c971339ee.tex new file mode 100644 index 00000000..60d58790 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mtvec_basefad37a1b29dd19f0e36c4f4c971339ee.tex @@ -0,0 +1 @@ +function _get_Mtvec_Base v = subrange_bits(v.Mtvec_chunk_0, 63, 2) diff --git a/sail_latex_riscv/fnz_get_mtvec_bitse609b5bdda2049f1b86a85566415ea34.tex b/sail_latex_riscv/fnz_get_mtvec_bitse609b5bdda2049f1b86a85566415ea34.tex new file mode 100644 index 00000000..d61252e6 --- /dev/null +++ b/sail_latex_riscv/fnz_get_mtvec_bitse609b5bdda2049f1b86a85566415ea34.tex @@ -0,0 +1 @@ +function _get_Mtvec_bits v = subrange_bits(v.Mtvec_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_mtvec_modeac4fc90b9c4014235eab8096eeec86f0.tex b/sail_latex_riscv/fnz_get_mtvec_modeac4fc90b9c4014235eab8096eeec86f0.tex new file mode 100644 index 00000000..447c743d --- /dev/null +++ b/sail_latex_riscv/fnz_get_mtvec_modeac4fc90b9c4014235eab8096eeec86f0.tex @@ -0,0 +1 @@ +function _get_Mtvec_Mode v = subrange_bits(v.Mtvec_chunk_0, 1, 0) diff --git a/sail_latex_riscv/fnz_get_pmpcfg_ent_a91770fb51fbff6c4cb08646293fdf39f.tex b/sail_latex_riscv/fnz_get_pmpcfg_ent_a91770fb51fbff6c4cb08646293fdf39f.tex new file mode 100644 index 00000000..1deae2ba --- /dev/null +++ b/sail_latex_riscv/fnz_get_pmpcfg_ent_a91770fb51fbff6c4cb08646293fdf39f.tex @@ -0,0 +1 @@ +function _get_Pmpcfg_ent_A v = subrange_bits(v.Pmpcfg_ent_chunk_0, 4, 3) diff --git a/sail_latex_riscv/fnz_get_pmpcfg_ent_bits548ab0717907b301f5b9c16399b10032.tex b/sail_latex_riscv/fnz_get_pmpcfg_ent_bits548ab0717907b301f5b9c16399b10032.tex new file mode 100644 index 00000000..049b89a2 --- /dev/null +++ b/sail_latex_riscv/fnz_get_pmpcfg_ent_bits548ab0717907b301f5b9c16399b10032.tex @@ -0,0 +1 @@ +function _get_Pmpcfg_ent_bits v = subrange_bits(v.Pmpcfg_ent_chunk_0, 7, 0) diff --git a/sail_latex_riscv/fnz_get_pmpcfg_ent_l809319223a792af7a0eb5574371df331.tex b/sail_latex_riscv/fnz_get_pmpcfg_ent_l809319223a792af7a0eb5574371df331.tex new file mode 100644 index 00000000..451c812f --- /dev/null +++ b/sail_latex_riscv/fnz_get_pmpcfg_ent_l809319223a792af7a0eb5574371df331.tex @@ -0,0 +1 @@ +function _get_Pmpcfg_ent_L v = subrange_bits(v.Pmpcfg_ent_chunk_0, 7, 7) diff --git a/sail_latex_riscv/fnz_get_pmpcfg_ent_r2cdcfc9666bd2e243c0c9c0473f345d2.tex b/sail_latex_riscv/fnz_get_pmpcfg_ent_r2cdcfc9666bd2e243c0c9c0473f345d2.tex new file mode 100644 index 00000000..05184cda --- /dev/null +++ b/sail_latex_riscv/fnz_get_pmpcfg_ent_r2cdcfc9666bd2e243c0c9c0473f345d2.tex @@ -0,0 +1 @@ +function _get_Pmpcfg_ent_R v = subrange_bits(v.Pmpcfg_ent_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_pmpcfg_ent_w9a2773642113e6c2af77db6f82354b24.tex b/sail_latex_riscv/fnz_get_pmpcfg_ent_w9a2773642113e6c2af77db6f82354b24.tex new file mode 100644 index 00000000..226f5d2f --- /dev/null +++ b/sail_latex_riscv/fnz_get_pmpcfg_ent_w9a2773642113e6c2af77db6f82354b24.tex @@ -0,0 +1 @@ +function _get_Pmpcfg_ent_W v = subrange_bits(v.Pmpcfg_ent_chunk_0, 1, 1) diff --git a/sail_latex_riscv/fnz_get_pmpcfg_ent_x7298f9632eb08a3009a272d71e240aee.tex b/sail_latex_riscv/fnz_get_pmpcfg_ent_x7298f9632eb08a3009a272d71e240aee.tex new file mode 100644 index 00000000..c041d51c --- /dev/null +++ b/sail_latex_riscv/fnz_get_pmpcfg_ent_x7298f9632eb08a3009a272d71e240aee.tex @@ -0,0 +1 @@ +function _get_Pmpcfg_ent_X v = subrange_bits(v.Pmpcfg_ent_chunk_0, 2, 2) diff --git a/sail_latex_riscv/fnz_get_pte_bits_adca5243c2ba1646df88e501938973569.tex b/sail_latex_riscv/fnz_get_pte_bits_adca5243c2ba1646df88e501938973569.tex new file mode 100644 index 00000000..44eb6ad8 --- /dev/null +++ b/sail_latex_riscv/fnz_get_pte_bits_adca5243c2ba1646df88e501938973569.tex @@ -0,0 +1 @@ +function _get_PTE_Bits_A v = subrange_bits(v.PTE_Bits_chunk_0, 6, 6) diff --git a/sail_latex_riscv/fnz_get_pte_bits_bits6cd7748e02dfe09da9dd53f24f9ac073.tex b/sail_latex_riscv/fnz_get_pte_bits_bits6cd7748e02dfe09da9dd53f24f9ac073.tex new file mode 100644 index 00000000..9a5c9577 --- /dev/null +++ b/sail_latex_riscv/fnz_get_pte_bits_bits6cd7748e02dfe09da9dd53f24f9ac073.tex @@ -0,0 +1 @@ +function _get_PTE_Bits_bits v = subrange_bits(v.PTE_Bits_chunk_0, 7, 0) diff --git a/sail_latex_riscv/fnz_get_pte_bits_d1ee6a89af287b35ae0a1cf2945b86d59.tex b/sail_latex_riscv/fnz_get_pte_bits_d1ee6a89af287b35ae0a1cf2945b86d59.tex new file mode 100644 index 00000000..2181159b --- /dev/null +++ b/sail_latex_riscv/fnz_get_pte_bits_d1ee6a89af287b35ae0a1cf2945b86d59.tex @@ -0,0 +1 @@ +function _get_PTE_Bits_D v = subrange_bits(v.PTE_Bits_chunk_0, 7, 7) diff --git a/sail_latex_riscv/fnz_get_pte_bits_g072ec08934990455850facd53f018b89.tex b/sail_latex_riscv/fnz_get_pte_bits_g072ec08934990455850facd53f018b89.tex new file mode 100644 index 00000000..832d686c --- /dev/null +++ b/sail_latex_riscv/fnz_get_pte_bits_g072ec08934990455850facd53f018b89.tex @@ -0,0 +1 @@ +function _get_PTE_Bits_G v = subrange_bits(v.PTE_Bits_chunk_0, 5, 5) diff --git a/sail_latex_riscv/fnz_get_pte_bits_r3a52c7a77cb754fb6a6eb55405de30cd.tex b/sail_latex_riscv/fnz_get_pte_bits_r3a52c7a77cb754fb6a6eb55405de30cd.tex new file mode 100644 index 00000000..77f1f5ee --- /dev/null +++ b/sail_latex_riscv/fnz_get_pte_bits_r3a52c7a77cb754fb6a6eb55405de30cd.tex @@ -0,0 +1 @@ +function _get_PTE_Bits_R v = subrange_bits(v.PTE_Bits_chunk_0, 1, 1) diff --git a/sail_latex_riscv/fnz_get_pte_bits_u300741c1239ab0c65dc451f1700b52d8.tex b/sail_latex_riscv/fnz_get_pte_bits_u300741c1239ab0c65dc451f1700b52d8.tex new file mode 100644 index 00000000..b0cf7041 --- /dev/null +++ b/sail_latex_riscv/fnz_get_pte_bits_u300741c1239ab0c65dc451f1700b52d8.tex @@ -0,0 +1 @@ +function _get_PTE_Bits_U v = subrange_bits(v.PTE_Bits_chunk_0, 4, 4) diff --git a/sail_latex_riscv/fnz_get_pte_bits_vb582fda618233a0ee7948c90600227f6.tex b/sail_latex_riscv/fnz_get_pte_bits_vb582fda618233a0ee7948c90600227f6.tex new file mode 100644 index 00000000..b1816237 --- /dev/null +++ b/sail_latex_riscv/fnz_get_pte_bits_vb582fda618233a0ee7948c90600227f6.tex @@ -0,0 +1 @@ +function _get_PTE_Bits_V v = subrange_bits(v.PTE_Bits_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_pte_bits_w1d621d1d07d6e1ee0c6cbdd6eff9e867.tex b/sail_latex_riscv/fnz_get_pte_bits_w1d621d1d07d6e1ee0c6cbdd6eff9e867.tex new file mode 100644 index 00000000..08497481 --- /dev/null +++ b/sail_latex_riscv/fnz_get_pte_bits_w1d621d1d07d6e1ee0c6cbdd6eff9e867.tex @@ -0,0 +1 @@ +function _get_PTE_Bits_W v = subrange_bits(v.PTE_Bits_chunk_0, 2, 2) diff --git a/sail_latex_riscv/fnz_get_pte_bits_x1b94d5b50779d8431b6a164038524c85.tex b/sail_latex_riscv/fnz_get_pte_bits_x1b94d5b50779d8431b6a164038524c85.tex new file mode 100644 index 00000000..4b148ff1 --- /dev/null +++ b/sail_latex_riscv/fnz_get_pte_bits_x1b94d5b50779d8431b6a164038524c85.tex @@ -0,0 +1 @@ +function _get_PTE_Bits_X v = subrange_bits(v.PTE_Bits_chunk_0, 3, 3) diff --git a/sail_latex_riscv/fnz_get_satp32_asid79b89125e014e4824b79940178c13320.tex b/sail_latex_riscv/fnz_get_satp32_asid79b89125e014e4824b79940178c13320.tex new file mode 100644 index 00000000..0db10dd3 --- /dev/null +++ b/sail_latex_riscv/fnz_get_satp32_asid79b89125e014e4824b79940178c13320.tex @@ -0,0 +1 @@ +function _get_Satp32_Asid v = subrange_bits(v.Satp32_chunk_0, 30, 22) diff --git a/sail_latex_riscv/fnz_get_satp32_bits4ef2050c8a62cb83e3a3f48d91f2a8d8.tex b/sail_latex_riscv/fnz_get_satp32_bits4ef2050c8a62cb83e3a3f48d91f2a8d8.tex new file mode 100644 index 00000000..8003ac30 --- /dev/null +++ b/sail_latex_riscv/fnz_get_satp32_bits4ef2050c8a62cb83e3a3f48d91f2a8d8.tex @@ -0,0 +1 @@ +function _get_Satp32_bits v = subrange_bits(v.Satp32_chunk_0, 31, 0) diff --git a/sail_latex_riscv/fnz_get_satp32_modeb053b6b63fe63dd46382110a8b594bfd.tex b/sail_latex_riscv/fnz_get_satp32_modeb053b6b63fe63dd46382110a8b594bfd.tex new file mode 100644 index 00000000..e49f5ac3 --- /dev/null +++ b/sail_latex_riscv/fnz_get_satp32_modeb053b6b63fe63dd46382110a8b594bfd.tex @@ -0,0 +1 @@ +function _get_Satp32_Mode v = subrange_bits(v.Satp32_chunk_0, 31, 31) diff --git a/sail_latex_riscv/fnz_get_satp32_ppn09e489a7e17eb50d41a060c4cfdf4452.tex b/sail_latex_riscv/fnz_get_satp32_ppn09e489a7e17eb50d41a060c4cfdf4452.tex new file mode 100644 index 00000000..47210e60 --- /dev/null +++ b/sail_latex_riscv/fnz_get_satp32_ppn09e489a7e17eb50d41a060c4cfdf4452.tex @@ -0,0 +1 @@ +function _get_Satp32_PPN v = subrange_bits(v.Satp32_chunk_0, 21, 0) diff --git a/sail_latex_riscv/fnz_get_satp64_asid5a55ab259b6bd85453ad8708a0fb485a.tex b/sail_latex_riscv/fnz_get_satp64_asid5a55ab259b6bd85453ad8708a0fb485a.tex new file mode 100644 index 00000000..6bf0188b --- /dev/null +++ b/sail_latex_riscv/fnz_get_satp64_asid5a55ab259b6bd85453ad8708a0fb485a.tex @@ -0,0 +1 @@ +function _get_Satp64_Asid v = subrange_bits(v.Satp64_chunk_0, 59, 44) diff --git a/sail_latex_riscv/fnz_get_satp64_bitsdb6de00ddfe8eefd1a814354aac4a548.tex b/sail_latex_riscv/fnz_get_satp64_bitsdb6de00ddfe8eefd1a814354aac4a548.tex new file mode 100644 index 00000000..b7b8cac9 --- /dev/null +++ b/sail_latex_riscv/fnz_get_satp64_bitsdb6de00ddfe8eefd1a814354aac4a548.tex @@ -0,0 +1 @@ +function _get_Satp64_bits v = subrange_bits(v.Satp64_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_satp64_mode5542c94fbfcb40171b429bef968a7954.tex b/sail_latex_riscv/fnz_get_satp64_mode5542c94fbfcb40171b429bef968a7954.tex new file mode 100644 index 00000000..21a5500d --- /dev/null +++ b/sail_latex_riscv/fnz_get_satp64_mode5542c94fbfcb40171b429bef968a7954.tex @@ -0,0 +1 @@ +function _get_Satp64_Mode v = subrange_bits(v.Satp64_chunk_0, 63, 60) diff --git a/sail_latex_riscv/fnz_get_satp64_ppn5c0b704bfa56e2113c29e0d13f46b734.tex b/sail_latex_riscv/fnz_get_satp64_ppn5c0b704bfa56e2113c29e0d13f46b734.tex new file mode 100644 index 00000000..907d4e9a --- /dev/null +++ b/sail_latex_riscv/fnz_get_satp64_ppn5c0b704bfa56e2113c29e0d13f46b734.tex @@ -0,0 +1 @@ +function _get_Satp64_PPN v = subrange_bits(v.Satp64_chunk_0, 43, 0) diff --git a/sail_latex_riscv/fnz_get_sedeleg_bitsf6b9b215e547db1e045ee7ddfb1f2f7a.tex b/sail_latex_riscv/fnz_get_sedeleg_bitsf6b9b215e547db1e045ee7ddfb1f2f7a.tex new file mode 100644 index 00000000..1bae89b0 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sedeleg_bitsf6b9b215e547db1e045ee7ddfb1f2f7a.tex @@ -0,0 +1 @@ +function _get_Sedeleg_bits v = subrange_bits(v.Sedeleg_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_sedeleg_breakpointc77d25240c231ee118b1655024dfeea6.tex b/sail_latex_riscv/fnz_get_sedeleg_breakpointc77d25240c231ee118b1655024dfeea6.tex new file mode 100644 index 00000000..bde18463 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sedeleg_breakpointc77d25240c231ee118b1655024dfeea6.tex @@ -0,0 +1 @@ +function _get_Sedeleg_Breakpoint v = subrange_bits(v.Sedeleg_chunk_0, 3, 3) diff --git a/sail_latex_riscv/fnz_get_sedeleg_fetch_access_faultf8861e3f9e14da4d59e7ab55d00a289b.tex b/sail_latex_riscv/fnz_get_sedeleg_fetch_access_faultf8861e3f9e14da4d59e7ab55d00a289b.tex new file mode 100644 index 00000000..2ac0c692 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sedeleg_fetch_access_faultf8861e3f9e14da4d59e7ab55d00a289b.tex @@ -0,0 +1 @@ +function _get_Sedeleg_Fetch_Access_Fault v = subrange_bits(v.Sedeleg_chunk_0, 1, 1) diff --git a/sail_latex_riscv/fnz_get_sedeleg_fetch_addr_alignee0f20da19f67b8d187355d5547984ca.tex b/sail_latex_riscv/fnz_get_sedeleg_fetch_addr_alignee0f20da19f67b8d187355d5547984ca.tex new file mode 100644 index 00000000..c4e50a7e --- /dev/null +++ b/sail_latex_riscv/fnz_get_sedeleg_fetch_addr_alignee0f20da19f67b8d187355d5547984ca.tex @@ -0,0 +1 @@ +function _get_Sedeleg_Fetch_Addr_Align v = subrange_bits(v.Sedeleg_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_sedeleg_illegal_instrb6d9314c6ab6f5e95202046d9dfe0756.tex b/sail_latex_riscv/fnz_get_sedeleg_illegal_instrb6d9314c6ab6f5e95202046d9dfe0756.tex new file mode 100644 index 00000000..2d7eff1d --- /dev/null +++ b/sail_latex_riscv/fnz_get_sedeleg_illegal_instrb6d9314c6ab6f5e95202046d9dfe0756.tex @@ -0,0 +1 @@ +function _get_Sedeleg_Illegal_Instr v = subrange_bits(v.Sedeleg_chunk_0, 2, 2) diff --git a/sail_latex_riscv/fnz_get_sedeleg_load_access_faultac09796aa8cbf3a86b1fed3ecd8f3c88.tex b/sail_latex_riscv/fnz_get_sedeleg_load_access_faultac09796aa8cbf3a86b1fed3ecd8f3c88.tex new file mode 100644 index 00000000..5306ea37 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sedeleg_load_access_faultac09796aa8cbf3a86b1fed3ecd8f3c88.tex @@ -0,0 +1 @@ +function _get_Sedeleg_Load_Access_Fault v = subrange_bits(v.Sedeleg_chunk_0, 5, 5) diff --git a/sail_latex_riscv/fnz_get_sedeleg_load_addr_aligna36eb31e7e82330db9574602098e9a62.tex b/sail_latex_riscv/fnz_get_sedeleg_load_addr_aligna36eb31e7e82330db9574602098e9a62.tex new file mode 100644 index 00000000..52c86af7 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sedeleg_load_addr_aligna36eb31e7e82330db9574602098e9a62.tex @@ -0,0 +1 @@ +function _get_Sedeleg_Load_Addr_Align v = subrange_bits(v.Sedeleg_chunk_0, 4, 4) diff --git a/sail_latex_riscv/fnz_get_sedeleg_samo_access_fault3592b648b74f292f7582352512f54c43.tex b/sail_latex_riscv/fnz_get_sedeleg_samo_access_fault3592b648b74f292f7582352512f54c43.tex new file mode 100644 index 00000000..75e6e48f --- /dev/null +++ b/sail_latex_riscv/fnz_get_sedeleg_samo_access_fault3592b648b74f292f7582352512f54c43.tex @@ -0,0 +1 @@ +function _get_Sedeleg_SAMO_Access_Fault v = subrange_bits(v.Sedeleg_chunk_0, 7, 7) diff --git a/sail_latex_riscv/fnz_get_sedeleg_samo_addr_align20af8fdcd584bdebc6b45b3bf763ab61.tex b/sail_latex_riscv/fnz_get_sedeleg_samo_addr_align20af8fdcd584bdebc6b45b3bf763ab61.tex new file mode 100644 index 00000000..835a87a0 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sedeleg_samo_addr_align20af8fdcd584bdebc6b45b3bf763ab61.tex @@ -0,0 +1 @@ +function _get_Sedeleg_SAMO_Addr_Align v = subrange_bits(v.Sedeleg_chunk_0, 6, 6) diff --git a/sail_latex_riscv/fnz_get_sedeleg_uenvcall9adf65053b570cbc347b25630db85fa1.tex b/sail_latex_riscv/fnz_get_sedeleg_uenvcall9adf65053b570cbc347b25630db85fa1.tex new file mode 100644 index 00000000..3cb3a295 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sedeleg_uenvcall9adf65053b570cbc347b25630db85fa1.tex @@ -0,0 +1 @@ +function _get_Sedeleg_UEnvCall v = subrange_bits(v.Sedeleg_chunk_0, 8, 8) diff --git a/sail_latex_riscv/fnz_get_sinterrupts_bits890ab2f21b741ac095ede551b06b14b0.tex b/sail_latex_riscv/fnz_get_sinterrupts_bits890ab2f21b741ac095ede551b06b14b0.tex new file mode 100644 index 00000000..586f86f1 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sinterrupts_bits890ab2f21b741ac095ede551b06b14b0.tex @@ -0,0 +1 @@ +function _get_Sinterrupts_bits v = subrange_bits(v.Sinterrupts_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_sinterrupts_sei5458488d503712b6667d489b56acd5e1.tex b/sail_latex_riscv/fnz_get_sinterrupts_sei5458488d503712b6667d489b56acd5e1.tex new file mode 100644 index 00000000..596c9aa0 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sinterrupts_sei5458488d503712b6667d489b56acd5e1.tex @@ -0,0 +1 @@ +function _get_Sinterrupts_SEI v = subrange_bits(v.Sinterrupts_chunk_0, 9, 9) diff --git a/sail_latex_riscv/fnz_get_sinterrupts_ssi240024e06c4365a8f0ed4ba1b36afb6c.tex b/sail_latex_riscv/fnz_get_sinterrupts_ssi240024e06c4365a8f0ed4ba1b36afb6c.tex new file mode 100644 index 00000000..149ecfbb --- /dev/null +++ b/sail_latex_riscv/fnz_get_sinterrupts_ssi240024e06c4365a8f0ed4ba1b36afb6c.tex @@ -0,0 +1 @@ +function _get_Sinterrupts_SSI v = subrange_bits(v.Sinterrupts_chunk_0, 1, 1) diff --git a/sail_latex_riscv/fnz_get_sinterrupts_sti9ba6390e5ddbefa9f37ab560c671354e.tex b/sail_latex_riscv/fnz_get_sinterrupts_sti9ba6390e5ddbefa9f37ab560c671354e.tex new file mode 100644 index 00000000..79a3e12d --- /dev/null +++ b/sail_latex_riscv/fnz_get_sinterrupts_sti9ba6390e5ddbefa9f37ab560c671354e.tex @@ -0,0 +1 @@ +function _get_Sinterrupts_STI v = subrange_bits(v.Sinterrupts_chunk_0, 5, 5) diff --git a/sail_latex_riscv/fnz_get_sinterrupts_uei29ec1fbe91082e4eaef04b2891fe1177.tex b/sail_latex_riscv/fnz_get_sinterrupts_uei29ec1fbe91082e4eaef04b2891fe1177.tex new file mode 100644 index 00000000..cbc27bb4 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sinterrupts_uei29ec1fbe91082e4eaef04b2891fe1177.tex @@ -0,0 +1 @@ +function _get_Sinterrupts_UEI v = subrange_bits(v.Sinterrupts_chunk_0, 8, 8) diff --git a/sail_latex_riscv/fnz_get_sinterrupts_usidbf3fbc5878b2118ded205939499c8c9.tex b/sail_latex_riscv/fnz_get_sinterrupts_usidbf3fbc5878b2118ded205939499c8c9.tex new file mode 100644 index 00000000..437f287e --- /dev/null +++ b/sail_latex_riscv/fnz_get_sinterrupts_usidbf3fbc5878b2118ded205939499c8c9.tex @@ -0,0 +1 @@ +function _get_Sinterrupts_USI v = subrange_bits(v.Sinterrupts_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_sinterrupts_utiecf1d7ffb74e287dbae46219d8f856cb.tex b/sail_latex_riscv/fnz_get_sinterrupts_utiecf1d7ffb74e287dbae46219d8f856cb.tex new file mode 100644 index 00000000..1346d72d --- /dev/null +++ b/sail_latex_riscv/fnz_get_sinterrupts_utiecf1d7ffb74e287dbae46219d8f856cb.tex @@ -0,0 +1 @@ +function _get_Sinterrupts_UTI v = subrange_bits(v.Sinterrupts_chunk_0, 4, 4) diff --git a/sail_latex_riscv/fnz_get_sstatus_bits47345191d41288d1bd8a7c67bc24ffc6.tex b/sail_latex_riscv/fnz_get_sstatus_bits47345191d41288d1bd8a7c67bc24ffc6.tex new file mode 100644 index 00000000..a53d5461 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sstatus_bits47345191d41288d1bd8a7c67bc24ffc6.tex @@ -0,0 +1 @@ +function _get_Sstatus_bits v = subrange_bits(v.Sstatus_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_sstatus_fs1460ce74aab98835a1244cb2459d0b77.tex b/sail_latex_riscv/fnz_get_sstatus_fs1460ce74aab98835a1244cb2459d0b77.tex new file mode 100644 index 00000000..248418a9 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sstatus_fs1460ce74aab98835a1244cb2459d0b77.tex @@ -0,0 +1 @@ +function _get_Sstatus_FS v = subrange_bits(v.Sstatus_chunk_0, 14, 13) diff --git a/sail_latex_riscv/fnz_get_sstatus_mxr1ed9764969d17c97d4b45acc9309595b.tex b/sail_latex_riscv/fnz_get_sstatus_mxr1ed9764969d17c97d4b45acc9309595b.tex new file mode 100644 index 00000000..5bb63fb8 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sstatus_mxr1ed9764969d17c97d4b45acc9309595b.tex @@ -0,0 +1 @@ +function _get_Sstatus_MXR v = subrange_bits(v.Sstatus_chunk_0, 19, 19) diff --git a/sail_latex_riscv/fnz_get_sstatus_sd12bb5cef6bc9eaf62712c3b06c0754ff.tex b/sail_latex_riscv/fnz_get_sstatus_sd12bb5cef6bc9eaf62712c3b06c0754ff.tex new file mode 100644 index 00000000..4dfd4dc3 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sstatus_sd12bb5cef6bc9eaf62712c3b06c0754ff.tex @@ -0,0 +1 @@ +function _get_Sstatus_SD v = subrange_bits(v.Sstatus_chunk_0, 63, 63) diff --git a/sail_latex_riscv/fnz_get_sstatus_sie9e01f0fa9797876074411f8310096e19.tex b/sail_latex_riscv/fnz_get_sstatus_sie9e01f0fa9797876074411f8310096e19.tex new file mode 100644 index 00000000..8360242b --- /dev/null +++ b/sail_latex_riscv/fnz_get_sstatus_sie9e01f0fa9797876074411f8310096e19.tex @@ -0,0 +1 @@ +function _get_Sstatus_SIE v = subrange_bits(v.Sstatus_chunk_0, 1, 1) diff --git a/sail_latex_riscv/fnz_get_sstatus_spie72f0239373389161757a30610914f136.tex b/sail_latex_riscv/fnz_get_sstatus_spie72f0239373389161757a30610914f136.tex new file mode 100644 index 00000000..4268da68 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sstatus_spie72f0239373389161757a30610914f136.tex @@ -0,0 +1 @@ +function _get_Sstatus_SPIE v = subrange_bits(v.Sstatus_chunk_0, 5, 5) diff --git a/sail_latex_riscv/fnz_get_sstatus_spp7cc37e9faad99d47707d2a3ed85339cb.tex b/sail_latex_riscv/fnz_get_sstatus_spp7cc37e9faad99d47707d2a3ed85339cb.tex new file mode 100644 index 00000000..d7a6edca --- /dev/null +++ b/sail_latex_riscv/fnz_get_sstatus_spp7cc37e9faad99d47707d2a3ed85339cb.tex @@ -0,0 +1 @@ +function _get_Sstatus_SPP v = subrange_bits(v.Sstatus_chunk_0, 8, 8) diff --git a/sail_latex_riscv/fnz_get_sstatus_sumfd7d657ad527ac995d1fbf0ded8ce3f5.tex b/sail_latex_riscv/fnz_get_sstatus_sumfd7d657ad527ac995d1fbf0ded8ce3f5.tex new file mode 100644 index 00000000..7d63202f --- /dev/null +++ b/sail_latex_riscv/fnz_get_sstatus_sumfd7d657ad527ac995d1fbf0ded8ce3f5.tex @@ -0,0 +1 @@ +function _get_Sstatus_SUM v = subrange_bits(v.Sstatus_chunk_0, 18, 18) diff --git a/sail_latex_riscv/fnz_get_sstatus_uie5a504087d59c8a2af6de9c1f7a14b612.tex b/sail_latex_riscv/fnz_get_sstatus_uie5a504087d59c8a2af6de9c1f7a14b612.tex new file mode 100644 index 00000000..e82ff128 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sstatus_uie5a504087d59c8a2af6de9c1f7a14b612.tex @@ -0,0 +1 @@ +function _get_Sstatus_UIE v = subrange_bits(v.Sstatus_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_sstatus_upie1fbaa84eb888e534ff854d4d873dff79.tex b/sail_latex_riscv/fnz_get_sstatus_upie1fbaa84eb888e534ff854d4d873dff79.tex new file mode 100644 index 00000000..f6a05203 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sstatus_upie1fbaa84eb888e534ff854d4d873dff79.tex @@ -0,0 +1 @@ +function _get_Sstatus_UPIE v = subrange_bits(v.Sstatus_chunk_0, 4, 4) diff --git a/sail_latex_riscv/fnz_get_sstatus_xs83df09eb63f5261e086c2a1e7e0f1c7a.tex b/sail_latex_riscv/fnz_get_sstatus_xs83df09eb63f5261e086c2a1e7e0f1c7a.tex new file mode 100644 index 00000000..8e6eeba4 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sstatus_xs83df09eb63f5261e086c2a1e7e0f1c7a.tex @@ -0,0 +1 @@ +function _get_Sstatus_XS v = subrange_bits(v.Sstatus_chunk_0, 16, 15) diff --git a/sail_latex_riscv/fnz_get_sv32_paddr_bitsc60ef4da8b2834c670d1e63afd2220ae.tex b/sail_latex_riscv/fnz_get_sv32_paddr_bitsc60ef4da8b2834c670d1e63afd2220ae.tex new file mode 100644 index 00000000..cc9aedfa --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv32_paddr_bitsc60ef4da8b2834c670d1e63afd2220ae.tex @@ -0,0 +1 @@ +function _get_SV32_Paddr_bits v = subrange_bits(v.SV32_Paddr_chunk_0, 33, 0) diff --git a/sail_latex_riscv/fnz_get_sv32_paddr_pgofs835ba010b40a7fd02d4a61e2ab2de4b4.tex b/sail_latex_riscv/fnz_get_sv32_paddr_pgofs835ba010b40a7fd02d4a61e2ab2de4b4.tex new file mode 100644 index 00000000..f1c20a4f --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv32_paddr_pgofs835ba010b40a7fd02d4a61e2ab2de4b4.tex @@ -0,0 +1 @@ +function _get_SV32_Paddr_PgOfs v = subrange_bits(v.SV32_Paddr_chunk_0, 11, 0) diff --git a/sail_latex_riscv/fnz_get_sv32_paddr_ppni1504c6497d4791cfe4234a5cc0365252.tex b/sail_latex_riscv/fnz_get_sv32_paddr_ppni1504c6497d4791cfe4234a5cc0365252.tex new file mode 100644 index 00000000..c1d0fb11 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv32_paddr_ppni1504c6497d4791cfe4234a5cc0365252.tex @@ -0,0 +1 @@ +function _get_SV32_Paddr_PPNi v = subrange_bits(v.SV32_Paddr_chunk_0, 33, 12) diff --git a/sail_latex_riscv/fnz_get_sv32_pte_bits184b603cf04702f500c26a3f44a95bce.tex b/sail_latex_riscv/fnz_get_sv32_pte_bits184b603cf04702f500c26a3f44a95bce.tex new file mode 100644 index 00000000..eeff7e10 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv32_pte_bits184b603cf04702f500c26a3f44a95bce.tex @@ -0,0 +1 @@ +function _get_SV32_PTE_bits v = subrange_bits(v.SV32_PTE_chunk_0, 31, 0) diff --git a/sail_latex_riscv/fnz_get_sv32_pte_bitse339fd2b2bd11b8fd6c71664018dafca.tex b/sail_latex_riscv/fnz_get_sv32_pte_bitse339fd2b2bd11b8fd6c71664018dafca.tex new file mode 100644 index 00000000..ce5464d7 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv32_pte_bitse339fd2b2bd11b8fd6c71664018dafca.tex @@ -0,0 +1 @@ +function _get_SV32_PTE_BITS v = subrange_bits(v.SV32_PTE_chunk_0, 7, 0) diff --git a/sail_latex_riscv/fnz_get_sv32_pte_ppni0d6471170f5c73c025591b74f4c1fe5e.tex b/sail_latex_riscv/fnz_get_sv32_pte_ppni0d6471170f5c73c025591b74f4c1fe5e.tex new file mode 100644 index 00000000..ccb13935 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv32_pte_ppni0d6471170f5c73c025591b74f4c1fe5e.tex @@ -0,0 +1 @@ +function _get_SV32_PTE_PPNi v = subrange_bits(v.SV32_PTE_chunk_0, 31, 10) diff --git a/sail_latex_riscv/fnz_get_sv32_pte_rswe20144b93e162ff3dff60d8ea711bcfe.tex b/sail_latex_riscv/fnz_get_sv32_pte_rswe20144b93e162ff3dff60d8ea711bcfe.tex new file mode 100644 index 00000000..319325d7 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv32_pte_rswe20144b93e162ff3dff60d8ea711bcfe.tex @@ -0,0 +1 @@ +function _get_SV32_PTE_RSW v = subrange_bits(v.SV32_PTE_chunk_0, 9, 8) diff --git a/sail_latex_riscv/fnz_get_sv32_vaddr_bits0caf929432208e7079ae87374085c96f.tex b/sail_latex_riscv/fnz_get_sv32_vaddr_bits0caf929432208e7079ae87374085c96f.tex new file mode 100644 index 00000000..210edc78 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv32_vaddr_bits0caf929432208e7079ae87374085c96f.tex @@ -0,0 +1 @@ +function _get_SV32_Vaddr_bits v = subrange_bits(v.SV32_Vaddr_chunk_0, 31, 0) diff --git a/sail_latex_riscv/fnz_get_sv32_vaddr_pgofsdbfd9837672881608e9b05eff50b2e99.tex b/sail_latex_riscv/fnz_get_sv32_vaddr_pgofsdbfd9837672881608e9b05eff50b2e99.tex new file mode 100644 index 00000000..840071d4 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv32_vaddr_pgofsdbfd9837672881608e9b05eff50b2e99.tex @@ -0,0 +1 @@ +function _get_SV32_Vaddr_PgOfs v = subrange_bits(v.SV32_Vaddr_chunk_0, 11, 0) diff --git a/sail_latex_riscv/fnz_get_sv32_vaddr_vpniab523206431fb7d5db154d45287e96ba.tex b/sail_latex_riscv/fnz_get_sv32_vaddr_vpniab523206431fb7d5db154d45287e96ba.tex new file mode 100644 index 00000000..91643768 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv32_vaddr_vpniab523206431fb7d5db154d45287e96ba.tex @@ -0,0 +1 @@ +function _get_SV32_Vaddr_VPNi v = subrange_bits(v.SV32_Vaddr_chunk_0, 31, 12) diff --git a/sail_latex_riscv/fnz_get_sv39_paddr_bits834b4f44fc6e69ffd391c9b6237cce2b.tex b/sail_latex_riscv/fnz_get_sv39_paddr_bits834b4f44fc6e69ffd391c9b6237cce2b.tex new file mode 100644 index 00000000..81c68599 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv39_paddr_bits834b4f44fc6e69ffd391c9b6237cce2b.tex @@ -0,0 +1 @@ +function _get_SV39_Paddr_bits v = subrange_bits(v.SV39_Paddr_chunk_0, 55, 0) diff --git a/sail_latex_riscv/fnz_get_sv39_paddr_pgofsb92f2e38ca030595309ba60289cfc67e.tex b/sail_latex_riscv/fnz_get_sv39_paddr_pgofsb92f2e38ca030595309ba60289cfc67e.tex new file mode 100644 index 00000000..73292e71 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv39_paddr_pgofsb92f2e38ca030595309ba60289cfc67e.tex @@ -0,0 +1 @@ +function _get_SV39_Paddr_PgOfs v = subrange_bits(v.SV39_Paddr_chunk_0, 11, 0) diff --git a/sail_latex_riscv/fnz_get_sv39_paddr_ppnie78045a960397b424c97285aca9dd29b.tex b/sail_latex_riscv/fnz_get_sv39_paddr_ppnie78045a960397b424c97285aca9dd29b.tex new file mode 100644 index 00000000..bdf8d421 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv39_paddr_ppnie78045a960397b424c97285aca9dd29b.tex @@ -0,0 +1 @@ +function _get_SV39_Paddr_PPNi v = subrange_bits(v.SV39_Paddr_chunk_0, 55, 12) diff --git a/sail_latex_riscv/fnz_get_sv39_pte_bits0a004475205374ae82c050106619c089.tex b/sail_latex_riscv/fnz_get_sv39_pte_bits0a004475205374ae82c050106619c089.tex new file mode 100644 index 00000000..4be9e0d5 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv39_pte_bits0a004475205374ae82c050106619c089.tex @@ -0,0 +1 @@ +function _get_SV39_PTE_bits v = subrange_bits(v.SV39_PTE_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_sv39_pte_bits2894d61e8f7557590f0240a44dc9dca4.tex b/sail_latex_riscv/fnz_get_sv39_pte_bits2894d61e8f7557590f0240a44dc9dca4.tex new file mode 100644 index 00000000..f83076a1 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv39_pte_bits2894d61e8f7557590f0240a44dc9dca4.tex @@ -0,0 +1 @@ +function _get_SV39_PTE_BITS v = subrange_bits(v.SV39_PTE_chunk_0, 7, 0) diff --git a/sail_latex_riscv/fnz_get_sv39_pte_ext400fef25828eab6cdcb38e7e7fd21c72.tex b/sail_latex_riscv/fnz_get_sv39_pte_ext400fef25828eab6cdcb38e7e7fd21c72.tex new file mode 100644 index 00000000..669e6169 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv39_pte_ext400fef25828eab6cdcb38e7e7fd21c72.tex @@ -0,0 +1 @@ +function _get_SV39_PTE_Ext v = subrange_bits(v.SV39_PTE_chunk_0, 63, 54) diff --git a/sail_latex_riscv/fnz_get_sv39_pte_ppni426489f4764a5d0ade3e9346a0b394c7.tex b/sail_latex_riscv/fnz_get_sv39_pte_ppni426489f4764a5d0ade3e9346a0b394c7.tex new file mode 100644 index 00000000..318f72b6 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv39_pte_ppni426489f4764a5d0ade3e9346a0b394c7.tex @@ -0,0 +1 @@ +function _get_SV39_PTE_PPNi v = subrange_bits(v.SV39_PTE_chunk_0, 53, 10) diff --git a/sail_latex_riscv/fnz_get_sv39_pte_rswb7f6ce3a77a6a7a556a5530cded759fa.tex b/sail_latex_riscv/fnz_get_sv39_pte_rswb7f6ce3a77a6a7a556a5530cded759fa.tex new file mode 100644 index 00000000..1769bb21 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv39_pte_rswb7f6ce3a77a6a7a556a5530cded759fa.tex @@ -0,0 +1 @@ +function _get_SV39_PTE_RSW v = subrange_bits(v.SV39_PTE_chunk_0, 9, 8) diff --git a/sail_latex_riscv/fnz_get_sv39_vaddr_bits364185505ec9c15373ab9c1464724954.tex b/sail_latex_riscv/fnz_get_sv39_vaddr_bits364185505ec9c15373ab9c1464724954.tex new file mode 100644 index 00000000..2815b8ee --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv39_vaddr_bits364185505ec9c15373ab9c1464724954.tex @@ -0,0 +1 @@ +function _get_SV39_Vaddr_bits v = subrange_bits(v.SV39_Vaddr_chunk_0, 38, 0) diff --git a/sail_latex_riscv/fnz_get_sv39_vaddr_pgofs4e8b61f46949b7eec961a817eeb9caf2.tex b/sail_latex_riscv/fnz_get_sv39_vaddr_pgofs4e8b61f46949b7eec961a817eeb9caf2.tex new file mode 100644 index 00000000..cb78fd4d --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv39_vaddr_pgofs4e8b61f46949b7eec961a817eeb9caf2.tex @@ -0,0 +1 @@ +function _get_SV39_Vaddr_PgOfs v = subrange_bits(v.SV39_Vaddr_chunk_0, 11, 0) diff --git a/sail_latex_riscv/fnz_get_sv39_vaddr_vpni21781895f7de6beeab4c3b9429948ba9.tex b/sail_latex_riscv/fnz_get_sv39_vaddr_vpni21781895f7de6beeab4c3b9429948ba9.tex new file mode 100644 index 00000000..a388578c --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv39_vaddr_vpni21781895f7de6beeab4c3b9429948ba9.tex @@ -0,0 +1 @@ +function _get_SV39_Vaddr_VPNi v = subrange_bits(v.SV39_Vaddr_chunk_0, 38, 12) diff --git a/sail_latex_riscv/fnz_get_sv48_paddr_bits254b25d43747ddb1b15788364bb3ff6f.tex b/sail_latex_riscv/fnz_get_sv48_paddr_bits254b25d43747ddb1b15788364bb3ff6f.tex new file mode 100644 index 00000000..ede91d69 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv48_paddr_bits254b25d43747ddb1b15788364bb3ff6f.tex @@ -0,0 +1 @@ +function _get_SV48_Paddr_bits v = subrange_bits(v.SV48_Paddr_chunk_0, 55, 0) diff --git a/sail_latex_riscv/fnz_get_sv48_paddr_pgofs7fbf559e6e9712930b86b30c8364e938.tex b/sail_latex_riscv/fnz_get_sv48_paddr_pgofs7fbf559e6e9712930b86b30c8364e938.tex new file mode 100644 index 00000000..99f3886a --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv48_paddr_pgofs7fbf559e6e9712930b86b30c8364e938.tex @@ -0,0 +1 @@ +function _get_SV48_Paddr_PgOfs v = subrange_bits(v.SV48_Paddr_chunk_0, 11, 0) diff --git a/sail_latex_riscv/fnz_get_sv48_paddr_ppni9c768f41f1a5703418c459280b46b7c6.tex b/sail_latex_riscv/fnz_get_sv48_paddr_ppni9c768f41f1a5703418c459280b46b7c6.tex new file mode 100644 index 00000000..b39a1497 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv48_paddr_ppni9c768f41f1a5703418c459280b46b7c6.tex @@ -0,0 +1 @@ +function _get_SV48_Paddr_PPNi v = subrange_bits(v.SV48_Paddr_chunk_0, 55, 12) diff --git a/sail_latex_riscv/fnz_get_sv48_pte_bits3cedec2ea70a0849ea60d8d346d0f936.tex b/sail_latex_riscv/fnz_get_sv48_pte_bits3cedec2ea70a0849ea60d8d346d0f936.tex new file mode 100644 index 00000000..301a2a39 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv48_pte_bits3cedec2ea70a0849ea60d8d346d0f936.tex @@ -0,0 +1 @@ +function _get_SV48_PTE_BITS v = subrange_bits(v.SV48_PTE_chunk_0, 7, 0) diff --git a/sail_latex_riscv/fnz_get_sv48_pte_bitsb58b3209e52ef5413579ee91bdf5b83d.tex b/sail_latex_riscv/fnz_get_sv48_pte_bitsb58b3209e52ef5413579ee91bdf5b83d.tex new file mode 100644 index 00000000..368d7f73 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv48_pte_bitsb58b3209e52ef5413579ee91bdf5b83d.tex @@ -0,0 +1 @@ +function _get_SV48_PTE_bits v = subrange_bits(v.SV48_PTE_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_sv48_pte_ext9e4ca3d27e7c17dad6458361686784bb.tex b/sail_latex_riscv/fnz_get_sv48_pte_ext9e4ca3d27e7c17dad6458361686784bb.tex new file mode 100644 index 00000000..eaa47748 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv48_pte_ext9e4ca3d27e7c17dad6458361686784bb.tex @@ -0,0 +1 @@ +function _get_SV48_PTE_Ext v = subrange_bits(v.SV48_PTE_chunk_0, 63, 54) diff --git a/sail_latex_riscv/fnz_get_sv48_pte_ppni308a2407b318a165e64cac46fe1d2d0b.tex b/sail_latex_riscv/fnz_get_sv48_pte_ppni308a2407b318a165e64cac46fe1d2d0b.tex new file mode 100644 index 00000000..c1c02de5 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv48_pte_ppni308a2407b318a165e64cac46fe1d2d0b.tex @@ -0,0 +1 @@ +function _get_SV48_PTE_PPNi v = subrange_bits(v.SV48_PTE_chunk_0, 53, 10) diff --git a/sail_latex_riscv/fnz_get_sv48_pte_rsw44e860cbd993f79b4ea9ef51b7de8885.tex b/sail_latex_riscv/fnz_get_sv48_pte_rsw44e860cbd993f79b4ea9ef51b7de8885.tex new file mode 100644 index 00000000..cb62ce4e --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv48_pte_rsw44e860cbd993f79b4ea9ef51b7de8885.tex @@ -0,0 +1 @@ +function _get_SV48_PTE_RSW v = subrange_bits(v.SV48_PTE_chunk_0, 9, 8) diff --git a/sail_latex_riscv/fnz_get_sv48_vaddr_bits2beaae5ea8854498717f33a471bb5c12.tex b/sail_latex_riscv/fnz_get_sv48_vaddr_bits2beaae5ea8854498717f33a471bb5c12.tex new file mode 100644 index 00000000..9aff6635 --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv48_vaddr_bits2beaae5ea8854498717f33a471bb5c12.tex @@ -0,0 +1 @@ +function _get_SV48_Vaddr_bits v = subrange_bits(v.SV48_Vaddr_chunk_0, 47, 0) diff --git a/sail_latex_riscv/fnz_get_sv48_vaddr_pgofsb1f1b723984e85436ebf972d3c0794b0.tex b/sail_latex_riscv/fnz_get_sv48_vaddr_pgofsb1f1b723984e85436ebf972d3c0794b0.tex new file mode 100644 index 00000000..69fefefd --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv48_vaddr_pgofsb1f1b723984e85436ebf972d3c0794b0.tex @@ -0,0 +1 @@ +function _get_SV48_Vaddr_PgOfs v = subrange_bits(v.SV48_Vaddr_chunk_0, 11, 0) diff --git a/sail_latex_riscv/fnz_get_sv48_vaddr_vpnibe8fbceb3423612d8be18c52f74da3d9.tex b/sail_latex_riscv/fnz_get_sv48_vaddr_vpnibe8fbceb3423612d8be18c52f74da3d9.tex new file mode 100644 index 00000000..18daed9f --- /dev/null +++ b/sail_latex_riscv/fnz_get_sv48_vaddr_vpnibe8fbceb3423612d8be18c52f74da3d9.tex @@ -0,0 +1 @@ +function _get_SV48_Vaddr_VPNi v = subrange_bits(v.SV48_Vaddr_chunk_0, 38, 12) diff --git a/sail_latex_riscv/fnz_get_uinterrupts_bits0b7d0f2f07976b876318898e01847c70.tex b/sail_latex_riscv/fnz_get_uinterrupts_bits0b7d0f2f07976b876318898e01847c70.tex new file mode 100644 index 00000000..519115f7 --- /dev/null +++ b/sail_latex_riscv/fnz_get_uinterrupts_bits0b7d0f2f07976b876318898e01847c70.tex @@ -0,0 +1 @@ +function _get_Uinterrupts_bits v = subrange_bits(v.Uinterrupts_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_uinterrupts_uei6c329ab1295c95ff6f49fe4076feabea.tex b/sail_latex_riscv/fnz_get_uinterrupts_uei6c329ab1295c95ff6f49fe4076feabea.tex new file mode 100644 index 00000000..0947119a --- /dev/null +++ b/sail_latex_riscv/fnz_get_uinterrupts_uei6c329ab1295c95ff6f49fe4076feabea.tex @@ -0,0 +1 @@ +function _get_Uinterrupts_UEI v = subrange_bits(v.Uinterrupts_chunk_0, 8, 8) diff --git a/sail_latex_riscv/fnz_get_uinterrupts_usi1b085056d929d854a848f905b87c060b.tex b/sail_latex_riscv/fnz_get_uinterrupts_usi1b085056d929d854a848f905b87c060b.tex new file mode 100644 index 00000000..abdac9f6 --- /dev/null +++ b/sail_latex_riscv/fnz_get_uinterrupts_usi1b085056d929d854a848f905b87c060b.tex @@ -0,0 +1 @@ +function _get_Uinterrupts_USI v = subrange_bits(v.Uinterrupts_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_uinterrupts_uti4f7a1e53cab567fa843f7436769357a0.tex b/sail_latex_riscv/fnz_get_uinterrupts_uti4f7a1e53cab567fa843f7436769357a0.tex new file mode 100644 index 00000000..ebdbafff --- /dev/null +++ b/sail_latex_riscv/fnz_get_uinterrupts_uti4f7a1e53cab567fa843f7436769357a0.tex @@ -0,0 +1 @@ +function _get_Uinterrupts_UTI v = subrange_bits(v.Uinterrupts_chunk_0, 4, 4) diff --git a/sail_latex_riscv/fnz_get_ustatus_bits230116890e8a3e29f1d043be407c7237.tex b/sail_latex_riscv/fnz_get_ustatus_bits230116890e8a3e29f1d043be407c7237.tex new file mode 100644 index 00000000..93b777f1 --- /dev/null +++ b/sail_latex_riscv/fnz_get_ustatus_bits230116890e8a3e29f1d043be407c7237.tex @@ -0,0 +1 @@ +function _get_Ustatus_bits v = subrange_bits(v.Ustatus_chunk_0, 63, 0) diff --git a/sail_latex_riscv/fnz_get_ustatus_uie443e8ee7d068af4b9b66e7cbf42dd57e.tex b/sail_latex_riscv/fnz_get_ustatus_uie443e8ee7d068af4b9b66e7cbf42dd57e.tex new file mode 100644 index 00000000..1fe8c4f3 --- /dev/null +++ b/sail_latex_riscv/fnz_get_ustatus_uie443e8ee7d068af4b9b66e7cbf42dd57e.tex @@ -0,0 +1 @@ +function _get_Ustatus_UIE v = subrange_bits(v.Ustatus_chunk_0, 0, 0) diff --git a/sail_latex_riscv/fnz_get_ustatus_upiec1c1afe6b971883383e700b3ef0f0b35.tex b/sail_latex_riscv/fnz_get_ustatus_upiec1c1afe6b971883383e700b3ef0f0b35.tex new file mode 100644 index 00000000..37536121 --- /dev/null +++ b/sail_latex_riscv/fnz_get_ustatus_upiec1c1afe6b971883383e700b3ef0f0b35.tex @@ -0,0 +1 @@ +function _get_Ustatus_UPIE v = subrange_bits(v.Ustatus_chunk_0, 4, 4) diff --git a/sail_latex_riscv/fnz_set_ccsr_bits3806e9d0f8a05e576c1382f4734c757e.tex b/sail_latex_riscv/fnz_set_ccsr_bits3806e9d0f8a05e576c1382f4734c757e.tex new file mode 100644 index 00000000..98bfc571 --- /dev/null +++ b/sail_latex_riscv/fnz_set_ccsr_bits3806e9d0f8a05e576c1382f4734c757e.tex @@ -0,0 +1,5 @@ +function _set_ccsr_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.ccsr_chunk_0 = update_subrange_bits(r.ccsr_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_ccsr_cap_idxf1dab003746059638583e08318dd0939.tex b/sail_latex_riscv/fnz_set_ccsr_cap_idxf1dab003746059638583e08318dd0939.tex new file mode 100644 index 00000000..ea000b9f --- /dev/null +++ b/sail_latex_riscv/fnz_set_ccsr_cap_idxf1dab003746059638583e08318dd0939.tex @@ -0,0 +1,5 @@ +function _set_ccsr_cap_idx (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.ccsr_chunk_0 = update_subrange_bits(r.ccsr_chunk_0, 15, 10, subrange_bits(v, 5, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_ccsr_causea61c64eff6f93cf534fa898aaa26f2b0.tex b/sail_latex_riscv/fnz_set_ccsr_causea61c64eff6f93cf534fa898aaa26f2b0.tex new file mode 100644 index 00000000..64caadbf --- /dev/null +++ b/sail_latex_riscv/fnz_set_ccsr_causea61c64eff6f93cf534fa898aaa26f2b0.tex @@ -0,0 +1,5 @@ +function _set_ccsr_cause (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.ccsr_chunk_0 = update_subrange_bits(r.ccsr_chunk_0, 9, 5, subrange_bits(v, 4, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_ccsr_db32b59142df24c8fe9016263b659269d.tex b/sail_latex_riscv/fnz_set_ccsr_db32b59142df24c8fe9016263b659269d.tex new file mode 100644 index 00000000..f3324915 --- /dev/null +++ b/sail_latex_riscv/fnz_set_ccsr_db32b59142df24c8fe9016263b659269d.tex @@ -0,0 +1,5 @@ +function _set_ccsr_d (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.ccsr_chunk_0 = update_subrange_bits(r.ccsr_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_ccsr_e1c0d679cfed0abc1454ed21db9246e96.tex b/sail_latex_riscv/fnz_set_ccsr_e1c0d679cfed0abc1454ed21db9246e96.tex new file mode 100644 index 00000000..160e2ce3 --- /dev/null +++ b/sail_latex_riscv/fnz_set_ccsr_e1c0d679cfed0abc1454ed21db9246e96.tex @@ -0,0 +1,5 @@ +function _set_ccsr_e (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.ccsr_chunk_0 = update_subrange_bits(r.ccsr_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_counteren_bits645facfec852be9a4b81ed364e1460c2.tex b/sail_latex_riscv/fnz_set_counteren_bits645facfec852be9a4b81ed364e1460c2.tex new file mode 100644 index 00000000..7c600906 --- /dev/null +++ b/sail_latex_riscv/fnz_set_counteren_bits645facfec852be9a4b81ed364e1460c2.tex @@ -0,0 +1,5 @@ +function _set_Counteren_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Counteren_chunk_0 = update_subrange_bits(r.Counteren_chunk_0, 31, 0, subrange_bits(v, 31, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_counteren_cy596db6893acf37ac3bd153f29c01a4f5.tex b/sail_latex_riscv/fnz_set_counteren_cy596db6893acf37ac3bd153f29c01a4f5.tex new file mode 100644 index 00000000..055a6cd5 --- /dev/null +++ b/sail_latex_riscv/fnz_set_counteren_cy596db6893acf37ac3bd153f29c01a4f5.tex @@ -0,0 +1,5 @@ +function _set_Counteren_CY (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Counteren_chunk_0 = update_subrange_bits(r.Counteren_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_counteren_hpme0b60e00eab80a2934fe853d7cc21c79.tex b/sail_latex_riscv/fnz_set_counteren_hpme0b60e00eab80a2934fe853d7cc21c79.tex new file mode 100644 index 00000000..5d707d05 --- /dev/null +++ b/sail_latex_riscv/fnz_set_counteren_hpme0b60e00eab80a2934fe853d7cc21c79.tex @@ -0,0 +1,5 @@ +function _set_Counteren_HPM (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Counteren_chunk_0 = update_subrange_bits(r.Counteren_chunk_0, 31, 3, subrange_bits(v, 28, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_counteren_irc2c31e7ff83f5b56636c924d61b260d2.tex b/sail_latex_riscv/fnz_set_counteren_irc2c31e7ff83f5b56636c924d61b260d2.tex new file mode 100644 index 00000000..57f3aa0b --- /dev/null +++ b/sail_latex_riscv/fnz_set_counteren_irc2c31e7ff83f5b56636c924d61b260d2.tex @@ -0,0 +1,5 @@ +function _set_Counteren_IR (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Counteren_chunk_0 = update_subrange_bits(r.Counteren_chunk_0, 2, 2, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_counteren_tmed5ea23cd819bd09590e67c1c76777b7.tex b/sail_latex_riscv/fnz_set_counteren_tmed5ea23cd819bd09590e67c1c76777b7.tex new file mode 100644 index 00000000..a4dcc481 --- /dev/null +++ b/sail_latex_riscv/fnz_set_counteren_tmed5ea23cd819bd09590e67c1c76777b7.tex @@ -0,0 +1,5 @@ +function _set_Counteren_TM (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Counteren_chunk_0 = update_subrange_bits(r.Counteren_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_counterin_bits4d906fc122c4b0829e669029457bff46.tex b/sail_latex_riscv/fnz_set_counterin_bits4d906fc122c4b0829e669029457bff46.tex new file mode 100644 index 00000000..fba09db6 --- /dev/null +++ b/sail_latex_riscv/fnz_set_counterin_bits4d906fc122c4b0829e669029457bff46.tex @@ -0,0 +1,5 @@ +function _set_Counterin_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Counterin_chunk_0 = update_subrange_bits(r.Counterin_chunk_0, 31, 0, subrange_bits(v, 31, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_counterin_cy2ee6f977ede334731ad36d7afe6e2be4.tex b/sail_latex_riscv/fnz_set_counterin_cy2ee6f977ede334731ad36d7afe6e2be4.tex new file mode 100644 index 00000000..61431a6f --- /dev/null +++ b/sail_latex_riscv/fnz_set_counterin_cy2ee6f977ede334731ad36d7afe6e2be4.tex @@ -0,0 +1,5 @@ +function _set_Counterin_CY (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Counterin_chunk_0 = update_subrange_bits(r.Counterin_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_counterin_ir7435617becd3df612dd905733de79ab0.tex b/sail_latex_riscv/fnz_set_counterin_ir7435617becd3df612dd905733de79ab0.tex new file mode 100644 index 00000000..7fc624e5 --- /dev/null +++ b/sail_latex_riscv/fnz_set_counterin_ir7435617becd3df612dd905733de79ab0.tex @@ -0,0 +1,5 @@ +function _set_Counterin_IR (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Counterin_chunk_0 = update_subrange_bits(r.Counterin_chunk_0, 2, 2, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_ext_pte_bits_bitsa761c9ca2c6e788009a6f80b588af6be.tex b/sail_latex_riscv/fnz_set_ext_pte_bits_bitsa761c9ca2c6e788009a6f80b588af6be.tex new file mode 100644 index 00000000..939c8f68 --- /dev/null +++ b/sail_latex_riscv/fnz_set_ext_pte_bits_bitsa761c9ca2c6e788009a6f80b588af6be.tex @@ -0,0 +1,5 @@ +function _set_Ext_PTE_Bits_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Ext_PTE_Bits_chunk_0 = update_subrange_bits(r.Ext_PTE_Bits_chunk_0, 9, 0, subrange_bits(v, 9, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_ext_pte_bits_capreadfba293dd04ef2251e165147b0523320d.tex b/sail_latex_riscv/fnz_set_ext_pte_bits_capreadfba293dd04ef2251e165147b0523320d.tex new file mode 100644 index 00000000..c794eb0e --- /dev/null +++ b/sail_latex_riscv/fnz_set_ext_pte_bits_capreadfba293dd04ef2251e165147b0523320d.tex @@ -0,0 +1,5 @@ +function _set_Ext_PTE_Bits_CapRead (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Ext_PTE_Bits_chunk_0 = update_subrange_bits(r.Ext_PTE_Bits_chunk_0, 8, 8, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_ext_pte_bits_capwriteccb693fb16cf80f8b094a130c168d1f7.tex b/sail_latex_riscv/fnz_set_ext_pte_bits_capwriteccb693fb16cf80f8b094a130c168d1f7.tex new file mode 100644 index 00000000..a4b8a843 --- /dev/null +++ b/sail_latex_riscv/fnz_set_ext_pte_bits_capwriteccb693fb16cf80f8b094a130c168d1f7.tex @@ -0,0 +1,5 @@ +function _set_Ext_PTE_Bits_CapWrite (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Ext_PTE_Bits_chunk_0 = update_subrange_bits(r.Ext_PTE_Bits_chunk_0, 9, 9, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_fcsr_bits14808d6e9585f49863a62ef97cfccc18.tex b/sail_latex_riscv/fnz_set_fcsr_bits14808d6e9585f49863a62ef97cfccc18.tex new file mode 100644 index 00000000..2430129b --- /dev/null +++ b/sail_latex_riscv/fnz_set_fcsr_bits14808d6e9585f49863a62ef97cfccc18.tex @@ -0,0 +1,5 @@ +function _set_Fcsr_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Fcsr_chunk_0 = update_subrange_bits(r.Fcsr_chunk_0, 31, 0, subrange_bits(v, 31, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_fcsr_fflagsd8192cedf9e30718ca38134692e797b3.tex b/sail_latex_riscv/fnz_set_fcsr_fflagsd8192cedf9e30718ca38134692e797b3.tex new file mode 100644 index 00000000..d23e9367 --- /dev/null +++ b/sail_latex_riscv/fnz_set_fcsr_fflagsd8192cedf9e30718ca38134692e797b3.tex @@ -0,0 +1,5 @@ +function _set_Fcsr_FFLAGS (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Fcsr_chunk_0 = update_subrange_bits(r.Fcsr_chunk_0, 4, 0, subrange_bits(v, 4, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_fcsr_frmadaccc6e48224bd13dc49815c7dca973.tex b/sail_latex_riscv/fnz_set_fcsr_frmadaccc6e48224bd13dc49815c7dca973.tex new file mode 100644 index 00000000..1500ae84 --- /dev/null +++ b/sail_latex_riscv/fnz_set_fcsr_frmadaccc6e48224bd13dc49815c7dca973.tex @@ -0,0 +1,5 @@ +function _set_Fcsr_FRM (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Fcsr_chunk_0 = update_subrange_bits(r.Fcsr_chunk_0, 7, 5, subrange_bits(v, 2, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_htif_cmd_bits689a1226135e157ab73f85b4e32f7b0e.tex b/sail_latex_riscv/fnz_set_htif_cmd_bits689a1226135e157ab73f85b4e32f7b0e.tex new file mode 100644 index 00000000..3110afb5 --- /dev/null +++ b/sail_latex_riscv/fnz_set_htif_cmd_bits689a1226135e157ab73f85b4e32f7b0e.tex @@ -0,0 +1,5 @@ +function _set_htif_cmd_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.htif_cmd_chunk_0 = update_subrange_bits(r.htif_cmd_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_htif_cmd_cmd0433aa4c5b2a4721f8f44a87e408d238.tex b/sail_latex_riscv/fnz_set_htif_cmd_cmd0433aa4c5b2a4721f8f44a87e408d238.tex new file mode 100644 index 00000000..bc9ab0ec --- /dev/null +++ b/sail_latex_riscv/fnz_set_htif_cmd_cmd0433aa4c5b2a4721f8f44a87e408d238.tex @@ -0,0 +1,5 @@ +function _set_htif_cmd_cmd (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.htif_cmd_chunk_0 = update_subrange_bits(r.htif_cmd_chunk_0, 55, 48, subrange_bits(v, 7, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_htif_cmd_deviceca3d219cd020878f1e936d65dadd246c.tex b/sail_latex_riscv/fnz_set_htif_cmd_deviceca3d219cd020878f1e936d65dadd246c.tex new file mode 100644 index 00000000..6667bc63 --- /dev/null +++ b/sail_latex_riscv/fnz_set_htif_cmd_deviceca3d219cd020878f1e936d65dadd246c.tex @@ -0,0 +1,5 @@ +function _set_htif_cmd_device (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.htif_cmd_chunk_0 = update_subrange_bits(r.htif_cmd_chunk_0, 63, 56, subrange_bits(v, 7, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_htif_cmd_payload54f16ea011075a1e7c5afa0c27e684a6.tex b/sail_latex_riscv/fnz_set_htif_cmd_payload54f16ea011075a1e7c5afa0c27e684a6.tex new file mode 100644 index 00000000..76aa5052 --- /dev/null +++ b/sail_latex_riscv/fnz_set_htif_cmd_payload54f16ea011075a1e7c5afa0c27e684a6.tex @@ -0,0 +1,5 @@ +function _set_htif_cmd_payload (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.htif_cmd_chunk_0 = update_subrange_bits(r.htif_cmd_chunk_0, 47, 0, subrange_bits(v, 47, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mcause_bits80b6d4b61ba8cd659ac54309cbdb9ea7.tex b/sail_latex_riscv/fnz_set_mcause_bits80b6d4b61ba8cd659ac54309cbdb9ea7.tex new file mode 100644 index 00000000..6326a83d --- /dev/null +++ b/sail_latex_riscv/fnz_set_mcause_bits80b6d4b61ba8cd659ac54309cbdb9ea7.tex @@ -0,0 +1,5 @@ +function _set_Mcause_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mcause_chunk_0 = update_subrange_bits(r.Mcause_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mcause_causecce7178eb6a826303b904fd987904cff.tex b/sail_latex_riscv/fnz_set_mcause_causecce7178eb6a826303b904fd987904cff.tex new file mode 100644 index 00000000..98d33ace --- /dev/null +++ b/sail_latex_riscv/fnz_set_mcause_causecce7178eb6a826303b904fd987904cff.tex @@ -0,0 +1,5 @@ +function _set_Mcause_Cause (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mcause_chunk_0 = update_subrange_bits(r.Mcause_chunk_0, 62, 0, subrange_bits(v, 62, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mcause_isinterrupt6acecb43461e553536ef76a71d78c3e7.tex b/sail_latex_riscv/fnz_set_mcause_isinterrupt6acecb43461e553536ef76a71d78c3e7.tex new file mode 100644 index 00000000..ae4af249 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mcause_isinterrupt6acecb43461e553536ef76a71d78c3e7.tex @@ -0,0 +1,5 @@ +function _set_Mcause_IsInterrupt (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mcause_chunk_0 = update_subrange_bits(r.Mcause_chunk_0, 63, 63, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_bitsa5164a346cdd02dcec13d6e5c2839918.tex b/sail_latex_riscv/fnz_set_medeleg_bitsa5164a346cdd02dcec13d6e5c2839918.tex new file mode 100644 index 00000000..61345196 --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_bitsa5164a346cdd02dcec13d6e5c2839918.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_breakpoint65522090d2dce601562eb82bb71ebd27.tex b/sail_latex_riscv/fnz_set_medeleg_breakpoint65522090d2dce601562eb82bb71ebd27.tex new file mode 100644 index 00000000..973411d8 --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_breakpoint65522090d2dce601562eb82bb71ebd27.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_Breakpoint (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 3, 3, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_fetch_access_fault8b3d91a41393ae3c76d0df3e801928e9.tex b/sail_latex_riscv/fnz_set_medeleg_fetch_access_fault8b3d91a41393ae3c76d0df3e801928e9.tex new file mode 100644 index 00000000..b4af8637 --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_fetch_access_fault8b3d91a41393ae3c76d0df3e801928e9.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_Fetch_Access_Fault (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_fetch_addr_align514673a27e7f896be9dea81dc7662148.tex b/sail_latex_riscv/fnz_set_medeleg_fetch_addr_align514673a27e7f896be9dea81dc7662148.tex new file mode 100644 index 00000000..e409c2aa --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_fetch_addr_align514673a27e7f896be9dea81dc7662148.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_Fetch_Addr_Align (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_fetch_page_faultefe8fe08b8ed5f78322e6a4864364068.tex b/sail_latex_riscv/fnz_set_medeleg_fetch_page_faultefe8fe08b8ed5f78322e6a4864364068.tex new file mode 100644 index 00000000..177942ae --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_fetch_page_faultefe8fe08b8ed5f78322e6a4864364068.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_Fetch_Page_Fault (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 12, 12, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_illegal_instr0ddff62c362ec255b511a781fc6e9551.tex b/sail_latex_riscv/fnz_set_medeleg_illegal_instr0ddff62c362ec255b511a781fc6e9551.tex new file mode 100644 index 00000000..2c7a864b --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_illegal_instr0ddff62c362ec255b511a781fc6e9551.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_Illegal_Instr (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 2, 2, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_load_access_fault6e32b99197543196d68c443430ddcd76.tex b/sail_latex_riscv/fnz_set_medeleg_load_access_fault6e32b99197543196d68c443430ddcd76.tex new file mode 100644 index 00000000..ff5fde8c --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_load_access_fault6e32b99197543196d68c443430ddcd76.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_Load_Access_Fault (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 5, 5, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_load_addr_align477e12d39eacad577451a2c4ce6c5028.tex b/sail_latex_riscv/fnz_set_medeleg_load_addr_align477e12d39eacad577451a2c4ce6c5028.tex new file mode 100644 index 00000000..186d05c2 --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_load_addr_align477e12d39eacad577451a2c4ce6c5028.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_Load_Addr_Align (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 4, 4, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_load_page_fault9d4748d81d2b444605a3e9cebc4943d7.tex b/sail_latex_riscv/fnz_set_medeleg_load_page_fault9d4748d81d2b444605a3e9cebc4943d7.tex new file mode 100644 index 00000000..f0e0d3ef --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_load_page_fault9d4748d81d2b444605a3e9cebc4943d7.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_Load_Page_Fault (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 13, 13, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_menvcall1e30100a01455a75d7aaa14d1ba8b171.tex b/sail_latex_riscv/fnz_set_medeleg_menvcall1e30100a01455a75d7aaa14d1ba8b171.tex new file mode 100644 index 00000000..f6a4e462 --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_menvcall1e30100a01455a75d7aaa14d1ba8b171.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_MEnvCall (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 10, 10, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_samo_access_fault1dfec566f185ab6cce1059f544290cf1.tex b/sail_latex_riscv/fnz_set_medeleg_samo_access_fault1dfec566f185ab6cce1059f544290cf1.tex new file mode 100644 index 00000000..cb65406e --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_samo_access_fault1dfec566f185ab6cce1059f544290cf1.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_SAMO_Access_Fault (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 7, 7, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_samo_addr_align00c5e4839832dee86f8bfd26cc3f2a80.tex b/sail_latex_riscv/fnz_set_medeleg_samo_addr_align00c5e4839832dee86f8bfd26cc3f2a80.tex new file mode 100644 index 00000000..7d2f435f --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_samo_addr_align00c5e4839832dee86f8bfd26cc3f2a80.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_SAMO_Addr_Align (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 6, 6, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_samo_page_fault3b09cdf77cb2b2817f7c0f833cc758ce.tex b/sail_latex_riscv/fnz_set_medeleg_samo_page_fault3b09cdf77cb2b2817f7c0f833cc758ce.tex new file mode 100644 index 00000000..0f8d96c3 --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_samo_page_fault3b09cdf77cb2b2817f7c0f833cc758ce.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_SAMO_Page_Fault (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 15, 15, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_senvcall9eab904bcf0e2130341264216cb52176.tex b/sail_latex_riscv/fnz_set_medeleg_senvcall9eab904bcf0e2130341264216cb52176.tex new file mode 100644 index 00000000..2293e1c5 --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_senvcall9eab904bcf0e2130341264216cb52176.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_SEnvCall (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 9, 9, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_medeleg_uenvcallb8f205a15af52cac02b9bb0657a52d33.tex b/sail_latex_riscv/fnz_set_medeleg_uenvcallb8f205a15af52cac02b9bb0657a52d33.tex new file mode 100644 index 00000000..388a9316 --- /dev/null +++ b/sail_latex_riscv/fnz_set_medeleg_uenvcallb8f205a15af52cac02b9bb0657a52d33.tex @@ -0,0 +1,5 @@ +function _set_Medeleg_UEnvCall (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Medeleg_chunk_0 = update_subrange_bits(r.Medeleg_chunk_0, 8, 8, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_minterrupts_bits33c9485121287572c28dfb5038fc3d62.tex b/sail_latex_riscv/fnz_set_minterrupts_bits33c9485121287572c28dfb5038fc3d62.tex new file mode 100644 index 00000000..42b04a2c --- /dev/null +++ b/sail_latex_riscv/fnz_set_minterrupts_bits33c9485121287572c28dfb5038fc3d62.tex @@ -0,0 +1,5 @@ +function _set_Minterrupts_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Minterrupts_chunk_0 = update_subrange_bits(r.Minterrupts_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_minterrupts_mei9744cce951b17c7e2932ca8ace0338c4.tex b/sail_latex_riscv/fnz_set_minterrupts_mei9744cce951b17c7e2932ca8ace0338c4.tex new file mode 100644 index 00000000..e5a6dea7 --- /dev/null +++ b/sail_latex_riscv/fnz_set_minterrupts_mei9744cce951b17c7e2932ca8ace0338c4.tex @@ -0,0 +1,5 @@ +function _set_Minterrupts_MEI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Minterrupts_chunk_0 = update_subrange_bits(r.Minterrupts_chunk_0, 11, 11, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_minterrupts_msi2f29aeb62fd44e400e4d6811ee58eff4.tex b/sail_latex_riscv/fnz_set_minterrupts_msi2f29aeb62fd44e400e4d6811ee58eff4.tex new file mode 100644 index 00000000..649c5c2e --- /dev/null +++ b/sail_latex_riscv/fnz_set_minterrupts_msi2f29aeb62fd44e400e4d6811ee58eff4.tex @@ -0,0 +1,5 @@ +function _set_Minterrupts_MSI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Minterrupts_chunk_0 = update_subrange_bits(r.Minterrupts_chunk_0, 3, 3, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_minterrupts_mtia7bb5032baba4531a4c7bb5fe29eed89.tex b/sail_latex_riscv/fnz_set_minterrupts_mtia7bb5032baba4531a4c7bb5fe29eed89.tex new file mode 100644 index 00000000..3a89e39e --- /dev/null +++ b/sail_latex_riscv/fnz_set_minterrupts_mtia7bb5032baba4531a4c7bb5fe29eed89.tex @@ -0,0 +1,5 @@ +function _set_Minterrupts_MTI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Minterrupts_chunk_0 = update_subrange_bits(r.Minterrupts_chunk_0, 7, 7, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_minterrupts_seied3b72a76b0168176b36aa09bb08b409.tex b/sail_latex_riscv/fnz_set_minterrupts_seied3b72a76b0168176b36aa09bb08b409.tex new file mode 100644 index 00000000..d68f8ee9 --- /dev/null +++ b/sail_latex_riscv/fnz_set_minterrupts_seied3b72a76b0168176b36aa09bb08b409.tex @@ -0,0 +1,5 @@ +function _set_Minterrupts_SEI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Minterrupts_chunk_0 = update_subrange_bits(r.Minterrupts_chunk_0, 9, 9, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_minterrupts_ssi862fdaa740d3553d0b00abbad005b654.tex b/sail_latex_riscv/fnz_set_minterrupts_ssi862fdaa740d3553d0b00abbad005b654.tex new file mode 100644 index 00000000..39bd8cbb --- /dev/null +++ b/sail_latex_riscv/fnz_set_minterrupts_ssi862fdaa740d3553d0b00abbad005b654.tex @@ -0,0 +1,5 @@ +function _set_Minterrupts_SSI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Minterrupts_chunk_0 = update_subrange_bits(r.Minterrupts_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_minterrupts_sti916655477209971ff8cdb58c26f6ef93.tex b/sail_latex_riscv/fnz_set_minterrupts_sti916655477209971ff8cdb58c26f6ef93.tex new file mode 100644 index 00000000..f87cc5af --- /dev/null +++ b/sail_latex_riscv/fnz_set_minterrupts_sti916655477209971ff8cdb58c26f6ef93.tex @@ -0,0 +1,5 @@ +function _set_Minterrupts_STI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Minterrupts_chunk_0 = update_subrange_bits(r.Minterrupts_chunk_0, 5, 5, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_minterrupts_uei094ebc68e14480c18355d8aa2f610f29.tex b/sail_latex_riscv/fnz_set_minterrupts_uei094ebc68e14480c18355d8aa2f610f29.tex new file mode 100644 index 00000000..8d68e42f --- /dev/null +++ b/sail_latex_riscv/fnz_set_minterrupts_uei094ebc68e14480c18355d8aa2f610f29.tex @@ -0,0 +1,5 @@ +function _set_Minterrupts_UEI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Minterrupts_chunk_0 = update_subrange_bits(r.Minterrupts_chunk_0, 8, 8, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_minterrupts_usi073c76e1d0b95c4329e14eefe61bddb2.tex b/sail_latex_riscv/fnz_set_minterrupts_usi073c76e1d0b95c4329e14eefe61bddb2.tex new file mode 100644 index 00000000..28b9d81f --- /dev/null +++ b/sail_latex_riscv/fnz_set_minterrupts_usi073c76e1d0b95c4329e14eefe61bddb2.tex @@ -0,0 +1,5 @@ +function _set_Minterrupts_USI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Minterrupts_chunk_0 = update_subrange_bits(r.Minterrupts_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_minterrupts_utid09c8a6e5f537755c8564dc71a61f188.tex b/sail_latex_riscv/fnz_set_minterrupts_utid09c8a6e5f537755c8564dc71a61f188.tex new file mode 100644 index 00000000..99712092 --- /dev/null +++ b/sail_latex_riscv/fnz_set_minterrupts_utid09c8a6e5f537755c8564dc71a61f188.tex @@ -0,0 +1,5 @@ +function _set_Minterrupts_UTI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Minterrupts_chunk_0 = update_subrange_bits(r.Minterrupts_chunk_0, 4, 4, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_af2a884db4759788724edc2e8603b8be4.tex b/sail_latex_riscv/fnz_set_misa_af2a884db4759788724edc2e8603b8be4.tex new file mode 100644 index 00000000..b86a0099 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_af2a884db4759788724edc2e8603b8be4.tex @@ -0,0 +1,5 @@ +function _set_Misa_A (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_b0a197892362ef80b92b24e457a36fe2e.tex b/sail_latex_riscv/fnz_set_misa_b0a197892362ef80b92b24e457a36fe2e.tex new file mode 100644 index 00000000..3dba60fd --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_b0a197892362ef80b92b24e457a36fe2e.tex @@ -0,0 +1,5 @@ +function _set_Misa_B (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_bits8a8c7777988f3569033d87950ad2055d.tex b/sail_latex_riscv/fnz_set_misa_bits8a8c7777988f3569033d87950ad2055d.tex new file mode 100644 index 00000000..d85bd4fe --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_bits8a8c7777988f3569033d87950ad2055d.tex @@ -0,0 +1,5 @@ +function _set_Misa_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_cdd88b98e41a5e410ecf7b2bf6be19aa8.tex b/sail_latex_riscv/fnz_set_misa_cdd88b98e41a5e410ecf7b2bf6be19aa8.tex new file mode 100644 index 00000000..bcbf6e37 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_cdd88b98e41a5e410ecf7b2bf6be19aa8.tex @@ -0,0 +1,5 @@ +function _set_Misa_C (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 2, 2, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_dc53b7d60ef59832cce8ea7080073ac39.tex b/sail_latex_riscv/fnz_set_misa_dc53b7d60ef59832cce8ea7080073ac39.tex new file mode 100644 index 00000000..af09ba8e --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_dc53b7d60ef59832cce8ea7080073ac39.tex @@ -0,0 +1,5 @@ +function _set_Misa_D (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 3, 3, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_e36282592c3981fb3312fd0b0b03227bd.tex b/sail_latex_riscv/fnz_set_misa_e36282592c3981fb3312fd0b0b03227bd.tex new file mode 100644 index 00000000..bd6e48d4 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_e36282592c3981fb3312fd0b0b03227bd.tex @@ -0,0 +1,5 @@ +function _set_Misa_E (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 4, 4, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_f8c698083198450c6a61ec00abe038c08.tex b/sail_latex_riscv/fnz_set_misa_f8c698083198450c6a61ec00abe038c08.tex new file mode 100644 index 00000000..d5783a46 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_f8c698083198450c6a61ec00abe038c08.tex @@ -0,0 +1,5 @@ +function _set_Misa_F (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 5, 5, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_g7e6256e7a4ea213c35876542280b8601.tex b/sail_latex_riscv/fnz_set_misa_g7e6256e7a4ea213c35876542280b8601.tex new file mode 100644 index 00000000..d7ef50d5 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_g7e6256e7a4ea213c35876542280b8601.tex @@ -0,0 +1,5 @@ +function _set_Misa_G (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 6, 6, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_h7a13933c5ad288a885bba1ccd7aa1003.tex b/sail_latex_riscv/fnz_set_misa_h7a13933c5ad288a885bba1ccd7aa1003.tex new file mode 100644 index 00000000..c7a84d6f --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_h7a13933c5ad288a885bba1ccd7aa1003.tex @@ -0,0 +1,5 @@ +function _set_Misa_H (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 7, 7, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_i459bf00eda120c5909e07545e00c48c1.tex b/sail_latex_riscv/fnz_set_misa_i459bf00eda120c5909e07545e00c48c1.tex new file mode 100644 index 00000000..c02c515d --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_i459bf00eda120c5909e07545e00c48c1.tex @@ -0,0 +1,5 @@ +function _set_Misa_I (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 8, 8, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_jf62a4ffaf2eeedcd5ec20654000caf02.tex b/sail_latex_riscv/fnz_set_misa_jf62a4ffaf2eeedcd5ec20654000caf02.tex new file mode 100644 index 00000000..cf3942e7 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_jf62a4ffaf2eeedcd5ec20654000caf02.tex @@ -0,0 +1,5 @@ +function _set_Misa_J (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 9, 9, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_k32d9915ba6161247dfa2e07599b14f05.tex b/sail_latex_riscv/fnz_set_misa_k32d9915ba6161247dfa2e07599b14f05.tex new file mode 100644 index 00000000..18f9cda0 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_k32d9915ba6161247dfa2e07599b14f05.tex @@ -0,0 +1,5 @@ +function _set_Misa_K (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 10, 10, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_lce522273afcdcceb0fff20729aec4ac4.tex b/sail_latex_riscv/fnz_set_misa_lce522273afcdcceb0fff20729aec4ac4.tex new file mode 100644 index 00000000..1cae05d8 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_lce522273afcdcceb0fff20729aec4ac4.tex @@ -0,0 +1,5 @@ +function _set_Misa_L (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 11, 11, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_m9fc1a0ff196728bb0dbae698e2e8a7e9.tex b/sail_latex_riscv/fnz_set_misa_m9fc1a0ff196728bb0dbae698e2e8a7e9.tex new file mode 100644 index 00000000..170fc5a2 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_m9fc1a0ff196728bb0dbae698e2e8a7e9.tex @@ -0,0 +1,5 @@ +function _set_Misa_M (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 12, 12, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_mxlfaf2da4a42816291e01fbd0451c6cfc5.tex b/sail_latex_riscv/fnz_set_misa_mxlfaf2da4a42816291e01fbd0451c6cfc5.tex new file mode 100644 index 00000000..c837d50c --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_mxlfaf2da4a42816291e01fbd0451c6cfc5.tex @@ -0,0 +1,5 @@ +function _set_Misa_MXL (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 63, 62, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_n1bb6db66ab4e88190d63b918228487ea.tex b/sail_latex_riscv/fnz_set_misa_n1bb6db66ab4e88190d63b918228487ea.tex new file mode 100644 index 00000000..a8a5fa32 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_n1bb6db66ab4e88190d63b918228487ea.tex @@ -0,0 +1,5 @@ +function _set_Misa_N (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 13, 13, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_o6e1ac3382cd1de0c3fbbaf6bbce3e104.tex b/sail_latex_riscv/fnz_set_misa_o6e1ac3382cd1de0c3fbbaf6bbce3e104.tex new file mode 100644 index 00000000..58c0e51e --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_o6e1ac3382cd1de0c3fbbaf6bbce3e104.tex @@ -0,0 +1,5 @@ +function _set_Misa_O (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 14, 14, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_p0c9c63b8a5952a51bae2365cdbc17092.tex b/sail_latex_riscv/fnz_set_misa_p0c9c63b8a5952a51bae2365cdbc17092.tex new file mode 100644 index 00000000..d2eb3cdf --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_p0c9c63b8a5952a51bae2365cdbc17092.tex @@ -0,0 +1,5 @@ +function _set_Misa_P (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 15, 15, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_q0b750236d1f52d9ca63b5ff7f29aeaad.tex b/sail_latex_riscv/fnz_set_misa_q0b750236d1f52d9ca63b5ff7f29aeaad.tex new file mode 100644 index 00000000..d2b71478 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_q0b750236d1f52d9ca63b5ff7f29aeaad.tex @@ -0,0 +1,5 @@ +function _set_Misa_Q (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 16, 16, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_r2e9e070264ac8e4df4365cbcd9bfec35.tex b/sail_latex_riscv/fnz_set_misa_r2e9e070264ac8e4df4365cbcd9bfec35.tex new file mode 100644 index 00000000..b0cda564 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_r2e9e070264ac8e4df4365cbcd9bfec35.tex @@ -0,0 +1,5 @@ +function _set_Misa_R (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 17, 17, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_s4c44d8942646231e0c7666a1590a0a92.tex b/sail_latex_riscv/fnz_set_misa_s4c44d8942646231e0c7666a1590a0a92.tex new file mode 100644 index 00000000..c99a45a1 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_s4c44d8942646231e0c7666a1590a0a92.tex @@ -0,0 +1,5 @@ +function _set_Misa_S (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 18, 18, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_tc2c88db403b799714c1a38812acd037c.tex b/sail_latex_riscv/fnz_set_misa_tc2c88db403b799714c1a38812acd037c.tex new file mode 100644 index 00000000..64c760db --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_tc2c88db403b799714c1a38812acd037c.tex @@ -0,0 +1,5 @@ +function _set_Misa_T (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 19, 19, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_ub0a56841c43a9fb3c49a6bee644b7362.tex b/sail_latex_riscv/fnz_set_misa_ub0a56841c43a9fb3c49a6bee644b7362.tex new file mode 100644 index 00000000..fbffe86b --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_ub0a56841c43a9fb3c49a6bee644b7362.tex @@ -0,0 +1,5 @@ +function _set_Misa_U (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 20, 20, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_vd4a716e627db58a7aa372269cb454a1e.tex b/sail_latex_riscv/fnz_set_misa_vd4a716e627db58a7aa372269cb454a1e.tex new file mode 100644 index 00000000..1448db0a --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_vd4a716e627db58a7aa372269cb454a1e.tex @@ -0,0 +1,5 @@ +function _set_Misa_V (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 21, 21, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_wcf078697ae48ea6fcaebfe7fc01e054a.tex b/sail_latex_riscv/fnz_set_misa_wcf078697ae48ea6fcaebfe7fc01e054a.tex new file mode 100644 index 00000000..d948f0ef --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_wcf078697ae48ea6fcaebfe7fc01e054a.tex @@ -0,0 +1,5 @@ +function _set_Misa_W (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 22, 22, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_x73ca1bfd41ee29a68574f834d43acd6b.tex b/sail_latex_riscv/fnz_set_misa_x73ca1bfd41ee29a68574f834d43acd6b.tex new file mode 100644 index 00000000..af321674 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_x73ca1bfd41ee29a68574f834d43acd6b.tex @@ -0,0 +1,5 @@ +function _set_Misa_X (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 23, 23, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_y0780ac18d01eba2171fd0f4807b7f5eb.tex b/sail_latex_riscv/fnz_set_misa_y0780ac18d01eba2171fd0f4807b7f5eb.tex new file mode 100644 index 00000000..35c3bd88 --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_y0780ac18d01eba2171fd0f4807b7f5eb.tex @@ -0,0 +1,5 @@ +function _set_Misa_Y (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 24, 24, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_misa_z0aa6e14567359f53c59523971c522eda.tex b/sail_latex_riscv/fnz_set_misa_z0aa6e14567359f53c59523971c522eda.tex new file mode 100644 index 00000000..f4f0544c --- /dev/null +++ b/sail_latex_riscv/fnz_set_misa_z0aa6e14567359f53c59523971c522eda.tex @@ -0,0 +1,5 @@ +function _set_Misa_Z (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Misa_chunk_0 = update_subrange_bits(r.Misa_chunk_0, 25, 25, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_bits70d36d4b6b9dcb53e2c6533f6831dfa1.tex b/sail_latex_riscv/fnz_set_mstatus_bits70d36d4b6b9dcb53e2c6533f6831dfa1.tex new file mode 100644 index 00000000..c9306ff9 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_bits70d36d4b6b9dcb53e2c6533f6831dfa1.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_fsf8cc24d417ffb4c08683df543afa5120.tex b/sail_latex_riscv/fnz_set_mstatus_fsf8cc24d417ffb4c08683df543afa5120.tex new file mode 100644 index 00000000..00c015ef --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_fsf8cc24d417ffb4c08683df543afa5120.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_FS (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 14, 13, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_mie3ca1abf74b0d93affa2751898f9cdd5b.tex b/sail_latex_riscv/fnz_set_mstatus_mie3ca1abf74b0d93affa2751898f9cdd5b.tex new file mode 100644 index 00000000..8486c844 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_mie3ca1abf74b0d93affa2751898f9cdd5b.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_MIE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 3, 3, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_mpieb229e5b0c3cc862190502f8c77503c18.tex b/sail_latex_riscv/fnz_set_mstatus_mpieb229e5b0c3cc862190502f8c77503c18.tex new file mode 100644 index 00000000..58041805 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_mpieb229e5b0c3cc862190502f8c77503c18.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_MPIE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 7, 7, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_mppaeee0122745c7341c92694423c1d67fa.tex b/sail_latex_riscv/fnz_set_mstatus_mppaeee0122745c7341c92694423c1d67fa.tex new file mode 100644 index 00000000..315f96c0 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_mppaeee0122745c7341c92694423c1d67fa.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_MPP (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 12, 11, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_mprv7cb39a57c743d887daa45479299eb721.tex b/sail_latex_riscv/fnz_set_mstatus_mprv7cb39a57c743d887daa45479299eb721.tex new file mode 100644 index 00000000..ab55837b --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_mprv7cb39a57c743d887daa45479299eb721.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_MPRV (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 17, 17, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_mxr7d2c792dc408468b6a36d6dccfe73ce3.tex b/sail_latex_riscv/fnz_set_mstatus_mxr7d2c792dc408468b6a36d6dccfe73ce3.tex new file mode 100644 index 00000000..6c8c3ff5 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_mxr7d2c792dc408468b6a36d6dccfe73ce3.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_MXR (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 19, 19, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_sdd513d7f81bd0e504ac04f4e053f73dea.tex b/sail_latex_riscv/fnz_set_mstatus_sdd513d7f81bd0e504ac04f4e053f73dea.tex new file mode 100644 index 00000000..ca5878b5 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_sdd513d7f81bd0e504ac04f4e053f73dea.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_SD (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 63, 63, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_sie307ee7865e3a638cfafc30565428356d.tex b/sail_latex_riscv/fnz_set_mstatus_sie307ee7865e3a638cfafc30565428356d.tex new file mode 100644 index 00000000..f309e708 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_sie307ee7865e3a638cfafc30565428356d.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_SIE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_spie57764ca3799b0493ec493d655361699e.tex b/sail_latex_riscv/fnz_set_mstatus_spie57764ca3799b0493ec493d655361699e.tex new file mode 100644 index 00000000..eb2d7ab8 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_spie57764ca3799b0493ec493d655361699e.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_SPIE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 5, 5, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_sppf813af50b83110182ea2f06174cb1d20.tex b/sail_latex_riscv/fnz_set_mstatus_sppf813af50b83110182ea2f06174cb1d20.tex new file mode 100644 index 00000000..869ba5ce --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_sppf813af50b83110182ea2f06174cb1d20.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_SPP (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 8, 8, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_sume93a07e55c0ec08fc5f1fff8ec36c08c.tex b/sail_latex_riscv/fnz_set_mstatus_sume93a07e55c0ec08fc5f1fff8ec36c08c.tex new file mode 100644 index 00000000..1ffc4c1c --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_sume93a07e55c0ec08fc5f1fff8ec36c08c.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_SUM (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 18, 18, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_tsraafd8a43c6d53a07c488b0efb80af394.tex b/sail_latex_riscv/fnz_set_mstatus_tsraafd8a43c6d53a07c488b0efb80af394.tex new file mode 100644 index 00000000..8318604c --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_tsraafd8a43c6d53a07c488b0efb80af394.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_TSR (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 22, 22, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_tvmb162bee39ba51b064f3dd93188326775.tex b/sail_latex_riscv/fnz_set_mstatus_tvmb162bee39ba51b064f3dd93188326775.tex new file mode 100644 index 00000000..da611ac0 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_tvmb162bee39ba51b064f3dd93188326775.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_TVM (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 20, 20, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_tw07f419963ff98d483c7b9ce832c90eb4.tex b/sail_latex_riscv/fnz_set_mstatus_tw07f419963ff98d483c7b9ce832c90eb4.tex new file mode 100644 index 00000000..2a72b476 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_tw07f419963ff98d483c7b9ce832c90eb4.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_TW (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 21, 21, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_uieb479c3c10676b772a02256f3db5428da.tex b/sail_latex_riscv/fnz_set_mstatus_uieb479c3c10676b772a02256f3db5428da.tex new file mode 100644 index 00000000..9deb17b1 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_uieb479c3c10676b772a02256f3db5428da.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_UIE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_upie97f5fcc7e74b28a97eb44ae99226200f.tex b/sail_latex_riscv/fnz_set_mstatus_upie97f5fcc7e74b28a97eb44ae99226200f.tex new file mode 100644 index 00000000..4250f58a --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_upie97f5fcc7e74b28a97eb44ae99226200f.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_UPIE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 4, 4, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mstatus_xs13adea89de69c7b934d405e2c5369191.tex b/sail_latex_riscv/fnz_set_mstatus_xs13adea89de69c7b934d405e2c5369191.tex new file mode 100644 index 00000000..81da2272 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mstatus_xs13adea89de69c7b934d405e2c5369191.tex @@ -0,0 +1,5 @@ +function _set_Mstatus_XS (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mstatus_chunk_0 = update_subrange_bits(r.Mstatus_chunk_0, 16, 15, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mtvec_base86e6903a9eebeb1822f298249988800a.tex b/sail_latex_riscv/fnz_set_mtvec_base86e6903a9eebeb1822f298249988800a.tex new file mode 100644 index 00000000..b8bbd762 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mtvec_base86e6903a9eebeb1822f298249988800a.tex @@ -0,0 +1,5 @@ +function _set_Mtvec_Base (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mtvec_chunk_0 = update_subrange_bits(r.Mtvec_chunk_0, 63, 2, subrange_bits(v, 61, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mtvec_bitsbae28d0fb32e4a35886c4c0190acdeb8.tex b/sail_latex_riscv/fnz_set_mtvec_bitsbae28d0fb32e4a35886c4c0190acdeb8.tex new file mode 100644 index 00000000..f9cb26a8 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mtvec_bitsbae28d0fb32e4a35886c4c0190acdeb8.tex @@ -0,0 +1,5 @@ +function _set_Mtvec_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mtvec_chunk_0 = update_subrange_bits(r.Mtvec_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_mtvec_mode83a05e7666364d3e4e87f1aedc208023.tex b/sail_latex_riscv/fnz_set_mtvec_mode83a05e7666364d3e4e87f1aedc208023.tex new file mode 100644 index 00000000..e2700f48 --- /dev/null +++ b/sail_latex_riscv/fnz_set_mtvec_mode83a05e7666364d3e4e87f1aedc208023.tex @@ -0,0 +1,5 @@ +function _set_Mtvec_Mode (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Mtvec_chunk_0 = update_subrange_bits(r.Mtvec_chunk_0, 1, 0, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pmpcfg_ent_a9693fd9f223e2207b066d9000b8199c1.tex b/sail_latex_riscv/fnz_set_pmpcfg_ent_a9693fd9f223e2207b066d9000b8199c1.tex new file mode 100644 index 00000000..849f9024 --- /dev/null +++ b/sail_latex_riscv/fnz_set_pmpcfg_ent_a9693fd9f223e2207b066d9000b8199c1.tex @@ -0,0 +1,5 @@ +function _set_Pmpcfg_ent_A (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Pmpcfg_ent_chunk_0 = update_subrange_bits(r.Pmpcfg_ent_chunk_0, 4, 3, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pmpcfg_ent_bits594540475f6835a77bc55f1853c82f34.tex b/sail_latex_riscv/fnz_set_pmpcfg_ent_bits594540475f6835a77bc55f1853c82f34.tex new file mode 100644 index 00000000..ab1cf461 --- /dev/null +++ b/sail_latex_riscv/fnz_set_pmpcfg_ent_bits594540475f6835a77bc55f1853c82f34.tex @@ -0,0 +1,5 @@ +function _set_Pmpcfg_ent_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Pmpcfg_ent_chunk_0 = update_subrange_bits(r.Pmpcfg_ent_chunk_0, 7, 0, subrange_bits(v, 7, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pmpcfg_ent_l3838182dc02b8ff73f27360aa88f7580.tex b/sail_latex_riscv/fnz_set_pmpcfg_ent_l3838182dc02b8ff73f27360aa88f7580.tex new file mode 100644 index 00000000..0bcb13c0 --- /dev/null +++ b/sail_latex_riscv/fnz_set_pmpcfg_ent_l3838182dc02b8ff73f27360aa88f7580.tex @@ -0,0 +1,5 @@ +function _set_Pmpcfg_ent_L (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Pmpcfg_ent_chunk_0 = update_subrange_bits(r.Pmpcfg_ent_chunk_0, 7, 7, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pmpcfg_ent_re7495d5157c5145daf88a430c7faa2ea.tex b/sail_latex_riscv/fnz_set_pmpcfg_ent_re7495d5157c5145daf88a430c7faa2ea.tex new file mode 100644 index 00000000..10bb4db8 --- /dev/null +++ b/sail_latex_riscv/fnz_set_pmpcfg_ent_re7495d5157c5145daf88a430c7faa2ea.tex @@ -0,0 +1,5 @@ +function _set_Pmpcfg_ent_R (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Pmpcfg_ent_chunk_0 = update_subrange_bits(r.Pmpcfg_ent_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pmpcfg_ent_wce1529faf12026bc7cc93760d4dd2183.tex b/sail_latex_riscv/fnz_set_pmpcfg_ent_wce1529faf12026bc7cc93760d4dd2183.tex new file mode 100644 index 00000000..f3879e9f --- /dev/null +++ b/sail_latex_riscv/fnz_set_pmpcfg_ent_wce1529faf12026bc7cc93760d4dd2183.tex @@ -0,0 +1,5 @@ +function _set_Pmpcfg_ent_W (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Pmpcfg_ent_chunk_0 = update_subrange_bits(r.Pmpcfg_ent_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pmpcfg_ent_x673f5396d42ee8881cf0e4a176b53225.tex b/sail_latex_riscv/fnz_set_pmpcfg_ent_x673f5396d42ee8881cf0e4a176b53225.tex new file mode 100644 index 00000000..34b0f5a7 --- /dev/null +++ b/sail_latex_riscv/fnz_set_pmpcfg_ent_x673f5396d42ee8881cf0e4a176b53225.tex @@ -0,0 +1,5 @@ +function _set_Pmpcfg_ent_X (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Pmpcfg_ent_chunk_0 = update_subrange_bits(r.Pmpcfg_ent_chunk_0, 2, 2, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pte_bits_aac67ea7f6b10ab3673728f748f93c292.tex b/sail_latex_riscv/fnz_set_pte_bits_aac67ea7f6b10ab3673728f748f93c292.tex new file mode 100644 index 00000000..36bae9ce --- /dev/null +++ b/sail_latex_riscv/fnz_set_pte_bits_aac67ea7f6b10ab3673728f748f93c292.tex @@ -0,0 +1,5 @@ +function _set_PTE_Bits_A (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.PTE_Bits_chunk_0 = update_subrange_bits(r.PTE_Bits_chunk_0, 6, 6, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pte_bits_bits6d0635987f7718a8a39cf3033064c503.tex b/sail_latex_riscv/fnz_set_pte_bits_bits6d0635987f7718a8a39cf3033064c503.tex new file mode 100644 index 00000000..0421f802 --- /dev/null +++ b/sail_latex_riscv/fnz_set_pte_bits_bits6d0635987f7718a8a39cf3033064c503.tex @@ -0,0 +1,5 @@ +function _set_PTE_Bits_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.PTE_Bits_chunk_0 = update_subrange_bits(r.PTE_Bits_chunk_0, 7, 0, subrange_bits(v, 7, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pte_bits_d91bbe4815197f856eaded6975a2b164b.tex b/sail_latex_riscv/fnz_set_pte_bits_d91bbe4815197f856eaded6975a2b164b.tex new file mode 100644 index 00000000..58cf9fe1 --- /dev/null +++ b/sail_latex_riscv/fnz_set_pte_bits_d91bbe4815197f856eaded6975a2b164b.tex @@ -0,0 +1,5 @@ +function _set_PTE_Bits_D (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.PTE_Bits_chunk_0 = update_subrange_bits(r.PTE_Bits_chunk_0, 7, 7, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pte_bits_g31ff87423c27525881946540eb3368f0.tex b/sail_latex_riscv/fnz_set_pte_bits_g31ff87423c27525881946540eb3368f0.tex new file mode 100644 index 00000000..3349c6d4 --- /dev/null +++ b/sail_latex_riscv/fnz_set_pte_bits_g31ff87423c27525881946540eb3368f0.tex @@ -0,0 +1,5 @@ +function _set_PTE_Bits_G (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.PTE_Bits_chunk_0 = update_subrange_bits(r.PTE_Bits_chunk_0, 5, 5, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pte_bits_r7ddb8623ba4795fb0437583737d032bc.tex b/sail_latex_riscv/fnz_set_pte_bits_r7ddb8623ba4795fb0437583737d032bc.tex new file mode 100644 index 00000000..89dd0010 --- /dev/null +++ b/sail_latex_riscv/fnz_set_pte_bits_r7ddb8623ba4795fb0437583737d032bc.tex @@ -0,0 +1,5 @@ +function _set_PTE_Bits_R (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.PTE_Bits_chunk_0 = update_subrange_bits(r.PTE_Bits_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pte_bits_u7152ad61970d5f3617d43634186dfaf6.tex b/sail_latex_riscv/fnz_set_pte_bits_u7152ad61970d5f3617d43634186dfaf6.tex new file mode 100644 index 00000000..b946c154 --- /dev/null +++ b/sail_latex_riscv/fnz_set_pte_bits_u7152ad61970d5f3617d43634186dfaf6.tex @@ -0,0 +1,5 @@ +function _set_PTE_Bits_U (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.PTE_Bits_chunk_0 = update_subrange_bits(r.PTE_Bits_chunk_0, 4, 4, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pte_bits_ve9a7a4a2a11bf5683da07253607039cb.tex b/sail_latex_riscv/fnz_set_pte_bits_ve9a7a4a2a11bf5683da07253607039cb.tex new file mode 100644 index 00000000..28d364e6 --- /dev/null +++ b/sail_latex_riscv/fnz_set_pte_bits_ve9a7a4a2a11bf5683da07253607039cb.tex @@ -0,0 +1,5 @@ +function _set_PTE_Bits_V (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.PTE_Bits_chunk_0 = update_subrange_bits(r.PTE_Bits_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pte_bits_w6af9664f46a96e5953a99351ac9f2eec.tex b/sail_latex_riscv/fnz_set_pte_bits_w6af9664f46a96e5953a99351ac9f2eec.tex new file mode 100644 index 00000000..d7b3b558 --- /dev/null +++ b/sail_latex_riscv/fnz_set_pte_bits_w6af9664f46a96e5953a99351ac9f2eec.tex @@ -0,0 +1,5 @@ +function _set_PTE_Bits_W (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.PTE_Bits_chunk_0 = update_subrange_bits(r.PTE_Bits_chunk_0, 2, 2, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_pte_bits_xd8616f420b73ae2b89e310bf44d3a11a.tex b/sail_latex_riscv/fnz_set_pte_bits_xd8616f420b73ae2b89e310bf44d3a11a.tex new file mode 100644 index 00000000..74e85fea --- /dev/null +++ b/sail_latex_riscv/fnz_set_pte_bits_xd8616f420b73ae2b89e310bf44d3a11a.tex @@ -0,0 +1,5 @@ +function _set_PTE_Bits_X (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.PTE_Bits_chunk_0 = update_subrange_bits(r.PTE_Bits_chunk_0, 3, 3, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_satp32_asid1e472f8b9d87ee7ce4dc47786138f7af.tex b/sail_latex_riscv/fnz_set_satp32_asid1e472f8b9d87ee7ce4dc47786138f7af.tex new file mode 100644 index 00000000..e1adf438 --- /dev/null +++ b/sail_latex_riscv/fnz_set_satp32_asid1e472f8b9d87ee7ce4dc47786138f7af.tex @@ -0,0 +1,5 @@ +function _set_Satp32_Asid (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Satp32_chunk_0 = update_subrange_bits(r.Satp32_chunk_0, 30, 22, subrange_bits(v, 8, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_satp32_bits1d19cd20b80cea73ba6dc6c4919c83bd.tex b/sail_latex_riscv/fnz_set_satp32_bits1d19cd20b80cea73ba6dc6c4919c83bd.tex new file mode 100644 index 00000000..d087d430 --- /dev/null +++ b/sail_latex_riscv/fnz_set_satp32_bits1d19cd20b80cea73ba6dc6c4919c83bd.tex @@ -0,0 +1,5 @@ +function _set_Satp32_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Satp32_chunk_0 = update_subrange_bits(r.Satp32_chunk_0, 31, 0, subrange_bits(v, 31, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_satp32_mode92a8ae476bd67a0a5ff16c383b2067ca.tex b/sail_latex_riscv/fnz_set_satp32_mode92a8ae476bd67a0a5ff16c383b2067ca.tex new file mode 100644 index 00000000..6bbf388d --- /dev/null +++ b/sail_latex_riscv/fnz_set_satp32_mode92a8ae476bd67a0a5ff16c383b2067ca.tex @@ -0,0 +1,5 @@ +function _set_Satp32_Mode (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Satp32_chunk_0 = update_subrange_bits(r.Satp32_chunk_0, 31, 31, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_satp32_ppne026770b9c95405e7d420506a450e1f8.tex b/sail_latex_riscv/fnz_set_satp32_ppne026770b9c95405e7d420506a450e1f8.tex new file mode 100644 index 00000000..526909f7 --- /dev/null +++ b/sail_latex_riscv/fnz_set_satp32_ppne026770b9c95405e7d420506a450e1f8.tex @@ -0,0 +1,5 @@ +function _set_Satp32_PPN (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Satp32_chunk_0 = update_subrange_bits(r.Satp32_chunk_0, 21, 0, subrange_bits(v, 21, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_satp64_asid2ddaf59d37788d7a3a27cef76891dfb8.tex b/sail_latex_riscv/fnz_set_satp64_asid2ddaf59d37788d7a3a27cef76891dfb8.tex new file mode 100644 index 00000000..e8f1455c --- /dev/null +++ b/sail_latex_riscv/fnz_set_satp64_asid2ddaf59d37788d7a3a27cef76891dfb8.tex @@ -0,0 +1,5 @@ +function _set_Satp64_Asid (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Satp64_chunk_0 = update_subrange_bits(r.Satp64_chunk_0, 59, 44, subrange_bits(v, 15, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_satp64_bits1ef37f6f328908e0dfa046d4c516d3b7.tex b/sail_latex_riscv/fnz_set_satp64_bits1ef37f6f328908e0dfa046d4c516d3b7.tex new file mode 100644 index 00000000..ba19579b --- /dev/null +++ b/sail_latex_riscv/fnz_set_satp64_bits1ef37f6f328908e0dfa046d4c516d3b7.tex @@ -0,0 +1,5 @@ +function _set_Satp64_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Satp64_chunk_0 = update_subrange_bits(r.Satp64_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_satp64_modedd62965c996bac9cb96fa44094dbf974.tex b/sail_latex_riscv/fnz_set_satp64_modedd62965c996bac9cb96fa44094dbf974.tex new file mode 100644 index 00000000..92491c62 --- /dev/null +++ b/sail_latex_riscv/fnz_set_satp64_modedd62965c996bac9cb96fa44094dbf974.tex @@ -0,0 +1,5 @@ +function _set_Satp64_Mode (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Satp64_chunk_0 = update_subrange_bits(r.Satp64_chunk_0, 63, 60, subrange_bits(v, 3, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_satp64_ppn31d9614063b4541d68753b5e3090b133.tex b/sail_latex_riscv/fnz_set_satp64_ppn31d9614063b4541d68753b5e3090b133.tex new file mode 100644 index 00000000..07c5b7f0 --- /dev/null +++ b/sail_latex_riscv/fnz_set_satp64_ppn31d9614063b4541d68753b5e3090b133.tex @@ -0,0 +1,5 @@ +function _set_Satp64_PPN (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Satp64_chunk_0 = update_subrange_bits(r.Satp64_chunk_0, 43, 0, subrange_bits(v, 43, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sedeleg_bitsa2dbd669d717e67fa0750d9be9a12cee.tex b/sail_latex_riscv/fnz_set_sedeleg_bitsa2dbd669d717e67fa0750d9be9a12cee.tex new file mode 100644 index 00000000..aaf22f29 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sedeleg_bitsa2dbd669d717e67fa0750d9be9a12cee.tex @@ -0,0 +1,5 @@ +function _set_Sedeleg_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sedeleg_chunk_0 = update_subrange_bits(r.Sedeleg_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sedeleg_breakpoint2acb469996a4630099a56b45b59c2861.tex b/sail_latex_riscv/fnz_set_sedeleg_breakpoint2acb469996a4630099a56b45b59c2861.tex new file mode 100644 index 00000000..4e24e761 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sedeleg_breakpoint2acb469996a4630099a56b45b59c2861.tex @@ -0,0 +1,5 @@ +function _set_Sedeleg_Breakpoint (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sedeleg_chunk_0 = update_subrange_bits(r.Sedeleg_chunk_0, 3, 3, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sedeleg_fetch_access_fault193173c32591a593674fa8e5c0a550fc.tex b/sail_latex_riscv/fnz_set_sedeleg_fetch_access_fault193173c32591a593674fa8e5c0a550fc.tex new file mode 100644 index 00000000..8ed285d7 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sedeleg_fetch_access_fault193173c32591a593674fa8e5c0a550fc.tex @@ -0,0 +1,5 @@ +function _set_Sedeleg_Fetch_Access_Fault (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sedeleg_chunk_0 = update_subrange_bits(r.Sedeleg_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sedeleg_fetch_addr_aligna2669337b650c15def12b3457ae83d4f.tex b/sail_latex_riscv/fnz_set_sedeleg_fetch_addr_aligna2669337b650c15def12b3457ae83d4f.tex new file mode 100644 index 00000000..9858c4b8 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sedeleg_fetch_addr_aligna2669337b650c15def12b3457ae83d4f.tex @@ -0,0 +1,5 @@ +function _set_Sedeleg_Fetch_Addr_Align (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sedeleg_chunk_0 = update_subrange_bits(r.Sedeleg_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sedeleg_illegal_instrd248f17962068c21c567c4bc40790c19.tex b/sail_latex_riscv/fnz_set_sedeleg_illegal_instrd248f17962068c21c567c4bc40790c19.tex new file mode 100644 index 00000000..565d3cc0 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sedeleg_illegal_instrd248f17962068c21c567c4bc40790c19.tex @@ -0,0 +1,5 @@ +function _set_Sedeleg_Illegal_Instr (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sedeleg_chunk_0 = update_subrange_bits(r.Sedeleg_chunk_0, 2, 2, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sedeleg_load_access_fault3dcfaa698c0c375f65a901a1c187a93b.tex b/sail_latex_riscv/fnz_set_sedeleg_load_access_fault3dcfaa698c0c375f65a901a1c187a93b.tex new file mode 100644 index 00000000..1d2e3b85 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sedeleg_load_access_fault3dcfaa698c0c375f65a901a1c187a93b.tex @@ -0,0 +1,5 @@ +function _set_Sedeleg_Load_Access_Fault (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sedeleg_chunk_0 = update_subrange_bits(r.Sedeleg_chunk_0, 5, 5, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sedeleg_load_addr_align3845e25f6585eadcab3b640d7c9d0c9a.tex b/sail_latex_riscv/fnz_set_sedeleg_load_addr_align3845e25f6585eadcab3b640d7c9d0c9a.tex new file mode 100644 index 00000000..ebabe54b --- /dev/null +++ b/sail_latex_riscv/fnz_set_sedeleg_load_addr_align3845e25f6585eadcab3b640d7c9d0c9a.tex @@ -0,0 +1,5 @@ +function _set_Sedeleg_Load_Addr_Align (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sedeleg_chunk_0 = update_subrange_bits(r.Sedeleg_chunk_0, 4, 4, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sedeleg_samo_access_fault9cc04f455b39e7c1866c125033bf2f03.tex b/sail_latex_riscv/fnz_set_sedeleg_samo_access_fault9cc04f455b39e7c1866c125033bf2f03.tex new file mode 100644 index 00000000..69d35afd --- /dev/null +++ b/sail_latex_riscv/fnz_set_sedeleg_samo_access_fault9cc04f455b39e7c1866c125033bf2f03.tex @@ -0,0 +1,5 @@ +function _set_Sedeleg_SAMO_Access_Fault (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sedeleg_chunk_0 = update_subrange_bits(r.Sedeleg_chunk_0, 7, 7, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sedeleg_samo_addr_align9567cfb032fb426d3c4292d506d6a9d2.tex b/sail_latex_riscv/fnz_set_sedeleg_samo_addr_align9567cfb032fb426d3c4292d506d6a9d2.tex new file mode 100644 index 00000000..39e2e45b --- /dev/null +++ b/sail_latex_riscv/fnz_set_sedeleg_samo_addr_align9567cfb032fb426d3c4292d506d6a9d2.tex @@ -0,0 +1,5 @@ +function _set_Sedeleg_SAMO_Addr_Align (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sedeleg_chunk_0 = update_subrange_bits(r.Sedeleg_chunk_0, 6, 6, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sedeleg_uenvcall80b0a54fdfebf30e056fa7c713788315.tex b/sail_latex_riscv/fnz_set_sedeleg_uenvcall80b0a54fdfebf30e056fa7c713788315.tex new file mode 100644 index 00000000..fd4741b8 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sedeleg_uenvcall80b0a54fdfebf30e056fa7c713788315.tex @@ -0,0 +1,5 @@ +function _set_Sedeleg_UEnvCall (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sedeleg_chunk_0 = update_subrange_bits(r.Sedeleg_chunk_0, 8, 8, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sinterrupts_bits11d675c3310ec7be4b053dce213f9e13.tex b/sail_latex_riscv/fnz_set_sinterrupts_bits11d675c3310ec7be4b053dce213f9e13.tex new file mode 100644 index 00000000..a089b1b8 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sinterrupts_bits11d675c3310ec7be4b053dce213f9e13.tex @@ -0,0 +1,5 @@ +function _set_Sinterrupts_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sinterrupts_chunk_0 = update_subrange_bits(r.Sinterrupts_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sinterrupts_seid1a27b6ed01fc08d7ed92e7473ca0c67.tex b/sail_latex_riscv/fnz_set_sinterrupts_seid1a27b6ed01fc08d7ed92e7473ca0c67.tex new file mode 100644 index 00000000..3e1f561c --- /dev/null +++ b/sail_latex_riscv/fnz_set_sinterrupts_seid1a27b6ed01fc08d7ed92e7473ca0c67.tex @@ -0,0 +1,5 @@ +function _set_Sinterrupts_SEI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sinterrupts_chunk_0 = update_subrange_bits(r.Sinterrupts_chunk_0, 9, 9, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sinterrupts_ssi34d088bb8c03bd9774e94278832e9c78.tex b/sail_latex_riscv/fnz_set_sinterrupts_ssi34d088bb8c03bd9774e94278832e9c78.tex new file mode 100644 index 00000000..30a3683b --- /dev/null +++ b/sail_latex_riscv/fnz_set_sinterrupts_ssi34d088bb8c03bd9774e94278832e9c78.tex @@ -0,0 +1,5 @@ +function _set_Sinterrupts_SSI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sinterrupts_chunk_0 = update_subrange_bits(r.Sinterrupts_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sinterrupts_sti6ee1684f0baef5e2b4c1b77cfad5548a.tex b/sail_latex_riscv/fnz_set_sinterrupts_sti6ee1684f0baef5e2b4c1b77cfad5548a.tex new file mode 100644 index 00000000..0fe58e74 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sinterrupts_sti6ee1684f0baef5e2b4c1b77cfad5548a.tex @@ -0,0 +1,5 @@ +function _set_Sinterrupts_STI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sinterrupts_chunk_0 = update_subrange_bits(r.Sinterrupts_chunk_0, 5, 5, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sinterrupts_ueid6db53e4645f60442d748c9717159555.tex b/sail_latex_riscv/fnz_set_sinterrupts_ueid6db53e4645f60442d748c9717159555.tex new file mode 100644 index 00000000..b3a76788 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sinterrupts_ueid6db53e4645f60442d748c9717159555.tex @@ -0,0 +1,5 @@ +function _set_Sinterrupts_UEI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sinterrupts_chunk_0 = update_subrange_bits(r.Sinterrupts_chunk_0, 8, 8, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sinterrupts_usi4837f15564ed5aede9a0c1c6ed9d89c6.tex b/sail_latex_riscv/fnz_set_sinterrupts_usi4837f15564ed5aede9a0c1c6ed9d89c6.tex new file mode 100644 index 00000000..32a2e22a --- /dev/null +++ b/sail_latex_riscv/fnz_set_sinterrupts_usi4837f15564ed5aede9a0c1c6ed9d89c6.tex @@ -0,0 +1,5 @@ +function _set_Sinterrupts_USI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sinterrupts_chunk_0 = update_subrange_bits(r.Sinterrupts_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sinterrupts_utid6108a193d51614aeb91d29cae7b52d4.tex b/sail_latex_riscv/fnz_set_sinterrupts_utid6108a193d51614aeb91d29cae7b52d4.tex new file mode 100644 index 00000000..9a4be5bd --- /dev/null +++ b/sail_latex_riscv/fnz_set_sinterrupts_utid6108a193d51614aeb91d29cae7b52d4.tex @@ -0,0 +1,5 @@ +function _set_Sinterrupts_UTI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sinterrupts_chunk_0 = update_subrange_bits(r.Sinterrupts_chunk_0, 4, 4, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sstatus_bitsa6c8fba93c0c18f7fc69cd591748cdfa.tex b/sail_latex_riscv/fnz_set_sstatus_bitsa6c8fba93c0c18f7fc69cd591748cdfa.tex new file mode 100644 index 00000000..341604b9 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sstatus_bitsa6c8fba93c0c18f7fc69cd591748cdfa.tex @@ -0,0 +1,5 @@ +function _set_Sstatus_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sstatus_chunk_0 = update_subrange_bits(r.Sstatus_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sstatus_fse0f398b51eea363e05016843c2c595a4.tex b/sail_latex_riscv/fnz_set_sstatus_fse0f398b51eea363e05016843c2c595a4.tex new file mode 100644 index 00000000..f9b38560 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sstatus_fse0f398b51eea363e05016843c2c595a4.tex @@ -0,0 +1,5 @@ +function _set_Sstatus_FS (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sstatus_chunk_0 = update_subrange_bits(r.Sstatus_chunk_0, 14, 13, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sstatus_mxra2eba57c040b3e2ec7adb22d3d1de868.tex b/sail_latex_riscv/fnz_set_sstatus_mxra2eba57c040b3e2ec7adb22d3d1de868.tex new file mode 100644 index 00000000..bedbfb31 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sstatus_mxra2eba57c040b3e2ec7adb22d3d1de868.tex @@ -0,0 +1,5 @@ +function _set_Sstatus_MXR (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sstatus_chunk_0 = update_subrange_bits(r.Sstatus_chunk_0, 19, 19, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sstatus_sdd76fee105151cc55a95224ff72515795.tex b/sail_latex_riscv/fnz_set_sstatus_sdd76fee105151cc55a95224ff72515795.tex new file mode 100644 index 00000000..707a79d4 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sstatus_sdd76fee105151cc55a95224ff72515795.tex @@ -0,0 +1,5 @@ +function _set_Sstatus_SD (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sstatus_chunk_0 = update_subrange_bits(r.Sstatus_chunk_0, 63, 63, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sstatus_siead9f271cff4bf9d22da8464c4d1ca3b4.tex b/sail_latex_riscv/fnz_set_sstatus_siead9f271cff4bf9d22da8464c4d1ca3b4.tex new file mode 100644 index 00000000..09485acc --- /dev/null +++ b/sail_latex_riscv/fnz_set_sstatus_siead9f271cff4bf9d22da8464c4d1ca3b4.tex @@ -0,0 +1,5 @@ +function _set_Sstatus_SIE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sstatus_chunk_0 = update_subrange_bits(r.Sstatus_chunk_0, 1, 1, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sstatus_spie739993a605bcb322c2dbdf0ca5ddd2bc.tex b/sail_latex_riscv/fnz_set_sstatus_spie739993a605bcb322c2dbdf0ca5ddd2bc.tex new file mode 100644 index 00000000..176b66f8 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sstatus_spie739993a605bcb322c2dbdf0ca5ddd2bc.tex @@ -0,0 +1,5 @@ +function _set_Sstatus_SPIE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sstatus_chunk_0 = update_subrange_bits(r.Sstatus_chunk_0, 5, 5, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sstatus_spp8d87600dabd1a0a5c7d063db6e618a28.tex b/sail_latex_riscv/fnz_set_sstatus_spp8d87600dabd1a0a5c7d063db6e618a28.tex new file mode 100644 index 00000000..c600dbf9 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sstatus_spp8d87600dabd1a0a5c7d063db6e618a28.tex @@ -0,0 +1,5 @@ +function _set_Sstatus_SPP (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sstatus_chunk_0 = update_subrange_bits(r.Sstatus_chunk_0, 8, 8, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sstatus_sumd6e6c88b359702301526305ad3ae0775.tex b/sail_latex_riscv/fnz_set_sstatus_sumd6e6c88b359702301526305ad3ae0775.tex new file mode 100644 index 00000000..df80ba1f --- /dev/null +++ b/sail_latex_riscv/fnz_set_sstatus_sumd6e6c88b359702301526305ad3ae0775.tex @@ -0,0 +1,5 @@ +function _set_Sstatus_SUM (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sstatus_chunk_0 = update_subrange_bits(r.Sstatus_chunk_0, 18, 18, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sstatus_uie05848044f6bfa6902b92558093153733.tex b/sail_latex_riscv/fnz_set_sstatus_uie05848044f6bfa6902b92558093153733.tex new file mode 100644 index 00000000..fe00a459 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sstatus_uie05848044f6bfa6902b92558093153733.tex @@ -0,0 +1,5 @@ +function _set_Sstatus_UIE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sstatus_chunk_0 = update_subrange_bits(r.Sstatus_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sstatus_upiec20707b779f0d69be936cc46a8acab83.tex b/sail_latex_riscv/fnz_set_sstatus_upiec20707b779f0d69be936cc46a8acab83.tex new file mode 100644 index 00000000..3dad49cc --- /dev/null +++ b/sail_latex_riscv/fnz_set_sstatus_upiec20707b779f0d69be936cc46a8acab83.tex @@ -0,0 +1,5 @@ +function _set_Sstatus_UPIE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sstatus_chunk_0 = update_subrange_bits(r.Sstatus_chunk_0, 4, 4, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sstatus_xs051efb5955770c941a701fd96e8879a7.tex b/sail_latex_riscv/fnz_set_sstatus_xs051efb5955770c941a701fd96e8879a7.tex new file mode 100644 index 00000000..f7a43fe8 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sstatus_xs051efb5955770c941a701fd96e8879a7.tex @@ -0,0 +1,5 @@ +function _set_Sstatus_XS (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Sstatus_chunk_0 = update_subrange_bits(r.Sstatus_chunk_0, 16, 15, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv32_paddr_bits7ac5072e9a9d0f202a9169b342d1027c.tex b/sail_latex_riscv/fnz_set_sv32_paddr_bits7ac5072e9a9d0f202a9169b342d1027c.tex new file mode 100644 index 00000000..0a09ca2a --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv32_paddr_bits7ac5072e9a9d0f202a9169b342d1027c.tex @@ -0,0 +1,5 @@ +function _set_SV32_Paddr_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV32_Paddr_chunk_0 = update_subrange_bits(r.SV32_Paddr_chunk_0, 33, 0, subrange_bits(v, 33, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv32_paddr_pgofsab302689c37e31253a4e6531b82c42ab.tex b/sail_latex_riscv/fnz_set_sv32_paddr_pgofsab302689c37e31253a4e6531b82c42ab.tex new file mode 100644 index 00000000..93009ddc --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv32_paddr_pgofsab302689c37e31253a4e6531b82c42ab.tex @@ -0,0 +1,5 @@ +function _set_SV32_Paddr_PgOfs (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV32_Paddr_chunk_0 = update_subrange_bits(r.SV32_Paddr_chunk_0, 11, 0, subrange_bits(v, 11, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv32_paddr_ppni94a2cc32ea73c50cb5cac893287046f5.tex b/sail_latex_riscv/fnz_set_sv32_paddr_ppni94a2cc32ea73c50cb5cac893287046f5.tex new file mode 100644 index 00000000..24e6c7d7 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv32_paddr_ppni94a2cc32ea73c50cb5cac893287046f5.tex @@ -0,0 +1,5 @@ +function _set_SV32_Paddr_PPNi (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV32_Paddr_chunk_0 = update_subrange_bits(r.SV32_Paddr_chunk_0, 33, 12, subrange_bits(v, 21, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv32_pte_bits4f565be9958b1f59ab14509c2773579f.tex b/sail_latex_riscv/fnz_set_sv32_pte_bits4f565be9958b1f59ab14509c2773579f.tex new file mode 100644 index 00000000..1c21e2de --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv32_pte_bits4f565be9958b1f59ab14509c2773579f.tex @@ -0,0 +1,5 @@ +function _set_SV32_PTE_BITS (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV32_PTE_chunk_0 = update_subrange_bits(r.SV32_PTE_chunk_0, 7, 0, subrange_bits(v, 7, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv32_pte_bitsaf6e5291a5df8cafbd0f8c816eb211d7.tex b/sail_latex_riscv/fnz_set_sv32_pte_bitsaf6e5291a5df8cafbd0f8c816eb211d7.tex new file mode 100644 index 00000000..1d60b2e4 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv32_pte_bitsaf6e5291a5df8cafbd0f8c816eb211d7.tex @@ -0,0 +1,5 @@ +function _set_SV32_PTE_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV32_PTE_chunk_0 = update_subrange_bits(r.SV32_PTE_chunk_0, 31, 0, subrange_bits(v, 31, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv32_pte_ppnifab6de1238f9a347277b22b09cad438b.tex b/sail_latex_riscv/fnz_set_sv32_pte_ppnifab6de1238f9a347277b22b09cad438b.tex new file mode 100644 index 00000000..c84a0b33 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv32_pte_ppnifab6de1238f9a347277b22b09cad438b.tex @@ -0,0 +1,5 @@ +function _set_SV32_PTE_PPNi (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV32_PTE_chunk_0 = update_subrange_bits(r.SV32_PTE_chunk_0, 31, 10, subrange_bits(v, 21, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv32_pte_rsw8ae54b55d6031c4f79807b3714efee6a.tex b/sail_latex_riscv/fnz_set_sv32_pte_rsw8ae54b55d6031c4f79807b3714efee6a.tex new file mode 100644 index 00000000..a5e0e4df --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv32_pte_rsw8ae54b55d6031c4f79807b3714efee6a.tex @@ -0,0 +1,5 @@ +function _set_SV32_PTE_RSW (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV32_PTE_chunk_0 = update_subrange_bits(r.SV32_PTE_chunk_0, 9, 8, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv32_vaddr_bits598a6533ea70614d0d53c8cea8eced8e.tex b/sail_latex_riscv/fnz_set_sv32_vaddr_bits598a6533ea70614d0d53c8cea8eced8e.tex new file mode 100644 index 00000000..b7141c81 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv32_vaddr_bits598a6533ea70614d0d53c8cea8eced8e.tex @@ -0,0 +1,5 @@ +function _set_SV32_Vaddr_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV32_Vaddr_chunk_0 = update_subrange_bits(r.SV32_Vaddr_chunk_0, 31, 0, subrange_bits(v, 31, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv32_vaddr_pgofse1f36d8f721e1df38bd5c772d609bd45.tex b/sail_latex_riscv/fnz_set_sv32_vaddr_pgofse1f36d8f721e1df38bd5c772d609bd45.tex new file mode 100644 index 00000000..b03150ed --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv32_vaddr_pgofse1f36d8f721e1df38bd5c772d609bd45.tex @@ -0,0 +1,5 @@ +function _set_SV32_Vaddr_PgOfs (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV32_Vaddr_chunk_0 = update_subrange_bits(r.SV32_Vaddr_chunk_0, 11, 0, subrange_bits(v, 11, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv32_vaddr_vpnib8665127c6a283f2aacb5e3825422f5f.tex b/sail_latex_riscv/fnz_set_sv32_vaddr_vpnib8665127c6a283f2aacb5e3825422f5f.tex new file mode 100644 index 00000000..57c77ee4 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv32_vaddr_vpnib8665127c6a283f2aacb5e3825422f5f.tex @@ -0,0 +1,5 @@ +function _set_SV32_Vaddr_VPNi (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV32_Vaddr_chunk_0 = update_subrange_bits(r.SV32_Vaddr_chunk_0, 31, 12, subrange_bits(v, 19, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv39_paddr_bits3ec2652094be77813b00186e0c009ce4.tex b/sail_latex_riscv/fnz_set_sv39_paddr_bits3ec2652094be77813b00186e0c009ce4.tex new file mode 100644 index 00000000..569ceece --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv39_paddr_bits3ec2652094be77813b00186e0c009ce4.tex @@ -0,0 +1,5 @@ +function _set_SV39_Paddr_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV39_Paddr_chunk_0 = update_subrange_bits(r.SV39_Paddr_chunk_0, 55, 0, subrange_bits(v, 55, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv39_paddr_pgofscbde8c5af7576e92ba5fca9143abbb66.tex b/sail_latex_riscv/fnz_set_sv39_paddr_pgofscbde8c5af7576e92ba5fca9143abbb66.tex new file mode 100644 index 00000000..6524a1e2 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv39_paddr_pgofscbde8c5af7576e92ba5fca9143abbb66.tex @@ -0,0 +1,5 @@ +function _set_SV39_Paddr_PgOfs (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV39_Paddr_chunk_0 = update_subrange_bits(r.SV39_Paddr_chunk_0, 11, 0, subrange_bits(v, 11, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv39_paddr_ppni179def635ee83e4cac60b403fcd2e376.tex b/sail_latex_riscv/fnz_set_sv39_paddr_ppni179def635ee83e4cac60b403fcd2e376.tex new file mode 100644 index 00000000..bd565c25 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv39_paddr_ppni179def635ee83e4cac60b403fcd2e376.tex @@ -0,0 +1,5 @@ +function _set_SV39_Paddr_PPNi (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV39_Paddr_chunk_0 = update_subrange_bits(r.SV39_Paddr_chunk_0, 55, 12, subrange_bits(v, 43, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv39_pte_bitsde1d8d06cbfb62b5b9924a167cdc23ec.tex b/sail_latex_riscv/fnz_set_sv39_pte_bitsde1d8d06cbfb62b5b9924a167cdc23ec.tex new file mode 100644 index 00000000..1df40d59 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv39_pte_bitsde1d8d06cbfb62b5b9924a167cdc23ec.tex @@ -0,0 +1,5 @@ +function _set_SV39_PTE_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV39_PTE_chunk_0 = update_subrange_bits(r.SV39_PTE_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv39_pte_bitse9589b312fc9f713a1d54dadb5f0e45d.tex b/sail_latex_riscv/fnz_set_sv39_pte_bitse9589b312fc9f713a1d54dadb5f0e45d.tex new file mode 100644 index 00000000..60344c4f --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv39_pte_bitse9589b312fc9f713a1d54dadb5f0e45d.tex @@ -0,0 +1,5 @@ +function _set_SV39_PTE_BITS (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV39_PTE_chunk_0 = update_subrange_bits(r.SV39_PTE_chunk_0, 7, 0, subrange_bits(v, 7, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv39_pte_ext579db3d4726a0e68687d2bef859f8658.tex b/sail_latex_riscv/fnz_set_sv39_pte_ext579db3d4726a0e68687d2bef859f8658.tex new file mode 100644 index 00000000..b2a88d75 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv39_pte_ext579db3d4726a0e68687d2bef859f8658.tex @@ -0,0 +1,5 @@ +function _set_SV39_PTE_Ext (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV39_PTE_chunk_0 = update_subrange_bits(r.SV39_PTE_chunk_0, 63, 54, subrange_bits(v, 9, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv39_pte_ppnif74fb7c03da31075e81899e241f18909.tex b/sail_latex_riscv/fnz_set_sv39_pte_ppnif74fb7c03da31075e81899e241f18909.tex new file mode 100644 index 00000000..af6af619 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv39_pte_ppnif74fb7c03da31075e81899e241f18909.tex @@ -0,0 +1,5 @@ +function _set_SV39_PTE_PPNi (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV39_PTE_chunk_0 = update_subrange_bits(r.SV39_PTE_chunk_0, 53, 10, subrange_bits(v, 43, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv39_pte_rsw9dcf0d2943fb66aef30725a715b1c011.tex b/sail_latex_riscv/fnz_set_sv39_pte_rsw9dcf0d2943fb66aef30725a715b1c011.tex new file mode 100644 index 00000000..1db8a5f5 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv39_pte_rsw9dcf0d2943fb66aef30725a715b1c011.tex @@ -0,0 +1,5 @@ +function _set_SV39_PTE_RSW (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV39_PTE_chunk_0 = update_subrange_bits(r.SV39_PTE_chunk_0, 9, 8, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv39_vaddr_bits9dda733adeb14d86c90ae7719235d0bc.tex b/sail_latex_riscv/fnz_set_sv39_vaddr_bits9dda733adeb14d86c90ae7719235d0bc.tex new file mode 100644 index 00000000..6870dd57 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv39_vaddr_bits9dda733adeb14d86c90ae7719235d0bc.tex @@ -0,0 +1,5 @@ +function _set_SV39_Vaddr_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV39_Vaddr_chunk_0 = update_subrange_bits(r.SV39_Vaddr_chunk_0, 38, 0, subrange_bits(v, 38, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv39_vaddr_pgofs10da37447f07e7766bd99c3f4712450e.tex b/sail_latex_riscv/fnz_set_sv39_vaddr_pgofs10da37447f07e7766bd99c3f4712450e.tex new file mode 100644 index 00000000..e8c62ef9 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv39_vaddr_pgofs10da37447f07e7766bd99c3f4712450e.tex @@ -0,0 +1,5 @@ +function _set_SV39_Vaddr_PgOfs (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV39_Vaddr_chunk_0 = update_subrange_bits(r.SV39_Vaddr_chunk_0, 11, 0, subrange_bits(v, 11, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv39_vaddr_vpni862fded28960b086e268044e94d900bd.tex b/sail_latex_riscv/fnz_set_sv39_vaddr_vpni862fded28960b086e268044e94d900bd.tex new file mode 100644 index 00000000..fe380d8a --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv39_vaddr_vpni862fded28960b086e268044e94d900bd.tex @@ -0,0 +1,5 @@ +function _set_SV39_Vaddr_VPNi (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV39_Vaddr_chunk_0 = update_subrange_bits(r.SV39_Vaddr_chunk_0, 38, 12, subrange_bits(v, 26, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv48_paddr_bits50513db01891b630792f1d6a843c784b.tex b/sail_latex_riscv/fnz_set_sv48_paddr_bits50513db01891b630792f1d6a843c784b.tex new file mode 100644 index 00000000..5efc75df --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv48_paddr_bits50513db01891b630792f1d6a843c784b.tex @@ -0,0 +1,5 @@ +function _set_SV48_Paddr_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV48_Paddr_chunk_0 = update_subrange_bits(r.SV48_Paddr_chunk_0, 55, 0, subrange_bits(v, 55, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv48_paddr_pgofs562f79909d47d2b0eba8ebce320e03c4.tex b/sail_latex_riscv/fnz_set_sv48_paddr_pgofs562f79909d47d2b0eba8ebce320e03c4.tex new file mode 100644 index 00000000..8a984037 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv48_paddr_pgofs562f79909d47d2b0eba8ebce320e03c4.tex @@ -0,0 +1,5 @@ +function _set_SV48_Paddr_PgOfs (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV48_Paddr_chunk_0 = update_subrange_bits(r.SV48_Paddr_chunk_0, 11, 0, subrange_bits(v, 11, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv48_paddr_ppni6d70c043fcdc253e5c9daadde935dc78.tex b/sail_latex_riscv/fnz_set_sv48_paddr_ppni6d70c043fcdc253e5c9daadde935dc78.tex new file mode 100644 index 00000000..f54e4cba --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv48_paddr_ppni6d70c043fcdc253e5c9daadde935dc78.tex @@ -0,0 +1,5 @@ +function _set_SV48_Paddr_PPNi (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV48_Paddr_chunk_0 = update_subrange_bits(r.SV48_Paddr_chunk_0, 55, 12, subrange_bits(v, 43, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv48_pte_bits0b444a773ec492c3163a73656822756d.tex b/sail_latex_riscv/fnz_set_sv48_pte_bits0b444a773ec492c3163a73656822756d.tex new file mode 100644 index 00000000..f3af8d3f --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv48_pte_bits0b444a773ec492c3163a73656822756d.tex @@ -0,0 +1,5 @@ +function _set_SV48_PTE_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV48_PTE_chunk_0 = update_subrange_bits(r.SV48_PTE_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv48_pte_bitsad0cc90eccc969a6500100c935bee630.tex b/sail_latex_riscv/fnz_set_sv48_pte_bitsad0cc90eccc969a6500100c935bee630.tex new file mode 100644 index 00000000..4c9e664a --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv48_pte_bitsad0cc90eccc969a6500100c935bee630.tex @@ -0,0 +1,5 @@ +function _set_SV48_PTE_BITS (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV48_PTE_chunk_0 = update_subrange_bits(r.SV48_PTE_chunk_0, 7, 0, subrange_bits(v, 7, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv48_pte_ext6ca7bfb443ac18c8ef730a785a66e223.tex b/sail_latex_riscv/fnz_set_sv48_pte_ext6ca7bfb443ac18c8ef730a785a66e223.tex new file mode 100644 index 00000000..cca5170e --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv48_pte_ext6ca7bfb443ac18c8ef730a785a66e223.tex @@ -0,0 +1,5 @@ +function _set_SV48_PTE_Ext (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV48_PTE_chunk_0 = update_subrange_bits(r.SV48_PTE_chunk_0, 63, 54, subrange_bits(v, 9, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv48_pte_ppnif14b23da9aa27f230829cd1afd9a766b.tex b/sail_latex_riscv/fnz_set_sv48_pte_ppnif14b23da9aa27f230829cd1afd9a766b.tex new file mode 100644 index 00000000..c7d1891d --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv48_pte_ppnif14b23da9aa27f230829cd1afd9a766b.tex @@ -0,0 +1,5 @@ +function _set_SV48_PTE_PPNi (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV48_PTE_chunk_0 = update_subrange_bits(r.SV48_PTE_chunk_0, 53, 10, subrange_bits(v, 43, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv48_pte_rswc91c2908d341bbe5216582c940bf7837.tex b/sail_latex_riscv/fnz_set_sv48_pte_rswc91c2908d341bbe5216582c940bf7837.tex new file mode 100644 index 00000000..0602224d --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv48_pte_rswc91c2908d341bbe5216582c940bf7837.tex @@ -0,0 +1,5 @@ +function _set_SV48_PTE_RSW (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV48_PTE_chunk_0 = update_subrange_bits(r.SV48_PTE_chunk_0, 9, 8, subrange_bits(v, 1, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv48_vaddr_bitsd37e2d8f1c88cf733caeb08edd844785.tex b/sail_latex_riscv/fnz_set_sv48_vaddr_bitsd37e2d8f1c88cf733caeb08edd844785.tex new file mode 100644 index 00000000..646053a5 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv48_vaddr_bitsd37e2d8f1c88cf733caeb08edd844785.tex @@ -0,0 +1,5 @@ +function _set_SV48_Vaddr_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV48_Vaddr_chunk_0 = update_subrange_bits(r.SV48_Vaddr_chunk_0, 47, 0, subrange_bits(v, 47, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv48_vaddr_pgofsed661e13958cf27c80315e6cd60b8a36.tex b/sail_latex_riscv/fnz_set_sv48_vaddr_pgofsed661e13958cf27c80315e6cd60b8a36.tex new file mode 100644 index 00000000..e56391f2 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv48_vaddr_pgofsed661e13958cf27c80315e6cd60b8a36.tex @@ -0,0 +1,5 @@ +function _set_SV48_Vaddr_PgOfs (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV48_Vaddr_chunk_0 = update_subrange_bits(r.SV48_Vaddr_chunk_0, 11, 0, subrange_bits(v, 11, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_sv48_vaddr_vpni49c5d04a526f6722627d07f53e7f09dc.tex b/sail_latex_riscv/fnz_set_sv48_vaddr_vpni49c5d04a526f6722627d07f53e7f09dc.tex new file mode 100644 index 00000000..805fad24 --- /dev/null +++ b/sail_latex_riscv/fnz_set_sv48_vaddr_vpni49c5d04a526f6722627d07f53e7f09dc.tex @@ -0,0 +1,5 @@ +function _set_SV48_Vaddr_VPNi (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.SV48_Vaddr_chunk_0 = update_subrange_bits(r.SV48_Vaddr_chunk_0, 38, 12, subrange_bits(v, 26, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_uinterrupts_bits727060290947315f91798504a8e1220d.tex b/sail_latex_riscv/fnz_set_uinterrupts_bits727060290947315f91798504a8e1220d.tex new file mode 100644 index 00000000..f5ca3823 --- /dev/null +++ b/sail_latex_riscv/fnz_set_uinterrupts_bits727060290947315f91798504a8e1220d.tex @@ -0,0 +1,5 @@ +function _set_Uinterrupts_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Uinterrupts_chunk_0 = update_subrange_bits(r.Uinterrupts_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_uinterrupts_uei6395a09166c9287c4cbab9ca7e87e0bd.tex b/sail_latex_riscv/fnz_set_uinterrupts_uei6395a09166c9287c4cbab9ca7e87e0bd.tex new file mode 100644 index 00000000..fafd1449 --- /dev/null +++ b/sail_latex_riscv/fnz_set_uinterrupts_uei6395a09166c9287c4cbab9ca7e87e0bd.tex @@ -0,0 +1,5 @@ +function _set_Uinterrupts_UEI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Uinterrupts_chunk_0 = update_subrange_bits(r.Uinterrupts_chunk_0, 8, 8, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_uinterrupts_usi8050a61e8750bb4582bb9dda39b65457.tex b/sail_latex_riscv/fnz_set_uinterrupts_usi8050a61e8750bb4582bb9dda39b65457.tex new file mode 100644 index 00000000..76f47379 --- /dev/null +++ b/sail_latex_riscv/fnz_set_uinterrupts_usi8050a61e8750bb4582bb9dda39b65457.tex @@ -0,0 +1,5 @@ +function _set_Uinterrupts_USI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Uinterrupts_chunk_0 = update_subrange_bits(r.Uinterrupts_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_uinterrupts_uti74ee6b037b2bfa28007515ce9e1e9566.tex b/sail_latex_riscv/fnz_set_uinterrupts_uti74ee6b037b2bfa28007515ce9e1e9566.tex new file mode 100644 index 00000000..daf78453 --- /dev/null +++ b/sail_latex_riscv/fnz_set_uinterrupts_uti74ee6b037b2bfa28007515ce9e1e9566.tex @@ -0,0 +1,5 @@ +function _set_Uinterrupts_UTI (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Uinterrupts_chunk_0 = update_subrange_bits(r.Uinterrupts_chunk_0, 4, 4, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_ustatus_bits30b27147d374fd2bd7fadc954e833c3f.tex b/sail_latex_riscv/fnz_set_ustatus_bits30b27147d374fd2bd7fadc954e833c3f.tex new file mode 100644 index 00000000..86f1483e --- /dev/null +++ b/sail_latex_riscv/fnz_set_ustatus_bits30b27147d374fd2bd7fadc954e833c3f.tex @@ -0,0 +1,5 @@ +function _set_Ustatus_bits (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Ustatus_chunk_0 = update_subrange_bits(r.Ustatus_chunk_0, 63, 0, subrange_bits(v, 63, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_ustatus_uied66ad7f688ead51a86b377a82d67ff47.tex b/sail_latex_riscv/fnz_set_ustatus_uied66ad7f688ead51a86b377a82d67ff47.tex new file mode 100644 index 00000000..5b10d398 --- /dev/null +++ b/sail_latex_riscv/fnz_set_ustatus_uied66ad7f688ead51a86b377a82d67ff47.tex @@ -0,0 +1,5 @@ +function _set_Ustatus_UIE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Ustatus_chunk_0 = update_subrange_bits(r.Ustatus_chunk_0, 0, 0, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_set_ustatus_upie36655d5ae32856b4d8e9eefbf763af27.tex b/sail_latex_riscv/fnz_set_ustatus_upie36655d5ae32856b4d8e9eefbf763af27.tex new file mode 100644 index 00000000..f34caaa4 --- /dev/null +++ b/sail_latex_riscv/fnz_set_ustatus_upie36655d5ae32856b4d8e9eefbf763af27.tex @@ -0,0 +1,5 @@ +function _set_Ustatus_UPIE (r_ref, v) = { + r = __bitfield_deref(r_ref); + r.Ustatus_chunk_0 = update_subrange_bits(r.Ustatus_chunk_0, 4, 4, subrange_bits(v, 0, 0)); + (*r_ref) = r +} diff --git a/sail_latex_riscv/fnz_update_ccsr_bitscab95b9f107541973f0ca10985835467.tex b/sail_latex_riscv/fnz_update_ccsr_bitscab95b9f107541973f0ca10985835467.tex new file mode 100644 index 00000000..b03f9769 --- /dev/null +++ b/sail_latex_riscv/fnz_update_ccsr_bitscab95b9f107541973f0ca10985835467.tex @@ -0,0 +1,2 @@ +function _update_ccsr_bits (v, x) = let v = { v with ccsr_chunk_0 = update_subrange_bits(v.ccsr_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_ccsr_cap_idxcf97e2a26597f29b63eaa57befa11cea.tex b/sail_latex_riscv/fnz_update_ccsr_cap_idxcf97e2a26597f29b63eaa57befa11cea.tex new file mode 100644 index 00000000..478b6b0b --- /dev/null +++ b/sail_latex_riscv/fnz_update_ccsr_cap_idxcf97e2a26597f29b63eaa57befa11cea.tex @@ -0,0 +1,2 @@ +function _update_ccsr_cap_idx (v, x) = let v = { v with ccsr_chunk_0 = update_subrange_bits(v.ccsr_chunk_0, 15, 10, subrange_bits(x, 5, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_ccsr_causecd8b7254c686be403e4e906a346f4642.tex b/sail_latex_riscv/fnz_update_ccsr_causecd8b7254c686be403e4e906a346f4642.tex new file mode 100644 index 00000000..86d30aed --- /dev/null +++ b/sail_latex_riscv/fnz_update_ccsr_causecd8b7254c686be403e4e906a346f4642.tex @@ -0,0 +1,2 @@ +function _update_ccsr_cause (v, x) = let v = { v with ccsr_chunk_0 = update_subrange_bits(v.ccsr_chunk_0, 9, 5, subrange_bits(x, 4, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_ccsr_dad4c6c7e8973232b0249a9b870dab8b8.tex b/sail_latex_riscv/fnz_update_ccsr_dad4c6c7e8973232b0249a9b870dab8b8.tex new file mode 100644 index 00000000..45c191f7 --- /dev/null +++ b/sail_latex_riscv/fnz_update_ccsr_dad4c6c7e8973232b0249a9b870dab8b8.tex @@ -0,0 +1,2 @@ +function _update_ccsr_d (v, x) = let v = { v with ccsr_chunk_0 = update_subrange_bits(v.ccsr_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_ccsr_e79adbf3ff342d3a9fc182dd2dd614be3.tex b/sail_latex_riscv/fnz_update_ccsr_e79adbf3ff342d3a9fc182dd2dd614be3.tex new file mode 100644 index 00000000..733bdd6b --- /dev/null +++ b/sail_latex_riscv/fnz_update_ccsr_e79adbf3ff342d3a9fc182dd2dd614be3.tex @@ -0,0 +1,2 @@ +function _update_ccsr_e (v, x) = let v = { v with ccsr_chunk_0 = update_subrange_bits(v.ccsr_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_counteren_bitsab054ba63ba12cbce69135a6de8c9fad.tex b/sail_latex_riscv/fnz_update_counteren_bitsab054ba63ba12cbce69135a6de8c9fad.tex new file mode 100644 index 00000000..c246e3fe --- /dev/null +++ b/sail_latex_riscv/fnz_update_counteren_bitsab054ba63ba12cbce69135a6de8c9fad.tex @@ -0,0 +1,2 @@ +function _update_Counteren_bits (v, x) = let v = { v with Counteren_chunk_0 = update_subrange_bits(v.Counteren_chunk_0, 31, 0, subrange_bits(x, 31, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_counteren_cyb4f1e37eac32f7b9365943e5600beec9.tex b/sail_latex_riscv/fnz_update_counteren_cyb4f1e37eac32f7b9365943e5600beec9.tex new file mode 100644 index 00000000..893d54d6 --- /dev/null +++ b/sail_latex_riscv/fnz_update_counteren_cyb4f1e37eac32f7b9365943e5600beec9.tex @@ -0,0 +1,2 @@ +function _update_Counteren_CY (v, x) = let v = { v with Counteren_chunk_0 = update_subrange_bits(v.Counteren_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_counteren_hpma99adbaf80dd358f59495d6ca7717d3b.tex b/sail_latex_riscv/fnz_update_counteren_hpma99adbaf80dd358f59495d6ca7717d3b.tex new file mode 100644 index 00000000..3f492313 --- /dev/null +++ b/sail_latex_riscv/fnz_update_counteren_hpma99adbaf80dd358f59495d6ca7717d3b.tex @@ -0,0 +1,2 @@ +function _update_Counteren_HPM (v, x) = let v = { v with Counteren_chunk_0 = update_subrange_bits(v.Counteren_chunk_0, 31, 3, subrange_bits(x, 28, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_counteren_ir66176b4373b2eec827fbf9030a5406d0.tex b/sail_latex_riscv/fnz_update_counteren_ir66176b4373b2eec827fbf9030a5406d0.tex new file mode 100644 index 00000000..209cf9b8 --- /dev/null +++ b/sail_latex_riscv/fnz_update_counteren_ir66176b4373b2eec827fbf9030a5406d0.tex @@ -0,0 +1,2 @@ +function _update_Counteren_IR (v, x) = let v = { v with Counteren_chunk_0 = update_subrange_bits(v.Counteren_chunk_0, 2, 2, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_counteren_tmab580665d1404d6531c604b4b0827504.tex b/sail_latex_riscv/fnz_update_counteren_tmab580665d1404d6531c604b4b0827504.tex new file mode 100644 index 00000000..5d4a0da5 --- /dev/null +++ b/sail_latex_riscv/fnz_update_counteren_tmab580665d1404d6531c604b4b0827504.tex @@ -0,0 +1,2 @@ +function _update_Counteren_TM (v, x) = let v = { v with Counteren_chunk_0 = update_subrange_bits(v.Counteren_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_counterin_bits2487a90cdc32df9b1556a37b4d85fe52.tex b/sail_latex_riscv/fnz_update_counterin_bits2487a90cdc32df9b1556a37b4d85fe52.tex new file mode 100644 index 00000000..821c5d59 --- /dev/null +++ b/sail_latex_riscv/fnz_update_counterin_bits2487a90cdc32df9b1556a37b4d85fe52.tex @@ -0,0 +1,2 @@ +function _update_Counterin_bits (v, x) = let v = { v with Counterin_chunk_0 = update_subrange_bits(v.Counterin_chunk_0, 31, 0, subrange_bits(x, 31, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_counterin_cy16506512e1a71f4a75459533622c36ab.tex b/sail_latex_riscv/fnz_update_counterin_cy16506512e1a71f4a75459533622c36ab.tex new file mode 100644 index 00000000..c6c8c17d --- /dev/null +++ b/sail_latex_riscv/fnz_update_counterin_cy16506512e1a71f4a75459533622c36ab.tex @@ -0,0 +1,2 @@ +function _update_Counterin_CY (v, x) = let v = { v with Counterin_chunk_0 = update_subrange_bits(v.Counterin_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_counterin_ire83041be7a3bb70aa6f359785f4856ef.tex b/sail_latex_riscv/fnz_update_counterin_ire83041be7a3bb70aa6f359785f4856ef.tex new file mode 100644 index 00000000..8d049e45 --- /dev/null +++ b/sail_latex_riscv/fnz_update_counterin_ire83041be7a3bb70aa6f359785f4856ef.tex @@ -0,0 +1,2 @@ +function _update_Counterin_IR (v, x) = let v = { v with Counterin_chunk_0 = update_subrange_bits(v.Counterin_chunk_0, 2, 2, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_ext_pte_bits_bits5b635310b9455d491454822f0311285b.tex b/sail_latex_riscv/fnz_update_ext_pte_bits_bits5b635310b9455d491454822f0311285b.tex new file mode 100644 index 00000000..3ef88331 --- /dev/null +++ b/sail_latex_riscv/fnz_update_ext_pte_bits_bits5b635310b9455d491454822f0311285b.tex @@ -0,0 +1,2 @@ +function _update_Ext_PTE_Bits_bits (v, x) = let v = { v with Ext_PTE_Bits_chunk_0 = update_subrange_bits(v.Ext_PTE_Bits_chunk_0, 9, 0, subrange_bits(x, 9, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_ext_pte_bits_capreadb593f0e07fbd2201e626b373cddf00e2.tex b/sail_latex_riscv/fnz_update_ext_pte_bits_capreadb593f0e07fbd2201e626b373cddf00e2.tex new file mode 100644 index 00000000..f3a7fbf3 --- /dev/null +++ b/sail_latex_riscv/fnz_update_ext_pte_bits_capreadb593f0e07fbd2201e626b373cddf00e2.tex @@ -0,0 +1,2 @@ +function _update_Ext_PTE_Bits_CapRead (v, x) = let v = { v with Ext_PTE_Bits_chunk_0 = update_subrange_bits(v.Ext_PTE_Bits_chunk_0, 8, 8, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_ext_pte_bits_capwritedcd59d2d59ab5341029d35f94ab8d27f.tex b/sail_latex_riscv/fnz_update_ext_pte_bits_capwritedcd59d2d59ab5341029d35f94ab8d27f.tex new file mode 100644 index 00000000..177a39cd --- /dev/null +++ b/sail_latex_riscv/fnz_update_ext_pte_bits_capwritedcd59d2d59ab5341029d35f94ab8d27f.tex @@ -0,0 +1,2 @@ +function _update_Ext_PTE_Bits_CapWrite (v, x) = let v = { v with Ext_PTE_Bits_chunk_0 = update_subrange_bits(v.Ext_PTE_Bits_chunk_0, 9, 9, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_fcsr_bitsd93593273c229b56f42c5419848120a5.tex b/sail_latex_riscv/fnz_update_fcsr_bitsd93593273c229b56f42c5419848120a5.tex new file mode 100644 index 00000000..8dd461ab --- /dev/null +++ b/sail_latex_riscv/fnz_update_fcsr_bitsd93593273c229b56f42c5419848120a5.tex @@ -0,0 +1,2 @@ +function _update_Fcsr_bits (v, x) = let v = { v with Fcsr_chunk_0 = update_subrange_bits(v.Fcsr_chunk_0, 31, 0, subrange_bits(x, 31, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_fcsr_fflags358f6ae3cab298c0e35ab7d81a328b5f.tex b/sail_latex_riscv/fnz_update_fcsr_fflags358f6ae3cab298c0e35ab7d81a328b5f.tex new file mode 100644 index 00000000..c145198c --- /dev/null +++ b/sail_latex_riscv/fnz_update_fcsr_fflags358f6ae3cab298c0e35ab7d81a328b5f.tex @@ -0,0 +1,2 @@ +function _update_Fcsr_FFLAGS (v, x) = let v = { v with Fcsr_chunk_0 = update_subrange_bits(v.Fcsr_chunk_0, 4, 0, subrange_bits(x, 4, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_fcsr_frmdde96c8b780c41e6aa00deb4160779be.tex b/sail_latex_riscv/fnz_update_fcsr_frmdde96c8b780c41e6aa00deb4160779be.tex new file mode 100644 index 00000000..ed067911 --- /dev/null +++ b/sail_latex_riscv/fnz_update_fcsr_frmdde96c8b780c41e6aa00deb4160779be.tex @@ -0,0 +1,2 @@ +function _update_Fcsr_FRM (v, x) = let v = { v with Fcsr_chunk_0 = update_subrange_bits(v.Fcsr_chunk_0, 7, 5, subrange_bits(x, 2, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_htif_cmd_bitsf4016ddf8b504ce2ad50554db668de5e.tex b/sail_latex_riscv/fnz_update_htif_cmd_bitsf4016ddf8b504ce2ad50554db668de5e.tex new file mode 100644 index 00000000..ad96fcb7 --- /dev/null +++ b/sail_latex_riscv/fnz_update_htif_cmd_bitsf4016ddf8b504ce2ad50554db668de5e.tex @@ -0,0 +1,2 @@ +function _update_htif_cmd_bits (v, x) = let v = { v with htif_cmd_chunk_0 = update_subrange_bits(v.htif_cmd_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_htif_cmd_cmd6ec3dd793a5d6eea4a6de9c247ff1ed7.tex b/sail_latex_riscv/fnz_update_htif_cmd_cmd6ec3dd793a5d6eea4a6de9c247ff1ed7.tex new file mode 100644 index 00000000..24262624 --- /dev/null +++ b/sail_latex_riscv/fnz_update_htif_cmd_cmd6ec3dd793a5d6eea4a6de9c247ff1ed7.tex @@ -0,0 +1,2 @@ +function _update_htif_cmd_cmd (v, x) = let v = { v with htif_cmd_chunk_0 = update_subrange_bits(v.htif_cmd_chunk_0, 55, 48, subrange_bits(x, 7, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_htif_cmd_device37d8d93e2615eb16246d9d3624507e12.tex b/sail_latex_riscv/fnz_update_htif_cmd_device37d8d93e2615eb16246d9d3624507e12.tex new file mode 100644 index 00000000..d5d1820d --- /dev/null +++ b/sail_latex_riscv/fnz_update_htif_cmd_device37d8d93e2615eb16246d9d3624507e12.tex @@ -0,0 +1,2 @@ +function _update_htif_cmd_device (v, x) = let v = { v with htif_cmd_chunk_0 = update_subrange_bits(v.htif_cmd_chunk_0, 63, 56, subrange_bits(x, 7, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_htif_cmd_payloadf8c76e11f35c2157b590a60e4678b1cc.tex b/sail_latex_riscv/fnz_update_htif_cmd_payloadf8c76e11f35c2157b590a60e4678b1cc.tex new file mode 100644 index 00000000..5dfc79da --- /dev/null +++ b/sail_latex_riscv/fnz_update_htif_cmd_payloadf8c76e11f35c2157b590a60e4678b1cc.tex @@ -0,0 +1,2 @@ +function _update_htif_cmd_payload (v, x) = let v = { v with htif_cmd_chunk_0 = update_subrange_bits(v.htif_cmd_chunk_0, 47, 0, subrange_bits(x, 47, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mcause_bitsf7e305192beebf30554f7e43f12ae4ed.tex b/sail_latex_riscv/fnz_update_mcause_bitsf7e305192beebf30554f7e43f12ae4ed.tex new file mode 100644 index 00000000..9e439ef6 --- /dev/null +++ b/sail_latex_riscv/fnz_update_mcause_bitsf7e305192beebf30554f7e43f12ae4ed.tex @@ -0,0 +1,2 @@ +function _update_Mcause_bits (v, x) = let v = { v with Mcause_chunk_0 = update_subrange_bits(v.Mcause_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mcause_cause36f08972c0051221257ac44d915e866d.tex b/sail_latex_riscv/fnz_update_mcause_cause36f08972c0051221257ac44d915e866d.tex new file mode 100644 index 00000000..3e0ba9d9 --- /dev/null +++ b/sail_latex_riscv/fnz_update_mcause_cause36f08972c0051221257ac44d915e866d.tex @@ -0,0 +1,2 @@ +function _update_Mcause_Cause (v, x) = let v = { v with Mcause_chunk_0 = update_subrange_bits(v.Mcause_chunk_0, 62, 0, subrange_bits(x, 62, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mcause_isinterrupt642fe02b577ce4d39155750b612ad77c.tex b/sail_latex_riscv/fnz_update_mcause_isinterrupt642fe02b577ce4d39155750b612ad77c.tex new file mode 100644 index 00000000..4c5c6599 --- /dev/null +++ b/sail_latex_riscv/fnz_update_mcause_isinterrupt642fe02b577ce4d39155750b612ad77c.tex @@ -0,0 +1,2 @@ +function _update_Mcause_IsInterrupt (v, x) = let v = { v with Mcause_chunk_0 = update_subrange_bits(v.Mcause_chunk_0, 63, 63, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_bitsf3dc3e6f3f131d1cc6e32b1c37c8cdde.tex b/sail_latex_riscv/fnz_update_medeleg_bitsf3dc3e6f3f131d1cc6e32b1c37c8cdde.tex new file mode 100644 index 00000000..660c426f --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_bitsf3dc3e6f3f131d1cc6e32b1c37c8cdde.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_bits (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_breakpointbd84cf9145e5e18dc467f4a838f67957.tex b/sail_latex_riscv/fnz_update_medeleg_breakpointbd84cf9145e5e18dc467f4a838f67957.tex new file mode 100644 index 00000000..72870478 --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_breakpointbd84cf9145e5e18dc467f4a838f67957.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_Breakpoint (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 3, 3, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_fetch_access_fault31fef2dab7b4fcdd2b8d5a549f3df1ee.tex b/sail_latex_riscv/fnz_update_medeleg_fetch_access_fault31fef2dab7b4fcdd2b8d5a549f3df1ee.tex new file mode 100644 index 00000000..f7add7e1 --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_fetch_access_fault31fef2dab7b4fcdd2b8d5a549f3df1ee.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_Fetch_Access_Fault (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_fetch_addr_aligna193083f9170990caf0b815723cfe4f5.tex b/sail_latex_riscv/fnz_update_medeleg_fetch_addr_aligna193083f9170990caf0b815723cfe4f5.tex new file mode 100644 index 00000000..e5efa239 --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_fetch_addr_aligna193083f9170990caf0b815723cfe4f5.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_Fetch_Addr_Align (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_fetch_page_faulta2bc84a2cd9018bb44ab5c81423ca187.tex b/sail_latex_riscv/fnz_update_medeleg_fetch_page_faulta2bc84a2cd9018bb44ab5c81423ca187.tex new file mode 100644 index 00000000..6dec14e5 --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_fetch_page_faulta2bc84a2cd9018bb44ab5c81423ca187.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_Fetch_Page_Fault (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 12, 12, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_illegal_instr1f275bdf5831e7748612e30e7fc1ce66.tex b/sail_latex_riscv/fnz_update_medeleg_illegal_instr1f275bdf5831e7748612e30e7fc1ce66.tex new file mode 100644 index 00000000..0745d92b --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_illegal_instr1f275bdf5831e7748612e30e7fc1ce66.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_Illegal_Instr (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 2, 2, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_load_access_faultf83e5fdaf6895717efc1bb0820a40bcc.tex b/sail_latex_riscv/fnz_update_medeleg_load_access_faultf83e5fdaf6895717efc1bb0820a40bcc.tex new file mode 100644 index 00000000..0c353b28 --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_load_access_faultf83e5fdaf6895717efc1bb0820a40bcc.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_Load_Access_Fault (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 5, 5, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_load_addr_alignae797c478ddd9ca50ad25f75c4177b59.tex b/sail_latex_riscv/fnz_update_medeleg_load_addr_alignae797c478ddd9ca50ad25f75c4177b59.tex new file mode 100644 index 00000000..2105f51f --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_load_addr_alignae797c478ddd9ca50ad25f75c4177b59.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_Load_Addr_Align (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 4, 4, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_load_page_faultf06c6ed3cf5f5fb5c53b68b1755f26be.tex b/sail_latex_riscv/fnz_update_medeleg_load_page_faultf06c6ed3cf5f5fb5c53b68b1755f26be.tex new file mode 100644 index 00000000..76e4da56 --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_load_page_faultf06c6ed3cf5f5fb5c53b68b1755f26be.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_Load_Page_Fault (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 13, 13, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_menvcall2d8b71da00a8a28b5fb607a33f36612f.tex b/sail_latex_riscv/fnz_update_medeleg_menvcall2d8b71da00a8a28b5fb607a33f36612f.tex new file mode 100644 index 00000000..6317a2eb --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_menvcall2d8b71da00a8a28b5fb607a33f36612f.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_MEnvCall (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 10, 10, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_samo_access_fault6974daf13df1fa6adbf6f8461fbb31e1.tex b/sail_latex_riscv/fnz_update_medeleg_samo_access_fault6974daf13df1fa6adbf6f8461fbb31e1.tex new file mode 100644 index 00000000..53298489 --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_samo_access_fault6974daf13df1fa6adbf6f8461fbb31e1.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_SAMO_Access_Fault (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 7, 7, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_samo_addr_alignfbf844afddf59029f1bfa6e7730e572d.tex b/sail_latex_riscv/fnz_update_medeleg_samo_addr_alignfbf844afddf59029f1bfa6e7730e572d.tex new file mode 100644 index 00000000..e9194c09 --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_samo_addr_alignfbf844afddf59029f1bfa6e7730e572d.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_SAMO_Addr_Align (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 6, 6, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_samo_page_fault0f5a6e51d39c262ed16dd03fd0f6fd33.tex b/sail_latex_riscv/fnz_update_medeleg_samo_page_fault0f5a6e51d39c262ed16dd03fd0f6fd33.tex new file mode 100644 index 00000000..5c7c67d3 --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_samo_page_fault0f5a6e51d39c262ed16dd03fd0f6fd33.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_SAMO_Page_Fault (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 15, 15, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_senvcalld3587b88d31060a18775842e14fa2e28.tex b/sail_latex_riscv/fnz_update_medeleg_senvcalld3587b88d31060a18775842e14fa2e28.tex new file mode 100644 index 00000000..fc8be55f --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_senvcalld3587b88d31060a18775842e14fa2e28.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_SEnvCall (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 9, 9, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_medeleg_uenvcalle92cde6b912da5ac5a47cd901345bbf9.tex b/sail_latex_riscv/fnz_update_medeleg_uenvcalle92cde6b912da5ac5a47cd901345bbf9.tex new file mode 100644 index 00000000..829974b9 --- /dev/null +++ b/sail_latex_riscv/fnz_update_medeleg_uenvcalle92cde6b912da5ac5a47cd901345bbf9.tex @@ -0,0 +1,2 @@ +function _update_Medeleg_UEnvCall (v, x) = let v = { v with Medeleg_chunk_0 = update_subrange_bits(v.Medeleg_chunk_0, 8, 8, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_minterrupts_bitsd26668b9d73aea27c77c64039eabb63d.tex b/sail_latex_riscv/fnz_update_minterrupts_bitsd26668b9d73aea27c77c64039eabb63d.tex new file mode 100644 index 00000000..17a53d45 --- /dev/null +++ b/sail_latex_riscv/fnz_update_minterrupts_bitsd26668b9d73aea27c77c64039eabb63d.tex @@ -0,0 +1,2 @@ +function _update_Minterrupts_bits (v, x) = let v = { v with Minterrupts_chunk_0 = update_subrange_bits(v.Minterrupts_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_minterrupts_mei7bb6606e9f2d34ff0ba0b340c3513751.tex b/sail_latex_riscv/fnz_update_minterrupts_mei7bb6606e9f2d34ff0ba0b340c3513751.tex new file mode 100644 index 00000000..6718e517 --- /dev/null +++ b/sail_latex_riscv/fnz_update_minterrupts_mei7bb6606e9f2d34ff0ba0b340c3513751.tex @@ -0,0 +1,2 @@ +function _update_Minterrupts_MEI (v, x) = let v = { v with Minterrupts_chunk_0 = update_subrange_bits(v.Minterrupts_chunk_0, 11, 11, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_minterrupts_msib1e866772ecd94b3b9b2c2c19feb2efc.tex b/sail_latex_riscv/fnz_update_minterrupts_msib1e866772ecd94b3b9b2c2c19feb2efc.tex new file mode 100644 index 00000000..8c25ab62 --- /dev/null +++ b/sail_latex_riscv/fnz_update_minterrupts_msib1e866772ecd94b3b9b2c2c19feb2efc.tex @@ -0,0 +1,2 @@ +function _update_Minterrupts_MSI (v, x) = let v = { v with Minterrupts_chunk_0 = update_subrange_bits(v.Minterrupts_chunk_0, 3, 3, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_minterrupts_mtic13c165f79b6b9773ec4f922e35a0ebd.tex b/sail_latex_riscv/fnz_update_minterrupts_mtic13c165f79b6b9773ec4f922e35a0ebd.tex new file mode 100644 index 00000000..47e670a7 --- /dev/null +++ b/sail_latex_riscv/fnz_update_minterrupts_mtic13c165f79b6b9773ec4f922e35a0ebd.tex @@ -0,0 +1,2 @@ +function _update_Minterrupts_MTI (v, x) = let v = { v with Minterrupts_chunk_0 = update_subrange_bits(v.Minterrupts_chunk_0, 7, 7, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_minterrupts_seib6916fd16d950d563a0f6ee65919136c.tex b/sail_latex_riscv/fnz_update_minterrupts_seib6916fd16d950d563a0f6ee65919136c.tex new file mode 100644 index 00000000..f7f26248 --- /dev/null +++ b/sail_latex_riscv/fnz_update_minterrupts_seib6916fd16d950d563a0f6ee65919136c.tex @@ -0,0 +1,2 @@ +function _update_Minterrupts_SEI (v, x) = let v = { v with Minterrupts_chunk_0 = update_subrange_bits(v.Minterrupts_chunk_0, 9, 9, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_minterrupts_ssid8971c54b6d3c79de9fcf8f4e40c9bff.tex b/sail_latex_riscv/fnz_update_minterrupts_ssid8971c54b6d3c79de9fcf8f4e40c9bff.tex new file mode 100644 index 00000000..52a769a8 --- /dev/null +++ b/sail_latex_riscv/fnz_update_minterrupts_ssid8971c54b6d3c79de9fcf8f4e40c9bff.tex @@ -0,0 +1,2 @@ +function _update_Minterrupts_SSI (v, x) = let v = { v with Minterrupts_chunk_0 = update_subrange_bits(v.Minterrupts_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_minterrupts_sti2b202ceb3ff9251d1c300cb53ff1c320.tex b/sail_latex_riscv/fnz_update_minterrupts_sti2b202ceb3ff9251d1c300cb53ff1c320.tex new file mode 100644 index 00000000..b46a069c --- /dev/null +++ b/sail_latex_riscv/fnz_update_minterrupts_sti2b202ceb3ff9251d1c300cb53ff1c320.tex @@ -0,0 +1,2 @@ +function _update_Minterrupts_STI (v, x) = let v = { v with Minterrupts_chunk_0 = update_subrange_bits(v.Minterrupts_chunk_0, 5, 5, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_minterrupts_uei72e8cc258b8ba110b65ac0940a170b2c.tex b/sail_latex_riscv/fnz_update_minterrupts_uei72e8cc258b8ba110b65ac0940a170b2c.tex new file mode 100644 index 00000000..e456bea0 --- /dev/null +++ b/sail_latex_riscv/fnz_update_minterrupts_uei72e8cc258b8ba110b65ac0940a170b2c.tex @@ -0,0 +1,2 @@ +function _update_Minterrupts_UEI (v, x) = let v = { v with Minterrupts_chunk_0 = update_subrange_bits(v.Minterrupts_chunk_0, 8, 8, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_minterrupts_usi77886994f9fcf884ac05c59c57948f29.tex b/sail_latex_riscv/fnz_update_minterrupts_usi77886994f9fcf884ac05c59c57948f29.tex new file mode 100644 index 00000000..0ea5424f --- /dev/null +++ b/sail_latex_riscv/fnz_update_minterrupts_usi77886994f9fcf884ac05c59c57948f29.tex @@ -0,0 +1,2 @@ +function _update_Minterrupts_USI (v, x) = let v = { v with Minterrupts_chunk_0 = update_subrange_bits(v.Minterrupts_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_minterrupts_utiadd0aa7121b36a517ccef2ac029d52ac.tex b/sail_latex_riscv/fnz_update_minterrupts_utiadd0aa7121b36a517ccef2ac029d52ac.tex new file mode 100644 index 00000000..0559ce4b --- /dev/null +++ b/sail_latex_riscv/fnz_update_minterrupts_utiadd0aa7121b36a517ccef2ac029d52ac.tex @@ -0,0 +1,2 @@ +function _update_Minterrupts_UTI (v, x) = let v = { v with Minterrupts_chunk_0 = update_subrange_bits(v.Minterrupts_chunk_0, 4, 4, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_a84a3cc4727896aed6b903b7b0d0caa83.tex b/sail_latex_riscv/fnz_update_misa_a84a3cc4727896aed6b903b7b0d0caa83.tex new file mode 100644 index 00000000..6bc4d0d3 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_a84a3cc4727896aed6b903b7b0d0caa83.tex @@ -0,0 +1,2 @@ +function _update_Misa_A (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_be5486da384cf1d6bc28f1b8e40ddf4ad.tex b/sail_latex_riscv/fnz_update_misa_be5486da384cf1d6bc28f1b8e40ddf4ad.tex new file mode 100644 index 00000000..ef2dbd10 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_be5486da384cf1d6bc28f1b8e40ddf4ad.tex @@ -0,0 +1,2 @@ +function _update_Misa_B (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_bitsf571d9035c480faf7559a6b750d4b5d1.tex b/sail_latex_riscv/fnz_update_misa_bitsf571d9035c480faf7559a6b750d4b5d1.tex new file mode 100644 index 00000000..27a315dc --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_bitsf571d9035c480faf7559a6b750d4b5d1.tex @@ -0,0 +1,2 @@ +function _update_Misa_bits (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_c57e3c86e55b96ffdd3750d922289ff67.tex b/sail_latex_riscv/fnz_update_misa_c57e3c86e55b96ffdd3750d922289ff67.tex new file mode 100644 index 00000000..4d104859 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_c57e3c86e55b96ffdd3750d922289ff67.tex @@ -0,0 +1,2 @@ +function _update_Misa_C (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 2, 2, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_dae3fb84a048be1ee677eb585143660b4.tex b/sail_latex_riscv/fnz_update_misa_dae3fb84a048be1ee677eb585143660b4.tex new file mode 100644 index 00000000..eea8c7c7 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_dae3fb84a048be1ee677eb585143660b4.tex @@ -0,0 +1,2 @@ +function _update_Misa_D (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 3, 3, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_e410ef028122a879e5db0523a611dbfe5.tex b/sail_latex_riscv/fnz_update_misa_e410ef028122a879e5db0523a611dbfe5.tex new file mode 100644 index 00000000..02659f68 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_e410ef028122a879e5db0523a611dbfe5.tex @@ -0,0 +1,2 @@ +function _update_Misa_E (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 4, 4, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_fc88c899133c0200ee42f24494da679a4.tex b/sail_latex_riscv/fnz_update_misa_fc88c899133c0200ee42f24494da679a4.tex new file mode 100644 index 00000000..1ba0e961 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_fc88c899133c0200ee42f24494da679a4.tex @@ -0,0 +1,2 @@ +function _update_Misa_F (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 5, 5, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_g10edea49b1441082ca8d42e45e1480ab.tex b/sail_latex_riscv/fnz_update_misa_g10edea49b1441082ca8d42e45e1480ab.tex new file mode 100644 index 00000000..4b73d85c --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_g10edea49b1441082ca8d42e45e1480ab.tex @@ -0,0 +1,2 @@ +function _update_Misa_G (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 6, 6, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_h360ae205342d957f7a624e4c1114fe8f.tex b/sail_latex_riscv/fnz_update_misa_h360ae205342d957f7a624e4c1114fe8f.tex new file mode 100644 index 00000000..d2bf5f17 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_h360ae205342d957f7a624e4c1114fe8f.tex @@ -0,0 +1,2 @@ +function _update_Misa_H (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 7, 7, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_i139fa4ff8a9c72a06d7ffebdda92436a.tex b/sail_latex_riscv/fnz_update_misa_i139fa4ff8a9c72a06d7ffebdda92436a.tex new file mode 100644 index 00000000..f8039c1c --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_i139fa4ff8a9c72a06d7ffebdda92436a.tex @@ -0,0 +1,2 @@ +function _update_Misa_I (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 8, 8, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_j103955d7d1e9e399dfbb839d275455e0.tex b/sail_latex_riscv/fnz_update_misa_j103955d7d1e9e399dfbb839d275455e0.tex new file mode 100644 index 00000000..8f184955 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_j103955d7d1e9e399dfbb839d275455e0.tex @@ -0,0 +1,2 @@ +function _update_Misa_J (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 9, 9, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_kc4683fd490bb981aba37613fc8cdcb37.tex b/sail_latex_riscv/fnz_update_misa_kc4683fd490bb981aba37613fc8cdcb37.tex new file mode 100644 index 00000000..ea95c717 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_kc4683fd490bb981aba37613fc8cdcb37.tex @@ -0,0 +1,2 @@ +function _update_Misa_K (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 10, 10, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_l26aa92a8b1cde2502fe1736a8838b22e.tex b/sail_latex_riscv/fnz_update_misa_l26aa92a8b1cde2502fe1736a8838b22e.tex new file mode 100644 index 00000000..8483e31c --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_l26aa92a8b1cde2502fe1736a8838b22e.tex @@ -0,0 +1,2 @@ +function _update_Misa_L (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 11, 11, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_m698989b85ca48a2f975a5588f3dc7491.tex b/sail_latex_riscv/fnz_update_misa_m698989b85ca48a2f975a5588f3dc7491.tex new file mode 100644 index 00000000..14500191 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_m698989b85ca48a2f975a5588f3dc7491.tex @@ -0,0 +1,2 @@ +function _update_Misa_M (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 12, 12, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_mxla1af4e187cbc1f82dd5ef946cabac371.tex b/sail_latex_riscv/fnz_update_misa_mxla1af4e187cbc1f82dd5ef946cabac371.tex new file mode 100644 index 00000000..631a1aab --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_mxla1af4e187cbc1f82dd5ef946cabac371.tex @@ -0,0 +1,2 @@ +function _update_Misa_MXL (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 63, 62, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_n83ee893338b4bd792d81b5cf59f2ebce.tex b/sail_latex_riscv/fnz_update_misa_n83ee893338b4bd792d81b5cf59f2ebce.tex new file mode 100644 index 00000000..0751e32c --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_n83ee893338b4bd792d81b5cf59f2ebce.tex @@ -0,0 +1,2 @@ +function _update_Misa_N (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 13, 13, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_obfc0e4a05dbc52b81817844c67df04f7.tex b/sail_latex_riscv/fnz_update_misa_obfc0e4a05dbc52b81817844c67df04f7.tex new file mode 100644 index 00000000..3c97a421 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_obfc0e4a05dbc52b81817844c67df04f7.tex @@ -0,0 +1,2 @@ +function _update_Misa_O (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 14, 14, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_pc6c8bc56b2633630ff91deb372f972a7.tex b/sail_latex_riscv/fnz_update_misa_pc6c8bc56b2633630ff91deb372f972a7.tex new file mode 100644 index 00000000..4e6e9dc0 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_pc6c8bc56b2633630ff91deb372f972a7.tex @@ -0,0 +1,2 @@ +function _update_Misa_P (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 15, 15, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_q17b883fc2058f678be34555bf03acf4e.tex b/sail_latex_riscv/fnz_update_misa_q17b883fc2058f678be34555bf03acf4e.tex new file mode 100644 index 00000000..99cfa902 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_q17b883fc2058f678be34555bf03acf4e.tex @@ -0,0 +1,2 @@ +function _update_Misa_Q (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 16, 16, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_r1f6eba10007c144d1b33e8eff2959c17.tex b/sail_latex_riscv/fnz_update_misa_r1f6eba10007c144d1b33e8eff2959c17.tex new file mode 100644 index 00000000..2abef811 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_r1f6eba10007c144d1b33e8eff2959c17.tex @@ -0,0 +1,2 @@ +function _update_Misa_R (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 17, 17, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_sa29e6cb2dba70d986fb8ff30487dfbad.tex b/sail_latex_riscv/fnz_update_misa_sa29e6cb2dba70d986fb8ff30487dfbad.tex new file mode 100644 index 00000000..61130995 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_sa29e6cb2dba70d986fb8ff30487dfbad.tex @@ -0,0 +1,2 @@ +function _update_Misa_S (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 18, 18, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_tab0b967322f8b3d8c5d8c510963c8722.tex b/sail_latex_riscv/fnz_update_misa_tab0b967322f8b3d8c5d8c510963c8722.tex new file mode 100644 index 00000000..0f32b623 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_tab0b967322f8b3d8c5d8c510963c8722.tex @@ -0,0 +1,2 @@ +function _update_Misa_T (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 19, 19, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_uac3943ed1944a21d61ef4550883e07f7.tex b/sail_latex_riscv/fnz_update_misa_uac3943ed1944a21d61ef4550883e07f7.tex new file mode 100644 index 00000000..144a71df --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_uac3943ed1944a21d61ef4550883e07f7.tex @@ -0,0 +1,2 @@ +function _update_Misa_U (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 20, 20, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_v1a8b5a29274e9567bae2f9671be4372a.tex b/sail_latex_riscv/fnz_update_misa_v1a8b5a29274e9567bae2f9671be4372a.tex new file mode 100644 index 00000000..919696a3 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_v1a8b5a29274e9567bae2f9671be4372a.tex @@ -0,0 +1,2 @@ +function _update_Misa_V (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 21, 21, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_wd53860d44fba8bd03071c9b2edd62e86.tex b/sail_latex_riscv/fnz_update_misa_wd53860d44fba8bd03071c9b2edd62e86.tex new file mode 100644 index 00000000..12ddccda --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_wd53860d44fba8bd03071c9b2edd62e86.tex @@ -0,0 +1,2 @@ +function _update_Misa_W (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 22, 22, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_x51e71056e58398948e16168b5c3c2df9.tex b/sail_latex_riscv/fnz_update_misa_x51e71056e58398948e16168b5c3c2df9.tex new file mode 100644 index 00000000..c22c67b0 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_x51e71056e58398948e16168b5c3c2df9.tex @@ -0,0 +1,2 @@ +function _update_Misa_X (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 23, 23, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_y44689f65180da16f003ee1c86f6b157e.tex b/sail_latex_riscv/fnz_update_misa_y44689f65180da16f003ee1c86f6b157e.tex new file mode 100644 index 00000000..7f93dc83 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_y44689f65180da16f003ee1c86f6b157e.tex @@ -0,0 +1,2 @@ +function _update_Misa_Y (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 24, 24, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_misa_z801b78039b962c298e7fc5710e8ae3c4.tex b/sail_latex_riscv/fnz_update_misa_z801b78039b962c298e7fc5710e8ae3c4.tex new file mode 100644 index 00000000..53ddee67 --- /dev/null +++ b/sail_latex_riscv/fnz_update_misa_z801b78039b962c298e7fc5710e8ae3c4.tex @@ -0,0 +1,2 @@ +function _update_Misa_Z (v, x) = let v = { v with Misa_chunk_0 = update_subrange_bits(v.Misa_chunk_0, 25, 25, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_bits62d247fffd2b228018ee801927d13b83.tex b/sail_latex_riscv/fnz_update_mstatus_bits62d247fffd2b228018ee801927d13b83.tex new file mode 100644 index 00000000..9ef404ef --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_bits62d247fffd2b228018ee801927d13b83.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_bits (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_fsf06a4782f53e6ed8e2818ec43a049e21.tex b/sail_latex_riscv/fnz_update_mstatus_fsf06a4782f53e6ed8e2818ec43a049e21.tex new file mode 100644 index 00000000..d38fed3f --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_fsf06a4782f53e6ed8e2818ec43a049e21.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_FS (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 14, 13, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_mie80faf2146d01111ce6c4739dfadf9c5a.tex b/sail_latex_riscv/fnz_update_mstatus_mie80faf2146d01111ce6c4739dfadf9c5a.tex new file mode 100644 index 00000000..0c402f7f --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_mie80faf2146d01111ce6c4739dfadf9c5a.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_MIE (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 3, 3, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_mpie66bbd7d75ad543a33368f099d66c2ad3.tex b/sail_latex_riscv/fnz_update_mstatus_mpie66bbd7d75ad543a33368f099d66c2ad3.tex new file mode 100644 index 00000000..5019c2c7 --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_mpie66bbd7d75ad543a33368f099d66c2ad3.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_MPIE (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 7, 7, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_mpp0dfb32efcb28c9f2f9f70f8b7fc4edeb.tex b/sail_latex_riscv/fnz_update_mstatus_mpp0dfb32efcb28c9f2f9f70f8b7fc4edeb.tex new file mode 100644 index 00000000..62cfcc3a --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_mpp0dfb32efcb28c9f2f9f70f8b7fc4edeb.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_MPP (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 12, 11, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_mprv5d1e4d26fc69487fc2e371466a2aefda.tex b/sail_latex_riscv/fnz_update_mstatus_mprv5d1e4d26fc69487fc2e371466a2aefda.tex new file mode 100644 index 00000000..d0331220 --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_mprv5d1e4d26fc69487fc2e371466a2aefda.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_MPRV (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 17, 17, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_mxr86db170c1ee7edaf7ee350f188d44e71.tex b/sail_latex_riscv/fnz_update_mstatus_mxr86db170c1ee7edaf7ee350f188d44e71.tex new file mode 100644 index 00000000..ba33047a --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_mxr86db170c1ee7edaf7ee350f188d44e71.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_MXR (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 19, 19, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_sda4daaeb7cf3d3804c84f8f3adc875435.tex b/sail_latex_riscv/fnz_update_mstatus_sda4daaeb7cf3d3804c84f8f3adc875435.tex new file mode 100644 index 00000000..a1b2509a --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_sda4daaeb7cf3d3804c84f8f3adc875435.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_SD (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 63, 63, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_sie59e9df0f2de34ad900e35dadcacc511b.tex b/sail_latex_riscv/fnz_update_mstatus_sie59e9df0f2de34ad900e35dadcacc511b.tex new file mode 100644 index 00000000..df481eda --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_sie59e9df0f2de34ad900e35dadcacc511b.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_SIE (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_spie6da04c490b761f34be7c9f4b5f75dd15.tex b/sail_latex_riscv/fnz_update_mstatus_spie6da04c490b761f34be7c9f4b5f75dd15.tex new file mode 100644 index 00000000..da55de1a --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_spie6da04c490b761f34be7c9f4b5f75dd15.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_SPIE (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 5, 5, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_sppfa488292080686e2372e721aece0aca4.tex b/sail_latex_riscv/fnz_update_mstatus_sppfa488292080686e2372e721aece0aca4.tex new file mode 100644 index 00000000..bd99bbd2 --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_sppfa488292080686e2372e721aece0aca4.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_SPP (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 8, 8, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_sumb7a60974e206e5c4db1cb80fdf3bcfe5.tex b/sail_latex_riscv/fnz_update_mstatus_sumb7a60974e206e5c4db1cb80fdf3bcfe5.tex new file mode 100644 index 00000000..fe4e8b53 --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_sumb7a60974e206e5c4db1cb80fdf3bcfe5.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_SUM (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 18, 18, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_tsr911d1e468313451d39d3edd62969f771.tex b/sail_latex_riscv/fnz_update_mstatus_tsr911d1e468313451d39d3edd62969f771.tex new file mode 100644 index 00000000..21ed4ee7 --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_tsr911d1e468313451d39d3edd62969f771.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_TSR (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 22, 22, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_tvmf7d012651ef54cac1cdafef6e0e98a7f.tex b/sail_latex_riscv/fnz_update_mstatus_tvmf7d012651ef54cac1cdafef6e0e98a7f.tex new file mode 100644 index 00000000..3aebafc4 --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_tvmf7d012651ef54cac1cdafef6e0e98a7f.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_TVM (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 20, 20, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_tw2d7307276d7507e86718caff9b05aee8.tex b/sail_latex_riscv/fnz_update_mstatus_tw2d7307276d7507e86718caff9b05aee8.tex new file mode 100644 index 00000000..50db675d --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_tw2d7307276d7507e86718caff9b05aee8.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_TW (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 21, 21, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_uie24981f834cc06df1bad9dd31da0f462b.tex b/sail_latex_riscv/fnz_update_mstatus_uie24981f834cc06df1bad9dd31da0f462b.tex new file mode 100644 index 00000000..fcb0a8c7 --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_uie24981f834cc06df1bad9dd31da0f462b.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_UIE (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_upie62eccd6c3bcbfbe552e26c27d8c9e73e.tex b/sail_latex_riscv/fnz_update_mstatus_upie62eccd6c3bcbfbe552e26c27d8c9e73e.tex new file mode 100644 index 00000000..8767f1c7 --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_upie62eccd6c3bcbfbe552e26c27d8c9e73e.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_UPIE (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 4, 4, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mstatus_xsa631910853fd5409435e58ed9e2273a3.tex b/sail_latex_riscv/fnz_update_mstatus_xsa631910853fd5409435e58ed9e2273a3.tex new file mode 100644 index 00000000..c9f98d43 --- /dev/null +++ b/sail_latex_riscv/fnz_update_mstatus_xsa631910853fd5409435e58ed9e2273a3.tex @@ -0,0 +1,2 @@ +function _update_Mstatus_XS (v, x) = let v = { v with Mstatus_chunk_0 = update_subrange_bits(v.Mstatus_chunk_0, 16, 15, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mtvec_base2276531f23752a05146b70a788934e75.tex b/sail_latex_riscv/fnz_update_mtvec_base2276531f23752a05146b70a788934e75.tex new file mode 100644 index 00000000..7216947d --- /dev/null +++ b/sail_latex_riscv/fnz_update_mtvec_base2276531f23752a05146b70a788934e75.tex @@ -0,0 +1,2 @@ +function _update_Mtvec_Base (v, x) = let v = { v with Mtvec_chunk_0 = update_subrange_bits(v.Mtvec_chunk_0, 63, 2, subrange_bits(x, 61, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mtvec_bits158581c836e4cf68e74f750598d54083.tex b/sail_latex_riscv/fnz_update_mtvec_bits158581c836e4cf68e74f750598d54083.tex new file mode 100644 index 00000000..1ba861f8 --- /dev/null +++ b/sail_latex_riscv/fnz_update_mtvec_bits158581c836e4cf68e74f750598d54083.tex @@ -0,0 +1,2 @@ +function _update_Mtvec_bits (v, x) = let v = { v with Mtvec_chunk_0 = update_subrange_bits(v.Mtvec_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_mtvec_moded92fe8c6eb43d3e69a83d0a2b060e3a2.tex b/sail_latex_riscv/fnz_update_mtvec_moded92fe8c6eb43d3e69a83d0a2b060e3a2.tex new file mode 100644 index 00000000..e3aac9bb --- /dev/null +++ b/sail_latex_riscv/fnz_update_mtvec_moded92fe8c6eb43d3e69a83d0a2b060e3a2.tex @@ -0,0 +1,2 @@ +function _update_Mtvec_Mode (v, x) = let v = { v with Mtvec_chunk_0 = update_subrange_bits(v.Mtvec_chunk_0, 1, 0, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pmpcfg_ent_adadbb540a1c6bab1c55bd9a61e3b9e0a.tex b/sail_latex_riscv/fnz_update_pmpcfg_ent_adadbb540a1c6bab1c55bd9a61e3b9e0a.tex new file mode 100644 index 00000000..69424b9c --- /dev/null +++ b/sail_latex_riscv/fnz_update_pmpcfg_ent_adadbb540a1c6bab1c55bd9a61e3b9e0a.tex @@ -0,0 +1,2 @@ +function _update_Pmpcfg_ent_A (v, x) = let v = { v with Pmpcfg_ent_chunk_0 = update_subrange_bits(v.Pmpcfg_ent_chunk_0, 4, 3, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pmpcfg_ent_bits6dc08fac70bb607f44a679981ff8591f.tex b/sail_latex_riscv/fnz_update_pmpcfg_ent_bits6dc08fac70bb607f44a679981ff8591f.tex new file mode 100644 index 00000000..65f0ad0b --- /dev/null +++ b/sail_latex_riscv/fnz_update_pmpcfg_ent_bits6dc08fac70bb607f44a679981ff8591f.tex @@ -0,0 +1,2 @@ +function _update_Pmpcfg_ent_bits (v, x) = let v = { v with Pmpcfg_ent_chunk_0 = update_subrange_bits(v.Pmpcfg_ent_chunk_0, 7, 0, subrange_bits(x, 7, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pmpcfg_ent_lb0e2b34db62383c5c6ef62efd629c305.tex b/sail_latex_riscv/fnz_update_pmpcfg_ent_lb0e2b34db62383c5c6ef62efd629c305.tex new file mode 100644 index 00000000..90574e14 --- /dev/null +++ b/sail_latex_riscv/fnz_update_pmpcfg_ent_lb0e2b34db62383c5c6ef62efd629c305.tex @@ -0,0 +1,2 @@ +function _update_Pmpcfg_ent_L (v, x) = let v = { v with Pmpcfg_ent_chunk_0 = update_subrange_bits(v.Pmpcfg_ent_chunk_0, 7, 7, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pmpcfg_ent_r2c785198293c46ff7260dc7a32aa6331.tex b/sail_latex_riscv/fnz_update_pmpcfg_ent_r2c785198293c46ff7260dc7a32aa6331.tex new file mode 100644 index 00000000..759ef6c1 --- /dev/null +++ b/sail_latex_riscv/fnz_update_pmpcfg_ent_r2c785198293c46ff7260dc7a32aa6331.tex @@ -0,0 +1,2 @@ +function _update_Pmpcfg_ent_R (v, x) = let v = { v with Pmpcfg_ent_chunk_0 = update_subrange_bits(v.Pmpcfg_ent_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pmpcfg_ent_w74feb7c9463c0ec331329f44cf100d0f.tex b/sail_latex_riscv/fnz_update_pmpcfg_ent_w74feb7c9463c0ec331329f44cf100d0f.tex new file mode 100644 index 00000000..048fdd2c --- /dev/null +++ b/sail_latex_riscv/fnz_update_pmpcfg_ent_w74feb7c9463c0ec331329f44cf100d0f.tex @@ -0,0 +1,2 @@ +function _update_Pmpcfg_ent_W (v, x) = let v = { v with Pmpcfg_ent_chunk_0 = update_subrange_bits(v.Pmpcfg_ent_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pmpcfg_ent_x097e4626d7a8cfe0234214857e298c86.tex b/sail_latex_riscv/fnz_update_pmpcfg_ent_x097e4626d7a8cfe0234214857e298c86.tex new file mode 100644 index 00000000..db775a15 --- /dev/null +++ b/sail_latex_riscv/fnz_update_pmpcfg_ent_x097e4626d7a8cfe0234214857e298c86.tex @@ -0,0 +1,2 @@ +function _update_Pmpcfg_ent_X (v, x) = let v = { v with Pmpcfg_ent_chunk_0 = update_subrange_bits(v.Pmpcfg_ent_chunk_0, 2, 2, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pte_bits_a3004f24784d29ad77e6bb0801c41e98e.tex b/sail_latex_riscv/fnz_update_pte_bits_a3004f24784d29ad77e6bb0801c41e98e.tex new file mode 100644 index 00000000..7907fa65 --- /dev/null +++ b/sail_latex_riscv/fnz_update_pte_bits_a3004f24784d29ad77e6bb0801c41e98e.tex @@ -0,0 +1,2 @@ +function _update_PTE_Bits_A (v, x) = let v = { v with PTE_Bits_chunk_0 = update_subrange_bits(v.PTE_Bits_chunk_0, 6, 6, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pte_bits_bits103014768edd92dc714fb7a033a0405f.tex b/sail_latex_riscv/fnz_update_pte_bits_bits103014768edd92dc714fb7a033a0405f.tex new file mode 100644 index 00000000..c1613111 --- /dev/null +++ b/sail_latex_riscv/fnz_update_pte_bits_bits103014768edd92dc714fb7a033a0405f.tex @@ -0,0 +1,2 @@ +function _update_PTE_Bits_bits (v, x) = let v = { v with PTE_Bits_chunk_0 = update_subrange_bits(v.PTE_Bits_chunk_0, 7, 0, subrange_bits(x, 7, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pte_bits_d0702d6e9e8c79296c17be6a87f7d2bcb.tex b/sail_latex_riscv/fnz_update_pte_bits_d0702d6e9e8c79296c17be6a87f7d2bcb.tex new file mode 100644 index 00000000..621bc76c --- /dev/null +++ b/sail_latex_riscv/fnz_update_pte_bits_d0702d6e9e8c79296c17be6a87f7d2bcb.tex @@ -0,0 +1,2 @@ +function _update_PTE_Bits_D (v, x) = let v = { v with PTE_Bits_chunk_0 = update_subrange_bits(v.PTE_Bits_chunk_0, 7, 7, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pte_bits_g7f8aa128b55e6f52846f32adb9e9a045.tex b/sail_latex_riscv/fnz_update_pte_bits_g7f8aa128b55e6f52846f32adb9e9a045.tex new file mode 100644 index 00000000..b5999ba0 --- /dev/null +++ b/sail_latex_riscv/fnz_update_pte_bits_g7f8aa128b55e6f52846f32adb9e9a045.tex @@ -0,0 +1,2 @@ +function _update_PTE_Bits_G (v, x) = let v = { v with PTE_Bits_chunk_0 = update_subrange_bits(v.PTE_Bits_chunk_0, 5, 5, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pte_bits_r320dc9e678d3a436f17fb038197c377c.tex b/sail_latex_riscv/fnz_update_pte_bits_r320dc9e678d3a436f17fb038197c377c.tex new file mode 100644 index 00000000..ecadb38c --- /dev/null +++ b/sail_latex_riscv/fnz_update_pte_bits_r320dc9e678d3a436f17fb038197c377c.tex @@ -0,0 +1,2 @@ +function _update_PTE_Bits_R (v, x) = let v = { v with PTE_Bits_chunk_0 = update_subrange_bits(v.PTE_Bits_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pte_bits_u977bcbc754c6423b417ff582c0113450.tex b/sail_latex_riscv/fnz_update_pte_bits_u977bcbc754c6423b417ff582c0113450.tex new file mode 100644 index 00000000..570d0a9a --- /dev/null +++ b/sail_latex_riscv/fnz_update_pte_bits_u977bcbc754c6423b417ff582c0113450.tex @@ -0,0 +1,2 @@ +function _update_PTE_Bits_U (v, x) = let v = { v with PTE_Bits_chunk_0 = update_subrange_bits(v.PTE_Bits_chunk_0, 4, 4, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pte_bits_vf1ed439c0a93204c0e278d68fd72351c.tex b/sail_latex_riscv/fnz_update_pte_bits_vf1ed439c0a93204c0e278d68fd72351c.tex new file mode 100644 index 00000000..effd552a --- /dev/null +++ b/sail_latex_riscv/fnz_update_pte_bits_vf1ed439c0a93204c0e278d68fd72351c.tex @@ -0,0 +1,2 @@ +function _update_PTE_Bits_V (v, x) = let v = { v with PTE_Bits_chunk_0 = update_subrange_bits(v.PTE_Bits_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pte_bits_w18528f50b9477178a61c7f8ca1c44e05.tex b/sail_latex_riscv/fnz_update_pte_bits_w18528f50b9477178a61c7f8ca1c44e05.tex new file mode 100644 index 00000000..511bffa3 --- /dev/null +++ b/sail_latex_riscv/fnz_update_pte_bits_w18528f50b9477178a61c7f8ca1c44e05.tex @@ -0,0 +1,2 @@ +function _update_PTE_Bits_W (v, x) = let v = { v with PTE_Bits_chunk_0 = update_subrange_bits(v.PTE_Bits_chunk_0, 2, 2, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_pte_bits_xe681f15474cf63965beb076cc7920964.tex b/sail_latex_riscv/fnz_update_pte_bits_xe681f15474cf63965beb076cc7920964.tex new file mode 100644 index 00000000..d5786a96 --- /dev/null +++ b/sail_latex_riscv/fnz_update_pte_bits_xe681f15474cf63965beb076cc7920964.tex @@ -0,0 +1,2 @@ +function _update_PTE_Bits_X (v, x) = let v = { v with PTE_Bits_chunk_0 = update_subrange_bits(v.PTE_Bits_chunk_0, 3, 3, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_satp32_asid4a10333ee9adcd6b560d2b22f799b1c2.tex b/sail_latex_riscv/fnz_update_satp32_asid4a10333ee9adcd6b560d2b22f799b1c2.tex new file mode 100644 index 00000000..5bc3d92e --- /dev/null +++ b/sail_latex_riscv/fnz_update_satp32_asid4a10333ee9adcd6b560d2b22f799b1c2.tex @@ -0,0 +1,2 @@ +function _update_Satp32_Asid (v, x) = let v = { v with Satp32_chunk_0 = update_subrange_bits(v.Satp32_chunk_0, 30, 22, subrange_bits(x, 8, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_satp32_bits040735762104e2eb7ee468b2c73a3376.tex b/sail_latex_riscv/fnz_update_satp32_bits040735762104e2eb7ee468b2c73a3376.tex new file mode 100644 index 00000000..dd1004d1 --- /dev/null +++ b/sail_latex_riscv/fnz_update_satp32_bits040735762104e2eb7ee468b2c73a3376.tex @@ -0,0 +1,2 @@ +function _update_Satp32_bits (v, x) = let v = { v with Satp32_chunk_0 = update_subrange_bits(v.Satp32_chunk_0, 31, 0, subrange_bits(x, 31, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_satp32_modeeff3936a1c725a7de10614f5e8bbdc94.tex b/sail_latex_riscv/fnz_update_satp32_modeeff3936a1c725a7de10614f5e8bbdc94.tex new file mode 100644 index 00000000..cc0f18f1 --- /dev/null +++ b/sail_latex_riscv/fnz_update_satp32_modeeff3936a1c725a7de10614f5e8bbdc94.tex @@ -0,0 +1,2 @@ +function _update_Satp32_Mode (v, x) = let v = { v with Satp32_chunk_0 = update_subrange_bits(v.Satp32_chunk_0, 31, 31, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_satp32_ppnfdc6c798de82ace5c37372a64d41dbd8.tex b/sail_latex_riscv/fnz_update_satp32_ppnfdc6c798de82ace5c37372a64d41dbd8.tex new file mode 100644 index 00000000..b2a03daf --- /dev/null +++ b/sail_latex_riscv/fnz_update_satp32_ppnfdc6c798de82ace5c37372a64d41dbd8.tex @@ -0,0 +1,2 @@ +function _update_Satp32_PPN (v, x) = let v = { v with Satp32_chunk_0 = update_subrange_bits(v.Satp32_chunk_0, 21, 0, subrange_bits(x, 21, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_satp64_asid4587433548bd071c272c301c9b049f40.tex b/sail_latex_riscv/fnz_update_satp64_asid4587433548bd071c272c301c9b049f40.tex new file mode 100644 index 00000000..48ec8662 --- /dev/null +++ b/sail_latex_riscv/fnz_update_satp64_asid4587433548bd071c272c301c9b049f40.tex @@ -0,0 +1,2 @@ +function _update_Satp64_Asid (v, x) = let v = { v with Satp64_chunk_0 = update_subrange_bits(v.Satp64_chunk_0, 59, 44, subrange_bits(x, 15, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_satp64_bits2b386da295e07d09d86a4906f50a6dcf.tex b/sail_latex_riscv/fnz_update_satp64_bits2b386da295e07d09d86a4906f50a6dcf.tex new file mode 100644 index 00000000..5d1d292b --- /dev/null +++ b/sail_latex_riscv/fnz_update_satp64_bits2b386da295e07d09d86a4906f50a6dcf.tex @@ -0,0 +1,2 @@ +function _update_Satp64_bits (v, x) = let v = { v with Satp64_chunk_0 = update_subrange_bits(v.Satp64_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_satp64_modef6a327a4e9deddb4a58d5af1293fb1e4.tex b/sail_latex_riscv/fnz_update_satp64_modef6a327a4e9deddb4a58d5af1293fb1e4.tex new file mode 100644 index 00000000..3e88b7cb --- /dev/null +++ b/sail_latex_riscv/fnz_update_satp64_modef6a327a4e9deddb4a58d5af1293fb1e4.tex @@ -0,0 +1,2 @@ +function _update_Satp64_Mode (v, x) = let v = { v with Satp64_chunk_0 = update_subrange_bits(v.Satp64_chunk_0, 63, 60, subrange_bits(x, 3, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_satp64_ppne5381a5ff516a83023a3ab6b001812ea.tex b/sail_latex_riscv/fnz_update_satp64_ppne5381a5ff516a83023a3ab6b001812ea.tex new file mode 100644 index 00000000..43f9d791 --- /dev/null +++ b/sail_latex_riscv/fnz_update_satp64_ppne5381a5ff516a83023a3ab6b001812ea.tex @@ -0,0 +1,2 @@ +function _update_Satp64_PPN (v, x) = let v = { v with Satp64_chunk_0 = update_subrange_bits(v.Satp64_chunk_0, 43, 0, subrange_bits(x, 43, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sedeleg_bits2cf1d3152200555a4daa2092a724ca06.tex b/sail_latex_riscv/fnz_update_sedeleg_bits2cf1d3152200555a4daa2092a724ca06.tex new file mode 100644 index 00000000..d7a64d2c --- /dev/null +++ b/sail_latex_riscv/fnz_update_sedeleg_bits2cf1d3152200555a4daa2092a724ca06.tex @@ -0,0 +1,2 @@ +function _update_Sedeleg_bits (v, x) = let v = { v with Sedeleg_chunk_0 = update_subrange_bits(v.Sedeleg_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sedeleg_breakpoint4d1939da47af81029ca375f5c1c080e4.tex b/sail_latex_riscv/fnz_update_sedeleg_breakpoint4d1939da47af81029ca375f5c1c080e4.tex new file mode 100644 index 00000000..bcecb837 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sedeleg_breakpoint4d1939da47af81029ca375f5c1c080e4.tex @@ -0,0 +1,2 @@ +function _update_Sedeleg_Breakpoint (v, x) = let v = { v with Sedeleg_chunk_0 = update_subrange_bits(v.Sedeleg_chunk_0, 3, 3, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sedeleg_fetch_access_faultda711a3adc64706197c584b3f07a0e63.tex b/sail_latex_riscv/fnz_update_sedeleg_fetch_access_faultda711a3adc64706197c584b3f07a0e63.tex new file mode 100644 index 00000000..1935a4bd --- /dev/null +++ b/sail_latex_riscv/fnz_update_sedeleg_fetch_access_faultda711a3adc64706197c584b3f07a0e63.tex @@ -0,0 +1,2 @@ +function _update_Sedeleg_Fetch_Access_Fault (v, x) = let v = { v with Sedeleg_chunk_0 = update_subrange_bits(v.Sedeleg_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sedeleg_fetch_addr_align57e1b55e0654637983d88a45a3d27115.tex b/sail_latex_riscv/fnz_update_sedeleg_fetch_addr_align57e1b55e0654637983d88a45a3d27115.tex new file mode 100644 index 00000000..661c188e --- /dev/null +++ b/sail_latex_riscv/fnz_update_sedeleg_fetch_addr_align57e1b55e0654637983d88a45a3d27115.tex @@ -0,0 +1,2 @@ +function _update_Sedeleg_Fetch_Addr_Align (v, x) = let v = { v with Sedeleg_chunk_0 = update_subrange_bits(v.Sedeleg_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sedeleg_illegal_instr9f8eba51e2ce66c712c8a83a69cb47a0.tex b/sail_latex_riscv/fnz_update_sedeleg_illegal_instr9f8eba51e2ce66c712c8a83a69cb47a0.tex new file mode 100644 index 00000000..00f144cd --- /dev/null +++ b/sail_latex_riscv/fnz_update_sedeleg_illegal_instr9f8eba51e2ce66c712c8a83a69cb47a0.tex @@ -0,0 +1,2 @@ +function _update_Sedeleg_Illegal_Instr (v, x) = let v = { v with Sedeleg_chunk_0 = update_subrange_bits(v.Sedeleg_chunk_0, 2, 2, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sedeleg_load_access_fault6594e15b80693a22fb20ab7451df6720.tex b/sail_latex_riscv/fnz_update_sedeleg_load_access_fault6594e15b80693a22fb20ab7451df6720.tex new file mode 100644 index 00000000..318da9b0 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sedeleg_load_access_fault6594e15b80693a22fb20ab7451df6720.tex @@ -0,0 +1,2 @@ +function _update_Sedeleg_Load_Access_Fault (v, x) = let v = { v with Sedeleg_chunk_0 = update_subrange_bits(v.Sedeleg_chunk_0, 5, 5, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sedeleg_load_addr_alignddc26fe8167315620c0f5b98d7cf6b8d.tex b/sail_latex_riscv/fnz_update_sedeleg_load_addr_alignddc26fe8167315620c0f5b98d7cf6b8d.tex new file mode 100644 index 00000000..b43489bf --- /dev/null +++ b/sail_latex_riscv/fnz_update_sedeleg_load_addr_alignddc26fe8167315620c0f5b98d7cf6b8d.tex @@ -0,0 +1,2 @@ +function _update_Sedeleg_Load_Addr_Align (v, x) = let v = { v with Sedeleg_chunk_0 = update_subrange_bits(v.Sedeleg_chunk_0, 4, 4, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sedeleg_samo_access_fault9638c0015422d7509a2a078d70f56ba2.tex b/sail_latex_riscv/fnz_update_sedeleg_samo_access_fault9638c0015422d7509a2a078d70f56ba2.tex new file mode 100644 index 00000000..fa56a2ee --- /dev/null +++ b/sail_latex_riscv/fnz_update_sedeleg_samo_access_fault9638c0015422d7509a2a078d70f56ba2.tex @@ -0,0 +1,2 @@ +function _update_Sedeleg_SAMO_Access_Fault (v, x) = let v = { v with Sedeleg_chunk_0 = update_subrange_bits(v.Sedeleg_chunk_0, 7, 7, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sedeleg_samo_addr_align39928f0de9fb23d2068681efa4f6e746.tex b/sail_latex_riscv/fnz_update_sedeleg_samo_addr_align39928f0de9fb23d2068681efa4f6e746.tex new file mode 100644 index 00000000..213fafc0 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sedeleg_samo_addr_align39928f0de9fb23d2068681efa4f6e746.tex @@ -0,0 +1,2 @@ +function _update_Sedeleg_SAMO_Addr_Align (v, x) = let v = { v with Sedeleg_chunk_0 = update_subrange_bits(v.Sedeleg_chunk_0, 6, 6, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sedeleg_uenvcall0461d2c07b3055bf1fc4d0b3ea5739ef.tex b/sail_latex_riscv/fnz_update_sedeleg_uenvcall0461d2c07b3055bf1fc4d0b3ea5739ef.tex new file mode 100644 index 00000000..5e7222ca --- /dev/null +++ b/sail_latex_riscv/fnz_update_sedeleg_uenvcall0461d2c07b3055bf1fc4d0b3ea5739ef.tex @@ -0,0 +1,2 @@ +function _update_Sedeleg_UEnvCall (v, x) = let v = { v with Sedeleg_chunk_0 = update_subrange_bits(v.Sedeleg_chunk_0, 8, 8, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sinterrupts_bitsb82a5eaca518d7033ee5b65b76de6fc3.tex b/sail_latex_riscv/fnz_update_sinterrupts_bitsb82a5eaca518d7033ee5b65b76de6fc3.tex new file mode 100644 index 00000000..d2c49730 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sinterrupts_bitsb82a5eaca518d7033ee5b65b76de6fc3.tex @@ -0,0 +1,2 @@ +function _update_Sinterrupts_bits (v, x) = let v = { v with Sinterrupts_chunk_0 = update_subrange_bits(v.Sinterrupts_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sinterrupts_seidfae2f173d12134865a23f8b06b92d56.tex b/sail_latex_riscv/fnz_update_sinterrupts_seidfae2f173d12134865a23f8b06b92d56.tex new file mode 100644 index 00000000..d2fa2ed6 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sinterrupts_seidfae2f173d12134865a23f8b06b92d56.tex @@ -0,0 +1,2 @@ +function _update_Sinterrupts_SEI (v, x) = let v = { v with Sinterrupts_chunk_0 = update_subrange_bits(v.Sinterrupts_chunk_0, 9, 9, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sinterrupts_ssi41e461cfb1d80cf6497915184ac067fe.tex b/sail_latex_riscv/fnz_update_sinterrupts_ssi41e461cfb1d80cf6497915184ac067fe.tex new file mode 100644 index 00000000..0a04974d --- /dev/null +++ b/sail_latex_riscv/fnz_update_sinterrupts_ssi41e461cfb1d80cf6497915184ac067fe.tex @@ -0,0 +1,2 @@ +function _update_Sinterrupts_SSI (v, x) = let v = { v with Sinterrupts_chunk_0 = update_subrange_bits(v.Sinterrupts_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sinterrupts_sti3fd7347767c86ca33481e1dbc90ce93c.tex b/sail_latex_riscv/fnz_update_sinterrupts_sti3fd7347767c86ca33481e1dbc90ce93c.tex new file mode 100644 index 00000000..65e82dd5 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sinterrupts_sti3fd7347767c86ca33481e1dbc90ce93c.tex @@ -0,0 +1,2 @@ +function _update_Sinterrupts_STI (v, x) = let v = { v with Sinterrupts_chunk_0 = update_subrange_bits(v.Sinterrupts_chunk_0, 5, 5, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sinterrupts_uei4e9add8c9d8edc1f50674d5eb879d669.tex b/sail_latex_riscv/fnz_update_sinterrupts_uei4e9add8c9d8edc1f50674d5eb879d669.tex new file mode 100644 index 00000000..2f5ba3a9 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sinterrupts_uei4e9add8c9d8edc1f50674d5eb879d669.tex @@ -0,0 +1,2 @@ +function _update_Sinterrupts_UEI (v, x) = let v = { v with Sinterrupts_chunk_0 = update_subrange_bits(v.Sinterrupts_chunk_0, 8, 8, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sinterrupts_usia415b4e062e30257cfefa06256955512.tex b/sail_latex_riscv/fnz_update_sinterrupts_usia415b4e062e30257cfefa06256955512.tex new file mode 100644 index 00000000..05822695 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sinterrupts_usia415b4e062e30257cfefa06256955512.tex @@ -0,0 +1,2 @@ +function _update_Sinterrupts_USI (v, x) = let v = { v with Sinterrupts_chunk_0 = update_subrange_bits(v.Sinterrupts_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sinterrupts_uti76436fc7f8e1e46117a090613db49900.tex b/sail_latex_riscv/fnz_update_sinterrupts_uti76436fc7f8e1e46117a090613db49900.tex new file mode 100644 index 00000000..80d66515 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sinterrupts_uti76436fc7f8e1e46117a090613db49900.tex @@ -0,0 +1,2 @@ +function _update_Sinterrupts_UTI (v, x) = let v = { v with Sinterrupts_chunk_0 = update_subrange_bits(v.Sinterrupts_chunk_0, 4, 4, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sstatus_bits1ba4fa3c8cd21f04fa8e9a269f477a52.tex b/sail_latex_riscv/fnz_update_sstatus_bits1ba4fa3c8cd21f04fa8e9a269f477a52.tex new file mode 100644 index 00000000..b8bac64f --- /dev/null +++ b/sail_latex_riscv/fnz_update_sstatus_bits1ba4fa3c8cd21f04fa8e9a269f477a52.tex @@ -0,0 +1,2 @@ +function _update_Sstatus_bits (v, x) = let v = { v with Sstatus_chunk_0 = update_subrange_bits(v.Sstatus_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sstatus_fs5ae270f58355a8043214a3e56ea4ecb9.tex b/sail_latex_riscv/fnz_update_sstatus_fs5ae270f58355a8043214a3e56ea4ecb9.tex new file mode 100644 index 00000000..2f92ca42 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sstatus_fs5ae270f58355a8043214a3e56ea4ecb9.tex @@ -0,0 +1,2 @@ +function _update_Sstatus_FS (v, x) = let v = { v with Sstatus_chunk_0 = update_subrange_bits(v.Sstatus_chunk_0, 14, 13, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sstatus_mxre42b7942f7975353cbe85a0c0e124cdd.tex b/sail_latex_riscv/fnz_update_sstatus_mxre42b7942f7975353cbe85a0c0e124cdd.tex new file mode 100644 index 00000000..dab69cee --- /dev/null +++ b/sail_latex_riscv/fnz_update_sstatus_mxre42b7942f7975353cbe85a0c0e124cdd.tex @@ -0,0 +1,2 @@ +function _update_Sstatus_MXR (v, x) = let v = { v with Sstatus_chunk_0 = update_subrange_bits(v.Sstatus_chunk_0, 19, 19, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sstatus_sda2846124209293b81711916fe96d61c9.tex b/sail_latex_riscv/fnz_update_sstatus_sda2846124209293b81711916fe96d61c9.tex new file mode 100644 index 00000000..e872abe2 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sstatus_sda2846124209293b81711916fe96d61c9.tex @@ -0,0 +1,2 @@ +function _update_Sstatus_SD (v, x) = let v = { v with Sstatus_chunk_0 = update_subrange_bits(v.Sstatus_chunk_0, 63, 63, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sstatus_siea3c5fb4c611f7dacc262fcbe33a89902.tex b/sail_latex_riscv/fnz_update_sstatus_siea3c5fb4c611f7dacc262fcbe33a89902.tex new file mode 100644 index 00000000..22546fef --- /dev/null +++ b/sail_latex_riscv/fnz_update_sstatus_siea3c5fb4c611f7dacc262fcbe33a89902.tex @@ -0,0 +1,2 @@ +function _update_Sstatus_SIE (v, x) = let v = { v with Sstatus_chunk_0 = update_subrange_bits(v.Sstatus_chunk_0, 1, 1, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sstatus_spiea58b5496b1efe334d89b66e4df1f6a37.tex b/sail_latex_riscv/fnz_update_sstatus_spiea58b5496b1efe334d89b66e4df1f6a37.tex new file mode 100644 index 00000000..f89f2ac6 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sstatus_spiea58b5496b1efe334d89b66e4df1f6a37.tex @@ -0,0 +1,2 @@ +function _update_Sstatus_SPIE (v, x) = let v = { v with Sstatus_chunk_0 = update_subrange_bits(v.Sstatus_chunk_0, 5, 5, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sstatus_spp6bca059909e0ea5d1dca7a5f6a4c496d.tex b/sail_latex_riscv/fnz_update_sstatus_spp6bca059909e0ea5d1dca7a5f6a4c496d.tex new file mode 100644 index 00000000..c037ef04 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sstatus_spp6bca059909e0ea5d1dca7a5f6a4c496d.tex @@ -0,0 +1,2 @@ +function _update_Sstatus_SPP (v, x) = let v = { v with Sstatus_chunk_0 = update_subrange_bits(v.Sstatus_chunk_0, 8, 8, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sstatus_sum0cb0974a1d97890dd07f5d0a8a0e2a1f.tex b/sail_latex_riscv/fnz_update_sstatus_sum0cb0974a1d97890dd07f5d0a8a0e2a1f.tex new file mode 100644 index 00000000..00637822 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sstatus_sum0cb0974a1d97890dd07f5d0a8a0e2a1f.tex @@ -0,0 +1,2 @@ +function _update_Sstatus_SUM (v, x) = let v = { v with Sstatus_chunk_0 = update_subrange_bits(v.Sstatus_chunk_0, 18, 18, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sstatus_uie0de3308b00b5fa027c405d5ba7ea56a8.tex b/sail_latex_riscv/fnz_update_sstatus_uie0de3308b00b5fa027c405d5ba7ea56a8.tex new file mode 100644 index 00000000..f36aca0f --- /dev/null +++ b/sail_latex_riscv/fnz_update_sstatus_uie0de3308b00b5fa027c405d5ba7ea56a8.tex @@ -0,0 +1,2 @@ +function _update_Sstatus_UIE (v, x) = let v = { v with Sstatus_chunk_0 = update_subrange_bits(v.Sstatus_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sstatus_upie90c90f6e3ef912c0267408b59aaaec07.tex b/sail_latex_riscv/fnz_update_sstatus_upie90c90f6e3ef912c0267408b59aaaec07.tex new file mode 100644 index 00000000..521a5b2e --- /dev/null +++ b/sail_latex_riscv/fnz_update_sstatus_upie90c90f6e3ef912c0267408b59aaaec07.tex @@ -0,0 +1,2 @@ +function _update_Sstatus_UPIE (v, x) = let v = { v with Sstatus_chunk_0 = update_subrange_bits(v.Sstatus_chunk_0, 4, 4, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sstatus_xs8ed6c14d8c84fed994d5b6f62a6f95ff.tex b/sail_latex_riscv/fnz_update_sstatus_xs8ed6c14d8c84fed994d5b6f62a6f95ff.tex new file mode 100644 index 00000000..4b4aa860 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sstatus_xs8ed6c14d8c84fed994d5b6f62a6f95ff.tex @@ -0,0 +1,2 @@ +function _update_Sstatus_XS (v, x) = let v = { v with Sstatus_chunk_0 = update_subrange_bits(v.Sstatus_chunk_0, 16, 15, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv32_paddr_bits471b1f564b9f112d8202c1386e4a2c40.tex b/sail_latex_riscv/fnz_update_sv32_paddr_bits471b1f564b9f112d8202c1386e4a2c40.tex new file mode 100644 index 00000000..67576561 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv32_paddr_bits471b1f564b9f112d8202c1386e4a2c40.tex @@ -0,0 +1,2 @@ +function _update_SV32_Paddr_bits (v, x) = let v = { v with SV32_Paddr_chunk_0 = update_subrange_bits(v.SV32_Paddr_chunk_0, 33, 0, subrange_bits(x, 33, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv32_paddr_pgofsece69bfc0ddb3bbee82163605c655cd8.tex b/sail_latex_riscv/fnz_update_sv32_paddr_pgofsece69bfc0ddb3bbee82163605c655cd8.tex new file mode 100644 index 00000000..a6f8cd16 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv32_paddr_pgofsece69bfc0ddb3bbee82163605c655cd8.tex @@ -0,0 +1,2 @@ +function _update_SV32_Paddr_PgOfs (v, x) = let v = { v with SV32_Paddr_chunk_0 = update_subrange_bits(v.SV32_Paddr_chunk_0, 11, 0, subrange_bits(x, 11, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv32_paddr_ppnic2e893ade647c24a430ebfdfc1376233.tex b/sail_latex_riscv/fnz_update_sv32_paddr_ppnic2e893ade647c24a430ebfdfc1376233.tex new file mode 100644 index 00000000..c282b57a --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv32_paddr_ppnic2e893ade647c24a430ebfdfc1376233.tex @@ -0,0 +1,2 @@ +function _update_SV32_Paddr_PPNi (v, x) = let v = { v with SV32_Paddr_chunk_0 = update_subrange_bits(v.SV32_Paddr_chunk_0, 33, 12, subrange_bits(x, 21, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv32_pte_bits55ab6942a6f92e27c0aaaffec4bc5b75.tex b/sail_latex_riscv/fnz_update_sv32_pte_bits55ab6942a6f92e27c0aaaffec4bc5b75.tex new file mode 100644 index 00000000..71cd7564 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv32_pte_bits55ab6942a6f92e27c0aaaffec4bc5b75.tex @@ -0,0 +1,2 @@ +function _update_SV32_PTE_BITS (v, x) = let v = { v with SV32_PTE_chunk_0 = update_subrange_bits(v.SV32_PTE_chunk_0, 7, 0, subrange_bits(x, 7, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv32_pte_bits6ed5ef3d3bdb39782740d15add28a8ca.tex b/sail_latex_riscv/fnz_update_sv32_pte_bits6ed5ef3d3bdb39782740d15add28a8ca.tex new file mode 100644 index 00000000..0d06cc0f --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv32_pte_bits6ed5ef3d3bdb39782740d15add28a8ca.tex @@ -0,0 +1,2 @@ +function _update_SV32_PTE_bits (v, x) = let v = { v with SV32_PTE_chunk_0 = update_subrange_bits(v.SV32_PTE_chunk_0, 31, 0, subrange_bits(x, 31, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv32_pte_ppni21f940c0d0da732c90fb464f03b30e8e.tex b/sail_latex_riscv/fnz_update_sv32_pte_ppni21f940c0d0da732c90fb464f03b30e8e.tex new file mode 100644 index 00000000..0e9529cd --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv32_pte_ppni21f940c0d0da732c90fb464f03b30e8e.tex @@ -0,0 +1,2 @@ +function _update_SV32_PTE_PPNi (v, x) = let v = { v with SV32_PTE_chunk_0 = update_subrange_bits(v.SV32_PTE_chunk_0, 31, 10, subrange_bits(x, 21, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv32_pte_rsw2127473fcefd5043f7339af205217e28.tex b/sail_latex_riscv/fnz_update_sv32_pte_rsw2127473fcefd5043f7339af205217e28.tex new file mode 100644 index 00000000..161cf266 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv32_pte_rsw2127473fcefd5043f7339af205217e28.tex @@ -0,0 +1,2 @@ +function _update_SV32_PTE_RSW (v, x) = let v = { v with SV32_PTE_chunk_0 = update_subrange_bits(v.SV32_PTE_chunk_0, 9, 8, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv32_vaddr_bitsc681e87f3f4d859da7fee6d71d8b62c6.tex b/sail_latex_riscv/fnz_update_sv32_vaddr_bitsc681e87f3f4d859da7fee6d71d8b62c6.tex new file mode 100644 index 00000000..2b307387 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv32_vaddr_bitsc681e87f3f4d859da7fee6d71d8b62c6.tex @@ -0,0 +1,2 @@ +function _update_SV32_Vaddr_bits (v, x) = let v = { v with SV32_Vaddr_chunk_0 = update_subrange_bits(v.SV32_Vaddr_chunk_0, 31, 0, subrange_bits(x, 31, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv32_vaddr_pgofs4d5270a8a6277991b4da2a32d070beba.tex b/sail_latex_riscv/fnz_update_sv32_vaddr_pgofs4d5270a8a6277991b4da2a32d070beba.tex new file mode 100644 index 00000000..1a3043f4 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv32_vaddr_pgofs4d5270a8a6277991b4da2a32d070beba.tex @@ -0,0 +1,2 @@ +function _update_SV32_Vaddr_PgOfs (v, x) = let v = { v with SV32_Vaddr_chunk_0 = update_subrange_bits(v.SV32_Vaddr_chunk_0, 11, 0, subrange_bits(x, 11, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv32_vaddr_vpnif3d232fd203d42def1af1b10dd8639df.tex b/sail_latex_riscv/fnz_update_sv32_vaddr_vpnif3d232fd203d42def1af1b10dd8639df.tex new file mode 100644 index 00000000..65df3fd0 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv32_vaddr_vpnif3d232fd203d42def1af1b10dd8639df.tex @@ -0,0 +1,2 @@ +function _update_SV32_Vaddr_VPNi (v, x) = let v = { v with SV32_Vaddr_chunk_0 = update_subrange_bits(v.SV32_Vaddr_chunk_0, 31, 12, subrange_bits(x, 19, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv39_paddr_bits95d51c315963bb06758677d399020d4c.tex b/sail_latex_riscv/fnz_update_sv39_paddr_bits95d51c315963bb06758677d399020d4c.tex new file mode 100644 index 00000000..20b389a2 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv39_paddr_bits95d51c315963bb06758677d399020d4c.tex @@ -0,0 +1,2 @@ +function _update_SV39_Paddr_bits (v, x) = let v = { v with SV39_Paddr_chunk_0 = update_subrange_bits(v.SV39_Paddr_chunk_0, 55, 0, subrange_bits(x, 55, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv39_paddr_pgofs92e3fd4a4ef641b9bd4695bcb4e6865d.tex b/sail_latex_riscv/fnz_update_sv39_paddr_pgofs92e3fd4a4ef641b9bd4695bcb4e6865d.tex new file mode 100644 index 00000000..af38758f --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv39_paddr_pgofs92e3fd4a4ef641b9bd4695bcb4e6865d.tex @@ -0,0 +1,2 @@ +function _update_SV39_Paddr_PgOfs (v, x) = let v = { v with SV39_Paddr_chunk_0 = update_subrange_bits(v.SV39_Paddr_chunk_0, 11, 0, subrange_bits(x, 11, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv39_paddr_ppni64a04f2f491820010df9118b96fe3bb1.tex b/sail_latex_riscv/fnz_update_sv39_paddr_ppni64a04f2f491820010df9118b96fe3bb1.tex new file mode 100644 index 00000000..602b0b4c --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv39_paddr_ppni64a04f2f491820010df9118b96fe3bb1.tex @@ -0,0 +1,2 @@ +function _update_SV39_Paddr_PPNi (v, x) = let v = { v with SV39_Paddr_chunk_0 = update_subrange_bits(v.SV39_Paddr_chunk_0, 55, 12, subrange_bits(x, 43, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv39_pte_bits3f8498b470f391c57cca777dadcbfb2e.tex b/sail_latex_riscv/fnz_update_sv39_pte_bits3f8498b470f391c57cca777dadcbfb2e.tex new file mode 100644 index 00000000..d3a8bcdc --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv39_pte_bits3f8498b470f391c57cca777dadcbfb2e.tex @@ -0,0 +1,2 @@ +function _update_SV39_PTE_BITS (v, x) = let v = { v with SV39_PTE_chunk_0 = update_subrange_bits(v.SV39_PTE_chunk_0, 7, 0, subrange_bits(x, 7, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv39_pte_bitsf70d63d10d4409523d5b20cddef1d791.tex b/sail_latex_riscv/fnz_update_sv39_pte_bitsf70d63d10d4409523d5b20cddef1d791.tex new file mode 100644 index 00000000..ba373567 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv39_pte_bitsf70d63d10d4409523d5b20cddef1d791.tex @@ -0,0 +1,2 @@ +function _update_SV39_PTE_bits (v, x) = let v = { v with SV39_PTE_chunk_0 = update_subrange_bits(v.SV39_PTE_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv39_pte_ext7389da76692695bdeeaa0a6612d2ddf3.tex b/sail_latex_riscv/fnz_update_sv39_pte_ext7389da76692695bdeeaa0a6612d2ddf3.tex new file mode 100644 index 00000000..7691ad93 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv39_pte_ext7389da76692695bdeeaa0a6612d2ddf3.tex @@ -0,0 +1,2 @@ +function _update_SV39_PTE_Ext (v, x) = let v = { v with SV39_PTE_chunk_0 = update_subrange_bits(v.SV39_PTE_chunk_0, 63, 54, subrange_bits(x, 9, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv39_pte_ppni4bb75edea91e119f5e4b777a201ca7de.tex b/sail_latex_riscv/fnz_update_sv39_pte_ppni4bb75edea91e119f5e4b777a201ca7de.tex new file mode 100644 index 00000000..6f57b41e --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv39_pte_ppni4bb75edea91e119f5e4b777a201ca7de.tex @@ -0,0 +1,2 @@ +function _update_SV39_PTE_PPNi (v, x) = let v = { v with SV39_PTE_chunk_0 = update_subrange_bits(v.SV39_PTE_chunk_0, 53, 10, subrange_bits(x, 43, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv39_pte_rsw7d745d7147024b1db9a0ab778ae3aa90.tex b/sail_latex_riscv/fnz_update_sv39_pte_rsw7d745d7147024b1db9a0ab778ae3aa90.tex new file mode 100644 index 00000000..41f6b773 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv39_pte_rsw7d745d7147024b1db9a0ab778ae3aa90.tex @@ -0,0 +1,2 @@ +function _update_SV39_PTE_RSW (v, x) = let v = { v with SV39_PTE_chunk_0 = update_subrange_bits(v.SV39_PTE_chunk_0, 9, 8, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv39_vaddr_bits9b5c877641996c39232fdaa69695b175.tex b/sail_latex_riscv/fnz_update_sv39_vaddr_bits9b5c877641996c39232fdaa69695b175.tex new file mode 100644 index 00000000..32602379 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv39_vaddr_bits9b5c877641996c39232fdaa69695b175.tex @@ -0,0 +1,2 @@ +function _update_SV39_Vaddr_bits (v, x) = let v = { v with SV39_Vaddr_chunk_0 = update_subrange_bits(v.SV39_Vaddr_chunk_0, 38, 0, subrange_bits(x, 38, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv39_vaddr_pgofs2203553b5bf9afd58276a7958197b4c6.tex b/sail_latex_riscv/fnz_update_sv39_vaddr_pgofs2203553b5bf9afd58276a7958197b4c6.tex new file mode 100644 index 00000000..22cbad5e --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv39_vaddr_pgofs2203553b5bf9afd58276a7958197b4c6.tex @@ -0,0 +1,2 @@ +function _update_SV39_Vaddr_PgOfs (v, x) = let v = { v with SV39_Vaddr_chunk_0 = update_subrange_bits(v.SV39_Vaddr_chunk_0, 11, 0, subrange_bits(x, 11, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv39_vaddr_vpnibc20f5f41da77bf31c390df8cd865198.tex b/sail_latex_riscv/fnz_update_sv39_vaddr_vpnibc20f5f41da77bf31c390df8cd865198.tex new file mode 100644 index 00000000..b404de6e --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv39_vaddr_vpnibc20f5f41da77bf31c390df8cd865198.tex @@ -0,0 +1,2 @@ +function _update_SV39_Vaddr_VPNi (v, x) = let v = { v with SV39_Vaddr_chunk_0 = update_subrange_bits(v.SV39_Vaddr_chunk_0, 38, 12, subrange_bits(x, 26, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv48_paddr_bitsd392e84dd67a8ca48490ef502cca7bd9.tex b/sail_latex_riscv/fnz_update_sv48_paddr_bitsd392e84dd67a8ca48490ef502cca7bd9.tex new file mode 100644 index 00000000..fea49247 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv48_paddr_bitsd392e84dd67a8ca48490ef502cca7bd9.tex @@ -0,0 +1,2 @@ +function _update_SV48_Paddr_bits (v, x) = let v = { v with SV48_Paddr_chunk_0 = update_subrange_bits(v.SV48_Paddr_chunk_0, 55, 0, subrange_bits(x, 55, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv48_paddr_pgofsd71fa33c7b6f3543d0d9b5dc2d8380f5.tex b/sail_latex_riscv/fnz_update_sv48_paddr_pgofsd71fa33c7b6f3543d0d9b5dc2d8380f5.tex new file mode 100644 index 00000000..14fc8faa --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv48_paddr_pgofsd71fa33c7b6f3543d0d9b5dc2d8380f5.tex @@ -0,0 +1,2 @@ +function _update_SV48_Paddr_PgOfs (v, x) = let v = { v with SV48_Paddr_chunk_0 = update_subrange_bits(v.SV48_Paddr_chunk_0, 11, 0, subrange_bits(x, 11, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv48_paddr_ppni3e4b50484e79dc7761373bc124441fd0.tex b/sail_latex_riscv/fnz_update_sv48_paddr_ppni3e4b50484e79dc7761373bc124441fd0.tex new file mode 100644 index 00000000..2410e969 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv48_paddr_ppni3e4b50484e79dc7761373bc124441fd0.tex @@ -0,0 +1,2 @@ +function _update_SV48_Paddr_PPNi (v, x) = let v = { v with SV48_Paddr_chunk_0 = update_subrange_bits(v.SV48_Paddr_chunk_0, 55, 12, subrange_bits(x, 43, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv48_pte_bits0a6df26df13de159300f6127a4b286db.tex b/sail_latex_riscv/fnz_update_sv48_pte_bits0a6df26df13de159300f6127a4b286db.tex new file mode 100644 index 00000000..0b23c2c2 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv48_pte_bits0a6df26df13de159300f6127a4b286db.tex @@ -0,0 +1,2 @@ +function _update_SV48_PTE_bits (v, x) = let v = { v with SV48_PTE_chunk_0 = update_subrange_bits(v.SV48_PTE_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv48_pte_bits5dd960679bb9cad63f93bb029f042c00.tex b/sail_latex_riscv/fnz_update_sv48_pte_bits5dd960679bb9cad63f93bb029f042c00.tex new file mode 100644 index 00000000..a2ac01cd --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv48_pte_bits5dd960679bb9cad63f93bb029f042c00.tex @@ -0,0 +1,2 @@ +function _update_SV48_PTE_BITS (v, x) = let v = { v with SV48_PTE_chunk_0 = update_subrange_bits(v.SV48_PTE_chunk_0, 7, 0, subrange_bits(x, 7, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv48_pte_ext35aecfa61e536a6e82b25c27b17d2b27.tex b/sail_latex_riscv/fnz_update_sv48_pte_ext35aecfa61e536a6e82b25c27b17d2b27.tex new file mode 100644 index 00000000..ab459d2f --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv48_pte_ext35aecfa61e536a6e82b25c27b17d2b27.tex @@ -0,0 +1,2 @@ +function _update_SV48_PTE_Ext (v, x) = let v = { v with SV48_PTE_chunk_0 = update_subrange_bits(v.SV48_PTE_chunk_0, 63, 54, subrange_bits(x, 9, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv48_pte_ppni151ef3d95182ce7f10853d377fa591b3.tex b/sail_latex_riscv/fnz_update_sv48_pte_ppni151ef3d95182ce7f10853d377fa591b3.tex new file mode 100644 index 00000000..08be936a --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv48_pte_ppni151ef3d95182ce7f10853d377fa591b3.tex @@ -0,0 +1,2 @@ +function _update_SV48_PTE_PPNi (v, x) = let v = { v with SV48_PTE_chunk_0 = update_subrange_bits(v.SV48_PTE_chunk_0, 53, 10, subrange_bits(x, 43, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv48_pte_rsw6c601ebf0d644b711cbbe304a5538b5e.tex b/sail_latex_riscv/fnz_update_sv48_pte_rsw6c601ebf0d644b711cbbe304a5538b5e.tex new file mode 100644 index 00000000..28345404 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv48_pte_rsw6c601ebf0d644b711cbbe304a5538b5e.tex @@ -0,0 +1,2 @@ +function _update_SV48_PTE_RSW (v, x) = let v = { v with SV48_PTE_chunk_0 = update_subrange_bits(v.SV48_PTE_chunk_0, 9, 8, subrange_bits(x, 1, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv48_vaddr_bits591ffccf87e6224a472977f7dbf4b171.tex b/sail_latex_riscv/fnz_update_sv48_vaddr_bits591ffccf87e6224a472977f7dbf4b171.tex new file mode 100644 index 00000000..f0ef3916 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv48_vaddr_bits591ffccf87e6224a472977f7dbf4b171.tex @@ -0,0 +1,2 @@ +function _update_SV48_Vaddr_bits (v, x) = let v = { v with SV48_Vaddr_chunk_0 = update_subrange_bits(v.SV48_Vaddr_chunk_0, 47, 0, subrange_bits(x, 47, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv48_vaddr_pgofs474bdc293738ab8c86555518304df3b0.tex b/sail_latex_riscv/fnz_update_sv48_vaddr_pgofs474bdc293738ab8c86555518304df3b0.tex new file mode 100644 index 00000000..d0fee9e3 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv48_vaddr_pgofs474bdc293738ab8c86555518304df3b0.tex @@ -0,0 +1,2 @@ +function _update_SV48_Vaddr_PgOfs (v, x) = let v = { v with SV48_Vaddr_chunk_0 = update_subrange_bits(v.SV48_Vaddr_chunk_0, 11, 0, subrange_bits(x, 11, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_sv48_vaddr_vpni9035d832e2b055cf87646fbf4511fccb.tex b/sail_latex_riscv/fnz_update_sv48_vaddr_vpni9035d832e2b055cf87646fbf4511fccb.tex new file mode 100644 index 00000000..cc22bad7 --- /dev/null +++ b/sail_latex_riscv/fnz_update_sv48_vaddr_vpni9035d832e2b055cf87646fbf4511fccb.tex @@ -0,0 +1,2 @@ +function _update_SV48_Vaddr_VPNi (v, x) = let v = { v with SV48_Vaddr_chunk_0 = update_subrange_bits(v.SV48_Vaddr_chunk_0, 38, 12, subrange_bits(x, 26, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_uinterrupts_bits9c553d2ae4d62c448e09c704b0d8bba7.tex b/sail_latex_riscv/fnz_update_uinterrupts_bits9c553d2ae4d62c448e09c704b0d8bba7.tex new file mode 100644 index 00000000..583b3eb1 --- /dev/null +++ b/sail_latex_riscv/fnz_update_uinterrupts_bits9c553d2ae4d62c448e09c704b0d8bba7.tex @@ -0,0 +1,2 @@ +function _update_Uinterrupts_bits (v, x) = let v = { v with Uinterrupts_chunk_0 = update_subrange_bits(v.Uinterrupts_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_uinterrupts_ueib05aa22b4bb2fffd287cb5a502f86a7d.tex b/sail_latex_riscv/fnz_update_uinterrupts_ueib05aa22b4bb2fffd287cb5a502f86a7d.tex new file mode 100644 index 00000000..d29bdf0e --- /dev/null +++ b/sail_latex_riscv/fnz_update_uinterrupts_ueib05aa22b4bb2fffd287cb5a502f86a7d.tex @@ -0,0 +1,2 @@ +function _update_Uinterrupts_UEI (v, x) = let v = { v with Uinterrupts_chunk_0 = update_subrange_bits(v.Uinterrupts_chunk_0, 8, 8, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_uinterrupts_usi1ec1151a92f98583f7c0c3cb9f03ca01.tex b/sail_latex_riscv/fnz_update_uinterrupts_usi1ec1151a92f98583f7c0c3cb9f03ca01.tex new file mode 100644 index 00000000..878fe94b --- /dev/null +++ b/sail_latex_riscv/fnz_update_uinterrupts_usi1ec1151a92f98583f7c0c3cb9f03ca01.tex @@ -0,0 +1,2 @@ +function _update_Uinterrupts_USI (v, x) = let v = { v with Uinterrupts_chunk_0 = update_subrange_bits(v.Uinterrupts_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_uinterrupts_uti881f938d0d5ebb68be2d1bcc7637dc77.tex b/sail_latex_riscv/fnz_update_uinterrupts_uti881f938d0d5ebb68be2d1bcc7637dc77.tex new file mode 100644 index 00000000..1fc447aa --- /dev/null +++ b/sail_latex_riscv/fnz_update_uinterrupts_uti881f938d0d5ebb68be2d1bcc7637dc77.tex @@ -0,0 +1,2 @@ +function _update_Uinterrupts_UTI (v, x) = let v = { v with Uinterrupts_chunk_0 = update_subrange_bits(v.Uinterrupts_chunk_0, 4, 4, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_ustatus_bits58fc869676c24d63b7324b3ddc882d14.tex b/sail_latex_riscv/fnz_update_ustatus_bits58fc869676c24d63b7324b3ddc882d14.tex new file mode 100644 index 00000000..ebe7f579 --- /dev/null +++ b/sail_latex_riscv/fnz_update_ustatus_bits58fc869676c24d63b7324b3ddc882d14.tex @@ -0,0 +1,2 @@ +function _update_Ustatus_bits (v, x) = let v = { v with Ustatus_chunk_0 = update_subrange_bits(v.Ustatus_chunk_0, 63, 0, subrange_bits(x, 63, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_ustatus_uie937a13d13f328a695bd490140941d1ad.tex b/sail_latex_riscv/fnz_update_ustatus_uie937a13d13f328a695bd490140941d1ad.tex new file mode 100644 index 00000000..ecfe2c69 --- /dev/null +++ b/sail_latex_riscv/fnz_update_ustatus_uie937a13d13f328a695bd490140941d1ad.tex @@ -0,0 +1,2 @@ +function _update_Ustatus_UIE (v, x) = let v = { v with Ustatus_chunk_0 = update_subrange_bits(v.Ustatus_chunk_0, 0, 0, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnz_update_ustatus_upie620a46996c155948c916224ee8c0d297.tex b/sail_latex_riscv/fnz_update_ustatus_upie620a46996c155948c916224ee8c0d297.tex new file mode 100644 index 00000000..27716780 --- /dev/null +++ b/sail_latex_riscv/fnz_update_ustatus_upie620a46996c155948c916224ee8c0d297.tex @@ -0,0 +1,2 @@ +function _update_Ustatus_UPIE (v, x) = let v = { v with Ustatus_chunk_0 = update_subrange_bits(v.Ustatus_chunk_0, 4, 4, subrange_bits(x, 0, 0)) } in + v diff --git a/sail_latex_riscv/fnza64_barrier_domain_of_num6e122924ff562010f42f288ecc2cdbe3.tex b/sail_latex_riscv/fnza64_barrier_domain_of_num6e122924ff562010f42f288ecc2cdbe3.tex new file mode 100644 index 00000000..499c8a57 --- /dev/null +++ b/sail_latex_riscv/fnza64_barrier_domain_of_num6e122924ff562010f42f288ecc2cdbe3.tex @@ -0,0 +1,6 @@ +function a64_barrier_domain_of_num arg# = match arg# { + 0 => A64_FullShare, + 1 => A64_InnerShare, + 2 => A64_OuterShare, + _ => A64_NonShare +} diff --git a/sail_latex_riscv/fnza64_barrier_type_of_numc06c55fe3b04f35ecb4741ea01acc85e.tex b/sail_latex_riscv/fnza64_barrier_type_of_numc06c55fe3b04f35ecb4741ea01acc85e.tex new file mode 100644 index 00000000..57cc95db --- /dev/null +++ b/sail_latex_riscv/fnza64_barrier_type_of_numc06c55fe3b04f35ecb4741ea01acc85e.tex @@ -0,0 +1,5 @@ +function a64_barrier_type_of_num arg# = match arg# { + 0 => A64_barrier_all, + 1 => A64_barrier_LD, + _ => A64_barrier_ST +} diff --git a/sail_latex_riscv/fnzaccesstype_to_str58f7a46d6b3e326411426e3cf0fe52cf.tex b/sail_latex_riscv/fnzaccesstype_to_str58f7a46d6b3e326411426e3cf0fe52cf.tex new file mode 100644 index 00000000..90c31f90 --- /dev/null +++ b/sail_latex_riscv/fnzaccesstype_to_str58f7a46d6b3e326411426e3cf0fe52cf.tex @@ -0,0 +1,12 @@ +function #\hyperref[sailRISCVzaccessTypezytozystr]{accessType\_to\_str}# (a) = + match (a) { + #\hyperref[sailRISCVzRead]{Read}#(Data) => "R", + #\hyperref[sailRISCVzWrite]{Write}#(Data) => "W", + #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Data, Data) => "RW", + #\hyperref[sailRISCVzRead]{Read}#(Cap) => "RC", + #\hyperref[sailRISCVzWrite]{Write}#(Cap) => "WC", + #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Cap, Cap) => "RCWC", + #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Data, Cap) => "RWC", + #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Cap, Data) => "RCW", + #\hyperref[sailRISCVzExecute]{Execute}#() => "X" + } diff --git a/sail_latex_riscv/fnzaccrue_fflags6f6e494f89bde56691f40e88b063e194.tex b/sail_latex_riscv/fnzaccrue_fflags6f6e494f89bde56691f40e88b063e194.tex new file mode 100644 index 00000000..670512e6 --- /dev/null +++ b/sail_latex_riscv/fnzaccrue_fflags6f6e494f89bde56691f40e88b063e194.tex @@ -0,0 +1,9 @@ +function #\hyperref[sailRISCVzaccruezyfflags]{accrue\_fflags}#(flags) = { + let f = fcsr.#\hyperref[sailRISCVzFFLAGS]{FFLAGS}#() | flags; + if fcsr.#\hyperref[sailRISCVzFFLAGS]{FFLAGS}#() != f + then { + fcsr->#\hyperref[sailRISCVzFFLAGS]{FFLAGS}#() = f; + #\hyperref[sailRISCVzupdatezysoftfloatzyfflags]{update\_softfloat\_fflags}#(f); + #\hyperref[sailRISCVzdirtyzyfdzycontext]{dirty\_fd\_context}#(); + } +} diff --git a/sail_latex_riscv/fnzadd_to_tlb39f45d8d071e2986dede49d7c2109cd4f5.tex b/sail_latex_riscv/fnzadd_to_tlb39f45d8d071e2986dede49d7c2109cd4f5.tex new file mode 100644 index 00000000..ee0f0971 --- /dev/null +++ b/sail_latex_riscv/fnzadd_to_tlb39f45d8d071e2986dede49d7c2109cd4f5.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzaddzytozyTLB39]{add\_to\_TLB39}#(asid, vAddr, pAddr, pte, pteAddr, level, global) = { + let ent : TLB39_Entry = #\hyperref[sailRISCVzmakezyTLBzyEntry]{make\_TLB\_Entry}#(asid, global, vAddr, pAddr, pte.#\hyperref[sailRISCVzbits]{bits}#(), level, pteAddr, SV39_LEVEL_BITS); + tlb39 = #\hyperref[sailRISCVzSome]{Some}#(ent) +} diff --git a/sail_latex_riscv/fnzadd_to_tlb48a08cb99b91f9c80121525cc743b92593.tex b/sail_latex_riscv/fnzadd_to_tlb48a08cb99b91f9c80121525cc743b92593.tex new file mode 100644 index 00000000..e4e35b27 --- /dev/null +++ b/sail_latex_riscv/fnzadd_to_tlb48a08cb99b91f9c80121525cc743b92593.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzaddzytozyTLB48]{add\_to\_TLB48}#(asid, vAddr, pAddr, pte, pteAddr, level, global) = { + let ent : TLB48_Entry = #\hyperref[sailRISCVzmakezyTLBzyEntry]{make\_TLB\_Entry}#(asid, global, vAddr, pAddr, pte.#\hyperref[sailRISCVzbits]{bits}#(), level, pteAddr, SV48_LEVEL_BITS); + tlb48 = #\hyperref[sailRISCVzSome]{Some}#(ent) +} diff --git a/sail_latex_riscv/fnzaddr_to_tag_addr21cfb55575f4fc24f9ec71484b7d4eb8.tex b/sail_latex_riscv/fnzaddr_to_tag_addr21cfb55575f4fc24f9ec71484b7d4eb8.tex new file mode 100644 index 00000000..71e7e840 --- /dev/null +++ b/sail_latex_riscv/fnzaddr_to_tag_addr21cfb55575f4fc24f9ec71484b7d4eb8.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzaddrzytozytagzyaddr]{addr\_to\_tag\_addr}#(addr : xlenbits) -> tagaddrbits = #\hyperref[sailRISCVztruncateLSB]{truncateLSB}#(addr, sizeof(xlen) - log2_cap_size) diff --git a/sail_latex_riscv/fnzamoop_of_num66fc14378761bc8bd8137ac63cffe431.tex b/sail_latex_riscv/fnzamoop_of_num66fc14378761bc8bd8137ac63cffe431.tex new file mode 100644 index 00000000..f4666837 --- /dev/null +++ b/sail_latex_riscv/fnzamoop_of_num66fc14378761bc8bd8137ac63cffe431.tex @@ -0,0 +1,11 @@ +function amoop_of_num arg# = match arg# { + 0 => AMOSWAP, + 1 => AMOADD, + 2 => AMOXOR, + 3 => AMOAND, + 4 => AMOOR, + 5 => AMOMIN, + 6 => AMOMAX, + 7 => AMOMINU, + _ => AMOMAXU +} diff --git a/sail_latex_riscv/fnzaqrl_str43f7a950ecb4ae033c3d54ba744ac285.tex b/sail_latex_riscv/fnzaqrl_str43f7a950ecb4ae033c3d54ba744ac285.tex new file mode 100644 index 00000000..04bd48ce --- /dev/null +++ b/sail_latex_riscv/fnzaqrl_str43f7a950ecb4ae033c3d54ba744ac285.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzaqrlzystr]{aqrl\_str}#(aq : bool, rl : bool) -> string = + match (aq, rl) { + (false, false) => "", + (false, true) => ".rl", + (true, false) => ".aq", + (true, true) => ".aqrl" + } diff --git a/sail_latex_riscv/fnzarch_to_bits5b82edd15605cd21ec0f9d9dc63af541.tex b/sail_latex_riscv/fnzarch_to_bits5b82edd15605cd21ec0f9d9dc63af541.tex new file mode 100644 index 00000000..368de0e3 --- /dev/null +++ b/sail_latex_riscv/fnzarch_to_bits5b82edd15605cd21ec0f9d9dc63af541.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzarchzytozybits]{arch\_to\_bits}#(a : Architecture) -> arch_xlen = + match (a) { + RV32 => 0b01, + RV64 => 0b10, + RV128 => 0b11 + } diff --git a/sail_latex_riscv/fnzarchitecture892e99af11725086f28c1c30cefffa9c.tex b/sail_latex_riscv/fnzarchitecture892e99af11725086f28c1c30cefffa9c.tex new file mode 100644 index 00000000..06b54af9 --- /dev/null +++ b/sail_latex_riscv/fnzarchitecture892e99af11725086f28c1c30cefffa9c.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzarchitecture]{architecture}#(a : arch_xlen) -> #\hyperref[sailRISCVzoption]{option}#(Architecture) = + match (a) { + 0b01 => #\hyperref[sailRISCVzSome]{Some}#(RV32), + 0b10 => #\hyperref[sailRISCVzSome]{Some}#(RV64), + 0b11 => #\hyperref[sailRISCVzSome]{Some}#(RV128), + _ => #\hyperref[sailRISCVzNone]{None}#() + } diff --git a/sail_latex_riscv/fnzarchitecture_of_num798cfe8625bb4fedb9343d4984208b4c.tex b/sail_latex_riscv/fnzarchitecture_of_num798cfe8625bb4fedb9343d4984208b4c.tex new file mode 100644 index 00000000..c36f1af3 --- /dev/null +++ b/sail_latex_riscv/fnzarchitecture_of_num798cfe8625bb4fedb9343d4984208b4c.tex @@ -0,0 +1,5 @@ +function Architecture_of_num arg# = match arg# { + 0 => RV32, + 1 => RV64, + _ => RV128 +} diff --git a/sail_latex_riscv/fnzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex b/sail_latex_riscv/fnzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex new file mode 100644 index 00000000..dd7d295f --- /dev/null +++ b/sail_latex_riscv/fnzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex @@ -0,0 +1,4 @@ +function bit_to_bool b = match b { + bitone => true, + bitzero => false +} diff --git a/sail_latex_riscv/fnzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex b/sail_latex_riscv/fnzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex new file mode 100644 index 00000000..d20ce1c9 --- /dev/null +++ b/sail_latex_riscv/fnzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex @@ -0,0 +1 @@ +function bool_to_bit x = if x then bitone else bitzero diff --git a/sail_latex_riscv/fnzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex b/sail_latex_riscv/fnzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex new file mode 100644 index 00000000..99075369 --- /dev/null +++ b/sail_latex_riscv/fnzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex @@ -0,0 +1 @@ +function bool_to_bits x = if x then 0b1 else 0b0 diff --git a/sail_latex_riscv/fnzbop_of_num74cd9479863c5a21d66fa86ae45f1bd5.tex b/sail_latex_riscv/fnzbop_of_num74cd9479863c5a21d66fa86ae45f1bd5.tex new file mode 100644 index 00000000..24a03846 --- /dev/null +++ b/sail_latex_riscv/fnzbop_of_num74cd9479863c5a21d66fa86ae45f1bd5.tex @@ -0,0 +1,8 @@ +function bop_of_num arg# = match arg# { + 0 => RISCV_BEQ, + 1 => RISCV_BNE, + 2 => RISCV_BLT, + 3 => RISCV_BGE, + 4 => RISCV_BLTU, + _ => RISCV_BGEU +} diff --git a/sail_latex_riscv/fnzcache_op_kind_of_num612a346f1c1edf9d5bae987ac9d9912c.tex b/sail_latex_riscv/fnzcache_op_kind_of_num612a346f1c1edf9d5bae987ac9d9912c.tex new file mode 100644 index 00000000..c945d7f2 --- /dev/null +++ b/sail_latex_riscv/fnzcache_op_kind_of_num612a346f1c1edf9d5bae987ac9d9912c.tex @@ -0,0 +1,13 @@ +function cache_op_kind_of_num arg# = match arg# { + 0 => Cache_op_D_IVAC, + 1 => Cache_op_D_ISW, + 2 => Cache_op_D_CSW, + 3 => Cache_op_D_CISW, + 4 => Cache_op_D_ZVA, + 5 => Cache_op_D_CVAC, + 6 => Cache_op_D_CVAU, + 7 => Cache_op_D_CIVAC, + 8 => Cache_op_I_IALLUIS, + 9 => Cache_op_I_IALLU, + _ => Cache_op_I_IVAU +} diff --git a/sail_latex_riscv/fnzcanonical_nan_d7d468e933fb666b50bdf56e90272edf5.tex b/sail_latex_riscv/fnzcanonical_nan_d7d468e933fb666b50bdf56e90272edf5.tex new file mode 100644 index 00000000..faf3ee3f --- /dev/null +++ b/sail_latex_riscv/fnzcanonical_nan_d7d468e933fb666b50bdf56e90272edf5.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzcanonicalzyNaNzyD]{canonical\_NaN\_D}#() -> #\hyperref[sailRISCVzbits]{bits}#(64) = 0x_7ff8_0000_0000_0000 diff --git a/sail_latex_riscv/fnzcanonical_nan_s21045df28a8988e296d9749590d92369.tex b/sail_latex_riscv/fnzcanonical_nan_s21045df28a8988e296d9749590d92369.tex new file mode 100644 index 00000000..f76870e3 --- /dev/null +++ b/sail_latex_riscv/fnzcanonical_nan_s21045df28a8988e296d9749590d92369.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzcanonicalzyNaNzyS]{canonical\_NaN\_S}#() -> #\hyperref[sailRISCVzbits]{bits}#(32) = 0x_7fc0_0000 diff --git a/sail_latex_riscv/fnzcap_reg_name_abi719d69842e8a63e886ffe0791675d4e0.tex b/sail_latex_riscv/fnzcap_reg_name_abi719d69842e8a63e886ffe0791675d4e0.tex new file mode 100644 index 00000000..688727a1 --- /dev/null +++ b/sail_latex_riscv/fnzcap_reg_name_abi719d69842e8a63e886ffe0791675d4e0.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzcapzyregzynamezyabi]{cap\_reg\_name\_abi}#(r) = { + match (r) { + 0b00000 => "cnull", + _ => "c" ^ #\hyperref[sailRISCVzregzynamezyabi]{reg\_name\_abi}#(r) + } +} diff --git a/sail_latex_riscv/fnzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex b/sail_latex_riscv/fnzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex new file mode 100644 index 00000000..198b327e --- /dev/null +++ b/sail_latex_riscv/fnzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex @@ -0,0 +1,52 @@ +function #\hyperref[sailRISCVzcapBitsToCapability]{capBitsToCapability}#(t, c) : (bool, CapBits) -> Capability = { + internal_exponent : bool = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[90]); + otype : #\hyperref[sailRISCVzbits]{bits}#(18) = c[108..91]; + E : #\hyperref[sailRISCVzbits]{bits}#(6) = #\hyperref[sailRISCVzzzeros]{zeros}#(); + Bs : #\hyperref[sailRISCVzbits]{bits}#(14) = #\hyperref[sailRISCVzzzeros]{zeros}#(); + T : #\hyperref[sailRISCVzbits]{bits}#(12) = #\hyperref[sailRISCVzzzeros]{zeros}#(); + lenMSBs : #\hyperref[sailRISCVzbits]{bits}#(2) = #\hyperref[sailRISCVzzzeros]{zeros}#(); + if internal_exponent then { + /* Exponent stored instead of T[2..0] and B[2..0] */ + E = c[80..78] @ c [66..64]; + /* Exponent chosen so that length MSBs is 01 */ + lenMSBs = 0b01; + T = c[89..81] @ 0b000; + Bs = c[77..67] @ 0b000; + } else { + /* Exponent zero */ + lenMSBs = 0b00; + T = c[89..78]; + Bs = c[77..64]; + }; + /* Reconstruct top two bits of T given T = B + len and: + * 1) the top two bits of B + * 2) most significant two bits of length derived from format above + * 3) carry out of B[20..0] + len[20..0] that is implied if T[20..0] < B[20..0] + */ + carry_out = if T <_u Bs[11..0] then 0b01 else 0b00; + Ttop2 = Bs[13..12] + lenMSBs + carry_out; + return struct { + tag = t, + uperms = c[127..124], + permit_set_CID = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[123]), + access_system_regs = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[122]), + permit_unseal = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[121]), + permit_cinvoke = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[120]), + permit_seal = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[119]), + permit_store_local_cap = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[118]), + permit_store_cap = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[117]), + permit_load_cap = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[116]), + permit_store = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[115]), + permit_load = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[114]), + permit_execute = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[113]), + global = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[112]), + reserved = c[111..110], + flag_cap_mode = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(c[109]), + internal_e = internal_exponent, + E = E, + B = Bs, + T = Ttop2 @ T, + otype = otype, + address = c[63..0] + } +} diff --git a/sail_latex_riscv/fnzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex b/sail_latex_riscv/fnzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex new file mode 100644 index 00000000..9b7a4bd0 --- /dev/null +++ b/sail_latex_riscv/fnzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzcapBoundsEqual]{capBoundsEqual}# (c1, c2) : (Capability, Capability) -> bool = + let (base1, top1) = #\hyperref[sailRISCVzgetCapBounds]{getCapBounds}#(c1) in + let (base2, top2) = #\hyperref[sailRISCVzgetCapBounds]{getCapBounds}#(c2) in + (base1 == base2) & (top1 == top2) diff --git a/sail_latex_riscv/fnzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex b/sail_latex_riscv/fnzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex new file mode 100644 index 00000000..44808f2f --- /dev/null +++ b/sail_latex_riscv/fnzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex @@ -0,0 +1,26 @@ +function CapEx_of_num arg# = match arg# { + 0 => CapEx_None, + 1 => CapEx_LengthViolation, + 2 => CapEx_TagViolation, + 3 => CapEx_SealViolation, + 4 => CapEx_TypeViolation, + 5 => CapEx_CallTrap, + 6 => CapEx_ReturnTrap, + 7 => CapEx_TSSUnderFlow, + 8 => CapEx_UserDefViolation, + 9 => CapEx_InexactBounds, + 10 => CapEx_UnalignedBase, + 11 => CapEx_GlobalViolation, + 12 => CapEx_PermitExecuteViolation, + 13 => CapEx_PermitLoadViolation, + 14 => CapEx_PermitStoreViolation, + 15 => CapEx_PermitLoadCapViolation, + 16 => CapEx_PermitStoreCapViolation, + 17 => CapEx_PermitStoreLocalCapViolation, + 18 => CapEx_PermitSealViolation, + 19 => CapEx_AccessSystemRegsViolation, + 20 => CapEx_PermitCInvokeViolation, + 21 => CapEx_AccessCInvokeIDCViolation, + 22 => CapEx_PermitUnsealViolation, + _ => CapEx_PermitSetCIDViolation +} diff --git a/sail_latex_riscv/fnzcapexcodee065d40e92bb99703db21c8c18bedf11.tex b/sail_latex_riscv/fnzcapexcodee065d40e92bb99703db21c8c18bedf11.tex new file mode 100644 index 00000000..fcbf7ac2 --- /dev/null +++ b/sail_latex_riscv/fnzcapexcodee065d40e92bb99703db21c8c18bedf11.tex @@ -0,0 +1,27 @@ +function #\hyperref[sailRISCVzCapExCode]{CapExCode}#(ex) : CapEx -> #\hyperref[sailRISCVzbits]{bits}#(5) = + match ex { + CapEx_None => 0b00000, + CapEx_LengthViolation => 0b00001, + CapEx_TagViolation => 0b00010, + CapEx_SealViolation => 0b00011, + CapEx_TypeViolation => 0b00100, + CapEx_CallTrap => 0b00101, + CapEx_ReturnTrap => 0b00110, + CapEx_TSSUnderFlow => 0b00111, + CapEx_UserDefViolation => 0b01000, + CapEx_InexactBounds => 0b01010, + CapEx_UnalignedBase => 0b01011, + CapEx_GlobalViolation => 0b10000, + CapEx_PermitExecuteViolation => 0b10001, + CapEx_PermitLoadViolation => 0b10010, + CapEx_PermitStoreViolation => 0b10011, + CapEx_PermitLoadCapViolation => 0b10100, + CapEx_PermitStoreCapViolation => 0b10101, + CapEx_PermitStoreLocalCapViolation => 0b10110, + CapEx_PermitSealViolation => 0b10111, + CapEx_AccessSystemRegsViolation => 0b11000, + CapEx_PermitCInvokeViolation => 0b11001, + CapEx_AccessCInvokeIDCViolation => 0b11010, + CapEx_PermitUnsealViolation => 0b11011, + CapEx_PermitSetCIDViolation => 0b11100 + } diff --git a/sail_latex_riscv/fnzcaptobits025010a6e8c284beecc438f72babcc70.tex b/sail_latex_riscv/fnzcaptobits025010a6e8c284beecc438f72babcc70.tex new file mode 100644 index 00000000..d406b9f4 --- /dev/null +++ b/sail_latex_riscv/fnzcaptobits025010a6e8c284beecc438f72babcc70.tex @@ -0,0 +1,22 @@ +function #\hyperref[sailRISCVzcapToBits]{capToBits}#(cap) : Capability -> CapBits = { + t_hi : #\hyperref[sailRISCVzbits]{bits}#(cap_mantissa_width - 5) = cap.T[cap_mantissa_width - 3..3]; + t_lo : #\hyperref[sailRISCVzbits]{bits}#(3) = cap.T[2..0]; + b_hi : #\hyperref[sailRISCVzbits]{bits}#(cap_mantissa_width - 3) = cap.B[cap_mantissa_width - 1..3]; + b_lo : #\hyperref[sailRISCVzbits]{bits}#(3) = cap.B[2..0]; + if cap.internal_e then { + t_lo = cap.E[5..3]; + b_lo = cap.E[2..0]; + }; + return (cap.uperms + @ #\hyperref[sailRISCVzgetCapHardPerms]{getCapHardPerms}#(cap) + @ cap.reserved + @ #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.flag_cap_mode) + @ cap.otype + @ #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.internal_e) + @ t_hi + @ t_lo + @ b_hi + @ b_lo + @ cap.address + ); +} diff --git a/sail_latex_riscv/fnzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex b/sail_latex_riscv/fnzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex new file mode 100644 index 00000000..a561e5f2 --- /dev/null +++ b/sail_latex_riscv/fnzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzcapToMemBits]{capToMemBits}#(cap) : Capability -> CapBits = + #\hyperref[sailRISCVzcapToBits]{capToBits}#(cap) ^ null_cap_bits diff --git a/sail_latex_riscv/fnzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex b/sail_latex_riscv/fnzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex new file mode 100644 index 00000000..027c3c1e --- /dev/null +++ b/sail_latex_riscv/fnzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex @@ -0,0 +1,19 @@ +function #\hyperref[sailRISCVzcapToString]{capToString}# (cap) = { + let len = #\hyperref[sailRISCVzgetCapLength]{getCapLength}#(cap); + let len_str = #\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVztozybits]{to\_bits}#(cap_len_width + 3, len)); + /* Print architectural type which is -1 for unsealed caps */ + let otype64 : CapAddrBits = if #\hyperref[sailRISCVzhasReservedOType]{hasReservedOType}#(cap) then #\hyperref[sailRISCVzEXTS]{EXTS}#(cap.otype) else #\hyperref[sailRISCVzEXTZ]{EXTZ}#(cap.otype); + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(" t:", + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(if cap.tag then "1" else "0", + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(" s:", + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cap) then "1" else "0", + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(" perms:", + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(#\hyperref[sailRISCVzBitStr]{BitStr}#(0b0 @ #\hyperref[sailRISCVzgetCapPerms]{getCapPerms}#(cap)), + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(" type:", + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(#\hyperref[sailRISCVzBitStr]{BitStr}#(otype64), + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(" offset:", + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(#\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(cap)), + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(" base:", + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(#\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(cap)), + #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(" length:", len_str))))))))))))) +} diff --git a/sail_latex_riscv/fnzcheck_counteren24e3081662742c5feea4ad876dc0a51c.tex b/sail_latex_riscv/fnzcheck_counteren24e3081662742c5feea4ad876dc0a51c.tex new file mode 100644 index 00000000..d5b16e73 --- /dev/null +++ b/sail_latex_riscv/fnzcheck_counteren24e3081662742c5feea4ad876dc0a51c.tex @@ -0,0 +1,15 @@ +function #\hyperref[sailRISCVzcheckzyCounteren]{check\_Counteren}#(csr : csreg, p : Privilege) -> bool = + match(csr, p) { + (0xC00, Supervisor) => mcounteren.#\hyperref[sailRISCVzCY]{CY}#() == 0b1, + (0xC01, Supervisor) => mcounteren.#\hyperref[sailRISCVzTM]{TM}#() == 0b1, + (0xC02, Supervisor) => mcounteren.#\hyperref[sailRISCVzIR]{IR}#() == 0b1, + + (0xC00, User) => mcounteren.#\hyperref[sailRISCVzCY]{CY}#() == 0b1 & ((~ (#\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#())) | scounteren.#\hyperref[sailRISCVzCY]{CY}#() == 0b1), + (0xC01, User) => mcounteren.#\hyperref[sailRISCVzTM]{TM}#() == 0b1 & ((~ (#\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#())) | scounteren.#\hyperref[sailRISCVzTM]{TM}#() == 0b1), + (0xC02, User) => mcounteren.#\hyperref[sailRISCVzIR]{IR}#() == 0b1 & ((~ (#\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#())) | scounteren.#\hyperref[sailRISCVzIR]{IR}#() == 0b1), + + (_, _) => /* no HPM counters for now */ + if 0xC03 <=_u csr & csr <=_u 0xC1F + then false + else true + } diff --git a/sail_latex_riscv/fnzcheck_csr588ba7a7f36d1f6476f0b3640406ee0a.tex b/sail_latex_riscv/fnzcheck_csr588ba7a7f36d1f6476f0b3640406ee0a.tex new file mode 100644 index 00000000..3bc447f2 --- /dev/null +++ b/sail_latex_riscv/fnzcheck_csr588ba7a7f36d1f6476f0b3640406ee0a.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzcheckzyCSR]{check\_CSR}#(csr : csreg, p : Privilege, isWrite : bool) -> bool = + #\hyperref[sailRISCVziszyCSRzydefined]{is\_CSR\_defined}#(csr, p) + & #\hyperref[sailRISCVzcheckzyCSRzyaccess]{check\_CSR\_access}#(#\hyperref[sailRISCVzcsrAccess]{csrAccess}#(csr), #\hyperref[sailRISCVzcsrPriv]{csrPriv}#(csr), p, isWrite) + & #\hyperref[sailRISCVzcheckzyTVMzySATP]{check\_TVM\_SATP}#(csr, p) + & #\hyperref[sailRISCVzcheckzyCounteren]{check\_Counteren}#(csr, p) diff --git a/sail_latex_riscv/fnzcheck_csr_access77b52cf2ed56bd5489c2fcc29e6efff7.tex b/sail_latex_riscv/fnzcheck_csr_access77b52cf2ed56bd5489c2fcc29e6efff7.tex new file mode 100644 index 00000000..a3a6251e --- /dev/null +++ b/sail_latex_riscv/fnzcheck_csr_access77b52cf2ed56bd5489c2fcc29e6efff7.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzcheckzyCSRzyaccess]{check\_CSR\_access}#(csrrw, csrpr, p, isWrite) = + (~ (isWrite == true & csrrw == 0b11)) /* read/write */ + & (#\hyperref[sailRISCVzprivLevelzytozybits]{privLevel\_to\_bits}#(p) >=_u csrpr) /* privilege */ diff --git a/sail_latex_riscv/fnzcheck_misaligned6730e75ccee79325a38a992b6314fd91.tex b/sail_latex_riscv/fnzcheck_misaligned6730e75ccee79325a38a992b6314fd91.tex new file mode 100644 index 00000000..f6a25a37 --- /dev/null +++ b/sail_latex_riscv/fnzcheck_misaligned6730e75ccee79325a38a992b6314fd91.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzcheckzymisaligned]{check\_misaligned}#(vaddr : xlenbits, width : word_width) -> bool = + if #\hyperref[sailRISCVzplatzyenablezymisalignedzyaccess]{plat\_enable\_misaligned\_access}#() then false + else match width { + BYTE => false, + HALF => vaddr[0] == bitone, + WORD => vaddr[0] == bitone | vaddr[1] == bitone, + DOUBLE => vaddr[0] == bitone | vaddr[1] == bitone | vaddr[2] == bitone + } diff --git a/sail_latex_riscv/fnzcheck_res_misalignede05ad7adc37fbdff34459806aaddc074.tex b/sail_latex_riscv/fnzcheck_res_misalignede05ad7adc37fbdff34459806aaddc074.tex new file mode 100644 index 00000000..f1871c2e --- /dev/null +++ b/sail_latex_riscv/fnzcheck_res_misalignede05ad7adc37fbdff34459806aaddc074.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzcheckzyreszymisaligned]{check\_res\_misaligned}#(vaddr : xlenbits, width : word_width) -> bool = + match width { + BYTE => false, + HALF => vaddr[0] == bitone, + WORD => vaddr[0] == bitone | vaddr[1] == bitone, + DOUBLE => vaddr[0] == bitone | vaddr[1] == bitone | vaddr[2] == bitone + } diff --git a/sail_latex_riscv/fnzcheck_tvm_satp8e66c1c4a67c389d24c42619a3634b21.tex b/sail_latex_riscv/fnzcheck_tvm_satp8e66c1c4a67c389d24c42619a3634b21.tex new file mode 100644 index 00000000..92c70a08 --- /dev/null +++ b/sail_latex_riscv/fnzcheck_tvm_satp8e66c1c4a67c389d24c42619a3634b21.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzcheckzyTVMzySATP]{check\_TVM\_SATP}#(csr : csreg, p : Privilege) -> bool = + ~ (csr == 0x180 & p == Supervisor & mstatus.#\hyperref[sailRISCVzTVM]{TVM}#() == 0b1) diff --git a/sail_latex_riscv/fnzchecked_mem_read46a92fcd62c31279edfc3bc18c424fa0.tex b/sail_latex_riscv/fnzchecked_mem_read46a92fcd62c31279edfc3bc18c424fa0.tex new file mode 100644 index 00000000..3a5e0577 --- /dev/null +++ b/sail_latex_riscv/fnzchecked_mem_read46a92fcd62c31279edfc3bc18c424fa0.tex @@ -0,0 +1,10 @@ +function checked_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : #\hyperref[sailRISCVzAccessType]{AccessType}#(ext_access_type), paddr : xlenbits, width : atom('n), aq : bool, rl : bool, res: bool, meta : bool) -> #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#((#\hyperref[sailRISCVzbits]{bits}#(8 * 'n), mem_meta)) = + if #\hyperref[sailRISCVzwithinzymmiozyreadable]{within\_mmio\_readable}#(paddr, width) + then #\hyperref[sailRISCVzMemoryOpResultzyaddzymeta]{MemoryOpResult\_add\_meta}#(#\hyperref[sailRISCVzmmiozyread]{mmio\_read}#(t, paddr, width), default_meta) + else if #\hyperref[sailRISCVzwithinzyphyszymem]{within\_phys\_mem}#(paddr, width) + then #\hyperref[sailRISCVzphyszymemzyread]{phys\_mem\_read}#(t, paddr, width, aq, rl, res, meta) + else match t { + #\hyperref[sailRISCVzExecute]{Execute}#() => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzyFetchzyAccesszyFault]{E\_Fetch\_Access\_Fault}#()), + #\hyperref[sailRISCVzRead]{Read}#(Data) => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzyLoadzyAccesszyFault]{E\_Load\_Access\_Fault}#()), + _ => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#()) + } diff --git a/sail_latex_riscv/fnzchecked_mem_write765e0693788c9f4b01c2243ece39909e.tex b/sail_latex_riscv/fnzchecked_mem_write765e0693788c9f4b01c2243ece39909e.tex new file mode 100644 index 00000000..b158f509 --- /dev/null +++ b/sail_latex_riscv/fnzchecked_mem_write765e0693788c9f4b01c2243ece39909e.tex @@ -0,0 +1,6 @@ +function checked_mem_write forall 'n, 0 < 'n <= max_mem_access . (wk : write_kind, paddr : xlenbits, width : atom('n), data: #\hyperref[sailRISCVzbits]{bits}#(8 * 'n), meta: mem_meta) -> #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(bool) = + if #\hyperref[sailRISCVzwithinzymmiozywritable]{within\_mmio\_writable}#(paddr, width) + then #\hyperref[sailRISCVzmmiozywrite]{mmio\_write}#(paddr, width, data) + else if #\hyperref[sailRISCVzwithinzyphyszymem]{within\_phys\_mem}#(paddr, width) + then #\hyperref[sailRISCVzphyszymemzywrite]{phys\_mem\_write}#(wk, paddr, width, data, meta) + else #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#()) diff --git a/sail_latex_riscv/fnzcheckptepermissione94004ed8067442121c54ab1b95848d0.tex b/sail_latex_riscv/fnzcheckptepermissione94004ed8067442121c54ab1b95848d0.tex new file mode 100644 index 00000000..5345563d --- /dev/null +++ b/sail_latex_riscv/fnzcheckptepermissione94004ed8067442121c54ab1b95848d0.tex @@ -0,0 +1,52 @@ +function #\hyperref[sailRISCVzcheckPTEPermission]{checkPTEPermission}#(ac : #\hyperref[sailRISCVzAccessType]{AccessType}#(ext_access_type), priv : Privilege, mxr : bool, do_sum : bool, p : PTE_Bits, ext : extPte, ext_ptw : ext_ptw) -> PTE_Check = { + /* + * Although in many cases MXR doesn't make sense for capabilities, we honour + * it for three reasons: + * + * 1. It provides uniformity rather than giving strange and surprising edge cases. + * + * 2. The tag-dependence of stores is achieved by passing Data in for untagged + * capabilities. Thus, not honouring MXR for capabilities would result in + * differences in whether MXR had an effect based on the tag. + * + * 3. It's simpler to implement yet still #\hyperref[sailRISCVzsafe]{safe}# (LC is unaffected by MXR). + */ + let base_succ : bool = + match (ac, priv) { + (#\hyperref[sailRISCVzRead]{Read}#(_), User) => p.#\hyperref[sailRISCVzU]{U}#() == 0b1 & (p.#\hyperref[sailRISCVzR]{R}#() == 0b1 | (p.#\hyperref[sailRISCVzX]{X}#() == 0b1 & mxr)), + (#\hyperref[sailRISCVzWrite]{Write}#(_), User) => p.#\hyperref[sailRISCVzU]{U}#() == 0b1 & p.#\hyperref[sailRISCVzW]{W}#() == 0b1, + (#\hyperref[sailRISCVzReadWrite]{ReadWrite}#(_), User) => p.#\hyperref[sailRISCVzU]{U}#() == 0b1 & p.#\hyperref[sailRISCVzW]{W}#() == 0b1 & (p.#\hyperref[sailRISCVzR]{R}#() == 0b1 | (p.#\hyperref[sailRISCVzX]{X}#() == 0b1 & mxr)), + (#\hyperref[sailRISCVzExecute]{Execute}#(), User) => p.#\hyperref[sailRISCVzU]{U}#() == 0b1 & p.#\hyperref[sailRISCVzX]{X}#() == 0b1, + + (#\hyperref[sailRISCVzRead]{Read}#(_), Supervisor) => (p.#\hyperref[sailRISCVzU]{U}#() == 0b0 | do_sum) & (p.#\hyperref[sailRISCVzR]{R}#() == 0b1 | (p.#\hyperref[sailRISCVzX]{X}#() == 0b1 & mxr)), + (#\hyperref[sailRISCVzWrite]{Write}#(_), Supervisor) => (p.#\hyperref[sailRISCVzU]{U}#() == 0b0 | do_sum) & p.#\hyperref[sailRISCVzW]{W}#() == 0b1, + (#\hyperref[sailRISCVzReadWrite]{ReadWrite}#(_), Supervisor) => (p.#\hyperref[sailRISCVzU]{U}#() == 0b0 | do_sum) & p.#\hyperref[sailRISCVzW]{W}#() == 0b1 & (p.#\hyperref[sailRISCVzR]{R}#() == 0b1 | (p.#\hyperref[sailRISCVzX]{X}#() == 0b1 & mxr)), + (#\hyperref[sailRISCVzExecute]{Execute}#(), Supervisor) => p.#\hyperref[sailRISCVzU]{U}#() == 0b0 & p.#\hyperref[sailRISCVzX]{X}#() == 0b1, + + (_, Machine) => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("m-mode mem perm check") + }; + + let e = #\hyperref[sailRISCVzMkzyExtzyPTEzyBits]{Mk\_Ext\_PTE\_Bits}#(ext); + let ptw_lc = if e.#\hyperref[sailRISCVzCapRead]{CapRead}#() == 0b1 then PTW_LC_OK else PTW_LC_CLEAR; + let ptw_sc = if e.#\hyperref[sailRISCVzCapWrite]{CapWrite}#() == 0b1 then PTW_SC_OK else PTW_SC_TRAP; + let (succ, ext_ptw') : (bool, ext_ptw) = + match (base_succ, ac) { + /* Base translation exceptions take priority over CHERI exceptions */ + (false, _) => (false, init_ext_ptw), + + (true, #\hyperref[sailRISCVzRead]{Read}#(Cap)) => (true, #\hyperref[sailRISCVzextzyptwzylczyjoin]{ext\_ptw\_lc\_join}#(ext_ptw, ptw_lc)), + (true, #\hyperref[sailRISCVzWrite]{Write}#(Cap)) => (true, #\hyperref[sailRISCVzextzyptwzysczyjoin]{ext\_ptw\_sc\_join}#(ext_ptw, ptw_sc)), + (true, #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Data, Cap)) => (true, #\hyperref[sailRISCVzextzyptwzysczyjoin]{ext\_ptw\_sc\_join}#(ext_ptw, ptw_sc)), + (true, #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Cap, Data)) => (true, #\hyperref[sailRISCVzextzyptwzylczyjoin]{ext\_ptw\_lc\_join}#(ext_ptw, ptw_lc)), + (true, #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Cap, Cap)) => (true, #\hyperref[sailRISCVzextzyptwzysczyjoin]{ext\_ptw\_sc\_join}#(#\hyperref[sailRISCVzextzyptwzylczyjoin]{ext\_ptw\_lc\_join}#(ext_ptw, ptw_lc), ptw_sc)), + + (true, #\hyperref[sailRISCVzRead]{Read}#(Data)) => (true, ext_ptw), + (true, #\hyperref[sailRISCVzWrite]{Write}#(Data)) => (true, ext_ptw), + (true, #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Data, Data)) => (true, ext_ptw), + (true, #\hyperref[sailRISCVzExecute]{Execute}#()) => (true, ext_ptw) + }; + + if succ + then #\hyperref[sailRISCVzPTEzyCheckzySuccess]{PTE\_Check\_Success}#(ext_ptw') + else #\hyperref[sailRISCVzPTEzyCheckzyFailure]{PTE\_Check\_Failure}#(ext_ptw', if ext_ptw'.ptw_sc == PTW_SC_TRAP then EPTWF_CAP_ERR else EPTWF_NO_PERM) +} diff --git a/sail_latex_riscv/fnzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex b/sail_latex_riscv/fnzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex new file mode 100644 index 00000000..690f376b --- /dev/null +++ b/sail_latex_riscv/fnzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex @@ -0,0 +1,4 @@ +function ClearRegSet_of_num arg# = match arg# { + 0 => GPRegs, + _ => FPRegs +} diff --git a/sail_latex_riscv/fnzclint_dispatch8f07ea27f21c1842cfbd7abdf66f1da6.tex b/sail_latex_riscv/fnzclint_dispatch8f07ea27f21c1842cfbd7abdf66f1da6.tex new file mode 100644 index 00000000..f115893a --- /dev/null +++ b/sail_latex_riscv/fnzclint_dispatch8f07ea27f21c1842cfbd7abdf66f1da6.tex @@ -0,0 +1,10 @@ +function #\hyperref[sailRISCVzclintzydispatch]{clint\_dispatch}#() -> unit = { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint::tick mtime <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mtime)); + mip->#\hyperref[sailRISCVzMTI]{MTI}#() = 0b0; + if mtimecmp <=_u mtime then { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#(" clint timer pending at mtime " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mtime)); + mip->#\hyperref[sailRISCVzMTI]{MTI}#() = 0b1 + } +} diff --git a/sail_latex_riscv/fnzclint_load21de915eadac54aac5354dd7bcbb8d32.tex b/sail_latex_riscv/fnzclint_load21de915eadac54aac5354dd7bcbb8d32.tex new file mode 100644 index 00000000..eb70f885 --- /dev/null +++ b/sail_latex_riscv/fnzclint_load21de915eadac54aac5354dd7bcbb8d32.tex @@ -0,0 +1,58 @@ +function #\hyperref[sailRISCVzclintzyload]{clint\_load}#(t, addr, width) = { + let addr = addr - #\hyperref[sailRISCVzplatzyclintzybase]{plat\_clint\_base}# (); + /* FIXME: For now, only allow exact aligned access. */ + if addr == MSIP_BASE & ('n == 8 | 'n == 4) + then { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ "] -> " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mip.#\hyperref[sailRISCVzMSI]{MSI}#())); + #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(mip.#\hyperref[sailRISCVzMSI]{MSI}#(), sizeof(8 * 'n))) + } + else if addr == MTIMECMP_BASE & ('n == 4) + then { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint<4>[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ "] -> " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mtimecmp[31..0])); + /* FIXME: Redundant zero_extend currently required by Lem backend */ + #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(mtimecmp[31..0], 32)) + } + else if addr == MTIMECMP_BASE & ('n == 8) + then { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint<8>[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ "] -> " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mtimecmp)); + /* FIXME: Redundant zero_extend currently required by Lem backend */ + #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(mtimecmp, 64)) + } + else if addr == MTIMECMP_BASE_HI & ('n == 4) + then { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint-hi<4>[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ "] -> " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mtimecmp[63..32])); + /* FIXME: Redundant zero_extend currently required by Lem backend */ + #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(mtimecmp[63..32], 32)) + } + else if addr == MTIME_BASE & ('n == 4) + then { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ "] -> " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mtime)); + #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(mtime[31..0], 32)) + } + else if addr == MTIME_BASE & ('n == 8) + then { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ "] -> " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mtime)); + #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(mtime, 64)) + } + else if addr == MTIME_BASE_HI & ('n == 4) + then { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ "] -> " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mtime)); + #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(mtime[63..32], 32)) + } + else { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ "] -> "); + match t { + #\hyperref[sailRISCVzExecute]{Execute}#() => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzyFetchzyAccesszyFault]{E\_Fetch\_Access\_Fault}#()), + #\hyperref[sailRISCVzRead]{Read}#(Data) => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzyLoadzyAccesszyFault]{E\_Load\_Access\_Fault}#()), + _ => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#()) + } + } +} diff --git a/sail_latex_riscv/fnzclint_store5ac6a4caa2fe222e7b924cd9a27ec52f.tex b/sail_latex_riscv/fnzclint_store5ac6a4caa2fe222e7b924cd9a27ec52f.tex new file mode 100644 index 00000000..6fe51d13 --- /dev/null +++ b/sail_latex_riscv/fnzclint_store5ac6a4caa2fe222e7b924cd9a27ec52f.tex @@ -0,0 +1,32 @@ +function #\hyperref[sailRISCVzclintzystore]{clint\_store}#(addr, width, data) = { + let addr = addr - #\hyperref[sailRISCVzplatzyclintzybase]{plat\_clint\_base}# (); + if addr == MSIP_BASE & ('n == 8 | 'n == 4) then { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ "] <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(data) ^ " (mip.MSI <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(data[0]) ^ ")"); + mip->#\hyperref[sailRISCVzMSI]{MSI}#() = [data[0]]; + #\hyperref[sailRISCVzclintzydispatch]{clint\_dispatch}#(); + #\hyperref[sailRISCVzMemValue]{MemValue}#(true) + } else if addr == MTIMECMP_BASE & 'n == 8 then { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint<8>[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ "] <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(data) ^ " (mtimecmp)"); + mtimecmp = #\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(data, 64); /* FIXME: Redundant zero_extend currently required by Lem backend */ + #\hyperref[sailRISCVzclintzydispatch]{clint\_dispatch}#(); + #\hyperref[sailRISCVzMemValue]{MemValue}#(true) + } else if addr == MTIMECMP_BASE & 'n == 4 then { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint<4>[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ "] <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(data) ^ " (mtimecmp)"); + mtimecmp = #\hyperref[sailRISCVzvectorzyupdatezysubrange]{vector\_update\_subrange}#(mtimecmp, 31, 0, #\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(data, 32)); /* FIXME: Redundant zero_extend currently required by Lem backend */ + #\hyperref[sailRISCVzclintzydispatch]{clint\_dispatch}#(); + #\hyperref[sailRISCVzMemValue]{MemValue}#(true) + } else if addr == MTIMECMP_BASE_HI & 'n == 4 then { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint<4>[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ "] <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(data) ^ " (mtimecmp)"); + mtimecmp = #\hyperref[sailRISCVzvectorzyupdatezysubrange]{vector\_update\_subrange}#(mtimecmp, 63, 32, #\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(data, 32)); /* FIXME: Redundant zero_extend currently required by Lem backend */ + #\hyperref[sailRISCVzclintzydispatch]{clint\_dispatch}#(); + #\hyperref[sailRISCVzMemValue]{MemValue}#(true) + } else { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("clint[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ "] <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(data) ^ " ()"); + #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#()) + } +} diff --git a/sail_latex_riscv/fnzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex b/sail_latex_riscv/fnzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex new file mode 100644 index 00000000..dee45f26 --- /dev/null +++ b/sail_latex_riscv/fnzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzconcatzystrzybits]{concat\_str\_bits}#(str, x) = #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(str, #\hyperref[sailRISCVzbitszystr]{bits\_str}#(x)) diff --git a/sail_latex_riscv/fnzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex b/sail_latex_riscv/fnzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex new file mode 100644 index 00000000..1170c214 --- /dev/null +++ b/sail_latex_riscv/fnzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzconcatzystrzydec]{concat\_str\_dec}#(str, x) = #\hyperref[sailRISCVzconcatzystr]{concat\_str}#(str, #\hyperref[sailRISCVzdeczystr]{dec\_str}#(x)) diff --git a/sail_latex_riscv/fnzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex b/sail_latex_riscv/fnzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex new file mode 100644 index 00000000..6ab563f3 --- /dev/null +++ b/sail_latex_riscv/fnzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex @@ -0,0 +1,10 @@ +function CPtrCmpOp_of_num arg# = match arg# { + 0 => CEQ, + 1 => CNE, + 2 => CLT, + 3 => CLE, + 4 => CLTU, + 5 => CLEU, + 6 => CEXEQ, + _ => CNEXEQ +} diff --git a/sail_latex_riscv/fnzcreg2reg_idxe272195325d960d58ce119619a5a1c75.tex b/sail_latex_riscv/fnzcreg2reg_idxe272195325d960d58ce119619a5a1c75.tex new file mode 100644 index 00000000..b7756efe --- /dev/null +++ b/sail_latex_riscv/fnzcreg2reg_idxe272195325d960d58ce119619a5a1c75.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzcreg2regzyidx]{creg2reg\_idx}#(creg) = 0b01 @ creg diff --git a/sail_latex_riscv/fnzcsr_name355619c0d72f0a56dfaf2d45f4b72967.tex b/sail_latex_riscv/fnzcsr_name355619c0d72f0a56dfaf2d45f4b72967.tex new file mode 100644 index 00000000..f12268f0 --- /dev/null +++ b/sail_latex_riscv/fnzcsr_name355619c0d72f0a56dfaf2d45f4b72967.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzcsrzyname]{csr\_name}#(csr) = #\hyperref[sailRISCVzcsrzynamezymap]{csr\_name\_map}#(csr) diff --git a/sail_latex_riscv/fnzcsraccess68432d7ad570023367f89beb42b653aa.tex b/sail_latex_riscv/fnzcsraccess68432d7ad570023367f89beb42b653aa.tex new file mode 100644 index 00000000..c775a54a --- /dev/null +++ b/sail_latex_riscv/fnzcsraccess68432d7ad570023367f89beb42b653aa.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzcsrAccess]{csrAccess}#(csr : csreg) -> csrRW = csr[11..10] diff --git a/sail_latex_riscv/fnzcsrop_of_numfc0e82db24db14fec87d0613c91892f2.tex b/sail_latex_riscv/fnzcsrop_of_numfc0e82db24db14fec87d0613c91892f2.tex new file mode 100644 index 00000000..5df81b13 --- /dev/null +++ b/sail_latex_riscv/fnzcsrop_of_numfc0e82db24db14fec87d0613c91892f2.tex @@ -0,0 +1,5 @@ +function csrop_of_num arg# = match arg# { + 0 => CSRRW, + 1 => CSRRS, + _ => CSRRC +} diff --git a/sail_latex_riscv/fnzcsrprivc196a9e4f8a034a73a295c0ac67907ed.tex b/sail_latex_riscv/fnzcsrprivc196a9e4f8a034a73a295c0ac67907ed.tex new file mode 100644 index 00000000..56cb99f4 --- /dev/null +++ b/sail_latex_riscv/fnzcsrprivc196a9e4f8a034a73a295c0ac67907ed.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzcsrPriv]{csrPriv}#(csr : csreg) -> priv_level = csr[9..8] diff --git a/sail_latex_riscv/fnzcur_architecture146db9bbeb421361d412d7f5f7f40511.tex b/sail_latex_riscv/fnzcur_architecture146db9bbeb421361d412d7f5f7f40511.tex new file mode 100644 index 00000000..183c12ed --- /dev/null +++ b/sail_latex_riscv/fnzcur_architecture146db9bbeb421361d412d7f5f7f40511.tex @@ -0,0 +1,12 @@ +function #\hyperref[sailRISCVzcurzyArchitecture]{cur\_Architecture}#() -> Architecture = { + let a : arch_xlen = + match (cur_privilege) { + Machine => misa.#\hyperref[sailRISCVzMXL]{MXL}#(), + Supervisor => #\hyperref[sailRISCVzgetzymstatuszySXL]{get\_mstatus\_SXL}#(mstatus), + User => #\hyperref[sailRISCVzgetzymstatuszyUXL]{get\_mstatus\_UXL}#(mstatus) + }; + match #\hyperref[sailRISCVzarchitecture]{architecture}#(a) { + #\hyperref[sailRISCVzSome]{Some}#(a) => a, + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("Invalid current architecture") + } +} diff --git a/sail_latex_riscv/fnzcurasid32f5f0e43e5813461351dff485d90e4aa4.tex b/sail_latex_riscv/fnzcurasid32f5f0e43e5813461351dff485d90e4aa4.tex new file mode 100644 index 00000000..3e0856f9 --- /dev/null +++ b/sail_latex_riscv/fnzcurasid32f5f0e43e5813461351dff485d90e4aa4.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzcurAsid32]{curAsid32}#(satp : #\hyperref[sailRISCVzbits]{bits}#(32)) -> asid32 = { + let s = #\hyperref[sailRISCVzMkzySatp32]{Mk\_Satp32}#(satp); + s.#\hyperref[sailRISCVzAsid]{Asid}#() +} diff --git a/sail_latex_riscv/fnzcurasid64b2c4a622c945e46b0aea25ce9a07740f.tex b/sail_latex_riscv/fnzcurasid64b2c4a622c945e46b0aea25ce9a07740f.tex new file mode 100644 index 00000000..309f7786 --- /dev/null +++ b/sail_latex_riscv/fnzcurasid64b2c4a622c945e46b0aea25ce9a07740f.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzcurAsid64]{curAsid64}#(satp : #\hyperref[sailRISCVzbits]{bits}#(64)) -> asid64 = { + let s = #\hyperref[sailRISCVzMkzySatp64]{Mk\_Satp64}#(satp); + s.#\hyperref[sailRISCVzAsid]{Asid}#() +} diff --git a/sail_latex_riscv/fnzcurptb320f32995fafcf5ebca7eeda72aee3f74f.tex b/sail_latex_riscv/fnzcurptb320f32995fafcf5ebca7eeda72aee3f74f.tex new file mode 100644 index 00000000..ad730b31 --- /dev/null +++ b/sail_latex_riscv/fnzcurptb320f32995fafcf5ebca7eeda72aee3f74f.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzcurPTB32]{curPTB32}#(satp : #\hyperref[sailRISCVzbits]{bits}#(32)) -> paddr32 = { + let s : Satp32 = #\hyperref[sailRISCVzMkzySatp32]{Mk\_Satp32}#(satp); + #\hyperref[sailRISCVzshiftl]{shiftl}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(s.#\hyperref[sailRISCVzPPN]{PPN}#()), PAGESIZE_BITS) +} diff --git a/sail_latex_riscv/fnzcurptb6479eaa1d344e911b626ff56a8856bcd50.tex b/sail_latex_riscv/fnzcurptb6479eaa1d344e911b626ff56a8856bcd50.tex new file mode 100644 index 00000000..e440387c --- /dev/null +++ b/sail_latex_riscv/fnzcurptb6479eaa1d344e911b626ff56a8856bcd50.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzcurPTB64]{curPTB64}#(satp : #\hyperref[sailRISCVzbits]{bits}#(64)) -> paddr64 = { + let s = #\hyperref[sailRISCVzMkzySatp64]{Mk\_Satp64}#(satp); + #\hyperref[sailRISCVzshiftl]{shiftl}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(s.#\hyperref[sailRISCVzPPN]{PPN}#()), PAGESIZE_BITS) +} diff --git a/sail_latex_riscv/fnzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_riscv/fnzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..86705730 --- /dev/null +++ b/sail_latex_riscv/fnzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +function decode bv = #\hyperref[sailRISCVzencdec]{encdec}#(bv) diff --git a/sail_latex_riscv/fnzdecodecompresseda0c5feab498dd29a69efe0353146e981.tex b/sail_latex_riscv/fnzdecodecompresseda0c5feab498dd29a69efe0353146e981.tex new file mode 100644 index 00000000..0799c663 --- /dev/null +++ b/sail_latex_riscv/fnzdecodecompresseda0c5feab498dd29a69efe0353146e981.tex @@ -0,0 +1 @@ +function decodeCompressed bv = #\hyperref[sailRISCVzencdeczycompressed]{encdec\_compressed}#(bv) diff --git a/sail_latex_riscv/fnzdef_spc_backwardseab568d1f8e592642bb1655eb934a620.tex b/sail_latex_riscv/fnzdef_spc_backwardseab568d1f8e592642bb1655eb934a620.tex new file mode 100644 index 00000000..b48b8458 --- /dev/null +++ b/sail_latex_riscv/fnzdef_spc_backwardseab568d1f8e592642bb1655eb934a620.tex @@ -0,0 +1 @@ +function def_spc_backwards s = () diff --git a/sail_latex_riscv/fnzdef_spc_forwards4eafa854d5b706686aca12e499e738fa.tex b/sail_latex_riscv/fnzdef_spc_forwards4eafa854d5b706686aca12e499e738fa.tex new file mode 100644 index 00000000..b8e5fed8 --- /dev/null +++ b/sail_latex_riscv/fnzdef_spc_forwards4eafa854d5b706686aca12e499e738fa.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzdefzyspczyforwards]{def\_spc\_forwards}# () = " " diff --git a/sail_latex_riscv/fnzdef_spc_matches_prefix0e41afd1e8fe11919b3e9439288e00c3.tex b/sail_latex_riscv/fnzdef_spc_matches_prefix0e41afd1e8fe11919b3e9439288e00c3.tex new file mode 100644 index 00000000..94a6b180 --- /dev/null +++ b/sail_latex_riscv/fnzdef_spc_matches_prefix0e41afd1e8fe11919b3e9439288e00c3.tex @@ -0,0 +1 @@ +function def_spc_matches_prefix s = #\hyperref[sailRISCVzoptzyspczymatcheszyprefix]{opt\_spc\_matches\_prefix}#(s) diff --git a/sail_latex_riscv/fnzdirty_fd_context8f0fcc8b7745d7294388295307af4058.tex b/sail_latex_riscv/fnzdirty_fd_context8f0fcc8b7745d7294388295307af4058.tex new file mode 100644 index 00000000..7aec704c --- /dev/null +++ b/sail_latex_riscv/fnzdirty_fd_context8f0fcc8b7745d7294388295307af4058.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzdirtyzyfdzycontext]{dirty\_fd\_context}#() -> unit = { + mstatus->#\hyperref[sailRISCVzFS]{FS}#() = #\hyperref[sailRISCVzextStatuszytozybits]{extStatus\_to\_bits}#(Dirty); + mstatus->#\hyperref[sailRISCVzSD]{SD}#() = 0b1 +} diff --git a/sail_latex_riscv/fnzdispatchinterruptaf83562ba97e1882252696fd8999b3e7.tex b/sail_latex_riscv/fnzdispatchinterruptaf83562ba97e1882252696fd8999b3e7.tex new file mode 100644 index 00000000..73eb2b2a --- /dev/null +++ b/sail_latex_riscv/fnzdispatchinterruptaf83562ba97e1882252696fd8999b3e7.tex @@ -0,0 +1,21 @@ +function #\hyperref[sailRISCVzdispatchInterrupt]{dispatchInterrupt}#(priv : Privilege) -> #\hyperref[sailRISCVzoption]{option}#((InterruptType, Privilege)) = { + /* If we don't have different privilege levels, we don't need to check delegation. + * Absence of U-mode implies absence of S-mode. + */ + if (~ (#\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#())) | ((~ (#\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#())) & (~ (#\hyperref[sailRISCVzhaveNExt]{haveNExt}#()))) then { + assert(priv == Machine, "invalid current privilege"); + let enabled_pending = mip.#\hyperref[sailRISCVzbits]{bits}#() & mie.#\hyperref[sailRISCVzbits]{bits}#(); + match #\hyperref[sailRISCVzfindPendingInterrupt]{findPendingInterrupt}#(enabled_pending) { + #\hyperref[sailRISCVzSome]{Some}#(i) => let r = (i, Machine) in #\hyperref[sailRISCVzSome]{Some}#(r), + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzNone]{None}#() + } + } else { + match #\hyperref[sailRISCVzgetPendingSet]{getPendingSet}#(priv) { + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzNone]{None}#(), + #\hyperref[sailRISCVzSome]{Some}#(ip, p) => match #\hyperref[sailRISCVzfindPendingInterrupt]{findPendingInterrupt}#(ip) { + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzNone]{None}#(), + #\hyperref[sailRISCVzSome]{Some}#(i) => let r = (i, p) in #\hyperref[sailRISCVzSome]{Some}#(r) + } + } + } +} diff --git a/sail_latex_riscv/fnzdzzflagcea95ae2581be09607c095ea1558f21b.tex b/sail_latex_riscv/fnzdzzflagcea95ae2581be09607c095ea1558f21b.tex new file mode 100644 index 00000000..6e1be37a --- /dev/null +++ b/sail_latex_riscv/fnzdzzflagcea95ae2581be09607c095ea1558f21b.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzdzzFlag]{dzFlag}#() -> #\hyperref[sailRISCVzbits]{bits}#(5) = 0b_01000 diff --git a/sail_latex_riscv/fnzeffectiveprivilegeb14beb91b9202c1aefb99c45054bcb23.tex b/sail_latex_riscv/fnzeffectiveprivilegeb14beb91b9202c1aefb99c45054bcb23.tex new file mode 100644 index 00000000..5ac04001 --- /dev/null +++ b/sail_latex_riscv/fnzeffectiveprivilegeb14beb91b9202c1aefb99c45054bcb23.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzeffectivePrivilege]{effectivePrivilege}#(t : #\hyperref[sailRISCVzAccessType]{AccessType}#(ext_access_type), m : Mstatus, priv : Privilege) -> Privilege = + if t != #\hyperref[sailRISCVzExecute]{Execute}#() & m.#\hyperref[sailRISCVzMPRV]{MPRV}#() == 0b1 + then #\hyperref[sailRISCVzprivLevelzyofzybits]{privLevel\_of\_bits}#(mstatus.#\hyperref[sailRISCVzMPP]{MPP}#()) + else cur_privilege diff --git a/sail_latex_riscv/fnzeq_unit996f84433ac0995f4aadfca5b68cd358.tex b/sail_latex_riscv/fnzeq_unit996f84433ac0995f4aadfca5b68cd358.tex new file mode 100644 index 00000000..dd4cfe97 --- /dev/null +++ b/sail_latex_riscv/fnzeq_unit996f84433ac0995f4aadfca5b68cd358.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzeqzyunit]{eq\_unit}#(_, _) = true diff --git a/sail_latex_riscv/fnzexception_delegateefb7e9252abe9f7e50e2f06577208c695.tex b/sail_latex_riscv/fnzexception_delegateefb7e9252abe9f7e50e2f06577208c695.tex new file mode 100644 index 00000000..2e1b38b6 --- /dev/null +++ b/sail_latex_riscv/fnzexception_delegateefb7e9252abe9f7e50e2f06577208c695.tex @@ -0,0 +1,14 @@ +function #\hyperref[sailRISCVzexceptionzydelegatee]{exception\_delegatee}#(e : ExceptionType, p : Privilege) -> Privilege = { + let idx = #\hyperref[sailRISCVznumzyofzyExceptionType]{num\_of\_ExceptionType}#(e); + let super = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(medeleg.#\hyperref[sailRISCVzbits]{bits}#()[idx]); + /* if S-mode is absent, medeleg delegates to U-mode if 'N' is supported. */ + let user = if #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() + then super & #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() & #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(sedeleg.#\hyperref[sailRISCVzbits]{bits}#()[idx]) + else super & #\hyperref[sailRISCVzhaveNExt]{haveNExt}#(); + let deleg = if #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() & user then User + else if #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & super then Supervisor + else Machine; + /* We cannot transition to a less-privileged mode. */ + if #\hyperref[sailRISCVzprivLevelzytozybits]{privLevel\_to\_bits}#(deleg) <_u #\hyperref[sailRISCVzprivLevelzytozybits]{privLevel\_to\_bits}#(p) + then p else deleg +} diff --git a/sail_latex_riscv/fnzexception_handlerf03729146a8718cee62ce35044e16202.tex b/sail_latex_riscv/fnzexception_handlerf03729146a8718cee62ce35044e16202.tex new file mode 100644 index 00000000..a1fb2018 --- /dev/null +++ b/sail_latex_riscv/fnzexception_handlerf03729146a8718cee62ce35044e16202.tex @@ -0,0 +1,61 @@ +function #\hyperref[sailRISCVzexceptionzyhandler]{exception\_handler}#(cur_priv : Privilege, ctl : ctl_result, + pc: xlenbits) -> xlenbits = { + match (cur_priv, ctl) { + (_, #\hyperref[sailRISCVzCTLzyTRAP]{CTL\_TRAP}#(e)) => { + let del_priv = #\hyperref[sailRISCVzexceptionzydelegatee]{exception\_delegatee}#(e.trap, cur_priv); + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("trapping from " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(cur_priv) ^ " to " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(del_priv) + ^ " to handle " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(e.trap)); + #\hyperref[sailRISCVztrapzyhandler]{trap\_handler}#(del_priv, false, #\hyperref[sailRISCVzexceptionTypezytozybits]{exceptionType\_to\_bits}#(e.trap), pc, e.excinfo, e.ext) + }, + (_, #\hyperref[sailRISCVzCTLzyMRET]{CTL\_MRET}#()) => { + let prev_priv = cur_privilege; + mstatus->#\hyperref[sailRISCVzMIE]{MIE}#() = mstatus.#\hyperref[sailRISCVzMPIE]{MPIE}#(); + mstatus->#\hyperref[sailRISCVzMPIE]{MPIE}#() = 0b1; + cur_privilege = #\hyperref[sailRISCVzprivLevelzyofzybits]{privLevel\_of\_bits}#(mstatus.#\hyperref[sailRISCVzMPP]{MPP}#()); + mstatus->#\hyperref[sailRISCVzMPP]{MPP}#() = #\hyperref[sailRISCVzprivLevelzytozybits]{privLevel\_to\_bits}#(if #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() then User else Machine); + if cur_privilege != Machine + then mstatus->#\hyperref[sailRISCVzMPRV]{MPRV}#() = 0b0; + + if #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}#() + then #\hyperref[sailRISCVzprintzyreg]{print\_reg}#("CSR mstatus <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mstatus.#\hyperref[sailRISCVzbits]{bits}#())); + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("ret-ing from " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(prev_priv) ^ " to " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(cur_privilege)); + + #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); + #\hyperref[sailRISCVzpreparezyxretzytarget]{prepare\_xret\_target}#(Machine) & #\hyperref[sailRISCVzpczyalignmentzymask]{pc\_alignment\_mask}#() + }, + (_, #\hyperref[sailRISCVzCTLzySRET]{CTL\_SRET}#()) => { + let prev_priv = cur_privilege; + mstatus->#\hyperref[sailRISCVzSIE]{SIE}#() = mstatus.#\hyperref[sailRISCVzSPIE]{SPIE}#(); + mstatus->#\hyperref[sailRISCVzSPIE]{SPIE}#() = 0b1; + cur_privilege = if mstatus.#\hyperref[sailRISCVzSPP]{SPP}#() == 0b1 then Supervisor else User; + mstatus->#\hyperref[sailRISCVzSPP]{SPP}#() = 0b0; + if cur_privilege != Machine + then mstatus->#\hyperref[sailRISCVzMPRV]{MPRV}#() = 0b0; + + if #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}#() + then #\hyperref[sailRISCVzprintzyreg]{print\_reg}#("CSR mstatus <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mstatus.#\hyperref[sailRISCVzbits]{bits}#())); + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("ret-ing from " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(prev_priv) + ^ " to " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(cur_privilege)); + + #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); + #\hyperref[sailRISCVzpreparezyxretzytarget]{prepare\_xret\_target}#(Supervisor) & #\hyperref[sailRISCVzpczyalignmentzymask]{pc\_alignment\_mask}#() + }, + (_, #\hyperref[sailRISCVzCTLzyURET]{CTL\_URET}#()) => { + let prev_priv = cur_privilege; + mstatus->#\hyperref[sailRISCVzUIE]{UIE}#() = mstatus.#\hyperref[sailRISCVzUPIE]{UPIE}#(); + mstatus->#\hyperref[sailRISCVzUPIE]{UPIE}#() = 0b1; + cur_privilege = User; + + if #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}#() + then #\hyperref[sailRISCVzprintzyreg]{print\_reg}#("CSR mstatus <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mstatus.#\hyperref[sailRISCVzbits]{bits}#())); + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("ret-ing from " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(prev_priv) ^ " to " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(cur_privilege)); + + #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); + #\hyperref[sailRISCVzpreparezyxretzytarget]{prepare\_xret\_target}#(User) & #\hyperref[sailRISCVzpczyalignmentzymask]{pc\_alignment\_mask}#() + } + } +} diff --git a/sail_latex_riscv/fnzexceptiontype_to_bits6edc76877c2677590096c351d9b431f1.tex b/sail_latex_riscv/fnzexceptiontype_to_bits6edc76877c2677590096c351d9b431f1.tex new file mode 100644 index 00000000..b19b2acf --- /dev/null +++ b/sail_latex_riscv/fnzexceptiontype_to_bits6edc76877c2677590096c351d9b431f1.tex @@ -0,0 +1,22 @@ +function #\hyperref[sailRISCVzexceptionTypezytozybits]{exceptionType\_to\_bits}#(e) = + match (e) { + #\hyperref[sailRISCVzEzyFetchzyAddrzyAlign]{E\_Fetch\_Addr\_Align}#() => 0x00, + #\hyperref[sailRISCVzEzyFetchzyAccesszyFault]{E\_Fetch\_Access\_Fault}#() => 0x01, + #\hyperref[sailRISCVzEzyIllegalzyInstr]{E\_Illegal\_Instr}#() => 0x02, + #\hyperref[sailRISCVzEzyBreakpoint]{E\_Breakpoint}#() => 0x03, + #\hyperref[sailRISCVzEzyLoadzyAddrzyAlign]{E\_Load\_Addr\_Align}#() => 0x04, + #\hyperref[sailRISCVzEzyLoadzyAccesszyFault]{E\_Load\_Access\_Fault}#() => 0x05, + #\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#() => 0x06, + #\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#() => 0x07, + #\hyperref[sailRISCVzEzyUzyEnvCall]{E\_U\_EnvCall}#() => 0x08, + #\hyperref[sailRISCVzEzySzyEnvCall]{E\_S\_EnvCall}#() => 0x09, + #\hyperref[sailRISCVzEzyReservedzy10]{E\_Reserved\_10}#() => 0x0a, + #\hyperref[sailRISCVzEzyMzyEnvCall]{E\_M\_EnvCall}#() => 0x0b, + #\hyperref[sailRISCVzEzyFetchzyPagezyFault]{E\_Fetch\_Page\_Fault}#() => 0x0c, + #\hyperref[sailRISCVzEzyLoadzyPagezyFault]{E\_Load\_Page\_Fault}#() => 0x0d, + #\hyperref[sailRISCVzEzyReservedzy14]{E\_Reserved\_14}#() => 0x0e, + #\hyperref[sailRISCVzEzySAMOzyPagezyFault]{E\_SAMO\_Page\_Fault}#() => 0x0f, + + /* extensions */ + #\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(e) => #\hyperref[sailRISCVzextzyexczytypezytozybits]{ext\_exc\_type\_to\_bits}#(e) + } diff --git a/sail_latex_riscv/fnzexceptiontype_to_str566b70f16fdf6ed4d1850ec75465ec4b.tex b/sail_latex_riscv/fnzexceptiontype_to_str566b70f16fdf6ed4d1850ec75465ec4b.tex new file mode 100644 index 00000000..c070b4ee --- /dev/null +++ b/sail_latex_riscv/fnzexceptiontype_to_str566b70f16fdf6ed4d1850ec75465ec4b.tex @@ -0,0 +1,22 @@ +function #\hyperref[sailRISCVzexceptionTypezytozystr]{exceptionType\_to\_str}#(e) = + match (e) { + #\hyperref[sailRISCVzEzyFetchzyAddrzyAlign]{E\_Fetch\_Addr\_Align}#() => "misaligned-fetch", + #\hyperref[sailRISCVzEzyFetchzyAccesszyFault]{E\_Fetch\_Access\_Fault}#() => "fetch-access-fault", + #\hyperref[sailRISCVzEzyIllegalzyInstr]{E\_Illegal\_Instr}#() => "illegal-instruction", + #\hyperref[sailRISCVzEzyBreakpoint]{E\_Breakpoint}#() => "breakpoint", + #\hyperref[sailRISCVzEzyLoadzyAddrzyAlign]{E\_Load\_Addr\_Align}#() => "misaligned-load", + #\hyperref[sailRISCVzEzyLoadzyAccesszyFault]{E\_Load\_Access\_Fault}#() => "load-access-fault", + #\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#() => "misaliged-store/amo", + #\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#() => "store/amo-access-fault", + #\hyperref[sailRISCVzEzyUzyEnvCall]{E\_U\_EnvCall}#() => "u-call", + #\hyperref[sailRISCVzEzySzyEnvCall]{E\_S\_EnvCall}#() => "s-call", + #\hyperref[sailRISCVzEzyReservedzy10]{E\_Reserved\_10}#() => "reserved-0", + #\hyperref[sailRISCVzEzyMzyEnvCall]{E\_M\_EnvCall}#() => "m-call", + #\hyperref[sailRISCVzEzyFetchzyPagezyFault]{E\_Fetch\_Page\_Fault}#() => "fetch-page-fault", + #\hyperref[sailRISCVzEzyLoadzyPagezyFault]{E\_Load\_Page\_Fault}#() => "load-page-fault", + #\hyperref[sailRISCVzEzyReservedzy14]{E\_Reserved\_14}#() => "reserved-1", + #\hyperref[sailRISCVzEzySAMOzyPagezyFault]{E\_SAMO\_Page\_Fault}#() => "store/amo-page-fault", + + /* extensions */ + #\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(e) => #\hyperref[sailRISCVzextzyexczytypezytozystr]{ext\_exc\_type\_to\_str}#(e) + } diff --git a/sail_latex_riscv/fnzext_access_type_of_num6a15c4e70d2e9820f649a1cc6760e30a.tex b/sail_latex_riscv/fnzext_access_type_of_num6a15c4e70d2e9820f649a1cc6760e30a.tex new file mode 100644 index 00000000..e2af0d55 --- /dev/null +++ b/sail_latex_riscv/fnzext_access_type_of_num6a15c4e70d2e9820f649a1cc6760e30a.tex @@ -0,0 +1,4 @@ +function ext_access_type_of_num arg# = match arg# { + 0 => Data, + _ => Cap +} diff --git a/sail_latex_riscv/fnzext_check_csr_fail991cc4645a62a48eb645391d3988288a.tex b/sail_latex_riscv/fnzext_check_csr_fail991cc4645a62a48eb645391d3988288a.tex new file mode 100644 index 00000000..04c2c77b --- /dev/null +++ b/sail_latex_riscv/fnzext_check_csr_fail991cc4645a62a48eb645391d3988288a.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzextzycheckzyCSRzyfail]{ext\_check\_CSR\_fail}# () -> unit = + #\hyperref[sailRISCVzhandlezycherizypcczyexception]{handle\_cheri\_pcc\_exception}#(CapEx_AccessSystemRegsViolation) diff --git a/sail_latex_riscv/fnzext_check_csreef82c82c124fe04d74fc6fd8219bb68.tex b/sail_latex_riscv/fnzext_check_csreef82c82c124fe04d74fc6fd8219bb68.tex new file mode 100644 index 00000000..fa970fec --- /dev/null +++ b/sail_latex_riscv/fnzext_check_csreef82c82c124fe04d74fc6fd8219bb68.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzextzycheckzyCSR]{ext\_check\_CSR}# (csrno : #\hyperref[sailRISCVzbits]{bits}#(12), p : Privilege, isWrite : bool) -> bool = + #\hyperref[sailRISCVzpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}#() /* XXX need to make this more granular e.g. a whitelist of allowed CSR diff --git a/sail_latex_riscv/fnzext_check_xret_priv92677d070503a361c4ac308adba53957.tex b/sail_latex_riscv/fnzext_check_xret_priv92677d070503a361c4ac308adba53957.tex new file mode 100644 index 00000000..a311464b --- /dev/null +++ b/sail_latex_riscv/fnzext_check_xret_priv92677d070503a361c4ac308adba53957.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzextzycheckzyxretzypriv]{ext\_check\_xret\_priv}# (p : Privilege) : Privilege -> bool = + #\hyperref[sailRISCVzpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}#() diff --git a/sail_latex_riscv/fnzext_control_check_addr2d404fc3390578d569e3f547f0d18fce.tex b/sail_latex_riscv/fnzext_control_check_addr2d404fc3390578d569e3f547f0d18fce.tex new file mode 100644 index 00000000..7a0f0c65 --- /dev/null +++ b/sail_latex_riscv/fnzext_control_check_addr2d404fc3390578d569e3f547f0d18fce.tex @@ -0,0 +1,11 @@ +function #\hyperref[sailRISCVzextzycontrolzycheckzyaddr]{ext\_control\_check\_addr}#(pc : xlenbits) -> #\hyperref[sailRISCVzExtzyControlAddrzyCheck]{Ext\_ControlAddr\_Check}#(ext_control_addr_error) = { + let pcc_base = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC); + /* We are given the addr without any bit[0] clearing, so the addition + * below may include a set addr[0], and so the bounds checks should + * be accurate. + */ + let target : xlenbits = [pcc_base + pc with 0=bitzero]; + if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(PCC, target, #\hyperref[sailRISCVzminzyinstructionzybytes]{min\_instruction\_bytes}# ())) + then #\hyperref[sailRISCVzExtzyControlAddrzyError]{Ext\_ControlAddr\_Error}#(CapEx_LengthViolation, PCC_IDX) + else #\hyperref[sailRISCVzExtzyControlAddrzyOK]{Ext\_ControlAddr\_OK}#(target) +} diff --git a/sail_latex_riscv/fnzext_control_check_pc92c2579f955b827738ac1e5c79b85839.tex b/sail_latex_riscv/fnzext_control_check_pc92c2579f955b827738ac1e5c79b85839.tex new file mode 100644 index 00000000..886c4b0f --- /dev/null +++ b/sail_latex_riscv/fnzext_control_check_pc92c2579f955b827738ac1e5c79b85839.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzextzycontrolzycheckzypc]{ext\_control\_check\_pc}#(pc : xlenbits) -> #\hyperref[sailRISCVzExtzyControlAddrzyCheck]{Ext\_ControlAddr\_Check}#(ext_control_addr_error) = { + if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(PCC, pc, #\hyperref[sailRISCVzminzyinstructionzybytes]{min\_instruction\_bytes}# ())) + then #\hyperref[sailRISCVzExtzyControlAddrzyError]{Ext\_ControlAddr\_Error}#(CapEx_LengthViolation, PCC_IDX) + else #\hyperref[sailRISCVzExtzyControlAddrzyOK]{Ext\_ControlAddr\_OK}#(pc) +} diff --git a/sail_latex_riscv/fnzext_data_get_addra719d6978c6003ef3b6e2e57ccbf64b8.tex b/sail_latex_riscv/fnzext_data_get_addra719d6978c6003ef3b6e2e57ccbf64b8.tex new file mode 100644 index 00000000..9b99afdd --- /dev/null +++ b/sail_latex_riscv/fnzext_data_get_addra719d6978c6003ef3b6e2e57ccbf64b8.tex @@ -0,0 +1,28 @@ +function #\hyperref[sailRISCVzextzydatazygetzyaddr]{ext\_data\_get\_addr}#(base_reg : regidx, offset : xlenbits, acc : #\hyperref[sailRISCVzAccessType]{AccessType}#(ext_access_type), width : word_width) + -> #\hyperref[sailRISCVzExtzyDataAddrzyCheck]{Ext\_DataAddr\_Check}#(ext_data_addr_error) = { + + let (auth_val, newAddr, auth_idx) = #\hyperref[sailRISCVzgetzycherizymodezycapzyaddr]{get\_cheri\_mode\_cap\_addr}#(base_reg, offset); + + let (have_rqd_load_perm, have_rqd_store_perm) : (bool, bool) = match acc { + #\hyperref[sailRISCVzRead]{Read}#(Data) => (auth_val.permit_load, true ), + #\hyperref[sailRISCVzWrite]{Write}#(Data) => (true , auth_val.permit_store), + #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Data, Data) => (auth_val.permit_load, auth_val.permit_store), + #\hyperref[sailRISCVzExecute]{Execute}#() => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("ext_data_get_addr for Execute"), + #\hyperref[sailRISCVzRead]{Read}#(_) => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("ext_data_get_addr for #\hyperref[sailRISCVzRead]{Read}#(_)"), + #\hyperref[sailRISCVzWrite]{Write}#(_) => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("ext_data_get_addr for #\hyperref[sailRISCVzWrite]{Write}#(_)"), + #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(_, _) => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("ext_data_get_addr for #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(_, _)") + }; + + if #\hyperref[sailRISCVznot]{not}#(auth_val.tag) then + #\hyperref[sailRISCVzExtzyDataAddrzyError]{Ext\_DataAddr\_Error}#(CapEx_TagViolation, auth_idx) + else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(auth_val) then + #\hyperref[sailRISCVzExtzyDataAddrzyError]{Ext\_DataAddr\_Error}#(CapEx_SealViolation, auth_idx) + else if #\hyperref[sailRISCVznot]{not}#(have_rqd_load_perm) then + #\hyperref[sailRISCVzExtzyDataAddrzyError]{Ext\_DataAddr\_Error}#(CapEx_PermitLoadViolation, auth_idx) + else if #\hyperref[sailRISCVznot]{not}#(have_rqd_store_perm) then + #\hyperref[sailRISCVzExtzyDataAddrzyError]{Ext\_DataAddr\_Error}#(CapEx_PermitStoreViolation, auth_idx) + else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(auth_val, newAddr, #\hyperref[sailRISCVzwordzywidthzybytes]{word\_width\_bytes}#(width))) then + #\hyperref[sailRISCVzExtzyDataAddrzyError]{Ext\_DataAddr\_Error}#(CapEx_LengthViolation, auth_idx) + else + #\hyperref[sailRISCVzExtzyDataAddrzyOK]{Ext\_DataAddr\_OK}#(newAddr) +} diff --git a/sail_latex_riscv/fnzext_exc_type_of_numa5807bd3284ecfd6e2edf0e304dee26e.tex b/sail_latex_riscv/fnzext_exc_type_of_numa5807bd3284ecfd6e2edf0e304dee26e.tex new file mode 100644 index 00000000..673bcb4c --- /dev/null +++ b/sail_latex_riscv/fnzext_exc_type_of_numa5807bd3284ecfd6e2edf0e304dee26e.tex @@ -0,0 +1,5 @@ +function ext_exc_type_of_num arg# = match arg# { + 0 => EXC_LOAD_CAP_PAGE_FAULT, + 1 => EXC_SAMO_CAP_PAGE_FAULT, + _ => EXC_CHERI +} diff --git a/sail_latex_riscv/fnzext_exc_type_to_bitse12334413f8dedca96749d4413e3150b.tex b/sail_latex_riscv/fnzext_exc_type_to_bitse12334413f8dedca96749d4413e3150b.tex new file mode 100644 index 00000000..dd755452 --- /dev/null +++ b/sail_latex_riscv/fnzext_exc_type_to_bitse12334413f8dedca96749d4413e3150b.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzextzyexczytypezytozybits]{ext\_exc\_type\_to\_bits}#(e) = + match (e) { + EXC_LOAD_CAP_PAGE_FAULT => 0x1a, + EXC_SAMO_CAP_PAGE_FAULT => 0x1b, + EXC_CHERI => 0x1c + } diff --git a/sail_latex_riscv/fnzext_exc_type_to_strc4b005a75959aeec9fce26f39219c666.tex b/sail_latex_riscv/fnzext_exc_type_to_strc4b005a75959aeec9fce26f39219c666.tex new file mode 100644 index 00000000..29cf3006 --- /dev/null +++ b/sail_latex_riscv/fnzext_exc_type_to_strc4b005a75959aeec9fce26f39219c666.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzextzyexczytypezytozystr]{ext\_exc\_type\_to\_str}#(e) = + match (e) { + EXC_LOAD_CAP_PAGE_FAULT => "load-cap-page-fault", + EXC_SAMO_CAP_PAGE_FAULT => "store/amo-cap-page-fault", + EXC_CHERI => "cheri" + } diff --git a/sail_latex_riscv/fnzext_fail_xret_priva071b88d32f48ad8e720a4cae916da8b.tex b/sail_latex_riscv/fnzext_fail_xret_priva071b88d32f48ad8e720a4cae916da8b.tex new file mode 100644 index 00000000..1f69eb45 --- /dev/null +++ b/sail_latex_riscv/fnzext_fail_xret_priva071b88d32f48ad8e720a4cae916da8b.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzextzyfailzyxretzypriv]{ext\_fail\_xret\_priv}# () : unit -> unit = + #\hyperref[sailRISCVzhandlezycherizypcczyexception]{handle\_cheri\_pcc\_exception}#(CapEx_AccessSystemRegsViolation) diff --git a/sail_latex_riscv/fnzext_fetch_check_pc2e82f09c4f4da5465b70e5f9e6f48b77.tex b/sail_latex_riscv/fnzext_fetch_check_pc2e82f09c4f4da5465b70e5f9e6f48b77.tex new file mode 100644 index 00000000..66f9eb15 --- /dev/null +++ b/sail_latex_riscv/fnzext_fetch_check_pc2e82f09c4f4da5465b70e5f9e6f48b77.tex @@ -0,0 +1,25 @@ +function #\hyperref[sailRISCVzextzyfetchzycheckzypc]{ext\_fetch\_check\_pc}#(start_pc, pc) = { + if start_pc == pc + then { + pcc_base = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC); + /* We need to perform the permission checks only for the first granule. */ + if #\hyperref[sailRISCVznot]{not}#(PCC.tag) + then #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(CapEx_TagViolation) + else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(PCC) + then #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(CapEx_SealViolation) + else if #\hyperref[sailRISCVznot]{not}#(PCC.permit_execute) + then #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(CapEx_PermitExecuteViolation) + else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(PCC, pc, 2)) + then #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(CapEx_LengthViolation) + /* Require that PCC.base be as aligned as PC. This + is also enforced when setting PCC in most places. */ + else if pcc_base[0] != bitzero | (pcc_base[1] != bitzero & ~(#\hyperref[sailRISCVzhaveRVC]{haveRVC}#())) + then #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(CapEx_UnalignedBase) + else #\hyperref[sailRISCVzExtzyFetchAddrzyOK]{Ext\_FetchAddr\_OK}#(pc) + } else { + /* Perform only the bounds checks on the current granule, i.e. pc. */ + if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(PCC, pc, 2)) + then #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(CapEx_LengthViolation) + else #\hyperref[sailRISCVzExtzyFetchAddrzyOK]{Ext\_FetchAddr\_OK}#(pc) + } +} diff --git a/sail_latex_riscv/fnzext_fetch_hookb78ddd15c7be769c4a0783ef122b9767.tex b/sail_latex_riscv/fnzext_fetch_hookb78ddd15c7be769c4a0783ef122b9767.tex new file mode 100644 index 00000000..86faa610 --- /dev/null +++ b/sail_latex_riscv/fnzext_fetch_hookb78ddd15c7be769c4a0783ef122b9767.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzextzyfetchzyhook]{ext\_fetch\_hook}#(f : FetchResult) -> FetchResult = f diff --git a/sail_latex_riscv/fnzext_get_ptw_errorb38503fe4519ddae4ed13f9933d3c0a5.tex b/sail_latex_riscv/fnzext_get_ptw_errorb38503fe4519ddae4ed13f9933d3c0a5.tex new file mode 100644 index 00000000..c5cc8a48 --- /dev/null +++ b/sail_latex_riscv/fnzext_get_ptw_errorb38503fe4519ddae4ed13f9933d3c0a5.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzextzygetzyptwzyerror]{ext\_get\_ptw\_error}#(eptwf : ext_ptw_fail) -> PTW_Error = + match (eptwf) { + EPTWF_NO_PERM => #\hyperref[sailRISCVzPTWzyNozyPermission]{PTW\_No\_Permission}#(), + EPTWF_CAP_ERR => #\hyperref[sailRISCVzPTWzyExtzyError]{PTW\_Ext\_Error}#(AT_CAP_ERR) + } diff --git a/sail_latex_riscv/fnzext_handle_control_check_error7b80ca54e4133f98238aa5f1371bfc1f.tex b/sail_latex_riscv/fnzext_handle_control_check_error7b80ca54e4133f98238aa5f1371bfc1f.tex new file mode 100644 index 00000000..bc6d722f --- /dev/null +++ b/sail_latex_riscv/fnzext_handle_control_check_error7b80ca54e4133f98238aa5f1371bfc1f.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzextzyhandlezycontrolzycheckzyerror]{ext\_handle\_control\_check\_error}#(err : ext_control_addr_error) -> unit = { + let (capEx, regnum) = err; + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(capEx, regnum) +} diff --git a/sail_latex_riscv/fnzext_handle_data_check_errorad2507fc7050fbd24451608767d75b73.tex b/sail_latex_riscv/fnzext_handle_data_check_errorad2507fc7050fbd24451608767d75b73.tex new file mode 100644 index 00000000..516ce286 --- /dev/null +++ b/sail_latex_riscv/fnzext_handle_data_check_errorad2507fc7050fbd24451608767d75b73.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzextzyhandlezydatazycheckzyerror]{ext\_handle\_data\_check\_error}#(err : ext_data_addr_error) -> unit = { + let (capEx, regnum) = err; + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(capEx, regnum) +} diff --git a/sail_latex_riscv/fnzext_handle_fetch_check_error1c773c1438a4c5dcc256df216f0a1aa9.tex b/sail_latex_riscv/fnzext_handle_fetch_check_error1c773c1438a4c5dcc256df216f0a1aa9.tex new file mode 100644 index 00000000..7312d106 --- /dev/null +++ b/sail_latex_riscv/fnzext_handle_fetch_check_error1c773c1438a4c5dcc256df216f0a1aa9.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzextzyhandlezyfetchzycheckzyerror]{ext\_handle\_fetch\_check\_error}#(e : ext_fetch_addr_error) -> unit = + #\hyperref[sailRISCVzhandlezycherizypcczyexception]{handle\_cheri\_pcc\_exception}#(e) diff --git a/sail_latex_riscv/fnzext_init_regs1d9ff00ce58fd5712eb26190e338015a.tex b/sail_latex_riscv/fnzext_init_regs1d9ff00ce58fd5712eb26190e338015a.tex new file mode 100644 index 00000000..7da7dcac --- /dev/null +++ b/sail_latex_riscv/fnzext_init_regs1d9ff00ce58fd5712eb26190e338015a.tex @@ -0,0 +1,56 @@ +function #\hyperref[sailRISCVzextzyinitzyregs]{ext\_init\_regs}# () = { + PCC = default_cap; + DDC = default_cap; + nextPCC = default_cap; + + UTCC = default_cap; + UTDC = null_cap; + UScratchC = null_cap; + UEPCC = default_cap; + + STCC = default_cap; + STDC = null_cap; + SScratchC = null_cap; + SEPCC = default_cap; + + MTCC = default_cap; + MTDC = null_cap; + MScratchC = null_cap; + MEPCC = default_cap; + + x1 = null_cap; + x2 = null_cap; + x3 = null_cap; + x4 = null_cap; + x5 = null_cap; + x6 = null_cap; + x7 = null_cap; + x8 = null_cap; + x9 = null_cap; + x10 = null_cap; + x11 = null_cap; + x12 = null_cap; + x13 = null_cap; + x14 = null_cap; + x15 = null_cap; + x16 = null_cap; + x17 = null_cap; + x18 = null_cap; + x19 = null_cap; + x20 = null_cap; + x21 = null_cap; + x22 = null_cap; + x23 = null_cap; + x24 = null_cap; + x25 = null_cap; + x26 = null_cap; + x27 = null_cap; + x28 = null_cap; + x29 = null_cap; + x30 = null_cap; + x31 = null_cap; + + misa->#\hyperref[sailRISCVzX]{X}#() = 0b1; + mccsr->#\hyperref[sailRISCVzd]{d}#() = 0b1; + mccsr->#\hyperref[sailRISCVze]{e}#() = 0b1; +} diff --git a/sail_latex_riscv/fnzext_initaf8e3807fa5c1bbef01331f40e0f99a4.tex b/sail_latex_riscv/fnzext_initaf8e3807fa5c1bbef01331f40e0f99a4.tex new file mode 100644 index 00000000..81b18d44 --- /dev/null +++ b/sail_latex_riscv/fnzext_initaf8e3807fa5c1bbef01331f40e0f99a4.tex @@ -0,0 +1,9 @@ +function #\hyperref[sailRISCVzextzyinit]{ext\_init}# () = { + misa->#\hyperref[sailRISCVzX]{X}#() = 0b1; + mccsr->#\hyperref[sailRISCVzd]{d}#() = 0b1; + mccsr->#\hyperref[sailRISCVze]{e}#() = 0b1; + sccsr->#\hyperref[sailRISCVzd]{d}#() = 0b1; + sccsr->#\hyperref[sailRISCVze]{e}#() = 0b1; + uccsr->#\hyperref[sailRISCVzd]{d}#() = 0b1; + uccsr->#\hyperref[sailRISCVze]{e}#() = 0b1; +} diff --git a/sail_latex_riscv/fnzext_post_decode_hook0ea81b52fdd64a9c28fe27bce7cc93bb.tex b/sail_latex_riscv/fnzext_post_decode_hook0ea81b52fdd64a9c28fe27bce7cc93bb.tex new file mode 100644 index 00000000..16abfe60 --- /dev/null +++ b/sail_latex_riscv/fnzext_post_decode_hook0ea81b52fdd64a9c28fe27bce7cc93bb.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzextzypostzydecodezyhook]{ext\_post\_decode\_hook}#(x) : ast -> ast = { + if (PCC.flag_cap_mode) then match(x) { + #\hyperref[sailRISCVzUTYPE]{UTYPE}#(imm, cd, RISCV_AUIPC) => #\hyperref[sailRISCVzAUIPCC]{AUIPCC}#(imm, cd), + OTHERS => OTHERS + } else + x +} diff --git a/sail_latex_riscv/fnzext_post_step_hook12041b61939f7dc96fabf0eb4cecd40e.tex b/sail_latex_riscv/fnzext_post_step_hook12041b61939f7dc96fabf0eb4cecd40e.tex new file mode 100644 index 00000000..69a09ba0 --- /dev/null +++ b/sail_latex_riscv/fnzext_post_step_hook12041b61939f7dc96fabf0eb4cecd40e.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzextzypostzystepzyhook]{ext\_post\_step\_hook}#() -> unit = () diff --git a/sail_latex_riscv/fnzext_pre_step_hookbaa423b1418b5f3048ae14ba522eabb5.tex b/sail_latex_riscv/fnzext_pre_step_hookbaa423b1418b5f3048ae14ba522eabb5.tex new file mode 100644 index 00000000..5ee778db --- /dev/null +++ b/sail_latex_riscv/fnzext_pre_step_hookbaa423b1418b5f3048ae14ba522eabb5.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzextzyprezystepzyhook]{ext\_pre\_step\_hook}#() -> unit = () diff --git a/sail_latex_riscv/fnzext_ptw_error_of_num6c265a5359168121d0772efe3f31cd45.tex b/sail_latex_riscv/fnzext_ptw_error_of_num6c265a5359168121d0772efe3f31cd45.tex new file mode 100644 index 00000000..1ddcf987 --- /dev/null +++ b/sail_latex_riscv/fnzext_ptw_error_of_num6c265a5359168121d0772efe3f31cd45.tex @@ -0,0 +1 @@ +function ext_ptw_error_of_num arg# = match arg# {_ => AT_CAP_ERR} diff --git a/sail_latex_riscv/fnzext_ptw_fail_of_numcc5cb6ad05de49125f246aa8627fb15b.tex b/sail_latex_riscv/fnzext_ptw_fail_of_numcc5cb6ad05de49125f246aa8627fb15b.tex new file mode 100644 index 00000000..2ba4b859 --- /dev/null +++ b/sail_latex_riscv/fnzext_ptw_fail_of_numcc5cb6ad05de49125f246aa8627fb15b.tex @@ -0,0 +1,4 @@ +function ext_ptw_fail_of_num arg# = match arg# { + 0 => EPTWF_NO_PERM, + _ => EPTWF_CAP_ERR +} diff --git a/sail_latex_riscv/fnzext_ptw_lc_joindc735a27ea989374f5eabf813141d337.tex b/sail_latex_riscv/fnzext_ptw_lc_joindc735a27ea989374f5eabf813141d337.tex new file mode 100644 index 00000000..68749ee3 --- /dev/null +++ b/sail_latex_riscv/fnzext_ptw_lc_joindc735a27ea989374f5eabf813141d337.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzextzyptwzylczyjoin]{ext\_ptw\_lc\_join}#(e : ext_ptw, l : ext_ptw_lc) -> ext_ptw = + { e with ptw_lc = + match l { + PTW_LC_OK => e.ptw_lc, + PTW_LC_CLEAR => l + } + } diff --git a/sail_latex_riscv/fnzext_ptw_lc_of_numfefbb86ad247369523da5c5114df83a8.tex b/sail_latex_riscv/fnzext_ptw_lc_of_numfefbb86ad247369523da5c5114df83a8.tex new file mode 100644 index 00000000..11f7ad8d --- /dev/null +++ b/sail_latex_riscv/fnzext_ptw_lc_of_numfefbb86ad247369523da5c5114df83a8.tex @@ -0,0 +1,4 @@ +function ext_ptw_lc_of_num arg# = match arg# { + 0 => PTW_LC_OK, + _ => PTW_LC_CLEAR +} diff --git a/sail_latex_riscv/fnzext_ptw_sc_join88636243b559a2aba809497742e7ce00.tex b/sail_latex_riscv/fnzext_ptw_sc_join88636243b559a2aba809497742e7ce00.tex new file mode 100644 index 00000000..2ba45c54 --- /dev/null +++ b/sail_latex_riscv/fnzext_ptw_sc_join88636243b559a2aba809497742e7ce00.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzextzyptwzysczyjoin]{ext\_ptw\_sc\_join}#(e : ext_ptw, s : ext_ptw_sc) -> ext_ptw = + { e with ptw_sc = + match s { + PTW_SC_OK => e.ptw_sc, + PTW_SC_TRAP => s + } + } diff --git a/sail_latex_riscv/fnzext_ptw_sc_of_num2137f22f5407b82d12c8574662600e18.tex b/sail_latex_riscv/fnzext_ptw_sc_of_num2137f22f5407b82d12c8574662600e18.tex new file mode 100644 index 00000000..deeee3c6 --- /dev/null +++ b/sail_latex_riscv/fnzext_ptw_sc_of_num2137f22f5407b82d12c8574662600e18.tex @@ -0,0 +1,4 @@ +function ext_ptw_sc_of_num arg# = match arg# { + 0 => PTW_SC_OK, + _ => PTW_SC_TRAP +} diff --git a/sail_latex_riscv/fnzext_rvfi_init925272b6b4282430111c3e89a50f1e0b.tex b/sail_latex_riscv/fnzext_rvfi_init925272b6b4282430111c3e89a50f1e0b.tex new file mode 100644 index 00000000..1d952a92 --- /dev/null +++ b/sail_latex_riscv/fnzext_rvfi_init925272b6b4282430111c3e89a50f1e0b.tex @@ -0,0 +1,33 @@ +function #\hyperref[sailRISCVzextzyrvfizyinit]{ext\_rvfi\_init}# () = { + x1 = default_cap; + x2 = default_cap; + x3 = default_cap; + x4 = default_cap; + x5 = default_cap; + x6 = default_cap; + x7 = default_cap; + x8 = default_cap; + x9 = default_cap; + x10 = default_cap; + x11 = default_cap; + x12 = default_cap; + x13 = default_cap; + x14 = default_cap; + x15 = default_cap; + x16 = default_cap; + x17 = default_cap; + x18 = default_cap; + x19 = default_cap; + x20 = default_cap; + x21 = default_cap; + x22 = default_cap; + x23 = default_cap; + x24 = default_cap; + x25 = default_cap; + x26 = default_cap; + x27 = default_cap; + x28 = default_cap; + x29 = default_cap; + x30 = default_cap; + x31 = default_cap; +} diff --git a/sail_latex_riscv/fnzext_veto_disable_cd10c2d1c5077060fa007c1628d7aaa8c.tex b/sail_latex_riscv/fnzext_veto_disable_cd10c2d1c5077060fa007c1628d7aaa8c.tex new file mode 100644 index 00000000..f0ef29ea --- /dev/null +++ b/sail_latex_riscv/fnzext_veto_disable_cd10c2d1c5077060fa007c1628d7aaa8c.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzextzyvetozydisablezyC]{ext\_veto\_disable\_C}# () = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC)[1] == bitone diff --git a/sail_latex_riscv/fnzext_write_fcsr8225c20959aaf9205d48c42ffe341a87.tex b/sail_latex_riscv/fnzext_write_fcsr8225c20959aaf9205d48c42ffe341a87.tex new file mode 100644 index 00000000..964bc4ee --- /dev/null +++ b/sail_latex_riscv/fnzext_write_fcsr8225c20959aaf9205d48c42ffe341a87.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzextzywritezyfcsr]{ext\_write\_fcsr}# (frm, fflags) = { + fcsr->#\hyperref[sailRISCVzFRM]{FRM}#() = frm; /* Note: frm can be an illegal value, 101, 110, 111 */ + fcsr->#\hyperref[sailRISCVzFFLAGS]{FFLAGS}#() = fflags; + #\hyperref[sailRISCVzupdatezysoftfloatzyfflags]{update\_softfloat\_fflags}#(fflags); + #\hyperref[sailRISCVzdirtyzyfdzycontext]{dirty\_fd\_context}#(); +} diff --git a/sail_latex_riscv/fnzextend_value8ddb26f3f92f6848beaff0fbcaa992f6.tex b/sail_latex_riscv/fnzextend_value8ddb26f3f92f6848beaff0fbcaa992f6.tex new file mode 100644 index 00000000..a65a71b8 --- /dev/null +++ b/sail_latex_riscv/fnzextend_value8ddb26f3f92f6848beaff0fbcaa992f6.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzextendzyvalue]{extend\_value}#(is_unsigned, value) = match (value) { + #\hyperref[sailRISCVzMemValue]{MemValue}#(v) => #\hyperref[sailRISCVzMemValue]{MemValue}#(if is_unsigned then #\hyperref[sailRISCVzEXTZ]{EXTZ}#(v) else #\hyperref[sailRISCVzEXTS]{EXTS}#(v) : xlenbits), + #\hyperref[sailRISCVzMemException]{MemException}#(e) => #\hyperref[sailRISCVzMemException]{MemException}#(e) +} diff --git a/sail_latex_riscv/fnzexts8a10d418fac6a2072ef1dfede4580873.tex b/sail_latex_riscv/fnzexts8a10d418fac6a2072ef1dfede4580873.tex new file mode 100644 index 00000000..25cfcd4f --- /dev/null +++ b/sail_latex_riscv/fnzexts8a10d418fac6a2072ef1dfede4580873.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzEXTS]{EXTS}#(m, v) = #\hyperref[sailRISCVzsailzysignzyextend]{sail\_sign\_extend}#(v, m) diff --git a/sail_latex_riscv/fnzextstatus_of_bits9da79344bfec7cda3e374a5ba6b49e27.tex b/sail_latex_riscv/fnzextstatus_of_bits9da79344bfec7cda3e374a5ba6b49e27.tex new file mode 100644 index 00000000..af0e129a --- /dev/null +++ b/sail_latex_riscv/fnzextstatus_of_bits9da79344bfec7cda3e374a5ba6b49e27.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzextStatuszyofzybits]{extStatus\_of\_bits}#(e) = + match (e) { + 0b00 => Off, + 0b01 => Initial, + 0b10 => Clean, + 0b11 => Dirty + } diff --git a/sail_latex_riscv/fnzextstatus_of_num31bfbda5f90ad0f3cdbc5a0f1b63da2d.tex b/sail_latex_riscv/fnzextstatus_of_num31bfbda5f90ad0f3cdbc5a0f1b63da2d.tex new file mode 100644 index 00000000..6b5366cc --- /dev/null +++ b/sail_latex_riscv/fnzextstatus_of_num31bfbda5f90ad0f3cdbc5a0f1b63da2d.tex @@ -0,0 +1,6 @@ +function ExtStatus_of_num arg# = match arg# { + 0 => Off, + 1 => Initial, + 2 => Clean, + _ => Dirty +} diff --git a/sail_latex_riscv/fnzextstatus_to_bits95f7e744a463eb9cfccacc81efa252ae.tex b/sail_latex_riscv/fnzextstatus_to_bits95f7e744a463eb9cfccacc81efa252ae.tex new file mode 100644 index 00000000..75a19615 --- /dev/null +++ b/sail_latex_riscv/fnzextstatus_to_bits95f7e744a463eb9cfccacc81efa252ae.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzextStatuszytozybits]{extStatus\_to\_bits}#(e) = + match (e) { + Off => 0b00, + Initial => 0b01, + Clean => 0b10, + Dirty => 0b11 + } diff --git a/sail_latex_riscv/fnzextzdb77018947d632a113deb15d298290d4.tex b/sail_latex_riscv/fnzextzdb77018947d632a113deb15d298290d4.tex new file mode 100644 index 00000000..fc94d861 --- /dev/null +++ b/sail_latex_riscv/fnzextzdb77018947d632a113deb15d298290d4.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzEXTZ]{EXTZ}#(m, v) = #\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(v, m) diff --git a/sail_latex_riscv/fnzf_bin_op_d_of_num97322de52afcea7a7f630a9ec29b7900.tex b/sail_latex_riscv/fnzf_bin_op_d_of_num97322de52afcea7a7f630a9ec29b7900.tex new file mode 100644 index 00000000..d41e1407 --- /dev/null +++ b/sail_latex_riscv/fnzf_bin_op_d_of_num97322de52afcea7a7f630a9ec29b7900.tex @@ -0,0 +1,10 @@ +function f_bin_op_D_of_num arg# = match arg# { + 0 => FSGNJ_D, + 1 => FSGNJN_D, + 2 => FSGNJX_D, + 3 => FMIN_D, + 4 => FMAX_D, + 5 => FEQ_D, + 6 => FLT_D, + _ => FLE_D +} diff --git a/sail_latex_riscv/fnzf_bin_op_s_of_num66d590442d54517898ad2679db0d80bc.tex b/sail_latex_riscv/fnzf_bin_op_s_of_num66d590442d54517898ad2679db0d80bc.tex new file mode 100644 index 00000000..347189b7 --- /dev/null +++ b/sail_latex_riscv/fnzf_bin_op_s_of_num66d590442d54517898ad2679db0d80bc.tex @@ -0,0 +1,10 @@ +function f_bin_op_S_of_num arg# = match arg# { + 0 => FSGNJ_S, + 1 => FSGNJN_S, + 2 => FSGNJX_S, + 3 => FMIN_S, + 4 => FMAX_S, + 5 => FEQ_S, + 6 => FLT_S, + _ => FLE_S +} diff --git a/sail_latex_riscv/fnzf_bin_rm_op_d_of_num4f1c6a877a7fdb6ce5cba8edac489378.tex b/sail_latex_riscv/fnzf_bin_rm_op_d_of_num4f1c6a877a7fdb6ce5cba8edac489378.tex new file mode 100644 index 00000000..8a924ae6 --- /dev/null +++ b/sail_latex_riscv/fnzf_bin_rm_op_d_of_num4f1c6a877a7fdb6ce5cba8edac489378.tex @@ -0,0 +1,6 @@ +function f_bin_rm_op_D_of_num arg# = match arg# { + 0 => FADD_D, + 1 => FSUB_D, + 2 => FMUL_D, + _ => FDIV_D +} diff --git a/sail_latex_riscv/fnzf_bin_rm_op_s_of_num425ba7f76e47ae16326c0417fe340273.tex b/sail_latex_riscv/fnzf_bin_rm_op_s_of_num425ba7f76e47ae16326c0417fe340273.tex new file mode 100644 index 00000000..cf71e20c --- /dev/null +++ b/sail_latex_riscv/fnzf_bin_rm_op_s_of_num425ba7f76e47ae16326c0417fe340273.tex @@ -0,0 +1,6 @@ +function f_bin_rm_op_S_of_num arg# = match arg# { + 0 => FADD_S, + 1 => FSUB_S, + 2 => FMUL_S, + _ => FDIV_S +} diff --git a/sail_latex_riscv/fnzf_is_nan_d970e43a6bafb89b645fab556a4ad623c.tex b/sail_latex_riscv/fnzf_is_nan_d970e43a6bafb89b645fab556a4ad623c.tex new file mode 100644 index 00000000..3b65e977 --- /dev/null +++ b/sail_latex_riscv/fnzf_is_nan_d970e43a6bafb89b645fab556a4ad623c.tex @@ -0,0 +1,5 @@ +function f_is_NaN_D x64 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (x64); + ( (exp == #\hyperref[sailRISCVzones]{ones}#()) + & (mant != #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_nan_s0d165c8ab9495379c496e3667f21236f.tex b/sail_latex_riscv/fnzf_is_nan_s0d165c8ab9495379c496e3667f21236f.tex new file mode 100644 index 00000000..629427a5 --- /dev/null +++ b/sail_latex_riscv/fnzf_is_nan_s0d165c8ab9495379c496e3667f21236f.tex @@ -0,0 +1,5 @@ +function f_is_NaN_S x32 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (x32); + ( (exp == #\hyperref[sailRISCVzones]{ones}#()) + & (mant != #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_neg_inf_d3f44c40462ec32ab41b8fa4dc4e6f998.tex b/sail_latex_riscv/fnzf_is_neg_inf_d3f44c40462ec32ab41b8fa4dc4e6f998.tex new file mode 100644 index 00000000..5021368f --- /dev/null +++ b/sail_latex_riscv/fnzf_is_neg_inf_d3f44c40462ec32ab41b8fa4dc4e6f998.tex @@ -0,0 +1,6 @@ +function f_is_neg_inf_D x64 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (x64); + ( (sign == 0b1) + & (exp == #\hyperref[sailRISCVzones]{ones}#()) + & (mant == #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_neg_inf_sf1e927a0ea24a891ce2c85c8d22d9613.tex b/sail_latex_riscv/fnzf_is_neg_inf_sf1e927a0ea24a891ce2c85c8d22d9613.tex new file mode 100644 index 00000000..9465a0c6 --- /dev/null +++ b/sail_latex_riscv/fnzf_is_neg_inf_sf1e927a0ea24a891ce2c85c8d22d9613.tex @@ -0,0 +1,6 @@ +function f_is_neg_inf_S x32 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (x32); + ( (sign == 0b1) + & (exp == #\hyperref[sailRISCVzones]{ones}#()) + & (mant == #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_neg_norm_d9b9e067af3304bb1fae5d1501327fd53.tex b/sail_latex_riscv/fnzf_is_neg_norm_d9b9e067af3304bb1fae5d1501327fd53.tex new file mode 100644 index 00000000..9b9ad71f --- /dev/null +++ b/sail_latex_riscv/fnzf_is_neg_norm_d9b9e067af3304bb1fae5d1501327fd53.tex @@ -0,0 +1,6 @@ +function f_is_neg_norm_D x64 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (x64); + ( (sign == 0b1) + & (exp != #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (exp != #\hyperref[sailRISCVzones]{ones}#())) +} diff --git a/sail_latex_riscv/fnzf_is_neg_norm_s8bfccfb981e547ad5f5c42e4a17c2a1f.tex b/sail_latex_riscv/fnzf_is_neg_norm_s8bfccfb981e547ad5f5c42e4a17c2a1f.tex new file mode 100644 index 00000000..b7623b9f --- /dev/null +++ b/sail_latex_riscv/fnzf_is_neg_norm_s8bfccfb981e547ad5f5c42e4a17c2a1f.tex @@ -0,0 +1,6 @@ +function f_is_neg_norm_S x32 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (x32); + ( (sign == 0b1) + & (exp != #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (exp != #\hyperref[sailRISCVzones]{ones}#())) +} diff --git a/sail_latex_riscv/fnzf_is_neg_subnorm_d808d9c9ea664491fe0b23b650d1e996c.tex b/sail_latex_riscv/fnzf_is_neg_subnorm_d808d9c9ea664491fe0b23b650d1e996c.tex new file mode 100644 index 00000000..aa8c6216 --- /dev/null +++ b/sail_latex_riscv/fnzf_is_neg_subnorm_d808d9c9ea664491fe0b23b650d1e996c.tex @@ -0,0 +1,6 @@ +function f_is_neg_subnorm_D x64 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (x64); + ( (sign == 0b1) + & (exp == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (mant != #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_neg_subnorm_sd8c8d47f6284f9e99142031238418d6e.tex b/sail_latex_riscv/fnzf_is_neg_subnorm_sd8c8d47f6284f9e99142031238418d6e.tex new file mode 100644 index 00000000..d0918a51 --- /dev/null +++ b/sail_latex_riscv/fnzf_is_neg_subnorm_sd8c8d47f6284f9e99142031238418d6e.tex @@ -0,0 +1,6 @@ +function f_is_neg_subnorm_S x32 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (x32); + ( (sign == 0b1) + & (exp == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (mant != #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_neg_zzero_d7855947d702bd41cc96dbb033e17918f.tex b/sail_latex_riscv/fnzf_is_neg_zzero_d7855947d702bd41cc96dbb033e17918f.tex new file mode 100644 index 00000000..dfef59f6 --- /dev/null +++ b/sail_latex_riscv/fnzf_is_neg_zzero_d7855947d702bd41cc96dbb033e17918f.tex @@ -0,0 +1,6 @@ +function f_is_neg_zero_D x64 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (x64); + ( (sign == #\hyperref[sailRISCVzones]{ones}#()) + & (exp == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (mant == #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_neg_zzero_s01b2d7b1def55db2428888908b29c669.tex b/sail_latex_riscv/fnzf_is_neg_zzero_s01b2d7b1def55db2428888908b29c669.tex new file mode 100644 index 00000000..2ebc04ad --- /dev/null +++ b/sail_latex_riscv/fnzf_is_neg_zzero_s01b2d7b1def55db2428888908b29c669.tex @@ -0,0 +1,6 @@ +function f_is_neg_zero_S x32 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (x32); + ( (sign == #\hyperref[sailRISCVzones]{ones}#()) + & (exp == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (mant == #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_pos_inf_ddc033c6bfe555dfe790113dec0ddb7e3.tex b/sail_latex_riscv/fnzf_is_pos_inf_ddc033c6bfe555dfe790113dec0ddb7e3.tex new file mode 100644 index 00000000..70d5dea9 --- /dev/null +++ b/sail_latex_riscv/fnzf_is_pos_inf_ddc033c6bfe555dfe790113dec0ddb7e3.tex @@ -0,0 +1,6 @@ +function f_is_pos_inf_D x64 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (x64); + ( (sign == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (exp == #\hyperref[sailRISCVzones]{ones}#()) + & (mant == #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_pos_inf_sf714fc249168edfd360262aca5e55c4d.tex b/sail_latex_riscv/fnzf_is_pos_inf_sf714fc249168edfd360262aca5e55c4d.tex new file mode 100644 index 00000000..dad0b5c0 --- /dev/null +++ b/sail_latex_riscv/fnzf_is_pos_inf_sf714fc249168edfd360262aca5e55c4d.tex @@ -0,0 +1,6 @@ +function f_is_pos_inf_S x32 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (x32); + ( (sign == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (exp == #\hyperref[sailRISCVzones]{ones}#()) + & (mant == #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_pos_norm_d6611be4e31c69209487c037c5336c370.tex b/sail_latex_riscv/fnzf_is_pos_norm_d6611be4e31c69209487c037c5336c370.tex new file mode 100644 index 00000000..38b8e5ff --- /dev/null +++ b/sail_latex_riscv/fnzf_is_pos_norm_d6611be4e31c69209487c037c5336c370.tex @@ -0,0 +1,6 @@ +function f_is_pos_norm_D x64 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (x64); + ( (sign == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (exp != #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (exp != #\hyperref[sailRISCVzones]{ones}#())) +} diff --git a/sail_latex_riscv/fnzf_is_pos_norm_s19872015fda671aa1dca05b90a2680c4.tex b/sail_latex_riscv/fnzf_is_pos_norm_s19872015fda671aa1dca05b90a2680c4.tex new file mode 100644 index 00000000..f0df21ab --- /dev/null +++ b/sail_latex_riscv/fnzf_is_pos_norm_s19872015fda671aa1dca05b90a2680c4.tex @@ -0,0 +1,6 @@ +function f_is_pos_norm_S x32 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (x32); + ( (sign == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (exp != #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (exp != #\hyperref[sailRISCVzones]{ones}#())) +} diff --git a/sail_latex_riscv/fnzf_is_pos_subnorm_d7e83f87299dae2035e33b7c97dd6be45.tex b/sail_latex_riscv/fnzf_is_pos_subnorm_d7e83f87299dae2035e33b7c97dd6be45.tex new file mode 100644 index 00000000..255d0d99 --- /dev/null +++ b/sail_latex_riscv/fnzf_is_pos_subnorm_d7e83f87299dae2035e33b7c97dd6be45.tex @@ -0,0 +1,6 @@ +function f_is_pos_subnorm_D x64 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (x64); + ( (sign == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (exp == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (mant != #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_pos_subnorm_s4efdacb98629e85ea864b456e8377a98.tex b/sail_latex_riscv/fnzf_is_pos_subnorm_s4efdacb98629e85ea864b456e8377a98.tex new file mode 100644 index 00000000..3ffff7ac --- /dev/null +++ b/sail_latex_riscv/fnzf_is_pos_subnorm_s4efdacb98629e85ea864b456e8377a98.tex @@ -0,0 +1,6 @@ +function f_is_pos_subnorm_S x32 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (x32); + ( (sign == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (exp == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (mant != #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_pos_zzero_d7e379cb7f8f90c1af7e79d78e2a86f37.tex b/sail_latex_riscv/fnzf_is_pos_zzero_d7e379cb7f8f90c1af7e79d78e2a86f37.tex new file mode 100644 index 00000000..82d3f428 --- /dev/null +++ b/sail_latex_riscv/fnzf_is_pos_zzero_d7e379cb7f8f90c1af7e79d78e2a86f37.tex @@ -0,0 +1,6 @@ +function f_is_pos_zero_D x64 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (x64); + ( (sign == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (exp == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (mant == #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_pos_zzero_s92eacf7245b38cd8fbe2b7411cc24794.tex b/sail_latex_riscv/fnzf_is_pos_zzero_s92eacf7245b38cd8fbe2b7411cc24794.tex new file mode 100644 index 00000000..edea3f6f --- /dev/null +++ b/sail_latex_riscv/fnzf_is_pos_zzero_s92eacf7245b38cd8fbe2b7411cc24794.tex @@ -0,0 +1,6 @@ +function f_is_pos_zero_S x32 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (x32); + ( (sign == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (exp == #\hyperref[sailRISCVzzzeros]{zeros}#()) + & (mant == #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_qnan_d5bbb21fc7537d62baacf94741f71226d.tex b/sail_latex_riscv/fnzf_is_qnan_d5bbb21fc7537d62baacf94741f71226d.tex new file mode 100644 index 00000000..f9fd0108 --- /dev/null +++ b/sail_latex_riscv/fnzf_is_qnan_d5bbb21fc7537d62baacf94741f71226d.tex @@ -0,0 +1,5 @@ +function f_is_QNaN_D x64 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (x64); + ( (exp == #\hyperref[sailRISCVzones]{ones}#()) + & (mant [51] == bitone)) +} diff --git a/sail_latex_riscv/fnzf_is_qnan_s36343ea7477dd88c6d9f512ad8587fd3.tex b/sail_latex_riscv/fnzf_is_qnan_s36343ea7477dd88c6d9f512ad8587fd3.tex new file mode 100644 index 00000000..6169d69a --- /dev/null +++ b/sail_latex_riscv/fnzf_is_qnan_s36343ea7477dd88c6d9f512ad8587fd3.tex @@ -0,0 +1,5 @@ +function f_is_QNaN_S x32 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (x32); + ( (exp == #\hyperref[sailRISCVzones]{ones}#()) + & (mant [22] == bitone)) +} diff --git a/sail_latex_riscv/fnzf_is_snan_d3e7f4d132d4d3fe4846581a123c48b56.tex b/sail_latex_riscv/fnzf_is_snan_d3e7f4d132d4d3fe4846581a123c48b56.tex new file mode 100644 index 00000000..2e1eeada --- /dev/null +++ b/sail_latex_riscv/fnzf_is_snan_d3e7f4d132d4d3fe4846581a123c48b56.tex @@ -0,0 +1,6 @@ +function f_is_SNaN_D x64 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (x64); + ( (exp == #\hyperref[sailRISCVzones]{ones}#()) + & (mant [51] == bitzero) + & (mant != #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_is_snan_s4f74c8b27b066b5e2d6856d63c0d8113.tex b/sail_latex_riscv/fnzf_is_snan_s4f74c8b27b066b5e2d6856d63c0d8113.tex new file mode 100644 index 00000000..23e654f9 --- /dev/null +++ b/sail_latex_riscv/fnzf_is_snan_s4f74c8b27b066b5e2d6856d63c0d8113.tex @@ -0,0 +1,6 @@ +function f_is_SNaN_S x32 = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (x32); + ( (exp == #\hyperref[sailRISCVzones]{ones}#()) + & (mant [22] == bitzero) + & (mant != #\hyperref[sailRISCVzzzeros]{zeros}#())) +} diff --git a/sail_latex_riscv/fnzf_madd_op_d_of_num115462b951eadf3acf4b0a2bb11e801b.tex b/sail_latex_riscv/fnzf_madd_op_d_of_num115462b951eadf3acf4b0a2bb11e801b.tex new file mode 100644 index 00000000..f72437d7 --- /dev/null +++ b/sail_latex_riscv/fnzf_madd_op_d_of_num115462b951eadf3acf4b0a2bb11e801b.tex @@ -0,0 +1,6 @@ +function f_madd_op_D_of_num arg# = match arg# { + 0 => FMADD_D, + 1 => FMSUB_D, + 2 => FNMSUB_D, + _ => FNMADD_D +} diff --git a/sail_latex_riscv/fnzf_madd_op_s_of_num9bfe1beb29f1f97cf6b7643bd9febe9b.tex b/sail_latex_riscv/fnzf_madd_op_s_of_num9bfe1beb29f1f97cf6b7643bd9febe9b.tex new file mode 100644 index 00000000..dc52192e --- /dev/null +++ b/sail_latex_riscv/fnzf_madd_op_s_of_num9bfe1beb29f1f97cf6b7643bd9febe9b.tex @@ -0,0 +1,6 @@ +function f_madd_op_S_of_num arg# = match arg# { + 0 => FMADD_S, + 1 => FMSUB_S, + 2 => FNMSUB_S, + _ => FNMADD_S +} diff --git a/sail_latex_riscv/fnzf_un_op_d_of_num20c93bb1c359c6ff0f65b3c91dbe8c85.tex b/sail_latex_riscv/fnzf_un_op_d_of_num20c93bb1c359c6ff0f65b3c91dbe8c85.tex new file mode 100644 index 00000000..6cd73671 --- /dev/null +++ b/sail_latex_riscv/fnzf_un_op_d_of_num20c93bb1c359c6ff0f65b3c91dbe8c85.tex @@ -0,0 +1,5 @@ +function f_un_op_D_of_num arg# = match arg# { + 0 => FCLASS_D, + 1 => FMV_X_D, + _ => FMV_D_X +} diff --git a/sail_latex_riscv/fnzf_un_op_s_of_num428b8623c493e45bc273b3e1a0c895e0.tex b/sail_latex_riscv/fnzf_un_op_s_of_num428b8623c493e45bc273b3e1a0c895e0.tex new file mode 100644 index 00000000..984da56b --- /dev/null +++ b/sail_latex_riscv/fnzf_un_op_s_of_num428b8623c493e45bc273b3e1a0c895e0.tex @@ -0,0 +1,5 @@ +function f_un_op_S_of_num arg# = match arg# { + 0 => FCLASS_S, + 1 => FMV_X_W, + _ => FMV_W_X +} diff --git a/sail_latex_riscv/fnzf_un_rm_op_d_of_num3c7528aaf2a777986f767617d6c66717.tex b/sail_latex_riscv/fnzf_un_rm_op_d_of_num3c7528aaf2a777986f767617d6c66717.tex new file mode 100644 index 00000000..093fe8a9 --- /dev/null +++ b/sail_latex_riscv/fnzf_un_rm_op_d_of_num3c7528aaf2a777986f767617d6c66717.tex @@ -0,0 +1,13 @@ +function f_un_rm_op_D_of_num arg# = match arg# { + 0 => FSQRT_D, + 1 => FCVT_W_D, + 2 => FCVT_WU_D, + 3 => FCVT_D_W, + 4 => FCVT_D_WU, + 5 => FCVT_S_D, + 6 => FCVT_D_S, + 7 => FCVT_L_D, + 8 => FCVT_LU_D, + 9 => FCVT_D_L, + _ => FCVT_D_LU +} diff --git a/sail_latex_riscv/fnzf_un_rm_op_s_of_numcf978158d6a6f45fe1893c4a9c122140.tex b/sail_latex_riscv/fnzf_un_rm_op_s_of_numcf978158d6a6f45fe1893c4a9c122140.tex new file mode 100644 index 00000000..78150f65 --- /dev/null +++ b/sail_latex_riscv/fnzf_un_rm_op_s_of_numcf978158d6a6f45fe1893c4a9c122140.tex @@ -0,0 +1,11 @@ +function f_un_rm_op_S_of_num arg# = match arg# { + 0 => FSQRT_S, + 1 => FCVT_W_S, + 2 => FCVT_WU_S, + 3 => FCVT_S_W, + 4 => FCVT_S_WU, + 5 => FCVT_L_S, + 6 => FCVT_LU_S, + 7 => FCVT_S_L, + _ => FCVT_S_LU +} diff --git a/sail_latex_riscv/fnzfastrepcheck592cc92c49a4599da60647f87c331420.tex b/sail_latex_riscv/fnzfastrepcheck592cc92c49a4599da60647f87c331420.tex new file mode 100644 index 00000000..8197ad3f --- /dev/null +++ b/sail_latex_riscv/fnzfastrepcheck592cc92c49a4599da60647f87c331420.tex @@ -0,0 +1,24 @@ +function #\hyperref[sailRISCVzfastRepCheck]{fastRepCheck}#(c, i) : (Capability, CapAddrBits) -> bool= + let E = #\hyperref[sailRISCVzunsigned]{unsigned}#(c.E) in + if (E >= maxE - 2) then + true /* in this case representable region is whole address space */ + else + let i_top = #\hyperref[sailRISCVzsigned]{signed}#(i >>#\hyperref[sailRISCVzzys]{\_s}# (E + cap_mantissa_width)) in + let i_mid = #\hyperref[sailRISCVztruncate]{truncate}#(i >> E, cap_mantissa_width)in + let a_mid = #\hyperref[sailRISCVztruncate]{truncate}#(c.address >> E, cap_mantissa_width) in + let B3 = #\hyperref[sailRISCVztruncateLSB]{truncateLSB}#(c.B, 3) in + let R3 = B3 - 0b001 in + let R = R3 @ #\hyperref[sailRISCVzzzeros]{zeros}#(cap_mantissa_width - 3) in + let diff = R - a_mid in + let diff1 = diff - 1 in + /* i_top determines 1. whether the increment is inRange + i.e. less than the size of the representable region + (2**(E+MW)) and 2. whether it is positive or negative. To + satisfy 1. all top bits must be the same so we are + interested in the cases i_top is 0 or -1 */ + if (i_top == 0) then + i_mid <_u diff1 + else if (i_top == -1) then + (i_mid >=_u diff) & (R != a_mid) + else + false diff --git a/sail_latex_riscv/fnzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex b/sail_latex_riscv/fnzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex new file mode 100644 index 00000000..67b28b12 --- /dev/null +++ b/sail_latex_riscv/fnzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex @@ -0,0 +1,9 @@ +function #\hyperref[sailRISCVzfdivzyint]{fdiv\_int}#(n: int, m: int) -> int = { + if n < 0 & m > 0 then { + #\hyperref[sailRISCVztdivzyint]{tdiv\_int}#(n + 1, m) - 1 + } else if n > 0 & m < 0 then { + #\hyperref[sailRISCVztdivzyint]{tdiv\_int}#(n - 1, m) - 1 + } else { + #\hyperref[sailRISCVztdivzyint]{tdiv\_int}#(n, m) + } +} diff --git a/sail_latex_riscv/fnzfeq_quiet_d0b6b5eb435e8b9c9bcf3b77e16fff044.tex b/sail_latex_riscv/fnzfeq_quiet_d0b6b5eb435e8b9c9bcf3b77e16fff044.tex new file mode 100644 index 00000000..87627efe --- /dev/null +++ b/sail_latex_riscv/fnzfeq_quiet_d0b6b5eb435e8b9c9bcf3b77e16fff044.tex @@ -0,0 +1,15 @@ +function #\hyperref[sailRISCVzfeqzyquietzyD]{feq\_quiet\_D}# (v1, v2) = { + let (s1, e1, m1) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (v1); + let (s2, e2, m2) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (v2); + + let v1Is0 = #\hyperref[sailRISCVzfzyiszynegzyzzerozyD]{f\_is\_neg\_zero\_D}#(v1) | #\hyperref[sailRISCVzfzyiszyposzyzzerozyD]{f\_is\_pos\_zero\_D}#(v1); + let v2Is0 = #\hyperref[sailRISCVzfzyiszynegzyzzerozyD]{f\_is\_neg\_zero\_D}#(v2) | #\hyperref[sailRISCVzfzyiszyposzyzzerozyD]{f\_is\_pos\_zero\_D}#(v2); + + let result = ((v1 == v2) | (v1Is0 & v2Is0)); + + let fflags = if (#\hyperref[sailRISCVzfzyiszySNaNzyD]{f\_is\_SNaN\_D}#(v1) | #\hyperref[sailRISCVzfzyiszySNaNzyD]{f\_is\_SNaN\_D}#(v2)) + then #\hyperref[sailRISCVznvFlag]{nvFlag}#() + else #\hyperref[sailRISCVzzzeros]{zeros}#(); + + (result, fflags) +} diff --git a/sail_latex_riscv/fnzfeq_quiet_saed522b017dd40dd277d80aee28e4fe9.tex b/sail_latex_riscv/fnzfeq_quiet_saed522b017dd40dd277d80aee28e4fe9.tex new file mode 100644 index 00000000..3c70cbb8 --- /dev/null +++ b/sail_latex_riscv/fnzfeq_quiet_saed522b017dd40dd277d80aee28e4fe9.tex @@ -0,0 +1,15 @@ +function #\hyperref[sailRISCVzfeqzyquietzyS]{feq\_quiet\_S}# (v1, v2) = { + let (s1, e1, m1) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (v1); + let (s2, e2, m2) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (v2); + + let v1Is0 = #\hyperref[sailRISCVzfzyiszynegzyzzerozyS]{f\_is\_neg\_zero\_S}#(v1) | #\hyperref[sailRISCVzfzyiszyposzyzzerozyS]{f\_is\_pos\_zero\_S}#(v1); + let v2Is0 = #\hyperref[sailRISCVzfzyiszynegzyzzerozyS]{f\_is\_neg\_zero\_S}#(v2) | #\hyperref[sailRISCVzfzyiszyposzyzzerozyS]{f\_is\_pos\_zero\_S}#(v2); + + let result = ((v1 == v2) | (v1Is0 & v2Is0)); + + let fflags = if (#\hyperref[sailRISCVzfzyiszySNaNzyS]{f\_is\_SNaN\_S}#(v1) | #\hyperref[sailRISCVzfzyiszySNaNzyS]{f\_is\_SNaN\_S}#(v2)) + then #\hyperref[sailRISCVznvFlag]{nvFlag}#() + else #\hyperref[sailRISCVzzzeros]{zeros}#(); + + (result, fflags) +} diff --git a/sail_latex_riscv/fnzfetch5e1d71b1ad15beedbd2dacb5ddbcd2b6.tex b/sail_latex_riscv/fnzfetch5e1d71b1ad15beedbd2dacb5ddbcd2b6.tex new file mode 100644 index 00000000..7a6081ff --- /dev/null +++ b/sail_latex_riscv/fnzfetch5e1d71b1ad15beedbd2dacb5ddbcd2b6.tex @@ -0,0 +1,45 @@ +function #\hyperref[sailRISCVzfetch]{fetch}#() -> FetchResult = + /* fetch PC check for extensions: extensions return a transformed PC to fetch, + * but any exceptions use the untransformed PC. + */ + match #\hyperref[sailRISCVzextzyfetchzycheckzypc]{ext\_fetch\_check\_pc}#(PC, PC) { + #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(e) => #\hyperref[sailRISCVzFzyExtzyError]{F\_Ext\_Error}#(e), + #\hyperref[sailRISCVzExtzyFetchAddrzyOK]{Ext\_FetchAddr\_OK}#(use_pc) => { + if (use_pc[0] != bitzero | (use_pc[1] != bitzero & (~ (#\hyperref[sailRISCVzhaveRVC]{haveRVC}#())))) + then #\hyperref[sailRISCVzFzyError]{F\_Error}#(#\hyperref[sailRISCVzEzyFetchzyAddrzyAlign]{E\_Fetch\_Addr\_Align}#(), PC) + else match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(use_pc, #\hyperref[sailRISCVzExecute]{Execute}#()) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => #\hyperref[sailRISCVzFzyError]{F\_Error}#(e, PC), + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(ppclo, _) => { + /* split instruction fetch into 16-bit granules to handle RVC, as + * well as to generate precise fault addresses in any fetch + * exceptions. + */ + match #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzExecute]{Execute}#(), ppclo, 2, false, false, false) { + #\hyperref[sailRISCVzMemException]{MemException}#(e) => #\hyperref[sailRISCVzFzyError]{F\_Error}#(e, PC), + #\hyperref[sailRISCVzMemValue]{MemValue}#(ilo) => { + if #\hyperref[sailRISCVzisRVC]{isRVC}#(ilo) + then #\hyperref[sailRISCVzFzyRVC]{F\_RVC}#(ilo) + else { + /* fetch PC check for the next instruction granule */ + PC_hi : xlenbits = PC + 2; + match #\hyperref[sailRISCVzextzyfetchzycheckzypc]{ext\_fetch\_check\_pc}#(PC, PC_hi) { + #\hyperref[sailRISCVzExtzyFetchAddrzyError]{Ext\_FetchAddr\_Error}#(e) => #\hyperref[sailRISCVzFzyExtzyError]{F\_Ext\_Error}#(e), + #\hyperref[sailRISCVzExtzyFetchAddrzyOK]{Ext\_FetchAddr\_OK}#(use_pc_hi) => { + match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(use_pc_hi, #\hyperref[sailRISCVzExecute]{Execute}#()) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => #\hyperref[sailRISCVzFzyError]{F\_Error}#(e, PC_hi), + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(ppchi, _) => { + match #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzExecute]{Execute}#(), ppchi, 2, false, false, false) { + #\hyperref[sailRISCVzMemException]{MemException}#(e) => #\hyperref[sailRISCVzFzyError]{F\_Error}#(e, PC_hi), + #\hyperref[sailRISCVzMemValue]{MemValue}#(ihi) => #\hyperref[sailRISCVzFzyBase]{F\_Base}#(#\hyperref[sailRISCVzappend]{append}#(ihi, ilo)) + } + } + } + } + } + } + } + } + } + } + } + } diff --git a/sail_latex_riscv/fnzfindpendinginterrupt0ed4e5cc6469ca27b20724b51027ab4c.tex b/sail_latex_riscv/fnzfindpendinginterrupt0ed4e5cc6469ca27b20724b51027ab4c.tex new file mode 100644 index 00000000..6e0cd0ed --- /dev/null +++ b/sail_latex_riscv/fnzfindpendinginterrupt0ed4e5cc6469ca27b20724b51027ab4c.tex @@ -0,0 +1,13 @@ +function #\hyperref[sailRISCVzfindPendingInterrupt]{findPendingInterrupt}#(ip : xlenbits) -> #\hyperref[sailRISCVzoption]{option}#(InterruptType) = { + let ip = #\hyperref[sailRISCVzMkzyMinterrupts]{Mk\_Minterrupts}#(ip); + if ip.#\hyperref[sailRISCVzMEI]{MEI}#() == 0b1 then #\hyperref[sailRISCVzSome]{Some}#(I_M_External) + else if ip.#\hyperref[sailRISCVzMSI]{MSI}#() == 0b1 then #\hyperref[sailRISCVzSome]{Some}#(I_M_Software) + else if ip.#\hyperref[sailRISCVzMTI]{MTI}#() == 0b1 then #\hyperref[sailRISCVzSome]{Some}#(I_M_Timer) + else if ip.#\hyperref[sailRISCVzSEI]{SEI}#() == 0b1 then #\hyperref[sailRISCVzSome]{Some}#(I_S_External) + else if ip.#\hyperref[sailRISCVzSSI]{SSI}#() == 0b1 then #\hyperref[sailRISCVzSome]{Some}#(I_S_Software) + else if ip.#\hyperref[sailRISCVzSTI]{STI}#() == 0b1 then #\hyperref[sailRISCVzSome]{Some}#(I_S_Timer) + else if ip.#\hyperref[sailRISCVzUEI]{UEI}#() == 0b1 then #\hyperref[sailRISCVzSome]{Some}#(I_U_External) + else if ip.#\hyperref[sailRISCVzUSI]{USI}#() == 0b1 then #\hyperref[sailRISCVzSome]{Some}#(I_U_Software) + else if ip.#\hyperref[sailRISCVzUTI]{UTI}#() == 0b1 then #\hyperref[sailRISCVzSome]{Some}#(I_U_Timer) + else #\hyperref[sailRISCVzNone]{None}#() +} diff --git a/sail_latex_riscv/fnzfle_dc504d6eb55e9a730eda7235ae654dd1c.tex b/sail_latex_riscv/fnzfle_dc504d6eb55e9a730eda7235ae654dd1c.tex new file mode 100644 index 00000000..30a58326 --- /dev/null +++ b/sail_latex_riscv/fnzfle_dc504d6eb55e9a730eda7235ae654dd1c.tex @@ -0,0 +1,32 @@ +function #\hyperref[sailRISCVzflezyD]{fle\_D}# (v1, v2, is_quiet) = { + let (s1, e1, m1) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (v1); + let (s2, e2, m2) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (v2); + + let v1Is0 = #\hyperref[sailRISCVzfzyiszynegzyzzerozyD]{f\_is\_neg\_zero\_D}#(v1) | #\hyperref[sailRISCVzfzyiszyposzyzzerozyD]{f\_is\_pos\_zero\_D}#(v1); + let v2Is0 = #\hyperref[sailRISCVzfzyiszynegzyzzerozyD]{f\_is\_neg\_zero\_D}#(v2) | #\hyperref[sailRISCVzfzyiszyposzyzzerozyD]{f\_is\_pos\_zero\_D}#(v2); + + let result : bool = + if (s1 == 0b0) & (s2 == 0b0) then + if (e1 == e2) + then #\hyperref[sailRISCVzunsigned]{unsigned}# (m1) <= #\hyperref[sailRISCVzunsigned]{unsigned}# (m2) + else #\hyperref[sailRISCVzunsigned]{unsigned}# (e1) < #\hyperref[sailRISCVzunsigned]{unsigned}# (e2) + else if (s1 == 0b0) & (s2 == 0b1) then + (v1Is0 & v2Is0) /* Equal in this #\hyperref[sailRISCVzcase]{case}# (+0=-0) */ + else if (s1 == 0b1) & (s2 == 0b0) then + true + else + if (e1 == e2) + then #\hyperref[sailRISCVzunsigned]{unsigned}# (m1) >= #\hyperref[sailRISCVzunsigned]{unsigned}# (m2) + else #\hyperref[sailRISCVzunsigned]{unsigned}# (e1) > #\hyperref[sailRISCVzunsigned]{unsigned}# (e2); + + let fflags = if is_quiet then + if (#\hyperref[sailRISCVzfzyiszySNaNzyD]{f\_is\_SNaN\_D}#(v1) | #\hyperref[sailRISCVzfzyiszySNaNzyD]{f\_is\_SNaN\_D}#(v2)) + then #\hyperref[sailRISCVznvFlag]{nvFlag}#() + else #\hyperref[sailRISCVzzzeros]{zeros}#() + else + if (#\hyperref[sailRISCVzfzyiszyNaNzyD]{f\_is\_NaN\_D}#(v1) | #\hyperref[sailRISCVzfzyiszyNaNzyD]{f\_is\_NaN\_D}#(v2)) + then #\hyperref[sailRISCVznvFlag]{nvFlag}#() + else #\hyperref[sailRISCVzzzeros]{zeros}#(); + + (result, fflags) +} diff --git a/sail_latex_riscv/fnzfle_s93e035a8ca13e7d64b965c7c750ae56d.tex b/sail_latex_riscv/fnzfle_s93e035a8ca13e7d64b965c7c750ae56d.tex new file mode 100644 index 00000000..caef0de8 --- /dev/null +++ b/sail_latex_riscv/fnzfle_s93e035a8ca13e7d64b965c7c750ae56d.tex @@ -0,0 +1,32 @@ +function #\hyperref[sailRISCVzflezyS]{fle\_S}# (v1, v2, is_quiet) = { + let (s1, e1, m1) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (v1); + let (s2, e2, m2) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (v2); + + let v1Is0 = #\hyperref[sailRISCVzfzyiszynegzyzzerozyS]{f\_is\_neg\_zero\_S}#(v1) | #\hyperref[sailRISCVzfzyiszyposzyzzerozyS]{f\_is\_pos\_zero\_S}#(v1); + let v2Is0 = #\hyperref[sailRISCVzfzyiszynegzyzzerozyS]{f\_is\_neg\_zero\_S}#(v2) | #\hyperref[sailRISCVzfzyiszyposzyzzerozyS]{f\_is\_pos\_zero\_S}#(v2); + + let result : bool = + if (s1 == 0b0) & (s2 == 0b0) then + if (e1 == e2) + then #\hyperref[sailRISCVzunsigned]{unsigned}# (m1) <= #\hyperref[sailRISCVzunsigned]{unsigned}# (m2) + else #\hyperref[sailRISCVzunsigned]{unsigned}# (e1) < #\hyperref[sailRISCVzunsigned]{unsigned}# (e2) + else if (s1 == 0b0) & (s2 == 0b1) + then (v1Is0 & v2Is0) /* Equal in this #\hyperref[sailRISCVzcase]{case}# (+0=-0) */ + else if (s1 == 0b1) & (s2 == 0b0) + then true + else + if (e1 == e2) + then #\hyperref[sailRISCVzunsigned]{unsigned}# (m1) >= #\hyperref[sailRISCVzunsigned]{unsigned}# (m2) + else #\hyperref[sailRISCVzunsigned]{unsigned}# (e1) > #\hyperref[sailRISCVzunsigned]{unsigned}# (e2); + + let fflags = if is_quiet then + if (#\hyperref[sailRISCVzfzyiszySNaNzyS]{f\_is\_SNaN\_S}#(v1) | #\hyperref[sailRISCVzfzyiszySNaNzyS]{f\_is\_SNaN\_S}#(v2)) + then #\hyperref[sailRISCVznvFlag]{nvFlag}#() + else #\hyperref[sailRISCVzzzeros]{zeros}#() + else + if (#\hyperref[sailRISCVzfzyiszyNaNzyS]{f\_is\_NaN\_S}#(v1) | #\hyperref[sailRISCVzfzyiszyNaNzyS]{f\_is\_NaN\_S}#(v2)) + then #\hyperref[sailRISCVznvFlag]{nvFlag}#() + else #\hyperref[sailRISCVzzzeros]{zeros}#(); + + (result, fflags) +} diff --git a/sail_latex_riscv/fnzflt_dc45e113a7fb9ece6e62166679b975f44.tex b/sail_latex_riscv/fnzflt_dc45e113a7fb9ece6e62166679b975f44.tex new file mode 100644 index 00000000..041994d1 --- /dev/null +++ b/sail_latex_riscv/fnzflt_dc45e113a7fb9ece6e62166679b975f44.tex @@ -0,0 +1,29 @@ +function #\hyperref[sailRISCVzfltzyD]{flt\_D}# (v1, v2, is_quiet) = { + let (s1, e1, m1) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (v1); + let (s2, e2, m2) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (v2); + + let result : bool = + if (s1 == 0b0) & (s2 == 0b0) then + if (e1 == e2) + then #\hyperref[sailRISCVzunsigned]{unsigned}# (m1) < #\hyperref[sailRISCVzunsigned]{unsigned}# (m2) + else #\hyperref[sailRISCVzunsigned]{unsigned}# (e1) < #\hyperref[sailRISCVzunsigned]{unsigned}# (e2) + else if (s1 == 0b0) & (s2 == 0b1) then + false + else if (s1 == 0b1) & (s2 == 0b0) then + true + else + if (e1 == e2) + then #\hyperref[sailRISCVzunsigned]{unsigned}# (m1) > #\hyperref[sailRISCVzunsigned]{unsigned}# (m2) + else #\hyperref[sailRISCVzunsigned]{unsigned}# (e1) > #\hyperref[sailRISCVzunsigned]{unsigned}# (e2); + + let fflags = if is_quiet then + if (#\hyperref[sailRISCVzfzyiszySNaNzyD]{f\_is\_SNaN\_D}#(v1) | #\hyperref[sailRISCVzfzyiszySNaNzyD]{f\_is\_SNaN\_D}#(v2)) + then #\hyperref[sailRISCVznvFlag]{nvFlag}#() + else #\hyperref[sailRISCVzzzeros]{zeros}#() + else + if (#\hyperref[sailRISCVzfzyiszyNaNzyD]{f\_is\_NaN\_D}#(v1) | #\hyperref[sailRISCVzfzyiszyNaNzyD]{f\_is\_NaN\_D}#(v2)) + then #\hyperref[sailRISCVznvFlag]{nvFlag}#() + else #\hyperref[sailRISCVzzzeros]{zeros}#(); + + (result, fflags) +} diff --git a/sail_latex_riscv/fnzflt_sb42cf5853deeee1a9c0ed2ff1e36a52b.tex b/sail_latex_riscv/fnzflt_sb42cf5853deeee1a9c0ed2ff1e36a52b.tex new file mode 100644 index 00000000..019bd21d --- /dev/null +++ b/sail_latex_riscv/fnzflt_sb42cf5853deeee1a9c0ed2ff1e36a52b.tex @@ -0,0 +1,29 @@ +function #\hyperref[sailRISCVzfltzyS]{flt\_S}# (v1, v2, is_quiet) = { + let (s1, e1, m1) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (v1); + let (s2, e2, m2) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (v2); + + let result : bool = + if (s1 == 0b0) & (s2 == 0b0) then + if (e1 == e2) + then #\hyperref[sailRISCVzunsigned]{unsigned}# (m1) < #\hyperref[sailRISCVzunsigned]{unsigned}# (m2) + else #\hyperref[sailRISCVzunsigned]{unsigned}# (e1) < #\hyperref[sailRISCVzunsigned]{unsigned}# (e2) + else if (s1 == 0b0) & (s2 == 0b1) + then false + else if (s1 == 0b1) & (s2 == 0b0) + then true + else + if (e1 == e2) + then #\hyperref[sailRISCVzunsigned]{unsigned}# (m1) > #\hyperref[sailRISCVzunsigned]{unsigned}# (m2) + else #\hyperref[sailRISCVzunsigned]{unsigned}# (e1) > #\hyperref[sailRISCVzunsigned]{unsigned}# (e2); + + let fflags = if is_quiet then + if (#\hyperref[sailRISCVzfzyiszySNaNzyS]{f\_is\_SNaN\_S}#(v1) | #\hyperref[sailRISCVzfzyiszySNaNzyS]{f\_is\_SNaN\_S}#(v2)) + then #\hyperref[sailRISCVznvFlag]{nvFlag}#() + else #\hyperref[sailRISCVzzzeros]{zeros}#() + else + if (#\hyperref[sailRISCVzfzyiszyNaNzyS]{f\_is\_NaN\_S}#(v1) | #\hyperref[sailRISCVzfzyiszyNaNzyS]{f\_is\_NaN\_S}#(v2)) + then #\hyperref[sailRISCVznvFlag]{nvFlag}#() + else #\hyperref[sailRISCVzzzeros]{zeros}#(); + + (result, fflags) +} diff --git a/sail_latex_riscv/fnzflush_tlb39155d346596461ed0e3ab611745b6738a.tex b/sail_latex_riscv/fnzflush_tlb39155d346596461ed0e3ab611745b6738a.tex new file mode 100644 index 00000000..7299c318 --- /dev/null +++ b/sail_latex_riscv/fnzflush_tlb39155d346596461ed0e3ab611745b6738a.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzflushzyTLB39]{flush\_TLB39}#(asid, addr) = + match (tlb39) { + #\hyperref[sailRISCVzNone]{None}#() => (), + #\hyperref[sailRISCVzSome]{Some}#(e) => if #\hyperref[sailRISCVzflushzyTLBzyEntry]{flush\_TLB\_Entry}#(e, asid, addr) + then tlb39 = #\hyperref[sailRISCVzNone]{None}#() + else () + } diff --git a/sail_latex_riscv/fnzflush_tlb482377e6a21b0e61c1f15d8ef64c6ac044.tex b/sail_latex_riscv/fnzflush_tlb482377e6a21b0e61c1f15d8ef64c6ac044.tex new file mode 100644 index 00000000..9c356849 --- /dev/null +++ b/sail_latex_riscv/fnzflush_tlb482377e6a21b0e61c1f15d8ef64c6ac044.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzflushzyTLB48]{flush\_TLB48}#(asid, addr) = + match (tlb48) { + #\hyperref[sailRISCVzNone]{None}#() => (), + #\hyperref[sailRISCVzSome]{Some}#(e) => if #\hyperref[sailRISCVzflushzyTLBzyEntry]{flush\_TLB\_Entry}#(e, asid, addr) + then tlb48 = #\hyperref[sailRISCVzNone]{None}#() + else () + } diff --git a/sail_latex_riscv/fnzflush_tlb_entry8073b262f27cbbda50ac10a3cc21c463.tex b/sail_latex_riscv/fnzflush_tlb_entry8073b262f27cbbda50ac10a3cc21c463.tex new file mode 100644 index 00000000..34ff4537 --- /dev/null +++ b/sail_latex_riscv/fnzflush_tlb_entry8073b262f27cbbda50ac10a3cc21c463.tex @@ -0,0 +1,9 @@ +function #\hyperref[sailRISCVzflushzyTLBzyEntry]{flush\_TLB\_Entry}#(e, asid, addr) = { + match(asid, addr) { + ( #\hyperref[sailRISCVzNone]{None}#(), #\hyperref[sailRISCVzNone]{None}#()) => true, + ( #\hyperref[sailRISCVzNone]{None}#(), #\hyperref[sailRISCVzSome]{Some}#(a)) => e.vAddr == (e.vMatchMask & a), + (#\hyperref[sailRISCVzSome]{Some}#(i), #\hyperref[sailRISCVzNone]{None}#()) => (e.asid == i) & (~ (e.global)), + (#\hyperref[sailRISCVzSome]{Some}#(i), #\hyperref[sailRISCVzSome]{Some}#(a)) => ( (e.asid == i) & (e.vAddr == (a & e.vMatchMask)) + & (~ (e.global))) + } +} diff --git a/sail_latex_riscv/fnzflush_tlbf2c831dee428b5971141e383ef962e36.tex b/sail_latex_riscv/fnzflush_tlbf2c831dee428b5971141e383ef962e36.tex new file mode 100644 index 00000000..553f831a --- /dev/null +++ b/sail_latex_riscv/fnzflush_tlbf2c831dee428b5971141e383ef962e36.tex @@ -0,0 +1,15 @@ +function #\hyperref[sailRISCVzflushzyTLB]{flush\_TLB}#(asid_xlen, addr_xlen) -> unit = { + /* Flush both Sv39 and Sv48 TLBs. */ + let (addr39, addr48) : (#\hyperref[sailRISCVzoption]{option}#(vaddr39), #\hyperref[sailRISCVzoption]{option}#(vaddr48)) = + match addr_xlen { + #\hyperref[sailRISCVzNone]{None}#() => (#\hyperref[sailRISCVzNone]{None}#(), #\hyperref[sailRISCVzNone]{None}#()), + #\hyperref[sailRISCVzSome]{Some}#(a) => (#\hyperref[sailRISCVzSome]{Some}#(a[38 .. 0]), #\hyperref[sailRISCVzSome]{Some}#(a[47 .. 0])) + }; + let asid : #\hyperref[sailRISCVzoption]{option}#(asid64) = + match asid_xlen { + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzNone]{None}#(), + #\hyperref[sailRISCVzSome]{Some}#(a) => #\hyperref[sailRISCVzSome]{Some}#(a[15 .. 0]) + }; + #\hyperref[sailRISCVzflushzyTLB39]{flush\_TLB39}#(asid, addr39); + #\hyperref[sailRISCVzflushzyTLB48]{flush\_TLB48}#(asid, addr48) +} diff --git a/sail_latex_riscv/fnzfmake_de1abf4e676ae7d02ecd6d0037a7d77ee.tex b/sail_latex_riscv/fnzfmake_de1abf4e676ae7d02ecd6d0037a7d77ee.tex new file mode 100644 index 00000000..fed7b053 --- /dev/null +++ b/sail_latex_riscv/fnzfmake_de1abf4e676ae7d02ecd6d0037a7d77ee.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzfmakezyD]{fmake\_D}# (sign, exp, mant) = sign @ exp @ mant diff --git a/sail_latex_riscv/fnzfmake_sf09ffe3c3e52a17eb1e248d73c150f66.tex b/sail_latex_riscv/fnzfmake_sf09ffe3c3e52a17eb1e248d73c150f66.tex new file mode 100644 index 00000000..bfea1a4b --- /dev/null +++ b/sail_latex_riscv/fnzfmake_sf09ffe3c3e52a17eb1e248d73c150f66.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzfmakezyS]{fmake\_S}# (sign, exp, mant) = sign @ exp @ mant diff --git a/sail_latex_riscv/fnzfmod_int7e215ca2b888f4e92201959fd40958a5.tex b/sail_latex_riscv/fnzfmod_int7e215ca2b888f4e92201959fd40958a5.tex new file mode 100644 index 00000000..0a89b009 --- /dev/null +++ b/sail_latex_riscv/fnzfmod_int7e215ca2b888f4e92201959fd40958a5.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzfmodzyint]{fmod\_int}#(n: int, m: int) -> int = { + n - (m * #\hyperref[sailRISCVzfdivzyint]{fdiv\_int}#(n, m)) +} diff --git a/sail_latex_riscv/fnzfregstr48009e974e6089e7ac15bb0f9271a481.tex b/sail_latex_riscv/fnzfregstr48009e974e6089e7ac15bb0f9271a481.tex new file mode 100644 index 00000000..99ee1440 --- /dev/null +++ b/sail_latex_riscv/fnzfregstr48009e974e6089e7ac15bb0f9271a481.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzFRegStr]{FRegStr}#(r) = #\hyperref[sailRISCVzBitStr]{BitStr}#(r) diff --git a/sail_latex_riscv/fnzfregval_from_freg24f4c96a7be559c758c7de5e3dfe669b.tex b/sail_latex_riscv/fnzfregval_from_freg24f4c96a7be559c758c7de5e3dfe669b.tex new file mode 100644 index 00000000..700901d6 --- /dev/null +++ b/sail_latex_riscv/fnzfregval_from_freg24f4c96a7be559c758c7de5e3dfe669b.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzfregvalzyfromzyfreg]{fregval\_from\_freg}#(r) = r diff --git a/sail_latex_riscv/fnzfregval_into_fregc2bccb9e14fa0e7ca1dec382b998fa46.tex b/sail_latex_riscv/fnzfregval_into_fregc2bccb9e14fa0e7ca1dec382b998fa46.tex new file mode 100644 index 00000000..0153d400 --- /dev/null +++ b/sail_latex_riscv/fnzfregval_into_fregc2bccb9e14fa0e7ca1dec382b998fa46.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzfregvalzyintozyfreg]{fregval\_into\_freg}#(v) = v diff --git a/sail_latex_riscv/fnzfsplit_d774cb8ca3d70fb4590f5725c3fd93ad0.tex b/sail_latex_riscv/fnzfsplit_d774cb8ca3d70fb4590f5725c3fd93ad0.tex new file mode 100644 index 00000000..3e0dbf45 --- /dev/null +++ b/sail_latex_riscv/fnzfsplit_d774cb8ca3d70fb4590f5725c3fd93ad0.tex @@ -0,0 +1 @@ +function fsplit_D x64 = (x64[63..63], x64[62..52], x64[51..0]) diff --git a/sail_latex_riscv/fnzfsplit_s587b8f3a581d4f6ab15969163c75b5ff.tex b/sail_latex_riscv/fnzfsplit_s587b8f3a581d4f6ab15969163c75b5ff.tex new file mode 100644 index 00000000..31f900f4 --- /dev/null +++ b/sail_latex_riscv/fnzfsplit_s587b8f3a581d4f6ab15969163c75b5ff.tex @@ -0,0 +1 @@ +function fsplit_S x32 = (x32[31..31], x32[30..23], x32[22..0]) diff --git a/sail_latex_riscv/fnzget_arch_pc874e1e50a5765cd3e317d37fa710a52d.tex b/sail_latex_riscv/fnzget_arch_pc874e1e50a5765cd3e317d37fa710a52d.tex new file mode 100644 index 00000000..f906bff1 --- /dev/null +++ b/sail_latex_riscv/fnzget_arch_pc874e1e50a5765cd3e317d37fa710a52d.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzgetzyarchzypc]{get\_arch\_pc}# () = + PC - #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC) diff --git a/sail_latex_riscv/fnzget_cheri_mode_cap_addr267a231c94a9ae3cf08d67cb43590a2e.tex b/sail_latex_riscv/fnzget_cheri_mode_cap_addr267a231c94a9ae3cf08d67cb43590a2e.tex new file mode 100644 index 00000000..7a51dbf3 --- /dev/null +++ b/sail_latex_riscv/fnzget_cheri_mode_cap_addr267a231c94a9ae3cf08d67cb43590a2e.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzgetzycherizymodezycapzyaddr]{get\_cheri\_mode\_cap\_addr}# (base_reg : regidx, offset : xlenbits) = { + if (PCC.flag_cap_mode) then + let base_cap = #\hyperref[sailRISCVzC]{C}#(base_reg) in + (base_cap, base_cap.address + offset, 0b0 @ base_reg) + else + let ddc = DDC in + (ddc, ddc.address + #\hyperref[sailRISCVzX]{X}#(base_reg) + offset, DDC_IDX); +} diff --git a/sail_latex_riscv/fnzget_config_print_instrcd725d09d3941c391aadf6b945a364c4.tex b/sail_latex_riscv/fnzget_config_print_instrcd725d09d3941c391aadf6b945a364c4.tex new file mode 100644 index 00000000..4c0d1b1d --- /dev/null +++ b/sail_latex_riscv/fnzget_config_print_instrcd725d09d3941c391aadf6b945a364c4.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzgetzyconfigzyprintzyinstr]{get\_config\_print\_instr}# () = false diff --git a/sail_latex_riscv/fnzget_config_print_memae95e5785b79c4a3f0105a772bf99dca.tex b/sail_latex_riscv/fnzget_config_print_memae95e5785b79c4a3f0105a772bf99dca.tex new file mode 100644 index 00000000..a4b9c13c --- /dev/null +++ b/sail_latex_riscv/fnzget_config_print_memae95e5785b79c4a3f0105a772bf99dca.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzgetzyconfigzyprintzymem]{get\_config\_print\_mem}# () = false diff --git a/sail_latex_riscv/fnzget_config_print_platform65eee2fe1a7d52174acea1de4e724e03.tex b/sail_latex_riscv/fnzget_config_print_platform65eee2fe1a7d52174acea1de4e724e03.tex new file mode 100644 index 00000000..c7647aab --- /dev/null +++ b/sail_latex_riscv/fnzget_config_print_platform65eee2fe1a7d52174acea1de4e724e03.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}# () = false diff --git a/sail_latex_riscv/fnzget_config_print_rega14ad214dae5f2d46538a3770abc93e2.tex b/sail_latex_riscv/fnzget_config_print_rega14ad214dae5f2d46538a3770abc93e2.tex new file mode 100644 index 00000000..5343b6d9 --- /dev/null +++ b/sail_latex_riscv/fnzget_config_print_rega14ad214dae5f2d46538a3770abc93e2.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}# () = false diff --git a/sail_latex_riscv/fnzget_mstatus_sxl360b4b5f8d3130ad7ed7bb536d1d7019.tex b/sail_latex_riscv/fnzget_mstatus_sxl360b4b5f8d3130ad7ed7bb536d1d7019.tex new file mode 100644 index 00000000..0f8f0d13 --- /dev/null +++ b/sail_latex_riscv/fnzget_mstatus_sxl360b4b5f8d3130ad7ed7bb536d1d7019.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzgetzymstatuszySXL]{get\_mstatus\_SXL}#(m : Mstatus) -> arch_xlen = { + if sizeof(xlen) == 32 + then #\hyperref[sailRISCVzarchzytozybits]{arch\_to\_bits}#(RV32) + else m.#\hyperref[sailRISCVzbits]{bits}#()[35 .. 34] +} diff --git a/sail_latex_riscv/fnzget_mstatus_uxl7f41d7b1028a3b1a7e11b635a0524660.tex b/sail_latex_riscv/fnzget_mstatus_uxl7f41d7b1028a3b1a7e11b635a0524660.tex new file mode 100644 index 00000000..eb154ea6 --- /dev/null +++ b/sail_latex_riscv/fnzget_mstatus_uxl7f41d7b1028a3b1a7e11b635a0524660.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzgetzymstatuszyUXL]{get\_mstatus\_UXL}#(m : Mstatus) -> arch_xlen = { + if sizeof(xlen) == 32 + then #\hyperref[sailRISCVzarchzytozybits]{arch\_to\_bits}#(RV32) + else m.#\hyperref[sailRISCVzbits]{bits}#()[33 .. 32] +} diff --git a/sail_latex_riscv/fnzget_mtvec134cdc828faab7bf9f19733fba43da2f.tex b/sail_latex_riscv/fnzget_mtvec134cdc828faab7bf9f19733fba43da2f.tex new file mode 100644 index 00000000..b0b9f9c8 --- /dev/null +++ b/sail_latex_riscv/fnzget_mtvec134cdc828faab7bf9f19733fba43da2f.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzgetzymtvec]{get\_mtvec}#() -> xlenbits = + #\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(MTCC) diff --git a/sail_latex_riscv/fnzget_next_pc52098782da35f914abcd4b708363813b.tex b/sail_latex_riscv/fnzget_next_pc52098782da35f914abcd4b708363813b.tex new file mode 100644 index 00000000..3bdaf282 --- /dev/null +++ b/sail_latex_riscv/fnzget_next_pc52098782da35f914abcd4b708363813b.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzgetzynextzypc]{get\_next\_pc}#() = + nextPC - #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(PCC) diff --git a/sail_latex_riscv/fnzget_sstatus_uxl1156c19b76a50f309373d09741dbfe73.tex b/sail_latex_riscv/fnzget_sstatus_uxl1156c19b76a50f309373d09741dbfe73.tex new file mode 100644 index 00000000..f3b83672 --- /dev/null +++ b/sail_latex_riscv/fnzget_sstatus_uxl1156c19b76a50f309373d09741dbfe73.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzgetzysstatuszyUXL]{get\_sstatus\_UXL}#(s : Sstatus) -> arch_xlen = { + let m = #\hyperref[sailRISCVzMkzyMstatus]{Mk\_Mstatus}#(s.#\hyperref[sailRISCVzbits]{bits}#()); + #\hyperref[sailRISCVzgetzymstatuszyUXL]{get\_mstatus\_UXL}#(m) +} diff --git a/sail_latex_riscv/fnzget_stvec8e871a236060976d6c548af2b67478db.tex b/sail_latex_riscv/fnzget_stvec8e871a236060976d6c548af2b67478db.tex new file mode 100644 index 00000000..7a46b46e --- /dev/null +++ b/sail_latex_riscv/fnzget_stvec8e871a236060976d6c548af2b67478db.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzgetzystvec]{get\_stvec}#() -> xlenbits = + #\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(STCC) diff --git a/sail_latex_riscv/fnzget_utvec375b7b6fc923ff7174c10f9b93b1b2cf.tex b/sail_latex_riscv/fnzget_utvec375b7b6fc923ff7174c10f9b93b1b2cf.tex new file mode 100644 index 00000000..17ac50c4 --- /dev/null +++ b/sail_latex_riscv/fnzget_utvec375b7b6fc923ff7174c10f9b93b1b2cf.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzgetzyutvec]{get\_utvec}#() -> xlenbits = + #\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(UTCC) diff --git a/sail_latex_riscv/fnzget_xret_target26ce66652c1cd67f2e91b685c1d44e62.tex b/sail_latex_riscv/fnzget_xret_target26ce66652c1cd67f2e91b685c1d44e62.tex new file mode 100644 index 00000000..c1719457 --- /dev/null +++ b/sail_latex_riscv/fnzget_xret_target26ce66652c1cd67f2e91b685c1d44e62.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzgetzyxretzytarget]{get\_xret\_target}#(p) = { + let cap : Capability = match p { + Machine => MEPCC, + Supervisor => SEPCC, + User => UEPCC + }; + #\hyperref[sailRISCVzlegalizzezyxepc]{legalize\_xepc}#(#\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(cap)) +} diff --git a/sail_latex_riscv/fnzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex b/sail_latex_riscv/fnzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex new file mode 100644 index 00000000..6fa482d2 --- /dev/null +++ b/sail_latex_riscv/fnzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzgetCapBase]{getCapBase}#(c) : Capability -> CapAddrInt = + #\hyperref[sailRISCVzunsigned]{unsigned}#(#\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(c)) diff --git a/sail_latex_riscv/fnzgetcapbasebits475f0d31f4d2e3d821fa3069875fc752.tex b/sail_latex_riscv/fnzgetcapbasebits475f0d31f4d2e3d821fa3069875fc752.tex new file mode 100644 index 00000000..4b628a10 --- /dev/null +++ b/sail_latex_riscv/fnzgetcapbasebits475f0d31f4d2e3d821fa3069875fc752.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(c) : Capability -> CapAddrBits = + let (base, _) = #\hyperref[sailRISCVzgetCapBoundsBits]{getCapBoundsBits}#(c) in + base diff --git a/sail_latex_riscv/fnzgetcapboundsbitscff2a996e27fb45794770bad0b82e1fe.tex b/sail_latex_riscv/fnzgetcapboundsbitscff2a996e27fb45794770bad0b82e1fe.tex new file mode 100644 index 00000000..7d9e14d2 --- /dev/null +++ b/sail_latex_riscv/fnzgetcapboundsbitscff2a996e27fb45794770bad0b82e1fe.tex @@ -0,0 +1,34 @@ +function #\hyperref[sailRISCVzgetCapBoundsBits]{getCapBoundsBits}#(c) : Capability -> (CapAddrBits, CapLenBits) = + let E = #\hyperref[sailRISCVzmin]{min}#(maxE, #\hyperref[sailRISCVzunsigned]{unsigned}#(c.E)) in + let a : CapAddrBits = c.address in + /* Extract bits we need to make the top correction and calculate representable limit */ + let a3 = #\hyperref[sailRISCVztruncate]{truncate}#(a >> (E + cap_mantissa_width - 3), 3) in + let B3 = #\hyperref[sailRISCVztruncateLSB]{truncateLSB}#(c.B, 3) in + let T3 = #\hyperref[sailRISCVztruncateLSB]{truncateLSB}#(c.T, 3) in + let R3 = B3 - 0b001 in /* wraps */ + /* Do address, base and top lie in the R aligned region above the one containing R? */ + let aHi = if a3 <_u R3 then 1 else 0 in + let bHi = if B3 <_u R3 then 1 else 0 in + let tHi = if T3 <_u R3 then 1 else 0 in + /* Compute region corrections for top and base relative to a */ + let correction_base = bHi - aHi in + let correction_top = tHi - aHi in + let a_top = (a >> (E + cap_mantissa_width)) in { + base : CapLenBits = #\hyperref[sailRISCVztruncate]{truncate}#((a_top + correction_base) @ c.B @ #\hyperref[sailRISCVzzzeros]{zeros}#(E), cap_len_width); + top : CapLenBits = #\hyperref[sailRISCVztruncate]{truncate}#((a_top + correction_top) @ c.T @ #\hyperref[sailRISCVzzzeros]{zeros}#(E), cap_len_width); + /* If the base and top are more than an address space away from each other, + invert the MSB of top. This corrects for errors that happen when the + representable space wraps the address space. */ + let base2 : #\hyperref[sailRISCVzbits]{bits}#(2) = 0b0 @ [base[cap_addr_width - 1]]; + let top2 : #\hyperref[sailRISCVzbits]{bits}#(2) = top[cap_addr_width .. cap_addr_width - 1]; + if (E < (maxE - 1)) & (#\hyperref[sailRISCVzunsigned]{unsigned}#(top2 - base2) > 1) then { + top[cap_addr_width] = ~(top[cap_addr_width]); + }; + /* TODO The following top MSB correction was thought to be equivalent + to the one above, but differs at least in some cases where E >= maxE - 1 + if (base[cap_addr_width] == bitone) then { + top[cap_addr_width] = if (aHi == 1) & (tHi == 1) then bitone else bitzero; + }; + */ + (base[(cap_addr_width - 1)..0], top) + } diff --git a/sail_latex_riscv/fnzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex b/sail_latex_riscv/fnzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex new file mode 100644 index 00000000..924f62e3 --- /dev/null +++ b/sail_latex_riscv/fnzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzgetCapBounds]{getCapBounds}#(cap) : Capability -> (CapAddrInt, CapLen) = + let (base, top) = #\hyperref[sailRISCVzgetCapBoundsBits]{getCapBoundsBits}#(cap) in + (#\hyperref[sailRISCVzunsigned]{unsigned}#(base), #\hyperref[sailRISCVzunsigned]{unsigned}#(top)) diff --git a/sail_latex_riscv/fnzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex b/sail_latex_riscv/fnzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex new file mode 100644 index 00000000..c9b72315 --- /dev/null +++ b/sail_latex_riscv/fnzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzgetCapCursor]{getCapCursor}#(cap) : Capability -> CapAddrInt = #\hyperref[sailRISCVzunsigned]{unsigned}#(cap.address) diff --git a/sail_latex_riscv/fnzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex b/sail_latex_riscv/fnzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex new file mode 100644 index 00000000..7816e147 --- /dev/null +++ b/sail_latex_riscv/fnzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzgetCapFlags]{getCapFlags}#(cap) = #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.flag_cap_mode) diff --git a/sail_latex_riscv/fnzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex b/sail_latex_riscv/fnzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex new file mode 100644 index 00000000..ff2df8a4 --- /dev/null +++ b/sail_latex_riscv/fnzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex @@ -0,0 +1,13 @@ +function #\hyperref[sailRISCVzgetCapHardPerms]{getCapHardPerms}#(cap) : Capability -> #\hyperref[sailRISCVzbits]{bits}#(cap_hperms_width) = + (#\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.permit_set_CID) + @ #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.access_system_regs) + @ #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.permit_unseal) + @ #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.permit_cinvoke) + @ #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.permit_seal) + @ #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.permit_store_local_cap) + @ #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.permit_store_cap) + @ #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.permit_load_cap) + @ #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.permit_store) + @ #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.permit_load) + @ #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.permit_execute) + @ #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(cap.global)) diff --git a/sail_latex_riscv/fnzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex b/sail_latex_riscv/fnzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex new file mode 100644 index 00000000..002b2113 --- /dev/null +++ b/sail_latex_riscv/fnzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex @@ -0,0 +1,10 @@ +function #\hyperref[sailRISCVzgetCapLength]{getCapLength}#(c) : Capability -> CapLen = + let ('base, 'top) = #\hyperref[sailRISCVzgetCapBounds]{getCapBounds}#(c) in { + /* For valid capabilties we expect top >= base and hence + * length >= 0 but representation does allow top < base in some + * cases so might encounter on untagged capabilities. Here we just + * pretend it is a 65-bit quantitiy and wrap. + */ + assert (#\hyperref[sailRISCVznot]{not}#(c.tag) | top >= base); + (top - base) % #\hyperref[sailRISCVzpow2]{pow2}#(cap_len_width) + } diff --git a/sail_latex_riscv/fnzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex b/sail_latex_riscv/fnzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex new file mode 100644 index 00000000..fd7ba17b --- /dev/null +++ b/sail_latex_riscv/fnzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzgetCapOffset]{getCapOffset}#(c) : Capability -> CapAddrInt = + #\hyperref[sailRISCVzunsigned]{unsigned}#(#\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(c)) diff --git a/sail_latex_riscv/fnzgetcapoffsetbits4ee7332151f133f0a8370e45dc0808ca.tex b/sail_latex_riscv/fnzgetcapoffsetbits4ee7332151f133f0a8370e45dc0808ca.tex new file mode 100644 index 00000000..ee492687 --- /dev/null +++ b/sail_latex_riscv/fnzgetcapoffsetbits4ee7332151f133f0a8370e45dc0808ca.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(c) : Capability -> CapAddrBits = + let base : CapAddrBits = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(c) in + c.address - base diff --git a/sail_latex_riscv/fnzgetcapperms6aed04c1602f540bb5d604425f922d92.tex b/sail_latex_riscv/fnzgetcapperms6aed04c1602f540bb5d604425f922d92.tex new file mode 100644 index 00000000..19185da4 --- /dev/null +++ b/sail_latex_riscv/fnzgetcapperms6aed04c1602f540bb5d604425f922d92.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzgetCapPerms]{getCapPerms}#(cap) : Capability -> CapPermsBits = + let perms : #\hyperref[sailRISCVzbits]{bits}#(cap_uperms_shift) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzgetCapHardPerms]{getCapHardPerms}#(cap)) in + cap.uperms @ perms diff --git a/sail_latex_riscv/fnzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex b/sail_latex_riscv/fnzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex new file mode 100644 index 00000000..8a4d931d --- /dev/null +++ b/sail_latex_riscv/fnzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzgetCapTop]{getCapTop}# (c) : Capability -> CapLen = + #\hyperref[sailRISCVzunsigned]{unsigned}#(#\hyperref[sailRISCVzgetCapTopBits]{getCapTopBits}#(c)) diff --git a/sail_latex_riscv/fnzgetcaptopbits5ee890f973b03f4c37ec6911afe96449.tex b/sail_latex_riscv/fnzgetcaptopbits5ee890f973b03f4c37ec6911afe96449.tex new file mode 100644 index 00000000..1aa724b5 --- /dev/null +++ b/sail_latex_riscv/fnzgetcaptopbits5ee890f973b03f4c37ec6911afe96449.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzgetCapTopBits]{getCapTopBits}#(c) : Capability -> CapLenBits = + let (_, top) = #\hyperref[sailRISCVzgetCapBoundsBits]{getCapBoundsBits}#(c) in + top diff --git a/sail_latex_riscv/fnzgetpendingsetfe7aa2453fb185b904f0c1c2ec773ed8.tex b/sail_latex_riscv/fnzgetpendingsetfe7aa2453fb185b904f0c1c2ec773ed8.tex new file mode 100644 index 00000000..98ee2259 --- /dev/null +++ b/sail_latex_riscv/fnzgetpendingsetfe7aa2453fb185b904f0c1c2ec773ed8.tex @@ -0,0 +1,32 @@ +function #\hyperref[sailRISCVzgetPendingSet]{getPendingSet}#(priv : Privilege) -> #\hyperref[sailRISCVzoption]{option}#((xlenbits, Privilege)) = { + assert(#\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#(), "no user mode: M/U or M/S/U system required"); + let effective_pending = mip.#\hyperref[sailRISCVzbits]{bits}#() & mie.#\hyperref[sailRISCVzbits]{bits}#(); + if effective_pending == #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0) then #\hyperref[sailRISCVzNone]{None}#() /* fast path */ + else { + /* Higher privileges than the current one are implicitly enabled, + * while lower privileges are blocked. An unsupported privilege is + * considered blocked. + */ + let mIE = priv != Machine | (priv == Machine & mstatus.#\hyperref[sailRISCVzMIE]{MIE}#() == 0b1); + let sIE = #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (priv == User | (priv == Supervisor & mstatus.#\hyperref[sailRISCVzSIE]{SIE}#() == 0b1)); + let uIE = #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() & (priv == User & mstatus.#\hyperref[sailRISCVzUIE]{UIE}#() == 0b1); + match #\hyperref[sailRISCVzprocessPending]{processPending}#(mip, mie, mideleg.#\hyperref[sailRISCVzbits]{bits}#(), mIE) { + #\hyperref[sailRISCVzIntszyEmpty]{Ints\_Empty}#() => #\hyperref[sailRISCVzNone]{None}#(), + #\hyperref[sailRISCVzIntszyPending]{Ints\_Pending}#(p) => let r = (p, Machine) in #\hyperref[sailRISCVzSome]{Some}#(r), + #\hyperref[sailRISCVzIntszyDelegated]{Ints\_Delegated}#(d) => + if (~ (#\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#())) then { + if uIE then let r = (d, User) in #\hyperref[sailRISCVzSome]{Some}#(r) + else #\hyperref[sailRISCVzNone]{None}#() + } else { + /* the delegated bits are pending for S-mode */ + match #\hyperref[sailRISCVzprocessPending]{processPending}#(#\hyperref[sailRISCVzMkzyMinterrupts]{Mk\_Minterrupts}#(d), mie, sideleg.#\hyperref[sailRISCVzbits]{bits}#(), sIE) { + #\hyperref[sailRISCVzIntszyEmpty]{Ints\_Empty}#() => #\hyperref[sailRISCVzNone]{None}#(), + #\hyperref[sailRISCVzIntszyPending]{Ints\_Pending}#(p) => let r = (p, Supervisor) in #\hyperref[sailRISCVzSome]{Some}#(r), + #\hyperref[sailRISCVzIntszyDelegated]{Ints\_Delegated}#(d) => if uIE + then let r = (d, User) in #\hyperref[sailRISCVzSome]{Some}#(r) + else #\hyperref[sailRISCVzNone]{None}#() + } + } + } + } +} diff --git a/sail_latex_riscv/fnzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex b/sail_latex_riscv/fnzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex new file mode 100644 index 00000000..da643f41 --- /dev/null +++ b/sail_latex_riscv/fnzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzgetRepresentableAlignmentMask]{getRepresentableAlignmentMask}#(len) : xlenbits -> xlenbits = { + let (exact, c) = #\hyperref[sailRISCVzsetCapBounds]{setCapBounds}#(default_cap, #\hyperref[sailRISCVztozybits]{to\_bits}#(sizeof(xlen), 0), 0b0 @ len); + let e = #\hyperref[sailRISCVzmin]{min}#(#\hyperref[sailRISCVzunsigned]{unsigned}#(c.E), maxE); + let e' = if c.internal_e then e + internal_exponent_take_bits else 0; + #\hyperref[sailRISCVzones]{ones}#(sizeof(xlen)-e') @ #\hyperref[sailRISCVzzzeros]{zeros}#(e') +} diff --git a/sail_latex_riscv/fnzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex b/sail_latex_riscv/fnzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex new file mode 100644 index 00000000..a6a5a9c8 --- /dev/null +++ b/sail_latex_riscv/fnzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzgetRepresentableLength]{getRepresentableLength}#(len) : xlenbits -> xlenbits = { + let m = #\hyperref[sailRISCVzgetRepresentableAlignmentMask]{getRepresentableAlignmentMask}#(len); + (len + ~(m)) & m +} diff --git a/sail_latex_riscv/fnzgprstr8a694e087c131a3070bde7e75ad3a570.tex b/sail_latex_riscv/fnzgprstr8a694e087c131a3070bde7e75ad3a570.tex new file mode 100644 index 00000000..f8c83e3f --- /dev/null +++ b/sail_latex_riscv/fnzgprstr8a694e087c131a3070bde7e75ad3a570.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzGPRstr]{GPRstr}#(i: #\hyperref[sailRISCVzbits]{bits}#(5)) -> string = GPRstrs[#\hyperref[sailRISCVzunsigned]{unsigned}#(i)] diff --git a/sail_latex_riscv/fnzhandle_cheri_cap_exceptionc1ff083ca6d0a739fb48243e22ff4898.tex b/sail_latex_riscv/fnzhandle_cheri_cap_exceptionc1ff083ca6d0a739fb48243e22ff4898.tex new file mode 100644 index 00000000..83381a3f --- /dev/null +++ b/sail_latex_riscv/fnzhandle_cheri_cap_exceptionc1ff083ca6d0a739fb48243e22ff4898.tex @@ -0,0 +1,14 @@ +function #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(capEx, regnum) = + { + #\hyperref[sailRISCVzprint]{print}#("CHERI " ^ #\hyperref[sailRISCVzstringzyofzycapex]{string\_of\_capex}#(capEx) ^ " Reg=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(regnum)); + let cause : cheri_cause = struct { + cap_idx = regnum, + capEx = capEx + }; + let t : sync_exception = struct { + trap = #\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(EXC_CHERI), + excinfo = (#\hyperref[sailRISCVzNone]{None}#() : #\hyperref[sailRISCVzoption]{option}#(xlenbits)), + ext = #\hyperref[sailRISCVzSome]{Some}#(cause) + }; + #\hyperref[sailRISCVzsetzynextzypc]{set\_next\_pc}#(#\hyperref[sailRISCVzexceptionzyhandler]{exception\_handler}#(cur_privilege, #\hyperref[sailRISCVzCTLzyTRAP]{CTL\_TRAP}#(t), PC)) + } diff --git a/sail_latex_riscv/fnzhandle_cheri_pcc_exception3ca0178a61c5394ac2c49197cedda1c1.tex b/sail_latex_riscv/fnzhandle_cheri_pcc_exception3ca0178a61c5394ac2c49197cedda1c1.tex new file mode 100644 index 00000000..3434c16c --- /dev/null +++ b/sail_latex_riscv/fnzhandle_cheri_pcc_exception3ca0178a61c5394ac2c49197cedda1c1.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzhandlezycherizypcczyexception]{handle\_cheri\_pcc\_exception}#(capEx) = + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(capEx, 0b100000) diff --git a/sail_latex_riscv/fnzhandle_cheri_reg_exceptionfad1b48ae08f4eb90d02a5d75771c894.tex b/sail_latex_riscv/fnzhandle_cheri_reg_exceptionfad1b48ae08f4eb90d02a5d75771c894.tex new file mode 100644 index 00000000..3b39099e --- /dev/null +++ b/sail_latex_riscv/fnzhandle_cheri_reg_exceptionfad1b48ae08f4eb90d02a5d75771c894.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzhandlezycherizyregzyexception]{handle\_cheri\_reg\_exception}#(capEx, regnum) = + let reg6 = 0b0 @ regnum in + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(capEx, reg6) diff --git a/sail_latex_riscv/fnzhandle_exception5b7a94266182a8a2ef0291c83b256387.tex b/sail_latex_riscv/fnzhandle_exception5b7a94266182a8a2ef0291c83b256387.tex new file mode 100644 index 00000000..4fe0fb78 --- /dev/null +++ b/sail_latex_riscv/fnzhandle_exception5b7a94266182a8a2ef0291c83b256387.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzhandlezyexception]{handle\_exception}#(e: ExceptionType) -> unit = { + let t : sync_exception = struct { trap = e, + excinfo = #\hyperref[sailRISCVzNone]{None}#(), + ext = #\hyperref[sailRISCVzNone]{None}#() } in + #\hyperref[sailRISCVzsetzynextzypc]{set\_next\_pc}#(#\hyperref[sailRISCVzexceptionzyhandler]{exception\_handler}#(cur_privilege, #\hyperref[sailRISCVzCTLzyTRAP]{CTL\_TRAP}#(t), PC)) +} diff --git a/sail_latex_riscv/fnzhandle_illegal5907526c9d8e4989ca440b67ea4948c3.tex b/sail_latex_riscv/fnzhandle_illegal5907526c9d8e4989ca440b67ea4948c3.tex new file mode 100644 index 00000000..ba7cf23f --- /dev/null +++ b/sail_latex_riscv/fnzhandle_illegal5907526c9d8e4989ca440b67ea4948c3.tex @@ -0,0 +1,9 @@ +function #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#() -> unit = { + let info = if #\hyperref[sailRISCVzplatzymtvalzyhaszyillegalzyinstzybits]{plat\_mtval\_has\_illegal\_inst\_bits}# () + then #\hyperref[sailRISCVzSome]{Some}#(instbits) + else #\hyperref[sailRISCVzNone]{None}#(); + let t : sync_exception = struct { trap = #\hyperref[sailRISCVzEzyIllegalzyInstr]{E\_Illegal\_Instr}#(), + excinfo = info, + ext = #\hyperref[sailRISCVzNone]{None}#() }; + #\hyperref[sailRISCVzsetzynextzypc]{set\_next\_pc}#(#\hyperref[sailRISCVzexceptionzyhandler]{exception\_handler}#(cur_privilege, #\hyperref[sailRISCVzCTLzyTRAP]{CTL\_TRAP}#(t), PC)) +} diff --git a/sail_latex_riscv/fnzhandle_interrupt9048a02caa891e49449f7a1f3f4e9ee4.tex b/sail_latex_riscv/fnzhandle_interrupt9048a02caa891e49449f7a1f3f4e9ee4.tex new file mode 100644 index 00000000..a4912fc9 --- /dev/null +++ b/sail_latex_riscv/fnzhandle_interrupt9048a02caa891e49449f7a1f3f4e9ee4.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzhandlezyinterrupt]{handle\_interrupt}#(i : InterruptType, del_priv : Privilege) -> unit = + #\hyperref[sailRISCVzsetzynextzypc]{set\_next\_pc}#(#\hyperref[sailRISCVztrapzyhandler]{trap\_handler}#(del_priv, true, #\hyperref[sailRISCVzinterruptTypezytozybits]{interruptType\_to\_bits}#(i), PC, #\hyperref[sailRISCVzNone]{None}#(), #\hyperref[sailRISCVzNone]{None}#())) diff --git a/sail_latex_riscv/fnzhandle_load_cap_via_capc983c32af845a3dec84f2d1241c33390.tex b/sail_latex_riscv/fnzhandle_load_cap_via_capc983c32af845a3dec84f2d1241c33390.tex new file mode 100644 index 00000000..d99d6ae1 --- /dev/null +++ b/sail_latex_riscv/fnzhandle_load_cap_via_capc983c32af845a3dec84f2d1241c33390.tex @@ -0,0 +1,36 @@ +function #\hyperref[sailRISCVzhandlezyloadzycapzyviazycap]{handle\_load\_cap\_via\_cap}#(cd, auth_idx, auth_val, vaddrBits) = { + let aq : bool = false; + let rl : bool = false; + if #\hyperref[sailRISCVznot]{not}#(auth_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_TagViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(auth_val) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_SealViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}# (auth_val.permit_load) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_PermitLoadViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(auth_val, vaddrBits, cap_size)) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_LengthViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVziszyalignedzyaddr]{is\_aligned\_addr}#(vaddrBits, cap_size)) then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, #\hyperref[sailRISCVzEzyLoadzyAddrzyAlign]{E\_Load\_Addr\_Align}#()); + RETIRE_FAIL + } else match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddrBits, #\hyperref[sailRISCVzRead]{Read}#(Cap)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(_), _) => { #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("unexpected cheri exception for cap load") }, + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, ptw_info) => { + let c = #\hyperref[sailRISCVzmemzyreadzycap]{mem\_read\_cap}#(addr, aq, rl, false); + match c { + #\hyperref[sailRISCVzMemValue]{MemValue}#(v) => { + let cr = if ptw_info.ptw_lc == PTW_LC_CLEAR + then {v with tag = false} /* strip the tag */ + else {v with tag = v.tag & auth_val.permit_load_cap}; + #\hyperref[sailRISCVzC]{C}#(cd) = cr; + RETIRE_SUCCESS + }, + #\hyperref[sailRISCVzMemException]{MemException}#(e) => {#\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL } + } + } + } +} diff --git a/sail_latex_riscv/fnzhandle_load_data_via_capf2827ba9c795213ba1703c9ae04ec80e.tex b/sail_latex_riscv/fnzhandle_load_data_via_capf2827ba9c795213ba1703c9ae04ec80e.tex new file mode 100644 index 00000000..5f19cc5a --- /dev/null +++ b/sail_latex_riscv/fnzhandle_load_data_via_capf2827ba9c795213ba1703c9ae04ec80e.tex @@ -0,0 +1,31 @@ +function #\hyperref[sailRISCVzhandlezyloadzydatazyviazycap]{handle\_load\_data\_via\_cap}#(rd, auth_idx, auth_val, vaddrBits, is_unsigned, width) = { + let size = #\hyperref[sailRISCVzwordzywidthzybytes]{word\_width\_bytes}#(width); + let aq : bool = false; + let rl : bool = false; + if #\hyperref[sailRISCVznot]{not}#(auth_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_TagViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(auth_val) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_SealViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}# (auth_val.permit_load) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_PermitLoadViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(auth_val, vaddrBits, size)) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_LengthViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzcheckzymisaligned]{check\_misaligned}#(vaddrBits, width) then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, #\hyperref[sailRISCVzEzyLoadzyAddrzyAlign]{E\_Load\_Addr\_Align}#()); + RETIRE_FAIL + } else match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddrBits, #\hyperref[sailRISCVzRead]{Read}#(Data)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(_), _) => { #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("unexpected cheri exception for data load") }, + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, _) => + match (width, sizeof(xlen)) { + (BYTE, _) => #\hyperref[sailRISCVzprocesszyload]{process\_load}#(rd, vaddrBits, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), addr, 1, aq, rl, false), is_unsigned), + (HALF, _) => #\hyperref[sailRISCVzprocesszyload]{process\_load}#(rd, vaddrBits, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), addr, 2, aq, rl, false), is_unsigned), + (WORD, _) => #\hyperref[sailRISCVzprocesszyload]{process\_load}#(rd, vaddrBits, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), addr, 4, aq, rl, false), is_unsigned), + (DOUBLE, 64) => #\hyperref[sailRISCVzprocesszyload]{process\_load}#(rd, vaddrBits, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), addr, 8, aq, rl, false), is_unsigned) + } + } +} diff --git a/sail_latex_riscv/fnzhandle_loadres_cap_via_capcff54276a28e84c26d372dc8f545b3f0.tex b/sail_latex_riscv/fnzhandle_loadres_cap_via_capcff54276a28e84c26d372dc8f545b3f0.tex new file mode 100644 index 00000000..9d94fc24 --- /dev/null +++ b/sail_latex_riscv/fnzhandle_loadres_cap_via_capcff54276a28e84c26d372dc8f545b3f0.tex @@ -0,0 +1,41 @@ +function #\hyperref[sailRISCVzhandlezyloadreszycapzyviazycap]{handle\_loadres\_cap\_via\_cap}#(cd, auth_idx, auth_val, vaddrBits) = { + let aq : bool = true; /* cheri-specific aq/rl */ + let rl : bool = true; + let is_unsigned = false; +if #\hyperref[sailRISCVznot]{not}#(auth_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_TagViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(auth_val) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_SealViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}# (auth_val.permit_load) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_PermitLoadViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(auth_val, vaddrBits, cap_size)) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_LengthViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVziszyalignedzyaddr]{is\_aligned\_addr}#(vaddrBits, cap_size)) then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, #\hyperref[sailRISCVzEzyLoadzyAddrzyAlign]{E\_Load\_Addr\_Align}#()); + RETIRE_FAIL + } else match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddrBits, #\hyperref[sailRISCVzRead]{Read}#(Cap)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(_), _) => { #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("unexpected cheri exception for cap load") }, + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, ptw_info) => { + let c = #\hyperref[sailRISCVzmemzyreadzycap]{mem\_read\_cap}#(addr, aq, rl, false); + match c { + #\hyperref[sailRISCVzMemValue]{MemValue}#(v) => { + let cr = if ptw_info.ptw_lc == PTW_LC_CLEAR + then {v with tag = false} /* strip the tag */ + else { + /* the Sail model currently reserves virtual addresses */ + #\hyperref[sailRISCVzloadzyreservation]{load\_reservation}#(addr); + {v with tag = v.tag & auth_val.permit_load_cap} + }; + #\hyperref[sailRISCVzC]{C}#(cd) = cr; + RETIRE_SUCCESS + }, + #\hyperref[sailRISCVzMemException]{MemException}#(e) => {#\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL } + } + } + } +} diff --git a/sail_latex_riscv/fnzhandle_loadres_data_via_cap08189f30ce7dd627d16d9228026d4005.tex b/sail_latex_riscv/fnzhandle_loadres_data_via_cap08189f30ce7dd627d16d9228026d4005.tex new file mode 100644 index 00000000..30a432ed --- /dev/null +++ b/sail_latex_riscv/fnzhandle_loadres_data_via_cap08189f30ce7dd627d16d9228026d4005.tex @@ -0,0 +1,32 @@ +function #\hyperref[sailRISCVzhandlezyloadreszydatazyviazycap]{handle\_loadres\_data\_via\_cap}#(rd, auth_idx, auth_val, vaddrBits, width) = { + let size = #\hyperref[sailRISCVzwordzywidthzybytes]{word\_width\_bytes}#(width); + let aq : bool = false; + let rl : bool = false; + let is_unsigned = false; + if #\hyperref[sailRISCVznot]{not}#(auth_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_TagViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(auth_val) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_SealViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}# (auth_val.permit_load) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_PermitLoadViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(auth_val, vaddrBits, size)) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_LengthViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzcheckzyreszymisaligned]{check\_res\_misaligned}#(vaddrBits, width) then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, #\hyperref[sailRISCVzEzyLoadzyAddrzyAlign]{E\_Load\_Addr\_Align}#()); + RETIRE_FAIL + } else match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddrBits, #\hyperref[sailRISCVzRead]{Read}#(Data)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(_), _) => { #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("unexpected cheri exception for data load") }, + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, _) => + match (width, sizeof(xlen)) { + (BYTE, _) => #\hyperref[sailRISCVzprocesszyloadres]{process\_loadres}#(rd, vaddrBits, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), addr, 1, aq, rl, false), is_unsigned), + (HALF, _) => #\hyperref[sailRISCVzprocesszyloadres]{process\_loadres}#(rd, vaddrBits, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), addr, 2, aq, rl, false), is_unsigned), + (WORD, _) => #\hyperref[sailRISCVzprocesszyloadres]{process\_loadres}#(rd, vaddrBits, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), addr, 4, aq, rl, false), is_unsigned), + (DOUBLE, 64) => #\hyperref[sailRISCVzprocesszyloadres]{process\_loadres}#(rd, vaddrBits, #\hyperref[sailRISCVzmemzyread]{mem\_read}#(#\hyperref[sailRISCVzRead]{Read}#(Data), addr, 8, aq, rl, false), is_unsigned) + } + } +} diff --git a/sail_latex_riscv/fnzhandle_mem_exceptionec2a0168c4f7affdb0652fb9992ac72e.tex b/sail_latex_riscv/fnzhandle_mem_exceptionec2a0168c4f7affdb0652fb9992ac72e.tex new file mode 100644 index 00000000..8d5c0807 --- /dev/null +++ b/sail_latex_riscv/fnzhandle_mem_exceptionec2a0168c4f7affdb0652fb9992ac72e.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(addr : xlenbits, e : ExceptionType) -> unit = { + let t : sync_exception = struct { trap = e, + excinfo = #\hyperref[sailRISCVzSome]{Some}#(addr), + ext = #\hyperref[sailRISCVzNone]{None}#() } in + #\hyperref[sailRISCVzsetzynextzypc]{set\_next\_pc}#(#\hyperref[sailRISCVzexceptionzyhandler]{exception\_handler}#(cur_privilege, #\hyperref[sailRISCVzCTLzyTRAP]{CTL\_TRAP}#(t), PC)) +} diff --git a/sail_latex_riscv/fnzhandle_store_cap_via_cap4d789b2f59a39e53239d073296e45c38.tex b/sail_latex_riscv/fnzhandle_store_cap_via_cap4d789b2f59a39e53239d073296e45c38.tex new file mode 100644 index 00000000..9a42c162 --- /dev/null +++ b/sail_latex_riscv/fnzhandle_store_cap_via_cap4d789b2f59a39e53239d073296e45c38.tex @@ -0,0 +1,43 @@ +function #\hyperref[sailRISCVzhandlezystorezycapzyviazycap]{handle\_store\_cap\_via\_cap}#(cs2, auth_idx, auth_val, vaddrBits) = { + let cs2_val = #\hyperref[sailRISCVzC]{C}#(cs2); + let aq : bool = false; + let rl : bool = false; + if #\hyperref[sailRISCVznot]{not}#(auth_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_TagViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(auth_val) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_SealViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}# (auth_val.permit_store) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_PermitStoreViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}# (auth_val.permit_store_cap) & cs2_val.tag then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_PermitStoreCapViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}# (auth_val.permit_store_local_cap) & cs2_val.tag & #\hyperref[sailRISCVznot]{not}#(cs2_val.global) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_PermitStoreLocalCapViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(auth_val, vaddrBits, cap_size)) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_LengthViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVziszyalignedzyaddr]{is\_aligned\_addr}#(vaddrBits, cap_size)) then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, #\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#()); + RETIRE_FAIL + } else match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddrBits, #\hyperref[sailRISCVzWrite]{Write}#(if cs2_val.tag then Cap else Data)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, _) => { + let eares : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(unit) = #\hyperref[sailRISCVzmemzywritezyeazycap]{mem\_write\_ea\_cap}#(addr, aq, rl, false); + match (eares) { + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(_) => { + let res : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(bool) = #\hyperref[sailRISCVzmemzywritezycap]{mem\_write\_cap}#(addr, cs2_val, aq, rl, false); + match (res) { + #\hyperref[sailRISCVzMemValue]{MemValue}#(true) => RETIRE_SUCCESS, + #\hyperref[sailRISCVzMemValue]{MemValue}#(false) => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("store got false from mem_write_value"), + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL } + } + } + } + } + } +} diff --git a/sail_latex_riscv/fnzhandle_store_cond_cap_via_capdfc2c7d93322ab0a720ded29c24438b2.tex b/sail_latex_riscv/fnzhandle_store_cond_cap_via_capdfc2c7d93322ab0a720ded29c24438b2.tex new file mode 100644 index 00000000..de7df2b3 --- /dev/null +++ b/sail_latex_riscv/fnzhandle_store_cond_cap_via_capdfc2c7d93322ab0a720ded29c24438b2.tex @@ -0,0 +1,61 @@ +function #\hyperref[sailRISCVzhandlezystorezycondzycapzyviazycap]{handle\_store\_cond\_cap\_via\_cap}#(cs2, auth_idx, auth_val, vaddrBits) = { + let cs2_val = #\hyperref[sailRISCVzC]{C}#(cs2); + let aq : bool = true; /* cheri-specific aq/rl */ + let rl : bool = true; + if #\hyperref[sailRISCVznot]{not}#(auth_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_TagViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(auth_val) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_SealViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}# (auth_val.permit_store) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_PermitStoreViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}# (auth_val.permit_store_cap) & cs2_val.tag then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_PermitStoreCapViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}# (auth_val.permit_store_local_cap) & cs2_val.tag & #\hyperref[sailRISCVznot]{not}#(cs2_val.global) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_PermitStoreLocalCapViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(auth_val, vaddrBits, cap_size)) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_LengthViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVziszyalignedzyaddr]{is\_aligned\_addr}#(vaddrBits, cap_size)) then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, #\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#()); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzmatchzyreservation]{match\_reservation}#(vaddrBits) == false then { + /* cannot happen in rmem */ + #\hyperref[sailRISCVzC]{C}#(cs2) = #\hyperref[sailRISCVzintzytozycap]{int\_to\_cap}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1)); + #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); + RETIRE_SUCCESS + } else { + match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddrBits, #\hyperref[sailRISCVzWrite]{Write}#(if cs2_val.tag then Cap else Data)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, _) => { + let eares : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(unit) = #\hyperref[sailRISCVzmemzywritezyeazycap]{mem\_write\_ea\_cap}#(addr, aq, rl, false); + match (eares) { + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(_) => { + let res : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(bool) = #\hyperref[sailRISCVzmemzywritezycap]{mem\_write\_cap}#(addr, cs2_val, aq, rl, false); + match (res) { + #\hyperref[sailRISCVzMemValue]{MemValue}#(true) => { + #\hyperref[sailRISCVzC]{C}#(cs2) = #\hyperref[sailRISCVzintzytozycap]{int\_to\_cap}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0)); + #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); + RETIRE_SUCCESS + }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(false) => { + #\hyperref[sailRISCVzC]{C}#(cs2) = #\hyperref[sailRISCVzintzytozycap]{int\_to\_cap}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1)); + #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); + RETIRE_SUCCESS + }, + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); + RETIRE_FAIL + } + } + } + } + } + } + } +} diff --git a/sail_latex_riscv/fnzhandle_store_cond_data_via_cap90bf472704e0e0e2072d2afbb0123121.tex b/sail_latex_riscv/fnzhandle_store_cond_data_via_cap90bf472704e0e0e2072d2afbb0123121.tex new file mode 100644 index 00000000..29cc0485 --- /dev/null +++ b/sail_latex_riscv/fnzhandle_store_cond_data_via_cap90bf472704e0e0e2072d2afbb0123121.tex @@ -0,0 +1,50 @@ +function #\hyperref[sailRISCVzhandlezystorezycondzydatazyviazycap]{handle\_store\_cond\_data\_via\_cap}#(rs2, auth_idx, auth_val, vaddrBits, width) = { + let size = #\hyperref[sailRISCVzwordzywidthzybytes]{word\_width\_bytes}#(width); + let aq : bool = true; /* cheri-specific aq/rl */ + let rl : bool = true; + if #\hyperref[sailRISCVznot]{not}#(auth_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_TagViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(auth_val) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_SealViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}# (auth_val.permit_store) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_PermitStoreViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(auth_val, vaddrBits, size)) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_LengthViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzcheckzyreszymisaligned]{check\_res\_misaligned}#(vaddrBits, width) then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, #\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#()); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzmatchzyreservation]{match\_reservation}#(vaddrBits) == false then { + #\hyperref[sailRISCVzX]{X}#(rs2) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1); + #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); + RETIRE_SUCCESS + } else { + match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddrBits, #\hyperref[sailRISCVzWrite]{Write}#(Data)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(_), _) => { #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("unexpected cheri exception for data store") }, + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, _) => { + let eares : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(unit) = #\hyperref[sailRISCVzmemzywritezyea]{mem\_write\_ea}#(addr, size, aq, rl, false); + match (eares) { + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(_) => { + let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); + let res : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 1, rs2_val[7..0], aq, rl, false), + (HALF, _) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 2, rs2_val[15..0], aq, rl, false), + (WORD, _) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 4, rs2_val[31..0], aq, rl, false), + (DOUBLE, 64) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 8, rs2_val, aq, rl, false) + }; + match (res) { + #\hyperref[sailRISCVzMemValue]{MemValue}#(true) => { #\hyperref[sailRISCVzX]{X}#(rs2) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); RETIRE_SUCCESS }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(false) => { #\hyperref[sailRISCVzX]{X}#(rs2) = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1); #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); RETIRE_SUCCESS }, + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL } + } + } + } + } + } + } +} diff --git a/sail_latex_riscv/fnzhandle_store_data_via_capa375706a8b6644ee610b608c6152f081.tex b/sail_latex_riscv/fnzhandle_store_data_via_capa375706a8b6644ee610b608c6152f081.tex new file mode 100644 index 00000000..4da530aa --- /dev/null +++ b/sail_latex_riscv/fnzhandle_store_data_via_capa375706a8b6644ee610b608c6152f081.tex @@ -0,0 +1,44 @@ +function #\hyperref[sailRISCVzhandlezystorezydatazyviazycap]{handle\_store\_data\_via\_cap}#(rs2, auth_idx, auth_val, vaddrBits, width) = { + let size = #\hyperref[sailRISCVzwordzywidthzybytes]{word\_width\_bytes}#(width); + let aq : bool = false; + let rl : bool = false; + if #\hyperref[sailRISCVznot]{not}#(auth_val.tag) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_TagViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(auth_val) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_SealViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}# (auth_val.permit_store) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_PermitStoreViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzinCapBounds]{inCapBounds}#(auth_val, vaddrBits, size)) then { + #\hyperref[sailRISCVzhandlezycherizycapzyexception]{handle\_cheri\_cap\_exception}#(CapEx_LengthViolation, auth_idx); + RETIRE_FAIL + } else if #\hyperref[sailRISCVzcheckzymisaligned]{check\_misaligned}#(vaddrBits, width) then { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, #\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#()); + RETIRE_FAIL + } else match #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vaddrBits, #\hyperref[sailRISCVzWrite]{Write}#(Data)) { + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(_), _) => { #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("unexpected cheri exception for data store") }, + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(e, _) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(addr, _) => { + let eares : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(unit) = #\hyperref[sailRISCVzmemzywritezyea]{mem\_write\_ea}#(addr, size, aq, rl, false); + match (eares) { + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(_) => { + let rs2_val = #\hyperref[sailRISCVzX]{X}#(rs2); + let res : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 1, rs2_val[7..0], aq, rl, false), + (HALF, _) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 2, rs2_val[15..0], aq, rl, false), + (WORD, _) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 4, rs2_val[31..0], aq, rl, false), + (DOUBLE, 64) => #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(addr, 8, rs2_val, aq, rl, false) + }; + match (res) { + #\hyperref[sailRISCVzMemValue]{MemValue}#(true) => RETIRE_SUCCESS, + #\hyperref[sailRISCVzMemValue]{MemValue}#(false) => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("store got false from mem_write_value"), + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddrBits, e); RETIRE_FAIL } + } + } + } + } + } +} diff --git a/sail_latex_riscv/fnzhandle_trap_extension9480b0ad72ce05ffcdcc27185eb4525c.tex b/sail_latex_riscv/fnzhandle_trap_extension9480b0ad72ce05ffcdcc27185eb4525c.tex new file mode 100644 index 00000000..1070153d --- /dev/null +++ b/sail_latex_riscv/fnzhandle_trap_extension9480b0ad72ce05ffcdcc27185eb4525c.tex @@ -0,0 +1,34 @@ +function #\hyperref[sailRISCVzhandlezytrapzyextension]{handle\_trap\_extension}#(p : Privilege, pc : xlenbits, ccause : #\hyperref[sailRISCVzoption]{option}#(cheri_cause)) -> unit = { + match p { + Machine => { + match ccause { + #\hyperref[sailRISCVzSome]{Some}#(c) => { mccsr->#\hyperref[sailRISCVzcapzyidx]{cap\_idx}#() = c.cap_idx; + mccsr->#\hyperref[sailRISCVzcause]{cause}#() = #\hyperref[sailRISCVzCapExCode]{CapExCode}#(c.capEx) }, + _ => () + }; + let (representable, mepcc) = #\hyperref[sailRISCVzsetCapAddr]{setCapAddr}#(PCC, pc); + assert(representable, "mepcc should always be representable"); + MEPCC = mepcc + }, + Supervisor => { + match ccause { + #\hyperref[sailRISCVzSome]{Some}#(c) => { sccsr->#\hyperref[sailRISCVzcapzyidx]{cap\_idx}#() = c.cap_idx; + sccsr->#\hyperref[sailRISCVzcause]{cause}#() = #\hyperref[sailRISCVzCapExCode]{CapExCode}#(c.capEx) }, + _ => () + }; + let (representable, sepcc) = #\hyperref[sailRISCVzsetCapAddr]{setCapAddr}#(PCC, pc); + assert(representable, "sepcc should always be representable"); + SEPCC = sepcc + }, + User => { + match ccause { + #\hyperref[sailRISCVzSome]{Some}#(c) => { uccsr->#\hyperref[sailRISCVzcapzyidx]{cap\_idx}#() = c.cap_idx; + uccsr->#\hyperref[sailRISCVzcause]{cause}#() = #\hyperref[sailRISCVzCapExCode]{CapExCode}#(c.capEx) }, + _ => () + }; + let (representable, uepcc) = #\hyperref[sailRISCVzsetCapAddr]{setCapAddr}#(PCC, pc); + assert(representable, "uepcc should always be representable"); + UEPCC = uepcc + } + } +} diff --git a/sail_latex_riscv/fnzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex b/sail_latex_riscv/fnzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex new file mode 100644 index 00000000..f93e1c5a --- /dev/null +++ b/sail_latex_riscv/fnzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhasReservedOType]{hasReservedOType}#(cap) = #\hyperref[sailRISCVzunsigned]{unsigned}#(cap.otype) > max_otype diff --git a/sail_latex_riscv/fnzhaveatomics63cb703b1e3f955440fac8b850da53f7.tex b/sail_latex_riscv/fnzhaveatomics63cb703b1e3f955440fac8b850da53f7.tex new file mode 100644 index 00000000..4ccd4172 --- /dev/null +++ b/sail_latex_riscv/fnzhaveatomics63cb703b1e3f955440fac8b850da53f7.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhaveAtomics]{haveAtomics}#() -> bool = misa.#\hyperref[sailRISCVzA]{A}#() == 0b1 diff --git a/sail_latex_riscv/fnzhavedextbb6a692871d46f160484ca963a3fffd0.tex b/sail_latex_riscv/fnzhavedextbb6a692871d46f160484ca963a3fffd0.tex new file mode 100644 index 00000000..44c8c206 --- /dev/null +++ b/sail_latex_riscv/fnzhavedextbb6a692871d46f160484ca963a3fffd0.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhaveDExt]{haveDExt}#() -> bool = (misa.#\hyperref[sailRISCVzD]{D}#() == 0b1) & (mstatus.#\hyperref[sailRISCVzFS]{FS}#() != 0b00) diff --git a/sail_latex_riscv/fnzhavefext496ba4ad5d47088bd723ab96ed6356d0.tex b/sail_latex_riscv/fnzhavefext496ba4ad5d47088bd723ab96ed6356d0.tex new file mode 100644 index 00000000..d858338b --- /dev/null +++ b/sail_latex_riscv/fnzhavefext496ba4ad5d47088bd723ab96ed6356d0.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhaveFExt]{haveFExt}#() -> bool = (misa.#\hyperref[sailRISCVzF]{F}#() == 0b1) & (mstatus.#\hyperref[sailRISCVzFS]{FS}#() != 0b00) diff --git a/sail_latex_riscv/fnzhavemuldivee13dcf875cf3974336f980d6be89b2a.tex b/sail_latex_riscv/fnzhavemuldivee13dcf875cf3974336f980d6be89b2a.tex new file mode 100644 index 00000000..ef89d2ae --- /dev/null +++ b/sail_latex_riscv/fnzhavemuldivee13dcf875cf3974336f980d6be89b2a.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhaveMulDiv]{haveMulDiv}#() -> bool = misa.#\hyperref[sailRISCVzM]{M}#() == 0b1 diff --git a/sail_latex_riscv/fnzhavenext74060caf84942f39cfe17eb66bce56e4.tex b/sail_latex_riscv/fnzhavenext74060caf84942f39cfe17eb66bce56e4.tex new file mode 100644 index 00000000..4077d3f8 --- /dev/null +++ b/sail_latex_riscv/fnzhavenext74060caf84942f39cfe17eb66bce56e4.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() -> bool = misa.#\hyperref[sailRISCVzN]{N}#() == 0b1 diff --git a/sail_latex_riscv/fnzhavervcd1bab8584f566314057babec4a4bfcce.tex b/sail_latex_riscv/fnzhavervcd1bab8584f566314057babec4a4bfcce.tex new file mode 100644 index 00000000..4ba6e2fb --- /dev/null +++ b/sail_latex_riscv/fnzhavervcd1bab8584f566314057babec4a4bfcce.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhaveRVC]{haveRVC}#() -> bool = misa.#\hyperref[sailRISCVzC]{C}#() == 0b1 diff --git a/sail_latex_riscv/fnzhavesupmode3f08edf2b0386d18c650f34868f384db.tex b/sail_latex_riscv/fnzhavesupmode3f08edf2b0386d18c650f34868f384db.tex new file mode 100644 index 00000000..9b127483 --- /dev/null +++ b/sail_latex_riscv/fnzhavesupmode3f08edf2b0386d18c650f34868f384db.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() -> bool = misa.#\hyperref[sailRISCVzS]{S}#() == 0b1 diff --git a/sail_latex_riscv/fnzhaveusrmode2e520828ead805e9613cc1f88f964861.tex b/sail_latex_riscv/fnzhaveusrmode2e520828ead805e9613cc1f88f964861.tex new file mode 100644 index 00000000..37542302 --- /dev/null +++ b/sail_latex_riscv/fnzhaveusrmode2e520828ead805e9613cc1f88f964861.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() -> bool = misa.#\hyperref[sailRISCVzU]{U}#() == 0b1 diff --git a/sail_latex_riscv/fnzhavexcheri36112408abb05cceef19a84af1e5a22a.tex b/sail_latex_riscv/fnzhavexcheri36112408abb05cceef19a84af1e5a22a.tex new file mode 100644 index 00000000..46aa68c8 --- /dev/null +++ b/sail_latex_riscv/fnzhavexcheri36112408abb05cceef19a84af1e5a22a.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzhaveXcheri]{haveXcheri}# () -> bool = + /* This is a necessary but not sufficient condition, but should do for now. */ + misa.#\hyperref[sailRISCVzX]{X}#() == 0b1 diff --git a/sail_latex_riscv/fnzhex_bits_10_backwards3ea67a7e3b03c19fc3f62bce5d70adcf.tex b/sail_latex_riscv/fnzhex_bits_10_backwards3ea67a7e3b03c19fc3f62bce5d70adcf.tex new file mode 100644 index 00000000..4a7df09e --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_10_backwards3ea67a7e3b03c19fc3f62bce5d70adcf.tex @@ -0,0 +1,4 @@ +function hex_bits_10_backwards s = + match #\hyperref[sailRISCVzhexzybitszy10zymatcheszyprefix]{hex\_bits\_10\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_10_backwards_matches40e05acb0a138e49841d114ad4d36956.tex b/sail_latex_riscv/fnzhex_bits_10_backwards_matches40e05acb0a138e49841d114ad4d36956.tex new file mode 100644 index 00000000..01615f8b --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_10_backwards_matches40e05acb0a138e49841d114ad4d36956.tex @@ -0,0 +1,7 @@ +function hex_bits_10_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy10zymatcheszyprefix]{hex\_bits\_10\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_10_forwards_matches5805c03590a8c87ee15c304ac5e14038.tex b/sail_latex_riscv/fnzhex_bits_10_forwards_matches5805c03590a8c87ee15c304ac5e14038.tex new file mode 100644 index 00000000..bc4664e6 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_10_forwards_matches5805c03590a8c87ee15c304ac5e14038.tex @@ -0,0 +1 @@ +function hex_bits_10_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_11_backwards2baa8535235545b1d36570cd9bfa54d3.tex b/sail_latex_riscv/fnzhex_bits_11_backwards2baa8535235545b1d36570cd9bfa54d3.tex new file mode 100644 index 00000000..1df16607 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_11_backwards2baa8535235545b1d36570cd9bfa54d3.tex @@ -0,0 +1,4 @@ +function hex_bits_11_backwards s = + match #\hyperref[sailRISCVzhexzybitszy11zymatcheszyprefix]{hex\_bits\_11\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_11_backwards_matchesd1ccc1a72470b9d5d21bdc4ac13ff26b.tex b/sail_latex_riscv/fnzhex_bits_11_backwards_matchesd1ccc1a72470b9d5d21bdc4ac13ff26b.tex new file mode 100644 index 00000000..4609b047 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_11_backwards_matchesd1ccc1a72470b9d5d21bdc4ac13ff26b.tex @@ -0,0 +1,7 @@ +function hex_bits_11_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy11zymatcheszyprefix]{hex\_bits\_11\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_11_forwards_matchesc72e36f9e9259ad52cfd038ae9c0251f.tex b/sail_latex_riscv/fnzhex_bits_11_forwards_matchesc72e36f9e9259ad52cfd038ae9c0251f.tex new file mode 100644 index 00000000..c9faf425 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_11_forwards_matchesc72e36f9e9259ad52cfd038ae9c0251f.tex @@ -0,0 +1 @@ +function hex_bits_11_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_12_backwards3d80f810c3a0bfaf0d29151a18d72567.tex b/sail_latex_riscv/fnzhex_bits_12_backwards3d80f810c3a0bfaf0d29151a18d72567.tex new file mode 100644 index 00000000..1ce6e1dc --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_12_backwards3d80f810c3a0bfaf0d29151a18d72567.tex @@ -0,0 +1,4 @@ +function hex_bits_12_backwards s = + match #\hyperref[sailRISCVzhexzybitszy12zymatcheszyprefix]{hex\_bits\_12\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_12_backwards_matches6a7e459d92157f0ba9dee2e4c7899300.tex b/sail_latex_riscv/fnzhex_bits_12_backwards_matches6a7e459d92157f0ba9dee2e4c7899300.tex new file mode 100644 index 00000000..d57c7e1b --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_12_backwards_matches6a7e459d92157f0ba9dee2e4c7899300.tex @@ -0,0 +1,7 @@ +function hex_bits_12_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy12zymatcheszyprefix]{hex\_bits\_12\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_12_forwards_matches23afc09f193a32dea040a72b95ec91b2.tex b/sail_latex_riscv/fnzhex_bits_12_forwards_matches23afc09f193a32dea040a72b95ec91b2.tex new file mode 100644 index 00000000..0fefefe4 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_12_forwards_matches23afc09f193a32dea040a72b95ec91b2.tex @@ -0,0 +1 @@ +function hex_bits_12_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_12_matches_prefixc31c0737edfea85e61e2e4a0e4afa0dc.tex b/sail_latex_riscv/fnzhex_bits_12_matches_prefixc31c0737edfea85e61e2e4a0e4afa0dc.tex new file mode 100644 index 00000000..f9de37b7 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_12_matches_prefixc31c0737edfea85e61e2e4a0e4afa0dc.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzhexzybitszy12zymatcheszyprefix]{hex\_bits\_12\_matches\_prefix}# (s : string) -> #\hyperref[sailRISCVzoption]{option}#((#\hyperref[sailRISCVzbits]{bits}#(12), nat)) = #\hyperref[sailRISCVzNone]{None}#() diff --git a/sail_latex_riscv/fnzhex_bits_13_backwards75db4a8adaa37e62b3ea51d810cbbf3b.tex b/sail_latex_riscv/fnzhex_bits_13_backwards75db4a8adaa37e62b3ea51d810cbbf3b.tex new file mode 100644 index 00000000..9ef93ff3 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_13_backwards75db4a8adaa37e62b3ea51d810cbbf3b.tex @@ -0,0 +1,4 @@ +function hex_bits_13_backwards s = + match #\hyperref[sailRISCVzhexzybitszy13zymatcheszyprefix]{hex\_bits\_13\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_13_backwards_matches3380960c8e44f21f0eeafd0244600ee6.tex b/sail_latex_riscv/fnzhex_bits_13_backwards_matches3380960c8e44f21f0eeafd0244600ee6.tex new file mode 100644 index 00000000..bf08f998 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_13_backwards_matches3380960c8e44f21f0eeafd0244600ee6.tex @@ -0,0 +1,7 @@ +function hex_bits_13_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy13zymatcheszyprefix]{hex\_bits\_13\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_13_forwards_matches24cf47063279787f52ede006100876ff.tex b/sail_latex_riscv/fnzhex_bits_13_forwards_matches24cf47063279787f52ede006100876ff.tex new file mode 100644 index 00000000..8735399a --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_13_forwards_matches24cf47063279787f52ede006100876ff.tex @@ -0,0 +1 @@ +function hex_bits_13_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_14_backwards825f2ad69791fa9a1bb2792ac85efc54.tex b/sail_latex_riscv/fnzhex_bits_14_backwards825f2ad69791fa9a1bb2792ac85efc54.tex new file mode 100644 index 00000000..3fb63a23 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_14_backwards825f2ad69791fa9a1bb2792ac85efc54.tex @@ -0,0 +1,4 @@ +function hex_bits_14_backwards s = + match #\hyperref[sailRISCVzhexzybitszy14zymatcheszyprefix]{hex\_bits\_14\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_14_backwards_matches7a9acb89282cc5c0ad18d89d22bf3cfa.tex b/sail_latex_riscv/fnzhex_bits_14_backwards_matches7a9acb89282cc5c0ad18d89d22bf3cfa.tex new file mode 100644 index 00000000..9af98529 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_14_backwards_matches7a9acb89282cc5c0ad18d89d22bf3cfa.tex @@ -0,0 +1,7 @@ +function hex_bits_14_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy14zymatcheszyprefix]{hex\_bits\_14\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_14_forwards_matches229689dc85657ccebc6a0143fb21144e.tex b/sail_latex_riscv/fnzhex_bits_14_forwards_matches229689dc85657ccebc6a0143fb21144e.tex new file mode 100644 index 00000000..9dc1ec05 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_14_forwards_matches229689dc85657ccebc6a0143fb21144e.tex @@ -0,0 +1 @@ +function hex_bits_14_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_15_backwards_matchesc6cd9235f40d6808371474280c964ff1.tex b/sail_latex_riscv/fnzhex_bits_15_backwards_matchesc6cd9235f40d6808371474280c964ff1.tex new file mode 100644 index 00000000..532cc7e7 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_15_backwards_matchesc6cd9235f40d6808371474280c964ff1.tex @@ -0,0 +1,7 @@ +function hex_bits_15_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy15zymatcheszyprefix]{hex\_bits\_15\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_15_backwardscb4ce484e79dc8d005cf2bda729e7867.tex b/sail_latex_riscv/fnzhex_bits_15_backwardscb4ce484e79dc8d005cf2bda729e7867.tex new file mode 100644 index 00000000..e4744314 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_15_backwardscb4ce484e79dc8d005cf2bda729e7867.tex @@ -0,0 +1,4 @@ +function hex_bits_15_backwards s = + match #\hyperref[sailRISCVzhexzybitszy15zymatcheszyprefix]{hex\_bits\_15\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_15_forwards_matches923e93be7d0b466ae08582f59a3c9529.tex b/sail_latex_riscv/fnzhex_bits_15_forwards_matches923e93be7d0b466ae08582f59a3c9529.tex new file mode 100644 index 00000000..d03c7be4 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_15_forwards_matches923e93be7d0b466ae08582f59a3c9529.tex @@ -0,0 +1 @@ +function hex_bits_15_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_16_backwards8afef1c1c4af4f381f60fc4dc7267c9c.tex b/sail_latex_riscv/fnzhex_bits_16_backwards8afef1c1c4af4f381f60fc4dc7267c9c.tex new file mode 100644 index 00000000..c180ed6b --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_16_backwards8afef1c1c4af4f381f60fc4dc7267c9c.tex @@ -0,0 +1,4 @@ +function hex_bits_16_backwards s = + match #\hyperref[sailRISCVzhexzybitszy16zymatcheszyprefix]{hex\_bits\_16\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_16_backwards_matches8ff37bbe35e588c9d66f041b5b32d8e0.tex b/sail_latex_riscv/fnzhex_bits_16_backwards_matches8ff37bbe35e588c9d66f041b5b32d8e0.tex new file mode 100644 index 00000000..e7618eba --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_16_backwards_matches8ff37bbe35e588c9d66f041b5b32d8e0.tex @@ -0,0 +1,7 @@ +function hex_bits_16_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy16zymatcheszyprefix]{hex\_bits\_16\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_16_forwards_matches99127000f54090aaa9f0aeb2c20f4685.tex b/sail_latex_riscv/fnzhex_bits_16_forwards_matches99127000f54090aaa9f0aeb2c20f4685.tex new file mode 100644 index 00000000..aef597bc --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_16_forwards_matches99127000f54090aaa9f0aeb2c20f4685.tex @@ -0,0 +1 @@ +function hex_bits_16_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_17_backwards96076e6b0ee1d8c887acfae20a696145.tex b/sail_latex_riscv/fnzhex_bits_17_backwards96076e6b0ee1d8c887acfae20a696145.tex new file mode 100644 index 00000000..514030a9 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_17_backwards96076e6b0ee1d8c887acfae20a696145.tex @@ -0,0 +1,4 @@ +function hex_bits_17_backwards s = + match #\hyperref[sailRISCVzhexzybitszy17zymatcheszyprefix]{hex\_bits\_17\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_17_backwards_matchesd594e6fb2cf338d85aa8e3a859821359.tex b/sail_latex_riscv/fnzhex_bits_17_backwards_matchesd594e6fb2cf338d85aa8e3a859821359.tex new file mode 100644 index 00000000..24286b9d --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_17_backwards_matchesd594e6fb2cf338d85aa8e3a859821359.tex @@ -0,0 +1,7 @@ +function hex_bits_17_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy17zymatcheszyprefix]{hex\_bits\_17\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_17_forwards_matches45df8bfd52709ac4d9906f538498742e.tex b/sail_latex_riscv/fnzhex_bits_17_forwards_matches45df8bfd52709ac4d9906f538498742e.tex new file mode 100644 index 00000000..e1c2cb5f --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_17_forwards_matches45df8bfd52709ac4d9906f538498742e.tex @@ -0,0 +1 @@ +function hex_bits_17_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_18_backwards0500c1a0187a21072c3255f60243909f.tex b/sail_latex_riscv/fnzhex_bits_18_backwards0500c1a0187a21072c3255f60243909f.tex new file mode 100644 index 00000000..4f08b0e6 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_18_backwards0500c1a0187a21072c3255f60243909f.tex @@ -0,0 +1,4 @@ +function hex_bits_18_backwards s = + match #\hyperref[sailRISCVzhexzybitszy18zymatcheszyprefix]{hex\_bits\_18\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_18_backwards_matches72b528c9dd8e982607b88bd8ab46a37d.tex b/sail_latex_riscv/fnzhex_bits_18_backwards_matches72b528c9dd8e982607b88bd8ab46a37d.tex new file mode 100644 index 00000000..cce36c29 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_18_backwards_matches72b528c9dd8e982607b88bd8ab46a37d.tex @@ -0,0 +1,7 @@ +function hex_bits_18_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy18zymatcheszyprefix]{hex\_bits\_18\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_18_forwards_matches6e035e739a1d5414f87357bc391d08b3.tex b/sail_latex_riscv/fnzhex_bits_18_forwards_matches6e035e739a1d5414f87357bc391d08b3.tex new file mode 100644 index 00000000..996a5030 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_18_forwards_matches6e035e739a1d5414f87357bc391d08b3.tex @@ -0,0 +1 @@ +function hex_bits_18_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_19_backwards8a1ab4ffc6b6e5e3c0cf6702ec74b710.tex b/sail_latex_riscv/fnzhex_bits_19_backwards8a1ab4ffc6b6e5e3c0cf6702ec74b710.tex new file mode 100644 index 00000000..24e881fa --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_19_backwards8a1ab4ffc6b6e5e3c0cf6702ec74b710.tex @@ -0,0 +1,4 @@ +function hex_bits_19_backwards s = + match #\hyperref[sailRISCVzhexzybitszy19zymatcheszyprefix]{hex\_bits\_19\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_19_backwards_matchesd823f57016d205b9df109966ee967db9.tex b/sail_latex_riscv/fnzhex_bits_19_backwards_matchesd823f57016d205b9df109966ee967db9.tex new file mode 100644 index 00000000..bf93d004 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_19_backwards_matchesd823f57016d205b9df109966ee967db9.tex @@ -0,0 +1,7 @@ +function hex_bits_19_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy19zymatcheszyprefix]{hex\_bits\_19\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_19_forwards_matches07c7d804aca651680480475ad9d45b66.tex b/sail_latex_riscv/fnzhex_bits_19_forwards_matches07c7d804aca651680480475ad9d45b66.tex new file mode 100644 index 00000000..5c809433 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_19_forwards_matches07c7d804aca651680480475ad9d45b66.tex @@ -0,0 +1 @@ +function hex_bits_19_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_1_backwards90e5440bb0c40b9363498a8d972dba41.tex b/sail_latex_riscv/fnzhex_bits_1_backwards90e5440bb0c40b9363498a8d972dba41.tex new file mode 100644 index 00000000..47ffcd65 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_1_backwards90e5440bb0c40b9363498a8d972dba41.tex @@ -0,0 +1,4 @@ +function hex_bits_1_backwards s = + match #\hyperref[sailRISCVzhexzybitszy1zymatcheszyprefix]{hex\_bits\_1\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_1_backwards_matches3d78f15da2768104290b952c286f2f91.tex b/sail_latex_riscv/fnzhex_bits_1_backwards_matches3d78f15da2768104290b952c286f2f91.tex new file mode 100644 index 00000000..2e2f0afe --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_1_backwards_matches3d78f15da2768104290b952c286f2f91.tex @@ -0,0 +1,7 @@ +function hex_bits_1_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy1zymatcheszyprefix]{hex\_bits\_1\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_1_forwards_matches95bbf636d6fecebea6adab4fb1b42ac0.tex b/sail_latex_riscv/fnzhex_bits_1_forwards_matches95bbf636d6fecebea6adab4fb1b42ac0.tex new file mode 100644 index 00000000..4741d3eb --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_1_forwards_matches95bbf636d6fecebea6adab4fb1b42ac0.tex @@ -0,0 +1 @@ +function hex_bits_1_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_20_backwards_matches8c546ae28d487f510dca7fe30ea629c5.tex b/sail_latex_riscv/fnzhex_bits_20_backwards_matches8c546ae28d487f510dca7fe30ea629c5.tex new file mode 100644 index 00000000..db254fe1 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_20_backwards_matches8c546ae28d487f510dca7fe30ea629c5.tex @@ -0,0 +1,7 @@ +function hex_bits_20_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy20zymatcheszyprefix]{hex\_bits\_20\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_20_backwardsed333b625b69d435d8e8df1b980d11ef.tex b/sail_latex_riscv/fnzhex_bits_20_backwardsed333b625b69d435d8e8df1b980d11ef.tex new file mode 100644 index 00000000..2b46fa33 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_20_backwardsed333b625b69d435d8e8df1b980d11ef.tex @@ -0,0 +1,4 @@ +function hex_bits_20_backwards s = + match #\hyperref[sailRISCVzhexzybitszy20zymatcheszyprefix]{hex\_bits\_20\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_20_forwards_matchesde8955f96663b48788095ef74c50f0aa.tex b/sail_latex_riscv/fnzhex_bits_20_forwards_matchesde8955f96663b48788095ef74c50f0aa.tex new file mode 100644 index 00000000..08b7b7dc --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_20_forwards_matchesde8955f96663b48788095ef74c50f0aa.tex @@ -0,0 +1 @@ +function hex_bits_20_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_21_backwards_matches477a84c0bff49ab6511438197e40d9c3.tex b/sail_latex_riscv/fnzhex_bits_21_backwards_matches477a84c0bff49ab6511438197e40d9c3.tex new file mode 100644 index 00000000..f55e8e3f --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_21_backwards_matches477a84c0bff49ab6511438197e40d9c3.tex @@ -0,0 +1,7 @@ +function hex_bits_21_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy21zymatcheszyprefix]{hex\_bits\_21\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_21_backwardsc44f7bb35fd47e4506558a2d7d995f8e.tex b/sail_latex_riscv/fnzhex_bits_21_backwardsc44f7bb35fd47e4506558a2d7d995f8e.tex new file mode 100644 index 00000000..8711bc68 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_21_backwardsc44f7bb35fd47e4506558a2d7d995f8e.tex @@ -0,0 +1,4 @@ +function hex_bits_21_backwards s = + match #\hyperref[sailRISCVzhexzybitszy21zymatcheszyprefix]{hex\_bits\_21\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_21_forwards_matches05f5fa78d5ad49b7efae27025b546cb7.tex b/sail_latex_riscv/fnzhex_bits_21_forwards_matches05f5fa78d5ad49b7efae27025b546cb7.tex new file mode 100644 index 00000000..34e9eb93 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_21_forwards_matches05f5fa78d5ad49b7efae27025b546cb7.tex @@ -0,0 +1 @@ +function hex_bits_21_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_22_backwards_matchesfd56758d4cd0fd6150ee51afa372c83b.tex b/sail_latex_riscv/fnzhex_bits_22_backwards_matchesfd56758d4cd0fd6150ee51afa372c83b.tex new file mode 100644 index 00000000..ea0e1ea2 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_22_backwards_matchesfd56758d4cd0fd6150ee51afa372c83b.tex @@ -0,0 +1,7 @@ +function hex_bits_22_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy22zymatcheszyprefix]{hex\_bits\_22\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_22_backwardsfbed1dd3d215529ff44a9e8165218968.tex b/sail_latex_riscv/fnzhex_bits_22_backwardsfbed1dd3d215529ff44a9e8165218968.tex new file mode 100644 index 00000000..8143f3e2 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_22_backwardsfbed1dd3d215529ff44a9e8165218968.tex @@ -0,0 +1,4 @@ +function hex_bits_22_backwards s = + match #\hyperref[sailRISCVzhexzybitszy22zymatcheszyprefix]{hex\_bits\_22\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_22_forwards_matches4fe97899c8181992923cd1daaa36d526.tex b/sail_latex_riscv/fnzhex_bits_22_forwards_matches4fe97899c8181992923cd1daaa36d526.tex new file mode 100644 index 00000000..72c8c6f8 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_22_forwards_matches4fe97899c8181992923cd1daaa36d526.tex @@ -0,0 +1 @@ +function hex_bits_22_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_23_backwards2183795dfc2ff2f588be2709c2cd7639.tex b/sail_latex_riscv/fnzhex_bits_23_backwards2183795dfc2ff2f588be2709c2cd7639.tex new file mode 100644 index 00000000..79c4c6bf --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_23_backwards2183795dfc2ff2f588be2709c2cd7639.tex @@ -0,0 +1,4 @@ +function hex_bits_23_backwards s = + match #\hyperref[sailRISCVzhexzybitszy23zymatcheszyprefix]{hex\_bits\_23\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_23_backwards_matchesa97370178cb502dd696426e4a347c318.tex b/sail_latex_riscv/fnzhex_bits_23_backwards_matchesa97370178cb502dd696426e4a347c318.tex new file mode 100644 index 00000000..53470481 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_23_backwards_matchesa97370178cb502dd696426e4a347c318.tex @@ -0,0 +1,7 @@ +function hex_bits_23_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy23zymatcheszyprefix]{hex\_bits\_23\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_23_forwards_matchesb58b33da7b8d1a86392eabd6cc87b2c3.tex b/sail_latex_riscv/fnzhex_bits_23_forwards_matchesb58b33da7b8d1a86392eabd6cc87b2c3.tex new file mode 100644 index 00000000..36ab17d9 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_23_forwards_matchesb58b33da7b8d1a86392eabd6cc87b2c3.tex @@ -0,0 +1 @@ +function hex_bits_23_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_24_backwards_matchesb2a483aa8b7cae87c37d98bc8b2a7345.tex b/sail_latex_riscv/fnzhex_bits_24_backwards_matchesb2a483aa8b7cae87c37d98bc8b2a7345.tex new file mode 100644 index 00000000..0eff3f43 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_24_backwards_matchesb2a483aa8b7cae87c37d98bc8b2a7345.tex @@ -0,0 +1,7 @@ +function hex_bits_24_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy24zymatcheszyprefix]{hex\_bits\_24\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_24_backwardsa48c754c7049ebcb72d1fbba8bcfaadf.tex b/sail_latex_riscv/fnzhex_bits_24_backwardsa48c754c7049ebcb72d1fbba8bcfaadf.tex new file mode 100644 index 00000000..2688e178 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_24_backwardsa48c754c7049ebcb72d1fbba8bcfaadf.tex @@ -0,0 +1,4 @@ +function hex_bits_24_backwards s = + match #\hyperref[sailRISCVzhexzybitszy24zymatcheszyprefix]{hex\_bits\_24\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_24_forwards_matchesf4dd0da48edd6a31433b0bae1bedc1f5.tex b/sail_latex_riscv/fnzhex_bits_24_forwards_matchesf4dd0da48edd6a31433b0bae1bedc1f5.tex new file mode 100644 index 00000000..3380074f --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_24_forwards_matchesf4dd0da48edd6a31433b0bae1bedc1f5.tex @@ -0,0 +1 @@ +function hex_bits_24_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_25_backwards_matchese97e136616a70048191383b2a45471f6.tex b/sail_latex_riscv/fnzhex_bits_25_backwards_matchese97e136616a70048191383b2a45471f6.tex new file mode 100644 index 00000000..c1ac0bf6 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_25_backwards_matchese97e136616a70048191383b2a45471f6.tex @@ -0,0 +1,7 @@ +function hex_bits_25_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy25zymatcheszyprefix]{hex\_bits\_25\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_25_backwardsb4f6ac6cc03e034620b7a4a11a89c5fc.tex b/sail_latex_riscv/fnzhex_bits_25_backwardsb4f6ac6cc03e034620b7a4a11a89c5fc.tex new file mode 100644 index 00000000..df5e43cb --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_25_backwardsb4f6ac6cc03e034620b7a4a11a89c5fc.tex @@ -0,0 +1,4 @@ +function hex_bits_25_backwards s = + match #\hyperref[sailRISCVzhexzybitszy25zymatcheszyprefix]{hex\_bits\_25\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_25_forwards_matches6d8831afa1ed150c2dca6afcd8d46fd1.tex b/sail_latex_riscv/fnzhex_bits_25_forwards_matches6d8831afa1ed150c2dca6afcd8d46fd1.tex new file mode 100644 index 00000000..9caa5153 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_25_forwards_matches6d8831afa1ed150c2dca6afcd8d46fd1.tex @@ -0,0 +1 @@ +function hex_bits_25_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_26_backwards_matches0ea73e31736f776e20958f45ec3e81bd.tex b/sail_latex_riscv/fnzhex_bits_26_backwards_matches0ea73e31736f776e20958f45ec3e81bd.tex new file mode 100644 index 00000000..c14513fa --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_26_backwards_matches0ea73e31736f776e20958f45ec3e81bd.tex @@ -0,0 +1,7 @@ +function hex_bits_26_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy26zymatcheszyprefix]{hex\_bits\_26\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_26_backwardsca9980b4fb1beb5e20216094b1b6b352.tex b/sail_latex_riscv/fnzhex_bits_26_backwardsca9980b4fb1beb5e20216094b1b6b352.tex new file mode 100644 index 00000000..03f37ae8 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_26_backwardsca9980b4fb1beb5e20216094b1b6b352.tex @@ -0,0 +1,4 @@ +function hex_bits_26_backwards s = + match #\hyperref[sailRISCVzhexzybitszy26zymatcheszyprefix]{hex\_bits\_26\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_26_forwards_matchesec5940b6c813530a4c8c509af6c000b6.tex b/sail_latex_riscv/fnzhex_bits_26_forwards_matchesec5940b6c813530a4c8c509af6c000b6.tex new file mode 100644 index 00000000..5f58edcf --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_26_forwards_matchesec5940b6c813530a4c8c509af6c000b6.tex @@ -0,0 +1 @@ +function hex_bits_26_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_27_backwards4d49d22a17608696fe779e708d0d5091.tex b/sail_latex_riscv/fnzhex_bits_27_backwards4d49d22a17608696fe779e708d0d5091.tex new file mode 100644 index 00000000..24d7d8c5 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_27_backwards4d49d22a17608696fe779e708d0d5091.tex @@ -0,0 +1,4 @@ +function hex_bits_27_backwards s = + match #\hyperref[sailRISCVzhexzybitszy27zymatcheszyprefix]{hex\_bits\_27\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_27_backwards_matchesc36973ea671b22434d73ad552c3b36f1.tex b/sail_latex_riscv/fnzhex_bits_27_backwards_matchesc36973ea671b22434d73ad552c3b36f1.tex new file mode 100644 index 00000000..4a698dc9 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_27_backwards_matchesc36973ea671b22434d73ad552c3b36f1.tex @@ -0,0 +1,7 @@ +function hex_bits_27_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy27zymatcheszyprefix]{hex\_bits\_27\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_27_forwards_matches6867770d92d07d048cf22050458e9a6f.tex b/sail_latex_riscv/fnzhex_bits_27_forwards_matches6867770d92d07d048cf22050458e9a6f.tex new file mode 100644 index 00000000..880fb65e --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_27_forwards_matches6867770d92d07d048cf22050458e9a6f.tex @@ -0,0 +1 @@ +function hex_bits_27_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_28_backwards2c2d2daf166e3a6a7935d895391a113e.tex b/sail_latex_riscv/fnzhex_bits_28_backwards2c2d2daf166e3a6a7935d895391a113e.tex new file mode 100644 index 00000000..cabd9438 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_28_backwards2c2d2daf166e3a6a7935d895391a113e.tex @@ -0,0 +1,4 @@ +function hex_bits_28_backwards s = + match #\hyperref[sailRISCVzhexzybitszy28zymatcheszyprefix]{hex\_bits\_28\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_28_backwards_matches0baec25715c212015f55f72f54702da4.tex b/sail_latex_riscv/fnzhex_bits_28_backwards_matches0baec25715c212015f55f72f54702da4.tex new file mode 100644 index 00000000..0291c81f --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_28_backwards_matches0baec25715c212015f55f72f54702da4.tex @@ -0,0 +1,7 @@ +function hex_bits_28_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy28zymatcheszyprefix]{hex\_bits\_28\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_28_forwards_matchesc4d71e8f4caf976479bf0fd50de2a1f7.tex b/sail_latex_riscv/fnzhex_bits_28_forwards_matchesc4d71e8f4caf976479bf0fd50de2a1f7.tex new file mode 100644 index 00000000..909064ce --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_28_forwards_matchesc4d71e8f4caf976479bf0fd50de2a1f7.tex @@ -0,0 +1 @@ +function hex_bits_28_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_29_backwards388cf5f0a97b7aadfda6550d7d52cc35.tex b/sail_latex_riscv/fnzhex_bits_29_backwards388cf5f0a97b7aadfda6550d7d52cc35.tex new file mode 100644 index 00000000..080f8ba8 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_29_backwards388cf5f0a97b7aadfda6550d7d52cc35.tex @@ -0,0 +1,4 @@ +function hex_bits_29_backwards s = + match #\hyperref[sailRISCVzhexzybitszy29zymatcheszyprefix]{hex\_bits\_29\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_29_backwards_matchese61c62311ca330ee022b0ce689f2bf7a.tex b/sail_latex_riscv/fnzhex_bits_29_backwards_matchese61c62311ca330ee022b0ce689f2bf7a.tex new file mode 100644 index 00000000..4a367be7 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_29_backwards_matchese61c62311ca330ee022b0ce689f2bf7a.tex @@ -0,0 +1,7 @@ +function hex_bits_29_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy29zymatcheszyprefix]{hex\_bits\_29\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_29_forwards_matchesed84d3ffca269bb316dc98b23b11184a.tex b/sail_latex_riscv/fnzhex_bits_29_forwards_matchesed84d3ffca269bb316dc98b23b11184a.tex new file mode 100644 index 00000000..574f68e5 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_29_forwards_matchesed84d3ffca269bb316dc98b23b11184a.tex @@ -0,0 +1 @@ +function hex_bits_29_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_2_backwards18d79d6a578203ebce0993a1703a4245.tex b/sail_latex_riscv/fnzhex_bits_2_backwards18d79d6a578203ebce0993a1703a4245.tex new file mode 100644 index 00000000..21c15c34 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_2_backwards18d79d6a578203ebce0993a1703a4245.tex @@ -0,0 +1,4 @@ +function hex_bits_2_backwards s = + match #\hyperref[sailRISCVzhexzybitszy2zymatcheszyprefix]{hex\_bits\_2\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_2_backwards_matches823cb41992ed3a26886d992e75e86734.tex b/sail_latex_riscv/fnzhex_bits_2_backwards_matches823cb41992ed3a26886d992e75e86734.tex new file mode 100644 index 00000000..81d24954 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_2_backwards_matches823cb41992ed3a26886d992e75e86734.tex @@ -0,0 +1,7 @@ +function hex_bits_2_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy2zymatcheszyprefix]{hex\_bits\_2\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_2_forwards_matches7ab140c97f69659d3ab1d910b07425fb.tex b/sail_latex_riscv/fnzhex_bits_2_forwards_matches7ab140c97f69659d3ab1d910b07425fb.tex new file mode 100644 index 00000000..4ac01f7a --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_2_forwards_matches7ab140c97f69659d3ab1d910b07425fb.tex @@ -0,0 +1 @@ +function hex_bits_2_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_30_backwards3391751afa83c025b48e297fc4113f6e.tex b/sail_latex_riscv/fnzhex_bits_30_backwards3391751afa83c025b48e297fc4113f6e.tex new file mode 100644 index 00000000..8364e04e --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_30_backwards3391751afa83c025b48e297fc4113f6e.tex @@ -0,0 +1,4 @@ +function hex_bits_30_backwards s = + match #\hyperref[sailRISCVzhexzybitszy30zymatcheszyprefix]{hex\_bits\_30\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_30_backwards_matches55c635ce0a1a3c012b3119662b49178c.tex b/sail_latex_riscv/fnzhex_bits_30_backwards_matches55c635ce0a1a3c012b3119662b49178c.tex new file mode 100644 index 00000000..07c3b242 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_30_backwards_matches55c635ce0a1a3c012b3119662b49178c.tex @@ -0,0 +1,7 @@ +function hex_bits_30_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy30zymatcheszyprefix]{hex\_bits\_30\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_30_forwards_matches3630c22b1e1e03c4f0e0de4c42a765db.tex b/sail_latex_riscv/fnzhex_bits_30_forwards_matches3630c22b1e1e03c4f0e0de4c42a765db.tex new file mode 100644 index 00000000..26991406 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_30_forwards_matches3630c22b1e1e03c4f0e0de4c42a765db.tex @@ -0,0 +1 @@ +function hex_bits_30_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_31_backwards36aadfc7c167e0b19e4147eb55e51cba.tex b/sail_latex_riscv/fnzhex_bits_31_backwards36aadfc7c167e0b19e4147eb55e51cba.tex new file mode 100644 index 00000000..4b44d7f8 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_31_backwards36aadfc7c167e0b19e4147eb55e51cba.tex @@ -0,0 +1,4 @@ +function hex_bits_31_backwards s = + match #\hyperref[sailRISCVzhexzybitszy31zymatcheszyprefix]{hex\_bits\_31\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_31_backwards_matches68cc0d3844c92f7e0ebe6bcaa48a03ca.tex b/sail_latex_riscv/fnzhex_bits_31_backwards_matches68cc0d3844c92f7e0ebe6bcaa48a03ca.tex new file mode 100644 index 00000000..c5b1b87b --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_31_backwards_matches68cc0d3844c92f7e0ebe6bcaa48a03ca.tex @@ -0,0 +1,7 @@ +function hex_bits_31_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy31zymatcheszyprefix]{hex\_bits\_31\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_31_forwards_matches830a8b6e6851a2528701adaae04355bf.tex b/sail_latex_riscv/fnzhex_bits_31_forwards_matches830a8b6e6851a2528701adaae04355bf.tex new file mode 100644 index 00000000..071a0de2 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_31_forwards_matches830a8b6e6851a2528701adaae04355bf.tex @@ -0,0 +1 @@ +function hex_bits_31_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_32_backwards_matchesc5862ab9ce54a89fb3d05c1a1e742ba8.tex b/sail_latex_riscv/fnzhex_bits_32_backwards_matchesc5862ab9ce54a89fb3d05c1a1e742ba8.tex new file mode 100644 index 00000000..7d22a7ea --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_32_backwards_matchesc5862ab9ce54a89fb3d05c1a1e742ba8.tex @@ -0,0 +1,7 @@ +function hex_bits_32_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy32zymatcheszyprefix]{hex\_bits\_32\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_32_backwardse98f8968c64c820f7d6ab0adad242eea.tex b/sail_latex_riscv/fnzhex_bits_32_backwardse98f8968c64c820f7d6ab0adad242eea.tex new file mode 100644 index 00000000..69586515 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_32_backwardse98f8968c64c820f7d6ab0adad242eea.tex @@ -0,0 +1,4 @@ +function hex_bits_32_backwards s = + match #\hyperref[sailRISCVzhexzybitszy32zymatcheszyprefix]{hex\_bits\_32\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_32_forwards_matches6b2dec12f42cfb341d5a812b57201577.tex b/sail_latex_riscv/fnzhex_bits_32_forwards_matches6b2dec12f42cfb341d5a812b57201577.tex new file mode 100644 index 00000000..8a018a0d --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_32_forwards_matches6b2dec12f42cfb341d5a812b57201577.tex @@ -0,0 +1 @@ +function hex_bits_32_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_33_backwards_matchesa0efa80a7912e2204c7a08b11236c3ea.tex b/sail_latex_riscv/fnzhex_bits_33_backwards_matchesa0efa80a7912e2204c7a08b11236c3ea.tex new file mode 100644 index 00000000..8779a4c6 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_33_backwards_matchesa0efa80a7912e2204c7a08b11236c3ea.tex @@ -0,0 +1,7 @@ +function hex_bits_33_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy33zymatcheszyprefix]{hex\_bits\_33\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_33_backwardscc814f008a05b1129f62004b8fa5c8e5.tex b/sail_latex_riscv/fnzhex_bits_33_backwardscc814f008a05b1129f62004b8fa5c8e5.tex new file mode 100644 index 00000000..1d61cba7 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_33_backwardscc814f008a05b1129f62004b8fa5c8e5.tex @@ -0,0 +1,4 @@ +function hex_bits_33_backwards s = + match #\hyperref[sailRISCVzhexzybitszy33zymatcheszyprefix]{hex\_bits\_33\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_33_forwards_matches4b4b2c7ba9f6a4dd54548314428e59f6.tex b/sail_latex_riscv/fnzhex_bits_33_forwards_matches4b4b2c7ba9f6a4dd54548314428e59f6.tex new file mode 100644 index 00000000..56b61d66 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_33_forwards_matches4b4b2c7ba9f6a4dd54548314428e59f6.tex @@ -0,0 +1 @@ +function hex_bits_33_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_3_backwards_matches952f17dffac18d98619e00bc97a700fc.tex b/sail_latex_riscv/fnzhex_bits_3_backwards_matches952f17dffac18d98619e00bc97a700fc.tex new file mode 100644 index 00000000..cc5d0cdc --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_3_backwards_matches952f17dffac18d98619e00bc97a700fc.tex @@ -0,0 +1,7 @@ +function hex_bits_3_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy3zymatcheszyprefix]{hex\_bits\_3\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_3_backwardsf853f7ad9bfed642772b10dafd6910d1.tex b/sail_latex_riscv/fnzhex_bits_3_backwardsf853f7ad9bfed642772b10dafd6910d1.tex new file mode 100644 index 00000000..8bb8a141 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_3_backwardsf853f7ad9bfed642772b10dafd6910d1.tex @@ -0,0 +1,4 @@ +function hex_bits_3_backwards s = + match #\hyperref[sailRISCVzhexzybitszy3zymatcheszyprefix]{hex\_bits\_3\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_3_forwards_matchese79d3588a48711c3aab539462e1e83ad.tex b/sail_latex_riscv/fnzhex_bits_3_forwards_matchese79d3588a48711c3aab539462e1e83ad.tex new file mode 100644 index 00000000..b1eaf77e --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_3_forwards_matchese79d3588a48711c3aab539462e1e83ad.tex @@ -0,0 +1 @@ +function hex_bits_3_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_48_backwards57285976d132280592935deb245ad737.tex b/sail_latex_riscv/fnzhex_bits_48_backwards57285976d132280592935deb245ad737.tex new file mode 100644 index 00000000..e9699ef0 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_48_backwards57285976d132280592935deb245ad737.tex @@ -0,0 +1,4 @@ +function hex_bits_48_backwards s = + match #\hyperref[sailRISCVzhexzybitszy48zymatcheszyprefix]{hex\_bits\_48\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_48_backwards_matches3765c7a672ed4a4188e6adcad2e1769c.tex b/sail_latex_riscv/fnzhex_bits_48_backwards_matches3765c7a672ed4a4188e6adcad2e1769c.tex new file mode 100644 index 00000000..369f6d01 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_48_backwards_matches3765c7a672ed4a4188e6adcad2e1769c.tex @@ -0,0 +1,7 @@ +function hex_bits_48_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy48zymatcheszyprefix]{hex\_bits\_48\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_48_forwards_matchesf2b53432d5d61a0c6dbc5e249b95d790.tex b/sail_latex_riscv/fnzhex_bits_48_forwards_matchesf2b53432d5d61a0c6dbc5e249b95d790.tex new file mode 100644 index 00000000..fb713927 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_48_forwards_matchesf2b53432d5d61a0c6dbc5e249b95d790.tex @@ -0,0 +1 @@ +function hex_bits_48_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_4_backwards_matches798cb282812c7bc9b083a091bb0b23ca.tex b/sail_latex_riscv/fnzhex_bits_4_backwards_matches798cb282812c7bc9b083a091bb0b23ca.tex new file mode 100644 index 00000000..9316e9b7 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_4_backwards_matches798cb282812c7bc9b083a091bb0b23ca.tex @@ -0,0 +1,7 @@ +function hex_bits_4_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy4zymatcheszyprefix]{hex\_bits\_4\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_4_backwardsf22b435ac96c309eec82519c5c010323.tex b/sail_latex_riscv/fnzhex_bits_4_backwardsf22b435ac96c309eec82519c5c010323.tex new file mode 100644 index 00000000..d9cb25c1 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_4_backwardsf22b435ac96c309eec82519c5c010323.tex @@ -0,0 +1,4 @@ +function hex_bits_4_backwards s = + match #\hyperref[sailRISCVzhexzybitszy4zymatcheszyprefix]{hex\_bits\_4\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_4_forwards_matchesc9b2af172c13a489fa870acdd673758a.tex b/sail_latex_riscv/fnzhex_bits_4_forwards_matchesc9b2af172c13a489fa870acdd673758a.tex new file mode 100644 index 00000000..a126ac67 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_4_forwards_matchesc9b2af172c13a489fa870acdd673758a.tex @@ -0,0 +1 @@ +function hex_bits_4_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_5_backwards79c47a53cbcc5ca893c439296fe2bd3f.tex b/sail_latex_riscv/fnzhex_bits_5_backwards79c47a53cbcc5ca893c439296fe2bd3f.tex new file mode 100644 index 00000000..7e849a39 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_5_backwards79c47a53cbcc5ca893c439296fe2bd3f.tex @@ -0,0 +1,4 @@ +function hex_bits_5_backwards s = + match #\hyperref[sailRISCVzhexzybitszy5zymatcheszyprefix]{hex\_bits\_5\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_5_backwards_matchesf675096dc18dd61104842d90f51800a8.tex b/sail_latex_riscv/fnzhex_bits_5_backwards_matchesf675096dc18dd61104842d90f51800a8.tex new file mode 100644 index 00000000..d1b14ca4 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_5_backwards_matchesf675096dc18dd61104842d90f51800a8.tex @@ -0,0 +1,7 @@ +function hex_bits_5_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy5zymatcheszyprefix]{hex\_bits\_5\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_5_forwards_matches3e31f036e77b0ee1a3e8312b0067959b.tex b/sail_latex_riscv/fnzhex_bits_5_forwards_matches3e31f036e77b0ee1a3e8312b0067959b.tex new file mode 100644 index 00000000..4a987066 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_5_forwards_matches3e31f036e77b0ee1a3e8312b0067959b.tex @@ -0,0 +1 @@ +function hex_bits_5_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_64_backwards_matches2ac7f320ee670e1403b866f7b48f9b95.tex b/sail_latex_riscv/fnzhex_bits_64_backwards_matches2ac7f320ee670e1403b866f7b48f9b95.tex new file mode 100644 index 00000000..5c6e3b1c --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_64_backwards_matches2ac7f320ee670e1403b866f7b48f9b95.tex @@ -0,0 +1,7 @@ +function hex_bits_64_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy64zymatcheszyprefix]{hex\_bits\_64\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_64_backwardsef9778c97dfbfdc25f03d089d5788d24.tex b/sail_latex_riscv/fnzhex_bits_64_backwardsef9778c97dfbfdc25f03d089d5788d24.tex new file mode 100644 index 00000000..69576280 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_64_backwardsef9778c97dfbfdc25f03d089d5788d24.tex @@ -0,0 +1,4 @@ +function hex_bits_64_backwards s = + match #\hyperref[sailRISCVzhexzybitszy64zymatcheszyprefix]{hex\_bits\_64\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_64_forwards_matches9b4aa7858f48288bd5ee715f31bb0cdb.tex b/sail_latex_riscv/fnzhex_bits_64_forwards_matches9b4aa7858f48288bd5ee715f31bb0cdb.tex new file mode 100644 index 00000000..9a4035dd --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_64_forwards_matches9b4aa7858f48288bd5ee715f31bb0cdb.tex @@ -0,0 +1 @@ +function hex_bits_64_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_6_backwards_matches4f038823a669140ed233992d9e5ddb69.tex b/sail_latex_riscv/fnzhex_bits_6_backwards_matches4f038823a669140ed233992d9e5ddb69.tex new file mode 100644 index 00000000..526d6634 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_6_backwards_matches4f038823a669140ed233992d9e5ddb69.tex @@ -0,0 +1,7 @@ +function hex_bits_6_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy6zymatcheszyprefix]{hex\_bits\_6\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_6_backwardsabaf13af56590b164adcda6b4fd1b52f.tex b/sail_latex_riscv/fnzhex_bits_6_backwardsabaf13af56590b164adcda6b4fd1b52f.tex new file mode 100644 index 00000000..f0e74ee8 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_6_backwardsabaf13af56590b164adcda6b4fd1b52f.tex @@ -0,0 +1,4 @@ +function hex_bits_6_backwards s = + match #\hyperref[sailRISCVzhexzybitszy6zymatcheszyprefix]{hex\_bits\_6\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_6_forwards_matchescaeea7989719fec9093c81797a7f4155.tex b/sail_latex_riscv/fnzhex_bits_6_forwards_matchescaeea7989719fec9093c81797a7f4155.tex new file mode 100644 index 00000000..80cebb1b --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_6_forwards_matchescaeea7989719fec9093c81797a7f4155.tex @@ -0,0 +1 @@ +function hex_bits_6_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_7_backwards33c217f9145eec45b693f09bca0d89ea.tex b/sail_latex_riscv/fnzhex_bits_7_backwards33c217f9145eec45b693f09bca0d89ea.tex new file mode 100644 index 00000000..e0b7df16 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_7_backwards33c217f9145eec45b693f09bca0d89ea.tex @@ -0,0 +1,4 @@ +function hex_bits_7_backwards s = + match #\hyperref[sailRISCVzhexzybitszy7zymatcheszyprefix]{hex\_bits\_7\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_7_backwards_matchescc985ebeb5f5adedc7e184499a8978db.tex b/sail_latex_riscv/fnzhex_bits_7_backwards_matchescc985ebeb5f5adedc7e184499a8978db.tex new file mode 100644 index 00000000..c2e9bfa5 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_7_backwards_matchescc985ebeb5f5adedc7e184499a8978db.tex @@ -0,0 +1,7 @@ +function hex_bits_7_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy7zymatcheszyprefix]{hex\_bits\_7\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_7_forwards_matches9d7aa1993e9d141c0950fe9e67734abc.tex b/sail_latex_riscv/fnzhex_bits_7_forwards_matches9d7aa1993e9d141c0950fe9e67734abc.tex new file mode 100644 index 00000000..937270d8 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_7_forwards_matches9d7aa1993e9d141c0950fe9e67734abc.tex @@ -0,0 +1 @@ +function hex_bits_7_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_8_backwards8502ba5c5fdfe5404c185ff925d26a02.tex b/sail_latex_riscv/fnzhex_bits_8_backwards8502ba5c5fdfe5404c185ff925d26a02.tex new file mode 100644 index 00000000..7929ccd0 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_8_backwards8502ba5c5fdfe5404c185ff925d26a02.tex @@ -0,0 +1,4 @@ +function hex_bits_8_backwards s = + match #\hyperref[sailRISCVzhexzybitszy8zymatcheszyprefix]{hex\_bits\_8\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_8_backwards_matchesa183109b599ae5e880adc653bde047ba.tex b/sail_latex_riscv/fnzhex_bits_8_backwards_matchesa183109b599ae5e880adc653bde047ba.tex new file mode 100644 index 00000000..502172d3 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_8_backwards_matchesa183109b599ae5e880adc653bde047ba.tex @@ -0,0 +1,7 @@ +function hex_bits_8_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy8zymatcheszyprefix]{hex\_bits\_8\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_8_forwards_matches0746becf5ca996196bfae6048bab9bb1.tex b/sail_latex_riscv/fnzhex_bits_8_forwards_matches0746becf5ca996196bfae6048bab9bb1.tex new file mode 100644 index 00000000..6f5a3870 --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_8_forwards_matches0746becf5ca996196bfae6048bab9bb1.tex @@ -0,0 +1 @@ +function hex_bits_8_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhex_bits_9_backwards90cddf73654805833800c2414c31ab0f.tex b/sail_latex_riscv/fnzhex_bits_9_backwards90cddf73654805833800c2414c31ab0f.tex new file mode 100644 index 00000000..478ced2e --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_9_backwards90cddf73654805833800c2414c31ab0f.tex @@ -0,0 +1,4 @@ +function hex_bits_9_backwards s = + match #\hyperref[sailRISCVzhexzybitszy9zymatcheszyprefix]{hex\_bits\_9\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (bv, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => bv + } diff --git a/sail_latex_riscv/fnzhex_bits_9_backwards_matches34e146fa5f101fa17110f57d272dec69.tex b/sail_latex_riscv/fnzhex_bits_9_backwards_matches34e146fa5f101fa17110f57d272dec69.tex new file mode 100644 index 00000000..9b58d59e --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_9_backwards_matches34e146fa5f101fa17110f57d272dec69.tex @@ -0,0 +1,7 @@ +function hex_bits_9_backwards_matches s = match s { + s if match #\hyperref[sailRISCVzhexzybitszy9zymatcheszyprefix]{hex\_bits\_9\_matches\_prefix}#(s) { + #\hyperref[sailRISCVzSome]{Some}# (_, n) if n == #\hyperref[sailRISCVzstringzylength]{string\_length}#(s) => true, + _ => false + } => true, + _ => false +} diff --git a/sail_latex_riscv/fnzhex_bits_9_forwards_matches73ffbf54790f1b1c63b0dc63773cd0c0.tex b/sail_latex_riscv/fnzhex_bits_9_forwards_matches73ffbf54790f1b1c63b0dc63773cd0c0.tex new file mode 100644 index 00000000..7171487a --- /dev/null +++ b/sail_latex_riscv/fnzhex_bits_9_forwards_matches73ffbf54790f1b1c63b0dc63773cd0c0.tex @@ -0,0 +1 @@ +function hex_bits_9_forwards_matches bv = true diff --git a/sail_latex_riscv/fnzhtif_load7bc11b4853a5dae019f61722a0a6d6d7.tex b/sail_latex_riscv/fnzhtif_load7bc11b4853a5dae019f61722a0a6d6d7.tex new file mode 100644 index 00000000..6c7d3be0 --- /dev/null +++ b/sail_latex_riscv/fnzhtif_load7bc11b4853a5dae019f61722a0a6d6d7.tex @@ -0,0 +1,16 @@ +function #\hyperref[sailRISCVzhtifzyload]{htif\_load}#(t, paddr, width) = { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("htif[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(paddr) ^ "] -> " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(htif_tohost)); + /* FIXME: For now, only allow the expected access widths. */ + if width == 8 & (paddr == #\hyperref[sailRISCVzplatzyhtifzytohost]{plat\_htif\_tohost}#()) + then #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(htif_tohost, 64)) /* FIXME: Redundant zero_extend currently required by Lem backend */ + else if width == 4 & paddr == #\hyperref[sailRISCVzplatzyhtifzytohost]{plat\_htif\_tohost}#() + then #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(htif_tohost[31..0], 32)) /* FIXME: Redundant zero_extend currently required by Lem backend */ + else if width == 4 & paddr == #\hyperref[sailRISCVzplatzyhtifzytohost]{plat\_htif\_tohost}#() + 4 + then #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(htif_tohost[63..32], 32)) /* FIXME: Redundant zero_extend currently required by Lem backend */ + else match t { + #\hyperref[sailRISCVzExecute]{Execute}#() => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzyFetchzyAccesszyFault]{E\_Fetch\_Access\_Fault}#()), + #\hyperref[sailRISCVzRead]{Read}#(Data) => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzyLoadzyAccesszyFault]{E\_Load\_Access\_Fault}#()), + _ => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#()) + } +} diff --git a/sail_latex_riscv/fnzhtif_storeab9d062182e5f884583204ccd435221d.tex b/sail_latex_riscv/fnzhtif_storeab9d062182e5f884583204ccd435221d.tex new file mode 100644 index 00000000..bbee8fc2 --- /dev/null +++ b/sail_latex_riscv/fnzhtif_storeab9d062182e5f884583204ccd435221d.tex @@ -0,0 +1,38 @@ +function #\hyperref[sailRISCVzhtifzystore]{htif\_store}#(paddr, width, data) = { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("htif[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(paddr) ^ "] <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(data)); + /* Store the written value so that we can ack it later. */ + if width == 8 + then { htif_tohost = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(data) } + else if width == 4 & paddr == #\hyperref[sailRISCVzplatzyhtifzytohost]{plat\_htif\_tohost}#() + then { htif_tohost = #\hyperref[sailRISCVzvectorzyupdatezysubrange]{vector\_update\_subrange}#(htif_tohost, 31, 0, data) } + else if width == 4 & paddr == #\hyperref[sailRISCVzplatzyhtifzytohost]{plat\_htif\_tohost}#() + 4 + then { htif_tohost = #\hyperref[sailRISCVzvectorzyupdatezysubrange]{vector\_update\_subrange}#(htif_tohost, 63, 32, data) } + else { htif_tohost = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(data) }; + + /* Process the cmd immediately; this is needed for terminal output. */ + let cmd = #\hyperref[sailRISCVzMkzyhtifzycmd]{Mk\_htif\_cmd}#(htif_tohost); + match cmd.#\hyperref[sailRISCVzdevice]{device}#() { + 0x00 => { /* syscall-proxy */ + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("htif-syscall-proxy cmd: " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(cmd.#\hyperref[sailRISCVzpayload]{payload}#())); + if cmd.#\hyperref[sailRISCVzpayload]{payload}#()[0] == bitone + then { + htif_done = true; + htif_exit_code = (#\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(cmd.#\hyperref[sailRISCVzpayload]{payload}#(), 64) >> 1) + } + else () + }, + 0x01 => { /* terminal */ + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("htif-term cmd: " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(cmd.#\hyperref[sailRISCVzpayload]{payload}#())); + match cmd.#\hyperref[sailRISCVzcmd]{cmd}#() { + 0x00 => /* TODO: terminal input handling */ (), + 0x01 => #\hyperref[sailRISCVzplatzytermzywrite]{plat\_term\_write}#(cmd.#\hyperref[sailRISCVzpayload]{payload}#()[7..0]), + c => #\hyperref[sailRISCVzprint]{print}#("Unknown term cmd: " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(c)) + } + }, + d => #\hyperref[sailRISCVzprint]{print}#("htif-???? cmd: " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(data)) + }; + #\hyperref[sailRISCVzMemValue]{MemValue}#(true) +} diff --git a/sail_latex_riscv/fnzhtif_tick227711b74637bcd9c79730b4942f90fb.tex b/sail_latex_riscv/fnzhtif_tick227711b74637bcd9c79730b4942f90fb.tex new file mode 100644 index 00000000..d1ce28ad --- /dev/null +++ b/sail_latex_riscv/fnzhtif_tick227711b74637bcd9c79730b4942f90fb.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzhtifzytick]{htif\_tick}#() = { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("htif::tick " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(htif_tohost)); + htif_tohost = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0) /* htif ack */ +} diff --git a/sail_latex_riscv/fnzin32bitmode1fa9d4b065e1807e1dff8fc7b86cca8d.tex b/sail_latex_riscv/fnzin32bitmode1fa9d4b065e1807e1dff8fc7b86cca8d.tex new file mode 100644 index 00000000..a3b46f37 --- /dev/null +++ b/sail_latex_riscv/fnzin32bitmode1fa9d4b065e1807e1dff8fc7b86cca8d.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzin32BitMode]{in32BitMode}#() -> bool = { + #\hyperref[sailRISCVzcurzyArchitecture]{cur\_Architecture}#() == RV32 +} diff --git a/sail_latex_riscv/fnzincapboundsc6e70952d3c6507cf32d75b499b90335.tex b/sail_latex_riscv/fnzincapboundsc6e70952d3c6507cf32d75b499b90335.tex new file mode 100644 index 00000000..e9d321b2 --- /dev/null +++ b/sail_latex_riscv/fnzincapboundsc6e70952d3c6507cf32d75b499b90335.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzinCapBounds]{inCapBounds}# (cap, addr, size) = { + let (base, top) = #\hyperref[sailRISCVzgetCapBounds]{getCapBounds}#(cap); + let a = #\hyperref[sailRISCVzunsigned]{unsigned}#(addr); + (a >= base) & ((a + size) <= top) +} diff --git a/sail_latex_riscv/fnzinccapoffsetc4735d243650e78b90bacb6efb419260.tex b/sail_latex_riscv/fnzinccapoffsetc4735d243650e78b90bacb6efb419260.tex new file mode 100644 index 00000000..5da4f4d1 --- /dev/null +++ b/sail_latex_riscv/fnzinccapoffsetc4735d243650e78b90bacb6efb419260.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzincCapOffset]{incCapOffset}#(c, delta) : (Capability, CapAddrBits) -> (bool, Capability) = + let newAddress : CapAddrBits = c.address + delta in + let newCap = { c with address = newAddress } in + /* let representable = #\hyperref[sailRISCVzcapBoundsEqual]{capBoundsEqual}#(c, newCap) in */ + let representable = #\hyperref[sailRISCVzfastRepCheck]{fastRepCheck}#(c, delta) in + (representable, newCap) diff --git a/sail_latex_riscv/fnzinit_base_regs92fa12c31a7794db853235a9147b1c7b.tex b/sail_latex_riscv/fnzinit_base_regs92fa12c31a7794db853235a9147b1c7b.tex new file mode 100644 index 00000000..3e6f68df --- /dev/null +++ b/sail_latex_riscv/fnzinit_base_regs92fa12c31a7794db853235a9147b1c7b.tex @@ -0,0 +1,33 @@ +function #\hyperref[sailRISCVzinitzybasezyregs]{init\_base\_regs}# () = { + x1 = zero_reg; + x2 = zero_reg; + x3 = zero_reg; + x4 = zero_reg; + x5 = zero_reg; + x6 = zero_reg; + x7 = zero_reg; + x8 = zero_reg; + x9 = zero_reg; + x10 = zero_reg; + x11 = zero_reg; + x12 = zero_reg; + x13 = zero_reg; + x14 = zero_reg; + x15 = zero_reg; + x16 = zero_reg; + x17 = zero_reg; + x18 = zero_reg; + x19 = zero_reg; + x20 = zero_reg; + x21 = zero_reg; + x22 = zero_reg; + x23 = zero_reg; + x24 = zero_reg; + x25 = zero_reg; + x26 = zero_reg; + x27 = zero_reg; + x28 = zero_reg; + x29 = zero_reg; + x30 = zero_reg; + x31 = zero_reg +} diff --git a/sail_latex_riscv/fnzinit_fdext_regs66a16bff324f831ac63cd022934bcc14.tex b/sail_latex_riscv/fnzinit_fdext_regs66a16bff324f831ac63cd022934bcc14.tex new file mode 100644 index 00000000..9253de04 --- /dev/null +++ b/sail_latex_riscv/fnzinit_fdext_regs66a16bff324f831ac63cd022934bcc14.tex @@ -0,0 +1,34 @@ +function #\hyperref[sailRISCVzinitzyfdextzyregs]{init\_fdext\_regs}# () = { + f0 = zero_freg; + f1 = zero_freg; + f2 = zero_freg; + f3 = zero_freg; + f4 = zero_freg; + f5 = zero_freg; + f6 = zero_freg; + f7 = zero_freg; + f8 = zero_freg; + f9 = zero_freg; + f10 = zero_freg; + f11 = zero_freg; + f12 = zero_freg; + f13 = zero_freg; + f14 = zero_freg; + f15 = zero_freg; + f16 = zero_freg; + f17 = zero_freg; + f18 = zero_freg; + f19 = zero_freg; + f20 = zero_freg; + f21 = zero_freg; + f22 = zero_freg; + f23 = zero_freg; + f24 = zero_freg; + f25 = zero_freg; + f26 = zero_freg; + f27 = zero_freg; + f28 = zero_freg; + f29 = zero_freg; + f30 = zero_freg; + f31 = zero_freg +} diff --git a/sail_latex_riscv/fnzinit_model2343c87c630c8dc589bf21c69bd047d3.tex b/sail_latex_riscv/fnzinit_model2343c87c630c8dc589bf21c69bd047d3.tex new file mode 100644 index 00000000..a39affde --- /dev/null +++ b/sail_latex_riscv/fnzinit_model2343c87c630c8dc589bf21c69bd047d3.tex @@ -0,0 +1,9 @@ +function #\hyperref[sailRISCVzinitzymodel]{init\_model}# () -> unit = { + #\hyperref[sailRISCVzinitzyplatform]{init\_platform}# (); /* devices */ + #\hyperref[sailRISCVzinitzysys]{init\_sys}# (); /* processor */ + #\hyperref[sailRISCVzinitzyvmem]{init\_vmem}# (); /* virtual memory */ + + /* initialize extensions last */ + #\hyperref[sailRISCVzextzyinit]{ext\_init}# (); + #\hyperref[sailRISCVzextzyinitzyregs]{ext\_init\_regs}# (); +} diff --git a/sail_latex_riscv/fnzinit_platform487cad4292d23a20d6a3d0b81157a250.tex b/sail_latex_riscv/fnzinit_platform487cad4292d23a20d6a3d0b81157a250.tex new file mode 100644 index 00000000..61bb9ec7 --- /dev/null +++ b/sail_latex_riscv/fnzinit_platform487cad4292d23a20d6a3d0b81157a250.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzinitzyplatform]{init\_platform}#() -> unit = { + htif_tohost = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + htif_done = false; + htif_exit_code = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0) +} diff --git a/sail_latex_riscv/fnzinit_pmp10ae24a767d242e86512a2c1a55970ef.tex b/sail_latex_riscv/fnzinit_pmp10ae24a767d242e86512a2c1a55970ef.tex new file mode 100644 index 00000000..ba6963b2 --- /dev/null +++ b/sail_latex_riscv/fnzinit_pmp10ae24a767d242e86512a2c1a55970ef.tex @@ -0,0 +1,18 @@ +function #\hyperref[sailRISCVzinitzypmp]{init\_pmp}#() -> unit = { + pmp0cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp0cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp1cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp1cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp2cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp2cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp3cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp3cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp4cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp4cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp5cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp5cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp6cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp6cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp7cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp7cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp8cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp8cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp9cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp9cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp10cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp10cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp11cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp11cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp12cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp12cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp13cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp13cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp14cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp14cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)); + pmp15cfg = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(pmp15cfg, #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(OFF)) +} diff --git a/sail_latex_riscv/fnzinit_sysc92898d1b2b72595dd36bce10e6a67fb.tex b/sail_latex_riscv/fnzinit_sysc92898d1b2b72595dd36bce10e6a67fb.tex new file mode 100644 index 00000000..39e2617c --- /dev/null +++ b/sail_latex_riscv/fnzinit_sysc92898d1b2b72595dd36bce10e6a67fb.tex @@ -0,0 +1,49 @@ +function #\hyperref[sailRISCVzinitzysys]{init\_sys}#() -> unit = { + cur_privilege = Machine; + + mhartid = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + + misa->#\hyperref[sailRISCVzMXL]{MXL}#() = #\hyperref[sailRISCVzarchzytozybits]{arch\_to\_bits}#(if sizeof(xlen) == 32 then RV32 else RV64); + misa->#\hyperref[sailRISCVzA]{A}#() = 0b1; /* atomics */ + misa->#\hyperref[sailRISCVzC]{C}#() = #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(#\hyperref[sailRISCVzsyszyenablezyrvc]{sys\_enable\_rvc}#()); /* RVC */ + misa->#\hyperref[sailRISCVzI]{I}#() = 0b1; /* base integer ISA */ + misa->#\hyperref[sailRISCVzM]{M}#() = 0b1; /* integer multiply/divide */ + misa->#\hyperref[sailRISCVzU]{U}#() = 0b1; /* user-mode */ + misa->#\hyperref[sailRISCVzS]{S}#() = 0b1; /* supervisor-mode */ + + /* On RV64, we currently support either both F and D, or neither. + * On RV32, we currently only support F. + */ + misa->#\hyperref[sailRISCVzF]{F}#() = #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#()); /* single-precision */ + misa->#\hyperref[sailRISCVzD]{D}#() = if sizeof(xlen) == 64 + then #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#()) /* double-precision */ + else 0b0; + + mstatus = #\hyperref[sailRISCVzsetzymstatuszySXL]{set\_mstatus\_SXL}#(mstatus, misa.#\hyperref[sailRISCVzMXL]{MXL}#()); + mstatus = #\hyperref[sailRISCVzsetzymstatuszyUXL]{set\_mstatus\_UXL}#(mstatus, misa.#\hyperref[sailRISCVzMXL]{MXL}#()); + mstatus->#\hyperref[sailRISCVzSD]{SD}#() = 0b0; + + mip->#\hyperref[sailRISCVzbits]{bits}#() = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + mie->#\hyperref[sailRISCVzbits]{bits}#() = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + mideleg->#\hyperref[sailRISCVzbits]{bits}#() = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + medeleg->#\hyperref[sailRISCVzbits]{bits}#() = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + mtvec->#\hyperref[sailRISCVzbits]{bits}#() = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + mcause->#\hyperref[sailRISCVzbits]{bits}#() = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + mepc = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + mtval = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + mscratch = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + + mcycle = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + mtime = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + + mcounteren->#\hyperref[sailRISCVzbits]{bits}#() = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + + minstret = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0); + minstret_written = false; + + #\hyperref[sailRISCVzinitzypmp]{init\_pmp}#(); + + // log compatibility with spike + if #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}#() + then #\hyperref[sailRISCVzprintzyreg]{print\_reg}#("CSR mstatus <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mstatus.#\hyperref[sailRISCVzbits]{bits}#()) ^ " (input: " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0) : xlenbits) ^ ")") +} diff --git a/sail_latex_riscv/fnzinit_vmem811d98ebf1d4d536d0e4070a3b67fe03.tex b/sail_latex_riscv/fnzinit_vmem811d98ebf1d4d536d0e4070a3b67fe03.tex new file mode 100644 index 00000000..5207e733 --- /dev/null +++ b/sail_latex_riscv/fnzinit_vmem811d98ebf1d4d536d0e4070a3b67fe03.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzinitzyvmem]{init\_vmem}#() -> unit = { + #\hyperref[sailRISCVzinitzyvmemzysv39]{init\_vmem\_sv39}#(); + #\hyperref[sailRISCVzinitzyvmemzysv48]{init\_vmem\_sv48}#() +} diff --git a/sail_latex_riscv/fnzinit_vmem_sv390a83d23f548fedfc48c542ac764df587.tex b/sail_latex_riscv/fnzinit_vmem_sv390a83d23f548fedfc48c542ac764df587.tex new file mode 100644 index 00000000..9e773639 --- /dev/null +++ b/sail_latex_riscv/fnzinit_vmem_sv390a83d23f548fedfc48c542ac764df587.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzinitzyvmemzysv39]{init\_vmem\_sv39}#() -> unit = { + tlb39 = #\hyperref[sailRISCVzNone]{None}#() +} diff --git a/sail_latex_riscv/fnzinit_vmem_sv487afaa3d38e7e9ff21a6cbfad52504311.tex b/sail_latex_riscv/fnzinit_vmem_sv487afaa3d38e7e9ff21a6cbfad52504311.tex new file mode 100644 index 00000000..7406a1b6 --- /dev/null +++ b/sail_latex_riscv/fnzinit_vmem_sv487afaa3d38e7e9ff21a6cbfad52504311.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzinitzyvmemzysv48]{init\_vmem\_sv48}#() -> unit = { + tlb48 = #\hyperref[sailRISCVzNone]{None}#() +} diff --git a/sail_latex_riscv/fnzinitial_analysis58ef2bf9252095b4ead796191551d1ec.tex b/sail_latex_riscv/fnzinitial_analysis58ef2bf9252095b4ead796191551d1ec.tex new file mode 100644 index 00000000..68012b19 --- /dev/null +++ b/sail_latex_riscv/fnzinitial_analysis58ef2bf9252095b4ead796191551d1ec.tex @@ -0,0 +1,169 @@ +function #\hyperref[sailRISCVzinitialzyanalysis]{initial\_analysis}# (instr:ast) -> (regfps,regfps,regfps,niafps,diafp,instruction_kind) = { + iR = [| |] : regfps; + oR = [| |] : regfps; + aR = [| |] : regfps; + ik = #\hyperref[sailRISCVzIKzysimple]{IK\_simple}#() : instruction_kind; + Nias = [| #\hyperref[sailRISCVzNIAFPzysuccessor]{NIAFP\_successor}#() |] : niafps; + Dia = #\hyperref[sailRISCVzDIAFPzynone]{DIAFP\_none}#() : diafp; + + match instr { + #\hyperref[sailRISCVzEBREAK]{EBREAK}#() => (), + #\hyperref[sailRISCVzUTYPE]{UTYPE}#(imm, rd, op) => { + if (rd == 0b00000) then () else oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + }, + #\hyperref[sailRISCVzRISCVzyJAL]{RISCV\_JAL}#(imm, rd) => { + if (rd == 0b00000) then () else oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + let offset : #\hyperref[sailRISCVzbits]{bits}#(64) = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm) in + Nias = [| #\hyperref[sailRISCVzNIAFPzyconcretezyaddress]{NIAFP\_concrete\_address}# (PC + offset) |]; + ik = #\hyperref[sailRISCVzIKzybranch]{IK\_branch}#(); + }, + #\hyperref[sailRISCVzRISCVzyJALR]{RISCV\_JALR}#(imm, rs, rd) => { + if (rs == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs)) :: iR; + if (rd == 0b00000) then () else oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + let offset : #\hyperref[sailRISCVzbits]{bits}#(64) = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm) in + Nias = [| #\hyperref[sailRISCVzNIAFPzyindirectzyaddress]{NIAFP\_indirect\_address}#() |]; + ik = #\hyperref[sailRISCVzIKzybranch]{IK\_branch}#(); + }, + #\hyperref[sailRISCVzBTYPE]{BTYPE}#(imm, rs2, rs1, op) => { + if (rs2 == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs2)) :: iR; + if (rs1 == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs1)) :: iR; + ik = #\hyperref[sailRISCVzIKzybranch]{IK\_branch}#(); + let offset : #\hyperref[sailRISCVzbits]{bits}#(64) = #\hyperref[sailRISCVzEXTS]{EXTS}#(imm) in + Nias = [| #\hyperref[sailRISCVzNIAFPzyconcretezyaddress]{NIAFP\_concrete\_address}#(PC + offset), #\hyperref[sailRISCVzNIAFPzysuccessor]{NIAFP\_successor}#() |]; + }, + #\hyperref[sailRISCVzITYPE]{ITYPE}#(imm, rs, rd, op) => { + if (rs == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs)) :: iR; + if (rd == 0b00000) then () else oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + }, + #\hyperref[sailRISCVzSHIFTIOP]{SHIFTIOP}#(imm, rs, rd, op) => { + if (rs == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs)) :: iR; + if (rd == 0b00000) then () else oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + }, + #\hyperref[sailRISCVzRTYPE]{RTYPE}#(rs2, rs1, rd, op) => { + if (rs2 == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs2)) :: iR; + if (rs1 == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs1)) :: iR; + if (rd == 0b00000) then () else oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + }, + #\hyperref[sailRISCVzCSR]{CSR}#(csr, rs1, rd, is_imm, op) => { + let isWrite : bool = match op { + CSRRW => true, + _ => if is_imm then #\hyperref[sailRISCVzunsigned]{unsigned}#(rs1) != 0 else #\hyperref[sailRISCVzunsigned]{unsigned}#(rs1) != 0 + }; + iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzcsrzyname]{csr\_name}#(csr)) :: iR; + if ~(is_imm) then { + iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs1)) :: iR; + }; + if isWrite then { + oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzcsrzyname]{csr\_name}#(csr)) :: oR; + }; + oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + }, + #\hyperref[sailRISCVzLOAD]{LOAD}#(imm, rs, rd, unsign, width, aq, rl) => { /* XXX "unsigned" causes name conflict in lem shallow embedding... */ + if (rs == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs)) :: iR; + if (rd == 0b00000) then () else oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + aR = iR; + ik = + match (aq, rl) { + (false, false) => #\hyperref[sailRISCVzIKzymemzyread]{IK\_mem\_read}# (Read_plain), + (true, false) => #\hyperref[sailRISCVzIKzymemzyread]{IK\_mem\_read}# (Read_RISCV_acquire), + (true, true) => #\hyperref[sailRISCVzIKzymemzyread]{IK\_mem\_read}# (Read_RISCV_strong_acquire), + + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("LOAD type not implemented in initial_analysis") + } + }, + #\hyperref[sailRISCVzSTORE]{STORE}#(imm, rs2, rs1, width, aq, rl) => { + if (rs2 == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs2)) :: iR; + if (rs1 == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs1)) :: iR; + if (rs1 == 0b00000) then () else aR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs1)) :: aR; + ik = + match (aq, rl) { + (false, false) => #\hyperref[sailRISCVzIKzymemzywrite]{IK\_mem\_write}# (Write_plain), + (false, true) => #\hyperref[sailRISCVzIKzymemzywrite]{IK\_mem\_write}# (Write_RISCV_release), + (true, true) => #\hyperref[sailRISCVzIKzymemzywrite]{IK\_mem\_write}# (Write_RISCV_strong_release), + + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("STORE type not implemented in initial_analysis") + } + }, + #\hyperref[sailRISCVzADDIW]{ADDIW}#(imm, rs, rd) => { + if (rs == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs)) :: iR; + if (rd == 0b00000) then () else oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + }, + #\hyperref[sailRISCVzSHIFTW]{SHIFTW}#(imm, rs, rd, op) => { + if (rs == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs)) :: iR; + if (rd == 0b00000) then () else oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + }, + #\hyperref[sailRISCVzRTYPEW]{RTYPEW}#(rs2, rs1, rd, op) => { + if (rs2 == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs2)) :: iR; + if (rs1 == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs1)) :: iR; + if (rd == 0b00000) then () else oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + }, + #\hyperref[sailRISCVzFENCE]{FENCE}#(pred, succ) => { + ik = + match (pred, succ) { + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11) => #\hyperref[sailRISCVzIKzybarrier]{IK\_barrier}# (#\hyperref[sailRISCVzBarrierzyRISCVzyrwzyrw]{Barrier\_RISCV\_rw\_rw}# ()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b10, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11) => #\hyperref[sailRISCVzIKzybarrier]{IK\_barrier}# (#\hyperref[sailRISCVzBarrierzyRISCVzyrzyrw]{Barrier\_RISCV\_r\_rw}# ()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b10, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b10) => #\hyperref[sailRISCVzIKzybarrier]{IK\_barrier}# (#\hyperref[sailRISCVzBarrierzyRISCVzyrzyr]{Barrier\_RISCV\_r\_r}# ()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b01) => #\hyperref[sailRISCVzIKzybarrier]{IK\_barrier}# (#\hyperref[sailRISCVzBarrierzyRISCVzyrwzyw]{Barrier\_RISCV\_rw\_w}# ()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b01, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b01) => #\hyperref[sailRISCVzIKzybarrier]{IK\_barrier}# (#\hyperref[sailRISCVzBarrierzyRISCVzywzyw]{Barrier\_RISCV\_w\_w}# ()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b01, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11) => #\hyperref[sailRISCVzIKzybarrier]{IK\_barrier}# (#\hyperref[sailRISCVzBarrierzyRISCVzywzyrw]{Barrier\_RISCV\_w\_rw}# ()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b10) => #\hyperref[sailRISCVzIKzybarrier]{IK\_barrier}# (#\hyperref[sailRISCVzBarrierzyRISCVzyrwzyr]{Barrier\_RISCV\_rw\_r}# ()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b10, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b01) => #\hyperref[sailRISCVzIKzybarrier]{IK\_barrier}# (#\hyperref[sailRISCVzBarrierzyRISCVzyrzyw]{Barrier\_RISCV\_r\_w}# ()), + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b01, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b10) => #\hyperref[sailRISCVzIKzybarrier]{IK\_barrier}# (#\hyperref[sailRISCVzBarrierzyRISCVzywzyr]{Barrier\_RISCV\_w\_r}# ()), + + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b00, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b00) => #\hyperref[sailRISCVzIKzysimple]{IK\_simple}# (), + + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("barrier type not implemented in initial_analysis") + }; + }, + #\hyperref[sailRISCVzFENCEzyTSO]{FENCE\_TSO}#(pred, succ) => { + ik = + match (pred, succ) { + (_ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11, _ : #\hyperref[sailRISCVzbits]{bits}#(2) @ 0b11) => #\hyperref[sailRISCVzIKzybarrier]{IK\_barrier}# (#\hyperref[sailRISCVzBarrierzyRISCVzytso]{Barrier\_RISCV\_tso}# ()), + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("barrier type not implemented in initial_analysis") + }; + }, + #\hyperref[sailRISCVzFENCEI]{FENCEI}#() => { + ik = #\hyperref[sailRISCVzIKzysimple]{IK\_simple}# (); // for RMEM, should morally be Barrier_RISCV_i + }, + #\hyperref[sailRISCVzLOADRES]{LOADRES}#(aq, rl, rs1, width, rd) => { + if (rs1 == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs1)) :: iR; + if (rd == 0b00000) then () else oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + aR = iR; + ik = match (aq, rl) { + (false, false) => #\hyperref[sailRISCVzIKzymemzyread]{IK\_mem\_read}# (Read_RISCV_reserved), + (true, false) => #\hyperref[sailRISCVzIKzymemzyread]{IK\_mem\_read}# (Read_RISCV_reserved_acquire), + (true, true) => #\hyperref[sailRISCVzIKzymemzyread]{IK\_mem\_read}# (Read_RISCV_reserved_strong_acquire), + (false, true) => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("LOADRES type not implemented in initial_analysis") + }; + }, + #\hyperref[sailRISCVzSTORECON]{STORECON}#(aq, rl, rs2, rs1, width, rd) => { + if (rs2 == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs2)) :: iR; + if (rs1 == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs1)) :: iR; + if (rs1 == 0b00000) then () else aR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs1)) :: aR; + if (rd == 0b00000) then () else oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + ik = match (aq, rl) { + (false, false) => #\hyperref[sailRISCVzIKzymemzywrite]{IK\_mem\_write}# (Write_RISCV_conditional), + (false, true) => #\hyperref[sailRISCVzIKzymemzywrite]{IK\_mem\_write}# (Write_RISCV_conditional_release), + (true, true) => #\hyperref[sailRISCVzIKzymemzywrite]{IK\_mem\_write}# (Write_RISCV_conditional_strong_release), + + (true, false) => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("STORECON type not implemented in initial_analysis") + }; + }, + #\hyperref[sailRISCVzAMO]{AMO}#(op, aq, rl, rs2, rs1, width, rd) => { + if (rs2 == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs2)) :: iR; + if (rs1 == 0b00000) then () else iR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs1)) :: iR; + if (rs1 == 0b00000) then () else aR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rs1)) :: aR; + if (rd == 0b00000) then () else oR = #\hyperref[sailRISCVzRFull]{RFull}#(#\hyperref[sailRISCVzGPRstr]{GPRstr}#(rd)) :: oR; + ik = match (aq, rl) { + (false, false) => #\hyperref[sailRISCVzIKzymemzyrmw]{IK\_mem\_rmw}# (Read_RISCV_reserved, Write_RISCV_conditional), + (false, true) => #\hyperref[sailRISCVzIKzymemzyrmw]{IK\_mem\_rmw}# (Read_RISCV_reserved, Write_RISCV_conditional_release), + (true, false) => #\hyperref[sailRISCVzIKzymemzyrmw]{IK\_mem\_rmw}# (Read_RISCV_reserved_acquire, + Write_RISCV_conditional), + (true, true) => #\hyperref[sailRISCVzIKzymemzyrmw]{IK\_mem\_rmw}# (Read_RISCV_reserved_acquire, + Write_RISCV_conditional_release) + }; + }, + _ => () + }; + (iR,oR,aR,Nias,Dia,ik) +} diff --git a/sail_latex_riscv/fnzint_to_capf8526cbe276f6bcb8e84d62c62d4f9a1.tex b/sail_latex_riscv/fnzint_to_capf8526cbe276f6bcb8e84d62c62d4f9a1.tex new file mode 100644 index 00000000..4ed1e37f --- /dev/null +++ b/sail_latex_riscv/fnzint_to_capf8526cbe276f6bcb8e84d62c62d4f9a1.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzintzytozycap]{int\_to\_cap}# (offset) : CapAddrBits -> Capability = + {null_cap with address = offset} diff --git a/sail_latex_riscv/fnzinternal_error92c3548c19282819d20d44565303aa89.tex b/sail_latex_riscv/fnzinternal_error92c3548c19282819d20d44565303aa89.tex new file mode 100644 index 00000000..9ea94357 --- /dev/null +++ b/sail_latex_riscv/fnzinternal_error92c3548c19282819d20d44565303aa89.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#(s) = { + assert (false, s); + throw #\hyperref[sailRISCVzErrorzyinternalzyerror]{Error\_internal\_error}#() +} diff --git a/sail_latex_riscv/fnzinterrupttype_of_numbcca70e199dd805ea962d03dd661ceb8.tex b/sail_latex_riscv/fnzinterrupttype_of_numbcca70e199dd805ea962d03dd661ceb8.tex new file mode 100644 index 00000000..b74caa91 --- /dev/null +++ b/sail_latex_riscv/fnzinterrupttype_of_numbcca70e199dd805ea962d03dd661ceb8.tex @@ -0,0 +1,11 @@ +function InterruptType_of_num arg# = match arg# { + 0 => I_U_Software, + 1 => I_S_Software, + 2 => I_M_Software, + 3 => I_U_Timer, + 4 => I_S_Timer, + 5 => I_M_Timer, + 6 => I_U_External, + 7 => I_S_External, + _ => I_M_External +} diff --git a/sail_latex_riscv/fnzinterrupttype_to_bits80d6193c8205e91dcda1e3a5b6126a81.tex b/sail_latex_riscv/fnzinterrupttype_to_bits80d6193c8205e91dcda1e3a5b6126a81.tex new file mode 100644 index 00000000..cb68a4d5 --- /dev/null +++ b/sail_latex_riscv/fnzinterrupttype_to_bits80d6193c8205e91dcda1e3a5b6126a81.tex @@ -0,0 +1,12 @@ +function #\hyperref[sailRISCVzinterruptTypezytozybits]{interruptType\_to\_bits}# (i) = + match (i) { + I_U_Software => 0x00, + I_S_Software => 0x01, + I_M_Software => 0x03, + I_U_Timer => 0x04, + I_S_Timer => 0x05, + I_M_Timer => 0x07, + I_U_External => 0x08, + I_S_External => 0x09, + I_M_External => 0x0b + } diff --git a/sail_latex_riscv/fnzinvalidatecap831c5555c31b163a19988faa291f9c20.tex b/sail_latex_riscv/fnzinvalidatecap831c5555c31b163a19988faa291f9c20.tex new file mode 100644 index 00000000..76eacbf8 --- /dev/null +++ b/sail_latex_riscv/fnzinvalidatecap831c5555c31b163a19988faa291f9c20.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzinvalidateCap]{invalidateCap}#(cap) : Capability -> Capability = {cap with tag=false} diff --git a/sail_latex_riscv/fnziop_of_numd466c8622bc5d10ff829fe51ba16e9a6.tex b/sail_latex_riscv/fnziop_of_numd466c8622bc5d10ff829fe51ba16e9a6.tex new file mode 100644 index 00000000..162c8629 --- /dev/null +++ b/sail_latex_riscv/fnziop_of_numd466c8622bc5d10ff829fe51ba16e9a6.tex @@ -0,0 +1,8 @@ +function iop_of_num arg# = match arg# { + 0 => RISCV_ADDI, + 1 => RISCV_SLTI, + 2 => RISCV_SLTIU, + 3 => RISCV_XORI, + 4 => RISCV_ORI, + _ => RISCV_ANDI +} diff --git a/sail_latex_riscv/fnzis_aligned_addr6fae0ea13237382ac6720d04123fd943.tex b/sail_latex_riscv/fnzis_aligned_addr6fae0ea13237382ac6720d04123fd943.tex new file mode 100644 index 00000000..3cf4de73 --- /dev/null +++ b/sail_latex_riscv/fnzis_aligned_addr6fae0ea13237382ac6720d04123fd943.tex @@ -0,0 +1,2 @@ +function is_aligned_addr forall 'n. (addr : xlenbits, width : atom('n)) -> bool = + #\hyperref[sailRISCVzunsigned]{unsigned}#(addr) % width == 0 diff --git a/sail_latex_riscv/fnzis_csr_definedcd68bcdc8a87dceb6e3521cc036a67d0.tex b/sail_latex_riscv/fnzis_csr_definedcd68bcdc8a87dceb6e3521cc036a67d0.tex new file mode 100644 index 00000000..d531f1e5 --- /dev/null +++ b/sail_latex_riscv/fnzis_csr_definedcd68bcdc8a87dceb6e3521cc036a67d0.tex @@ -0,0 +1,84 @@ +function #\hyperref[sailRISCVziszyCSRzydefined]{is\_CSR\_defined}# (csr : csreg, p : Privilege) -> bool = + match (csr) { + /* machine mode: informational */ + 0xf11 => p == Machine, // mvendorid + 0xf12 => p == Machine, // marchdid + 0xf13 => p == Machine, // mimpid + 0xf14 => p == Machine, // mhartid + /* machine mode: trap setup */ + 0x300 => p == Machine, // mstatus + 0x301 => p == Machine, // misa + 0x302 => p == Machine, // medeleg + 0x303 => p == Machine, // mideleg + 0x304 => p == Machine, // mie + 0x305 => p == Machine, // mtvec + 0x306 => p == Machine, // mcounteren + /* machine mode: trap handling */ + 0x340 => p == Machine, // mscratch + 0x341 => p == Machine, // mepc + 0x342 => p == Machine, // mcause + 0x343 => p == Machine, // mtval + 0x344 => p == Machine, // mip + + 0x3A0 => p == Machine, // pmpcfg0 + 0x3A1 => p == Machine & (sizeof(xlen) == 32), // pmpcfg1 + 0x3A2 => p == Machine, // pmpcfg2 + 0x3A3 => p == Machine & (sizeof(xlen) == 32), // pmpcfg3 + + 0x3B0 => p == Machine, // pmpaddr0 + 0x3B1 => p == Machine, // pmpaddr1 + 0x3B2 => p == Machine, // pmpaddr2 + 0x3B3 => p == Machine, // pmpaddr3 + 0x3B4 => p == Machine, // pmpaddr4 + 0x3B5 => p == Machine, // pmpaddr5 + 0x3B6 => p == Machine, // pmpaddr6 + 0x3B7 => p == Machine, // pmpaddr7 + 0x3B8 => p == Machine, // pmpaddr8 + 0x3B9 => p == Machine, // pmpaddr9 + 0x3BA => p == Machine, // pmpaddrA + 0x3BB => p == Machine, // pmpaddrB + 0x3BC => p == Machine, // pmpaddrC + 0x3BD => p == Machine, // pmpaddrD + 0x3BE => p == Machine, // pmpaddrE + 0x3BF => p == Machine, // pmpaddrF + + /* counters */ + 0xB00 => p == Machine, // mcycle + 0xB02 => p == Machine, // minstret + + 0xB80 => p == Machine & (sizeof(xlen) == 32), // mcycleh + 0xB82 => p == Machine & (sizeof(xlen) == 32), // minstreth + + /* disabled trigger/debug module */ + 0x7a0 => p == Machine, + + /* supervisor mode: trap setup */ + 0x100 => #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (p == Machine | p == Supervisor), // sstatus + 0x102 => #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (p == Machine | p == Supervisor), // sedeleg + 0x103 => #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (p == Machine | p == Supervisor), // sideleg + 0x104 => #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (p == Machine | p == Supervisor), // sie + 0x105 => #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (p == Machine | p == Supervisor), // stvec + 0x106 => #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (p == Machine | p == Supervisor), // scounteren + + /* supervisor mode: trap handling */ + 0x140 => #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (p == Machine | p == Supervisor), // sscratch + 0x141 => #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (p == Machine | p == Supervisor), // sepc + 0x142 => #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (p == Machine | p == Supervisor), // scause + 0x143 => #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (p == Machine | p == Supervisor), // stval + 0x144 => #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (p == Machine | p == Supervisor), // sip + + /* supervisor mode: address translation */ + 0x180 => #\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#() & (p == Machine | p == Supervisor), // satp + + /* user mode: counters */ + 0xC00 => p == User, // cycle + 0xC01 => p == User, // time + 0xC02 => p == User, // instret + + 0xC80 => p == User & (sizeof(xlen) == 32), // cycleh + 0xC81 => p == User & (sizeof(xlen) == 32), // timeh + 0xC82 => p == User & (sizeof(xlen) == 32), // instreth + + /* check extensions */ + _ => #\hyperref[sailRISCVzextzyiszyCSRzydefined]{ext\_is\_CSR\_defined}#(csr, p) + } diff --git a/sail_latex_riscv/fnzis_nonebebf4558161c4d567fb50f7df9e82374.tex b/sail_latex_riscv/fnzis_nonebebf4558161c4d567fb50f7df9e82374.tex new file mode 100644 index 00000000..c5c05230 --- /dev/null +++ b/sail_latex_riscv/fnzis_nonebebf4558161c4d567fb50f7df9e82374.tex @@ -0,0 +1,4 @@ +function is_none opt = match opt { + #\hyperref[sailRISCVzSome]{Some}#(_) => false, + #\hyperref[sailRISCVzNone]{None}#() => true +} diff --git a/sail_latex_riscv/fnzis_rv32d_or_rv64d3518fa18b37b3eaa9c4945d112044e98.tex b/sail_latex_riscv/fnzis_rv32d_or_rv64d3518fa18b37b3eaa9c4945d112044e98.tex new file mode 100644 index 00000000..f420e727 --- /dev/null +++ b/sail_latex_riscv/fnzis_rv32d_or_rv64d3518fa18b37b3eaa9c4945d112044e98.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVziszyRV32DzyorzyRV64D]{is\_RV32D\_or\_RV64D}# () -> bool = (#\hyperref[sailRISCVzhaveDExt]{haveDExt}#() & (sizeof(xlen) == 32 | sizeof(xlen) == 64)) diff --git a/sail_latex_riscv/fnzis_rv32f_or_rv64f0479eeacd8ff6d333014b8d2bd493bf0.tex b/sail_latex_riscv/fnzis_rv32f_or_rv64f0479eeacd8ff6d333014b8d2bd493bf0.tex new file mode 100644 index 00000000..bc807195 --- /dev/null +++ b/sail_latex_riscv/fnzis_rv32f_or_rv64f0479eeacd8ff6d333014b8d2bd493bf0.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVziszyRV32FzyorzyRV64F]{is\_RV32F\_or\_RV64F}# () -> bool = (#\hyperref[sailRISCVzhaveFExt]{haveFExt}#() & (sizeof(xlen) == 32 | sizeof(xlen) == 64)) diff --git a/sail_latex_riscv/fnzis_rv64d2ec4297accd40afbaf8305bfa55a08ef.tex b/sail_latex_riscv/fnzis_rv64d2ec4297accd40afbaf8305bfa55a08ef.tex new file mode 100644 index 00000000..a43b4569 --- /dev/null +++ b/sail_latex_riscv/fnzis_rv64d2ec4297accd40afbaf8305bfa55a08ef.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVziszyRV64D]{is\_RV64D}# () -> bool = (#\hyperref[sailRISCVzhaveDExt]{haveDExt}#() & sizeof(xlen) == 64) diff --git a/sail_latex_riscv/fnzis_rv64f294d3f4a32a15e369d15c34498a07034.tex b/sail_latex_riscv/fnzis_rv64f294d3f4a32a15e369d15c34498a07034.tex new file mode 100644 index 00000000..16f0b185 --- /dev/null +++ b/sail_latex_riscv/fnzis_rv64f294d3f4a32a15e369d15c34498a07034.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVziszyRV64F]{is\_RV64F}# () -> bool = (#\hyperref[sailRISCVzhaveFExt]{haveFExt}#() & sizeof(xlen) == 64) diff --git a/sail_latex_riscv/fnzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex b/sail_latex_riscv/fnzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex new file mode 100644 index 00000000..fc1bffc1 --- /dev/null +++ b/sail_latex_riscv/fnzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex @@ -0,0 +1,4 @@ +function is_some opt = match opt { + #\hyperref[sailRISCVzSome]{Some}#(_) => true, + #\hyperref[sailRISCVzNone]{None}#() => false +} diff --git a/sail_latex_riscv/fnziscapsealeda9077bc28a9d2efcd12e42755a4de536.tex b/sail_latex_riscv/fnziscapsealeda9077bc28a9d2efcd12e42755a4de536.tex new file mode 100644 index 00000000..bfa5353b --- /dev/null +++ b/sail_latex_riscv/fnziscapsealeda9077bc28a9d2efcd12e42755a4de536.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cap) = #\hyperref[sailRISCVzsigned]{signed}#(cap.otype) != otype_unsealed diff --git a/sail_latex_riscv/fnzisinvalidpte046e5b8d20df2f7ed228312986edeed3.tex b/sail_latex_riscv/fnzisinvalidpte046e5b8d20df2f7ed228312986edeed3.tex new file mode 100644 index 00000000..592f12be --- /dev/null +++ b/sail_latex_riscv/fnzisinvalidpte046e5b8d20df2f7ed228312986edeed3.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzisInvalidPTE]{isInvalidPTE}#(p : pteAttribs, ext : extPte) -> bool = { + let a = #\hyperref[sailRISCVzMkzyPTEzyBits]{Mk\_PTE\_Bits}#(p); + a.#\hyperref[sailRISCVzV]{V}#() == 0b0 | (a.#\hyperref[sailRISCVzW]{W}#() == 0b1 & a.#\hyperref[sailRISCVzR]{R}#() == 0b0) +} diff --git a/sail_latex_riscv/fnzispteptrba43877f6dc42c078f937aa41c879446.tex b/sail_latex_riscv/fnzispteptrba43877f6dc42c078f937aa41c879446.tex new file mode 100644 index 00000000..e7f35f3e --- /dev/null +++ b/sail_latex_riscv/fnzispteptrba43877f6dc42c078f937aa41c879446.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzisPTEPtr]{isPTEPtr}#(p : pteAttribs, ext : extPte) -> bool = { + let a = #\hyperref[sailRISCVzMkzyPTEzyBits]{Mk\_PTE\_Bits}#(p); + a.#\hyperref[sailRISCVzR]{R}#() == 0b0 & a.#\hyperref[sailRISCVzW]{W}#() == 0b0 & a.#\hyperref[sailRISCVzX]{X}#() == 0b0 +} diff --git a/sail_latex_riscv/fnzisrvcd64dda5fc24513d78f480d3583dee004.tex b/sail_latex_riscv/fnzisrvcd64dda5fc24513d78f480d3583dee004.tex new file mode 100644 index 00000000..28bd393d --- /dev/null +++ b/sail_latex_riscv/fnzisrvcd64dda5fc24513d78f480d3583dee004.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzisRVC]{isRVC}#(h : half) -> bool = ~ (h[1 .. 0] == 0b11) diff --git a/sail_latex_riscv/fnzisvalidsv39addr6225e53e2f01610f83ab9bea1f3201bf.tex b/sail_latex_riscv/fnzisvalidsv39addr6225e53e2f01610f83ab9bea1f3201bf.tex new file mode 100644 index 00000000..b1628ead --- /dev/null +++ b/sail_latex_riscv/fnzisvalidsv39addr6225e53e2f01610f83ab9bea1f3201bf.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzisValidSv39Addr]{isValidSv39Addr}#(vAddr : xlenbits) -> bool = { + vAddr[63 .. 39] == (if vAddr[38] == bitone + then #\hyperref[sailRISCVzones]{ones}#() + else #\hyperref[sailRISCVzzzeros]{zeros}#()) +} diff --git a/sail_latex_riscv/fnzisvalidsv48addr5c09db742963fd3c2cd1457f6411e837.tex b/sail_latex_riscv/fnzisvalidsv48addr5c09db742963fd3c2cd1457f6411e837.tex new file mode 100644 index 00000000..dcd1c25c --- /dev/null +++ b/sail_latex_riscv/fnzisvalidsv48addr5c09db742963fd3c2cd1457f6411e837.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzisValidSv48Addr]{isValidSv48Addr}#(vAddr : xlenbits) -> bool = { + vAddr[63 .. 48] == (if vAddr[47] == bitone + then #\hyperref[sailRISCVzones]{ones}#() + else #\hyperref[sailRISCVzzzeros]{zeros}#()) +} diff --git a/sail_latex_riscv/fnzlegalizze_ccsr8248d36ab83d1808c1e3e0b64d88c1cf.tex b/sail_latex_riscv/fnzlegalizze_ccsr8248d36ab83d1808c1e3e0b64d88c1cf.tex new file mode 100644 index 00000000..106f919d --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_ccsr8248d36ab83d1808c1e3e0b64d88c1cf.tex @@ -0,0 +1,12 @@ +function #\hyperref[sailRISCVzlegalizzezyccsr]{legalize\_ccsr}#(c : ccsr, v : xlenbits) -> ccsr = { + // write only the defined bits, leaving the other bits untouched + // Technically, WPRI does not need a legalizer, since software is + // assumed to legalize; so we could remove this function. + let v = #\hyperref[sailRISCVzMkzyccsr]{Mk\_ccsr}#(v); + let c = #\hyperref[sailRISCVzupdatezycapzyidx]{update\_cap\_idx}#(c, v.#\hyperref[sailRISCVzcapzyidx]{cap\_idx}#()); + let c = #\hyperref[sailRISCVzupdatezycause]{update\_cause}#(c, v.#\hyperref[sailRISCVzcause]{cause}#()); + /* For now these bits are not really supported so hardwired to true */ + let c = #\hyperref[sailRISCVzupdatezyd]{update\_d}#(c, 0b1); + let c = #\hyperref[sailRISCVzupdatezye]{update\_e}#(c, 0b1); + c +} diff --git a/sail_latex_riscv/fnzlegalizze_epccfd09ccf016c22f97fa9a6b5dfba65e84.tex b/sail_latex_riscv/fnzlegalizze_epccfd09ccf016c22f97fa9a6b5dfba65e84.tex new file mode 100644 index 00000000..6515d200 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_epccfd09ccf016c22f97fa9a6b5dfba65e84.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzlegalizzezyepcc]{legalize\_epcc}# (v : Capability) -> Capability = { + let voffset = #\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(v); + let legalized = #\hyperref[sailRISCVzlegalizzezyxepc]{legalize\_xepc}#(voffset); + + if legalized == voffset + then v /* avoid possibly attempting to set the offset of a sentry */ + else #\hyperref[sailRISCVzsetCapOffsetOrNull]{setCapOffsetOrNull}#(v, legalized) +} diff --git a/sail_latex_riscv/fnzlegalizze_mcounteren34ab1d8bf1d636c1c12eb9e0b743229f.tex b/sail_latex_riscv/fnzlegalizze_mcounteren34ab1d8bf1d636c1c12eb9e0b743229f.tex new file mode 100644 index 00000000..02f74c5d --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_mcounteren34ab1d8bf1d636c1c12eb9e0b743229f.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzlegalizzezymcounteren]{legalize\_mcounteren}#(c : Counteren, v : xlenbits) -> Counteren = { + /* no HPM counters yet */ + let c = #\hyperref[sailRISCVzupdatezyIR]{update\_IR}#(c, [v[2]]); + let c = #\hyperref[sailRISCVzupdatezyTM]{update\_TM}#(c, [v[1]]); + let c = #\hyperref[sailRISCVzupdatezyCY]{update\_CY}#(c, [v[0]]); + c +} diff --git a/sail_latex_riscv/fnzlegalizze_mcountinhibit83a4863cf81084082c5c66150150e695.tex b/sail_latex_riscv/fnzlegalizze_mcountinhibit83a4863cf81084082c5c66150150e695.tex new file mode 100644 index 00000000..930aa761 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_mcountinhibit83a4863cf81084082c5c66150150e695.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzlegalizzezymcountinhibit]{legalize\_mcountinhibit}#(c : Counterin, v : xlenbits) -> Counterin = { + let c = #\hyperref[sailRISCVzupdatezyIR]{update\_IR}#(c, [v[2]]); + let c = #\hyperref[sailRISCVzupdatezyCY]{update\_CY}#(c, [v[0]]); + c +} diff --git a/sail_latex_riscv/fnzlegalizze_medeleg4472d564e1553d1bbac6c6cbaeff95c9.tex b/sail_latex_riscv/fnzlegalizze_medeleg4472d564e1553d1bbac6c6cbaeff95c9.tex new file mode 100644 index 00000000..ac27f771 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_medeleg4472d564e1553d1bbac6c6cbaeff95c9.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzlegalizzezymedeleg]{legalize\_medeleg}#(o : Medeleg, v : xlenbits) -> Medeleg = { + let m = #\hyperref[sailRISCVzMkzyMedeleg]{Mk\_Medeleg}#(v); + /* M-EnvCalls delegation is not supported */ + let m = #\hyperref[sailRISCVzupdatezyMEnvCall]{update\_MEnvCall}#(m, 0b0); + m +} diff --git a/sail_latex_riscv/fnzlegalizze_mideleg301fb79c822ffefd5b20e289875da3e4.tex b/sail_latex_riscv/fnzlegalizze_mideleg301fb79c822ffefd5b20e289875da3e4.tex new file mode 100644 index 00000000..e3d2fd23 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_mideleg301fb79c822ffefd5b20e289875da3e4.tex @@ -0,0 +1,9 @@ +function #\hyperref[sailRISCVzlegalizzezymideleg]{legalize\_mideleg}#(o : Minterrupts, v : xlenbits) -> Minterrupts = { + /* M-mode interrupt delegation bits "should" be hardwired to 0. */ + /* FIXME: needs verification against eventual spec language. */ + let m = #\hyperref[sailRISCVzMkzyMinterrupts]{Mk\_Minterrupts}#(v); + let m = #\hyperref[sailRISCVzupdatezyMEI]{update\_MEI}#(m, 0b0); + let m = #\hyperref[sailRISCVzupdatezyMTI]{update\_MTI}#(m, 0b0); + let m = #\hyperref[sailRISCVzupdatezyMSI]{update\_MSI}#(m, 0b0); + m +} diff --git a/sail_latex_riscv/fnzlegalizze_miea3d44a6b9220a2e1cbd134912a2b63af.tex b/sail_latex_riscv/fnzlegalizze_miea3d44a6b9220a2e1cbd134912a2b63af.tex new file mode 100644 index 00000000..84a717d5 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_miea3d44a6b9220a2e1cbd134912a2b63af.tex @@ -0,0 +1,16 @@ +function #\hyperref[sailRISCVzlegalizzezymie]{legalize\_mie}#(o : Minterrupts, v : xlenbits) -> Minterrupts = { + let v = #\hyperref[sailRISCVzMkzyMinterrupts]{Mk\_Minterrupts}#(v); + let m = #\hyperref[sailRISCVzupdatezyMEI]{update\_MEI}#(o, v.#\hyperref[sailRISCVzMEI]{MEI}#()); + let m = #\hyperref[sailRISCVzupdatezyMTI]{update\_MTI}#(m, v.#\hyperref[sailRISCVzMTI]{MTI}#()); + let m = #\hyperref[sailRISCVzupdatezyMSI]{update\_MSI}#(m, v.#\hyperref[sailRISCVzMSI]{MSI}#()); + let m = #\hyperref[sailRISCVzupdatezySEI]{update\_SEI}#(m, v.#\hyperref[sailRISCVzSEI]{SEI}#()); + let m = #\hyperref[sailRISCVzupdatezySTI]{update\_STI}#(m, v.#\hyperref[sailRISCVzSTI]{STI}#()); + let m = #\hyperref[sailRISCVzupdatezySSI]{update\_SSI}#(m, v.#\hyperref[sailRISCVzSSI]{SSI}#()); + /* The U-mode bits will be modified if we have the 'N' extension. */ + if #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() & #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() then { + let m = #\hyperref[sailRISCVzupdatezyUEI]{update\_UEI}#(m, v.#\hyperref[sailRISCVzUEI]{UEI}#()); + let m = #\hyperref[sailRISCVzupdatezyUTI]{update\_UTI}#(m, v.#\hyperref[sailRISCVzUTI]{UTI}#()); + let m = #\hyperref[sailRISCVzupdatezyUSI]{update\_USI}#(m, v.#\hyperref[sailRISCVzUSI]{USI}#()); + m + } else m +} diff --git a/sail_latex_riscv/fnzlegalizze_mip6b35097c942aa7a4220cfbae774dd473.tex b/sail_latex_riscv/fnzlegalizze_mip6b35097c942aa7a4220cfbae774dd473.tex new file mode 100644 index 00000000..9c3c26dd --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_mip6b35097c942aa7a4220cfbae774dd473.tex @@ -0,0 +1,14 @@ +function #\hyperref[sailRISCVzlegalizzezymip]{legalize\_mip}#(o : Minterrupts, v : xlenbits) -> Minterrupts = { + /* The only writable bits are the S-mode bits, and with the 'N' + * extension, the U-mode bits. */ + let v = #\hyperref[sailRISCVzMkzyMinterrupts]{Mk\_Minterrupts}#(v); + let m = #\hyperref[sailRISCVzupdatezySEI]{update\_SEI}#(o, v.#\hyperref[sailRISCVzSEI]{SEI}#()); + let m = #\hyperref[sailRISCVzupdatezySTI]{update\_STI}#(m, v.#\hyperref[sailRISCVzSTI]{STI}#()); + let m = #\hyperref[sailRISCVzupdatezySSI]{update\_SSI}#(m, v.#\hyperref[sailRISCVzSSI]{SSI}#()); + if #\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#() & #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() then { + let m = #\hyperref[sailRISCVzupdatezyUEI]{update\_UEI}#(m, v.#\hyperref[sailRISCVzUEI]{UEI}#()); + let m = #\hyperref[sailRISCVzupdatezyUTI]{update\_UTI}#(m, v.#\hyperref[sailRISCVzUTI]{UTI}#()); + let m = #\hyperref[sailRISCVzupdatezyUSI]{update\_USI}#(m, v.#\hyperref[sailRISCVzUSI]{USI}#()); + m + } else m +} diff --git a/sail_latex_riscv/fnzlegalizze_misad494764bfeb5d382d189645941a1bce6.tex b/sail_latex_riscv/fnzlegalizze_misad494764bfeb5d382d189645941a1bce6.tex new file mode 100644 index 00000000..d2c56ed9 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_misad494764bfeb5d382d189645941a1bce6.tex @@ -0,0 +1,16 @@ +function #\hyperref[sailRISCVzlegalizzezymisa]{legalize\_misa}#(m : Misa, v : xlenbits) -> Misa = { + if #\hyperref[sailRISCVzsyszyenablezywritablezymisa]{sys\_enable\_writable\_misa}# () + then { /* Handle modifications to C. */ + let v = #\hyperref[sailRISCVzMkzyMisa]{Mk\_Misa}#(v); + /* Suppress changing C if nextPC would become misaligned or an extension vetoes or C was disabled at #\hyperref[sailRISCVzboot]{boot}# (i.e. not supported). */ + let m = + if (v.#\hyperref[sailRISCVzC]{C}#() == 0b0 & (nextPC[1] == bitone | #\hyperref[sailRISCVzextzyvetozydisablezyC]{ext\_veto\_disable\_C}#())) | ~(#\hyperref[sailRISCVzsyszyenablezyrvc]{sys\_enable\_rvc}#()) + then m + else #\hyperref[sailRISCVzupdatezyC]{update\_C}#(m, v.#\hyperref[sailRISCVzC]{C}#()); + /* Handle updates for F/D. */ + if ~(#\hyperref[sailRISCVzsyszyenablezyfdext]{sys\_enable\_fdext}#()) | (v.#\hyperref[sailRISCVzD]{D}#() == 0b1 & v.#\hyperref[sailRISCVzF]{F}#() == 0b0) + then m + else #\hyperref[sailRISCVzupdatezyD]{update\_D}#(#\hyperref[sailRISCVzupdatezyF]{update\_F}#(m, v.#\hyperref[sailRISCVzF]{F}#()), v.#\hyperref[sailRISCVzD]{D}#()) + } + else m +} diff --git a/sail_latex_riscv/fnzlegalizze_mstatus99091e0733640797e5a873808232271b.tex b/sail_latex_riscv/fnzlegalizze_mstatus99091e0733640797e5a873808232271b.tex new file mode 100644 index 00000000..3847f8ea --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_mstatus99091e0733640797e5a873808232271b.tex @@ -0,0 +1,29 @@ +function #\hyperref[sailRISCVzlegalizzezymstatus]{legalize\_mstatus}#(o : Mstatus, v : xlenbits) -> Mstatus = { + let m : Mstatus = #\hyperref[sailRISCVzMkzyMstatus]{Mk\_Mstatus}#(v); + + /* We don't have any extension context yet. */ + let m = #\hyperref[sailRISCVzupdatezyXS]{update\_XS}#(m, #\hyperref[sailRISCVzextStatuszytozybits]{extStatus\_to\_bits}#(Off)); + /* FS is WARL, and making FS writable can support the M-mode emulation of an FPU + * to support code running in S/U-modes. Spike does this, and for now, we match it. + * FIXME: This should be made a platform parameter. + */ + + let dirty = #\hyperref[sailRISCVzextStatuszyofzybits]{extStatus\_of\_bits}#(m.#\hyperref[sailRISCVzFS]{FS}#()) == Dirty | #\hyperref[sailRISCVzextStatuszyofzybits]{extStatus\_of\_bits}#(m.#\hyperref[sailRISCVzXS]{XS}#()) == Dirty; + let m = #\hyperref[sailRISCVzupdatezySD]{update\_SD}#(m, #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(dirty)); + + /* We don't support dynamic changes to SXL and UXL. */ + let m = #\hyperref[sailRISCVzsetzymstatuszySXL]{set\_mstatus\_SXL}#(m, #\hyperref[sailRISCVzgetzymstatuszySXL]{get\_mstatus\_SXL}#(o)); + let m = #\hyperref[sailRISCVzsetzymstatuszyUXL]{set\_mstatus\_UXL}#(m, #\hyperref[sailRISCVzgetzymstatuszyUXL]{get\_mstatus\_UXL}#(o)); + + /* Hardwired to zero in the absence of 'U' or 'N'. */ + let m = if (~ (#\hyperref[sailRISCVzhaveNExt]{haveNExt}#())) then { + let m = #\hyperref[sailRISCVzupdatezyUPIE]{update\_UPIE}#(m, 0b0); + let m = #\hyperref[sailRISCVzupdatezyUIE]{update\_UIE}#(m, 0b0); + m + } else m; + + if (~ (#\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#())) then { + let m = #\hyperref[sailRISCVzupdatezyMPRV]{update\_MPRV}#(m, 0b0); + m + } else m +} diff --git a/sail_latex_riscv/fnzlegalizze_satp1fbfb541ef401311caafca983cb812d6.tex b/sail_latex_riscv/fnzlegalizze_satp1fbfb541ef401311caafca983cb812d6.tex new file mode 100644 index 00000000..0d54c1e5 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_satp1fbfb541ef401311caafca983cb812d6.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzlegalizzezysatp]{legalize\_satp}#(a : Architecture, o : xlenbits, v : xlenbits) -> xlenbits = + #\hyperref[sailRISCVzlegalizzezysatp64]{legalize\_satp64}#(a, o, v) diff --git a/sail_latex_riscv/fnzlegalizze_satp32b15f7b0d2d9380033f3e1b09fe370a61.tex b/sail_latex_riscv/fnzlegalizze_satp32b15f7b0d2d9380033f3e1b09fe370a61.tex new file mode 100644 index 00000000..9b10313f --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_satp32b15f7b0d2d9380033f3e1b09fe370a61.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzlegalizzezysatp32]{legalize\_satp32}#(a : Architecture, o : #\hyperref[sailRISCVzbits]{bits}#(32), v : #\hyperref[sailRISCVzbits]{bits}#(32)) -> #\hyperref[sailRISCVzbits]{bits}#(32) = { + /* all 32-bit satp modes are valid */ + v +} diff --git a/sail_latex_riscv/fnzlegalizze_satp64c07dfcb94af8010eb535b5f77fbb8614.tex b/sail_latex_riscv/fnzlegalizze_satp64c07dfcb94af8010eb535b5f77fbb8614.tex new file mode 100644 index 00000000..b042294a --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_satp64c07dfcb94af8010eb535b5f77fbb8614.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzlegalizzezysatp64]{legalize\_satp64}#(a : Architecture, o : #\hyperref[sailRISCVzbits]{bits}#(64), v : #\hyperref[sailRISCVzbits]{bits}#(64)) -> #\hyperref[sailRISCVzbits]{bits}#(64) = { + let s = #\hyperref[sailRISCVzMkzySatp64]{Mk\_Satp64}#(v); + match #\hyperref[sailRISCVzsatp64Modezyofzybits]{satp64Mode\_of\_bits}#(a, s.#\hyperref[sailRISCVzMode]{Mode}#()) { + #\hyperref[sailRISCVzNone]{None}#() => o, + #\hyperref[sailRISCVzSome]{Some}#(Sv32) => o, /* Sv32 is unsupported for now */ + #\hyperref[sailRISCVzSome]{Some}#(_) => s.#\hyperref[sailRISCVzbits]{bits}#() + } +} diff --git a/sail_latex_riscv/fnzlegalizze_scountereneb4feb895f759dc11e62dedd5be1c232.tex b/sail_latex_riscv/fnzlegalizze_scountereneb4feb895f759dc11e62dedd5be1c232.tex new file mode 100644 index 00000000..0e381695 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_scountereneb4feb895f759dc11e62dedd5be1c232.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzlegalizzezyscounteren]{legalize\_scounteren}#(c : Counteren, v : xlenbits) -> Counteren = { + /* no HPM counters yet */ + let c = #\hyperref[sailRISCVzupdatezyIR]{update\_IR}#(c, [v[2]]); + let c = #\hyperref[sailRISCVzupdatezyTM]{update\_TM}#(c, [v[1]]); + let c = #\hyperref[sailRISCVzupdatezyCY]{update\_CY}#(c, [v[0]]); + c +} diff --git a/sail_latex_riscv/fnzlegalizze_sedelegd33e4c93e76af1c9ae6a7795974dbcc3.tex b/sail_latex_riscv/fnzlegalizze_sedelegd33e4c93e76af1c9ae6a7795974dbcc3.tex new file mode 100644 index 00000000..162b74ee --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_sedelegd33e4c93e76af1c9ae6a7795974dbcc3.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzlegalizzezysedeleg]{legalize\_sedeleg}#(s : Sedeleg, v : xlenbits) -> Sedeleg = { + #\hyperref[sailRISCVzMkzySedeleg]{Mk\_Sedeleg}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(v[8..0])) +} diff --git a/sail_latex_riscv/fnzlegalizze_sie49baa5a30e7d5365e2d6c1dc23c7686d.tex b/sail_latex_riscv/fnzlegalizze_sie49baa5a30e7d5365e2d6c1dc23c7686d.tex new file mode 100644 index 00000000..59ede5f4 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_sie49baa5a30e7d5365e2d6c1dc23c7686d.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzlegalizzezysie]{legalize\_sie}#(m : Minterrupts, d : Minterrupts, v : xlenbits) -> Minterrupts = { + #\hyperref[sailRISCVzliftzysie]{lift\_sie}#(m, d, #\hyperref[sailRISCVzMkzySinterrupts]{Mk\_Sinterrupts}#(v)) +} diff --git a/sail_latex_riscv/fnzlegalizze_sip8870e10af087ca0981c61bf7bdfe8175.tex b/sail_latex_riscv/fnzlegalizze_sip8870e10af087ca0981c61bf7bdfe8175.tex new file mode 100644 index 00000000..4a3640d9 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_sip8870e10af087ca0981c61bf7bdfe8175.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzlegalizzezysip]{legalize\_sip}#(m : Minterrupts, d : Minterrupts, v : xlenbits) -> Minterrupts = { + #\hyperref[sailRISCVzliftzysip]{lift\_sip}#(m, d, #\hyperref[sailRISCVzMkzySinterrupts]{Mk\_Sinterrupts}#(v)) +} diff --git a/sail_latex_riscv/fnzlegalizze_sstatus6838bd21db8615a2ed1602fc6dd7f8da.tex b/sail_latex_riscv/fnzlegalizze_sstatus6838bd21db8615a2ed1602fc6dd7f8da.tex new file mode 100644 index 00000000..2f852b5b --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_sstatus6838bd21db8615a2ed1602fc6dd7f8da.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzlegalizzezysstatus]{legalize\_sstatus}#(m : Mstatus, v : xlenbits) -> Mstatus = { + #\hyperref[sailRISCVzliftzysstatus]{lift\_sstatus}#(m, #\hyperref[sailRISCVzMkzySstatus]{Mk\_Sstatus}#(v)) +} diff --git a/sail_latex_riscv/fnzlegalizze_tccfd2d2ccb3d791b05f6d62114b5036cb9.tex b/sail_latex_riscv/fnzlegalizze_tccfd2d2ccb3d791b05f6d62114b5036cb9.tex new file mode 100644 index 00000000..16ec4fe3 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_tccfd2d2ccb3d791b05f6d62114b5036cb9.tex @@ -0,0 +1,12 @@ +function #\hyperref[sailRISCVzlegalizzezytcc]{legalize\_tcc}#(o : Capability, v : Capability) -> Capability = { + new_base = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(v); + /* Ignore writes that attempt to set unaligned TCC base */ + if new_base[0] != bitzero | new_base[1] != bitzero then + o /* keep original TCC value */ + else { + /* legalize new TCC #\hyperref[sailRISCVzoffset]{offset}# (RISC-V tvec) */ + new_tvec = v.address - new_base; + legalized_tvec = #\hyperref[sailRISCVzlegalizzezytvec]{legalize\_tvec}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(#\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(o)), new_tvec); + #\hyperref[sailRISCVzsetCapOffsetOrNull]{setCapOffsetOrNull}#(v, legalized_tvec.#\hyperref[sailRISCVzbits]{bits}#()) + } +} diff --git a/sail_latex_riscv/fnzlegalizze_tvec4a108f656cfc40d55dcc9e2cd9614e5c.tex b/sail_latex_riscv/fnzlegalizze_tvec4a108f656cfc40d55dcc9e2cd9614e5c.tex new file mode 100644 index 00000000..1bb89113 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_tvec4a108f656cfc40d55dcc9e2cd9614e5c.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzlegalizzezytvec]{legalize\_tvec}#(o : Mtvec, v : xlenbits) -> Mtvec = { + let v = #\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(v); + match (#\hyperref[sailRISCVztrapVectorModezyofzybits]{trapVectorMode\_of\_bits}#(v.#\hyperref[sailRISCVzMode]{Mode}#())) { + TV_Direct => v, + TV_Vector => v, + _ => #\hyperref[sailRISCVzupdatezyMode]{update\_Mode}#(v, o.#\hyperref[sailRISCVzMode]{Mode}#()) + } +} diff --git a/sail_latex_riscv/fnzlegalizze_uie26bad63954765d654a99bf56da523d30.tex b/sail_latex_riscv/fnzlegalizze_uie26bad63954765d654a99bf56da523d30.tex new file mode 100644 index 00000000..7db9496d --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_uie26bad63954765d654a99bf56da523d30.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzlegalizzezyuie]{legalize\_uie}#(s : Sinterrupts, d : Sinterrupts, v : xlenbits) -> Sinterrupts = { + #\hyperref[sailRISCVzliftzyuie]{lift\_uie}#(s, d, #\hyperref[sailRISCVzMkzyUinterrupts]{Mk\_Uinterrupts}#(v)) +} diff --git a/sail_latex_riscv/fnzlegalizze_uipc8133dbe8104c4fd25f4a3933fa30bbb.tex b/sail_latex_riscv/fnzlegalizze_uipc8133dbe8104c4fd25f4a3933fa30bbb.tex new file mode 100644 index 00000000..7701be94 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_uipc8133dbe8104c4fd25f4a3933fa30bbb.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzlegalizzezyuip]{legalize\_uip}#(s : Sinterrupts, d : Sinterrupts, v : xlenbits) -> Sinterrupts = { + #\hyperref[sailRISCVzliftzyuip]{lift\_uip}#(s, d, #\hyperref[sailRISCVzMkzyUinterrupts]{Mk\_Uinterrupts}#(v)) +} diff --git a/sail_latex_riscv/fnzlegalizze_ustatusae91980d0571269b3dd8a4a779cb06c6.tex b/sail_latex_riscv/fnzlegalizze_ustatusae91980d0571269b3dd8a4a779cb06c6.tex new file mode 100644 index 00000000..d6704171 --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_ustatusae91980d0571269b3dd8a4a779cb06c6.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzlegalizzezyustatus]{legalize\_ustatus}#(m : Mstatus, v : xlenbits) -> Mstatus = { + let u = #\hyperref[sailRISCVzMkzyUstatus]{Mk\_Ustatus}#(v); + let s = #\hyperref[sailRISCVzlowerzymstatus]{lower\_mstatus}#(m); // lower current mstatus to sstatus + let s = #\hyperref[sailRISCVzliftzyustatus]{lift\_ustatus}#(s, u); // get updated sstatus + let m = #\hyperref[sailRISCVzliftzysstatus]{lift\_sstatus}#(m, s); // lift it to an updated mstatus + m +} diff --git a/sail_latex_riscv/fnzlegalizze_xepc8416dd9133f6232df0898ca0ae2784c2.tex b/sail_latex_riscv/fnzlegalizze_xepc8416dd9133f6232df0898ca0ae2784c2.tex new file mode 100644 index 00000000..8404292d --- /dev/null +++ b/sail_latex_riscv/fnzlegalizze_xepc8416dd9133f6232df0898ca0ae2784c2.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzlegalizzezyxepc]{legalize\_xepc}#(v : xlenbits) -> xlenbits = + /* allow writing xepc[1] only if misa.C is enabled or could be enabled + XXX specification says this legalization should be done on read */ + if (#\hyperref[sailRISCVzsyszyenablezywritablezymisa]{sys\_enable\_writable\_misa}#() & #\hyperref[sailRISCVzsyszyenablezyrvc]{sys\_enable\_rvc}#()) | misa.#\hyperref[sailRISCVzC]{C}#() == 0b1 + then [v with 0 = bitzero] + else v & #\hyperref[sailRISCVzEXTS]{EXTS}#(0b100) diff --git a/sail_latex_riscv/fnzlift_sie0866dcb30be948749bf6a401d4f6594e.tex b/sail_latex_riscv/fnzlift_sie0866dcb30be948749bf6a401d4f6594e.tex new file mode 100644 index 00000000..f546ea58 --- /dev/null +++ b/sail_latex_riscv/fnzlift_sie0866dcb30be948749bf6a401d4f6594e.tex @@ -0,0 +1,12 @@ +function #\hyperref[sailRISCVzliftzysie]{lift\_sie}#(o : Minterrupts, d : Minterrupts, s : Sinterrupts) -> Minterrupts = { + let m : Minterrupts = o; + let m = if d.#\hyperref[sailRISCVzSEI]{SEI}#() == 0b1 then #\hyperref[sailRISCVzupdatezySEI]{update\_SEI}#(m, s.#\hyperref[sailRISCVzSEI]{SEI}#()) else m; + let m = if d.#\hyperref[sailRISCVzSTI]{STI}#() == 0b1 then #\hyperref[sailRISCVzupdatezySTI]{update\_STI}#(m, s.#\hyperref[sailRISCVzSTI]{STI}#()) else m; + let m = if d.#\hyperref[sailRISCVzSSI]{SSI}#() == 0b1 then #\hyperref[sailRISCVzupdatezySSI]{update\_SSI}#(m, s.#\hyperref[sailRISCVzSSI]{SSI}#()) else m; + if #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() then { + let m = if d.#\hyperref[sailRISCVzUEI]{UEI}#() == 0b1 then #\hyperref[sailRISCVzupdatezyUEI]{update\_UEI}#(m, s.#\hyperref[sailRISCVzUEI]{UEI}#()) else m; + let m = if d.#\hyperref[sailRISCVzUTI]{UTI}#() == 0b1 then #\hyperref[sailRISCVzupdatezyUTI]{update\_UTI}#(m, s.#\hyperref[sailRISCVzUTI]{UTI}#()) else m; + let m = if d.#\hyperref[sailRISCVzUSI]{USI}#() == 0b1 then #\hyperref[sailRISCVzupdatezyUSI]{update\_USI}#(m, s.#\hyperref[sailRISCVzUSI]{USI}#()) else m; + m + } else m +} diff --git a/sail_latex_riscv/fnzlift_sip492375a8cff775f29029156b44dfe1bf.tex b/sail_latex_riscv/fnzlift_sip492375a8cff775f29029156b44dfe1bf.tex new file mode 100644 index 00000000..8c54735e --- /dev/null +++ b/sail_latex_riscv/fnzlift_sip492375a8cff775f29029156b44dfe1bf.tex @@ -0,0 +1,9 @@ +function #\hyperref[sailRISCVzliftzysip]{lift\_sip}#(o : Minterrupts, d : Minterrupts, s : Sinterrupts) -> Minterrupts = { + let m : Minterrupts = o; + let m = #\hyperref[sailRISCVzupdatezySSI]{update\_SSI}#(m, s.#\hyperref[sailRISCVzSSI]{SSI}#() & d.#\hyperref[sailRISCVzSSI]{SSI}#()); + if #\hyperref[sailRISCVzhaveNExt]{haveNExt}#() then { + let m = if d.#\hyperref[sailRISCVzUEI]{UEI}#() == 0b1 then #\hyperref[sailRISCVzupdatezyUEI]{update\_UEI}#(m, s.#\hyperref[sailRISCVzUEI]{UEI}#()) else m; + let m = if d.#\hyperref[sailRISCVzUSI]{USI}#() == 0b1 then #\hyperref[sailRISCVzupdatezyUSI]{update\_USI}#(m, s.#\hyperref[sailRISCVzUSI]{USI}#()) else m; + m + } else m +} diff --git a/sail_latex_riscv/fnzlift_sstatus8b6865e3f513094f03fd5bfc83d2ed77.tex b/sail_latex_riscv/fnzlift_sstatus8b6865e3f513094f03fd5bfc83d2ed77.tex new file mode 100644 index 00000000..5baeba67 --- /dev/null +++ b/sail_latex_riscv/fnzlift_sstatus8b6865e3f513094f03fd5bfc83d2ed77.tex @@ -0,0 +1,17 @@ +function #\hyperref[sailRISCVzliftzysstatus]{lift\_sstatus}#(m : Mstatus, s : Sstatus) -> Mstatus = { + let m = #\hyperref[sailRISCVzupdatezyMXR]{update\_MXR}#(m, s.#\hyperref[sailRISCVzMXR]{MXR}#()); + let m = #\hyperref[sailRISCVzupdatezySUM]{update\_SUM}#(m, s.#\hyperref[sailRISCVzSUM]{SUM}#()); + + let m = #\hyperref[sailRISCVzupdatezyXS]{update\_XS}#(m, s.#\hyperref[sailRISCVzXS]{XS}#()); + // See comment for mstatus.FS. + let m = #\hyperref[sailRISCVzupdatezyFS]{update\_FS}#(m, s.#\hyperref[sailRISCVzFS]{FS}#()); + let dirty = #\hyperref[sailRISCVzextStatuszyofzybits]{extStatus\_of\_bits}#(m.#\hyperref[sailRISCVzFS]{FS}#()) == Dirty | #\hyperref[sailRISCVzextStatuszyofzybits]{extStatus\_of\_bits}#(m.#\hyperref[sailRISCVzXS]{XS}#()) == Dirty; + let m = #\hyperref[sailRISCVzupdatezySD]{update\_SD}#(m, #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(dirty)); + + let m = #\hyperref[sailRISCVzupdatezySPP]{update\_SPP}#(m, s.#\hyperref[sailRISCVzSPP]{SPP}#()); + let m = #\hyperref[sailRISCVzupdatezySPIE]{update\_SPIE}#(m, s.#\hyperref[sailRISCVzSPIE]{SPIE}#()); + let m = #\hyperref[sailRISCVzupdatezyUPIE]{update\_UPIE}#(m, s.#\hyperref[sailRISCVzUPIE]{UPIE}#()); + let m = #\hyperref[sailRISCVzupdatezySIE]{update\_SIE}#(m, s.#\hyperref[sailRISCVzSIE]{SIE}#()); + let m = #\hyperref[sailRISCVzupdatezyUIE]{update\_UIE}#(m, s.#\hyperref[sailRISCVzUIE]{UIE}#()); + m +} diff --git a/sail_latex_riscv/fnzlift_uied44a5d7049b27cdb894913f74634a628.tex b/sail_latex_riscv/fnzlift_uied44a5d7049b27cdb894913f74634a628.tex new file mode 100644 index 00000000..e71087d9 --- /dev/null +++ b/sail_latex_riscv/fnzlift_uied44a5d7049b27cdb894913f74634a628.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzliftzyuie]{lift\_uie}#(o : Sinterrupts, d : Sinterrupts, u : Uinterrupts) -> Sinterrupts = { + let s : Sinterrupts = o; + let s = if d.#\hyperref[sailRISCVzUEI]{UEI}#() == 0b1 then #\hyperref[sailRISCVzupdatezyUEI]{update\_UEI}#(s, u.#\hyperref[sailRISCVzUEI]{UEI}#()) else s; + let s = if d.#\hyperref[sailRISCVzUTI]{UTI}#() == 0b1 then #\hyperref[sailRISCVzupdatezyUTI]{update\_UTI}#(s, u.#\hyperref[sailRISCVzUTI]{UTI}#()) else s; + let s = if d.#\hyperref[sailRISCVzUSI]{USI}#() == 0b1 then #\hyperref[sailRISCVzupdatezyUSI]{update\_USI}#(s, u.#\hyperref[sailRISCVzUSI]{USI}#()) else s; + s +} diff --git a/sail_latex_riscv/fnzlift_uipc541c535c8821c63ef55fd81254b1078.tex b/sail_latex_riscv/fnzlift_uipc541c535c8821c63ef55fd81254b1078.tex new file mode 100644 index 00000000..672d6ac0 --- /dev/null +++ b/sail_latex_riscv/fnzlift_uipc541c535c8821c63ef55fd81254b1078.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzliftzyuip]{lift\_uip}#(o : Sinterrupts, d : Sinterrupts, u : Uinterrupts) -> Sinterrupts = { + let s : Sinterrupts = o; + let s = if d.#\hyperref[sailRISCVzUSI]{USI}#() == 0b1 then #\hyperref[sailRISCVzupdatezyUSI]{update\_USI}#(s, u.#\hyperref[sailRISCVzUSI]{USI}#()) else s; + s +} diff --git a/sail_latex_riscv/fnzlift_ustatus9f7d2e2291fdb3a746dca97290479c47.tex b/sail_latex_riscv/fnzlift_ustatus9f7d2e2291fdb3a746dca97290479c47.tex new file mode 100644 index 00000000..1ca2746c --- /dev/null +++ b/sail_latex_riscv/fnzlift_ustatus9f7d2e2291fdb3a746dca97290479c47.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzliftzyustatus]{lift\_ustatus}#(s : Sstatus, u : Ustatus) -> Sstatus = { + let s = #\hyperref[sailRISCVzupdatezyUPIE]{update\_UPIE}#(s, u.#\hyperref[sailRISCVzUPIE]{UPIE}#()); + let s = #\hyperref[sailRISCVzupdatezyUIE]{update\_UIE}#(s, u.#\hyperref[sailRISCVzUIE]{UIE}#()); + s +} diff --git a/sail_latex_riscv/fnzlookup_tlb39701cebd3fa43ee6815ecaa975a199f5b.tex b/sail_latex_riscv/fnzlookup_tlb39701cebd3fa43ee6815ecaa975a199f5b.tex new file mode 100644 index 00000000..90e6e55e --- /dev/null +++ b/sail_latex_riscv/fnzlookup_tlb39701cebd3fa43ee6815ecaa975a199f5b.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzlookupzyTLB39]{lookup\_TLB39}#(asid, vaddr) = + match tlb39 { + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzNone]{None}#(), + #\hyperref[sailRISCVzSome]{Some}#(e) => if #\hyperref[sailRISCVzmatchzyTLBzyEntry]{match\_TLB\_Entry}#(e, asid, vaddr) then #\hyperref[sailRISCVzSome]{Some}#((0, e)) else #\hyperref[sailRISCVzNone]{None}#() + } diff --git a/sail_latex_riscv/fnzlookup_tlb481be2085cbc29568c5c522b87bd854b70.tex b/sail_latex_riscv/fnzlookup_tlb481be2085cbc29568c5c522b87bd854b70.tex new file mode 100644 index 00000000..e8f27bd1 --- /dev/null +++ b/sail_latex_riscv/fnzlookup_tlb481be2085cbc29568c5c522b87bd854b70.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzlookupzyTLB48]{lookup\_TLB48}#(asid, vaddr) = + match tlb48 { + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzNone]{None}#(), + #\hyperref[sailRISCVzSome]{Some}#(e) => if #\hyperref[sailRISCVzmatchzyTLBzyEntry]{match\_TLB\_Entry}#(e, asid, vaddr) then #\hyperref[sailRISCVzSome]{Some}#((0, e)) else #\hyperref[sailRISCVzNone]{None}#() + } diff --git a/sail_latex_riscv/fnzloop939222c31aec6e03415219d7c5a4ee7a.tex b/sail_latex_riscv/fnzloop939222c31aec6e03415219d7c5a4ee7a.tex new file mode 100644 index 00000000..5fc018db --- /dev/null +++ b/sail_latex_riscv/fnzloop939222c31aec6e03415219d7c5a4ee7a.tex @@ -0,0 +1,25 @@ +function #\hyperref[sailRISCVzloop]{loop}# () : unit -> unit = { + let insns_per_tick = #\hyperref[sailRISCVzplatzyinsnszyperzytick]{plat\_insns\_per\_tick}#(); + i : int = 0; + step_no : int = 0; + #\hyperref[sailRISCVzwhile]{while}# (~ (htif_done)) do { + let stepped = #\hyperref[sailRISCVzstep]{step}#(step_no); + if stepped then step_no = step_no + 1; + + /* check htif exit */ + if htif_done then { + let exit_val = #\hyperref[sailRISCVzunsigned]{unsigned}#(htif_exit_code); + if exit_val == 0 then #\hyperref[sailRISCVzprint]{print}#("SUCCESS") + else #\hyperref[sailRISCVzprintzyint]{print\_int}#("FAILURE: ", exit_val); + } else { + /* update time */ + i = i + 1; + if i == insns_per_tick then { + #\hyperref[sailRISCVztickzyclock]{tick\_clock}#(); + /* for now, we drive the platform i/o at every clock tick. */ + #\hyperref[sailRISCVztickzyplatform]{tick\_platform}#(); + i = 0; + } + } + } +} diff --git a/sail_latex_riscv/fnzlower_mie31369302ff2457befa23f7f9d54a6b02.tex b/sail_latex_riscv/fnzlower_mie31369302ff2457befa23f7f9d54a6b02.tex new file mode 100644 index 00000000..a8e9d33a --- /dev/null +++ b/sail_latex_riscv/fnzlower_mie31369302ff2457befa23f7f9d54a6b02.tex @@ -0,0 +1,10 @@ +function #\hyperref[sailRISCVzlowerzymie]{lower\_mie}#(m : Minterrupts, d : Minterrupts) -> Sinterrupts = { + let s : Sinterrupts = #\hyperref[sailRISCVzMkzySinterrupts]{Mk\_Sinterrupts}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0)); + let s = #\hyperref[sailRISCVzupdatezySEI]{update\_SEI}#(s, m.#\hyperref[sailRISCVzSEI]{SEI}#() & d.#\hyperref[sailRISCVzSEI]{SEI}#()); + let s = #\hyperref[sailRISCVzupdatezySTI]{update\_STI}#(s, m.#\hyperref[sailRISCVzSTI]{STI}#() & d.#\hyperref[sailRISCVzSTI]{STI}#()); + let s = #\hyperref[sailRISCVzupdatezySSI]{update\_SSI}#(s, m.#\hyperref[sailRISCVzSSI]{SSI}#() & d.#\hyperref[sailRISCVzSSI]{SSI}#()); + let s = #\hyperref[sailRISCVzupdatezyUEI]{update\_UEI}#(s, m.#\hyperref[sailRISCVzUEI]{UEI}#() & d.#\hyperref[sailRISCVzUEI]{UEI}#()); + let s = #\hyperref[sailRISCVzupdatezyUTI]{update\_UTI}#(s, m.#\hyperref[sailRISCVzUTI]{UTI}#() & d.#\hyperref[sailRISCVzUTI]{UTI}#()); + let s = #\hyperref[sailRISCVzupdatezyUSI]{update\_USI}#(s, m.#\hyperref[sailRISCVzUSI]{USI}#() & d.#\hyperref[sailRISCVzUSI]{USI}#()); + s +} diff --git a/sail_latex_riscv/fnzlower_mip782f0e78d1db1ca14e49fae5b84aab3a.tex b/sail_latex_riscv/fnzlower_mip782f0e78d1db1ca14e49fae5b84aab3a.tex new file mode 100644 index 00000000..466d4844 --- /dev/null +++ b/sail_latex_riscv/fnzlower_mip782f0e78d1db1ca14e49fae5b84aab3a.tex @@ -0,0 +1,11 @@ +function #\hyperref[sailRISCVzlowerzymip]{lower\_mip}#(m : Minterrupts, d : Minterrupts) -> Sinterrupts = { + let s : Sinterrupts = #\hyperref[sailRISCVzMkzySinterrupts]{Mk\_Sinterrupts}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0)); + let s = #\hyperref[sailRISCVzupdatezySEI]{update\_SEI}#(s, m.#\hyperref[sailRISCVzSEI]{SEI}#() & d.#\hyperref[sailRISCVzSEI]{SEI}#()); + let s = #\hyperref[sailRISCVzupdatezySTI]{update\_STI}#(s, m.#\hyperref[sailRISCVzSTI]{STI}#() & d.#\hyperref[sailRISCVzSTI]{STI}#()); + let s = #\hyperref[sailRISCVzupdatezySSI]{update\_SSI}#(s, m.#\hyperref[sailRISCVzSSI]{SSI}#() & d.#\hyperref[sailRISCVzSSI]{SSI}#()); + + let s = #\hyperref[sailRISCVzupdatezyUEI]{update\_UEI}#(s, m.#\hyperref[sailRISCVzUEI]{UEI}#() & d.#\hyperref[sailRISCVzUEI]{UEI}#()); + let s = #\hyperref[sailRISCVzupdatezyUTI]{update\_UTI}#(s, m.#\hyperref[sailRISCVzUTI]{UTI}#() & d.#\hyperref[sailRISCVzUTI]{UTI}#()); + let s = #\hyperref[sailRISCVzupdatezyUSI]{update\_USI}#(s, m.#\hyperref[sailRISCVzUSI]{USI}#() & d.#\hyperref[sailRISCVzUSI]{USI}#()); + s +} diff --git a/sail_latex_riscv/fnzlower_mstatuse71dfbedf80129bee76a841456768dd1.tex b/sail_latex_riscv/fnzlower_mstatuse71dfbedf80129bee76a841456768dd1.tex new file mode 100644 index 00000000..6cfa4f7f --- /dev/null +++ b/sail_latex_riscv/fnzlower_mstatuse71dfbedf80129bee76a841456768dd1.tex @@ -0,0 +1,15 @@ +function #\hyperref[sailRISCVzlowerzymstatus]{lower\_mstatus}#(m : Mstatus) -> Sstatus = { + let s = #\hyperref[sailRISCVzMkzySstatus]{Mk\_Sstatus}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0)); + let s = #\hyperref[sailRISCVzupdatezySD]{update\_SD}#(s, m.#\hyperref[sailRISCVzSD]{SD}#()); + let s = #\hyperref[sailRISCVzsetzysstatuszyUXL]{set\_sstatus\_UXL}#(s, #\hyperref[sailRISCVzgetzymstatuszyUXL]{get\_mstatus\_UXL}#(m)); + let s = #\hyperref[sailRISCVzupdatezyMXR]{update\_MXR}#(s, m.#\hyperref[sailRISCVzMXR]{MXR}#()); + let s = #\hyperref[sailRISCVzupdatezySUM]{update\_SUM}#(s, m.#\hyperref[sailRISCVzSUM]{SUM}#()); + let s = #\hyperref[sailRISCVzupdatezyXS]{update\_XS}#(s, m.#\hyperref[sailRISCVzXS]{XS}#()); + let s = #\hyperref[sailRISCVzupdatezyFS]{update\_FS}#(s, m.#\hyperref[sailRISCVzFS]{FS}#()); + let s = #\hyperref[sailRISCVzupdatezySPP]{update\_SPP}#(s, m.#\hyperref[sailRISCVzSPP]{SPP}#()); + let s = #\hyperref[sailRISCVzupdatezySPIE]{update\_SPIE}#(s, m.#\hyperref[sailRISCVzSPIE]{SPIE}#()); + let s = #\hyperref[sailRISCVzupdatezyUPIE]{update\_UPIE}#(s, m.#\hyperref[sailRISCVzUPIE]{UPIE}#()); + let s = #\hyperref[sailRISCVzupdatezySIE]{update\_SIE}#(s, m.#\hyperref[sailRISCVzSIE]{SIE}#()); + let s = #\hyperref[sailRISCVzupdatezyUIE]{update\_UIE}#(s, m.#\hyperref[sailRISCVzUIE]{UIE}#()); + s +} diff --git a/sail_latex_riscv/fnzlower_siea6b1bfe3227230c0b4c5a544f98a7636.tex b/sail_latex_riscv/fnzlower_siea6b1bfe3227230c0b4c5a544f98a7636.tex new file mode 100644 index 00000000..1ce01c4f --- /dev/null +++ b/sail_latex_riscv/fnzlower_siea6b1bfe3227230c0b4c5a544f98a7636.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzlowerzysie]{lower\_sie}#(s : Sinterrupts, d : Sinterrupts) -> Uinterrupts = { + let u : Uinterrupts = #\hyperref[sailRISCVzMkzyUinterrupts]{Mk\_Uinterrupts}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0)); + let u = #\hyperref[sailRISCVzupdatezyUEI]{update\_UEI}#(u, s.#\hyperref[sailRISCVzUEI]{UEI}#() & d.#\hyperref[sailRISCVzUEI]{UEI}#()); + let u = #\hyperref[sailRISCVzupdatezyUTI]{update\_UTI}#(u, s.#\hyperref[sailRISCVzUTI]{UTI}#() & d.#\hyperref[sailRISCVzUTI]{UTI}#()); + let u = #\hyperref[sailRISCVzupdatezyUSI]{update\_USI}#(u, s.#\hyperref[sailRISCVzUSI]{USI}#() & d.#\hyperref[sailRISCVzUSI]{USI}#()); + u +} diff --git a/sail_latex_riscv/fnzlower_sipfb2971a9ef35ea1e2a4c00f905ec894c.tex b/sail_latex_riscv/fnzlower_sipfb2971a9ef35ea1e2a4c00f905ec894c.tex new file mode 100644 index 00000000..b4fb2e4c --- /dev/null +++ b/sail_latex_riscv/fnzlower_sipfb2971a9ef35ea1e2a4c00f905ec894c.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzlowerzysip]{lower\_sip}#(s : Sinterrupts, d : Sinterrupts) -> Uinterrupts = { + let u : Uinterrupts = #\hyperref[sailRISCVzMkzyUinterrupts]{Mk\_Uinterrupts}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0)); + let u = #\hyperref[sailRISCVzupdatezyUEI]{update\_UEI}#(u, s.#\hyperref[sailRISCVzUEI]{UEI}#() & d.#\hyperref[sailRISCVzUEI]{UEI}#()); + let u = #\hyperref[sailRISCVzupdatezyUTI]{update\_UTI}#(u, s.#\hyperref[sailRISCVzUTI]{UTI}#() & d.#\hyperref[sailRISCVzUTI]{UTI}#()); + let u = #\hyperref[sailRISCVzupdatezyUSI]{update\_USI}#(u, s.#\hyperref[sailRISCVzUSI]{USI}#() & d.#\hyperref[sailRISCVzUSI]{USI}#()); + u +} diff --git a/sail_latex_riscv/fnzlower_sstatusee8227db3ac1f80e02871989d3ac7837.tex b/sail_latex_riscv/fnzlower_sstatusee8227db3ac1f80e02871989d3ac7837.tex new file mode 100644 index 00000000..0c21c610 --- /dev/null +++ b/sail_latex_riscv/fnzlower_sstatusee8227db3ac1f80e02871989d3ac7837.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzlowerzysstatus]{lower\_sstatus}#(s : Sstatus) -> Ustatus = { + let u = #\hyperref[sailRISCVzMkzyUstatus]{Mk\_Ustatus}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0)); + let u = #\hyperref[sailRISCVzupdatezyUPIE]{update\_UPIE}#(u, s.#\hyperref[sailRISCVzUPIE]{UPIE}#()); + let u = #\hyperref[sailRISCVzupdatezyUIE]{update\_UIE}#(u, s.#\hyperref[sailRISCVzUIE]{UIE}#()); + u +} diff --git a/sail_latex_riscv/fnzlrsc_width_str1a32b7e5b18a83477d13203cd0eca601.tex b/sail_latex_riscv/fnzlrsc_width_str1a32b7e5b18a83477d13203cd0eca601.tex new file mode 100644 index 00000000..b99ed39f --- /dev/null +++ b/sail_latex_riscv/fnzlrsc_width_str1a32b7e5b18a83477d13203cd0eca601.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzlrsczywidthzystr]{lrsc\_width\_str}#(width : word_width) -> string = + match (width) { + BYTE => ".b", + HALF => ".h", + WORD => ".w", + DOUBLE => ".d" + } diff --git a/sail_latex_riscv/fnzmake_tlb_entry6b22aedb2f264f70f3e1bd2d5dd6f057.tex b/sail_latex_riscv/fnzmake_tlb_entry6b22aedb2f264f70f3e1bd2d5dd6f057.tex new file mode 100644 index 00000000..8c45d7dd --- /dev/null +++ b/sail_latex_riscv/fnzmake_tlb_entry6b22aedb2f264f70f3e1bd2d5dd6f057.tex @@ -0,0 +1,17 @@ +function #\hyperref[sailRISCVzmakezyTLBzyEntry]{make\_TLB\_Entry}#(asid, global, vAddr, pAddr, pte, level, pteAddr, levelBitSize) = { + let shift : nat = PAGESIZE_BITS + (level * levelBitSize); + /* fixme hack: use a better idiom for masks */ + let vAddrMask : #\hyperref[sailRISCVzbits]{bits}#('valen) = #\hyperref[sailRISCVzshiftl]{shiftl}#(vAddr ^ vAddr ^ #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1), shift) - 1; + let vMatchMask : #\hyperref[sailRISCVzbits]{bits}#('valen) = ~ (vAddrMask); + struct { + asid = asid, + global = global, + pte = pte, + pteAddr = pteAddr, + vAddrMask = vAddrMask, + vMatchMask = vMatchMask, + vAddr = vAddr & vMatchMask, + pAddr = #\hyperref[sailRISCVzshiftl]{shiftl}#(#\hyperref[sailRISCVzshiftr]{shiftr}#(pAddr, shift), shift), + age = mcycle + } +} diff --git a/sail_latex_riscv/fnzmatch_tlb_entry15cb314356c461bfc7d1b30f45fecb98.tex b/sail_latex_riscv/fnzmatch_tlb_entry15cb314356c461bfc7d1b30f45fecb98.tex new file mode 100644 index 00000000..9573f07e --- /dev/null +++ b/sail_latex_riscv/fnzmatch_tlb_entry15cb314356c461bfc7d1b30f45fecb98.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzmatchzyTLBzyEntry]{match\_TLB\_Entry}#(ent, asid, vaddr) = + (ent.global | (ent.asid == asid)) & (ent.vAddr == (ent.vMatchMask & vaddr)) diff --git a/sail_latex_riscv/fnzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex b/sail_latex_riscv/fnzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex new file mode 100644 index 00000000..bb27c6cb --- /dev/null +++ b/sail_latex_riscv/fnzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzMAX]{MAX}#(n) = #\hyperref[sailRISCVzpow2]{pow2}#(n) - 1 diff --git a/sail_latex_riscv/fnzmem_read_cap518c2935d72d61e3ceee2abb80c9fce5.tex b/sail_latex_riscv/fnzmem_read_cap518c2935d72d61e3ceee2abb80c9fce5.tex new file mode 100644 index 00000000..e8be27e1 --- /dev/null +++ b/sail_latex_riscv/fnzmem_read_cap518c2935d72d61e3ceee2abb80c9fce5.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzmemzyreadzycap]{mem\_read\_cap}# (addr, aq, rl, res) = { + let result : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#((CapBits, bool)) = #\hyperref[sailRISCVzmemzyreadzymeta]{mem\_read\_meta}#(#\hyperref[sailRISCVzRead]{Read}#(Data), addr, cap_size, aq, rl, res, true); + match result { + #\hyperref[sailRISCVzMemValue]{MemValue}#(v, tag) => #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzmemBitsToCapability]{memBitsToCapability}#(tag, v)), + #\hyperref[sailRISCVzMemException]{MemException}#(e) => #\hyperref[sailRISCVzMemException]{MemException}#(e) : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(Capability) + } +} diff --git a/sail_latex_riscv/fnzmem_read_metaa66233a97620233d3f80f4bf1a13c232.tex b/sail_latex_riscv/fnzmem_read_metaa66233a97620233d3f80f4bf1a13c232.tex new file mode 100644 index 00000000..f57b1615 --- /dev/null +++ b/sail_latex_riscv/fnzmem_read_metaa66233a97620233d3f80f4bf1a13c232.tex @@ -0,0 +1,12 @@ +function #\hyperref[sailRISCVzmemzyreadzymeta]{mem\_read\_meta}# (typ, paddr, width, aq, rl, res, meta) = { + let result : #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#((#\hyperref[sailRISCVzbits]{bits}#(8 * 'n), mem_meta)) = + if (aq | res) & (~ (#\hyperref[sailRISCVziszyalignedzyaddr]{is\_aligned\_addr}#(paddr, width))) + then #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzyLoadzyAddrzyAlign]{E\_Load\_Addr\_Align}#()) + else match (aq, rl, res) { + (false, true, false) => throw(#\hyperref[sailRISCVzErrorzynotzyimplemented]{Error\_not\_implemented}#("load.rl")), + (false, true, true) => throw(#\hyperref[sailRISCVzErrorzynotzyimplemented]{Error\_not\_implemented}#("lr.rl")), + (_, _, _) => #\hyperref[sailRISCVzpmpzymemzyread]{pmp\_mem\_read}#(typ, paddr, width, aq, rl, res, meta) + }; + #\hyperref[sailRISCVzrvfizyread]{rvfi\_read}#(paddr, width, #\hyperref[sailRISCVzMemoryOpResultzydropzymeta]{MemoryOpResult\_drop\_meta}#(result)); + result +} diff --git a/sail_latex_riscv/fnzmem_readbc59b9b8e622af015b97ceb8dcd5c69e.tex b/sail_latex_riscv/fnzmem_readbc59b9b8e622af015b97ceb8dcd5c69e.tex new file mode 100644 index 00000000..24cd7648 --- /dev/null +++ b/sail_latex_riscv/fnzmem_readbc59b9b8e622af015b97ceb8dcd5c69e.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzmemzyread]{mem\_read}# (typ, paddr, width, aq, rl, res) = + #\hyperref[sailRISCVzMemoryOpResultzydropzymeta]{MemoryOpResult\_drop\_meta}#(#\hyperref[sailRISCVzmemzyreadzymeta]{mem\_read\_meta}#(typ, paddr, width, aq, rl, res, false)) diff --git a/sail_latex_riscv/fnzmem_write_cap1a1d6143df72b48afdcbdae2e99e77f4.tex b/sail_latex_riscv/fnzmem_write_cap1a1d6143df72b48afdcbdae2e99e77f4.tex new file mode 100644 index 00000000..680deecc --- /dev/null +++ b/sail_latex_riscv/fnzmem_write_cap1a1d6143df72b48afdcbdae2e99e77f4.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzmemzywritezycap]{mem\_write\_cap}# (addr, cap, aq, rl, con) = { + let cap_bits = #\hyperref[sailRISCVzcapToMemBits]{capToMemBits}#(cap); + /* Assume that conversion to bits and back does not change the capability. + TODO: State closed-form normalised-ness criterion that implies this, + and prove it as an invariant of capabilities in the system. */ + assert(#\hyperref[sailRISCVzmemBitsToCapability]{memBitsToCapability}#(cap.tag, cap_bits) == cap); + #\hyperref[sailRISCVzmemzywritezyvaluezymeta]{mem\_write\_value\_meta}#(addr, cap_size, cap_bits, Cap, cap.tag, aq, rl, con) +} diff --git a/sail_latex_riscv/fnzmem_write_ea_capaa2cfa0cf86165d13bd79024ad44b71d.tex b/sail_latex_riscv/fnzmem_write_ea_capaa2cfa0cf86165d13bd79024ad44b71d.tex new file mode 100644 index 00000000..b174daaf --- /dev/null +++ b/sail_latex_riscv/fnzmem_write_ea_capaa2cfa0cf86165d13bd79024ad44b71d.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzmemzywritezyeazycap]{mem\_write\_ea\_cap}#(addr, aq, rl, con) = { + if ~(#\hyperref[sailRISCVziszyalignedzyaddr]{is\_aligned\_addr}#(addr, cap_size)) + then #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#()) + else #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzzyzywritezymemzyea]{\_\_write\_mem\_ea}#(Write_plain, sizeof(xlen), addr, cap_size)) // FIXME: is Write_plain correct? +} diff --git a/sail_latex_riscv/fnzmem_write_eaf1486ee81ccf925e874de8977b0270e9.tex b/sail_latex_riscv/fnzmem_write_eaf1486ee81ccf925e874de8977b0270e9.tex new file mode 100644 index 00000000..d664f7d5 --- /dev/null +++ b/sail_latex_riscv/fnzmem_write_eaf1486ee81ccf925e874de8977b0270e9.tex @@ -0,0 +1,14 @@ +function #\hyperref[sailRISCVzmemzywritezyea]{mem\_write\_ea}# (addr, width, aq, rl, con) = { + if (rl | con) & (~ (#\hyperref[sailRISCVziszyalignedzyaddr]{is\_aligned\_addr}#(addr, width))) + then #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#()) + else match (aq, rl, con) { + (false, false, false) => #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzwritezyramzyea]{write\_ram\_ea}#(Write_plain, addr, width)), + (false, true, false) => #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzwritezyramzyea]{write\_ram\_ea}#(Write_RISCV_release, addr, width)), + (false, false, true) => #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzwritezyramzyea]{write\_ram\_ea}#(Write_RISCV_conditional, addr, width)), + (false, true , true) => #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzwritezyramzyea]{write\_ram\_ea}#(Write_RISCV_conditional_release, addr, width)), + (true, false, false) => throw(#\hyperref[sailRISCVzErrorzynotzyimplemented]{Error\_not\_implemented}#("store.aq")), + (true, true, false) => #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzwritezyramzyea]{write\_ram\_ea}#(Write_RISCV_strong_release, addr, width)), + (true, false, true) => throw(#\hyperref[sailRISCVzErrorzynotzyimplemented]{Error\_not\_implemented}#("sc.aq")), + (true, true , true) => #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzwritezyramzyea]{write\_ram\_ea}#(Write_RISCV_conditional_strong_release, addr, width)) + } +} diff --git a/sail_latex_riscv/fnzmem_write_value_meta586f37dd78d9b5be2a948e83778e6186.tex b/sail_latex_riscv/fnzmem_write_value_meta586f37dd78d9b5be2a948e83778e6186.tex new file mode 100644 index 00000000..d52f1067 --- /dev/null +++ b/sail_latex_riscv/fnzmem_write_value_meta586f37dd78d9b5be2a948e83778e6186.tex @@ -0,0 +1,16 @@ +function #\hyperref[sailRISCVzmemzywritezyvaluezymeta]{mem\_write\_value\_meta}# (paddr, width, value, ext_acc, meta, aq, rl, con) = { + #\hyperref[sailRISCVzrvfizywrite]{rvfi\_write}#(paddr, width, value); + if (rl | con) & (~ (#\hyperref[sailRISCVziszyalignedzyaddr]{is\_aligned\_addr}#(paddr, width))) + then #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#()) + else match (aq, rl, con) { + (false, false, false) => #\hyperref[sailRISCVzpmpzymemzywrite]{pmp\_mem\_write}#(Write_plain, paddr, width, value, ext_acc, meta), + (false, true, false) => #\hyperref[sailRISCVzpmpzymemzywrite]{pmp\_mem\_write}#(Write_RISCV_release, paddr, width, value, ext_acc, meta), + (false, false, true) => #\hyperref[sailRISCVzpmpzymemzywrite]{pmp\_mem\_write}#(Write_RISCV_conditional, paddr, width, value, ext_acc, meta), + (false, true , true) => #\hyperref[sailRISCVzpmpzymemzywrite]{pmp\_mem\_write}#(Write_RISCV_conditional_release, paddr, width, value, ext_acc, meta), + (true, true, false) => #\hyperref[sailRISCVzpmpzymemzywrite]{pmp\_mem\_write}#(Write_RISCV_strong_release, paddr, width, value, ext_acc, meta), + (true, true , true) => #\hyperref[sailRISCVzpmpzymemzywrite]{pmp\_mem\_write}#(Write_RISCV_conditional_strong_release, paddr, width, value, ext_acc, meta), + // throw an illegal instruction here? + (true, false, false) => throw(#\hyperref[sailRISCVzErrorzynotzyimplemented]{Error\_not\_implemented}#("store.aq")), + (true, false, true) => throw(#\hyperref[sailRISCVzErrorzynotzyimplemented]{Error\_not\_implemented}#("sc.aq")) + } +} diff --git a/sail_latex_riscv/fnzmem_write_valuec32f59efd2dcb7ea78ea4c9778bdf2e1.tex b/sail_latex_riscv/fnzmem_write_valuec32f59efd2dcb7ea78ea4c9778bdf2e1.tex new file mode 100644 index 00000000..2e7579be --- /dev/null +++ b/sail_latex_riscv/fnzmem_write_valuec32f59efd2dcb7ea78ea4c9778bdf2e1.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}# (paddr, width, value, aq, rl, con) = + #\hyperref[sailRISCVzmemzywritezyvaluezymeta]{mem\_write\_value\_meta}#(paddr, width, value, default_write_acc, default_meta, aq, rl, con) diff --git a/sail_latex_riscv/fnzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex b/sail_latex_riscv/fnzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex new file mode 100644 index 00000000..4efb2787 --- /dev/null +++ b/sail_latex_riscv/fnzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzmemBitsToCapability]{memBitsToCapability}#(tag, b) : (bool, CapBits) -> Capability = + #\hyperref[sailRISCVzcapBitsToCapability]{capBitsToCapability}#(tag, b ^ null_cap_bits) diff --git a/sail_latex_riscv/fnzmemoryopresult_add_meta6f4337fb08e42f593b3375a2d1083593.tex b/sail_latex_riscv/fnzmemoryopresult_add_meta6f4337fb08e42f593b3375a2d1083593.tex new file mode 100644 index 00000000..c2f4b59e --- /dev/null +++ b/sail_latex_riscv/fnzmemoryopresult_add_meta6f4337fb08e42f593b3375a2d1083593.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzMemoryOpResultzyaddzymeta]{MemoryOpResult\_add\_meta}#(r, m) = match r { + #\hyperref[sailRISCVzMemValue]{MemValue}#(v) => #\hyperref[sailRISCVzMemValue]{MemValue}#(v, m), + #\hyperref[sailRISCVzMemException]{MemException}#(e) => #\hyperref[sailRISCVzMemException]{MemException}#(e) +} diff --git a/sail_latex_riscv/fnzmemoryopresult_drop_metafa9388b5fdd8fbe880aa4e686c59bab1.tex b/sail_latex_riscv/fnzmemoryopresult_drop_metafa9388b5fdd8fbe880aa4e686c59bab1.tex new file mode 100644 index 00000000..ef7e1265 --- /dev/null +++ b/sail_latex_riscv/fnzmemoryopresult_drop_metafa9388b5fdd8fbe880aa4e686c59bab1.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzMemoryOpResultzydropzymeta]{MemoryOpResult\_drop\_meta}#(r) = match r { + #\hyperref[sailRISCVzMemValue]{MemValue}#(v, m) => #\hyperref[sailRISCVzMemValue]{MemValue}#(v), + #\hyperref[sailRISCVzMemException]{MemException}#(e) => #\hyperref[sailRISCVzMemException]{MemException}#(e) +} diff --git a/sail_latex_riscv/fnzmin_instruction_bytesb10dab453fbe2e946cf3f20de7511e71.tex b/sail_latex_riscv/fnzmin_instruction_bytesb10dab453fbe2e946cf3f20de7511e71.tex new file mode 100644 index 00000000..4154341c --- /dev/null +++ b/sail_latex_riscv/fnzmin_instruction_bytesb10dab453fbe2e946cf3f20de7511e71.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzminzyinstructionzybytes]{min\_instruction\_bytes}# () -> CapAddrInt = { + if (~ (#\hyperref[sailRISCVzsyszyenablezywritablezymisa]{sys\_enable\_writable\_misa}# ())) & (~ (#\hyperref[sailRISCVzsyszyenablezyrvc]{sys\_enable\_rvc}# ())) + then 4 /* RVC is hardwired to be disabled */ + else 2 /* RVC is active or it could become active */ +} diff --git a/sail_latex_riscv/fnzmk_ccsre3234e42694bb21773ea7b0780c04af8.tex b/sail_latex_riscv/fnzmk_ccsre3234e42694bb21773ea7b0780c04af8.tex new file mode 100644 index 00000000..7c51a10b --- /dev/null +++ b/sail_latex_riscv/fnzmk_ccsre3234e42694bb21773ea7b0780c04af8.tex @@ -0,0 +1 @@ +function Mk_ccsr v = struct { ccsr_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_counterenf15701a312ca5765a184f9c5e5a93c32.tex b/sail_latex_riscv/fnzmk_counterenf15701a312ca5765a184f9c5e5a93c32.tex new file mode 100644 index 00000000..ef7165d4 --- /dev/null +++ b/sail_latex_riscv/fnzmk_counterenf15701a312ca5765a184f9c5e5a93c32.tex @@ -0,0 +1 @@ +function Mk_Counteren v = struct { Counteren_chunk_0 = subrange_bits(v, 31, 0) } diff --git a/sail_latex_riscv/fnzmk_counterin5d7512dddbfaeea7688a2e6a3c88ed68.tex b/sail_latex_riscv/fnzmk_counterin5d7512dddbfaeea7688a2e6a3c88ed68.tex new file mode 100644 index 00000000..1782426b --- /dev/null +++ b/sail_latex_riscv/fnzmk_counterin5d7512dddbfaeea7688a2e6a3c88ed68.tex @@ -0,0 +1 @@ +function Mk_Counterin v = struct { Counterin_chunk_0 = subrange_bits(v, 31, 0) } diff --git a/sail_latex_riscv/fnzmk_ext_pte_bitsc4519926cf8a81ebbc7a7489bdaaf1ef.tex b/sail_latex_riscv/fnzmk_ext_pte_bitsc4519926cf8a81ebbc7a7489bdaaf1ef.tex new file mode 100644 index 00000000..a1478a8f --- /dev/null +++ b/sail_latex_riscv/fnzmk_ext_pte_bitsc4519926cf8a81ebbc7a7489bdaaf1ef.tex @@ -0,0 +1 @@ +function Mk_Ext_PTE_Bits v = struct { Ext_PTE_Bits_chunk_0 = subrange_bits(v, 9, 0) } diff --git a/sail_latex_riscv/fnzmk_fcsr9657e355ebbcf62f95e4a48aa5de149a.tex b/sail_latex_riscv/fnzmk_fcsr9657e355ebbcf62f95e4a48aa5de149a.tex new file mode 100644 index 00000000..ebcf434d --- /dev/null +++ b/sail_latex_riscv/fnzmk_fcsr9657e355ebbcf62f95e4a48aa5de149a.tex @@ -0,0 +1 @@ +function Mk_Fcsr v = struct { Fcsr_chunk_0 = subrange_bits(v, 31, 0) } diff --git a/sail_latex_riscv/fnzmk_htif_cmde6729ad1ed1b5a3925de51048804de68.tex b/sail_latex_riscv/fnzmk_htif_cmde6729ad1ed1b5a3925de51048804de68.tex new file mode 100644 index 00000000..54e10cce --- /dev/null +++ b/sail_latex_riscv/fnzmk_htif_cmde6729ad1ed1b5a3925de51048804de68.tex @@ -0,0 +1 @@ +function Mk_htif_cmd v = struct { htif_cmd_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_mcause0c621c96c15db1b801688d6c698bfddd.tex b/sail_latex_riscv/fnzmk_mcause0c621c96c15db1b801688d6c698bfddd.tex new file mode 100644 index 00000000..cd1c191a --- /dev/null +++ b/sail_latex_riscv/fnzmk_mcause0c621c96c15db1b801688d6c698bfddd.tex @@ -0,0 +1 @@ +function Mk_Mcause v = struct { Mcause_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_medeleg3829c83ea6bb677825f964507254a95c.tex b/sail_latex_riscv/fnzmk_medeleg3829c83ea6bb677825f964507254a95c.tex new file mode 100644 index 00000000..197e0356 --- /dev/null +++ b/sail_latex_riscv/fnzmk_medeleg3829c83ea6bb677825f964507254a95c.tex @@ -0,0 +1 @@ +function Mk_Medeleg v = struct { Medeleg_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_minterruptsaf75f6e1eef17a71d4f11eede706901d.tex b/sail_latex_riscv/fnzmk_minterruptsaf75f6e1eef17a71d4f11eede706901d.tex new file mode 100644 index 00000000..b74a613c --- /dev/null +++ b/sail_latex_riscv/fnzmk_minterruptsaf75f6e1eef17a71d4f11eede706901d.tex @@ -0,0 +1 @@ +function Mk_Minterrupts v = struct { Minterrupts_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_misa9e5f00faa0413197c9cc5f0f7791d5b7.tex b/sail_latex_riscv/fnzmk_misa9e5f00faa0413197c9cc5f0f7791d5b7.tex new file mode 100644 index 00000000..7043037e --- /dev/null +++ b/sail_latex_riscv/fnzmk_misa9e5f00faa0413197c9cc5f0f7791d5b7.tex @@ -0,0 +1 @@ +function Mk_Misa v = struct { Misa_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_mstatus5db327fc42d9fe4de62eca1e3915bd06.tex b/sail_latex_riscv/fnzmk_mstatus5db327fc42d9fe4de62eca1e3915bd06.tex new file mode 100644 index 00000000..fe401911 --- /dev/null +++ b/sail_latex_riscv/fnzmk_mstatus5db327fc42d9fe4de62eca1e3915bd06.tex @@ -0,0 +1 @@ +function Mk_Mstatus v = struct { Mstatus_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_mtvec60ead547a4a385f88360115e550b4ab2.tex b/sail_latex_riscv/fnzmk_mtvec60ead547a4a385f88360115e550b4ab2.tex new file mode 100644 index 00000000..567c84ca --- /dev/null +++ b/sail_latex_riscv/fnzmk_mtvec60ead547a4a385f88360115e550b4ab2.tex @@ -0,0 +1 @@ +function Mk_Mtvec v = struct { Mtvec_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_pmpcfg_ent3c5800ef8bd6fce928dfecddb43bbdaf.tex b/sail_latex_riscv/fnzmk_pmpcfg_ent3c5800ef8bd6fce928dfecddb43bbdaf.tex new file mode 100644 index 00000000..515b75bc --- /dev/null +++ b/sail_latex_riscv/fnzmk_pmpcfg_ent3c5800ef8bd6fce928dfecddb43bbdaf.tex @@ -0,0 +1 @@ +function Mk_Pmpcfg_ent v = struct { Pmpcfg_ent_chunk_0 = subrange_bits(v, 7, 0) } diff --git a/sail_latex_riscv/fnzmk_pte_bits2f40a3dc189d8feaf027fdaa7cd0c939.tex b/sail_latex_riscv/fnzmk_pte_bits2f40a3dc189d8feaf027fdaa7cd0c939.tex new file mode 100644 index 00000000..e1334bcc --- /dev/null +++ b/sail_latex_riscv/fnzmk_pte_bits2f40a3dc189d8feaf027fdaa7cd0c939.tex @@ -0,0 +1 @@ +function Mk_PTE_Bits v = struct { PTE_Bits_chunk_0 = subrange_bits(v, 7, 0) } diff --git a/sail_latex_riscv/fnzmk_satp322e54e0b7f463382f08c680a0164f0a0d.tex b/sail_latex_riscv/fnzmk_satp322e54e0b7f463382f08c680a0164f0a0d.tex new file mode 100644 index 00000000..d4acd59a --- /dev/null +++ b/sail_latex_riscv/fnzmk_satp322e54e0b7f463382f08c680a0164f0a0d.tex @@ -0,0 +1 @@ +function Mk_Satp32 v = struct { Satp32_chunk_0 = subrange_bits(v, 31, 0) } diff --git a/sail_latex_riscv/fnzmk_satp64329969f3c15112d031d796680dc02dba.tex b/sail_latex_riscv/fnzmk_satp64329969f3c15112d031d796680dc02dba.tex new file mode 100644 index 00000000..d5ddee6b --- /dev/null +++ b/sail_latex_riscv/fnzmk_satp64329969f3c15112d031d796680dc02dba.tex @@ -0,0 +1 @@ +function Mk_Satp64 v = struct { Satp64_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_sedeleg222d7d880065c377c672b48be0312b58.tex b/sail_latex_riscv/fnzmk_sedeleg222d7d880065c377c672b48be0312b58.tex new file mode 100644 index 00000000..f384ea20 --- /dev/null +++ b/sail_latex_riscv/fnzmk_sedeleg222d7d880065c377c672b48be0312b58.tex @@ -0,0 +1 @@ +function Mk_Sedeleg v = struct { Sedeleg_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_sinterrupts50ead85256a5e42901dcc54cd50f0280.tex b/sail_latex_riscv/fnzmk_sinterrupts50ead85256a5e42901dcc54cd50f0280.tex new file mode 100644 index 00000000..9b257eac --- /dev/null +++ b/sail_latex_riscv/fnzmk_sinterrupts50ead85256a5e42901dcc54cd50f0280.tex @@ -0,0 +1 @@ +function Mk_Sinterrupts v = struct { Sinterrupts_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_sstatus103c07d81aa6bb97a5681c36b23d8d7f.tex b/sail_latex_riscv/fnzmk_sstatus103c07d81aa6bb97a5681c36b23d8d7f.tex new file mode 100644 index 00000000..81d0f7d7 --- /dev/null +++ b/sail_latex_riscv/fnzmk_sstatus103c07d81aa6bb97a5681c36b23d8d7f.tex @@ -0,0 +1 @@ +function Mk_Sstatus v = struct { Sstatus_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_sv32_paddr38cec8bc7eb5a8f367e53058939b7ee9.tex b/sail_latex_riscv/fnzmk_sv32_paddr38cec8bc7eb5a8f367e53058939b7ee9.tex new file mode 100644 index 00000000..925a667a --- /dev/null +++ b/sail_latex_riscv/fnzmk_sv32_paddr38cec8bc7eb5a8f367e53058939b7ee9.tex @@ -0,0 +1 @@ +function Mk_SV32_Paddr v = struct { SV32_Paddr_chunk_0 = subrange_bits(v, 33, 0) } diff --git a/sail_latex_riscv/fnzmk_sv32_pte36c66a6cb6c5db181eeea4960a6a2882.tex b/sail_latex_riscv/fnzmk_sv32_pte36c66a6cb6c5db181eeea4960a6a2882.tex new file mode 100644 index 00000000..f6084540 --- /dev/null +++ b/sail_latex_riscv/fnzmk_sv32_pte36c66a6cb6c5db181eeea4960a6a2882.tex @@ -0,0 +1 @@ +function Mk_SV32_PTE v = struct { SV32_PTE_chunk_0 = subrange_bits(v, 31, 0) } diff --git a/sail_latex_riscv/fnzmk_sv32_vaddrd462eac178a4cd9186df0d708de0cabf.tex b/sail_latex_riscv/fnzmk_sv32_vaddrd462eac178a4cd9186df0d708de0cabf.tex new file mode 100644 index 00000000..8f9d6f35 --- /dev/null +++ b/sail_latex_riscv/fnzmk_sv32_vaddrd462eac178a4cd9186df0d708de0cabf.tex @@ -0,0 +1 @@ +function Mk_SV32_Vaddr v = struct { SV32_Vaddr_chunk_0 = subrange_bits(v, 31, 0) } diff --git a/sail_latex_riscv/fnzmk_sv39_paddr9839b2830ababd96b40ec4ed4e215f85.tex b/sail_latex_riscv/fnzmk_sv39_paddr9839b2830ababd96b40ec4ed4e215f85.tex new file mode 100644 index 00000000..9051d1df --- /dev/null +++ b/sail_latex_riscv/fnzmk_sv39_paddr9839b2830ababd96b40ec4ed4e215f85.tex @@ -0,0 +1 @@ +function Mk_SV39_Paddr v = struct { SV39_Paddr_chunk_0 = subrange_bits(v, 55, 0) } diff --git a/sail_latex_riscv/fnzmk_sv39_pte72f20a67de4a391e796c728a1b1411bf.tex b/sail_latex_riscv/fnzmk_sv39_pte72f20a67de4a391e796c728a1b1411bf.tex new file mode 100644 index 00000000..643de2f4 --- /dev/null +++ b/sail_latex_riscv/fnzmk_sv39_pte72f20a67de4a391e796c728a1b1411bf.tex @@ -0,0 +1 @@ +function Mk_SV39_PTE v = struct { SV39_PTE_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_sv39_vaddr6221e811d934736591eeb06d6df3537c.tex b/sail_latex_riscv/fnzmk_sv39_vaddr6221e811d934736591eeb06d6df3537c.tex new file mode 100644 index 00000000..c4f5cb30 --- /dev/null +++ b/sail_latex_riscv/fnzmk_sv39_vaddr6221e811d934736591eeb06d6df3537c.tex @@ -0,0 +1 @@ +function Mk_SV39_Vaddr v = struct { SV39_Vaddr_chunk_0 = subrange_bits(v, 38, 0) } diff --git a/sail_latex_riscv/fnzmk_sv48_paddr2e91c2bf0030c89b31d06021ef3c01eb.tex b/sail_latex_riscv/fnzmk_sv48_paddr2e91c2bf0030c89b31d06021ef3c01eb.tex new file mode 100644 index 00000000..73be519f --- /dev/null +++ b/sail_latex_riscv/fnzmk_sv48_paddr2e91c2bf0030c89b31d06021ef3c01eb.tex @@ -0,0 +1 @@ +function Mk_SV48_Paddr v = struct { SV48_Paddr_chunk_0 = subrange_bits(v, 55, 0) } diff --git a/sail_latex_riscv/fnzmk_sv48_pte98d38b79a0d0a08a23bc295e90c40a75.tex b/sail_latex_riscv/fnzmk_sv48_pte98d38b79a0d0a08a23bc295e90c40a75.tex new file mode 100644 index 00000000..c8183ed1 --- /dev/null +++ b/sail_latex_riscv/fnzmk_sv48_pte98d38b79a0d0a08a23bc295e90c40a75.tex @@ -0,0 +1 @@ +function Mk_SV48_PTE v = struct { SV48_PTE_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_sv48_vaddr1a3eef2a9372d3cb53334a8a4bf1eaf9.tex b/sail_latex_riscv/fnzmk_sv48_vaddr1a3eef2a9372d3cb53334a8a4bf1eaf9.tex new file mode 100644 index 00000000..cf4cb72d --- /dev/null +++ b/sail_latex_riscv/fnzmk_sv48_vaddr1a3eef2a9372d3cb53334a8a4bf1eaf9.tex @@ -0,0 +1 @@ +function Mk_SV48_Vaddr v = struct { SV48_Vaddr_chunk_0 = subrange_bits(v, 47, 0) } diff --git a/sail_latex_riscv/fnzmk_uinterrupts22955e59610459ed7c6ad97089d22498.tex b/sail_latex_riscv/fnzmk_uinterrupts22955e59610459ed7c6ad97089d22498.tex new file mode 100644 index 00000000..2c3d6dec --- /dev/null +++ b/sail_latex_riscv/fnzmk_uinterrupts22955e59610459ed7c6ad97089d22498.tex @@ -0,0 +1 @@ +function Mk_Uinterrupts v = struct { Uinterrupts_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmk_ustatus6494ac5e1dcede8689e33b27d65d3204.tex b/sail_latex_riscv/fnzmk_ustatus6494ac5e1dcede8689e33b27d65d3204.tex new file mode 100644 index 00000000..dd958518 --- /dev/null +++ b/sail_latex_riscv/fnzmk_ustatus6494ac5e1dcede8689e33b27d65d3204.tex @@ -0,0 +1 @@ +function Mk_Ustatus v = struct { Ustatus_chunk_0 = subrange_bits(v, 63, 0) } diff --git a/sail_latex_riscv/fnzmmio_read910c976398a0cf73e8b4d12641a665c1.tex b/sail_latex_riscv/fnzmmio_read910c976398a0cf73e8b4d12641a665c1.tex new file mode 100644 index 00000000..1ccc8e84 --- /dev/null +++ b/sail_latex_riscv/fnzmmio_read910c976398a0cf73e8b4d12641a665c1.tex @@ -0,0 +1,10 @@ +function mmio_read forall 'n, 0 < 'n <= max_mem_access . (t : #\hyperref[sailRISCVzAccessType]{AccessType}#(ext_access_type), paddr : xlenbits, width : atom('n)) -> #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(#\hyperref[sailRISCVzbits]{bits}#(8 * 'n)) = + if #\hyperref[sailRISCVzwithinzyclint]{within\_clint}#(paddr, width) + then #\hyperref[sailRISCVzclintzyload]{clint\_load}#(t, paddr, width) + else if #\hyperref[sailRISCVzwithinzyhtifzyreadable]{within\_htif\_readable}#(paddr, width) & (1 <= 'n) + then #\hyperref[sailRISCVzhtifzyload]{htif\_load}#(t, paddr, width) + else match t { + #\hyperref[sailRISCVzExecute]{Execute}#() => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzyFetchzyAccesszyFault]{E\_Fetch\_Access\_Fault}#()), + #\hyperref[sailRISCVzRead]{Read}#(Data) => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzyLoadzyAccesszyFault]{E\_Load\_Access\_Fault}#()), + _ => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#()) + } diff --git a/sail_latex_riscv/fnzmmio_writec1bd5fc64a027d200e43ae1730320ed7.tex b/sail_latex_riscv/fnzmmio_writec1bd5fc64a027d200e43ae1730320ed7.tex new file mode 100644 index 00000000..4fee66ad --- /dev/null +++ b/sail_latex_riscv/fnzmmio_writec1bd5fc64a027d200e43ae1730320ed7.tex @@ -0,0 +1,6 @@ +function mmio_write forall 'n, 0 <'n <= max_mem_access . (paddr : xlenbits, width : atom('n), data: #\hyperref[sailRISCVzbits]{bits}#(8 * 'n)) -> #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(bool) = + if #\hyperref[sailRISCVzwithinzyclint]{within\_clint}#(paddr, width) + then #\hyperref[sailRISCVzclintzystore]{clint\_store}#(paddr, width, data) + else if #\hyperref[sailRISCVzwithinzyhtifzywritable]{within\_htif\_writable}#(paddr, width) & 'n <= 8 + then #\hyperref[sailRISCVzhtifzystore]{htif\_store}#(paddr, width, data) + else #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#()) diff --git a/sail_latex_riscv/fnzn_leading_spaces05ea6c2f03435a60412f4bef062a912a.tex b/sail_latex_riscv/fnzn_leading_spaces05ea6c2f03435a60412f4bef062a912a.tex new file mode 100644 index 00000000..e40c5296 --- /dev/null +++ b/sail_latex_riscv/fnzn_leading_spaces05ea6c2f03435a60412f4bef062a912a.tex @@ -0,0 +1,8 @@ +function n_leading_spaces s = + match s { + "" => 0, + _ => match #\hyperref[sailRISCVzstringzytake]{string\_take}#(s, 1) { + " " => 1 + #\hyperref[sailRISCVznzyleadingzyspaces]{n\_leading\_spaces}#(#\hyperref[sailRISCVzstringzydrop]{string\_drop}#(s, 1)), + _ => 0 + } + } diff --git a/sail_latex_riscv/fnznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex b/sail_latex_riscv/fnznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex new file mode 100644 index 00000000..8c8816f9 --- /dev/null +++ b/sail_latex_riscv/fnznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex @@ -0,0 +1,4 @@ +function nan_box val_32b = + if (sizeof(flen) == 32) + then val_32b + else 0x_FFFF_FFFF @ val_32b diff --git a/sail_latex_riscv/fnznan_unbox6971c840905d637f635a4793907fe38e.tex b/sail_latex_riscv/fnznan_unbox6971c840905d637f635a4793907fe38e.tex new file mode 100644 index 00000000..4157fe56 --- /dev/null +++ b/sail_latex_riscv/fnznan_unbox6971c840905d637f635a4793907fe38e.tex @@ -0,0 +1,6 @@ +function nan_unbox regval = + if (sizeof(flen) == 32) + then regval + else if regval [63..32] == 0x_FFFF_FFFF + then regval [31..0] + else #\hyperref[sailRISCVzcanonicalzyNaNzyS]{canonical\_NaN\_S}#() diff --git a/sail_latex_riscv/fnznegate_dc9622c2a4f7fec13696be94bec5ae96c.tex b/sail_latex_riscv/fnznegate_dc9622c2a4f7fec13696be94bec5ae96c.tex new file mode 100644 index 00000000..6703841a --- /dev/null +++ b/sail_latex_riscv/fnznegate_dc9622c2a4f7fec13696be94bec5ae96c.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVznegatezyD]{negate\_D}# (x64) = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyD]{fsplit\_D}# (x64); + let new_sign = if (sign == 0b0) then 0b1 else 0b0; + #\hyperref[sailRISCVzfmakezyD]{fmake\_D}# (new_sign, exp, mant) +} diff --git a/sail_latex_riscv/fnznegate_s602acdc6547e76adb79aa6072014fa3e.tex b/sail_latex_riscv/fnznegate_s602acdc6547e76adb79aa6072014fa3e.tex new file mode 100644 index 00000000..933d29d6 --- /dev/null +++ b/sail_latex_riscv/fnznegate_s602acdc6547e76adb79aa6072014fa3e.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVznegatezyS]{negate\_S}# (x32) = { + let (sign, exp, mant) = #\hyperref[sailRISCVzfsplitzyS]{fsplit\_S}# (x32); + let new_sign = if (sign == 0b0) then 0b1 else 0b0; + #\hyperref[sailRISCVzfmakezyS]{fmake\_S}# (new_sign, exp, mant) +} diff --git a/sail_latex_riscv/fnzneq_anythingf220233154ca93d75c0323f604bb8d16.tex b/sail_latex_riscv/fnzneq_anythingf220233154ca93d75c0323f604bb8d16.tex new file mode 100644 index 00000000..7bdb4b4e --- /dev/null +++ b/sail_latex_riscv/fnzneq_anythingf220233154ca93d75c0323f604bb8d16.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzneqzyanything]{neq\_anything}# (x, y) = #\hyperref[sailRISCVznotzybool]{not\_bool}#(x == y) diff --git a/sail_latex_riscv/fnzneq_bits167748c906c068e62596c88540a84f42.tex b/sail_latex_riscv/fnzneq_bits167748c906c068e62596c88540a84f42.tex new file mode 100644 index 00000000..9cf64c1d --- /dev/null +++ b/sail_latex_riscv/fnzneq_bits167748c906c068e62596c88540a84f42.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzneqzybits]{neq\_bits}#(x, y) = #\hyperref[sailRISCVznotzybool]{not\_bool}#(#\hyperref[sailRISCVzeqzybits]{eq\_bits}#(x, y)) diff --git a/sail_latex_riscv/fnzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex b/sail_latex_riscv/fnzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex new file mode 100644 index 00000000..b7d53fd9 --- /dev/null +++ b/sail_latex_riscv/fnzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzneqzybool]{neq\_bool}# (x, y) = #\hyperref[sailRISCVznotzybool]{not\_bool}#(#\hyperref[sailRISCVzeqzybool]{eq\_bool}#(x, y)) diff --git a/sail_latex_riscv/fnzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex b/sail_latex_riscv/fnzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex new file mode 100644 index 00000000..647c688d --- /dev/null +++ b/sail_latex_riscv/fnzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzneqzyint]{neq\_int}# (x, y) = #\hyperref[sailRISCVznotzybool]{not\_bool}#(#\hyperref[sailRISCVzeqzyint]{eq\_int}#(x, y)) diff --git a/sail_latex_riscv/fnzneq_vecefa97ba9877d7fde3cd929d8ec7a401a.tex b/sail_latex_riscv/fnzneq_vecefa97ba9877d7fde3cd929d8ec7a401a.tex new file mode 100644 index 00000000..60a587a9 --- /dev/null +++ b/sail_latex_riscv/fnzneq_vecefa97ba9877d7fde3cd929d8ec7a401a.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzneqzyvec]{neq\_vec}# (x, y) = #\hyperref[sailRISCVznotzybool]{not\_bool}#(#\hyperref[sailRISCVzeqzybits]{eq\_bits}#(x, y)) diff --git a/sail_latex_riscv/fnznot_bit3b618f3ab6887bbe967eaa12bf52b297.tex b/sail_latex_riscv/fnznot_bit3b618f3ab6887bbe967eaa12bf52b297.tex new file mode 100644 index 00000000..745e7ad2 --- /dev/null +++ b/sail_latex_riscv/fnznot_bit3b618f3ab6887bbe967eaa12bf52b297.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVznotzybit]{not\_bit}#(b) = if b == bitone then bitzero else bitone diff --git a/sail_latex_riscv/fnznot_implementedde41164205ef21773733c511f05a2946.tex b/sail_latex_riscv/fnznot_implementedde41164205ef21773733c511f05a2946.tex new file mode 100644 index 00000000..32d67cec --- /dev/null +++ b/sail_latex_riscv/fnznot_implementedde41164205ef21773733c511f05a2946.tex @@ -0,0 +1 @@ +function not_implemented message = throw(#\hyperref[sailRISCVzErrorzynotzyimplemented]{Error\_not\_implemented}#(message)) diff --git a/sail_latex_riscv/fnznum_of_a64_barrier_domainfd9b4ecf6f4c38bf5c7e299b7fb7b219.tex b/sail_latex_riscv/fnznum_of_a64_barrier_domainfd9b4ecf6f4c38bf5c7e299b7fb7b219.tex new file mode 100644 index 00000000..c6df7e6f --- /dev/null +++ b/sail_latex_riscv/fnznum_of_a64_barrier_domainfd9b4ecf6f4c38bf5c7e299b7fb7b219.tex @@ -0,0 +1,6 @@ +function num_of_a64_barrier_domain arg# = match arg# { + A64_FullShare => 0, + A64_InnerShare => 1, + A64_OuterShare => 2, + A64_NonShare => 3 +} diff --git a/sail_latex_riscv/fnznum_of_a64_barrier_typef15d849f5523574b740454d956b74505.tex b/sail_latex_riscv/fnznum_of_a64_barrier_typef15d849f5523574b740454d956b74505.tex new file mode 100644 index 00000000..ae8d2044 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_a64_barrier_typef15d849f5523574b740454d956b74505.tex @@ -0,0 +1,5 @@ +function num_of_a64_barrier_type arg# = match arg# { + A64_barrier_all => 0, + A64_barrier_LD => 1, + A64_barrier_ST => 2 +} diff --git a/sail_latex_riscv/fnznum_of_amoop3990788e22835bf2e0af928f223c3eba.tex b/sail_latex_riscv/fnznum_of_amoop3990788e22835bf2e0af928f223c3eba.tex new file mode 100644 index 00000000..8d9f0116 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_amoop3990788e22835bf2e0af928f223c3eba.tex @@ -0,0 +1,11 @@ +function num_of_amoop arg# = match arg# { + AMOSWAP => 0, + AMOADD => 1, + AMOXOR => 2, + AMOAND => 3, + AMOOR => 4, + AMOMIN => 5, + AMOMAX => 6, + AMOMINU => 7, + AMOMAXU => 8 +} diff --git a/sail_latex_riscv/fnznum_of_architecture1ae1fee7c4b64fc1c08b7336a9784f4a.tex b/sail_latex_riscv/fnznum_of_architecture1ae1fee7c4b64fc1c08b7336a9784f4a.tex new file mode 100644 index 00000000..07e0678e --- /dev/null +++ b/sail_latex_riscv/fnznum_of_architecture1ae1fee7c4b64fc1c08b7336a9784f4a.tex @@ -0,0 +1,5 @@ +function num_of_Architecture arg# = match arg# { + RV32 => 0, + RV64 => 1, + RV128 => 2 +} diff --git a/sail_latex_riscv/fnznum_of_bop465de2d51df014a233592af62fc5056d.tex b/sail_latex_riscv/fnznum_of_bop465de2d51df014a233592af62fc5056d.tex new file mode 100644 index 00000000..d4827091 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_bop465de2d51df014a233592af62fc5056d.tex @@ -0,0 +1,8 @@ +function num_of_bop arg# = match arg# { + RISCV_BEQ => 0, + RISCV_BNE => 1, + RISCV_BLT => 2, + RISCV_BGE => 3, + RISCV_BLTU => 4, + RISCV_BGEU => 5 +} diff --git a/sail_latex_riscv/fnznum_of_cache_op_kindbd96e6225a906fea23a868ff35718006.tex b/sail_latex_riscv/fnznum_of_cache_op_kindbd96e6225a906fea23a868ff35718006.tex new file mode 100644 index 00000000..2c2b829c --- /dev/null +++ b/sail_latex_riscv/fnznum_of_cache_op_kindbd96e6225a906fea23a868ff35718006.tex @@ -0,0 +1,13 @@ +function num_of_cache_op_kind arg# = match arg# { + Cache_op_D_IVAC => 0, + Cache_op_D_ISW => 1, + Cache_op_D_CSW => 2, + Cache_op_D_CISW => 3, + Cache_op_D_ZVA => 4, + Cache_op_D_CVAC => 5, + Cache_op_D_CVAU => 6, + Cache_op_D_CIVAC => 7, + Cache_op_I_IALLUIS => 8, + Cache_op_I_IALLU => 9, + Cache_op_I_IVAU => 10 +} diff --git a/sail_latex_riscv/fnznum_of_capexa430f3db535161473e26bac337cc3ffe.tex b/sail_latex_riscv/fnznum_of_capexa430f3db535161473e26bac337cc3ffe.tex new file mode 100644 index 00000000..16cd02d4 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_capexa430f3db535161473e26bac337cc3ffe.tex @@ -0,0 +1,26 @@ +function num_of_CapEx arg# = match arg# { + CapEx_None => 0, + CapEx_LengthViolation => 1, + CapEx_TagViolation => 2, + CapEx_SealViolation => 3, + CapEx_TypeViolation => 4, + CapEx_CallTrap => 5, + CapEx_ReturnTrap => 6, + CapEx_TSSUnderFlow => 7, + CapEx_UserDefViolation => 8, + CapEx_InexactBounds => 9, + CapEx_UnalignedBase => 10, + CapEx_GlobalViolation => 11, + CapEx_PermitExecuteViolation => 12, + CapEx_PermitLoadViolation => 13, + CapEx_PermitStoreViolation => 14, + CapEx_PermitLoadCapViolation => 15, + CapEx_PermitStoreCapViolation => 16, + CapEx_PermitStoreLocalCapViolation => 17, + CapEx_PermitSealViolation => 18, + CapEx_AccessSystemRegsViolation => 19, + CapEx_PermitCInvokeViolation => 20, + CapEx_AccessCInvokeIDCViolation => 21, + CapEx_PermitUnsealViolation => 22, + CapEx_PermitSetCIDViolation => 23 +} diff --git a/sail_latex_riscv/fnznum_of_clearregset49e10f200544574f819f7f660071e10b.tex b/sail_latex_riscv/fnznum_of_clearregset49e10f200544574f819f7f660071e10b.tex new file mode 100644 index 00000000..1934704a --- /dev/null +++ b/sail_latex_riscv/fnznum_of_clearregset49e10f200544574f819f7f660071e10b.tex @@ -0,0 +1,4 @@ +function num_of_ClearRegSet arg# = match arg# { + GPRegs => 0, + FPRegs => 1 +} diff --git a/sail_latex_riscv/fnznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex b/sail_latex_riscv/fnznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex new file mode 100644 index 00000000..4d20546b --- /dev/null +++ b/sail_latex_riscv/fnznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex @@ -0,0 +1,10 @@ +function num_of_CPtrCmpOp arg# = match arg# { + CEQ => 0, + CNE => 1, + CLT => 2, + CLE => 3, + CLTU => 4, + CLEU => 5, + CEXEQ => 6, + CNEXEQ => 7 +} diff --git a/sail_latex_riscv/fnznum_of_csropc21ef48aae10c4abc2e72f7386a31ce9.tex b/sail_latex_riscv/fnznum_of_csropc21ef48aae10c4abc2e72f7386a31ce9.tex new file mode 100644 index 00000000..190e4a2b --- /dev/null +++ b/sail_latex_riscv/fnznum_of_csropc21ef48aae10c4abc2e72f7386a31ce9.tex @@ -0,0 +1,5 @@ +function num_of_csrop arg# = match arg# { + CSRRW => 0, + CSRRS => 1, + CSRRC => 2 +} diff --git a/sail_latex_riscv/fnznum_of_exceptiontype13e59fd83201d81140ba0f6bbcbd1a7b.tex b/sail_latex_riscv/fnznum_of_exceptiontype13e59fd83201d81140ba0f6bbcbd1a7b.tex new file mode 100644 index 00000000..f27380cd --- /dev/null +++ b/sail_latex_riscv/fnznum_of_exceptiontype13e59fd83201d81140ba0f6bbcbd1a7b.tex @@ -0,0 +1,23 @@ +function #\hyperref[sailRISCVznumzyofzyExceptionType]{num\_of\_ExceptionType}#(e) = + match (e) { + #\hyperref[sailRISCVzEzyFetchzyAddrzyAlign]{E\_Fetch\_Addr\_Align}#() => 0, + #\hyperref[sailRISCVzEzyFetchzyAccesszyFault]{E\_Fetch\_Access\_Fault}#() => 1, + #\hyperref[sailRISCVzEzyIllegalzyInstr]{E\_Illegal\_Instr}#() => 2, + #\hyperref[sailRISCVzEzyBreakpoint]{E\_Breakpoint}#() => 3, + #\hyperref[sailRISCVzEzyLoadzyAddrzyAlign]{E\_Load\_Addr\_Align}#() => 4, + #\hyperref[sailRISCVzEzyLoadzyAccesszyFault]{E\_Load\_Access\_Fault}#() => 5, + #\hyperref[sailRISCVzEzySAMOzyAddrzyAlign]{E\_SAMO\_Addr\_Align}#() => 6, + #\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#() => 7, + #\hyperref[sailRISCVzEzyUzyEnvCall]{E\_U\_EnvCall}#() => 8, + #\hyperref[sailRISCVzEzySzyEnvCall]{E\_S\_EnvCall}#() => 9, + #\hyperref[sailRISCVzEzyReservedzy10]{E\_Reserved\_10}#() => 10, + #\hyperref[sailRISCVzEzyMzyEnvCall]{E\_M\_EnvCall}#() => 11, + #\hyperref[sailRISCVzEzyFetchzyPagezyFault]{E\_Fetch\_Page\_Fault}#() => 12, + #\hyperref[sailRISCVzEzyLoadzyPagezyFault]{E\_Load\_Page\_Fault}#() => 13, + #\hyperref[sailRISCVzEzyReservedzy14]{E\_Reserved\_14}#() => 14, + #\hyperref[sailRISCVzEzySAMOzyPagezyFault]{E\_SAMO\_Page\_Fault}#() => 15, + + /* extensions */ + #\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(e) => #\hyperref[sailRISCVznumzyofzyextzyexczytype]{num\_of\_ext\_exc\_type}#(e) + + } diff --git a/sail_latex_riscv/fnznum_of_ext_access_typea973217ed477a3d18820058dd3b21729.tex b/sail_latex_riscv/fnznum_of_ext_access_typea973217ed477a3d18820058dd3b21729.tex new file mode 100644 index 00000000..ac60bad3 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_ext_access_typea973217ed477a3d18820058dd3b21729.tex @@ -0,0 +1,4 @@ +function num_of_ext_access_type arg# = match arg# { + Data => 0, + Cap => 1 +} diff --git a/sail_latex_riscv/fnznum_of_ext_exc_type79451fb17925bed3ec8d5058c42d301d.tex b/sail_latex_riscv/fnznum_of_ext_exc_type79451fb17925bed3ec8d5058c42d301d.tex new file mode 100644 index 00000000..008da226 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_ext_exc_type79451fb17925bed3ec8d5058c42d301d.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVznumzyofzyextzyexczytype]{num\_of\_ext\_exc\_type}#(e) = + match (e) { + EXC_LOAD_CAP_PAGE_FAULT => 26, + EXC_SAMO_CAP_PAGE_FAULT => 27, + EXC_CHERI => 28 + } diff --git a/sail_latex_riscv/fnznum_of_ext_ptw_error7daeb8fc5a17e215ccad3f2a24541927.tex b/sail_latex_riscv/fnznum_of_ext_ptw_error7daeb8fc5a17e215ccad3f2a24541927.tex new file mode 100644 index 00000000..68d9b413 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_ext_ptw_error7daeb8fc5a17e215ccad3f2a24541927.tex @@ -0,0 +1 @@ +function num_of_ext_ptw_error arg# = match arg# {AT_CAP_ERR => 0} diff --git a/sail_latex_riscv/fnznum_of_ext_ptw_fail785ab48a0d85159cd76e2d20768c9173.tex b/sail_latex_riscv/fnznum_of_ext_ptw_fail785ab48a0d85159cd76e2d20768c9173.tex new file mode 100644 index 00000000..fb1e5158 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_ext_ptw_fail785ab48a0d85159cd76e2d20768c9173.tex @@ -0,0 +1,4 @@ +function num_of_ext_ptw_fail arg# = match arg# { + EPTWF_NO_PERM => 0, + EPTWF_CAP_ERR => 1 +} diff --git a/sail_latex_riscv/fnznum_of_ext_ptw_lcfde46f3a7b817078010b5dc3a4f25be7.tex b/sail_latex_riscv/fnznum_of_ext_ptw_lcfde46f3a7b817078010b5dc3a4f25be7.tex new file mode 100644 index 00000000..6366e24e --- /dev/null +++ b/sail_latex_riscv/fnznum_of_ext_ptw_lcfde46f3a7b817078010b5dc3a4f25be7.tex @@ -0,0 +1,4 @@ +function num_of_ext_ptw_lc arg# = match arg# { + PTW_LC_OK => 0, + PTW_LC_CLEAR => 1 +} diff --git a/sail_latex_riscv/fnznum_of_ext_ptw_sc2a22418de077e3289633414d48a30bbe.tex b/sail_latex_riscv/fnznum_of_ext_ptw_sc2a22418de077e3289633414d48a30bbe.tex new file mode 100644 index 00000000..59c9cbeb --- /dev/null +++ b/sail_latex_riscv/fnznum_of_ext_ptw_sc2a22418de077e3289633414d48a30bbe.tex @@ -0,0 +1,4 @@ +function num_of_ext_ptw_sc arg# = match arg# { + PTW_SC_OK => 0, + PTW_SC_TRAP => 1 +} diff --git a/sail_latex_riscv/fnznum_of_extstatus8d29ae3139c8c2d5d4fa7489689b6a41.tex b/sail_latex_riscv/fnznum_of_extstatus8d29ae3139c8c2d5d4fa7489689b6a41.tex new file mode 100644 index 00000000..78eefc1b --- /dev/null +++ b/sail_latex_riscv/fnznum_of_extstatus8d29ae3139c8c2d5d4fa7489689b6a41.tex @@ -0,0 +1,6 @@ +function num_of_ExtStatus arg# = match arg# { + Off => 0, + Initial => 1, + Clean => 2, + Dirty => 3 +} diff --git a/sail_latex_riscv/fnznum_of_f_bin_op_dd209f84b003673fbf65e2d0267de89cd.tex b/sail_latex_riscv/fnznum_of_f_bin_op_dd209f84b003673fbf65e2d0267de89cd.tex new file mode 100644 index 00000000..f70a2d30 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_f_bin_op_dd209f84b003673fbf65e2d0267de89cd.tex @@ -0,0 +1,10 @@ +function num_of_f_bin_op_D arg# = match arg# { + FSGNJ_D => 0, + FSGNJN_D => 1, + FSGNJX_D => 2, + FMIN_D => 3, + FMAX_D => 4, + FEQ_D => 5, + FLT_D => 6, + FLE_D => 7 +} diff --git a/sail_latex_riscv/fnznum_of_f_bin_op_s67646ca4512abf0a4d4b44cd4f5b13ca.tex b/sail_latex_riscv/fnznum_of_f_bin_op_s67646ca4512abf0a4d4b44cd4f5b13ca.tex new file mode 100644 index 00000000..42a49a8a --- /dev/null +++ b/sail_latex_riscv/fnznum_of_f_bin_op_s67646ca4512abf0a4d4b44cd4f5b13ca.tex @@ -0,0 +1,10 @@ +function num_of_f_bin_op_S arg# = match arg# { + FSGNJ_S => 0, + FSGNJN_S => 1, + FSGNJX_S => 2, + FMIN_S => 3, + FMAX_S => 4, + FEQ_S => 5, + FLT_S => 6, + FLE_S => 7 +} diff --git a/sail_latex_riscv/fnznum_of_f_bin_rm_op_dc153c7dd1e01a91df37cddfd46dfd9da.tex b/sail_latex_riscv/fnznum_of_f_bin_rm_op_dc153c7dd1e01a91df37cddfd46dfd9da.tex new file mode 100644 index 00000000..3c3824fd --- /dev/null +++ b/sail_latex_riscv/fnznum_of_f_bin_rm_op_dc153c7dd1e01a91df37cddfd46dfd9da.tex @@ -0,0 +1,6 @@ +function num_of_f_bin_rm_op_D arg# = match arg# { + FADD_D => 0, + FSUB_D => 1, + FMUL_D => 2, + FDIV_D => 3 +} diff --git a/sail_latex_riscv/fnznum_of_f_bin_rm_op_s893f36c63d593d34b1cf67930090a6d2.tex b/sail_latex_riscv/fnznum_of_f_bin_rm_op_s893f36c63d593d34b1cf67930090a6d2.tex new file mode 100644 index 00000000..014e1248 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_f_bin_rm_op_s893f36c63d593d34b1cf67930090a6d2.tex @@ -0,0 +1,6 @@ +function num_of_f_bin_rm_op_S arg# = match arg# { + FADD_S => 0, + FSUB_S => 1, + FMUL_S => 2, + FDIV_S => 3 +} diff --git a/sail_latex_riscv/fnznum_of_f_madd_op_d37717f7c44daba9b30789132320443ff.tex b/sail_latex_riscv/fnznum_of_f_madd_op_d37717f7c44daba9b30789132320443ff.tex new file mode 100644 index 00000000..b5d42c45 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_f_madd_op_d37717f7c44daba9b30789132320443ff.tex @@ -0,0 +1,6 @@ +function num_of_f_madd_op_D arg# = match arg# { + FMADD_D => 0, + FMSUB_D => 1, + FNMSUB_D => 2, + FNMADD_D => 3 +} diff --git a/sail_latex_riscv/fnznum_of_f_madd_op_s775906828ed91e55055481dedc5d9da4.tex b/sail_latex_riscv/fnznum_of_f_madd_op_s775906828ed91e55055481dedc5d9da4.tex new file mode 100644 index 00000000..7de899b8 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_f_madd_op_s775906828ed91e55055481dedc5d9da4.tex @@ -0,0 +1,6 @@ +function num_of_f_madd_op_S arg# = match arg# { + FMADD_S => 0, + FMSUB_S => 1, + FNMSUB_S => 2, + FNMADD_S => 3 +} diff --git a/sail_latex_riscv/fnznum_of_f_un_op_d6d388f339a377c4a985a55a3c728bb8f.tex b/sail_latex_riscv/fnznum_of_f_un_op_d6d388f339a377c4a985a55a3c728bb8f.tex new file mode 100644 index 00000000..70e65784 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_f_un_op_d6d388f339a377c4a985a55a3c728bb8f.tex @@ -0,0 +1,5 @@ +function num_of_f_un_op_D arg# = match arg# { + FCLASS_D => 0, + FMV_X_D => 1, + FMV_D_X => 2 +} diff --git a/sail_latex_riscv/fnznum_of_f_un_op_se59a01770756c5c1ccc368187228ef32.tex b/sail_latex_riscv/fnznum_of_f_un_op_se59a01770756c5c1ccc368187228ef32.tex new file mode 100644 index 00000000..d55f4f4c --- /dev/null +++ b/sail_latex_riscv/fnznum_of_f_un_op_se59a01770756c5c1ccc368187228ef32.tex @@ -0,0 +1,5 @@ +function num_of_f_un_op_S arg# = match arg# { + FCLASS_S => 0, + FMV_X_W => 1, + FMV_W_X => 2 +} diff --git a/sail_latex_riscv/fnznum_of_f_un_rm_op_d6e3378f59faf04b5d017d7c996a625e0.tex b/sail_latex_riscv/fnznum_of_f_un_rm_op_d6e3378f59faf04b5d017d7c996a625e0.tex new file mode 100644 index 00000000..6393fe36 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_f_un_rm_op_d6e3378f59faf04b5d017d7c996a625e0.tex @@ -0,0 +1,13 @@ +function num_of_f_un_rm_op_D arg# = match arg# { + FSQRT_D => 0, + FCVT_W_D => 1, + FCVT_WU_D => 2, + FCVT_D_W => 3, + FCVT_D_WU => 4, + FCVT_S_D => 5, + FCVT_D_S => 6, + FCVT_L_D => 7, + FCVT_LU_D => 8, + FCVT_D_L => 9, + FCVT_D_LU => 10 +} diff --git a/sail_latex_riscv/fnznum_of_f_un_rm_op_se915d9a4f61459b98b43ab8bc6055666.tex b/sail_latex_riscv/fnznum_of_f_un_rm_op_se915d9a4f61459b98b43ab8bc6055666.tex new file mode 100644 index 00000000..9caa1fb8 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_f_un_rm_op_se915d9a4f61459b98b43ab8bc6055666.tex @@ -0,0 +1,11 @@ +function num_of_f_un_rm_op_S arg# = match arg# { + FSQRT_S => 0, + FCVT_W_S => 1, + FCVT_WU_S => 2, + FCVT_S_W => 3, + FCVT_S_WU => 4, + FCVT_L_S => 5, + FCVT_LU_S => 6, + FCVT_S_L => 7, + FCVT_S_LU => 8 +} diff --git a/sail_latex_riscv/fnznum_of_interrupttype186751debed5f5a4e5f875749623071b.tex b/sail_latex_riscv/fnznum_of_interrupttype186751debed5f5a4e5f875749623071b.tex new file mode 100644 index 00000000..4564893c --- /dev/null +++ b/sail_latex_riscv/fnznum_of_interrupttype186751debed5f5a4e5f875749623071b.tex @@ -0,0 +1,11 @@ +function num_of_InterruptType arg# = match arg# { + I_U_Software => 0, + I_S_Software => 1, + I_M_Software => 2, + I_U_Timer => 3, + I_S_Timer => 4, + I_M_Timer => 5, + I_U_External => 6, + I_S_External => 7, + I_M_External => 8 +} diff --git a/sail_latex_riscv/fnznum_of_iop7e0f948724eaec1edf1ab6539e332d14.tex b/sail_latex_riscv/fnznum_of_iop7e0f948724eaec1edf1ab6539e332d14.tex new file mode 100644 index 00000000..9912ec70 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_iop7e0f948724eaec1edf1ab6539e332d14.tex @@ -0,0 +1,8 @@ +function num_of_iop arg# = match arg# { + RISCV_ADDI => 0, + RISCV_SLTI => 1, + RISCV_SLTIU => 2, + RISCV_XORI => 3, + RISCV_ORI => 4, + RISCV_ANDI => 5 +} diff --git a/sail_latex_riscv/fnznum_of_pmpaddrmatch6db470099c3f03581d51f40437610a39.tex b/sail_latex_riscv/fnznum_of_pmpaddrmatch6db470099c3f03581d51f40437610a39.tex new file mode 100644 index 00000000..19969d01 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_pmpaddrmatch6db470099c3f03581d51f40437610a39.tex @@ -0,0 +1,5 @@ +function num_of_pmpAddrMatch arg# = match arg# { + PMP_NoMatch => 0, + PMP_PartialMatch => 1, + PMP_Match => 2 +} diff --git a/sail_latex_riscv/fnznum_of_pmpaddrmatchtypee330d16c3db664232af948049b8edeb9.tex b/sail_latex_riscv/fnznum_of_pmpaddrmatchtypee330d16c3db664232af948049b8edeb9.tex new file mode 100644 index 00000000..041d20bb --- /dev/null +++ b/sail_latex_riscv/fnznum_of_pmpaddrmatchtypee330d16c3db664232af948049b8edeb9.tex @@ -0,0 +1,6 @@ +function num_of_PmpAddrMatchType arg# = match arg# { + OFF => 0, + TOR => 1, + NA4 => 2, + NAPOT => 3 +} diff --git a/sail_latex_riscv/fnznum_of_pmpmatch3a839a54108c809c88766e9119a0bce5.tex b/sail_latex_riscv/fnznum_of_pmpmatch3a839a54108c809c88766e9119a0bce5.tex new file mode 100644 index 00000000..6836f9f0 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_pmpmatch3a839a54108c809c88766e9119a0bce5.tex @@ -0,0 +1,5 @@ +function num_of_pmpMatch arg# = match arg# { + PMP_Success => 0, + PMP_Continue => 1, + PMP_Fail => 2 +} diff --git a/sail_latex_riscv/fnznum_of_privilege40c636ca569f6d4bb59a57bee3b2742d.tex b/sail_latex_riscv/fnznum_of_privilege40c636ca569f6d4bb59a57bee3b2742d.tex new file mode 100644 index 00000000..b7bf9f49 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_privilege40c636ca569f6d4bb59a57bee3b2742d.tex @@ -0,0 +1,5 @@ +function num_of_Privilege arg# = match arg# { + User => 0, + Supervisor => 1, + Machine => 2 +} diff --git a/sail_latex_riscv/fnznum_of_read_kind9f1d12d5627d7618c1e31c888906fc68.tex b/sail_latex_riscv/fnznum_of_read_kind9f1d12d5627d7618c1e31c888906fc68.tex new file mode 100644 index 00000000..d9c5b9c8 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_read_kind9f1d12d5627d7618c1e31c888906fc68.tex @@ -0,0 +1,14 @@ +function num_of_read_kind arg# = match arg# { + Read_plain => 0, + Read_reserve => 1, + Read_acquire => 2, + Read_exclusive => 3, + Read_exclusive_acquire => 4, + Read_stream => 5, + Read_RISCV_acquire => 6, + Read_RISCV_strong_acquire => 7, + Read_RISCV_reserved => 8, + Read_RISCV_reserved_acquire => 9, + Read_RISCV_reserved_strong_acquire => 10, + Read_X86_locked => 11 +} diff --git a/sail_latex_riscv/fnznum_of_retiredc5322d8e56eb574c7eb3ebf89e0586af.tex b/sail_latex_riscv/fnznum_of_retiredc5322d8e56eb574c7eb3ebf89e0586af.tex new file mode 100644 index 00000000..d01f4475 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_retiredc5322d8e56eb574c7eb3ebf89e0586af.tex @@ -0,0 +1,4 @@ +function num_of_Retired arg# = match arg# { + RETIRE_SUCCESS => 0, + RETIRE_FAIL => 1 +} diff --git a/sail_latex_riscv/fnznum_of_rop6b1530298b7a57e62b47f86bb5f1b15c.tex b/sail_latex_riscv/fnznum_of_rop6b1530298b7a57e62b47f86bb5f1b15c.tex new file mode 100644 index 00000000..4441cbff --- /dev/null +++ b/sail_latex_riscv/fnznum_of_rop6b1530298b7a57e62b47f86bb5f1b15c.tex @@ -0,0 +1,12 @@ +function num_of_rop arg# = match arg# { + RISCV_ADD => 0, + RISCV_SUB => 1, + RISCV_SLL => 2, + RISCV_SLT => 3, + RISCV_SLTU => 4, + RISCV_XOR => 5, + RISCV_SRL => 6, + RISCV_SRA => 7, + RISCV_OR => 8, + RISCV_AND => 9 +} diff --git a/sail_latex_riscv/fnznum_of_ropw2d1d1b64d2060822876c1a3c1d164870.tex b/sail_latex_riscv/fnznum_of_ropw2d1d1b64d2060822876c1a3c1d164870.tex new file mode 100644 index 00000000..60925de9 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_ropw2d1d1b64d2060822876c1a3c1d164870.tex @@ -0,0 +1,7 @@ +function num_of_ropw arg# = match arg# { + RISCV_ADDW => 0, + RISCV_SUBW => 1, + RISCV_SLLW => 2, + RISCV_SRLW => 3, + RISCV_SRAW => 4 +} diff --git a/sail_latex_riscv/fnznum_of_rounding_mode41a60e82308e6507de434c7dc6e17db8.tex b/sail_latex_riscv/fnznum_of_rounding_mode41a60e82308e6507de434c7dc6e17db8.tex new file mode 100644 index 00000000..bd8171e2 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_rounding_mode41a60e82308e6507de434c7dc6e17db8.tex @@ -0,0 +1,8 @@ +function num_of_rounding_mode arg# = match arg# { + RM_RNE => 0, + RM_RTZ => 1, + RM_RDN => 2, + RM_RUP => 3, + RM_RMM => 4, + RM_DYN => 5 +} diff --git a/sail_latex_riscv/fnznum_of_satpmode714998a67cc48d1f59bc52de3d9a052f.tex b/sail_latex_riscv/fnznum_of_satpmode714998a67cc48d1f59bc52de3d9a052f.tex new file mode 100644 index 00000000..21793d8f --- /dev/null +++ b/sail_latex_riscv/fnznum_of_satpmode714998a67cc48d1f59bc52de3d9a052f.tex @@ -0,0 +1,6 @@ +function num_of_SATPMode arg# = match arg# { + Sbare => 0, + Sv32 => 1, + Sv39 => 2, + Sv48 => 3 +} diff --git a/sail_latex_riscv/fnznum_of_sopfa04a24d46338146566ae6e8a80132f0.tex b/sail_latex_riscv/fnznum_of_sopfa04a24d46338146566ae6e8a80132f0.tex new file mode 100644 index 00000000..b4c0989f --- /dev/null +++ b/sail_latex_riscv/fnznum_of_sopfa04a24d46338146566ae6e8a80132f0.tex @@ -0,0 +1,5 @@ +function num_of_sop arg# = match arg# { + RISCV_SLLI => 0, + RISCV_SRLI => 1, + RISCV_SRAI => 2 +} diff --git a/sail_latex_riscv/fnznum_of_sopw352409ee6a8831f827129fc3d78cd4d6.tex b/sail_latex_riscv/fnznum_of_sopw352409ee6a8831f827129fc3d78cd4d6.tex new file mode 100644 index 00000000..acecaa26 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_sopw352409ee6a8831f827129fc3d78cd4d6.tex @@ -0,0 +1,5 @@ +function num_of_sopw arg# = match arg# { + RISCV_SLLIW => 0, + RISCV_SRLIW => 1, + RISCV_SRAIW => 2 +} diff --git a/sail_latex_riscv/fnznum_of_trans_kind7086883ee37c97f3e6858f19cebb2163.tex b/sail_latex_riscv/fnznum_of_trans_kind7086883ee37c97f3e6858f19cebb2163.tex new file mode 100644 index 00000000..21021abe --- /dev/null +++ b/sail_latex_riscv/fnznum_of_trans_kind7086883ee37c97f3e6858f19cebb2163.tex @@ -0,0 +1,5 @@ +function num_of_trans_kind arg# = match arg# { + Transaction_start => 0, + Transaction_commit => 1, + Transaction_abort => 2 +} diff --git a/sail_latex_riscv/fnznum_of_trapvectormode9673c0ba1b150ae7d0c789bf1ea8f4fe.tex b/sail_latex_riscv/fnznum_of_trapvectormode9673c0ba1b150ae7d0c789bf1ea8f4fe.tex new file mode 100644 index 00000000..72c1b38d --- /dev/null +++ b/sail_latex_riscv/fnznum_of_trapvectormode9673c0ba1b150ae7d0c789bf1ea8f4fe.tex @@ -0,0 +1,5 @@ +function num_of_TrapVectorMode arg# = match arg# { + TV_Direct => 0, + TV_Vector => 1, + TV_Reserved => 2 +} diff --git a/sail_latex_riscv/fnznum_of_uop5155bc57344db1e0852d69264b07f354.tex b/sail_latex_riscv/fnznum_of_uop5155bc57344db1e0852d69264b07f354.tex new file mode 100644 index 00000000..1ea4c673 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_uop5155bc57344db1e0852d69264b07f354.tex @@ -0,0 +1,4 @@ +function num_of_uop arg# = match arg# { + RISCV_LUI => 0, + RISCV_AUIPC => 1 +} diff --git a/sail_latex_riscv/fnznum_of_word_width80798ebf687d8b1ac16aea948967912d.tex b/sail_latex_riscv/fnznum_of_word_width80798ebf687d8b1ac16aea948967912d.tex new file mode 100644 index 00000000..2aa7ec31 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_word_width80798ebf687d8b1ac16aea948967912d.tex @@ -0,0 +1,6 @@ +function num_of_word_width arg# = match arg# { + BYTE => 0, + HALF => 1, + WORD => 2, + DOUBLE => 3 +} diff --git a/sail_latex_riscv/fnznum_of_write_kind056951dbaa3b47d3c25ba586d7093c91.tex b/sail_latex_riscv/fnznum_of_write_kind056951dbaa3b47d3c25ba586d7093c91.tex new file mode 100644 index 00000000..99a33a26 --- /dev/null +++ b/sail_latex_riscv/fnznum_of_write_kind056951dbaa3b47d3c25ba586d7093c91.tex @@ -0,0 +1,13 @@ +function num_of_write_kind arg# = match arg# { + Write_plain => 0, + Write_conditional => 1, + Write_release => 2, + Write_exclusive => 3, + Write_exclusive_release => 4, + Write_RISCV_release => 5, + Write_RISCV_strong_release => 6, + Write_RISCV_conditional => 7, + Write_RISCV_conditional_release => 8, + Write_RISCV_conditional_strong_release => 9, + Write_X86_locked => 10 +} diff --git a/sail_latex_riscv/fnznvflag96f5e3b2efdbb80ea87eb99f361ac158.tex b/sail_latex_riscv/fnznvflag96f5e3b2efdbb80ea87eb99f361ac158.tex new file mode 100644 index 00000000..4b9a7c18 --- /dev/null +++ b/sail_latex_riscv/fnznvflag96f5e3b2efdbb80ea87eb99f361ac158.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVznvFlag]{nvFlag}#() -> #\hyperref[sailRISCVzbits]{bits}#(5) = 0b_10000 diff --git a/sail_latex_riscv/fnznxflaga9ef0edc4edc03b79abaa230aaad20a6.tex b/sail_latex_riscv/fnznxflaga9ef0edc4edc03b79abaa230aaad20a6.tex new file mode 100644 index 00000000..7a4c87fd --- /dev/null +++ b/sail_latex_riscv/fnznxflaga9ef0edc4edc03b79abaa230aaad20a6.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVznxFlag]{nxFlag}#() -> #\hyperref[sailRISCVzbits]{bits}#(5) = 0b_00001 diff --git a/sail_latex_riscv/fnzofflag1be1156688e569fa940a9118708be17d.tex b/sail_latex_riscv/fnzofflag1be1156688e569fa940a9118708be17d.tex new file mode 100644 index 00000000..b6e8eb5e --- /dev/null +++ b/sail_latex_riscv/fnzofflag1be1156688e569fa940a9118708be17d.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzofFlag]{ofFlag}#() -> #\hyperref[sailRISCVzbits]{bits}#(5) = 0b_00100 diff --git a/sail_latex_riscv/fnzones26f94136f5db8afd4e9df1e512f7fdc5.tex b/sail_latex_riscv/fnzones26f94136f5db8afd4e9df1e512f7fdc5.tex new file mode 100644 index 00000000..ef088fef --- /dev/null +++ b/sail_latex_riscv/fnzones26f94136f5db8afd4e9df1e512f7fdc5.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzones]{ones}# (n) = #\hyperref[sailRISCVzsailzyones]{sail\_ones}# (n) diff --git a/sail_latex_riscv/fnzopt_spc_backwards68e297450ccdf6f2339325379c27029f.tex b/sail_latex_riscv/fnzopt_spc_backwards68e297450ccdf6f2339325379c27029f.tex new file mode 100644 index 00000000..76b2db3a --- /dev/null +++ b/sail_latex_riscv/fnzopt_spc_backwards68e297450ccdf6f2339325379c27029f.tex @@ -0,0 +1 @@ +function opt_spc_backwards s = () diff --git a/sail_latex_riscv/fnzopt_spc_forwards395c7cf20c474712cbbb7c80edd24bda.tex b/sail_latex_riscv/fnzopt_spc_forwards395c7cf20c474712cbbb7c80edd24bda.tex new file mode 100644 index 00000000..59ca8122 --- /dev/null +++ b/sail_latex_riscv/fnzopt_spc_forwards395c7cf20c474712cbbb7c80edd24bda.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzoptzyspczyforwards]{opt\_spc\_forwards}# () = "" diff --git a/sail_latex_riscv/fnzopt_spc_matches_prefix495f7798e6650e2ff628a5b7715c161c.tex b/sail_latex_riscv/fnzopt_spc_matches_prefix495f7798e6650e2ff628a5b7715c161c.tex new file mode 100644 index 00000000..b7c8a027 --- /dev/null +++ b/sail_latex_riscv/fnzopt_spc_matches_prefix495f7798e6650e2ff628a5b7715c161c.tex @@ -0,0 +1,2 @@ +function opt_spc_matches_prefix s = + #\hyperref[sailRISCVzSome]{Some}#((), #\hyperref[sailRISCVznzyleadingzyspaces]{n\_leading\_spaces}#(s)) diff --git a/sail_latex_riscv/fnzpc_alignment_mask1943267c124397815476842d08d3901e.tex b/sail_latex_riscv/fnzpc_alignment_mask1943267c124397815476842d08d3901e.tex new file mode 100644 index 00000000..fc57f8bb --- /dev/null +++ b/sail_latex_riscv/fnzpc_alignment_mask1943267c124397815476842d08d3901e.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzpczyalignmentzymask]{pc\_alignment\_mask}#() -> xlenbits = + ~(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(if misa.#\hyperref[sailRISCVzC]{C}#() == 0b1 then 0b00 else 0b10)) diff --git a/sail_latex_riscv/fnzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex b/sail_latex_riscv/fnzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex new file mode 100644 index 00000000..e78a556e --- /dev/null +++ b/sail_latex_riscv/fnzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzpcczyaccesszysystemzyregs]{pcc\_access\_system\_regs}# () = PCC.access_system_regs diff --git a/sail_latex_riscv/fnzphys_mem_readdcad862ae3a42c22bfc78bad8e3328db.tex b/sail_latex_riscv/fnzphys_mem_readdcad862ae3a42c22bfc78bad8e3328db.tex new file mode 100644 index 00000000..9da15122 --- /dev/null +++ b/sail_latex_riscv/fnzphys_mem_readdcad862ae3a42c22bfc78bad8e3328db.tex @@ -0,0 +1,14 @@ +function phys_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : #\hyperref[sailRISCVzAccessType]{AccessType}#(ext_access_type), paddr : xlenbits, width : atom('n), aq : bool, rl: bool, res : bool, meta : bool) -> #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#((#\hyperref[sailRISCVzbits]{bits}#(8 * 'n), mem_meta)) = { + let result = (match #\hyperref[sailRISCVzreadzykindzyofzyflags]{read\_kind\_of\_flags}#(aq, rl, res) { + #\hyperref[sailRISCVzSome]{Some}#(rk) => #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzreadzyram]{read\_ram}#(rk, paddr, width, meta)), + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzNone]{None}#() + }) : #\hyperref[sailRISCVzoption]{option}#((#\hyperref[sailRISCVzbits]{bits}#(8 * 'n), mem_meta)); + match (t, result) { + (#\hyperref[sailRISCVzExecute]{Execute}#(), #\hyperref[sailRISCVzNone]{None}#()) => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzyFetchzyAccesszyFault]{E\_Fetch\_Access\_Fault}#()), + (#\hyperref[sailRISCVzRead]{Read}#(Data), #\hyperref[sailRISCVzNone]{None}#()) => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzyLoadzyAccesszyFault]{E\_Load\_Access\_Fault}#()), + (_, #\hyperref[sailRISCVzNone]{None}#()) => #\hyperref[sailRISCVzMemException]{MemException}#(#\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#()), + (_, #\hyperref[sailRISCVzSome]{Some}#(v, m)) => { if #\hyperref[sailRISCVzgetzyconfigzyprintzymem]{get\_config\_print\_mem}#() + then #\hyperref[sailRISCVzprintzymem]{print\_mem}#("mem[" ^ #\hyperref[sailRISCVztozystr]{to\_str}#(t) ^ "," ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(paddr) ^ "] -> " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(v)); + #\hyperref[sailRISCVzMemValue]{MemValue}#(v, m) } + } +} diff --git a/sail_latex_riscv/fnzphys_mem_segments83ff72aa5aa998a329fa30de106aa0a7.tex b/sail_latex_riscv/fnzphys_mem_segments83ff72aa5aa998a329fa30de106aa0a7.tex new file mode 100644 index 00000000..1144d00c --- /dev/null +++ b/sail_latex_riscv/fnzphys_mem_segments83ff72aa5aa998a329fa30de106aa0a7.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzphyszymemzysegments]{phys\_mem\_segments}#() = + (#\hyperref[sailRISCVzplatzyromzybase]{plat\_rom\_base}# (), #\hyperref[sailRISCVzplatzyromzysizze]{plat\_rom\_size}# ()) :: + (#\hyperref[sailRISCVzplatzyramzybase]{plat\_ram\_base}# (), #\hyperref[sailRISCVzplatzyramzysizze]{plat\_ram\_size}# ()) :: + [||] diff --git a/sail_latex_riscv/fnzphys_mem_writefae7815adda192bed56129eba4b7bb01.tex b/sail_latex_riscv/fnzphys_mem_writefae7815adda192bed56129eba4b7bb01.tex new file mode 100644 index 00000000..4f6f1494 --- /dev/null +++ b/sail_latex_riscv/fnzphys_mem_writefae7815adda192bed56129eba4b7bb01.tex @@ -0,0 +1,7 @@ +function phys_mem_write forall 'n, 0 < 'n <= max_mem_access . (wk : write_kind, paddr : xlenbits, width : atom('n), data : #\hyperref[sailRISCVzbits]{bits}#(8 * 'n), meta : mem_meta) -> #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(bool) = { + #\hyperref[sailRISCVzrvfizywrite]{rvfi\_write}#(paddr, width, data); + let result = #\hyperref[sailRISCVzMemValue]{MemValue}#(#\hyperref[sailRISCVzwritezyram]{write\_ram}#(wk, paddr, width, data, meta)); + if #\hyperref[sailRISCVzgetzyconfigzyprintzymem]{get\_config\_print\_mem}#() + then #\hyperref[sailRISCVzprintzymem]{print\_mem}#("mem[" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(paddr) ^ "] <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(data)); + result +} diff --git a/sail_latex_riscv/fnzplat_htif_tohostf9ba2e7ae67de81976fbefc0304b89d1.tex b/sail_latex_riscv/fnzplat_htif_tohostf9ba2e7ae67de81976fbefc0304b89d1.tex new file mode 100644 index 00000000..0ab2a27a --- /dev/null +++ b/sail_latex_riscv/fnzplat_htif_tohostf9ba2e7ae67de81976fbefc0304b89d1.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzplatzyhtifzytohost]{plat\_htif\_tohost}# () = #\hyperref[sailRISCVztozybits]{to\_bits}#(sizeof(xlen), #\hyperref[sailRISCVzelfzytohost]{elf\_tohost}# ()) diff --git a/sail_latex_riscv/fnzplatform_wfi377b23f6619d58844892f179f2934ac6.tex b/sail_latex_riscv/fnzplatform_wfi377b23f6619d58844892f179f2934ac6.tex new file mode 100644 index 00000000..7e7930df --- /dev/null +++ b/sail_latex_riscv/fnzplatform_wfi377b23f6619d58844892f179f2934ac6.tex @@ -0,0 +1,10 @@ +function #\hyperref[sailRISCVzplatformzywfi]{platform\_wfi}#() -> unit = { + #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); + /* speed execution by getting the timer to fire at the next instruction, + * since we currently don't have any other devices raising interrupts. + */ + if mtime <_u mtimecmp then { + mtime = mtimecmp; + mcycle = mtimecmp; + } +} diff --git a/sail_latex_riscv/fnzpmp_mem_readc45533831bda1c394396c536ba168b7a.tex b/sail_latex_riscv/fnzpmp_mem_readc45533831bda1c394396c536ba168b7a.tex new file mode 100644 index 00000000..0dec4f60 --- /dev/null +++ b/sail_latex_riscv/fnzpmp_mem_readc45533831bda1c394396c536ba168b7a.tex @@ -0,0 +1,9 @@ +function pmp_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : #\hyperref[sailRISCVzAccessType]{AccessType}#(ext_access_type), paddr : xlenbits, width : atom('n), aq : bool, rl : bool, res: bool, meta : bool) -> #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#((#\hyperref[sailRISCVzbits]{bits}#(8 * 'n), mem_meta)) = + if (~ (#\hyperref[sailRISCVzplatzyenablezypmp]{plat\_enable\_pmp}# ())) + then #\hyperref[sailRISCVzcheckedzymemzyread]{checked\_mem\_read}#(t, paddr, width, aq, rl, res, meta) + else { + match #\hyperref[sailRISCVzpmpCheck]{pmpCheck}#(paddr, width, t, #\hyperref[sailRISCVzeffectivePrivilege]{effectivePrivilege}#(t, mstatus, cur_privilege)) { + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzcheckedzymemzyread]{checked\_mem\_read}#(t, paddr, width, aq, rl, res, meta), + #\hyperref[sailRISCVzSome]{Some}#(e) => #\hyperref[sailRISCVzMemException]{MemException}#(e) + } + } diff --git a/sail_latex_riscv/fnzpmp_mem_write4ae53a6de2384826cc3e765eccd350e8.tex b/sail_latex_riscv/fnzpmp_mem_write4ae53a6de2384826cc3e765eccd350e8.tex new file mode 100644 index 00000000..66109e09 --- /dev/null +++ b/sail_latex_riscv/fnzpmp_mem_write4ae53a6de2384826cc3e765eccd350e8.tex @@ -0,0 +1,10 @@ +function pmp_mem_write forall 'n, 0 < 'n <= max_mem_access . (wk: write_kind, paddr : xlenbits, width : atom('n), data: #\hyperref[sailRISCVzbits]{bits}#(8 * 'n), ext_acc: ext_access_type, meta: mem_meta) -> #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}#(bool) = + if (~ (#\hyperref[sailRISCVzplatzyenablezypmp]{plat\_enable\_pmp}# ())) + then #\hyperref[sailRISCVzcheckedzymemzywrite]{checked\_mem\_write}#(wk, paddr, width, data, meta) + else { + let typ : #\hyperref[sailRISCVzAccessType]{AccessType}#(ext_access_type) = #\hyperref[sailRISCVzWrite]{Write}#(ext_acc); + match #\hyperref[sailRISCVzpmpCheck]{pmpCheck}#(paddr, width, typ, #\hyperref[sailRISCVzeffectivePrivilege]{effectivePrivilege}#(typ, mstatus, cur_privilege)) { + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzcheckedzymemzywrite]{checked\_mem\_write}#(wk, paddr, width, data, meta), + #\hyperref[sailRISCVzSome]{Some}#(e) => #\hyperref[sailRISCVzMemException]{MemException}#(e) + } + } diff --git a/sail_latex_riscv/fnzpmpaddrmatch_of_num92a36380d4ab664cee1f4ee0143e390f.tex b/sail_latex_riscv/fnzpmpaddrmatch_of_num92a36380d4ab664cee1f4ee0143e390f.tex new file mode 100644 index 00000000..e8afdc73 --- /dev/null +++ b/sail_latex_riscv/fnzpmpaddrmatch_of_num92a36380d4ab664cee1f4ee0143e390f.tex @@ -0,0 +1,5 @@ +function pmpAddrMatch_of_num arg# = match arg# { + 0 => PMP_NoMatch, + 1 => PMP_PartialMatch, + _ => PMP_Match +} diff --git a/sail_latex_riscv/fnzpmpaddrmatchtype_of_bits8b4e245ce3d01f111a1f89404623ac98.tex b/sail_latex_riscv/fnzpmpaddrmatchtype_of_bits8b4e245ce3d01f111a1f89404623ac98.tex new file mode 100644 index 00000000..4e2b7090 --- /dev/null +++ b/sail_latex_riscv/fnzpmpaddrmatchtype_of_bits8b4e245ce3d01f111a1f89404623ac98.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzpmpAddrMatchTypezyofzybits]{pmpAddrMatchType\_of\_bits}#(bs) = { + match bs { + 0b00 => OFF, + 0b01 => TOR, + 0b10 => NA4, + 0b11 => NAPOT + } +} diff --git a/sail_latex_riscv/fnzpmpaddrmatchtype_of_num05d549dd7f3bf4d35f3c38ea6a015bf3.tex b/sail_latex_riscv/fnzpmpaddrmatchtype_of_num05d549dd7f3bf4d35f3c38ea6a015bf3.tex new file mode 100644 index 00000000..1c09e99e --- /dev/null +++ b/sail_latex_riscv/fnzpmpaddrmatchtype_of_num05d549dd7f3bf4d35f3c38ea6a015bf3.tex @@ -0,0 +1,6 @@ +function PmpAddrMatchType_of_num arg# = match arg# { + 0 => OFF, + 1 => TOR, + 2 => NA4, + _ => NAPOT +} diff --git a/sail_latex_riscv/fnzpmpaddrmatchtype_to_bitsd16d593c276e8bc21809612105ac8913.tex b/sail_latex_riscv/fnzpmpaddrmatchtype_to_bitsd16d593c276e8bc21809612105ac8913.tex new file mode 100644 index 00000000..9c974f92 --- /dev/null +++ b/sail_latex_riscv/fnzpmpaddrmatchtype_to_bitsd16d593c276e8bc21809612105ac8913.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzpmpAddrMatchTypezytozybits]{pmpAddrMatchType\_to\_bits}#(bs) = { + match bs { + OFF => 0b00, + TOR => 0b01, + NA4 => 0b10, + NAPOT => 0b11 + } +} diff --git a/sail_latex_riscv/fnzpmpaddrranged0e482997ef7d22fddc89c097e038f0d.tex b/sail_latex_riscv/fnzpmpaddrranged0e482997ef7d22fddc89c097e038f0d.tex new file mode 100644 index 00000000..5b17c3ca --- /dev/null +++ b/sail_latex_riscv/fnzpmpaddrranged0e482997ef7d22fddc89c097e038f0d.tex @@ -0,0 +1,17 @@ +function #\hyperref[sailRISCVzpmpAddrRange]{pmpAddrRange}#(cfg: Pmpcfg_ent, pmpaddr: xlenbits, prev_pmpaddr: xlenbits) -> pmp_addr_range = { + match #\hyperref[sailRISCVzpmpAddrMatchTypezyofzybits]{pmpAddrMatchType\_of\_bits}#(cfg.#\hyperref[sailRISCVzA]{A}#()) { + OFF => #\hyperref[sailRISCVzNone]{None}#(), + TOR => { #\hyperref[sailRISCVzSome]{Some}# ((prev_pmpaddr << 2, pmpaddr << 2)) }, + NA4 => { // TODO: I find the spec unclear for entries marked NA4 and G = 1. + // (for G >= 2, it is the same as NAPOT). In particular, it affects + // whether pmpaddr[0] is always read as 0. + let lo = pmpaddr << 2; + #\hyperref[sailRISCVzSome]{Some}#((lo, lo + 4)) + }, + NAPOT => { let mask = pmpaddr ^ (pmpaddr + 1); // generate 1s in signifying bits + let lo = pmpaddr & (~ (mask)); + let len = mask + 1; + #\hyperref[sailRISCVzSome]{Some}#((lo << 2, (lo + len) << 2)) + } + } +} diff --git a/sail_latex_riscv/fnzpmpcheck818accaacf804d4474fe874d5c97929a.tex b/sail_latex_riscv/fnzpmpcheck818accaacf804d4474fe874d5c97929a.tex new file mode 100644 index 00000000..c3a6124b --- /dev/null +++ b/sail_latex_riscv/fnzpmpcheck818accaacf804d4474fe874d5c97929a.tex @@ -0,0 +1,82 @@ +function pmpCheck forall 'n, 'n > 0. (addr: xlenbits, width: atom('n), acc: #\hyperref[sailRISCVzAccessType]{AccessType}#(ext_access_type), priv: Privilege) + -> #\hyperref[sailRISCVzoption]{option}#(ExceptionType) = { + let width : xlenbits = #\hyperref[sailRISCVztozybits]{to\_bits}#(sizeof(xlen), width); + let check : bool = + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp0cfg, pmpaddr0, #\hyperref[sailRISCVzzzeros]{zeros}#()) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp1cfg, pmpaddr1, pmpaddr0) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp2cfg, pmpaddr2, pmpaddr1) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp3cfg, pmpaddr3, pmpaddr2) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp4cfg, pmpaddr4, pmpaddr3) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp5cfg, pmpaddr5, pmpaddr4) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp6cfg, pmpaddr6, pmpaddr5) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp7cfg, pmpaddr7, pmpaddr6) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp8cfg, pmpaddr8, pmpaddr7) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp9cfg, pmpaddr9, pmpaddr8) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp10cfg, pmpaddr10, pmpaddr9) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp11cfg, pmpaddr11, pmpaddr10) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp12cfg, pmpaddr12, pmpaddr11) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp13cfg, pmpaddr13, pmpaddr12) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp14cfg, pmpaddr14, pmpaddr13) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => + match #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr, width, acc, priv, pmp15cfg, pmpaddr15, pmpaddr14) { + PMP_Success => true, + PMP_Fail => false, + PMP_Continue => match priv { + Machine => true, + _ => false + } + }}}}}}}}}}}}}}}}; + + if check + then #\hyperref[sailRISCVzNone]{None}#() + else match acc { + #\hyperref[sailRISCVzRead]{Read}#(_) => #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzEzyLoadzyAccesszyFault]{E\_Load\_Access\_Fault}#()), + #\hyperref[sailRISCVzWrite]{Write}#(_) => #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#()), + #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(_) => #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#()), + #\hyperref[sailRISCVzExecute]{Execute}#() => #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzEzyFetchzyAccesszyFault]{E\_Fetch\_Access\_Fault}#()) + } +} diff --git a/sail_latex_riscv/fnzpmpcheckperms43a47caab37d2bebaa37cc41235e7387.tex b/sail_latex_riscv/fnzpmpcheckperms43a47caab37d2bebaa37cc41235e7387.tex new file mode 100644 index 00000000..ad4bf323 --- /dev/null +++ b/sail_latex_riscv/fnzpmpcheckperms43a47caab37d2bebaa37cc41235e7387.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzpmpCheckPerms]{pmpCheckPerms}#(ent, acc, priv) = { + match priv { + Machine => if #\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(ent) + then #\hyperref[sailRISCVzpmpCheckRWX]{pmpCheckRWX}#(ent, acc) + else true, + _ => #\hyperref[sailRISCVzpmpCheckRWX]{pmpCheckRWX}#(ent, acc) + } +} diff --git a/sail_latex_riscv/fnzpmpcheckrwx6a81da10e740c25fedddbe430f079b7d.tex b/sail_latex_riscv/fnzpmpcheckrwx6a81da10e740c25fedddbe430f079b7d.tex new file mode 100644 index 00000000..d3f6476c --- /dev/null +++ b/sail_latex_riscv/fnzpmpcheckrwx6a81da10e740c25fedddbe430f079b7d.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzpmpCheckRWX]{pmpCheckRWX}#(ent, acc) = { + match acc { + #\hyperref[sailRISCVzRead]{Read}#(_) => ent.#\hyperref[sailRISCVzR]{R}#() == 0b1, + #\hyperref[sailRISCVzWrite]{Write}#(_) => ent.#\hyperref[sailRISCVzW]{W}#() == 0b1, + #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(_) => ent.#\hyperref[sailRISCVzR]{R}#() == 0b1 & ent.#\hyperref[sailRISCVzW]{W}#() == 0b1, + #\hyperref[sailRISCVzExecute]{Execute}#() => ent.#\hyperref[sailRISCVzX]{X}#() == 0b1 + } +} diff --git a/sail_latex_riscv/fnzpmplocked32d6273cc49a9c7a22cf1a063f7a3d9b.tex b/sail_latex_riscv/fnzpmplocked32d6273cc49a9c7a22cf1a063f7a3d9b.tex new file mode 100644 index 00000000..4a08469c --- /dev/null +++ b/sail_latex_riscv/fnzpmplocked32d6273cc49a9c7a22cf1a063f7a3d9b.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(cfg: Pmpcfg_ent) -> bool = + cfg.#\hyperref[sailRISCVzL]{L}#() == 0b1 diff --git a/sail_latex_riscv/fnzpmpmatch_of_num271d71ea451fba2032d2e5ea441d9f49.tex b/sail_latex_riscv/fnzpmpmatch_of_num271d71ea451fba2032d2e5ea441d9f49.tex new file mode 100644 index 00000000..1ff33a6e --- /dev/null +++ b/sail_latex_riscv/fnzpmpmatch_of_num271d71ea451fba2032d2e5ea441d9f49.tex @@ -0,0 +1,5 @@ +function pmpMatch_of_num arg# = match arg# { + 0 => PMP_Success, + 1 => PMP_Continue, + _ => PMP_Fail +} diff --git a/sail_latex_riscv/fnzpmpmatchaddr4db797384cb60b665d5b05ce2f54ea2f.tex b/sail_latex_riscv/fnzpmpmatchaddr4db797384cb60b665d5b05ce2f54ea2f.tex new file mode 100644 index 00000000..dfd599e5 --- /dev/null +++ b/sail_latex_riscv/fnzpmpmatchaddr4db797384cb60b665d5b05ce2f54ea2f.tex @@ -0,0 +1,14 @@ +function #\hyperref[sailRISCVzpmpMatchAddr]{pmpMatchAddr}#(addr: xlenbits, width: xlenbits, rng: pmp_addr_range) -> pmpAddrMatch = { + match rng { + #\hyperref[sailRISCVzNone]{None}#() => PMP_NoMatch, + #\hyperref[sailRISCVzSome]{Some}#((lo, hi)) => if hi <_u lo /* to handle mis-configuration */ + then PMP_NoMatch + else { + if (addr + width <_u lo) | (hi <_u addr) + then PMP_NoMatch + else if (lo <=_u addr) & (addr + width <=_u hi) + then PMP_Match + else PMP_PartialMatch + } + } +} diff --git a/sail_latex_riscv/fnzpmpmatchentryb540666374b1cccee76fe8eb4dc7362f.tex b/sail_latex_riscv/fnzpmpmatchentryb540666374b1cccee76fe8eb4dc7362f.tex new file mode 100644 index 00000000..f98d7245 --- /dev/null +++ b/sail_latex_riscv/fnzpmpmatchentryb540666374b1cccee76fe8eb4dc7362f.tex @@ -0,0 +1,11 @@ +function #\hyperref[sailRISCVzpmpMatchEntry]{pmpMatchEntry}#(addr: xlenbits, width: xlenbits, acc: #\hyperref[sailRISCVzAccessType]{AccessType}#(ext_access_type), priv: Privilege, + ent: Pmpcfg_ent, pmpaddr: xlenbits, prev_pmpaddr: xlenbits) -> pmpMatch = { + let rng = #\hyperref[sailRISCVzpmpAddrRange]{pmpAddrRange}#(ent, pmpaddr, prev_pmpaddr); + match #\hyperref[sailRISCVzpmpMatchAddr]{pmpMatchAddr}#(addr, width, rng) { + PMP_NoMatch => PMP_Continue, + PMP_PartialMatch => PMP_Fail, + PMP_Match => if #\hyperref[sailRISCVzpmpCheckPerms]{pmpCheckPerms}#(ent, acc, priv) + then PMP_Success + else PMP_Fail + } +} diff --git a/sail_latex_riscv/fnzpmpreadcfgreg4f212865b80d1cf6286c5525466852bb.tex b/sail_latex_riscv/fnzpmpreadcfgreg4f212865b80d1cf6286c5525466852bb.tex new file mode 100644 index 00000000..63daa975 --- /dev/null +++ b/sail_latex_riscv/fnzpmpreadcfgreg4f212865b80d1cf6286c5525466852bb.tex @@ -0,0 +1,13 @@ +function #\hyperref[sailRISCVzpmpReadCfgReg]{pmpReadCfgReg}#(n) = { + if sizeof(xlen) == 32 + then match n { + 0 => #\hyperref[sailRISCVzappend]{append}#(pmp3cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp2cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp1cfg.#\hyperref[sailRISCVzbits]{bits}#(), pmp0cfg.#\hyperref[sailRISCVzbits]{bits}#()))), + 1 => #\hyperref[sailRISCVzappend]{append}#(pmp7cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp6cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp5cfg.#\hyperref[sailRISCVzbits]{bits}#(), pmp4cfg.#\hyperref[sailRISCVzbits]{bits}#()))), + 2 => #\hyperref[sailRISCVzappend]{append}#(pmp11cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp10cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp9cfg.#\hyperref[sailRISCVzbits]{bits}#(), pmp8cfg.#\hyperref[sailRISCVzbits]{bits}#()))), + 3 => #\hyperref[sailRISCVzappend]{append}#(pmp15cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp14cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp13cfg.#\hyperref[sailRISCVzbits]{bits}#(), pmp12cfg.#\hyperref[sailRISCVzbits]{bits}#()))) + } + else match n { // sizeof(xlen) == 64 + 0 => #\hyperref[sailRISCVzappend]{append}#(pmp7cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp6cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp5cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp4cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp3cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp2cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp1cfg.#\hyperref[sailRISCVzbits]{bits}#(), pmp0cfg.#\hyperref[sailRISCVzbits]{bits}#()))))))), + 2 => #\hyperref[sailRISCVzappend]{append}#(pmp15cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp14cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp13cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp12cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp11cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp10cfg.#\hyperref[sailRISCVzbits]{bits}#(), #\hyperref[sailRISCVzappend]{append}#(pmp9cfg.#\hyperref[sailRISCVzbits]{bits}#(), pmp8cfg.#\hyperref[sailRISCVzbits]{bits}#()))))))) + } +} diff --git a/sail_latex_riscv/fnzpmptorlockedc6616187f2e2905a9fb7c4ac60d52920.tex b/sail_latex_riscv/fnzpmptorlockedc6616187f2e2905a9fb7c4ac60d52920.tex new file mode 100644 index 00000000..90de6bf9 --- /dev/null +++ b/sail_latex_riscv/fnzpmptorlockedc6616187f2e2905a9fb7c4ac60d52920.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(cfg: Pmpcfg_ent) -> bool = + (cfg.#\hyperref[sailRISCVzL]{L}#() == 0b1) & (#\hyperref[sailRISCVzpmpAddrMatchTypezyofzybits]{pmpAddrMatchType\_of\_bits}#(cfg.#\hyperref[sailRISCVzA]{A}#()) == TOR) diff --git a/sail_latex_riscv/fnzpmpwriteaddr35a89b2e3be238e40992648bdf6c2e4c.tex b/sail_latex_riscv/fnzpmpwriteaddr35a89b2e3be238e40992648bdf6c2e4c.tex new file mode 100644 index 00000000..586558fc --- /dev/null +++ b/sail_latex_riscv/fnzpmpwriteaddr35a89b2e3be238e40992648bdf6c2e4c.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(locked: bool, tor_locked: bool, reg: xlenbits, v: xlenbits) -> xlenbits = + if sizeof(xlen) == 32 + then { if (locked | tor_locked) then reg else v } + else { if (locked | tor_locked) then reg else #\hyperref[sailRISCVzEXTZ]{EXTZ}#(v[53..0]) } diff --git a/sail_latex_riscv/fnzpmpwritecfg2cde3ea402426e32bb50a4bc91e0c983.tex b/sail_latex_riscv/fnzpmpwritecfg2cde3ea402426e32bb50a4bc91e0c983.tex new file mode 100644 index 00000000..b1b88237 --- /dev/null +++ b/sail_latex_riscv/fnzpmpwritecfg2cde3ea402426e32bb50a4bc91e0c983.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(cfg: Pmpcfg_ent, v: #\hyperref[sailRISCVzbits]{bits}#(8)) -> Pmpcfg_ent = + if #\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(cfg) then cfg + else #\hyperref[sailRISCVzMkzyPmpcfgzyent]{Mk\_Pmpcfg\_ent}#(v & 0x9f) // Bits 5 and 6 are zero. diff --git a/sail_latex_riscv/fnzpmpwritecfgregf08572520295a822ab88e05e223953db.tex b/sail_latex_riscv/fnzpmpwritecfgregf08572520295a822ab88e05e223953db.tex new file mode 100644 index 00000000..60999c5c --- /dev/null +++ b/sail_latex_riscv/fnzpmpwritecfgregf08572520295a822ab88e05e223953db.tex @@ -0,0 +1,46 @@ +function #\hyperref[sailRISCVzpmpWriteCfgReg]{pmpWriteCfgReg}#(n, v) = { + if sizeof(xlen) == 32 + then match n { + 0 => { pmp0cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp0cfg, v[7 ..0]); + pmp1cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp1cfg, v[15..8]); + pmp2cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp2cfg, v[23..16]); + pmp3cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp3cfg, v[31..24]); + }, + 1 => { pmp4cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp4cfg, v[7 ..0]); + pmp5cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp5cfg, v[15..8]); + pmp6cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp6cfg, v[23..16]); + pmp7cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp7cfg, v[31..24]); + }, + 2 => { pmp8cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp8cfg, v[7 ..0]); + pmp9cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp9cfg, v[15..8]); + pmp10cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp10cfg, v[23..16]); + pmp11cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp11cfg, v[31..24]); + }, + 3 => { pmp12cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp12cfg, v[7 ..0]); + pmp13cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp13cfg, v[15..8]); + pmp14cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp14cfg, v[23..16]); + pmp15cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp15cfg, v[31..24]); + } + } + else if sizeof(xlen) == 64 + then match n { + 0 => { pmp0cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp0cfg, v[7 ..0]); + pmp1cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp1cfg, v[15..8]); + pmp2cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp2cfg, v[23..16]); + pmp3cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp3cfg, v[31..24]); + pmp4cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp4cfg, v[39..32]); + pmp5cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp5cfg, v[47..40]); + pmp6cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp6cfg, v[55..48]); + pmp7cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp7cfg, v[63..56]) + }, + 2 => { pmp8cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp8cfg, v[7 ..0]); + pmp9cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp9cfg, v[15..8]); + pmp10cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp10cfg, v[23..16]); + pmp11cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp11cfg, v[31..24]); + pmp12cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp12cfg, v[39..32]); + pmp13cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp13cfg, v[47..40]); + pmp14cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp14cfg, v[55..48]); + pmp15cfg = #\hyperref[sailRISCVzpmpWriteCfg]{pmpWriteCfg}#(pmp15cfg, v[63..56]) + } + } +} diff --git a/sail_latex_riscv/fnzprepare_trap_vector90a104f40adfa987d74a613f4061790f.tex b/sail_latex_riscv/fnzprepare_trap_vector90a104f40adfa987d74a613f4061790f.tex new file mode 100644 index 00000000..513c25e1 --- /dev/null +++ b/sail_latex_riscv/fnzprepare_trap_vector90a104f40adfa987d74a613f4061790f.tex @@ -0,0 +1,15 @@ +function #\hyperref[sailRISCVzpreparezytrapzyvector]{prepare\_trap\_vector}#(p : Privilege, c : Mcause) -> xlenbits = { + let tcc : Capability = match p { + Machine => MTCC, + Supervisor => STCC, + User => UTCC + }; + + /* NB we use address, not offset here because even though tvec is the offset + we want the absolute address to insert in PC. The bottom two #\hyperref[sailRISCVzbits]{bits}# (mode) should + be the same because we enforce aligned tcc base. */ + match #\hyperref[sailRISCVztveczyaddr]{tvec\_addr}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(tcc.address), c) { + #\hyperref[sailRISCVzSome]{Some}#(addr) => { nextPCC = tcc; addr }, + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("Invalid tvec mode") + } +} diff --git a/sail_latex_riscv/fnzprepare_xret_target77691a306ebd6df5d988335f19693ba0.tex b/sail_latex_riscv/fnzprepare_xret_target77691a306ebd6df5d988335f19693ba0.tex new file mode 100644 index 00000000..47a513fc --- /dev/null +++ b/sail_latex_riscv/fnzprepare_xret_target77691a306ebd6df5d988335f19693ba0.tex @@ -0,0 +1,22 @@ +function #\hyperref[sailRISCVzpreparezyxretzytarget]{prepare\_xret\_target}#(p) = { + /* Similar to prepare_trap_vector above we need to return the absolute address + destined for PC, rather than the #\hyperref[sailRISCVzoffset]{offset}# (architecutral PC) */ + let epcc : Capability = match p { + Machine => MEPCC, + Supervisor => SEPCC, + User => UEPCC + }; + + let epcc = #\hyperref[sailRISCVzlegalizzezyepcc]{legalize\_epcc}#(epcc); + + /* + * Sentries unseal on transfer into nextPCC; other sealed types will trap + * with a seal violation later, when we go to do a fetch from nextPCC. + */ + let epcc = if epcc.otype == #\hyperref[sailRISCVztozybits]{to\_bits}#(cap_otype_width, otype_sentry) + then #\hyperref[sailRISCVzunsealCap]{unsealCap}#(epcc) + else epcc; + + nextPCC = epcc; + epcc.address +} diff --git a/sail_latex_riscv/fnzprint_insn34adb9871c343ddeeb08d9e768ad4c92.tex b/sail_latex_riscv/fnzprint_insn34adb9871c343ddeeb08d9e768ad4c92.tex new file mode 100644 index 00000000..42a9acc6 --- /dev/null +++ b/sail_latex_riscv/fnzprint_insn34adb9871c343ddeeb08d9e768ad4c92.tex @@ -0,0 +1 @@ +function print_insn insn = #\hyperref[sailRISCVzassembly]{assembly}#(insn) diff --git a/sail_latex_riscv/fnzprivilege_of_num84ee3b92a1b0c896120347634e28615d.tex b/sail_latex_riscv/fnzprivilege_of_num84ee3b92a1b0c896120347634e28615d.tex new file mode 100644 index 00000000..6b608105 --- /dev/null +++ b/sail_latex_riscv/fnzprivilege_of_num84ee3b92a1b0c896120347634e28615d.tex @@ -0,0 +1,5 @@ +function Privilege_of_num arg# = match arg# { + 0 => User, + 1 => Supervisor, + _ => Machine +} diff --git a/sail_latex_riscv/fnzprivlevel_of_bitsf8754d7aa9d9aeada7d193ecf64e148c.tex b/sail_latex_riscv/fnzprivlevel_of_bitsf8754d7aa9d9aeada7d193ecf64e148c.tex new file mode 100644 index 00000000..8eebbdd0 --- /dev/null +++ b/sail_latex_riscv/fnzprivlevel_of_bitsf8754d7aa9d9aeada7d193ecf64e148c.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzprivLevelzyofzybits]{privLevel\_of\_bits}# (p) = + match (p) { + 0b00 => User, + 0b01 => Supervisor, + 0b11 => Machine + } diff --git a/sail_latex_riscv/fnzprivlevel_to_bits4b6f72dec94db401093759e81957be6b.tex b/sail_latex_riscv/fnzprivlevel_to_bits4b6f72dec94db401093759e81957be6b.tex new file mode 100644 index 00000000..810c8120 --- /dev/null +++ b/sail_latex_riscv/fnzprivlevel_to_bits4b6f72dec94db401093759e81957be6b.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzprivLevelzytozybits]{privLevel\_to\_bits}# (p) = + match (p) { + User => 0b00, + Supervisor => 0b01, + Machine => 0b11 + } diff --git a/sail_latex_riscv/fnzprivlevel_to_str130b731da9dd60ea89c77efcbbe0d598.tex b/sail_latex_riscv/fnzprivlevel_to_str130b731da9dd60ea89c77efcbbe0d598.tex new file mode 100644 index 00000000..096a5adb --- /dev/null +++ b/sail_latex_riscv/fnzprivlevel_to_str130b731da9dd60ea89c77efcbbe0d598.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzprivLevelzytozystr]{privLevel\_to\_str}# (p) = + match (p) { + User => "U", + Supervisor => "S", + Machine => "M" + } diff --git a/sail_latex_riscv/fnzprocess_fload322b1b2657ee5e1571b2af7b0d3a6631b7.tex b/sail_latex_riscv/fnzprocess_fload322b1b2657ee5e1571b2af7b0d3a6631b7.tex new file mode 100644 index 00000000..1ab5dcf7 --- /dev/null +++ b/sail_latex_riscv/fnzprocess_fload322b1b2657ee5e1571b2af7b0d3a6631b7.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzprocesszyfload32]{process\_fload32}#(rd, addr, value) = + match value { + #\hyperref[sailRISCVzMemValue]{MemValue}#(result) => { #\hyperref[sailRISCVzF]{F}#(rd) = #\hyperref[sailRISCVznanzybox]{nan\_box}#(result); RETIRE_SUCCESS }, + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(addr, e); RETIRE_FAIL } + } diff --git a/sail_latex_riscv/fnzprocess_fload64aaf81fa4052296eb2993198993f6472c.tex b/sail_latex_riscv/fnzprocess_fload64aaf81fa4052296eb2993198993f6472c.tex new file mode 100644 index 00000000..27d4d1cb --- /dev/null +++ b/sail_latex_riscv/fnzprocess_fload64aaf81fa4052296eb2993198993f6472c.tex @@ -0,0 +1,10 @@ +function #\hyperref[sailRISCVzprocesszyfload64]{process\_fload64}#(rd, addr, value) = + if sizeof(flen) == 64 + then match value { + #\hyperref[sailRISCVzMemValue]{MemValue}#(result) => { #\hyperref[sailRISCVzF]{F}#(rd) = result; RETIRE_SUCCESS }, + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(addr, e); RETIRE_FAIL } + } + else { + /* should not get here */ + RETIRE_FAIL + } diff --git a/sail_latex_riscv/fnzprocess_fstoree9440c013cfdcc23312bc61d5762f1d1.tex b/sail_latex_riscv/fnzprocess_fstoree9440c013cfdcc23312bc61d5762f1d1.tex new file mode 100644 index 00000000..b392edb0 --- /dev/null +++ b/sail_latex_riscv/fnzprocess_fstoree9440c013cfdcc23312bc61d5762f1d1.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVzprocesszyfstore]{process\_fstore}#(vaddr, value) = + match value { + #\hyperref[sailRISCVzMemValue]{MemValue}#(true) => { RETIRE_SUCCESS }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(false) => { #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("store got false from mem_write_value") }, + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, e); RETIRE_FAIL } + } diff --git a/sail_latex_riscv/fnzprocess_load7d9288eb90dd41d1aa3c47eda679c483.tex b/sail_latex_riscv/fnzprocess_load7d9288eb90dd41d1aa3c47eda679c483.tex new file mode 100644 index 00000000..f3d1a8d3 --- /dev/null +++ b/sail_latex_riscv/fnzprocess_load7d9288eb90dd41d1aa3c47eda679c483.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzprocesszyload]{process\_load}#(rd, vaddr, value, is_unsigned) = + match #\hyperref[sailRISCVzextendzyvalue]{extend\_value}#(is_unsigned, value) { + #\hyperref[sailRISCVzMemValue]{MemValue}#(result) => { #\hyperref[sailRISCVzX]{X}#(rd) = result; RETIRE_SUCCESS }, + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(vaddr, e); RETIRE_FAIL } + } diff --git a/sail_latex_riscv/fnzprocess_loadres3acadfd67bd540642036cf41405a27c0.tex b/sail_latex_riscv/fnzprocess_loadres3acadfd67bd540642036cf41405a27c0.tex new file mode 100644 index 00000000..2eef6215 --- /dev/null +++ b/sail_latex_riscv/fnzprocess_loadres3acadfd67bd540642036cf41405a27c0.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzprocesszyloadres]{process\_loadres}#(rd, addr, value, is_unsigned) = + match #\hyperref[sailRISCVzextendzyvalue]{extend\_value}#(is_unsigned, value) { + #\hyperref[sailRISCVzMemValue]{MemValue}#(result) => { #\hyperref[sailRISCVzloadzyreservation]{load\_reservation}#(addr); #\hyperref[sailRISCVzX]{X}#(rd) = result; RETIRE_SUCCESS }, + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(addr, e); RETIRE_FAIL } + } diff --git a/sail_latex_riscv/fnzprocesspendingf31f33d163f06483630c9da88eafecaa.tex b/sail_latex_riscv/fnzprocesspendingf31f33d163f06483630c9da88eafecaa.tex new file mode 100644 index 00000000..25e1c3b8 --- /dev/null +++ b/sail_latex_riscv/fnzprocesspendingf31f33d163f06483630c9da88eafecaa.tex @@ -0,0 +1,13 @@ +function #\hyperref[sailRISCVzprocessPending]{processPending}#(xip : Minterrupts, xie : Minterrupts, xideleg : xlenbits, + priv_enabled : bool) -> interrupt_set = { + /* interrupts that are enabled but not delegated are pending */ + let effective_pend = xip.#\hyperref[sailRISCVzbits]{bits}#() & xie.#\hyperref[sailRISCVzbits]{bits}#() & (~ (xideleg)); + /* the others are delegated */ + let effective_delg = xip.#\hyperref[sailRISCVzbits]{bits}#() & xideleg; + /* we have pending interrupts if this privilege is enabled */ + if priv_enabled & (effective_pend != #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0)) + then #\hyperref[sailRISCVzIntszyPending]{Ints\_Pending}#(effective_pend) + else if effective_delg != #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0) + then #\hyperref[sailRISCVzIntszyDelegated]{Ints\_Delegated}#(effective_delg) + else #\hyperref[sailRISCVzIntszyEmpty]{Ints\_Empty}#() +} diff --git a/sail_latex_riscv/fnzptw_error_to_stra1d14633b5815718af0734f3fe6896fb.tex b/sail_latex_riscv/fnzptw_error_to_stra1d14633b5815718af0734f3fe6896fb.tex new file mode 100644 index 00000000..f938874e --- /dev/null +++ b/sail_latex_riscv/fnzptw_error_to_stra1d14633b5815718af0734f3fe6896fb.tex @@ -0,0 +1,10 @@ +function #\hyperref[sailRISCVzptwzyerrorzytozystr]{ptw\_error\_to\_str}#(e) = + match (e) { + #\hyperref[sailRISCVzPTWzyInvalidzyAddr]{PTW\_Invalid\_Addr}#() => "invalid-source-addr", + #\hyperref[sailRISCVzPTWzyAccess]{PTW\_Access}#() => "mem-access-error", + #\hyperref[sailRISCVzPTWzyInvalidzyPTE]{PTW\_Invalid\_PTE}#() => "invalid-pte", + #\hyperref[sailRISCVzPTWzyNozyPermission]{PTW\_No\_Permission}#() => "no-permission", + #\hyperref[sailRISCVzPTWzyMisaligned]{PTW\_Misaligned}#() => "misaligned-superpage", + #\hyperref[sailRISCVzPTWzyPTEzyUpdate]{PTW\_PTE\_Update}#() => "pte-update-needed", + #\hyperref[sailRISCVzPTWzyExtzyError]{PTW\_Ext\_Error}#(e) => "extension-error" + } diff --git a/sail_latex_riscv/fnzrc_bits18d7e232c147203cdc9c7cd0ffbe7ec0.tex b/sail_latex_riscv/fnzrc_bits18d7e232c147203cdc9c7cd0ffbe7ec0.tex new file mode 100644 index 00000000..b3f443c4 --- /dev/null +++ b/sail_latex_riscv/fnzrc_bits18d7e232c147203cdc9c7cd0ffbe7ec0.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzrCzybits]{rC\_bits}#(r: #\hyperref[sailRISCVzbits]{bits}#(5)) -> regtype = #\hyperref[sailRISCVzrC]{rC}#(#\hyperref[sailRISCVzunsigned]{unsigned}#(r)) diff --git a/sail_latex_riscv/fnzrcda9d82cd736deb89a37d9ca089373805.tex b/sail_latex_riscv/fnzrcda9d82cd736deb89a37d9ca089373805.tex new file mode 100644 index 00000000..ef280743 --- /dev/null +++ b/sail_latex_riscv/fnzrcda9d82cd736deb89a37d9ca089373805.tex @@ -0,0 +1,37 @@ +function rC r = { + match r { + 0 => zero_reg, + 1 => x1, + 2 => x2, + 3 => x3, + 4 => x4, + 5 => x5, + 6 => x6, + 7 => x7, + 8 => x8, + 9 => x9, + 10 => x10, + 11 => x11, + 12 => x12, + 13 => x13, + 14 => x14, + 15 => x15, + 16 => x16, + 17 => x17, + 18 => x18, + 19 => x19, + 20 => x20, + 21 => x21, + 22 => x22, + 23 => x23, + 24 => x24, + 25 => x25, + 26 => x26, + 27 => x27, + 28 => x28, + 29 => x29, + 30 => x30, + 31 => x31, + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("Invalid capability register") + } +} diff --git a/sail_latex_riscv/fnzread_kind_of_flagsbdfde0c548450764d5ed916ca1cb98ac.tex b/sail_latex_riscv/fnzread_kind_of_flagsbdfde0c548450764d5ed916ca1cb98ac.tex new file mode 100644 index 00000000..c315fece --- /dev/null +++ b/sail_latex_riscv/fnzread_kind_of_flagsbdfde0c548450764d5ed916ca1cb98ac.tex @@ -0,0 +1,11 @@ +function #\hyperref[sailRISCVzreadzykindzyofzyflags]{read\_kind\_of\_flags}# (aq : bool, rl : bool, res : bool) -> #\hyperref[sailRISCVzoption]{option}#(read_kind) = + match (aq, rl, res) { + (false, false, false) => #\hyperref[sailRISCVzSome]{Some}#(Read_plain), + (true, false, false) => #\hyperref[sailRISCVzSome]{Some}#(Read_RISCV_acquire), + (true, true, false) => #\hyperref[sailRISCVzSome]{Some}#(Read_RISCV_strong_acquire), + (false, false, true) => #\hyperref[sailRISCVzSome]{Some}#(Read_RISCV_reserved), + (true, false, true) => #\hyperref[sailRISCVzSome]{Some}#(Read_RISCV_reserved_acquire), + (true, true, true) => #\hyperref[sailRISCVzSome]{Some}#(Read_RISCV_reserved_strong_acquire), + (false, true, false) => #\hyperref[sailRISCVzNone]{None}#(), /* should these be instead throwing error_not_implemented as below? */ + (false, true, true) => #\hyperref[sailRISCVzNone]{None}#() + } diff --git a/sail_latex_riscv/fnzread_kind_of_numd8fea9b1331732e205bdd70279e0ba47.tex b/sail_latex_riscv/fnzread_kind_of_numd8fea9b1331732e205bdd70279e0ba47.tex new file mode 100644 index 00000000..4dbc0430 --- /dev/null +++ b/sail_latex_riscv/fnzread_kind_of_numd8fea9b1331732e205bdd70279e0ba47.tex @@ -0,0 +1,14 @@ +function read_kind_of_num arg# = match arg# { + 0 => Read_plain, + 1 => Read_reserve, + 2 => Read_acquire, + 3 => Read_exclusive, + 4 => Read_exclusive_acquire, + 5 => Read_stream, + 6 => Read_RISCV_acquire, + 7 => Read_RISCV_strong_acquire, + 8 => Read_RISCV_reserved, + 9 => Read_RISCV_reserved_acquire, + 10 => Read_RISCV_reserved_strong_acquire, + _ => Read_X86_locked +} diff --git a/sail_latex_riscv/fnzread_ram020d2ffaf84d982d4588177095c24b8e.tex b/sail_latex_riscv/fnzread_ram020d2ffaf84d982d4588177095c24b8e.tex new file mode 100644 index 00000000..a89114f7 --- /dev/null +++ b/sail_latex_riscv/fnzread_ram020d2ffaf84d982d4588177095c24b8e.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzreadzyram]{read\_ram}#(rk, addr, width, read_meta) = + let meta = if read_meta then #\hyperref[sailRISCVzzyzyReadRAMzyMeta]{\_\_ReadRAM\_Meta}#(addr, width) else default_meta in + (#\hyperref[sailRISCVzzyzyreadzymem]{\_\_read\_mem}#(rk, sizeof(xlen), addr, width), meta) diff --git a/sail_latex_riscv/fnzreadcsr1a9ed1f2dac4690038fbe34a4617edca.tex b/sail_latex_riscv/fnzreadcsr1a9ed1f2dac4690038fbe34a4617edca.tex new file mode 100644 index 00000000..e7addd2a --- /dev/null +++ b/sail_latex_riscv/fnzreadcsr1a9ed1f2dac4690038fbe34a4617edca.tex @@ -0,0 +1,87 @@ +function readCSR csr : csreg -> xlenbits = { + let res : xlenbits = + match (csr, sizeof(xlen)) { + /* machine mode */ + (0xF11, _) => #\hyperref[sailRISCVzEXTZ]{EXTZ}#(mvendorid), + (0xF12, _) => marchid, + (0xF13, _) => mimpid, + (0xF14, _) => mhartid, + (0x300, _) => mstatus.#\hyperref[sailRISCVzbits]{bits}#(), + (0x301, _) => misa.#\hyperref[sailRISCVzbits]{bits}#(), + (0x302, _) => medeleg.#\hyperref[sailRISCVzbits]{bits}#(), + (0x303, _) => mideleg.#\hyperref[sailRISCVzbits]{bits}#(), + (0x304, _) => mie.#\hyperref[sailRISCVzbits]{bits}#(), + (0x305, _) => #\hyperref[sailRISCVzgetzymtvec]{get\_mtvec}#(), + (0x306, _) => #\hyperref[sailRISCVzEXTZ]{EXTZ}#(mcounteren.#\hyperref[sailRISCVzbits]{bits}#()), + (0x320, _) => #\hyperref[sailRISCVzEXTZ]{EXTZ}#(mcountinhibit.#\hyperref[sailRISCVzbits]{bits}#()), + + (0x340, _) => mscratch, + (0x341, _) => #\hyperref[sailRISCVzgetzyxretzytarget]{get\_xret\_target}#(Machine) & #\hyperref[sailRISCVzpczyalignmentzymask]{pc\_alignment\_mask}#(), + (0x342, _) => mcause.#\hyperref[sailRISCVzbits]{bits}#(), + (0x343, _) => mtval, + (0x344, _) => mip.#\hyperref[sailRISCVzbits]{bits}#(), + + (0x3A0, _) => #\hyperref[sailRISCVzpmpReadCfgReg]{pmpReadCfgReg}#(0), // pmpcfg0 + (0x3A1, 32) => #\hyperref[sailRISCVzpmpReadCfgReg]{pmpReadCfgReg}#(1), // pmpcfg1 + (0x3A2, _) => #\hyperref[sailRISCVzpmpReadCfgReg]{pmpReadCfgReg}#(2), // pmpcfg2 + (0x3A3, 32) => #\hyperref[sailRISCVzpmpReadCfgReg]{pmpReadCfgReg}#(3), // pmpcfg3 + + (0x3B0, _) => pmpaddr0, + (0x3B1, _) => pmpaddr1, + (0x3B2, _) => pmpaddr2, + (0x3B3, _) => pmpaddr3, + (0x3B4, _) => pmpaddr4, + (0x3B5, _) => pmpaddr5, + (0x3B6, _) => pmpaddr6, + (0x3B7, _) => pmpaddr7, + (0x3B8, _) => pmpaddr8, + (0x3B9, _) => pmpaddr9, + (0x3BA, _) => pmpaddr10, + (0x3BB, _) => pmpaddr11, + (0x3BC, _) => pmpaddr12, + (0x3BD, _) => pmpaddr13, + (0x3BE, _) => pmpaddr14, + (0x3BF, _) => pmpaddr15, + + /* machine mode counters */ + (0xB00, _) => mcycle[(sizeof(xlen) - 1) .. 0], + (0xB02, _) => minstret[(sizeof(xlen) - 1) .. 0], + (0xB80, 32) => mcycle[63 .. 32], + (0xB82, 32) => minstret[63 .. 32], + + /* trigger/debug */ + (0x7a0, _) => ~(tselect), /* this indicates we don't have any trigger support */ + + /* supervisor mode */ + (0x100, _) => #\hyperref[sailRISCVzlowerzymstatus]{lower\_mstatus}#(mstatus).#\hyperref[sailRISCVzbits]{bits}#(), + (0x102, _) => sedeleg.#\hyperref[sailRISCVzbits]{bits}#(), + (0x103, _) => sideleg.#\hyperref[sailRISCVzbits]{bits}#(), + (0x104, _) => #\hyperref[sailRISCVzlowerzymie]{lower\_mie}#(mie, mideleg).#\hyperref[sailRISCVzbits]{bits}#(), + (0x105, _) => #\hyperref[sailRISCVzgetzystvec]{get\_stvec}#(), + (0x106, _) => #\hyperref[sailRISCVzEXTZ]{EXTZ}#(scounteren.#\hyperref[sailRISCVzbits]{bits}#()), + (0x140, _) => sscratch, + (0x141, _) => #\hyperref[sailRISCVzgetzyxretzytarget]{get\_xret\_target}#(Supervisor) & #\hyperref[sailRISCVzpczyalignmentzymask]{pc\_alignment\_mask}#(), + (0x142, _) => scause.#\hyperref[sailRISCVzbits]{bits}#(), + (0x143, _) => stval, + (0x144, _) => #\hyperref[sailRISCVzlowerzymip]{lower\_mip}#(mip, mideleg).#\hyperref[sailRISCVzbits]{bits}#(), + (0x180, _) => satp, + + /* user mode counters */ + (0xC00, _) => mcycle[(sizeof(xlen) - 1) .. 0], + (0xC01, _) => mtime[(sizeof(xlen) - 1) .. 0], + (0xC02, _) => minstret[(sizeof(xlen) - 1) .. 0], + (0xC80, 32) => mcycle[63 .. 32], + (0xC81, 32) => mtime[63 .. 32], + (0xC82, 32) => minstret[63 .. 32], + + _ => /* check extensions */ + match #\hyperref[sailRISCVzextzyreadzyCSR]{ext\_read\_CSR}#(csr) { + #\hyperref[sailRISCVzSome]{Some}#(res) => res, + #\hyperref[sailRISCVzNone]{None}#() => { #\hyperref[sailRISCVzprintzybits]{print\_bits}#("unhandled read to CSR ", csr); + #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0x0) } + } + }; + if #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}#() + then #\hyperref[sailRISCVzprintzyreg]{print\_reg}#("CSR " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(csr) ^ " -> " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(res)); + res +} diff --git a/sail_latex_riscv/fnzreg_name_abi8c36e923dc671675cb54fb0175878a3f.tex b/sail_latex_riscv/fnzreg_name_abi8c36e923dc671675cb54fb0175878a3f.tex new file mode 100644 index 00000000..1bea85f2 --- /dev/null +++ b/sail_latex_riscv/fnzreg_name_abi8c36e923dc671675cb54fb0175878a3f.tex @@ -0,0 +1,36 @@ +function #\hyperref[sailRISCVzregzynamezyabi]{reg\_name\_abi}#(r) = { + match (r) { + 0b00000 => "zero", + 0b00001 => "ra", + 0b00010 => "sp", + 0b00011 => "gp", + 0b00100 => "tp", + 0b00101 => "t0", + 0b00110 => "t1", + 0b00111 => "t2", + 0b01000 => "fp", + 0b01001 => "s1", + 0b01010 => "a0", + 0b01011 => "a1", + 0b01100 => "a2", + 0b01101 => "a3", + 0b01110 => "a4", + 0b01111 => "a5", + 0b10000 => "a6", + 0b10001 => "a7", + 0b10010 => "s2", + 0b10011 => "s3", + 0b10100 => "s4", + 0b10101 => "s5", + 0b10110 => "s6", + 0b10111 => "s7", + 0b11000 => "s8", + 0b11001 => "s9", + 0b11010 => "s10", + 0b11011 => "s11", + 0b11100 => "t3", + 0b11101 => "t4", + 0b11110 => "t5", + 0b11111 => "t6" + } +} diff --git a/sail_latex_riscv/fnzregidx_to_regno46c7ee8e863ba355f36bf094aa680714.tex b/sail_latex_riscv/fnzregidx_to_regno46c7ee8e863ba355f36bf094aa680714.tex new file mode 100644 index 00000000..ffc7da4c --- /dev/null +++ b/sail_latex_riscv/fnzregidx_to_regno46c7ee8e863ba355f36bf094aa680714.tex @@ -0,0 +1 @@ +function regidx_to_regno b = let 'r = #\hyperref[sailRISCVzunsigned]{unsigned}#(b) in r diff --git a/sail_latex_riscv/fnzregstrf07d744c662238e6879fb1aee407788d.tex b/sail_latex_riscv/fnzregstrf07d744c662238e6879fb1aee407788d.tex new file mode 100644 index 00000000..64e4c7be --- /dev/null +++ b/sail_latex_riscv/fnzregstrf07d744c662238e6879fb1aee407788d.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzRegStr]{RegStr}#(r) = #\hyperref[sailRISCVzcapToString]{capToString}#(r) diff --git a/sail_latex_riscv/fnzregval_from_rega072b7983f1f9ac4a9021e76a911b9c9.tex b/sail_latex_riscv/fnzregval_from_rega072b7983f1f9ac4a9021e76a911b9c9.tex new file mode 100644 index 00000000..3f9d0433 --- /dev/null +++ b/sail_latex_riscv/fnzregval_from_rega072b7983f1f9ac4a9021e76a911b9c9.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzregvalzyfromzyreg]{regval\_from\_reg}#(r) = r.address diff --git a/sail_latex_riscv/fnzregval_into_reg03a5bdeabb3e6169090e6ed21f1a84cb.tex b/sail_latex_riscv/fnzregval_into_reg03a5bdeabb3e6169090e6ed21f1a84cb.tex new file mode 100644 index 00000000..5b310ea6 --- /dev/null +++ b/sail_latex_riscv/fnzregval_into_reg03a5bdeabb3e6169090e6ed21f1a84cb.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzregvalzyintozyreg]{regval\_into\_reg}#(v) = {null_cap with address = v} diff --git a/sail_latex_riscv/fnzretire_instructionc9e2e6b25fd8f4e5a96cd82a0dd2a675.tex b/sail_latex_riscv/fnzretire_instructionc9e2e6b25fd8f4e5a96cd82a0dd2a675.tex new file mode 100644 index 00000000..48f91abb --- /dev/null +++ b/sail_latex_riscv/fnzretire_instructionc9e2e6b25fd8f4e5a96cd82a0dd2a675.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzretirezyinstruction]{retire\_instruction}#() -> unit = { + if minstret_written == true + then minstret_written = false + else minstret = minstret + 1 +} diff --git a/sail_latex_riscv/fnzretired_of_num68ab3748534f762d814246f11fcf7c77.tex b/sail_latex_riscv/fnzretired_of_num68ab3748534f762d814246f11fcf7c77.tex new file mode 100644 index 00000000..a519a889 --- /dev/null +++ b/sail_latex_riscv/fnzretired_of_num68ab3748534f762d814246f11fcf7c77.tex @@ -0,0 +1,4 @@ +function Retired_of_num arg# = match arg# { + 0 => RETIRE_SUCCESS, + _ => RETIRE_FAIL +} diff --git a/sail_latex_riscv/fnzrf_bits63ac239a90c8d4bdc4ca1b8375c08531.tex b/sail_latex_riscv/fnzrf_bits63ac239a90c8d4bdc4ca1b8375c08531.tex new file mode 100644 index 00000000..b9d0f6b9 --- /dev/null +++ b/sail_latex_riscv/fnzrf_bits63ac239a90c8d4bdc4ca1b8375c08531.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzrFzybits]{rF\_bits}#(i: #\hyperref[sailRISCVzbits]{bits}#(5)) -> flenbits = #\hyperref[sailRISCVzrF]{rF}#(#\hyperref[sailRISCVzunsigned]{unsigned}#(i)) diff --git a/sail_latex_riscv/fnzrff2ed1bbacd3ac737af7186c6d8884885.tex b/sail_latex_riscv/fnzrff2ed1bbacd3ac737af7186c6d8884885.tex new file mode 100644 index 00000000..2323889f --- /dev/null +++ b/sail_latex_riscv/fnzrff2ed1bbacd3ac737af7186c6d8884885.tex @@ -0,0 +1,39 @@ +function rF r = { + let v : fregtype = + match r { + 0 => f0, + 1 => f1, + 2 => f2, + 3 => f3, + 4 => f4, + 5 => f5, + 6 => f6, + 7 => f7, + 8 => f8, + 9 => f9, + 10 => f10, + 11 => f11, + 12 => f12, + 13 => f13, + 14 => f14, + 15 => f15, + 16 => f16, + 17 => f17, + 18 => f18, + 19 => f19, + 20 => f20, + 21 => f21, + 22 => f22, + 23 => f23, + 24 => f24, + 25 => f25, + 26 => f26, + 27 => f27, + 28 => f28, + 29 => f29, + 30 => f30, + 31 => f31, + _ => {assert(false, "invalid floating point register number"); zero_freg} + }; + #\hyperref[sailRISCVzfregvalzyfromzyfreg]{fregval\_from\_freg}#(v) +} diff --git a/sail_latex_riscv/fnzriscv_f32add558e9569237c3f82255e78eba6e4d963.tex b/sail_latex_riscv/fnzriscv_f32add558e9569237c3f82255e78eba6e4d963.tex new file mode 100644 index 00000000..7364657d --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32add558e9569237c3f82255e78eba6e4d963.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32Add]{riscv\_f32Add}# (rm, v1, v2) = { + #\hyperref[sailRISCVzexternzyf32Add]{extern\_f32Add}#(rm, v1, v2); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f32div86cc53dd9bb61e6f44380c708e0673ca.tex b/sail_latex_riscv/fnzriscv_f32div86cc53dd9bb61e6f44380c708e0673ca.tex new file mode 100644 index 00000000..cf914adc --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32div86cc53dd9bb61e6f44380c708e0673ca.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32Div]{riscv\_f32Div}# (rm, v1, v2) = { + #\hyperref[sailRISCVzexternzyf32Div]{extern\_f32Div}#(rm, v1, v2); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f32eqbb5f45f4706cd2893dcaf9d3d15d7b11.tex b/sail_latex_riscv/fnzriscv_f32eqbb5f45f4706cd2893dcaf9d3d15d7b11.tex new file mode 100644 index 00000000..b11dfa74 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32eqbb5f45f4706cd2893dcaf9d3d15d7b11.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32Eq]{riscv\_f32Eq}# (v1, v2) = { + #\hyperref[sailRISCVzexternzyf32Eq]{extern\_f32Eq}#(v1, v2); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f32le5580a4448a4b6b5ef89a7a80b6f5e23a.tex b/sail_latex_riscv/fnzriscv_f32le5580a4448a4b6b5ef89a7a80b6f5e23a.tex new file mode 100644 index 00000000..44287f50 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32le5580a4448a4b6b5ef89a7a80b6f5e23a.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32Le]{riscv\_f32Le}# (v1, v2) = { + #\hyperref[sailRISCVzexternzyf32Le]{extern\_f32Le}#(v1, v2); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f32lt4e30f0abd945d0950f5c75c3397e58b8.tex b/sail_latex_riscv/fnzriscv_f32lt4e30f0abd945d0950f5c75c3397e58b8.tex new file mode 100644 index 00000000..65ad71bc --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32lt4e30f0abd945d0950f5c75c3397e58b8.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32Lt]{riscv\_f32Lt}# (v1, v2) = { + #\hyperref[sailRISCVzexternzyf32Lt]{extern\_f32Lt}#(v1, v2); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f32muladdc6b7d5aa910c0cf67022d34e7a745cd8.tex b/sail_latex_riscv/fnzriscv_f32muladdc6b7d5aa910c0cf67022d34e7a745cd8.tex new file mode 100644 index 00000000..2ded7a46 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32muladdc6b7d5aa910c0cf67022d34e7a745cd8.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32MulAdd]{riscv\_f32MulAdd}# (rm, v1, v2, v3) = { + #\hyperref[sailRISCVzexternzyf32MulAdd]{extern\_f32MulAdd}#(rm, v1, v2, v3); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f32mulc9ec954a141b4f26110e9e3c2b42b73c.tex b/sail_latex_riscv/fnzriscv_f32mulc9ec954a141b4f26110e9e3c2b42b73c.tex new file mode 100644 index 00000000..f53b0c10 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32mulc9ec954a141b4f26110e9e3c2b42b73c.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32Mul]{riscv\_f32Mul}# (rm, v1, v2) = { + #\hyperref[sailRISCVzexternzyf32Mul]{extern\_f32Mul}#(rm, v1, v2); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f32sqrtd0c4078227e28f52a7984b6a7f89ce8a.tex b/sail_latex_riscv/fnzriscv_f32sqrtd0c4078227e28f52a7984b6a7f89ce8a.tex new file mode 100644 index 00000000..3f239cff --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32sqrtd0c4078227e28f52a7984b6a7f89ce8a.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32Sqrt]{riscv\_f32Sqrt}# (rm, v) = { + #\hyperref[sailRISCVzexternzyf32Sqrt]{extern\_f32Sqrt}#(rm, v); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f32sub247ea008998dd84d9a3c22db11127bea.tex b/sail_latex_riscv/fnzriscv_f32sub247ea008998dd84d9a3c22db11127bea.tex new file mode 100644 index 00000000..6b4b8a02 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32sub247ea008998dd84d9a3c22db11127bea.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32Sub]{riscv\_f32Sub}# (rm, v1, v2) = { + #\hyperref[sailRISCVzexternzyf32Sub]{extern\_f32Sub}#(rm, v1, v2); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f32tof6463cfa807ac39aea5d45f7cb4ee2d9248.tex b/sail_latex_riscv/fnzriscv_f32tof6463cfa807ac39aea5d45f7cb4ee2d9248.tex new file mode 100644 index 00000000..6276e86a --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32tof6463cfa807ac39aea5d45f7cb4ee2d9248.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32ToF64]{riscv\_f32ToF64}# (rm, v) = { + #\hyperref[sailRISCVzexternzyf32ToF64]{extern\_f32ToF64}#(rm, v); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_f32toi32b5d471852e14b8b79d2ad8fd065ac832.tex b/sail_latex_riscv/fnzriscv_f32toi32b5d471852e14b8b79d2ad8fd065ac832.tex new file mode 100644 index 00000000..975bb0d6 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32toi32b5d471852e14b8b79d2ad8fd065ac832.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32ToI32]{riscv\_f32ToI32}# (rm, v) = { + #\hyperref[sailRISCVzexternzyf32ToI32]{extern\_f32ToI32}#(rm, v); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f32toi640208fd5f6c45fde93d3e7c63a2825d81.tex b/sail_latex_riscv/fnzriscv_f32toi640208fd5f6c45fde93d3e7c63a2825d81.tex new file mode 100644 index 00000000..607b43e8 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32toi640208fd5f6c45fde93d3e7c63a2825d81.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32ToI64]{riscv\_f32ToI64}# (rm, v) = { + #\hyperref[sailRISCVzexternzyf32ToI64]{extern\_f32ToI64}#(rm, v); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_f32toui329abf292f8a5b1458fd639f0b62a9b052.tex b/sail_latex_riscv/fnzriscv_f32toui329abf292f8a5b1458fd639f0b62a9b052.tex new file mode 100644 index 00000000..318a7825 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32toui329abf292f8a5b1458fd639f0b62a9b052.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32ToUi32]{riscv\_f32ToUi32}# (rm, v) = { + #\hyperref[sailRISCVzexternzyf32ToUi32]{extern\_f32ToUi32}#(rm, v); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f32toui6423479b6a7ca0f54a5c926da7d7620403.tex b/sail_latex_riscv/fnzriscv_f32toui6423479b6a7ca0f54a5c926da7d7620403.tex new file mode 100644 index 00000000..9307f815 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f32toui6423479b6a7ca0f54a5c926da7d7620403.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf32ToUi64]{riscv\_f32ToUi64}# (rm, v) = { + #\hyperref[sailRISCVzexternzyf32ToUi64]{extern\_f32ToUi64}#(rm, v); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_f64add33e6272fa354fe4e7b1963d6545bc4f7.tex b/sail_latex_riscv/fnzriscv_f64add33e6272fa354fe4e7b1963d6545bc4f7.tex new file mode 100644 index 00000000..e2b47713 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64add33e6272fa354fe4e7b1963d6545bc4f7.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64Add]{riscv\_f64Add}# (rm, v1, v2) = { + #\hyperref[sailRISCVzexternzyf64Add]{extern\_f64Add}#(rm, v1, v2); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_f64divecc62207bb7fa437fcf66a19597ada83.tex b/sail_latex_riscv/fnzriscv_f64divecc62207bb7fa437fcf66a19597ada83.tex new file mode 100644 index 00000000..3c12b6ca --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64divecc62207bb7fa437fcf66a19597ada83.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64Div]{riscv\_f64Div}# (rm, v1, v2) = { + #\hyperref[sailRISCVzexternzyf64Div]{extern\_f64Div}#(rm, v1, v2); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_f64eq911a3686fab30a7dbcecd0d21d7bc788.tex b/sail_latex_riscv/fnzriscv_f64eq911a3686fab30a7dbcecd0d21d7bc788.tex new file mode 100644 index 00000000..37da06a5 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64eq911a3686fab30a7dbcecd0d21d7bc788.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64Eq]{riscv\_f64Eq}# (v1, v2) = { + #\hyperref[sailRISCVzexternzyf64Eq]{extern\_f64Eq}#(v1, v2); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_f64leedff2d39af8855d31503064db9e49593.tex b/sail_latex_riscv/fnzriscv_f64leedff2d39af8855d31503064db9e49593.tex new file mode 100644 index 00000000..0afeb066 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64leedff2d39af8855d31503064db9e49593.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64Le]{riscv\_f64Le}# (v1, v2) = { + #\hyperref[sailRISCVzexternzyf64Le]{extern\_f64Le}#(v1, v2); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_f64lt7fe1cae2d039f2771557eafe4cff0d62.tex b/sail_latex_riscv/fnzriscv_f64lt7fe1cae2d039f2771557eafe4cff0d62.tex new file mode 100644 index 00000000..73289a5b --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64lt7fe1cae2d039f2771557eafe4cff0d62.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64Lt]{riscv\_f64Lt}# (v1, v2) = { + #\hyperref[sailRISCVzexternzyf64Lt]{extern\_f64Lt}#(v1, v2); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_f64mul1bf597fee8433219c830072b7c0b998e.tex b/sail_latex_riscv/fnzriscv_f64mul1bf597fee8433219c830072b7c0b998e.tex new file mode 100644 index 00000000..4a2ddcfa --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64mul1bf597fee8433219c830072b7c0b998e.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64Mul]{riscv\_f64Mul}# (rm, v1, v2) = { + #\hyperref[sailRISCVzexternzyf64Mul]{extern\_f64Mul}#(rm, v1, v2); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_f64muladdf20eb35780f2858aa3087b34aba2250a.tex b/sail_latex_riscv/fnzriscv_f64muladdf20eb35780f2858aa3087b34aba2250a.tex new file mode 100644 index 00000000..6ecfab75 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64muladdf20eb35780f2858aa3087b34aba2250a.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64MulAdd]{riscv\_f64MulAdd}# (rm, v1, v2, v3) = { + #\hyperref[sailRISCVzexternzyf64MulAdd]{extern\_f64MulAdd}#(rm, v1, v2, v3); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_f64sqrta506b6089ecf799deb21b124eaf60f0c.tex b/sail_latex_riscv/fnzriscv_f64sqrta506b6089ecf799deb21b124eaf60f0c.tex new file mode 100644 index 00000000..81bff222 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64sqrta506b6089ecf799deb21b124eaf60f0c.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64Sqrt]{riscv\_f64Sqrt}# (rm, v) = { + #\hyperref[sailRISCVzexternzyf64Sqrt]{extern\_f64Sqrt}#(rm, v); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_f64sub64a17c7e3b243ed3af4bc99790d41a9f.tex b/sail_latex_riscv/fnzriscv_f64sub64a17c7e3b243ed3af4bc99790d41a9f.tex new file mode 100644 index 00000000..520729fb --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64sub64a17c7e3b243ed3af4bc99790d41a9f.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64Sub]{riscv\_f64Sub}# (rm, v1, v2) = { + #\hyperref[sailRISCVzexternzyf64Sub]{extern\_f64Sub}#(rm, v1, v2); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_f64tof326b35917fadbed27b5d3cecd2f8762d01.tex b/sail_latex_riscv/fnzriscv_f64tof326b35917fadbed27b5d3cecd2f8762d01.tex new file mode 100644 index 00000000..47f3e884 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64tof326b35917fadbed27b5d3cecd2f8762d01.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64ToF32]{riscv\_f64ToF32}# (rm, v) = { + #\hyperref[sailRISCVzexternzyf64ToF32]{extern\_f64ToF32}#(rm, v); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f64toi32390e064989835e074118b56d834e6d48.tex b/sail_latex_riscv/fnzriscv_f64toi32390e064989835e074118b56d834e6d48.tex new file mode 100644 index 00000000..c00a8259 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64toi32390e064989835e074118b56d834e6d48.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64ToI32]{riscv\_f64ToI32}# (rm, v) = { + #\hyperref[sailRISCVzexternzyf64ToI32]{extern\_f64ToI32}#(rm, v); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f64toi64b279b582ab789b7d76bd4628cf864db9.tex b/sail_latex_riscv/fnzriscv_f64toi64b279b582ab789b7d76bd4628cf864db9.tex new file mode 100644 index 00000000..1655bbb2 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64toi64b279b582ab789b7d76bd4628cf864db9.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64ToI64]{riscv\_f64ToI64}# (rm, v) = { + #\hyperref[sailRISCVzexternzyf64ToI64]{extern\_f64ToI64}#(rm, v); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_f64toui32df8698a76aef244e4d021f6db07ed8aa.tex b/sail_latex_riscv/fnzriscv_f64toui32df8698a76aef244e4d021f6db07ed8aa.tex new file mode 100644 index 00000000..fe6e854c --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64toui32df8698a76aef244e4d021f6db07ed8aa.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64ToUi32]{riscv\_f64ToUi32}# (rm, v) = { + #\hyperref[sailRISCVzexternzyf64ToUi32]{extern\_f64ToUi32}#(rm, v); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_f64toui64a8c06df736f513b3e5ec73bfb9385733.tex b/sail_latex_riscv/fnzriscv_f64toui64a8c06df736f513b3e5ec73bfb9385733.tex new file mode 100644 index 00000000..f72576f6 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_f64toui64a8c06df736f513b3e5ec73bfb9385733.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyf64ToUi64]{riscv\_f64ToUi64}# (rm, v) = { + #\hyperref[sailRISCVzexternzyf64ToUi64]{extern\_f64ToUi64}#(rm, v); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_i32tof32262d900b5276fc61cfada0a2c080dd00.tex b/sail_latex_riscv/fnzriscv_i32tof32262d900b5276fc61cfada0a2c080dd00.tex new file mode 100644 index 00000000..70e62e5c --- /dev/null +++ b/sail_latex_riscv/fnzriscv_i32tof32262d900b5276fc61cfada0a2c080dd00.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyi32ToF32]{riscv\_i32ToF32}# (rm, v) = { + #\hyperref[sailRISCVzexternzyi32ToF32]{extern\_i32ToF32}#(rm, v); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_i32tof64e97e000de9456cb796f52f30b64c9715.tex b/sail_latex_riscv/fnzriscv_i32tof64e97e000de9456cb796f52f30b64c9715.tex new file mode 100644 index 00000000..c42904fd --- /dev/null +++ b/sail_latex_riscv/fnzriscv_i32tof64e97e000de9456cb796f52f30b64c9715.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyi32ToF64]{riscv\_i32ToF64}# (rm, v) = { + #\hyperref[sailRISCVzexternzyi32ToF64]{extern\_i32ToF64}#(rm, v); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_i64tof329ea93669bfe183b3595b128f97eb0d64.tex b/sail_latex_riscv/fnzriscv_i64tof329ea93669bfe183b3595b128f97eb0d64.tex new file mode 100644 index 00000000..ebad0453 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_i64tof329ea93669bfe183b3595b128f97eb0d64.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyi64ToF32]{riscv\_i64ToF32}# (rm, v) = { + #\hyperref[sailRISCVzexternzyi64ToF32]{extern\_i64ToF32}#(rm, v); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_i64tof645552b730328b5e488a5469c4d60ba48e.tex b/sail_latex_riscv/fnzriscv_i64tof645552b730328b5e488a5469c4d60ba48e.tex new file mode 100644 index 00000000..19c78e28 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_i64tof645552b730328b5e488a5469c4d60ba48e.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyi64ToF64]{riscv\_i64ToF64}# (rm, v) = { + #\hyperref[sailRISCVzexternzyi64ToF64]{extern\_i64ToF64}#(rm, v); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_ui32tof3277c5e2e314e991c265ecd083fea05bf0.tex b/sail_latex_riscv/fnzriscv_ui32tof3277c5e2e314e991c265ecd083fea05bf0.tex new file mode 100644 index 00000000..a6a93d94 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_ui32tof3277c5e2e314e991c265ecd083fea05bf0.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyui32ToF32]{riscv\_ui32ToF32}# (rm, v) = { + #\hyperref[sailRISCVzexternzyui32ToF32]{extern\_ui32ToF32}#(rm, v); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_ui32tof6485dd2d5d0818e64745a16c8bd2e6f3ad.tex b/sail_latex_riscv/fnzriscv_ui32tof6485dd2d5d0818e64745a16c8bd2e6f3ad.tex new file mode 100644 index 00000000..1f94351d --- /dev/null +++ b/sail_latex_riscv/fnzriscv_ui32tof6485dd2d5d0818e64745a16c8bd2e6f3ad.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyui32ToF64]{riscv\_ui32ToF64}# (rm, v) = { + #\hyperref[sailRISCVzexternzyui32ToF64]{extern\_ui32ToF64}#(rm, v); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzriscv_ui64tof32006c37b85131ebfdf4c65a0ecf2d321b.tex b/sail_latex_riscv/fnzriscv_ui64tof32006c37b85131ebfdf4c65a0ecf2d321b.tex new file mode 100644 index 00000000..be9e558c --- /dev/null +++ b/sail_latex_riscv/fnzriscv_ui64tof32006c37b85131ebfdf4c65a0ecf2d321b.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyui64ToF32]{riscv\_ui64ToF32}# (rm, v) = { + #\hyperref[sailRISCVzexternzyui64ToF32]{extern\_ui64ToF32}#(rm, v); + (float_fflags[4 .. 0], float_result[31 .. 0]) +} diff --git a/sail_latex_riscv/fnzriscv_ui64tof647831c3694f6a0849ff1899ade6b08220.tex b/sail_latex_riscv/fnzriscv_ui64tof647831c3694f6a0849ff1899ade6b08220.tex new file mode 100644 index 00000000..836c1916 --- /dev/null +++ b/sail_latex_riscv/fnzriscv_ui64tof647831c3694f6a0849ff1899ade6b08220.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzriscvzyui64ToF64]{riscv\_ui64ToF64}# (rm, v) = { + #\hyperref[sailRISCVzexternzyui64ToF64]{extern\_ui64ToF64}#(rm, v); + (float_fflags[4 .. 0], float_result) +} diff --git a/sail_latex_riscv/fnzrop_of_numdb49159dd280dafb7370c6477b545c05.tex b/sail_latex_riscv/fnzrop_of_numdb49159dd280dafb7370c6477b545c05.tex new file mode 100644 index 00000000..8a884ed3 --- /dev/null +++ b/sail_latex_riscv/fnzrop_of_numdb49159dd280dafb7370c6477b545c05.tex @@ -0,0 +1,12 @@ +function rop_of_num arg# = match arg# { + 0 => RISCV_ADD, + 1 => RISCV_SUB, + 2 => RISCV_SLL, + 3 => RISCV_SLT, + 4 => RISCV_SLTU, + 5 => RISCV_XOR, + 6 => RISCV_SRL, + 7 => RISCV_SRA, + 8 => RISCV_OR, + _ => RISCV_AND +} diff --git a/sail_latex_riscv/fnzropw_of_numbc49d41e4663ce1e2313189dca74c7f1.tex b/sail_latex_riscv/fnzropw_of_numbc49d41e4663ce1e2313189dca74c7f1.tex new file mode 100644 index 00000000..200ca7bc --- /dev/null +++ b/sail_latex_riscv/fnzropw_of_numbc49d41e4663ce1e2313189dca74c7f1.tex @@ -0,0 +1,7 @@ +function ropw_of_num arg# = match arg# { + 0 => RISCV_ADDW, + 1 => RISCV_SUBW, + 2 => RISCV_SLLW, + 3 => RISCV_SRLW, + _ => RISCV_SRAW +} diff --git a/sail_latex_riscv/fnzrounding_mode_of_num6135245be40748c506fabd0190282238.tex b/sail_latex_riscv/fnzrounding_mode_of_num6135245be40748c506fabd0190282238.tex new file mode 100644 index 00000000..a7597046 --- /dev/null +++ b/sail_latex_riscv/fnzrounding_mode_of_num6135245be40748c506fabd0190282238.tex @@ -0,0 +1,8 @@ +function rounding_mode_of_num arg# = match arg# { + 0 => RM_RNE, + 1 => RM_RTZ, + 2 => RM_RDN, + 3 => RM_RUP, + 4 => RM_RMM, + _ => RM_DYN +} diff --git a/sail_latex_riscv/fnzrvfi_readaee7411fcd70e67f9e6d2f7f9f563435.tex b/sail_latex_riscv/fnzrvfi_readaee7411fcd70e67f9e6d2f7f9f563435.tex new file mode 100644 index 00000000..1f776ddf --- /dev/null +++ b/sail_latex_riscv/fnzrvfi_readaee7411fcd70e67f9e6d2f7f9f563435.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzrvfizyread]{rvfi\_read}# (addr, width, value) = () diff --git a/sail_latex_riscv/fnzrvfi_trap0d0ddd87deff120444aa8feac182c6ce.tex b/sail_latex_riscv/fnzrvfi_trap0d0ddd87deff120444aa8feac182c6ce.tex new file mode 100644 index 00000000..74deea6b --- /dev/null +++ b/sail_latex_riscv/fnzrvfi_trap0d0ddd87deff120444aa8feac182c6ce.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzrvfizytrap]{rvfi\_trap}# () = () diff --git a/sail_latex_riscv/fnzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex b/sail_latex_riscv/fnzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex new file mode 100644 index 00000000..7871d6d3 --- /dev/null +++ b/sail_latex_riscv/fnzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzrvfizywrite]{rvfi\_write}# (addr, width, value) = () diff --git a/sail_latex_riscv/fnzrvfi_wxed842ecfeb56ef18626194f2f22935f3.tex b/sail_latex_riscv/fnzrvfi_wxed842ecfeb56ef18626194f2f22935f3.tex new file mode 100644 index 00000000..1e19b284 --- /dev/null +++ b/sail_latex_riscv/fnzrvfi_wxed842ecfeb56ef18626194f2f22935f3.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzrvfizywX]{rvfi\_wX}# (r,v) = () diff --git a/sail_latex_riscv/fnzrx_bitsba4d35e6c426ac476fdbf36efdd5d0da.tex b/sail_latex_riscv/fnzrx_bitsba4d35e6c426ac476fdbf36efdd5d0da.tex new file mode 100644 index 00000000..393e87b1 --- /dev/null +++ b/sail_latex_riscv/fnzrx_bitsba4d35e6c426ac476fdbf36efdd5d0da.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzrXzybits]{rX\_bits}#(i: #\hyperref[sailRISCVzbits]{bits}#(5)) -> xlenbits = #\hyperref[sailRISCVzrX]{rX}#(#\hyperref[sailRISCVzunsigned]{unsigned}#(i)) diff --git a/sail_latex_riscv/fnzrxa8aad9466d0653707390b940aa9282e7.tex b/sail_latex_riscv/fnzrxa8aad9466d0653707390b940aa9282e7.tex new file mode 100644 index 00000000..b92330ab --- /dev/null +++ b/sail_latex_riscv/fnzrxa8aad9466d0653707390b940aa9282e7.tex @@ -0,0 +1,39 @@ +function rX r = { + let v : regtype = + match r { + 0 => zero_reg, + 1 => x1, + 2 => x2, + 3 => x3, + 4 => x4, + 5 => x5, + 6 => x6, + 7 => x7, + 8 => x8, + 9 => x9, + 10 => x10, + 11 => x11, + 12 => x12, + 13 => x13, + 14 => x14, + 15 => x15, + 16 => x16, + 17 => x17, + 18 => x18, + 19 => x19, + 20 => x20, + 21 => x21, + 22 => x22, + 23 => x23, + 24 => x24, + 25 => x25, + 26 => x26, + 27 => x27, + 28 => x28, + 29 => x29, + 30 => x30, + 31 => x31, + _ => {assert(false, "invalid register number"); zero_reg} + }; + #\hyperref[sailRISCVzregvalzyfromzyreg]{regval\_from\_reg}#(v) +} diff --git a/sail_latex_riscv/fnzsail_maske146b73afc824e90813dd8234bfa3053.tex b/sail_latex_riscv/fnzsail_maske146b73afc824e90813dd8234bfa3053.tex new file mode 100644 index 00000000..e7045be5 --- /dev/null +++ b/sail_latex_riscv/fnzsail_maske146b73afc824e90813dd8234bfa3053.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzsailzymask]{sail\_mask}#(len, v) = if len <= #\hyperref[sailRISCVzlength]{length}#(v) then #\hyperref[sailRISCVztruncate]{truncate}#(v, len) else #\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(v, len) diff --git a/sail_latex_riscv/fnzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex b/sail_latex_riscv/fnzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex new file mode 100644 index 00000000..33e4a01b --- /dev/null +++ b/sail_latex_riscv/fnzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzsailzyones]{sail\_ones}#(n) = #\hyperref[sailRISCVznotzyvec]{not\_vec}#(#\hyperref[sailRISCVzsailzyzzeros]{sail\_zeros}#(n)) diff --git a/sail_latex_riscv/fnzsatp64mode_of_bits11c1e0e3eda64d7361d8ec4950c9f1ea.tex b/sail_latex_riscv/fnzsatp64mode_of_bits11c1e0e3eda64d7361d8ec4950c9f1ea.tex new file mode 100644 index 00000000..5cf02462 --- /dev/null +++ b/sail_latex_riscv/fnzsatp64mode_of_bits11c1e0e3eda64d7361d8ec4950c9f1ea.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzsatp64Modezyofzybits]{satp64Mode\_of\_bits}#(a : Architecture, m : satp_mode) -> #\hyperref[sailRISCVzoption]{option}#(SATPMode) = + match (a, m) { + (_, 0x0) => #\hyperref[sailRISCVzSome]{Some}#(Sbare), + (RV32, 0x1) => #\hyperref[sailRISCVzSome]{Some}#(Sv32), + (RV64, 0x8) => #\hyperref[sailRISCVzSome]{Some}#(Sv39), + (RV64, 0x9) => #\hyperref[sailRISCVzSome]{Some}#(Sv48), + (_, _) => #\hyperref[sailRISCVzNone]{None}#() + } diff --git a/sail_latex_riscv/fnzsatpmode_of_num09ad57622dbe0d0a7b111194f1a36856.tex b/sail_latex_riscv/fnzsatpmode_of_num09ad57622dbe0d0a7b111194f1a36856.tex new file mode 100644 index 00000000..91de9495 --- /dev/null +++ b/sail_latex_riscv/fnzsatpmode_of_num09ad57622dbe0d0a7b111194f1a36856.tex @@ -0,0 +1,6 @@ +function SATPMode_of_num arg# = match arg# { + 0 => Sbare, + 1 => Sv32, + 2 => Sv39, + _ => Sv48 +} diff --git a/sail_latex_riscv/fnzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex b/sail_latex_riscv/fnzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex new file mode 100644 index 00000000..cc898b3e --- /dev/null +++ b/sail_latex_riscv/fnzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzsealCap]{sealCap}#(cap, otyp) : (Capability, #\hyperref[sailRISCVzbits]{bits}#(cap_otype_width)) -> Capability = + {cap with otype=otyp} diff --git a/sail_latex_riscv/fnzselect_instr_or_fcsr_rm8a489b01095486a7dc41b6fb5b17b9a7.tex b/sail_latex_riscv/fnzselect_instr_or_fcsr_rm8a489b01095486a7dc41b6fb5b17b9a7.tex new file mode 100644 index 00000000..f4f97fe1 --- /dev/null +++ b/sail_latex_riscv/fnzselect_instr_or_fcsr_rm8a489b01095486a7dc41b6fb5b17b9a7.tex @@ -0,0 +1,4 @@ +function select_instr_or_fcsr_rm instr_rm = + if (instr_rm == RM_DYN) + then #\hyperref[sailRISCVzencdeczyroundingzymode]{encdec\_rounding\_mode}# (fcsr.#\hyperref[sailRISCVzFRM]{FRM}#()) + else instr_rm diff --git a/sail_latex_riscv/fnzset_mstatus_sxl3c993e2659d94bb903dbbc607aa47f8c.tex b/sail_latex_riscv/fnzset_mstatus_sxl3c993e2659d94bb903dbbc607aa47f8c.tex new file mode 100644 index 00000000..04af1356 --- /dev/null +++ b/sail_latex_riscv/fnzset_mstatus_sxl3c993e2659d94bb903dbbc607aa47f8c.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzsetzymstatuszySXL]{set\_mstatus\_SXL}#(m : Mstatus, a : arch_xlen) -> Mstatus = { + if sizeof(xlen) == 32 + then m + else { + let m = #\hyperref[sailRISCVzvectorzyupdatezysubrange]{vector\_update\_subrange}#(m.#\hyperref[sailRISCVzbits]{bits}#(), 35, 34, a); + #\hyperref[sailRISCVzMkzyMstatus]{Mk\_Mstatus}#(m) + } +} diff --git a/sail_latex_riscv/fnzset_mstatus_uxl030f4a70ceca0610271994fbfcb96d4d.tex b/sail_latex_riscv/fnzset_mstatus_uxl030f4a70ceca0610271994fbfcb96d4d.tex new file mode 100644 index 00000000..751f8b64 --- /dev/null +++ b/sail_latex_riscv/fnzset_mstatus_uxl030f4a70ceca0610271994fbfcb96d4d.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzsetzymstatuszyUXL]{set\_mstatus\_UXL}#(m : Mstatus, a : arch_xlen) -> Mstatus = { + if sizeof(xlen) == 32 + then m + else { + let m = #\hyperref[sailRISCVzvectorzyupdatezysubrange]{vector\_update\_subrange}#(m.#\hyperref[sailRISCVzbits]{bits}#(), 33, 32, a); + #\hyperref[sailRISCVzMkzyMstatus]{Mk\_Mstatus}#(m) + } +} diff --git a/sail_latex_riscv/fnzset_mtvec628ceb1975fa7b69631fcc224f1bbbc0.tex b/sail_latex_riscv/fnzset_mtvec628ceb1975fa7b69631fcc224f1bbbc0.tex new file mode 100644 index 00000000..4f8f82c9 --- /dev/null +++ b/sail_latex_riscv/fnzset_mtvec628ceb1975fa7b69631fcc224f1bbbc0.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzsetzymtvec]{set\_mtvec}#(value : xlenbits) -> xlenbits = { + let mtv = #\hyperref[sailRISCVzlegalizzezytvec]{legalize\_tvec}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(#\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(MTCC)), value); + MTCC = #\hyperref[sailRISCVzsetCapOffsetOrNull]{setCapOffsetOrNull}#(MTCC, mtv.#\hyperref[sailRISCVzbits]{bits}#()); + mtv.#\hyperref[sailRISCVzbits]{bits}#() +} diff --git a/sail_latex_riscv/fnzset_next_pc4a8ca0d1733a6630871f9f58d4ea2e08.tex b/sail_latex_riscv/fnzset_next_pc4a8ca0d1733a6630871f9f58d4ea2e08.tex new file mode 100644 index 00000000..4b05a363 --- /dev/null +++ b/sail_latex_riscv/fnzset_next_pc4a8ca0d1733a6630871f9f58d4ea2e08.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzsetzynextzypc]{set\_next\_pc}#(pc) = + /* could check for internal errors here on invalid pc */ + nextPC = pc diff --git a/sail_latex_riscv/fnzset_sstatus_uxl4d602a7109609248f9b54c8c905b4ad0.tex b/sail_latex_riscv/fnzset_sstatus_uxl4d602a7109609248f9b54c8c905b4ad0.tex new file mode 100644 index 00000000..6a4c3932 --- /dev/null +++ b/sail_latex_riscv/fnzset_sstatus_uxl4d602a7109609248f9b54c8c905b4ad0.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzsetzysstatuszyUXL]{set\_sstatus\_UXL}#(s : Sstatus, a : arch_xlen) -> Sstatus = { + let m = #\hyperref[sailRISCVzMkzyMstatus]{Mk\_Mstatus}#(s.#\hyperref[sailRISCVzbits]{bits}#()); + let m = #\hyperref[sailRISCVzsetzymstatuszyUXL]{set\_mstatus\_UXL}#(m, a); + #\hyperref[sailRISCVzMkzySstatus]{Mk\_Sstatus}#(m.#\hyperref[sailRISCVzbits]{bits}#()) +} diff --git a/sail_latex_riscv/fnzset_stvec0d8dcc20a4d9dd912d52b9252d2370a7.tex b/sail_latex_riscv/fnzset_stvec0d8dcc20a4d9dd912d52b9252d2370a7.tex new file mode 100644 index 00000000..30e56c74 --- /dev/null +++ b/sail_latex_riscv/fnzset_stvec0d8dcc20a4d9dd912d52b9252d2370a7.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzsetzystvec]{set\_stvec}#(value : xlenbits) -> xlenbits = { + let stv = #\hyperref[sailRISCVzlegalizzezytvec]{legalize\_tvec}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(#\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(STCC)), value); + STCC = #\hyperref[sailRISCVzsetCapOffsetOrNull]{setCapOffsetOrNull}#(STCC, stv.#\hyperref[sailRISCVzbits]{bits}#()); + stv.#\hyperref[sailRISCVzbits]{bits}#() +} diff --git a/sail_latex_riscv/fnzset_utvec4e028b19c2b4db0c1c1a0a48f1c4a330.tex b/sail_latex_riscv/fnzset_utvec4e028b19c2b4db0c1c1a0a48f1c4a330.tex new file mode 100644 index 00000000..dca6b104 --- /dev/null +++ b/sail_latex_riscv/fnzset_utvec4e028b19c2b4db0c1c1a0a48f1c4a330.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzsetzyutvec]{set\_utvec}#(value : xlenbits) -> xlenbits = { + let utv = #\hyperref[sailRISCVzlegalizzezytvec]{legalize\_tvec}#(#\hyperref[sailRISCVzMkzyMtvec]{Mk\_Mtvec}#(#\hyperref[sailRISCVzgetCapOffsetBits]{getCapOffsetBits}#(UTCC)), value); + UTCC = #\hyperref[sailRISCVzsetCapOffsetOrNull]{setCapOffsetOrNull}#(UTCC, utv.#\hyperref[sailRISCVzbits]{bits}#()); + utv.#\hyperref[sailRISCVzbits]{bits}#() +} diff --git a/sail_latex_riscv/fnzset_xret_target81095db6e6bb6da6b746ed406dccd45e.tex b/sail_latex_riscv/fnzset_xret_target81095db6e6bb6da6b746ed406dccd45e.tex new file mode 100644 index 00000000..8ca217ef --- /dev/null +++ b/sail_latex_riscv/fnzset_xret_target81095db6e6bb6da6b746ed406dccd45e.tex @@ -0,0 +1,8 @@ +function #\hyperref[sailRISCVzsetzyxretzytarget]{set\_xret\_target}#(p, value) = { + match p { + Machine => MEPCC = #\hyperref[sailRISCVzsetCapOffsetOrNull]{setCapOffsetOrNull}#(MEPCC, value), + Supervisor => SEPCC = #\hyperref[sailRISCVzsetCapOffsetOrNull]{setCapOffsetOrNull}#(SEPCC, value), + User => UEPCC = #\hyperref[sailRISCVzsetCapOffsetOrNull]{setCapOffsetOrNull}#(UEPCC, value) + }; + value +} diff --git a/sail_latex_riscv/fnzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex b/sail_latex_riscv/fnzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex new file mode 100644 index 00000000..b2512846 --- /dev/null +++ b/sail_latex_riscv/fnzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVzsetCapAddr]{setCapAddr}#(c, addr) = + let newCap = { c with address = addr } in + let representable = #\hyperref[sailRISCVzcapBoundsEqual]{capBoundsEqual}#(c, newCap) in + (representable, newCap) diff --git a/sail_latex_riscv/fnzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex b/sail_latex_riscv/fnzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex new file mode 100644 index 00000000..bc87f6c0 --- /dev/null +++ b/sail_latex_riscv/fnzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex @@ -0,0 +1,63 @@ +function #\hyperref[sailRISCVzsetCapBounds]{setCapBounds}#(cap, base, top) : (Capability, CapAddrBits, CapLenBits) -> (bool, Capability) = { + /* {cap with base=base; length=(#\hyperref[sailRISCVzbits]{bits}#(64)) length; offset=0} */ + let ext_base = 0b0 @ base; + let length = top - ext_base; + /* Find an exponent that will put the most significant bit of length + * second from the top as assumed during decoding. We ignore the bottom + * MW bits because those are handled by the ie = 0 format. + */ + let e = maxE - #\hyperref[sailRISCVzcountzyleadingzyzzeros]{count\_leading\_zeros}#(length[cap_addr_width..cap_mantissa_width - 1]); + // Use use internal exponent if e is non-zero or if e is zero but + // but the implied bit of length is not #\hyperref[sailRISCVzzzero]{zero}# (denormal vs. normal case) + let ie = (e != 0) | length[cap_mantissa_width - 2] == bitone; + + /* The non-ie e == 0 case is easy. It is exact so just extract relevant bits. */ + Bbits = #\hyperref[sailRISCVztruncate]{truncate}#(base, cap_mantissa_width); + Tbits = #\hyperref[sailRISCVztruncate]{truncate}#(top, cap_mantissa_width); + lostSignificantTop : bool = false; + lostSignificantBase : bool = false; + incE : bool = false; + + if ie then { + /* the internal exponent case is trickier */ + + /* Extract B and T #\hyperref[sailRISCVzbits]{bits}# (we lose 3 bits of each to store the exponent) */ + B_ie = #\hyperref[sailRISCVztruncate]{truncate}#(base >> (e + 3), cap_mantissa_width - 3); + T_ie = #\hyperref[sailRISCVztruncate]{truncate}#(top >> (e + 3), cap_mantissa_width - 3); + + /* Find out whether we have lost significant bits of base and top using a + * mask of bits that we will #\hyperref[sailRISCVzlose]{lose}# (including 3 extra for exp). + */ + maskLo : CapLenBits = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzones]{ones}#(e+3)); + lostSignificantBase = #\hyperref[sailRISCVzunsigned]{unsigned}#(ext_base & maskLo) != 0; + lostSignificantTop = #\hyperref[sailRISCVzunsigned]{unsigned}#(top & maskLo) != 0; + + if lostSignificantTop then { + /* we must increment T to make sure it is still above top even with lost bits. + It might wrap around but if that makes B> (e + 4), cap_mantissa_width - 3); + let incT : range(0,1) = if lostSignificantTop then 1 else 0; + T_ie = #\hyperref[sailRISCVztruncate]{truncate}#(top >> (e + 4), cap_mantissa_width - 3) + incT; + }; + + Bbits = B_ie @ 0b000; + Tbits = T_ie @ 0b000; + }; + let newCap = {cap with address=base, E=#\hyperref[sailRISCVztozybits]{to\_bits}#(6, if incE then e + 1 else e), B=Bbits, T=Tbits, internal_e=ie}; + let exact = #\hyperref[sailRISCVznot]{not}#(lostSignificantBase | lostSignificantTop); + (exact, newCap) +} diff --git a/sail_latex_riscv/fnzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex b/sail_latex_riscv/fnzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex new file mode 100644 index 00000000..92909055 --- /dev/null +++ b/sail_latex_riscv/fnzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzsetCapFlags]{setCapFlags}#(cap, flags) = {cap with flag_cap_mode = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(flags[0])} diff --git a/sail_latex_riscv/fnzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex b/sail_latex_riscv/fnzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex new file mode 100644 index 00000000..3f21bd41 --- /dev/null +++ b/sail_latex_riscv/fnzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzsetCapOffset]{setCapOffset}#(c, offset) : (Capability, CapAddrBits) -> (bool, Capability) = + let base = #\hyperref[sailRISCVzgetCapBaseBits]{getCapBaseBits}#(c) in + let newAddress = base + offset in + let newCap = { c with address = newAddress } in + /* let representable = #\hyperref[sailRISCVzcapBoundsEqual]{capBoundsEqual}#(c, newCap) in */ + let representable = #\hyperref[sailRISCVzfastRepCheck]{fastRepCheck}#(c, (newAddress - c.address)) in + (representable, newCap) diff --git a/sail_latex_riscv/fnzsetcapoffsetornullc7b6ed6c2844187ec5b671dc1ca3eae0.tex b/sail_latex_riscv/fnzsetcapoffsetornullc7b6ed6c2844187ec5b671dc1ca3eae0.tex new file mode 100644 index 00000000..abdc0963 --- /dev/null +++ b/sail_latex_riscv/fnzsetcapoffsetornullc7b6ed6c2844187ec5b671dc1ca3eae0.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzsetCapOffsetOrNull]{setCapOffsetOrNull}# (cap, offset) : (Capability, CapAddrBits) -> Capability = + let (representable, newCap) = #\hyperref[sailRISCVzsetCapOffset]{setCapOffset}#(cap, offset) in + if representable & #\hyperref[sailRISCVznot]{not}#(#\hyperref[sailRISCVzisCapSealed]{isCapSealed}#(cap)) then newCap else #\hyperref[sailRISCVzinvalidateCap]{invalidateCap}#(newCap) diff --git a/sail_latex_riscv/fnzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex b/sail_latex_riscv/fnzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex new file mode 100644 index 00000000..ea497370 --- /dev/null +++ b/sail_latex_riscv/fnzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex @@ -0,0 +1,17 @@ +function #\hyperref[sailRISCVzsetCapPerms]{setCapPerms}#(cap, perms) : (Capability, CapPermsBits) -> Capability = + { cap with + uperms = #\hyperref[sailRISCVztruncate]{truncate}#(perms >> cap_uperms_shift, cap_uperms_width), + /* 14..12 reserved -- ignore */ + permit_set_CID = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(perms[11]), + access_system_regs = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(perms[10]), + permit_unseal = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(perms[9]), + permit_cinvoke = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(perms[8]), + permit_seal = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(perms[7]), + permit_store_local_cap = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(perms[6]), + permit_store_cap = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(perms[5]), + permit_load_cap = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(perms[4]), + permit_store = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(perms[3]), + permit_load = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(perms[2]), + permit_execute = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(perms[1]), + global = #\hyperref[sailRISCVzbitzytozybool]{bit\_to\_bool}#(perms[0]) + } diff --git a/sail_latex_riscv/fnzshift_right_arith32247e0e7505241d38fca8e6a3bcdfea9e.tex b/sail_latex_riscv/fnzshift_right_arith32247e0e7505241d38fca8e6a3bcdfea9e.tex new file mode 100644 index 00000000..bd68f62b --- /dev/null +++ b/sail_latex_riscv/fnzshift_right_arith32247e0e7505241d38fca8e6a3bcdfea9e.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzshiftzyrightzyarith32]{shift\_right\_arith32}# (v : #\hyperref[sailRISCVzbits]{bits}#(32), shift : #\hyperref[sailRISCVzbits]{bits}#(5)) -> #\hyperref[sailRISCVzbits]{bits}#(32) = + let v64 : #\hyperref[sailRISCVzbits]{bits}#(64) = #\hyperref[sailRISCVzEXTS]{EXTS}#(v) in + (v64 >> shift)[31..0] diff --git a/sail_latex_riscv/fnzshift_right_arith642d6a56971daae2b1fdb862ebbbaf6a46.tex b/sail_latex_riscv/fnzshift_right_arith642d6a56971daae2b1fdb862ebbbaf6a46.tex new file mode 100644 index 00000000..25cbcbef --- /dev/null +++ b/sail_latex_riscv/fnzshift_right_arith642d6a56971daae2b1fdb862ebbbaf6a46.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzshiftzyrightzyarith64]{shift\_right\_arith64}# (v : #\hyperref[sailRISCVzbits]{bits}#(64), shift : #\hyperref[sailRISCVzbits]{bits}#(6)) -> #\hyperref[sailRISCVzbits]{bits}#(64) = + let v128 : #\hyperref[sailRISCVzbits]{bits}#(128) = #\hyperref[sailRISCVzEXTS]{EXTS}#(v) in + (v128 >> shift)[63..0] diff --git a/sail_latex_riscv/fnzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex b/sail_latex_riscv/fnzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex new file mode 100644 index 00000000..ab916275 --- /dev/null +++ b/sail_latex_riscv/fnzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVzslicezymask]{slice\_mask}#(n,i,l) = + if l >= n then { + #\hyperref[sailRISCVzsailzyshiftleft]{sail\_shiftleft}#(#\hyperref[sailRISCVzsailzyones]{sail\_ones}#(n), i) + } else { + let one : #\hyperref[sailRISCVzbits]{bits}#('n) = #\hyperref[sailRISCVzsailzymask]{sail\_mask}#(n, [bitone] : #\hyperref[sailRISCVzbits]{bits}#(1)) in + #\hyperref[sailRISCVzsailzyshiftleft]{sail\_shiftleft}#(#\hyperref[sailRISCVzsubzybits]{sub\_bits}#(#\hyperref[sailRISCVzsailzyshiftleft]{sail\_shiftleft}#(one, l), one), i) + } diff --git a/sail_latex_riscv/fnzsop_of_num788240d3b5d5ef8334c5920b24c291e9.tex b/sail_latex_riscv/fnzsop_of_num788240d3b5d5ef8334c5920b24c291e9.tex new file mode 100644 index 00000000..1cb2f9eb --- /dev/null +++ b/sail_latex_riscv/fnzsop_of_num788240d3b5d5ef8334c5920b24c291e9.tex @@ -0,0 +1,5 @@ +function sop_of_num arg# = match arg# { + 0 => RISCV_SLLI, + 1 => RISCV_SRLI, + _ => RISCV_SRAI +} diff --git a/sail_latex_riscv/fnzsopw_of_num696c7b3c0b6fb9b9c9d699cd0a410ea3.tex b/sail_latex_riscv/fnzsopw_of_num696c7b3c0b6fb9b9c9d699cd0a410ea3.tex new file mode 100644 index 00000000..b8d8c5ff --- /dev/null +++ b/sail_latex_riscv/fnzsopw_of_num696c7b3c0b6fb9b9c9d699cd0a410ea3.tex @@ -0,0 +1,5 @@ +function sopw_of_num arg# = match arg# { + 0 => RISCV_SLLIW, + 1 => RISCV_SRLIW, + _ => RISCV_SRAIW +} diff --git a/sail_latex_riscv/fnzspc_backwardsa712e20ab4070963924d2974cc8aa941.tex b/sail_latex_riscv/fnzspc_backwardsa712e20ab4070963924d2974cc8aa941.tex new file mode 100644 index 00000000..789a4ece --- /dev/null +++ b/sail_latex_riscv/fnzspc_backwardsa712e20ab4070963924d2974cc8aa941.tex @@ -0,0 +1 @@ +function spc_backwards s = () diff --git a/sail_latex_riscv/fnzspc_forwardsabfa1efbce2d58c6d3e26c86435d3af4.tex b/sail_latex_riscv/fnzspc_forwardsabfa1efbce2d58c6d3e26c86435d3af4.tex new file mode 100644 index 00000000..c03bfe01 --- /dev/null +++ b/sail_latex_riscv/fnzspc_forwardsabfa1efbce2d58c6d3e26c86435d3af4.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzspczyforwards]{spc\_forwards}# () = " " diff --git a/sail_latex_riscv/fnzspc_matches_prefix38c7965c7edeefb5fb2ccd6915f5bdbb.tex b/sail_latex_riscv/fnzspc_matches_prefix38c7965c7edeefb5fb2ccd6915f5bdbb.tex new file mode 100644 index 00000000..97f9c322 --- /dev/null +++ b/sail_latex_riscv/fnzspc_matches_prefix38c7965c7edeefb5fb2ccd6915f5bdbb.tex @@ -0,0 +1,7 @@ +function spc_matches_prefix s = { + let n = #\hyperref[sailRISCVznzyleadingzyspaces]{n\_leading\_spaces}#(s); + match n { + 0 => #\hyperref[sailRISCVzNone]{None}#(), + _ => #\hyperref[sailRISCVzSome]{Some}#((), n) + } +} diff --git a/sail_latex_riscv/fnzstepb001f84c8bf78b78b44b98d2b7f1f7d7.tex b/sail_latex_riscv/fnzstepb001f84c8bf78b78b44b98d2b7f1f7d7.tex new file mode 100644 index 00000000..377c4616 --- /dev/null +++ b/sail_latex_riscv/fnzstepb001f84c8bf78b78b44b98d2b7f1f7d7.tex @@ -0,0 +1,69 @@ +function #\hyperref[sailRISCVzstep]{step}#(step_no : int) -> bool = { + /* for step extensions */ + #\hyperref[sailRISCVzextzyprezystepzyhook]{ext\_pre\_step\_hook}#(); + + minstret_written = false; /* see note for minstret */ + let (retired, stepped) : (Retired, bool) = + match #\hyperref[sailRISCVzdispatchInterrupt]{dispatchInterrupt}#(cur_privilege) { + #\hyperref[sailRISCVzSome]{Some}#(intr, priv) => { + if #\hyperref[sailRISCVzgetzyconfigzyprintzyinstr]{get\_config\_print\_instr}#() + then #\hyperref[sailRISCVzprintzybits]{print\_bits}#("Handling interrupt: ", #\hyperref[sailRISCVzinterruptTypezytozybits]{interruptType\_to\_bits}#(intr)); + #\hyperref[sailRISCVzhandlezyinterrupt]{handle\_interrupt}#(intr, priv); + (RETIRE_FAIL, false) + }, + #\hyperref[sailRISCVzNone]{None}#() => { + /* the extension hook interposes on the fetch result */ + let f : FetchResult = #\hyperref[sailRISCVzextzyfetchzyhook]{ext\_fetch\_hook}#(#\hyperref[sailRISCVzfetch]{fetch}#()); + match f { + /* extension error */ + #\hyperref[sailRISCVzFzyExtzyError]{F\_Ext\_Error}#(e) => { + #\hyperref[sailRISCVzextzyhandlezyfetchzycheckzyerror]{ext\_handle\_fetch\_check\_error}#(e); + (RETIRE_FAIL, false) + }, + /* standard error */ + #\hyperref[sailRISCVzFzyError]{F\_Error}#(e, addr) => { + #\hyperref[sailRISCVzhandlezymemzyexception]{handle\_mem\_exception}#(addr, e); + (RETIRE_FAIL, false) + }, + /* non-error cases: */ + #\hyperref[sailRISCVzFzyRVC]{F\_RVC}#(h) => { + let ast = #\hyperref[sailRISCVzdecodeCompressed]{decodeCompressed}#(h); + if #\hyperref[sailRISCVzgetzyconfigzyprintzyinstr]{get\_config\_print\_instr}#() + then { + #\hyperref[sailRISCVzprintzyinstr]{print\_instr}#("[" ^ #\hyperref[sailRISCVzstringzyofzyint]{string\_of\_int}#(step_no) ^ "] [" ^ #\hyperref[sailRISCVztozystr]{to\_str}#(cur_privilege) ^ "]: " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(PC) ^ " (" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(h) ^ ") " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(ast)); + }; + /* check for RVC once here instead of every RVC execute clause. */ + if #\hyperref[sailRISCVzhaveRVC]{haveRVC}#() then { + nextPC = PC + 2; + (#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzextzypostzydecodezyhook]{ext\_post\_decode\_hook}#(ast)), true) + } else { + #\hyperref[sailRISCVzhandlezyillegal]{handle\_illegal}#(); + (RETIRE_FAIL, true) + } + }, + #\hyperref[sailRISCVzFzyBase]{F\_Base}#(w) => { + let ast = #\hyperref[sailRISCVzdecode]{decode}#(w); + if #\hyperref[sailRISCVzgetzyconfigzyprintzyinstr]{get\_config\_print\_instr}#() + then { + #\hyperref[sailRISCVzprintzyinstr]{print\_instr}#("[" ^ #\hyperref[sailRISCVzstringzyofzyint]{string\_of\_int}#(step_no) ^ "] [" ^ #\hyperref[sailRISCVztozystr]{to\_str}#(cur_privilege) ^ "]: " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(PC) ^ " (" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(w) ^ ") " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(ast)); + }; + nextPC = PC + 4; + (#\hyperref[sailRISCVzexecute]{execute}#(#\hyperref[sailRISCVzextzypostzydecodezyhook]{ext\_post\_decode\_hook}#(ast)), true) + } + } + } + }; + + #\hyperref[sailRISCVztickzypc]{tick\_pc}#(); + + /* update minstret */ + match retired { + RETIRE_SUCCESS => #\hyperref[sailRISCVzretirezyinstruction]{retire\_instruction}#(), + RETIRE_FAIL => () + }; + + /* for step extensions */ + #\hyperref[sailRISCVzextzypostzystepzyhook]{ext\_post\_step\_hook}#(); + + stepped +} diff --git a/sail_latex_riscv/fnzstring_of_bit7313cdbf7b05129d4977581f9bb14794.tex b/sail_latex_riscv/fnzstring_of_bit7313cdbf7b05129d4977581f9bb14794.tex new file mode 100644 index 00000000..dec12fe9 --- /dev/null +++ b/sail_latex_riscv/fnzstring_of_bit7313cdbf7b05129d4977581f9bb14794.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzstringzyofzybit]{string\_of\_bit}#(b: bit) -> string = + match b { + bitzero => "0b0", + bitone => "0b1" + } diff --git a/sail_latex_riscv/fnzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex b/sail_latex_riscv/fnzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex new file mode 100644 index 00000000..8df99489 --- /dev/null +++ b/sail_latex_riscv/fnzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex @@ -0,0 +1,27 @@ +function #\hyperref[sailRISCVzstringzyofzycapex]{string\_of\_capex}# (ex) : CapEx -> string = + match ex { + CapEx_None => "None" , + CapEx_LengthViolation => "LengthViolation" , + CapEx_TagViolation => "TagViolation" , + CapEx_SealViolation => "SealViolation" , + CapEx_TypeViolation => "TypeViolation" , + CapEx_CallTrap => "CallTrap" , + CapEx_ReturnTrap => "ReturnTrap" , + CapEx_TSSUnderFlow => "TSSUnderFlow" , + CapEx_UserDefViolation => "UserDefViolation" , + CapEx_InexactBounds => "InexactBounds" , + CapEx_UnalignedBase => "UnalignedBounds" , + CapEx_GlobalViolation => "GlobalViolation" , + CapEx_PermitExecuteViolation => "PermitExecuteViolation" , + CapEx_PermitLoadViolation => "PermitLoadViolation" , + CapEx_PermitStoreViolation => "PermitStoreViolation" , + CapEx_PermitLoadCapViolation => "PermitLoadCapViolation" , + CapEx_PermitStoreCapViolation => "PermitStoreCapViolation" , + CapEx_PermitStoreLocalCapViolation => "PermitStoreLocalCapViolation", + CapEx_PermitSealViolation => "PermitSealViolation" , + CapEx_AccessSystemRegsViolation => "AccessSystemRegsViolation" , + CapEx_PermitCInvokeViolation => "PermitCInvokeViolation" , + CapEx_AccessCInvokeIDCViolation => "AccessCInvokeIDCViolation" , + CapEx_PermitUnsealViolation => "PermitUnsealViolation" , + CapEx_PermitSetCIDViolation => "PermitSetCIDViolation" + } diff --git a/sail_latex_riscv/fnztag_addr_to_addrec4cd9758dc545430904849bc06af049.tex b/sail_latex_riscv/fnztag_addr_to_addrec4cd9758dc545430904849bc06af049.tex new file mode 100644 index 00000000..a1438bdb --- /dev/null +++ b/sail_latex_riscv/fnztag_addr_to_addrec4cd9758dc545430904849bc06af049.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVztagzyaddrzytozyaddr]{tag\_addr\_to\_addr}#(tag_addr : tagaddrbits) -> xlenbits = tag_addr @ #\hyperref[sailRISCVzzzeros]{zeros}#(log2_cap_size) diff --git a/sail_latex_riscv/fnztick_clocka855f1c53aa2515a7a67cd69b5b3d663.tex b/sail_latex_riscv/fnztick_clocka855f1c53aa2515a7a67cd69b5b3d663.tex new file mode 100644 index 00000000..d06595ef --- /dev/null +++ b/sail_latex_riscv/fnztick_clocka855f1c53aa2515a7a67cd69b5b3d663.tex @@ -0,0 +1,7 @@ +function #\hyperref[sailRISCVztickzyclock]{tick\_clock}#() = { + if mcountinhibit.#\hyperref[sailRISCVzCY]{CY}#() == 0b0 + then mcycle = mcycle + 1; + + mtime = mtime + 1; + #\hyperref[sailRISCVzclintzydispatch]{clint\_dispatch}#() +} diff --git a/sail_latex_riscv/fnztick_pc459868e2ecb79c51cd3817471ae33696.tex b/sail_latex_riscv/fnztick_pc459868e2ecb79c51cd3817471ae33696.tex new file mode 100644 index 00000000..3cf4987d --- /dev/null +++ b/sail_latex_riscv/fnztick_pc459868e2ecb79c51cd3817471ae33696.tex @@ -0,0 +1,4 @@ +function #\hyperref[sailRISCVztickzypc]{tick\_pc}#() = { + PCC = nextPCC; + PC = nextPC +} diff --git a/sail_latex_riscv/fnztick_platformc49251d76e66d78fce3dd1f18a27869c.tex b/sail_latex_riscv/fnztick_platformc49251d76e66d78fce3dd1f18a27869c.tex new file mode 100644 index 00000000..9f6cef25 --- /dev/null +++ b/sail_latex_riscv/fnztick_platformc49251d76e66d78fce3dd1f18a27869c.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVztickzyplatform]{tick\_platform}#() -> unit = { + #\hyperref[sailRISCVzhtifzytick]{htif\_tick}#(); +} diff --git a/sail_latex_riscv/fnzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex b/sail_latex_riscv/fnzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex new file mode 100644 index 00000000..7b9c5a3e --- /dev/null +++ b/sail_latex_riscv/fnzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVztozybits]{to\_bits}# (l, n) = #\hyperref[sailRISCVzgetzyslicezyint]{get\_slice\_int}#(l, n, 0) diff --git a/sail_latex_riscv/fnztrans_kind_of_num89fdff5348b6925bdad7af7bbcc092d6.tex b/sail_latex_riscv/fnztrans_kind_of_num89fdff5348b6925bdad7af7bbcc092d6.tex new file mode 100644 index 00000000..97d89661 --- /dev/null +++ b/sail_latex_riscv/fnztrans_kind_of_num89fdff5348b6925bdad7af7bbcc092d6.tex @@ -0,0 +1,5 @@ +function trans_kind_of_num arg# = match arg# { + 0 => Transaction_start, + 1 => Transaction_commit, + _ => Transaction_abort +} diff --git a/sail_latex_riscv/fnztranslate39daa42428c4ec23bd5def028158b476c6.tex b/sail_latex_riscv/fnztranslate39daa42428c4ec23bd5def028158b476c6.tex new file mode 100644 index 00000000..66f815bb --- /dev/null +++ b/sail_latex_riscv/fnztranslate39daa42428c4ec23bd5def028158b476c6.tex @@ -0,0 +1,70 @@ +function #\hyperref[sailRISCVztranslate39]{translate39}#(asid, ptb, vAddr, ac, priv, mxr, do_sum, level, ext_ptw) = { + match #\hyperref[sailRISCVzlookupzyTLB39]{lookup\_TLB39}#(asid, vAddr) { + #\hyperref[sailRISCVzSome]{Some}#(idx, ent) => { +/* #\hyperref[sailRISCVzprint]{print}#("translate39: TLB39 hit for " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(vAddr)); */ + let pte = #\hyperref[sailRISCVzMkzySV39zyPTE]{Mk\_SV39\_PTE}#(ent.pte); + let ext_pte = pte.#\hyperref[sailRISCVzExt]{Ext}#(); + let pteBits = #\hyperref[sailRISCVzMkzyPTEzyBits]{Mk\_PTE\_Bits}#(pte.#\hyperref[sailRISCVzBITS]{BITS}#()); + match #\hyperref[sailRISCVzcheckPTEPermission]{checkPTEPermission}#(ac, priv, mxr, do_sum, pteBits, ext_pte, ext_ptw) { + #\hyperref[sailRISCVzPTEzyCheckzyFailure]{PTE\_Check\_Failure}#(ext_ptw, ext_ptw_fail) => { #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVzextzygetzyptwzyerror]{ext\_get\_ptw\_error}#(ext_ptw_fail), ext_ptw) }, + #\hyperref[sailRISCVzPTEzyCheckzySuccess]{PTE\_Check\_Success}#(ext_ptw) => { + match #\hyperref[sailRISCVzupdatezyPTEzyBits]{update\_PTE\_Bits}#(pteBits, ac, ext_pte) { + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(ent.pAddr | #\hyperref[sailRISCVzEXTZ]{EXTZ}#(vAddr & ent.vAddrMask), ext_ptw), + #\hyperref[sailRISCVzSome]{Some}#(pbits, ext) => { + if ~ (#\hyperref[sailRISCVzplatzyenablezydirtyzyupdate]{plat\_enable\_dirty\_update}# ()) + then { + /* pte needs dirty/accessed update but that is not enabled */ + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVzPTWzyPTEzyUpdate]{PTW\_PTE\_Update}#(), ext_ptw) + } else { + /* update PTE entry and TLB */ + n_pte = #\hyperref[sailRISCVzupdatezyBITS]{update\_BITS}#(pte, pbits.#\hyperref[sailRISCVzbits]{bits}#()); + n_pte = #\hyperref[sailRISCVzupdatezyExt]{update\_Ext}#(n_pte, ext); + n_ent : TLB39_Entry = ent; + n_ent.pte = n_pte.#\hyperref[sailRISCVzbits]{bits}#(); + #\hyperref[sailRISCVzwritezyTLB39]{write\_TLB39}#(idx, n_ent); + /* update page table */ + match #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(ent.pteAddr), 8, n_pte.#\hyperref[sailRISCVzbits]{bits}#(), false, false, false) { + #\hyperref[sailRISCVzMemValue]{MemValue}#(_) => (), + #\hyperref[sailRISCVzMemException]{MemException}#(e) => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("invalid physical address in TLB") + }; + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(ent.pAddr | #\hyperref[sailRISCVzEXTZ]{EXTZ}#(vAddr & ent.vAddrMask), ext_ptw) + } + } + } + } + } + }, + #\hyperref[sailRISCVzNone]{None}#() => { + match #\hyperref[sailRISCVzwalk39]{walk39}#(vAddr, ac, priv, mxr, do_sum, ptb, level, false, ext_ptw) { + #\hyperref[sailRISCVzPTWzyFailure]{PTW\_Failure}#(f, ext_ptw) => #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(f, ext_ptw), + #\hyperref[sailRISCVzPTWzySuccess]{PTW\_Success}#(pAddr, pte, pteAddr, level, global, ext_ptw) => { + match #\hyperref[sailRISCVzupdatezyPTEzyBits]{update\_PTE\_Bits}#(#\hyperref[sailRISCVzMkzyPTEzyBits]{Mk\_PTE\_Bits}#(pte.#\hyperref[sailRISCVzBITS]{BITS}#()), ac, pte.#\hyperref[sailRISCVzExt]{Ext}#()) { + #\hyperref[sailRISCVzNone]{None}#() => { + #\hyperref[sailRISCVzaddzytozyTLB39]{add\_to\_TLB39}#(asid, vAddr, pAddr, pte, pteAddr, level, global); + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(pAddr, ext_ptw) + }, + #\hyperref[sailRISCVzSome]{Some}#(pbits, ext) => + if ~ (#\hyperref[sailRISCVzplatzyenablezydirtyzyupdate]{plat\_enable\_dirty\_update}# ()) + then { + /* pte needs dirty/accessed update but that is not enabled */ + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVzPTWzyPTEzyUpdate]{PTW\_PTE\_Update}#(), ext_ptw) + } else { + w_pte : SV39_PTE = #\hyperref[sailRISCVzupdatezyBITS]{update\_BITS}#(pte, pbits.#\hyperref[sailRISCVzbits]{bits}#()); + w_pte : SV39_PTE = #\hyperref[sailRISCVzupdatezyExt]{update\_Ext}#(w_pte, ext); + match #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(pteAddr), 8, w_pte.#\hyperref[sailRISCVzbits]{bits}#(), false, false, false) { + #\hyperref[sailRISCVzMemValue]{MemValue}#(_) => { + #\hyperref[sailRISCVzaddzytozyTLB39]{add\_to\_TLB39}#(asid, vAddr, pAddr, w_pte, pteAddr, level, global); + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(pAddr, ext_ptw) + }, + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { + /* pte is not in valid memory */ + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVzPTWzyAccess]{PTW\_Access}#(), ext_ptw) + } + } + } + } + } + } + } + } +} diff --git a/sail_latex_riscv/fnztranslate488637bc30f662c37b22a80c3d053c14e5.tex b/sail_latex_riscv/fnztranslate488637bc30f662c37b22a80c3d053c14e5.tex new file mode 100644 index 00000000..bd127023 --- /dev/null +++ b/sail_latex_riscv/fnztranslate488637bc30f662c37b22a80c3d053c14e5.tex @@ -0,0 +1,32 @@ +function #\hyperref[sailRISCVztranslate48]{translate48}#(asid, ptb, vAddr, ac, priv, mxr, do_sum, level, ext_ptw) = { + match #\hyperref[sailRISCVzwalk48]{walk48}#(vAddr, ac, priv, mxr, do_sum, ptb, level, false, ext_ptw) { + #\hyperref[sailRISCVzPTWzyFailure]{PTW\_Failure}#(f, ext_ptw) => #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(f, ext_ptw), + #\hyperref[sailRISCVzPTWzySuccess]{PTW\_Success}#(pAddr, pte, pteAddr, level, global, ext_ptw) => { + match #\hyperref[sailRISCVzupdatezyPTEzyBits]{update\_PTE\_Bits}#(#\hyperref[sailRISCVzMkzyPTEzyBits]{Mk\_PTE\_Bits}#(pte.#\hyperref[sailRISCVzBITS]{BITS}#()), ac, pte.#\hyperref[sailRISCVzExt]{Ext}#()) { + #\hyperref[sailRISCVzNone]{None}#() => { + #\hyperref[sailRISCVzaddzytozyTLB48]{add\_to\_TLB48}#(asid, vAddr, pAddr, pte, pteAddr, level, global); + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(pAddr, ext_ptw) + }, + #\hyperref[sailRISCVzSome]{Some}#(pbits, ext) => + if ~ (#\hyperref[sailRISCVzplatzyenablezydirtyzyupdate]{plat\_enable\_dirty\_update}# ()) + then { + /* pte needs dirty/accessed update but that is not enabled */ + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVzPTWzyPTEzyUpdate]{PTW\_PTE\_Update}#(), ext_ptw) + } else { + w_pte : SV48_PTE = #\hyperref[sailRISCVzupdatezyBITS]{update\_BITS}#(pte, pbits.#\hyperref[sailRISCVzbits]{bits}#()); + w_pte : SV48_PTE = #\hyperref[sailRISCVzupdatezyExt]{update\_Ext}#(w_pte, ext); + match #\hyperref[sailRISCVzmemzywritezyvalue]{mem\_write\_value}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(pteAddr), 8, w_pte.#\hyperref[sailRISCVzbits]{bits}#(), false, false, false) { + #\hyperref[sailRISCVzMemValue]{MemValue}#(_) => { + #\hyperref[sailRISCVzaddzytozyTLB48]{add\_to\_TLB48}#(asid, vAddr, pAddr, w_pte, pteAddr, level, global); + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(pAddr, ext_ptw) + }, + #\hyperref[sailRISCVzMemException]{MemException}#(e) => { + /* pte is not in valid memory */ + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVzPTWzyAccess]{PTW\_Access}#(), ext_ptw) + } + } + } + } + } + } +} diff --git a/sail_latex_riscv/fnztranslateaddr7dc6bd4ea43d006224000f7b68f6a187.tex b/sail_latex_riscv/fnztranslateaddr7dc6bd4ea43d006224000f7b68f6a187.tex new file mode 100644 index 00000000..005e4b62 --- /dev/null +++ b/sail_latex_riscv/fnztranslateaddr7dc6bd4ea43d006224000f7b68f6a187.tex @@ -0,0 +1,31 @@ +function #\hyperref[sailRISCVztranslateAddr]{translateAddr}#(vAddr, ac) = { + let effPriv : Privilege = #\hyperref[sailRISCVzeffectivePrivilege]{effectivePrivilege}#(ac, mstatus, cur_privilege); + let mxr : bool = mstatus.#\hyperref[sailRISCVzMXR]{MXR}#() == 0b1; + let do_sum : bool = mstatus.#\hyperref[sailRISCVzSUM]{SUM}#() == 0b1; + let mode : SATPMode = #\hyperref[sailRISCVztranslationMode]{translationMode}#(effPriv); + + let asid = #\hyperref[sailRISCVzcurAsid64]{curAsid64}#(satp); + let ptb = #\hyperref[sailRISCVzcurPTB64]{curPTB64}#(satp); + + /* PTW extensions: initialize the PTW extension state. */ + let ext_ptw : ext_ptw = init_ext_ptw; + + match mode { + Sbare => #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(vAddr, ext_ptw), + Sv39 => { if #\hyperref[sailRISCVzisValidSv39Addr]{isValidSv39Addr}#(vAddr) + then match #\hyperref[sailRISCVztranslate39]{translate39}#(asid, ptb, vAddr[38 .. 0], ac, effPriv, mxr, do_sum, SV39_LEVELS - 1, ext_ptw) { + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(pa, ext_ptw) => #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(pa), ext_ptw), + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(f, ext_ptw) => #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVztranslationException]{translationException}#(ac, f), ext_ptw) + } + else #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVztranslationException]{translationException}#(ac, #\hyperref[sailRISCVzPTWzyInvalidzyAddr]{PTW\_Invalid\_Addr}#()), ext_ptw) + }, + Sv48 => { if #\hyperref[sailRISCVzisValidSv48Addr]{isValidSv48Addr}#(vAddr) + then match #\hyperref[sailRISCVztranslate48]{translate48}#(asid, ptb, vAddr[47 .. 0], ac, effPriv, mxr, do_sum, SV48_LEVELS - 1, ext_ptw) { + #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(pa, ext_ptw) => #\hyperref[sailRISCVzTRzyAddress]{TR\_Address}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(pa), ext_ptw), + #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(f, ext_ptw) => #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVztranslationException]{translationException}#(ac, f), ext_ptw) + } + else #\hyperref[sailRISCVzTRzyFailure]{TR\_Failure}#(#\hyperref[sailRISCVztranslationException]{translationException}#(ac, #\hyperref[sailRISCVzPTWzyInvalidzyAddr]{PTW\_Invalid\_Addr}#()), ext_ptw) + }, + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("unsupported address translation scheme") + } +} diff --git a/sail_latex_riscv/fnztranslationexceptionbd47ba58dcb6fcc0be14f6efdd551ad8.tex b/sail_latex_riscv/fnztranslationexceptionbd47ba58dcb6fcc0be14f6efdd551ad8.tex new file mode 100644 index 00000000..0d94e1e7 --- /dev/null +++ b/sail_latex_riscv/fnztranslationexceptionbd47ba58dcb6fcc0be14f6efdd551ad8.tex @@ -0,0 +1,26 @@ +function #\hyperref[sailRISCVztranslationException]{translationException}#(a : #\hyperref[sailRISCVzAccessType]{AccessType}#(ext_access_type), f : PTW_Error) -> ExceptionType = { + let e : ExceptionType = + match (a, f) { + /* Tag-asserting stores can raise CHERI page faults. */ + (#\hyperref[sailRISCVzWrite]{Write}#(Cap), #\hyperref[sailRISCVzPTWzyExtzyError]{PTW\_Ext\_Error}#(AT_CAP_ERR)) => #\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(EXC_SAMO_CAP_PAGE_FAULT), + (#\hyperref[sailRISCVzReadWrite]{ReadWrite}#(Cap, _), #\hyperref[sailRISCVzPTWzyExtzyError]{PTW\_Ext\_Error}#(AT_CAP_ERR)) => #\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(EXC_SAMO_CAP_PAGE_FAULT), + (#\hyperref[sailRISCVzReadWrite]{ReadWrite}#(_, Cap), #\hyperref[sailRISCVzPTWzyExtzyError]{PTW\_Ext\_Error}#(AT_CAP_ERR)) => #\hyperref[sailRISCVzEzyExtension]{E\_Extension}#(EXC_SAMO_CAP_PAGE_FAULT), + + /* No other operations should raise CHERI-specific page faults */ + (_, #\hyperref[sailRISCVzPTWzyExtzyError]{PTW\_Ext\_Error}#(_)) => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("Unexpected PTW Extension Error"), + + /* For other exceptions, Cap and Data accesses fault in the same way. */ + (#\hyperref[sailRISCVzReadWrite]{ReadWrite}#(_, _), #\hyperref[sailRISCVzPTWzyAccess]{PTW\_Access}#()) => #\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#(), + (#\hyperref[sailRISCVzReadWrite]{ReadWrite}#(_, _), _) => #\hyperref[sailRISCVzEzySAMOzyPagezyFault]{E\_SAMO\_Page\_Fault}#(), + (#\hyperref[sailRISCVzRead]{Read}#(_), #\hyperref[sailRISCVzPTWzyAccess]{PTW\_Access}#()) => #\hyperref[sailRISCVzEzyLoadzyAccesszyFault]{E\_Load\_Access\_Fault}#(), + (#\hyperref[sailRISCVzRead]{Read}#(_), _) => #\hyperref[sailRISCVzEzyLoadzyPagezyFault]{E\_Load\_Page\_Fault}#(), + (#\hyperref[sailRISCVzWrite]{Write}#(_), #\hyperref[sailRISCVzPTWzyAccess]{PTW\_Access}#()) => #\hyperref[sailRISCVzEzySAMOzyAccesszyFault]{E\_SAMO\_Access\_Fault}#(), + (#\hyperref[sailRISCVzWrite]{Write}#(_), _) => #\hyperref[sailRISCVzEzySAMOzyPagezyFault]{E\_SAMO\_Page\_Fault}#(), + + (#\hyperref[sailRISCVzExecute]{Execute}#(), #\hyperref[sailRISCVzPTWzyAccess]{PTW\_Access}#()) => #\hyperref[sailRISCVzEzyFetchzyAccesszyFault]{E\_Fetch\_Access\_Fault}#(), + (#\hyperref[sailRISCVzExecute]{Execute}#(), _) => #\hyperref[sailRISCVzEzyFetchzyPagezyFault]{E\_Fetch\_Page\_Fault}#() + } in { +/* #\hyperref[sailRISCVzprintzymem]{print\_mem}#("#\hyperref[sailRISCVztranslationException]{translationException}#(" ^ a ^ ", " ^ f ^ ") -> " ^ e); */ + e + } +} diff --git a/sail_latex_riscv/fnztranslationmode51f0fd652f39ec2f6d4c16847f0d4345.tex b/sail_latex_riscv/fnztranslationmode51f0fd652f39ec2f6d4c16847f0d4345.tex new file mode 100644 index 00000000..6da6d37c --- /dev/null +++ b/sail_latex_riscv/fnztranslationmode51f0fd652f39ec2f6d4c16847f0d4345.tex @@ -0,0 +1,20 @@ +function #\hyperref[sailRISCVztranslationMode]{translationMode}#(priv) = { + if priv == Machine then Sbare + else { + let arch = #\hyperref[sailRISCVzarchitecture]{architecture}#(#\hyperref[sailRISCVzgetzymstatuszySXL]{get\_mstatus\_SXL}#(mstatus)); + match arch { + #\hyperref[sailRISCVzSome]{Some}#(RV64) => { + let mbits : satp_mode = #\hyperref[sailRISCVzMkzySatp64]{Mk\_Satp64}#(satp).#\hyperref[sailRISCVzMode]{Mode}#(); + match #\hyperref[sailRISCVzsatp64Modezyofzybits]{satp64Mode\_of\_bits}#(RV64, mbits) { + #\hyperref[sailRISCVzSome]{Some}#(m) => m, + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("invalid RV64 translation mode in satp") + } + }, + #\hyperref[sailRISCVzSome]{Some}#(RV32) => { + let s = #\hyperref[sailRISCVzMkzySatp32]{Mk\_Satp32}#(satp[31..0]); + if s.#\hyperref[sailRISCVzMode]{Mode}#() == 0b0 then Sbare else Sv32 + }, + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("unsupported address translation arch") + } + } +} diff --git a/sail_latex_riscv/fnztrap_handler0acf2ac9f6239ac64448b463d4df9cf4.tex b/sail_latex_riscv/fnztrap_handler0acf2ac9f6239ac64448b463d4df9cf4.tex new file mode 100644 index 00000000..2e1b728a --- /dev/null +++ b/sail_latex_riscv/fnztrap_handler0acf2ac9f6239ac64448b463d4df9cf4.tex @@ -0,0 +1,77 @@ +function #\hyperref[sailRISCVztrapzyhandler]{trap\_handler}#(del_priv : Privilege, intr : bool, c : exc_code, pc : xlenbits, info : #\hyperref[sailRISCVzoption]{option}#(xlenbits), ext : #\hyperref[sailRISCVzoption]{option}#(ext_exception)) + -> xlenbits = { + #\hyperref[sailRISCVzrvfizytrap]{rvfi\_trap}#(); + if #\hyperref[sailRISCVzgetzyconfigzyprintzyplatform]{get\_config\_print\_platform}#() + then #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("handling " ^ (if intr then "int#" else "exc#") + ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(c) ^ " at priv " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(del_priv) + ^ " with tval " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVztval]{tval}#(info))); + + #\hyperref[sailRISCVzcancelzyreservation]{cancel\_reservation}#(); + + match (del_priv) { + Machine => { + mcause->#\hyperref[sailRISCVzIsInterrupt]{IsInterrupt}#() = #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(intr); + mcause->#\hyperref[sailRISCVzCause]{Cause}#() = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(c); + + mstatus->#\hyperref[sailRISCVzMPIE]{MPIE}#() = mstatus.#\hyperref[sailRISCVzMIE]{MIE}#(); + mstatus->#\hyperref[sailRISCVzMIE]{MIE}#() = 0b0; + mstatus->#\hyperref[sailRISCVzMPP]{MPP}#() = #\hyperref[sailRISCVzprivLevelzytozybits]{privLevel\_to\_bits}#(cur_privilege); + mtval = #\hyperref[sailRISCVztval]{tval}#(info); + mepc = pc; + + cur_privilege = del_priv; + + #\hyperref[sailRISCVzhandlezytrapzyextension]{handle\_trap\_extension}#(del_priv, pc, ext); + + if #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}#() + then #\hyperref[sailRISCVzprintzyreg]{print\_reg}#("CSR mstatus <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mstatus.#\hyperref[sailRISCVzbits]{bits}#())); + + #\hyperref[sailRISCVzpreparezytrapzyvector]{prepare\_trap\_vector}#(del_priv, mcause) + }, + Supervisor => { + assert (#\hyperref[sailRISCVzhaveSupMode]{haveSupMode}#(), "no supervisor mode present for delegation"); + + scause->#\hyperref[sailRISCVzIsInterrupt]{IsInterrupt}#() = #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(intr); + scause->#\hyperref[sailRISCVzCause]{Cause}#() = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(c); + + mstatus->#\hyperref[sailRISCVzSPIE]{SPIE}#() = mstatus.#\hyperref[sailRISCVzSIE]{SIE}#(); + mstatus->#\hyperref[sailRISCVzSIE]{SIE}#() = 0b0; + mstatus->#\hyperref[sailRISCVzSPP]{SPP}#() = match cur_privilege { + User => 0b0, + Supervisor => 0b1, + Machine => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("invalid privilege for s-mode trap") + }; + stval = #\hyperref[sailRISCVztval]{tval}#(info); + sepc = pc; + + cur_privilege = del_priv; + + #\hyperref[sailRISCVzhandlezytrapzyextension]{handle\_trap\_extension}#(del_priv, pc, ext); + + if #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}#() + then #\hyperref[sailRISCVzprintzyreg]{print\_reg}#("CSR mstatus <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mstatus.#\hyperref[sailRISCVzbits]{bits}#())); + + #\hyperref[sailRISCVzpreparezytrapzyvector]{prepare\_trap\_vector}#(del_priv, scause) + }, + User => { + assert(#\hyperref[sailRISCVzhaveUsrMode]{haveUsrMode}#(), "no user mode present for delegation"); + + ucause->#\hyperref[sailRISCVzIsInterrupt]{IsInterrupt}#() = #\hyperref[sailRISCVzboolzytozybits]{bool\_to\_bits}#(intr); + ucause->#\hyperref[sailRISCVzCause]{Cause}#() = #\hyperref[sailRISCVzEXTZ]{EXTZ}#(c); + + mstatus->#\hyperref[sailRISCVzUPIE]{UPIE}#() = mstatus.#\hyperref[sailRISCVzUIE]{UIE}#(); + mstatus->#\hyperref[sailRISCVzUIE]{UIE}#() = 0b0; + utval = #\hyperref[sailRISCVztval]{tval}#(info); + uepc = pc; + + cur_privilege = del_priv; + + #\hyperref[sailRISCVzhandlezytrapzyextension]{handle\_trap\_extension}#(del_priv, pc, ext); + + if #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}#() + then #\hyperref[sailRISCVzprintzyreg]{print\_reg}#("CSR mstatus <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(mstatus.#\hyperref[sailRISCVzbits]{bits}#())); + + #\hyperref[sailRISCVzpreparezytrapzyvector]{prepare\_trap\_vector}#(del_priv, ucause) + } + }; +} diff --git a/sail_latex_riscv/fnztrapvectormode_of_bits3ab887814163c96ab28aec41cb9b44f6.tex b/sail_latex_riscv/fnztrapvectormode_of_bits3ab887814163c96ab28aec41cb9b44f6.tex new file mode 100644 index 00000000..0ddbde7b --- /dev/null +++ b/sail_latex_riscv/fnztrapvectormode_of_bits3ab887814163c96ab28aec41cb9b44f6.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVztrapVectorModezyofzybits]{trapVectorMode\_of\_bits}# (m) = + match (m) { + 0b00 => TV_Direct, + 0b01 => TV_Vector, + _ => TV_Reserved + } diff --git a/sail_latex_riscv/fnztrapvectormode_of_num8f2938d16cb187b62f9cdbbb35278d48.tex b/sail_latex_riscv/fnztrapvectormode_of_num8f2938d16cb187b62f9cdbbb35278d48.tex new file mode 100644 index 00000000..2d7c9d35 --- /dev/null +++ b/sail_latex_riscv/fnztrapvectormode_of_num8f2938d16cb187b62f9cdbbb35278d48.tex @@ -0,0 +1,5 @@ +function TrapVectorMode_of_num arg# = match arg# { + 0 => TV_Direct, + 1 => TV_Vector, + _ => TV_Reserved +} diff --git a/sail_latex_riscv/fnztval0ee7d37a987a82754891fc591aec5852.tex b/sail_latex_riscv/fnztval0ee7d37a987a82754891fc591aec5852.tex new file mode 100644 index 00000000..de9dc03f --- /dev/null +++ b/sail_latex_riscv/fnztval0ee7d37a987a82754891fc591aec5852.tex @@ -0,0 +1,6 @@ +function #\hyperref[sailRISCVztval]{tval}#(excinfo : #\hyperref[sailRISCVzoption]{option}#(xlenbits)) -> xlenbits = { + match (excinfo) { + #\hyperref[sailRISCVzSome]{Some}#(e) => e, + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0) + } +} diff --git a/sail_latex_riscv/fnztvec_addrc6c52b287eacbc1aca798406d1b08576.tex b/sail_latex_riscv/fnztvec_addrc6c52b287eacbc1aca798406d1b08576.tex new file mode 100644 index 00000000..9cb50eb0 --- /dev/null +++ b/sail_latex_riscv/fnztvec_addrc6c52b287eacbc1aca798406d1b08576.tex @@ -0,0 +1,10 @@ +function #\hyperref[sailRISCVztveczyaddr]{tvec\_addr}#(m : Mtvec, c : Mcause) -> #\hyperref[sailRISCVzoption]{option}#(xlenbits) = { + let base : xlenbits = m.#\hyperref[sailRISCVzBase]{Base}#() @ 0b00; + match (#\hyperref[sailRISCVztrapVectorModezyofzybits]{trapVectorMode\_of\_bits}#(m.#\hyperref[sailRISCVzMode]{Mode}#())) { + TV_Direct => #\hyperref[sailRISCVzSome]{Some}#(base), + TV_Vector => if c.#\hyperref[sailRISCVzIsInterrupt]{IsInterrupt}#() == 0b1 + then #\hyperref[sailRISCVzSome]{Some}#(base + (#\hyperref[sailRISCVzEXTZ]{EXTZ}#(c.#\hyperref[sailRISCVzCause]{Cause}#()) << 2)) + else #\hyperref[sailRISCVzSome]{Some}#(base), + TV_Reserved => #\hyperref[sailRISCVzNone]{None}#() + } +} diff --git a/sail_latex_riscv/fnzufflagb3d552180ae10d9ed1b23a8e10ad2e9c.tex b/sail_latex_riscv/fnzufflagb3d552180ae10d9ed1b23a8e10ad2e9c.tex new file mode 100644 index 00000000..2cbd0f95 --- /dev/null +++ b/sail_latex_riscv/fnzufflagb3d552180ae10d9ed1b23a8e10ad2e9c.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzufFlag]{ufFlag}#() -> #\hyperref[sailRISCVzbits]{bits}#(5) = 0b_00010 diff --git a/sail_latex_riscv/fnzunsealcap58689ae49a7317c60147327414a678d2.tex b/sail_latex_riscv/fnzunsealcap58689ae49a7317c60147327414a678d2.tex new file mode 100644 index 00000000..f2d6862a --- /dev/null +++ b/sail_latex_riscv/fnzunsealcap58689ae49a7317c60147327414a678d2.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzunsealCap]{unsealCap}#(cap) : Capability -> Capability = + {cap with otype=#\hyperref[sailRISCVztozybits]{to\_bits}#(cap_otype_width, otype_unsealed)} diff --git a/sail_latex_riscv/fnzuop_of_num86c5f7f375d0126822beff686eb42370.tex b/sail_latex_riscv/fnzuop_of_num86c5f7f375d0126822beff686eb42370.tex new file mode 100644 index 00000000..ebe2ab18 --- /dev/null +++ b/sail_latex_riscv/fnzuop_of_num86c5f7f375d0126822beff686eb42370.tex @@ -0,0 +1,4 @@ +function uop_of_num arg# = match arg# { + 0 => RISCV_LUI, + _ => RISCV_AUIPC +} diff --git a/sail_latex_riscv/fnzupdate_pte_bitsd84d357c2799412dbae43ca95464282b.tex b/sail_latex_riscv/fnzupdate_pte_bitsd84d357c2799412dbae43ca95464282b.tex new file mode 100644 index 00000000..579ee54d --- /dev/null +++ b/sail_latex_riscv/fnzupdate_pte_bitsd84d357c2799412dbae43ca95464282b.tex @@ -0,0 +1,18 @@ +function #\hyperref[sailRISCVzupdatezyPTEzyBits]{update\_PTE\_Bits}#(p : PTE_Bits, a : #\hyperref[sailRISCVzAccessType]{AccessType}#(ext_access_type), ext : extPte) -> #\hyperref[sailRISCVzoption]{option}#((PTE_Bits, extPte)) = { + // dirty bit + let update_d = p.#\hyperref[sailRISCVzD]{D}#() == 0b0 & (match a { + #\hyperref[sailRISCVzExecute]{Execute}#() => false, + #\hyperref[sailRISCVzRead]{Read}#(_) => false, + #\hyperref[sailRISCVzWrite]{Write}#(_) => true, + #\hyperref[sailRISCVzReadWrite]{ReadWrite}#(_, _) => true + }); + + // accessed bit + let update_a = p.#\hyperref[sailRISCVzA]{A}#() == 0b0; + + if update_d | update_a then { + let np = #\hyperref[sailRISCVzupdatezyA]{update\_A}#(p, 0b1); + let np = if update_d then #\hyperref[sailRISCVzupdatezyD]{update\_D}#(np, 0b1) else np; + #\hyperref[sailRISCVzSome]{Some}#(np, ext) + } else #\hyperref[sailRISCVzNone]{None}#() +} diff --git a/sail_latex_riscv/fnzupdate_softfloat_fflagsc33a686e24584b0b748b2ae8f801c505.tex b/sail_latex_riscv/fnzupdate_softfloat_fflagsc33a686e24584b0b748b2ae8f801c505.tex new file mode 100644 index 00000000..abe629d6 --- /dev/null +++ b/sail_latex_riscv/fnzupdate_softfloat_fflagsc33a686e24584b0b748b2ae8f801c505.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzupdatezysoftfloatzyfflags]{update\_softfloat\_fflags}#(flags) = { + float_fflags = #\hyperref[sailRISCVzsailzyzzerozyextend]{sail\_zero\_extend}#(flags, 64); +} diff --git a/sail_latex_riscv/fnzwalk398233e1f75321f48773213830a045bfac.tex b/sail_latex_riscv/fnzwalk398233e1f75321f48773213830a045bfac.tex new file mode 100644 index 00000000..21ca8d4a --- /dev/null +++ b/sail_latex_riscv/fnzwalk398233e1f75321f48773213830a045bfac.tex @@ -0,0 +1,73 @@ +function #\hyperref[sailRISCVzwalk39]{walk39}#(vaddr, ac, priv, mxr, do_sum, ptb, level, global, ext_ptw) = { + let va = #\hyperref[sailRISCVzMkzySV39zyVaddr]{Mk\_SV39\_Vaddr}#(vaddr); + let pt_ofs : paddr64 = #\hyperref[sailRISCVzshiftl]{shiftl}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzshiftr]{shiftr}#(va.#\hyperref[sailRISCVzVPNi]{VPNi}#(), (level * SV39_LEVEL_BITS))[(SV39_LEVEL_BITS - 1) .. 0]), + PTE39_LOG_SIZE); + let pte_addr = ptb + pt_ofs; + match (#\hyperref[sailRISCVzmemzyread]{mem\_read}#(ac, #\hyperref[sailRISCVzEXTZ]{EXTZ}#(pte_addr), 8, false, false, false)) { + #\hyperref[sailRISCVzMemException]{MemException}#(_) => { +/* #\hyperref[sailRISCVzprint]{print}#("#\hyperref[sailRISCVzwalk39]{walk39}#(vaddr=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(vaddr) ^ " level=" ^ #\hyperref[sailRISCVzstringzyofzyint]{string\_of\_int}#(level) + ^ " pt_base=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(ptb) + ^ " pt_ofs=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pt_ofs) + ^ " pte_addr=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pte_addr) + ^ ": invalid pte address"); */ + #\hyperref[sailRISCVzPTWzyFailure]{PTW\_Failure}#(#\hyperref[sailRISCVzPTWzyAccess]{PTW\_Access}#(), ext_ptw) + }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(v) => { + let pte = #\hyperref[sailRISCVzMkzySV39zyPTE]{Mk\_SV39\_PTE}#(v); + let pbits = pte.#\hyperref[sailRISCVzBITS]{BITS}#(); + let ext_pte = pte.#\hyperref[sailRISCVzExt]{Ext}#(); + let pattr = #\hyperref[sailRISCVzMkzyPTEzyBits]{Mk\_PTE\_Bits}#(pbits); + let is_global = global | (pattr.#\hyperref[sailRISCVzG]{G}#() == 0b1); +/* #\hyperref[sailRISCVzprint]{print}#("#\hyperref[sailRISCVzwalk39]{walk39}#(vaddr=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(vaddr) ^ " level=" ^ #\hyperref[sailRISCVzstringzyofzyint]{string\_of\_int}#(level) + ^ " pt_base=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(ptb) + ^ " pt_ofs=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pt_ofs) + ^ " pte_addr=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pte_addr) + ^ " pte=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(v)); */ + if #\hyperref[sailRISCVzisInvalidPTE]{isInvalidPTE}#(pbits, ext_pte) then { +/* #\hyperref[sailRISCVzprint]{print}#("walk39: invalid pte"); */ + #\hyperref[sailRISCVzPTWzyFailure]{PTW\_Failure}#(#\hyperref[sailRISCVzPTWzyInvalidzyPTE]{PTW\_Invalid\_PTE}#(), ext_ptw) + } else { + if #\hyperref[sailRISCVzisPTEPtr]{isPTEPtr}#(pbits, ext_pte) then { + if level > 0 then { + /* walk down the pointer to the next level */ + #\hyperref[sailRISCVzwalk39]{walk39}#(vaddr, ac, priv, mxr, do_sum, #\hyperref[sailRISCVzshiftl]{shiftl}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#()), PAGESIZE_BITS), level - 1, is_global, ext_ptw) + } else { + /* last-level PTE contains a pointer instead of a leaf */ +/* #\hyperref[sailRISCVzprint]{print}#("walk39: last-level pte contains a ptr"); */ + #\hyperref[sailRISCVzPTWzyFailure]{PTW\_Failure}#(#\hyperref[sailRISCVzPTWzyInvalidzyPTE]{PTW\_Invalid\_PTE}#(), ext_ptw) + } + } else { /* leaf PTE */ + match #\hyperref[sailRISCVzcheckPTEPermission]{checkPTEPermission}#(ac, priv, mxr, do_sum, pattr, ext_pte, ext_ptw) { + #\hyperref[sailRISCVzPTEzyCheckzyFailure]{PTE\_Check\_Failure}#(ext_ptw, ext_ptw_fail) => { +/* #\hyperref[sailRISCVzprint]{print}#("walk39: pte permission check failure"); */ + #\hyperref[sailRISCVzPTWzyFailure]{PTW\_Failure}#(#\hyperref[sailRISCVzextzygetzyptwzyerror]{ext\_get\_ptw\_error}#(ext_ptw_fail), ext_ptw) + }, + #\hyperref[sailRISCVzPTEzyCheckzySuccess]{PTE\_Check\_Success}#(ext_ptw) => { + if level > 0 then { /* superpage */ + /* fixme hack: to get a mask of appropriate size */ + let mask = #\hyperref[sailRISCVzshiftl]{shiftl}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#() ^ pte.#\hyperref[sailRISCVzPPNi]{PPNi}#() ^ #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1), level * SV39_LEVEL_BITS) - 1; + if (pte.#\hyperref[sailRISCVzPPNi]{PPNi}#() & mask) != #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0) then { + /* misaligned superpage mapping */ +/* #\hyperref[sailRISCVzprint]{print}#("walk39: misaligned superpage mapping"); */ + #\hyperref[sailRISCVzPTWzyFailure]{PTW\_Failure}#(#\hyperref[sailRISCVzPTWzyMisaligned]{PTW\_Misaligned}#(), ext_ptw) + } else { + /* add the appropriate bits of the VPN to the superpage PPN */ + let ppn = pte.#\hyperref[sailRISCVzPPNi]{PPNi}#() | (#\hyperref[sailRISCVzEXTZ]{EXTZ}#(va.#\hyperref[sailRISCVzVPNi]{VPNi}#()) & mask); +/* let res = #\hyperref[sailRISCVzappend]{append}#(ppn, va.#\hyperref[sailRISCVzPgOfs]{PgOfs}#()); + #\hyperref[sailRISCVzprint]{print}#("walk39: using superpage: pte.ppn=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#()) + ^ " ppn=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(ppn) ^ " res=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(res)); */ + #\hyperref[sailRISCVzPTWzySuccess]{PTW\_Success}#(#\hyperref[sailRISCVzappend]{append}#(ppn, va.#\hyperref[sailRISCVzPgOfs]{PgOfs}#()), pte, pte_addr, level, is_global, ext_ptw) + } + } else { + /* normal leaf PTE */ +/* let res = #\hyperref[sailRISCVzappend]{append}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#(), va.#\hyperref[sailRISCVzPgOfs]{PgOfs}#()); + #\hyperref[sailRISCVzprint]{print}#("walk39: pte.ppn=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#()) ^ " ppn=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#()) ^ " res=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(res)); */ + #\hyperref[sailRISCVzPTWzySuccess]{PTW\_Success}#(#\hyperref[sailRISCVzappend]{append}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#(), va.#\hyperref[sailRISCVzPgOfs]{PgOfs}#()), pte, pte_addr, level, is_global, ext_ptw) + } + } + } + } + } + } + } +} diff --git a/sail_latex_riscv/fnzwalk486c4033235ca01e713873e89320a939ac.tex b/sail_latex_riscv/fnzwalk486c4033235ca01e713873e89320a939ac.tex new file mode 100644 index 00000000..be1360c9 --- /dev/null +++ b/sail_latex_riscv/fnzwalk486c4033235ca01e713873e89320a939ac.tex @@ -0,0 +1,73 @@ +function #\hyperref[sailRISCVzwalk48]{walk48}#(vaddr, ac, priv, mxr, do_sum, ptb, level, global, ext_ptw) = { + let va = #\hyperref[sailRISCVzMkzySV48zyVaddr]{Mk\_SV48\_Vaddr}#(vaddr); + let pt_ofs : paddr64 = #\hyperref[sailRISCVzshiftl]{shiftl}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(#\hyperref[sailRISCVzshiftr]{shiftr}#(va.#\hyperref[sailRISCVzVPNi]{VPNi}#(), (level * SV48_LEVEL_BITS))[(SV48_LEVEL_BITS - 1) .. 0]), + PTE48_LOG_SIZE); + let pte_addr = ptb + pt_ofs; + match (#\hyperref[sailRISCVzmemzyread]{mem\_read}#(ac, #\hyperref[sailRISCVzEXTZ]{EXTZ}#(pte_addr), 8, false, false, false)) { + #\hyperref[sailRISCVzMemException]{MemException}#(_) => { +/* #\hyperref[sailRISCVzprint]{print}#("#\hyperref[sailRISCVzwalk48]{walk48}#(vaddr=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(vaddr) ^ " level=" ^ #\hyperref[sailRISCVzstringzyofzyint]{string\_of\_int}#(level) + ^ " pt_base=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(ptb) + ^ " pt_ofs=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pt_ofs) + ^ " pte_addr=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pte_addr) + ^ ": invalid pte address"); */ + #\hyperref[sailRISCVzPTWzyFailure]{PTW\_Failure}#(#\hyperref[sailRISCVzPTWzyAccess]{PTW\_Access}#(), ext_ptw) + }, + #\hyperref[sailRISCVzMemValue]{MemValue}#(v) => { + let pte = #\hyperref[sailRISCVzMkzySV48zyPTE]{Mk\_SV48\_PTE}#(v); + let pbits = pte.#\hyperref[sailRISCVzBITS]{BITS}#(); + let ext_pte = pte.#\hyperref[sailRISCVzExt]{Ext}#(); + let pattr = #\hyperref[sailRISCVzMkzyPTEzyBits]{Mk\_PTE\_Bits}#(pbits); + let is_global = global | (pattr.#\hyperref[sailRISCVzG]{G}#() == 0b1); +/* #\hyperref[sailRISCVzprint]{print}#("#\hyperref[sailRISCVzwalk48]{walk48}#(vaddr=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(vaddr) ^ " level=" ^ #\hyperref[sailRISCVzstringzyofzyint]{string\_of\_int}#(level) + ^ " pt_base=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(ptb) + ^ " pt_ofs=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pt_ofs) + ^ " pte_addr=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pte_addr) + ^ " pte=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(v)); */ + if #\hyperref[sailRISCVzisInvalidPTE]{isInvalidPTE}#(pbits, ext_pte) then { +/* #\hyperref[sailRISCVzprint]{print}#("walk48: invalid pte"); */ + #\hyperref[sailRISCVzPTWzyFailure]{PTW\_Failure}#(#\hyperref[sailRISCVzPTWzyInvalidzyPTE]{PTW\_Invalid\_PTE}#(), ext_ptw) + } else { + if #\hyperref[sailRISCVzisPTEPtr]{isPTEPtr}#(pbits, ext_pte) then { + if level > 0 then { + /* walk down the pointer to the next level */ + #\hyperref[sailRISCVzwalk48]{walk48}#(vaddr, ac, priv, mxr, do_sum, #\hyperref[sailRISCVzshiftl]{shiftl}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#()), PAGESIZE_BITS), level - 1, is_global, ext_ptw) + } else { + /* last-level PTE contains a pointer instead of a leaf */ +/* #\hyperref[sailRISCVzprint]{print}#("walk48: last-level pte contains a ptr"); */ + #\hyperref[sailRISCVzPTWzyFailure]{PTW\_Failure}#(#\hyperref[sailRISCVzPTWzyInvalidzyPTE]{PTW\_Invalid\_PTE}#(), ext_ptw) + } + } else { /* leaf PTE */ + match #\hyperref[sailRISCVzcheckPTEPermission]{checkPTEPermission}#(ac, priv, mxr, do_sum, pattr, ext_pte, ext_ptw) { + #\hyperref[sailRISCVzPTEzyCheckzyFailure]{PTE\_Check\_Failure}#(ext_ptw, ext_ptw_fail) => { +/* #\hyperref[sailRISCVzprint]{print}#("walk48: pte permission check failure"); */ + #\hyperref[sailRISCVzPTWzyFailure]{PTW\_Failure}#(#\hyperref[sailRISCVzextzygetzyptwzyerror]{ext\_get\_ptw\_error}#(ext_ptw_fail), ext_ptw) + }, + #\hyperref[sailRISCVzPTEzyCheckzySuccess]{PTE\_Check\_Success}#(ext_ptw) => { + if level > 0 then { /* superpage */ + /* fixme hack: to get a mask of appropriate size */ + let mask = #\hyperref[sailRISCVzshiftl]{shiftl}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#() ^ pte.#\hyperref[sailRISCVzPPNi]{PPNi}#() ^ #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b1), level * SV48_LEVEL_BITS) - 1; + if (pte.#\hyperref[sailRISCVzPPNi]{PPNi}#() & mask) != #\hyperref[sailRISCVzEXTZ]{EXTZ}#(0b0) then { + /* misaligned superpage mapping */ +/* #\hyperref[sailRISCVzprint]{print}#("walk48: misaligned superpage mapping"); */ + #\hyperref[sailRISCVzPTWzyFailure]{PTW\_Failure}#(#\hyperref[sailRISCVzPTWzyMisaligned]{PTW\_Misaligned}#(), ext_ptw) + } else { + /* add the appropriate bits of the VPN to the superpage PPN */ + let ppn = pte.#\hyperref[sailRISCVzPPNi]{PPNi}#() | (#\hyperref[sailRISCVzEXTZ]{EXTZ}#(va.#\hyperref[sailRISCVzVPNi]{VPNi}#()) & mask); +/* let res = #\hyperref[sailRISCVzappend]{append}#(ppn, va.#\hyperref[sailRISCVzPgOfs]{PgOfs}#()); + #\hyperref[sailRISCVzprint]{print}#("walk48: using superpage: pte.ppn=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#()) + ^ " ppn=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(ppn) ^ " res=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(res)); */ + #\hyperref[sailRISCVzPTWzySuccess]{PTW\_Success}#(#\hyperref[sailRISCVzappend]{append}#(ppn, va.#\hyperref[sailRISCVzPgOfs]{PgOfs}#()), pte, pte_addr, level, is_global, ext_ptw) + } + } else { + /* normal leaf PTE */ +/* let res = #\hyperref[sailRISCVzappend]{append}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#(), va.#\hyperref[sailRISCVzPgOfs]{PgOfs}#()); + #\hyperref[sailRISCVzprint]{print}#("walk48: pte.ppn=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#()) ^ " ppn=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#()) ^ " res=" ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(res)); */ + #\hyperref[sailRISCVzPTWzySuccess]{PTW\_Success}#(#\hyperref[sailRISCVzappend]{append}#(pte.#\hyperref[sailRISCVzPPNi]{PPNi}#(), va.#\hyperref[sailRISCVzPgOfs]{PgOfs}#()), pte, pte_addr, level, is_global, ext_ptw) + } + } + } + } + } + } + } +} diff --git a/sail_latex_riscv/fnzwc721d52ce2fe818d0148aaf1d5b6e2bec.tex b/sail_latex_riscv/fnzwc721d52ce2fe818d0148aaf1d5b6e2bec.tex new file mode 100644 index 00000000..fadb30a7 --- /dev/null +++ b/sail_latex_riscv/fnzwc721d52ce2fe818d0148aaf1d5b6e2bec.tex @@ -0,0 +1,42 @@ +function #\hyperref[sailRISCVzwC]{wC}# (r, v) = { + match r { + 0 => (), + 1 => x1 = v, + 2 => x2 = v, + 3 => x3 = v, + 4 => x4 = v, + 5 => x5 = v, + 6 => x6 = v, + 7 => x7 = v, + 8 => x8 = v, + 9 => x9 = v, + 10 => x10 = v, + 11 => x11 = v, + 12 => x12 = v, + 13 => x13 = v, + 14 => x14 = v, + 15 => x15 = v, + 16 => x16 = v, + 17 => x17 = v, + 18 => x18 = v, + 19 => x19 = v, + 20 => x20 = v, + 21 => x21 = v, + 22 => x22 = v, + 23 => x23 = v, + 24 => x24 = v, + 25 => x25 = v, + 26 => x26 = v, + 27 => x27 = v, + 28 => x28 = v, + 29 => x29 = v, + 30 => x30 = v, + 31 => x31 = v, + _ => #\hyperref[sailRISCVzinternalzyerror]{internal\_error}#("Invalid capability register") + }; + if (r != 0) then { + #\hyperref[sailRISCVzrvfizywX]{rvfi\_wX}#(r, v.address); + if #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}#() then + #\hyperref[sailRISCVzprintzyreg]{print\_reg}#("x" ^ #\hyperref[sailRISCVzstringzyofzyint]{string\_of\_int}#(r) ^ " <- " ^ #\hyperref[sailRISCVzRegStr]{RegStr}#(v)); + } +} diff --git a/sail_latex_riscv/fnzwc_bitsb8b2d4f53308d4bb8d154a1f6664d336.tex b/sail_latex_riscv/fnzwc_bitsb8b2d4f53308d4bb8d154a1f6664d336.tex new file mode 100644 index 00000000..f018548e --- /dev/null +++ b/sail_latex_riscv/fnzwc_bitsb8b2d4f53308d4bb8d154a1f6664d336.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzwCzybits]{wC\_bits}#(r: #\hyperref[sailRISCVzbits]{bits}#(5), v: regtype) -> unit = #\hyperref[sailRISCVzwC]{wC}#(#\hyperref[sailRISCVzunsigned]{unsigned}#(r), v) diff --git a/sail_latex_riscv/fnzwf_bits141c8aafc4ef81f118d39a00d8a5249d.tex b/sail_latex_riscv/fnzwf_bits141c8aafc4ef81f118d39a00d8a5249d.tex new file mode 100644 index 00000000..118f9780 --- /dev/null +++ b/sail_latex_riscv/fnzwf_bits141c8aafc4ef81f118d39a00d8a5249d.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzwFzybits]{wF\_bits}#(i: #\hyperref[sailRISCVzbits]{bits}#(5), data: flenbits) -> unit = { + #\hyperref[sailRISCVzwF]{wF}#(#\hyperref[sailRISCVzunsigned]{unsigned}#(i)) = data +} diff --git a/sail_latex_riscv/fnzwfd3e403dd75784ce7e0cfdf609e32706e.tex b/sail_latex_riscv/fnzwfd3e403dd75784ce7e0cfdf609e32706e.tex new file mode 100644 index 00000000..3fdb6ea8 --- /dev/null +++ b/sail_latex_riscv/fnzwfd3e403dd75784ce7e0cfdf609e32706e.tex @@ -0,0 +1,45 @@ +function #\hyperref[sailRISCVzwF]{wF}# (r, in_v) = { + let v = #\hyperref[sailRISCVzfregvalzyintozyfreg]{fregval\_into\_freg}#(in_v); + match r { + 0 => f0 = v, + 1 => f1 = v, + 2 => f2 = v, + 3 => f3 = v, + 4 => f4 = v, + 5 => f5 = v, + 6 => f6 = v, + 7 => f7 = v, + 8 => f8 = v, + 9 => f9 = v, + 10 => f10 = v, + 11 => f11 = v, + 12 => f12 = v, + 13 => f13 = v, + 14 => f14 = v, + 15 => f15 = v, + 16 => f16 = v, + 17 => f17 = v, + 18 => f18 = v, + 19 => f19 = v, + 20 => f20 = v, + 21 => f21 = v, + 22 => f22 = v, + 23 => f23 = v, + 24 => f24 = v, + 25 => f25 = v, + 26 => f26 = v, + 27 => f27 = v, + 28 => f28 = v, + 29 => f29 = v, + 30 => f30 = v, + 31 => f31 = v, + _ => assert(false, "invalid floating point register number") + }; + + #\hyperref[sailRISCVzdirtyzyfdzycontext]{dirty\_fd\_context}#(); + + if #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}#() + then + /* TODO: will only print bits; should we print in floating point format? */ + #\hyperref[sailRISCVzprintzyreg]{print\_reg}#("f" ^ #\hyperref[sailRISCVzstringzyofzyint]{string\_of\_int}#(r) ^ " <- " ^ #\hyperref[sailRISCVzFRegStr]{FRegStr}#(v)); +} diff --git a/sail_latex_riscv/fnzwithin_clintc139e042afc9910b6edf55c2c70f2e80.tex b/sail_latex_riscv/fnzwithin_clintc139e042afc9910b6edf55c2c70f2e80.tex new file mode 100644 index 00000000..064acab4 --- /dev/null +++ b/sail_latex_riscv/fnzwithin_clintc139e042afc9910b6edf55c2c70f2e80.tex @@ -0,0 +1,11 @@ +function within_clint forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool = { + /* To avoid overflow issues when physical memory extends to the end + * of the addressable range, we need to perform address bound checks + * on unsigned unbounded integers. + */ + let addr_int = #\hyperref[sailRISCVzunsigned]{unsigned}#(addr); + let clint_base_int = #\hyperref[sailRISCVzunsigned]{unsigned}#(#\hyperref[sailRISCVzplatzyclintzybase]{plat\_clint\_base}# ()); + let clint_size_int = #\hyperref[sailRISCVzunsigned]{unsigned}#(#\hyperref[sailRISCVzplatzyclintzysizze]{plat\_clint\_size}# ()); + clint_base_int <= addr_int + & (addr_int + sizeof('n)) <= (clint_base_int + clint_size_int) +} diff --git a/sail_latex_riscv/fnzwithin_htif_readable2f6131e40985c12d9270943521113c33.tex b/sail_latex_riscv/fnzwithin_htif_readable2f6131e40985c12d9270943521113c33.tex new file mode 100644 index 00000000..05183d63 --- /dev/null +++ b/sail_latex_riscv/fnzwithin_htif_readable2f6131e40985c12d9270943521113c33.tex @@ -0,0 +1,2 @@ +function within_htif_readable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool = + #\hyperref[sailRISCVzplatzyhtifzytohost]{plat\_htif\_tohost}#() == addr | (#\hyperref[sailRISCVzplatzyhtifzytohost]{plat\_htif\_tohost}#() + 4 == addr & width == 4) diff --git a/sail_latex_riscv/fnzwithin_htif_writablec356d0ea372a60437fdf28745e5e9ae3.tex b/sail_latex_riscv/fnzwithin_htif_writablec356d0ea372a60437fdf28745e5e9ae3.tex new file mode 100644 index 00000000..b3651fe3 --- /dev/null +++ b/sail_latex_riscv/fnzwithin_htif_writablec356d0ea372a60437fdf28745e5e9ae3.tex @@ -0,0 +1,2 @@ +function within_htif_writable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool = + #\hyperref[sailRISCVzplatzyhtifzytohost]{plat\_htif\_tohost}#() == addr | (#\hyperref[sailRISCVzplatzyhtifzytohost]{plat\_htif\_tohost}#() + 4 == addr & width == 4) diff --git a/sail_latex_riscv/fnzwithin_mmio_readable2afaf2bf016b6ead5a5708ec8508d184.tex b/sail_latex_riscv/fnzwithin_mmio_readable2afaf2bf016b6ead5a5708ec8508d184.tex new file mode 100644 index 00000000..3814b8e8 --- /dev/null +++ b/sail_latex_riscv/fnzwithin_mmio_readable2afaf2bf016b6ead5a5708ec8508d184.tex @@ -0,0 +1,2 @@ +function within_mmio_readable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool = + #\hyperref[sailRISCVzwithinzyclint]{within\_clint}#(addr, width) | (#\hyperref[sailRISCVzwithinzyhtifzyreadable]{within\_htif\_readable}#(addr, width) & 1 <= 'n) diff --git a/sail_latex_riscv/fnzwithin_mmio_writable310089204ce2d4e6a33811b1982373ad.tex b/sail_latex_riscv/fnzwithin_mmio_writable310089204ce2d4e6a33811b1982373ad.tex new file mode 100644 index 00000000..8dff7569 --- /dev/null +++ b/sail_latex_riscv/fnzwithin_mmio_writable310089204ce2d4e6a33811b1982373ad.tex @@ -0,0 +1,2 @@ +function within_mmio_writable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool = + #\hyperref[sailRISCVzwithinzyclint]{within\_clint}#(addr, width) | (#\hyperref[sailRISCVzwithinzyhtifzywritable]{within\_htif\_writable}#(addr, width) & 'n <= 8) diff --git a/sail_latex_riscv/fnzwithin_phys_mem5b6233a64f93394cb594812a945dcbb2.tex b/sail_latex_riscv/fnzwithin_phys_mem5b6233a64f93394cb594812a945dcbb2.tex new file mode 100644 index 00000000..af45bcbc --- /dev/null +++ b/sail_latex_riscv/fnzwithin_phys_mem5b6233a64f93394cb594812a945dcbb2.tex @@ -0,0 +1,27 @@ +function within_phys_mem forall 'n, 'n <= max_mem_access. (addr : xlenbits, width : atom('n)) -> bool = { + /* To avoid overflow issues when physical memory extends to the end + * of the addressable range, we need to perform address bound checks + * on unsigned unbounded integers. + */ + let addr_int = #\hyperref[sailRISCVzunsigned]{unsigned}#(addr); + let ram_base_int = #\hyperref[sailRISCVzunsigned]{unsigned}#(#\hyperref[sailRISCVzplatzyramzybase]{plat\_ram\_base}# ()); + let rom_base_int = #\hyperref[sailRISCVzunsigned]{unsigned}#(#\hyperref[sailRISCVzplatzyromzybase]{plat\_rom\_base}# ()); + let ram_size_int = #\hyperref[sailRISCVzunsigned]{unsigned}#(#\hyperref[sailRISCVzplatzyramzysizze]{plat\_ram\_size}# ()); + let rom_size_int = #\hyperref[sailRISCVzunsigned]{unsigned}#(#\hyperref[sailRISCVzplatzyromzysizze]{plat\_rom\_size}# ()); + + /* todo: iterate over segment list */ + if ( ram_base_int <= addr_int + & (addr_int + sizeof('n)) <= (ram_base_int + ram_size_int)) + then true + else if ( rom_base_int <= addr_int + & (addr_int + sizeof('n)) <= (rom_base_int + rom_size_int)) + then true + else { + #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#("within_phys_mem: " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(addr) ^ " not within phys-mem:"); + #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#(" plat_rom_base: " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVzplatzyromzybase]{plat\_rom\_base}# ())); + #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#(" plat_rom_size: " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVzplatzyromzysizze]{plat\_rom\_size}# ())); + #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#(" plat_ram_base: " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVzplatzyramzybase]{plat\_ram\_base}# ())); + #\hyperref[sailRISCVzprintzyplatform]{print\_platform}#(" plat_ram_size: " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(#\hyperref[sailRISCVzplatzyramzysizze]{plat\_ram\_size}# ())); + false + } +} diff --git a/sail_latex_riscv/fnzword_width_bytes3499487c0f03a80d8659fa504a62261f.tex b/sail_latex_riscv/fnzword_width_bytes3499487c0f03a80d8659fa504a62261f.tex new file mode 100644 index 00000000..c1791de3 --- /dev/null +++ b/sail_latex_riscv/fnzword_width_bytes3499487c0f03a80d8659fa504a62261f.tex @@ -0,0 +1,6 @@ +function word_width_bytes width = match width { + BYTE => 1, + HALF => 2, + WORD => 4, + DOUBLE => 8 +} diff --git a/sail_latex_riscv/fnzword_width_of_num5022e9594f19a45eb3d8079a7a770a00.tex b/sail_latex_riscv/fnzword_width_of_num5022e9594f19a45eb3d8079a7a770a00.tex new file mode 100644 index 00000000..f7fd9949 --- /dev/null +++ b/sail_latex_riscv/fnzword_width_of_num5022e9594f19a45eb3d8079a7a770a00.tex @@ -0,0 +1,6 @@ +function word_width_of_num arg# = match arg# { + 0 => BYTE, + 1 => HALF, + 2 => WORD, + _ => DOUBLE +} diff --git a/sail_latex_riscv/fnzwrite_fflagsf7610eb4597d886b515ad9553608a8d7.tex b/sail_latex_riscv/fnzwrite_fflagsf7610eb4597d886b515ad9553608a8d7.tex new file mode 100644 index 00000000..43eb153f --- /dev/null +++ b/sail_latex_riscv/fnzwrite_fflagsf7610eb4597d886b515ad9553608a8d7.tex @@ -0,0 +1,5 @@ +function #\hyperref[sailRISCVzwritezyfflags]{write\_fflags}#(fflags) = { + if fcsr.#\hyperref[sailRISCVzFFLAGS]{FFLAGS}#() != fflags + then #\hyperref[sailRISCVzdirtyzyfdzycontext]{dirty\_fd\_context}#(); + fcsr->#\hyperref[sailRISCVzFFLAGS]{FFLAGS}#() = fflags; +} diff --git a/sail_latex_riscv/fnzwrite_kind_of_num3c6c37285ad605eea3332f170d5b12d9.tex b/sail_latex_riscv/fnzwrite_kind_of_num3c6c37285ad605eea3332f170d5b12d9.tex new file mode 100644 index 00000000..78218e37 --- /dev/null +++ b/sail_latex_riscv/fnzwrite_kind_of_num3c6c37285ad605eea3332f170d5b12d9.tex @@ -0,0 +1,13 @@ +function write_kind_of_num arg# = match arg# { + 0 => Write_plain, + 1 => Write_conditional, + 2 => Write_release, + 3 => Write_exclusive, + 4 => Write_exclusive_release, + 5 => Write_RISCV_release, + 6 => Write_RISCV_strong_release, + 7 => Write_RISCV_conditional, + 8 => Write_RISCV_conditional_release, + 9 => Write_RISCV_conditional_strong_release, + _ => Write_X86_locked +} diff --git a/sail_latex_riscv/fnzwrite_ram_ea38ee1d0d3a88b7ca22f44ac1921c34c8.tex b/sail_latex_riscv/fnzwrite_ram_ea38ee1d0d3a88b7ca22f44ac1921c34c8.tex new file mode 100644 index 00000000..8e17b718 --- /dev/null +++ b/sail_latex_riscv/fnzwrite_ram_ea38ee1d0d3a88b7ca22f44ac1921c34c8.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzwritezyramzyea]{write\_ram\_ea}#(wk, addr, width) = + #\hyperref[sailRISCVzzyzywritezymemzyea]{\_\_write\_mem\_ea}#(wk, sizeof(xlen), addr, width) diff --git a/sail_latex_riscv/fnzwrite_ramaf59f53ca3a497b3b8d64cf319996fb8.tex b/sail_latex_riscv/fnzwrite_ramaf59f53ca3a497b3b8d64cf319996fb8.tex new file mode 100644 index 00000000..55c5a623 --- /dev/null +++ b/sail_latex_riscv/fnzwrite_ramaf59f53ca3a497b3b8d64cf319996fb8.tex @@ -0,0 +1,12 @@ +function #\hyperref[sailRISCVzwritezyram]{write\_ram}#(wk, addr, width, data, meta) = { + /* Write out metadata only if the value write succeeds. + * It is assumed for now that this write always succeeds; + * there is currently no return value. + * FIXME: We should convert the external API for all backends + * (not just for Lem) to consume the value along with the + * metadata to ensure atomicity. + */ + let ret : bool = #\hyperref[sailRISCVzzyzywritezymem]{\_\_write\_mem}#(wk, sizeof(xlen), addr, width, data); + if ret then #\hyperref[sailRISCVzzyzyWriteRAMzyMeta]{\_\_WriteRAM\_Meta}#(addr, width, meta); + ret +} diff --git a/sail_latex_riscv/fnzwrite_tlb39d07866694d7288e6a3cb2ac08a58c288.tex b/sail_latex_riscv/fnzwrite_tlb39d07866694d7288e6a3cb2ac08a58c288.tex new file mode 100644 index 00000000..c8ab4d78 --- /dev/null +++ b/sail_latex_riscv/fnzwrite_tlb39d07866694d7288e6a3cb2ac08a58c288.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzwritezyTLB39]{write\_TLB39}#(idx : nat, ent : TLB39_Entry) -> unit = + tlb39 = #\hyperref[sailRISCVzSome]{Some}#(ent) diff --git a/sail_latex_riscv/fnzwrite_tlb48c2deeba6fb9156609619ba23dcc84e5a.tex b/sail_latex_riscv/fnzwrite_tlb48c2deeba6fb9156609619ba23dcc84e5a.tex new file mode 100644 index 00000000..1bbd8b4f --- /dev/null +++ b/sail_latex_riscv/fnzwrite_tlb48c2deeba6fb9156609619ba23dcc84e5a.tex @@ -0,0 +1,2 @@ +function #\hyperref[sailRISCVzwritezyTLB48]{write\_TLB48}#(idx : nat, ent : TLB48_Entry) -> unit = + tlb48 = #\hyperref[sailRISCVzSome]{Some}#(ent) diff --git a/sail_latex_riscv/fnzwritecsr7af48520171f4dd0cd06c1b6876196a7.tex b/sail_latex_riscv/fnzwritecsr7af48520171f4dd0cd06c1b6876196a7.tex new file mode 100644 index 00000000..8e4766e5 --- /dev/null +++ b/sail_latex_riscv/fnzwritecsr7af48520171f4dd0cd06c1b6876196a7.tex @@ -0,0 +1,72 @@ +function #\hyperref[sailRISCVzwriteCSR]{writeCSR}# (csr : csreg, value : xlenbits) -> unit = { + let res : #\hyperref[sailRISCVzoption]{option}#(xlenbits) = + match (csr, sizeof(xlen)) { + /* machine mode */ + (0x300, _) => { mstatus = #\hyperref[sailRISCVzlegalizzezymstatus]{legalize\_mstatus}#(mstatus, value); #\hyperref[sailRISCVzSome]{Some}#(mstatus.#\hyperref[sailRISCVzbits]{bits}#()) }, + (0x301, _) => { misa = #\hyperref[sailRISCVzlegalizzezymisa]{legalize\_misa}#(misa, value); #\hyperref[sailRISCVzSome]{Some}#(misa.#\hyperref[sailRISCVzbits]{bits}#()) }, + (0x302, _) => { medeleg = #\hyperref[sailRISCVzlegalizzezymedeleg]{legalize\_medeleg}#(medeleg, value); #\hyperref[sailRISCVzSome]{Some}#(medeleg.#\hyperref[sailRISCVzbits]{bits}#()) }, + (0x303, _) => { mideleg = #\hyperref[sailRISCVzlegalizzezymideleg]{legalize\_mideleg}#(mideleg, value); #\hyperref[sailRISCVzSome]{Some}#(mideleg.#\hyperref[sailRISCVzbits]{bits}#()) }, + (0x304, _) => { mie = #\hyperref[sailRISCVzlegalizzezymie]{legalize\_mie}#(mie, value); #\hyperref[sailRISCVzSome]{Some}#(mie.#\hyperref[sailRISCVzbits]{bits}#()) }, + (0x305, _) => { #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzsetzymtvec]{set\_mtvec}#(value)) }, + (0x306, _) => { mcounteren = #\hyperref[sailRISCVzlegalizzezymcounteren]{legalize\_mcounteren}#(mcounteren, value); #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(mcounteren.#\hyperref[sailRISCVzbits]{bits}#())) }, + (0x320, _) => { mcountinhibit = #\hyperref[sailRISCVzlegalizzezymcountinhibit]{legalize\_mcountinhibit}#(mcountinhibit, value); #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(mcountinhibit.#\hyperref[sailRISCVzbits]{bits}#())) }, + (0x340, _) => { mscratch = value; #\hyperref[sailRISCVzSome]{Some}#(mscratch) }, + (0x341, _) => { #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzsetzyxretzytarget]{set\_xret\_target}#(Machine, value)) }, + (0x342, _) => { mcause->#\hyperref[sailRISCVzbits]{bits}#() = value; #\hyperref[sailRISCVzSome]{Some}#(mcause.#\hyperref[sailRISCVzbits]{bits}#()) }, + (0x343, _) => { mtval = value; #\hyperref[sailRISCVzSome]{Some}#(mtval) }, + (0x344, _) => { mip = #\hyperref[sailRISCVzlegalizzezymip]{legalize\_mip}#(mip, value); #\hyperref[sailRISCVzSome]{Some}#(mip.#\hyperref[sailRISCVzbits]{bits}#()) }, + + // Note: #\hyperref[sailRISCVzSome]{Some}#(value) returned below is not the legalized value due to locked entries + (0x3A0, _) => { #\hyperref[sailRISCVzpmpWriteCfgReg]{pmpWriteCfgReg}#(0, value); #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzpmpReadCfgReg]{pmpReadCfgReg}#(0)) }, // pmpcfg0 + (0x3A1, 32) => { #\hyperref[sailRISCVzpmpWriteCfgReg]{pmpWriteCfgReg}#(1, value); #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzpmpReadCfgReg]{pmpReadCfgReg}#(1)) }, // pmpcfg1 + (0x3A2, _) => { #\hyperref[sailRISCVzpmpWriteCfgReg]{pmpWriteCfgReg}#(2, value); #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzpmpReadCfgReg]{pmpReadCfgReg}#(2)) }, // pmpcfg2 + (0x3A3, 32) => { #\hyperref[sailRISCVzpmpWriteCfgReg]{pmpWriteCfgReg}#(3, value); #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzpmpReadCfgReg]{pmpReadCfgReg}#(3)) }, // pmpcfg3 + + (0x3B0, _) => { pmpaddr0 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp0cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp1cfg), pmpaddr0, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr0) }, + (0x3B1, _) => { pmpaddr1 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp1cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp2cfg), pmpaddr1, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr1) }, + (0x3B2, _) => { pmpaddr2 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp2cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp3cfg), pmpaddr2, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr2) }, + (0x3B3, _) => { pmpaddr3 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp3cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp4cfg), pmpaddr3, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr3) }, + (0x3B4, _) => { pmpaddr4 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp4cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp5cfg), pmpaddr4, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr4) }, + (0x3B5, _) => { pmpaddr5 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp5cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp6cfg), pmpaddr5, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr5) }, + (0x3B6, _) => { pmpaddr6 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp6cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp7cfg), pmpaddr6, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr6) }, + (0x3B7, _) => { pmpaddr7 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp7cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp8cfg), pmpaddr7, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr7) }, + (0x3B8, _) => { pmpaddr8 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp8cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp9cfg), pmpaddr8, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr8) }, + (0x3B9, _) => { pmpaddr9 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp9cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp10cfg), pmpaddr9, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr9) }, + (0x3BA, _) => { pmpaddr10 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp10cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp11cfg), pmpaddr10, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr10) }, + (0x3BB, _) => { pmpaddr11 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp11cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp12cfg), pmpaddr11, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr11) }, + (0x3BC, _) => { pmpaddr12 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp12cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp13cfg), pmpaddr12, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr12) }, + (0x3BD, _) => { pmpaddr13 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp13cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp14cfg), pmpaddr13, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr13) }, + (0x3BE, _) => { pmpaddr14 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp14cfg), #\hyperref[sailRISCVzpmpTORLocked]{pmpTORLocked}#(pmp15cfg), pmpaddr14, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr14) }, + (0x3BF, _) => { pmpaddr15 = #\hyperref[sailRISCVzpmpWriteAddr]{pmpWriteAddr}#(#\hyperref[sailRISCVzpmpLocked]{pmpLocked}#(pmp15cfg), false, pmpaddr15, value); #\hyperref[sailRISCVzSome]{Some}#(pmpaddr15) }, + + /* machine mode counters */ + (0xB00, _) => { mcycle[(sizeof(xlen) - 1) .. 0] = value; #\hyperref[sailRISCVzSome]{Some}#(value) }, + (0xB02, _) => { minstret[(sizeof(xlen) - 1) .. 0] = value; minstret_written = true; #\hyperref[sailRISCVzSome]{Some}#(value) }, + (0xB80, 32) => { mcycle[63 .. 32] = value; #\hyperref[sailRISCVzSome]{Some}#(value) }, + (0xB82, 32) => { minstret[63 .. 32] = value; minstret_written = true; #\hyperref[sailRISCVzSome]{Some}#(value) }, + + /* trigger/debug */ + (0x7a0, _) => { tselect = value; #\hyperref[sailRISCVzSome]{Some}#(tselect) }, + + /* supervisor mode */ + (0x100, _) => { mstatus = #\hyperref[sailRISCVzlegalizzezysstatus]{legalize\_sstatus}#(mstatus, value); #\hyperref[sailRISCVzSome]{Some}#(mstatus.#\hyperref[sailRISCVzbits]{bits}#()) }, + (0x102, _) => { sedeleg = #\hyperref[sailRISCVzlegalizzezysedeleg]{legalize\_sedeleg}#(sedeleg, value); #\hyperref[sailRISCVzSome]{Some}#(sedeleg.#\hyperref[sailRISCVzbits]{bits}#()) }, + (0x103, _) => { sideleg->#\hyperref[sailRISCVzbits]{bits}#() = value; #\hyperref[sailRISCVzSome]{Some}#(sideleg.#\hyperref[sailRISCVzbits]{bits}#()) }, /* TODO: does this need legalization? */ + (0x104, _) => { mie = #\hyperref[sailRISCVzlegalizzezysie]{legalize\_sie}#(mie, mideleg, value); #\hyperref[sailRISCVzSome]{Some}#(mie.#\hyperref[sailRISCVzbits]{bits}#()) }, + (0x105, _) => { #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzsetzystvec]{set\_stvec}#(value)) }, + (0x106, _) => { scounteren = #\hyperref[sailRISCVzlegalizzezyscounteren]{legalize\_scounteren}#(scounteren, value); #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzEXTZ]{EXTZ}#(scounteren.#\hyperref[sailRISCVzbits]{bits}#())) }, + (0x140, _) => { sscratch = value; #\hyperref[sailRISCVzSome]{Some}#(sscratch) }, + (0x141, _) => { #\hyperref[sailRISCVzSome]{Some}#(#\hyperref[sailRISCVzsetzyxretzytarget]{set\_xret\_target}#(Supervisor, value)) }, + (0x142, _) => { scause->#\hyperref[sailRISCVzbits]{bits}#() = value; #\hyperref[sailRISCVzSome]{Some}#(scause.#\hyperref[sailRISCVzbits]{bits}#()) }, + (0x143, _) => { stval = value; #\hyperref[sailRISCVzSome]{Some}#(stval) }, + (0x144, _) => { mip = #\hyperref[sailRISCVzlegalizzezysip]{legalize\_sip}#(mip, mideleg, value); #\hyperref[sailRISCVzSome]{Some}#(mip.#\hyperref[sailRISCVzbits]{bits}#()) }, + (0x180, _) => { satp = #\hyperref[sailRISCVzlegalizzezysatp]{legalize\_satp}#(#\hyperref[sailRISCVzcurzyArchitecture]{cur\_Architecture}#(), satp, value); #\hyperref[sailRISCVzSome]{Some}#(satp) }, + + _ => #\hyperref[sailRISCVzextzywritezyCSR]{ext\_write\_CSR}#(csr, value) + }; + match res { + #\hyperref[sailRISCVzSome]{Some}#(v) => if #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}#() + then #\hyperref[sailRISCVzprintzyreg]{print\_reg}#("CSR " ^ #\hyperref[sailRISCVztozystr]{to\_str}#(csr) ^ " <- " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(v) ^ " (input: " ^ #\hyperref[sailRISCVzBitStr]{BitStr}#(value) ^ ")"), + #\hyperref[sailRISCVzNone]{None}#() => #\hyperref[sailRISCVzprintzybits]{print\_bits}#("unhandled write to CSR ", csr) + } +} diff --git a/sail_latex_riscv/fnzwx0042b1ee0bdb45d47dcb45d5a9461882.tex b/sail_latex_riscv/fnzwx0042b1ee0bdb45d47dcb45d5a9461882.tex new file mode 100644 index 00000000..76d30a6d --- /dev/null +++ b/sail_latex_riscv/fnzwx0042b1ee0bdb45d47dcb45d5a9461882.tex @@ -0,0 +1,43 @@ +function #\hyperref[sailRISCVzwX]{wX}# (r, in_v) = { + let v = #\hyperref[sailRISCVzregvalzyintozyreg]{regval\_into\_reg}#(in_v); + match r { + 0 => (), + 1 => x1 = v, + 2 => x2 = v, + 3 => x3 = v, + 4 => x4 = v, + 5 => x5 = v, + 6 => x6 = v, + 7 => x7 = v, + 8 => x8 = v, + 9 => x9 = v, + 10 => x10 = v, + 11 => x11 = v, + 12 => x12 = v, + 13 => x13 = v, + 14 => x14 = v, + 15 => x15 = v, + 16 => x16 = v, + 17 => x17 = v, + 18 => x18 = v, + 19 => x19 = v, + 20 => x20 = v, + 21 => x21 = v, + 22 => x22 = v, + 23 => x23 = v, + 24 => x24 = v, + 25 => x25 = v, + 26 => x26 = v, + 27 => x27 = v, + 28 => x28 = v, + 29 => x29 = v, + 30 => x30 = v, + 31 => x31 = v, + _ => assert(false, "invalid register number") + }; + if (r != 0) then { + #\hyperref[sailRISCVzrvfizywX]{rvfi\_wX}#(r, in_v); + if #\hyperref[sailRISCVzgetzyconfigzyprintzyreg]{get\_config\_print\_reg}#() + then #\hyperref[sailRISCVzprintzyreg]{print\_reg}#("x" ^ #\hyperref[sailRISCVzstringzyofzyint]{string\_of\_int}#(r) ^ " <- " ^ #\hyperref[sailRISCVzRegStr]{RegStr}#(v)); + } +} diff --git a/sail_latex_riscv/fnzwx_bitseb6ef5be72b31b8cb0f1595602665261.tex b/sail_latex_riscv/fnzwx_bitseb6ef5be72b31b8cb0f1595602665261.tex new file mode 100644 index 00000000..ebae7a8d --- /dev/null +++ b/sail_latex_riscv/fnzwx_bitseb6ef5be72b31b8cb0f1595602665261.tex @@ -0,0 +1,3 @@ +function #\hyperref[sailRISCVzwXzybits]{wX\_bits}#(i: #\hyperref[sailRISCVzbits]{bits}#(5), data: xlenbits) -> unit = { + #\hyperref[sailRISCVzwX]{wX}#(#\hyperref[sailRISCVzunsigned]{unsigned}#(i)) = data +} diff --git a/sail_latex_riscv/fnzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex b/sail_latex_riscv/fnzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex new file mode 100644 index 00000000..5bb37631 --- /dev/null +++ b/sail_latex_riscv/fnzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex @@ -0,0 +1 @@ +function operator <#\hyperref[sailRISCVzzys]{\_s}# (x, y) = #\hyperref[sailRISCVzsigned]{signed}#(x) < #\hyperref[sailRISCVzsigned]{signed}#(y) diff --git a/sail_latex_riscv/fnzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex b/sail_latex_riscv/fnzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex new file mode 100644 index 00000000..9b02c07d --- /dev/null +++ b/sail_latex_riscv/fnzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex @@ -0,0 +1 @@ +function operator <#\hyperref[sailRISCVzzyu]{\_u}# (x, y) = #\hyperref[sailRISCVzunsigned]{unsigned}#(x) < #\hyperref[sailRISCVzunsigned]{unsigned}#(y) diff --git a/sail_latex_riscv/fnzz8operatorz0zizj_uz99c310fa9a514922f781c01ba7354f99f.tex b/sail_latex_riscv/fnzz8operatorz0zizj_uz99c310fa9a514922f781c01ba7354f99f.tex new file mode 100644 index 00000000..7b07e88a --- /dev/null +++ b/sail_latex_riscv/fnzz8operatorz0zizj_uz99c310fa9a514922f781c01ba7354f99f.tex @@ -0,0 +1 @@ +function operator <=#\hyperref[sailRISCVzzyu]{\_u}# (x, y) = #\hyperref[sailRISCVzunsigned]{unsigned}#(x) <= #\hyperref[sailRISCVzunsigned]{unsigned}#(y) diff --git a/sail_latex_riscv/fnzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex b/sail_latex_riscv/fnzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex new file mode 100644 index 00000000..6070b00d --- /dev/null +++ b/sail_latex_riscv/fnzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex @@ -0,0 +1 @@ +function operator >=#\hyperref[sailRISCVzzys]{\_s}# (x, y) = #\hyperref[sailRISCVzsigned]{signed}#(x) >= #\hyperref[sailRISCVzsigned]{signed}#(y) diff --git a/sail_latex_riscv/fnzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex b/sail_latex_riscv/fnzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex new file mode 100644 index 00000000..9bd71744 --- /dev/null +++ b/sail_latex_riscv/fnzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex @@ -0,0 +1 @@ +function operator >=#\hyperref[sailRISCVzzyu]{\_u}# (x, y) = #\hyperref[sailRISCVzunsigned]{unsigned}#(x) >= #\hyperref[sailRISCVzunsigned]{unsigned}#(y) diff --git a/sail_latex_riscv/fnzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex b/sail_latex_riscv/fnzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex new file mode 100644 index 00000000..96ac7417 --- /dev/null +++ b/sail_latex_riscv/fnzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex @@ -0,0 +1 @@ +function #\hyperref[sailRISCVzzzeroszyimplicit]{zeros\_implicit}# (n) = #\hyperref[sailRISCVzsailzyzzeros]{sail\_zeros}#(n) diff --git a/sail_latex_riscv/overloadAAAAAAAAAAAAAAAAAAzupdate_bits5a3f6688b4b8427544fc33354e84149f.tex b/sail_latex_riscv/overloadAAAAAAAAAAAAAAAAAAzupdate_bits5a3f6688b4b8427544fc33354e84149f.tex new file mode 100644 index 00000000..1d86bda0 --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAAAAAAAAAAAAAAzupdate_bits5a3f6688b4b8427544fc33354e84149f.tex @@ -0,0 +1 @@ +overload update_BITS = {_update_SV48_PTE_BITS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAAAAAAAAAAAAAAzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex b/sail_latex_riscv/overloadAAAAAAAAAAAAAAAAAzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex new file mode 100644 index 00000000..578de351 --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAAAAAAAAAAAAAzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex @@ -0,0 +1 @@ +overload update_PPNi = {_update_SV39_PTE_PPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAAAAAAAAAAAAAzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex b/sail_latex_riscv/overloadAAAAAAAAAAAAAAAAzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex new file mode 100644 index 00000000..d81ed09d --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAAAAAAAAAAAAzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex @@ -0,0 +1 @@ +overload update_PgOfs = {_update_SV32_Paddr_PgOfs} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAAAAAAAAAAAAz_mod_u960ee5decf6c18ea57af0e0387ef7d9c.tex b/sail_latex_riscv/overloadAAAAAAAAAAAAAAAz_mod_u960ee5decf6c18ea57af0e0387ef7d9c.tex new file mode 100644 index 00000000..8f3846c5 --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAAAAAAAAAAAz_mod_u960ee5decf6c18ea57af0e0387ef7d9c.tex @@ -0,0 +1 @@ +overload _mod_U = {_get_PTE_Bits_U, _set_PTE_Bits_U} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAAAAAAAAAAAz_mod_usif3c3aecb7417cc350ad372adfb40e4d3.tex b/sail_latex_riscv/overloadAAAAAAAAAAAAAAz_mod_usif3c3aecb7417cc350ad372adfb40e4d3.tex new file mode 100644 index 00000000..ed0ef9c1 --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAAAAAAAAAAz_mod_usif3c3aecb7417cc350ad372adfb40e4d3.tex @@ -0,0 +1 @@ +overload _mod_USI = {_get_Uinterrupts_USI, _set_Uinterrupts_USI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAAAAAAAAAAz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex b/sail_latex_riscv/overloadAAAAAAAAAAAAAz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex new file mode 100644 index 00000000..f7086907 --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAAAAAAAAAz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex @@ -0,0 +1 @@ +overload _mod_R = {_get_Pmpcfg_ent_R, _set_Pmpcfg_ent_R} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAAAAAAAAAz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadAAAAAAAAAAAAz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..53a0af78 --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAAAAAAAAz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Satp64_bits, _set_Satp64_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAAAAAAAAz_mod_load_access_fault185ee80ec13fa3fdeb7c2cd3a76688c9.tex b/sail_latex_riscv/overloadAAAAAAAAAAAz_mod_load_access_fault185ee80ec13fa3fdeb7c2cd3a76688c9.tex new file mode 100644 index 00000000..baf3c73b --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAAAAAAAz_mod_load_access_fault185ee80ec13fa3fdeb7c2cd3a76688c9.tex @@ -0,0 +1 @@ +overload _mod_Load_Access_Fault = {_get_Sedeleg_Load_Access_Fault, _set_Sedeleg_Load_Access_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAAAAAAAz_mod_mxr626efb0dadf77d402ea180eddd656377.tex b/sail_latex_riscv/overloadAAAAAAAAAAz_mod_mxr626efb0dadf77d402ea180eddd656377.tex new file mode 100644 index 00000000..5eff3025 --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAAAAAAz_mod_mxr626efb0dadf77d402ea180eddd656377.tex @@ -0,0 +1 @@ +overload _mod_MXR = {_get_Sstatus_MXR, _set_Sstatus_MXR} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAAAAAAz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadAAAAAAAAAz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..29e6b17b --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAAAAAz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Mcause_bits, _set_Mcause_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAAAAAz_mod_senvcall87d5357e73e0d0d061971d3b4ae4f615.tex b/sail_latex_riscv/overloadAAAAAAAAz_mod_senvcall87d5357e73e0d0d061971d3b4ae4f615.tex new file mode 100644 index 00000000..9a757fb0 --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAAAAz_mod_senvcall87d5357e73e0d0d061971d3b4ae4f615.tex @@ -0,0 +1 @@ +overload _mod_SEnvCall = {_get_Medeleg_SEnvCall, _set_Medeleg_SEnvCall} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAAAAz_mod_sei769b57e17c0057e7ca956b7721915a2e.tex b/sail_latex_riscv/overloadAAAAAAAz_mod_sei769b57e17c0057e7ca956b7721915a2e.tex new file mode 100644 index 00000000..799d44fd --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAAAz_mod_sei769b57e17c0057e7ca956b7721915a2e.tex @@ -0,0 +1 @@ +overload _mod_SEI = {_get_Minterrupts_SEI, _set_Minterrupts_SEI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAAAz_mod_mprv5b120c5e51154d4f8a5780bd0310aa4b.tex b/sail_latex_riscv/overloadAAAAAAz_mod_mprv5b120c5e51154d4f8a5780bd0310aa4b.tex new file mode 100644 index 00000000..8497b285 --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAAz_mod_mprv5b120c5e51154d4f8a5780bd0310aa4b.tex @@ -0,0 +1 @@ +overload _mod_MPRV = {_get_Mstatus_MPRV, _set_Mstatus_MPRV} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAAz_mod_fd77a6e62ab1cfa45a61b48a241cf22f2.tex b/sail_latex_riscv/overloadAAAAAz_mod_fd77a6e62ab1cfa45a61b48a241cf22f2.tex new file mode 100644 index 00000000..1e360679 --- /dev/null +++ b/sail_latex_riscv/overloadAAAAAz_mod_fd77a6e62ab1cfa45a61b48a241cf22f2.tex @@ -0,0 +1 @@ +overload _mod_F = {_get_Misa_F, _set_Misa_F} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAAz_mod_sd4c32983c0a4bd556ddaf553d2e450b6.tex b/sail_latex_riscv/overloadAAAAz_mod_sd4c32983c0a4bd556ddaf553d2e450b6.tex new file mode 100644 index 00000000..aa58a5db --- /dev/null +++ b/sail_latex_riscv/overloadAAAAz_mod_sd4c32983c0a4bd556ddaf553d2e450b6.tex @@ -0,0 +1 @@ +overload _mod_S = {_get_Misa_S, _set_Misa_S} \ No newline at end of file diff --git a/sail_latex_riscv/overloadAAAzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadAAAzto_str8b7a6895ae35945bd4740e9f790c43ee.tex new file mode 100644 index 00000000..e8eeca48 --- /dev/null +++ b/sail_latex_riscv/overloadAAAzto_str8b7a6895ae35945bd4740e9f790c43ee.tex @@ -0,0 +1 @@ +overload to_str = {privLevel_to_str} diff --git a/sail_latex_riscv/overloadAAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex b/sail_latex_riscv/overloadAAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex new file mode 100644 index 00000000..e121fc77 --- /dev/null +++ b/sail_latex_riscv/overloadAAzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex @@ -0,0 +1 @@ +overload vector_update = {bitvector_update, plain_vector_update} diff --git a/sail_latex_riscv/overloadBBBBBBBBBBBBBBBBBBz_mod_bits60455a5b4231baf7b82d860f6efc2682.tex b/sail_latex_riscv/overloadBBBBBBBBBBBBBBBBBBz_mod_bits60455a5b4231baf7b82d860f6efc2682.tex new file mode 100644 index 00000000..d23406ed --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBBBBBBBBBBBBBBz_mod_bits60455a5b4231baf7b82d860f6efc2682.tex @@ -0,0 +1 @@ +overload _mod_BITS = {_get_SV48_PTE_BITS, _set_SV48_PTE_BITS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBBBBBBBBBBBBBBBz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex b/sail_latex_riscv/overloadBBBBBBBBBBBBBBBBBz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex new file mode 100644 index 00000000..e648b3aa --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBBBBBBBBBBBBBz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex @@ -0,0 +1 @@ +overload _mod_PPNi = {_get_SV39_PTE_PPNi, _set_SV39_PTE_PPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBBBBBBBBBBBBBBz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex b/sail_latex_riscv/overloadBBBBBBBBBBBBBBBBz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex new file mode 100644 index 00000000..85b30e21 --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBBBBBBBBBBBBz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex @@ -0,0 +1 @@ +overload _mod_PgOfs = {_get_SV32_Paddr_PgOfs, _set_SV32_Paddr_PgOfs} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBBBBBBBBBBBBBzupdate_x647abdeca7ac108f059148e19df0452e.tex b/sail_latex_riscv/overloadBBBBBBBBBBBBBBBzupdate_x647abdeca7ac108f059148e19df0452e.tex new file mode 100644 index 00000000..0e9311ef --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBBBBBBBBBBBzupdate_x647abdeca7ac108f059148e19df0452e.tex @@ -0,0 +1 @@ +overload update_X = {_update_PTE_Bits_X} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBBBBBBBBBBBBzf71805d10b9ea2a56437652aba0daf9bf.tex b/sail_latex_riscv/overloadBBBBBBBBBBBBBBzf71805d10b9ea2a56437652aba0daf9bf.tex new file mode 100644 index 00000000..2db84e80 --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBBBBBBBBBBzf71805d10b9ea2a56437652aba0daf9bf.tex @@ -0,0 +1 @@ +overload F = {rF_bits, wF_bits, rF, wF} diff --git a/sail_latex_riscv/overloadBBBBBBBBBBBBBzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadBBBBBBBBBBBBBzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..5e3163ec --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBBBBBBBBBzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_ccsr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBBBBBBBBBBzupdate_modea8b179bc2887fad34e9a3f8cefc9cf29.tex b/sail_latex_riscv/overloadBBBBBBBBBBBBzupdate_modea8b179bc2887fad34e9a3f8cefc9cf29.tex new file mode 100644 index 00000000..9661ad5b --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBBBBBBBBzupdate_modea8b179bc2887fad34e9a3f8cefc9cf29.tex @@ -0,0 +1 @@ +overload update_Mode = {_update_Satp64_Mode} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBBBBBBBBBzupdate_load_addr_aligna304d90cb1ef10e79624a3324854bad0.tex b/sail_latex_riscv/overloadBBBBBBBBBBBzupdate_load_addr_aligna304d90cb1ef10e79624a3324854bad0.tex new file mode 100644 index 00000000..2dfccaa9 --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBBBBBBBzupdate_load_addr_aligna304d90cb1ef10e79624a3324854bad0.tex @@ -0,0 +1 @@ +overload update_Load_Addr_Align = {_update_Sedeleg_Load_Addr_Align} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBBBBBBBBzupdate_sum45aaa4f77ddaa1e976bb9719406d8d4d.tex b/sail_latex_riscv/overloadBBBBBBBBBBzupdate_sum45aaa4f77ddaa1e976bb9719406d8d4d.tex new file mode 100644 index 00000000..f1929027 --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBBBBBBzupdate_sum45aaa4f77ddaa1e976bb9719406d8d4d.tex @@ -0,0 +1 @@ +overload update_SUM = {_update_Sstatus_SUM} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBBBBBBBzupdate_isinterrupt7cba1e6a14631a642becc8e33e0de341.tex b/sail_latex_riscv/overloadBBBBBBBBBzupdate_isinterrupt7cba1e6a14631a642becc8e33e0de341.tex new file mode 100644 index 00000000..e843578e --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBBBBBzupdate_isinterrupt7cba1e6a14631a642becc8e33e0de341.tex @@ -0,0 +1 @@ +overload update_IsInterrupt = {_update_Mcause_IsInterrupt} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBBBBBBzupdate_uenvcall1a8e9c082fb9f272d5370bee121f426d.tex b/sail_latex_riscv/overloadBBBBBBBBzupdate_uenvcall1a8e9c082fb9f272d5370bee121f426d.tex new file mode 100644 index 00000000..03c01ffb --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBBBBzupdate_uenvcall1a8e9c082fb9f272d5370bee121f426d.tex @@ -0,0 +1 @@ +overload update_UEnvCall = {_update_Medeleg_UEnvCall} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBBBBBzupdate_uei8252f0ae84161aa560a37211f39d1461.tex b/sail_latex_riscv/overloadBBBBBBBzupdate_uei8252f0ae84161aa560a37211f39d1461.tex new file mode 100644 index 00000000..4cb48dbe --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBBBzupdate_uei8252f0ae84161aa560a37211f39d1461.tex @@ -0,0 +1 @@ +overload update_UEI = {_update_Minterrupts_UEI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBBBBzupdate_xsd577805c39539bb2ca85cd57d24ab51e.tex b/sail_latex_riscv/overloadBBBBBBzupdate_xsd577805c39539bb2ca85cd57d24ab51e.tex new file mode 100644 index 00000000..ab878835 --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBBzupdate_xsd577805c39539bb2ca85cd57d24ab51e.tex @@ -0,0 +1 @@ +overload update_XS = {_update_Mstatus_XS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBBBzupdate_e5b6e9655311268e198c390cdf59ecba9.tex b/sail_latex_riscv/overloadBBBBBzupdate_e5b6e9655311268e198c390cdf59ecba9.tex new file mode 100644 index 00000000..0b744466 --- /dev/null +++ b/sail_latex_riscv/overloadBBBBBzupdate_e5b6e9655311268e198c390cdf59ecba9.tex @@ -0,0 +1 @@ +overload update_E = {_update_Misa_E} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBBzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex b/sail_latex_riscv/overloadBBBBzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex new file mode 100644 index 00000000..b929cef0 --- /dev/null +++ b/sail_latex_riscv/overloadBBBBzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex @@ -0,0 +1 @@ +overload update_R = {_update_Misa_R} \ No newline at end of file diff --git a/sail_latex_riscv/overloadBBBzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadBBBzto_str8b7a6895ae35945bd4740e9f790c43ee.tex new file mode 100644 index 00000000..211ab355 --- /dev/null +++ b/sail_latex_riscv/overloadBBBzto_str8b7a6895ae35945bd4740e9f790c43ee.tex @@ -0,0 +1 @@ +overload to_str = {exceptionType_to_str} diff --git a/sail_latex_riscv/overloadBBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex b/sail_latex_riscv/overloadBBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex new file mode 100644 index 00000000..2ffe7431 --- /dev/null +++ b/sail_latex_riscv/overloadBBzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex @@ -0,0 +1 @@ +overload operator + = {add_bits, add_bits_int} diff --git a/sail_latex_riscv/overloadBzabs_intef5fbb521189282054dc80dc7173013d.tex b/sail_latex_riscv/overloadBzabs_intef5fbb521189282054dc80dc7173013d.tex new file mode 100644 index 00000000..047f6d0c --- /dev/null +++ b/sail_latex_riscv/overloadBzabs_intef5fbb521189282054dc80dc7173013d.tex @@ -0,0 +1 @@ +overload abs_int = {abs_int_atom} diff --git a/sail_latex_riscv/overloadCCCCCCCCCCCCCCCCCCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadCCCCCCCCCCCCCCCCCCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex new file mode 100644 index 00000000..c1857eab --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCCCCCCCCCCCCCCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex @@ -0,0 +1 @@ +overload to_str = {print_insn} diff --git a/sail_latex_riscv/overloadCCCCCCCCCCCCCCCCCzupdate_rsw7e773e2fdd93d70f9490f8401b97d4e9.tex b/sail_latex_riscv/overloadCCCCCCCCCCCCCCCCCzupdate_rsw7e773e2fdd93d70f9490f8401b97d4e9.tex new file mode 100644 index 00000000..2cfd4ae1 --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCCCCCCCCCCCCCzupdate_rsw7e773e2fdd93d70f9490f8401b97d4e9.tex @@ -0,0 +1 @@ +overload update_RSW = {_update_SV39_PTE_RSW} \ No newline at end of file diff --git a/sail_latex_riscv/overloadCCCCCCCCCCCCCCCCzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadCCCCCCCCCCCCCCCCzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..9e490e41 --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCCCCCCCCCCCCzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_SV32_PTE_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadCCCCCCCCCCCCCCCz_mod_xc906d7554de3b79cd0cc78501a562587.tex b/sail_latex_riscv/overloadCCCCCCCCCCCCCCCz_mod_xc906d7554de3b79cd0cc78501a562587.tex new file mode 100644 index 00000000..41c41c0f --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCCCCCCCCCCCz_mod_xc906d7554de3b79cd0cc78501a562587.tex @@ -0,0 +1 @@ +overload _mod_X = {_get_PTE_Bits_X, _set_PTE_Bits_X} \ No newline at end of file diff --git a/sail_latex_riscv/overloadCCCCCCCCCCCCCCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadCCCCCCCCCCCCCCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex new file mode 100644 index 00000000..9b6a139d --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCCCCCCCCCCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex @@ -0,0 +1 @@ +overload to_str = {freg_name_abi} diff --git a/sail_latex_riscv/overloadCCCCCCCCCCCCCz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadCCCCCCCCCCCCCz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..0778373e --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCCCCCCCCCz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_ccsr_bits, _set_ccsr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadCCCCCCCCCCCCz_mod_mode7dda808a114a5634018c73fc24f43140.tex b/sail_latex_riscv/overloadCCCCCCCCCCCCz_mod_mode7dda808a114a5634018c73fc24f43140.tex new file mode 100644 index 00000000..26d60c5b --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCCCCCCCCz_mod_mode7dda808a114a5634018c73fc24f43140.tex @@ -0,0 +1 @@ +overload _mod_Mode = {_get_Satp64_Mode, _set_Satp64_Mode} \ No newline at end of file diff --git a/sail_latex_riscv/overloadCCCCCCCCCCCz_mod_load_addr_align34e982fd800fd67969b64a5932439781.tex b/sail_latex_riscv/overloadCCCCCCCCCCCz_mod_load_addr_align34e982fd800fd67969b64a5932439781.tex new file mode 100644 index 00000000..89bbd995 --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCCCCCCCz_mod_load_addr_align34e982fd800fd67969b64a5932439781.tex @@ -0,0 +1 @@ +overload _mod_Load_Addr_Align = {_get_Sedeleg_Load_Addr_Align, _set_Sedeleg_Load_Addr_Align} \ No newline at end of file diff --git a/sail_latex_riscv/overloadCCCCCCCCCCz_mod_sum9c28eec9a0977f334c917bffeb75d7eb.tex b/sail_latex_riscv/overloadCCCCCCCCCCz_mod_sum9c28eec9a0977f334c917bffeb75d7eb.tex new file mode 100644 index 00000000..2aa17c9d --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCCCCCCz_mod_sum9c28eec9a0977f334c917bffeb75d7eb.tex @@ -0,0 +1 @@ +overload _mod_SUM = {_get_Sstatus_SUM, _set_Sstatus_SUM} \ No newline at end of file diff --git a/sail_latex_riscv/overloadCCCCCCCCCz_mod_isinterrupt2bb38c1a3ef90daa70a3b0957628b7d4.tex b/sail_latex_riscv/overloadCCCCCCCCCz_mod_isinterrupt2bb38c1a3ef90daa70a3b0957628b7d4.tex new file mode 100644 index 00000000..827580b5 --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCCCCCz_mod_isinterrupt2bb38c1a3ef90daa70a3b0957628b7d4.tex @@ -0,0 +1 @@ +overload _mod_IsInterrupt = {_get_Mcause_IsInterrupt, _set_Mcause_IsInterrupt} \ No newline at end of file diff --git a/sail_latex_riscv/overloadCCCCCCCCz_mod_uenvcall837e3a85bd98d15f2f4b32f9230ddef6.tex b/sail_latex_riscv/overloadCCCCCCCCz_mod_uenvcall837e3a85bd98d15f2f4b32f9230ddef6.tex new file mode 100644 index 00000000..0726277f --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCCCCz_mod_uenvcall837e3a85bd98d15f2f4b32f9230ddef6.tex @@ -0,0 +1 @@ +overload _mod_UEnvCall = {_get_Medeleg_UEnvCall, _set_Medeleg_UEnvCall} \ No newline at end of file diff --git a/sail_latex_riscv/overloadCCCCCCCz_mod_uei7faef47ef8aacd0d1b2ad1e0530fdf8e.tex b/sail_latex_riscv/overloadCCCCCCCz_mod_uei7faef47ef8aacd0d1b2ad1e0530fdf8e.tex new file mode 100644 index 00000000..5b761612 --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCCCz_mod_uei7faef47ef8aacd0d1b2ad1e0530fdf8e.tex @@ -0,0 +1 @@ +overload _mod_UEI = {_get_Minterrupts_UEI, _set_Minterrupts_UEI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadCCCCCCz_mod_xs4cdc96063571eef4b6f09a5174c4405f.tex b/sail_latex_riscv/overloadCCCCCCz_mod_xs4cdc96063571eef4b6f09a5174c4405f.tex new file mode 100644 index 00000000..f85e215b --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCCz_mod_xs4cdc96063571eef4b6f09a5174c4405f.tex @@ -0,0 +1 @@ +overload _mod_XS = {_get_Mstatus_XS, _set_Mstatus_XS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadCCCCCz_mod_e788189af4a7082aacc7ac54449a1c6f5.tex b/sail_latex_riscv/overloadCCCCCz_mod_e788189af4a7082aacc7ac54449a1c6f5.tex new file mode 100644 index 00000000..056f734b --- /dev/null +++ b/sail_latex_riscv/overloadCCCCCz_mod_e788189af4a7082aacc7ac54449a1c6f5.tex @@ -0,0 +1 @@ +overload _mod_E = {_get_Misa_E, _set_Misa_E} \ No newline at end of file diff --git a/sail_latex_riscv/overloadCCCCz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex b/sail_latex_riscv/overloadCCCCz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex new file mode 100644 index 00000000..dc30d0c8 --- /dev/null +++ b/sail_latex_riscv/overloadCCCCz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex @@ -0,0 +1 @@ +overload _mod_R = {_get_Misa_R, _set_Misa_R} \ No newline at end of file diff --git a/sail_latex_riscv/overloadCCCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadCCCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex new file mode 100644 index 00000000..f4d341e4 --- /dev/null +++ b/sail_latex_riscv/overloadCCCzto_str8b7a6895ae35945bd4740e9f790c43ee.tex @@ -0,0 +1 @@ +overload to_str = {csr_name} diff --git a/sail_latex_riscv/overloadCCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex b/sail_latex_riscv/overloadCCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex new file mode 100644 index 00000000..cf01736a --- /dev/null +++ b/sail_latex_riscv/overloadCCzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex @@ -0,0 +1 @@ +overload operator & = {and_vec} diff --git a/sail_latex_riscv/overloadCzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_riscv/overloadCzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex new file mode 100644 index 00000000..751094be --- /dev/null +++ b/sail_latex_riscv/overloadCzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex @@ -0,0 +1 @@ +overload operator == = {eq_int, eq_bit, eq_bool, eq_unit} diff --git a/sail_latex_riscv/overloadDDDDDDDDDDDDDDDDDz_mod_rswf4989a734cfde890cb5a1c8d3b4e6798.tex b/sail_latex_riscv/overloadDDDDDDDDDDDDDDDDDz_mod_rswf4989a734cfde890cb5a1c8d3b4e6798.tex new file mode 100644 index 00000000..952422c4 --- /dev/null +++ b/sail_latex_riscv/overloadDDDDDDDDDDDDDDDDDz_mod_rswf4989a734cfde890cb5a1c8d3b4e6798.tex @@ -0,0 +1 @@ +overload _mod_RSW = {_get_SV39_PTE_RSW, _set_SV39_PTE_RSW} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDDDDDDDDDDDDDDz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadDDDDDDDDDDDDDDDDz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..db439773 --- /dev/null +++ b/sail_latex_riscv/overloadDDDDDDDDDDDDDDDDz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_SV32_PTE_bits, _set_SV32_PTE_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDDDDDDDDDDDDDzupdate_w3209efc3cdd41bbc0810494fad257f06.tex b/sail_latex_riscv/overloadDDDDDDDDDDDDDDDzupdate_w3209efc3cdd41bbc0810494fad257f06.tex new file mode 100644 index 00000000..aa855842 --- /dev/null +++ b/sail_latex_riscv/overloadDDDDDDDDDDDDDDDzupdate_w3209efc3cdd41bbc0810494fad257f06.tex @@ -0,0 +1 @@ +overload update_W = {_update_PTE_Bits_W} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDDDDDDDDDDDDzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadDDDDDDDDDDDDDDzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..f5abffe8 --- /dev/null +++ b/sail_latex_riscv/overloadDDDDDDDDDDDDDDzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Fcsr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDDDDDDDDDDDzupdate_cap_idxe77ade3df0db97f2d0c7e159a697bce8.tex b/sail_latex_riscv/overloadDDDDDDDDDDDDDzupdate_cap_idxe77ade3df0db97f2d0c7e159a697bce8.tex new file mode 100644 index 00000000..161e7314 --- /dev/null +++ b/sail_latex_riscv/overloadDDDDDDDDDDDDDzupdate_cap_idxe77ade3df0db97f2d0c7e159a697bce8.tex @@ -0,0 +1 @@ +overload update_cap_idx = {_update_ccsr_cap_idx} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDDDDDDDDDDzupdate_asid5cc334067dcbe9c9a4eb59266b7b5404.tex b/sail_latex_riscv/overloadDDDDDDDDDDDDzupdate_asid5cc334067dcbe9c9a4eb59266b7b5404.tex new file mode 100644 index 00000000..1a5d16a2 --- /dev/null +++ b/sail_latex_riscv/overloadDDDDDDDDDDDDzupdate_asid5cc334067dcbe9c9a4eb59266b7b5404.tex @@ -0,0 +1 @@ +overload update_Asid = {_update_Satp64_Asid} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDDDDDDDDDzupdate_breakpoint560b5628b33be91263dd76c1c88c6a06.tex b/sail_latex_riscv/overloadDDDDDDDDDDDzupdate_breakpoint560b5628b33be91263dd76c1c88c6a06.tex new file mode 100644 index 00000000..c64b70d9 --- /dev/null +++ b/sail_latex_riscv/overloadDDDDDDDDDDDzupdate_breakpoint560b5628b33be91263dd76c1c88c6a06.tex @@ -0,0 +1 @@ +overload update_Breakpoint = {_update_Sedeleg_Breakpoint} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDDDDDDDDzupdate_xsd577805c39539bb2ca85cd57d24ab51e.tex b/sail_latex_riscv/overloadDDDDDDDDDDzupdate_xsd577805c39539bb2ca85cd57d24ab51e.tex new file mode 100644 index 00000000..ff2cab01 --- /dev/null +++ b/sail_latex_riscv/overloadDDDDDDDDDDzupdate_xsd577805c39539bb2ca85cd57d24ab51e.tex @@ -0,0 +1 @@ +overload update_XS = {_update_Sstatus_XS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDDDDDDDzupdate_cause0e0260fdee4fbd12d08cac973b1bc938.tex b/sail_latex_riscv/overloadDDDDDDDDDzupdate_cause0e0260fdee4fbd12d08cac973b1bc938.tex new file mode 100644 index 00000000..bde5704a --- /dev/null +++ b/sail_latex_riscv/overloadDDDDDDDDDzupdate_cause0e0260fdee4fbd12d08cac973b1bc938.tex @@ -0,0 +1 @@ +overload update_Cause = {_update_Mcause_Cause} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDDDDDDzupdate_samo_access_faulte622f01b5ab60ce658092d165d64a4f9.tex b/sail_latex_riscv/overloadDDDDDDDDzupdate_samo_access_faulte622f01b5ab60ce658092d165d64a4f9.tex new file mode 100644 index 00000000..c5449651 --- /dev/null +++ b/sail_latex_riscv/overloadDDDDDDDDzupdate_samo_access_faulte622f01b5ab60ce658092d165d64a4f9.tex @@ -0,0 +1 @@ +overload update_SAMO_Access_Fault = {_update_Medeleg_SAMO_Access_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDDDDDzupdate_mtie9a0e80e380d13919203a8a6c5c07d8d.tex b/sail_latex_riscv/overloadDDDDDDDzupdate_mtie9a0e80e380d13919203a8a6c5c07d8d.tex new file mode 100644 index 00000000..b442659b --- /dev/null +++ b/sail_latex_riscv/overloadDDDDDDDzupdate_mtie9a0e80e380d13919203a8a6c5c07d8d.tex @@ -0,0 +1 @@ +overload update_MTI = {_update_Minterrupts_MTI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDDDDzupdate_fs64e6ca4d39ea47b95fa1da5e3e2e0921.tex b/sail_latex_riscv/overloadDDDDDDzupdate_fs64e6ca4d39ea47b95fa1da5e3e2e0921.tex new file mode 100644 index 00000000..5b5d60dc --- /dev/null +++ b/sail_latex_riscv/overloadDDDDDDzupdate_fs64e6ca4d39ea47b95fa1da5e3e2e0921.tex @@ -0,0 +1 @@ +overload update_FS = {_update_Mstatus_FS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDDDzupdate_da9201c8a6710e680d16238f3581a0227.tex b/sail_latex_riscv/overloadDDDDDzupdate_da9201c8a6710e680d16238f3581a0227.tex new file mode 100644 index 00000000..07e9da7f --- /dev/null +++ b/sail_latex_riscv/overloadDDDDDzupdate_da9201c8a6710e680d16238f3581a0227.tex @@ -0,0 +1 @@ +overload update_D = {_update_Misa_D} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDDzupdate_q789d0c6855d20e12d058ed6a4170014d.tex b/sail_latex_riscv/overloadDDDDzupdate_q789d0c6855d20e12d058ed6a4170014d.tex new file mode 100644 index 00000000..789901ed --- /dev/null +++ b/sail_latex_riscv/overloadDDDDzupdate_q789d0c6855d20e12d058ed6a4170014d.tex @@ -0,0 +1 @@ +overload update_Q = {_update_Misa_Q} \ No newline at end of file diff --git a/sail_latex_riscv/overloadDDDzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadDDDzto_str8b7a6895ae35945bd4740e9f790c43ee.tex new file mode 100644 index 00000000..1a53e27c --- /dev/null +++ b/sail_latex_riscv/overloadDDDzto_str8b7a6895ae35945bd4740e9f790c43ee.tex @@ -0,0 +1 @@ +overload to_str = {scr_name} diff --git a/sail_latex_riscv/overloadDDzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex b/sail_latex_riscv/overloadDDzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex new file mode 100644 index 00000000..0bb9bf01 --- /dev/null +++ b/sail_latex_riscv/overloadDDzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex @@ -0,0 +1 @@ +overload operator | = {or_vec} diff --git a/sail_latex_riscv/overloadDzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex b/sail_latex_riscv/overloadDzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex new file mode 100644 index 00000000..8be31818 --- /dev/null +++ b/sail_latex_riscv/overloadDzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex @@ -0,0 +1 @@ +overload operator != = {neq_int, neq_bool} diff --git a/sail_latex_riscv/overloadEEEEEEEEEEEEEEEEEzupdate_bits5a3f6688b4b8427544fc33354e84149f.tex b/sail_latex_riscv/overloadEEEEEEEEEEEEEEEEEzupdate_bits5a3f6688b4b8427544fc33354e84149f.tex new file mode 100644 index 00000000..7695a1ee --- /dev/null +++ b/sail_latex_riscv/overloadEEEEEEEEEEEEEEEEEzupdate_bits5a3f6688b4b8427544fc33354e84149f.tex @@ -0,0 +1 @@ +overload update_BITS = {_update_SV39_PTE_BITS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEEEEEEEEEEEEEEzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex b/sail_latex_riscv/overloadEEEEEEEEEEEEEEEEzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex new file mode 100644 index 00000000..64256c37 --- /dev/null +++ b/sail_latex_riscv/overloadEEEEEEEEEEEEEEEEzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex @@ -0,0 +1 @@ +overload update_PPNi = {_update_SV32_PTE_PPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEEEEEEEEEEEEEz_mod_w196183ee717bdd84cd7d5e4b2af0b219.tex b/sail_latex_riscv/overloadEEEEEEEEEEEEEEEz_mod_w196183ee717bdd84cd7d5e4b2af0b219.tex new file mode 100644 index 00000000..fc63b623 --- /dev/null +++ b/sail_latex_riscv/overloadEEEEEEEEEEEEEEEz_mod_w196183ee717bdd84cd7d5e4b2af0b219.tex @@ -0,0 +1 @@ +overload _mod_W = {_get_PTE_Bits_W, _set_PTE_Bits_W} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEEEEEEEEEEEEz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadEEEEEEEEEEEEEEz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..5299e856 --- /dev/null +++ b/sail_latex_riscv/overloadEEEEEEEEEEEEEEz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Fcsr_bits, _set_Fcsr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEEEEEEEEEEEz_mod_cap_idx2aa9e57d92bb9ee2c5c8636b1e91e4b8.tex b/sail_latex_riscv/overloadEEEEEEEEEEEEEz_mod_cap_idx2aa9e57d92bb9ee2c5c8636b1e91e4b8.tex new file mode 100644 index 00000000..b2c2169e --- /dev/null +++ b/sail_latex_riscv/overloadEEEEEEEEEEEEEz_mod_cap_idx2aa9e57d92bb9ee2c5c8636b1e91e4b8.tex @@ -0,0 +1 @@ +overload _mod_cap_idx = {_get_ccsr_cap_idx, _set_ccsr_cap_idx} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEEEEEEEEEEz_mod_asid55036e3f51de771bc07215ff1caec750.tex b/sail_latex_riscv/overloadEEEEEEEEEEEEz_mod_asid55036e3f51de771bc07215ff1caec750.tex new file mode 100644 index 00000000..7f9816b3 --- /dev/null +++ b/sail_latex_riscv/overloadEEEEEEEEEEEEz_mod_asid55036e3f51de771bc07215ff1caec750.tex @@ -0,0 +1 @@ +overload _mod_Asid = {_get_Satp64_Asid, _set_Satp64_Asid} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEEEEEEEEEz_mod_breakpointfb455863fb6768bbcbc1b984dbef6360.tex b/sail_latex_riscv/overloadEEEEEEEEEEEz_mod_breakpointfb455863fb6768bbcbc1b984dbef6360.tex new file mode 100644 index 00000000..a9d3620c --- /dev/null +++ b/sail_latex_riscv/overloadEEEEEEEEEEEz_mod_breakpointfb455863fb6768bbcbc1b984dbef6360.tex @@ -0,0 +1 @@ +overload _mod_Breakpoint = {_get_Sedeleg_Breakpoint, _set_Sedeleg_Breakpoint} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEEEEEEEEz_mod_xs4cdc96063571eef4b6f09a5174c4405f.tex b/sail_latex_riscv/overloadEEEEEEEEEEz_mod_xs4cdc96063571eef4b6f09a5174c4405f.tex new file mode 100644 index 00000000..976b19d6 --- /dev/null +++ b/sail_latex_riscv/overloadEEEEEEEEEEz_mod_xs4cdc96063571eef4b6f09a5174c4405f.tex @@ -0,0 +1 @@ +overload _mod_XS = {_get_Sstatus_XS, _set_Sstatus_XS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEEEEEEEz_mod_cause6fb7970fc86ee1af49227b574ab5c281.tex b/sail_latex_riscv/overloadEEEEEEEEEz_mod_cause6fb7970fc86ee1af49227b574ab5c281.tex new file mode 100644 index 00000000..63739ac1 --- /dev/null +++ b/sail_latex_riscv/overloadEEEEEEEEEz_mod_cause6fb7970fc86ee1af49227b574ab5c281.tex @@ -0,0 +1 @@ +overload _mod_Cause = {_get_Mcause_Cause, _set_Mcause_Cause} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEEEEEEz_mod_samo_access_faultef1cf7b1db2bf21d4e773b1a41ea8eea.tex b/sail_latex_riscv/overloadEEEEEEEEz_mod_samo_access_faultef1cf7b1db2bf21d4e773b1a41ea8eea.tex new file mode 100644 index 00000000..e93fa30a --- /dev/null +++ b/sail_latex_riscv/overloadEEEEEEEEz_mod_samo_access_faultef1cf7b1db2bf21d4e773b1a41ea8eea.tex @@ -0,0 +1 @@ +overload _mod_SAMO_Access_Fault = {_get_Medeleg_SAMO_Access_Fault, _set_Medeleg_SAMO_Access_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEEEEEz_mod_mti2df88e254ec8ac5958e47465bf888c25.tex b/sail_latex_riscv/overloadEEEEEEEz_mod_mti2df88e254ec8ac5958e47465bf888c25.tex new file mode 100644 index 00000000..e3d638f5 --- /dev/null +++ b/sail_latex_riscv/overloadEEEEEEEz_mod_mti2df88e254ec8ac5958e47465bf888c25.tex @@ -0,0 +1 @@ +overload _mod_MTI = {_get_Minterrupts_MTI, _set_Minterrupts_MTI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEEEEz_mod_fs91fd3eaccea19c4e4e7d0eef23a6ae9a.tex b/sail_latex_riscv/overloadEEEEEEz_mod_fs91fd3eaccea19c4e4e7d0eef23a6ae9a.tex new file mode 100644 index 00000000..9f97d2c6 --- /dev/null +++ b/sail_latex_riscv/overloadEEEEEEz_mod_fs91fd3eaccea19c4e4e7d0eef23a6ae9a.tex @@ -0,0 +1 @@ +overload _mod_FS = {_get_Mstatus_FS, _set_Mstatus_FS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEEEz_mod_d8c29507d9735e49d608a373bd2e2c599.tex b/sail_latex_riscv/overloadEEEEEz_mod_d8c29507d9735e49d608a373bd2e2c599.tex new file mode 100644 index 00000000..ab90905c --- /dev/null +++ b/sail_latex_riscv/overloadEEEEEz_mod_d8c29507d9735e49d608a373bd2e2c599.tex @@ -0,0 +1 @@ +overload _mod_D = {_get_Misa_D, _set_Misa_D} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEEz_mod_qba4e572e9225df8e5fc28e66a1a59f8b.tex b/sail_latex_riscv/overloadEEEEz_mod_qba4e572e9225df8e5fc28e66a1a59f8b.tex new file mode 100644 index 00000000..900d14b4 --- /dev/null +++ b/sail_latex_riscv/overloadEEEEz_mod_qba4e572e9225df8e5fc28e66a1a59f8b.tex @@ -0,0 +1 @@ +overload _mod_Q = {_get_Misa_Q, _set_Misa_Q} \ No newline at end of file diff --git a/sail_latex_riscv/overloadEEEzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadEEEzto_str8b7a6895ae35945bd4740e9f790c43ee.tex new file mode 100644 index 00000000..1a14905b --- /dev/null +++ b/sail_latex_riscv/overloadEEEzto_str8b7a6895ae35945bd4740e9f790c43ee.tex @@ -0,0 +1 @@ +overload to_str = {accessType_to_str} diff --git a/sail_latex_riscv/overloadEEzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex b/sail_latex_riscv/overloadEEzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex new file mode 100644 index 00000000..30bebb96 --- /dev/null +++ b/sail_latex_riscv/overloadEEzvector_subrange270c799ffa6c20b5244f22c64fba0367.tex @@ -0,0 +1 @@ +overload vector_subrange = {subrange_bits} diff --git a/sail_latex_riscv/overloadEzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex b/sail_latex_riscv/overloadEzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex new file mode 100644 index 00000000..acd09503 --- /dev/null +++ b/sail_latex_riscv/overloadEzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex @@ -0,0 +1 @@ +overload operator | = {or_bool} diff --git a/sail_latex_riscv/overloadFFFFFFFFFFFFFFFFFz_mod_bits60455a5b4231baf7b82d860f6efc2682.tex b/sail_latex_riscv/overloadFFFFFFFFFFFFFFFFFz_mod_bits60455a5b4231baf7b82d860f6efc2682.tex new file mode 100644 index 00000000..bed710a7 --- /dev/null +++ b/sail_latex_riscv/overloadFFFFFFFFFFFFFFFFFz_mod_bits60455a5b4231baf7b82d860f6efc2682.tex @@ -0,0 +1 @@ +overload _mod_BITS = {_get_SV39_PTE_BITS, _set_SV39_PTE_BITS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFFFFFFFFFFFFFFz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex b/sail_latex_riscv/overloadFFFFFFFFFFFFFFFFz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex new file mode 100644 index 00000000..0adc87a4 --- /dev/null +++ b/sail_latex_riscv/overloadFFFFFFFFFFFFFFFFz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex @@ -0,0 +1 @@ +overload _mod_PPNi = {_get_SV32_PTE_PPNi, _set_SV32_PTE_PPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFFFFFFFFFFFFFzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex b/sail_latex_riscv/overloadFFFFFFFFFFFFFFFzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex new file mode 100644 index 00000000..ac7fbcf3 --- /dev/null +++ b/sail_latex_riscv/overloadFFFFFFFFFFFFFFFzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex @@ -0,0 +1 @@ +overload update_R = {_update_PTE_Bits_R} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFFFFFFFFFFFFzupdate_frm523f62f4860983773adf9a52ee1eea5c.tex b/sail_latex_riscv/overloadFFFFFFFFFFFFFFzupdate_frm523f62f4860983773adf9a52ee1eea5c.tex new file mode 100644 index 00000000..887b46bd --- /dev/null +++ b/sail_latex_riscv/overloadFFFFFFFFFFFFFFzupdate_frm523f62f4860983773adf9a52ee1eea5c.tex @@ -0,0 +1 @@ +overload update_FRM = {_update_Fcsr_FRM} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFFFFFFFFFFFzupdate_cause68e022ebb6a1524860ca61573bc7f0b3.tex b/sail_latex_riscv/overloadFFFFFFFFFFFFFzupdate_cause68e022ebb6a1524860ca61573bc7f0b3.tex new file mode 100644 index 00000000..90d79b2a --- /dev/null +++ b/sail_latex_riscv/overloadFFFFFFFFFFFFFzupdate_cause68e022ebb6a1524860ca61573bc7f0b3.tex @@ -0,0 +1 @@ +overload update_cause = {_update_ccsr_cause} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFFFFFFFFFFzupdate_ppn97bb9a526eb6125397ee215b375879df.tex b/sail_latex_riscv/overloadFFFFFFFFFFFFzupdate_ppn97bb9a526eb6125397ee215b375879df.tex new file mode 100644 index 00000000..6c0bd2d9 --- /dev/null +++ b/sail_latex_riscv/overloadFFFFFFFFFFFFzupdate_ppn97bb9a526eb6125397ee215b375879df.tex @@ -0,0 +1 @@ +overload update_PPN = {_update_Satp64_PPN} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFFFFFFFFFzupdate_illegal_instr455fc8a1f0aa354556519de0f7b2c27b.tex b/sail_latex_riscv/overloadFFFFFFFFFFFzupdate_illegal_instr455fc8a1f0aa354556519de0f7b2c27b.tex new file mode 100644 index 00000000..4fd44919 --- /dev/null +++ b/sail_latex_riscv/overloadFFFFFFFFFFFzupdate_illegal_instr455fc8a1f0aa354556519de0f7b2c27b.tex @@ -0,0 +1 @@ +overload update_Illegal_Instr = {_update_Sedeleg_Illegal_Instr} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFFFFFFFFzupdate_fs64e6ca4d39ea47b95fa1da5e3e2e0921.tex b/sail_latex_riscv/overloadFFFFFFFFFFzupdate_fs64e6ca4d39ea47b95fa1da5e3e2e0921.tex new file mode 100644 index 00000000..55574e2a --- /dev/null +++ b/sail_latex_riscv/overloadFFFFFFFFFFzupdate_fs64e6ca4d39ea47b95fa1da5e3e2e0921.tex @@ -0,0 +1 @@ +overload update_FS = {_update_Sstatus_FS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFFFFFFFzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadFFFFFFFFFzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..f7cf2207 --- /dev/null +++ b/sail_latex_riscv/overloadFFFFFFFFFzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Counteren_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFFFFFFzupdate_samo_addr_alignb6f17cfe030aff1cf9413eeaa67b67ee.tex b/sail_latex_riscv/overloadFFFFFFFFzupdate_samo_addr_alignb6f17cfe030aff1cf9413eeaa67b67ee.tex new file mode 100644 index 00000000..0b9117bd --- /dev/null +++ b/sail_latex_riscv/overloadFFFFFFFFzupdate_samo_addr_alignb6f17cfe030aff1cf9413eeaa67b67ee.tex @@ -0,0 +1 @@ +overload update_SAMO_Addr_Align = {_update_Medeleg_SAMO_Addr_Align} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFFFFFzupdate_stibc2608b6e320f416ad08499be50228f8.tex b/sail_latex_riscv/overloadFFFFFFFzupdate_stibc2608b6e320f416ad08499be50228f8.tex new file mode 100644 index 00000000..0e90aba6 --- /dev/null +++ b/sail_latex_riscv/overloadFFFFFFFzupdate_stibc2608b6e320f416ad08499be50228f8.tex @@ -0,0 +1 @@ +overload update_STI = {_update_Minterrupts_STI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFFFFzupdate_mpp3c9c58e612012b492912dc500a75dc6e.tex b/sail_latex_riscv/overloadFFFFFFzupdate_mpp3c9c58e612012b492912dc500a75dc6e.tex new file mode 100644 index 00000000..87068cbd --- /dev/null +++ b/sail_latex_riscv/overloadFFFFFFzupdate_mpp3c9c58e612012b492912dc500a75dc6e.tex @@ -0,0 +1 @@ +overload update_MPP = {_update_Mstatus_MPP} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFFFzupdate_c58b96a6767db6cbc4e0bfce6023a35b9.tex b/sail_latex_riscv/overloadFFFFFzupdate_c58b96a6767db6cbc4e0bfce6023a35b9.tex new file mode 100644 index 00000000..ebdd88fd --- /dev/null +++ b/sail_latex_riscv/overloadFFFFFzupdate_c58b96a6767db6cbc4e0bfce6023a35b9.tex @@ -0,0 +1 @@ +overload update_C = {_update_Misa_C} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFFzupdate_pe6a91f2bcf1dfe547ab54c91e21491d7.tex b/sail_latex_riscv/overloadFFFFzupdate_pe6a91f2bcf1dfe547ab54c91e21491d7.tex new file mode 100644 index 00000000..3e277665 --- /dev/null +++ b/sail_latex_riscv/overloadFFFFzupdate_pe6a91f2bcf1dfe547ab54c91e21491d7.tex @@ -0,0 +1 @@ +overload update_P = {_update_Misa_P} \ No newline at end of file diff --git a/sail_latex_riscv/overloadFFFzx1f3c57dd04ac52fd92f3346ca51f00ec.tex b/sail_latex_riscv/overloadFFFzx1f3c57dd04ac52fd92f3346ca51f00ec.tex new file mode 100644 index 00000000..af2c057f --- /dev/null +++ b/sail_latex_riscv/overloadFFFzx1f3c57dd04ac52fd92f3346ca51f00ec.tex @@ -0,0 +1 @@ +overload X = {rX_bits, wX_bits, rX, wX} diff --git a/sail_latex_riscv/overloadFFzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex b/sail_latex_riscv/overloadFFzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex new file mode 100644 index 00000000..22e3a8b8 --- /dev/null +++ b/sail_latex_riscv/overloadFFzvector_update_subrangeb77be803268d55f5f112399f9d0dfbc2.tex @@ -0,0 +1 @@ +overload vector_update_subrange = {update_subrange_bits} diff --git a/sail_latex_riscv/overloadFzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex b/sail_latex_riscv/overloadFzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex new file mode 100644 index 00000000..68ff151b --- /dev/null +++ b/sail_latex_riscv/overloadFzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex @@ -0,0 +1 @@ +overload operator & = {and_bool} diff --git a/sail_latex_riscv/overloadGGGGGGGGGGGGGGGGGzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadGGGGGGGGGGGGGGGGGzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..d9eb4b4c --- /dev/null +++ b/sail_latex_riscv/overloadGGGGGGGGGGGGGGGGGzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_SV48_Vaddr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGGGGGGGGGGGGGGzupdate_rsw7e773e2fdd93d70f9490f8401b97d4e9.tex b/sail_latex_riscv/overloadGGGGGGGGGGGGGGGGzupdate_rsw7e773e2fdd93d70f9490f8401b97d4e9.tex new file mode 100644 index 00000000..9f2de8a4 --- /dev/null +++ b/sail_latex_riscv/overloadGGGGGGGGGGGGGGGGzupdate_rsw7e773e2fdd93d70f9490f8401b97d4e9.tex @@ -0,0 +1 @@ +overload update_RSW = {_update_SV32_PTE_RSW} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGGGGGGGGGGGGGz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex b/sail_latex_riscv/overloadGGGGGGGGGGGGGGGz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex new file mode 100644 index 00000000..8f29bb7c --- /dev/null +++ b/sail_latex_riscv/overloadGGGGGGGGGGGGGGGz_mod_r2cb5b1200e8617fc71d89b8d03167318.tex @@ -0,0 +1 @@ +overload _mod_R = {_get_PTE_Bits_R, _set_PTE_Bits_R} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGGGGGGGGGGGGz_mod_frmd6735957b64e7c0e8f6762761df1daef.tex b/sail_latex_riscv/overloadGGGGGGGGGGGGGGz_mod_frmd6735957b64e7c0e8f6762761df1daef.tex new file mode 100644 index 00000000..a8272a43 --- /dev/null +++ b/sail_latex_riscv/overloadGGGGGGGGGGGGGGz_mod_frmd6735957b64e7c0e8f6762761df1daef.tex @@ -0,0 +1 @@ +overload _mod_FRM = {_get_Fcsr_FRM, _set_Fcsr_FRM} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGGGGGGGGGGGz_mod_causeb77ad00e2fa7ea0bcdf939ce8b0035af.tex b/sail_latex_riscv/overloadGGGGGGGGGGGGGz_mod_causeb77ad00e2fa7ea0bcdf939ce8b0035af.tex new file mode 100644 index 00000000..5ebef7ca --- /dev/null +++ b/sail_latex_riscv/overloadGGGGGGGGGGGGGz_mod_causeb77ad00e2fa7ea0bcdf939ce8b0035af.tex @@ -0,0 +1 @@ +overload _mod_cause = {_get_ccsr_cause, _set_ccsr_cause} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGGGGGGGGGGz_mod_ppne431ce60abd1029c297cc5814bcb183d.tex b/sail_latex_riscv/overloadGGGGGGGGGGGGz_mod_ppne431ce60abd1029c297cc5814bcb183d.tex new file mode 100644 index 00000000..b52b6562 --- /dev/null +++ b/sail_latex_riscv/overloadGGGGGGGGGGGGz_mod_ppne431ce60abd1029c297cc5814bcb183d.tex @@ -0,0 +1 @@ +overload _mod_PPN = {_get_Satp64_PPN, _set_Satp64_PPN} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGGGGGGGGGz_mod_illegal_instr52b43b228c609c9c311d02dfb920b702.tex b/sail_latex_riscv/overloadGGGGGGGGGGGz_mod_illegal_instr52b43b228c609c9c311d02dfb920b702.tex new file mode 100644 index 00000000..d97b501b --- /dev/null +++ b/sail_latex_riscv/overloadGGGGGGGGGGGz_mod_illegal_instr52b43b228c609c9c311d02dfb920b702.tex @@ -0,0 +1 @@ +overload _mod_Illegal_Instr = {_get_Sedeleg_Illegal_Instr, _set_Sedeleg_Illegal_Instr} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGGGGGGGGz_mod_fs91fd3eaccea19c4e4e7d0eef23a6ae9a.tex b/sail_latex_riscv/overloadGGGGGGGGGGz_mod_fs91fd3eaccea19c4e4e7d0eef23a6ae9a.tex new file mode 100644 index 00000000..44245334 --- /dev/null +++ b/sail_latex_riscv/overloadGGGGGGGGGGz_mod_fs91fd3eaccea19c4e4e7d0eef23a6ae9a.tex @@ -0,0 +1 @@ +overload _mod_FS = {_get_Sstatus_FS, _set_Sstatus_FS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGGGGGGGz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadGGGGGGGGGz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..61aa2a8a --- /dev/null +++ b/sail_latex_riscv/overloadGGGGGGGGGz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Counteren_bits, _set_Counteren_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGGGGGGz_mod_samo_addr_align71af067f49a8b506587ec718a5e1b7d2.tex b/sail_latex_riscv/overloadGGGGGGGGz_mod_samo_addr_align71af067f49a8b506587ec718a5e1b7d2.tex new file mode 100644 index 00000000..21a95cc8 --- /dev/null +++ b/sail_latex_riscv/overloadGGGGGGGGz_mod_samo_addr_align71af067f49a8b506587ec718a5e1b7d2.tex @@ -0,0 +1 @@ +overload _mod_SAMO_Addr_Align = {_get_Medeleg_SAMO_Addr_Align, _set_Medeleg_SAMO_Addr_Align} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGGGGGz_mod_sti42df95a06ca2a120a19277cb17015a3f.tex b/sail_latex_riscv/overloadGGGGGGGz_mod_sti42df95a06ca2a120a19277cb17015a3f.tex new file mode 100644 index 00000000..71312259 --- /dev/null +++ b/sail_latex_riscv/overloadGGGGGGGz_mod_sti42df95a06ca2a120a19277cb17015a3f.tex @@ -0,0 +1 @@ +overload _mod_STI = {_get_Minterrupts_STI, _set_Minterrupts_STI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGGGGz_mod_mpp3d9619db1e6f03e1e065c1fea13b6a67.tex b/sail_latex_riscv/overloadGGGGGGz_mod_mpp3d9619db1e6f03e1e065c1fea13b6a67.tex new file mode 100644 index 00000000..55b29449 --- /dev/null +++ b/sail_latex_riscv/overloadGGGGGGz_mod_mpp3d9619db1e6f03e1e065c1fea13b6a67.tex @@ -0,0 +1 @@ +overload _mod_MPP = {_get_Mstatus_MPP, _set_Mstatus_MPP} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGGGz_mod_ceb8c62eaf4804c4722a6c0c552f18d93.tex b/sail_latex_riscv/overloadGGGGGz_mod_ceb8c62eaf4804c4722a6c0c552f18d93.tex new file mode 100644 index 00000000..73139c42 --- /dev/null +++ b/sail_latex_riscv/overloadGGGGGz_mod_ceb8c62eaf4804c4722a6c0c552f18d93.tex @@ -0,0 +1 @@ +overload _mod_C = {_get_Misa_C, _set_Misa_C} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGGz_mod_p2173ed12d76a57820f7a2ec18bdf9649.tex b/sail_latex_riscv/overloadGGGGz_mod_p2173ed12d76a57820f7a2ec18bdf9649.tex new file mode 100644 index 00000000..9ff6a10e --- /dev/null +++ b/sail_latex_riscv/overloadGGGGz_mod_p2173ed12d76a57820f7a2ec18bdf9649.tex @@ -0,0 +1 @@ +overload _mod_P = {_get_Misa_P, _set_Misa_P} \ No newline at end of file diff --git a/sail_latex_riscv/overloadGGGzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadGGGzto_str8b7a6895ae35945bd4740e9f790c43ee.tex new file mode 100644 index 00000000..ec291659 --- /dev/null +++ b/sail_latex_riscv/overloadGGGzto_str8b7a6895ae35945bd4740e9f790c43ee.tex @@ -0,0 +1 @@ +overload to_str = {reg_name_abi} diff --git a/sail_latex_riscv/overloadGGz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex b/sail_latex_riscv/overloadGGz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex new file mode 100644 index 00000000..a32ee3d7 --- /dev/null +++ b/sail_latex_riscv/overloadGGz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex @@ -0,0 +1 @@ +overload __size = {__id, bitvector_length} diff --git a/sail_latex_riscv/overloadGzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex b/sail_latex_riscv/overloadGzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex new file mode 100644 index 00000000..a31bd82c --- /dev/null +++ b/sail_latex_riscv/overloadGzz8operatorz0zizjz95c366628fed7d8b7c251f1acd527ee3b.tex @@ -0,0 +1 @@ +overload operator <= = {lteq_int} diff --git a/sail_latex_riscv/overloadHHHHHHHHHHHHHHHHHz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadHHHHHHHHHHHHHHHHHz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..34fd37d6 --- /dev/null +++ b/sail_latex_riscv/overloadHHHHHHHHHHHHHHHHHz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_SV48_Vaddr_bits, _set_SV48_Vaddr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHHHHHHHHHHHHHHz_mod_rswf4989a734cfde890cb5a1c8d3b4e6798.tex b/sail_latex_riscv/overloadHHHHHHHHHHHHHHHHz_mod_rswf4989a734cfde890cb5a1c8d3b4e6798.tex new file mode 100644 index 00000000..939c0f0e --- /dev/null +++ b/sail_latex_riscv/overloadHHHHHHHHHHHHHHHHz_mod_rswf4989a734cfde890cb5a1c8d3b4e6798.tex @@ -0,0 +1 @@ +overload _mod_RSW = {_get_SV32_PTE_RSW, _set_SV32_PTE_RSW} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHHHHHHHHHHHHHzupdate_v550d76e01b2aee2bcdcdd8fcb788e6ae.tex b/sail_latex_riscv/overloadHHHHHHHHHHHHHHHzupdate_v550d76e01b2aee2bcdcdd8fcb788e6ae.tex new file mode 100644 index 00000000..d4895412 --- /dev/null +++ b/sail_latex_riscv/overloadHHHHHHHHHHHHHHHzupdate_v550d76e01b2aee2bcdcdd8fcb788e6ae.tex @@ -0,0 +1 @@ +overload update_V = {_update_PTE_Bits_V} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHHHHHHHHHHHHzupdate_fflags40cb509aa136e461ae0ef1ffa4627b5a.tex b/sail_latex_riscv/overloadHHHHHHHHHHHHHHzupdate_fflags40cb509aa136e461ae0ef1ffa4627b5a.tex new file mode 100644 index 00000000..80c3b89b --- /dev/null +++ b/sail_latex_riscv/overloadHHHHHHHHHHHHHHzupdate_fflags40cb509aa136e461ae0ef1ffa4627b5a.tex @@ -0,0 +1 @@ +overload update_FFLAGS = {_update_Fcsr_FFLAGS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHHHHHHHHHHHzupdate_d57d9225616475e802ecec210f39b5b9d.tex b/sail_latex_riscv/overloadHHHHHHHHHHHHHzupdate_d57d9225616475e802ecec210f39b5b9d.tex new file mode 100644 index 00000000..07c36fb4 --- /dev/null +++ b/sail_latex_riscv/overloadHHHHHHHHHHHHHzupdate_d57d9225616475e802ecec210f39b5b9d.tex @@ -0,0 +1 @@ +overload update_d = {_update_ccsr_d} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHHHHHHHHHHzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadHHHHHHHHHHHHzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..76e1811a --- /dev/null +++ b/sail_latex_riscv/overloadHHHHHHHHHHHHzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Satp32_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHHHHHHHHHzupdate_fetch_access_faultf6d3ea38a5b206db76f3d15e6b293e4e.tex b/sail_latex_riscv/overloadHHHHHHHHHHHzupdate_fetch_access_faultf6d3ea38a5b206db76f3d15e6b293e4e.tex new file mode 100644 index 00000000..2b6e5989 --- /dev/null +++ b/sail_latex_riscv/overloadHHHHHHHHHHHzupdate_fetch_access_faultf6d3ea38a5b206db76f3d15e6b293e4e.tex @@ -0,0 +1 @@ +overload update_Fetch_Access_Fault = {_update_Sedeleg_Fetch_Access_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHHHHHHHHzupdate_spp8c7dea9e7e0f6e12e0b546be06facdc6.tex b/sail_latex_riscv/overloadHHHHHHHHHHzupdate_spp8c7dea9e7e0f6e12e0b546be06facdc6.tex new file mode 100644 index 00000000..2ab59a49 --- /dev/null +++ b/sail_latex_riscv/overloadHHHHHHHHHHzupdate_spp8c7dea9e7e0f6e12e0b546be06facdc6.tex @@ -0,0 +1 @@ +overload update_SPP = {_update_Sstatus_SPP} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHHHHHHHzupdate_hpmd00b2501d0195e7ab575a2abf98eb98c.tex b/sail_latex_riscv/overloadHHHHHHHHHzupdate_hpmd00b2501d0195e7ab575a2abf98eb98c.tex new file mode 100644 index 00000000..5bb9de86 --- /dev/null +++ b/sail_latex_riscv/overloadHHHHHHHHHzupdate_hpmd00b2501d0195e7ab575a2abf98eb98c.tex @@ -0,0 +1 @@ +overload update_HPM = {_update_Counteren_HPM} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHHHHHHzupdate_load_access_faultcc580699ff14ff7930c001851a1463b8.tex b/sail_latex_riscv/overloadHHHHHHHHzupdate_load_access_faultcc580699ff14ff7930c001851a1463b8.tex new file mode 100644 index 00000000..2fe7f0cb --- /dev/null +++ b/sail_latex_riscv/overloadHHHHHHHHzupdate_load_access_faultcc580699ff14ff7930c001851a1463b8.tex @@ -0,0 +1 @@ +overload update_Load_Access_Fault = {_update_Medeleg_Load_Access_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHHHHHzupdate_uti7bb127f84633c2b4f4b4de5582168ddf.tex b/sail_latex_riscv/overloadHHHHHHHzupdate_uti7bb127f84633c2b4f4b4de5582168ddf.tex new file mode 100644 index 00000000..7b819c5e --- /dev/null +++ b/sail_latex_riscv/overloadHHHHHHHzupdate_uti7bb127f84633c2b4f4b4de5582168ddf.tex @@ -0,0 +1 @@ +overload update_UTI = {_update_Minterrupts_UTI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHHHHzupdate_spp8c7dea9e7e0f6e12e0b546be06facdc6.tex b/sail_latex_riscv/overloadHHHHHHzupdate_spp8c7dea9e7e0f6e12e0b546be06facdc6.tex new file mode 100644 index 00000000..f1be582d --- /dev/null +++ b/sail_latex_riscv/overloadHHHHHHzupdate_spp8c7dea9e7e0f6e12e0b546be06facdc6.tex @@ -0,0 +1 @@ +overload update_SPP = {_update_Mstatus_SPP} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHHHzupdate_ba3e6b1d1a0efbd004275eab5c1c3b711.tex b/sail_latex_riscv/overloadHHHHHzupdate_ba3e6b1d1a0efbd004275eab5c1c3b711.tex new file mode 100644 index 00000000..268943dd --- /dev/null +++ b/sail_latex_riscv/overloadHHHHHzupdate_ba3e6b1d1a0efbd004275eab5c1c3b711.tex @@ -0,0 +1 @@ +overload update_B = {_update_Misa_B} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHHzupdate_o1cf4a63b59c60634f3652ef5713b7f66.tex b/sail_latex_riscv/overloadHHHHzupdate_o1cf4a63b59c60634f3652ef5713b7f66.tex new file mode 100644 index 00000000..a8cf1955 --- /dev/null +++ b/sail_latex_riscv/overloadHHHHzupdate_o1cf4a63b59c60634f3652ef5713b7f66.tex @@ -0,0 +1 @@ +overload update_O = {_update_Misa_O} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHHzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadHHHzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..4254fe60 --- /dev/null +++ b/sail_latex_riscv/overloadHHHzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Misa_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadHHzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_riscv/overloadHHzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex new file mode 100644 index 00000000..913d52bc --- /dev/null +++ b/sail_latex_riscv/overloadHHzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex @@ -0,0 +1 @@ +overload operator == = {eq_string, eq_anything} diff --git a/sail_latex_riscv/overloadHzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex b/sail_latex_riscv/overloadHzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex new file mode 100644 index 00000000..12e27dc2 --- /dev/null +++ b/sail_latex_riscv/overloadHzz8operatorz0ziz9714b8c400aed24ebd80eac39b4f9d751.tex @@ -0,0 +1 @@ +overload operator < = {lt_int} diff --git a/sail_latex_riscv/overloadIIIIIIIIIIIIIIIIIzupdate_vpni561962844c1733722e96cd548b134172.tex b/sail_latex_riscv/overloadIIIIIIIIIIIIIIIIIzupdate_vpni561962844c1733722e96cd548b134172.tex new file mode 100644 index 00000000..5e00b16d --- /dev/null +++ b/sail_latex_riscv/overloadIIIIIIIIIIIIIIIIIzupdate_vpni561962844c1733722e96cd548b134172.tex @@ -0,0 +1 @@ +overload update_VPNi = {_update_SV48_Vaddr_VPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIIIIIIIIIIIIIIzupdate_bits5a3f6688b4b8427544fc33354e84149f.tex b/sail_latex_riscv/overloadIIIIIIIIIIIIIIIIzupdate_bits5a3f6688b4b8427544fc33354e84149f.tex new file mode 100644 index 00000000..a7d4db00 --- /dev/null +++ b/sail_latex_riscv/overloadIIIIIIIIIIIIIIIIzupdate_bits5a3f6688b4b8427544fc33354e84149f.tex @@ -0,0 +1 @@ +overload update_BITS = {_update_SV32_PTE_BITS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIIIIIIIIIIIIIz_mod_v136fe7ecc31e11f2521faa02b71b57fa.tex b/sail_latex_riscv/overloadIIIIIIIIIIIIIIIz_mod_v136fe7ecc31e11f2521faa02b71b57fa.tex new file mode 100644 index 00000000..2a26aed4 --- /dev/null +++ b/sail_latex_riscv/overloadIIIIIIIIIIIIIIIz_mod_v136fe7ecc31e11f2521faa02b71b57fa.tex @@ -0,0 +1 @@ +overload _mod_V = {_get_PTE_Bits_V, _set_PTE_Bits_V} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIIIIIIIIIIIIz_mod_fflags96236e6dd2fda3eab086581987046fc9.tex b/sail_latex_riscv/overloadIIIIIIIIIIIIIIz_mod_fflags96236e6dd2fda3eab086581987046fc9.tex new file mode 100644 index 00000000..36261eab --- /dev/null +++ b/sail_latex_riscv/overloadIIIIIIIIIIIIIIz_mod_fflags96236e6dd2fda3eab086581987046fc9.tex @@ -0,0 +1 @@ +overload _mod_FFLAGS = {_get_Fcsr_FFLAGS, _set_Fcsr_FFLAGS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIIIIIIIIIIIz_mod_db168473f6dc9a1201d80a180a02bc64a.tex b/sail_latex_riscv/overloadIIIIIIIIIIIIIz_mod_db168473f6dc9a1201d80a180a02bc64a.tex new file mode 100644 index 00000000..bcfed12c --- /dev/null +++ b/sail_latex_riscv/overloadIIIIIIIIIIIIIz_mod_db168473f6dc9a1201d80a180a02bc64a.tex @@ -0,0 +1 @@ +overload _mod_d = {_get_ccsr_d, _set_ccsr_d} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIIIIIIIIIIz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadIIIIIIIIIIIIz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..ebadf5a6 --- /dev/null +++ b/sail_latex_riscv/overloadIIIIIIIIIIIIz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Satp32_bits, _set_Satp32_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIIIIIIIIIz_mod_fetch_access_fault2d0b00483619a1a634b37492d7e87b39.tex b/sail_latex_riscv/overloadIIIIIIIIIIIz_mod_fetch_access_fault2d0b00483619a1a634b37492d7e87b39.tex new file mode 100644 index 00000000..37c827a9 --- /dev/null +++ b/sail_latex_riscv/overloadIIIIIIIIIIIz_mod_fetch_access_fault2d0b00483619a1a634b37492d7e87b39.tex @@ -0,0 +1 @@ +overload _mod_Fetch_Access_Fault = {_get_Sedeleg_Fetch_Access_Fault, _set_Sedeleg_Fetch_Access_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIIIIIIIIz_mod_spp50ceeb4c06bc3d145fb76bed24fa7e68.tex b/sail_latex_riscv/overloadIIIIIIIIIIz_mod_spp50ceeb4c06bc3d145fb76bed24fa7e68.tex new file mode 100644 index 00000000..c364a4db --- /dev/null +++ b/sail_latex_riscv/overloadIIIIIIIIIIz_mod_spp50ceeb4c06bc3d145fb76bed24fa7e68.tex @@ -0,0 +1 @@ +overload _mod_SPP = {_get_Sstatus_SPP, _set_Sstatus_SPP} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIIIIIIIz_mod_hpm583914551c880f3252ab7d2eb7c126a5.tex b/sail_latex_riscv/overloadIIIIIIIIIz_mod_hpm583914551c880f3252ab7d2eb7c126a5.tex new file mode 100644 index 00000000..77f24293 --- /dev/null +++ b/sail_latex_riscv/overloadIIIIIIIIIz_mod_hpm583914551c880f3252ab7d2eb7c126a5.tex @@ -0,0 +1 @@ +overload _mod_HPM = {_get_Counteren_HPM, _set_Counteren_HPM} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIIIIIIz_mod_load_access_fault185ee80ec13fa3fdeb7c2cd3a76688c9.tex b/sail_latex_riscv/overloadIIIIIIIIz_mod_load_access_fault185ee80ec13fa3fdeb7c2cd3a76688c9.tex new file mode 100644 index 00000000..9aeb3856 --- /dev/null +++ b/sail_latex_riscv/overloadIIIIIIIIz_mod_load_access_fault185ee80ec13fa3fdeb7c2cd3a76688c9.tex @@ -0,0 +1 @@ +overload _mod_Load_Access_Fault = {_get_Medeleg_Load_Access_Fault, _set_Medeleg_Load_Access_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIIIIIz_mod_utia23224af950fbe7be4b3db2f7092e6b4.tex b/sail_latex_riscv/overloadIIIIIIIz_mod_utia23224af950fbe7be4b3db2f7092e6b4.tex new file mode 100644 index 00000000..fa9c34f1 --- /dev/null +++ b/sail_latex_riscv/overloadIIIIIIIz_mod_utia23224af950fbe7be4b3db2f7092e6b4.tex @@ -0,0 +1 @@ +overload _mod_UTI = {_get_Minterrupts_UTI, _set_Minterrupts_UTI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIIIIz_mod_spp50ceeb4c06bc3d145fb76bed24fa7e68.tex b/sail_latex_riscv/overloadIIIIIIz_mod_spp50ceeb4c06bc3d145fb76bed24fa7e68.tex new file mode 100644 index 00000000..cc3bf15f --- /dev/null +++ b/sail_latex_riscv/overloadIIIIIIz_mod_spp50ceeb4c06bc3d145fb76bed24fa7e68.tex @@ -0,0 +1 @@ +overload _mod_SPP = {_get_Mstatus_SPP, _set_Mstatus_SPP} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIIIz_mod_bd3b147cd60c14b1c9fafe4194389bcdc.tex b/sail_latex_riscv/overloadIIIIIz_mod_bd3b147cd60c14b1c9fafe4194389bcdc.tex new file mode 100644 index 00000000..c811842a --- /dev/null +++ b/sail_latex_riscv/overloadIIIIIz_mod_bd3b147cd60c14b1c9fafe4194389bcdc.tex @@ -0,0 +1 @@ +overload _mod_B = {_get_Misa_B, _set_Misa_B} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIIz_mod_o90384a06c29bd45bb9fb8e11226e2dcc.tex b/sail_latex_riscv/overloadIIIIz_mod_o90384a06c29bd45bb9fb8e11226e2dcc.tex new file mode 100644 index 00000000..74b36799 --- /dev/null +++ b/sail_latex_riscv/overloadIIIIz_mod_o90384a06c29bd45bb9fb8e11226e2dcc.tex @@ -0,0 +1 @@ +overload _mod_O = {_get_Misa_O, _set_Misa_O} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIIz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadIIIz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..5eba51bd --- /dev/null +++ b/sail_latex_riscv/overloadIIIz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Misa_bits, _set_Misa_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadIIzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex b/sail_latex_riscv/overloadIIzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex new file mode 100644 index 00000000..6d92e11b --- /dev/null +++ b/sail_latex_riscv/overloadIIzvector_updateb14d5207ae01ed7fc9d9882c9cc3ebef.tex @@ -0,0 +1 @@ +overload vector_update = {any_vector_update} diff --git a/sail_latex_riscv/overloadIzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex b/sail_latex_riscv/overloadIzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex new file mode 100644 index 00000000..dfbcc136 --- /dev/null +++ b/sail_latex_riscv/overloadIzz8operatorz0zkzjz94161e4bfad2d20e5d25bc774612b6588.tex @@ -0,0 +1 @@ +overload operator >= = {gteq_int} diff --git a/sail_latex_riscv/overloadJJJJJJJJJJJJJJJJJz_mod_vpni3dea7adc47f37ae733dae17ca8f9a4fe.tex b/sail_latex_riscv/overloadJJJJJJJJJJJJJJJJJz_mod_vpni3dea7adc47f37ae733dae17ca8f9a4fe.tex new file mode 100644 index 00000000..7c3a00c5 --- /dev/null +++ b/sail_latex_riscv/overloadJJJJJJJJJJJJJJJJJz_mod_vpni3dea7adc47f37ae733dae17ca8f9a4fe.tex @@ -0,0 +1 @@ +overload _mod_VPNi = {_get_SV48_Vaddr_VPNi, _set_SV48_Vaddr_VPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJJJJJJJJJJJJJJz_mod_bits60455a5b4231baf7b82d860f6efc2682.tex b/sail_latex_riscv/overloadJJJJJJJJJJJJJJJJz_mod_bits60455a5b4231baf7b82d860f6efc2682.tex new file mode 100644 index 00000000..ecf3ce73 --- /dev/null +++ b/sail_latex_riscv/overloadJJJJJJJJJJJJJJJJz_mod_bits60455a5b4231baf7b82d860f6efc2682.tex @@ -0,0 +1 @@ +overload _mod_BITS = {_get_SV32_PTE_BITS, _set_SV32_PTE_BITS} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJJJJJJJJJJJJJzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadJJJJJJJJJJJJJJJzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..4935ea56 --- /dev/null +++ b/sail_latex_riscv/overloadJJJJJJJJJJJJJJJzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Ext_PTE_Bits_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJJJJJJJJJJJJzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadJJJJJJJJJJJJJJzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..75379eb7 --- /dev/null +++ b/sail_latex_riscv/overloadJJJJJJJJJJJJJJzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_htif_cmd_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJJJJJJJJJJJzupdate_e7a63b7e30669139ab9225922027a87d0.tex b/sail_latex_riscv/overloadJJJJJJJJJJJJJzupdate_e7a63b7e30669139ab9225922027a87d0.tex new file mode 100644 index 00000000..8a97cc28 --- /dev/null +++ b/sail_latex_riscv/overloadJJJJJJJJJJJJJzupdate_e7a63b7e30669139ab9225922027a87d0.tex @@ -0,0 +1 @@ +overload update_e = {_update_ccsr_e} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJJJJJJJJJJzupdate_modea8b179bc2887fad34e9a3f8cefc9cf29.tex b/sail_latex_riscv/overloadJJJJJJJJJJJJzupdate_modea8b179bc2887fad34e9a3f8cefc9cf29.tex new file mode 100644 index 00000000..8bc06302 --- /dev/null +++ b/sail_latex_riscv/overloadJJJJJJJJJJJJzupdate_modea8b179bc2887fad34e9a3f8cefc9cf29.tex @@ -0,0 +1 @@ +overload update_Mode = {_update_Satp32_Mode} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJJJJJJJJJzupdate_fetch_addr_aligned5113ea584423e01fcb4b2781a3aeab.tex b/sail_latex_riscv/overloadJJJJJJJJJJJzupdate_fetch_addr_aligned5113ea584423e01fcb4b2781a3aeab.tex new file mode 100644 index 00000000..0545581b --- /dev/null +++ b/sail_latex_riscv/overloadJJJJJJJJJJJzupdate_fetch_addr_aligned5113ea584423e01fcb4b2781a3aeab.tex @@ -0,0 +1 @@ +overload update_Fetch_Addr_Align = {_update_Sedeleg_Fetch_Addr_Align} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJJJJJJJJzupdate_spie94668fa3ad37daf933543298ec02f222.tex b/sail_latex_riscv/overloadJJJJJJJJJJzupdate_spie94668fa3ad37daf933543298ec02f222.tex new file mode 100644 index 00000000..8e7d67ff --- /dev/null +++ b/sail_latex_riscv/overloadJJJJJJJJJJzupdate_spie94668fa3ad37daf933543298ec02f222.tex @@ -0,0 +1 @@ +overload update_SPIE = {_update_Sstatus_SPIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJJJJJJJzupdate_ir0515bd19fecd95b93762d149f033240a.tex b/sail_latex_riscv/overloadJJJJJJJJJzupdate_ir0515bd19fecd95b93762d149f033240a.tex new file mode 100644 index 00000000..bf94e78a --- /dev/null +++ b/sail_latex_riscv/overloadJJJJJJJJJzupdate_ir0515bd19fecd95b93762d149f033240a.tex @@ -0,0 +1 @@ +overload update_IR = {_update_Counteren_IR} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJJJJJJzupdate_load_addr_aligna304d90cb1ef10e79624a3324854bad0.tex b/sail_latex_riscv/overloadJJJJJJJJzupdate_load_addr_aligna304d90cb1ef10e79624a3324854bad0.tex new file mode 100644 index 00000000..ff26ba3e --- /dev/null +++ b/sail_latex_riscv/overloadJJJJJJJJzupdate_load_addr_aligna304d90cb1ef10e79624a3324854bad0.tex @@ -0,0 +1 @@ +overload update_Load_Addr_Align = {_update_Medeleg_Load_Addr_Align} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJJJJJzupdate_msi05b568752ec5efb2935982bb126bbdae.tex b/sail_latex_riscv/overloadJJJJJJJzupdate_msi05b568752ec5efb2935982bb126bbdae.tex new file mode 100644 index 00000000..bd8b66e8 --- /dev/null +++ b/sail_latex_riscv/overloadJJJJJJJzupdate_msi05b568752ec5efb2935982bb126bbdae.tex @@ -0,0 +1 @@ +overload update_MSI = {_update_Minterrupts_MSI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJJJJzupdate_mpiea8e9bf67d46cea99b972f7713503794d.tex b/sail_latex_riscv/overloadJJJJJJzupdate_mpiea8e9bf67d46cea99b972f7713503794d.tex new file mode 100644 index 00000000..5e01562b --- /dev/null +++ b/sail_latex_riscv/overloadJJJJJJzupdate_mpiea8e9bf67d46cea99b972f7713503794d.tex @@ -0,0 +1 @@ +overload update_MPIE = {_update_Mstatus_MPIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJJJzupdate_ab740c1f378b55b3328b2a9f25ff6c1cf.tex b/sail_latex_riscv/overloadJJJJJzupdate_ab740c1f378b55b3328b2a9f25ff6c1cf.tex new file mode 100644 index 00000000..f86070de --- /dev/null +++ b/sail_latex_riscv/overloadJJJJJzupdate_ab740c1f378b55b3328b2a9f25ff6c1cf.tex @@ -0,0 +1 @@ +overload update_A = {_update_Misa_A} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJJzupdate_n06ad7e05862f7e6f8616952d94bf0cdf.tex b/sail_latex_riscv/overloadJJJJzupdate_n06ad7e05862f7e6f8616952d94bf0cdf.tex new file mode 100644 index 00000000..0875dd03 --- /dev/null +++ b/sail_latex_riscv/overloadJJJJzupdate_n06ad7e05862f7e6f8616952d94bf0cdf.tex @@ -0,0 +1 @@ +overload update_N = {_update_Misa_N} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJJzupdate_mxlb5a3c988cbea039f1e178bcd72815821.tex b/sail_latex_riscv/overloadJJJzupdate_mxlb5a3c988cbea039f1e178bcd72815821.tex new file mode 100644 index 00000000..3a3c97cc --- /dev/null +++ b/sail_latex_riscv/overloadJJJzupdate_mxlb5a3c988cbea039f1e178bcd72815821.tex @@ -0,0 +1 @@ +overload update_MXL = {_update_Misa_MXL} \ No newline at end of file diff --git a/sail_latex_riscv/overloadJJzappend88575169e0ec1639b6ae3851df999710.tex b/sail_latex_riscv/overloadJJzappend88575169e0ec1639b6ae3851df999710.tex new file mode 100644 index 00000000..3cebd671 --- /dev/null +++ b/sail_latex_riscv/overloadJJzappend88575169e0ec1639b6ae3851df999710.tex @@ -0,0 +1 @@ +overload append = {vector_concat} diff --git a/sail_latex_riscv/overloadJzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex b/sail_latex_riscv/overloadJzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex new file mode 100644 index 00000000..86b47f92 --- /dev/null +++ b/sail_latex_riscv/overloadJzz8operatorz0zkz93747e4d4a6f99eb3fca0b477d2437ed5.tex @@ -0,0 +1 @@ +overload operator > = {gt_int} diff --git a/sail_latex_riscv/overloadKKKKKKKKKKKKKKKKKzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex b/sail_latex_riscv/overloadKKKKKKKKKKKKKKKKKzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex new file mode 100644 index 00000000..b0ad6a6c --- /dev/null +++ b/sail_latex_riscv/overloadKKKKKKKKKKKKKKKKKzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex @@ -0,0 +1 @@ +overload update_PgOfs = {_update_SV48_Vaddr_PgOfs} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKKKKKKKKKKKKKKzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadKKKKKKKKKKKKKKKKzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..47c8ca98 --- /dev/null +++ b/sail_latex_riscv/overloadKKKKKKKKKKKKKKKKzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_SV39_Vaddr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKKKKKKKKKKKKKz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadKKKKKKKKKKKKKKKz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..9208871d --- /dev/null +++ b/sail_latex_riscv/overloadKKKKKKKKKKKKKKKz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Ext_PTE_Bits_bits, _set_Ext_PTE_Bits_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKKKKKKKKKKKKz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadKKKKKKKKKKKKKKz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..4a2613a2 --- /dev/null +++ b/sail_latex_riscv/overloadKKKKKKKKKKKKKKz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_htif_cmd_bits, _set_htif_cmd_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKKKKKKKKKKKz_mod_ed8b4db91b378334a887e790f3939603e.tex b/sail_latex_riscv/overloadKKKKKKKKKKKKKz_mod_ed8b4db91b378334a887e790f3939603e.tex new file mode 100644 index 00000000..9cd7b706 --- /dev/null +++ b/sail_latex_riscv/overloadKKKKKKKKKKKKKz_mod_ed8b4db91b378334a887e790f3939603e.tex @@ -0,0 +1 @@ +overload _mod_e = {_get_ccsr_e, _set_ccsr_e} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKKKKKKKKKKz_mod_mode7dda808a114a5634018c73fc24f43140.tex b/sail_latex_riscv/overloadKKKKKKKKKKKKz_mod_mode7dda808a114a5634018c73fc24f43140.tex new file mode 100644 index 00000000..903f57b0 --- /dev/null +++ b/sail_latex_riscv/overloadKKKKKKKKKKKKz_mod_mode7dda808a114a5634018c73fc24f43140.tex @@ -0,0 +1 @@ +overload _mod_Mode = {_get_Satp32_Mode, _set_Satp32_Mode} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKKKKKKKKKz_mod_fetch_addr_align94e1ec62c225ae16e8fbc401efa25352.tex b/sail_latex_riscv/overloadKKKKKKKKKKKz_mod_fetch_addr_align94e1ec62c225ae16e8fbc401efa25352.tex new file mode 100644 index 00000000..0ab14206 --- /dev/null +++ b/sail_latex_riscv/overloadKKKKKKKKKKKz_mod_fetch_addr_align94e1ec62c225ae16e8fbc401efa25352.tex @@ -0,0 +1 @@ +overload _mod_Fetch_Addr_Align = {_get_Sedeleg_Fetch_Addr_Align, _set_Sedeleg_Fetch_Addr_Align} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKKKKKKKKz_mod_spie8a60328109316a4d9a0f7769708c8522.tex b/sail_latex_riscv/overloadKKKKKKKKKKz_mod_spie8a60328109316a4d9a0f7769708c8522.tex new file mode 100644 index 00000000..b15ecd39 --- /dev/null +++ b/sail_latex_riscv/overloadKKKKKKKKKKz_mod_spie8a60328109316a4d9a0f7769708c8522.tex @@ -0,0 +1 @@ +overload _mod_SPIE = {_get_Sstatus_SPIE, _set_Sstatus_SPIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKKKKKKKz_mod_ira44a158ed08eebfa24118152fd099692.tex b/sail_latex_riscv/overloadKKKKKKKKKz_mod_ira44a158ed08eebfa24118152fd099692.tex new file mode 100644 index 00000000..66dcbf6b --- /dev/null +++ b/sail_latex_riscv/overloadKKKKKKKKKz_mod_ira44a158ed08eebfa24118152fd099692.tex @@ -0,0 +1 @@ +overload _mod_IR = {_get_Counteren_IR, _set_Counteren_IR} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKKKKKKz_mod_load_addr_align34e982fd800fd67969b64a5932439781.tex b/sail_latex_riscv/overloadKKKKKKKKz_mod_load_addr_align34e982fd800fd67969b64a5932439781.tex new file mode 100644 index 00000000..013558a5 --- /dev/null +++ b/sail_latex_riscv/overloadKKKKKKKKz_mod_load_addr_align34e982fd800fd67969b64a5932439781.tex @@ -0,0 +1 @@ +overload _mod_Load_Addr_Align = {_get_Medeleg_Load_Addr_Align, _set_Medeleg_Load_Addr_Align} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKKKKKz_mod_msid0d72e986b51e2572e46aebbb9db0de0.tex b/sail_latex_riscv/overloadKKKKKKKz_mod_msid0d72e986b51e2572e46aebbb9db0de0.tex new file mode 100644 index 00000000..a3568210 --- /dev/null +++ b/sail_latex_riscv/overloadKKKKKKKz_mod_msid0d72e986b51e2572e46aebbb9db0de0.tex @@ -0,0 +1 @@ +overload _mod_MSI = {_get_Minterrupts_MSI, _set_Minterrupts_MSI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKKKKz_mod_mpief0782a90b79bf243f3b4c31e5bf1eda0.tex b/sail_latex_riscv/overloadKKKKKKz_mod_mpief0782a90b79bf243f3b4c31e5bf1eda0.tex new file mode 100644 index 00000000..a35becdd --- /dev/null +++ b/sail_latex_riscv/overloadKKKKKKz_mod_mpief0782a90b79bf243f3b4c31e5bf1eda0.tex @@ -0,0 +1 @@ +overload _mod_MPIE = {_get_Mstatus_MPIE, _set_Mstatus_MPIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKKKz_mod_a62a6f88676512d98a363811f9f5ba327.tex b/sail_latex_riscv/overloadKKKKKz_mod_a62a6f88676512d98a363811f9f5ba327.tex new file mode 100644 index 00000000..f33e6014 --- /dev/null +++ b/sail_latex_riscv/overloadKKKKKz_mod_a62a6f88676512d98a363811f9f5ba327.tex @@ -0,0 +1 @@ +overload _mod_A = {_get_Misa_A, _set_Misa_A} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKKz_mod_n17a5dd1d9904ad5f32f920b05936d22a.tex b/sail_latex_riscv/overloadKKKKz_mod_n17a5dd1d9904ad5f32f920b05936d22a.tex new file mode 100644 index 00000000..9ae46a4b --- /dev/null +++ b/sail_latex_riscv/overloadKKKKz_mod_n17a5dd1d9904ad5f32f920b05936d22a.tex @@ -0,0 +1 @@ +overload _mod_N = {_get_Misa_N, _set_Misa_N} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKKz_mod_mxlaa066cfb7ec1d12283cbb376dd9b1101.tex b/sail_latex_riscv/overloadKKKz_mod_mxlaa066cfb7ec1d12283cbb376dd9b1101.tex new file mode 100644 index 00000000..4e5b1d4a --- /dev/null +++ b/sail_latex_riscv/overloadKKKz_mod_mxlaa066cfb7ec1d12283cbb376dd9b1101.tex @@ -0,0 +1 @@ +overload _mod_MXL = {_get_Misa_MXL, _set_Misa_MXL} \ No newline at end of file diff --git a/sail_latex_riscv/overloadKKzzw805a9067649c7cfeedcb41b57a7e2c86.tex b/sail_latex_riscv/overloadKKzzw805a9067649c7cfeedcb41b57a7e2c86.tex new file mode 100644 index 00000000..f315fd4e --- /dev/null +++ b/sail_latex_riscv/overloadKKzzw805a9067649c7cfeedcb41b57a7e2c86.tex @@ -0,0 +1 @@ +overload ~ = {not_bool, not_vec, not_bit} diff --git a/sail_latex_riscv/overloadKz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex b/sail_latex_riscv/overloadKz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex new file mode 100644 index 00000000..ec898306 --- /dev/null +++ b/sail_latex_riscv/overloadKz__sizze5b2e36a5dbb42eaba80b4d164e45d3ae.tex @@ -0,0 +1 @@ +overload __size = {__id} diff --git a/sail_latex_riscv/overloadLLLLLLLLLLLLLLLLLz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex b/sail_latex_riscv/overloadLLLLLLLLLLLLLLLLLz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex new file mode 100644 index 00000000..00f4d316 --- /dev/null +++ b/sail_latex_riscv/overloadLLLLLLLLLLLLLLLLLz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex @@ -0,0 +1 @@ +overload _mod_PgOfs = {_get_SV48_Vaddr_PgOfs, _set_SV48_Vaddr_PgOfs} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLLLLLLLLLLLLLLLz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadLLLLLLLLLLLLLLLLz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..ae2921ae --- /dev/null +++ b/sail_latex_riscv/overloadLLLLLLLLLLLLLLLLz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_SV39_Vaddr_bits, _set_SV39_Vaddr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLLLLLLLLLLLLLLzupdate_capwritec85de060c1310bedb36952771a329406.tex b/sail_latex_riscv/overloadLLLLLLLLLLLLLLLzupdate_capwritec85de060c1310bedb36952771a329406.tex new file mode 100644 index 00000000..60b01fa9 --- /dev/null +++ b/sail_latex_riscv/overloadLLLLLLLLLLLLLLLzupdate_capwritec85de060c1310bedb36952771a329406.tex @@ -0,0 +1 @@ +overload update_CapWrite = {_update_Ext_PTE_Bits_CapWrite} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLLLLLLLLLLLLLzupdate_device133872281fc83dcb5df6232f6344d8c0.tex b/sail_latex_riscv/overloadLLLLLLLLLLLLLLzupdate_device133872281fc83dcb5df6232f6344d8c0.tex new file mode 100644 index 00000000..9cb70fd2 --- /dev/null +++ b/sail_latex_riscv/overloadLLLLLLLLLLLLLLzupdate_device133872281fc83dcb5df6232f6344d8c0.tex @@ -0,0 +1 @@ +overload update_device = {_update_htif_cmd_device} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLLLLLLLLLLLLzc15f67105dab436b80b9241d87d1f8e9d.tex b/sail_latex_riscv/overloadLLLLLLLLLLLLLzc15f67105dab436b80b9241d87d1f8e9d.tex new file mode 100644 index 00000000..c14ae5d8 --- /dev/null +++ b/sail_latex_riscv/overloadLLLLLLLLLLLLLzc15f67105dab436b80b9241d87d1f8e9d.tex @@ -0,0 +1 @@ +overload C = {rC_bits, wC_bits, rC, wC} diff --git a/sail_latex_riscv/overloadLLLLLLLLLLLLzupdate_asid5cc334067dcbe9c9a4eb59266b7b5404.tex b/sail_latex_riscv/overloadLLLLLLLLLLLLzupdate_asid5cc334067dcbe9c9a4eb59266b7b5404.tex new file mode 100644 index 00000000..e7d254a7 --- /dev/null +++ b/sail_latex_riscv/overloadLLLLLLLLLLLLzupdate_asid5cc334067dcbe9c9a4eb59266b7b5404.tex @@ -0,0 +1 @@ +overload update_Asid = {_update_Satp32_Asid} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLLLLLLLLLLzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadLLLLLLLLLLLzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..5713a08b --- /dev/null +++ b/sail_latex_riscv/overloadLLLLLLLLLLLzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Sinterrupts_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLLLLLLLLLzupdate_upiea5ad86a550536087d757a5582d1a8bb9.tex b/sail_latex_riscv/overloadLLLLLLLLLLzupdate_upiea5ad86a550536087d757a5582d1a8bb9.tex new file mode 100644 index 00000000..b27519d6 --- /dev/null +++ b/sail_latex_riscv/overloadLLLLLLLLLLzupdate_upiea5ad86a550536087d757a5582d1a8bb9.tex @@ -0,0 +1 @@ +overload update_UPIE = {_update_Sstatus_UPIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLLLLLLLLzupdate_tm832684a0b7e0412ced303c57d9817272.tex b/sail_latex_riscv/overloadLLLLLLLLLzupdate_tm832684a0b7e0412ced303c57d9817272.tex new file mode 100644 index 00000000..cdfcccdf --- /dev/null +++ b/sail_latex_riscv/overloadLLLLLLLLLzupdate_tm832684a0b7e0412ced303c57d9817272.tex @@ -0,0 +1 @@ +overload update_TM = {_update_Counteren_TM} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLLLLLLLzupdate_breakpoint560b5628b33be91263dd76c1c88c6a06.tex b/sail_latex_riscv/overloadLLLLLLLLzupdate_breakpoint560b5628b33be91263dd76c1c88c6a06.tex new file mode 100644 index 00000000..f339646d --- /dev/null +++ b/sail_latex_riscv/overloadLLLLLLLLzupdate_breakpoint560b5628b33be91263dd76c1c88c6a06.tex @@ -0,0 +1 @@ +overload update_Breakpoint = {_update_Medeleg_Breakpoint} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLLLLLLzupdate_ssi5471fd96e5b7a8471f1ef66b598501a9.tex b/sail_latex_riscv/overloadLLLLLLLzupdate_ssi5471fd96e5b7a8471f1ef66b598501a9.tex new file mode 100644 index 00000000..18f4e3a0 --- /dev/null +++ b/sail_latex_riscv/overloadLLLLLLLzupdate_ssi5471fd96e5b7a8471f1ef66b598501a9.tex @@ -0,0 +1 @@ +overload update_SSI = {_update_Minterrupts_SSI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLLLLLzupdate_spie94668fa3ad37daf933543298ec02f222.tex b/sail_latex_riscv/overloadLLLLLLzupdate_spie94668fa3ad37daf933543298ec02f222.tex new file mode 100644 index 00000000..5dc892a0 --- /dev/null +++ b/sail_latex_riscv/overloadLLLLLLzupdate_spie94668fa3ad37daf933543298ec02f222.tex @@ -0,0 +1 @@ +overload update_SPIE = {_update_Mstatus_SPIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLLLLzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadLLLLLzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..72436193 --- /dev/null +++ b/sail_latex_riscv/overloadLLLLLzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Mstatus_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLLLzupdate_m412167d0e8698c4d2e3c5386d172d67a.tex b/sail_latex_riscv/overloadLLLLzupdate_m412167d0e8698c4d2e3c5386d172d67a.tex new file mode 100644 index 00000000..ef5cd932 --- /dev/null +++ b/sail_latex_riscv/overloadLLLLzupdate_m412167d0e8698c4d2e3c5386d172d67a.tex @@ -0,0 +1 @@ +overload update_M = {_update_Misa_M} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLLzupdate_z526c1a025fbdbfc03ac9334c924737a9.tex b/sail_latex_riscv/overloadLLLzupdate_z526c1a025fbdbfc03ac9334c924737a9.tex new file mode 100644 index 00000000..d34d7117 --- /dev/null +++ b/sail_latex_riscv/overloadLLLzupdate_z526c1a025fbdbfc03ac9334c924737a9.tex @@ -0,0 +1 @@ +overload update_Z = {_update_Misa_Z} \ No newline at end of file diff --git a/sail_latex_riscv/overloadLLzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex b/sail_latex_riscv/overloadLLzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex new file mode 100644 index 00000000..847c4038 --- /dev/null +++ b/sail_latex_riscv/overloadLLzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex @@ -0,0 +1 @@ +overload operator != = {neq_vec, neq_anything} diff --git a/sail_latex_riscv/overloadLzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex b/sail_latex_riscv/overloadLzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex new file mode 100644 index 00000000..2b2f05b1 --- /dev/null +++ b/sail_latex_riscv/overloadLzz8operatorz0zbz9a2d0168f574b152e5f31357e86602c16.tex @@ -0,0 +1 @@ +overload operator + = {add_atom, add_int} diff --git a/sail_latex_riscv/overloadMMMMMMMMMMMMMMMMMzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadMMMMMMMMMMMMMMMMMzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..0e734ffb --- /dev/null +++ b/sail_latex_riscv/overloadMMMMMMMMMMMMMMMMMzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_SV48_Paddr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMMMMMMMMMMMMMMMzupdate_vpni561962844c1733722e96cd548b134172.tex b/sail_latex_riscv/overloadMMMMMMMMMMMMMMMMzupdate_vpni561962844c1733722e96cd548b134172.tex new file mode 100644 index 00000000..b242d9c8 --- /dev/null +++ b/sail_latex_riscv/overloadMMMMMMMMMMMMMMMMzupdate_vpni561962844c1733722e96cd548b134172.tex @@ -0,0 +1 @@ +overload update_VPNi = {_update_SV39_Vaddr_VPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMMMMMMMMMMMMMMz_mod_capwritee4dbda0d648b2ccd05f17d2dddd34537.tex b/sail_latex_riscv/overloadMMMMMMMMMMMMMMMz_mod_capwritee4dbda0d648b2ccd05f17d2dddd34537.tex new file mode 100644 index 00000000..91bb61c9 --- /dev/null +++ b/sail_latex_riscv/overloadMMMMMMMMMMMMMMMz_mod_capwritee4dbda0d648b2ccd05f17d2dddd34537.tex @@ -0,0 +1 @@ +overload _mod_CapWrite = {_get_Ext_PTE_Bits_CapWrite, _set_Ext_PTE_Bits_CapWrite} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMMMMMMMMMMMMMz_mod_deviced59eb8a2803361d08f70d5dfe4de57a2.tex b/sail_latex_riscv/overloadMMMMMMMMMMMMMMz_mod_deviced59eb8a2803361d08f70d5dfe4de57a2.tex new file mode 100644 index 00000000..f108d6f5 --- /dev/null +++ b/sail_latex_riscv/overloadMMMMMMMMMMMMMMz_mod_deviced59eb8a2803361d08f70d5dfe4de57a2.tex @@ -0,0 +1 @@ +overload _mod_device = {_get_htif_cmd_device, _set_htif_cmd_device} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMMMMMMMMMMMMzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadMMMMMMMMMMMMMzto_str8b7a6895ae35945bd4740e9f790c43ee.tex new file mode 100644 index 00000000..2841bb52 --- /dev/null +++ b/sail_latex_riscv/overloadMMMMMMMMMMMMMzto_str8b7a6895ae35945bd4740e9f790c43ee.tex @@ -0,0 +1 @@ +overload to_str = {cap_reg_name_abi} diff --git a/sail_latex_riscv/overloadMMMMMMMMMMMMz_mod_asid55036e3f51de771bc07215ff1caec750.tex b/sail_latex_riscv/overloadMMMMMMMMMMMMz_mod_asid55036e3f51de771bc07215ff1caec750.tex new file mode 100644 index 00000000..ec21cd20 --- /dev/null +++ b/sail_latex_riscv/overloadMMMMMMMMMMMMz_mod_asid55036e3f51de771bc07215ff1caec750.tex @@ -0,0 +1 @@ +overload _mod_Asid = {_get_Satp32_Asid, _set_Satp32_Asid} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMMMMMMMMMMz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadMMMMMMMMMMMz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..e33dcc90 --- /dev/null +++ b/sail_latex_riscv/overloadMMMMMMMMMMMz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Sinterrupts_bits, _set_Sinterrupts_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMMMMMMMMMz_mod_upie27f56ba53dc72f512e0a128ab616ba83.tex b/sail_latex_riscv/overloadMMMMMMMMMMz_mod_upie27f56ba53dc72f512e0a128ab616ba83.tex new file mode 100644 index 00000000..e6c17745 --- /dev/null +++ b/sail_latex_riscv/overloadMMMMMMMMMMz_mod_upie27f56ba53dc72f512e0a128ab616ba83.tex @@ -0,0 +1 @@ +overload _mod_UPIE = {_get_Sstatus_UPIE, _set_Sstatus_UPIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMMMMMMMMz_mod_tm778e52c0329c82ffcc9fd72f0034a61e.tex b/sail_latex_riscv/overloadMMMMMMMMMz_mod_tm778e52c0329c82ffcc9fd72f0034a61e.tex new file mode 100644 index 00000000..21712aa6 --- /dev/null +++ b/sail_latex_riscv/overloadMMMMMMMMMz_mod_tm778e52c0329c82ffcc9fd72f0034a61e.tex @@ -0,0 +1 @@ +overload _mod_TM = {_get_Counteren_TM, _set_Counteren_TM} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMMMMMMMz_mod_breakpointfb455863fb6768bbcbc1b984dbef6360.tex b/sail_latex_riscv/overloadMMMMMMMMz_mod_breakpointfb455863fb6768bbcbc1b984dbef6360.tex new file mode 100644 index 00000000..ff188dea --- /dev/null +++ b/sail_latex_riscv/overloadMMMMMMMMz_mod_breakpointfb455863fb6768bbcbc1b984dbef6360.tex @@ -0,0 +1 @@ +overload _mod_Breakpoint = {_get_Medeleg_Breakpoint, _set_Medeleg_Breakpoint} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMMMMMMz_mod_ssicb14ae48c26ad162228aa44069530c95.tex b/sail_latex_riscv/overloadMMMMMMMz_mod_ssicb14ae48c26ad162228aa44069530c95.tex new file mode 100644 index 00000000..f4873868 --- /dev/null +++ b/sail_latex_riscv/overloadMMMMMMMz_mod_ssicb14ae48c26ad162228aa44069530c95.tex @@ -0,0 +1 @@ +overload _mod_SSI = {_get_Minterrupts_SSI, _set_Minterrupts_SSI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMMMMMz_mod_spie8a60328109316a4d9a0f7769708c8522.tex b/sail_latex_riscv/overloadMMMMMMz_mod_spie8a60328109316a4d9a0f7769708c8522.tex new file mode 100644 index 00000000..8c3e5e29 --- /dev/null +++ b/sail_latex_riscv/overloadMMMMMMz_mod_spie8a60328109316a4d9a0f7769708c8522.tex @@ -0,0 +1 @@ +overload _mod_SPIE = {_get_Mstatus_SPIE, _set_Mstatus_SPIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMMMMz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadMMMMMz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..2c1df176 --- /dev/null +++ b/sail_latex_riscv/overloadMMMMMz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Mstatus_bits, _set_Mstatus_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMMMz_mod_mec2059285eb3c26fd1e8311b63d5c502.tex b/sail_latex_riscv/overloadMMMMz_mod_mec2059285eb3c26fd1e8311b63d5c502.tex new file mode 100644 index 00000000..056690f9 --- /dev/null +++ b/sail_latex_riscv/overloadMMMMz_mod_mec2059285eb3c26fd1e8311b63d5c502.tex @@ -0,0 +1 @@ +overload _mod_M = {_get_Misa_M, _set_Misa_M} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMMz_mod_za28d358f8525c17052bc8ea6cdba9052.tex b/sail_latex_riscv/overloadMMMz_mod_za28d358f8525c17052bc8ea6cdba9052.tex new file mode 100644 index 00000000..64c65982 --- /dev/null +++ b/sail_latex_riscv/overloadMMMz_mod_za28d358f8525c17052bc8ea6cdba9052.tex @@ -0,0 +1 @@ +overload _mod_Z = {_get_Misa_Z, _set_Misa_Z} \ No newline at end of file diff --git a/sail_latex_riscv/overloadMMzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex b/sail_latex_riscv/overloadMMzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex new file mode 100644 index 00000000..cf01736a --- /dev/null +++ b/sail_latex_riscv/overloadMMzz8operatorz0z6z9d3731bb9b1c9d765858778ad48ba6b3a.tex @@ -0,0 +1 @@ +overload operator & = {and_vec} diff --git a/sail_latex_riscv/overloadMzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex b/sail_latex_riscv/overloadMzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex new file mode 100644 index 00000000..15a078ce --- /dev/null +++ b/sail_latex_riscv/overloadMzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex @@ -0,0 +1 @@ +overload operator - = {sub_atom, sub_int} diff --git a/sail_latex_riscv/overloadNNNNNNNNNNNNNNNNNz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadNNNNNNNNNNNNNNNNNz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..bc36ec62 --- /dev/null +++ b/sail_latex_riscv/overloadNNNNNNNNNNNNNNNNNz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_SV48_Paddr_bits, _set_SV48_Paddr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNNNNNNNNNNNNNNz_mod_vpni3dea7adc47f37ae733dae17ca8f9a4fe.tex b/sail_latex_riscv/overloadNNNNNNNNNNNNNNNNz_mod_vpni3dea7adc47f37ae733dae17ca8f9a4fe.tex new file mode 100644 index 00000000..83516a2c --- /dev/null +++ b/sail_latex_riscv/overloadNNNNNNNNNNNNNNNNz_mod_vpni3dea7adc47f37ae733dae17ca8f9a4fe.tex @@ -0,0 +1 @@ +overload _mod_VPNi = {_get_SV39_Vaddr_VPNi, _set_SV39_Vaddr_VPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNNNNNNNNNNNNNzupdate_capread56ae6dad86051d18043217916904fc13.tex b/sail_latex_riscv/overloadNNNNNNNNNNNNNNNzupdate_capread56ae6dad86051d18043217916904fc13.tex new file mode 100644 index 00000000..10527341 --- /dev/null +++ b/sail_latex_riscv/overloadNNNNNNNNNNNNNNNzupdate_capread56ae6dad86051d18043217916904fc13.tex @@ -0,0 +1 @@ +overload update_CapRead = {_update_Ext_PTE_Bits_CapRead} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNNNNNNNNNNNNzupdate_cmdfa3836cfddf11c618c06ae9d2b47cd43.tex b/sail_latex_riscv/overloadNNNNNNNNNNNNNNzupdate_cmdfa3836cfddf11c618c06ae9d2b47cd43.tex new file mode 100644 index 00000000..6e229442 --- /dev/null +++ b/sail_latex_riscv/overloadNNNNNNNNNNNNNNzupdate_cmdfa3836cfddf11c618c06ae9d2b47cd43.tex @@ -0,0 +1 @@ +overload update_cmd = {_update_htif_cmd_cmd} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNNNNNNNNNNNzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadNNNNNNNNNNNNNzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..da511cf6 --- /dev/null +++ b/sail_latex_riscv/overloadNNNNNNNNNNNNNzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Ustatus_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNNNNNNNNNNzupdate_ppn97bb9a526eb6125397ee215b375879df.tex b/sail_latex_riscv/overloadNNNNNNNNNNNNzupdate_ppn97bb9a526eb6125397ee215b375879df.tex new file mode 100644 index 00000000..fdf7e3a4 --- /dev/null +++ b/sail_latex_riscv/overloadNNNNNNNNNNNNzupdate_ppn97bb9a526eb6125397ee215b375879df.tex @@ -0,0 +1 @@ +overload update_PPN = {_update_Satp32_PPN} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNNNNNNNNNzupdate_seif1998ef482e23699637a58efcff9cf08.tex b/sail_latex_riscv/overloadNNNNNNNNNNNzupdate_seif1998ef482e23699637a58efcff9cf08.tex new file mode 100644 index 00000000..1ddcc343 --- /dev/null +++ b/sail_latex_riscv/overloadNNNNNNNNNNNzupdate_seif1998ef482e23699637a58efcff9cf08.tex @@ -0,0 +1 @@ +overload update_SEI = {_update_Sinterrupts_SEI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNNNNNNNNzupdate_sie1b2ed07072361c44e9ce7a8ca87b5555.tex b/sail_latex_riscv/overloadNNNNNNNNNNzupdate_sie1b2ed07072361c44e9ce7a8ca87b5555.tex new file mode 100644 index 00000000..38e08692 --- /dev/null +++ b/sail_latex_riscv/overloadNNNNNNNNNNzupdate_sie1b2ed07072361c44e9ce7a8ca87b5555.tex @@ -0,0 +1 @@ +overload update_SIE = {_update_Sstatus_SIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNNNNNNNzupdate_cyac1485e867c8bc776a140060ffab1295.tex b/sail_latex_riscv/overloadNNNNNNNNNzupdate_cyac1485e867c8bc776a140060ffab1295.tex new file mode 100644 index 00000000..2bea46d6 --- /dev/null +++ b/sail_latex_riscv/overloadNNNNNNNNNzupdate_cyac1485e867c8bc776a140060ffab1295.tex @@ -0,0 +1 @@ +overload update_CY = {_update_Counteren_CY} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNNNNNNzupdate_illegal_instr455fc8a1f0aa354556519de0f7b2c27b.tex b/sail_latex_riscv/overloadNNNNNNNNzupdate_illegal_instr455fc8a1f0aa354556519de0f7b2c27b.tex new file mode 100644 index 00000000..4a9afe54 --- /dev/null +++ b/sail_latex_riscv/overloadNNNNNNNNzupdate_illegal_instr455fc8a1f0aa354556519de0f7b2c27b.tex @@ -0,0 +1 @@ +overload update_Illegal_Instr = {_update_Medeleg_Illegal_Instr} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNNNNNzupdate_usi3c691c58ab628cbd10b9e21b62e0cfc4.tex b/sail_latex_riscv/overloadNNNNNNNzupdate_usi3c691c58ab628cbd10b9e21b62e0cfc4.tex new file mode 100644 index 00000000..5b63a19b --- /dev/null +++ b/sail_latex_riscv/overloadNNNNNNNzupdate_usi3c691c58ab628cbd10b9e21b62e0cfc4.tex @@ -0,0 +1 @@ +overload update_USI = {_update_Minterrupts_USI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNNNNzupdate_upiea5ad86a550536087d757a5582d1a8bb9.tex b/sail_latex_riscv/overloadNNNNNNzupdate_upiea5ad86a550536087d757a5582d1a8bb9.tex new file mode 100644 index 00000000..1f89b238 --- /dev/null +++ b/sail_latex_riscv/overloadNNNNNNzupdate_upiea5ad86a550536087d757a5582d1a8bb9.tex @@ -0,0 +1 @@ +overload update_UPIE = {_update_Mstatus_UPIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNNNzupdate_sd5d9e90ac938aa12ac2bdb01a3c3d6e92.tex b/sail_latex_riscv/overloadNNNNNzupdate_sd5d9e90ac938aa12ac2bdb01a3c3d6e92.tex new file mode 100644 index 00000000..b7bb578a --- /dev/null +++ b/sail_latex_riscv/overloadNNNNNzupdate_sd5d9e90ac938aa12ac2bdb01a3c3d6e92.tex @@ -0,0 +1 @@ +overload update_SD = {_update_Mstatus_SD} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNNzupdate_l18c2828f8e56660ea058db7889463318.tex b/sail_latex_riscv/overloadNNNNzupdate_l18c2828f8e56660ea058db7889463318.tex new file mode 100644 index 00000000..d20055b5 --- /dev/null +++ b/sail_latex_riscv/overloadNNNNzupdate_l18c2828f8e56660ea058db7889463318.tex @@ -0,0 +1 @@ +overload update_L = {_update_Misa_L} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNNzupdate_y18932cf4e3dad22b55782b0d44c2a5ed.tex b/sail_latex_riscv/overloadNNNzupdate_y18932cf4e3dad22b55782b0d44c2a5ed.tex new file mode 100644 index 00000000..ec5219d6 --- /dev/null +++ b/sail_latex_riscv/overloadNNNzupdate_y18932cf4e3dad22b55782b0d44c2a5ed.tex @@ -0,0 +1 @@ +overload update_Y = {_update_Misa_Y} \ No newline at end of file diff --git a/sail_latex_riscv/overloadNNzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex b/sail_latex_riscv/overloadNNzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex new file mode 100644 index 00000000..0bb9bf01 --- /dev/null +++ b/sail_latex_riscv/overloadNNzz8operatorz0zuz99af95b281314726fa91893b57fc290dc.tex @@ -0,0 +1 @@ +overload operator | = {or_vec} diff --git a/sail_latex_riscv/overloadNznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex b/sail_latex_riscv/overloadNznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex new file mode 100644 index 00000000..335dc856 --- /dev/null +++ b/sail_latex_riscv/overloadNznegatef5714e2e9cd970a9cb8b7c6fdf3732b8.tex @@ -0,0 +1 @@ +overload negate = {negate_atom, negate_int} diff --git a/sail_latex_riscv/overloadOOOOOOOOOOOOOOOOOzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex b/sail_latex_riscv/overloadOOOOOOOOOOOOOOOOOzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex new file mode 100644 index 00000000..befd5dc5 --- /dev/null +++ b/sail_latex_riscv/overloadOOOOOOOOOOOOOOOOOzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex @@ -0,0 +1 @@ +overload update_PPNi = {_update_SV48_Paddr_PPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOOOOOOOOOOOOOOzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex b/sail_latex_riscv/overloadOOOOOOOOOOOOOOOOzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex new file mode 100644 index 00000000..f0c334c5 --- /dev/null +++ b/sail_latex_riscv/overloadOOOOOOOOOOOOOOOOzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex @@ -0,0 +1 @@ +overload update_PgOfs = {_update_SV39_Vaddr_PgOfs} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOOOOOOOOOOOOOz_mod_capread786e2e18dc372ac62966150177d60d05.tex b/sail_latex_riscv/overloadOOOOOOOOOOOOOOOz_mod_capread786e2e18dc372ac62966150177d60d05.tex new file mode 100644 index 00000000..56f4d1b0 --- /dev/null +++ b/sail_latex_riscv/overloadOOOOOOOOOOOOOOOz_mod_capread786e2e18dc372ac62966150177d60d05.tex @@ -0,0 +1 @@ +overload _mod_CapRead = {_get_Ext_PTE_Bits_CapRead, _set_Ext_PTE_Bits_CapRead} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOOOOOOOOOOOOz_mod_cmda78881afb278208f2e0a03703f92acc3.tex b/sail_latex_riscv/overloadOOOOOOOOOOOOOOz_mod_cmda78881afb278208f2e0a03703f92acc3.tex new file mode 100644 index 00000000..96d3004d --- /dev/null +++ b/sail_latex_riscv/overloadOOOOOOOOOOOOOOz_mod_cmda78881afb278208f2e0a03703f92acc3.tex @@ -0,0 +1 @@ +overload _mod_cmd = {_get_htif_cmd_cmd, _set_htif_cmd_cmd} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOOOOOOOOOOOz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadOOOOOOOOOOOOOz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..a2fc4930 --- /dev/null +++ b/sail_latex_riscv/overloadOOOOOOOOOOOOOz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Ustatus_bits, _set_Ustatus_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOOOOOOOOOOz_mod_ppne431ce60abd1029c297cc5814bcb183d.tex b/sail_latex_riscv/overloadOOOOOOOOOOOOz_mod_ppne431ce60abd1029c297cc5814bcb183d.tex new file mode 100644 index 00000000..2c2125f7 --- /dev/null +++ b/sail_latex_riscv/overloadOOOOOOOOOOOOz_mod_ppne431ce60abd1029c297cc5814bcb183d.tex @@ -0,0 +1 @@ +overload _mod_PPN = {_get_Satp32_PPN, _set_Satp32_PPN} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOOOOOOOOOz_mod_sei769b57e17c0057e7ca956b7721915a2e.tex b/sail_latex_riscv/overloadOOOOOOOOOOOz_mod_sei769b57e17c0057e7ca956b7721915a2e.tex new file mode 100644 index 00000000..1c5c38fe --- /dev/null +++ b/sail_latex_riscv/overloadOOOOOOOOOOOz_mod_sei769b57e17c0057e7ca956b7721915a2e.tex @@ -0,0 +1 @@ +overload _mod_SEI = {_get_Sinterrupts_SEI, _set_Sinterrupts_SEI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOOOOOOOOz_mod_sieea56e4c7d22bb7c198ba004deeb422c9.tex b/sail_latex_riscv/overloadOOOOOOOOOOz_mod_sieea56e4c7d22bb7c198ba004deeb422c9.tex new file mode 100644 index 00000000..f7e3ad31 --- /dev/null +++ b/sail_latex_riscv/overloadOOOOOOOOOOz_mod_sieea56e4c7d22bb7c198ba004deeb422c9.tex @@ -0,0 +1 @@ +overload _mod_SIE = {_get_Sstatus_SIE, _set_Sstatus_SIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOOOOOOOz_mod_cy5609ca9870deee70dd1ee99cfdfb0c0d.tex b/sail_latex_riscv/overloadOOOOOOOOOz_mod_cy5609ca9870deee70dd1ee99cfdfb0c0d.tex new file mode 100644 index 00000000..ee14521b --- /dev/null +++ b/sail_latex_riscv/overloadOOOOOOOOOz_mod_cy5609ca9870deee70dd1ee99cfdfb0c0d.tex @@ -0,0 +1 @@ +overload _mod_CY = {_get_Counteren_CY, _set_Counteren_CY} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOOOOOOz_mod_illegal_instr52b43b228c609c9c311d02dfb920b702.tex b/sail_latex_riscv/overloadOOOOOOOOz_mod_illegal_instr52b43b228c609c9c311d02dfb920b702.tex new file mode 100644 index 00000000..9cce080e --- /dev/null +++ b/sail_latex_riscv/overloadOOOOOOOOz_mod_illegal_instr52b43b228c609c9c311d02dfb920b702.tex @@ -0,0 +1 @@ +overload _mod_Illegal_Instr = {_get_Medeleg_Illegal_Instr, _set_Medeleg_Illegal_Instr} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOOOOOz_mod_usif3c3aecb7417cc350ad372adfb40e4d3.tex b/sail_latex_riscv/overloadOOOOOOOz_mod_usif3c3aecb7417cc350ad372adfb40e4d3.tex new file mode 100644 index 00000000..679b88fb --- /dev/null +++ b/sail_latex_riscv/overloadOOOOOOOz_mod_usif3c3aecb7417cc350ad372adfb40e4d3.tex @@ -0,0 +1 @@ +overload _mod_USI = {_get_Minterrupts_USI, _set_Minterrupts_USI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOOOOz_mod_upie27f56ba53dc72f512e0a128ab616ba83.tex b/sail_latex_riscv/overloadOOOOOOz_mod_upie27f56ba53dc72f512e0a128ab616ba83.tex new file mode 100644 index 00000000..76aa108c --- /dev/null +++ b/sail_latex_riscv/overloadOOOOOOz_mod_upie27f56ba53dc72f512e0a128ab616ba83.tex @@ -0,0 +1 @@ +overload _mod_UPIE = {_get_Mstatus_UPIE, _set_Mstatus_UPIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOOOz_mod_sd1e51a771a9b628b657ecbb1ba7aa8f7c.tex b/sail_latex_riscv/overloadOOOOOz_mod_sd1e51a771a9b628b657ecbb1ba7aa8f7c.tex new file mode 100644 index 00000000..a0cb3609 --- /dev/null +++ b/sail_latex_riscv/overloadOOOOOz_mod_sd1e51a771a9b628b657ecbb1ba7aa8f7c.tex @@ -0,0 +1 @@ +overload _mod_SD = {_get_Mstatus_SD, _set_Mstatus_SD} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOOz_mod_lac2bd336f003b6226e212aa9fd493ac8.tex b/sail_latex_riscv/overloadOOOOz_mod_lac2bd336f003b6226e212aa9fd493ac8.tex new file mode 100644 index 00000000..539fa912 --- /dev/null +++ b/sail_latex_riscv/overloadOOOOz_mod_lac2bd336f003b6226e212aa9fd493ac8.tex @@ -0,0 +1 @@ +overload _mod_L = {_get_Misa_L, _set_Misa_L} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOOz_mod_y4993b5018b9fa96b0a5a3dff5d778b09.tex b/sail_latex_riscv/overloadOOOz_mod_y4993b5018b9fa96b0a5a3dff5d778b09.tex new file mode 100644 index 00000000..0933a683 --- /dev/null +++ b/sail_latex_riscv/overloadOOOz_mod_y4993b5018b9fa96b0a5a3dff5d778b09.tex @@ -0,0 +1 @@ +overload _mod_Y = {_get_Misa_Y, _set_Misa_Y} \ No newline at end of file diff --git a/sail_latex_riscv/overloadOOzbitstr0d04da018975c4776e05a9c59c2e380e.tex b/sail_latex_riscv/overloadOOzbitstr0d04da018975c4776e05a9c59c2e380e.tex new file mode 100644 index 00000000..b02b827e --- /dev/null +++ b/sail_latex_riscv/overloadOOzbitstr0d04da018975c4776e05a9c59c2e380e.tex @@ -0,0 +1 @@ +overload BitStr = {string_of_bits, string_of_bit} diff --git a/sail_latex_riscv/overloadOzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex b/sail_latex_riscv/overloadOzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex new file mode 100644 index 00000000..9e2c8c85 --- /dev/null +++ b/sail_latex_riscv/overloadOzz8operatorz0zaz94d99df7698c53c990108e8f028c06211.tex @@ -0,0 +1 @@ +overload operator * = {mult_atom, mult_int} diff --git a/sail_latex_riscv/overloadPPPPPPPPPPPPPPPPPz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex b/sail_latex_riscv/overloadPPPPPPPPPPPPPPPPPz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex new file mode 100644 index 00000000..b1bd6380 --- /dev/null +++ b/sail_latex_riscv/overloadPPPPPPPPPPPPPPPPPz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex @@ -0,0 +1 @@ +overload _mod_PPNi = {_get_SV48_Paddr_PPNi, _set_SV48_Paddr_PPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPPPPPPPPPPPPPPPz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex b/sail_latex_riscv/overloadPPPPPPPPPPPPPPPPz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex new file mode 100644 index 00000000..040a74b7 --- /dev/null +++ b/sail_latex_riscv/overloadPPPPPPPPPPPPPPPPz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex @@ -0,0 +1 @@ +overload _mod_PgOfs = {_get_SV39_Vaddr_PgOfs, _set_SV39_Vaddr_PgOfs} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPPPPPPPPPPPPPPzto_str8b7a6895ae35945bd4740e9f790c43ee.tex b/sail_latex_riscv/overloadPPPPPPPPPPPPPPPzto_str8b7a6895ae35945bd4740e9f790c43ee.tex new file mode 100644 index 00000000..ed3de958 --- /dev/null +++ b/sail_latex_riscv/overloadPPPPPPPPPPPPPPPzto_str8b7a6895ae35945bd4740e9f790c43ee.tex @@ -0,0 +1 @@ +overload to_str = {ptw_error_to_str} diff --git a/sail_latex_riscv/overloadPPPPPPPPPPPPPPzupdate_payload1cd3e49aac00ade7b567c8c5fce6bd11.tex b/sail_latex_riscv/overloadPPPPPPPPPPPPPPzupdate_payload1cd3e49aac00ade7b567c8c5fce6bd11.tex new file mode 100644 index 00000000..282483a9 --- /dev/null +++ b/sail_latex_riscv/overloadPPPPPPPPPPPPPPzupdate_payload1cd3e49aac00ade7b567c8c5fce6bd11.tex @@ -0,0 +1 @@ +overload update_payload = {_update_htif_cmd_payload} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPPPPPPPPPPPPzupdate_upiea5ad86a550536087d757a5582d1a8bb9.tex b/sail_latex_riscv/overloadPPPPPPPPPPPPPzupdate_upiea5ad86a550536087d757a5582d1a8bb9.tex new file mode 100644 index 00000000..3b2faae6 --- /dev/null +++ b/sail_latex_riscv/overloadPPPPPPPPPPPPPzupdate_upiea5ad86a550536087d757a5582d1a8bb9.tex @@ -0,0 +1 @@ +overload update_UPIE = {_update_Ustatus_UPIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPPPPPPPPPPPzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadPPPPPPPPPPPPzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..e618997e --- /dev/null +++ b/sail_latex_riscv/overloadPPPPPPPPPPPPzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Pmpcfg_ent_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPPPPPPPPPPzupdate_uei8252f0ae84161aa560a37211f39d1461.tex b/sail_latex_riscv/overloadPPPPPPPPPPPzupdate_uei8252f0ae84161aa560a37211f39d1461.tex new file mode 100644 index 00000000..582a5c35 --- /dev/null +++ b/sail_latex_riscv/overloadPPPPPPPPPPPzupdate_uei8252f0ae84161aa560a37211f39d1461.tex @@ -0,0 +1 @@ +overload update_UEI = {_update_Sinterrupts_UEI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPPPPPPPPPzupdate_uied194e7b32c7c54d35dfc1b602b4b5907.tex b/sail_latex_riscv/overloadPPPPPPPPPPzupdate_uied194e7b32c7c54d35dfc1b602b4b5907.tex new file mode 100644 index 00000000..68f96c77 --- /dev/null +++ b/sail_latex_riscv/overloadPPPPPPPPPPzupdate_uied194e7b32c7c54d35dfc1b602b4b5907.tex @@ -0,0 +1 @@ +overload update_UIE = {_update_Sstatus_UIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPPPPPPPPzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadPPPPPPPPPzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..91796d48 --- /dev/null +++ b/sail_latex_riscv/overloadPPPPPPPPPzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Counterin_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPPPPPPPzupdate_fetch_access_faultf6d3ea38a5b206db76f3d15e6b293e4e.tex b/sail_latex_riscv/overloadPPPPPPPPzupdate_fetch_access_faultf6d3ea38a5b206db76f3d15e6b293e4e.tex new file mode 100644 index 00000000..8e4189f7 --- /dev/null +++ b/sail_latex_riscv/overloadPPPPPPPPzupdate_fetch_access_faultf6d3ea38a5b206db76f3d15e6b293e4e.tex @@ -0,0 +1 @@ +overload update_Fetch_Access_Fault = {_update_Medeleg_Fetch_Access_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPPPPPPzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadPPPPPPPzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..6a69eea8 --- /dev/null +++ b/sail_latex_riscv/overloadPPPPPPPzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Medeleg_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPPPPPzupdate_mie814cfc4975c3e1f41026c234060b84d3.tex b/sail_latex_riscv/overloadPPPPPPzupdate_mie814cfc4975c3e1f41026c234060b84d3.tex new file mode 100644 index 00000000..392e9e93 --- /dev/null +++ b/sail_latex_riscv/overloadPPPPPPzupdate_mie814cfc4975c3e1f41026c234060b84d3.tex @@ -0,0 +1 @@ +overload update_MIE = {_update_Mstatus_MIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPPPPzupdate_tsr6f4c30747be8b86521f24a17848f44f8.tex b/sail_latex_riscv/overloadPPPPPzupdate_tsr6f4c30747be8b86521f24a17848f44f8.tex new file mode 100644 index 00000000..3993d1f7 --- /dev/null +++ b/sail_latex_riscv/overloadPPPPPzupdate_tsr6f4c30747be8b86521f24a17848f44f8.tex @@ -0,0 +1 @@ +overload update_TSR = {_update_Mstatus_TSR} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPPPzupdate_k022206cce3b142160f729d7bf95e8a36.tex b/sail_latex_riscv/overloadPPPPzupdate_k022206cce3b142160f729d7bf95e8a36.tex new file mode 100644 index 00000000..1eadef3b --- /dev/null +++ b/sail_latex_riscv/overloadPPPPzupdate_k022206cce3b142160f729d7bf95e8a36.tex @@ -0,0 +1 @@ +overload update_K = {_update_Misa_K} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPPzupdate_x647abdeca7ac108f059148e19df0452e.tex b/sail_latex_riscv/overloadPPPzupdate_x647abdeca7ac108f059148e19df0452e.tex new file mode 100644 index 00000000..1cd69272 --- /dev/null +++ b/sail_latex_riscv/overloadPPPzupdate_x647abdeca7ac108f059148e19df0452e.tex @@ -0,0 +1 @@ +overload update_X = {_update_Misa_X} \ No newline at end of file diff --git a/sail_latex_riscv/overloadPPzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex b/sail_latex_riscv/overloadPPzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex new file mode 100644 index 00000000..5de31eee --- /dev/null +++ b/sail_latex_riscv/overloadPPzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex @@ -0,0 +1 @@ +overload operator ^ = {xor_vec, int_power, concat_str} diff --git a/sail_latex_riscv/overloadPzshl_int4772030e3fc0913189e795ec25e86dc5.tex b/sail_latex_riscv/overloadPzshl_int4772030e3fc0913189e795ec25e86dc5.tex new file mode 100644 index 00000000..0aba6dd2 --- /dev/null +++ b/sail_latex_riscv/overloadPzshl_int4772030e3fc0913189e795ec25e86dc5.tex @@ -0,0 +1 @@ +overload shl_int = {_shl1, _shl8, _shl32, _shl_int} diff --git a/sail_latex_riscv/overloadQQQQQQQQQQQQQQQQQzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex b/sail_latex_riscv/overloadQQQQQQQQQQQQQQQQQzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex new file mode 100644 index 00000000..62ad3d54 --- /dev/null +++ b/sail_latex_riscv/overloadQQQQQQQQQQQQQQQQQzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex @@ -0,0 +1 @@ +overload update_PgOfs = {_update_SV48_Paddr_PgOfs} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQQQQQQQQQQQQQQzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadQQQQQQQQQQQQQQQQzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..233d1104 --- /dev/null +++ b/sail_latex_riscv/overloadQQQQQQQQQQQQQQQQzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_SV39_Paddr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQQQQQQQQQQQQQzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadQQQQQQQQQQQQQQQzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..7fcd0390 --- /dev/null +++ b/sail_latex_riscv/overloadQQQQQQQQQQQQQQQzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_SV32_Vaddr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQQQQQQQQQQQQz_mod_payload7f7d1a64858e00d9a581ddd7341ee771.tex b/sail_latex_riscv/overloadQQQQQQQQQQQQQQz_mod_payload7f7d1a64858e00d9a581ddd7341ee771.tex new file mode 100644 index 00000000..5a92328c --- /dev/null +++ b/sail_latex_riscv/overloadQQQQQQQQQQQQQQz_mod_payload7f7d1a64858e00d9a581ddd7341ee771.tex @@ -0,0 +1 @@ +overload _mod_payload = {_get_htif_cmd_payload, _set_htif_cmd_payload} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQQQQQQQQQQQz_mod_upie27f56ba53dc72f512e0a128ab616ba83.tex b/sail_latex_riscv/overloadQQQQQQQQQQQQQz_mod_upie27f56ba53dc72f512e0a128ab616ba83.tex new file mode 100644 index 00000000..aa6f7b68 --- /dev/null +++ b/sail_latex_riscv/overloadQQQQQQQQQQQQQz_mod_upie27f56ba53dc72f512e0a128ab616ba83.tex @@ -0,0 +1 @@ +overload _mod_UPIE = {_get_Ustatus_UPIE, _set_Ustatus_UPIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQQQQQQQQQQz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadQQQQQQQQQQQQz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..b7189fcf --- /dev/null +++ b/sail_latex_riscv/overloadQQQQQQQQQQQQz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Pmpcfg_ent_bits, _set_Pmpcfg_ent_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQQQQQQQQQz_mod_uei7faef47ef8aacd0d1b2ad1e0530fdf8e.tex b/sail_latex_riscv/overloadQQQQQQQQQQQz_mod_uei7faef47ef8aacd0d1b2ad1e0530fdf8e.tex new file mode 100644 index 00000000..b27e7ab8 --- /dev/null +++ b/sail_latex_riscv/overloadQQQQQQQQQQQz_mod_uei7faef47ef8aacd0d1b2ad1e0530fdf8e.tex @@ -0,0 +1 @@ +overload _mod_UEI = {_get_Sinterrupts_UEI, _set_Sinterrupts_UEI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQQQQQQQQz_mod_uie18b8fe18a506d4c612ff106c8cc5fb23.tex b/sail_latex_riscv/overloadQQQQQQQQQQz_mod_uie18b8fe18a506d4c612ff106c8cc5fb23.tex new file mode 100644 index 00000000..e2f6cc03 --- /dev/null +++ b/sail_latex_riscv/overloadQQQQQQQQQQz_mod_uie18b8fe18a506d4c612ff106c8cc5fb23.tex @@ -0,0 +1 @@ +overload _mod_UIE = {_get_Sstatus_UIE, _set_Sstatus_UIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQQQQQQQz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadQQQQQQQQQz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..ac831d27 --- /dev/null +++ b/sail_latex_riscv/overloadQQQQQQQQQz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Counterin_bits, _set_Counterin_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQQQQQQz_mod_fetch_access_fault2d0b00483619a1a634b37492d7e87b39.tex b/sail_latex_riscv/overloadQQQQQQQQz_mod_fetch_access_fault2d0b00483619a1a634b37492d7e87b39.tex new file mode 100644 index 00000000..6d887011 --- /dev/null +++ b/sail_latex_riscv/overloadQQQQQQQQz_mod_fetch_access_fault2d0b00483619a1a634b37492d7e87b39.tex @@ -0,0 +1 @@ +overload _mod_Fetch_Access_Fault = {_get_Medeleg_Fetch_Access_Fault, _set_Medeleg_Fetch_Access_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQQQQQz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadQQQQQQQz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..c9ac2a3e --- /dev/null +++ b/sail_latex_riscv/overloadQQQQQQQz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Medeleg_bits, _set_Medeleg_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQQQQz_mod_mie44478e86e68d533e6e7ad86bf6100f17.tex b/sail_latex_riscv/overloadQQQQQQz_mod_mie44478e86e68d533e6e7ad86bf6100f17.tex new file mode 100644 index 00000000..c8b8de6f --- /dev/null +++ b/sail_latex_riscv/overloadQQQQQQz_mod_mie44478e86e68d533e6e7ad86bf6100f17.tex @@ -0,0 +1 @@ +overload _mod_MIE = {_get_Mstatus_MIE, _set_Mstatus_MIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQQQz_mod_tsr0f7b8b3a1051c941d7b36c26a6689899.tex b/sail_latex_riscv/overloadQQQQQz_mod_tsr0f7b8b3a1051c941d7b36c26a6689899.tex new file mode 100644 index 00000000..267f346c --- /dev/null +++ b/sail_latex_riscv/overloadQQQQQz_mod_tsr0f7b8b3a1051c941d7b36c26a6689899.tex @@ -0,0 +1 @@ +overload _mod_TSR = {_get_Mstatus_TSR, _set_Mstatus_TSR} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQQz_mod_k2815acab0d1e9758841eb69be2dec6b4.tex b/sail_latex_riscv/overloadQQQQz_mod_k2815acab0d1e9758841eb69be2dec6b4.tex new file mode 100644 index 00000000..c2d3f17d --- /dev/null +++ b/sail_latex_riscv/overloadQQQQz_mod_k2815acab0d1e9758841eb69be2dec6b4.tex @@ -0,0 +1 @@ +overload _mod_K = {_get_Misa_K, _set_Misa_K} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQQz_mod_xc906d7554de3b79cd0cc78501a562587.tex b/sail_latex_riscv/overloadQQQz_mod_xc906d7554de3b79cd0cc78501a562587.tex new file mode 100644 index 00000000..aa3c7057 --- /dev/null +++ b/sail_latex_riscv/overloadQQQz_mod_xc906d7554de3b79cd0cc78501a562587.tex @@ -0,0 +1 @@ +overload _mod_X = {_get_Misa_X, _set_Misa_X} \ No newline at end of file diff --git a/sail_latex_riscv/overloadQQzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex b/sail_latex_riscv/overloadQQzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex new file mode 100644 index 00000000..6d748094 --- /dev/null +++ b/sail_latex_riscv/overloadQQzz8operatorz0zdz9aaaae29f381509679e21c2555127a5dd.tex @@ -0,0 +1 @@ +overload operator - = {sub_vec, sub_vec_int} diff --git a/sail_latex_riscv/overloadQzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex b/sail_latex_riscv/overloadQzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex new file mode 100644 index 00000000..be2ecb2a --- /dev/null +++ b/sail_latex_riscv/overloadQzshr_int5f4032eb21b9c850a9e2a8de5872a2a2.tex @@ -0,0 +1 @@ +overload shr_int = {_shr32, _shr_int} diff --git a/sail_latex_riscv/overloadRRRRRRRRRRRRRRRRRz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex b/sail_latex_riscv/overloadRRRRRRRRRRRRRRRRRz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex new file mode 100644 index 00000000..2448d04b --- /dev/null +++ b/sail_latex_riscv/overloadRRRRRRRRRRRRRRRRRz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex @@ -0,0 +1 @@ +overload _mod_PgOfs = {_get_SV48_Paddr_PgOfs, _set_SV48_Paddr_PgOfs} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRRRRRRRRRRRRRRz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadRRRRRRRRRRRRRRRRz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..8ecc0f49 --- /dev/null +++ b/sail_latex_riscv/overloadRRRRRRRRRRRRRRRRz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_SV39_Paddr_bits, _set_SV39_Paddr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRRRRRRRRRRRRRz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadRRRRRRRRRRRRRRRz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..09e9eba2 --- /dev/null +++ b/sail_latex_riscv/overloadRRRRRRRRRRRRRRRz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_SV32_Vaddr_bits, _set_SV32_Vaddr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRRRRRRRRRRRRzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadRRRRRRRRRRRRRRzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..5d2910ea --- /dev/null +++ b/sail_latex_riscv/overloadRRRRRRRRRRRRRRzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_PTE_Bits_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRRRRRRRRRRRzupdate_uied194e7b32c7c54d35dfc1b602b4b5907.tex b/sail_latex_riscv/overloadRRRRRRRRRRRRRzupdate_uied194e7b32c7c54d35dfc1b602b4b5907.tex new file mode 100644 index 00000000..70dfece2 --- /dev/null +++ b/sail_latex_riscv/overloadRRRRRRRRRRRRRzupdate_uied194e7b32c7c54d35dfc1b602b4b5907.tex @@ -0,0 +1 @@ +overload update_UIE = {_update_Ustatus_UIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRRRRRRRRRRzupdate_l18c2828f8e56660ea058db7889463318.tex b/sail_latex_riscv/overloadRRRRRRRRRRRRzupdate_l18c2828f8e56660ea058db7889463318.tex new file mode 100644 index 00000000..f9e3bc8d --- /dev/null +++ b/sail_latex_riscv/overloadRRRRRRRRRRRRzupdate_l18c2828f8e56660ea058db7889463318.tex @@ -0,0 +1 @@ +overload update_L = {_update_Pmpcfg_ent_L} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRRRRRRRRRzupdate_stibc2608b6e320f416ad08499be50228f8.tex b/sail_latex_riscv/overloadRRRRRRRRRRRzupdate_stibc2608b6e320f416ad08499be50228f8.tex new file mode 100644 index 00000000..fa773459 --- /dev/null +++ b/sail_latex_riscv/overloadRRRRRRRRRRRzupdate_stibc2608b6e320f416ad08499be50228f8.tex @@ -0,0 +1 @@ +overload update_STI = {_update_Sinterrupts_STI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRRRRRRRRzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadRRRRRRRRRRzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..2e445549 --- /dev/null +++ b/sail_latex_riscv/overloadRRRRRRRRRRzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Sedeleg_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRRRRRRRzupdate_ir0515bd19fecd95b93762d149f033240a.tex b/sail_latex_riscv/overloadRRRRRRRRRzupdate_ir0515bd19fecd95b93762d149f033240a.tex new file mode 100644 index 00000000..c131e470 --- /dev/null +++ b/sail_latex_riscv/overloadRRRRRRRRRzupdate_ir0515bd19fecd95b93762d149f033240a.tex @@ -0,0 +1 @@ +overload update_IR = {_update_Counterin_IR} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRRRRRRzupdate_fetch_addr_aligned5113ea584423e01fcb4b2781a3aeab.tex b/sail_latex_riscv/overloadRRRRRRRRzupdate_fetch_addr_aligned5113ea584423e01fcb4b2781a3aeab.tex new file mode 100644 index 00000000..869247a0 --- /dev/null +++ b/sail_latex_riscv/overloadRRRRRRRRzupdate_fetch_addr_aligned5113ea584423e01fcb4b2781a3aeab.tex @@ -0,0 +1 @@ +overload update_Fetch_Addr_Align = {_update_Medeleg_Fetch_Addr_Align} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRRRRRzupdate_samo_page_fault0e0044848164a2453737385b443e2a1d.tex b/sail_latex_riscv/overloadRRRRRRRzupdate_samo_page_fault0e0044848164a2453737385b443e2a1d.tex new file mode 100644 index 00000000..a12080ce --- /dev/null +++ b/sail_latex_riscv/overloadRRRRRRRzupdate_samo_page_fault0e0044848164a2453737385b443e2a1d.tex @@ -0,0 +1 @@ +overload update_SAMO_Page_Fault = {_update_Medeleg_SAMO_Page_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRRRRzupdate_sie1b2ed07072361c44e9ce7a8ca87b5555.tex b/sail_latex_riscv/overloadRRRRRRzupdate_sie1b2ed07072361c44e9ce7a8ca87b5555.tex new file mode 100644 index 00000000..5860b9c5 --- /dev/null +++ b/sail_latex_riscv/overloadRRRRRRzupdate_sie1b2ed07072361c44e9ce7a8ca87b5555.tex @@ -0,0 +1 @@ +overload update_SIE = {_update_Mstatus_SIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRRRzupdate_tw5ee4f2da170269d4a859283d302b33bb.tex b/sail_latex_riscv/overloadRRRRRzupdate_tw5ee4f2da170269d4a859283d302b33bb.tex new file mode 100644 index 00000000..3494970b --- /dev/null +++ b/sail_latex_riscv/overloadRRRRRzupdate_tw5ee4f2da170269d4a859283d302b33bb.tex @@ -0,0 +1 @@ +overload update_TW = {_update_Mstatus_TW} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRRzupdate_j42315d8e5eeed615464c6d7cd92ba743.tex b/sail_latex_riscv/overloadRRRRzupdate_j42315d8e5eeed615464c6d7cd92ba743.tex new file mode 100644 index 00000000..be68ddb0 --- /dev/null +++ b/sail_latex_riscv/overloadRRRRzupdate_j42315d8e5eeed615464c6d7cd92ba743.tex @@ -0,0 +1 @@ +overload update_J = {_update_Misa_J} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRRzupdate_w3209efc3cdd41bbc0810494fad257f06.tex b/sail_latex_riscv/overloadRRRzupdate_w3209efc3cdd41bbc0810494fad257f06.tex new file mode 100644 index 00000000..e834a611 --- /dev/null +++ b/sail_latex_riscv/overloadRRRzupdate_w3209efc3cdd41bbc0810494fad257f06.tex @@ -0,0 +1 @@ +overload update_W = {_update_Misa_W} \ No newline at end of file diff --git a/sail_latex_riscv/overloadRRzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex b/sail_latex_riscv/overloadRRzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex new file mode 100644 index 00000000..df6e19c0 --- /dev/null +++ b/sail_latex_riscv/overloadRRzz8operatorz0z5z9194a289f0ceb02e29c9b6febc5146071.tex @@ -0,0 +1 @@ +overload operator % = {emod_int, mod} diff --git a/sail_latex_riscv/overloadRztmod_int76b131b53b88df8b201279295eacebbe.tex b/sail_latex_riscv/overloadRztmod_int76b131b53b88df8b201279295eacebbe.tex new file mode 100644 index 00000000..7a8e2210 --- /dev/null +++ b/sail_latex_riscv/overloadRztmod_int76b131b53b88df8b201279295eacebbe.tex @@ -0,0 +1 @@ +overload tmod_int = {_tmod_int_positive, _tmod_int} diff --git a/sail_latex_riscv/overloadSSSSSSSSSSSSSSSSSzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadSSSSSSSSSSSSSSSSSzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..65317c4d --- /dev/null +++ b/sail_latex_riscv/overloadSSSSSSSSSSSSSSSSSzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_SV48_PTE_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSSSSSSSSSSSSSSzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex b/sail_latex_riscv/overloadSSSSSSSSSSSSSSSSzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex new file mode 100644 index 00000000..b2e94409 --- /dev/null +++ b/sail_latex_riscv/overloadSSSSSSSSSSSSSSSSzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex @@ -0,0 +1 @@ +overload update_PPNi = {_update_SV39_Paddr_PPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSSSSSSSSSSSSSzupdate_vpni561962844c1733722e96cd548b134172.tex b/sail_latex_riscv/overloadSSSSSSSSSSSSSSSzupdate_vpni561962844c1733722e96cd548b134172.tex new file mode 100644 index 00000000..b875c7b6 --- /dev/null +++ b/sail_latex_riscv/overloadSSSSSSSSSSSSSSSzupdate_vpni561962844c1733722e96cd548b134172.tex @@ -0,0 +1 @@ +overload update_VPNi = {_update_SV32_Vaddr_VPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSSSSSSSSSSSSz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadSSSSSSSSSSSSSSz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..4874a4f0 --- /dev/null +++ b/sail_latex_riscv/overloadSSSSSSSSSSSSSSz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_PTE_Bits_bits, _set_PTE_Bits_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSSSSSSSSSSSz_mod_uie18b8fe18a506d4c612ff106c8cc5fb23.tex b/sail_latex_riscv/overloadSSSSSSSSSSSSSz_mod_uie18b8fe18a506d4c612ff106c8cc5fb23.tex new file mode 100644 index 00000000..90f8c4f5 --- /dev/null +++ b/sail_latex_riscv/overloadSSSSSSSSSSSSSz_mod_uie18b8fe18a506d4c612ff106c8cc5fb23.tex @@ -0,0 +1 @@ +overload _mod_UIE = {_get_Ustatus_UIE, _set_Ustatus_UIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSSSSSSSSSSz_mod_lac2bd336f003b6226e212aa9fd493ac8.tex b/sail_latex_riscv/overloadSSSSSSSSSSSSz_mod_lac2bd336f003b6226e212aa9fd493ac8.tex new file mode 100644 index 00000000..b139f9db --- /dev/null +++ b/sail_latex_riscv/overloadSSSSSSSSSSSSz_mod_lac2bd336f003b6226e212aa9fd493ac8.tex @@ -0,0 +1 @@ +overload _mod_L = {_get_Pmpcfg_ent_L, _set_Pmpcfg_ent_L} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSSSSSSSSSz_mod_sti42df95a06ca2a120a19277cb17015a3f.tex b/sail_latex_riscv/overloadSSSSSSSSSSSz_mod_sti42df95a06ca2a120a19277cb17015a3f.tex new file mode 100644 index 00000000..6ab460f0 --- /dev/null +++ b/sail_latex_riscv/overloadSSSSSSSSSSSz_mod_sti42df95a06ca2a120a19277cb17015a3f.tex @@ -0,0 +1 @@ +overload _mod_STI = {_get_Sinterrupts_STI, _set_Sinterrupts_STI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSSSSSSSSz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadSSSSSSSSSSz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..2d3b8a1e --- /dev/null +++ b/sail_latex_riscv/overloadSSSSSSSSSSz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Sedeleg_bits, _set_Sedeleg_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSSSSSSSz_mod_ira44a158ed08eebfa24118152fd099692.tex b/sail_latex_riscv/overloadSSSSSSSSSz_mod_ira44a158ed08eebfa24118152fd099692.tex new file mode 100644 index 00000000..2a533634 --- /dev/null +++ b/sail_latex_riscv/overloadSSSSSSSSSz_mod_ira44a158ed08eebfa24118152fd099692.tex @@ -0,0 +1 @@ +overload _mod_IR = {_get_Counterin_IR, _set_Counterin_IR} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSSSSSSz_mod_fetch_addr_align94e1ec62c225ae16e8fbc401efa25352.tex b/sail_latex_riscv/overloadSSSSSSSSz_mod_fetch_addr_align94e1ec62c225ae16e8fbc401efa25352.tex new file mode 100644 index 00000000..4d780b58 --- /dev/null +++ b/sail_latex_riscv/overloadSSSSSSSSz_mod_fetch_addr_align94e1ec62c225ae16e8fbc401efa25352.tex @@ -0,0 +1 @@ +overload _mod_Fetch_Addr_Align = {_get_Medeleg_Fetch_Addr_Align, _set_Medeleg_Fetch_Addr_Align} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSSSSSz_mod_samo_page_fault43d7b42a58e066e14279c19346f8aa6e.tex b/sail_latex_riscv/overloadSSSSSSSz_mod_samo_page_fault43d7b42a58e066e14279c19346f8aa6e.tex new file mode 100644 index 00000000..b412a30f --- /dev/null +++ b/sail_latex_riscv/overloadSSSSSSSz_mod_samo_page_fault43d7b42a58e066e14279c19346f8aa6e.tex @@ -0,0 +1 @@ +overload _mod_SAMO_Page_Fault = {_get_Medeleg_SAMO_Page_Fault, _set_Medeleg_SAMO_Page_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSSSSz_mod_sieea56e4c7d22bb7c198ba004deeb422c9.tex b/sail_latex_riscv/overloadSSSSSSz_mod_sieea56e4c7d22bb7c198ba004deeb422c9.tex new file mode 100644 index 00000000..ef261d05 --- /dev/null +++ b/sail_latex_riscv/overloadSSSSSSz_mod_sieea56e4c7d22bb7c198ba004deeb422c9.tex @@ -0,0 +1 @@ +overload _mod_SIE = {_get_Mstatus_SIE, _set_Mstatus_SIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSSSz_mod_twd51a94299168a627db8ea29496d4ea83.tex b/sail_latex_riscv/overloadSSSSSz_mod_twd51a94299168a627db8ea29496d4ea83.tex new file mode 100644 index 00000000..21bab69a --- /dev/null +++ b/sail_latex_riscv/overloadSSSSSz_mod_twd51a94299168a627db8ea29496d4ea83.tex @@ -0,0 +1 @@ +overload _mod_TW = {_get_Mstatus_TW, _set_Mstatus_TW} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSSz_mod_j99da9691d0d08dd9802e57459c1a645b.tex b/sail_latex_riscv/overloadSSSSz_mod_j99da9691d0d08dd9802e57459c1a645b.tex new file mode 100644 index 00000000..d688c647 --- /dev/null +++ b/sail_latex_riscv/overloadSSSSz_mod_j99da9691d0d08dd9802e57459c1a645b.tex @@ -0,0 +1 @@ +overload _mod_J = {_get_Misa_J, _set_Misa_J} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSSz_mod_w196183ee717bdd84cd7d5e4b2af0b219.tex b/sail_latex_riscv/overloadSSSz_mod_w196183ee717bdd84cd7d5e4b2af0b219.tex new file mode 100644 index 00000000..977c3b9e --- /dev/null +++ b/sail_latex_riscv/overloadSSSz_mod_w196183ee717bdd84cd7d5e4b2af0b219.tex @@ -0,0 +1 @@ +overload _mod_W = {_get_Misa_W, _set_Misa_W} \ No newline at end of file diff --git a/sail_latex_riscv/overloadSSzmin95ae3c0ebde1421750e6db87bdf74801.tex b/sail_latex_riscv/overloadSSzmin95ae3c0ebde1421750e6db87bdf74801.tex new file mode 100644 index 00000000..677fc619 --- /dev/null +++ b/sail_latex_riscv/overloadSSzmin95ae3c0ebde1421750e6db87bdf74801.tex @@ -0,0 +1 @@ +overload min = {min_int} diff --git a/sail_latex_riscv/overloadSzabs_intef5fbb521189282054dc80dc7173013d.tex b/sail_latex_riscv/overloadSzabs_intef5fbb521189282054dc80dc7173013d.tex new file mode 100644 index 00000000..6598a227 --- /dev/null +++ b/sail_latex_riscv/overloadSzabs_intef5fbb521189282054dc80dc7173013d.tex @@ -0,0 +1 @@ +overload abs_int = {abs_int_plain} diff --git a/sail_latex_riscv/overloadTTTTTTTTTTTTTTTTTz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadTTTTTTTTTTTTTTTTTz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..0fbe36aa --- /dev/null +++ b/sail_latex_riscv/overloadTTTTTTTTTTTTTTTTTz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_SV48_PTE_bits, _set_SV48_PTE_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTTTTTTTTTTTTTTz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex b/sail_latex_riscv/overloadTTTTTTTTTTTTTTTTz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex new file mode 100644 index 00000000..36b47e44 --- /dev/null +++ b/sail_latex_riscv/overloadTTTTTTTTTTTTTTTTz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex @@ -0,0 +1 @@ +overload _mod_PPNi = {_get_SV39_Paddr_PPNi, _set_SV39_Paddr_PPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTTTTTTTTTTTTTz_mod_vpni3dea7adc47f37ae733dae17ca8f9a4fe.tex b/sail_latex_riscv/overloadTTTTTTTTTTTTTTTz_mod_vpni3dea7adc47f37ae733dae17ca8f9a4fe.tex new file mode 100644 index 00000000..68d4fc09 --- /dev/null +++ b/sail_latex_riscv/overloadTTTTTTTTTTTTTTTz_mod_vpni3dea7adc47f37ae733dae17ca8f9a4fe.tex @@ -0,0 +1 @@ +overload _mod_VPNi = {_get_SV32_Vaddr_VPNi, _set_SV32_Vaddr_VPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTTTTTTTTTTTTzupdate_da9201c8a6710e680d16238f3581a0227.tex b/sail_latex_riscv/overloadTTTTTTTTTTTTTTzupdate_da9201c8a6710e680d16238f3581a0227.tex new file mode 100644 index 00000000..10432908 --- /dev/null +++ b/sail_latex_riscv/overloadTTTTTTTTTTTTTTzupdate_da9201c8a6710e680d16238f3581a0227.tex @@ -0,0 +1 @@ +overload update_D = {_update_PTE_Bits_D} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTTTTTTTTTTTzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadTTTTTTTTTTTTTzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..86b9384f --- /dev/null +++ b/sail_latex_riscv/overloadTTTTTTTTTTTTTzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Uinterrupts_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTTTTTTTTTTzupdate_ab740c1f378b55b3328b2a9f25ff6c1cf.tex b/sail_latex_riscv/overloadTTTTTTTTTTTTzupdate_ab740c1f378b55b3328b2a9f25ff6c1cf.tex new file mode 100644 index 00000000..6d6f68ff --- /dev/null +++ b/sail_latex_riscv/overloadTTTTTTTTTTTTzupdate_ab740c1f378b55b3328b2a9f25ff6c1cf.tex @@ -0,0 +1 @@ +overload update_A = {_update_Pmpcfg_ent_A} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTTTTTTTTTzupdate_uti7bb127f84633c2b4f4b4de5582168ddf.tex b/sail_latex_riscv/overloadTTTTTTTTTTTzupdate_uti7bb127f84633c2b4f4b4de5582168ddf.tex new file mode 100644 index 00000000..81e37204 --- /dev/null +++ b/sail_latex_riscv/overloadTTTTTTTTTTTzupdate_uti7bb127f84633c2b4f4b4de5582168ddf.tex @@ -0,0 +1 @@ +overload update_UTI = {_update_Sinterrupts_UTI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTTTTTTTTzupdate_uenvcall1a8e9c082fb9f272d5370bee121f426d.tex b/sail_latex_riscv/overloadTTTTTTTTTTzupdate_uenvcall1a8e9c082fb9f272d5370bee121f426d.tex new file mode 100644 index 00000000..07e727c1 --- /dev/null +++ b/sail_latex_riscv/overloadTTTTTTTTTTzupdate_uenvcall1a8e9c082fb9f272d5370bee121f426d.tex @@ -0,0 +1 @@ +overload update_UEnvCall = {_update_Sedeleg_UEnvCall} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTTTTTTTzupdate_cyac1485e867c8bc776a140060ffab1295.tex b/sail_latex_riscv/overloadTTTTTTTTTzupdate_cyac1485e867c8bc776a140060ffab1295.tex new file mode 100644 index 00000000..46ebfdff --- /dev/null +++ b/sail_latex_riscv/overloadTTTTTTTTTzupdate_cyac1485e867c8bc776a140060ffab1295.tex @@ -0,0 +1 @@ +overload update_CY = {_update_Counterin_CY} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTTTTTTzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadTTTTTTTTzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..15a55b80 --- /dev/null +++ b/sail_latex_riscv/overloadTTTTTTTTzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Mtvec_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTTTTTzupdate_load_page_faultf0e55e39dc6672c621900ae1f5aaf5c8.tex b/sail_latex_riscv/overloadTTTTTTTzupdate_load_page_faultf0e55e39dc6672c621900ae1f5aaf5c8.tex new file mode 100644 index 00000000..16bb1620 --- /dev/null +++ b/sail_latex_riscv/overloadTTTTTTTzupdate_load_page_faultf0e55e39dc6672c621900ae1f5aaf5c8.tex @@ -0,0 +1 @@ +overload update_Load_Page_Fault = {_update_Medeleg_Load_Page_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTTTTzupdate_uied194e7b32c7c54d35dfc1b602b4b5907.tex b/sail_latex_riscv/overloadTTTTTTzupdate_uied194e7b32c7c54d35dfc1b602b4b5907.tex new file mode 100644 index 00000000..4c3af722 --- /dev/null +++ b/sail_latex_riscv/overloadTTTTTTzupdate_uied194e7b32c7c54d35dfc1b602b4b5907.tex @@ -0,0 +1 @@ +overload update_UIE = {_update_Mstatus_UIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTTTzupdate_tvm7e1e43bb3e8b7c252211bd33016cce23.tex b/sail_latex_riscv/overloadTTTTTzupdate_tvm7e1e43bb3e8b7c252211bd33016cce23.tex new file mode 100644 index 00000000..34b17a8a --- /dev/null +++ b/sail_latex_riscv/overloadTTTTTzupdate_tvm7e1e43bb3e8b7c252211bd33016cce23.tex @@ -0,0 +1 @@ +overload update_TVM = {_update_Mstatus_TVM} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTTzupdate_i23ad4da3401bf9554e20a8c3f705fe00.tex b/sail_latex_riscv/overloadTTTTzupdate_i23ad4da3401bf9554e20a8c3f705fe00.tex new file mode 100644 index 00000000..9b455472 --- /dev/null +++ b/sail_latex_riscv/overloadTTTTzupdate_i23ad4da3401bf9554e20a8c3f705fe00.tex @@ -0,0 +1 @@ +overload update_I = {_update_Misa_I} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTTzupdate_v550d76e01b2aee2bcdcdd8fcb788e6ae.tex b/sail_latex_riscv/overloadTTTzupdate_v550d76e01b2aee2bcdcdd8fcb788e6ae.tex new file mode 100644 index 00000000..388c0239 --- /dev/null +++ b/sail_latex_riscv/overloadTTTzupdate_v550d76e01b2aee2bcdcdd8fcb788e6ae.tex @@ -0,0 +1 @@ +overload update_V = {_update_Misa_V} \ No newline at end of file diff --git a/sail_latex_riscv/overloadTTzmax91b641c464c0dc87660499321a356d93.tex b/sail_latex_riscv/overloadTTzmax91b641c464c0dc87660499321a356d93.tex new file mode 100644 index 00000000..a957c4dd --- /dev/null +++ b/sail_latex_riscv/overloadTTzmax91b641c464c0dc87660499321a356d93.tex @@ -0,0 +1 @@ +overload max = {max_int} diff --git a/sail_latex_riscv/overloadTzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_riscv/overloadTzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex new file mode 100644 index 00000000..b5ecaaae --- /dev/null +++ b/sail_latex_riscv/overloadTzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex @@ -0,0 +1 @@ +overload operator == = {eq_string} diff --git a/sail_latex_riscv/overloadUUUUUUUUUUUUUUUUUzupdate_ext4723b679799a58fbdda2ba5058faef53.tex b/sail_latex_riscv/overloadUUUUUUUUUUUUUUUUUzupdate_ext4723b679799a58fbdda2ba5058faef53.tex new file mode 100644 index 00000000..3b324348 --- /dev/null +++ b/sail_latex_riscv/overloadUUUUUUUUUUUUUUUUUzupdate_ext4723b679799a58fbdda2ba5058faef53.tex @@ -0,0 +1 @@ +overload update_Ext = {_update_SV48_PTE_Ext} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUUUUUUUUUUUUUUzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex b/sail_latex_riscv/overloadUUUUUUUUUUUUUUUUzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex new file mode 100644 index 00000000..20441b86 --- /dev/null +++ b/sail_latex_riscv/overloadUUUUUUUUUUUUUUUUzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex @@ -0,0 +1 @@ +overload update_PgOfs = {_update_SV39_Paddr_PgOfs} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUUUUUUUUUUUUUzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex b/sail_latex_riscv/overloadUUUUUUUUUUUUUUUzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex new file mode 100644 index 00000000..9c71a063 --- /dev/null +++ b/sail_latex_riscv/overloadUUUUUUUUUUUUUUUzupdate_pgofs254c91319ab1d3e50b8917244b8212b1.tex @@ -0,0 +1 @@ +overload update_PgOfs = {_update_SV32_Vaddr_PgOfs} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUUUUUUUUUUUUz_mod_d8c29507d9735e49d608a373bd2e2c599.tex b/sail_latex_riscv/overloadUUUUUUUUUUUUUUz_mod_d8c29507d9735e49d608a373bd2e2c599.tex new file mode 100644 index 00000000..548e77c6 --- /dev/null +++ b/sail_latex_riscv/overloadUUUUUUUUUUUUUUz_mod_d8c29507d9735e49d608a373bd2e2c599.tex @@ -0,0 +1 @@ +overload _mod_D = {_get_PTE_Bits_D, _set_PTE_Bits_D} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUUUUUUUUUUUz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadUUUUUUUUUUUUUz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..7d2aafd2 --- /dev/null +++ b/sail_latex_riscv/overloadUUUUUUUUUUUUUz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Uinterrupts_bits, _set_Uinterrupts_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUUUUUUUUUUz_mod_a62a6f88676512d98a363811f9f5ba327.tex b/sail_latex_riscv/overloadUUUUUUUUUUUUz_mod_a62a6f88676512d98a363811f9f5ba327.tex new file mode 100644 index 00000000..bb7df79e --- /dev/null +++ b/sail_latex_riscv/overloadUUUUUUUUUUUUz_mod_a62a6f88676512d98a363811f9f5ba327.tex @@ -0,0 +1 @@ +overload _mod_A = {_get_Pmpcfg_ent_A, _set_Pmpcfg_ent_A} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUUUUUUUUUz_mod_utia23224af950fbe7be4b3db2f7092e6b4.tex b/sail_latex_riscv/overloadUUUUUUUUUUUz_mod_utia23224af950fbe7be4b3db2f7092e6b4.tex new file mode 100644 index 00000000..1c0a67a2 --- /dev/null +++ b/sail_latex_riscv/overloadUUUUUUUUUUUz_mod_utia23224af950fbe7be4b3db2f7092e6b4.tex @@ -0,0 +1 @@ +overload _mod_UTI = {_get_Sinterrupts_UTI, _set_Sinterrupts_UTI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUUUUUUUUz_mod_uenvcall837e3a85bd98d15f2f4b32f9230ddef6.tex b/sail_latex_riscv/overloadUUUUUUUUUUz_mod_uenvcall837e3a85bd98d15f2f4b32f9230ddef6.tex new file mode 100644 index 00000000..f7d377dc --- /dev/null +++ b/sail_latex_riscv/overloadUUUUUUUUUUz_mod_uenvcall837e3a85bd98d15f2f4b32f9230ddef6.tex @@ -0,0 +1 @@ +overload _mod_UEnvCall = {_get_Sedeleg_UEnvCall, _set_Sedeleg_UEnvCall} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUUUUUUUz_mod_cy5609ca9870deee70dd1ee99cfdfb0c0d.tex b/sail_latex_riscv/overloadUUUUUUUUUz_mod_cy5609ca9870deee70dd1ee99cfdfb0c0d.tex new file mode 100644 index 00000000..779c1cce --- /dev/null +++ b/sail_latex_riscv/overloadUUUUUUUUUz_mod_cy5609ca9870deee70dd1ee99cfdfb0c0d.tex @@ -0,0 +1 @@ +overload _mod_CY = {_get_Counterin_CY, _set_Counterin_CY} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUUUUUUz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadUUUUUUUUz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..14d1fda9 --- /dev/null +++ b/sail_latex_riscv/overloadUUUUUUUUz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Mtvec_bits, _set_Mtvec_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUUUUUz_mod_load_page_fault57094f7526c1aa35d9aef0746403aba6.tex b/sail_latex_riscv/overloadUUUUUUUz_mod_load_page_fault57094f7526c1aa35d9aef0746403aba6.tex new file mode 100644 index 00000000..34a0327c --- /dev/null +++ b/sail_latex_riscv/overloadUUUUUUUz_mod_load_page_fault57094f7526c1aa35d9aef0746403aba6.tex @@ -0,0 +1 @@ +overload _mod_Load_Page_Fault = {_get_Medeleg_Load_Page_Fault, _set_Medeleg_Load_Page_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUUUUz_mod_uie18b8fe18a506d4c612ff106c8cc5fb23.tex b/sail_latex_riscv/overloadUUUUUUz_mod_uie18b8fe18a506d4c612ff106c8cc5fb23.tex new file mode 100644 index 00000000..9f16b751 --- /dev/null +++ b/sail_latex_riscv/overloadUUUUUUz_mod_uie18b8fe18a506d4c612ff106c8cc5fb23.tex @@ -0,0 +1 @@ +overload _mod_UIE = {_get_Mstatus_UIE, _set_Mstatus_UIE} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUUUz_mod_tvm115bf3a71837868b1ca1b42515d8bf97.tex b/sail_latex_riscv/overloadUUUUUz_mod_tvm115bf3a71837868b1ca1b42515d8bf97.tex new file mode 100644 index 00000000..729b2af5 --- /dev/null +++ b/sail_latex_riscv/overloadUUUUUz_mod_tvm115bf3a71837868b1ca1b42515d8bf97.tex @@ -0,0 +1 @@ +overload _mod_TVM = {_get_Mstatus_TVM, _set_Mstatus_TVM} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUUz_mod_i10672a4f5733dfdc7d432fb5c80c7e42.tex b/sail_latex_riscv/overloadUUUUz_mod_i10672a4f5733dfdc7d432fb5c80c7e42.tex new file mode 100644 index 00000000..3706a3c8 --- /dev/null +++ b/sail_latex_riscv/overloadUUUUz_mod_i10672a4f5733dfdc7d432fb5c80c7e42.tex @@ -0,0 +1 @@ +overload _mod_I = {_get_Misa_I, _set_Misa_I} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUUz_mod_v136fe7ecc31e11f2521faa02b71b57fa.tex b/sail_latex_riscv/overloadUUUz_mod_v136fe7ecc31e11f2521faa02b71b57fa.tex new file mode 100644 index 00000000..8263f860 --- /dev/null +++ b/sail_latex_riscv/overloadUUUz_mod_v136fe7ecc31e11f2521faa02b71b57fa.tex @@ -0,0 +1 @@ +overload _mod_V = {_get_Misa_V, _set_Misa_V} \ No newline at end of file diff --git a/sail_latex_riscv/overloadUUzzzerosc530711942e216cef3921733c1c5d101.tex b/sail_latex_riscv/overloadUUzzzerosc530711942e216cef3921733c1c5d101.tex new file mode 100644 index 00000000..75e3eb9e --- /dev/null +++ b/sail_latex_riscv/overloadUUzzzerosc530711942e216cef3921733c1c5d101.tex @@ -0,0 +1 @@ +overload zeros = {zeros_implicit} diff --git a/sail_latex_riscv/overloadUzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex b/sail_latex_riscv/overloadUzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex new file mode 100644 index 00000000..49daed5c --- /dev/null +++ b/sail_latex_riscv/overloadUzz8operatorz0zjzjz9c650f45e06411dd4e97578ff2bad6338.tex @@ -0,0 +1 @@ +overload operator == = {eq_bit, eq_bits} diff --git a/sail_latex_riscv/overloadVVVVVVVVVVVVVVVVVz_mod_extee31bbe7b534e72c2dacd0c25ba837ba.tex b/sail_latex_riscv/overloadVVVVVVVVVVVVVVVVVz_mod_extee31bbe7b534e72c2dacd0c25ba837ba.tex new file mode 100644 index 00000000..dd3d6418 --- /dev/null +++ b/sail_latex_riscv/overloadVVVVVVVVVVVVVVVVVz_mod_extee31bbe7b534e72c2dacd0c25ba837ba.tex @@ -0,0 +1 @@ +overload _mod_Ext = {_get_SV48_PTE_Ext, _set_SV48_PTE_Ext} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVVVVVVVVVVVVVVz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex b/sail_latex_riscv/overloadVVVVVVVVVVVVVVVVz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex new file mode 100644 index 00000000..a208f5dd --- /dev/null +++ b/sail_latex_riscv/overloadVVVVVVVVVVVVVVVVz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex @@ -0,0 +1 @@ +overload _mod_PgOfs = {_get_SV39_Paddr_PgOfs, _set_SV39_Paddr_PgOfs} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVVVVVVVVVVVVVz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex b/sail_latex_riscv/overloadVVVVVVVVVVVVVVVz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex new file mode 100644 index 00000000..0a11c768 --- /dev/null +++ b/sail_latex_riscv/overloadVVVVVVVVVVVVVVVz_mod_pgofs8292bb5b3acdf7a2cf33be55fc8c35fc.tex @@ -0,0 +1 @@ +overload _mod_PgOfs = {_get_SV32_Vaddr_PgOfs, _set_SV32_Vaddr_PgOfs} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVVVVVVVVVVVVzupdate_ab740c1f378b55b3328b2a9f25ff6c1cf.tex b/sail_latex_riscv/overloadVVVVVVVVVVVVVVzupdate_ab740c1f378b55b3328b2a9f25ff6c1cf.tex new file mode 100644 index 00000000..867495b0 --- /dev/null +++ b/sail_latex_riscv/overloadVVVVVVVVVVVVVVzupdate_ab740c1f378b55b3328b2a9f25ff6c1cf.tex @@ -0,0 +1 @@ +overload update_A = {_update_PTE_Bits_A} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVVVVVVVVVVVzupdate_uei8252f0ae84161aa560a37211f39d1461.tex b/sail_latex_riscv/overloadVVVVVVVVVVVVVzupdate_uei8252f0ae84161aa560a37211f39d1461.tex new file mode 100644 index 00000000..b795c067 --- /dev/null +++ b/sail_latex_riscv/overloadVVVVVVVVVVVVVzupdate_uei8252f0ae84161aa560a37211f39d1461.tex @@ -0,0 +1 @@ +overload update_UEI = {_update_Uinterrupts_UEI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVVVVVVVVVVzupdate_x647abdeca7ac108f059148e19df0452e.tex b/sail_latex_riscv/overloadVVVVVVVVVVVVzupdate_x647abdeca7ac108f059148e19df0452e.tex new file mode 100644 index 00000000..47a900a5 --- /dev/null +++ b/sail_latex_riscv/overloadVVVVVVVVVVVVzupdate_x647abdeca7ac108f059148e19df0452e.tex @@ -0,0 +1 @@ +overload update_X = {_update_Pmpcfg_ent_X} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVVVVVVVVVzupdate_ssi5471fd96e5b7a8471f1ef66b598501a9.tex b/sail_latex_riscv/overloadVVVVVVVVVVVzupdate_ssi5471fd96e5b7a8471f1ef66b598501a9.tex new file mode 100644 index 00000000..8a78898f --- /dev/null +++ b/sail_latex_riscv/overloadVVVVVVVVVVVzupdate_ssi5471fd96e5b7a8471f1ef66b598501a9.tex @@ -0,0 +1 @@ +overload update_SSI = {_update_Sinterrupts_SSI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVVVVVVVVzupdate_samo_access_faulte622f01b5ab60ce658092d165d64a4f9.tex b/sail_latex_riscv/overloadVVVVVVVVVVzupdate_samo_access_faulte622f01b5ab60ce658092d165d64a4f9.tex new file mode 100644 index 00000000..b91ef450 --- /dev/null +++ b/sail_latex_riscv/overloadVVVVVVVVVVzupdate_samo_access_faulte622f01b5ab60ce658092d165d64a4f9.tex @@ -0,0 +1 @@ +overload update_SAMO_Access_Fault = {_update_Sedeleg_SAMO_Access_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVVVVVVVzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadVVVVVVVVVzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..925d40cb --- /dev/null +++ b/sail_latex_riscv/overloadVVVVVVVVVzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Sstatus_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVVVVVVzupdate_basef3805d7e016e708f5f63a87f731f0265.tex b/sail_latex_riscv/overloadVVVVVVVVzupdate_basef3805d7e016e708f5f63a87f731f0265.tex new file mode 100644 index 00000000..ccd7dddd --- /dev/null +++ b/sail_latex_riscv/overloadVVVVVVVVzupdate_basef3805d7e016e708f5f63a87f731f0265.tex @@ -0,0 +1 @@ +overload update_Base = {_update_Mtvec_Base} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVVVVVzupdate_fetch_page_fault5db4cf0b8a31dd60d34e3f4575579bf6.tex b/sail_latex_riscv/overloadVVVVVVVzupdate_fetch_page_fault5db4cf0b8a31dd60d34e3f4575579bf6.tex new file mode 100644 index 00000000..386e08be --- /dev/null +++ b/sail_latex_riscv/overloadVVVVVVVzupdate_fetch_page_fault5db4cf0b8a31dd60d34e3f4575579bf6.tex @@ -0,0 +1 @@ +overload update_Fetch_Page_Fault = {_update_Medeleg_Fetch_Page_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVVVVzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadVVVVVVzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..c96dd653 --- /dev/null +++ b/sail_latex_riscv/overloadVVVVVVzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Minterrupts_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVVVzupdate_mxra54b3693fefa5d6b0301ff08e0ea5a3f.tex b/sail_latex_riscv/overloadVVVVVzupdate_mxra54b3693fefa5d6b0301ff08e0ea5a3f.tex new file mode 100644 index 00000000..e9eb4f34 --- /dev/null +++ b/sail_latex_riscv/overloadVVVVVzupdate_mxra54b3693fefa5d6b0301ff08e0ea5a3f.tex @@ -0,0 +1 @@ +overload update_MXR = {_update_Mstatus_MXR} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVVzupdate_hae56bacde98340a2d95ba3256bd8ada9.tex b/sail_latex_riscv/overloadVVVVzupdate_hae56bacde98340a2d95ba3256bd8ada9.tex new file mode 100644 index 00000000..af3065fe --- /dev/null +++ b/sail_latex_riscv/overloadVVVVzupdate_hae56bacde98340a2d95ba3256bd8ada9.tex @@ -0,0 +1 @@ +overload update_H = {_update_Misa_H} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVVzupdate_uf25457b59a73b45bf964c7ab354d043c.tex b/sail_latex_riscv/overloadVVVzupdate_uf25457b59a73b45bf964c7ab354d043c.tex new file mode 100644 index 00000000..1a94f517 --- /dev/null +++ b/sail_latex_riscv/overloadVVVzupdate_uf25457b59a73b45bf964c7ab354d043c.tex @@ -0,0 +1 @@ +overload update_U = {_update_Misa_U} \ No newline at end of file diff --git a/sail_latex_riscv/overloadVVzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex b/sail_latex_riscv/overloadVVzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex new file mode 100644 index 00000000..589b0b26 --- /dev/null +++ b/sail_latex_riscv/overloadVVzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex @@ -0,0 +1 @@ +overload operator >> = {shift_bits_right, shiftr} diff --git a/sail_latex_riscv/overloadVzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex b/sail_latex_riscv/overloadVzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex new file mode 100644 index 00000000..a97ec66d --- /dev/null +++ b/sail_latex_riscv/overloadVzz8operatorz0z1zjz981ebe433e26f9e2dfa2a9d2c7f4fe1f4.tex @@ -0,0 +1 @@ +overload operator != = {neq_bits} diff --git a/sail_latex_riscv/overloadWWWWWWWWWWWWWWWWWzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex b/sail_latex_riscv/overloadWWWWWWWWWWWWWWWWWzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex new file mode 100644 index 00000000..b64af95c --- /dev/null +++ b/sail_latex_riscv/overloadWWWWWWWWWWWWWWWWWzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex @@ -0,0 +1 @@ +overload update_PPNi = {_update_SV48_PTE_PPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWWWWWWWWWWWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadWWWWWWWWWWWWWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..e09366ef --- /dev/null +++ b/sail_latex_riscv/overloadWWWWWWWWWWWWWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_SV39_PTE_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWWWWWWWWWWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadWWWWWWWWWWWWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..7b1c7009 --- /dev/null +++ b/sail_latex_riscv/overloadWWWWWWWWWWWWWWWzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_SV32_Paddr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWWWWWWWWWWWWz_mod_a62a6f88676512d98a363811f9f5ba327.tex b/sail_latex_riscv/overloadWWWWWWWWWWWWWWz_mod_a62a6f88676512d98a363811f9f5ba327.tex new file mode 100644 index 00000000..88c95321 --- /dev/null +++ b/sail_latex_riscv/overloadWWWWWWWWWWWWWWz_mod_a62a6f88676512d98a363811f9f5ba327.tex @@ -0,0 +1 @@ +overload _mod_A = {_get_PTE_Bits_A, _set_PTE_Bits_A} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWWWWWWWWWWWz_mod_uei7faef47ef8aacd0d1b2ad1e0530fdf8e.tex b/sail_latex_riscv/overloadWWWWWWWWWWWWWz_mod_uei7faef47ef8aacd0d1b2ad1e0530fdf8e.tex new file mode 100644 index 00000000..33e0ceff --- /dev/null +++ b/sail_latex_riscv/overloadWWWWWWWWWWWWWz_mod_uei7faef47ef8aacd0d1b2ad1e0530fdf8e.tex @@ -0,0 +1 @@ +overload _mod_UEI = {_get_Uinterrupts_UEI, _set_Uinterrupts_UEI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWWWWWWWWWWz_mod_xc906d7554de3b79cd0cc78501a562587.tex b/sail_latex_riscv/overloadWWWWWWWWWWWWz_mod_xc906d7554de3b79cd0cc78501a562587.tex new file mode 100644 index 00000000..7b86c365 --- /dev/null +++ b/sail_latex_riscv/overloadWWWWWWWWWWWWz_mod_xc906d7554de3b79cd0cc78501a562587.tex @@ -0,0 +1 @@ +overload _mod_X = {_get_Pmpcfg_ent_X, _set_Pmpcfg_ent_X} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWWWWWWWWWz_mod_ssicb14ae48c26ad162228aa44069530c95.tex b/sail_latex_riscv/overloadWWWWWWWWWWWz_mod_ssicb14ae48c26ad162228aa44069530c95.tex new file mode 100644 index 00000000..93d4bf68 --- /dev/null +++ b/sail_latex_riscv/overloadWWWWWWWWWWWz_mod_ssicb14ae48c26ad162228aa44069530c95.tex @@ -0,0 +1 @@ +overload _mod_SSI = {_get_Sinterrupts_SSI, _set_Sinterrupts_SSI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWWWWWWWWz_mod_samo_access_faultef1cf7b1db2bf21d4e773b1a41ea8eea.tex b/sail_latex_riscv/overloadWWWWWWWWWWz_mod_samo_access_faultef1cf7b1db2bf21d4e773b1a41ea8eea.tex new file mode 100644 index 00000000..8e8f4275 --- /dev/null +++ b/sail_latex_riscv/overloadWWWWWWWWWWz_mod_samo_access_faultef1cf7b1db2bf21d4e773b1a41ea8eea.tex @@ -0,0 +1 @@ +overload _mod_SAMO_Access_Fault = {_get_Sedeleg_SAMO_Access_Fault, _set_Sedeleg_SAMO_Access_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWWWWWWWz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadWWWWWWWWWz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..61b17bfc --- /dev/null +++ b/sail_latex_riscv/overloadWWWWWWWWWz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Sstatus_bits, _set_Sstatus_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWWWWWWz_mod_base4044bc65e2dc6a7a9071ee2819432775.tex b/sail_latex_riscv/overloadWWWWWWWWz_mod_base4044bc65e2dc6a7a9071ee2819432775.tex new file mode 100644 index 00000000..b4d9cb6a --- /dev/null +++ b/sail_latex_riscv/overloadWWWWWWWWz_mod_base4044bc65e2dc6a7a9071ee2819432775.tex @@ -0,0 +1 @@ +overload _mod_Base = {_get_Mtvec_Base, _set_Mtvec_Base} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWWWWWz_mod_fetch_page_faulta754353f965dceb2b48b5c02d38fb070.tex b/sail_latex_riscv/overloadWWWWWWWz_mod_fetch_page_faulta754353f965dceb2b48b5c02d38fb070.tex new file mode 100644 index 00000000..ac645948 --- /dev/null +++ b/sail_latex_riscv/overloadWWWWWWWz_mod_fetch_page_faulta754353f965dceb2b48b5c02d38fb070.tex @@ -0,0 +1 @@ +overload _mod_Fetch_Page_Fault = {_get_Medeleg_Fetch_Page_Fault, _set_Medeleg_Fetch_Page_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWWWWz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadWWWWWWz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..40443c8c --- /dev/null +++ b/sail_latex_riscv/overloadWWWWWWz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_Minterrupts_bits, _set_Minterrupts_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWWWz_mod_mxr626efb0dadf77d402ea180eddd656377.tex b/sail_latex_riscv/overloadWWWWWz_mod_mxr626efb0dadf77d402ea180eddd656377.tex new file mode 100644 index 00000000..21dff356 --- /dev/null +++ b/sail_latex_riscv/overloadWWWWWz_mod_mxr626efb0dadf77d402ea180eddd656377.tex @@ -0,0 +1 @@ +overload _mod_MXR = {_get_Mstatus_MXR, _set_Mstatus_MXR} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWWz_mod_h49b48eb0876f788743697a82df15f831.tex b/sail_latex_riscv/overloadWWWWz_mod_h49b48eb0876f788743697a82df15f831.tex new file mode 100644 index 00000000..0527ed58 --- /dev/null +++ b/sail_latex_riscv/overloadWWWWz_mod_h49b48eb0876f788743697a82df15f831.tex @@ -0,0 +1 @@ +overload _mod_H = {_get_Misa_H, _set_Misa_H} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWWz_mod_u960ee5decf6c18ea57af0e0387ef7d9c.tex b/sail_latex_riscv/overloadWWWz_mod_u960ee5decf6c18ea57af0e0387ef7d9c.tex new file mode 100644 index 00000000..0f9e6ce6 --- /dev/null +++ b/sail_latex_riscv/overloadWWWz_mod_u960ee5decf6c18ea57af0e0387ef7d9c.tex @@ -0,0 +1 @@ +overload _mod_U = {_get_Misa_U, _set_Misa_U} \ No newline at end of file diff --git a/sail_latex_riscv/overloadWWzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex b/sail_latex_riscv/overloadWWzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex new file mode 100644 index 00000000..07b14b4f --- /dev/null +++ b/sail_latex_riscv/overloadWWzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex @@ -0,0 +1 @@ +overload operator << = {shift_bits_left, shiftl} diff --git a/sail_latex_riscv/overloadWzlength469e3f917f7b24f4691faf3caf842eba.tex b/sail_latex_riscv/overloadWzlength469e3f917f7b24f4691faf3caf842eba.tex new file mode 100644 index 00000000..bff07a35 --- /dev/null +++ b/sail_latex_riscv/overloadWzlength469e3f917f7b24f4691faf3caf842eba.tex @@ -0,0 +1 @@ +overload length = {bitvector_length, vector_length} diff --git a/sail_latex_riscv/overloadXXXXXXXXXXXXXXXXXz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex b/sail_latex_riscv/overloadXXXXXXXXXXXXXXXXXz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex new file mode 100644 index 00000000..d6cf73ab --- /dev/null +++ b/sail_latex_riscv/overloadXXXXXXXXXXXXXXXXXz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex @@ -0,0 +1 @@ +overload _mod_PPNi = {_get_SV48_PTE_PPNi, _set_SV48_PTE_PPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXXXXXXXXXXXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadXXXXXXXXXXXXXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..d8cff52e --- /dev/null +++ b/sail_latex_riscv/overloadXXXXXXXXXXXXXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_SV39_PTE_bits, _set_SV39_PTE_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXXXXXXXXXXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex b/sail_latex_riscv/overloadXXXXXXXXXXXXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex new file mode 100644 index 00000000..b77c3210 --- /dev/null +++ b/sail_latex_riscv/overloadXXXXXXXXXXXXXXXz_mod_bits34655d348b672c050c646beeecebb43d.tex @@ -0,0 +1 @@ +overload _mod_bits = {_get_SV32_Paddr_bits, _set_SV32_Paddr_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXXXXXXXXXXXXzupdate_ga61979e0097ae60f8598f57688dbae8b.tex b/sail_latex_riscv/overloadXXXXXXXXXXXXXXzupdate_ga61979e0097ae60f8598f57688dbae8b.tex new file mode 100644 index 00000000..e9de49cb --- /dev/null +++ b/sail_latex_riscv/overloadXXXXXXXXXXXXXXzupdate_ga61979e0097ae60f8598f57688dbae8b.tex @@ -0,0 +1 @@ +overload update_G = {_update_PTE_Bits_G} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXXXXXXXXXXXzupdate_uti7bb127f84633c2b4f4b4de5582168ddf.tex b/sail_latex_riscv/overloadXXXXXXXXXXXXXzupdate_uti7bb127f84633c2b4f4b4de5582168ddf.tex new file mode 100644 index 00000000..41fd9bb3 --- /dev/null +++ b/sail_latex_riscv/overloadXXXXXXXXXXXXXzupdate_uti7bb127f84633c2b4f4b4de5582168ddf.tex @@ -0,0 +1 @@ +overload update_UTI = {_update_Uinterrupts_UTI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXXXXXXXXXXzupdate_w3209efc3cdd41bbc0810494fad257f06.tex b/sail_latex_riscv/overloadXXXXXXXXXXXXzupdate_w3209efc3cdd41bbc0810494fad257f06.tex new file mode 100644 index 00000000..541ac96a --- /dev/null +++ b/sail_latex_riscv/overloadXXXXXXXXXXXXzupdate_w3209efc3cdd41bbc0810494fad257f06.tex @@ -0,0 +1 @@ +overload update_W = {_update_Pmpcfg_ent_W} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXXXXXXXXXzupdate_usi3c691c58ab628cbd10b9e21b62e0cfc4.tex b/sail_latex_riscv/overloadXXXXXXXXXXXzupdate_usi3c691c58ab628cbd10b9e21b62e0cfc4.tex new file mode 100644 index 00000000..55809f96 --- /dev/null +++ b/sail_latex_riscv/overloadXXXXXXXXXXXzupdate_usi3c691c58ab628cbd10b9e21b62e0cfc4.tex @@ -0,0 +1 @@ +overload update_USI = {_update_Sinterrupts_USI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXXXXXXXXzupdate_samo_addr_alignb6f17cfe030aff1cf9413eeaa67b67ee.tex b/sail_latex_riscv/overloadXXXXXXXXXXzupdate_samo_addr_alignb6f17cfe030aff1cf9413eeaa67b67ee.tex new file mode 100644 index 00000000..27fff6d2 --- /dev/null +++ b/sail_latex_riscv/overloadXXXXXXXXXXzupdate_samo_addr_alignb6f17cfe030aff1cf9413eeaa67b67ee.tex @@ -0,0 +1 @@ +overload update_SAMO_Addr_Align = {_update_Sedeleg_SAMO_Addr_Align} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXXXXXXXzupdate_sd5d9e90ac938aa12ac2bdb01a3c3d6e92.tex b/sail_latex_riscv/overloadXXXXXXXXXzupdate_sd5d9e90ac938aa12ac2bdb01a3c3d6e92.tex new file mode 100644 index 00000000..3d46284f --- /dev/null +++ b/sail_latex_riscv/overloadXXXXXXXXXzupdate_sd5d9e90ac938aa12ac2bdb01a3c3d6e92.tex @@ -0,0 +1 @@ +overload update_SD = {_update_Sstatus_SD} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXXXXXXzupdate_modea8b179bc2887fad34e9a3f8cefc9cf29.tex b/sail_latex_riscv/overloadXXXXXXXXzupdate_modea8b179bc2887fad34e9a3f8cefc9cf29.tex new file mode 100644 index 00000000..08bd3f97 --- /dev/null +++ b/sail_latex_riscv/overloadXXXXXXXXzupdate_modea8b179bc2887fad34e9a3f8cefc9cf29.tex @@ -0,0 +1 @@ +overload update_Mode = {_update_Mtvec_Mode} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXXXXXzupdate_menvcall5801f983231805c1edca0da644dd7884.tex b/sail_latex_riscv/overloadXXXXXXXzupdate_menvcall5801f983231805c1edca0da644dd7884.tex new file mode 100644 index 00000000..6f185ef7 --- /dev/null +++ b/sail_latex_riscv/overloadXXXXXXXzupdate_menvcall5801f983231805c1edca0da644dd7884.tex @@ -0,0 +1 @@ +overload update_MEnvCall = {_update_Medeleg_MEnvCall} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXXXXzupdate_mei397a1d801cdc3d609ba62d313a1c78b6.tex b/sail_latex_riscv/overloadXXXXXXzupdate_mei397a1d801cdc3d609ba62d313a1c78b6.tex new file mode 100644 index 00000000..6be49bce --- /dev/null +++ b/sail_latex_riscv/overloadXXXXXXzupdate_mei397a1d801cdc3d609ba62d313a1c78b6.tex @@ -0,0 +1 @@ +overload update_MEI = {_update_Minterrupts_MEI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXXXzupdate_sum45aaa4f77ddaa1e976bb9719406d8d4d.tex b/sail_latex_riscv/overloadXXXXXzupdate_sum45aaa4f77ddaa1e976bb9719406d8d4d.tex new file mode 100644 index 00000000..6df94f4b --- /dev/null +++ b/sail_latex_riscv/overloadXXXXXzupdate_sum45aaa4f77ddaa1e976bb9719406d8d4d.tex @@ -0,0 +1 @@ +overload update_SUM = {_update_Mstatus_SUM} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXXzupdate_ga61979e0097ae60f8598f57688dbae8b.tex b/sail_latex_riscv/overloadXXXXzupdate_ga61979e0097ae60f8598f57688dbae8b.tex new file mode 100644 index 00000000..36af2ac5 --- /dev/null +++ b/sail_latex_riscv/overloadXXXXzupdate_ga61979e0097ae60f8598f57688dbae8b.tex @@ -0,0 +1 @@ +overload update_G = {_update_Misa_G} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXXzupdate_t4387a59a7ca6dbd358923def3d05d452.tex b/sail_latex_riscv/overloadXXXzupdate_t4387a59a7ca6dbd358923def3d05d452.tex new file mode 100644 index 00000000..df9e2181 --- /dev/null +++ b/sail_latex_riscv/overloadXXXzupdate_t4387a59a7ca6dbd358923def3d05d452.tex @@ -0,0 +1 @@ +overload update_T = {_update_Misa_T} \ No newline at end of file diff --git a/sail_latex_riscv/overloadXXzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex b/sail_latex_riscv/overloadXXzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex new file mode 100644 index 00000000..b185d7de --- /dev/null +++ b/sail_latex_riscv/overloadXXzz8operatorz0zkzkz9e772b5e121d0113826739b52dbbce0f8.tex @@ -0,0 +1 @@ +overload operator >> = {sail_shiftright} diff --git a/sail_latex_riscv/overloadXzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex b/sail_latex_riscv/overloadXzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex new file mode 100644 index 00000000..eab71d1d --- /dev/null +++ b/sail_latex_riscv/overloadXzz8operatorz0zqz9ccbd65071d8f0fbb9677c7f6e86d3527.tex @@ -0,0 +1 @@ +overload operator ^ = {sail_mask} diff --git a/sail_latex_riscv/overloadYYYYYYYYYYYYYYYYYzupdate_rsw7e773e2fdd93d70f9490f8401b97d4e9.tex b/sail_latex_riscv/overloadYYYYYYYYYYYYYYYYYzupdate_rsw7e773e2fdd93d70f9490f8401b97d4e9.tex new file mode 100644 index 00000000..aec8c8f0 --- /dev/null +++ b/sail_latex_riscv/overloadYYYYYYYYYYYYYYYYYzupdate_rsw7e773e2fdd93d70f9490f8401b97d4e9.tex @@ -0,0 +1 @@ +overload update_RSW = {_update_SV48_PTE_RSW} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYYYYYYYYYYYYYYzupdate_ext4723b679799a58fbdda2ba5058faef53.tex b/sail_latex_riscv/overloadYYYYYYYYYYYYYYYYzupdate_ext4723b679799a58fbdda2ba5058faef53.tex new file mode 100644 index 00000000..e3563e55 --- /dev/null +++ b/sail_latex_riscv/overloadYYYYYYYYYYYYYYYYzupdate_ext4723b679799a58fbdda2ba5058faef53.tex @@ -0,0 +1 @@ +overload update_Ext = {_update_SV39_PTE_Ext} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYYYYYYYYYYYYYzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex b/sail_latex_riscv/overloadYYYYYYYYYYYYYYYzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex new file mode 100644 index 00000000..3a62c76b --- /dev/null +++ b/sail_latex_riscv/overloadYYYYYYYYYYYYYYYzupdate_ppnidfbfd9e0d78d5c191808ac3733f67562.tex @@ -0,0 +1 @@ +overload update_PPNi = {_update_SV32_Paddr_PPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYYYYYYYYYYYYz_mod_g521053c016cb3f20bf7b96843a7a2cf4.tex b/sail_latex_riscv/overloadYYYYYYYYYYYYYYz_mod_g521053c016cb3f20bf7b96843a7a2cf4.tex new file mode 100644 index 00000000..1a68e0c1 --- /dev/null +++ b/sail_latex_riscv/overloadYYYYYYYYYYYYYYz_mod_g521053c016cb3f20bf7b96843a7a2cf4.tex @@ -0,0 +1 @@ +overload _mod_G = {_get_PTE_Bits_G, _set_PTE_Bits_G} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYYYYYYYYYYYz_mod_utia23224af950fbe7be4b3db2f7092e6b4.tex b/sail_latex_riscv/overloadYYYYYYYYYYYYYz_mod_utia23224af950fbe7be4b3db2f7092e6b4.tex new file mode 100644 index 00000000..061bacc4 --- /dev/null +++ b/sail_latex_riscv/overloadYYYYYYYYYYYYYz_mod_utia23224af950fbe7be4b3db2f7092e6b4.tex @@ -0,0 +1 @@ +overload _mod_UTI = {_get_Uinterrupts_UTI, _set_Uinterrupts_UTI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYYYYYYYYYYz_mod_w196183ee717bdd84cd7d5e4b2af0b219.tex b/sail_latex_riscv/overloadYYYYYYYYYYYYz_mod_w196183ee717bdd84cd7d5e4b2af0b219.tex new file mode 100644 index 00000000..bb8b05b1 --- /dev/null +++ b/sail_latex_riscv/overloadYYYYYYYYYYYYz_mod_w196183ee717bdd84cd7d5e4b2af0b219.tex @@ -0,0 +1 @@ +overload _mod_W = {_get_Pmpcfg_ent_W, _set_Pmpcfg_ent_W} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYYYYYYYYYz_mod_usif3c3aecb7417cc350ad372adfb40e4d3.tex b/sail_latex_riscv/overloadYYYYYYYYYYYz_mod_usif3c3aecb7417cc350ad372adfb40e4d3.tex new file mode 100644 index 00000000..04f87d97 --- /dev/null +++ b/sail_latex_riscv/overloadYYYYYYYYYYYz_mod_usif3c3aecb7417cc350ad372adfb40e4d3.tex @@ -0,0 +1 @@ +overload _mod_USI = {_get_Sinterrupts_USI, _set_Sinterrupts_USI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYYYYYYYYz_mod_samo_addr_align71af067f49a8b506587ec718a5e1b7d2.tex b/sail_latex_riscv/overloadYYYYYYYYYYz_mod_samo_addr_align71af067f49a8b506587ec718a5e1b7d2.tex new file mode 100644 index 00000000..7994a08a --- /dev/null +++ b/sail_latex_riscv/overloadYYYYYYYYYYz_mod_samo_addr_align71af067f49a8b506587ec718a5e1b7d2.tex @@ -0,0 +1 @@ +overload _mod_SAMO_Addr_Align = {_get_Sedeleg_SAMO_Addr_Align, _set_Sedeleg_SAMO_Addr_Align} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYYYYYYYz_mod_sd1e51a771a9b628b657ecbb1ba7aa8f7c.tex b/sail_latex_riscv/overloadYYYYYYYYYz_mod_sd1e51a771a9b628b657ecbb1ba7aa8f7c.tex new file mode 100644 index 00000000..19e6b44a --- /dev/null +++ b/sail_latex_riscv/overloadYYYYYYYYYz_mod_sd1e51a771a9b628b657ecbb1ba7aa8f7c.tex @@ -0,0 +1 @@ +overload _mod_SD = {_get_Sstatus_SD, _set_Sstatus_SD} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYYYYYYz_mod_mode7dda808a114a5634018c73fc24f43140.tex b/sail_latex_riscv/overloadYYYYYYYYz_mod_mode7dda808a114a5634018c73fc24f43140.tex new file mode 100644 index 00000000..3aecde90 --- /dev/null +++ b/sail_latex_riscv/overloadYYYYYYYYz_mod_mode7dda808a114a5634018c73fc24f43140.tex @@ -0,0 +1 @@ +overload _mod_Mode = {_get_Mtvec_Mode, _set_Mtvec_Mode} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYYYYYz_mod_menvcall76e08341162761e8373fc048ddccb8c9.tex b/sail_latex_riscv/overloadYYYYYYYz_mod_menvcall76e08341162761e8373fc048ddccb8c9.tex new file mode 100644 index 00000000..326b9e33 --- /dev/null +++ b/sail_latex_riscv/overloadYYYYYYYz_mod_menvcall76e08341162761e8373fc048ddccb8c9.tex @@ -0,0 +1 @@ +overload _mod_MEnvCall = {_get_Medeleg_MEnvCall, _set_Medeleg_MEnvCall} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYYYYz_mod_meicf8fd69c57324173193cd468636980ed.tex b/sail_latex_riscv/overloadYYYYYYz_mod_meicf8fd69c57324173193cd468636980ed.tex new file mode 100644 index 00000000..8694be86 --- /dev/null +++ b/sail_latex_riscv/overloadYYYYYYz_mod_meicf8fd69c57324173193cd468636980ed.tex @@ -0,0 +1 @@ +overload _mod_MEI = {_get_Minterrupts_MEI, _set_Minterrupts_MEI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYYYz_mod_sum9c28eec9a0977f334c917bffeb75d7eb.tex b/sail_latex_riscv/overloadYYYYYz_mod_sum9c28eec9a0977f334c917bffeb75d7eb.tex new file mode 100644 index 00000000..c61f83b1 --- /dev/null +++ b/sail_latex_riscv/overloadYYYYYz_mod_sum9c28eec9a0977f334c917bffeb75d7eb.tex @@ -0,0 +1 @@ +overload _mod_SUM = {_get_Mstatus_SUM, _set_Mstatus_SUM} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYYz_mod_g521053c016cb3f20bf7b96843a7a2cf4.tex b/sail_latex_riscv/overloadYYYYz_mod_g521053c016cb3f20bf7b96843a7a2cf4.tex new file mode 100644 index 00000000..72e33088 --- /dev/null +++ b/sail_latex_riscv/overloadYYYYz_mod_g521053c016cb3f20bf7b96843a7a2cf4.tex @@ -0,0 +1 @@ +overload _mod_G = {_get_Misa_G, _set_Misa_G} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYYz_mod_t20863ac4eec1cefcdefe7f2e08aeb65b.tex b/sail_latex_riscv/overloadYYYz_mod_t20863ac4eec1cefcdefe7f2e08aeb65b.tex new file mode 100644 index 00000000..bd00f27a --- /dev/null +++ b/sail_latex_riscv/overloadYYYz_mod_t20863ac4eec1cefcdefe7f2e08aeb65b.tex @@ -0,0 +1 @@ +overload _mod_T = {_get_Misa_T, _set_Misa_T} \ No newline at end of file diff --git a/sail_latex_riscv/overloadYYzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex b/sail_latex_riscv/overloadYYzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex new file mode 100644 index 00000000..ac442b22 --- /dev/null +++ b/sail_latex_riscv/overloadYYzz8operatorz0ziziz90068ca3610cb726b2dddda4048ca7686.tex @@ -0,0 +1 @@ +overload operator << = {sail_shiftleft} diff --git a/sail_latex_riscv/overloadYzappend88575169e0ec1639b6ae3851df999710.tex b/sail_latex_riscv/overloadYzappend88575169e0ec1639b6ae3851df999710.tex new file mode 100644 index 00000000..4897992d --- /dev/null +++ b/sail_latex_riscv/overloadYzappend88575169e0ec1639b6ae3851df999710.tex @@ -0,0 +1 @@ +overload append = {bitvector_concat} diff --git a/sail_latex_riscv/overloadZZZZZZZZZZZZZZZZZz_mod_rswf4989a734cfde890cb5a1c8d3b4e6798.tex b/sail_latex_riscv/overloadZZZZZZZZZZZZZZZZZz_mod_rswf4989a734cfde890cb5a1c8d3b4e6798.tex new file mode 100644 index 00000000..3903f434 --- /dev/null +++ b/sail_latex_riscv/overloadZZZZZZZZZZZZZZZZZz_mod_rswf4989a734cfde890cb5a1c8d3b4e6798.tex @@ -0,0 +1 @@ +overload _mod_RSW = {_get_SV48_PTE_RSW, _set_SV48_PTE_RSW} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZZZZZZZZZZZZZZz_mod_extee31bbe7b534e72c2dacd0c25ba837ba.tex b/sail_latex_riscv/overloadZZZZZZZZZZZZZZZZz_mod_extee31bbe7b534e72c2dacd0c25ba837ba.tex new file mode 100644 index 00000000..aa7e4274 --- /dev/null +++ b/sail_latex_riscv/overloadZZZZZZZZZZZZZZZZz_mod_extee31bbe7b534e72c2dacd0c25ba837ba.tex @@ -0,0 +1 @@ +overload _mod_Ext = {_get_SV39_PTE_Ext, _set_SV39_PTE_Ext} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZZZZZZZZZZZZZz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex b/sail_latex_riscv/overloadZZZZZZZZZZZZZZZz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex new file mode 100644 index 00000000..5d13e3e8 --- /dev/null +++ b/sail_latex_riscv/overloadZZZZZZZZZZZZZZZz_mod_ppnia961e365785da7376cd7bdac208fd0ad.tex @@ -0,0 +1 @@ +overload _mod_PPNi = {_get_SV32_Paddr_PPNi, _set_SV32_Paddr_PPNi} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZZZZZZZZZZZZzupdate_uf25457b59a73b45bf964c7ab354d043c.tex b/sail_latex_riscv/overloadZZZZZZZZZZZZZZzupdate_uf25457b59a73b45bf964c7ab354d043c.tex new file mode 100644 index 00000000..3fec3934 --- /dev/null +++ b/sail_latex_riscv/overloadZZZZZZZZZZZZZZzupdate_uf25457b59a73b45bf964c7ab354d043c.tex @@ -0,0 +1 @@ +overload update_U = {_update_PTE_Bits_U} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZZZZZZZZZZZzupdate_usi3c691c58ab628cbd10b9e21b62e0cfc4.tex b/sail_latex_riscv/overloadZZZZZZZZZZZZZzupdate_usi3c691c58ab628cbd10b9e21b62e0cfc4.tex new file mode 100644 index 00000000..ad3023b3 --- /dev/null +++ b/sail_latex_riscv/overloadZZZZZZZZZZZZZzupdate_usi3c691c58ab628cbd10b9e21b62e0cfc4.tex @@ -0,0 +1 @@ +overload update_USI = {_update_Uinterrupts_USI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZZZZZZZZZZzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex b/sail_latex_riscv/overloadZZZZZZZZZZZZzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex new file mode 100644 index 00000000..cf600615 --- /dev/null +++ b/sail_latex_riscv/overloadZZZZZZZZZZZZzupdate_ree87191d8946f350c6ec7e0b7d1dc14b.tex @@ -0,0 +1 @@ +overload update_R = {_update_Pmpcfg_ent_R} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZZZZZZZZZzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadZZZZZZZZZZZzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..439da5d8 --- /dev/null +++ b/sail_latex_riscv/overloadZZZZZZZZZZZzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Satp64_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZZZZZZZZzupdate_load_access_faultcc580699ff14ff7930c001851a1463b8.tex b/sail_latex_riscv/overloadZZZZZZZZZZzupdate_load_access_faultcc580699ff14ff7930c001851a1463b8.tex new file mode 100644 index 00000000..035858d8 --- /dev/null +++ b/sail_latex_riscv/overloadZZZZZZZZZZzupdate_load_access_faultcc580699ff14ff7930c001851a1463b8.tex @@ -0,0 +1 @@ +overload update_Load_Access_Fault = {_update_Sedeleg_Load_Access_Fault} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZZZZZZZzupdate_mxra54b3693fefa5d6b0301ff08e0ea5a3f.tex b/sail_latex_riscv/overloadZZZZZZZZZzupdate_mxra54b3693fefa5d6b0301ff08e0ea5a3f.tex new file mode 100644 index 00000000..8e2657cc --- /dev/null +++ b/sail_latex_riscv/overloadZZZZZZZZZzupdate_mxra54b3693fefa5d6b0301ff08e0ea5a3f.tex @@ -0,0 +1 @@ +overload update_MXR = {_update_Sstatus_MXR} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZZZZZZzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex b/sail_latex_riscv/overloadZZZZZZZZzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex new file mode 100644 index 00000000..05b53b67 --- /dev/null +++ b/sail_latex_riscv/overloadZZZZZZZZzupdate_bits2be2fea5efbb571e15941b4fd6a2d080.tex @@ -0,0 +1 @@ +overload update_bits = {_update_Mcause_bits} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZZZZZzupdate_senvcall3c3a7a2242c90957bc2c31d37c79e50a.tex b/sail_latex_riscv/overloadZZZZZZZzupdate_senvcall3c3a7a2242c90957bc2c31d37c79e50a.tex new file mode 100644 index 00000000..8d4dbce4 --- /dev/null +++ b/sail_latex_riscv/overloadZZZZZZZzupdate_senvcall3c3a7a2242c90957bc2c31d37c79e50a.tex @@ -0,0 +1 @@ +overload update_SEnvCall = {_update_Medeleg_SEnvCall} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZZZZzupdate_seif1998ef482e23699637a58efcff9cf08.tex b/sail_latex_riscv/overloadZZZZZZzupdate_seif1998ef482e23699637a58efcff9cf08.tex new file mode 100644 index 00000000..995e2741 --- /dev/null +++ b/sail_latex_riscv/overloadZZZZZZzupdate_seif1998ef482e23699637a58efcff9cf08.tex @@ -0,0 +1 @@ +overload update_SEI = {_update_Minterrupts_SEI} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZZZzupdate_mprv112ef4f0b7ba57dead1dd08473f677fa.tex b/sail_latex_riscv/overloadZZZZZzupdate_mprv112ef4f0b7ba57dead1dd08473f677fa.tex new file mode 100644 index 00000000..2d115047 --- /dev/null +++ b/sail_latex_riscv/overloadZZZZZzupdate_mprv112ef4f0b7ba57dead1dd08473f677fa.tex @@ -0,0 +1 @@ +overload update_MPRV = {_update_Mstatus_MPRV} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZZzupdate_ff24be4e6c534e2f8325e19562655da80.tex b/sail_latex_riscv/overloadZZZZzupdate_ff24be4e6c534e2f8325e19562655da80.tex new file mode 100644 index 00000000..8d3b842d --- /dev/null +++ b/sail_latex_riscv/overloadZZZZzupdate_ff24be4e6c534e2f8325e19562655da80.tex @@ -0,0 +1 @@ +overload update_F = {_update_Misa_F} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZZzupdate_sa0c87839ffa29da7fb0fae8f4724ad23.tex b/sail_latex_riscv/overloadZZZzupdate_sa0c87839ffa29da7fb0fae8f4724ad23.tex new file mode 100644 index 00000000..17491435 --- /dev/null +++ b/sail_latex_riscv/overloadZZZzupdate_sa0c87839ffa29da7fb0fae8f4724ad23.tex @@ -0,0 +1 @@ +overload update_S = {_update_Misa_S} \ No newline at end of file diff --git a/sail_latex_riscv/overloadZZzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex b/sail_latex_riscv/overloadZZzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex new file mode 100644 index 00000000..b39857eb --- /dev/null +++ b/sail_latex_riscv/overloadZZzz8operatorz0zkzk_sz9fd336467c8d7c9163cb44b900cb10522.tex @@ -0,0 +1 @@ +overload operator >>_s = {sail_arith_shiftright} diff --git a/sail_latex_riscv/overloadZzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex b/sail_latex_riscv/overloadZzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex new file mode 100644 index 00000000..07e283d8 --- /dev/null +++ b/sail_latex_riscv/overloadZzvector_accessbe81ec250d2df2ebadde393ea37a85a4.tex @@ -0,0 +1 @@ +overload vector_access = {bitvector_access, plain_vector_access} diff --git a/sail_latex_riscv/typeza64_barrier_domaind28b62adeb08a7dce5456d5fc74d0c80.tex b/sail_latex_riscv/typeza64_barrier_domaind28b62adeb08a7dce5456d5fc74d0c80.tex new file mode 100644 index 00000000..dfc87c17 --- /dev/null +++ b/sail_latex_riscv/typeza64_barrier_domaind28b62adeb08a7dce5456d5fc74d0c80.tex @@ -0,0 +1,6 @@ +enum a64_barrier_domain = { + A64_FullShare, + A64_InnerShare, + A64_OuterShare, + A64_NonShare +} diff --git a/sail_latex_riscv/typeza64_barrier_typec915d041169289864dae061f42a2c131.tex b/sail_latex_riscv/typeza64_barrier_typec915d041169289864dae061f42a2c131.tex new file mode 100644 index 00000000..eb08175b --- /dev/null +++ b/sail_latex_riscv/typeza64_barrier_typec915d041169289864dae061f42a2c131.tex @@ -0,0 +1,5 @@ +enum a64_barrier_type = { + A64_barrier_all, + A64_barrier_LD, + A64_barrier_ST +} diff --git a/sail_latex_riscv/typezaccesstype627dc4f8d60f616c352a3659c0dfbd61.tex b/sail_latex_riscv/typezaccesstype627dc4f8d60f616c352a3659c0dfbd61.tex new file mode 100644 index 00000000..559669c3 --- /dev/null +++ b/sail_latex_riscv/typezaccesstype627dc4f8d60f616c352a3659c0dfbd61.tex @@ -0,0 +1,6 @@ +union #\hyperref[sailRISCVzAccessType]{AccessType}# ('a : Type) = { + Read : 'a, + Write : 'a, + ReadWrite : ('a, 'a), + Execute : unit +} diff --git a/sail_latex_riscv/typezamo83bf3a088c1fa727e8019cb088f80417.tex b/sail_latex_riscv/typezamo83bf3a088c1fa727e8019cb088f80417.tex new file mode 100644 index 00000000..99843103 --- /dev/null +++ b/sail_latex_riscv/typezamo83bf3a088c1fa727e8019cb088f80417.tex @@ -0,0 +1 @@ +type amo = #\hyperref[sailRISCVzbits]{bits}#(1) /* amo opcode flags */ diff --git a/sail_latex_riscv/typezamoopd600bc1f48968cf6c909a7527f520a98.tex b/sail_latex_riscv/typezamoopd600bc1f48968cf6c909a7527f520a98.tex new file mode 100644 index 00000000..d61110f5 --- /dev/null +++ b/sail_latex_riscv/typezamoopd600bc1f48968cf6c909a7527f520a98.tex @@ -0,0 +1,2 @@ +enum amoop = {AMOSWAP, AMOADD, AMOXOR, AMOAND, AMOOR, + AMOMIN, AMOMAX, AMOMINU, AMOMAXU} /* AMO ops */ diff --git a/sail_latex_riscv/typezarch_xlene776da3b62a5ddb22c2789a29c4f62e0.tex b/sail_latex_riscv/typezarch_xlene776da3b62a5ddb22c2789a29c4f62e0.tex new file mode 100644 index 00000000..28fc8aea --- /dev/null +++ b/sail_latex_riscv/typezarch_xlene776da3b62a5ddb22c2789a29c4f62e0.tex @@ -0,0 +1 @@ +type arch_xlen = #\hyperref[sailRISCVzbits]{bits}#(2) diff --git a/sail_latex_riscv/typezarchitecture5b5b6aa873a23d1ef07eac267bb6da07.tex b/sail_latex_riscv/typezarchitecture5b5b6aa873a23d1ef07eac267bb6da07.tex new file mode 100644 index 00000000..9018bf6d --- /dev/null +++ b/sail_latex_riscv/typezarchitecture5b5b6aa873a23d1ef07eac267bb6da07.tex @@ -0,0 +1 @@ +enum Architecture = {RV32, RV64, RV128} diff --git a/sail_latex_riscv/typezasid322158fcb044d3d182ba538bfe0883c5fc.tex b/sail_latex_riscv/typezasid322158fcb044d3d182ba538bfe0883c5fc.tex new file mode 100644 index 00000000..8d74da62 --- /dev/null +++ b/sail_latex_riscv/typezasid322158fcb044d3d182ba538bfe0883c5fc.tex @@ -0,0 +1 @@ +type asid32 = #\hyperref[sailRISCVzbits]{bits}#(9) diff --git a/sail_latex_riscv/typezasid64774ad52daab98e87d2a0c714473b041f.tex b/sail_latex_riscv/typezasid64774ad52daab98e87d2a0c714473b041f.tex new file mode 100644 index 00000000..0aaceb1f --- /dev/null +++ b/sail_latex_riscv/typezasid64774ad52daab98e87d2a0c714473b041f.tex @@ -0,0 +1 @@ +type asid64 = #\hyperref[sailRISCVzbits]{bits}#(16) diff --git a/sail_latex_riscv/typezast6bb070d12e82e4887160cdfd016230c8.tex b/sail_latex_riscv/typezast6bb070d12e82e4887160cdfd016230c8.tex new file mode 100644 index 00000000..bcfcbb35 --- /dev/null +++ b/sail_latex_riscv/typezast6bb070d12e82e4887160cdfd016230c8.tex @@ -0,0 +1 @@ +scattered union ast diff --git a/sail_latex_riscv/typezbarrier_kind0e1536e14e65f0b7937be9cba7867981.tex b/sail_latex_riscv/typezbarrier_kind0e1536e14e65f0b7937be9cba7867981.tex new file mode 100644 index 00000000..d2af22c0 --- /dev/null +++ b/sail_latex_riscv/typezbarrier_kind0e1536e14e65f0b7937be9cba7867981.tex @@ -0,0 +1,22 @@ +union barrier_kind = { + Barrier_Sync : unit, + Barrier_LwSync : unit, + Barrier_Eieio : unit, + Barrier_Isync : unit, + Barrier_DMB : (a64_barrier_domain, a64_barrier_type), + Barrier_DSB : (a64_barrier_domain, a64_barrier_type), + Barrier_ISB : unit, + Barrier_MIPS_SYNC : unit, + Barrier_RISCV_rw_rw : unit, + Barrier_RISCV_r_rw : unit, + Barrier_RISCV_r_r : unit, + Barrier_RISCV_rw_w : unit, + Barrier_RISCV_w_w : unit, + Barrier_RISCV_w_rw : unit, + Barrier_RISCV_rw_r : unit, + Barrier_RISCV_r_w : unit, + Barrier_RISCV_w_r : unit, + Barrier_RISCV_tso : unit, + Barrier_RISCV_i : unit, + Barrier_x86_MFENCE : unit +} diff --git a/sail_latex_riscv/typezbits_db59c6343f76a23d300748dc232dd81da.tex b/sail_latex_riscv/typezbits_db59c6343f76a23d300748dc232dd81da.tex new file mode 100644 index 00000000..5aa2a517 --- /dev/null +++ b/sail_latex_riscv/typezbits_db59c6343f76a23d300748dc232dd81da.tex @@ -0,0 +1 @@ +type bits_D = #\hyperref[sailRISCVzbits]{bits}#(64) /* Double-precision float value */ diff --git a/sail_latex_riscv/typezbits_fflagsed9b9763ebe260174539e00fd7a0a522.tex b/sail_latex_riscv/typezbits_fflagsed9b9763ebe260174539e00fd7a0a522.tex new file mode 100644 index 00000000..37ef04f6 --- /dev/null +++ b/sail_latex_riscv/typezbits_fflagsed9b9763ebe260174539e00fd7a0a522.tex @@ -0,0 +1 @@ +type bits_fflags = #\hyperref[sailRISCVzbits]{bits}#(5) /* Accrued exceptions: NV,DZ,OF,UF,NX */ diff --git a/sail_latex_riscv/typezbits_l07cb308b5e4f91b7017ab58409d32070.tex b/sail_latex_riscv/typezbits_l07cb308b5e4f91b7017ab58409d32070.tex new file mode 100644 index 00000000..b3831277 --- /dev/null +++ b/sail_latex_riscv/typezbits_l07cb308b5e4f91b7017ab58409d32070.tex @@ -0,0 +1 @@ +type bits_L = #\hyperref[sailRISCVzbits]{bits}#(64) /* Signed integer */ diff --git a/sail_latex_riscv/typezbits_lu3ab4327e3a12cfe46ba2eb7149190854.tex b/sail_latex_riscv/typezbits_lu3ab4327e3a12cfe46ba2eb7149190854.tex new file mode 100644 index 00000000..6addc95b --- /dev/null +++ b/sail_latex_riscv/typezbits_lu3ab4327e3a12cfe46ba2eb7149190854.tex @@ -0,0 +1 @@ +type bits_LU = #\hyperref[sailRISCVzbits]{bits}#(64) /* Unsigned integer */ diff --git a/sail_latex_riscv/typezbits_rm5b1f0169c0e4579bf2dcf98ba6079158.tex b/sail_latex_riscv/typezbits_rm5b1f0169c0e4579bf2dcf98ba6079158.tex new file mode 100644 index 00000000..a30d4ac9 --- /dev/null +++ b/sail_latex_riscv/typezbits_rm5b1f0169c0e4579bf2dcf98ba6079158.tex @@ -0,0 +1 @@ +type bits_rm = #\hyperref[sailRISCVzbits]{bits}#(3) /* Rounding mode */ diff --git a/sail_latex_riscv/typezbits_s528d05a73240052d43e6da2026f5b50f.tex b/sail_latex_riscv/typezbits_s528d05a73240052d43e6da2026f5b50f.tex new file mode 100644 index 00000000..e3811198 --- /dev/null +++ b/sail_latex_riscv/typezbits_s528d05a73240052d43e6da2026f5b50f.tex @@ -0,0 +1 @@ +type bits_S = #\hyperref[sailRISCVzbits]{bits}#(32) /* Single-precision float value */ diff --git a/sail_latex_riscv/typezbits_wcd34ca70f55b1c3a8eca237a0b2e5a5b.tex b/sail_latex_riscv/typezbits_wcd34ca70f55b1c3a8eca237a0b2e5a5b.tex new file mode 100644 index 00000000..12ad737c --- /dev/null +++ b/sail_latex_riscv/typezbits_wcd34ca70f55b1c3a8eca237a0b2e5a5b.tex @@ -0,0 +1 @@ +type bits_W = #\hyperref[sailRISCVzbits]{bits}#(32) /* Signed integer */ diff --git a/sail_latex_riscv/typezbits_wud57fbe06e562e34a1f66b7832875f761.tex b/sail_latex_riscv/typezbits_wud57fbe06e562e34a1f66b7832875f761.tex new file mode 100644 index 00000000..fc3b2c4e --- /dev/null +++ b/sail_latex_riscv/typezbits_wud57fbe06e562e34a1f66b7832875f761.tex @@ -0,0 +1 @@ +type bits_WU = #\hyperref[sailRISCVzbits]{bits}#(32) /* Unsigned integer */ diff --git a/sail_latex_riscv/typezbitsa4b31f9b3dc11c921007b665e0d0fce6.tex b/sail_latex_riscv/typezbitsa4b31f9b3dc11c921007b665e0d0fce6.tex new file mode 100644 index 00000000..de2d6983 --- /dev/null +++ b/sail_latex_riscv/typezbitsa4b31f9b3dc11c921007b665e0d0fce6.tex @@ -0,0 +1 @@ +type #\hyperref[sailRISCVzbits]{bits}# ('n : Int) = #\hyperref[sailRISCVzbitvector]{bitvector}#('n, dec) diff --git a/sail_latex_riscv/typezbop5369d06602ae03217d614193dd3f84fa.tex b/sail_latex_riscv/typezbop5369d06602ae03217d614193dd3f84fa.tex new file mode 100644 index 00000000..52f5b20f --- /dev/null +++ b/sail_latex_riscv/typezbop5369d06602ae03217d614193dd3f84fa.tex @@ -0,0 +1,2 @@ +enum bop = {RISCV_BEQ, RISCV_BNE, RISCV_BLT, + RISCV_BGE, RISCV_BLTU, RISCV_BGEU} /* branch ops */ diff --git a/sail_latex_riscv/typezcache_op_kind900c2bd360568e5562e384cfad1cfbd4.tex b/sail_latex_riscv/typezcache_op_kind900c2bd360568e5562e384cfad1cfbd4.tex new file mode 100644 index 00000000..8b408478 --- /dev/null +++ b/sail_latex_riscv/typezcache_op_kind900c2bd360568e5562e384cfad1cfbd4.tex @@ -0,0 +1,7 @@ +enum cache_op_kind = { + /* AArch64 DC */ + Cache_op_D_IVAC, Cache_op_D_ISW, Cache_op_D_CSW, Cache_op_D_CISW, + Cache_op_D_ZVA, Cache_op_D_CVAC, Cache_op_D_CVAU, Cache_op_D_CIVAC, + /* AArch64 IC */ + Cache_op_I_IALLUIS, Cache_op_I_IALLU, Cache_op_I_IVAU +} diff --git a/sail_latex_riscv/typezcap_addr_width7d4b25117798a50c5addfe865237309d.tex b/sail_latex_riscv/typezcap_addr_width7d4b25117798a50c5addfe865237309d.tex new file mode 100644 index 00000000..f1dee4e4 --- /dev/null +++ b/sail_latex_riscv/typezcap_addr_width7d4b25117798a50c5addfe865237309d.tex @@ -0,0 +1 @@ +type cap_addr_width : Int = xlen diff --git a/sail_latex_riscv/typezcap_flags_width335bf4f42772a3e75f4dbee10e086942.tex b/sail_latex_riscv/typezcap_flags_width335bf4f42772a3e75f4dbee10e086942.tex new file mode 100644 index 00000000..1fae4d4c --- /dev/null +++ b/sail_latex_riscv/typezcap_flags_width335bf4f42772a3e75f4dbee10e086942.tex @@ -0,0 +1 @@ +type cap_flags_width : Int = 1 diff --git a/sail_latex_riscv/typezcap_hperms_width7a71e6f5d2bdf15a0098752dcdf93274.tex b/sail_latex_riscv/typezcap_hperms_width7a71e6f5d2bdf15a0098752dcdf93274.tex new file mode 100644 index 00000000..0e04fcc9 --- /dev/null +++ b/sail_latex_riscv/typezcap_hperms_width7a71e6f5d2bdf15a0098752dcdf93274.tex @@ -0,0 +1 @@ +type cap_hperms_width : Int = 12 diff --git a/sail_latex_riscv/typezcap_len_width9583637a11dff282b382f15c2de94120.tex b/sail_latex_riscv/typezcap_len_width9583637a11dff282b382f15c2de94120.tex new file mode 100644 index 00000000..d8ee2261 --- /dev/null +++ b/sail_latex_riscv/typezcap_len_width9583637a11dff282b382f15c2de94120.tex @@ -0,0 +1 @@ +type cap_len_width : Int = cap_addr_width + 1 diff --git a/sail_latex_riscv/typezcap_mantissa_width9664b91a58eac86639a6d61f4c90f63a.tex b/sail_latex_riscv/typezcap_mantissa_width9664b91a58eac86639a6d61f4c90f63a.tex new file mode 100644 index 00000000..361105f7 --- /dev/null +++ b/sail_latex_riscv/typezcap_mantissa_width9664b91a58eac86639a6d61f4c90f63a.tex @@ -0,0 +1 @@ +type cap_mantissa_width : Int = 14 diff --git a/sail_latex_riscv/typezcap_otype_widthcbba33421b0d173c367e3bd232817e06.tex b/sail_latex_riscv/typezcap_otype_widthcbba33421b0d173c367e3bd232817e06.tex new file mode 100644 index 00000000..3868da48 --- /dev/null +++ b/sail_latex_riscv/typezcap_otype_widthcbba33421b0d173c367e3bd232817e06.tex @@ -0,0 +1 @@ +type cap_otype_width : Int = 18 diff --git a/sail_latex_riscv/typezcap_perms_widthf1a97a7ea919ad9f42706f84547f5b1a.tex b/sail_latex_riscv/typezcap_perms_widthf1a97a7ea919ad9f42706f84547f5b1a.tex new file mode 100644 index 00000000..c1da7452 --- /dev/null +++ b/sail_latex_riscv/typezcap_perms_widthf1a97a7ea919ad9f42706f84547f5b1a.tex @@ -0,0 +1 @@ +type cap_perms_width : Int = cap_uperms_shift + cap_uperms_width diff --git a/sail_latex_riscv/typezcap_sizze1bdaf9cd8fe2936d527bdd4bc7dd72ca.tex b/sail_latex_riscv/typezcap_sizze1bdaf9cd8fe2936d527bdd4bc7dd72ca.tex new file mode 100644 index 00000000..cb792cb7 --- /dev/null +++ b/sail_latex_riscv/typezcap_sizze1bdaf9cd8fe2936d527bdd4bc7dd72ca.tex @@ -0,0 +1 @@ +type cap_size : Int = 16 diff --git a/sail_latex_riscv/typezcap_uperms_shiftbe2a57515ea08a94424ab7ec6686232b.tex b/sail_latex_riscv/typezcap_uperms_shiftbe2a57515ea08a94424ab7ec6686232b.tex new file mode 100644 index 00000000..0d5cf079 --- /dev/null +++ b/sail_latex_riscv/typezcap_uperms_shiftbe2a57515ea08a94424ab7ec6686232b.tex @@ -0,0 +1 @@ +type cap_uperms_shift : Int = 15 diff --git a/sail_latex_riscv/typezcap_uperms_widthf6dfed0942499b0c2d58b90971faca40.tex b/sail_latex_riscv/typezcap_uperms_widthf6dfed0942499b0c2d58b90971faca40.tex new file mode 100644 index 00000000..3aee6174 --- /dev/null +++ b/sail_latex_riscv/typezcap_uperms_widthf6dfed0942499b0c2d58b90971faca40.tex @@ -0,0 +1 @@ +type cap_uperms_width : Int = 4 diff --git a/sail_latex_riscv/typezcapability5646515621fe4c3bb7fe8874d1909f0e.tex b/sail_latex_riscv/typezcapability5646515621fe4c3bb7fe8874d1909f0e.tex new file mode 100644 index 00000000..2c927f9c --- /dev/null +++ b/sail_latex_riscv/typezcapability5646515621fe4c3bb7fe8874d1909f0e.tex @@ -0,0 +1,24 @@ +struct Capability = { + tag : bool , + uperms : #\hyperref[sailRISCVzbits]{bits}#(cap_uperms_width) , + permit_set_CID : bool , + access_system_regs : bool , + permit_unseal : bool , + permit_cinvoke : bool , + permit_seal : bool , + permit_store_local_cap : bool , + permit_store_cap : bool , + permit_load_cap : bool , + permit_store : bool , + permit_load : bool , + permit_execute : bool , + global : bool , + reserved : #\hyperref[sailRISCVzbits]{bits}#(2) , + flag_cap_mode : bool , + internal_e : bool , + E : #\hyperref[sailRISCVzbits]{bits}#(6) , + B : #\hyperref[sailRISCVzbits]{bits}#(cap_mantissa_width), + T : #\hyperref[sailRISCVzbits]{bits}#(cap_mantissa_width), + otype : #\hyperref[sailRISCVzbits]{bits}#(cap_otype_width), + address : #\hyperref[sailRISCVzbits]{bits}#(cap_addr_width) +} diff --git a/sail_latex_riscv/typezcapaddrbitsdbb96675d10b9e9b205f71df6a15d202.tex b/sail_latex_riscv/typezcapaddrbitsdbb96675d10b9e9b205f71df6a15d202.tex new file mode 100644 index 00000000..b9d553e2 --- /dev/null +++ b/sail_latex_riscv/typezcapaddrbitsdbb96675d10b9e9b205f71df6a15d202.tex @@ -0,0 +1 @@ +type CapAddrBits = #\hyperref[sailRISCVzbits]{bits}#(cap_addr_width) diff --git a/sail_latex_riscv/typezcapaddrintf3dc84d3e8f46c74b19aac7a9fd4f1f2.tex b/sail_latex_riscv/typezcapaddrintf3dc84d3e8f46c74b19aac7a9fd4f1f2.tex new file mode 100644 index 00000000..69717dfb --- /dev/null +++ b/sail_latex_riscv/typezcapaddrintf3dc84d3e8f46c74b19aac7a9fd4f1f2.tex @@ -0,0 +1 @@ +type CapAddrInt = range(0, (2 ^ 64) - 1) /* XXX should be cap_addr_width */ diff --git a/sail_latex_riscv/typezcapbits32830b87cefa69a0cdb78ef00d25b781.tex b/sail_latex_riscv/typezcapbits32830b87cefa69a0cdb78ef00d25b781.tex new file mode 100644 index 00000000..ce3b39f3 --- /dev/null +++ b/sail_latex_riscv/typezcapbits32830b87cefa69a0cdb78ef00d25b781.tex @@ -0,0 +1 @@ +type CapBits = #\hyperref[sailRISCVzbits]{bits}#(8 * cap_size) diff --git a/sail_latex_riscv/typezcapexbc9797bf8ddff0359677ca6657edba93.tex b/sail_latex_riscv/typezcapexbc9797bf8ddff0359677ca6657edba93.tex new file mode 100644 index 00000000..4351cf2d --- /dev/null +++ b/sail_latex_riscv/typezcapexbc9797bf8ddff0359677ca6657edba93.tex @@ -0,0 +1,26 @@ +enum CapEx = { + CapEx_None, + CapEx_LengthViolation, + CapEx_TagViolation, + CapEx_SealViolation, + CapEx_TypeViolation, + CapEx_CallTrap, + CapEx_ReturnTrap, + CapEx_TSSUnderFlow, + CapEx_UserDefViolation, + CapEx_InexactBounds, + CapEx_UnalignedBase, + CapEx_GlobalViolation, + CapEx_PermitExecuteViolation, + CapEx_PermitLoadViolation, + CapEx_PermitStoreViolation, + CapEx_PermitLoadCapViolation, + CapEx_PermitStoreCapViolation, + CapEx_PermitStoreLocalCapViolation, + CapEx_PermitSealViolation, + CapEx_AccessSystemRegsViolation, + CapEx_PermitCInvokeViolation, + CapEx_AccessCInvokeIDCViolation, + CapEx_PermitUnsealViolation, + CapEx_PermitSetCIDViolation +} diff --git a/sail_latex_riscv/typezcapflagsbitsc0aea8b13e99ce9586aae1d820edcb88.tex b/sail_latex_riscv/typezcapflagsbitsc0aea8b13e99ce9586aae1d820edcb88.tex new file mode 100644 index 00000000..af7b70b3 --- /dev/null +++ b/sail_latex_riscv/typezcapflagsbitsc0aea8b13e99ce9586aae1d820edcb88.tex @@ -0,0 +1 @@ +type CapFlagsBits = #\hyperref[sailRISCVzbits]{bits}#(cap_flags_width) diff --git a/sail_latex_riscv/typezcaplenbits0c88c644020f10b2ca144bfbaba3ec9e.tex b/sail_latex_riscv/typezcaplenbits0c88c644020f10b2ca144bfbaba3ec9e.tex new file mode 100644 index 00000000..5e190943 --- /dev/null +++ b/sail_latex_riscv/typezcaplenbits0c88c644020f10b2ca144bfbaba3ec9e.tex @@ -0,0 +1 @@ +type CapLenBits = #\hyperref[sailRISCVzbits]{bits}#(cap_len_width) diff --git a/sail_latex_riscv/typezcaplenf6618af706b03f95ca9741cffae7687d.tex b/sail_latex_riscv/typezcaplenf6618af706b03f95ca9741cffae7687d.tex new file mode 100644 index 00000000..115fd079 --- /dev/null +++ b/sail_latex_riscv/typezcaplenf6618af706b03f95ca9741cffae7687d.tex @@ -0,0 +1 @@ +type CapLen = range(0, 2 ^ 65) /* XXX sail can't handle if this is expressed as cap_len_width */ diff --git a/sail_latex_riscv/typezcappermsbits6613dfcf198c86f0eab4b7594494ef02.tex b/sail_latex_riscv/typezcappermsbits6613dfcf198c86f0eab4b7594494ef02.tex new file mode 100644 index 00000000..f97e0a29 --- /dev/null +++ b/sail_latex_riscv/typezcappermsbits6613dfcf198c86f0eab4b7594494ef02.tex @@ -0,0 +1 @@ +type CapPermsBits = #\hyperref[sailRISCVzbits]{bits}#(cap_perms_width) diff --git a/sail_latex_riscv/typezcapreg_idx46cb8ec24174ac7dafd6635c5040002d.tex b/sail_latex_riscv/typezcapreg_idx46cb8ec24174ac7dafd6635c5040002d.tex new file mode 100644 index 00000000..befc00f5 --- /dev/null +++ b/sail_latex_riscv/typezcapreg_idx46cb8ec24174ac7dafd6635c5040002d.tex @@ -0,0 +1 @@ +type capreg_idx = #\hyperref[sailRISCVzbits]{bits}#(6) diff --git a/sail_latex_riscv/typezcaps_per_cache_line7254e281fd7ea6b3c919ca9a34d729ad.tex b/sail_latex_riscv/typezcaps_per_cache_line7254e281fd7ea6b3c919ca9a34d729ad.tex new file mode 100644 index 00000000..fd06a9d6 --- /dev/null +++ b/sail_latex_riscv/typezcaps_per_cache_line7254e281fd7ea6b3c919ca9a34d729ad.tex @@ -0,0 +1 @@ +type caps_per_cache_line : Int = 4 diff --git a/sail_latex_riscv/typezccsrebba1b25012128c604b97c41d5de5508.tex b/sail_latex_riscv/typezccsrebba1b25012128c604b97c41d5de5508.tex new file mode 100644 index 00000000..9f1e815d --- /dev/null +++ b/sail_latex_riscv/typezccsrebba1b25012128c604b97c41d5de5508.tex @@ -0,0 +1 @@ +struct ccsr = {ccsr_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezcheri_causec1e7f09ff14a785b125a16b7f7b4f4fe.tex b/sail_latex_riscv/typezcheri_causec1e7f09ff14a785b125a16b7f7b4f4fe.tex new file mode 100644 index 00000000..9f9178af --- /dev/null +++ b/sail_latex_riscv/typezcheri_causec1e7f09ff14a785b125a16b7f7b4f4fe.tex @@ -0,0 +1,4 @@ +struct cheri_cause = { + cap_idx : capreg_idx, + capEx : CapEx +} diff --git a/sail_latex_riscv/typezclearregsete5eab3e282a2a338ddb8311b5edbb561.tex b/sail_latex_riscv/typezclearregsete5eab3e282a2a338ddb8311b5edbb561.tex new file mode 100644 index 00000000..fa0443f6 --- /dev/null +++ b/sail_latex_riscv/typezclearregsete5eab3e282a2a338ddb8311b5edbb561.tex @@ -0,0 +1,4 @@ +enum ClearRegSet = { + GPRegs, + FPRegs +} diff --git a/sail_latex_riscv/typezcounteren79441db7eb726d320a01493bb921db0e.tex b/sail_latex_riscv/typezcounteren79441db7eb726d320a01493bb921db0e.tex new file mode 100644 index 00000000..958b548e --- /dev/null +++ b/sail_latex_riscv/typezcounteren79441db7eb726d320a01493bb921db0e.tex @@ -0,0 +1 @@ +struct Counteren = {Counteren_chunk_0 : bitvector(32, dec)} diff --git a/sail_latex_riscv/typezcounterin25158d322f7a7f1b254bff0638245582.tex b/sail_latex_riscv/typezcounterin25158d322f7a7f1b254bff0638245582.tex new file mode 100644 index 00000000..be606372 --- /dev/null +++ b/sail_latex_riscv/typezcounterin25158d322f7a7f1b254bff0638245582.tex @@ -0,0 +1 @@ +struct Counterin = {Counterin_chunk_0 : bitvector(32, dec)} diff --git a/sail_latex_riscv/typezcptrcmpopb3b1dde403387930c5431415f0c993e5.tex b/sail_latex_riscv/typezcptrcmpopb3b1dde403387930c5431415f0c993e5.tex new file mode 100644 index 00000000..cb0a73ae --- /dev/null +++ b/sail_latex_riscv/typezcptrcmpopb3b1dde403387930c5431415f0c993e5.tex @@ -0,0 +1,10 @@ +enum CPtrCmpOp = { + CEQ, + CNE, + CLT, + CLE, + CLTU, + CLEU, + CEXEQ, + CNEXEQ +} diff --git a/sail_latex_riscv/typezcregidx93aa5af192dfa10c34a9c84f0c2ce1a1.tex b/sail_latex_riscv/typezcregidx93aa5af192dfa10c34a9c84f0c2ce1a1.tex new file mode 100644 index 00000000..cc55ca91 --- /dev/null +++ b/sail_latex_riscv/typezcregidx93aa5af192dfa10c34a9c84f0c2ce1a1.tex @@ -0,0 +1 @@ +type cregidx = #\hyperref[sailRISCVzbits]{bits}#(3) /* identifiers in RVC instructions */ diff --git a/sail_latex_riscv/typezcsreg01b93a287ca075effde1c3cdbc173b4e.tex b/sail_latex_riscv/typezcsreg01b93a287ca075effde1c3cdbc173b4e.tex new file mode 100644 index 00000000..44bb468f --- /dev/null +++ b/sail_latex_riscv/typezcsreg01b93a287ca075effde1c3cdbc173b4e.tex @@ -0,0 +1 @@ +type csreg = #\hyperref[sailRISCVzbits]{bits}#(12) /* CSR addressing */ diff --git a/sail_latex_riscv/typezcsrop2c5a5cf59f588ba61c955dc544ab5638.tex b/sail_latex_riscv/typezcsrop2c5a5cf59f588ba61c955dc544ab5638.tex new file mode 100644 index 00000000..d8d6f193 --- /dev/null +++ b/sail_latex_riscv/typezcsrop2c5a5cf59f588ba61c955dc544ab5638.tex @@ -0,0 +1 @@ +enum csrop = {CSRRW, CSRRS, CSRRC} /* CSR ops */ diff --git a/sail_latex_riscv/typezcsrrwa8d2be180025e67dbbe56d3c5c45b12e.tex b/sail_latex_riscv/typezcsrrwa8d2be180025e67dbbe56d3c5c45b12e.tex new file mode 100644 index 00000000..b7fa2a3b --- /dev/null +++ b/sail_latex_riscv/typezcsrrwa8d2be180025e67dbbe56d3c5c45b12e.tex @@ -0,0 +1 @@ +type csrRW = #\hyperref[sailRISCVzbits]{bits}#(2) /* read/write */ diff --git a/sail_latex_riscv/typezctl_result052149e0767cf8ed055fce7a562f2c3c.tex b/sail_latex_riscv/typezctl_result052149e0767cf8ed055fce7a562f2c3c.tex new file mode 100644 index 00000000..53ea28d6 --- /dev/null +++ b/sail_latex_riscv/typezctl_result052149e0767cf8ed055fce7a562f2c3c.tex @@ -0,0 +1,6 @@ +union ctl_result = { + CTL_TRAP : sync_exception, + CTL_SRET : unit, + CTL_MRET : unit, + CTL_URET : unit +} diff --git a/sail_latex_riscv/typezdiafp900a9a3c892b92c007276686dcd307f6.tex b/sail_latex_riscv/typezdiafp900a9a3c892b92c007276686dcd307f6.tex new file mode 100644 index 00000000..c40bf043 --- /dev/null +++ b/sail_latex_riscv/typezdiafp900a9a3c892b92c007276686dcd307f6.tex @@ -0,0 +1,5 @@ +union diafp = { + DIAFP_none : unit, + DIAFP_concrete : #\hyperref[sailRISCVzbits]{bits}#(64), + DIAFP_reg : regfp +} diff --git a/sail_latex_riscv/typezexc_code41fa41b8abb196633a02f07b51e90738.tex b/sail_latex_riscv/typezexc_code41fa41b8abb196633a02f07b51e90738.tex new file mode 100644 index 00000000..9db34a0c --- /dev/null +++ b/sail_latex_riscv/typezexc_code41fa41b8abb196633a02f07b51e90738.tex @@ -0,0 +1 @@ +type exc_code = bits(8) diff --git a/sail_latex_riscv/typezexceptionfaa4db8fab65c538edad4222e766a71a.tex b/sail_latex_riscv/typezexceptionfaa4db8fab65c538edad4222e766a71a.tex new file mode 100644 index 00000000..a5ee69f1 --- /dev/null +++ b/sail_latex_riscv/typezexceptionfaa4db8fab65c538edad4222e766a71a.tex @@ -0,0 +1,4 @@ +union exception = { + Error_not_implemented : string, + Error_internal_error : unit +} diff --git a/sail_latex_riscv/typezexceptiontype8574cf8632bbc8e423ccb2d23e61bdff.tex b/sail_latex_riscv/typezexceptiontype8574cf8632bbc8e423ccb2d23e61bdff.tex new file mode 100644 index 00000000..d3876184 --- /dev/null +++ b/sail_latex_riscv/typezexceptiontype8574cf8632bbc8e423ccb2d23e61bdff.tex @@ -0,0 +1,21 @@ +union ExceptionType = { + E_Fetch_Addr_Align : unit, + E_Fetch_Access_Fault : unit, + E_Illegal_Instr : unit, + E_Breakpoint : unit, + E_Load_Addr_Align : unit, + E_Load_Access_Fault : unit, + E_SAMO_Addr_Align : unit, + E_SAMO_Access_Fault : unit, + E_U_EnvCall : unit, + E_S_EnvCall : unit, + E_Reserved_10 : unit, + E_M_EnvCall : unit, + E_Fetch_Page_Fault : unit, + E_Load_Page_Fault : unit, + E_Reserved_14 : unit, + E_SAMO_Page_Fault : unit, + + /* extensions */ + E_Extension : ext_exc_type +} diff --git a/sail_latex_riscv/typezext_access_type8c60f923ce211fcdc0c77548b866673e.tex b/sail_latex_riscv/typezext_access_type8c60f923ce211fcdc0c77548b866673e.tex new file mode 100644 index 00000000..65364af6 --- /dev/null +++ b/sail_latex_riscv/typezext_access_type8c60f923ce211fcdc0c77548b866673e.tex @@ -0,0 +1,4 @@ +enum ext_access_type = { + Data, + Cap +} diff --git a/sail_latex_riscv/typezext_control_addr_error30fe954fdccd9382175241e7b6137d82.tex b/sail_latex_riscv/typezext_control_addr_error30fe954fdccd9382175241e7b6137d82.tex new file mode 100644 index 00000000..ec62b012 --- /dev/null +++ b/sail_latex_riscv/typezext_control_addr_error30fe954fdccd9382175241e7b6137d82.tex @@ -0,0 +1 @@ +type ext_control_addr_error = (CapEx, capreg_idx) diff --git a/sail_latex_riscv/typezext_controladdr_checka9d6f41abcba03f32cc75e65e808a059.tex b/sail_latex_riscv/typezext_controladdr_checka9d6f41abcba03f32cc75e65e808a059.tex new file mode 100644 index 00000000..0decb18d --- /dev/null +++ b/sail_latex_riscv/typezext_controladdr_checka9d6f41abcba03f32cc75e65e808a059.tex @@ -0,0 +1,4 @@ +union #\hyperref[sailRISCVzExtzyControlAddrzyCheck]{Ext\_ControlAddr\_Check}# ('a : Type) = { + Ext_ControlAddr_OK : xlenbits, /* PC value to use for the target of the control operation */ + Ext_ControlAddr_Error : 'a +} diff --git a/sail_latex_riscv/typezext_data_addr_errora4f74a5b44e1f0d7e46bc0f33c466dea.tex b/sail_latex_riscv/typezext_data_addr_errora4f74a5b44e1f0d7e46bc0f33c466dea.tex new file mode 100644 index 00000000..d2051a0c --- /dev/null +++ b/sail_latex_riscv/typezext_data_addr_errora4f74a5b44e1f0d7e46bc0f33c466dea.tex @@ -0,0 +1 @@ +type ext_data_addr_error = (CapEx, capreg_idx) diff --git a/sail_latex_riscv/typezext_dataaddr_checkae2f55c86bbc0d35297825ba44134f12.tex b/sail_latex_riscv/typezext_dataaddr_checkae2f55c86bbc0d35297825ba44134f12.tex new file mode 100644 index 00000000..c81fca74 --- /dev/null +++ b/sail_latex_riscv/typezext_dataaddr_checkae2f55c86bbc0d35297825ba44134f12.tex @@ -0,0 +1,4 @@ +union #\hyperref[sailRISCVzExtzyDataAddrzyCheck]{Ext\_DataAddr\_Check}# ('a : Type) = { + Ext_DataAddr_OK : xlenbits, /* Address to use for the data access */ + Ext_DataAddr_Error : 'a +} diff --git a/sail_latex_riscv/typezext_exc_type73c827d8e97122989947956ad800fcf5.tex b/sail_latex_riscv/typezext_exc_type73c827d8e97122989947956ad800fcf5.tex new file mode 100644 index 00000000..6fc28a86 --- /dev/null +++ b/sail_latex_riscv/typezext_exc_type73c827d8e97122989947956ad800fcf5.tex @@ -0,0 +1,5 @@ +enum ext_exc_type = { + EXC_LOAD_CAP_PAGE_FAULT, + EXC_SAMO_CAP_PAGE_FAULT, + EXC_CHERI +} diff --git a/sail_latex_riscv/typezext_exception91bbea5dcedef746789e1dfa97cb264d.tex b/sail_latex_riscv/typezext_exception91bbea5dcedef746789e1dfa97cb264d.tex new file mode 100644 index 00000000..91d0d7e2 --- /dev/null +++ b/sail_latex_riscv/typezext_exception91bbea5dcedef746789e1dfa97cb264d.tex @@ -0,0 +1 @@ +type ext_exception = cheri_cause diff --git a/sail_latex_riscv/typezext_fetch_addr_error77c89145df888a86f60f8c4b402dc719.tex b/sail_latex_riscv/typezext_fetch_addr_error77c89145df888a86f60f8c4b402dc719.tex new file mode 100644 index 00000000..0eebdbd3 --- /dev/null +++ b/sail_latex_riscv/typezext_fetch_addr_error77c89145df888a86f60f8c4b402dc719.tex @@ -0,0 +1 @@ +type ext_fetch_addr_error = CapEx diff --git a/sail_latex_riscv/typezext_fetchaddr_checkea47f0986744ae6c29753d54694485fe.tex b/sail_latex_riscv/typezext_fetchaddr_checkea47f0986744ae6c29753d54694485fe.tex new file mode 100644 index 00000000..d8a7bb57 --- /dev/null +++ b/sail_latex_riscv/typezext_fetchaddr_checkea47f0986744ae6c29753d54694485fe.tex @@ -0,0 +1,4 @@ +union #\hyperref[sailRISCVzExtzyFetchAddrzyCheck]{Ext\_FetchAddr\_Check}# ('a : Type) = { + Ext_FetchAddr_OK : xlenbits, /* PC value to use for the actual fetch */ + Ext_FetchAddr_Error : 'a +} diff --git a/sail_latex_riscv/typezext_pte_bitsa7158098bccf12e34e307673a27a3abd.tex b/sail_latex_riscv/typezext_pte_bitsa7158098bccf12e34e307673a27a3abd.tex new file mode 100644 index 00000000..47be57f3 --- /dev/null +++ b/sail_latex_riscv/typezext_pte_bitsa7158098bccf12e34e307673a27a3abd.tex @@ -0,0 +1 @@ +struct Ext_PTE_Bits = {Ext_PTE_Bits_chunk_0 : bitvector(10, dec)} diff --git a/sail_latex_riscv/typezext_ptw_error5964337ea2d10baef1f3c2ff9d6e6893.tex b/sail_latex_riscv/typezext_ptw_error5964337ea2d10baef1f3c2ff9d6e6893.tex new file mode 100644 index 00000000..c5b685c8 --- /dev/null +++ b/sail_latex_riscv/typezext_ptw_error5964337ea2d10baef1f3c2ff9d6e6893.tex @@ -0,0 +1 @@ +enum ext_ptw_error = {AT_CAP_ERR} diff --git a/sail_latex_riscv/typezext_ptw_fail2875647ee1ba483d4a452f6a98fef854.tex b/sail_latex_riscv/typezext_ptw_fail2875647ee1ba483d4a452f6a98fef854.tex new file mode 100644 index 00000000..bbbb8a90 --- /dev/null +++ b/sail_latex_riscv/typezext_ptw_fail2875647ee1ba483d4a452f6a98fef854.tex @@ -0,0 +1,4 @@ +enum ext_ptw_fail = { + EPTWF_NO_PERM, + EPTWF_CAP_ERR +} diff --git a/sail_latex_riscv/typezext_ptw_lcbba545a858359524aa6ef05819a4c22a.tex b/sail_latex_riscv/typezext_ptw_lcbba545a858359524aa6ef05819a4c22a.tex new file mode 100644 index 00000000..025c7a58 --- /dev/null +++ b/sail_latex_riscv/typezext_ptw_lcbba545a858359524aa6ef05819a4c22a.tex @@ -0,0 +1,7 @@ +enum ext_ptw_lc = { + /* Tags flow as might be expected */ + PTW_LC_OK, + + /* PTE settings require clearing tags */ + PTW_LC_CLEAR +} diff --git a/sail_latex_riscv/typezext_ptw_sccf7d1fb4d0ca02c7aa470f10faacf4b9.tex b/sail_latex_riscv/typezext_ptw_sccf7d1fb4d0ca02c7aa470f10faacf4b9.tex new file mode 100644 index 00000000..53aa8116 --- /dev/null +++ b/sail_latex_riscv/typezext_ptw_sccf7d1fb4d0ca02c7aa470f10faacf4b9.tex @@ -0,0 +1,7 @@ +enum ext_ptw_sc = { + /* Tag stores are permitted */ + PTW_SC_OK, + + /* Tag-asserting stores trap */ + PTW_SC_TRAP +} diff --git a/sail_latex_riscv/typezext_ptwde60d7352876746c4773d53f332b5137.tex b/sail_latex_riscv/typezext_ptwde60d7352876746c4773d53f332b5137.tex new file mode 100644 index 00000000..34ac8fb7 --- /dev/null +++ b/sail_latex_riscv/typezext_ptwde60d7352876746c4773d53f332b5137.tex @@ -0,0 +1,4 @@ +struct ext_ptw = { + ptw_lc : ext_ptw_lc, + ptw_sc : ext_ptw_sc +} diff --git a/sail_latex_riscv/typezext_statuscc754716d0653fa6ecbe317b319fb0e7.tex b/sail_latex_riscv/typezext_statuscc754716d0653fa6ecbe317b319fb0e7.tex new file mode 100644 index 00000000..7299fd1c --- /dev/null +++ b/sail_latex_riscv/typezext_statuscc754716d0653fa6ecbe317b319fb0e7.tex @@ -0,0 +1 @@ +type ext_status = #\hyperref[sailRISCVzbits]{bits}#(2) diff --git a/sail_latex_riscv/typezextpte08291a23c157d4bccbd0a79786be8e37.tex b/sail_latex_riscv/typezextpte08291a23c157d4bccbd0a79786be8e37.tex new file mode 100644 index 00000000..f40633bc --- /dev/null +++ b/sail_latex_riscv/typezextpte08291a23c157d4bccbd0a79786be8e37.tex @@ -0,0 +1 @@ +type extPte = #\hyperref[sailRISCVzbits]{bits}#(10) diff --git a/sail_latex_riscv/typezextstatus48f045aa452fc429aaaaf8df3f7b4a71.tex b/sail_latex_riscv/typezextstatus48f045aa452fc429aaaaf8df3f7b4a71.tex new file mode 100644 index 00000000..76f67d67 --- /dev/null +++ b/sail_latex_riscv/typezextstatus48f045aa452fc429aaaaf8df3f7b4a71.tex @@ -0,0 +1 @@ +enum ExtStatus = {Off, Initial, Clean, Dirty} diff --git a/sail_latex_riscv/typezf_bin_op_d997af8255aaaca7c24b987d847247564.tex b/sail_latex_riscv/typezf_bin_op_d997af8255aaaca7c24b987d847247564.tex new file mode 100644 index 00000000..406f8b5c --- /dev/null +++ b/sail_latex_riscv/typezf_bin_op_d997af8255aaaca7c24b987d847247564.tex @@ -0,0 +1 @@ +enum f_bin_op_D = {FSGNJ_D, FSGNJN_D, FSGNJX_D, FMIN_D, FMAX_D, FEQ_D, FLT_D, FLE_D} diff --git a/sail_latex_riscv/typezf_bin_op_s70d2d316fdfc1f5fd4d53696fd688829.tex b/sail_latex_riscv/typezf_bin_op_s70d2d316fdfc1f5fd4d53696fd688829.tex new file mode 100644 index 00000000..111f6274 --- /dev/null +++ b/sail_latex_riscv/typezf_bin_op_s70d2d316fdfc1f5fd4d53696fd688829.tex @@ -0,0 +1 @@ +enum f_bin_op_S = {FSGNJ_S, FSGNJN_S, FSGNJX_S, FMIN_S, FMAX_S, FEQ_S, FLT_S, FLE_S} diff --git a/sail_latex_riscv/typezf_bin_rm_op_d17db6dd54145474f7e451ccb8f074943.tex b/sail_latex_riscv/typezf_bin_rm_op_d17db6dd54145474f7e451ccb8f074943.tex new file mode 100644 index 00000000..c5047c21 --- /dev/null +++ b/sail_latex_riscv/typezf_bin_rm_op_d17db6dd54145474f7e451ccb8f074943.tex @@ -0,0 +1 @@ +enum f_bin_rm_op_D = {FADD_D, FSUB_D, FMUL_D, FDIV_D} diff --git a/sail_latex_riscv/typezf_bin_rm_op_s0fd11305b9d3dfc93e566ad91732c086.tex b/sail_latex_riscv/typezf_bin_rm_op_s0fd11305b9d3dfc93e566ad91732c086.tex new file mode 100644 index 00000000..ce5a56a8 --- /dev/null +++ b/sail_latex_riscv/typezf_bin_rm_op_s0fd11305b9d3dfc93e566ad91732c086.tex @@ -0,0 +1 @@ +enum f_bin_rm_op_S = {FADD_S, FSUB_S, FMUL_S, FDIV_S} diff --git a/sail_latex_riscv/typezf_madd_op_d3909a9cf5d4cc7f2d6f5dc2a8683ef42.tex b/sail_latex_riscv/typezf_madd_op_d3909a9cf5d4cc7f2d6f5dc2a8683ef42.tex new file mode 100644 index 00000000..dcadb58b --- /dev/null +++ b/sail_latex_riscv/typezf_madd_op_d3909a9cf5d4cc7f2d6f5dc2a8683ef42.tex @@ -0,0 +1 @@ +enum f_madd_op_D = {FMADD_D, FMSUB_D, FNMSUB_D, FNMADD_D} diff --git a/sail_latex_riscv/typezf_madd_op_sb37be1865406477b64362e39a00e2afe.tex b/sail_latex_riscv/typezf_madd_op_sb37be1865406477b64362e39a00e2afe.tex new file mode 100644 index 00000000..e9580a0d --- /dev/null +++ b/sail_latex_riscv/typezf_madd_op_sb37be1865406477b64362e39a00e2afe.tex @@ -0,0 +1 @@ +enum f_madd_op_S = {FMADD_S, FMSUB_S, FNMSUB_S, FNMADD_S} diff --git a/sail_latex_riscv/typezf_un_op_d60d5205abfb9c0cba7b1e1dbdf6ad69e.tex b/sail_latex_riscv/typezf_un_op_d60d5205abfb9c0cba7b1e1dbdf6ad69e.tex new file mode 100644 index 00000000..65801569 --- /dev/null +++ b/sail_latex_riscv/typezf_un_op_d60d5205abfb9c0cba7b1e1dbdf6ad69e.tex @@ -0,0 +1,2 @@ +enum f_un_op_D = {FCLASS_D, /* RV32 and RV64 */ + FMV_X_D, FMV_D_X} /* RV64 only */ diff --git a/sail_latex_riscv/typezf_un_op_s286e536373f63a1fa600b8619060bb26.tex b/sail_latex_riscv/typezf_un_op_s286e536373f63a1fa600b8619060bb26.tex new file mode 100644 index 00000000..47168898 --- /dev/null +++ b/sail_latex_riscv/typezf_un_op_s286e536373f63a1fa600b8619060bb26.tex @@ -0,0 +1 @@ +enum f_un_op_S = {FCLASS_S, FMV_X_W, FMV_W_X} /* RV32 and RV64 */ diff --git a/sail_latex_riscv/typezf_un_rm_op_de2fd51e1e803f0967e3388fb50d06082.tex b/sail_latex_riscv/typezf_un_rm_op_de2fd51e1e803f0967e3388fb50d06082.tex new file mode 100644 index 00000000..339d4742 --- /dev/null +++ b/sail_latex_riscv/typezf_un_rm_op_de2fd51e1e803f0967e3388fb50d06082.tex @@ -0,0 +1,3 @@ +enum f_un_rm_op_D = {FSQRT_D, FCVT_W_D, FCVT_WU_D, FCVT_D_W, FCVT_D_WU, // RV32 and RV64 + FCVT_S_D, FCVT_D_S, + FCVT_L_D, FCVT_LU_D, FCVT_D_L, FCVT_D_LU} // RV64 only diff --git a/sail_latex_riscv/typezf_un_rm_op_sd0ea7b4f9a759adc91555b3055b8016a.tex b/sail_latex_riscv/typezf_un_rm_op_sd0ea7b4f9a759adc91555b3055b8016a.tex new file mode 100644 index 00000000..c96cc8aa --- /dev/null +++ b/sail_latex_riscv/typezf_un_rm_op_sd0ea7b4f9a759adc91555b3055b8016a.tex @@ -0,0 +1,2 @@ +enum f_un_rm_op_S = {FSQRT_S, FCVT_W_S, FCVT_WU_S, FCVT_S_W, FCVT_S_WU, // RV32 and RV64 + FCVT_L_S, FCVT_LU_S, FCVT_S_L, FCVT_S_LU} // RV64 only diff --git a/sail_latex_riscv/typezfcsrb3f3a19258d9652856cfe0e745b7acf3.tex b/sail_latex_riscv/typezfcsrb3f3a19258d9652856cfe0e745b7acf3.tex new file mode 100644 index 00000000..ce8bfa9f --- /dev/null +++ b/sail_latex_riscv/typezfcsrb3f3a19258d9652856cfe0e745b7acf3.tex @@ -0,0 +1 @@ +struct Fcsr = {Fcsr_chunk_0 : bitvector(32, dec)} diff --git a/sail_latex_riscv/typezfetchresult170a566bc6b6cd6bbb373e14725091ab.tex b/sail_latex_riscv/typezfetchresult170a566bc6b6cd6bbb373e14725091ab.tex new file mode 100644 index 00000000..3d9581ec --- /dev/null +++ b/sail_latex_riscv/typezfetchresult170a566bc6b6cd6bbb373e14725091ab.tex @@ -0,0 +1,6 @@ +union FetchResult = { + F_Ext_Error : ext_fetch_addr_error, /* For extensions */ + F_Base : word, /* Base ISA */ + F_RVC : half, /* Compressed ISA */ + F_Error : (ExceptionType, xlenbits) /* standard exception and PC */ +} diff --git a/sail_latex_riscv/typezflen27ebfaa38e1d50ee3669425f05ac8951.tex b/sail_latex_riscv/typezflen27ebfaa38e1d50ee3669425f05ac8951.tex new file mode 100644 index 00000000..9be3e70c --- /dev/null +++ b/sail_latex_riscv/typezflen27ebfaa38e1d50ee3669425f05ac8951.tex @@ -0,0 +1 @@ +type flen : Int = 64 diff --git a/sail_latex_riscv/typezflen_bytesd7ba48b222b9ef1a7ea6335686de6c81.tex b/sail_latex_riscv/typezflen_bytesd7ba48b222b9ef1a7ea6335686de6c81.tex new file mode 100644 index 00000000..e0f71d4d --- /dev/null +++ b/sail_latex_riscv/typezflen_bytesd7ba48b222b9ef1a7ea6335686de6c81.tex @@ -0,0 +1 @@ +type flen_bytes : Int = 8 diff --git a/sail_latex_riscv/typezflenbits34a10f66673a8dd853aa9dcae8af6905.tex b/sail_latex_riscv/typezflenbits34a10f66673a8dd853aa9dcae8af6905.tex new file mode 100644 index 00000000..56e45706 --- /dev/null +++ b/sail_latex_riscv/typezflenbits34a10f66673a8dd853aa9dcae8af6905.tex @@ -0,0 +1 @@ +type flenbits = #\hyperref[sailRISCVzbits]{bits}#(flen) diff --git a/sail_latex_riscv/typezfregtype005522b0120ed9774e1ab7767fd5f4aa.tex b/sail_latex_riscv/typezfregtype005522b0120ed9774e1ab7767fd5f4aa.tex new file mode 100644 index 00000000..34052246 --- /dev/null +++ b/sail_latex_riscv/typezfregtype005522b0120ed9774e1ab7767fd5f4aa.tex @@ -0,0 +1 @@ +type fregtype = flenbits diff --git a/sail_latex_riscv/typezhalf6766630885293c014a0c4687f74d88fa.tex b/sail_latex_riscv/typezhalf6766630885293c014a0c4687f74d88fa.tex new file mode 100644 index 00000000..01a1e517 --- /dev/null +++ b/sail_latex_riscv/typezhalf6766630885293c014a0c4687f74d88fa.tex @@ -0,0 +1 @@ +type half = #\hyperref[sailRISCVzbits]{bits}#(16) diff --git a/sail_latex_riscv/typezhtif_cmd11bed6786969720c8c78224801520c9a.tex b/sail_latex_riscv/typezhtif_cmd11bed6786969720c8c78224801520c9a.tex new file mode 100644 index 00000000..c461d744 --- /dev/null +++ b/sail_latex_riscv/typezhtif_cmd11bed6786969720c8c78224801520c9a.tex @@ -0,0 +1 @@ +struct htif_cmd = {htif_cmd_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezimm12deef2ca6ef7ab7db2c410afab5972c9d.tex b/sail_latex_riscv/typezimm12deef2ca6ef7ab7db2c410afab5972c9d.tex new file mode 100644 index 00000000..b36affa4 --- /dev/null +++ b/sail_latex_riscv/typezimm12deef2ca6ef7ab7db2c410afab5972c9d.tex @@ -0,0 +1 @@ +type imm12 = #\hyperref[sailRISCVzbits]{bits}#(12) diff --git a/sail_latex_riscv/typezimm20575f3ad0e57a29fe015b13b4df3641d3.tex b/sail_latex_riscv/typezimm20575f3ad0e57a29fe015b13b4df3641d3.tex new file mode 100644 index 00000000..59124528 --- /dev/null +++ b/sail_latex_riscv/typezimm20575f3ad0e57a29fe015b13b4df3641d3.tex @@ -0,0 +1 @@ +type imm20 = #\hyperref[sailRISCVzbits]{bits}#(20) diff --git a/sail_latex_riscv/typezinstruction_kinda0a17f6dfb4c893282fe838bdd846354.tex b/sail_latex_riscv/typezinstruction_kinda0a17f6dfb4c893282fe838bdd846354.tex new file mode 100644 index 00000000..561689d7 --- /dev/null +++ b/sail_latex_riscv/typezinstruction_kinda0a17f6dfb4c893282fe838bdd846354.tex @@ -0,0 +1,10 @@ +union instruction_kind = { + IK_barrier : barrier_kind, + IK_mem_read : read_kind, + IK_mem_write : write_kind, + IK_mem_rmw : (read_kind, write_kind), + IK_branch : unit, + IK_trans : trans_kind, + IK_simple : unit, + IK_cache_op : cache_op_kind +} diff --git a/sail_latex_riscv/typezinterrupt_set44973ef906c7020fc165399cdb4dc72c.tex b/sail_latex_riscv/typezinterrupt_set44973ef906c7020fc165399cdb4dc72c.tex new file mode 100644 index 00000000..8b1c9449 --- /dev/null +++ b/sail_latex_riscv/typezinterrupt_set44973ef906c7020fc165399cdb4dc72c.tex @@ -0,0 +1,5 @@ +union interrupt_set = { + Ints_Pending : xlenbits, + Ints_Delegated : xlenbits, + Ints_Empty : unit +} diff --git a/sail_latex_riscv/typezinterrupttypeea26f192039f815bc5d0d5b058b4fac2.tex b/sail_latex_riscv/typezinterrupttypeea26f192039f815bc5d0d5b058b4fac2.tex new file mode 100644 index 00000000..fb2c4337 --- /dev/null +++ b/sail_latex_riscv/typezinterrupttypeea26f192039f815bc5d0d5b058b4fac2.tex @@ -0,0 +1,11 @@ +enum InterruptType = { + I_U_Software, + I_S_Software, + I_M_Software, + I_U_Timer, + I_S_Timer, + I_M_Timer, + I_U_External, + I_S_External, + I_M_External +} diff --git a/sail_latex_riscv/typeziop4f047e83f4bb42a95f028529f28b2b82.tex b/sail_latex_riscv/typeziop4f047e83f4bb42a95f028529f28b2b82.tex new file mode 100644 index 00000000..ea17c32d --- /dev/null +++ b/sail_latex_riscv/typeziop4f047e83f4bb42a95f028529f28b2b82.tex @@ -0,0 +1,2 @@ +enum iop = {RISCV_ADDI, RISCV_SLTI, RISCV_SLTIU, + RISCV_XORI, RISCV_ORI, RISCV_ANDI} /* immediate ops */ diff --git a/sail_latex_riscv/typezlog2_cap_sizzea1e54166750a789fdd63562b89a8f0d4.tex b/sail_latex_riscv/typezlog2_cap_sizzea1e54166750a789fdd63562b89a8f0d4.tex new file mode 100644 index 00000000..0ba2a0be --- /dev/null +++ b/sail_latex_riscv/typezlog2_cap_sizzea1e54166750a789fdd63562b89a8f0d4.tex @@ -0,0 +1 @@ +type log2_cap_size : Int = 4 diff --git a/sail_latex_riscv/typezmax_mem_access644b1e3f30ca973c2c87d72a6996dab7.tex b/sail_latex_riscv/typezmax_mem_access644b1e3f30ca973c2c87d72a6996dab7.tex new file mode 100644 index 00000000..0997e4f8 --- /dev/null +++ b/sail_latex_riscv/typezmax_mem_access644b1e3f30ca973c2c87d72a6996dab7.tex @@ -0,0 +1 @@ +type max_mem_access : Int = 16 diff --git a/sail_latex_riscv/typezmcausea662f8fdb3c01a6efcbdc5abf35af73e.tex b/sail_latex_riscv/typezmcausea662f8fdb3c01a6efcbdc5abf35af73e.tex new file mode 100644 index 00000000..2f97319e --- /dev/null +++ b/sail_latex_riscv/typezmcausea662f8fdb3c01a6efcbdc5abf35af73e.tex @@ -0,0 +1 @@ +struct Mcause = {Mcause_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezmedeleg2ea875f42b3c32731b094792df4272ce.tex b/sail_latex_riscv/typezmedeleg2ea875f42b3c32731b094792df4272ce.tex new file mode 100644 index 00000000..98ef1432 --- /dev/null +++ b/sail_latex_riscv/typezmedeleg2ea875f42b3c32731b094792df4272ce.tex @@ -0,0 +1 @@ +struct Medeleg = {Medeleg_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezmem_metaf5b381cf38597ad4a56a53301483f3c2.tex b/sail_latex_riscv/typezmem_metaf5b381cf38597ad4a56a53301483f3c2.tex new file mode 100644 index 00000000..9f0f4438 --- /dev/null +++ b/sail_latex_riscv/typezmem_metaf5b381cf38597ad4a56a53301483f3c2.tex @@ -0,0 +1 @@ +type mem_meta = bool diff --git a/sail_latex_riscv/typezmemoryopresult3416532231724086920f553567ecf72c.tex b/sail_latex_riscv/typezmemoryopresult3416532231724086920f553567ecf72c.tex new file mode 100644 index 00000000..73d1c4ee --- /dev/null +++ b/sail_latex_riscv/typezmemoryopresult3416532231724086920f553567ecf72c.tex @@ -0,0 +1,4 @@ +union #\hyperref[sailRISCVzMemoryOpResult]{MemoryOpResult}# ('a : Type) = { + MemValue : 'a, + MemException : ExceptionType +} diff --git a/sail_latex_riscv/typezminterrupts12bbecae04331c3c2bd6fea56af2709c.tex b/sail_latex_riscv/typezminterrupts12bbecae04331c3c2bd6fea56af2709c.tex new file mode 100644 index 00000000..8c24e10e --- /dev/null +++ b/sail_latex_riscv/typezminterrupts12bbecae04331c3c2bd6fea56af2709c.tex @@ -0,0 +1 @@ +struct Minterrupts = {Minterrupts_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezmisaa32c2c216e0702e03f7fa6ac32ade17d.tex b/sail_latex_riscv/typezmisaa32c2c216e0702e03f7fa6ac32ade17d.tex new file mode 100644 index 00000000..5ea42931 --- /dev/null +++ b/sail_latex_riscv/typezmisaa32c2c216e0702e03f7fa6ac32ade17d.tex @@ -0,0 +1 @@ +struct Misa = {Misa_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezmstatus6adeedf6ca37e8c03608d356a04db81f.tex b/sail_latex_riscv/typezmstatus6adeedf6ca37e8c03608d356a04db81f.tex new file mode 100644 index 00000000..7d2b0ba3 --- /dev/null +++ b/sail_latex_riscv/typezmstatus6adeedf6ca37e8c03608d356a04db81f.tex @@ -0,0 +1 @@ +struct Mstatus = {Mstatus_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezmtvec31778e1eff09235941858a1d4774e45c.tex b/sail_latex_riscv/typezmtvec31778e1eff09235941858a1d4774e45c.tex new file mode 100644 index 00000000..ce80e49b --- /dev/null +++ b/sail_latex_riscv/typezmtvec31778e1eff09235941858a1d4774e45c.tex @@ -0,0 +1 @@ +struct Mtvec = {Mtvec_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezniafpdcbcae7343979e4fb47e41a0909b121f.tex b/sail_latex_riscv/typezniafpdcbcae7343979e4fb47e41a0909b121f.tex new file mode 100644 index 00000000..fc627604 --- /dev/null +++ b/sail_latex_riscv/typezniafpdcbcae7343979e4fb47e41a0909b121f.tex @@ -0,0 +1,5 @@ +union niafp = { + NIAFP_successor : unit, + NIAFP_concrete_address : #\hyperref[sailRISCVzbits]{bits}#(64), + NIAFP_indirect_address : unit +} diff --git a/sail_latex_riscv/typezniafps1c85f5c2a0d9da30d236aad9e6b48b40.tex b/sail_latex_riscv/typezniafps1c85f5c2a0d9da30d236aad9e6b48b40.tex new file mode 100644 index 00000000..f591e283 --- /dev/null +++ b/sail_latex_riscv/typezniafps1c85f5c2a0d9da30d236aad9e6b48b40.tex @@ -0,0 +1 @@ +type niafps = #\hyperref[sailRISCVzlist]{list}#(niafp) diff --git a/sail_latex_riscv/typezopcode9a1291b5342e38220790ad44491e6b07.tex b/sail_latex_riscv/typezopcode9a1291b5342e38220790ad44491e6b07.tex new file mode 100644 index 00000000..9c8c6424 --- /dev/null +++ b/sail_latex_riscv/typezopcode9a1291b5342e38220790ad44491e6b07.tex @@ -0,0 +1 @@ +type opcode = #\hyperref[sailRISCVzbits]{bits}#(7) diff --git a/sail_latex_riscv/typezoptiona3271ef8b6a63c78e6db36dac0ee6547.tex b/sail_latex_riscv/typezoptiona3271ef8b6a63c78e6db36dac0ee6547.tex new file mode 100644 index 00000000..8f70e80b --- /dev/null +++ b/sail_latex_riscv/typezoptiona3271ef8b6a63c78e6db36dac0ee6547.tex @@ -0,0 +1,4 @@ +union #\hyperref[sailRISCVzoption]{option}#('a: Type) = { + Some : 'a, + None : unit +} diff --git a/sail_latex_riscv/typezpaddr326acc54e31f94adeb46900dacee685a4f.tex b/sail_latex_riscv/typezpaddr326acc54e31f94adeb46900dacee685a4f.tex new file mode 100644 index 00000000..07208d20 --- /dev/null +++ b/sail_latex_riscv/typezpaddr326acc54e31f94adeb46900dacee685a4f.tex @@ -0,0 +1 @@ +type paddr32 = #\hyperref[sailRISCVzbits]{bits}#(34) diff --git a/sail_latex_riscv/typezpaddr64f58cecb2121bad03c9e64da6cd15339b.tex b/sail_latex_riscv/typezpaddr64f58cecb2121bad03c9e64da6cd15339b.tex new file mode 100644 index 00000000..4393ccb9 --- /dev/null +++ b/sail_latex_riscv/typezpaddr64f58cecb2121bad03c9e64da6cd15339b.tex @@ -0,0 +1 @@ +type paddr64 = #\hyperref[sailRISCVzbits]{bits}#(56) diff --git a/sail_latex_riscv/typezpmp_addr_range0c14af966e97978e2e0bea3825363bf8.tex b/sail_latex_riscv/typezpmp_addr_range0c14af966e97978e2e0bea3825363bf8.tex new file mode 100644 index 00000000..40d7517e --- /dev/null +++ b/sail_latex_riscv/typezpmp_addr_range0c14af966e97978e2e0bea3825363bf8.tex @@ -0,0 +1 @@ +type pmp_addr_range = #\hyperref[sailRISCVzoption]{option}#((xlenbits, xlenbits)) diff --git a/sail_latex_riscv/typezpmpaddrmatch1b3d520a29cdf5ebe0ae194fe06ab693.tex b/sail_latex_riscv/typezpmpaddrmatch1b3d520a29cdf5ebe0ae194fe06ab693.tex new file mode 100644 index 00000000..92360ae0 --- /dev/null +++ b/sail_latex_riscv/typezpmpaddrmatch1b3d520a29cdf5ebe0ae194fe06ab693.tex @@ -0,0 +1 @@ +enum pmpAddrMatch = {PMP_NoMatch, PMP_PartialMatch, PMP_Match} diff --git a/sail_latex_riscv/typezpmpaddrmatchtype51c8a34448b8f2bea86b1b88c958b458.tex b/sail_latex_riscv/typezpmpaddrmatchtype51c8a34448b8f2bea86b1b88c958b458.tex new file mode 100644 index 00000000..b333783f --- /dev/null +++ b/sail_latex_riscv/typezpmpaddrmatchtype51c8a34448b8f2bea86b1b88c958b458.tex @@ -0,0 +1 @@ +enum PmpAddrMatchType = {OFF, TOR, NA4, NAPOT} diff --git a/sail_latex_riscv/typezpmpcfg_entf1f5c95dff6dbc5296f79013fd3eda09.tex b/sail_latex_riscv/typezpmpcfg_entf1f5c95dff6dbc5296f79013fd3eda09.tex new file mode 100644 index 00000000..b9d45539 --- /dev/null +++ b/sail_latex_riscv/typezpmpcfg_entf1f5c95dff6dbc5296f79013fd3eda09.tex @@ -0,0 +1 @@ +struct Pmpcfg_ent = {Pmpcfg_ent_chunk_0 : bitvector(8, dec)} diff --git a/sail_latex_riscv/typezpmpmatch43c06bad055792d6d43e48c69738fa97.tex b/sail_latex_riscv/typezpmpmatch43c06bad055792d6d43e48c69738fa97.tex new file mode 100644 index 00000000..63372f8e --- /dev/null +++ b/sail_latex_riscv/typezpmpmatch43c06bad055792d6d43e48c69738fa97.tex @@ -0,0 +1 @@ +enum pmpMatch = {PMP_Success, PMP_Continue, PMP_Fail} diff --git a/sail_latex_riscv/typezpriv_leveld5cdc3b186bdc20eb05333efc3cfd01c.tex b/sail_latex_riscv/typezpriv_leveld5cdc3b186bdc20eb05333efc3cfd01c.tex new file mode 100644 index 00000000..3705ed75 --- /dev/null +++ b/sail_latex_riscv/typezpriv_leveld5cdc3b186bdc20eb05333efc3cfd01c.tex @@ -0,0 +1 @@ +type priv_level = #\hyperref[sailRISCVzbits]{bits}#(2) diff --git a/sail_latex_riscv/typezprivilege9997cec8360c7da9f3608ad36bf538cc.tex b/sail_latex_riscv/typezprivilege9997cec8360c7da9f3608ad36bf538cc.tex new file mode 100644 index 00000000..8b71127d --- /dev/null +++ b/sail_latex_riscv/typezprivilege9997cec8360c7da9f3608ad36bf538cc.tex @@ -0,0 +1 @@ +enum Privilege = {User, Supervisor, Machine} diff --git a/sail_latex_riscv/typezpte3289880ebfd8a537e73fa0b03b58db09a5.tex b/sail_latex_riscv/typezpte3289880ebfd8a537e73fa0b03b58db09a5.tex new file mode 100644 index 00000000..ebc7825a --- /dev/null +++ b/sail_latex_riscv/typezpte3289880ebfd8a537e73fa0b03b58db09a5.tex @@ -0,0 +1 @@ +type pte32 = #\hyperref[sailRISCVzbits]{bits}#(32) diff --git a/sail_latex_riscv/typezpte48f7bf6ee72ef0ed2c1101c9e605f2f127.tex b/sail_latex_riscv/typezpte48f7bf6ee72ef0ed2c1101c9e605f2f127.tex new file mode 100644 index 00000000..30b2da7c --- /dev/null +++ b/sail_latex_riscv/typezpte48f7bf6ee72ef0ed2c1101c9e605f2f127.tex @@ -0,0 +1 @@ +type pte48 = #\hyperref[sailRISCVzbits]{bits}#(64) diff --git a/sail_latex_riscv/typezpte6458e3ea8a5bd698d68e67a410a526fd60.tex b/sail_latex_riscv/typezpte6458e3ea8a5bd698d68e67a410a526fd60.tex new file mode 100644 index 00000000..95d1895d --- /dev/null +++ b/sail_latex_riscv/typezpte6458e3ea8a5bd698d68e67a410a526fd60.tex @@ -0,0 +1 @@ +type pte64 = #\hyperref[sailRISCVzbits]{bits}#(64) diff --git a/sail_latex_riscv/typezpte_bits8fb42d02184f92f56f1b4720e0954290.tex b/sail_latex_riscv/typezpte_bits8fb42d02184f92f56f1b4720e0954290.tex new file mode 100644 index 00000000..184c08c0 --- /dev/null +++ b/sail_latex_riscv/typezpte_bits8fb42d02184f92f56f1b4720e0954290.tex @@ -0,0 +1 @@ +struct PTE_Bits = {PTE_Bits_chunk_0 : bitvector(8, dec)} diff --git a/sail_latex_riscv/typezpte_checke4890d6be3f8a927bdcbd51b1a5be9d3.tex b/sail_latex_riscv/typezpte_checke4890d6be3f8a927bdcbd51b1a5be9d3.tex new file mode 100644 index 00000000..91ceea68 --- /dev/null +++ b/sail_latex_riscv/typezpte_checke4890d6be3f8a927bdcbd51b1a5be9d3.tex @@ -0,0 +1,4 @@ +union PTE_Check = { + PTE_Check_Success : ext_ptw, + PTE_Check_Failure : (ext_ptw, ext_ptw_fail) +} diff --git a/sail_latex_riscv/typezpteattribs7d3296aef3ee8195982b63fe09ada4c1.tex b/sail_latex_riscv/typezpteattribs7d3296aef3ee8195982b63fe09ada4c1.tex new file mode 100644 index 00000000..e24aeba2 --- /dev/null +++ b/sail_latex_riscv/typezpteattribs7d3296aef3ee8195982b63fe09ada4c1.tex @@ -0,0 +1 @@ +type pteAttribs = #\hyperref[sailRISCVzbits]{bits}#(8) diff --git a/sail_latex_riscv/typezptw_errore6acdb6d9897199828c918d43d6e0475.tex b/sail_latex_riscv/typezptw_errore6acdb6d9897199828c918d43d6e0475.tex new file mode 100644 index 00000000..9a187534 --- /dev/null +++ b/sail_latex_riscv/typezptw_errore6acdb6d9897199828c918d43d6e0475.tex @@ -0,0 +1,9 @@ +union PTW_Error = { + PTW_Invalid_Addr : unit, /* invalid source address */ + PTW_Access : unit, /* physical memory access error for a PTE */ + PTW_Invalid_PTE : unit, + PTW_No_Permission : unit, + PTW_Misaligned : unit, /* misaligned superpage */ + PTW_PTE_Update : unit, /* PTE update needed but not enabled */ + PTW_Ext_Error : ext_ptw_error /* parameterized for errors from extensions */ +} diff --git a/sail_latex_riscv/typezptw_result387dae5ea1a379e54bc31c478988b63d.tex b/sail_latex_riscv/typezptw_result387dae5ea1a379e54bc31c478988b63d.tex new file mode 100644 index 00000000..89d40c11 --- /dev/null +++ b/sail_latex_riscv/typezptw_result387dae5ea1a379e54bc31c478988b63d.tex @@ -0,0 +1,4 @@ +union #\hyperref[sailRISCVzPTWzyResult]{PTW\_Result}#('paddr : Type, 'pte : Type) = { + PTW_Success: ('paddr, 'pte, 'paddr, nat, bool, ext_ptw), + PTW_Failure: (PTW_Error, ext_ptw) +} diff --git a/sail_latex_riscv/typezread_kindc722f7d2aff68c2bd16feb054ed367f8.tex b/sail_latex_riscv/typezread_kindc722f7d2aff68c2bd16feb054ed367f8.tex new file mode 100644 index 00000000..e464310f --- /dev/null +++ b/sail_latex_riscv/typezread_kindc722f7d2aff68c2bd16feb054ed367f8.tex @@ -0,0 +1,14 @@ +enum read_kind = { + Read_plain, + Read_reserve, + Read_acquire, + Read_exclusive, + Read_exclusive_acquire, + Read_stream, + Read_RISCV_acquire, + Read_RISCV_strong_acquire, + Read_RISCV_reserved, + Read_RISCV_reserved_acquire, + Read_RISCV_reserved_strong_acquire, + Read_X86_locked +} diff --git a/sail_latex_riscv/typezregfpedcf3a6440b11288a4e07504f1ebdfae.tex b/sail_latex_riscv/typezregfpedcf3a6440b11288a4e07504f1ebdfae.tex new file mode 100644 index 00000000..b1adee86 --- /dev/null +++ b/sail_latex_riscv/typezregfpedcf3a6440b11288a4e07504f1ebdfae.tex @@ -0,0 +1,6 @@ +union regfp = { + RFull : string, + RSlice : (string,nat,nat), + RSliceBit : (string,nat), + RField : (string,string) +} diff --git a/sail_latex_riscv/typezregfps6fc0ab735834848cecec1fbd72e56328.tex b/sail_latex_riscv/typezregfps6fc0ab735834848cecec1fbd72e56328.tex new file mode 100644 index 00000000..886b761e --- /dev/null +++ b/sail_latex_riscv/typezregfps6fc0ab735834848cecec1fbd72e56328.tex @@ -0,0 +1 @@ +type regfps = #\hyperref[sailRISCVzlist]{list}#(regfp) diff --git a/sail_latex_riscv/typezregidxb20ed6db135b3db9440370ddc1897517.tex b/sail_latex_riscv/typezregidxb20ed6db135b3db9440370ddc1897517.tex new file mode 100644 index 00000000..cf83b7cd --- /dev/null +++ b/sail_latex_riscv/typezregidxb20ed6db135b3db9440370ddc1897517.tex @@ -0,0 +1 @@ +type regidx = #\hyperref[sailRISCVzbits]{bits}#(5) diff --git a/sail_latex_riscv/typezregno1c2cd9b00ff5d991528ec5d711c3ace5.tex b/sail_latex_riscv/typezregno1c2cd9b00ff5d991528ec5d711c3ace5.tex new file mode 100644 index 00000000..3b04a222 --- /dev/null +++ b/sail_latex_riscv/typezregno1c2cd9b00ff5d991528ec5d711c3ace5.tex @@ -0,0 +1 @@ +type #\hyperref[sailRISCVzregno]{regno}# ('n : Int), 0 <= 'n < 32 = atom('n) diff --git a/sail_latex_riscv/typezregtype0be936c0d9e150ad1beff99e08691cf8.tex b/sail_latex_riscv/typezregtype0be936c0d9e150ad1beff99e08691cf8.tex new file mode 100644 index 00000000..c99051ed --- /dev/null +++ b/sail_latex_riscv/typezregtype0be936c0d9e150ad1beff99e08691cf8.tex @@ -0,0 +1 @@ +type regtype = Capability diff --git a/sail_latex_riscv/typezretired3cb36a9311620933468743a8b2d2f6f4.tex b/sail_latex_riscv/typezretired3cb36a9311620933468743a8b2d2f6f4.tex new file mode 100644 index 00000000..c77a063c --- /dev/null +++ b/sail_latex_riscv/typezretired3cb36a9311620933468743a8b2d2f6f4.tex @@ -0,0 +1 @@ +enum Retired = {RETIRE_SUCCESS, RETIRE_FAIL} diff --git a/sail_latex_riscv/typezrop291ca9b0f81265d59b554cd7976da946.tex b/sail_latex_riscv/typezrop291ca9b0f81265d59b554cd7976da946.tex new file mode 100644 index 00000000..85590682 --- /dev/null +++ b/sail_latex_riscv/typezrop291ca9b0f81265d59b554cd7976da946.tex @@ -0,0 +1,3 @@ +enum rop = {RISCV_ADD, RISCV_SUB, RISCV_SLL, RISCV_SLT, + RISCV_SLTU, RISCV_XOR, RISCV_SRL, RISCV_SRA, + RISCV_OR, RISCV_AND} /* reg-reg ops */ diff --git a/sail_latex_riscv/typezropw43e7b9e2c8f71c945acf86b7ec6e0687.tex b/sail_latex_riscv/typezropw43e7b9e2c8f71c945acf86b7ec6e0687.tex new file mode 100644 index 00000000..49b4c993 --- /dev/null +++ b/sail_latex_riscv/typezropw43e7b9e2c8f71c945acf86b7ec6e0687.tex @@ -0,0 +1,2 @@ +enum ropw = {RISCV_ADDW, RISCV_SUBW, RISCV_SLLW, + RISCV_SRLW, RISCV_SRAW} /* reg-reg 32-bit ops */ diff --git a/sail_latex_riscv/typezrounding_modea8ccd05712e3eb82022c72b8440f235b.tex b/sail_latex_riscv/typezrounding_modea8ccd05712e3eb82022c72b8440f235b.tex new file mode 100644 index 00000000..72430b98 --- /dev/null +++ b/sail_latex_riscv/typezrounding_modea8ccd05712e3eb82022c72b8440f235b.tex @@ -0,0 +1 @@ +enum rounding_mode = {RM_RNE, RM_RTZ, RM_RDN, RM_RUP, RM_RMM, RM_DYN} diff --git a/sail_latex_riscv/typezsatp321d6ed78cf9005ac8e6444a423cd6e618.tex b/sail_latex_riscv/typezsatp321d6ed78cf9005ac8e6444a423cd6e618.tex new file mode 100644 index 00000000..4c3c3463 --- /dev/null +++ b/sail_latex_riscv/typezsatp321d6ed78cf9005ac8e6444a423cd6e618.tex @@ -0,0 +1 @@ +struct Satp32 = {Satp32_chunk_0 : bitvector(32, dec)} diff --git a/sail_latex_riscv/typezsatp64bc81c51aa01ca27913d2b0a8ed23d481.tex b/sail_latex_riscv/typezsatp64bc81c51aa01ca27913d2b0a8ed23d481.tex new file mode 100644 index 00000000..f4e602f9 --- /dev/null +++ b/sail_latex_riscv/typezsatp64bc81c51aa01ca27913d2b0a8ed23d481.tex @@ -0,0 +1 @@ +struct Satp64 = {Satp64_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezsatp_mode578b50fd69503e82abb4182613570ec9.tex b/sail_latex_riscv/typezsatp_mode578b50fd69503e82abb4182613570ec9.tex new file mode 100644 index 00000000..92da9fbf --- /dev/null +++ b/sail_latex_riscv/typezsatp_mode578b50fd69503e82abb4182613570ec9.tex @@ -0,0 +1 @@ +type satp_mode = #\hyperref[sailRISCVzbits]{bits}#(4) diff --git a/sail_latex_riscv/typezsatpmodedc53ce733006f254af9d4e33c8ed6401.tex b/sail_latex_riscv/typezsatpmodedc53ce733006f254af9d4e33c8ed6401.tex new file mode 100644 index 00000000..4b70093f --- /dev/null +++ b/sail_latex_riscv/typezsatpmodedc53ce733006f254af9d4e33c8ed6401.tex @@ -0,0 +1 @@ +enum SATPMode = {Sbare, Sv32, Sv39, Sv48} diff --git a/sail_latex_riscv/typezscreg7666c10c12f9f7ff3cd4397f32a77413.tex b/sail_latex_riscv/typezscreg7666c10c12f9f7ff3cd4397f32a77413.tex new file mode 100644 index 00000000..1f6d6a4d --- /dev/null +++ b/sail_latex_riscv/typezscreg7666c10c12f9f7ff3cd4397f32a77413.tex @@ -0,0 +1 @@ +type screg = #\hyperref[sailRISCVzbits]{bits}#(5) diff --git a/sail_latex_riscv/typezsedeleg261f8092f9d360d308a10bcbcc83c5f6.tex b/sail_latex_riscv/typezsedeleg261f8092f9d360d308a10bcbcc83c5f6.tex new file mode 100644 index 00000000..58599348 --- /dev/null +++ b/sail_latex_riscv/typezsedeleg261f8092f9d360d308a10bcbcc83c5f6.tex @@ -0,0 +1 @@ +struct Sedeleg = {Sedeleg_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezsinterrupts37e2ae8cbcb085a9455d8333ab820af3.tex b/sail_latex_riscv/typezsinterrupts37e2ae8cbcb085a9455d8333ab820af3.tex new file mode 100644 index 00000000..71d75499 --- /dev/null +++ b/sail_latex_riscv/typezsinterrupts37e2ae8cbcb085a9455d8333ab820af3.tex @@ -0,0 +1 @@ +struct Sinterrupts = {Sinterrupts_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezsop278747973081fc221bd6ffe68d2fa910.tex b/sail_latex_riscv/typezsop278747973081fc221bd6ffe68d2fa910.tex new file mode 100644 index 00000000..4b3f853b --- /dev/null +++ b/sail_latex_riscv/typezsop278747973081fc221bd6ffe68d2fa910.tex @@ -0,0 +1 @@ +enum sop = {RISCV_SLLI, RISCV_SRLI, RISCV_SRAI} /* shift ops */ diff --git a/sail_latex_riscv/typezsopw29bbaf9eb4401b2d853623bfd0698c6e.tex b/sail_latex_riscv/typezsopw29bbaf9eb4401b2d853623bfd0698c6e.tex new file mode 100644 index 00000000..7379269a --- /dev/null +++ b/sail_latex_riscv/typezsopw29bbaf9eb4401b2d853623bfd0698c6e.tex @@ -0,0 +1,2 @@ +enum sopw = {RISCV_SLLIW, RISCV_SRLIW, + RISCV_SRAIW} /* RV64-only shift ops */ diff --git a/sail_latex_riscv/typezsstatusb3811444f066c3543008d60a23f2fb4b.tex b/sail_latex_riscv/typezsstatusb3811444f066c3543008d60a23f2fb4b.tex new file mode 100644 index 00000000..1b20994b --- /dev/null +++ b/sail_latex_riscv/typezsstatusb3811444f066c3543008d60a23f2fb4b.tex @@ -0,0 +1 @@ +struct Sstatus = {Sstatus_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezsv32_paddr9f5cfa9b0e96f55368dd46c5e00148a5.tex b/sail_latex_riscv/typezsv32_paddr9f5cfa9b0e96f55368dd46c5e00148a5.tex new file mode 100644 index 00000000..86f0e010 --- /dev/null +++ b/sail_latex_riscv/typezsv32_paddr9f5cfa9b0e96f55368dd46c5e00148a5.tex @@ -0,0 +1 @@ +struct SV32_Paddr = {SV32_Paddr_chunk_0 : bitvector(34, dec)} diff --git a/sail_latex_riscv/typezsv32_pte054d26e26929f0189a30c1313f7f54e1.tex b/sail_latex_riscv/typezsv32_pte054d26e26929f0189a30c1313f7f54e1.tex new file mode 100644 index 00000000..b5fdc997 --- /dev/null +++ b/sail_latex_riscv/typezsv32_pte054d26e26929f0189a30c1313f7f54e1.tex @@ -0,0 +1 @@ +struct SV32_PTE = {SV32_PTE_chunk_0 : bitvector(32, dec)} diff --git a/sail_latex_riscv/typezsv32_vaddre98811ac62644b6d3e91ca2d91e5afb3.tex b/sail_latex_riscv/typezsv32_vaddre98811ac62644b6d3e91ca2d91e5afb3.tex new file mode 100644 index 00000000..6e0fdce2 --- /dev/null +++ b/sail_latex_riscv/typezsv32_vaddre98811ac62644b6d3e91ca2d91e5afb3.tex @@ -0,0 +1 @@ +struct SV32_Vaddr = {SV32_Vaddr_chunk_0 : bitvector(32, dec)} diff --git a/sail_latex_riscv/typezsv39_paddr8e7ac2ddc4a718336a4f3894cdd91edd.tex b/sail_latex_riscv/typezsv39_paddr8e7ac2ddc4a718336a4f3894cdd91edd.tex new file mode 100644 index 00000000..0428afe5 --- /dev/null +++ b/sail_latex_riscv/typezsv39_paddr8e7ac2ddc4a718336a4f3894cdd91edd.tex @@ -0,0 +1 @@ +struct SV39_Paddr = {SV39_Paddr_chunk_0 : bitvector(56, dec)} diff --git a/sail_latex_riscv/typezsv39_ptea9e6dd73ae92b5be63b2a7edb5ccc8a3.tex b/sail_latex_riscv/typezsv39_ptea9e6dd73ae92b5be63b2a7edb5ccc8a3.tex new file mode 100644 index 00000000..d329fe8e --- /dev/null +++ b/sail_latex_riscv/typezsv39_ptea9e6dd73ae92b5be63b2a7edb5ccc8a3.tex @@ -0,0 +1 @@ +struct SV39_PTE = {SV39_PTE_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezsv39_vaddr9f1c1a92c2c683b5b23ddacf71051c03.tex b/sail_latex_riscv/typezsv39_vaddr9f1c1a92c2c683b5b23ddacf71051c03.tex new file mode 100644 index 00000000..5ef3e45b --- /dev/null +++ b/sail_latex_riscv/typezsv39_vaddr9f1c1a92c2c683b5b23ddacf71051c03.tex @@ -0,0 +1 @@ +struct SV39_Vaddr = {SV39_Vaddr_chunk_0 : bitvector(39, dec)} diff --git a/sail_latex_riscv/typezsv48_paddrb31db8c73707db172008fed5607c9247.tex b/sail_latex_riscv/typezsv48_paddrb31db8c73707db172008fed5607c9247.tex new file mode 100644 index 00000000..be24e2e5 --- /dev/null +++ b/sail_latex_riscv/typezsv48_paddrb31db8c73707db172008fed5607c9247.tex @@ -0,0 +1 @@ +struct SV48_Paddr = {SV48_Paddr_chunk_0 : bitvector(56, dec)} diff --git a/sail_latex_riscv/typezsv48_pte3a2f757f22affd3d18dd7c046956b713.tex b/sail_latex_riscv/typezsv48_pte3a2f757f22affd3d18dd7c046956b713.tex new file mode 100644 index 00000000..93ce7cb9 --- /dev/null +++ b/sail_latex_riscv/typezsv48_pte3a2f757f22affd3d18dd7c046956b713.tex @@ -0,0 +1 @@ +struct SV48_PTE = {SV48_PTE_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezsv48_vaddrd3fdeb6a4cba35ed677a6112bb677bc2.tex b/sail_latex_riscv/typezsv48_vaddrd3fdeb6a4cba35ed677a6112bb677bc2.tex new file mode 100644 index 00000000..a721519e --- /dev/null +++ b/sail_latex_riscv/typezsv48_vaddrd3fdeb6a4cba35ed677a6112bb677bc2.tex @@ -0,0 +1 @@ +struct SV48_Vaddr = {SV48_Vaddr_chunk_0 : bitvector(48, dec)} diff --git a/sail_latex_riscv/typezsync_exceptionf6f925de3b34f9256b962854b6415d97.tex b/sail_latex_riscv/typezsync_exceptionf6f925de3b34f9256b962854b6415d97.tex new file mode 100644 index 00000000..3f092c9d --- /dev/null +++ b/sail_latex_riscv/typezsync_exceptionf6f925de3b34f9256b962854b6415d97.tex @@ -0,0 +1,5 @@ +struct sync_exception = { + trap : ExceptionType, + excinfo : #\hyperref[sailRISCVzoption]{option}#(xlenbits), + ext : #\hyperref[sailRISCVzoption]{option}#(ext_exception) /* for extensions */ +} diff --git a/sail_latex_riscv/typeztagaddrbitsc26f5e6e74dd7ca6d16ebef3163d1a53.tex b/sail_latex_riscv/typeztagaddrbitsc26f5e6e74dd7ca6d16ebef3163d1a53.tex new file mode 100644 index 00000000..d5f6262c --- /dev/null +++ b/sail_latex_riscv/typeztagaddrbitsc26f5e6e74dd7ca6d16ebef3163d1a53.tex @@ -0,0 +1 @@ +type tagaddrbits = #\hyperref[sailRISCVzbits]{bits}#(xlen - log2_cap_size) diff --git a/sail_latex_riscv/typeztlb39_entrya6d01947ae0af49073403c37a147bc7a.tex b/sail_latex_riscv/typeztlb39_entrya6d01947ae0af49073403c37a147bc7a.tex new file mode 100644 index 00000000..53752230 --- /dev/null +++ b/sail_latex_riscv/typeztlb39_entrya6d01947ae0af49073403c37a147bc7a.tex @@ -0,0 +1 @@ +type TLB39_Entry = #\hyperref[sailRISCVzTLBzyEntry]{TLB\_Entry}#(16, 39, 56, 64) diff --git a/sail_latex_riscv/typeztlb48_entry26abc9d10a3e265edd1da0902c832cee.tex b/sail_latex_riscv/typeztlb48_entry26abc9d10a3e265edd1da0902c832cee.tex new file mode 100644 index 00000000..a89154e0 --- /dev/null +++ b/sail_latex_riscv/typeztlb48_entry26abc9d10a3e265edd1da0902c832cee.tex @@ -0,0 +1 @@ +type TLB48_Entry = #\hyperref[sailRISCVzTLBzyEntry]{TLB\_Entry}#(16, 48, 56, 64) diff --git a/sail_latex_riscv/typeztlb_entryd6a3e312d7372e7db4df8f6c3707b5fa.tex b/sail_latex_riscv/typeztlb_entryd6a3e312d7372e7db4df8f6c3707b5fa.tex new file mode 100644 index 00000000..a36d278a --- /dev/null +++ b/sail_latex_riscv/typeztlb_entryd6a3e312d7372e7db4df8f6c3707b5fa.tex @@ -0,0 +1,11 @@ +struct #\hyperref[sailRISCVzTLBzyEntry]{TLB\_Entry}#('asidlen: Int, 'valen: Int, 'palen: Int, 'ptelen: Int) = { + asid : #\hyperref[sailRISCVzbits]{bits}#('asidlen), + global : bool, + vAddr : #\hyperref[sailRISCVzbits]{bits}#('valen), /* VPN */ + pAddr : #\hyperref[sailRISCVzbits]{bits}#('palen), /* PPN */ + vMatchMask : #\hyperref[sailRISCVzbits]{bits}#('valen), /* matching mask for superpages */ + vAddrMask : #\hyperref[sailRISCVzbits]{bits}#('valen), /* selection mask for superpages */ + pte : #\hyperref[sailRISCVzbits]{bits}#('ptelen), /* PTE */ + pteAddr : #\hyperref[sailRISCVzbits]{bits}#('palen), /* for dirty writeback */ + age : #\hyperref[sailRISCVzbits]{bits}#(64) +} diff --git a/sail_latex_riscv/typeztr_result3a5e84bc36b624bd12e1a801e779c4c4.tex b/sail_latex_riscv/typeztr_result3a5e84bc36b624bd12e1a801e779c4c4.tex new file mode 100644 index 00000000..af358f30 --- /dev/null +++ b/sail_latex_riscv/typeztr_result3a5e84bc36b624bd12e1a801e779c4c4.tex @@ -0,0 +1,4 @@ +union #\hyperref[sailRISCVzTRzyResult]{TR\_Result}#('paddr : Type, 'failure : Type) = { + TR_Address : ('paddr, ext_ptw), + TR_Failure : ('failure, ext_ptw) +} diff --git a/sail_latex_riscv/typeztrans_kind8352eb8eb0b209f0054bd957c33bf07d.tex b/sail_latex_riscv/typeztrans_kind8352eb8eb0b209f0054bd957c33bf07d.tex new file mode 100644 index 00000000..cc497c7d --- /dev/null +++ b/sail_latex_riscv/typeztrans_kind8352eb8eb0b209f0054bd957c33bf07d.tex @@ -0,0 +1,5 @@ +enum trans_kind = { + Transaction_start, + Transaction_commit, + Transaction_abort +} diff --git a/sail_latex_riscv/typeztrapvectormodecc7f1b98e2e9e9062e5f9a94be7a00dd.tex b/sail_latex_riscv/typeztrapvectormodecc7f1b98e2e9e9062e5f9a94be7a00dd.tex new file mode 100644 index 00000000..75ae2430 --- /dev/null +++ b/sail_latex_riscv/typeztrapvectormodecc7f1b98e2e9e9062e5f9a94be7a00dd.tex @@ -0,0 +1 @@ +enum TrapVectorMode = {TV_Direct, TV_Vector, TV_Reserved} diff --git a/sail_latex_riscv/typeztv_modea724d5138c36f1ab6005c9051bd94ea0.tex b/sail_latex_riscv/typeztv_modea724d5138c36f1ab6005c9051bd94ea0.tex new file mode 100644 index 00000000..8748a4b7 --- /dev/null +++ b/sail_latex_riscv/typeztv_modea724d5138c36f1ab6005c9051bd94ea0.tex @@ -0,0 +1 @@ +type tv_mode = #\hyperref[sailRISCVzbits]{bits}#(2) diff --git a/sail_latex_riscv/typezuinterrupts1427c63818d0a5c9cb26ba06e84f503f.tex b/sail_latex_riscv/typezuinterrupts1427c63818d0a5c9cb26ba06e84f503f.tex new file mode 100644 index 00000000..0db7bc5f --- /dev/null +++ b/sail_latex_riscv/typezuinterrupts1427c63818d0a5c9cb26ba06e84f503f.tex @@ -0,0 +1 @@ +struct Uinterrupts = {Uinterrupts_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezuopd0b3f6267a24e3937a9850ce9ebaa872.tex b/sail_latex_riscv/typezuopd0b3f6267a24e3937a9850ce9ebaa872.tex new file mode 100644 index 00000000..da9cb29f --- /dev/null +++ b/sail_latex_riscv/typezuopd0b3f6267a24e3937a9850ce9ebaa872.tex @@ -0,0 +1 @@ +enum uop = {RISCV_LUI, RISCV_AUIPC} /* upper immediate ops */ diff --git a/sail_latex_riscv/typezustatusea9ad819ad5ad1c26e0977e4f7a545d6.tex b/sail_latex_riscv/typezustatusea9ad819ad5ad1c26e0977e4f7a545d6.tex new file mode 100644 index 00000000..ece37c6b --- /dev/null +++ b/sail_latex_riscv/typezustatusea9ad819ad5ad1c26e0977e4f7a545d6.tex @@ -0,0 +1 @@ +struct Ustatus = {Ustatus_chunk_0 : bitvector(64, dec)} diff --git a/sail_latex_riscv/typezvaddr321f5ce490361ac653dc4efb96fb3a4c98.tex b/sail_latex_riscv/typezvaddr321f5ce490361ac653dc4efb96fb3a4c98.tex new file mode 100644 index 00000000..62bd7052 --- /dev/null +++ b/sail_latex_riscv/typezvaddr321f5ce490361ac653dc4efb96fb3a4c98.tex @@ -0,0 +1 @@ +type vaddr32 = #\hyperref[sailRISCVzbits]{bits}#(32) diff --git a/sail_latex_riscv/typezvaddr39d9a5d0d949c4cbbbc71c053903cf73cb.tex b/sail_latex_riscv/typezvaddr39d9a5d0d949c4cbbbc71c053903cf73cb.tex new file mode 100644 index 00000000..1590864b --- /dev/null +++ b/sail_latex_riscv/typezvaddr39d9a5d0d949c4cbbbc71c053903cf73cb.tex @@ -0,0 +1 @@ +type vaddr39 = #\hyperref[sailRISCVzbits]{bits}#(39) diff --git a/sail_latex_riscv/typezvaddr4805a60a23d20e81c5ff9e6a5609aea22f.tex b/sail_latex_riscv/typezvaddr4805a60a23d20e81c5ff9e6a5609aea22f.tex new file mode 100644 index 00000000..c8e60ee6 --- /dev/null +++ b/sail_latex_riscv/typezvaddr4805a60a23d20e81c5ff9e6a5609aea22f.tex @@ -0,0 +1 @@ +type vaddr48 = #\hyperref[sailRISCVzbits]{bits}#(48) diff --git a/sail_latex_riscv/typezword9ee2a7d7876193e4985e692f6ae78f08.tex b/sail_latex_riscv/typezword9ee2a7d7876193e4985e692f6ae78f08.tex new file mode 100644 index 00000000..0ebb81bb --- /dev/null +++ b/sail_latex_riscv/typezword9ee2a7d7876193e4985e692f6ae78f08.tex @@ -0,0 +1 @@ +type word = #\hyperref[sailRISCVzbits]{bits}#(32) diff --git a/sail_latex_riscv/typezword_width15338b31164a0d031656f7f88e6114c8.tex b/sail_latex_riscv/typezword_width15338b31164a0d031656f7f88e6114c8.tex new file mode 100644 index 00000000..5a762ff3 --- /dev/null +++ b/sail_latex_riscv/typezword_width15338b31164a0d031656f7f88e6114c8.tex @@ -0,0 +1 @@ +enum word_width = {BYTE, HALF, WORD, DOUBLE} diff --git a/sail_latex_riscv/typezwrite_kindd407cee84c148660ae0b73dee4f0ddc7.tex b/sail_latex_riscv/typezwrite_kindd407cee84c148660ae0b73dee4f0ddc7.tex new file mode 100644 index 00000000..bf4bdc4c --- /dev/null +++ b/sail_latex_riscv/typezwrite_kindd407cee84c148660ae0b73dee4f0ddc7.tex @@ -0,0 +1,13 @@ +enum write_kind = { + Write_plain, + Write_conditional, + Write_release, + Write_exclusive, + Write_exclusive_release, + Write_RISCV_release, + Write_RISCV_strong_release, + Write_RISCV_conditional, + Write_RISCV_conditional_release, + Write_RISCV_conditional_strong_release, + Write_X86_locked +} diff --git a/sail_latex_riscv/typezxlen69b5c0c212b6eef630aa879251a43faf.tex b/sail_latex_riscv/typezxlen69b5c0c212b6eef630aa879251a43faf.tex new file mode 100644 index 00000000..5fd23721 --- /dev/null +++ b/sail_latex_riscv/typezxlen69b5c0c212b6eef630aa879251a43faf.tex @@ -0,0 +1 @@ +type xlen : Int = 64 diff --git a/sail_latex_riscv/typezxlen_bytesee19340a9dc2d174c74e7e66789a8ce5.tex b/sail_latex_riscv/typezxlen_bytesee19340a9dc2d174c74e7e66789a8ce5.tex new file mode 100644 index 00000000..1c841430 --- /dev/null +++ b/sail_latex_riscv/typezxlen_bytesee19340a9dc2d174c74e7e66789a8ce5.tex @@ -0,0 +1 @@ +type xlen_bytes : Int = 8 diff --git a/sail_latex_riscv/typezxlenbitsf5ff3be63c10995c090bf7946ccc6ec1.tex b/sail_latex_riscv/typezxlenbitsf5ff3be63c10995c090bf7946ccc6ec1.tex new file mode 100644 index 00000000..1cea5f5f --- /dev/null +++ b/sail_latex_riscv/typezxlenbitsf5ff3be63c10995c090bf7946ccc6ec1.tex @@ -0,0 +1 @@ +type xlenbits = #\hyperref[sailRISCVzbits]{bits}#(xlen) diff --git a/sail_latex_riscv/valz__barrier9c91ff87b358aa40ed8f2b1e1d97f44c.tex b/sail_latex_riscv/valz__barrier9c91ff87b358aa40ed8f2b1e1d97f44c.tex new file mode 100644 index 00000000..3415518d --- /dev/null +++ b/sail_latex_riscv/valz__barrier9c91ff87b358aa40ed8f2b1e1d97f44c.tex @@ -0,0 +1 @@ +__barrier : barrier_kind -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz__bitfield_deref5ed587b7c1b91cf82e42f865304262ca.tex b/sail_latex_riscv/valz__bitfield_deref5ed587b7c1b91cf82e42f865304262ca.tex new file mode 100644 index 00000000..3e8b4d9b --- /dev/null +++ b/sail_latex_riscv/valz__bitfield_deref5ed587b7c1b91cf82e42f865304262ca.tex @@ -0,0 +1 @@ +__bitfield_deref : forall ('a : Type). register('a) -> 'a \ No newline at end of file diff --git a/sail_latex_riscv/valz__branch_announce3f5ec48a7e84580ebc85c9d355048c29.tex b/sail_latex_riscv/valz__branch_announce3f5ec48a7e84580ebc85c9d355048c29.tex new file mode 100644 index 00000000..a28e573c --- /dev/null +++ b/sail_latex_riscv/valz__branch_announce3f5ec48a7e84580ebc85c9d355048c29.tex @@ -0,0 +1 @@ +__branch_announce : forall (constant 'addrsize : Int), 'addrsize in {32, 64}. (int('addrsize), bits('addrsize)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz__cache_maintenance664ff31aad5ce99f3549048fee01a578.tex b/sail_latex_riscv/valz__cache_maintenance664ff31aad5ce99f3549048fee01a578.tex new file mode 100644 index 00000000..f8f3bc84 --- /dev/null +++ b/sail_latex_riscv/valz__cache_maintenance664ff31aad5ce99f3549048fee01a578.tex @@ -0,0 +1,2 @@ +__cache_maintenance : forall (constant 'addrsize : Int), 'addrsize in {32, 64}. + (cache_op_kind, int('addrsize), bits('addrsize)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz__deref1dbc379e24bd1b182e1db755dea8c453.tex b/sail_latex_riscv/valz__deref1dbc379e24bd1b182e1db755dea8c453.tex new file mode 100644 index 00000000..66b83401 --- /dev/null +++ b/sail_latex_riscv/valz__deref1dbc379e24bd1b182e1db755dea8c453.tex @@ -0,0 +1 @@ +__deref : forall ('a : Type). register('a) -> 'a \ No newline at end of file diff --git a/sail_latex_riscv/valz__excl_res213a4f8bb9ba5c1a34b50a170a41bba0.tex b/sail_latex_riscv/valz__excl_res213a4f8bb9ba5c1a34b50a170a41bba0.tex new file mode 100644 index 00000000..e7a3e675 --- /dev/null +++ b/sail_latex_riscv/valz__excl_res213a4f8bb9ba5c1a34b50a170a41bba0.tex @@ -0,0 +1 @@ +__excl_res : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valz__ided888b8991a27578d5dd72f84db80bce.tex b/sail_latex_riscv/valz__ided888b8991a27578d5dd72f84db80bce.tex new file mode 100644 index 00000000..323b76d9 --- /dev/null +++ b/sail_latex_riscv/valz__ided888b8991a27578d5dd72f84db80bce.tex @@ -0,0 +1 @@ +__id : forall ('n : Int). int('n) -> int('n) \ No newline at end of file diff --git a/sail_latex_riscv/valz__instr_announce247eaf1a7feec56ee067d896e6f0ee3e.tex b/sail_latex_riscv/valz__instr_announce247eaf1a7feec56ee067d896e6f0ee3e.tex new file mode 100644 index 00000000..02b55c23 --- /dev/null +++ b/sail_latex_riscv/valz__instr_announce247eaf1a7feec56ee067d896e6f0ee3e.tex @@ -0,0 +1 @@ +__instr_announce : forall ('n : Int), 'n > 0. bits('n) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz__read_mem5b50614e040054739d7452238393251d.tex b/sail_latex_riscv/valz__read_mem5b50614e040054739d7452238393251d.tex new file mode 100644 index 00000000..86dca501 --- /dev/null +++ b/sail_latex_riscv/valz__read_mem5b50614e040054739d7452238393251d.tex @@ -0,0 +1,2 @@ +__read_mem : forall ('n : Int)(constant 'addrsize : Int), ('n > 0 & 'addrsize in {32, 64}). + (read_kind, int('addrsize), bits('addrsize), int('n)) -> bits(8 * 'n) \ No newline at end of file diff --git a/sail_latex_riscv/valz__read_memt00147dd8cf6dc9809e14fc1395c45ce6.tex b/sail_latex_riscv/valz__read_memt00147dd8cf6dc9809e14fc1395c45ce6.tex new file mode 100644 index 00000000..5f125ae2 --- /dev/null +++ b/sail_latex_riscv/valz__read_memt00147dd8cf6dc9809e14fc1395c45ce6.tex @@ -0,0 +1,2 @@ +__read_memt : forall ('n : Int)(constant 'addrsize : Int), ('n > 0 & 'addrsize in {32, 64}). + (read_kind, bits('addrsize), int('n)) -> (bits(8 * 'n), bit) \ No newline at end of file diff --git a/sail_latex_riscv/valz__readram_meta16c05ad578ee799cab7403aa8924f5dd.tex b/sail_latex_riscv/valz__readram_meta16c05ad578ee799cab7403aa8924f5dd.tex new file mode 100644 index 00000000..fe6f9367 --- /dev/null +++ b/sail_latex_riscv/valz__readram_meta16c05ad578ee799cab7403aa8924f5dd.tex @@ -0,0 +1 @@ +__ReadRAM_Meta : forall ('n : Int). (xlenbits, int('n)) -> mem_meta \ No newline at end of file diff --git a/sail_latex_riscv/valz__tracememoryread11a5e2cc4158cfc2c22e91249b3a83cb.tex b/sail_latex_riscv/valz__tracememoryread11a5e2cc4158cfc2c22e91249b3a83cb.tex new file mode 100644 index 00000000..2ff39602 --- /dev/null +++ b/sail_latex_riscv/valz__tracememoryread11a5e2cc4158cfc2c22e91249b3a83cb.tex @@ -0,0 +1 @@ +__TraceMemoryRead : forall ('n 'm : Int). (int('n), bits('m), bits(8 * 'n)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz__tracememorywrite59b064eac2207f0323d075cfc74a28ea.tex b/sail_latex_riscv/valz__tracememorywrite59b064eac2207f0323d075cfc74a28ea.tex new file mode 100644 index 00000000..54eaf7d6 --- /dev/null +++ b/sail_latex_riscv/valz__tracememorywrite59b064eac2207f0323d075cfc74a28ea.tex @@ -0,0 +1 @@ +__TraceMemoryWrite : forall ('n 'm : Int). (int('n), bits('m), bits(8 * 'n)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz__write_mem7fed12b7fc053a5ef3b5be1c753041b9.tex b/sail_latex_riscv/valz__write_mem7fed12b7fc053a5ef3b5be1c753041b9.tex new file mode 100644 index 00000000..025dfb18 --- /dev/null +++ b/sail_latex_riscv/valz__write_mem7fed12b7fc053a5ef3b5be1c753041b9.tex @@ -0,0 +1,2 @@ +__write_mem : forall ('n : Int)(constant 'addrsize : Int), ('n > 0 & 'addrsize in {32, 64}). + (write_kind, int('addrsize), bits('addrsize), int('n), bits(8 * 'n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valz__write_mem_ea084b77c6ab56479698cd76a013fd7cad.tex b/sail_latex_riscv/valz__write_mem_ea084b77c6ab56479698cd76a013fd7cad.tex new file mode 100644 index 00000000..815caa9b --- /dev/null +++ b/sail_latex_riscv/valz__write_mem_ea084b77c6ab56479698cd76a013fd7cad.tex @@ -0,0 +1,2 @@ +__write_mem_ea : forall ('n : Int)(constant 'addrsize : Int), ('n > 0 & 'addrsize in {32, 64}). + (write_kind, int('addrsize), bits('addrsize), int('n)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz__write_memte6e713c02b822271b225111a241edb5f.tex b/sail_latex_riscv/valz__write_memte6e713c02b822271b225111a241edb5f.tex new file mode 100644 index 00000000..6ce6396b --- /dev/null +++ b/sail_latex_riscv/valz__write_memte6e713c02b822271b225111a241edb5f.tex @@ -0,0 +1,2 @@ +__write_memt : forall ('n : Int)(constant 'addrsize : Int), ('n > 0 & 'addrsize in {32, 64}). + (write_kind, bits('addrsize), int('n), bits(8 * 'n), bit) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valz__writeram_meta071a60a48b7f4ceb27499d72826fb174.tex b/sail_latex_riscv/valz__writeram_meta071a60a48b7f4ceb27499d72826fb174.tex new file mode 100644 index 00000000..46043f4a --- /dev/null +++ b/sail_latex_riscv/valz__writeram_meta071a60a48b7f4ceb27499d72826fb174.tex @@ -0,0 +1 @@ +__WriteRAM_Meta : forall ('n : Int). (xlenbits, int('n), mem_meta) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_ccsr_bitsa5bf4f91be070c5e733b7c8dcd21079f.tex b/sail_latex_riscv/valz_get_ccsr_bitsa5bf4f91be070c5e733b7c8dcd21079f.tex new file mode 100644 index 00000000..dabe2b9f --- /dev/null +++ b/sail_latex_riscv/valz_get_ccsr_bitsa5bf4f91be070c5e733b7c8dcd21079f.tex @@ -0,0 +1 @@ +_get_ccsr_bits : ccsr -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_ccsr_cap_idx07f5b7d982282306c072600892773224.tex b/sail_latex_riscv/valz_get_ccsr_cap_idx07f5b7d982282306c072600892773224.tex new file mode 100644 index 00000000..944cd1a6 --- /dev/null +++ b/sail_latex_riscv/valz_get_ccsr_cap_idx07f5b7d982282306c072600892773224.tex @@ -0,0 +1 @@ +_get_ccsr_cap_idx : ccsr -> bitvector(6, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_ccsr_caused575f504e43b5c4f705e1e76299969a8.tex b/sail_latex_riscv/valz_get_ccsr_caused575f504e43b5c4f705e1e76299969a8.tex new file mode 100644 index 00000000..aece54c4 --- /dev/null +++ b/sail_latex_riscv/valz_get_ccsr_caused575f504e43b5c4f705e1e76299969a8.tex @@ -0,0 +1 @@ +_get_ccsr_cause : ccsr -> bitvector(5, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_ccsr_d5cb2dcaceb4937b225b4475484d2bf2d.tex b/sail_latex_riscv/valz_get_ccsr_d5cb2dcaceb4937b225b4475484d2bf2d.tex new file mode 100644 index 00000000..699ebe37 --- /dev/null +++ b/sail_latex_riscv/valz_get_ccsr_d5cb2dcaceb4937b225b4475484d2bf2d.tex @@ -0,0 +1 @@ +_get_ccsr_d : ccsr -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_ccsr_e6d359c132221ee638d3b99e5bb880b1c.tex b/sail_latex_riscv/valz_get_ccsr_e6d359c132221ee638d3b99e5bb880b1c.tex new file mode 100644 index 00000000..7006671e --- /dev/null +++ b/sail_latex_riscv/valz_get_ccsr_e6d359c132221ee638d3b99e5bb880b1c.tex @@ -0,0 +1 @@ +_get_ccsr_e : ccsr -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_counteren_bits63485ab688d4675e7f4e8ef14d9606ff.tex b/sail_latex_riscv/valz_get_counteren_bits63485ab688d4675e7f4e8ef14d9606ff.tex new file mode 100644 index 00000000..1856e99f --- /dev/null +++ b/sail_latex_riscv/valz_get_counteren_bits63485ab688d4675e7f4e8ef14d9606ff.tex @@ -0,0 +1 @@ +_get_Counteren_bits : Counteren -> bitvector(32, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_counteren_cy6e2b3bcf0f631c5bfe1602b7224ac3aa.tex b/sail_latex_riscv/valz_get_counteren_cy6e2b3bcf0f631c5bfe1602b7224ac3aa.tex new file mode 100644 index 00000000..f3fa688e --- /dev/null +++ b/sail_latex_riscv/valz_get_counteren_cy6e2b3bcf0f631c5bfe1602b7224ac3aa.tex @@ -0,0 +1 @@ +_get_Counteren_CY : Counteren -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_counteren_hpm3a5db98081f95347897bc13fea2e569f.tex b/sail_latex_riscv/valz_get_counteren_hpm3a5db98081f95347897bc13fea2e569f.tex new file mode 100644 index 00000000..83d378e5 --- /dev/null +++ b/sail_latex_riscv/valz_get_counteren_hpm3a5db98081f95347897bc13fea2e569f.tex @@ -0,0 +1 @@ +_get_Counteren_HPM : Counteren -> bitvector(29, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_counteren_ir0443e9a01364d655f672be9fb3f334c2.tex b/sail_latex_riscv/valz_get_counteren_ir0443e9a01364d655f672be9fb3f334c2.tex new file mode 100644 index 00000000..03253626 --- /dev/null +++ b/sail_latex_riscv/valz_get_counteren_ir0443e9a01364d655f672be9fb3f334c2.tex @@ -0,0 +1 @@ +_get_Counteren_IR : Counteren -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_counteren_tme8e19db38cbd8e49aa4656434c826c16.tex b/sail_latex_riscv/valz_get_counteren_tme8e19db38cbd8e49aa4656434c826c16.tex new file mode 100644 index 00000000..704f2aa9 --- /dev/null +++ b/sail_latex_riscv/valz_get_counteren_tme8e19db38cbd8e49aa4656434c826c16.tex @@ -0,0 +1 @@ +_get_Counteren_TM : Counteren -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_counterin_bits11d3d881d3130628193ac87a6d2fd74a.tex b/sail_latex_riscv/valz_get_counterin_bits11d3d881d3130628193ac87a6d2fd74a.tex new file mode 100644 index 00000000..4af8e3e8 --- /dev/null +++ b/sail_latex_riscv/valz_get_counterin_bits11d3d881d3130628193ac87a6d2fd74a.tex @@ -0,0 +1 @@ +_get_Counterin_bits : Counterin -> bitvector(32, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_counterin_cydc6f1e9f2967dff249969b51399a14ca.tex b/sail_latex_riscv/valz_get_counterin_cydc6f1e9f2967dff249969b51399a14ca.tex new file mode 100644 index 00000000..a7bffd91 --- /dev/null +++ b/sail_latex_riscv/valz_get_counterin_cydc6f1e9f2967dff249969b51399a14ca.tex @@ -0,0 +1 @@ +_get_Counterin_CY : Counterin -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_counterin_ira4b70e343466abb62da1c490774a9c7a.tex b/sail_latex_riscv/valz_get_counterin_ira4b70e343466abb62da1c490774a9c7a.tex new file mode 100644 index 00000000..e5dc1ad8 --- /dev/null +++ b/sail_latex_riscv/valz_get_counterin_ira4b70e343466abb62da1c490774a9c7a.tex @@ -0,0 +1 @@ +_get_Counterin_IR : Counterin -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_ext_pte_bits_bits65e7ce08656cda27553d43325a4acc17.tex b/sail_latex_riscv/valz_get_ext_pte_bits_bits65e7ce08656cda27553d43325a4acc17.tex new file mode 100644 index 00000000..d19d8e92 --- /dev/null +++ b/sail_latex_riscv/valz_get_ext_pte_bits_bits65e7ce08656cda27553d43325a4acc17.tex @@ -0,0 +1 @@ +_get_Ext_PTE_Bits_bits : Ext_PTE_Bits -> bitvector(10, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_ext_pte_bits_capread333ce4aba2e72cd3f2c792b515f6703a.tex b/sail_latex_riscv/valz_get_ext_pte_bits_capread333ce4aba2e72cd3f2c792b515f6703a.tex new file mode 100644 index 00000000..623adb80 --- /dev/null +++ b/sail_latex_riscv/valz_get_ext_pte_bits_capread333ce4aba2e72cd3f2c792b515f6703a.tex @@ -0,0 +1 @@ +_get_Ext_PTE_Bits_CapRead : Ext_PTE_Bits -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_ext_pte_bits_capwrite0baac5a6f85e40fbdac28ee04067e65c.tex b/sail_latex_riscv/valz_get_ext_pte_bits_capwrite0baac5a6f85e40fbdac28ee04067e65c.tex new file mode 100644 index 00000000..28fad609 --- /dev/null +++ b/sail_latex_riscv/valz_get_ext_pte_bits_capwrite0baac5a6f85e40fbdac28ee04067e65c.tex @@ -0,0 +1 @@ +_get_Ext_PTE_Bits_CapWrite : Ext_PTE_Bits -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_fcsr_bits38eb65790eec4fcba3d93a546d99637e.tex b/sail_latex_riscv/valz_get_fcsr_bits38eb65790eec4fcba3d93a546d99637e.tex new file mode 100644 index 00000000..f33962fe --- /dev/null +++ b/sail_latex_riscv/valz_get_fcsr_bits38eb65790eec4fcba3d93a546d99637e.tex @@ -0,0 +1 @@ +_get_Fcsr_bits : Fcsr -> bitvector(32, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_fcsr_fflagse7920eae191e6251650c82768d152824.tex b/sail_latex_riscv/valz_get_fcsr_fflagse7920eae191e6251650c82768d152824.tex new file mode 100644 index 00000000..5d7bc364 --- /dev/null +++ b/sail_latex_riscv/valz_get_fcsr_fflagse7920eae191e6251650c82768d152824.tex @@ -0,0 +1 @@ +_get_Fcsr_FFLAGS : Fcsr -> bitvector(5, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_fcsr_frmc585de536fb10558f0653a1315c2301e.tex b/sail_latex_riscv/valz_get_fcsr_frmc585de536fb10558f0653a1315c2301e.tex new file mode 100644 index 00000000..8e997635 --- /dev/null +++ b/sail_latex_riscv/valz_get_fcsr_frmc585de536fb10558f0653a1315c2301e.tex @@ -0,0 +1 @@ +_get_Fcsr_FRM : Fcsr -> bitvector(3, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_htif_cmd_bits1eb71429743386e681784c96e268deaf.tex b/sail_latex_riscv/valz_get_htif_cmd_bits1eb71429743386e681784c96e268deaf.tex new file mode 100644 index 00000000..5cd7e773 --- /dev/null +++ b/sail_latex_riscv/valz_get_htif_cmd_bits1eb71429743386e681784c96e268deaf.tex @@ -0,0 +1 @@ +_get_htif_cmd_bits : htif_cmd -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_htif_cmd_cmd819958801f753cde6a79cea6d1060596.tex b/sail_latex_riscv/valz_get_htif_cmd_cmd819958801f753cde6a79cea6d1060596.tex new file mode 100644 index 00000000..79b395e2 --- /dev/null +++ b/sail_latex_riscv/valz_get_htif_cmd_cmd819958801f753cde6a79cea6d1060596.tex @@ -0,0 +1 @@ +_get_htif_cmd_cmd : htif_cmd -> bitvector(8, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_htif_cmd_device49a4f976524fe1bb4129d075a7e50cb3.tex b/sail_latex_riscv/valz_get_htif_cmd_device49a4f976524fe1bb4129d075a7e50cb3.tex new file mode 100644 index 00000000..a1431a3d --- /dev/null +++ b/sail_latex_riscv/valz_get_htif_cmd_device49a4f976524fe1bb4129d075a7e50cb3.tex @@ -0,0 +1 @@ +_get_htif_cmd_device : htif_cmd -> bitvector(8, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_htif_cmd_payload61085de7e39b8efa3ae178ccc88eb7d5.tex b/sail_latex_riscv/valz_get_htif_cmd_payload61085de7e39b8efa3ae178ccc88eb7d5.tex new file mode 100644 index 00000000..bf044bf7 --- /dev/null +++ b/sail_latex_riscv/valz_get_htif_cmd_payload61085de7e39b8efa3ae178ccc88eb7d5.tex @@ -0,0 +1 @@ +_get_htif_cmd_payload : htif_cmd -> bitvector(48, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mcause_bits74f8f43c07e2abaa1ac3d45b4a2b6ba2.tex b/sail_latex_riscv/valz_get_mcause_bits74f8f43c07e2abaa1ac3d45b4a2b6ba2.tex new file mode 100644 index 00000000..70eedef6 --- /dev/null +++ b/sail_latex_riscv/valz_get_mcause_bits74f8f43c07e2abaa1ac3d45b4a2b6ba2.tex @@ -0,0 +1 @@ +_get_Mcause_bits : Mcause -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mcause_cause1bdd5398cd23fc4b4f8215c110954e19.tex b/sail_latex_riscv/valz_get_mcause_cause1bdd5398cd23fc4b4f8215c110954e19.tex new file mode 100644 index 00000000..d59eb29b --- /dev/null +++ b/sail_latex_riscv/valz_get_mcause_cause1bdd5398cd23fc4b4f8215c110954e19.tex @@ -0,0 +1 @@ +_get_Mcause_Cause : Mcause -> bitvector(63, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mcause_isinterruptca4d348b8a2eaccd2e92f7ee7d03bee7.tex b/sail_latex_riscv/valz_get_mcause_isinterruptca4d348b8a2eaccd2e92f7ee7d03bee7.tex new file mode 100644 index 00000000..818bdec0 --- /dev/null +++ b/sail_latex_riscv/valz_get_mcause_isinterruptca4d348b8a2eaccd2e92f7ee7d03bee7.tex @@ -0,0 +1 @@ +_get_Mcause_IsInterrupt : Mcause -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_bits254afc4d0ea5cd20737b995ecb86af96.tex b/sail_latex_riscv/valz_get_medeleg_bits254afc4d0ea5cd20737b995ecb86af96.tex new file mode 100644 index 00000000..9394ccef --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_bits254afc4d0ea5cd20737b995ecb86af96.tex @@ -0,0 +1 @@ +_get_Medeleg_bits : Medeleg -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_breakpointd7558e491e73df703b5f48b45fc459fb.tex b/sail_latex_riscv/valz_get_medeleg_breakpointd7558e491e73df703b5f48b45fc459fb.tex new file mode 100644 index 00000000..e006e2a3 --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_breakpointd7558e491e73df703b5f48b45fc459fb.tex @@ -0,0 +1 @@ +_get_Medeleg_Breakpoint : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_fetch_access_faulte776b2e2dd4e9f7381bf51e711dd1a07.tex b/sail_latex_riscv/valz_get_medeleg_fetch_access_faulte776b2e2dd4e9f7381bf51e711dd1a07.tex new file mode 100644 index 00000000..87d5830c --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_fetch_access_faulte776b2e2dd4e9f7381bf51e711dd1a07.tex @@ -0,0 +1 @@ +_get_Medeleg_Fetch_Access_Fault : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_fetch_addr_aligncd9c88ba625264505b33ace3265d8ea5.tex b/sail_latex_riscv/valz_get_medeleg_fetch_addr_aligncd9c88ba625264505b33ace3265d8ea5.tex new file mode 100644 index 00000000..b1f0ebd7 --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_fetch_addr_aligncd9c88ba625264505b33ace3265d8ea5.tex @@ -0,0 +1 @@ +_get_Medeleg_Fetch_Addr_Align : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_fetch_page_fault584acc3a0e750181acc1bdc03c42b15c.tex b/sail_latex_riscv/valz_get_medeleg_fetch_page_fault584acc3a0e750181acc1bdc03c42b15c.tex new file mode 100644 index 00000000..f94891ce --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_fetch_page_fault584acc3a0e750181acc1bdc03c42b15c.tex @@ -0,0 +1 @@ +_get_Medeleg_Fetch_Page_Fault : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_illegal_instre418e5763eb05a3ffb4d6c978a1e3ff3.tex b/sail_latex_riscv/valz_get_medeleg_illegal_instre418e5763eb05a3ffb4d6c978a1e3ff3.tex new file mode 100644 index 00000000..2fb9cf02 --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_illegal_instre418e5763eb05a3ffb4d6c978a1e3ff3.tex @@ -0,0 +1 @@ +_get_Medeleg_Illegal_Instr : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_load_access_fault83f8e20712f80aab31a1decf153c8956.tex b/sail_latex_riscv/valz_get_medeleg_load_access_fault83f8e20712f80aab31a1decf153c8956.tex new file mode 100644 index 00000000..98b4c328 --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_load_access_fault83f8e20712f80aab31a1decf153c8956.tex @@ -0,0 +1 @@ +_get_Medeleg_Load_Access_Fault : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_load_addr_alignb78e674217d39981dc173fc694981c59.tex b/sail_latex_riscv/valz_get_medeleg_load_addr_alignb78e674217d39981dc173fc694981c59.tex new file mode 100644 index 00000000..2a1ebc38 --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_load_addr_alignb78e674217d39981dc173fc694981c59.tex @@ -0,0 +1 @@ +_get_Medeleg_Load_Addr_Align : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_load_page_faultcad65281f15a01bca2163ece7e5c6ca2.tex b/sail_latex_riscv/valz_get_medeleg_load_page_faultcad65281f15a01bca2163ece7e5c6ca2.tex new file mode 100644 index 00000000..e519486d --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_load_page_faultcad65281f15a01bca2163ece7e5c6ca2.tex @@ -0,0 +1 @@ +_get_Medeleg_Load_Page_Fault : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_menvcalla548a3bce22dd9330ba9f237e8ccd8df.tex b/sail_latex_riscv/valz_get_medeleg_menvcalla548a3bce22dd9330ba9f237e8ccd8df.tex new file mode 100644 index 00000000..a9261309 --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_menvcalla548a3bce22dd9330ba9f237e8ccd8df.tex @@ -0,0 +1 @@ +_get_Medeleg_MEnvCall : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_samo_access_faultcb72d93dea2bae751976faa859f64fa9.tex b/sail_latex_riscv/valz_get_medeleg_samo_access_faultcb72d93dea2bae751976faa859f64fa9.tex new file mode 100644 index 00000000..745f1711 --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_samo_access_faultcb72d93dea2bae751976faa859f64fa9.tex @@ -0,0 +1 @@ +_get_Medeleg_SAMO_Access_Fault : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_samo_addr_alignad215ca9df0deef97bdff6842d7f4cb9.tex b/sail_latex_riscv/valz_get_medeleg_samo_addr_alignad215ca9df0deef97bdff6842d7f4cb9.tex new file mode 100644 index 00000000..c06a6c35 --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_samo_addr_alignad215ca9df0deef97bdff6842d7f4cb9.tex @@ -0,0 +1 @@ +_get_Medeleg_SAMO_Addr_Align : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_samo_page_fault02d4e5d413504e150668b23d70f40d9c.tex b/sail_latex_riscv/valz_get_medeleg_samo_page_fault02d4e5d413504e150668b23d70f40d9c.tex new file mode 100644 index 00000000..80c0dca2 --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_samo_page_fault02d4e5d413504e150668b23d70f40d9c.tex @@ -0,0 +1 @@ +_get_Medeleg_SAMO_Page_Fault : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_senvcall3e8e2ef741b16b80e855ffb13f17850d.tex b/sail_latex_riscv/valz_get_medeleg_senvcall3e8e2ef741b16b80e855ffb13f17850d.tex new file mode 100644 index 00000000..6906b9b1 --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_senvcall3e8e2ef741b16b80e855ffb13f17850d.tex @@ -0,0 +1 @@ +_get_Medeleg_SEnvCall : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_medeleg_uenvcallc38700f20f282265abd49a682cb3711d.tex b/sail_latex_riscv/valz_get_medeleg_uenvcallc38700f20f282265abd49a682cb3711d.tex new file mode 100644 index 00000000..c0e9087a --- /dev/null +++ b/sail_latex_riscv/valz_get_medeleg_uenvcallc38700f20f282265abd49a682cb3711d.tex @@ -0,0 +1 @@ +_get_Medeleg_UEnvCall : Medeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_minterrupts_bits9861684a481530d5524ef64aad179e28.tex b/sail_latex_riscv/valz_get_minterrupts_bits9861684a481530d5524ef64aad179e28.tex new file mode 100644 index 00000000..b48a0a2d --- /dev/null +++ b/sail_latex_riscv/valz_get_minterrupts_bits9861684a481530d5524ef64aad179e28.tex @@ -0,0 +1 @@ +_get_Minterrupts_bits : Minterrupts -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_minterrupts_mei515173f9dd00afe3be3a8f7e3877089a.tex b/sail_latex_riscv/valz_get_minterrupts_mei515173f9dd00afe3be3a8f7e3877089a.tex new file mode 100644 index 00000000..efb4d9c8 --- /dev/null +++ b/sail_latex_riscv/valz_get_minterrupts_mei515173f9dd00afe3be3a8f7e3877089a.tex @@ -0,0 +1 @@ +_get_Minterrupts_MEI : Minterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_minterrupts_msia5cfaf4688d1a0068789c380e6843d0e.tex b/sail_latex_riscv/valz_get_minterrupts_msia5cfaf4688d1a0068789c380e6843d0e.tex new file mode 100644 index 00000000..f75ea302 --- /dev/null +++ b/sail_latex_riscv/valz_get_minterrupts_msia5cfaf4688d1a0068789c380e6843d0e.tex @@ -0,0 +1 @@ +_get_Minterrupts_MSI : Minterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_minterrupts_mtia5225791c34b1551a9ad789bbc693091.tex b/sail_latex_riscv/valz_get_minterrupts_mtia5225791c34b1551a9ad789bbc693091.tex new file mode 100644 index 00000000..fcaabe1e --- /dev/null +++ b/sail_latex_riscv/valz_get_minterrupts_mtia5225791c34b1551a9ad789bbc693091.tex @@ -0,0 +1 @@ +_get_Minterrupts_MTI : Minterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_minterrupts_sei6f52e9424a41a0158d2b56253ab8fdd9.tex b/sail_latex_riscv/valz_get_minterrupts_sei6f52e9424a41a0158d2b56253ab8fdd9.tex new file mode 100644 index 00000000..0fd8003c --- /dev/null +++ b/sail_latex_riscv/valz_get_minterrupts_sei6f52e9424a41a0158d2b56253ab8fdd9.tex @@ -0,0 +1 @@ +_get_Minterrupts_SEI : Minterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_minterrupts_ssi8ebb8da6cffaa81a169231cdfe86edca.tex b/sail_latex_riscv/valz_get_minterrupts_ssi8ebb8da6cffaa81a169231cdfe86edca.tex new file mode 100644 index 00000000..e38b8768 --- /dev/null +++ b/sail_latex_riscv/valz_get_minterrupts_ssi8ebb8da6cffaa81a169231cdfe86edca.tex @@ -0,0 +1 @@ +_get_Minterrupts_SSI : Minterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_minterrupts_stic7fb02b96430cfa9febfe409633700b7.tex b/sail_latex_riscv/valz_get_minterrupts_stic7fb02b96430cfa9febfe409633700b7.tex new file mode 100644 index 00000000..eeb02980 --- /dev/null +++ b/sail_latex_riscv/valz_get_minterrupts_stic7fb02b96430cfa9febfe409633700b7.tex @@ -0,0 +1 @@ +_get_Minterrupts_STI : Minterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_minterrupts_uei0f43bea7cfb1473c624d84e67401f902.tex b/sail_latex_riscv/valz_get_minterrupts_uei0f43bea7cfb1473c624d84e67401f902.tex new file mode 100644 index 00000000..c4670c5b --- /dev/null +++ b/sail_latex_riscv/valz_get_minterrupts_uei0f43bea7cfb1473c624d84e67401f902.tex @@ -0,0 +1 @@ +_get_Minterrupts_UEI : Minterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_minterrupts_usi01d28f9f2001eba94bf8de985b2cc8cd.tex b/sail_latex_riscv/valz_get_minterrupts_usi01d28f9f2001eba94bf8de985b2cc8cd.tex new file mode 100644 index 00000000..b00e8b5c --- /dev/null +++ b/sail_latex_riscv/valz_get_minterrupts_usi01d28f9f2001eba94bf8de985b2cc8cd.tex @@ -0,0 +1 @@ +_get_Minterrupts_USI : Minterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_minterrupts_uti7d38c0c4d8098334626461d0c0734e18.tex b/sail_latex_riscv/valz_get_minterrupts_uti7d38c0c4d8098334626461d0c0734e18.tex new file mode 100644 index 00000000..5bef72f3 --- /dev/null +++ b/sail_latex_riscv/valz_get_minterrupts_uti7d38c0c4d8098334626461d0c0734e18.tex @@ -0,0 +1 @@ +_get_Minterrupts_UTI : Minterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_af461bea08dc77aa785842eb918466700.tex b/sail_latex_riscv/valz_get_misa_af461bea08dc77aa785842eb918466700.tex new file mode 100644 index 00000000..17ef69fb --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_af461bea08dc77aa785842eb918466700.tex @@ -0,0 +1 @@ +_get_Misa_A : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_b1d772b9d019b6aaad84ed1639e5e0d09.tex b/sail_latex_riscv/valz_get_misa_b1d772b9d019b6aaad84ed1639e5e0d09.tex new file mode 100644 index 00000000..38bd978f --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_b1d772b9d019b6aaad84ed1639e5e0d09.tex @@ -0,0 +1 @@ +_get_Misa_B : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_bits227fd8e446573e270b2f6ea70e25b072.tex b/sail_latex_riscv/valz_get_misa_bits227fd8e446573e270b2f6ea70e25b072.tex new file mode 100644 index 00000000..1c32e146 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_bits227fd8e446573e270b2f6ea70e25b072.tex @@ -0,0 +1 @@ +_get_Misa_bits : Misa -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_c79dc24d8a0b99e961dd504cd6b697318.tex b/sail_latex_riscv/valz_get_misa_c79dc24d8a0b99e961dd504cd6b697318.tex new file mode 100644 index 00000000..c89f58f3 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_c79dc24d8a0b99e961dd504cd6b697318.tex @@ -0,0 +1 @@ +_get_Misa_C : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_d254b68e0fd6637680c01aa4da6738280.tex b/sail_latex_riscv/valz_get_misa_d254b68e0fd6637680c01aa4da6738280.tex new file mode 100644 index 00000000..1d40c11e --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_d254b68e0fd6637680c01aa4da6738280.tex @@ -0,0 +1 @@ +_get_Misa_D : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_efde9ad5723fbd21ad73d9649cc491dd4.tex b/sail_latex_riscv/valz_get_misa_efde9ad5723fbd21ad73d9649cc491dd4.tex new file mode 100644 index 00000000..79354937 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_efde9ad5723fbd21ad73d9649cc491dd4.tex @@ -0,0 +1 @@ +_get_Misa_E : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_f684dc9ab9b0a463db4389e87dc7e784f.tex b/sail_latex_riscv/valz_get_misa_f684dc9ab9b0a463db4389e87dc7e784f.tex new file mode 100644 index 00000000..6c0abc3b --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_f684dc9ab9b0a463db4389e87dc7e784f.tex @@ -0,0 +1 @@ +_get_Misa_F : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_gcfcd286901f53880700e0bb46ee4c493.tex b/sail_latex_riscv/valz_get_misa_gcfcd286901f53880700e0bb46ee4c493.tex new file mode 100644 index 00000000..4063f1f9 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_gcfcd286901f53880700e0bb46ee4c493.tex @@ -0,0 +1 @@ +_get_Misa_G : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_hd877c2daaecfe719a9d7c418c493c805.tex b/sail_latex_riscv/valz_get_misa_hd877c2daaecfe719a9d7c418c493c805.tex new file mode 100644 index 00000000..3909edbf --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_hd877c2daaecfe719a9d7c418c493c805.tex @@ -0,0 +1 @@ +_get_Misa_H : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_ifd11140b556fe14f486f51c949a8637b.tex b/sail_latex_riscv/valz_get_misa_ifd11140b556fe14f486f51c949a8637b.tex new file mode 100644 index 00000000..45d2fa33 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_ifd11140b556fe14f486f51c949a8637b.tex @@ -0,0 +1 @@ +_get_Misa_I : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_j2bd628593035d085073fabfda59a3691.tex b/sail_latex_riscv/valz_get_misa_j2bd628593035d085073fabfda59a3691.tex new file mode 100644 index 00000000..a7f91181 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_j2bd628593035d085073fabfda59a3691.tex @@ -0,0 +1 @@ +_get_Misa_J : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_k16049cc76852c9c8026f567e68a54414.tex b/sail_latex_riscv/valz_get_misa_k16049cc76852c9c8026f567e68a54414.tex new file mode 100644 index 00000000..65b9fcc3 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_k16049cc76852c9c8026f567e68a54414.tex @@ -0,0 +1 @@ +_get_Misa_K : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_lf087e66a72a445f7b73881c1235233c0.tex b/sail_latex_riscv/valz_get_misa_lf087e66a72a445f7b73881c1235233c0.tex new file mode 100644 index 00000000..84844430 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_lf087e66a72a445f7b73881c1235233c0.tex @@ -0,0 +1 @@ +_get_Misa_L : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_meaba66535fc1510348a6e72b1dbef759.tex b/sail_latex_riscv/valz_get_misa_meaba66535fc1510348a6e72b1dbef759.tex new file mode 100644 index 00000000..17092a98 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_meaba66535fc1510348a6e72b1dbef759.tex @@ -0,0 +1 @@ +_get_Misa_M : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_mxl28cf17010b1a2667fba28101a95eb2ae.tex b/sail_latex_riscv/valz_get_misa_mxl28cf17010b1a2667fba28101a95eb2ae.tex new file mode 100644 index 00000000..5d8e4548 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_mxl28cf17010b1a2667fba28101a95eb2ae.tex @@ -0,0 +1 @@ +_get_Misa_MXL : Misa -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_n58245b65aecd8d3dded8e5951d67f763.tex b/sail_latex_riscv/valz_get_misa_n58245b65aecd8d3dded8e5951d67f763.tex new file mode 100644 index 00000000..a5904b0a --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_n58245b65aecd8d3dded8e5951d67f763.tex @@ -0,0 +1 @@ +_get_Misa_N : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_o286d096661b36149b410863337f15d31.tex b/sail_latex_riscv/valz_get_misa_o286d096661b36149b410863337f15d31.tex new file mode 100644 index 00000000..edd2bc51 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_o286d096661b36149b410863337f15d31.tex @@ -0,0 +1 @@ +_get_Misa_O : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_p728ca41f7e9225442cea7a2d06fda1ba.tex b/sail_latex_riscv/valz_get_misa_p728ca41f7e9225442cea7a2d06fda1ba.tex new file mode 100644 index 00000000..48d5f0b8 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_p728ca41f7e9225442cea7a2d06fda1ba.tex @@ -0,0 +1 @@ +_get_Misa_P : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_q90da1bead4ec3b742728fa054935bbc0.tex b/sail_latex_riscv/valz_get_misa_q90da1bead4ec3b742728fa054935bbc0.tex new file mode 100644 index 00000000..d5d8245f --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_q90da1bead4ec3b742728fa054935bbc0.tex @@ -0,0 +1 @@ +_get_Misa_Q : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_rd0abea1daab407b029000fb4e1d3af0d.tex b/sail_latex_riscv/valz_get_misa_rd0abea1daab407b029000fb4e1d3af0d.tex new file mode 100644 index 00000000..4e418e17 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_rd0abea1daab407b029000fb4e1d3af0d.tex @@ -0,0 +1 @@ +_get_Misa_R : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_s8d44106b93832cd46e00cba3d0fd7cc8.tex b/sail_latex_riscv/valz_get_misa_s8d44106b93832cd46e00cba3d0fd7cc8.tex new file mode 100644 index 00000000..f4a500c2 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_s8d44106b93832cd46e00cba3d0fd7cc8.tex @@ -0,0 +1 @@ +_get_Misa_S : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_t964cf69481b883e83863eb9ac05b8d52.tex b/sail_latex_riscv/valz_get_misa_t964cf69481b883e83863eb9ac05b8d52.tex new file mode 100644 index 00000000..69699d3e --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_t964cf69481b883e83863eb9ac05b8d52.tex @@ -0,0 +1 @@ +_get_Misa_T : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_u2220c5041e723fd883e5ca3aad46843a.tex b/sail_latex_riscv/valz_get_misa_u2220c5041e723fd883e5ca3aad46843a.tex new file mode 100644 index 00000000..922c6bc3 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_u2220c5041e723fd883e5ca3aad46843a.tex @@ -0,0 +1 @@ +_get_Misa_U : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_v3c3bbe0f72733630524d92db60c14a02.tex b/sail_latex_riscv/valz_get_misa_v3c3bbe0f72733630524d92db60c14a02.tex new file mode 100644 index 00000000..ed78137c --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_v3c3bbe0f72733630524d92db60c14a02.tex @@ -0,0 +1 @@ +_get_Misa_V : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_w4b9d3d940363386a3b964f5d156642f8.tex b/sail_latex_riscv/valz_get_misa_w4b9d3d940363386a3b964f5d156642f8.tex new file mode 100644 index 00000000..e36f511c --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_w4b9d3d940363386a3b964f5d156642f8.tex @@ -0,0 +1 @@ +_get_Misa_W : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_xd43796eb311a89255d0382867f07ad38.tex b/sail_latex_riscv/valz_get_misa_xd43796eb311a89255d0382867f07ad38.tex new file mode 100644 index 00000000..44d80477 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_xd43796eb311a89255d0382867f07ad38.tex @@ -0,0 +1 @@ +_get_Misa_X : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_ycb7d2d02e2edfcdcd44bdf6e4764863d.tex b/sail_latex_riscv/valz_get_misa_ycb7d2d02e2edfcdcd44bdf6e4764863d.tex new file mode 100644 index 00000000..447e0625 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_ycb7d2d02e2edfcdcd44bdf6e4764863d.tex @@ -0,0 +1 @@ +_get_Misa_Y : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_misa_z0279590775f9ece96e2d9030ddcdfa1d.tex b/sail_latex_riscv/valz_get_misa_z0279590775f9ece96e2d9030ddcdfa1d.tex new file mode 100644 index 00000000..3ad21b98 --- /dev/null +++ b/sail_latex_riscv/valz_get_misa_z0279590775f9ece96e2d9030ddcdfa1d.tex @@ -0,0 +1 @@ +_get_Misa_Z : Misa -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_bits0aa5b9575406d172210cdde6ef45d6cd.tex b/sail_latex_riscv/valz_get_mstatus_bits0aa5b9575406d172210cdde6ef45d6cd.tex new file mode 100644 index 00000000..afc72795 --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_bits0aa5b9575406d172210cdde6ef45d6cd.tex @@ -0,0 +1 @@ +_get_Mstatus_bits : Mstatus -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_fs330eb17a3e05d1bdbd6f51377b6d3412.tex b/sail_latex_riscv/valz_get_mstatus_fs330eb17a3e05d1bdbd6f51377b6d3412.tex new file mode 100644 index 00000000..04d146b8 --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_fs330eb17a3e05d1bdbd6f51377b6d3412.tex @@ -0,0 +1 @@ +_get_Mstatus_FS : Mstatus -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_mie663746b59e574a55bd4a0897e80f3213.tex b/sail_latex_riscv/valz_get_mstatus_mie663746b59e574a55bd4a0897e80f3213.tex new file mode 100644 index 00000000..3c260327 --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_mie663746b59e574a55bd4a0897e80f3213.tex @@ -0,0 +1 @@ +_get_Mstatus_MIE : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_mpie70d0deda1607434a8f6fc4a7553fa022.tex b/sail_latex_riscv/valz_get_mstatus_mpie70d0deda1607434a8f6fc4a7553fa022.tex new file mode 100644 index 00000000..87a26832 --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_mpie70d0deda1607434a8f6fc4a7553fa022.tex @@ -0,0 +1 @@ +_get_Mstatus_MPIE : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_mppaf78fafa2a77f2e77dbce07a488444bf.tex b/sail_latex_riscv/valz_get_mstatus_mppaf78fafa2a77f2e77dbce07a488444bf.tex new file mode 100644 index 00000000..b6932668 --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_mppaf78fafa2a77f2e77dbce07a488444bf.tex @@ -0,0 +1 @@ +_get_Mstatus_MPP : Mstatus -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_mprv4b66922b817797bb81a3c2cdfdeff3e4.tex b/sail_latex_riscv/valz_get_mstatus_mprv4b66922b817797bb81a3c2cdfdeff3e4.tex new file mode 100644 index 00000000..aae56449 --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_mprv4b66922b817797bb81a3c2cdfdeff3e4.tex @@ -0,0 +1 @@ +_get_Mstatus_MPRV : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_mxrc3cb8fda7e9db55ac7c86e5a6c05793f.tex b/sail_latex_riscv/valz_get_mstatus_mxrc3cb8fda7e9db55ac7c86e5a6c05793f.tex new file mode 100644 index 00000000..3d1dd987 --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_mxrc3cb8fda7e9db55ac7c86e5a6c05793f.tex @@ -0,0 +1 @@ +_get_Mstatus_MXR : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_sdd1de4e48331a465d1f6bc8b70c10db69.tex b/sail_latex_riscv/valz_get_mstatus_sdd1de4e48331a465d1f6bc8b70c10db69.tex new file mode 100644 index 00000000..387feb7a --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_sdd1de4e48331a465d1f6bc8b70c10db69.tex @@ -0,0 +1 @@ +_get_Mstatus_SD : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_sied77d2cea6c4c5513b90c521245df3f40.tex b/sail_latex_riscv/valz_get_mstatus_sied77d2cea6c4c5513b90c521245df3f40.tex new file mode 100644 index 00000000..8e487d74 --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_sied77d2cea6c4c5513b90c521245df3f40.tex @@ -0,0 +1 @@ +_get_Mstatus_SIE : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_spie13e7c8fd06a819c72ff0319a1708039d.tex b/sail_latex_riscv/valz_get_mstatus_spie13e7c8fd06a819c72ff0319a1708039d.tex new file mode 100644 index 00000000..c42799cd --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_spie13e7c8fd06a819c72ff0319a1708039d.tex @@ -0,0 +1 @@ +_get_Mstatus_SPIE : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_spp27a2b01ae2feb0234f716a7027839bbd.tex b/sail_latex_riscv/valz_get_mstatus_spp27a2b01ae2feb0234f716a7027839bbd.tex new file mode 100644 index 00000000..08bb6252 --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_spp27a2b01ae2feb0234f716a7027839bbd.tex @@ -0,0 +1 @@ +_get_Mstatus_SPP : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_sumdf310d1f826fe16b715b86b635711496.tex b/sail_latex_riscv/valz_get_mstatus_sumdf310d1f826fe16b715b86b635711496.tex new file mode 100644 index 00000000..1b25938f --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_sumdf310d1f826fe16b715b86b635711496.tex @@ -0,0 +1 @@ +_get_Mstatus_SUM : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_tsr45a4c5c29b4ca69f189205bb23dbb516.tex b/sail_latex_riscv/valz_get_mstatus_tsr45a4c5c29b4ca69f189205bb23dbb516.tex new file mode 100644 index 00000000..02978630 --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_tsr45a4c5c29b4ca69f189205bb23dbb516.tex @@ -0,0 +1 @@ +_get_Mstatus_TSR : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_tvm0a763585a6834af9f476c5b07d9dcce6.tex b/sail_latex_riscv/valz_get_mstatus_tvm0a763585a6834af9f476c5b07d9dcce6.tex new file mode 100644 index 00000000..8fa21610 --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_tvm0a763585a6834af9f476c5b07d9dcce6.tex @@ -0,0 +1 @@ +_get_Mstatus_TVM : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_twdd04977b0ac22974f609e5b00f1a09e9.tex b/sail_latex_riscv/valz_get_mstatus_twdd04977b0ac22974f609e5b00f1a09e9.tex new file mode 100644 index 00000000..8a8e0a02 --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_twdd04977b0ac22974f609e5b00f1a09e9.tex @@ -0,0 +1 @@ +_get_Mstatus_TW : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_uie038bd3276e1254d44c8bafbeafa41955.tex b/sail_latex_riscv/valz_get_mstatus_uie038bd3276e1254d44c8bafbeafa41955.tex new file mode 100644 index 00000000..a4dd673f --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_uie038bd3276e1254d44c8bafbeafa41955.tex @@ -0,0 +1 @@ +_get_Mstatus_UIE : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_upieb1f082dfe5cc07cf43ceb1a9c5ddd9e4.tex b/sail_latex_riscv/valz_get_mstatus_upieb1f082dfe5cc07cf43ceb1a9c5ddd9e4.tex new file mode 100644 index 00000000..bee391c8 --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_upieb1f082dfe5cc07cf43ceb1a9c5ddd9e4.tex @@ -0,0 +1 @@ +_get_Mstatus_UPIE : Mstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mstatus_xsb541df8fdc5ba9ddaf95a2890f06b4b1.tex b/sail_latex_riscv/valz_get_mstatus_xsb541df8fdc5ba9ddaf95a2890f06b4b1.tex new file mode 100644 index 00000000..bfb51afb --- /dev/null +++ b/sail_latex_riscv/valz_get_mstatus_xsb541df8fdc5ba9ddaf95a2890f06b4b1.tex @@ -0,0 +1 @@ +_get_Mstatus_XS : Mstatus -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mtvec_basefad37a1b29dd19f0e36c4f4c971339ee.tex b/sail_latex_riscv/valz_get_mtvec_basefad37a1b29dd19f0e36c4f4c971339ee.tex new file mode 100644 index 00000000..855991cd --- /dev/null +++ b/sail_latex_riscv/valz_get_mtvec_basefad37a1b29dd19f0e36c4f4c971339ee.tex @@ -0,0 +1 @@ +_get_Mtvec_Base : Mtvec -> bitvector(62, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mtvec_bitse609b5bdda2049f1b86a85566415ea34.tex b/sail_latex_riscv/valz_get_mtvec_bitse609b5bdda2049f1b86a85566415ea34.tex new file mode 100644 index 00000000..214cf6c4 --- /dev/null +++ b/sail_latex_riscv/valz_get_mtvec_bitse609b5bdda2049f1b86a85566415ea34.tex @@ -0,0 +1 @@ +_get_Mtvec_bits : Mtvec -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_mtvec_modeac4fc90b9c4014235eab8096eeec86f0.tex b/sail_latex_riscv/valz_get_mtvec_modeac4fc90b9c4014235eab8096eeec86f0.tex new file mode 100644 index 00000000..2699ea4d --- /dev/null +++ b/sail_latex_riscv/valz_get_mtvec_modeac4fc90b9c4014235eab8096eeec86f0.tex @@ -0,0 +1 @@ +_get_Mtvec_Mode : Mtvec -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pmpcfg_ent_a91770fb51fbff6c4cb08646293fdf39f.tex b/sail_latex_riscv/valz_get_pmpcfg_ent_a91770fb51fbff6c4cb08646293fdf39f.tex new file mode 100644 index 00000000..136d99bb --- /dev/null +++ b/sail_latex_riscv/valz_get_pmpcfg_ent_a91770fb51fbff6c4cb08646293fdf39f.tex @@ -0,0 +1 @@ +_get_Pmpcfg_ent_A : Pmpcfg_ent -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pmpcfg_ent_bits548ab0717907b301f5b9c16399b10032.tex b/sail_latex_riscv/valz_get_pmpcfg_ent_bits548ab0717907b301f5b9c16399b10032.tex new file mode 100644 index 00000000..76340527 --- /dev/null +++ b/sail_latex_riscv/valz_get_pmpcfg_ent_bits548ab0717907b301f5b9c16399b10032.tex @@ -0,0 +1 @@ +_get_Pmpcfg_ent_bits : Pmpcfg_ent -> bitvector(8, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pmpcfg_ent_l809319223a792af7a0eb5574371df331.tex b/sail_latex_riscv/valz_get_pmpcfg_ent_l809319223a792af7a0eb5574371df331.tex new file mode 100644 index 00000000..327faa54 --- /dev/null +++ b/sail_latex_riscv/valz_get_pmpcfg_ent_l809319223a792af7a0eb5574371df331.tex @@ -0,0 +1 @@ +_get_Pmpcfg_ent_L : Pmpcfg_ent -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pmpcfg_ent_r2cdcfc9666bd2e243c0c9c0473f345d2.tex b/sail_latex_riscv/valz_get_pmpcfg_ent_r2cdcfc9666bd2e243c0c9c0473f345d2.tex new file mode 100644 index 00000000..16d33b2b --- /dev/null +++ b/sail_latex_riscv/valz_get_pmpcfg_ent_r2cdcfc9666bd2e243c0c9c0473f345d2.tex @@ -0,0 +1 @@ +_get_Pmpcfg_ent_R : Pmpcfg_ent -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pmpcfg_ent_w9a2773642113e6c2af77db6f82354b24.tex b/sail_latex_riscv/valz_get_pmpcfg_ent_w9a2773642113e6c2af77db6f82354b24.tex new file mode 100644 index 00000000..59d668ad --- /dev/null +++ b/sail_latex_riscv/valz_get_pmpcfg_ent_w9a2773642113e6c2af77db6f82354b24.tex @@ -0,0 +1 @@ +_get_Pmpcfg_ent_W : Pmpcfg_ent -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pmpcfg_ent_x7298f9632eb08a3009a272d71e240aee.tex b/sail_latex_riscv/valz_get_pmpcfg_ent_x7298f9632eb08a3009a272d71e240aee.tex new file mode 100644 index 00000000..f7d5f7ff --- /dev/null +++ b/sail_latex_riscv/valz_get_pmpcfg_ent_x7298f9632eb08a3009a272d71e240aee.tex @@ -0,0 +1 @@ +_get_Pmpcfg_ent_X : Pmpcfg_ent -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pte_bits_adca5243c2ba1646df88e501938973569.tex b/sail_latex_riscv/valz_get_pte_bits_adca5243c2ba1646df88e501938973569.tex new file mode 100644 index 00000000..91874e1c --- /dev/null +++ b/sail_latex_riscv/valz_get_pte_bits_adca5243c2ba1646df88e501938973569.tex @@ -0,0 +1 @@ +_get_PTE_Bits_A : PTE_Bits -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pte_bits_bits6cd7748e02dfe09da9dd53f24f9ac073.tex b/sail_latex_riscv/valz_get_pte_bits_bits6cd7748e02dfe09da9dd53f24f9ac073.tex new file mode 100644 index 00000000..bf7fb315 --- /dev/null +++ b/sail_latex_riscv/valz_get_pte_bits_bits6cd7748e02dfe09da9dd53f24f9ac073.tex @@ -0,0 +1 @@ +_get_PTE_Bits_bits : PTE_Bits -> bitvector(8, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pte_bits_d1ee6a89af287b35ae0a1cf2945b86d59.tex b/sail_latex_riscv/valz_get_pte_bits_d1ee6a89af287b35ae0a1cf2945b86d59.tex new file mode 100644 index 00000000..8513100b --- /dev/null +++ b/sail_latex_riscv/valz_get_pte_bits_d1ee6a89af287b35ae0a1cf2945b86d59.tex @@ -0,0 +1 @@ +_get_PTE_Bits_D : PTE_Bits -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pte_bits_g072ec08934990455850facd53f018b89.tex b/sail_latex_riscv/valz_get_pte_bits_g072ec08934990455850facd53f018b89.tex new file mode 100644 index 00000000..41f47b7e --- /dev/null +++ b/sail_latex_riscv/valz_get_pte_bits_g072ec08934990455850facd53f018b89.tex @@ -0,0 +1 @@ +_get_PTE_Bits_G : PTE_Bits -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pte_bits_r3a52c7a77cb754fb6a6eb55405de30cd.tex b/sail_latex_riscv/valz_get_pte_bits_r3a52c7a77cb754fb6a6eb55405de30cd.tex new file mode 100644 index 00000000..b6916bb8 --- /dev/null +++ b/sail_latex_riscv/valz_get_pte_bits_r3a52c7a77cb754fb6a6eb55405de30cd.tex @@ -0,0 +1 @@ +_get_PTE_Bits_R : PTE_Bits -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pte_bits_u300741c1239ab0c65dc451f1700b52d8.tex b/sail_latex_riscv/valz_get_pte_bits_u300741c1239ab0c65dc451f1700b52d8.tex new file mode 100644 index 00000000..b323773a --- /dev/null +++ b/sail_latex_riscv/valz_get_pte_bits_u300741c1239ab0c65dc451f1700b52d8.tex @@ -0,0 +1 @@ +_get_PTE_Bits_U : PTE_Bits -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pte_bits_vb582fda618233a0ee7948c90600227f6.tex b/sail_latex_riscv/valz_get_pte_bits_vb582fda618233a0ee7948c90600227f6.tex new file mode 100644 index 00000000..1873b79d --- /dev/null +++ b/sail_latex_riscv/valz_get_pte_bits_vb582fda618233a0ee7948c90600227f6.tex @@ -0,0 +1 @@ +_get_PTE_Bits_V : PTE_Bits -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pte_bits_w1d621d1d07d6e1ee0c6cbdd6eff9e867.tex b/sail_latex_riscv/valz_get_pte_bits_w1d621d1d07d6e1ee0c6cbdd6eff9e867.tex new file mode 100644 index 00000000..9afcc845 --- /dev/null +++ b/sail_latex_riscv/valz_get_pte_bits_w1d621d1d07d6e1ee0c6cbdd6eff9e867.tex @@ -0,0 +1 @@ +_get_PTE_Bits_W : PTE_Bits -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_pte_bits_x1b94d5b50779d8431b6a164038524c85.tex b/sail_latex_riscv/valz_get_pte_bits_x1b94d5b50779d8431b6a164038524c85.tex new file mode 100644 index 00000000..5a4dd6db --- /dev/null +++ b/sail_latex_riscv/valz_get_pte_bits_x1b94d5b50779d8431b6a164038524c85.tex @@ -0,0 +1 @@ +_get_PTE_Bits_X : PTE_Bits -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_satp32_asid79b89125e014e4824b79940178c13320.tex b/sail_latex_riscv/valz_get_satp32_asid79b89125e014e4824b79940178c13320.tex new file mode 100644 index 00000000..bcf975e6 --- /dev/null +++ b/sail_latex_riscv/valz_get_satp32_asid79b89125e014e4824b79940178c13320.tex @@ -0,0 +1 @@ +_get_Satp32_Asid : Satp32 -> bitvector(9, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_satp32_bits4ef2050c8a62cb83e3a3f48d91f2a8d8.tex b/sail_latex_riscv/valz_get_satp32_bits4ef2050c8a62cb83e3a3f48d91f2a8d8.tex new file mode 100644 index 00000000..b5e7610d --- /dev/null +++ b/sail_latex_riscv/valz_get_satp32_bits4ef2050c8a62cb83e3a3f48d91f2a8d8.tex @@ -0,0 +1 @@ +_get_Satp32_bits : Satp32 -> bitvector(32, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_satp32_modeb053b6b63fe63dd46382110a8b594bfd.tex b/sail_latex_riscv/valz_get_satp32_modeb053b6b63fe63dd46382110a8b594bfd.tex new file mode 100644 index 00000000..2a0afc24 --- /dev/null +++ b/sail_latex_riscv/valz_get_satp32_modeb053b6b63fe63dd46382110a8b594bfd.tex @@ -0,0 +1 @@ +_get_Satp32_Mode : Satp32 -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_satp32_ppn09e489a7e17eb50d41a060c4cfdf4452.tex b/sail_latex_riscv/valz_get_satp32_ppn09e489a7e17eb50d41a060c4cfdf4452.tex new file mode 100644 index 00000000..1e13c595 --- /dev/null +++ b/sail_latex_riscv/valz_get_satp32_ppn09e489a7e17eb50d41a060c4cfdf4452.tex @@ -0,0 +1 @@ +_get_Satp32_PPN : Satp32 -> bitvector(22, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_satp64_asid5a55ab259b6bd85453ad8708a0fb485a.tex b/sail_latex_riscv/valz_get_satp64_asid5a55ab259b6bd85453ad8708a0fb485a.tex new file mode 100644 index 00000000..fa00f0c1 --- /dev/null +++ b/sail_latex_riscv/valz_get_satp64_asid5a55ab259b6bd85453ad8708a0fb485a.tex @@ -0,0 +1 @@ +_get_Satp64_Asid : Satp64 -> bitvector(16, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_satp64_bitsdb6de00ddfe8eefd1a814354aac4a548.tex b/sail_latex_riscv/valz_get_satp64_bitsdb6de00ddfe8eefd1a814354aac4a548.tex new file mode 100644 index 00000000..dfa845c4 --- /dev/null +++ b/sail_latex_riscv/valz_get_satp64_bitsdb6de00ddfe8eefd1a814354aac4a548.tex @@ -0,0 +1 @@ +_get_Satp64_bits : Satp64 -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_satp64_mode5542c94fbfcb40171b429bef968a7954.tex b/sail_latex_riscv/valz_get_satp64_mode5542c94fbfcb40171b429bef968a7954.tex new file mode 100644 index 00000000..b6c2d266 --- /dev/null +++ b/sail_latex_riscv/valz_get_satp64_mode5542c94fbfcb40171b429bef968a7954.tex @@ -0,0 +1 @@ +_get_Satp64_Mode : Satp64 -> bitvector(4, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_satp64_ppn5c0b704bfa56e2113c29e0d13f46b734.tex b/sail_latex_riscv/valz_get_satp64_ppn5c0b704bfa56e2113c29e0d13f46b734.tex new file mode 100644 index 00000000..9623805b --- /dev/null +++ b/sail_latex_riscv/valz_get_satp64_ppn5c0b704bfa56e2113c29e0d13f46b734.tex @@ -0,0 +1 @@ +_get_Satp64_PPN : Satp64 -> bitvector(44, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sedeleg_bitsf6b9b215e547db1e045ee7ddfb1f2f7a.tex b/sail_latex_riscv/valz_get_sedeleg_bitsf6b9b215e547db1e045ee7ddfb1f2f7a.tex new file mode 100644 index 00000000..c4e44bf4 --- /dev/null +++ b/sail_latex_riscv/valz_get_sedeleg_bitsf6b9b215e547db1e045ee7ddfb1f2f7a.tex @@ -0,0 +1 @@ +_get_Sedeleg_bits : Sedeleg -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sedeleg_breakpointc77d25240c231ee118b1655024dfeea6.tex b/sail_latex_riscv/valz_get_sedeleg_breakpointc77d25240c231ee118b1655024dfeea6.tex new file mode 100644 index 00000000..ec8961af --- /dev/null +++ b/sail_latex_riscv/valz_get_sedeleg_breakpointc77d25240c231ee118b1655024dfeea6.tex @@ -0,0 +1 @@ +_get_Sedeleg_Breakpoint : Sedeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sedeleg_fetch_access_faultf8861e3f9e14da4d59e7ab55d00a289b.tex b/sail_latex_riscv/valz_get_sedeleg_fetch_access_faultf8861e3f9e14da4d59e7ab55d00a289b.tex new file mode 100644 index 00000000..1dde90e5 --- /dev/null +++ b/sail_latex_riscv/valz_get_sedeleg_fetch_access_faultf8861e3f9e14da4d59e7ab55d00a289b.tex @@ -0,0 +1 @@ +_get_Sedeleg_Fetch_Access_Fault : Sedeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sedeleg_fetch_addr_alignee0f20da19f67b8d187355d5547984ca.tex b/sail_latex_riscv/valz_get_sedeleg_fetch_addr_alignee0f20da19f67b8d187355d5547984ca.tex new file mode 100644 index 00000000..eead884b --- /dev/null +++ b/sail_latex_riscv/valz_get_sedeleg_fetch_addr_alignee0f20da19f67b8d187355d5547984ca.tex @@ -0,0 +1 @@ +_get_Sedeleg_Fetch_Addr_Align : Sedeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sedeleg_illegal_instrb6d9314c6ab6f5e95202046d9dfe0756.tex b/sail_latex_riscv/valz_get_sedeleg_illegal_instrb6d9314c6ab6f5e95202046d9dfe0756.tex new file mode 100644 index 00000000..0fca69f6 --- /dev/null +++ b/sail_latex_riscv/valz_get_sedeleg_illegal_instrb6d9314c6ab6f5e95202046d9dfe0756.tex @@ -0,0 +1 @@ +_get_Sedeleg_Illegal_Instr : Sedeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sedeleg_load_access_faultac09796aa8cbf3a86b1fed3ecd8f3c88.tex b/sail_latex_riscv/valz_get_sedeleg_load_access_faultac09796aa8cbf3a86b1fed3ecd8f3c88.tex new file mode 100644 index 00000000..620d41aa --- /dev/null +++ b/sail_latex_riscv/valz_get_sedeleg_load_access_faultac09796aa8cbf3a86b1fed3ecd8f3c88.tex @@ -0,0 +1 @@ +_get_Sedeleg_Load_Access_Fault : Sedeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sedeleg_load_addr_aligna36eb31e7e82330db9574602098e9a62.tex b/sail_latex_riscv/valz_get_sedeleg_load_addr_aligna36eb31e7e82330db9574602098e9a62.tex new file mode 100644 index 00000000..1bd4cf1c --- /dev/null +++ b/sail_latex_riscv/valz_get_sedeleg_load_addr_aligna36eb31e7e82330db9574602098e9a62.tex @@ -0,0 +1 @@ +_get_Sedeleg_Load_Addr_Align : Sedeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sedeleg_samo_access_fault3592b648b74f292f7582352512f54c43.tex b/sail_latex_riscv/valz_get_sedeleg_samo_access_fault3592b648b74f292f7582352512f54c43.tex new file mode 100644 index 00000000..4b56c328 --- /dev/null +++ b/sail_latex_riscv/valz_get_sedeleg_samo_access_fault3592b648b74f292f7582352512f54c43.tex @@ -0,0 +1 @@ +_get_Sedeleg_SAMO_Access_Fault : Sedeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sedeleg_samo_addr_align20af8fdcd584bdebc6b45b3bf763ab61.tex b/sail_latex_riscv/valz_get_sedeleg_samo_addr_align20af8fdcd584bdebc6b45b3bf763ab61.tex new file mode 100644 index 00000000..00dd3911 --- /dev/null +++ b/sail_latex_riscv/valz_get_sedeleg_samo_addr_align20af8fdcd584bdebc6b45b3bf763ab61.tex @@ -0,0 +1 @@ +_get_Sedeleg_SAMO_Addr_Align : Sedeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sedeleg_uenvcall9adf65053b570cbc347b25630db85fa1.tex b/sail_latex_riscv/valz_get_sedeleg_uenvcall9adf65053b570cbc347b25630db85fa1.tex new file mode 100644 index 00000000..956cb8a1 --- /dev/null +++ b/sail_latex_riscv/valz_get_sedeleg_uenvcall9adf65053b570cbc347b25630db85fa1.tex @@ -0,0 +1 @@ +_get_Sedeleg_UEnvCall : Sedeleg -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sinterrupts_bits890ab2f21b741ac095ede551b06b14b0.tex b/sail_latex_riscv/valz_get_sinterrupts_bits890ab2f21b741ac095ede551b06b14b0.tex new file mode 100644 index 00000000..33d09004 --- /dev/null +++ b/sail_latex_riscv/valz_get_sinterrupts_bits890ab2f21b741ac095ede551b06b14b0.tex @@ -0,0 +1 @@ +_get_Sinterrupts_bits : Sinterrupts -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sinterrupts_sei5458488d503712b6667d489b56acd5e1.tex b/sail_latex_riscv/valz_get_sinterrupts_sei5458488d503712b6667d489b56acd5e1.tex new file mode 100644 index 00000000..32dbd8cf --- /dev/null +++ b/sail_latex_riscv/valz_get_sinterrupts_sei5458488d503712b6667d489b56acd5e1.tex @@ -0,0 +1 @@ +_get_Sinterrupts_SEI : Sinterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sinterrupts_ssi240024e06c4365a8f0ed4ba1b36afb6c.tex b/sail_latex_riscv/valz_get_sinterrupts_ssi240024e06c4365a8f0ed4ba1b36afb6c.tex new file mode 100644 index 00000000..56484ec9 --- /dev/null +++ b/sail_latex_riscv/valz_get_sinterrupts_ssi240024e06c4365a8f0ed4ba1b36afb6c.tex @@ -0,0 +1 @@ +_get_Sinterrupts_SSI : Sinterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sinterrupts_sti9ba6390e5ddbefa9f37ab560c671354e.tex b/sail_latex_riscv/valz_get_sinterrupts_sti9ba6390e5ddbefa9f37ab560c671354e.tex new file mode 100644 index 00000000..02d8e556 --- /dev/null +++ b/sail_latex_riscv/valz_get_sinterrupts_sti9ba6390e5ddbefa9f37ab560c671354e.tex @@ -0,0 +1 @@ +_get_Sinterrupts_STI : Sinterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sinterrupts_uei29ec1fbe91082e4eaef04b2891fe1177.tex b/sail_latex_riscv/valz_get_sinterrupts_uei29ec1fbe91082e4eaef04b2891fe1177.tex new file mode 100644 index 00000000..63eaf54a --- /dev/null +++ b/sail_latex_riscv/valz_get_sinterrupts_uei29ec1fbe91082e4eaef04b2891fe1177.tex @@ -0,0 +1 @@ +_get_Sinterrupts_UEI : Sinterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sinterrupts_usidbf3fbc5878b2118ded205939499c8c9.tex b/sail_latex_riscv/valz_get_sinterrupts_usidbf3fbc5878b2118ded205939499c8c9.tex new file mode 100644 index 00000000..7da8f308 --- /dev/null +++ b/sail_latex_riscv/valz_get_sinterrupts_usidbf3fbc5878b2118ded205939499c8c9.tex @@ -0,0 +1 @@ +_get_Sinterrupts_USI : Sinterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sinterrupts_utiecf1d7ffb74e287dbae46219d8f856cb.tex b/sail_latex_riscv/valz_get_sinterrupts_utiecf1d7ffb74e287dbae46219d8f856cb.tex new file mode 100644 index 00000000..4ee856cd --- /dev/null +++ b/sail_latex_riscv/valz_get_sinterrupts_utiecf1d7ffb74e287dbae46219d8f856cb.tex @@ -0,0 +1 @@ +_get_Sinterrupts_UTI : Sinterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sstatus_bits47345191d41288d1bd8a7c67bc24ffc6.tex b/sail_latex_riscv/valz_get_sstatus_bits47345191d41288d1bd8a7c67bc24ffc6.tex new file mode 100644 index 00000000..44b65cbe --- /dev/null +++ b/sail_latex_riscv/valz_get_sstatus_bits47345191d41288d1bd8a7c67bc24ffc6.tex @@ -0,0 +1 @@ +_get_Sstatus_bits : Sstatus -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sstatus_fs1460ce74aab98835a1244cb2459d0b77.tex b/sail_latex_riscv/valz_get_sstatus_fs1460ce74aab98835a1244cb2459d0b77.tex new file mode 100644 index 00000000..1d9a3a38 --- /dev/null +++ b/sail_latex_riscv/valz_get_sstatus_fs1460ce74aab98835a1244cb2459d0b77.tex @@ -0,0 +1 @@ +_get_Sstatus_FS : Sstatus -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sstatus_mxr1ed9764969d17c97d4b45acc9309595b.tex b/sail_latex_riscv/valz_get_sstatus_mxr1ed9764969d17c97d4b45acc9309595b.tex new file mode 100644 index 00000000..7f8da91f --- /dev/null +++ b/sail_latex_riscv/valz_get_sstatus_mxr1ed9764969d17c97d4b45acc9309595b.tex @@ -0,0 +1 @@ +_get_Sstatus_MXR : Sstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sstatus_sd12bb5cef6bc9eaf62712c3b06c0754ff.tex b/sail_latex_riscv/valz_get_sstatus_sd12bb5cef6bc9eaf62712c3b06c0754ff.tex new file mode 100644 index 00000000..2f7d3b55 --- /dev/null +++ b/sail_latex_riscv/valz_get_sstatus_sd12bb5cef6bc9eaf62712c3b06c0754ff.tex @@ -0,0 +1 @@ +_get_Sstatus_SD : Sstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sstatus_sie9e01f0fa9797876074411f8310096e19.tex b/sail_latex_riscv/valz_get_sstatus_sie9e01f0fa9797876074411f8310096e19.tex new file mode 100644 index 00000000..1a631db2 --- /dev/null +++ b/sail_latex_riscv/valz_get_sstatus_sie9e01f0fa9797876074411f8310096e19.tex @@ -0,0 +1 @@ +_get_Sstatus_SIE : Sstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sstatus_spie72f0239373389161757a30610914f136.tex b/sail_latex_riscv/valz_get_sstatus_spie72f0239373389161757a30610914f136.tex new file mode 100644 index 00000000..fbd36593 --- /dev/null +++ b/sail_latex_riscv/valz_get_sstatus_spie72f0239373389161757a30610914f136.tex @@ -0,0 +1 @@ +_get_Sstatus_SPIE : Sstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sstatus_spp7cc37e9faad99d47707d2a3ed85339cb.tex b/sail_latex_riscv/valz_get_sstatus_spp7cc37e9faad99d47707d2a3ed85339cb.tex new file mode 100644 index 00000000..479768bc --- /dev/null +++ b/sail_latex_riscv/valz_get_sstatus_spp7cc37e9faad99d47707d2a3ed85339cb.tex @@ -0,0 +1 @@ +_get_Sstatus_SPP : Sstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sstatus_sumfd7d657ad527ac995d1fbf0ded8ce3f5.tex b/sail_latex_riscv/valz_get_sstatus_sumfd7d657ad527ac995d1fbf0ded8ce3f5.tex new file mode 100644 index 00000000..f5c9ae90 --- /dev/null +++ b/sail_latex_riscv/valz_get_sstatus_sumfd7d657ad527ac995d1fbf0ded8ce3f5.tex @@ -0,0 +1 @@ +_get_Sstatus_SUM : Sstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sstatus_uie5a504087d59c8a2af6de9c1f7a14b612.tex b/sail_latex_riscv/valz_get_sstatus_uie5a504087d59c8a2af6de9c1f7a14b612.tex new file mode 100644 index 00000000..2c316d81 --- /dev/null +++ b/sail_latex_riscv/valz_get_sstatus_uie5a504087d59c8a2af6de9c1f7a14b612.tex @@ -0,0 +1 @@ +_get_Sstatus_UIE : Sstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sstatus_upie1fbaa84eb888e534ff854d4d873dff79.tex b/sail_latex_riscv/valz_get_sstatus_upie1fbaa84eb888e534ff854d4d873dff79.tex new file mode 100644 index 00000000..c76de9d1 --- /dev/null +++ b/sail_latex_riscv/valz_get_sstatus_upie1fbaa84eb888e534ff854d4d873dff79.tex @@ -0,0 +1 @@ +_get_Sstatus_UPIE : Sstatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sstatus_xs83df09eb63f5261e086c2a1e7e0f1c7a.tex b/sail_latex_riscv/valz_get_sstatus_xs83df09eb63f5261e086c2a1e7e0f1c7a.tex new file mode 100644 index 00000000..088a94d9 --- /dev/null +++ b/sail_latex_riscv/valz_get_sstatus_xs83df09eb63f5261e086c2a1e7e0f1c7a.tex @@ -0,0 +1 @@ +_get_Sstatus_XS : Sstatus -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv32_paddr_bitsc60ef4da8b2834c670d1e63afd2220ae.tex b/sail_latex_riscv/valz_get_sv32_paddr_bitsc60ef4da8b2834c670d1e63afd2220ae.tex new file mode 100644 index 00000000..0ea74980 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv32_paddr_bitsc60ef4da8b2834c670d1e63afd2220ae.tex @@ -0,0 +1 @@ +_get_SV32_Paddr_bits : SV32_Paddr -> bitvector(34, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv32_paddr_pgofs835ba010b40a7fd02d4a61e2ab2de4b4.tex b/sail_latex_riscv/valz_get_sv32_paddr_pgofs835ba010b40a7fd02d4a61e2ab2de4b4.tex new file mode 100644 index 00000000..2643a42e --- /dev/null +++ b/sail_latex_riscv/valz_get_sv32_paddr_pgofs835ba010b40a7fd02d4a61e2ab2de4b4.tex @@ -0,0 +1 @@ +_get_SV32_Paddr_PgOfs : SV32_Paddr -> bitvector(12, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv32_paddr_ppni1504c6497d4791cfe4234a5cc0365252.tex b/sail_latex_riscv/valz_get_sv32_paddr_ppni1504c6497d4791cfe4234a5cc0365252.tex new file mode 100644 index 00000000..18008f8a --- /dev/null +++ b/sail_latex_riscv/valz_get_sv32_paddr_ppni1504c6497d4791cfe4234a5cc0365252.tex @@ -0,0 +1 @@ +_get_SV32_Paddr_PPNi : SV32_Paddr -> bitvector(22, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv32_pte_bits184b603cf04702f500c26a3f44a95bce.tex b/sail_latex_riscv/valz_get_sv32_pte_bits184b603cf04702f500c26a3f44a95bce.tex new file mode 100644 index 00000000..5fc98d5c --- /dev/null +++ b/sail_latex_riscv/valz_get_sv32_pte_bits184b603cf04702f500c26a3f44a95bce.tex @@ -0,0 +1 @@ +_get_SV32_PTE_bits : SV32_PTE -> bitvector(32, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv32_pte_bitse339fd2b2bd11b8fd6c71664018dafca.tex b/sail_latex_riscv/valz_get_sv32_pte_bitse339fd2b2bd11b8fd6c71664018dafca.tex new file mode 100644 index 00000000..ee3a7e7e --- /dev/null +++ b/sail_latex_riscv/valz_get_sv32_pte_bitse339fd2b2bd11b8fd6c71664018dafca.tex @@ -0,0 +1 @@ +_get_SV32_PTE_BITS : SV32_PTE -> bitvector(8, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv32_pte_ppni0d6471170f5c73c025591b74f4c1fe5e.tex b/sail_latex_riscv/valz_get_sv32_pte_ppni0d6471170f5c73c025591b74f4c1fe5e.tex new file mode 100644 index 00000000..392fc387 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv32_pte_ppni0d6471170f5c73c025591b74f4c1fe5e.tex @@ -0,0 +1 @@ +_get_SV32_PTE_PPNi : SV32_PTE -> bitvector(22, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv32_pte_rswe20144b93e162ff3dff60d8ea711bcfe.tex b/sail_latex_riscv/valz_get_sv32_pte_rswe20144b93e162ff3dff60d8ea711bcfe.tex new file mode 100644 index 00000000..28482bcf --- /dev/null +++ b/sail_latex_riscv/valz_get_sv32_pte_rswe20144b93e162ff3dff60d8ea711bcfe.tex @@ -0,0 +1 @@ +_get_SV32_PTE_RSW : SV32_PTE -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv32_vaddr_bits0caf929432208e7079ae87374085c96f.tex b/sail_latex_riscv/valz_get_sv32_vaddr_bits0caf929432208e7079ae87374085c96f.tex new file mode 100644 index 00000000..02f324eb --- /dev/null +++ b/sail_latex_riscv/valz_get_sv32_vaddr_bits0caf929432208e7079ae87374085c96f.tex @@ -0,0 +1 @@ +_get_SV32_Vaddr_bits : SV32_Vaddr -> bitvector(32, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv32_vaddr_pgofsdbfd9837672881608e9b05eff50b2e99.tex b/sail_latex_riscv/valz_get_sv32_vaddr_pgofsdbfd9837672881608e9b05eff50b2e99.tex new file mode 100644 index 00000000..3dad290a --- /dev/null +++ b/sail_latex_riscv/valz_get_sv32_vaddr_pgofsdbfd9837672881608e9b05eff50b2e99.tex @@ -0,0 +1 @@ +_get_SV32_Vaddr_PgOfs : SV32_Vaddr -> bitvector(12, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv32_vaddr_vpniab523206431fb7d5db154d45287e96ba.tex b/sail_latex_riscv/valz_get_sv32_vaddr_vpniab523206431fb7d5db154d45287e96ba.tex new file mode 100644 index 00000000..fd9ce52f --- /dev/null +++ b/sail_latex_riscv/valz_get_sv32_vaddr_vpniab523206431fb7d5db154d45287e96ba.tex @@ -0,0 +1 @@ +_get_SV32_Vaddr_VPNi : SV32_Vaddr -> bitvector(20, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv39_paddr_bits834b4f44fc6e69ffd391c9b6237cce2b.tex b/sail_latex_riscv/valz_get_sv39_paddr_bits834b4f44fc6e69ffd391c9b6237cce2b.tex new file mode 100644 index 00000000..cf26371e --- /dev/null +++ b/sail_latex_riscv/valz_get_sv39_paddr_bits834b4f44fc6e69ffd391c9b6237cce2b.tex @@ -0,0 +1 @@ +_get_SV39_Paddr_bits : SV39_Paddr -> bitvector(56, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv39_paddr_pgofsb92f2e38ca030595309ba60289cfc67e.tex b/sail_latex_riscv/valz_get_sv39_paddr_pgofsb92f2e38ca030595309ba60289cfc67e.tex new file mode 100644 index 00000000..6454748e --- /dev/null +++ b/sail_latex_riscv/valz_get_sv39_paddr_pgofsb92f2e38ca030595309ba60289cfc67e.tex @@ -0,0 +1 @@ +_get_SV39_Paddr_PgOfs : SV39_Paddr -> bitvector(12, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv39_paddr_ppnie78045a960397b424c97285aca9dd29b.tex b/sail_latex_riscv/valz_get_sv39_paddr_ppnie78045a960397b424c97285aca9dd29b.tex new file mode 100644 index 00000000..41ec6018 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv39_paddr_ppnie78045a960397b424c97285aca9dd29b.tex @@ -0,0 +1 @@ +_get_SV39_Paddr_PPNi : SV39_Paddr -> bitvector(44, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv39_pte_bits0a004475205374ae82c050106619c089.tex b/sail_latex_riscv/valz_get_sv39_pte_bits0a004475205374ae82c050106619c089.tex new file mode 100644 index 00000000..b01759c4 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv39_pte_bits0a004475205374ae82c050106619c089.tex @@ -0,0 +1 @@ +_get_SV39_PTE_bits : SV39_PTE -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv39_pte_bits2894d61e8f7557590f0240a44dc9dca4.tex b/sail_latex_riscv/valz_get_sv39_pte_bits2894d61e8f7557590f0240a44dc9dca4.tex new file mode 100644 index 00000000..340a5e6f --- /dev/null +++ b/sail_latex_riscv/valz_get_sv39_pte_bits2894d61e8f7557590f0240a44dc9dca4.tex @@ -0,0 +1 @@ +_get_SV39_PTE_BITS : SV39_PTE -> bitvector(8, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv39_pte_ext400fef25828eab6cdcb38e7e7fd21c72.tex b/sail_latex_riscv/valz_get_sv39_pte_ext400fef25828eab6cdcb38e7e7fd21c72.tex new file mode 100644 index 00000000..a4b5a6d1 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv39_pte_ext400fef25828eab6cdcb38e7e7fd21c72.tex @@ -0,0 +1 @@ +_get_SV39_PTE_Ext : SV39_PTE -> bitvector(10, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv39_pte_ppni426489f4764a5d0ade3e9346a0b394c7.tex b/sail_latex_riscv/valz_get_sv39_pte_ppni426489f4764a5d0ade3e9346a0b394c7.tex new file mode 100644 index 00000000..cad1e905 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv39_pte_ppni426489f4764a5d0ade3e9346a0b394c7.tex @@ -0,0 +1 @@ +_get_SV39_PTE_PPNi : SV39_PTE -> bitvector(44, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv39_pte_rswb7f6ce3a77a6a7a556a5530cded759fa.tex b/sail_latex_riscv/valz_get_sv39_pte_rswb7f6ce3a77a6a7a556a5530cded759fa.tex new file mode 100644 index 00000000..6cdee217 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv39_pte_rswb7f6ce3a77a6a7a556a5530cded759fa.tex @@ -0,0 +1 @@ +_get_SV39_PTE_RSW : SV39_PTE -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv39_vaddr_bits364185505ec9c15373ab9c1464724954.tex b/sail_latex_riscv/valz_get_sv39_vaddr_bits364185505ec9c15373ab9c1464724954.tex new file mode 100644 index 00000000..f6bea123 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv39_vaddr_bits364185505ec9c15373ab9c1464724954.tex @@ -0,0 +1 @@ +_get_SV39_Vaddr_bits : SV39_Vaddr -> bitvector(39, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv39_vaddr_pgofs4e8b61f46949b7eec961a817eeb9caf2.tex b/sail_latex_riscv/valz_get_sv39_vaddr_pgofs4e8b61f46949b7eec961a817eeb9caf2.tex new file mode 100644 index 00000000..68410c9c --- /dev/null +++ b/sail_latex_riscv/valz_get_sv39_vaddr_pgofs4e8b61f46949b7eec961a817eeb9caf2.tex @@ -0,0 +1 @@ +_get_SV39_Vaddr_PgOfs : SV39_Vaddr -> bitvector(12, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv39_vaddr_vpni21781895f7de6beeab4c3b9429948ba9.tex b/sail_latex_riscv/valz_get_sv39_vaddr_vpni21781895f7de6beeab4c3b9429948ba9.tex new file mode 100644 index 00000000..19faf1c2 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv39_vaddr_vpni21781895f7de6beeab4c3b9429948ba9.tex @@ -0,0 +1 @@ +_get_SV39_Vaddr_VPNi : SV39_Vaddr -> bitvector(27, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv48_paddr_bits254b25d43747ddb1b15788364bb3ff6f.tex b/sail_latex_riscv/valz_get_sv48_paddr_bits254b25d43747ddb1b15788364bb3ff6f.tex new file mode 100644 index 00000000..4d3d06f8 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv48_paddr_bits254b25d43747ddb1b15788364bb3ff6f.tex @@ -0,0 +1 @@ +_get_SV48_Paddr_bits : SV48_Paddr -> bitvector(56, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv48_paddr_pgofs7fbf559e6e9712930b86b30c8364e938.tex b/sail_latex_riscv/valz_get_sv48_paddr_pgofs7fbf559e6e9712930b86b30c8364e938.tex new file mode 100644 index 00000000..38a8e9ce --- /dev/null +++ b/sail_latex_riscv/valz_get_sv48_paddr_pgofs7fbf559e6e9712930b86b30c8364e938.tex @@ -0,0 +1 @@ +_get_SV48_Paddr_PgOfs : SV48_Paddr -> bitvector(12, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv48_paddr_ppni9c768f41f1a5703418c459280b46b7c6.tex b/sail_latex_riscv/valz_get_sv48_paddr_ppni9c768f41f1a5703418c459280b46b7c6.tex new file mode 100644 index 00000000..c2010c4b --- /dev/null +++ b/sail_latex_riscv/valz_get_sv48_paddr_ppni9c768f41f1a5703418c459280b46b7c6.tex @@ -0,0 +1 @@ +_get_SV48_Paddr_PPNi : SV48_Paddr -> bitvector(44, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv48_pte_bits3cedec2ea70a0849ea60d8d346d0f936.tex b/sail_latex_riscv/valz_get_sv48_pte_bits3cedec2ea70a0849ea60d8d346d0f936.tex new file mode 100644 index 00000000..b6aec861 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv48_pte_bits3cedec2ea70a0849ea60d8d346d0f936.tex @@ -0,0 +1 @@ +_get_SV48_PTE_BITS : SV48_PTE -> bitvector(8, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv48_pte_bitsb58b3209e52ef5413579ee91bdf5b83d.tex b/sail_latex_riscv/valz_get_sv48_pte_bitsb58b3209e52ef5413579ee91bdf5b83d.tex new file mode 100644 index 00000000..6d6c6fba --- /dev/null +++ b/sail_latex_riscv/valz_get_sv48_pte_bitsb58b3209e52ef5413579ee91bdf5b83d.tex @@ -0,0 +1 @@ +_get_SV48_PTE_bits : SV48_PTE -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv48_pte_ext9e4ca3d27e7c17dad6458361686784bb.tex b/sail_latex_riscv/valz_get_sv48_pte_ext9e4ca3d27e7c17dad6458361686784bb.tex new file mode 100644 index 00000000..8aad51d7 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv48_pte_ext9e4ca3d27e7c17dad6458361686784bb.tex @@ -0,0 +1 @@ +_get_SV48_PTE_Ext : SV48_PTE -> bitvector(10, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv48_pte_ppni308a2407b318a165e64cac46fe1d2d0b.tex b/sail_latex_riscv/valz_get_sv48_pte_ppni308a2407b318a165e64cac46fe1d2d0b.tex new file mode 100644 index 00000000..b98172cf --- /dev/null +++ b/sail_latex_riscv/valz_get_sv48_pte_ppni308a2407b318a165e64cac46fe1d2d0b.tex @@ -0,0 +1 @@ +_get_SV48_PTE_PPNi : SV48_PTE -> bitvector(44, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv48_pte_rsw44e860cbd993f79b4ea9ef51b7de8885.tex b/sail_latex_riscv/valz_get_sv48_pte_rsw44e860cbd993f79b4ea9ef51b7de8885.tex new file mode 100644 index 00000000..251feb89 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv48_pte_rsw44e860cbd993f79b4ea9ef51b7de8885.tex @@ -0,0 +1 @@ +_get_SV48_PTE_RSW : SV48_PTE -> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv48_vaddr_bits2beaae5ea8854498717f33a471bb5c12.tex b/sail_latex_riscv/valz_get_sv48_vaddr_bits2beaae5ea8854498717f33a471bb5c12.tex new file mode 100644 index 00000000..dcb787a6 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv48_vaddr_bits2beaae5ea8854498717f33a471bb5c12.tex @@ -0,0 +1 @@ +_get_SV48_Vaddr_bits : SV48_Vaddr -> bitvector(48, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv48_vaddr_pgofsb1f1b723984e85436ebf972d3c0794b0.tex b/sail_latex_riscv/valz_get_sv48_vaddr_pgofsb1f1b723984e85436ebf972d3c0794b0.tex new file mode 100644 index 00000000..2ee70831 --- /dev/null +++ b/sail_latex_riscv/valz_get_sv48_vaddr_pgofsb1f1b723984e85436ebf972d3c0794b0.tex @@ -0,0 +1 @@ +_get_SV48_Vaddr_PgOfs : SV48_Vaddr -> bitvector(12, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_sv48_vaddr_vpnibe8fbceb3423612d8be18c52f74da3d9.tex b/sail_latex_riscv/valz_get_sv48_vaddr_vpnibe8fbceb3423612d8be18c52f74da3d9.tex new file mode 100644 index 00000000..2d4779bf --- /dev/null +++ b/sail_latex_riscv/valz_get_sv48_vaddr_vpnibe8fbceb3423612d8be18c52f74da3d9.tex @@ -0,0 +1 @@ +_get_SV48_Vaddr_VPNi : SV48_Vaddr -> bitvector(27, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_uinterrupts_bits0b7d0f2f07976b876318898e01847c70.tex b/sail_latex_riscv/valz_get_uinterrupts_bits0b7d0f2f07976b876318898e01847c70.tex new file mode 100644 index 00000000..632f898e --- /dev/null +++ b/sail_latex_riscv/valz_get_uinterrupts_bits0b7d0f2f07976b876318898e01847c70.tex @@ -0,0 +1 @@ +_get_Uinterrupts_bits : Uinterrupts -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_uinterrupts_uei6c329ab1295c95ff6f49fe4076feabea.tex b/sail_latex_riscv/valz_get_uinterrupts_uei6c329ab1295c95ff6f49fe4076feabea.tex new file mode 100644 index 00000000..962b5f9d --- /dev/null +++ b/sail_latex_riscv/valz_get_uinterrupts_uei6c329ab1295c95ff6f49fe4076feabea.tex @@ -0,0 +1 @@ +_get_Uinterrupts_UEI : Uinterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_uinterrupts_usi1b085056d929d854a848f905b87c060b.tex b/sail_latex_riscv/valz_get_uinterrupts_usi1b085056d929d854a848f905b87c060b.tex new file mode 100644 index 00000000..efb42e28 --- /dev/null +++ b/sail_latex_riscv/valz_get_uinterrupts_usi1b085056d929d854a848f905b87c060b.tex @@ -0,0 +1 @@ +_get_Uinterrupts_USI : Uinterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_uinterrupts_uti4f7a1e53cab567fa843f7436769357a0.tex b/sail_latex_riscv/valz_get_uinterrupts_uti4f7a1e53cab567fa843f7436769357a0.tex new file mode 100644 index 00000000..2264b83c --- /dev/null +++ b/sail_latex_riscv/valz_get_uinterrupts_uti4f7a1e53cab567fa843f7436769357a0.tex @@ -0,0 +1 @@ +_get_Uinterrupts_UTI : Uinterrupts -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_ustatus_bits230116890e8a3e29f1d043be407c7237.tex b/sail_latex_riscv/valz_get_ustatus_bits230116890e8a3e29f1d043be407c7237.tex new file mode 100644 index 00000000..4672dceb --- /dev/null +++ b/sail_latex_riscv/valz_get_ustatus_bits230116890e8a3e29f1d043be407c7237.tex @@ -0,0 +1 @@ +_get_Ustatus_bits : Ustatus -> bitvector(64, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_ustatus_uie443e8ee7d068af4b9b66e7cbf42dd57e.tex b/sail_latex_riscv/valz_get_ustatus_uie443e8ee7d068af4b9b66e7cbf42dd57e.tex new file mode 100644 index 00000000..fcc452e3 --- /dev/null +++ b/sail_latex_riscv/valz_get_ustatus_uie443e8ee7d068af4b9b66e7cbf42dd57e.tex @@ -0,0 +1 @@ +_get_Ustatus_UIE : Ustatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_get_ustatus_upiec1c1afe6b971883383e700b3ef0f0b35.tex b/sail_latex_riscv/valz_get_ustatus_upiec1c1afe6b971883383e700b3ef0f0b35.tex new file mode 100644 index 00000000..4f4c7d61 --- /dev/null +++ b/sail_latex_riscv/valz_get_ustatus_upiec1c1afe6b971883383e700b3ef0f0b35.tex @@ -0,0 +1 @@ +_get_Ustatus_UPIE : Ustatus -> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valz_reg_deref95099334a598a80d1fa0f47df99c8b42.tex b/sail_latex_riscv/valz_reg_deref95099334a598a80d1fa0f47df99c8b42.tex new file mode 100644 index 00000000..5d96af52 --- /dev/null +++ b/sail_latex_riscv/valz_reg_deref95099334a598a80d1fa0f47df99c8b42.tex @@ -0,0 +1 @@ +_reg_deref : forall ('a : Type). register('a) -> 'a \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_ccsr_bits3806e9d0f8a05e576c1382f4734c757e.tex b/sail_latex_riscv/valz_set_ccsr_bits3806e9d0f8a05e576c1382f4734c757e.tex new file mode 100644 index 00000000..b4ccc343 --- /dev/null +++ b/sail_latex_riscv/valz_set_ccsr_bits3806e9d0f8a05e576c1382f4734c757e.tex @@ -0,0 +1 @@ +_set_ccsr_bits : (register(ccsr), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_ccsr_cap_idxf1dab003746059638583e08318dd0939.tex b/sail_latex_riscv/valz_set_ccsr_cap_idxf1dab003746059638583e08318dd0939.tex new file mode 100644 index 00000000..f8976800 --- /dev/null +++ b/sail_latex_riscv/valz_set_ccsr_cap_idxf1dab003746059638583e08318dd0939.tex @@ -0,0 +1 @@ +_set_ccsr_cap_idx : (register(ccsr), bitvector(6, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_ccsr_causea61c64eff6f93cf534fa898aaa26f2b0.tex b/sail_latex_riscv/valz_set_ccsr_causea61c64eff6f93cf534fa898aaa26f2b0.tex new file mode 100644 index 00000000..936eea6c --- /dev/null +++ b/sail_latex_riscv/valz_set_ccsr_causea61c64eff6f93cf534fa898aaa26f2b0.tex @@ -0,0 +1 @@ +_set_ccsr_cause : (register(ccsr), bitvector(5, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_ccsr_db32b59142df24c8fe9016263b659269d.tex b/sail_latex_riscv/valz_set_ccsr_db32b59142df24c8fe9016263b659269d.tex new file mode 100644 index 00000000..e1df6994 --- /dev/null +++ b/sail_latex_riscv/valz_set_ccsr_db32b59142df24c8fe9016263b659269d.tex @@ -0,0 +1 @@ +_set_ccsr_d : (register(ccsr), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_ccsr_e1c0d679cfed0abc1454ed21db9246e96.tex b/sail_latex_riscv/valz_set_ccsr_e1c0d679cfed0abc1454ed21db9246e96.tex new file mode 100644 index 00000000..a259b029 --- /dev/null +++ b/sail_latex_riscv/valz_set_ccsr_e1c0d679cfed0abc1454ed21db9246e96.tex @@ -0,0 +1 @@ +_set_ccsr_e : (register(ccsr), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_counteren_bits645facfec852be9a4b81ed364e1460c2.tex b/sail_latex_riscv/valz_set_counteren_bits645facfec852be9a4b81ed364e1460c2.tex new file mode 100644 index 00000000..0ba1e5d3 --- /dev/null +++ b/sail_latex_riscv/valz_set_counteren_bits645facfec852be9a4b81ed364e1460c2.tex @@ -0,0 +1 @@ +_set_Counteren_bits : (register(Counteren), bitvector(32, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_counteren_cy596db6893acf37ac3bd153f29c01a4f5.tex b/sail_latex_riscv/valz_set_counteren_cy596db6893acf37ac3bd153f29c01a4f5.tex new file mode 100644 index 00000000..f5514e16 --- /dev/null +++ b/sail_latex_riscv/valz_set_counteren_cy596db6893acf37ac3bd153f29c01a4f5.tex @@ -0,0 +1 @@ +_set_Counteren_CY : (register(Counteren), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_counteren_hpme0b60e00eab80a2934fe853d7cc21c79.tex b/sail_latex_riscv/valz_set_counteren_hpme0b60e00eab80a2934fe853d7cc21c79.tex new file mode 100644 index 00000000..9792d6c4 --- /dev/null +++ b/sail_latex_riscv/valz_set_counteren_hpme0b60e00eab80a2934fe853d7cc21c79.tex @@ -0,0 +1 @@ +_set_Counteren_HPM : (register(Counteren), bitvector(29, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_counteren_irc2c31e7ff83f5b56636c924d61b260d2.tex b/sail_latex_riscv/valz_set_counteren_irc2c31e7ff83f5b56636c924d61b260d2.tex new file mode 100644 index 00000000..3f35c001 --- /dev/null +++ b/sail_latex_riscv/valz_set_counteren_irc2c31e7ff83f5b56636c924d61b260d2.tex @@ -0,0 +1 @@ +_set_Counteren_IR : (register(Counteren), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_counteren_tmed5ea23cd819bd09590e67c1c76777b7.tex b/sail_latex_riscv/valz_set_counteren_tmed5ea23cd819bd09590e67c1c76777b7.tex new file mode 100644 index 00000000..3f62f536 --- /dev/null +++ b/sail_latex_riscv/valz_set_counteren_tmed5ea23cd819bd09590e67c1c76777b7.tex @@ -0,0 +1 @@ +_set_Counteren_TM : (register(Counteren), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_counterin_bits4d906fc122c4b0829e669029457bff46.tex b/sail_latex_riscv/valz_set_counterin_bits4d906fc122c4b0829e669029457bff46.tex new file mode 100644 index 00000000..dd7b72b5 --- /dev/null +++ b/sail_latex_riscv/valz_set_counterin_bits4d906fc122c4b0829e669029457bff46.tex @@ -0,0 +1 @@ +_set_Counterin_bits : (register(Counterin), bitvector(32, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_counterin_cy2ee6f977ede334731ad36d7afe6e2be4.tex b/sail_latex_riscv/valz_set_counterin_cy2ee6f977ede334731ad36d7afe6e2be4.tex new file mode 100644 index 00000000..2c4ca7d9 --- /dev/null +++ b/sail_latex_riscv/valz_set_counterin_cy2ee6f977ede334731ad36d7afe6e2be4.tex @@ -0,0 +1 @@ +_set_Counterin_CY : (register(Counterin), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_counterin_ir7435617becd3df612dd905733de79ab0.tex b/sail_latex_riscv/valz_set_counterin_ir7435617becd3df612dd905733de79ab0.tex new file mode 100644 index 00000000..27280254 --- /dev/null +++ b/sail_latex_riscv/valz_set_counterin_ir7435617becd3df612dd905733de79ab0.tex @@ -0,0 +1 @@ +_set_Counterin_IR : (register(Counterin), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_ext_pte_bits_bitsa761c9ca2c6e788009a6f80b588af6be.tex b/sail_latex_riscv/valz_set_ext_pte_bits_bitsa761c9ca2c6e788009a6f80b588af6be.tex new file mode 100644 index 00000000..005dca16 --- /dev/null +++ b/sail_latex_riscv/valz_set_ext_pte_bits_bitsa761c9ca2c6e788009a6f80b588af6be.tex @@ -0,0 +1 @@ +_set_Ext_PTE_Bits_bits : (register(Ext_PTE_Bits), bitvector(10, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_ext_pte_bits_capreadfba293dd04ef2251e165147b0523320d.tex b/sail_latex_riscv/valz_set_ext_pte_bits_capreadfba293dd04ef2251e165147b0523320d.tex new file mode 100644 index 00000000..e8f4680b --- /dev/null +++ b/sail_latex_riscv/valz_set_ext_pte_bits_capreadfba293dd04ef2251e165147b0523320d.tex @@ -0,0 +1 @@ +_set_Ext_PTE_Bits_CapRead : (register(Ext_PTE_Bits), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_ext_pte_bits_capwriteccb693fb16cf80f8b094a130c168d1f7.tex b/sail_latex_riscv/valz_set_ext_pte_bits_capwriteccb693fb16cf80f8b094a130c168d1f7.tex new file mode 100644 index 00000000..cccfda43 --- /dev/null +++ b/sail_latex_riscv/valz_set_ext_pte_bits_capwriteccb693fb16cf80f8b094a130c168d1f7.tex @@ -0,0 +1 @@ +_set_Ext_PTE_Bits_CapWrite : (register(Ext_PTE_Bits), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_fcsr_bits14808d6e9585f49863a62ef97cfccc18.tex b/sail_latex_riscv/valz_set_fcsr_bits14808d6e9585f49863a62ef97cfccc18.tex new file mode 100644 index 00000000..11c973fa --- /dev/null +++ b/sail_latex_riscv/valz_set_fcsr_bits14808d6e9585f49863a62ef97cfccc18.tex @@ -0,0 +1 @@ +_set_Fcsr_bits : (register(Fcsr), bitvector(32, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_fcsr_fflagsd8192cedf9e30718ca38134692e797b3.tex b/sail_latex_riscv/valz_set_fcsr_fflagsd8192cedf9e30718ca38134692e797b3.tex new file mode 100644 index 00000000..a6f71db2 --- /dev/null +++ b/sail_latex_riscv/valz_set_fcsr_fflagsd8192cedf9e30718ca38134692e797b3.tex @@ -0,0 +1 @@ +_set_Fcsr_FFLAGS : (register(Fcsr), bitvector(5, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_fcsr_frmadaccc6e48224bd13dc49815c7dca973.tex b/sail_latex_riscv/valz_set_fcsr_frmadaccc6e48224bd13dc49815c7dca973.tex new file mode 100644 index 00000000..76b4aa37 --- /dev/null +++ b/sail_latex_riscv/valz_set_fcsr_frmadaccc6e48224bd13dc49815c7dca973.tex @@ -0,0 +1 @@ +_set_Fcsr_FRM : (register(Fcsr), bitvector(3, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_htif_cmd_bits689a1226135e157ab73f85b4e32f7b0e.tex b/sail_latex_riscv/valz_set_htif_cmd_bits689a1226135e157ab73f85b4e32f7b0e.tex new file mode 100644 index 00000000..2dae7d86 --- /dev/null +++ b/sail_latex_riscv/valz_set_htif_cmd_bits689a1226135e157ab73f85b4e32f7b0e.tex @@ -0,0 +1 @@ +_set_htif_cmd_bits : (register(htif_cmd), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_htif_cmd_cmd0433aa4c5b2a4721f8f44a87e408d238.tex b/sail_latex_riscv/valz_set_htif_cmd_cmd0433aa4c5b2a4721f8f44a87e408d238.tex new file mode 100644 index 00000000..f9acd0fa --- /dev/null +++ b/sail_latex_riscv/valz_set_htif_cmd_cmd0433aa4c5b2a4721f8f44a87e408d238.tex @@ -0,0 +1 @@ +_set_htif_cmd_cmd : (register(htif_cmd), bitvector(8, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_htif_cmd_deviceca3d219cd020878f1e936d65dadd246c.tex b/sail_latex_riscv/valz_set_htif_cmd_deviceca3d219cd020878f1e936d65dadd246c.tex new file mode 100644 index 00000000..bdad2d16 --- /dev/null +++ b/sail_latex_riscv/valz_set_htif_cmd_deviceca3d219cd020878f1e936d65dadd246c.tex @@ -0,0 +1 @@ +_set_htif_cmd_device : (register(htif_cmd), bitvector(8, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_htif_cmd_payload54f16ea011075a1e7c5afa0c27e684a6.tex b/sail_latex_riscv/valz_set_htif_cmd_payload54f16ea011075a1e7c5afa0c27e684a6.tex new file mode 100644 index 00000000..c742c0b8 --- /dev/null +++ b/sail_latex_riscv/valz_set_htif_cmd_payload54f16ea011075a1e7c5afa0c27e684a6.tex @@ -0,0 +1 @@ +_set_htif_cmd_payload : (register(htif_cmd), bitvector(48, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mcause_bits80b6d4b61ba8cd659ac54309cbdb9ea7.tex b/sail_latex_riscv/valz_set_mcause_bits80b6d4b61ba8cd659ac54309cbdb9ea7.tex new file mode 100644 index 00000000..fc734b88 --- /dev/null +++ b/sail_latex_riscv/valz_set_mcause_bits80b6d4b61ba8cd659ac54309cbdb9ea7.tex @@ -0,0 +1 @@ +_set_Mcause_bits : (register(Mcause), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mcause_causecce7178eb6a826303b904fd987904cff.tex b/sail_latex_riscv/valz_set_mcause_causecce7178eb6a826303b904fd987904cff.tex new file mode 100644 index 00000000..34211b53 --- /dev/null +++ b/sail_latex_riscv/valz_set_mcause_causecce7178eb6a826303b904fd987904cff.tex @@ -0,0 +1 @@ +_set_Mcause_Cause : (register(Mcause), bitvector(63, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mcause_isinterrupt6acecb43461e553536ef76a71d78c3e7.tex b/sail_latex_riscv/valz_set_mcause_isinterrupt6acecb43461e553536ef76a71d78c3e7.tex new file mode 100644 index 00000000..1eca65d6 --- /dev/null +++ b/sail_latex_riscv/valz_set_mcause_isinterrupt6acecb43461e553536ef76a71d78c3e7.tex @@ -0,0 +1 @@ +_set_Mcause_IsInterrupt : (register(Mcause), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_bitsa5164a346cdd02dcec13d6e5c2839918.tex b/sail_latex_riscv/valz_set_medeleg_bitsa5164a346cdd02dcec13d6e5c2839918.tex new file mode 100644 index 00000000..c14ad0ea --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_bitsa5164a346cdd02dcec13d6e5c2839918.tex @@ -0,0 +1 @@ +_set_Medeleg_bits : (register(Medeleg), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_breakpoint65522090d2dce601562eb82bb71ebd27.tex b/sail_latex_riscv/valz_set_medeleg_breakpoint65522090d2dce601562eb82bb71ebd27.tex new file mode 100644 index 00000000..02ec0209 --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_breakpoint65522090d2dce601562eb82bb71ebd27.tex @@ -0,0 +1 @@ +_set_Medeleg_Breakpoint : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_fetch_access_fault8b3d91a41393ae3c76d0df3e801928e9.tex b/sail_latex_riscv/valz_set_medeleg_fetch_access_fault8b3d91a41393ae3c76d0df3e801928e9.tex new file mode 100644 index 00000000..059a10c2 --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_fetch_access_fault8b3d91a41393ae3c76d0df3e801928e9.tex @@ -0,0 +1 @@ +_set_Medeleg_Fetch_Access_Fault : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_fetch_addr_align514673a27e7f896be9dea81dc7662148.tex b/sail_latex_riscv/valz_set_medeleg_fetch_addr_align514673a27e7f896be9dea81dc7662148.tex new file mode 100644 index 00000000..edfc5c7c --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_fetch_addr_align514673a27e7f896be9dea81dc7662148.tex @@ -0,0 +1 @@ +_set_Medeleg_Fetch_Addr_Align : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_fetch_page_faultefe8fe08b8ed5f78322e6a4864364068.tex b/sail_latex_riscv/valz_set_medeleg_fetch_page_faultefe8fe08b8ed5f78322e6a4864364068.tex new file mode 100644 index 00000000..2af6aa05 --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_fetch_page_faultefe8fe08b8ed5f78322e6a4864364068.tex @@ -0,0 +1 @@ +_set_Medeleg_Fetch_Page_Fault : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_illegal_instr0ddff62c362ec255b511a781fc6e9551.tex b/sail_latex_riscv/valz_set_medeleg_illegal_instr0ddff62c362ec255b511a781fc6e9551.tex new file mode 100644 index 00000000..686f94a6 --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_illegal_instr0ddff62c362ec255b511a781fc6e9551.tex @@ -0,0 +1 @@ +_set_Medeleg_Illegal_Instr : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_load_access_fault6e32b99197543196d68c443430ddcd76.tex b/sail_latex_riscv/valz_set_medeleg_load_access_fault6e32b99197543196d68c443430ddcd76.tex new file mode 100644 index 00000000..c53f0b77 --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_load_access_fault6e32b99197543196d68c443430ddcd76.tex @@ -0,0 +1 @@ +_set_Medeleg_Load_Access_Fault : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_load_addr_align477e12d39eacad577451a2c4ce6c5028.tex b/sail_latex_riscv/valz_set_medeleg_load_addr_align477e12d39eacad577451a2c4ce6c5028.tex new file mode 100644 index 00000000..344c5c10 --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_load_addr_align477e12d39eacad577451a2c4ce6c5028.tex @@ -0,0 +1 @@ +_set_Medeleg_Load_Addr_Align : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_load_page_fault9d4748d81d2b444605a3e9cebc4943d7.tex b/sail_latex_riscv/valz_set_medeleg_load_page_fault9d4748d81d2b444605a3e9cebc4943d7.tex new file mode 100644 index 00000000..d0850bda --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_load_page_fault9d4748d81d2b444605a3e9cebc4943d7.tex @@ -0,0 +1 @@ +_set_Medeleg_Load_Page_Fault : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_menvcall1e30100a01455a75d7aaa14d1ba8b171.tex b/sail_latex_riscv/valz_set_medeleg_menvcall1e30100a01455a75d7aaa14d1ba8b171.tex new file mode 100644 index 00000000..5ccf3419 --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_menvcall1e30100a01455a75d7aaa14d1ba8b171.tex @@ -0,0 +1 @@ +_set_Medeleg_MEnvCall : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_samo_access_fault1dfec566f185ab6cce1059f544290cf1.tex b/sail_latex_riscv/valz_set_medeleg_samo_access_fault1dfec566f185ab6cce1059f544290cf1.tex new file mode 100644 index 00000000..136d8085 --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_samo_access_fault1dfec566f185ab6cce1059f544290cf1.tex @@ -0,0 +1 @@ +_set_Medeleg_SAMO_Access_Fault : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_samo_addr_align00c5e4839832dee86f8bfd26cc3f2a80.tex b/sail_latex_riscv/valz_set_medeleg_samo_addr_align00c5e4839832dee86f8bfd26cc3f2a80.tex new file mode 100644 index 00000000..e800dccf --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_samo_addr_align00c5e4839832dee86f8bfd26cc3f2a80.tex @@ -0,0 +1 @@ +_set_Medeleg_SAMO_Addr_Align : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_samo_page_fault3b09cdf77cb2b2817f7c0f833cc758ce.tex b/sail_latex_riscv/valz_set_medeleg_samo_page_fault3b09cdf77cb2b2817f7c0f833cc758ce.tex new file mode 100644 index 00000000..58160d6c --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_samo_page_fault3b09cdf77cb2b2817f7c0f833cc758ce.tex @@ -0,0 +1 @@ +_set_Medeleg_SAMO_Page_Fault : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_senvcall9eab904bcf0e2130341264216cb52176.tex b/sail_latex_riscv/valz_set_medeleg_senvcall9eab904bcf0e2130341264216cb52176.tex new file mode 100644 index 00000000..158e6563 --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_senvcall9eab904bcf0e2130341264216cb52176.tex @@ -0,0 +1 @@ +_set_Medeleg_SEnvCall : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_medeleg_uenvcallb8f205a15af52cac02b9bb0657a52d33.tex b/sail_latex_riscv/valz_set_medeleg_uenvcallb8f205a15af52cac02b9bb0657a52d33.tex new file mode 100644 index 00000000..c5cf58a2 --- /dev/null +++ b/sail_latex_riscv/valz_set_medeleg_uenvcallb8f205a15af52cac02b9bb0657a52d33.tex @@ -0,0 +1 @@ +_set_Medeleg_UEnvCall : (register(Medeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_minterrupts_bits33c9485121287572c28dfb5038fc3d62.tex b/sail_latex_riscv/valz_set_minterrupts_bits33c9485121287572c28dfb5038fc3d62.tex new file mode 100644 index 00000000..7008f1b8 --- /dev/null +++ b/sail_latex_riscv/valz_set_minterrupts_bits33c9485121287572c28dfb5038fc3d62.tex @@ -0,0 +1 @@ +_set_Minterrupts_bits : (register(Minterrupts), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_minterrupts_mei9744cce951b17c7e2932ca8ace0338c4.tex b/sail_latex_riscv/valz_set_minterrupts_mei9744cce951b17c7e2932ca8ace0338c4.tex new file mode 100644 index 00000000..b8a0856f --- /dev/null +++ b/sail_latex_riscv/valz_set_minterrupts_mei9744cce951b17c7e2932ca8ace0338c4.tex @@ -0,0 +1 @@ +_set_Minterrupts_MEI : (register(Minterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_minterrupts_msi2f29aeb62fd44e400e4d6811ee58eff4.tex b/sail_latex_riscv/valz_set_minterrupts_msi2f29aeb62fd44e400e4d6811ee58eff4.tex new file mode 100644 index 00000000..48e85666 --- /dev/null +++ b/sail_latex_riscv/valz_set_minterrupts_msi2f29aeb62fd44e400e4d6811ee58eff4.tex @@ -0,0 +1 @@ +_set_Minterrupts_MSI : (register(Minterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_minterrupts_mtia7bb5032baba4531a4c7bb5fe29eed89.tex b/sail_latex_riscv/valz_set_minterrupts_mtia7bb5032baba4531a4c7bb5fe29eed89.tex new file mode 100644 index 00000000..3c39501b --- /dev/null +++ b/sail_latex_riscv/valz_set_minterrupts_mtia7bb5032baba4531a4c7bb5fe29eed89.tex @@ -0,0 +1 @@ +_set_Minterrupts_MTI : (register(Minterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_minterrupts_seied3b72a76b0168176b36aa09bb08b409.tex b/sail_latex_riscv/valz_set_minterrupts_seied3b72a76b0168176b36aa09bb08b409.tex new file mode 100644 index 00000000..8104b9cc --- /dev/null +++ b/sail_latex_riscv/valz_set_minterrupts_seied3b72a76b0168176b36aa09bb08b409.tex @@ -0,0 +1 @@ +_set_Minterrupts_SEI : (register(Minterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_minterrupts_ssi862fdaa740d3553d0b00abbad005b654.tex b/sail_latex_riscv/valz_set_minterrupts_ssi862fdaa740d3553d0b00abbad005b654.tex new file mode 100644 index 00000000..01f0f02d --- /dev/null +++ b/sail_latex_riscv/valz_set_minterrupts_ssi862fdaa740d3553d0b00abbad005b654.tex @@ -0,0 +1 @@ +_set_Minterrupts_SSI : (register(Minterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_minterrupts_sti916655477209971ff8cdb58c26f6ef93.tex b/sail_latex_riscv/valz_set_minterrupts_sti916655477209971ff8cdb58c26f6ef93.tex new file mode 100644 index 00000000..490426f7 --- /dev/null +++ b/sail_latex_riscv/valz_set_minterrupts_sti916655477209971ff8cdb58c26f6ef93.tex @@ -0,0 +1 @@ +_set_Minterrupts_STI : (register(Minterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_minterrupts_uei094ebc68e14480c18355d8aa2f610f29.tex b/sail_latex_riscv/valz_set_minterrupts_uei094ebc68e14480c18355d8aa2f610f29.tex new file mode 100644 index 00000000..2b7abb96 --- /dev/null +++ b/sail_latex_riscv/valz_set_minterrupts_uei094ebc68e14480c18355d8aa2f610f29.tex @@ -0,0 +1 @@ +_set_Minterrupts_UEI : (register(Minterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_minterrupts_usi073c76e1d0b95c4329e14eefe61bddb2.tex b/sail_latex_riscv/valz_set_minterrupts_usi073c76e1d0b95c4329e14eefe61bddb2.tex new file mode 100644 index 00000000..539c261d --- /dev/null +++ b/sail_latex_riscv/valz_set_minterrupts_usi073c76e1d0b95c4329e14eefe61bddb2.tex @@ -0,0 +1 @@ +_set_Minterrupts_USI : (register(Minterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_minterrupts_utid09c8a6e5f537755c8564dc71a61f188.tex b/sail_latex_riscv/valz_set_minterrupts_utid09c8a6e5f537755c8564dc71a61f188.tex new file mode 100644 index 00000000..7008a6a3 --- /dev/null +++ b/sail_latex_riscv/valz_set_minterrupts_utid09c8a6e5f537755c8564dc71a61f188.tex @@ -0,0 +1 @@ +_set_Minterrupts_UTI : (register(Minterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_af2a884db4759788724edc2e8603b8be4.tex b/sail_latex_riscv/valz_set_misa_af2a884db4759788724edc2e8603b8be4.tex new file mode 100644 index 00000000..4719519f --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_af2a884db4759788724edc2e8603b8be4.tex @@ -0,0 +1 @@ +_set_Misa_A : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_b0a197892362ef80b92b24e457a36fe2e.tex b/sail_latex_riscv/valz_set_misa_b0a197892362ef80b92b24e457a36fe2e.tex new file mode 100644 index 00000000..db3dced8 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_b0a197892362ef80b92b24e457a36fe2e.tex @@ -0,0 +1 @@ +_set_Misa_B : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_bits8a8c7777988f3569033d87950ad2055d.tex b/sail_latex_riscv/valz_set_misa_bits8a8c7777988f3569033d87950ad2055d.tex new file mode 100644 index 00000000..8e76f655 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_bits8a8c7777988f3569033d87950ad2055d.tex @@ -0,0 +1 @@ +_set_Misa_bits : (register(Misa), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_cdd88b98e41a5e410ecf7b2bf6be19aa8.tex b/sail_latex_riscv/valz_set_misa_cdd88b98e41a5e410ecf7b2bf6be19aa8.tex new file mode 100644 index 00000000..450454c2 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_cdd88b98e41a5e410ecf7b2bf6be19aa8.tex @@ -0,0 +1 @@ +_set_Misa_C : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_dc53b7d60ef59832cce8ea7080073ac39.tex b/sail_latex_riscv/valz_set_misa_dc53b7d60ef59832cce8ea7080073ac39.tex new file mode 100644 index 00000000..c5f413fd --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_dc53b7d60ef59832cce8ea7080073ac39.tex @@ -0,0 +1 @@ +_set_Misa_D : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_e36282592c3981fb3312fd0b0b03227bd.tex b/sail_latex_riscv/valz_set_misa_e36282592c3981fb3312fd0b0b03227bd.tex new file mode 100644 index 00000000..7f1ebc54 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_e36282592c3981fb3312fd0b0b03227bd.tex @@ -0,0 +1 @@ +_set_Misa_E : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_f8c698083198450c6a61ec00abe038c08.tex b/sail_latex_riscv/valz_set_misa_f8c698083198450c6a61ec00abe038c08.tex new file mode 100644 index 00000000..3cca55d6 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_f8c698083198450c6a61ec00abe038c08.tex @@ -0,0 +1 @@ +_set_Misa_F : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_g7e6256e7a4ea213c35876542280b8601.tex b/sail_latex_riscv/valz_set_misa_g7e6256e7a4ea213c35876542280b8601.tex new file mode 100644 index 00000000..ad640688 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_g7e6256e7a4ea213c35876542280b8601.tex @@ -0,0 +1 @@ +_set_Misa_G : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_h7a13933c5ad288a885bba1ccd7aa1003.tex b/sail_latex_riscv/valz_set_misa_h7a13933c5ad288a885bba1ccd7aa1003.tex new file mode 100644 index 00000000..c67da43c --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_h7a13933c5ad288a885bba1ccd7aa1003.tex @@ -0,0 +1 @@ +_set_Misa_H : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_i459bf00eda120c5909e07545e00c48c1.tex b/sail_latex_riscv/valz_set_misa_i459bf00eda120c5909e07545e00c48c1.tex new file mode 100644 index 00000000..acd9dee4 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_i459bf00eda120c5909e07545e00c48c1.tex @@ -0,0 +1 @@ +_set_Misa_I : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_jf62a4ffaf2eeedcd5ec20654000caf02.tex b/sail_latex_riscv/valz_set_misa_jf62a4ffaf2eeedcd5ec20654000caf02.tex new file mode 100644 index 00000000..28e89c99 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_jf62a4ffaf2eeedcd5ec20654000caf02.tex @@ -0,0 +1 @@ +_set_Misa_J : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_k32d9915ba6161247dfa2e07599b14f05.tex b/sail_latex_riscv/valz_set_misa_k32d9915ba6161247dfa2e07599b14f05.tex new file mode 100644 index 00000000..f5334e9e --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_k32d9915ba6161247dfa2e07599b14f05.tex @@ -0,0 +1 @@ +_set_Misa_K : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_lce522273afcdcceb0fff20729aec4ac4.tex b/sail_latex_riscv/valz_set_misa_lce522273afcdcceb0fff20729aec4ac4.tex new file mode 100644 index 00000000..87bc9d8e --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_lce522273afcdcceb0fff20729aec4ac4.tex @@ -0,0 +1 @@ +_set_Misa_L : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_m9fc1a0ff196728bb0dbae698e2e8a7e9.tex b/sail_latex_riscv/valz_set_misa_m9fc1a0ff196728bb0dbae698e2e8a7e9.tex new file mode 100644 index 00000000..7f958486 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_m9fc1a0ff196728bb0dbae698e2e8a7e9.tex @@ -0,0 +1 @@ +_set_Misa_M : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_mxlfaf2da4a42816291e01fbd0451c6cfc5.tex b/sail_latex_riscv/valz_set_misa_mxlfaf2da4a42816291e01fbd0451c6cfc5.tex new file mode 100644 index 00000000..086e5576 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_mxlfaf2da4a42816291e01fbd0451c6cfc5.tex @@ -0,0 +1 @@ +_set_Misa_MXL : (register(Misa), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_n1bb6db66ab4e88190d63b918228487ea.tex b/sail_latex_riscv/valz_set_misa_n1bb6db66ab4e88190d63b918228487ea.tex new file mode 100644 index 00000000..5b60e803 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_n1bb6db66ab4e88190d63b918228487ea.tex @@ -0,0 +1 @@ +_set_Misa_N : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_o6e1ac3382cd1de0c3fbbaf6bbce3e104.tex b/sail_latex_riscv/valz_set_misa_o6e1ac3382cd1de0c3fbbaf6bbce3e104.tex new file mode 100644 index 00000000..36c08ee8 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_o6e1ac3382cd1de0c3fbbaf6bbce3e104.tex @@ -0,0 +1 @@ +_set_Misa_O : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_p0c9c63b8a5952a51bae2365cdbc17092.tex b/sail_latex_riscv/valz_set_misa_p0c9c63b8a5952a51bae2365cdbc17092.tex new file mode 100644 index 00000000..875cab13 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_p0c9c63b8a5952a51bae2365cdbc17092.tex @@ -0,0 +1 @@ +_set_Misa_P : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_q0b750236d1f52d9ca63b5ff7f29aeaad.tex b/sail_latex_riscv/valz_set_misa_q0b750236d1f52d9ca63b5ff7f29aeaad.tex new file mode 100644 index 00000000..eaed9c01 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_q0b750236d1f52d9ca63b5ff7f29aeaad.tex @@ -0,0 +1 @@ +_set_Misa_Q : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_r2e9e070264ac8e4df4365cbcd9bfec35.tex b/sail_latex_riscv/valz_set_misa_r2e9e070264ac8e4df4365cbcd9bfec35.tex new file mode 100644 index 00000000..d6d7fb37 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_r2e9e070264ac8e4df4365cbcd9bfec35.tex @@ -0,0 +1 @@ +_set_Misa_R : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_s4c44d8942646231e0c7666a1590a0a92.tex b/sail_latex_riscv/valz_set_misa_s4c44d8942646231e0c7666a1590a0a92.tex new file mode 100644 index 00000000..cf0c781a --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_s4c44d8942646231e0c7666a1590a0a92.tex @@ -0,0 +1 @@ +_set_Misa_S : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_tc2c88db403b799714c1a38812acd037c.tex b/sail_latex_riscv/valz_set_misa_tc2c88db403b799714c1a38812acd037c.tex new file mode 100644 index 00000000..00c65058 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_tc2c88db403b799714c1a38812acd037c.tex @@ -0,0 +1 @@ +_set_Misa_T : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_ub0a56841c43a9fb3c49a6bee644b7362.tex b/sail_latex_riscv/valz_set_misa_ub0a56841c43a9fb3c49a6bee644b7362.tex new file mode 100644 index 00000000..8b585cab --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_ub0a56841c43a9fb3c49a6bee644b7362.tex @@ -0,0 +1 @@ +_set_Misa_U : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_vd4a716e627db58a7aa372269cb454a1e.tex b/sail_latex_riscv/valz_set_misa_vd4a716e627db58a7aa372269cb454a1e.tex new file mode 100644 index 00000000..956b7cbb --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_vd4a716e627db58a7aa372269cb454a1e.tex @@ -0,0 +1 @@ +_set_Misa_V : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_wcf078697ae48ea6fcaebfe7fc01e054a.tex b/sail_latex_riscv/valz_set_misa_wcf078697ae48ea6fcaebfe7fc01e054a.tex new file mode 100644 index 00000000..c65670da --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_wcf078697ae48ea6fcaebfe7fc01e054a.tex @@ -0,0 +1 @@ +_set_Misa_W : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_x73ca1bfd41ee29a68574f834d43acd6b.tex b/sail_latex_riscv/valz_set_misa_x73ca1bfd41ee29a68574f834d43acd6b.tex new file mode 100644 index 00000000..949f5d49 --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_x73ca1bfd41ee29a68574f834d43acd6b.tex @@ -0,0 +1 @@ +_set_Misa_X : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_y0780ac18d01eba2171fd0f4807b7f5eb.tex b/sail_latex_riscv/valz_set_misa_y0780ac18d01eba2171fd0f4807b7f5eb.tex new file mode 100644 index 00000000..6fed5dab --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_y0780ac18d01eba2171fd0f4807b7f5eb.tex @@ -0,0 +1 @@ +_set_Misa_Y : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_misa_z0aa6e14567359f53c59523971c522eda.tex b/sail_latex_riscv/valz_set_misa_z0aa6e14567359f53c59523971c522eda.tex new file mode 100644 index 00000000..f549b28d --- /dev/null +++ b/sail_latex_riscv/valz_set_misa_z0aa6e14567359f53c59523971c522eda.tex @@ -0,0 +1 @@ +_set_Misa_Z : (register(Misa), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_bits70d36d4b6b9dcb53e2c6533f6831dfa1.tex b/sail_latex_riscv/valz_set_mstatus_bits70d36d4b6b9dcb53e2c6533f6831dfa1.tex new file mode 100644 index 00000000..07a04d79 --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_bits70d36d4b6b9dcb53e2c6533f6831dfa1.tex @@ -0,0 +1 @@ +_set_Mstatus_bits : (register(Mstatus), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_fsf8cc24d417ffb4c08683df543afa5120.tex b/sail_latex_riscv/valz_set_mstatus_fsf8cc24d417ffb4c08683df543afa5120.tex new file mode 100644 index 00000000..40ee1127 --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_fsf8cc24d417ffb4c08683df543afa5120.tex @@ -0,0 +1 @@ +_set_Mstatus_FS : (register(Mstatus), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_mie3ca1abf74b0d93affa2751898f9cdd5b.tex b/sail_latex_riscv/valz_set_mstatus_mie3ca1abf74b0d93affa2751898f9cdd5b.tex new file mode 100644 index 00000000..171db17b --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_mie3ca1abf74b0d93affa2751898f9cdd5b.tex @@ -0,0 +1 @@ +_set_Mstatus_MIE : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_mpieb229e5b0c3cc862190502f8c77503c18.tex b/sail_latex_riscv/valz_set_mstatus_mpieb229e5b0c3cc862190502f8c77503c18.tex new file mode 100644 index 00000000..dd182608 --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_mpieb229e5b0c3cc862190502f8c77503c18.tex @@ -0,0 +1 @@ +_set_Mstatus_MPIE : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_mppaeee0122745c7341c92694423c1d67fa.tex b/sail_latex_riscv/valz_set_mstatus_mppaeee0122745c7341c92694423c1d67fa.tex new file mode 100644 index 00000000..f7d8779f --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_mppaeee0122745c7341c92694423c1d67fa.tex @@ -0,0 +1 @@ +_set_Mstatus_MPP : (register(Mstatus), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_mprv7cb39a57c743d887daa45479299eb721.tex b/sail_latex_riscv/valz_set_mstatus_mprv7cb39a57c743d887daa45479299eb721.tex new file mode 100644 index 00000000..68a0edb6 --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_mprv7cb39a57c743d887daa45479299eb721.tex @@ -0,0 +1 @@ +_set_Mstatus_MPRV : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_mxr7d2c792dc408468b6a36d6dccfe73ce3.tex b/sail_latex_riscv/valz_set_mstatus_mxr7d2c792dc408468b6a36d6dccfe73ce3.tex new file mode 100644 index 00000000..09155805 --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_mxr7d2c792dc408468b6a36d6dccfe73ce3.tex @@ -0,0 +1 @@ +_set_Mstatus_MXR : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_sdd513d7f81bd0e504ac04f4e053f73dea.tex b/sail_latex_riscv/valz_set_mstatus_sdd513d7f81bd0e504ac04f4e053f73dea.tex new file mode 100644 index 00000000..1738bcdd --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_sdd513d7f81bd0e504ac04f4e053f73dea.tex @@ -0,0 +1 @@ +_set_Mstatus_SD : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_sie307ee7865e3a638cfafc30565428356d.tex b/sail_latex_riscv/valz_set_mstatus_sie307ee7865e3a638cfafc30565428356d.tex new file mode 100644 index 00000000..f01b4e6f --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_sie307ee7865e3a638cfafc30565428356d.tex @@ -0,0 +1 @@ +_set_Mstatus_SIE : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_spie57764ca3799b0493ec493d655361699e.tex b/sail_latex_riscv/valz_set_mstatus_spie57764ca3799b0493ec493d655361699e.tex new file mode 100644 index 00000000..9215f9ef --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_spie57764ca3799b0493ec493d655361699e.tex @@ -0,0 +1 @@ +_set_Mstatus_SPIE : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_sppf813af50b83110182ea2f06174cb1d20.tex b/sail_latex_riscv/valz_set_mstatus_sppf813af50b83110182ea2f06174cb1d20.tex new file mode 100644 index 00000000..fd0787d1 --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_sppf813af50b83110182ea2f06174cb1d20.tex @@ -0,0 +1 @@ +_set_Mstatus_SPP : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_sume93a07e55c0ec08fc5f1fff8ec36c08c.tex b/sail_latex_riscv/valz_set_mstatus_sume93a07e55c0ec08fc5f1fff8ec36c08c.tex new file mode 100644 index 00000000..35e47b2a --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_sume93a07e55c0ec08fc5f1fff8ec36c08c.tex @@ -0,0 +1 @@ +_set_Mstatus_SUM : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_tsraafd8a43c6d53a07c488b0efb80af394.tex b/sail_latex_riscv/valz_set_mstatus_tsraafd8a43c6d53a07c488b0efb80af394.tex new file mode 100644 index 00000000..aea3f088 --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_tsraafd8a43c6d53a07c488b0efb80af394.tex @@ -0,0 +1 @@ +_set_Mstatus_TSR : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_tvmb162bee39ba51b064f3dd93188326775.tex b/sail_latex_riscv/valz_set_mstatus_tvmb162bee39ba51b064f3dd93188326775.tex new file mode 100644 index 00000000..1625833a --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_tvmb162bee39ba51b064f3dd93188326775.tex @@ -0,0 +1 @@ +_set_Mstatus_TVM : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_tw07f419963ff98d483c7b9ce832c90eb4.tex b/sail_latex_riscv/valz_set_mstatus_tw07f419963ff98d483c7b9ce832c90eb4.tex new file mode 100644 index 00000000..0b84051d --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_tw07f419963ff98d483c7b9ce832c90eb4.tex @@ -0,0 +1 @@ +_set_Mstatus_TW : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_uieb479c3c10676b772a02256f3db5428da.tex b/sail_latex_riscv/valz_set_mstatus_uieb479c3c10676b772a02256f3db5428da.tex new file mode 100644 index 00000000..ad13ec0b --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_uieb479c3c10676b772a02256f3db5428da.tex @@ -0,0 +1 @@ +_set_Mstatus_UIE : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_upie97f5fcc7e74b28a97eb44ae99226200f.tex b/sail_latex_riscv/valz_set_mstatus_upie97f5fcc7e74b28a97eb44ae99226200f.tex new file mode 100644 index 00000000..12163c9c --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_upie97f5fcc7e74b28a97eb44ae99226200f.tex @@ -0,0 +1 @@ +_set_Mstatus_UPIE : (register(Mstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mstatus_xs13adea89de69c7b934d405e2c5369191.tex b/sail_latex_riscv/valz_set_mstatus_xs13adea89de69c7b934d405e2c5369191.tex new file mode 100644 index 00000000..8174b8fd --- /dev/null +++ b/sail_latex_riscv/valz_set_mstatus_xs13adea89de69c7b934d405e2c5369191.tex @@ -0,0 +1 @@ +_set_Mstatus_XS : (register(Mstatus), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mtvec_base86e6903a9eebeb1822f298249988800a.tex b/sail_latex_riscv/valz_set_mtvec_base86e6903a9eebeb1822f298249988800a.tex new file mode 100644 index 00000000..15493ada --- /dev/null +++ b/sail_latex_riscv/valz_set_mtvec_base86e6903a9eebeb1822f298249988800a.tex @@ -0,0 +1 @@ +_set_Mtvec_Base : (register(Mtvec), bitvector(62, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mtvec_bitsbae28d0fb32e4a35886c4c0190acdeb8.tex b/sail_latex_riscv/valz_set_mtvec_bitsbae28d0fb32e4a35886c4c0190acdeb8.tex new file mode 100644 index 00000000..30e1b480 --- /dev/null +++ b/sail_latex_riscv/valz_set_mtvec_bitsbae28d0fb32e4a35886c4c0190acdeb8.tex @@ -0,0 +1 @@ +_set_Mtvec_bits : (register(Mtvec), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_mtvec_mode83a05e7666364d3e4e87f1aedc208023.tex b/sail_latex_riscv/valz_set_mtvec_mode83a05e7666364d3e4e87f1aedc208023.tex new file mode 100644 index 00000000..f882c2d9 --- /dev/null +++ b/sail_latex_riscv/valz_set_mtvec_mode83a05e7666364d3e4e87f1aedc208023.tex @@ -0,0 +1 @@ +_set_Mtvec_Mode : (register(Mtvec), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pmpcfg_ent_a9693fd9f223e2207b066d9000b8199c1.tex b/sail_latex_riscv/valz_set_pmpcfg_ent_a9693fd9f223e2207b066d9000b8199c1.tex new file mode 100644 index 00000000..639eb1c4 --- /dev/null +++ b/sail_latex_riscv/valz_set_pmpcfg_ent_a9693fd9f223e2207b066d9000b8199c1.tex @@ -0,0 +1 @@ +_set_Pmpcfg_ent_A : (register(Pmpcfg_ent), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pmpcfg_ent_bits594540475f6835a77bc55f1853c82f34.tex b/sail_latex_riscv/valz_set_pmpcfg_ent_bits594540475f6835a77bc55f1853c82f34.tex new file mode 100644 index 00000000..05e43ab5 --- /dev/null +++ b/sail_latex_riscv/valz_set_pmpcfg_ent_bits594540475f6835a77bc55f1853c82f34.tex @@ -0,0 +1 @@ +_set_Pmpcfg_ent_bits : (register(Pmpcfg_ent), bitvector(8, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pmpcfg_ent_l3838182dc02b8ff73f27360aa88f7580.tex b/sail_latex_riscv/valz_set_pmpcfg_ent_l3838182dc02b8ff73f27360aa88f7580.tex new file mode 100644 index 00000000..3d0cea16 --- /dev/null +++ b/sail_latex_riscv/valz_set_pmpcfg_ent_l3838182dc02b8ff73f27360aa88f7580.tex @@ -0,0 +1 @@ +_set_Pmpcfg_ent_L : (register(Pmpcfg_ent), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pmpcfg_ent_re7495d5157c5145daf88a430c7faa2ea.tex b/sail_latex_riscv/valz_set_pmpcfg_ent_re7495d5157c5145daf88a430c7faa2ea.tex new file mode 100644 index 00000000..e1c938cb --- /dev/null +++ b/sail_latex_riscv/valz_set_pmpcfg_ent_re7495d5157c5145daf88a430c7faa2ea.tex @@ -0,0 +1 @@ +_set_Pmpcfg_ent_R : (register(Pmpcfg_ent), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pmpcfg_ent_wce1529faf12026bc7cc93760d4dd2183.tex b/sail_latex_riscv/valz_set_pmpcfg_ent_wce1529faf12026bc7cc93760d4dd2183.tex new file mode 100644 index 00000000..5a24a979 --- /dev/null +++ b/sail_latex_riscv/valz_set_pmpcfg_ent_wce1529faf12026bc7cc93760d4dd2183.tex @@ -0,0 +1 @@ +_set_Pmpcfg_ent_W : (register(Pmpcfg_ent), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pmpcfg_ent_x673f5396d42ee8881cf0e4a176b53225.tex b/sail_latex_riscv/valz_set_pmpcfg_ent_x673f5396d42ee8881cf0e4a176b53225.tex new file mode 100644 index 00000000..f58181ef --- /dev/null +++ b/sail_latex_riscv/valz_set_pmpcfg_ent_x673f5396d42ee8881cf0e4a176b53225.tex @@ -0,0 +1 @@ +_set_Pmpcfg_ent_X : (register(Pmpcfg_ent), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pte_bits_aac67ea7f6b10ab3673728f748f93c292.tex b/sail_latex_riscv/valz_set_pte_bits_aac67ea7f6b10ab3673728f748f93c292.tex new file mode 100644 index 00000000..9ae12ecf --- /dev/null +++ b/sail_latex_riscv/valz_set_pte_bits_aac67ea7f6b10ab3673728f748f93c292.tex @@ -0,0 +1 @@ +_set_PTE_Bits_A : (register(PTE_Bits), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pte_bits_bits6d0635987f7718a8a39cf3033064c503.tex b/sail_latex_riscv/valz_set_pte_bits_bits6d0635987f7718a8a39cf3033064c503.tex new file mode 100644 index 00000000..e1c3131b --- /dev/null +++ b/sail_latex_riscv/valz_set_pte_bits_bits6d0635987f7718a8a39cf3033064c503.tex @@ -0,0 +1 @@ +_set_PTE_Bits_bits : (register(PTE_Bits), bitvector(8, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pte_bits_d91bbe4815197f856eaded6975a2b164b.tex b/sail_latex_riscv/valz_set_pte_bits_d91bbe4815197f856eaded6975a2b164b.tex new file mode 100644 index 00000000..8d99800d --- /dev/null +++ b/sail_latex_riscv/valz_set_pte_bits_d91bbe4815197f856eaded6975a2b164b.tex @@ -0,0 +1 @@ +_set_PTE_Bits_D : (register(PTE_Bits), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pte_bits_g31ff87423c27525881946540eb3368f0.tex b/sail_latex_riscv/valz_set_pte_bits_g31ff87423c27525881946540eb3368f0.tex new file mode 100644 index 00000000..f77944b0 --- /dev/null +++ b/sail_latex_riscv/valz_set_pte_bits_g31ff87423c27525881946540eb3368f0.tex @@ -0,0 +1 @@ +_set_PTE_Bits_G : (register(PTE_Bits), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pte_bits_r7ddb8623ba4795fb0437583737d032bc.tex b/sail_latex_riscv/valz_set_pte_bits_r7ddb8623ba4795fb0437583737d032bc.tex new file mode 100644 index 00000000..6d40e205 --- /dev/null +++ b/sail_latex_riscv/valz_set_pte_bits_r7ddb8623ba4795fb0437583737d032bc.tex @@ -0,0 +1 @@ +_set_PTE_Bits_R : (register(PTE_Bits), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pte_bits_u7152ad61970d5f3617d43634186dfaf6.tex b/sail_latex_riscv/valz_set_pte_bits_u7152ad61970d5f3617d43634186dfaf6.tex new file mode 100644 index 00000000..913780a7 --- /dev/null +++ b/sail_latex_riscv/valz_set_pte_bits_u7152ad61970d5f3617d43634186dfaf6.tex @@ -0,0 +1 @@ +_set_PTE_Bits_U : (register(PTE_Bits), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pte_bits_ve9a7a4a2a11bf5683da07253607039cb.tex b/sail_latex_riscv/valz_set_pte_bits_ve9a7a4a2a11bf5683da07253607039cb.tex new file mode 100644 index 00000000..6ad7fd3c --- /dev/null +++ b/sail_latex_riscv/valz_set_pte_bits_ve9a7a4a2a11bf5683da07253607039cb.tex @@ -0,0 +1 @@ +_set_PTE_Bits_V : (register(PTE_Bits), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pte_bits_w6af9664f46a96e5953a99351ac9f2eec.tex b/sail_latex_riscv/valz_set_pte_bits_w6af9664f46a96e5953a99351ac9f2eec.tex new file mode 100644 index 00000000..69f5ea86 --- /dev/null +++ b/sail_latex_riscv/valz_set_pte_bits_w6af9664f46a96e5953a99351ac9f2eec.tex @@ -0,0 +1 @@ +_set_PTE_Bits_W : (register(PTE_Bits), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_pte_bits_xd8616f420b73ae2b89e310bf44d3a11a.tex b/sail_latex_riscv/valz_set_pte_bits_xd8616f420b73ae2b89e310bf44d3a11a.tex new file mode 100644 index 00000000..2a9ca451 --- /dev/null +++ b/sail_latex_riscv/valz_set_pte_bits_xd8616f420b73ae2b89e310bf44d3a11a.tex @@ -0,0 +1 @@ +_set_PTE_Bits_X : (register(PTE_Bits), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_satp32_asid1e472f8b9d87ee7ce4dc47786138f7af.tex b/sail_latex_riscv/valz_set_satp32_asid1e472f8b9d87ee7ce4dc47786138f7af.tex new file mode 100644 index 00000000..2719f5c2 --- /dev/null +++ b/sail_latex_riscv/valz_set_satp32_asid1e472f8b9d87ee7ce4dc47786138f7af.tex @@ -0,0 +1 @@ +_set_Satp32_Asid : (register(Satp32), bitvector(9, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_satp32_bits1d19cd20b80cea73ba6dc6c4919c83bd.tex b/sail_latex_riscv/valz_set_satp32_bits1d19cd20b80cea73ba6dc6c4919c83bd.tex new file mode 100644 index 00000000..db3147e8 --- /dev/null +++ b/sail_latex_riscv/valz_set_satp32_bits1d19cd20b80cea73ba6dc6c4919c83bd.tex @@ -0,0 +1 @@ +_set_Satp32_bits : (register(Satp32), bitvector(32, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_satp32_mode92a8ae476bd67a0a5ff16c383b2067ca.tex b/sail_latex_riscv/valz_set_satp32_mode92a8ae476bd67a0a5ff16c383b2067ca.tex new file mode 100644 index 00000000..3aad62af --- /dev/null +++ b/sail_latex_riscv/valz_set_satp32_mode92a8ae476bd67a0a5ff16c383b2067ca.tex @@ -0,0 +1 @@ +_set_Satp32_Mode : (register(Satp32), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_satp32_ppne026770b9c95405e7d420506a450e1f8.tex b/sail_latex_riscv/valz_set_satp32_ppne026770b9c95405e7d420506a450e1f8.tex new file mode 100644 index 00000000..0d6ef34d --- /dev/null +++ b/sail_latex_riscv/valz_set_satp32_ppne026770b9c95405e7d420506a450e1f8.tex @@ -0,0 +1 @@ +_set_Satp32_PPN : (register(Satp32), bitvector(22, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_satp64_asid2ddaf59d37788d7a3a27cef76891dfb8.tex b/sail_latex_riscv/valz_set_satp64_asid2ddaf59d37788d7a3a27cef76891dfb8.tex new file mode 100644 index 00000000..c3abac1b --- /dev/null +++ b/sail_latex_riscv/valz_set_satp64_asid2ddaf59d37788d7a3a27cef76891dfb8.tex @@ -0,0 +1 @@ +_set_Satp64_Asid : (register(Satp64), bitvector(16, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_satp64_bits1ef37f6f328908e0dfa046d4c516d3b7.tex b/sail_latex_riscv/valz_set_satp64_bits1ef37f6f328908e0dfa046d4c516d3b7.tex new file mode 100644 index 00000000..d4d8d30b --- /dev/null +++ b/sail_latex_riscv/valz_set_satp64_bits1ef37f6f328908e0dfa046d4c516d3b7.tex @@ -0,0 +1 @@ +_set_Satp64_bits : (register(Satp64), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_satp64_modedd62965c996bac9cb96fa44094dbf974.tex b/sail_latex_riscv/valz_set_satp64_modedd62965c996bac9cb96fa44094dbf974.tex new file mode 100644 index 00000000..903a1034 --- /dev/null +++ b/sail_latex_riscv/valz_set_satp64_modedd62965c996bac9cb96fa44094dbf974.tex @@ -0,0 +1 @@ +_set_Satp64_Mode : (register(Satp64), bitvector(4, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_satp64_ppn31d9614063b4541d68753b5e3090b133.tex b/sail_latex_riscv/valz_set_satp64_ppn31d9614063b4541d68753b5e3090b133.tex new file mode 100644 index 00000000..0ced692c --- /dev/null +++ b/sail_latex_riscv/valz_set_satp64_ppn31d9614063b4541d68753b5e3090b133.tex @@ -0,0 +1 @@ +_set_Satp64_PPN : (register(Satp64), bitvector(44, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sedeleg_bitsa2dbd669d717e67fa0750d9be9a12cee.tex b/sail_latex_riscv/valz_set_sedeleg_bitsa2dbd669d717e67fa0750d9be9a12cee.tex new file mode 100644 index 00000000..2c78d630 --- /dev/null +++ b/sail_latex_riscv/valz_set_sedeleg_bitsa2dbd669d717e67fa0750d9be9a12cee.tex @@ -0,0 +1 @@ +_set_Sedeleg_bits : (register(Sedeleg), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sedeleg_breakpoint2acb469996a4630099a56b45b59c2861.tex b/sail_latex_riscv/valz_set_sedeleg_breakpoint2acb469996a4630099a56b45b59c2861.tex new file mode 100644 index 00000000..79b260d3 --- /dev/null +++ b/sail_latex_riscv/valz_set_sedeleg_breakpoint2acb469996a4630099a56b45b59c2861.tex @@ -0,0 +1 @@ +_set_Sedeleg_Breakpoint : (register(Sedeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sedeleg_fetch_access_fault193173c32591a593674fa8e5c0a550fc.tex b/sail_latex_riscv/valz_set_sedeleg_fetch_access_fault193173c32591a593674fa8e5c0a550fc.tex new file mode 100644 index 00000000..761d6817 --- /dev/null +++ b/sail_latex_riscv/valz_set_sedeleg_fetch_access_fault193173c32591a593674fa8e5c0a550fc.tex @@ -0,0 +1 @@ +_set_Sedeleg_Fetch_Access_Fault : (register(Sedeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sedeleg_fetch_addr_aligna2669337b650c15def12b3457ae83d4f.tex b/sail_latex_riscv/valz_set_sedeleg_fetch_addr_aligna2669337b650c15def12b3457ae83d4f.tex new file mode 100644 index 00000000..d60c15ca --- /dev/null +++ b/sail_latex_riscv/valz_set_sedeleg_fetch_addr_aligna2669337b650c15def12b3457ae83d4f.tex @@ -0,0 +1 @@ +_set_Sedeleg_Fetch_Addr_Align : (register(Sedeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sedeleg_illegal_instrd248f17962068c21c567c4bc40790c19.tex b/sail_latex_riscv/valz_set_sedeleg_illegal_instrd248f17962068c21c567c4bc40790c19.tex new file mode 100644 index 00000000..e3f8ee60 --- /dev/null +++ b/sail_latex_riscv/valz_set_sedeleg_illegal_instrd248f17962068c21c567c4bc40790c19.tex @@ -0,0 +1 @@ +_set_Sedeleg_Illegal_Instr : (register(Sedeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sedeleg_load_access_fault3dcfaa698c0c375f65a901a1c187a93b.tex b/sail_latex_riscv/valz_set_sedeleg_load_access_fault3dcfaa698c0c375f65a901a1c187a93b.tex new file mode 100644 index 00000000..a9ac2d8d --- /dev/null +++ b/sail_latex_riscv/valz_set_sedeleg_load_access_fault3dcfaa698c0c375f65a901a1c187a93b.tex @@ -0,0 +1 @@ +_set_Sedeleg_Load_Access_Fault : (register(Sedeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sedeleg_load_addr_align3845e25f6585eadcab3b640d7c9d0c9a.tex b/sail_latex_riscv/valz_set_sedeleg_load_addr_align3845e25f6585eadcab3b640d7c9d0c9a.tex new file mode 100644 index 00000000..f4350f41 --- /dev/null +++ b/sail_latex_riscv/valz_set_sedeleg_load_addr_align3845e25f6585eadcab3b640d7c9d0c9a.tex @@ -0,0 +1 @@ +_set_Sedeleg_Load_Addr_Align : (register(Sedeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sedeleg_samo_access_fault9cc04f455b39e7c1866c125033bf2f03.tex b/sail_latex_riscv/valz_set_sedeleg_samo_access_fault9cc04f455b39e7c1866c125033bf2f03.tex new file mode 100644 index 00000000..41e331cd --- /dev/null +++ b/sail_latex_riscv/valz_set_sedeleg_samo_access_fault9cc04f455b39e7c1866c125033bf2f03.tex @@ -0,0 +1 @@ +_set_Sedeleg_SAMO_Access_Fault : (register(Sedeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sedeleg_samo_addr_align9567cfb032fb426d3c4292d506d6a9d2.tex b/sail_latex_riscv/valz_set_sedeleg_samo_addr_align9567cfb032fb426d3c4292d506d6a9d2.tex new file mode 100644 index 00000000..d8887c62 --- /dev/null +++ b/sail_latex_riscv/valz_set_sedeleg_samo_addr_align9567cfb032fb426d3c4292d506d6a9d2.tex @@ -0,0 +1 @@ +_set_Sedeleg_SAMO_Addr_Align : (register(Sedeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sedeleg_uenvcall80b0a54fdfebf30e056fa7c713788315.tex b/sail_latex_riscv/valz_set_sedeleg_uenvcall80b0a54fdfebf30e056fa7c713788315.tex new file mode 100644 index 00000000..f4c3d7f1 --- /dev/null +++ b/sail_latex_riscv/valz_set_sedeleg_uenvcall80b0a54fdfebf30e056fa7c713788315.tex @@ -0,0 +1 @@ +_set_Sedeleg_UEnvCall : (register(Sedeleg), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sinterrupts_bits11d675c3310ec7be4b053dce213f9e13.tex b/sail_latex_riscv/valz_set_sinterrupts_bits11d675c3310ec7be4b053dce213f9e13.tex new file mode 100644 index 00000000..d8683b3a --- /dev/null +++ b/sail_latex_riscv/valz_set_sinterrupts_bits11d675c3310ec7be4b053dce213f9e13.tex @@ -0,0 +1 @@ +_set_Sinterrupts_bits : (register(Sinterrupts), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sinterrupts_seid1a27b6ed01fc08d7ed92e7473ca0c67.tex b/sail_latex_riscv/valz_set_sinterrupts_seid1a27b6ed01fc08d7ed92e7473ca0c67.tex new file mode 100644 index 00000000..57b14706 --- /dev/null +++ b/sail_latex_riscv/valz_set_sinterrupts_seid1a27b6ed01fc08d7ed92e7473ca0c67.tex @@ -0,0 +1 @@ +_set_Sinterrupts_SEI : (register(Sinterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sinterrupts_ssi34d088bb8c03bd9774e94278832e9c78.tex b/sail_latex_riscv/valz_set_sinterrupts_ssi34d088bb8c03bd9774e94278832e9c78.tex new file mode 100644 index 00000000..cb8ba5fe --- /dev/null +++ b/sail_latex_riscv/valz_set_sinterrupts_ssi34d088bb8c03bd9774e94278832e9c78.tex @@ -0,0 +1 @@ +_set_Sinterrupts_SSI : (register(Sinterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sinterrupts_sti6ee1684f0baef5e2b4c1b77cfad5548a.tex b/sail_latex_riscv/valz_set_sinterrupts_sti6ee1684f0baef5e2b4c1b77cfad5548a.tex new file mode 100644 index 00000000..39c354f6 --- /dev/null +++ b/sail_latex_riscv/valz_set_sinterrupts_sti6ee1684f0baef5e2b4c1b77cfad5548a.tex @@ -0,0 +1 @@ +_set_Sinterrupts_STI : (register(Sinterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sinterrupts_ueid6db53e4645f60442d748c9717159555.tex b/sail_latex_riscv/valz_set_sinterrupts_ueid6db53e4645f60442d748c9717159555.tex new file mode 100644 index 00000000..bfe80a19 --- /dev/null +++ b/sail_latex_riscv/valz_set_sinterrupts_ueid6db53e4645f60442d748c9717159555.tex @@ -0,0 +1 @@ +_set_Sinterrupts_UEI : (register(Sinterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sinterrupts_usi4837f15564ed5aede9a0c1c6ed9d89c6.tex b/sail_latex_riscv/valz_set_sinterrupts_usi4837f15564ed5aede9a0c1c6ed9d89c6.tex new file mode 100644 index 00000000..12c24647 --- /dev/null +++ b/sail_latex_riscv/valz_set_sinterrupts_usi4837f15564ed5aede9a0c1c6ed9d89c6.tex @@ -0,0 +1 @@ +_set_Sinterrupts_USI : (register(Sinterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sinterrupts_utid6108a193d51614aeb91d29cae7b52d4.tex b/sail_latex_riscv/valz_set_sinterrupts_utid6108a193d51614aeb91d29cae7b52d4.tex new file mode 100644 index 00000000..aabe1422 --- /dev/null +++ b/sail_latex_riscv/valz_set_sinterrupts_utid6108a193d51614aeb91d29cae7b52d4.tex @@ -0,0 +1 @@ +_set_Sinterrupts_UTI : (register(Sinterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sstatus_bitsa6c8fba93c0c18f7fc69cd591748cdfa.tex b/sail_latex_riscv/valz_set_sstatus_bitsa6c8fba93c0c18f7fc69cd591748cdfa.tex new file mode 100644 index 00000000..e5f86bd2 --- /dev/null +++ b/sail_latex_riscv/valz_set_sstatus_bitsa6c8fba93c0c18f7fc69cd591748cdfa.tex @@ -0,0 +1 @@ +_set_Sstatus_bits : (register(Sstatus), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sstatus_fse0f398b51eea363e05016843c2c595a4.tex b/sail_latex_riscv/valz_set_sstatus_fse0f398b51eea363e05016843c2c595a4.tex new file mode 100644 index 00000000..10045c71 --- /dev/null +++ b/sail_latex_riscv/valz_set_sstatus_fse0f398b51eea363e05016843c2c595a4.tex @@ -0,0 +1 @@ +_set_Sstatus_FS : (register(Sstatus), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sstatus_mxra2eba57c040b3e2ec7adb22d3d1de868.tex b/sail_latex_riscv/valz_set_sstatus_mxra2eba57c040b3e2ec7adb22d3d1de868.tex new file mode 100644 index 00000000..7207c595 --- /dev/null +++ b/sail_latex_riscv/valz_set_sstatus_mxra2eba57c040b3e2ec7adb22d3d1de868.tex @@ -0,0 +1 @@ +_set_Sstatus_MXR : (register(Sstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sstatus_sdd76fee105151cc55a95224ff72515795.tex b/sail_latex_riscv/valz_set_sstatus_sdd76fee105151cc55a95224ff72515795.tex new file mode 100644 index 00000000..3d2983a9 --- /dev/null +++ b/sail_latex_riscv/valz_set_sstatus_sdd76fee105151cc55a95224ff72515795.tex @@ -0,0 +1 @@ +_set_Sstatus_SD : (register(Sstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sstatus_siead9f271cff4bf9d22da8464c4d1ca3b4.tex b/sail_latex_riscv/valz_set_sstatus_siead9f271cff4bf9d22da8464c4d1ca3b4.tex new file mode 100644 index 00000000..7c38cd47 --- /dev/null +++ b/sail_latex_riscv/valz_set_sstatus_siead9f271cff4bf9d22da8464c4d1ca3b4.tex @@ -0,0 +1 @@ +_set_Sstatus_SIE : (register(Sstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sstatus_spie739993a605bcb322c2dbdf0ca5ddd2bc.tex b/sail_latex_riscv/valz_set_sstatus_spie739993a605bcb322c2dbdf0ca5ddd2bc.tex new file mode 100644 index 00000000..999ae27a --- /dev/null +++ b/sail_latex_riscv/valz_set_sstatus_spie739993a605bcb322c2dbdf0ca5ddd2bc.tex @@ -0,0 +1 @@ +_set_Sstatus_SPIE : (register(Sstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sstatus_spp8d87600dabd1a0a5c7d063db6e618a28.tex b/sail_latex_riscv/valz_set_sstatus_spp8d87600dabd1a0a5c7d063db6e618a28.tex new file mode 100644 index 00000000..ec412d4d --- /dev/null +++ b/sail_latex_riscv/valz_set_sstatus_spp8d87600dabd1a0a5c7d063db6e618a28.tex @@ -0,0 +1 @@ +_set_Sstatus_SPP : (register(Sstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sstatus_sumd6e6c88b359702301526305ad3ae0775.tex b/sail_latex_riscv/valz_set_sstatus_sumd6e6c88b359702301526305ad3ae0775.tex new file mode 100644 index 00000000..99249a22 --- /dev/null +++ b/sail_latex_riscv/valz_set_sstatus_sumd6e6c88b359702301526305ad3ae0775.tex @@ -0,0 +1 @@ +_set_Sstatus_SUM : (register(Sstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sstatus_uie05848044f6bfa6902b92558093153733.tex b/sail_latex_riscv/valz_set_sstatus_uie05848044f6bfa6902b92558093153733.tex new file mode 100644 index 00000000..641be309 --- /dev/null +++ b/sail_latex_riscv/valz_set_sstatus_uie05848044f6bfa6902b92558093153733.tex @@ -0,0 +1 @@ +_set_Sstatus_UIE : (register(Sstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sstatus_upiec20707b779f0d69be936cc46a8acab83.tex b/sail_latex_riscv/valz_set_sstatus_upiec20707b779f0d69be936cc46a8acab83.tex new file mode 100644 index 00000000..abb87410 --- /dev/null +++ b/sail_latex_riscv/valz_set_sstatus_upiec20707b779f0d69be936cc46a8acab83.tex @@ -0,0 +1 @@ +_set_Sstatus_UPIE : (register(Sstatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sstatus_xs051efb5955770c941a701fd96e8879a7.tex b/sail_latex_riscv/valz_set_sstatus_xs051efb5955770c941a701fd96e8879a7.tex new file mode 100644 index 00000000..e8f23bda --- /dev/null +++ b/sail_latex_riscv/valz_set_sstatus_xs051efb5955770c941a701fd96e8879a7.tex @@ -0,0 +1 @@ +_set_Sstatus_XS : (register(Sstatus), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv32_paddr_bits7ac5072e9a9d0f202a9169b342d1027c.tex b/sail_latex_riscv/valz_set_sv32_paddr_bits7ac5072e9a9d0f202a9169b342d1027c.tex new file mode 100644 index 00000000..d10112eb --- /dev/null +++ b/sail_latex_riscv/valz_set_sv32_paddr_bits7ac5072e9a9d0f202a9169b342d1027c.tex @@ -0,0 +1 @@ +_set_SV32_Paddr_bits : (register(SV32_Paddr), bitvector(34, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv32_paddr_pgofsab302689c37e31253a4e6531b82c42ab.tex b/sail_latex_riscv/valz_set_sv32_paddr_pgofsab302689c37e31253a4e6531b82c42ab.tex new file mode 100644 index 00000000..f284066d --- /dev/null +++ b/sail_latex_riscv/valz_set_sv32_paddr_pgofsab302689c37e31253a4e6531b82c42ab.tex @@ -0,0 +1 @@ +_set_SV32_Paddr_PgOfs : (register(SV32_Paddr), bitvector(12, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv32_paddr_ppni94a2cc32ea73c50cb5cac893287046f5.tex b/sail_latex_riscv/valz_set_sv32_paddr_ppni94a2cc32ea73c50cb5cac893287046f5.tex new file mode 100644 index 00000000..ac567288 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv32_paddr_ppni94a2cc32ea73c50cb5cac893287046f5.tex @@ -0,0 +1 @@ +_set_SV32_Paddr_PPNi : (register(SV32_Paddr), bitvector(22, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv32_pte_bits4f565be9958b1f59ab14509c2773579f.tex b/sail_latex_riscv/valz_set_sv32_pte_bits4f565be9958b1f59ab14509c2773579f.tex new file mode 100644 index 00000000..f2732a87 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv32_pte_bits4f565be9958b1f59ab14509c2773579f.tex @@ -0,0 +1 @@ +_set_SV32_PTE_BITS : (register(SV32_PTE), bitvector(8, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv32_pte_bitsaf6e5291a5df8cafbd0f8c816eb211d7.tex b/sail_latex_riscv/valz_set_sv32_pte_bitsaf6e5291a5df8cafbd0f8c816eb211d7.tex new file mode 100644 index 00000000..374ac05c --- /dev/null +++ b/sail_latex_riscv/valz_set_sv32_pte_bitsaf6e5291a5df8cafbd0f8c816eb211d7.tex @@ -0,0 +1 @@ +_set_SV32_PTE_bits : (register(SV32_PTE), bitvector(32, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv32_pte_ppnifab6de1238f9a347277b22b09cad438b.tex b/sail_latex_riscv/valz_set_sv32_pte_ppnifab6de1238f9a347277b22b09cad438b.tex new file mode 100644 index 00000000..e6fa147f --- /dev/null +++ b/sail_latex_riscv/valz_set_sv32_pte_ppnifab6de1238f9a347277b22b09cad438b.tex @@ -0,0 +1 @@ +_set_SV32_PTE_PPNi : (register(SV32_PTE), bitvector(22, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv32_pte_rsw8ae54b55d6031c4f79807b3714efee6a.tex b/sail_latex_riscv/valz_set_sv32_pte_rsw8ae54b55d6031c4f79807b3714efee6a.tex new file mode 100644 index 00000000..13feae1f --- /dev/null +++ b/sail_latex_riscv/valz_set_sv32_pte_rsw8ae54b55d6031c4f79807b3714efee6a.tex @@ -0,0 +1 @@ +_set_SV32_PTE_RSW : (register(SV32_PTE), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv32_vaddr_bits598a6533ea70614d0d53c8cea8eced8e.tex b/sail_latex_riscv/valz_set_sv32_vaddr_bits598a6533ea70614d0d53c8cea8eced8e.tex new file mode 100644 index 00000000..cfd14d15 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv32_vaddr_bits598a6533ea70614d0d53c8cea8eced8e.tex @@ -0,0 +1 @@ +_set_SV32_Vaddr_bits : (register(SV32_Vaddr), bitvector(32, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv32_vaddr_pgofse1f36d8f721e1df38bd5c772d609bd45.tex b/sail_latex_riscv/valz_set_sv32_vaddr_pgofse1f36d8f721e1df38bd5c772d609bd45.tex new file mode 100644 index 00000000..aef9fc8b --- /dev/null +++ b/sail_latex_riscv/valz_set_sv32_vaddr_pgofse1f36d8f721e1df38bd5c772d609bd45.tex @@ -0,0 +1 @@ +_set_SV32_Vaddr_PgOfs : (register(SV32_Vaddr), bitvector(12, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv32_vaddr_vpnib8665127c6a283f2aacb5e3825422f5f.tex b/sail_latex_riscv/valz_set_sv32_vaddr_vpnib8665127c6a283f2aacb5e3825422f5f.tex new file mode 100644 index 00000000..b5f2f20f --- /dev/null +++ b/sail_latex_riscv/valz_set_sv32_vaddr_vpnib8665127c6a283f2aacb5e3825422f5f.tex @@ -0,0 +1 @@ +_set_SV32_Vaddr_VPNi : (register(SV32_Vaddr), bitvector(20, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv39_paddr_bits3ec2652094be77813b00186e0c009ce4.tex b/sail_latex_riscv/valz_set_sv39_paddr_bits3ec2652094be77813b00186e0c009ce4.tex new file mode 100644 index 00000000..f7849d45 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv39_paddr_bits3ec2652094be77813b00186e0c009ce4.tex @@ -0,0 +1 @@ +_set_SV39_Paddr_bits : (register(SV39_Paddr), bitvector(56, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv39_paddr_pgofscbde8c5af7576e92ba5fca9143abbb66.tex b/sail_latex_riscv/valz_set_sv39_paddr_pgofscbde8c5af7576e92ba5fca9143abbb66.tex new file mode 100644 index 00000000..a1b285b0 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv39_paddr_pgofscbde8c5af7576e92ba5fca9143abbb66.tex @@ -0,0 +1 @@ +_set_SV39_Paddr_PgOfs : (register(SV39_Paddr), bitvector(12, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv39_paddr_ppni179def635ee83e4cac60b403fcd2e376.tex b/sail_latex_riscv/valz_set_sv39_paddr_ppni179def635ee83e4cac60b403fcd2e376.tex new file mode 100644 index 00000000..a38985f3 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv39_paddr_ppni179def635ee83e4cac60b403fcd2e376.tex @@ -0,0 +1 @@ +_set_SV39_Paddr_PPNi : (register(SV39_Paddr), bitvector(44, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv39_pte_bitsde1d8d06cbfb62b5b9924a167cdc23ec.tex b/sail_latex_riscv/valz_set_sv39_pte_bitsde1d8d06cbfb62b5b9924a167cdc23ec.tex new file mode 100644 index 00000000..95139147 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv39_pte_bitsde1d8d06cbfb62b5b9924a167cdc23ec.tex @@ -0,0 +1 @@ +_set_SV39_PTE_bits : (register(SV39_PTE), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv39_pte_bitse9589b312fc9f713a1d54dadb5f0e45d.tex b/sail_latex_riscv/valz_set_sv39_pte_bitse9589b312fc9f713a1d54dadb5f0e45d.tex new file mode 100644 index 00000000..08b0f56e --- /dev/null +++ b/sail_latex_riscv/valz_set_sv39_pte_bitse9589b312fc9f713a1d54dadb5f0e45d.tex @@ -0,0 +1 @@ +_set_SV39_PTE_BITS : (register(SV39_PTE), bitvector(8, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv39_pte_ext579db3d4726a0e68687d2bef859f8658.tex b/sail_latex_riscv/valz_set_sv39_pte_ext579db3d4726a0e68687d2bef859f8658.tex new file mode 100644 index 00000000..4ebc861c --- /dev/null +++ b/sail_latex_riscv/valz_set_sv39_pte_ext579db3d4726a0e68687d2bef859f8658.tex @@ -0,0 +1 @@ +_set_SV39_PTE_Ext : (register(SV39_PTE), bitvector(10, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv39_pte_ppnif74fb7c03da31075e81899e241f18909.tex b/sail_latex_riscv/valz_set_sv39_pte_ppnif74fb7c03da31075e81899e241f18909.tex new file mode 100644 index 00000000..37d9d471 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv39_pte_ppnif74fb7c03da31075e81899e241f18909.tex @@ -0,0 +1 @@ +_set_SV39_PTE_PPNi : (register(SV39_PTE), bitvector(44, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv39_pte_rsw9dcf0d2943fb66aef30725a715b1c011.tex b/sail_latex_riscv/valz_set_sv39_pte_rsw9dcf0d2943fb66aef30725a715b1c011.tex new file mode 100644 index 00000000..33f5d101 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv39_pte_rsw9dcf0d2943fb66aef30725a715b1c011.tex @@ -0,0 +1 @@ +_set_SV39_PTE_RSW : (register(SV39_PTE), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv39_vaddr_bits9dda733adeb14d86c90ae7719235d0bc.tex b/sail_latex_riscv/valz_set_sv39_vaddr_bits9dda733adeb14d86c90ae7719235d0bc.tex new file mode 100644 index 00000000..20046bf1 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv39_vaddr_bits9dda733adeb14d86c90ae7719235d0bc.tex @@ -0,0 +1 @@ +_set_SV39_Vaddr_bits : (register(SV39_Vaddr), bitvector(39, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv39_vaddr_pgofs10da37447f07e7766bd99c3f4712450e.tex b/sail_latex_riscv/valz_set_sv39_vaddr_pgofs10da37447f07e7766bd99c3f4712450e.tex new file mode 100644 index 00000000..1af57a1f --- /dev/null +++ b/sail_latex_riscv/valz_set_sv39_vaddr_pgofs10da37447f07e7766bd99c3f4712450e.tex @@ -0,0 +1 @@ +_set_SV39_Vaddr_PgOfs : (register(SV39_Vaddr), bitvector(12, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv39_vaddr_vpni862fded28960b086e268044e94d900bd.tex b/sail_latex_riscv/valz_set_sv39_vaddr_vpni862fded28960b086e268044e94d900bd.tex new file mode 100644 index 00000000..374fc111 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv39_vaddr_vpni862fded28960b086e268044e94d900bd.tex @@ -0,0 +1 @@ +_set_SV39_Vaddr_VPNi : (register(SV39_Vaddr), bitvector(27, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv48_paddr_bits50513db01891b630792f1d6a843c784b.tex b/sail_latex_riscv/valz_set_sv48_paddr_bits50513db01891b630792f1d6a843c784b.tex new file mode 100644 index 00000000..4c06b6ec --- /dev/null +++ b/sail_latex_riscv/valz_set_sv48_paddr_bits50513db01891b630792f1d6a843c784b.tex @@ -0,0 +1 @@ +_set_SV48_Paddr_bits : (register(SV48_Paddr), bitvector(56, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv48_paddr_pgofs562f79909d47d2b0eba8ebce320e03c4.tex b/sail_latex_riscv/valz_set_sv48_paddr_pgofs562f79909d47d2b0eba8ebce320e03c4.tex new file mode 100644 index 00000000..ed8ff7da --- /dev/null +++ b/sail_latex_riscv/valz_set_sv48_paddr_pgofs562f79909d47d2b0eba8ebce320e03c4.tex @@ -0,0 +1 @@ +_set_SV48_Paddr_PgOfs : (register(SV48_Paddr), bitvector(12, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv48_paddr_ppni6d70c043fcdc253e5c9daadde935dc78.tex b/sail_latex_riscv/valz_set_sv48_paddr_ppni6d70c043fcdc253e5c9daadde935dc78.tex new file mode 100644 index 00000000..60c891c0 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv48_paddr_ppni6d70c043fcdc253e5c9daadde935dc78.tex @@ -0,0 +1 @@ +_set_SV48_Paddr_PPNi : (register(SV48_Paddr), bitvector(44, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv48_pte_bits0b444a773ec492c3163a73656822756d.tex b/sail_latex_riscv/valz_set_sv48_pte_bits0b444a773ec492c3163a73656822756d.tex new file mode 100644 index 00000000..b954fad3 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv48_pte_bits0b444a773ec492c3163a73656822756d.tex @@ -0,0 +1 @@ +_set_SV48_PTE_bits : (register(SV48_PTE), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv48_pte_bitsad0cc90eccc969a6500100c935bee630.tex b/sail_latex_riscv/valz_set_sv48_pte_bitsad0cc90eccc969a6500100c935bee630.tex new file mode 100644 index 00000000..a3ea96cb --- /dev/null +++ b/sail_latex_riscv/valz_set_sv48_pte_bitsad0cc90eccc969a6500100c935bee630.tex @@ -0,0 +1 @@ +_set_SV48_PTE_BITS : (register(SV48_PTE), bitvector(8, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv48_pte_ext6ca7bfb443ac18c8ef730a785a66e223.tex b/sail_latex_riscv/valz_set_sv48_pte_ext6ca7bfb443ac18c8ef730a785a66e223.tex new file mode 100644 index 00000000..19e4d519 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv48_pte_ext6ca7bfb443ac18c8ef730a785a66e223.tex @@ -0,0 +1 @@ +_set_SV48_PTE_Ext : (register(SV48_PTE), bitvector(10, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv48_pte_ppnif14b23da9aa27f230829cd1afd9a766b.tex b/sail_latex_riscv/valz_set_sv48_pte_ppnif14b23da9aa27f230829cd1afd9a766b.tex new file mode 100644 index 00000000..ccda6ce2 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv48_pte_ppnif14b23da9aa27f230829cd1afd9a766b.tex @@ -0,0 +1 @@ +_set_SV48_PTE_PPNi : (register(SV48_PTE), bitvector(44, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv48_pte_rswc91c2908d341bbe5216582c940bf7837.tex b/sail_latex_riscv/valz_set_sv48_pte_rswc91c2908d341bbe5216582c940bf7837.tex new file mode 100644 index 00000000..32fd8c49 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv48_pte_rswc91c2908d341bbe5216582c940bf7837.tex @@ -0,0 +1 @@ +_set_SV48_PTE_RSW : (register(SV48_PTE), bitvector(2, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv48_vaddr_bitsd37e2d8f1c88cf733caeb08edd844785.tex b/sail_latex_riscv/valz_set_sv48_vaddr_bitsd37e2d8f1c88cf733caeb08edd844785.tex new file mode 100644 index 00000000..7d998fa7 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv48_vaddr_bitsd37e2d8f1c88cf733caeb08edd844785.tex @@ -0,0 +1 @@ +_set_SV48_Vaddr_bits : (register(SV48_Vaddr), bitvector(48, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv48_vaddr_pgofsed661e13958cf27c80315e6cd60b8a36.tex b/sail_latex_riscv/valz_set_sv48_vaddr_pgofsed661e13958cf27c80315e6cd60b8a36.tex new file mode 100644 index 00000000..f1fedfa0 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv48_vaddr_pgofsed661e13958cf27c80315e6cd60b8a36.tex @@ -0,0 +1 @@ +_set_SV48_Vaddr_PgOfs : (register(SV48_Vaddr), bitvector(12, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_sv48_vaddr_vpni49c5d04a526f6722627d07f53e7f09dc.tex b/sail_latex_riscv/valz_set_sv48_vaddr_vpni49c5d04a526f6722627d07f53e7f09dc.tex new file mode 100644 index 00000000..d10472f8 --- /dev/null +++ b/sail_latex_riscv/valz_set_sv48_vaddr_vpni49c5d04a526f6722627d07f53e7f09dc.tex @@ -0,0 +1 @@ +_set_SV48_Vaddr_VPNi : (register(SV48_Vaddr), bitvector(27, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_uinterrupts_bits727060290947315f91798504a8e1220d.tex b/sail_latex_riscv/valz_set_uinterrupts_bits727060290947315f91798504a8e1220d.tex new file mode 100644 index 00000000..25d191be --- /dev/null +++ b/sail_latex_riscv/valz_set_uinterrupts_bits727060290947315f91798504a8e1220d.tex @@ -0,0 +1 @@ +_set_Uinterrupts_bits : (register(Uinterrupts), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_uinterrupts_uei6395a09166c9287c4cbab9ca7e87e0bd.tex b/sail_latex_riscv/valz_set_uinterrupts_uei6395a09166c9287c4cbab9ca7e87e0bd.tex new file mode 100644 index 00000000..9ecd738c --- /dev/null +++ b/sail_latex_riscv/valz_set_uinterrupts_uei6395a09166c9287c4cbab9ca7e87e0bd.tex @@ -0,0 +1 @@ +_set_Uinterrupts_UEI : (register(Uinterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_uinterrupts_usi8050a61e8750bb4582bb9dda39b65457.tex b/sail_latex_riscv/valz_set_uinterrupts_usi8050a61e8750bb4582bb9dda39b65457.tex new file mode 100644 index 00000000..2fc5961c --- /dev/null +++ b/sail_latex_riscv/valz_set_uinterrupts_usi8050a61e8750bb4582bb9dda39b65457.tex @@ -0,0 +1 @@ +_set_Uinterrupts_USI : (register(Uinterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_uinterrupts_uti74ee6b037b2bfa28007515ce9e1e9566.tex b/sail_latex_riscv/valz_set_uinterrupts_uti74ee6b037b2bfa28007515ce9e1e9566.tex new file mode 100644 index 00000000..b26edde0 --- /dev/null +++ b/sail_latex_riscv/valz_set_uinterrupts_uti74ee6b037b2bfa28007515ce9e1e9566.tex @@ -0,0 +1 @@ +_set_Uinterrupts_UTI : (register(Uinterrupts), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_ustatus_bits30b27147d374fd2bd7fadc954e833c3f.tex b/sail_latex_riscv/valz_set_ustatus_bits30b27147d374fd2bd7fadc954e833c3f.tex new file mode 100644 index 00000000..cf43ab79 --- /dev/null +++ b/sail_latex_riscv/valz_set_ustatus_bits30b27147d374fd2bd7fadc954e833c3f.tex @@ -0,0 +1 @@ +_set_Ustatus_bits : (register(Ustatus), bitvector(64, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_ustatus_uied66ad7f688ead51a86b377a82d67ff47.tex b/sail_latex_riscv/valz_set_ustatus_uied66ad7f688ead51a86b377a82d67ff47.tex new file mode 100644 index 00000000..04db700d --- /dev/null +++ b/sail_latex_riscv/valz_set_ustatus_uied66ad7f688ead51a86b377a82d67ff47.tex @@ -0,0 +1 @@ +_set_Ustatus_UIE : (register(Ustatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_set_ustatus_upie36655d5ae32856b4d8e9eefbf763af27.tex b/sail_latex_riscv/valz_set_ustatus_upie36655d5ae32856b4d8e9eefbf763af27.tex new file mode 100644 index 00000000..112a229f --- /dev/null +++ b/sail_latex_riscv/valz_set_ustatus_upie36655d5ae32856b4d8e9eefbf763af27.tex @@ -0,0 +1 @@ +_set_Ustatus_UPIE : (register(Ustatus), bitvector(1, dec)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valz_shl1b261f5995acb90d475c10ee0cdbc12ce.tex b/sail_latex_riscv/valz_shl1b261f5995acb90d475c10ee0cdbc12ce.tex new file mode 100644 index 00000000..0c0d1c19 --- /dev/null +++ b/sail_latex_riscv/valz_shl1b261f5995acb90d475c10ee0cdbc12ce.tex @@ -0,0 +1 @@ +_shl1 : forall ('n : Int), (0 <= 'n & 'n <= 3). (int(1), int('n)) -> {|1, 2, 4, 8|} \ No newline at end of file diff --git a/sail_latex_riscv/valz_shl32469ae968a52f81e1a28aeacf7e2d496b.tex b/sail_latex_riscv/valz_shl32469ae968a52f81e1a28aeacf7e2d496b.tex new file mode 100644 index 00000000..eab4d671 --- /dev/null +++ b/sail_latex_riscv/valz_shl32469ae968a52f81e1a28aeacf7e2d496b.tex @@ -0,0 +1 @@ +_shl32 : forall ('n : Int), 'n in {0, 1}. (int(32), int('n)) -> {|32, 64|} \ No newline at end of file diff --git a/sail_latex_riscv/valz_shl8e01c74b934d4c323501a597baa8e6f73.tex b/sail_latex_riscv/valz_shl8e01c74b934d4c323501a597baa8e6f73.tex new file mode 100644 index 00000000..1c3bf9d3 --- /dev/null +++ b/sail_latex_riscv/valz_shl8e01c74b934d4c323501a597baa8e6f73.tex @@ -0,0 +1 @@ +_shl8 : forall ('n : Int), (0 <= 'n & 'n <= 3). (int(8), int('n)) -> {|8, 16, 32, 64|} \ No newline at end of file diff --git a/sail_latex_riscv/valz_shl_int86f4e1bc3609625860bc16734d7f2614.tex b/sail_latex_riscv/valz_shl_int86f4e1bc3609625860bc16734d7f2614.tex new file mode 100644 index 00000000..840e98cf --- /dev/null +++ b/sail_latex_riscv/valz_shl_int86f4e1bc3609625860bc16734d7f2614.tex @@ -0,0 +1 @@ +_shl_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_riscv/valz_shr328ec48e4bcaebfdbf5c374b77ca7b535b.tex b/sail_latex_riscv/valz_shr328ec48e4bcaebfdbf5c374b77ca7b535b.tex new file mode 100644 index 00000000..ddf9ffa7 --- /dev/null +++ b/sail_latex_riscv/valz_shr328ec48e4bcaebfdbf5c374b77ca7b535b.tex @@ -0,0 +1 @@ +_shr32 : forall ('n : Int), (0 <= 'n & 'n <= 31). (int('n), int(1)) -> {'m, (0 <= 'm & 'm <= 15). int('m)} \ No newline at end of file diff --git a/sail_latex_riscv/valz_shr_int34025c843d841a08930cb64bf99a1693.tex b/sail_latex_riscv/valz_shr_int34025c843d841a08930cb64bf99a1693.tex new file mode 100644 index 00000000..ed0e407c --- /dev/null +++ b/sail_latex_riscv/valz_shr_int34025c843d841a08930cb64bf99a1693.tex @@ -0,0 +1 @@ +_shr_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_riscv/valz_tmod_int_positive6f0621d972182279e90a43c082e50c10.tex b/sail_latex_riscv/valz_tmod_int_positive6f0621d972182279e90a43c082e50c10.tex new file mode 100644 index 00000000..f187115a --- /dev/null +++ b/sail_latex_riscv/valz_tmod_int_positive6f0621d972182279e90a43c082e50c10.tex @@ -0,0 +1 @@ +_tmod_int_positive : forall ('n : Int), 'n >= 1. (int, int('n)) -> nat \ No newline at end of file diff --git a/sail_latex_riscv/valz_tmod_inta2984ba6dbfa10758476d9b3b7f62560.tex b/sail_latex_riscv/valz_tmod_inta2984ba6dbfa10758476d9b3b7f62560.tex new file mode 100644 index 00000000..c861b270 --- /dev/null +++ b/sail_latex_riscv/valz_tmod_inta2984ba6dbfa10758476d9b3b7f62560.tex @@ -0,0 +1 @@ +_tmod_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_ccsr_bitscab95b9f107541973f0ca10985835467.tex b/sail_latex_riscv/valz_update_ccsr_bitscab95b9f107541973f0ca10985835467.tex new file mode 100644 index 00000000..35212129 --- /dev/null +++ b/sail_latex_riscv/valz_update_ccsr_bitscab95b9f107541973f0ca10985835467.tex @@ -0,0 +1 @@ +_update_ccsr_bits : (ccsr, bitvector(64, dec)) -> ccsr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_ccsr_cap_idxcf97e2a26597f29b63eaa57befa11cea.tex b/sail_latex_riscv/valz_update_ccsr_cap_idxcf97e2a26597f29b63eaa57befa11cea.tex new file mode 100644 index 00000000..885d2e0e --- /dev/null +++ b/sail_latex_riscv/valz_update_ccsr_cap_idxcf97e2a26597f29b63eaa57befa11cea.tex @@ -0,0 +1 @@ +_update_ccsr_cap_idx : (ccsr, bitvector(6, dec)) -> ccsr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_ccsr_causecd8b7254c686be403e4e906a346f4642.tex b/sail_latex_riscv/valz_update_ccsr_causecd8b7254c686be403e4e906a346f4642.tex new file mode 100644 index 00000000..b6ccf1d3 --- /dev/null +++ b/sail_latex_riscv/valz_update_ccsr_causecd8b7254c686be403e4e906a346f4642.tex @@ -0,0 +1 @@ +_update_ccsr_cause : (ccsr, bitvector(5, dec)) -> ccsr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_ccsr_dad4c6c7e8973232b0249a9b870dab8b8.tex b/sail_latex_riscv/valz_update_ccsr_dad4c6c7e8973232b0249a9b870dab8b8.tex new file mode 100644 index 00000000..a4d7cca4 --- /dev/null +++ b/sail_latex_riscv/valz_update_ccsr_dad4c6c7e8973232b0249a9b870dab8b8.tex @@ -0,0 +1 @@ +_update_ccsr_d : (ccsr, bitvector(1, dec)) -> ccsr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_ccsr_e79adbf3ff342d3a9fc182dd2dd614be3.tex b/sail_latex_riscv/valz_update_ccsr_e79adbf3ff342d3a9fc182dd2dd614be3.tex new file mode 100644 index 00000000..7e823c15 --- /dev/null +++ b/sail_latex_riscv/valz_update_ccsr_e79adbf3ff342d3a9fc182dd2dd614be3.tex @@ -0,0 +1 @@ +_update_ccsr_e : (ccsr, bitvector(1, dec)) -> ccsr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_counteren_bitsab054ba63ba12cbce69135a6de8c9fad.tex b/sail_latex_riscv/valz_update_counteren_bitsab054ba63ba12cbce69135a6de8c9fad.tex new file mode 100644 index 00000000..863c04c7 --- /dev/null +++ b/sail_latex_riscv/valz_update_counteren_bitsab054ba63ba12cbce69135a6de8c9fad.tex @@ -0,0 +1 @@ +_update_Counteren_bits : (Counteren, bitvector(32, dec)) -> Counteren \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_counteren_cyb4f1e37eac32f7b9365943e5600beec9.tex b/sail_latex_riscv/valz_update_counteren_cyb4f1e37eac32f7b9365943e5600beec9.tex new file mode 100644 index 00000000..f7cf18e2 --- /dev/null +++ b/sail_latex_riscv/valz_update_counteren_cyb4f1e37eac32f7b9365943e5600beec9.tex @@ -0,0 +1 @@ +_update_Counteren_CY : (Counteren, bitvector(1, dec)) -> Counteren \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_counteren_hpma99adbaf80dd358f59495d6ca7717d3b.tex b/sail_latex_riscv/valz_update_counteren_hpma99adbaf80dd358f59495d6ca7717d3b.tex new file mode 100644 index 00000000..6b2f9caf --- /dev/null +++ b/sail_latex_riscv/valz_update_counteren_hpma99adbaf80dd358f59495d6ca7717d3b.tex @@ -0,0 +1 @@ +_update_Counteren_HPM : (Counteren, bitvector(29, dec)) -> Counteren \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_counteren_ir66176b4373b2eec827fbf9030a5406d0.tex b/sail_latex_riscv/valz_update_counteren_ir66176b4373b2eec827fbf9030a5406d0.tex new file mode 100644 index 00000000..eba04907 --- /dev/null +++ b/sail_latex_riscv/valz_update_counteren_ir66176b4373b2eec827fbf9030a5406d0.tex @@ -0,0 +1 @@ +_update_Counteren_IR : (Counteren, bitvector(1, dec)) -> Counteren \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_counteren_tmab580665d1404d6531c604b4b0827504.tex b/sail_latex_riscv/valz_update_counteren_tmab580665d1404d6531c604b4b0827504.tex new file mode 100644 index 00000000..1d16d253 --- /dev/null +++ b/sail_latex_riscv/valz_update_counteren_tmab580665d1404d6531c604b4b0827504.tex @@ -0,0 +1 @@ +_update_Counteren_TM : (Counteren, bitvector(1, dec)) -> Counteren \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_counterin_bits2487a90cdc32df9b1556a37b4d85fe52.tex b/sail_latex_riscv/valz_update_counterin_bits2487a90cdc32df9b1556a37b4d85fe52.tex new file mode 100644 index 00000000..ad951535 --- /dev/null +++ b/sail_latex_riscv/valz_update_counterin_bits2487a90cdc32df9b1556a37b4d85fe52.tex @@ -0,0 +1 @@ +_update_Counterin_bits : (Counterin, bitvector(32, dec)) -> Counterin \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_counterin_cy16506512e1a71f4a75459533622c36ab.tex b/sail_latex_riscv/valz_update_counterin_cy16506512e1a71f4a75459533622c36ab.tex new file mode 100644 index 00000000..e305c9ec --- /dev/null +++ b/sail_latex_riscv/valz_update_counterin_cy16506512e1a71f4a75459533622c36ab.tex @@ -0,0 +1 @@ +_update_Counterin_CY : (Counterin, bitvector(1, dec)) -> Counterin \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_counterin_ire83041be7a3bb70aa6f359785f4856ef.tex b/sail_latex_riscv/valz_update_counterin_ire83041be7a3bb70aa6f359785f4856ef.tex new file mode 100644 index 00000000..36e3a011 --- /dev/null +++ b/sail_latex_riscv/valz_update_counterin_ire83041be7a3bb70aa6f359785f4856ef.tex @@ -0,0 +1 @@ +_update_Counterin_IR : (Counterin, bitvector(1, dec)) -> Counterin \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_ext_pte_bits_bits5b635310b9455d491454822f0311285b.tex b/sail_latex_riscv/valz_update_ext_pte_bits_bits5b635310b9455d491454822f0311285b.tex new file mode 100644 index 00000000..cd166d7f --- /dev/null +++ b/sail_latex_riscv/valz_update_ext_pte_bits_bits5b635310b9455d491454822f0311285b.tex @@ -0,0 +1 @@ +_update_Ext_PTE_Bits_bits : (Ext_PTE_Bits, bitvector(10, dec)) -> Ext_PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_ext_pte_bits_capreadb593f0e07fbd2201e626b373cddf00e2.tex b/sail_latex_riscv/valz_update_ext_pte_bits_capreadb593f0e07fbd2201e626b373cddf00e2.tex new file mode 100644 index 00000000..753d1a20 --- /dev/null +++ b/sail_latex_riscv/valz_update_ext_pte_bits_capreadb593f0e07fbd2201e626b373cddf00e2.tex @@ -0,0 +1 @@ +_update_Ext_PTE_Bits_CapRead : (Ext_PTE_Bits, bitvector(1, dec)) -> Ext_PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_ext_pte_bits_capwritedcd59d2d59ab5341029d35f94ab8d27f.tex b/sail_latex_riscv/valz_update_ext_pte_bits_capwritedcd59d2d59ab5341029d35f94ab8d27f.tex new file mode 100644 index 00000000..7e692e9f --- /dev/null +++ b/sail_latex_riscv/valz_update_ext_pte_bits_capwritedcd59d2d59ab5341029d35f94ab8d27f.tex @@ -0,0 +1 @@ +_update_Ext_PTE_Bits_CapWrite : (Ext_PTE_Bits, bitvector(1, dec)) -> Ext_PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_fcsr_bitsd93593273c229b56f42c5419848120a5.tex b/sail_latex_riscv/valz_update_fcsr_bitsd93593273c229b56f42c5419848120a5.tex new file mode 100644 index 00000000..ec5b76ba --- /dev/null +++ b/sail_latex_riscv/valz_update_fcsr_bitsd93593273c229b56f42c5419848120a5.tex @@ -0,0 +1 @@ +_update_Fcsr_bits : (Fcsr, bitvector(32, dec)) -> Fcsr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_fcsr_fflags358f6ae3cab298c0e35ab7d81a328b5f.tex b/sail_latex_riscv/valz_update_fcsr_fflags358f6ae3cab298c0e35ab7d81a328b5f.tex new file mode 100644 index 00000000..d05fb45c --- /dev/null +++ b/sail_latex_riscv/valz_update_fcsr_fflags358f6ae3cab298c0e35ab7d81a328b5f.tex @@ -0,0 +1 @@ +_update_Fcsr_FFLAGS : (Fcsr, bitvector(5, dec)) -> Fcsr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_fcsr_frmdde96c8b780c41e6aa00deb4160779be.tex b/sail_latex_riscv/valz_update_fcsr_frmdde96c8b780c41e6aa00deb4160779be.tex new file mode 100644 index 00000000..12ac8053 --- /dev/null +++ b/sail_latex_riscv/valz_update_fcsr_frmdde96c8b780c41e6aa00deb4160779be.tex @@ -0,0 +1 @@ +_update_Fcsr_FRM : (Fcsr, bitvector(3, dec)) -> Fcsr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_htif_cmd_bitsf4016ddf8b504ce2ad50554db668de5e.tex b/sail_latex_riscv/valz_update_htif_cmd_bitsf4016ddf8b504ce2ad50554db668de5e.tex new file mode 100644 index 00000000..b67f0f53 --- /dev/null +++ b/sail_latex_riscv/valz_update_htif_cmd_bitsf4016ddf8b504ce2ad50554db668de5e.tex @@ -0,0 +1 @@ +_update_htif_cmd_bits : (htif_cmd, bitvector(64, dec)) -> htif_cmd \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_htif_cmd_cmd6ec3dd793a5d6eea4a6de9c247ff1ed7.tex b/sail_latex_riscv/valz_update_htif_cmd_cmd6ec3dd793a5d6eea4a6de9c247ff1ed7.tex new file mode 100644 index 00000000..5afaa240 --- /dev/null +++ b/sail_latex_riscv/valz_update_htif_cmd_cmd6ec3dd793a5d6eea4a6de9c247ff1ed7.tex @@ -0,0 +1 @@ +_update_htif_cmd_cmd : (htif_cmd, bitvector(8, dec)) -> htif_cmd \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_htif_cmd_device37d8d93e2615eb16246d9d3624507e12.tex b/sail_latex_riscv/valz_update_htif_cmd_device37d8d93e2615eb16246d9d3624507e12.tex new file mode 100644 index 00000000..0aa7327e --- /dev/null +++ b/sail_latex_riscv/valz_update_htif_cmd_device37d8d93e2615eb16246d9d3624507e12.tex @@ -0,0 +1 @@ +_update_htif_cmd_device : (htif_cmd, bitvector(8, dec)) -> htif_cmd \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_htif_cmd_payloadf8c76e11f35c2157b590a60e4678b1cc.tex b/sail_latex_riscv/valz_update_htif_cmd_payloadf8c76e11f35c2157b590a60e4678b1cc.tex new file mode 100644 index 00000000..b0060644 --- /dev/null +++ b/sail_latex_riscv/valz_update_htif_cmd_payloadf8c76e11f35c2157b590a60e4678b1cc.tex @@ -0,0 +1 @@ +_update_htif_cmd_payload : (htif_cmd, bitvector(48, dec)) -> htif_cmd \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mcause_bitsf7e305192beebf30554f7e43f12ae4ed.tex b/sail_latex_riscv/valz_update_mcause_bitsf7e305192beebf30554f7e43f12ae4ed.tex new file mode 100644 index 00000000..c8f4644f --- /dev/null +++ b/sail_latex_riscv/valz_update_mcause_bitsf7e305192beebf30554f7e43f12ae4ed.tex @@ -0,0 +1 @@ +_update_Mcause_bits : (Mcause, bitvector(64, dec)) -> Mcause \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mcause_cause36f08972c0051221257ac44d915e866d.tex b/sail_latex_riscv/valz_update_mcause_cause36f08972c0051221257ac44d915e866d.tex new file mode 100644 index 00000000..b16ba3b2 --- /dev/null +++ b/sail_latex_riscv/valz_update_mcause_cause36f08972c0051221257ac44d915e866d.tex @@ -0,0 +1 @@ +_update_Mcause_Cause : (Mcause, bitvector(63, dec)) -> Mcause \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mcause_isinterrupt642fe02b577ce4d39155750b612ad77c.tex b/sail_latex_riscv/valz_update_mcause_isinterrupt642fe02b577ce4d39155750b612ad77c.tex new file mode 100644 index 00000000..282c65b3 --- /dev/null +++ b/sail_latex_riscv/valz_update_mcause_isinterrupt642fe02b577ce4d39155750b612ad77c.tex @@ -0,0 +1 @@ +_update_Mcause_IsInterrupt : (Mcause, bitvector(1, dec)) -> Mcause \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_bitsf3dc3e6f3f131d1cc6e32b1c37c8cdde.tex b/sail_latex_riscv/valz_update_medeleg_bitsf3dc3e6f3f131d1cc6e32b1c37c8cdde.tex new file mode 100644 index 00000000..fb0a906e --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_bitsf3dc3e6f3f131d1cc6e32b1c37c8cdde.tex @@ -0,0 +1 @@ +_update_Medeleg_bits : (Medeleg, bitvector(64, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_breakpointbd84cf9145e5e18dc467f4a838f67957.tex b/sail_latex_riscv/valz_update_medeleg_breakpointbd84cf9145e5e18dc467f4a838f67957.tex new file mode 100644 index 00000000..7728cc95 --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_breakpointbd84cf9145e5e18dc467f4a838f67957.tex @@ -0,0 +1 @@ +_update_Medeleg_Breakpoint : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_fetch_access_fault31fef2dab7b4fcdd2b8d5a549f3df1ee.tex b/sail_latex_riscv/valz_update_medeleg_fetch_access_fault31fef2dab7b4fcdd2b8d5a549f3df1ee.tex new file mode 100644 index 00000000..03ffade8 --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_fetch_access_fault31fef2dab7b4fcdd2b8d5a549f3df1ee.tex @@ -0,0 +1 @@ +_update_Medeleg_Fetch_Access_Fault : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_fetch_addr_aligna193083f9170990caf0b815723cfe4f5.tex b/sail_latex_riscv/valz_update_medeleg_fetch_addr_aligna193083f9170990caf0b815723cfe4f5.tex new file mode 100644 index 00000000..2ac19ca0 --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_fetch_addr_aligna193083f9170990caf0b815723cfe4f5.tex @@ -0,0 +1 @@ +_update_Medeleg_Fetch_Addr_Align : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_fetch_page_faulta2bc84a2cd9018bb44ab5c81423ca187.tex b/sail_latex_riscv/valz_update_medeleg_fetch_page_faulta2bc84a2cd9018bb44ab5c81423ca187.tex new file mode 100644 index 00000000..cdfa4960 --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_fetch_page_faulta2bc84a2cd9018bb44ab5c81423ca187.tex @@ -0,0 +1 @@ +_update_Medeleg_Fetch_Page_Fault : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_illegal_instr1f275bdf5831e7748612e30e7fc1ce66.tex b/sail_latex_riscv/valz_update_medeleg_illegal_instr1f275bdf5831e7748612e30e7fc1ce66.tex new file mode 100644 index 00000000..47709a1c --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_illegal_instr1f275bdf5831e7748612e30e7fc1ce66.tex @@ -0,0 +1 @@ +_update_Medeleg_Illegal_Instr : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_load_access_faultf83e5fdaf6895717efc1bb0820a40bcc.tex b/sail_latex_riscv/valz_update_medeleg_load_access_faultf83e5fdaf6895717efc1bb0820a40bcc.tex new file mode 100644 index 00000000..b6324b4d --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_load_access_faultf83e5fdaf6895717efc1bb0820a40bcc.tex @@ -0,0 +1 @@ +_update_Medeleg_Load_Access_Fault : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_load_addr_alignae797c478ddd9ca50ad25f75c4177b59.tex b/sail_latex_riscv/valz_update_medeleg_load_addr_alignae797c478ddd9ca50ad25f75c4177b59.tex new file mode 100644 index 00000000..52082956 --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_load_addr_alignae797c478ddd9ca50ad25f75c4177b59.tex @@ -0,0 +1 @@ +_update_Medeleg_Load_Addr_Align : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_load_page_faultf06c6ed3cf5f5fb5c53b68b1755f26be.tex b/sail_latex_riscv/valz_update_medeleg_load_page_faultf06c6ed3cf5f5fb5c53b68b1755f26be.tex new file mode 100644 index 00000000..9d75ecb0 --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_load_page_faultf06c6ed3cf5f5fb5c53b68b1755f26be.tex @@ -0,0 +1 @@ +_update_Medeleg_Load_Page_Fault : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_menvcall2d8b71da00a8a28b5fb607a33f36612f.tex b/sail_latex_riscv/valz_update_medeleg_menvcall2d8b71da00a8a28b5fb607a33f36612f.tex new file mode 100644 index 00000000..295380b0 --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_menvcall2d8b71da00a8a28b5fb607a33f36612f.tex @@ -0,0 +1 @@ +_update_Medeleg_MEnvCall : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_samo_access_fault6974daf13df1fa6adbf6f8461fbb31e1.tex b/sail_latex_riscv/valz_update_medeleg_samo_access_fault6974daf13df1fa6adbf6f8461fbb31e1.tex new file mode 100644 index 00000000..d413e396 --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_samo_access_fault6974daf13df1fa6adbf6f8461fbb31e1.tex @@ -0,0 +1 @@ +_update_Medeleg_SAMO_Access_Fault : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_samo_addr_alignfbf844afddf59029f1bfa6e7730e572d.tex b/sail_latex_riscv/valz_update_medeleg_samo_addr_alignfbf844afddf59029f1bfa6e7730e572d.tex new file mode 100644 index 00000000..4cc4cf97 --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_samo_addr_alignfbf844afddf59029f1bfa6e7730e572d.tex @@ -0,0 +1 @@ +_update_Medeleg_SAMO_Addr_Align : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_samo_page_fault0f5a6e51d39c262ed16dd03fd0f6fd33.tex b/sail_latex_riscv/valz_update_medeleg_samo_page_fault0f5a6e51d39c262ed16dd03fd0f6fd33.tex new file mode 100644 index 00000000..aea5da6d --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_samo_page_fault0f5a6e51d39c262ed16dd03fd0f6fd33.tex @@ -0,0 +1 @@ +_update_Medeleg_SAMO_Page_Fault : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_senvcalld3587b88d31060a18775842e14fa2e28.tex b/sail_latex_riscv/valz_update_medeleg_senvcalld3587b88d31060a18775842e14fa2e28.tex new file mode 100644 index 00000000..10ce6a4c --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_senvcalld3587b88d31060a18775842e14fa2e28.tex @@ -0,0 +1 @@ +_update_Medeleg_SEnvCall : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_medeleg_uenvcalle92cde6b912da5ac5a47cd901345bbf9.tex b/sail_latex_riscv/valz_update_medeleg_uenvcalle92cde6b912da5ac5a47cd901345bbf9.tex new file mode 100644 index 00000000..38293884 --- /dev/null +++ b/sail_latex_riscv/valz_update_medeleg_uenvcalle92cde6b912da5ac5a47cd901345bbf9.tex @@ -0,0 +1 @@ +_update_Medeleg_UEnvCall : (Medeleg, bitvector(1, dec)) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_minterrupts_bitsd26668b9d73aea27c77c64039eabb63d.tex b/sail_latex_riscv/valz_update_minterrupts_bitsd26668b9d73aea27c77c64039eabb63d.tex new file mode 100644 index 00000000..7339c4e6 --- /dev/null +++ b/sail_latex_riscv/valz_update_minterrupts_bitsd26668b9d73aea27c77c64039eabb63d.tex @@ -0,0 +1 @@ +_update_Minterrupts_bits : (Minterrupts, bitvector(64, dec)) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_minterrupts_mei7bb6606e9f2d34ff0ba0b340c3513751.tex b/sail_latex_riscv/valz_update_minterrupts_mei7bb6606e9f2d34ff0ba0b340c3513751.tex new file mode 100644 index 00000000..ef5eef77 --- /dev/null +++ b/sail_latex_riscv/valz_update_minterrupts_mei7bb6606e9f2d34ff0ba0b340c3513751.tex @@ -0,0 +1 @@ +_update_Minterrupts_MEI : (Minterrupts, bitvector(1, dec)) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_minterrupts_msib1e866772ecd94b3b9b2c2c19feb2efc.tex b/sail_latex_riscv/valz_update_minterrupts_msib1e866772ecd94b3b9b2c2c19feb2efc.tex new file mode 100644 index 00000000..ef604cdc --- /dev/null +++ b/sail_latex_riscv/valz_update_minterrupts_msib1e866772ecd94b3b9b2c2c19feb2efc.tex @@ -0,0 +1 @@ +_update_Minterrupts_MSI : (Minterrupts, bitvector(1, dec)) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_minterrupts_mtic13c165f79b6b9773ec4f922e35a0ebd.tex b/sail_latex_riscv/valz_update_minterrupts_mtic13c165f79b6b9773ec4f922e35a0ebd.tex new file mode 100644 index 00000000..a22f0d5f --- /dev/null +++ b/sail_latex_riscv/valz_update_minterrupts_mtic13c165f79b6b9773ec4f922e35a0ebd.tex @@ -0,0 +1 @@ +_update_Minterrupts_MTI : (Minterrupts, bitvector(1, dec)) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_minterrupts_seib6916fd16d950d563a0f6ee65919136c.tex b/sail_latex_riscv/valz_update_minterrupts_seib6916fd16d950d563a0f6ee65919136c.tex new file mode 100644 index 00000000..c281686e --- /dev/null +++ b/sail_latex_riscv/valz_update_minterrupts_seib6916fd16d950d563a0f6ee65919136c.tex @@ -0,0 +1 @@ +_update_Minterrupts_SEI : (Minterrupts, bitvector(1, dec)) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_minterrupts_ssid8971c54b6d3c79de9fcf8f4e40c9bff.tex b/sail_latex_riscv/valz_update_minterrupts_ssid8971c54b6d3c79de9fcf8f4e40c9bff.tex new file mode 100644 index 00000000..6f36e3a4 --- /dev/null +++ b/sail_latex_riscv/valz_update_minterrupts_ssid8971c54b6d3c79de9fcf8f4e40c9bff.tex @@ -0,0 +1 @@ +_update_Minterrupts_SSI : (Minterrupts, bitvector(1, dec)) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_minterrupts_sti2b202ceb3ff9251d1c300cb53ff1c320.tex b/sail_latex_riscv/valz_update_minterrupts_sti2b202ceb3ff9251d1c300cb53ff1c320.tex new file mode 100644 index 00000000..097db858 --- /dev/null +++ b/sail_latex_riscv/valz_update_minterrupts_sti2b202ceb3ff9251d1c300cb53ff1c320.tex @@ -0,0 +1 @@ +_update_Minterrupts_STI : (Minterrupts, bitvector(1, dec)) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_minterrupts_uei72e8cc258b8ba110b65ac0940a170b2c.tex b/sail_latex_riscv/valz_update_minterrupts_uei72e8cc258b8ba110b65ac0940a170b2c.tex new file mode 100644 index 00000000..f8f8fa3e --- /dev/null +++ b/sail_latex_riscv/valz_update_minterrupts_uei72e8cc258b8ba110b65ac0940a170b2c.tex @@ -0,0 +1 @@ +_update_Minterrupts_UEI : (Minterrupts, bitvector(1, dec)) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_minterrupts_usi77886994f9fcf884ac05c59c57948f29.tex b/sail_latex_riscv/valz_update_minterrupts_usi77886994f9fcf884ac05c59c57948f29.tex new file mode 100644 index 00000000..29b783c2 --- /dev/null +++ b/sail_latex_riscv/valz_update_minterrupts_usi77886994f9fcf884ac05c59c57948f29.tex @@ -0,0 +1 @@ +_update_Minterrupts_USI : (Minterrupts, bitvector(1, dec)) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_minterrupts_utiadd0aa7121b36a517ccef2ac029d52ac.tex b/sail_latex_riscv/valz_update_minterrupts_utiadd0aa7121b36a517ccef2ac029d52ac.tex new file mode 100644 index 00000000..68d31dd1 --- /dev/null +++ b/sail_latex_riscv/valz_update_minterrupts_utiadd0aa7121b36a517ccef2ac029d52ac.tex @@ -0,0 +1 @@ +_update_Minterrupts_UTI : (Minterrupts, bitvector(1, dec)) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_a84a3cc4727896aed6b903b7b0d0caa83.tex b/sail_latex_riscv/valz_update_misa_a84a3cc4727896aed6b903b7b0d0caa83.tex new file mode 100644 index 00000000..4f8d9276 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_a84a3cc4727896aed6b903b7b0d0caa83.tex @@ -0,0 +1 @@ +_update_Misa_A : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_be5486da384cf1d6bc28f1b8e40ddf4ad.tex b/sail_latex_riscv/valz_update_misa_be5486da384cf1d6bc28f1b8e40ddf4ad.tex new file mode 100644 index 00000000..db970d40 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_be5486da384cf1d6bc28f1b8e40ddf4ad.tex @@ -0,0 +1 @@ +_update_Misa_B : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_bitsf571d9035c480faf7559a6b750d4b5d1.tex b/sail_latex_riscv/valz_update_misa_bitsf571d9035c480faf7559a6b750d4b5d1.tex new file mode 100644 index 00000000..a1c34460 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_bitsf571d9035c480faf7559a6b750d4b5d1.tex @@ -0,0 +1 @@ +_update_Misa_bits : (Misa, bitvector(64, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_c57e3c86e55b96ffdd3750d922289ff67.tex b/sail_latex_riscv/valz_update_misa_c57e3c86e55b96ffdd3750d922289ff67.tex new file mode 100644 index 00000000..c32be85f --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_c57e3c86e55b96ffdd3750d922289ff67.tex @@ -0,0 +1 @@ +_update_Misa_C : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_dae3fb84a048be1ee677eb585143660b4.tex b/sail_latex_riscv/valz_update_misa_dae3fb84a048be1ee677eb585143660b4.tex new file mode 100644 index 00000000..74b6a319 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_dae3fb84a048be1ee677eb585143660b4.tex @@ -0,0 +1 @@ +_update_Misa_D : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_e410ef028122a879e5db0523a611dbfe5.tex b/sail_latex_riscv/valz_update_misa_e410ef028122a879e5db0523a611dbfe5.tex new file mode 100644 index 00000000..6e0d5357 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_e410ef028122a879e5db0523a611dbfe5.tex @@ -0,0 +1 @@ +_update_Misa_E : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_fc88c899133c0200ee42f24494da679a4.tex b/sail_latex_riscv/valz_update_misa_fc88c899133c0200ee42f24494da679a4.tex new file mode 100644 index 00000000..e7f8e09e --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_fc88c899133c0200ee42f24494da679a4.tex @@ -0,0 +1 @@ +_update_Misa_F : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_g10edea49b1441082ca8d42e45e1480ab.tex b/sail_latex_riscv/valz_update_misa_g10edea49b1441082ca8d42e45e1480ab.tex new file mode 100644 index 00000000..abd325b7 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_g10edea49b1441082ca8d42e45e1480ab.tex @@ -0,0 +1 @@ +_update_Misa_G : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_h360ae205342d957f7a624e4c1114fe8f.tex b/sail_latex_riscv/valz_update_misa_h360ae205342d957f7a624e4c1114fe8f.tex new file mode 100644 index 00000000..f81671f4 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_h360ae205342d957f7a624e4c1114fe8f.tex @@ -0,0 +1 @@ +_update_Misa_H : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_i139fa4ff8a9c72a06d7ffebdda92436a.tex b/sail_latex_riscv/valz_update_misa_i139fa4ff8a9c72a06d7ffebdda92436a.tex new file mode 100644 index 00000000..3f55121a --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_i139fa4ff8a9c72a06d7ffebdda92436a.tex @@ -0,0 +1 @@ +_update_Misa_I : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_j103955d7d1e9e399dfbb839d275455e0.tex b/sail_latex_riscv/valz_update_misa_j103955d7d1e9e399dfbb839d275455e0.tex new file mode 100644 index 00000000..3852302d --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_j103955d7d1e9e399dfbb839d275455e0.tex @@ -0,0 +1 @@ +_update_Misa_J : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_kc4683fd490bb981aba37613fc8cdcb37.tex b/sail_latex_riscv/valz_update_misa_kc4683fd490bb981aba37613fc8cdcb37.tex new file mode 100644 index 00000000..7618eb6f --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_kc4683fd490bb981aba37613fc8cdcb37.tex @@ -0,0 +1 @@ +_update_Misa_K : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_l26aa92a8b1cde2502fe1736a8838b22e.tex b/sail_latex_riscv/valz_update_misa_l26aa92a8b1cde2502fe1736a8838b22e.tex new file mode 100644 index 00000000..48d34ee7 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_l26aa92a8b1cde2502fe1736a8838b22e.tex @@ -0,0 +1 @@ +_update_Misa_L : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_m698989b85ca48a2f975a5588f3dc7491.tex b/sail_latex_riscv/valz_update_misa_m698989b85ca48a2f975a5588f3dc7491.tex new file mode 100644 index 00000000..f9e6a0af --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_m698989b85ca48a2f975a5588f3dc7491.tex @@ -0,0 +1 @@ +_update_Misa_M : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_mxla1af4e187cbc1f82dd5ef946cabac371.tex b/sail_latex_riscv/valz_update_misa_mxla1af4e187cbc1f82dd5ef946cabac371.tex new file mode 100644 index 00000000..46c34c42 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_mxla1af4e187cbc1f82dd5ef946cabac371.tex @@ -0,0 +1 @@ +_update_Misa_MXL : (Misa, bitvector(2, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_n83ee893338b4bd792d81b5cf59f2ebce.tex b/sail_latex_riscv/valz_update_misa_n83ee893338b4bd792d81b5cf59f2ebce.tex new file mode 100644 index 00000000..f440fed8 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_n83ee893338b4bd792d81b5cf59f2ebce.tex @@ -0,0 +1 @@ +_update_Misa_N : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_obfc0e4a05dbc52b81817844c67df04f7.tex b/sail_latex_riscv/valz_update_misa_obfc0e4a05dbc52b81817844c67df04f7.tex new file mode 100644 index 00000000..f736f74a --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_obfc0e4a05dbc52b81817844c67df04f7.tex @@ -0,0 +1 @@ +_update_Misa_O : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_pc6c8bc56b2633630ff91deb372f972a7.tex b/sail_latex_riscv/valz_update_misa_pc6c8bc56b2633630ff91deb372f972a7.tex new file mode 100644 index 00000000..8ee32485 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_pc6c8bc56b2633630ff91deb372f972a7.tex @@ -0,0 +1 @@ +_update_Misa_P : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_q17b883fc2058f678be34555bf03acf4e.tex b/sail_latex_riscv/valz_update_misa_q17b883fc2058f678be34555bf03acf4e.tex new file mode 100644 index 00000000..808d5258 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_q17b883fc2058f678be34555bf03acf4e.tex @@ -0,0 +1 @@ +_update_Misa_Q : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_r1f6eba10007c144d1b33e8eff2959c17.tex b/sail_latex_riscv/valz_update_misa_r1f6eba10007c144d1b33e8eff2959c17.tex new file mode 100644 index 00000000..b0c0ad28 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_r1f6eba10007c144d1b33e8eff2959c17.tex @@ -0,0 +1 @@ +_update_Misa_R : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_sa29e6cb2dba70d986fb8ff30487dfbad.tex b/sail_latex_riscv/valz_update_misa_sa29e6cb2dba70d986fb8ff30487dfbad.tex new file mode 100644 index 00000000..f8ec4da0 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_sa29e6cb2dba70d986fb8ff30487dfbad.tex @@ -0,0 +1 @@ +_update_Misa_S : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_tab0b967322f8b3d8c5d8c510963c8722.tex b/sail_latex_riscv/valz_update_misa_tab0b967322f8b3d8c5d8c510963c8722.tex new file mode 100644 index 00000000..cca94384 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_tab0b967322f8b3d8c5d8c510963c8722.tex @@ -0,0 +1 @@ +_update_Misa_T : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_uac3943ed1944a21d61ef4550883e07f7.tex b/sail_latex_riscv/valz_update_misa_uac3943ed1944a21d61ef4550883e07f7.tex new file mode 100644 index 00000000..53d4af24 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_uac3943ed1944a21d61ef4550883e07f7.tex @@ -0,0 +1 @@ +_update_Misa_U : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_v1a8b5a29274e9567bae2f9671be4372a.tex b/sail_latex_riscv/valz_update_misa_v1a8b5a29274e9567bae2f9671be4372a.tex new file mode 100644 index 00000000..3382b4b4 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_v1a8b5a29274e9567bae2f9671be4372a.tex @@ -0,0 +1 @@ +_update_Misa_V : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_wd53860d44fba8bd03071c9b2edd62e86.tex b/sail_latex_riscv/valz_update_misa_wd53860d44fba8bd03071c9b2edd62e86.tex new file mode 100644 index 00000000..eb9e0137 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_wd53860d44fba8bd03071c9b2edd62e86.tex @@ -0,0 +1 @@ +_update_Misa_W : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_x51e71056e58398948e16168b5c3c2df9.tex b/sail_latex_riscv/valz_update_misa_x51e71056e58398948e16168b5c3c2df9.tex new file mode 100644 index 00000000..b32901e3 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_x51e71056e58398948e16168b5c3c2df9.tex @@ -0,0 +1 @@ +_update_Misa_X : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_y44689f65180da16f003ee1c86f6b157e.tex b/sail_latex_riscv/valz_update_misa_y44689f65180da16f003ee1c86f6b157e.tex new file mode 100644 index 00000000..6aaca6ee --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_y44689f65180da16f003ee1c86f6b157e.tex @@ -0,0 +1 @@ +_update_Misa_Y : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_misa_z801b78039b962c298e7fc5710e8ae3c4.tex b/sail_latex_riscv/valz_update_misa_z801b78039b962c298e7fc5710e8ae3c4.tex new file mode 100644 index 00000000..eb676731 --- /dev/null +++ b/sail_latex_riscv/valz_update_misa_z801b78039b962c298e7fc5710e8ae3c4.tex @@ -0,0 +1 @@ +_update_Misa_Z : (Misa, bitvector(1, dec)) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_bits62d247fffd2b228018ee801927d13b83.tex b/sail_latex_riscv/valz_update_mstatus_bits62d247fffd2b228018ee801927d13b83.tex new file mode 100644 index 00000000..71f6af7a --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_bits62d247fffd2b228018ee801927d13b83.tex @@ -0,0 +1 @@ +_update_Mstatus_bits : (Mstatus, bitvector(64, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_fsf06a4782f53e6ed8e2818ec43a049e21.tex b/sail_latex_riscv/valz_update_mstatus_fsf06a4782f53e6ed8e2818ec43a049e21.tex new file mode 100644 index 00000000..0919bb96 --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_fsf06a4782f53e6ed8e2818ec43a049e21.tex @@ -0,0 +1 @@ +_update_Mstatus_FS : (Mstatus, bitvector(2, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_mie80faf2146d01111ce6c4739dfadf9c5a.tex b/sail_latex_riscv/valz_update_mstatus_mie80faf2146d01111ce6c4739dfadf9c5a.tex new file mode 100644 index 00000000..ba4fde66 --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_mie80faf2146d01111ce6c4739dfadf9c5a.tex @@ -0,0 +1 @@ +_update_Mstatus_MIE : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_mpie66bbd7d75ad543a33368f099d66c2ad3.tex b/sail_latex_riscv/valz_update_mstatus_mpie66bbd7d75ad543a33368f099d66c2ad3.tex new file mode 100644 index 00000000..95a6c879 --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_mpie66bbd7d75ad543a33368f099d66c2ad3.tex @@ -0,0 +1 @@ +_update_Mstatus_MPIE : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_mpp0dfb32efcb28c9f2f9f70f8b7fc4edeb.tex b/sail_latex_riscv/valz_update_mstatus_mpp0dfb32efcb28c9f2f9f70f8b7fc4edeb.tex new file mode 100644 index 00000000..ebf851dd --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_mpp0dfb32efcb28c9f2f9f70f8b7fc4edeb.tex @@ -0,0 +1 @@ +_update_Mstatus_MPP : (Mstatus, bitvector(2, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_mprv5d1e4d26fc69487fc2e371466a2aefda.tex b/sail_latex_riscv/valz_update_mstatus_mprv5d1e4d26fc69487fc2e371466a2aefda.tex new file mode 100644 index 00000000..c5ea1a5f --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_mprv5d1e4d26fc69487fc2e371466a2aefda.tex @@ -0,0 +1 @@ +_update_Mstatus_MPRV : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_mxr86db170c1ee7edaf7ee350f188d44e71.tex b/sail_latex_riscv/valz_update_mstatus_mxr86db170c1ee7edaf7ee350f188d44e71.tex new file mode 100644 index 00000000..90c887fb --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_mxr86db170c1ee7edaf7ee350f188d44e71.tex @@ -0,0 +1 @@ +_update_Mstatus_MXR : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_sda4daaeb7cf3d3804c84f8f3adc875435.tex b/sail_latex_riscv/valz_update_mstatus_sda4daaeb7cf3d3804c84f8f3adc875435.tex new file mode 100644 index 00000000..7b445167 --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_sda4daaeb7cf3d3804c84f8f3adc875435.tex @@ -0,0 +1 @@ +_update_Mstatus_SD : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_sie59e9df0f2de34ad900e35dadcacc511b.tex b/sail_latex_riscv/valz_update_mstatus_sie59e9df0f2de34ad900e35dadcacc511b.tex new file mode 100644 index 00000000..4915af01 --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_sie59e9df0f2de34ad900e35dadcacc511b.tex @@ -0,0 +1 @@ +_update_Mstatus_SIE : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_spie6da04c490b761f34be7c9f4b5f75dd15.tex b/sail_latex_riscv/valz_update_mstatus_spie6da04c490b761f34be7c9f4b5f75dd15.tex new file mode 100644 index 00000000..631b093b --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_spie6da04c490b761f34be7c9f4b5f75dd15.tex @@ -0,0 +1 @@ +_update_Mstatus_SPIE : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_sppfa488292080686e2372e721aece0aca4.tex b/sail_latex_riscv/valz_update_mstatus_sppfa488292080686e2372e721aece0aca4.tex new file mode 100644 index 00000000..906ba051 --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_sppfa488292080686e2372e721aece0aca4.tex @@ -0,0 +1 @@ +_update_Mstatus_SPP : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_sumb7a60974e206e5c4db1cb80fdf3bcfe5.tex b/sail_latex_riscv/valz_update_mstatus_sumb7a60974e206e5c4db1cb80fdf3bcfe5.tex new file mode 100644 index 00000000..a4fd9139 --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_sumb7a60974e206e5c4db1cb80fdf3bcfe5.tex @@ -0,0 +1 @@ +_update_Mstatus_SUM : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_tsr911d1e468313451d39d3edd62969f771.tex b/sail_latex_riscv/valz_update_mstatus_tsr911d1e468313451d39d3edd62969f771.tex new file mode 100644 index 00000000..5ca84fa9 --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_tsr911d1e468313451d39d3edd62969f771.tex @@ -0,0 +1 @@ +_update_Mstatus_TSR : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_tvmf7d012651ef54cac1cdafef6e0e98a7f.tex b/sail_latex_riscv/valz_update_mstatus_tvmf7d012651ef54cac1cdafef6e0e98a7f.tex new file mode 100644 index 00000000..2757a51b --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_tvmf7d012651ef54cac1cdafef6e0e98a7f.tex @@ -0,0 +1 @@ +_update_Mstatus_TVM : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_tw2d7307276d7507e86718caff9b05aee8.tex b/sail_latex_riscv/valz_update_mstatus_tw2d7307276d7507e86718caff9b05aee8.tex new file mode 100644 index 00000000..54deeea3 --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_tw2d7307276d7507e86718caff9b05aee8.tex @@ -0,0 +1 @@ +_update_Mstatus_TW : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_uie24981f834cc06df1bad9dd31da0f462b.tex b/sail_latex_riscv/valz_update_mstatus_uie24981f834cc06df1bad9dd31da0f462b.tex new file mode 100644 index 00000000..ffba7573 --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_uie24981f834cc06df1bad9dd31da0f462b.tex @@ -0,0 +1 @@ +_update_Mstatus_UIE : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_upie62eccd6c3bcbfbe552e26c27d8c9e73e.tex b/sail_latex_riscv/valz_update_mstatus_upie62eccd6c3bcbfbe552e26c27d8c9e73e.tex new file mode 100644 index 00000000..3509c7e0 --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_upie62eccd6c3bcbfbe552e26c27d8c9e73e.tex @@ -0,0 +1 @@ +_update_Mstatus_UPIE : (Mstatus, bitvector(1, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mstatus_xsa631910853fd5409435e58ed9e2273a3.tex b/sail_latex_riscv/valz_update_mstatus_xsa631910853fd5409435e58ed9e2273a3.tex new file mode 100644 index 00000000..dd30f805 --- /dev/null +++ b/sail_latex_riscv/valz_update_mstatus_xsa631910853fd5409435e58ed9e2273a3.tex @@ -0,0 +1 @@ +_update_Mstatus_XS : (Mstatus, bitvector(2, dec)) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mtvec_base2276531f23752a05146b70a788934e75.tex b/sail_latex_riscv/valz_update_mtvec_base2276531f23752a05146b70a788934e75.tex new file mode 100644 index 00000000..63e1ae7b --- /dev/null +++ b/sail_latex_riscv/valz_update_mtvec_base2276531f23752a05146b70a788934e75.tex @@ -0,0 +1 @@ +_update_Mtvec_Base : (Mtvec, bitvector(62, dec)) -> Mtvec \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mtvec_bits158581c836e4cf68e74f750598d54083.tex b/sail_latex_riscv/valz_update_mtvec_bits158581c836e4cf68e74f750598d54083.tex new file mode 100644 index 00000000..6f92ff03 --- /dev/null +++ b/sail_latex_riscv/valz_update_mtvec_bits158581c836e4cf68e74f750598d54083.tex @@ -0,0 +1 @@ +_update_Mtvec_bits : (Mtvec, bitvector(64, dec)) -> Mtvec \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_mtvec_moded92fe8c6eb43d3e69a83d0a2b060e3a2.tex b/sail_latex_riscv/valz_update_mtvec_moded92fe8c6eb43d3e69a83d0a2b060e3a2.tex new file mode 100644 index 00000000..87861769 --- /dev/null +++ b/sail_latex_riscv/valz_update_mtvec_moded92fe8c6eb43d3e69a83d0a2b060e3a2.tex @@ -0,0 +1 @@ +_update_Mtvec_Mode : (Mtvec, bitvector(2, dec)) -> Mtvec \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pmpcfg_ent_adadbb540a1c6bab1c55bd9a61e3b9e0a.tex b/sail_latex_riscv/valz_update_pmpcfg_ent_adadbb540a1c6bab1c55bd9a61e3b9e0a.tex new file mode 100644 index 00000000..4db3cf3c --- /dev/null +++ b/sail_latex_riscv/valz_update_pmpcfg_ent_adadbb540a1c6bab1c55bd9a61e3b9e0a.tex @@ -0,0 +1 @@ +_update_Pmpcfg_ent_A : (Pmpcfg_ent, bitvector(2, dec)) -> Pmpcfg_ent \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pmpcfg_ent_bits6dc08fac70bb607f44a679981ff8591f.tex b/sail_latex_riscv/valz_update_pmpcfg_ent_bits6dc08fac70bb607f44a679981ff8591f.tex new file mode 100644 index 00000000..efb6e54a --- /dev/null +++ b/sail_latex_riscv/valz_update_pmpcfg_ent_bits6dc08fac70bb607f44a679981ff8591f.tex @@ -0,0 +1 @@ +_update_Pmpcfg_ent_bits : (Pmpcfg_ent, bitvector(8, dec)) -> Pmpcfg_ent \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pmpcfg_ent_lb0e2b34db62383c5c6ef62efd629c305.tex b/sail_latex_riscv/valz_update_pmpcfg_ent_lb0e2b34db62383c5c6ef62efd629c305.tex new file mode 100644 index 00000000..be8881da --- /dev/null +++ b/sail_latex_riscv/valz_update_pmpcfg_ent_lb0e2b34db62383c5c6ef62efd629c305.tex @@ -0,0 +1 @@ +_update_Pmpcfg_ent_L : (Pmpcfg_ent, bitvector(1, dec)) -> Pmpcfg_ent \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pmpcfg_ent_r2c785198293c46ff7260dc7a32aa6331.tex b/sail_latex_riscv/valz_update_pmpcfg_ent_r2c785198293c46ff7260dc7a32aa6331.tex new file mode 100644 index 00000000..c61f929f --- /dev/null +++ b/sail_latex_riscv/valz_update_pmpcfg_ent_r2c785198293c46ff7260dc7a32aa6331.tex @@ -0,0 +1 @@ +_update_Pmpcfg_ent_R : (Pmpcfg_ent, bitvector(1, dec)) -> Pmpcfg_ent \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pmpcfg_ent_w74feb7c9463c0ec331329f44cf100d0f.tex b/sail_latex_riscv/valz_update_pmpcfg_ent_w74feb7c9463c0ec331329f44cf100d0f.tex new file mode 100644 index 00000000..d7b56a30 --- /dev/null +++ b/sail_latex_riscv/valz_update_pmpcfg_ent_w74feb7c9463c0ec331329f44cf100d0f.tex @@ -0,0 +1 @@ +_update_Pmpcfg_ent_W : (Pmpcfg_ent, bitvector(1, dec)) -> Pmpcfg_ent \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pmpcfg_ent_x097e4626d7a8cfe0234214857e298c86.tex b/sail_latex_riscv/valz_update_pmpcfg_ent_x097e4626d7a8cfe0234214857e298c86.tex new file mode 100644 index 00000000..965f7070 --- /dev/null +++ b/sail_latex_riscv/valz_update_pmpcfg_ent_x097e4626d7a8cfe0234214857e298c86.tex @@ -0,0 +1 @@ +_update_Pmpcfg_ent_X : (Pmpcfg_ent, bitvector(1, dec)) -> Pmpcfg_ent \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pte_bits_a3004f24784d29ad77e6bb0801c41e98e.tex b/sail_latex_riscv/valz_update_pte_bits_a3004f24784d29ad77e6bb0801c41e98e.tex new file mode 100644 index 00000000..4db823d6 --- /dev/null +++ b/sail_latex_riscv/valz_update_pte_bits_a3004f24784d29ad77e6bb0801c41e98e.tex @@ -0,0 +1 @@ +_update_PTE_Bits_A : (PTE_Bits, bitvector(1, dec)) -> PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pte_bits_bits103014768edd92dc714fb7a033a0405f.tex b/sail_latex_riscv/valz_update_pte_bits_bits103014768edd92dc714fb7a033a0405f.tex new file mode 100644 index 00000000..38ecdd0e --- /dev/null +++ b/sail_latex_riscv/valz_update_pte_bits_bits103014768edd92dc714fb7a033a0405f.tex @@ -0,0 +1 @@ +_update_PTE_Bits_bits : (PTE_Bits, bitvector(8, dec)) -> PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pte_bits_d0702d6e9e8c79296c17be6a87f7d2bcb.tex b/sail_latex_riscv/valz_update_pte_bits_d0702d6e9e8c79296c17be6a87f7d2bcb.tex new file mode 100644 index 00000000..491952ef --- /dev/null +++ b/sail_latex_riscv/valz_update_pte_bits_d0702d6e9e8c79296c17be6a87f7d2bcb.tex @@ -0,0 +1 @@ +_update_PTE_Bits_D : (PTE_Bits, bitvector(1, dec)) -> PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pte_bits_g7f8aa128b55e6f52846f32adb9e9a045.tex b/sail_latex_riscv/valz_update_pte_bits_g7f8aa128b55e6f52846f32adb9e9a045.tex new file mode 100644 index 00000000..9a4cda25 --- /dev/null +++ b/sail_latex_riscv/valz_update_pte_bits_g7f8aa128b55e6f52846f32adb9e9a045.tex @@ -0,0 +1 @@ +_update_PTE_Bits_G : (PTE_Bits, bitvector(1, dec)) -> PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pte_bits_r320dc9e678d3a436f17fb038197c377c.tex b/sail_latex_riscv/valz_update_pte_bits_r320dc9e678d3a436f17fb038197c377c.tex new file mode 100644 index 00000000..744d0a15 --- /dev/null +++ b/sail_latex_riscv/valz_update_pte_bits_r320dc9e678d3a436f17fb038197c377c.tex @@ -0,0 +1 @@ +_update_PTE_Bits_R : (PTE_Bits, bitvector(1, dec)) -> PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pte_bits_u977bcbc754c6423b417ff582c0113450.tex b/sail_latex_riscv/valz_update_pte_bits_u977bcbc754c6423b417ff582c0113450.tex new file mode 100644 index 00000000..be2755d4 --- /dev/null +++ b/sail_latex_riscv/valz_update_pte_bits_u977bcbc754c6423b417ff582c0113450.tex @@ -0,0 +1 @@ +_update_PTE_Bits_U : (PTE_Bits, bitvector(1, dec)) -> PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pte_bits_vf1ed439c0a93204c0e278d68fd72351c.tex b/sail_latex_riscv/valz_update_pte_bits_vf1ed439c0a93204c0e278d68fd72351c.tex new file mode 100644 index 00000000..32902a03 --- /dev/null +++ b/sail_latex_riscv/valz_update_pte_bits_vf1ed439c0a93204c0e278d68fd72351c.tex @@ -0,0 +1 @@ +_update_PTE_Bits_V : (PTE_Bits, bitvector(1, dec)) -> PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pte_bits_w18528f50b9477178a61c7f8ca1c44e05.tex b/sail_latex_riscv/valz_update_pte_bits_w18528f50b9477178a61c7f8ca1c44e05.tex new file mode 100644 index 00000000..5fb8a946 --- /dev/null +++ b/sail_latex_riscv/valz_update_pte_bits_w18528f50b9477178a61c7f8ca1c44e05.tex @@ -0,0 +1 @@ +_update_PTE_Bits_W : (PTE_Bits, bitvector(1, dec)) -> PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_pte_bits_xe681f15474cf63965beb076cc7920964.tex b/sail_latex_riscv/valz_update_pte_bits_xe681f15474cf63965beb076cc7920964.tex new file mode 100644 index 00000000..95829539 --- /dev/null +++ b/sail_latex_riscv/valz_update_pte_bits_xe681f15474cf63965beb076cc7920964.tex @@ -0,0 +1 @@ +_update_PTE_Bits_X : (PTE_Bits, bitvector(1, dec)) -> PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_satp32_asid4a10333ee9adcd6b560d2b22f799b1c2.tex b/sail_latex_riscv/valz_update_satp32_asid4a10333ee9adcd6b560d2b22f799b1c2.tex new file mode 100644 index 00000000..6e4d812d --- /dev/null +++ b/sail_latex_riscv/valz_update_satp32_asid4a10333ee9adcd6b560d2b22f799b1c2.tex @@ -0,0 +1 @@ +_update_Satp32_Asid : (Satp32, bitvector(9, dec)) -> Satp32 \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_satp32_bits040735762104e2eb7ee468b2c73a3376.tex b/sail_latex_riscv/valz_update_satp32_bits040735762104e2eb7ee468b2c73a3376.tex new file mode 100644 index 00000000..458f1b98 --- /dev/null +++ b/sail_latex_riscv/valz_update_satp32_bits040735762104e2eb7ee468b2c73a3376.tex @@ -0,0 +1 @@ +_update_Satp32_bits : (Satp32, bitvector(32, dec)) -> Satp32 \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_satp32_modeeff3936a1c725a7de10614f5e8bbdc94.tex b/sail_latex_riscv/valz_update_satp32_modeeff3936a1c725a7de10614f5e8bbdc94.tex new file mode 100644 index 00000000..23c52e82 --- /dev/null +++ b/sail_latex_riscv/valz_update_satp32_modeeff3936a1c725a7de10614f5e8bbdc94.tex @@ -0,0 +1 @@ +_update_Satp32_Mode : (Satp32, bitvector(1, dec)) -> Satp32 \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_satp32_ppnfdc6c798de82ace5c37372a64d41dbd8.tex b/sail_latex_riscv/valz_update_satp32_ppnfdc6c798de82ace5c37372a64d41dbd8.tex new file mode 100644 index 00000000..626cd970 --- /dev/null +++ b/sail_latex_riscv/valz_update_satp32_ppnfdc6c798de82ace5c37372a64d41dbd8.tex @@ -0,0 +1 @@ +_update_Satp32_PPN : (Satp32, bitvector(22, dec)) -> Satp32 \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_satp64_asid4587433548bd071c272c301c9b049f40.tex b/sail_latex_riscv/valz_update_satp64_asid4587433548bd071c272c301c9b049f40.tex new file mode 100644 index 00000000..67b523dd --- /dev/null +++ b/sail_latex_riscv/valz_update_satp64_asid4587433548bd071c272c301c9b049f40.tex @@ -0,0 +1 @@ +_update_Satp64_Asid : (Satp64, bitvector(16, dec)) -> Satp64 \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_satp64_bits2b386da295e07d09d86a4906f50a6dcf.tex b/sail_latex_riscv/valz_update_satp64_bits2b386da295e07d09d86a4906f50a6dcf.tex new file mode 100644 index 00000000..55f0173d --- /dev/null +++ b/sail_latex_riscv/valz_update_satp64_bits2b386da295e07d09d86a4906f50a6dcf.tex @@ -0,0 +1 @@ +_update_Satp64_bits : (Satp64, bitvector(64, dec)) -> Satp64 \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_satp64_modef6a327a4e9deddb4a58d5af1293fb1e4.tex b/sail_latex_riscv/valz_update_satp64_modef6a327a4e9deddb4a58d5af1293fb1e4.tex new file mode 100644 index 00000000..8e9c9504 --- /dev/null +++ b/sail_latex_riscv/valz_update_satp64_modef6a327a4e9deddb4a58d5af1293fb1e4.tex @@ -0,0 +1 @@ +_update_Satp64_Mode : (Satp64, bitvector(4, dec)) -> Satp64 \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_satp64_ppne5381a5ff516a83023a3ab6b001812ea.tex b/sail_latex_riscv/valz_update_satp64_ppne5381a5ff516a83023a3ab6b001812ea.tex new file mode 100644 index 00000000..34bb90df --- /dev/null +++ b/sail_latex_riscv/valz_update_satp64_ppne5381a5ff516a83023a3ab6b001812ea.tex @@ -0,0 +1 @@ +_update_Satp64_PPN : (Satp64, bitvector(44, dec)) -> Satp64 \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sedeleg_bits2cf1d3152200555a4daa2092a724ca06.tex b/sail_latex_riscv/valz_update_sedeleg_bits2cf1d3152200555a4daa2092a724ca06.tex new file mode 100644 index 00000000..0d49f991 --- /dev/null +++ b/sail_latex_riscv/valz_update_sedeleg_bits2cf1d3152200555a4daa2092a724ca06.tex @@ -0,0 +1 @@ +_update_Sedeleg_bits : (Sedeleg, bitvector(64, dec)) -> Sedeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sedeleg_breakpoint4d1939da47af81029ca375f5c1c080e4.tex b/sail_latex_riscv/valz_update_sedeleg_breakpoint4d1939da47af81029ca375f5c1c080e4.tex new file mode 100644 index 00000000..28e43eeb --- /dev/null +++ b/sail_latex_riscv/valz_update_sedeleg_breakpoint4d1939da47af81029ca375f5c1c080e4.tex @@ -0,0 +1 @@ +_update_Sedeleg_Breakpoint : (Sedeleg, bitvector(1, dec)) -> Sedeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sedeleg_fetch_access_faultda711a3adc64706197c584b3f07a0e63.tex b/sail_latex_riscv/valz_update_sedeleg_fetch_access_faultda711a3adc64706197c584b3f07a0e63.tex new file mode 100644 index 00000000..3b9a3daa --- /dev/null +++ b/sail_latex_riscv/valz_update_sedeleg_fetch_access_faultda711a3adc64706197c584b3f07a0e63.tex @@ -0,0 +1 @@ +_update_Sedeleg_Fetch_Access_Fault : (Sedeleg, bitvector(1, dec)) -> Sedeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sedeleg_fetch_addr_align57e1b55e0654637983d88a45a3d27115.tex b/sail_latex_riscv/valz_update_sedeleg_fetch_addr_align57e1b55e0654637983d88a45a3d27115.tex new file mode 100644 index 00000000..cc8cf26f --- /dev/null +++ b/sail_latex_riscv/valz_update_sedeleg_fetch_addr_align57e1b55e0654637983d88a45a3d27115.tex @@ -0,0 +1 @@ +_update_Sedeleg_Fetch_Addr_Align : (Sedeleg, bitvector(1, dec)) -> Sedeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sedeleg_illegal_instr9f8eba51e2ce66c712c8a83a69cb47a0.tex b/sail_latex_riscv/valz_update_sedeleg_illegal_instr9f8eba51e2ce66c712c8a83a69cb47a0.tex new file mode 100644 index 00000000..e27a79f5 --- /dev/null +++ b/sail_latex_riscv/valz_update_sedeleg_illegal_instr9f8eba51e2ce66c712c8a83a69cb47a0.tex @@ -0,0 +1 @@ +_update_Sedeleg_Illegal_Instr : (Sedeleg, bitvector(1, dec)) -> Sedeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sedeleg_load_access_fault6594e15b80693a22fb20ab7451df6720.tex b/sail_latex_riscv/valz_update_sedeleg_load_access_fault6594e15b80693a22fb20ab7451df6720.tex new file mode 100644 index 00000000..e2c9bc02 --- /dev/null +++ b/sail_latex_riscv/valz_update_sedeleg_load_access_fault6594e15b80693a22fb20ab7451df6720.tex @@ -0,0 +1 @@ +_update_Sedeleg_Load_Access_Fault : (Sedeleg, bitvector(1, dec)) -> Sedeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sedeleg_load_addr_alignddc26fe8167315620c0f5b98d7cf6b8d.tex b/sail_latex_riscv/valz_update_sedeleg_load_addr_alignddc26fe8167315620c0f5b98d7cf6b8d.tex new file mode 100644 index 00000000..874e000c --- /dev/null +++ b/sail_latex_riscv/valz_update_sedeleg_load_addr_alignddc26fe8167315620c0f5b98d7cf6b8d.tex @@ -0,0 +1 @@ +_update_Sedeleg_Load_Addr_Align : (Sedeleg, bitvector(1, dec)) -> Sedeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sedeleg_samo_access_fault9638c0015422d7509a2a078d70f56ba2.tex b/sail_latex_riscv/valz_update_sedeleg_samo_access_fault9638c0015422d7509a2a078d70f56ba2.tex new file mode 100644 index 00000000..b7e20bcb --- /dev/null +++ b/sail_latex_riscv/valz_update_sedeleg_samo_access_fault9638c0015422d7509a2a078d70f56ba2.tex @@ -0,0 +1 @@ +_update_Sedeleg_SAMO_Access_Fault : (Sedeleg, bitvector(1, dec)) -> Sedeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sedeleg_samo_addr_align39928f0de9fb23d2068681efa4f6e746.tex b/sail_latex_riscv/valz_update_sedeleg_samo_addr_align39928f0de9fb23d2068681efa4f6e746.tex new file mode 100644 index 00000000..f6d26136 --- /dev/null +++ b/sail_latex_riscv/valz_update_sedeleg_samo_addr_align39928f0de9fb23d2068681efa4f6e746.tex @@ -0,0 +1 @@ +_update_Sedeleg_SAMO_Addr_Align : (Sedeleg, bitvector(1, dec)) -> Sedeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sedeleg_uenvcall0461d2c07b3055bf1fc4d0b3ea5739ef.tex b/sail_latex_riscv/valz_update_sedeleg_uenvcall0461d2c07b3055bf1fc4d0b3ea5739ef.tex new file mode 100644 index 00000000..54a214ad --- /dev/null +++ b/sail_latex_riscv/valz_update_sedeleg_uenvcall0461d2c07b3055bf1fc4d0b3ea5739ef.tex @@ -0,0 +1 @@ +_update_Sedeleg_UEnvCall : (Sedeleg, bitvector(1, dec)) -> Sedeleg \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sinterrupts_bitsb82a5eaca518d7033ee5b65b76de6fc3.tex b/sail_latex_riscv/valz_update_sinterrupts_bitsb82a5eaca518d7033ee5b65b76de6fc3.tex new file mode 100644 index 00000000..34ca00ff --- /dev/null +++ b/sail_latex_riscv/valz_update_sinterrupts_bitsb82a5eaca518d7033ee5b65b76de6fc3.tex @@ -0,0 +1 @@ +_update_Sinterrupts_bits : (Sinterrupts, bitvector(64, dec)) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sinterrupts_seidfae2f173d12134865a23f8b06b92d56.tex b/sail_latex_riscv/valz_update_sinterrupts_seidfae2f173d12134865a23f8b06b92d56.tex new file mode 100644 index 00000000..45c57ac9 --- /dev/null +++ b/sail_latex_riscv/valz_update_sinterrupts_seidfae2f173d12134865a23f8b06b92d56.tex @@ -0,0 +1 @@ +_update_Sinterrupts_SEI : (Sinterrupts, bitvector(1, dec)) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sinterrupts_ssi41e461cfb1d80cf6497915184ac067fe.tex b/sail_latex_riscv/valz_update_sinterrupts_ssi41e461cfb1d80cf6497915184ac067fe.tex new file mode 100644 index 00000000..7f51774b --- /dev/null +++ b/sail_latex_riscv/valz_update_sinterrupts_ssi41e461cfb1d80cf6497915184ac067fe.tex @@ -0,0 +1 @@ +_update_Sinterrupts_SSI : (Sinterrupts, bitvector(1, dec)) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sinterrupts_sti3fd7347767c86ca33481e1dbc90ce93c.tex b/sail_latex_riscv/valz_update_sinterrupts_sti3fd7347767c86ca33481e1dbc90ce93c.tex new file mode 100644 index 00000000..065e52fd --- /dev/null +++ b/sail_latex_riscv/valz_update_sinterrupts_sti3fd7347767c86ca33481e1dbc90ce93c.tex @@ -0,0 +1 @@ +_update_Sinterrupts_STI : (Sinterrupts, bitvector(1, dec)) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sinterrupts_uei4e9add8c9d8edc1f50674d5eb879d669.tex b/sail_latex_riscv/valz_update_sinterrupts_uei4e9add8c9d8edc1f50674d5eb879d669.tex new file mode 100644 index 00000000..871eb094 --- /dev/null +++ b/sail_latex_riscv/valz_update_sinterrupts_uei4e9add8c9d8edc1f50674d5eb879d669.tex @@ -0,0 +1 @@ +_update_Sinterrupts_UEI : (Sinterrupts, bitvector(1, dec)) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sinterrupts_usia415b4e062e30257cfefa06256955512.tex b/sail_latex_riscv/valz_update_sinterrupts_usia415b4e062e30257cfefa06256955512.tex new file mode 100644 index 00000000..89450f76 --- /dev/null +++ b/sail_latex_riscv/valz_update_sinterrupts_usia415b4e062e30257cfefa06256955512.tex @@ -0,0 +1 @@ +_update_Sinterrupts_USI : (Sinterrupts, bitvector(1, dec)) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sinterrupts_uti76436fc7f8e1e46117a090613db49900.tex b/sail_latex_riscv/valz_update_sinterrupts_uti76436fc7f8e1e46117a090613db49900.tex new file mode 100644 index 00000000..16c21f0c --- /dev/null +++ b/sail_latex_riscv/valz_update_sinterrupts_uti76436fc7f8e1e46117a090613db49900.tex @@ -0,0 +1 @@ +_update_Sinterrupts_UTI : (Sinterrupts, bitvector(1, dec)) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sstatus_bits1ba4fa3c8cd21f04fa8e9a269f477a52.tex b/sail_latex_riscv/valz_update_sstatus_bits1ba4fa3c8cd21f04fa8e9a269f477a52.tex new file mode 100644 index 00000000..6cd4c98c --- /dev/null +++ b/sail_latex_riscv/valz_update_sstatus_bits1ba4fa3c8cd21f04fa8e9a269f477a52.tex @@ -0,0 +1 @@ +_update_Sstatus_bits : (Sstatus, bitvector(64, dec)) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sstatus_fs5ae270f58355a8043214a3e56ea4ecb9.tex b/sail_latex_riscv/valz_update_sstatus_fs5ae270f58355a8043214a3e56ea4ecb9.tex new file mode 100644 index 00000000..cdde51ec --- /dev/null +++ b/sail_latex_riscv/valz_update_sstatus_fs5ae270f58355a8043214a3e56ea4ecb9.tex @@ -0,0 +1 @@ +_update_Sstatus_FS : (Sstatus, bitvector(2, dec)) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sstatus_mxre42b7942f7975353cbe85a0c0e124cdd.tex b/sail_latex_riscv/valz_update_sstatus_mxre42b7942f7975353cbe85a0c0e124cdd.tex new file mode 100644 index 00000000..ea595277 --- /dev/null +++ b/sail_latex_riscv/valz_update_sstatus_mxre42b7942f7975353cbe85a0c0e124cdd.tex @@ -0,0 +1 @@ +_update_Sstatus_MXR : (Sstatus, bitvector(1, dec)) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sstatus_sda2846124209293b81711916fe96d61c9.tex b/sail_latex_riscv/valz_update_sstatus_sda2846124209293b81711916fe96d61c9.tex new file mode 100644 index 00000000..bf9c1c98 --- /dev/null +++ b/sail_latex_riscv/valz_update_sstatus_sda2846124209293b81711916fe96d61c9.tex @@ -0,0 +1 @@ +_update_Sstatus_SD : (Sstatus, bitvector(1, dec)) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sstatus_siea3c5fb4c611f7dacc262fcbe33a89902.tex b/sail_latex_riscv/valz_update_sstatus_siea3c5fb4c611f7dacc262fcbe33a89902.tex new file mode 100644 index 00000000..5fe78c73 --- /dev/null +++ b/sail_latex_riscv/valz_update_sstatus_siea3c5fb4c611f7dacc262fcbe33a89902.tex @@ -0,0 +1 @@ +_update_Sstatus_SIE : (Sstatus, bitvector(1, dec)) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sstatus_spiea58b5496b1efe334d89b66e4df1f6a37.tex b/sail_latex_riscv/valz_update_sstatus_spiea58b5496b1efe334d89b66e4df1f6a37.tex new file mode 100644 index 00000000..1cf7f978 --- /dev/null +++ b/sail_latex_riscv/valz_update_sstatus_spiea58b5496b1efe334d89b66e4df1f6a37.tex @@ -0,0 +1 @@ +_update_Sstatus_SPIE : (Sstatus, bitvector(1, dec)) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sstatus_spp6bca059909e0ea5d1dca7a5f6a4c496d.tex b/sail_latex_riscv/valz_update_sstatus_spp6bca059909e0ea5d1dca7a5f6a4c496d.tex new file mode 100644 index 00000000..98fe7244 --- /dev/null +++ b/sail_latex_riscv/valz_update_sstatus_spp6bca059909e0ea5d1dca7a5f6a4c496d.tex @@ -0,0 +1 @@ +_update_Sstatus_SPP : (Sstatus, bitvector(1, dec)) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sstatus_sum0cb0974a1d97890dd07f5d0a8a0e2a1f.tex b/sail_latex_riscv/valz_update_sstatus_sum0cb0974a1d97890dd07f5d0a8a0e2a1f.tex new file mode 100644 index 00000000..4770b6d5 --- /dev/null +++ b/sail_latex_riscv/valz_update_sstatus_sum0cb0974a1d97890dd07f5d0a8a0e2a1f.tex @@ -0,0 +1 @@ +_update_Sstatus_SUM : (Sstatus, bitvector(1, dec)) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sstatus_uie0de3308b00b5fa027c405d5ba7ea56a8.tex b/sail_latex_riscv/valz_update_sstatus_uie0de3308b00b5fa027c405d5ba7ea56a8.tex new file mode 100644 index 00000000..d588f32c --- /dev/null +++ b/sail_latex_riscv/valz_update_sstatus_uie0de3308b00b5fa027c405d5ba7ea56a8.tex @@ -0,0 +1 @@ +_update_Sstatus_UIE : (Sstatus, bitvector(1, dec)) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sstatus_upie90c90f6e3ef912c0267408b59aaaec07.tex b/sail_latex_riscv/valz_update_sstatus_upie90c90f6e3ef912c0267408b59aaaec07.tex new file mode 100644 index 00000000..c866604e --- /dev/null +++ b/sail_latex_riscv/valz_update_sstatus_upie90c90f6e3ef912c0267408b59aaaec07.tex @@ -0,0 +1 @@ +_update_Sstatus_UPIE : (Sstatus, bitvector(1, dec)) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sstatus_xs8ed6c14d8c84fed994d5b6f62a6f95ff.tex b/sail_latex_riscv/valz_update_sstatus_xs8ed6c14d8c84fed994d5b6f62a6f95ff.tex new file mode 100644 index 00000000..eee9e9ef --- /dev/null +++ b/sail_latex_riscv/valz_update_sstatus_xs8ed6c14d8c84fed994d5b6f62a6f95ff.tex @@ -0,0 +1 @@ +_update_Sstatus_XS : (Sstatus, bitvector(2, dec)) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv32_paddr_bits471b1f564b9f112d8202c1386e4a2c40.tex b/sail_latex_riscv/valz_update_sv32_paddr_bits471b1f564b9f112d8202c1386e4a2c40.tex new file mode 100644 index 00000000..cc50d208 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv32_paddr_bits471b1f564b9f112d8202c1386e4a2c40.tex @@ -0,0 +1 @@ +_update_SV32_Paddr_bits : (SV32_Paddr, bitvector(34, dec)) -> SV32_Paddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv32_paddr_pgofsece69bfc0ddb3bbee82163605c655cd8.tex b/sail_latex_riscv/valz_update_sv32_paddr_pgofsece69bfc0ddb3bbee82163605c655cd8.tex new file mode 100644 index 00000000..4c7f17bc --- /dev/null +++ b/sail_latex_riscv/valz_update_sv32_paddr_pgofsece69bfc0ddb3bbee82163605c655cd8.tex @@ -0,0 +1 @@ +_update_SV32_Paddr_PgOfs : (SV32_Paddr, bitvector(12, dec)) -> SV32_Paddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv32_paddr_ppnic2e893ade647c24a430ebfdfc1376233.tex b/sail_latex_riscv/valz_update_sv32_paddr_ppnic2e893ade647c24a430ebfdfc1376233.tex new file mode 100644 index 00000000..c34b3ce6 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv32_paddr_ppnic2e893ade647c24a430ebfdfc1376233.tex @@ -0,0 +1 @@ +_update_SV32_Paddr_PPNi : (SV32_Paddr, bitvector(22, dec)) -> SV32_Paddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv32_pte_bits55ab6942a6f92e27c0aaaffec4bc5b75.tex b/sail_latex_riscv/valz_update_sv32_pte_bits55ab6942a6f92e27c0aaaffec4bc5b75.tex new file mode 100644 index 00000000..5b1bfae9 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv32_pte_bits55ab6942a6f92e27c0aaaffec4bc5b75.tex @@ -0,0 +1 @@ +_update_SV32_PTE_BITS : (SV32_PTE, bitvector(8, dec)) -> SV32_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv32_pte_bits6ed5ef3d3bdb39782740d15add28a8ca.tex b/sail_latex_riscv/valz_update_sv32_pte_bits6ed5ef3d3bdb39782740d15add28a8ca.tex new file mode 100644 index 00000000..baec9095 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv32_pte_bits6ed5ef3d3bdb39782740d15add28a8ca.tex @@ -0,0 +1 @@ +_update_SV32_PTE_bits : (SV32_PTE, bitvector(32, dec)) -> SV32_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv32_pte_ppni21f940c0d0da732c90fb464f03b30e8e.tex b/sail_latex_riscv/valz_update_sv32_pte_ppni21f940c0d0da732c90fb464f03b30e8e.tex new file mode 100644 index 00000000..c30ac3ac --- /dev/null +++ b/sail_latex_riscv/valz_update_sv32_pte_ppni21f940c0d0da732c90fb464f03b30e8e.tex @@ -0,0 +1 @@ +_update_SV32_PTE_PPNi : (SV32_PTE, bitvector(22, dec)) -> SV32_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv32_pte_rsw2127473fcefd5043f7339af205217e28.tex b/sail_latex_riscv/valz_update_sv32_pte_rsw2127473fcefd5043f7339af205217e28.tex new file mode 100644 index 00000000..6d494d85 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv32_pte_rsw2127473fcefd5043f7339af205217e28.tex @@ -0,0 +1 @@ +_update_SV32_PTE_RSW : (SV32_PTE, bitvector(2, dec)) -> SV32_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv32_vaddr_bitsc681e87f3f4d859da7fee6d71d8b62c6.tex b/sail_latex_riscv/valz_update_sv32_vaddr_bitsc681e87f3f4d859da7fee6d71d8b62c6.tex new file mode 100644 index 00000000..3bd82148 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv32_vaddr_bitsc681e87f3f4d859da7fee6d71d8b62c6.tex @@ -0,0 +1 @@ +_update_SV32_Vaddr_bits : (SV32_Vaddr, bitvector(32, dec)) -> SV32_Vaddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv32_vaddr_pgofs4d5270a8a6277991b4da2a32d070beba.tex b/sail_latex_riscv/valz_update_sv32_vaddr_pgofs4d5270a8a6277991b4da2a32d070beba.tex new file mode 100644 index 00000000..2b659916 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv32_vaddr_pgofs4d5270a8a6277991b4da2a32d070beba.tex @@ -0,0 +1 @@ +_update_SV32_Vaddr_PgOfs : (SV32_Vaddr, bitvector(12, dec)) -> SV32_Vaddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv32_vaddr_vpnif3d232fd203d42def1af1b10dd8639df.tex b/sail_latex_riscv/valz_update_sv32_vaddr_vpnif3d232fd203d42def1af1b10dd8639df.tex new file mode 100644 index 00000000..f8afafd2 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv32_vaddr_vpnif3d232fd203d42def1af1b10dd8639df.tex @@ -0,0 +1 @@ +_update_SV32_Vaddr_VPNi : (SV32_Vaddr, bitvector(20, dec)) -> SV32_Vaddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv39_paddr_bits95d51c315963bb06758677d399020d4c.tex b/sail_latex_riscv/valz_update_sv39_paddr_bits95d51c315963bb06758677d399020d4c.tex new file mode 100644 index 00000000..26d1c40a --- /dev/null +++ b/sail_latex_riscv/valz_update_sv39_paddr_bits95d51c315963bb06758677d399020d4c.tex @@ -0,0 +1 @@ +_update_SV39_Paddr_bits : (SV39_Paddr, bitvector(56, dec)) -> SV39_Paddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv39_paddr_pgofs92e3fd4a4ef641b9bd4695bcb4e6865d.tex b/sail_latex_riscv/valz_update_sv39_paddr_pgofs92e3fd4a4ef641b9bd4695bcb4e6865d.tex new file mode 100644 index 00000000..d701f7c8 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv39_paddr_pgofs92e3fd4a4ef641b9bd4695bcb4e6865d.tex @@ -0,0 +1 @@ +_update_SV39_Paddr_PgOfs : (SV39_Paddr, bitvector(12, dec)) -> SV39_Paddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv39_paddr_ppni64a04f2f491820010df9118b96fe3bb1.tex b/sail_latex_riscv/valz_update_sv39_paddr_ppni64a04f2f491820010df9118b96fe3bb1.tex new file mode 100644 index 00000000..1544c2f1 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv39_paddr_ppni64a04f2f491820010df9118b96fe3bb1.tex @@ -0,0 +1 @@ +_update_SV39_Paddr_PPNi : (SV39_Paddr, bitvector(44, dec)) -> SV39_Paddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv39_pte_bits3f8498b470f391c57cca777dadcbfb2e.tex b/sail_latex_riscv/valz_update_sv39_pte_bits3f8498b470f391c57cca777dadcbfb2e.tex new file mode 100644 index 00000000..f1056b49 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv39_pte_bits3f8498b470f391c57cca777dadcbfb2e.tex @@ -0,0 +1 @@ +_update_SV39_PTE_BITS : (SV39_PTE, bitvector(8, dec)) -> SV39_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv39_pte_bitsf70d63d10d4409523d5b20cddef1d791.tex b/sail_latex_riscv/valz_update_sv39_pte_bitsf70d63d10d4409523d5b20cddef1d791.tex new file mode 100644 index 00000000..2ed542c4 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv39_pte_bitsf70d63d10d4409523d5b20cddef1d791.tex @@ -0,0 +1 @@ +_update_SV39_PTE_bits : (SV39_PTE, bitvector(64, dec)) -> SV39_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv39_pte_ext7389da76692695bdeeaa0a6612d2ddf3.tex b/sail_latex_riscv/valz_update_sv39_pte_ext7389da76692695bdeeaa0a6612d2ddf3.tex new file mode 100644 index 00000000..7324e4ea --- /dev/null +++ b/sail_latex_riscv/valz_update_sv39_pte_ext7389da76692695bdeeaa0a6612d2ddf3.tex @@ -0,0 +1 @@ +_update_SV39_PTE_Ext : (SV39_PTE, bitvector(10, dec)) -> SV39_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv39_pte_ppni4bb75edea91e119f5e4b777a201ca7de.tex b/sail_latex_riscv/valz_update_sv39_pte_ppni4bb75edea91e119f5e4b777a201ca7de.tex new file mode 100644 index 00000000..2e74d239 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv39_pte_ppni4bb75edea91e119f5e4b777a201ca7de.tex @@ -0,0 +1 @@ +_update_SV39_PTE_PPNi : (SV39_PTE, bitvector(44, dec)) -> SV39_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv39_pte_rsw7d745d7147024b1db9a0ab778ae3aa90.tex b/sail_latex_riscv/valz_update_sv39_pte_rsw7d745d7147024b1db9a0ab778ae3aa90.tex new file mode 100644 index 00000000..885f5db2 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv39_pte_rsw7d745d7147024b1db9a0ab778ae3aa90.tex @@ -0,0 +1 @@ +_update_SV39_PTE_RSW : (SV39_PTE, bitvector(2, dec)) -> SV39_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv39_vaddr_bits9b5c877641996c39232fdaa69695b175.tex b/sail_latex_riscv/valz_update_sv39_vaddr_bits9b5c877641996c39232fdaa69695b175.tex new file mode 100644 index 00000000..d6288267 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv39_vaddr_bits9b5c877641996c39232fdaa69695b175.tex @@ -0,0 +1 @@ +_update_SV39_Vaddr_bits : (SV39_Vaddr, bitvector(39, dec)) -> SV39_Vaddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv39_vaddr_pgofs2203553b5bf9afd58276a7958197b4c6.tex b/sail_latex_riscv/valz_update_sv39_vaddr_pgofs2203553b5bf9afd58276a7958197b4c6.tex new file mode 100644 index 00000000..2453c596 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv39_vaddr_pgofs2203553b5bf9afd58276a7958197b4c6.tex @@ -0,0 +1 @@ +_update_SV39_Vaddr_PgOfs : (SV39_Vaddr, bitvector(12, dec)) -> SV39_Vaddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv39_vaddr_vpnibc20f5f41da77bf31c390df8cd865198.tex b/sail_latex_riscv/valz_update_sv39_vaddr_vpnibc20f5f41da77bf31c390df8cd865198.tex new file mode 100644 index 00000000..ebf35908 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv39_vaddr_vpnibc20f5f41da77bf31c390df8cd865198.tex @@ -0,0 +1 @@ +_update_SV39_Vaddr_VPNi : (SV39_Vaddr, bitvector(27, dec)) -> SV39_Vaddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv48_paddr_bitsd392e84dd67a8ca48490ef502cca7bd9.tex b/sail_latex_riscv/valz_update_sv48_paddr_bitsd392e84dd67a8ca48490ef502cca7bd9.tex new file mode 100644 index 00000000..fc643ad0 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv48_paddr_bitsd392e84dd67a8ca48490ef502cca7bd9.tex @@ -0,0 +1 @@ +_update_SV48_Paddr_bits : (SV48_Paddr, bitvector(56, dec)) -> SV48_Paddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv48_paddr_pgofsd71fa33c7b6f3543d0d9b5dc2d8380f5.tex b/sail_latex_riscv/valz_update_sv48_paddr_pgofsd71fa33c7b6f3543d0d9b5dc2d8380f5.tex new file mode 100644 index 00000000..baee80a6 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv48_paddr_pgofsd71fa33c7b6f3543d0d9b5dc2d8380f5.tex @@ -0,0 +1 @@ +_update_SV48_Paddr_PgOfs : (SV48_Paddr, bitvector(12, dec)) -> SV48_Paddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv48_paddr_ppni3e4b50484e79dc7761373bc124441fd0.tex b/sail_latex_riscv/valz_update_sv48_paddr_ppni3e4b50484e79dc7761373bc124441fd0.tex new file mode 100644 index 00000000..6947a213 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv48_paddr_ppni3e4b50484e79dc7761373bc124441fd0.tex @@ -0,0 +1 @@ +_update_SV48_Paddr_PPNi : (SV48_Paddr, bitvector(44, dec)) -> SV48_Paddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv48_pte_bits0a6df26df13de159300f6127a4b286db.tex b/sail_latex_riscv/valz_update_sv48_pte_bits0a6df26df13de159300f6127a4b286db.tex new file mode 100644 index 00000000..a4411f0b --- /dev/null +++ b/sail_latex_riscv/valz_update_sv48_pte_bits0a6df26df13de159300f6127a4b286db.tex @@ -0,0 +1 @@ +_update_SV48_PTE_bits : (SV48_PTE, bitvector(64, dec)) -> SV48_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv48_pte_bits5dd960679bb9cad63f93bb029f042c00.tex b/sail_latex_riscv/valz_update_sv48_pte_bits5dd960679bb9cad63f93bb029f042c00.tex new file mode 100644 index 00000000..48ea24d6 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv48_pte_bits5dd960679bb9cad63f93bb029f042c00.tex @@ -0,0 +1 @@ +_update_SV48_PTE_BITS : (SV48_PTE, bitvector(8, dec)) -> SV48_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv48_pte_ext35aecfa61e536a6e82b25c27b17d2b27.tex b/sail_latex_riscv/valz_update_sv48_pte_ext35aecfa61e536a6e82b25c27b17d2b27.tex new file mode 100644 index 00000000..11f9a96a --- /dev/null +++ b/sail_latex_riscv/valz_update_sv48_pte_ext35aecfa61e536a6e82b25c27b17d2b27.tex @@ -0,0 +1 @@ +_update_SV48_PTE_Ext : (SV48_PTE, bitvector(10, dec)) -> SV48_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv48_pte_ppni151ef3d95182ce7f10853d377fa591b3.tex b/sail_latex_riscv/valz_update_sv48_pte_ppni151ef3d95182ce7f10853d377fa591b3.tex new file mode 100644 index 00000000..0ec21a20 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv48_pte_ppni151ef3d95182ce7f10853d377fa591b3.tex @@ -0,0 +1 @@ +_update_SV48_PTE_PPNi : (SV48_PTE, bitvector(44, dec)) -> SV48_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv48_pte_rsw6c601ebf0d644b711cbbe304a5538b5e.tex b/sail_latex_riscv/valz_update_sv48_pte_rsw6c601ebf0d644b711cbbe304a5538b5e.tex new file mode 100644 index 00000000..fb80b237 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv48_pte_rsw6c601ebf0d644b711cbbe304a5538b5e.tex @@ -0,0 +1 @@ +_update_SV48_PTE_RSW : (SV48_PTE, bitvector(2, dec)) -> SV48_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv48_vaddr_bits591ffccf87e6224a472977f7dbf4b171.tex b/sail_latex_riscv/valz_update_sv48_vaddr_bits591ffccf87e6224a472977f7dbf4b171.tex new file mode 100644 index 00000000..c146cc3b --- /dev/null +++ b/sail_latex_riscv/valz_update_sv48_vaddr_bits591ffccf87e6224a472977f7dbf4b171.tex @@ -0,0 +1 @@ +_update_SV48_Vaddr_bits : (SV48_Vaddr, bitvector(48, dec)) -> SV48_Vaddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv48_vaddr_pgofs474bdc293738ab8c86555518304df3b0.tex b/sail_latex_riscv/valz_update_sv48_vaddr_pgofs474bdc293738ab8c86555518304df3b0.tex new file mode 100644 index 00000000..d9e24d8b --- /dev/null +++ b/sail_latex_riscv/valz_update_sv48_vaddr_pgofs474bdc293738ab8c86555518304df3b0.tex @@ -0,0 +1 @@ +_update_SV48_Vaddr_PgOfs : (SV48_Vaddr, bitvector(12, dec)) -> SV48_Vaddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_sv48_vaddr_vpni9035d832e2b055cf87646fbf4511fccb.tex b/sail_latex_riscv/valz_update_sv48_vaddr_vpni9035d832e2b055cf87646fbf4511fccb.tex new file mode 100644 index 00000000..f323e150 --- /dev/null +++ b/sail_latex_riscv/valz_update_sv48_vaddr_vpni9035d832e2b055cf87646fbf4511fccb.tex @@ -0,0 +1 @@ +_update_SV48_Vaddr_VPNi : (SV48_Vaddr, bitvector(27, dec)) -> SV48_Vaddr \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_uinterrupts_bits9c553d2ae4d62c448e09c704b0d8bba7.tex b/sail_latex_riscv/valz_update_uinterrupts_bits9c553d2ae4d62c448e09c704b0d8bba7.tex new file mode 100644 index 00000000..643662bf --- /dev/null +++ b/sail_latex_riscv/valz_update_uinterrupts_bits9c553d2ae4d62c448e09c704b0d8bba7.tex @@ -0,0 +1 @@ +_update_Uinterrupts_bits : (Uinterrupts, bitvector(64, dec)) -> Uinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_uinterrupts_ueib05aa22b4bb2fffd287cb5a502f86a7d.tex b/sail_latex_riscv/valz_update_uinterrupts_ueib05aa22b4bb2fffd287cb5a502f86a7d.tex new file mode 100644 index 00000000..35bb9a88 --- /dev/null +++ b/sail_latex_riscv/valz_update_uinterrupts_ueib05aa22b4bb2fffd287cb5a502f86a7d.tex @@ -0,0 +1 @@ +_update_Uinterrupts_UEI : (Uinterrupts, bitvector(1, dec)) -> Uinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_uinterrupts_usi1ec1151a92f98583f7c0c3cb9f03ca01.tex b/sail_latex_riscv/valz_update_uinterrupts_usi1ec1151a92f98583f7c0c3cb9f03ca01.tex new file mode 100644 index 00000000..f01acd1c --- /dev/null +++ b/sail_latex_riscv/valz_update_uinterrupts_usi1ec1151a92f98583f7c0c3cb9f03ca01.tex @@ -0,0 +1 @@ +_update_Uinterrupts_USI : (Uinterrupts, bitvector(1, dec)) -> Uinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_uinterrupts_uti881f938d0d5ebb68be2d1bcc7637dc77.tex b/sail_latex_riscv/valz_update_uinterrupts_uti881f938d0d5ebb68be2d1bcc7637dc77.tex new file mode 100644 index 00000000..3246ade3 --- /dev/null +++ b/sail_latex_riscv/valz_update_uinterrupts_uti881f938d0d5ebb68be2d1bcc7637dc77.tex @@ -0,0 +1 @@ +_update_Uinterrupts_UTI : (Uinterrupts, bitvector(1, dec)) -> Uinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_ustatus_bits58fc869676c24d63b7324b3ddc882d14.tex b/sail_latex_riscv/valz_update_ustatus_bits58fc869676c24d63b7324b3ddc882d14.tex new file mode 100644 index 00000000..e521774c --- /dev/null +++ b/sail_latex_riscv/valz_update_ustatus_bits58fc869676c24d63b7324b3ddc882d14.tex @@ -0,0 +1 @@ +_update_Ustatus_bits : (Ustatus, bitvector(64, dec)) -> Ustatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_ustatus_uie937a13d13f328a695bd490140941d1ad.tex b/sail_latex_riscv/valz_update_ustatus_uie937a13d13f328a695bd490140941d1ad.tex new file mode 100644 index 00000000..bd4069d3 --- /dev/null +++ b/sail_latex_riscv/valz_update_ustatus_uie937a13d13f328a695bd490140941d1ad.tex @@ -0,0 +1 @@ +_update_Ustatus_UIE : (Ustatus, bitvector(1, dec)) -> Ustatus \ No newline at end of file diff --git a/sail_latex_riscv/valz_update_ustatus_upie620a46996c155948c916224ee8c0d297.tex b/sail_latex_riscv/valz_update_ustatus_upie620a46996c155948c916224ee8c0d297.tex new file mode 100644 index 00000000..fff8668e --- /dev/null +++ b/sail_latex_riscv/valz_update_ustatus_upie620a46996c155948c916224ee8c0d297.tex @@ -0,0 +1 @@ +_update_Ustatus_UPIE : (Ustatus, bitvector(1, dec)) -> Ustatus \ No newline at end of file diff --git a/sail_latex_riscv/valza64_barrier_domain_of_num6e122924ff562010f42f288ecc2cdbe3.tex b/sail_latex_riscv/valza64_barrier_domain_of_num6e122924ff562010f42f288ecc2cdbe3.tex new file mode 100644 index 00000000..5eb1e97c --- /dev/null +++ b/sail_latex_riscv/valza64_barrier_domain_of_num6e122924ff562010f42f288ecc2cdbe3.tex @@ -0,0 +1 @@ +a64_barrier_domain_of_num : forall ('e : Int), (0 <= 'e & 'e <= 3). int('e) -> a64_barrier_domain \ No newline at end of file diff --git a/sail_latex_riscv/valza64_barrier_type_of_numc06c55fe3b04f35ecb4741ea01acc85e.tex b/sail_latex_riscv/valza64_barrier_type_of_numc06c55fe3b04f35ecb4741ea01acc85e.tex new file mode 100644 index 00000000..cf52296b --- /dev/null +++ b/sail_latex_riscv/valza64_barrier_type_of_numc06c55fe3b04f35ecb4741ea01acc85e.tex @@ -0,0 +1 @@ +a64_barrier_type_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> a64_barrier_type \ No newline at end of file diff --git a/sail_latex_riscv/valzabs_int_atom414063313cc5ac5d9a742f9c8a111704.tex b/sail_latex_riscv/valzabs_int_atom414063313cc5ac5d9a742f9c8a111704.tex new file mode 100644 index 00000000..bafc4750 --- /dev/null +++ b/sail_latex_riscv/valzabs_int_atom414063313cc5ac5d9a742f9c8a111704.tex @@ -0,0 +1 @@ +abs_int_atom : forall ('n : Int). int('n) -> int(abs('n)) \ No newline at end of file diff --git a/sail_latex_riscv/valzabs_int_plainb54aa4afeed2c86b519a464eb2e4c77c.tex b/sail_latex_riscv/valzabs_int_plainb54aa4afeed2c86b519a464eb2e4c77c.tex new file mode 100644 index 00000000..327250de --- /dev/null +++ b/sail_latex_riscv/valzabs_int_plainb54aa4afeed2c86b519a464eb2e4c77c.tex @@ -0,0 +1 @@ +abs_int_plain : int -> int \ No newline at end of file diff --git a/sail_latex_riscv/valzaccesstype_to_str58f7a46d6b3e326411426e3cf0fe52cf.tex b/sail_latex_riscv/valzaccesstype_to_str58f7a46d6b3e326411426e3cf0fe52cf.tex new file mode 100644 index 00000000..b08c9189 --- /dev/null +++ b/sail_latex_riscv/valzaccesstype_to_str58f7a46d6b3e326411426e3cf0fe52cf.tex @@ -0,0 +1 @@ +accessType_to_str : AccessType(ext_access_type) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzaccrue_fflags6f6e494f89bde56691f40e88b063e194.tex b/sail_latex_riscv/valzaccrue_fflags6f6e494f89bde56691f40e88b063e194.tex new file mode 100644 index 00000000..7df02b10 --- /dev/null +++ b/sail_latex_riscv/valzaccrue_fflags6f6e494f89bde56691f40e88b063e194.tex @@ -0,0 +1 @@ +accrue_fflags : bits(5) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzadd_atomd34efc9e611b6d3b6757e17f4932b12b.tex b/sail_latex_riscv/valzadd_atomd34efc9e611b6d3b6757e17f4932b12b.tex new file mode 100644 index 00000000..baf41c80 --- /dev/null +++ b/sail_latex_riscv/valzadd_atomd34efc9e611b6d3b6757e17f4932b12b.tex @@ -0,0 +1 @@ +add_atom : forall ('n 'm : Int). (int('n), int('m)) -> int('n + 'm) \ No newline at end of file diff --git a/sail_latex_riscv/valzadd_bits24373ffc11f289d5bb648df2f4f41b25.tex b/sail_latex_riscv/valzadd_bits24373ffc11f289d5bb648df2f4f41b25.tex new file mode 100644 index 00000000..1e6dd7d0 --- /dev/null +++ b/sail_latex_riscv/valzadd_bits24373ffc11f289d5bb648df2f4f41b25.tex @@ -0,0 +1 @@ +add_bits : forall ('n : Int). (bits('n), bits('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzadd_bits_inta5424052402522ff4653275c899f7543.tex b/sail_latex_riscv/valzadd_bits_inta5424052402522ff4653275c899f7543.tex new file mode 100644 index 00000000..b08b96d2 --- /dev/null +++ b/sail_latex_riscv/valzadd_bits_inta5424052402522ff4653275c899f7543.tex @@ -0,0 +1 @@ +add_bits_int : forall ('n : Int). (bits('n), int) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzadd_intb17710be4fd02ace68d83b9dba907034.tex b/sail_latex_riscv/valzadd_intb17710be4fd02ace68d83b9dba907034.tex new file mode 100644 index 00000000..67398a30 --- /dev/null +++ b/sail_latex_riscv/valzadd_intb17710be4fd02ace68d83b9dba907034.tex @@ -0,0 +1 @@ +add_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_riscv/valzadd_to_tlb39f45d8d071e2986dede49d7c2109cd4f5.tex b/sail_latex_riscv/valzadd_to_tlb39f45d8d071e2986dede49d7c2109cd4f5.tex new file mode 100644 index 00000000..de3a8b62 --- /dev/null +++ b/sail_latex_riscv/valzadd_to_tlb39f45d8d071e2986dede49d7c2109cd4f5.tex @@ -0,0 +1 @@ +add_to_TLB39 : (asid64, vaddr39, paddr64, SV39_PTE, paddr64, nat, bool) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzadd_to_tlb48a08cb99b91f9c80121525cc743b92593.tex b/sail_latex_riscv/valzadd_to_tlb48a08cb99b91f9c80121525cc743b92593.tex new file mode 100644 index 00000000..3d0fae3a --- /dev/null +++ b/sail_latex_riscv/valzadd_to_tlb48a08cb99b91f9c80121525cc743b92593.tex @@ -0,0 +1 @@ +add_to_TLB48 : (asid64, vaddr48, paddr64, SV48_PTE, paddr64, nat, bool) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzaddr_to_tag_addr21cfb55575f4fc24f9ec71484b7d4eb8.tex b/sail_latex_riscv/valzaddr_to_tag_addr21cfb55575f4fc24f9ec71484b7d4eb8.tex new file mode 100644 index 00000000..6638f29d --- /dev/null +++ b/sail_latex_riscv/valzaddr_to_tag_addr21cfb55575f4fc24f9ec71484b7d4eb8.tex @@ -0,0 +1 @@ +addr_to_tag_addr : xlenbits -> tagaddrbits \ No newline at end of file diff --git a/sail_latex_riscv/valzamo_mnemonicac3b9dc5cf93b937e8a5514efa62f568.tex b/sail_latex_riscv/valzamo_mnemonicac3b9dc5cf93b937e8a5514efa62f568.tex new file mode 100644 index 00000000..0ba7874c --- /dev/null +++ b/sail_latex_riscv/valzamo_mnemonicac3b9dc5cf93b937e8a5514efa62f568.tex @@ -0,0 +1 @@ +amo_mnemonic : amoop <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzamoop_of_num66fc14378761bc8bd8137ac63cffe431.tex b/sail_latex_riscv/valzamoop_of_num66fc14378761bc8bd8137ac63cffe431.tex new file mode 100644 index 00000000..d07e5bc0 --- /dev/null +++ b/sail_latex_riscv/valzamoop_of_num66fc14378761bc8bd8137ac63cffe431.tex @@ -0,0 +1 @@ +amoop_of_num : forall ('e : Int), (0 <= 'e & 'e <= 8). int('e) -> amoop \ No newline at end of file diff --git a/sail_latex_riscv/valzand_bool_no_flow5d5041fa8ff689136cdc03e3a11eda3a.tex b/sail_latex_riscv/valzand_bool_no_flow5d5041fa8ff689136cdc03e3a11eda3a.tex new file mode 100644 index 00000000..7de0f497 --- /dev/null +++ b/sail_latex_riscv/valzand_bool_no_flow5d5041fa8ff689136cdc03e3a11eda3a.tex @@ -0,0 +1 @@ +and_bool_no_flow : (bool, bool) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzand_boola4a2cf9ccaa44106300961b15ab20e79.tex b/sail_latex_riscv/valzand_boola4a2cf9ccaa44106300961b15ab20e79.tex new file mode 100644 index 00000000..1840123d --- /dev/null +++ b/sail_latex_riscv/valzand_boola4a2cf9ccaa44106300961b15ab20e79.tex @@ -0,0 +1 @@ +and_bool : forall ('p 'q : Bool). (bool('p), bool('q)) -> bool(('p & 'q)) \ No newline at end of file diff --git a/sail_latex_riscv/valzand_vec99be3fe45d23194b597520c9e407ad35.tex b/sail_latex_riscv/valzand_vec99be3fe45d23194b597520c9e407ad35.tex new file mode 100644 index 00000000..0b8e5e04 --- /dev/null +++ b/sail_latex_riscv/valzand_vec99be3fe45d23194b597520c9e407ad35.tex @@ -0,0 +1 @@ +and_vec : forall ('n : Int). (bits('n), bits('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzany_vector_updatef0077a3dd1846db0e7c8f84fa1a2eed5.tex b/sail_latex_riscv/valzany_vector_updatef0077a3dd1846db0e7c8f84fa1a2eed5.tex new file mode 100644 index 00000000..0d8d35be --- /dev/null +++ b/sail_latex_riscv/valzany_vector_updatef0077a3dd1846db0e7c8f84fa1a2eed5.tex @@ -0,0 +1 @@ +any_vector_update : forall ('n : Int)('a : Type). (vector('n, dec, 'a), int, 'a) -> vector('n, dec, 'a) \ No newline at end of file diff --git a/sail_latex_riscv/valzappend_6433ef192058d4bf5f092d6f8b6d97f4c4.tex b/sail_latex_riscv/valzappend_6433ef192058d4bf5f092d6f8b6d97f4c4.tex new file mode 100644 index 00000000..eccf4152 --- /dev/null +++ b/sail_latex_riscv/valzappend_6433ef192058d4bf5f092d6f8b6d97f4c4.tex @@ -0,0 +1 @@ +append_64 : forall ('n : Int). (bits('n), bits(64)) -> bits('n + 64) \ No newline at end of file diff --git a/sail_latex_riscv/valzaqrl_str43f7a950ecb4ae033c3d54ba744ac285.tex b/sail_latex_riscv/valzaqrl_str43f7a950ecb4ae033c3d54ba744ac285.tex new file mode 100644 index 00000000..9f2e374b --- /dev/null +++ b/sail_latex_riscv/valzaqrl_str43f7a950ecb4ae033c3d54ba744ac285.tex @@ -0,0 +1 @@ +aqrl_str : (bool, bool) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzarch_to_bits5b82edd15605cd21ec0f9d9dc63af541.tex b/sail_latex_riscv/valzarch_to_bits5b82edd15605cd21ec0f9d9dc63af541.tex new file mode 100644 index 00000000..0c3cb30d --- /dev/null +++ b/sail_latex_riscv/valzarch_to_bits5b82edd15605cd21ec0f9d9dc63af541.tex @@ -0,0 +1 @@ +arch_to_bits : Architecture -> arch_xlen \ No newline at end of file diff --git a/sail_latex_riscv/valzarchitecture892e99af11725086f28c1c30cefffa9c.tex b/sail_latex_riscv/valzarchitecture892e99af11725086f28c1c30cefffa9c.tex new file mode 100644 index 00000000..eea9c851 --- /dev/null +++ b/sail_latex_riscv/valzarchitecture892e99af11725086f28c1c30cefffa9c.tex @@ -0,0 +1 @@ +architecture : arch_xlen -> option(Architecture) \ No newline at end of file diff --git a/sail_latex_riscv/valzarchitecture_of_num798cfe8625bb4fedb9343d4984208b4c.tex b/sail_latex_riscv/valzarchitecture_of_num798cfe8625bb4fedb9343d4984208b4c.tex new file mode 100644 index 00000000..21a299bb --- /dev/null +++ b/sail_latex_riscv/valzarchitecture_of_num798cfe8625bb4fedb9343d4984208b4c.tex @@ -0,0 +1 @@ +Architecture_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> Architecture \ No newline at end of file diff --git a/sail_latex_riscv/valzassembly6c256353098ca1294b0a3873338d670c.tex b/sail_latex_riscv/valzassembly6c256353098ca1294b0a3873338d670c.tex new file mode 100644 index 00000000..d100e2dc --- /dev/null +++ b/sail_latex_riscv/valzassembly6c256353098ca1294b0a3873338d670c.tex @@ -0,0 +1 @@ +assembly : ast <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzbit_maybe_iea1ce4e78632791b6873db323516744a.tex b/sail_latex_riscv/valzbit_maybe_iea1ce4e78632791b6873db323516744a.tex new file mode 100644 index 00000000..251e95fd --- /dev/null +++ b/sail_latex_riscv/valzbit_maybe_iea1ce4e78632791b6873db323516744a.tex @@ -0,0 +1 @@ +bit_maybe_i : bitvector(1, dec) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzbit_maybe_oa643ed77970ec3375ca02eb2a3d6d7e3.tex b/sail_latex_riscv/valzbit_maybe_oa643ed77970ec3375ca02eb2a3d6d7e3.tex new file mode 100644 index 00000000..b98bc7f1 --- /dev/null +++ b/sail_latex_riscv/valzbit_maybe_oa643ed77970ec3375ca02eb2a3d6d7e3.tex @@ -0,0 +1 @@ +bit_maybe_o : bitvector(1, dec) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzbit_maybe_r1c52279a1272ff324e99d5b1b65881cd.tex b/sail_latex_riscv/valzbit_maybe_r1c52279a1272ff324e99d5b1b65881cd.tex new file mode 100644 index 00000000..bd2d0d56 --- /dev/null +++ b/sail_latex_riscv/valzbit_maybe_r1c52279a1272ff324e99d5b1b65881cd.tex @@ -0,0 +1 @@ +bit_maybe_r : bitvector(1, dec) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzbit_maybe_w6d81c7531ae5006f39930eecd7114080.tex b/sail_latex_riscv/valzbit_maybe_w6d81c7531ae5006f39930eecd7114080.tex new file mode 100644 index 00000000..8c781016 --- /dev/null +++ b/sail_latex_riscv/valzbit_maybe_w6d81c7531ae5006f39930eecd7114080.tex @@ -0,0 +1 @@ +bit_maybe_w : bitvector(1, dec) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex b/sail_latex_riscv/valzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex new file mode 100644 index 00000000..9268010b --- /dev/null +++ b/sail_latex_riscv/valzbit_to_bool238fffa8d41cb3108fd20322f5500ff3.tex @@ -0,0 +1 @@ +bit_to_bool : bit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzbits_strae053d842c21f0867dea1e830d1773cc.tex b/sail_latex_riscv/valzbits_strae053d842c21f0867dea1e830d1773cc.tex new file mode 100644 index 00000000..eacc131f --- /dev/null +++ b/sail_latex_riscv/valzbits_strae053d842c21f0867dea1e830d1773cc.tex @@ -0,0 +1 @@ +bits_str : forall ('n : Int). bitvector('n, dec) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzbitvector_access8b584ca86770abb6b0da5ef059a02ed9.tex b/sail_latex_riscv/valzbitvector_access8b584ca86770abb6b0da5ef059a02ed9.tex new file mode 100644 index 00000000..626dd0f9 --- /dev/null +++ b/sail_latex_riscv/valzbitvector_access8b584ca86770abb6b0da5ef059a02ed9.tex @@ -0,0 +1 @@ +bitvector_access : forall ('n 'm : Int), (0 <= 'm & 'm < 'n). (bits('n), int('m)) -> bit \ No newline at end of file diff --git a/sail_latex_riscv/valzbitvector_concat6176f8be1468d8779ee8370fd3b4a6e0.tex b/sail_latex_riscv/valzbitvector_concat6176f8be1468d8779ee8370fd3b4a6e0.tex new file mode 100644 index 00000000..2fd31ec8 --- /dev/null +++ b/sail_latex_riscv/valzbitvector_concat6176f8be1468d8779ee8370fd3b4a6e0.tex @@ -0,0 +1 @@ +bitvector_concat : forall ('n 'm : Int). (bits('n), bits('m)) -> bits('n + 'm) \ No newline at end of file diff --git a/sail_latex_riscv/valzbitvector_lengthcd74a5cced7567d19500671e4b6e1031.tex b/sail_latex_riscv/valzbitvector_lengthcd74a5cced7567d19500671e4b6e1031.tex new file mode 100644 index 00000000..1b17c963 --- /dev/null +++ b/sail_latex_riscv/valzbitvector_lengthcd74a5cced7567d19500671e4b6e1031.tex @@ -0,0 +1 @@ +bitvector_length : forall ('n : Int). bits('n) -> int('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzbitvector_update20826799a1ff3ff40895206db0df14bb.tex b/sail_latex_riscv/valzbitvector_update20826799a1ff3ff40895206db0df14bb.tex new file mode 100644 index 00000000..d6e4114f --- /dev/null +++ b/sail_latex_riscv/valzbitvector_update20826799a1ff3ff40895206db0df14bb.tex @@ -0,0 +1 @@ +bitvector_update : forall ('n 'm : Int), (0 <= 'm & 'm < 'n). (bits('n), int('m), bit) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzbool_bitsc0498d89cd314b64ec44bc657a0630ec.tex b/sail_latex_riscv/valzbool_bitsc0498d89cd314b64ec44bc657a0630ec.tex new file mode 100644 index 00000000..e3688f90 --- /dev/null +++ b/sail_latex_riscv/valzbool_bitsc0498d89cd314b64ec44bc657a0630ec.tex @@ -0,0 +1 @@ +bool_bits : bool <-> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valzbool_not_bits8cc7dc8d8a4bcd7dc0a9851db7a322cc.tex b/sail_latex_riscv/valzbool_not_bits8cc7dc8d8a4bcd7dc0a9851db7a322cc.tex new file mode 100644 index 00000000..4d698796 --- /dev/null +++ b/sail_latex_riscv/valzbool_not_bits8cc7dc8d8a4bcd7dc0a9851db7a322cc.tex @@ -0,0 +1 @@ +bool_not_bits : bool <-> bitvector(1, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex b/sail_latex_riscv/valzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex new file mode 100644 index 00000000..4299f74f --- /dev/null +++ b/sail_latex_riscv/valzbool_to_bit5cc99dc0718457cc8a182fa8507f045a.tex @@ -0,0 +1 @@ +bool_to_bit : bool -> bit \ No newline at end of file diff --git a/sail_latex_riscv/valzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex b/sail_latex_riscv/valzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex new file mode 100644 index 00000000..5707b3bd --- /dev/null +++ b/sail_latex_riscv/valzbool_to_bits827ded794caf4c773562dc8baff6a29a.tex @@ -0,0 +1 @@ +bool_to_bits : bool -> bits(1) \ No newline at end of file diff --git a/sail_latex_riscv/valzbop_of_num74cd9479863c5a21d66fa86ae45f1bd5.tex b/sail_latex_riscv/valzbop_of_num74cd9479863c5a21d66fa86ae45f1bd5.tex new file mode 100644 index 00000000..bb27a862 --- /dev/null +++ b/sail_latex_riscv/valzbop_of_num74cd9479863c5a21d66fa86ae45f1bd5.tex @@ -0,0 +1 @@ +bop_of_num : forall ('e : Int), (0 <= 'e & 'e <= 5). int('e) -> bop \ No newline at end of file diff --git a/sail_latex_riscv/valzbtype_mnemonicee542cf061481e1e2c0e4ec1302a928b.tex b/sail_latex_riscv/valzbtype_mnemonicee542cf061481e1e2c0e4ec1302a928b.tex new file mode 100644 index 00000000..9eda65b7 --- /dev/null +++ b/sail_latex_riscv/valzbtype_mnemonicee542cf061481e1e2c0e4ec1302a928b.tex @@ -0,0 +1 @@ +btype_mnemonic : bop <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzcache_op_kind_of_num612a346f1c1edf9d5bae987ac9d9912c.tex b/sail_latex_riscv/valzcache_op_kind_of_num612a346f1c1edf9d5bae987ac9d9912c.tex new file mode 100644 index 00000000..a98cc1af --- /dev/null +++ b/sail_latex_riscv/valzcache_op_kind_of_num612a346f1c1edf9d5bae987ac9d9912c.tex @@ -0,0 +1 @@ +cache_op_kind_of_num : forall ('e : Int), (0 <= 'e & 'e <= 10). int('e) -> cache_op_kind \ No newline at end of file diff --git a/sail_latex_riscv/valzcancel_reservationf12c9af3ed835ad5be485ac1fad8d56f.tex b/sail_latex_riscv/valzcancel_reservationf12c9af3ed835ad5be485ac1fad8d56f.tex new file mode 100644 index 00000000..7ca35794 --- /dev/null +++ b/sail_latex_riscv/valzcancel_reservationf12c9af3ed835ad5be485ac1fad8d56f.tex @@ -0,0 +1 @@ +cancel_reservation : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzcanonical_nan_d7d468e933fb666b50bdf56e90272edf5.tex b/sail_latex_riscv/valzcanonical_nan_d7d468e933fb666b50bdf56e90272edf5.tex new file mode 100644 index 00000000..ae3eac09 --- /dev/null +++ b/sail_latex_riscv/valzcanonical_nan_d7d468e933fb666b50bdf56e90272edf5.tex @@ -0,0 +1 @@ +canonical_NaN_D : unit -> bits(64) \ No newline at end of file diff --git a/sail_latex_riscv/valzcanonical_nan_s21045df28a8988e296d9749590d92369.tex b/sail_latex_riscv/valzcanonical_nan_s21045df28a8988e296d9749590d92369.tex new file mode 100644 index 00000000..10bfe709 --- /dev/null +++ b/sail_latex_riscv/valzcanonical_nan_s21045df28a8988e296d9749590d92369.tex @@ -0,0 +1 @@ +canonical_NaN_S : unit -> bits(32) \ No newline at end of file diff --git a/sail_latex_riscv/valzcap_creg_nameb745905c258c936ba7a6eafe4633359f.tex b/sail_latex_riscv/valzcap_creg_nameb745905c258c936ba7a6eafe4633359f.tex new file mode 100644 index 00000000..20e964d8 --- /dev/null +++ b/sail_latex_riscv/valzcap_creg_nameb745905c258c936ba7a6eafe4633359f.tex @@ -0,0 +1 @@ +cap_creg_name : bitvector(3, dec) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzcap_reg_name2541adc6dad121efe53209371c0fbc68.tex b/sail_latex_riscv/valzcap_reg_name2541adc6dad121efe53209371c0fbc68.tex new file mode 100644 index 00000000..d33c20e3 --- /dev/null +++ b/sail_latex_riscv/valzcap_reg_name2541adc6dad121efe53209371c0fbc68.tex @@ -0,0 +1 @@ +cap_reg_name : bits(5) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzcap_reg_name_abi719d69842e8a63e886ffe0791675d4e0.tex b/sail_latex_riscv/valzcap_reg_name_abi719d69842e8a63e886ffe0791675d4e0.tex new file mode 100644 index 00000000..d5b03c28 --- /dev/null +++ b/sail_latex_riscv/valzcap_reg_name_abi719d69842e8a63e886ffe0791675d4e0.tex @@ -0,0 +1 @@ +cap_reg_name_abi : regidx -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex b/sail_latex_riscv/valzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex new file mode 100644 index 00000000..e687ee6d --- /dev/null +++ b/sail_latex_riscv/valzcapbitstocapability5a9b90d5c99889a6865e9bf96c63fbdd.tex @@ -0,0 +1 @@ +capBitsToCapability : (bool, CapBits) -> Capability \ No newline at end of file diff --git a/sail_latex_riscv/valzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex b/sail_latex_riscv/valzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex new file mode 100644 index 00000000..58cec3b3 --- /dev/null +++ b/sail_latex_riscv/valzcapboundsequal1d03aee0bdb04e1debef609dd2a20edc.tex @@ -0,0 +1 @@ +capBoundsEqual : (Capability, Capability) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex b/sail_latex_riscv/valzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex new file mode 100644 index 00000000..1cf86d76 --- /dev/null +++ b/sail_latex_riscv/valzcapex_of_num5060d93d1da28509784feb6c153b90e3.tex @@ -0,0 +1 @@ +CapEx_of_num : forall ('e : Int), (0 <= 'e & 'e <= 23). int('e) -> CapEx \ No newline at end of file diff --git a/sail_latex_riscv/valzcapexcodee065d40e92bb99703db21c8c18bedf11.tex b/sail_latex_riscv/valzcapexcodee065d40e92bb99703db21c8c18bedf11.tex new file mode 100644 index 00000000..94b547b3 --- /dev/null +++ b/sail_latex_riscv/valzcapexcodee065d40e92bb99703db21c8c18bedf11.tex @@ -0,0 +1 @@ +CapExCode : CapEx -> bits(5) \ No newline at end of file diff --git a/sail_latex_riscv/valzcaptobits025010a6e8c284beecc438f72babcc70.tex b/sail_latex_riscv/valzcaptobits025010a6e8c284beecc438f72babcc70.tex new file mode 100644 index 00000000..0ab3be0d --- /dev/null +++ b/sail_latex_riscv/valzcaptobits025010a6e8c284beecc438f72babcc70.tex @@ -0,0 +1 @@ +capToBits : Capability -> CapBits \ No newline at end of file diff --git a/sail_latex_riscv/valzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex b/sail_latex_riscv/valzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex new file mode 100644 index 00000000..9122e8ed --- /dev/null +++ b/sail_latex_riscv/valzcaptomembitsdd93cf3e1664bb5bed89aa04e4889329.tex @@ -0,0 +1 @@ +capToMemBits : Capability -> CapBits \ No newline at end of file diff --git a/sail_latex_riscv/valzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex b/sail_latex_riscv/valzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex new file mode 100644 index 00000000..561ef879 --- /dev/null +++ b/sail_latex_riscv/valzcaptostring7067e2f1e90748309c77a5de3d661e3d.tex @@ -0,0 +1 @@ +capToString : Capability -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzcheck_counteren24e3081662742c5feea4ad876dc0a51c.tex b/sail_latex_riscv/valzcheck_counteren24e3081662742c5feea4ad876dc0a51c.tex new file mode 100644 index 00000000..9f2abc8d --- /dev/null +++ b/sail_latex_riscv/valzcheck_counteren24e3081662742c5feea4ad876dc0a51c.tex @@ -0,0 +1 @@ +check_Counteren : (csreg, Privilege) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzcheck_csr588ba7a7f36d1f6476f0b3640406ee0a.tex b/sail_latex_riscv/valzcheck_csr588ba7a7f36d1f6476f0b3640406ee0a.tex new file mode 100644 index 00000000..33d2ef85 --- /dev/null +++ b/sail_latex_riscv/valzcheck_csr588ba7a7f36d1f6476f0b3640406ee0a.tex @@ -0,0 +1 @@ +check_CSR : (csreg, Privilege, bool) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzcheck_csr_access77b52cf2ed56bd5489c2fcc29e6efff7.tex b/sail_latex_riscv/valzcheck_csr_access77b52cf2ed56bd5489c2fcc29e6efff7.tex new file mode 100644 index 00000000..c8a08cdc --- /dev/null +++ b/sail_latex_riscv/valzcheck_csr_access77b52cf2ed56bd5489c2fcc29e6efff7.tex @@ -0,0 +1 @@ +check_CSR_access : (csrRW, priv_level, Privilege, bool) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzcheck_misaligned6730e75ccee79325a38a992b6314fd91.tex b/sail_latex_riscv/valzcheck_misaligned6730e75ccee79325a38a992b6314fd91.tex new file mode 100644 index 00000000..72d45404 --- /dev/null +++ b/sail_latex_riscv/valzcheck_misaligned6730e75ccee79325a38a992b6314fd91.tex @@ -0,0 +1 @@ +check_misaligned : (xlenbits, word_width) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzcheck_res_misalignede05ad7adc37fbdff34459806aaddc074.tex b/sail_latex_riscv/valzcheck_res_misalignede05ad7adc37fbdff34459806aaddc074.tex new file mode 100644 index 00000000..83b58041 --- /dev/null +++ b/sail_latex_riscv/valzcheck_res_misalignede05ad7adc37fbdff34459806aaddc074.tex @@ -0,0 +1 @@ +check_res_misaligned : (xlenbits, word_width) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzcheck_tvm_satp8e66c1c4a67c389d24c42619a3634b21.tex b/sail_latex_riscv/valzcheck_tvm_satp8e66c1c4a67c389d24c42619a3634b21.tex new file mode 100644 index 00000000..31bd895b --- /dev/null +++ b/sail_latex_riscv/valzcheck_tvm_satp8e66c1c4a67c389d24c42619a3634b21.tex @@ -0,0 +1 @@ +check_TVM_SATP : (csreg, Privilege) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzchecked_mem_read46a92fcd62c31279edfc3bc18c424fa0.tex b/sail_latex_riscv/valzchecked_mem_read46a92fcd62c31279edfc3bc18c424fa0.tex new file mode 100644 index 00000000..a3654c89 --- /dev/null +++ b/sail_latex_riscv/valzchecked_mem_read46a92fcd62c31279edfc3bc18c424fa0.tex @@ -0,0 +1,2 @@ +checked_mem_read : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (AccessType(ext_access_type), xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta)) \ No newline at end of file diff --git a/sail_latex_riscv/valzchecked_mem_write765e0693788c9f4b01c2243ece39909e.tex b/sail_latex_riscv/valzchecked_mem_write765e0693788c9f4b01c2243ece39909e.tex new file mode 100644 index 00000000..d76edc41 --- /dev/null +++ b/sail_latex_riscv/valzchecked_mem_write765e0693788c9f4b01c2243ece39909e.tex @@ -0,0 +1,2 @@ +checked_mem_write : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (write_kind, xlenbits, int('n), bits(8 * 'n), mem_meta) -> MemoryOpResult(bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzcheckptepermissione94004ed8067442121c54ab1b95848d0.tex b/sail_latex_riscv/valzcheckptepermissione94004ed8067442121c54ab1b95848d0.tex new file mode 100644 index 00000000..7b000cec --- /dev/null +++ b/sail_latex_riscv/valzcheckptepermissione94004ed8067442121c54ab1b95848d0.tex @@ -0,0 +1 @@ +checkPTEPermission : (AccessType(ext_access_type), Privilege, bool, bool, PTE_Bits, extPte, ext_ptw) -> PTE_Check \ No newline at end of file diff --git a/sail_latex_riscv/valzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex b/sail_latex_riscv/valzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex new file mode 100644 index 00000000..b447dfc9 --- /dev/null +++ b/sail_latex_riscv/valzclearregset_of_numcd5fbceac9f286632a9dd1aa0eafe241.tex @@ -0,0 +1 @@ +ClearRegSet_of_num : forall ('e : Int), (0 <= 'e & 'e <= 1). int('e) -> ClearRegSet \ No newline at end of file diff --git a/sail_latex_riscv/valzclint_dispatch8f07ea27f21c1842cfbd7abdf66f1da6.tex b/sail_latex_riscv/valzclint_dispatch8f07ea27f21c1842cfbd7abdf66f1da6.tex new file mode 100644 index 00000000..0cd531ee --- /dev/null +++ b/sail_latex_riscv/valzclint_dispatch8f07ea27f21c1842cfbd7abdf66f1da6.tex @@ -0,0 +1 @@ +clint_dispatch : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzclint_load21de915eadac54aac5354dd7bcbb8d32.tex b/sail_latex_riscv/valzclint_load21de915eadac54aac5354dd7bcbb8d32.tex new file mode 100644 index 00000000..778a8ba5 --- /dev/null +++ b/sail_latex_riscv/valzclint_load21de915eadac54aac5354dd7bcbb8d32.tex @@ -0,0 +1 @@ +clint_load : forall ('n : Int), 'n > 0. (AccessType(ext_access_type), xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n)) \ No newline at end of file diff --git a/sail_latex_riscv/valzclint_store5ac6a4caa2fe222e7b924cd9a27ec52f.tex b/sail_latex_riscv/valzclint_store5ac6a4caa2fe222e7b924cd9a27ec52f.tex new file mode 100644 index 00000000..ef0aaabf --- /dev/null +++ b/sail_latex_riscv/valzclint_store5ac6a4caa2fe222e7b924cd9a27ec52f.tex @@ -0,0 +1 @@ +clint_store : forall ('n : Int), 'n > 0. (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzconcat_str366019c233188ef65ab3d1f977f04112.tex b/sail_latex_riscv/valzconcat_str366019c233188ef65ab3d1f977f04112.tex new file mode 100644 index 00000000..4a38f2a2 --- /dev/null +++ b/sail_latex_riscv/valzconcat_str366019c233188ef65ab3d1f977f04112.tex @@ -0,0 +1 @@ +concat_str : (string, string) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex b/sail_latex_riscv/valzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex new file mode 100644 index 00000000..2daf03b4 --- /dev/null +++ b/sail_latex_riscv/valzconcat_str_bitsd8fc2224310ed49d394cba090cf60741.tex @@ -0,0 +1 @@ +concat_str_bits : forall ('n : Int). (string, bitvector('n, dec)) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex b/sail_latex_riscv/valzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex new file mode 100644 index 00000000..0654a682 --- /dev/null +++ b/sail_latex_riscv/valzconcat_str_dec4a6431591803433e2668ed9b4afaadd0.tex @@ -0,0 +1 @@ +concat_str_dec : (string, int) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzcount_leading_zzeros315ae28f559df1d42a7d2ca4cfff2905.tex b/sail_latex_riscv/valzcount_leading_zzeros315ae28f559df1d42a7d2ca4cfff2905.tex new file mode 100644 index 00000000..9036ecb3 --- /dev/null +++ b/sail_latex_riscv/valzcount_leading_zzeros315ae28f559df1d42a7d2ca4cfff2905.tex @@ -0,0 +1 @@ +count_leading_zeros : forall ('N : Int), 'N >= 1. bits('N) -> {'n, (0 <= 'n & 'n <= 'N). int('n)} \ No newline at end of file diff --git a/sail_latex_riscv/valzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex b/sail_latex_riscv/valzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex new file mode 100644 index 00000000..18dbe4c8 --- /dev/null +++ b/sail_latex_riscv/valzcptrcmpop_of_num73ef06bb0c979dffcf7e6619077debb0.tex @@ -0,0 +1 @@ +CPtrCmpOp_of_num : forall ('e : Int), (0 <= 'e & 'e <= 7). int('e) -> CPtrCmpOp \ No newline at end of file diff --git a/sail_latex_riscv/valzcreg2reg_idxe272195325d960d58ce119619a5a1c75.tex b/sail_latex_riscv/valzcreg2reg_idxe272195325d960d58ce119619a5a1c75.tex new file mode 100644 index 00000000..3822fbb5 --- /dev/null +++ b/sail_latex_riscv/valzcreg2reg_idxe272195325d960d58ce119619a5a1c75.tex @@ -0,0 +1 @@ +creg2reg_idx : cregidx -> regidx \ No newline at end of file diff --git a/sail_latex_riscv/valzcreg_name8aa7dd2adef25f1d7c38341bff05c8a9.tex b/sail_latex_riscv/valzcreg_name8aa7dd2adef25f1d7c38341bff05c8a9.tex new file mode 100644 index 00000000..e8112b43 --- /dev/null +++ b/sail_latex_riscv/valzcreg_name8aa7dd2adef25f1d7c38341bff05c8a9.tex @@ -0,0 +1 @@ +creg_name : bitvector(3, dec) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzcsr_mnemonic3a1dd26f3ac0095deadcf2bffb0adbc8.tex b/sail_latex_riscv/valzcsr_mnemonic3a1dd26f3ac0095deadcf2bffb0adbc8.tex new file mode 100644 index 00000000..39dbcb80 --- /dev/null +++ b/sail_latex_riscv/valzcsr_mnemonic3a1dd26f3ac0095deadcf2bffb0adbc8.tex @@ -0,0 +1 @@ +csr_mnemonic : csrop <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzcsr_name355619c0d72f0a56dfaf2d45f4b72967.tex b/sail_latex_riscv/valzcsr_name355619c0d72f0a56dfaf2d45f4b72967.tex new file mode 100644 index 00000000..a159371c --- /dev/null +++ b/sail_latex_riscv/valzcsr_name355619c0d72f0a56dfaf2d45f4b72967.tex @@ -0,0 +1 @@ +csr_name : csreg -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzcsr_name_map043e1d5f928269d79e6253854765ef21.tex b/sail_latex_riscv/valzcsr_name_map043e1d5f928269d79e6253854765ef21.tex new file mode 100644 index 00000000..5d55fcf6 --- /dev/null +++ b/sail_latex_riscv/valzcsr_name_map043e1d5f928269d79e6253854765ef21.tex @@ -0,0 +1 @@ +csr_name_map : csreg <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzcsraccess68432d7ad570023367f89beb42b653aa.tex b/sail_latex_riscv/valzcsraccess68432d7ad570023367f89beb42b653aa.tex new file mode 100644 index 00000000..cc6de10b --- /dev/null +++ b/sail_latex_riscv/valzcsraccess68432d7ad570023367f89beb42b653aa.tex @@ -0,0 +1 @@ +csrAccess : csreg -> csrRW \ No newline at end of file diff --git a/sail_latex_riscv/valzcsrop_of_numfc0e82db24db14fec87d0613c91892f2.tex b/sail_latex_riscv/valzcsrop_of_numfc0e82db24db14fec87d0613c91892f2.tex new file mode 100644 index 00000000..f42813a3 --- /dev/null +++ b/sail_latex_riscv/valzcsrop_of_numfc0e82db24db14fec87d0613c91892f2.tex @@ -0,0 +1 @@ +csrop_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> csrop \ No newline at end of file diff --git a/sail_latex_riscv/valzcsrprivc196a9e4f8a034a73a295c0ac67907ed.tex b/sail_latex_riscv/valzcsrprivc196a9e4f8a034a73a295c0ac67907ed.tex new file mode 100644 index 00000000..11122493 --- /dev/null +++ b/sail_latex_riscv/valzcsrprivc196a9e4f8a034a73a295c0ac67907ed.tex @@ -0,0 +1 @@ +csrPriv : csreg -> priv_level \ No newline at end of file diff --git a/sail_latex_riscv/valzcur_architecture146db9bbeb421361d412d7f5f7f40511.tex b/sail_latex_riscv/valzcur_architecture146db9bbeb421361d412d7f5f7f40511.tex new file mode 100644 index 00000000..eee3fde1 --- /dev/null +++ b/sail_latex_riscv/valzcur_architecture146db9bbeb421361d412d7f5f7f40511.tex @@ -0,0 +1 @@ +cur_Architecture : unit -> Architecture \ No newline at end of file diff --git a/sail_latex_riscv/valzcurasid32f5f0e43e5813461351dff485d90e4aa4.tex b/sail_latex_riscv/valzcurasid32f5f0e43e5813461351dff485d90e4aa4.tex new file mode 100644 index 00000000..1a49ee66 --- /dev/null +++ b/sail_latex_riscv/valzcurasid32f5f0e43e5813461351dff485d90e4aa4.tex @@ -0,0 +1 @@ +curAsid32 : bits(32) -> asid32 \ No newline at end of file diff --git a/sail_latex_riscv/valzcurasid64b2c4a622c945e46b0aea25ce9a07740f.tex b/sail_latex_riscv/valzcurasid64b2c4a622c945e46b0aea25ce9a07740f.tex new file mode 100644 index 00000000..e6286803 --- /dev/null +++ b/sail_latex_riscv/valzcurasid64b2c4a622c945e46b0aea25ce9a07740f.tex @@ -0,0 +1 @@ +curAsid64 : bits(64) -> asid64 \ No newline at end of file diff --git a/sail_latex_riscv/valzcurptb320f32995fafcf5ebca7eeda72aee3f74f.tex b/sail_latex_riscv/valzcurptb320f32995fafcf5ebca7eeda72aee3f74f.tex new file mode 100644 index 00000000..6be6ae36 --- /dev/null +++ b/sail_latex_riscv/valzcurptb320f32995fafcf5ebca7eeda72aee3f74f.tex @@ -0,0 +1 @@ +curPTB32 : bits(32) -> paddr32 \ No newline at end of file diff --git a/sail_latex_riscv/valzcurptb6479eaa1d344e911b626ff56a8856bcd50.tex b/sail_latex_riscv/valzcurptb6479eaa1d344e911b626ff56a8856bcd50.tex new file mode 100644 index 00000000..922fe31c --- /dev/null +++ b/sail_latex_riscv/valzcurptb6479eaa1d344e911b626ff56a8856bcd50.tex @@ -0,0 +1 @@ +curPTB64 : bits(64) -> paddr64 \ No newline at end of file diff --git a/sail_latex_riscv/valzdec_str7582ccea1482759c248b1f1ac9f6ae63.tex b/sail_latex_riscv/valzdec_str7582ccea1482759c248b1f1ac9f6ae63.tex new file mode 100644 index 00000000..ed6cf9db --- /dev/null +++ b/sail_latex_riscv/valzdec_str7582ccea1482759c248b1f1ac9f6ae63.tex @@ -0,0 +1 @@ +dec_str : int -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzdecimal_string_of_bits7da73b6b29137ed7163460292c5440b0.tex b/sail_latex_riscv/valzdecimal_string_of_bits7da73b6b29137ed7163460292c5440b0.tex new file mode 100644 index 00000000..44c9dc48 --- /dev/null +++ b/sail_latex_riscv/valzdecimal_string_of_bits7da73b6b29137ed7163460292c5440b0.tex @@ -0,0 +1 @@ +decimal_string_of_bits : forall ('n : Int). bits('n) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzdecodec2b8e713fb767e340b7b488fdcba3aab.tex b/sail_latex_riscv/valzdecodec2b8e713fb767e340b7b488fdcba3aab.tex new file mode 100644 index 00000000..625897f1 --- /dev/null +++ b/sail_latex_riscv/valzdecodec2b8e713fb767e340b7b488fdcba3aab.tex @@ -0,0 +1 @@ +decode : bits(32) -> ast \ No newline at end of file diff --git a/sail_latex_riscv/valzdecodecompresseda0c5feab498dd29a69efe0353146e981.tex b/sail_latex_riscv/valzdecodecompresseda0c5feab498dd29a69efe0353146e981.tex new file mode 100644 index 00000000..81f2bfd4 --- /dev/null +++ b/sail_latex_riscv/valzdecodecompresseda0c5feab498dd29a69efe0353146e981.tex @@ -0,0 +1 @@ +decodeCompressed : bits(16) -> ast \ No newline at end of file diff --git a/sail_latex_riscv/valzdef_spc_backwardseab568d1f8e592642bb1655eb934a620.tex b/sail_latex_riscv/valzdef_spc_backwardseab568d1f8e592642bb1655eb934a620.tex new file mode 100644 index 00000000..49e46ab8 --- /dev/null +++ b/sail_latex_riscv/valzdef_spc_backwardseab568d1f8e592642bb1655eb934a620.tex @@ -0,0 +1 @@ +def_spc_backwards : string -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzdef_spc_forwards4eafa854d5b706686aca12e499e738fa.tex b/sail_latex_riscv/valzdef_spc_forwards4eafa854d5b706686aca12e499e738fa.tex new file mode 100644 index 00000000..f8d57009 --- /dev/null +++ b/sail_latex_riscv/valzdef_spc_forwards4eafa854d5b706686aca12e499e738fa.tex @@ -0,0 +1 @@ +def_spc_forwards : unit -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzdef_spc_matches_prefix0e41afd1e8fe11919b3e9439288e00c3.tex b/sail_latex_riscv/valzdef_spc_matches_prefix0e41afd1e8fe11919b3e9439288e00c3.tex new file mode 100644 index 00000000..f16bd9db --- /dev/null +++ b/sail_latex_riscv/valzdef_spc_matches_prefix0e41afd1e8fe11919b3e9439288e00c3.tex @@ -0,0 +1 @@ +def_spc_matches_prefix : string -> option((unit, nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzdef_spce04ebdaa1e0acd4aa4dd3326642e673e.tex b/sail_latex_riscv/valzdef_spce04ebdaa1e0acd4aa4dd3326642e673e.tex new file mode 100644 index 00000000..7e148d74 --- /dev/null +++ b/sail_latex_riscv/valzdef_spce04ebdaa1e0acd4aa4dd3326642e673e.tex @@ -0,0 +1 @@ +def_spc : unit <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzdirty_fd_context8f0fcc8b7745d7294388295307af4058.tex b/sail_latex_riscv/valzdirty_fd_context8f0fcc8b7745d7294388295307af4058.tex new file mode 100644 index 00000000..850af4b7 --- /dev/null +++ b/sail_latex_riscv/valzdirty_fd_context8f0fcc8b7745d7294388295307af4058.tex @@ -0,0 +1 @@ +dirty_fd_context : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzdispatchinterruptaf83562ba97e1882252696fd8999b3e7.tex b/sail_latex_riscv/valzdispatchinterruptaf83562ba97e1882252696fd8999b3e7.tex new file mode 100644 index 00000000..e7d2a9f2 --- /dev/null +++ b/sail_latex_riscv/valzdispatchinterruptaf83562ba97e1882252696fd8999b3e7.tex @@ -0,0 +1 @@ +dispatchInterrupt : Privilege -> option((InterruptType, Privilege)) \ No newline at end of file diff --git a/sail_latex_riscv/valzdzzflagcea95ae2581be09607c095ea1558f21b.tex b/sail_latex_riscv/valzdzzflagcea95ae2581be09607c095ea1558f21b.tex new file mode 100644 index 00000000..c2a68e89 --- /dev/null +++ b/sail_latex_riscv/valzdzzflagcea95ae2581be09607c095ea1558f21b.tex @@ -0,0 +1 @@ +dzFlag : unit -> bits(5) \ No newline at end of file diff --git a/sail_latex_riscv/valzediv_int5aaf4d3d5a3d15a7aebaf90d3bfb6650.tex b/sail_latex_riscv/valzediv_int5aaf4d3d5a3d15a7aebaf90d3bfb6650.tex new file mode 100644 index 00000000..c61a86f5 --- /dev/null +++ b/sail_latex_riscv/valzediv_int5aaf4d3d5a3d15a7aebaf90d3bfb6650.tex @@ -0,0 +1 @@ +ediv_int : forall ('n 'm : Int). (int('n), int('m)) -> int(div('n, 'm)) \ No newline at end of file diff --git a/sail_latex_riscv/valzeffectiveprivilegeb14beb91b9202c1aefb99c45054bcb23.tex b/sail_latex_riscv/valzeffectiveprivilegeb14beb91b9202c1aefb99c45054bcb23.tex new file mode 100644 index 00000000..e6617c9f --- /dev/null +++ b/sail_latex_riscv/valzeffectiveprivilegeb14beb91b9202c1aefb99c45054bcb23.tex @@ -0,0 +1 @@ +effectivePrivilege : (AccessType(ext_access_type), Mstatus, Privilege) -> Privilege \ No newline at end of file diff --git a/sail_latex_riscv/valzelf_entry2a366da786fa7f56d47732b2fddb2821.tex b/sail_latex_riscv/valzelf_entry2a366da786fa7f56d47732b2fddb2821.tex new file mode 100644 index 00000000..a30f7f70 --- /dev/null +++ b/sail_latex_riscv/valzelf_entry2a366da786fa7f56d47732b2fddb2821.tex @@ -0,0 +1 @@ +elf_entry : unit -> int \ No newline at end of file diff --git a/sail_latex_riscv/valzelf_tohost30cafcd41bc201ebfe5bbd0510aa0b7c.tex b/sail_latex_riscv/valzelf_tohost30cafcd41bc201ebfe5bbd0510aa0b7c.tex new file mode 100644 index 00000000..098070de --- /dev/null +++ b/sail_latex_riscv/valzelf_tohost30cafcd41bc201ebfe5bbd0510aa0b7c.tex @@ -0,0 +1 @@ +elf_tohost : unit -> int \ No newline at end of file diff --git a/sail_latex_riscv/valzemod_int8e3d74b3b6a72e24e6bd03570d8e21ba.tex b/sail_latex_riscv/valzemod_int8e3d74b3b6a72e24e6bd03570d8e21ba.tex new file mode 100644 index 00000000..f1269583 --- /dev/null +++ b/sail_latex_riscv/valzemod_int8e3d74b3b6a72e24e6bd03570d8e21ba.tex @@ -0,0 +1 @@ +emod_int : forall ('n 'm : Int). (int('n), int('m)) -> int(mod('n, 'm)) \ No newline at end of file diff --git a/sail_latex_riscv/valzencdec_amoopad56ea38f11b2d2533d3cea1e6e89079.tex b/sail_latex_riscv/valzencdec_amoopad56ea38f11b2d2533d3cea1e6e89079.tex new file mode 100644 index 00000000..a596d9d4 --- /dev/null +++ b/sail_latex_riscv/valzencdec_amoopad56ea38f11b2d2533d3cea1e6e89079.tex @@ -0,0 +1 @@ +encdec_amoop : amoop <-> bitvector(5, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valzencdec_bop37935afdc8fb9d403964a671d7b8ef6f.tex b/sail_latex_riscv/valzencdec_bop37935afdc8fb9d403964a671d7b8ef6f.tex new file mode 100644 index 00000000..1c15c7f3 --- /dev/null +++ b/sail_latex_riscv/valzencdec_bop37935afdc8fb9d403964a671d7b8ef6f.tex @@ -0,0 +1 @@ +encdec_bop : bop <-> bitvector(3, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valzencdec_compressed480f14a33b2969971592c7ca63bcfde9.tex b/sail_latex_riscv/valzencdec_compressed480f14a33b2969971592c7ca63bcfde9.tex new file mode 100644 index 00000000..954922e1 --- /dev/null +++ b/sail_latex_riscv/valzencdec_compressed480f14a33b2969971592c7ca63bcfde9.tex @@ -0,0 +1 @@ +encdec_compressed : ast <-> bits(16) effect {rreg} \ No newline at end of file diff --git a/sail_latex_riscv/valzencdec_csrop402749395fac229088b2e6f6e6206c72.tex b/sail_latex_riscv/valzencdec_csrop402749395fac229088b2e6f6e6206c72.tex new file mode 100644 index 00000000..579b547c --- /dev/null +++ b/sail_latex_riscv/valzencdec_csrop402749395fac229088b2e6f6e6206c72.tex @@ -0,0 +1 @@ +encdec_csrop : csrop <-> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valzencdec_iopdc6254ab3f3dfdad4df376ed9499c048.tex b/sail_latex_riscv/valzencdec_iopdc6254ab3f3dfdad4df376ed9499c048.tex new file mode 100644 index 00000000..3dbdd84e --- /dev/null +++ b/sail_latex_riscv/valzencdec_iopdc6254ab3f3dfdad4df376ed9499c048.tex @@ -0,0 +1 @@ +encdec_iop : iop <-> bitvector(3, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valzencdec_mul_op4fddc1c61135e80f6618dd3c6fca770c.tex b/sail_latex_riscv/valzencdec_mul_op4fddc1c61135e80f6618dd3c6fca770c.tex new file mode 100644 index 00000000..d1508504 --- /dev/null +++ b/sail_latex_riscv/valzencdec_mul_op4fddc1c61135e80f6618dd3c6fca770c.tex @@ -0,0 +1 @@ +encdec_mul_op : (bool, bool, bool) <-> bitvector(3, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valzencdec_rounding_mode4e9de2b381b2971c0047c4587dc1aeff.tex b/sail_latex_riscv/valzencdec_rounding_mode4e9de2b381b2971c0047c4587dc1aeff.tex new file mode 100644 index 00000000..43f67ba0 --- /dev/null +++ b/sail_latex_riscv/valzencdec_rounding_mode4e9de2b381b2971c0047c4587dc1aeff.tex @@ -0,0 +1 @@ +encdec_rounding_mode : rounding_mode <-> bitvector(3, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valzencdec_sop073a7abc17ca60aa3455773907eb78c7.tex b/sail_latex_riscv/valzencdec_sop073a7abc17ca60aa3455773907eb78c7.tex new file mode 100644 index 00000000..4c62dca8 --- /dev/null +++ b/sail_latex_riscv/valzencdec_sop073a7abc17ca60aa3455773907eb78c7.tex @@ -0,0 +1 @@ +encdec_sop : sop <-> bitvector(3, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valzencdec_uop0feeafb72397448d1e686117bd04bd8d.tex b/sail_latex_riscv/valzencdec_uop0feeafb72397448d1e686117bd04bd8d.tex new file mode 100644 index 00000000..e7c673b9 --- /dev/null +++ b/sail_latex_riscv/valzencdec_uop0feeafb72397448d1e686117bd04bd8d.tex @@ -0,0 +1 @@ +encdec_uop : uop <-> bitvector(7, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valzencdeca7ceb0009f9b533ad47d2b69e8881c04.tex b/sail_latex_riscv/valzencdeca7ceb0009f9b533ad47d2b69e8881c04.tex new file mode 100644 index 00000000..cec3a6ce --- /dev/null +++ b/sail_latex_riscv/valzencdeca7ceb0009f9b533ad47d2b69e8881c04.tex @@ -0,0 +1 @@ +encdec : ast <-> bits(32) effect {rreg} \ No newline at end of file diff --git a/sail_latex_riscv/valzeq_anything99dff1d931070d33dac5c755eae24439.tex b/sail_latex_riscv/valzeq_anything99dff1d931070d33dac5c755eae24439.tex new file mode 100644 index 00000000..85bdae62 --- /dev/null +++ b/sail_latex_riscv/valzeq_anything99dff1d931070d33dac5c755eae24439.tex @@ -0,0 +1 @@ +eq_anything : forall ('a : Type). ('a, 'a) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzeq_bit7182cc37406e2c0d4c1e739a98e248ea.tex b/sail_latex_riscv/valzeq_bit7182cc37406e2c0d4c1e739a98e248ea.tex new file mode 100644 index 00000000..6ed18ab3 --- /dev/null +++ b/sail_latex_riscv/valzeq_bit7182cc37406e2c0d4c1e739a98e248ea.tex @@ -0,0 +1 @@ +eq_bit : (bit, bit) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzeq_bits886ce7cf3ec93a28308e8d4e9d63f4be.tex b/sail_latex_riscv/valzeq_bits886ce7cf3ec93a28308e8d4e9d63f4be.tex new file mode 100644 index 00000000..afb10eb0 --- /dev/null +++ b/sail_latex_riscv/valzeq_bits886ce7cf3ec93a28308e8d4e9d63f4be.tex @@ -0,0 +1 @@ +eq_bits : forall ('n : Int). (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzeq_bool0e93587306381c3f984dc7cea6ae190d.tex b/sail_latex_riscv/valzeq_bool0e93587306381c3f984dc7cea6ae190d.tex new file mode 100644 index 00000000..d5ef476b --- /dev/null +++ b/sail_latex_riscv/valzeq_bool0e93587306381c3f984dc7cea6ae190d.tex @@ -0,0 +1 @@ +eq_bool : (bool, bool) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzeq_int364a98dbf8a9faa70e666cce41d8c1aa.tex b/sail_latex_riscv/valzeq_int364a98dbf8a9faa70e666cce41d8c1aa.tex new file mode 100644 index 00000000..7d3ae0f1 --- /dev/null +++ b/sail_latex_riscv/valzeq_int364a98dbf8a9faa70e666cce41d8c1aa.tex @@ -0,0 +1 @@ +eq_int : forall ('n 'm : Int). (int('n), int('m)) -> bool('n == 'm) \ No newline at end of file diff --git a/sail_latex_riscv/valzeq_string75dfa57c0476ae3f43f8e55ffe51a116.tex b/sail_latex_riscv/valzeq_string75dfa57c0476ae3f43f8e55ffe51a116.tex new file mode 100644 index 00000000..d6db7aeb --- /dev/null +++ b/sail_latex_riscv/valzeq_string75dfa57c0476ae3f43f8e55ffe51a116.tex @@ -0,0 +1 @@ +eq_string : (string, string) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzeq_unit996f84433ac0995f4aadfca5b68cd358.tex b/sail_latex_riscv/valzeq_unit996f84433ac0995f4aadfca5b68cd358.tex new file mode 100644 index 00000000..3df558bf --- /dev/null +++ b/sail_latex_riscv/valzeq_unit996f84433ac0995f4aadfca5b68cd358.tex @@ -0,0 +1 @@ +eq_unit : (unit, unit) -> bool(true) \ No newline at end of file diff --git a/sail_latex_riscv/valzexception_delegateefb7e9252abe9f7e50e2f06577208c695.tex b/sail_latex_riscv/valzexception_delegateefb7e9252abe9f7e50e2f06577208c695.tex new file mode 100644 index 00000000..451e767d --- /dev/null +++ b/sail_latex_riscv/valzexception_delegateefb7e9252abe9f7e50e2f06577208c695.tex @@ -0,0 +1 @@ +exception_delegatee : (ExceptionType, Privilege) -> Privilege \ No newline at end of file diff --git a/sail_latex_riscv/valzexception_handlerf03729146a8718cee62ce35044e16202.tex b/sail_latex_riscv/valzexception_handlerf03729146a8718cee62ce35044e16202.tex new file mode 100644 index 00000000..45ecb8d9 --- /dev/null +++ b/sail_latex_riscv/valzexception_handlerf03729146a8718cee62ce35044e16202.tex @@ -0,0 +1 @@ +exception_handler : (Privilege, ctl_result, xlenbits) -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzexceptiontype_to_bits6edc76877c2677590096c351d9b431f1.tex b/sail_latex_riscv/valzexceptiontype_to_bits6edc76877c2677590096c351d9b431f1.tex new file mode 100644 index 00000000..209eb6b7 --- /dev/null +++ b/sail_latex_riscv/valzexceptiontype_to_bits6edc76877c2677590096c351d9b431f1.tex @@ -0,0 +1 @@ +exceptionType_to_bits : ExceptionType -> exc_code \ No newline at end of file diff --git a/sail_latex_riscv/valzexceptiontype_to_str566b70f16fdf6ed4d1850ec75465ec4b.tex b/sail_latex_riscv/valzexceptiontype_to_str566b70f16fdf6ed4d1850ec75465ec4b.tex new file mode 100644 index 00000000..3721dd38 --- /dev/null +++ b/sail_latex_riscv/valzexceptiontype_to_str566b70f16fdf6ed4d1850ec75465ec4b.tex @@ -0,0 +1 @@ +exceptionType_to_str : ExceptionType -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzexecute33a689e3a631b9b905b85461d3814943.tex b/sail_latex_riscv/valzexecute33a689e3a631b9b905b85461d3814943.tex new file mode 100644 index 00000000..d552435e --- /dev/null +++ b/sail_latex_riscv/valzexecute33a689e3a631b9b905b85461d3814943.tex @@ -0,0 +1 @@ +execute : ast -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzext_access_type_of_num6a15c4e70d2e9820f649a1cc6760e30a.tex b/sail_latex_riscv/valzext_access_type_of_num6a15c4e70d2e9820f649a1cc6760e30a.tex new file mode 100644 index 00000000..7dfc45a2 --- /dev/null +++ b/sail_latex_riscv/valzext_access_type_of_num6a15c4e70d2e9820f649a1cc6760e30a.tex @@ -0,0 +1 @@ +ext_access_type_of_num : forall ('e : Int), (0 <= 'e & 'e <= 1). int('e) -> ext_access_type \ No newline at end of file diff --git a/sail_latex_riscv/valzext_check_csr_fail991cc4645a62a48eb645391d3988288a.tex b/sail_latex_riscv/valzext_check_csr_fail991cc4645a62a48eb645391d3988288a.tex new file mode 100644 index 00000000..3756e7b5 --- /dev/null +++ b/sail_latex_riscv/valzext_check_csr_fail991cc4645a62a48eb645391d3988288a.tex @@ -0,0 +1 @@ +ext_check_CSR_fail : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzext_check_csreef82c82c124fe04d74fc6fd8219bb68.tex b/sail_latex_riscv/valzext_check_csreef82c82c124fe04d74fc6fd8219bb68.tex new file mode 100644 index 00000000..db0a9465 --- /dev/null +++ b/sail_latex_riscv/valzext_check_csreef82c82c124fe04d74fc6fd8219bb68.tex @@ -0,0 +1 @@ +ext_check_CSR : (bits(12), Privilege, bool) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzext_check_xret_priv92677d070503a361c4ac308adba53957.tex b/sail_latex_riscv/valzext_check_xret_priv92677d070503a361c4ac308adba53957.tex new file mode 100644 index 00000000..06670379 --- /dev/null +++ b/sail_latex_riscv/valzext_check_xret_priv92677d070503a361c4ac308adba53957.tex @@ -0,0 +1 @@ +ext_check_xret_priv : Privilege -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzext_control_check_addr2d404fc3390578d569e3f547f0d18fce.tex b/sail_latex_riscv/valzext_control_check_addr2d404fc3390578d569e3f547f0d18fce.tex new file mode 100644 index 00000000..82e74b64 --- /dev/null +++ b/sail_latex_riscv/valzext_control_check_addr2d404fc3390578d569e3f547f0d18fce.tex @@ -0,0 +1 @@ +ext_control_check_addr : xlenbits -> Ext_ControlAddr_Check(ext_control_addr_error) \ No newline at end of file diff --git a/sail_latex_riscv/valzext_control_check_pc92c2579f955b827738ac1e5c79b85839.tex b/sail_latex_riscv/valzext_control_check_pc92c2579f955b827738ac1e5c79b85839.tex new file mode 100644 index 00000000..111121bd --- /dev/null +++ b/sail_latex_riscv/valzext_control_check_pc92c2579f955b827738ac1e5c79b85839.tex @@ -0,0 +1 @@ +ext_control_check_pc : xlenbits -> Ext_ControlAddr_Check(ext_control_addr_error) \ No newline at end of file diff --git a/sail_latex_riscv/valzext_data_get_addra719d6978c6003ef3b6e2e57ccbf64b8.tex b/sail_latex_riscv/valzext_data_get_addra719d6978c6003ef3b6e2e57ccbf64b8.tex new file mode 100644 index 00000000..cb0ea3b1 --- /dev/null +++ b/sail_latex_riscv/valzext_data_get_addra719d6978c6003ef3b6e2e57ccbf64b8.tex @@ -0,0 +1 @@ +ext_data_get_addr : (regidx, xlenbits, AccessType(ext_access_type), word_width) -> Ext_DataAddr_Check(ext_data_addr_error) \ No newline at end of file diff --git a/sail_latex_riscv/valzext_exc_type_of_numa5807bd3284ecfd6e2edf0e304dee26e.tex b/sail_latex_riscv/valzext_exc_type_of_numa5807bd3284ecfd6e2edf0e304dee26e.tex new file mode 100644 index 00000000..c08af57b --- /dev/null +++ b/sail_latex_riscv/valzext_exc_type_of_numa5807bd3284ecfd6e2edf0e304dee26e.tex @@ -0,0 +1 @@ +ext_exc_type_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> ext_exc_type \ No newline at end of file diff --git a/sail_latex_riscv/valzext_exc_type_to_bitse12334413f8dedca96749d4413e3150b.tex b/sail_latex_riscv/valzext_exc_type_to_bitse12334413f8dedca96749d4413e3150b.tex new file mode 100644 index 00000000..7587a05f --- /dev/null +++ b/sail_latex_riscv/valzext_exc_type_to_bitse12334413f8dedca96749d4413e3150b.tex @@ -0,0 +1 @@ +ext_exc_type_to_bits : ext_exc_type -> exc_code \ No newline at end of file diff --git a/sail_latex_riscv/valzext_exc_type_to_strc4b005a75959aeec9fce26f39219c666.tex b/sail_latex_riscv/valzext_exc_type_to_strc4b005a75959aeec9fce26f39219c666.tex new file mode 100644 index 00000000..f01b3f46 --- /dev/null +++ b/sail_latex_riscv/valzext_exc_type_to_strc4b005a75959aeec9fce26f39219c666.tex @@ -0,0 +1 @@ +ext_exc_type_to_str : ext_exc_type -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzext_fail_xret_priva071b88d32f48ad8e720a4cae916da8b.tex b/sail_latex_riscv/valzext_fail_xret_priva071b88d32f48ad8e720a4cae916da8b.tex new file mode 100644 index 00000000..d9480756 --- /dev/null +++ b/sail_latex_riscv/valzext_fail_xret_priva071b88d32f48ad8e720a4cae916da8b.tex @@ -0,0 +1 @@ +ext_fail_xret_priv : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzext_fetch_check_pc2e82f09c4f4da5465b70e5f9e6f48b77.tex b/sail_latex_riscv/valzext_fetch_check_pc2e82f09c4f4da5465b70e5f9e6f48b77.tex new file mode 100644 index 00000000..148c9787 --- /dev/null +++ b/sail_latex_riscv/valzext_fetch_check_pc2e82f09c4f4da5465b70e5f9e6f48b77.tex @@ -0,0 +1 @@ +ext_fetch_check_pc : (xlenbits, xlenbits) -> Ext_FetchAddr_Check(ext_fetch_addr_error) \ No newline at end of file diff --git a/sail_latex_riscv/valzext_fetch_hookb78ddd15c7be769c4a0783ef122b9767.tex b/sail_latex_riscv/valzext_fetch_hookb78ddd15c7be769c4a0783ef122b9767.tex new file mode 100644 index 00000000..538d72d0 --- /dev/null +++ b/sail_latex_riscv/valzext_fetch_hookb78ddd15c7be769c4a0783ef122b9767.tex @@ -0,0 +1 @@ +ext_fetch_hook : FetchResult -> FetchResult \ No newline at end of file diff --git a/sail_latex_riscv/valzext_get_ptw_errorb38503fe4519ddae4ed13f9933d3c0a5.tex b/sail_latex_riscv/valzext_get_ptw_errorb38503fe4519ddae4ed13f9933d3c0a5.tex new file mode 100644 index 00000000..bea25611 --- /dev/null +++ b/sail_latex_riscv/valzext_get_ptw_errorb38503fe4519ddae4ed13f9933d3c0a5.tex @@ -0,0 +1 @@ +ext_get_ptw_error : ext_ptw_fail -> PTW_Error \ No newline at end of file diff --git a/sail_latex_riscv/valzext_handle_control_check_error7b80ca54e4133f98238aa5f1371bfc1f.tex b/sail_latex_riscv/valzext_handle_control_check_error7b80ca54e4133f98238aa5f1371bfc1f.tex new file mode 100644 index 00000000..6881d1a1 --- /dev/null +++ b/sail_latex_riscv/valzext_handle_control_check_error7b80ca54e4133f98238aa5f1371bfc1f.tex @@ -0,0 +1 @@ +ext_handle_control_check_error : ext_control_addr_error -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzext_handle_data_check_errorad2507fc7050fbd24451608767d75b73.tex b/sail_latex_riscv/valzext_handle_data_check_errorad2507fc7050fbd24451608767d75b73.tex new file mode 100644 index 00000000..c3b6eb0c --- /dev/null +++ b/sail_latex_riscv/valzext_handle_data_check_errorad2507fc7050fbd24451608767d75b73.tex @@ -0,0 +1 @@ +ext_handle_data_check_error : ext_data_addr_error -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzext_handle_fetch_check_error1c773c1438a4c5dcc256df216f0a1aa9.tex b/sail_latex_riscv/valzext_handle_fetch_check_error1c773c1438a4c5dcc256df216f0a1aa9.tex new file mode 100644 index 00000000..4887094a --- /dev/null +++ b/sail_latex_riscv/valzext_handle_fetch_check_error1c773c1438a4c5dcc256df216f0a1aa9.tex @@ -0,0 +1 @@ +ext_handle_fetch_check_error : ext_fetch_addr_error -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzext_init_regs1d9ff00ce58fd5712eb26190e338015a.tex b/sail_latex_riscv/valzext_init_regs1d9ff00ce58fd5712eb26190e338015a.tex new file mode 100644 index 00000000..9b2eb41e --- /dev/null +++ b/sail_latex_riscv/valzext_init_regs1d9ff00ce58fd5712eb26190e338015a.tex @@ -0,0 +1 @@ +ext_init_regs : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzext_initaf8e3807fa5c1bbef01331f40e0f99a4.tex b/sail_latex_riscv/valzext_initaf8e3807fa5c1bbef01331f40e0f99a4.tex new file mode 100644 index 00000000..16bc9156 --- /dev/null +++ b/sail_latex_riscv/valzext_initaf8e3807fa5c1bbef01331f40e0f99a4.tex @@ -0,0 +1 @@ +ext_init : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex b/sail_latex_riscv/valzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex new file mode 100644 index 00000000..fa8c89f1 --- /dev/null +++ b/sail_latex_riscv/valzext_is_csr_defined3e2540173eaa97b3902070bdfa6d0f6f.tex @@ -0,0 +1 @@ +ext_is_CSR_defined : (csreg, Privilege) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzext_post_decode_hook0ea81b52fdd64a9c28fe27bce7cc93bb.tex b/sail_latex_riscv/valzext_post_decode_hook0ea81b52fdd64a9c28fe27bce7cc93bb.tex new file mode 100644 index 00000000..99b88d8e --- /dev/null +++ b/sail_latex_riscv/valzext_post_decode_hook0ea81b52fdd64a9c28fe27bce7cc93bb.tex @@ -0,0 +1 @@ +ext_post_decode_hook : ast -> ast \ No newline at end of file diff --git a/sail_latex_riscv/valzext_post_step_hook12041b61939f7dc96fabf0eb4cecd40e.tex b/sail_latex_riscv/valzext_post_step_hook12041b61939f7dc96fabf0eb4cecd40e.tex new file mode 100644 index 00000000..2dfaec1c --- /dev/null +++ b/sail_latex_riscv/valzext_post_step_hook12041b61939f7dc96fabf0eb4cecd40e.tex @@ -0,0 +1 @@ +ext_post_step_hook : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzext_pre_step_hookbaa423b1418b5f3048ae14ba522eabb5.tex b/sail_latex_riscv/valzext_pre_step_hookbaa423b1418b5f3048ae14ba522eabb5.tex new file mode 100644 index 00000000..8ce78b6b --- /dev/null +++ b/sail_latex_riscv/valzext_pre_step_hookbaa423b1418b5f3048ae14ba522eabb5.tex @@ -0,0 +1 @@ +ext_pre_step_hook : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzext_ptw_error_of_num6c265a5359168121d0772efe3f31cd45.tex b/sail_latex_riscv/valzext_ptw_error_of_num6c265a5359168121d0772efe3f31cd45.tex new file mode 100644 index 00000000..5be23438 --- /dev/null +++ b/sail_latex_riscv/valzext_ptw_error_of_num6c265a5359168121d0772efe3f31cd45.tex @@ -0,0 +1 @@ +ext_ptw_error_of_num : forall ('e : Int), (0 <= 'e & 'e <= 0). int('e) -> ext_ptw_error \ No newline at end of file diff --git a/sail_latex_riscv/valzext_ptw_fail_of_numcc5cb6ad05de49125f246aa8627fb15b.tex b/sail_latex_riscv/valzext_ptw_fail_of_numcc5cb6ad05de49125f246aa8627fb15b.tex new file mode 100644 index 00000000..56b34ee8 --- /dev/null +++ b/sail_latex_riscv/valzext_ptw_fail_of_numcc5cb6ad05de49125f246aa8627fb15b.tex @@ -0,0 +1 @@ +ext_ptw_fail_of_num : forall ('e : Int), (0 <= 'e & 'e <= 1). int('e) -> ext_ptw_fail \ No newline at end of file diff --git a/sail_latex_riscv/valzext_ptw_lc_joindc735a27ea989374f5eabf813141d337.tex b/sail_latex_riscv/valzext_ptw_lc_joindc735a27ea989374f5eabf813141d337.tex new file mode 100644 index 00000000..589507da --- /dev/null +++ b/sail_latex_riscv/valzext_ptw_lc_joindc735a27ea989374f5eabf813141d337.tex @@ -0,0 +1 @@ +ext_ptw_lc_join : (ext_ptw, ext_ptw_lc) -> ext_ptw \ No newline at end of file diff --git a/sail_latex_riscv/valzext_ptw_lc_of_numfefbb86ad247369523da5c5114df83a8.tex b/sail_latex_riscv/valzext_ptw_lc_of_numfefbb86ad247369523da5c5114df83a8.tex new file mode 100644 index 00000000..2162c4c5 --- /dev/null +++ b/sail_latex_riscv/valzext_ptw_lc_of_numfefbb86ad247369523da5c5114df83a8.tex @@ -0,0 +1 @@ +ext_ptw_lc_of_num : forall ('e : Int), (0 <= 'e & 'e <= 1). int('e) -> ext_ptw_lc \ No newline at end of file diff --git a/sail_latex_riscv/valzext_ptw_sc_join88636243b559a2aba809497742e7ce00.tex b/sail_latex_riscv/valzext_ptw_sc_join88636243b559a2aba809497742e7ce00.tex new file mode 100644 index 00000000..949f7476 --- /dev/null +++ b/sail_latex_riscv/valzext_ptw_sc_join88636243b559a2aba809497742e7ce00.tex @@ -0,0 +1 @@ +ext_ptw_sc_join : (ext_ptw, ext_ptw_sc) -> ext_ptw \ No newline at end of file diff --git a/sail_latex_riscv/valzext_ptw_sc_of_num2137f22f5407b82d12c8574662600e18.tex b/sail_latex_riscv/valzext_ptw_sc_of_num2137f22f5407b82d12c8574662600e18.tex new file mode 100644 index 00000000..f7d2586d --- /dev/null +++ b/sail_latex_riscv/valzext_ptw_sc_of_num2137f22f5407b82d12c8574662600e18.tex @@ -0,0 +1 @@ +ext_ptw_sc_of_num : forall ('e : Int), (0 <= 'e & 'e <= 1). int('e) -> ext_ptw_sc \ No newline at end of file diff --git a/sail_latex_riscv/valzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex b/sail_latex_riscv/valzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex new file mode 100644 index 00000000..56b16980 --- /dev/null +++ b/sail_latex_riscv/valzext_read_csr8af202f75b7d6e7536c08d920bd54264.tex @@ -0,0 +1 @@ +ext_read_CSR : csreg -> option(xlenbits) \ No newline at end of file diff --git a/sail_latex_riscv/valzext_rvfi_init925272b6b4282430111c3e89a50f1e0b.tex b/sail_latex_riscv/valzext_rvfi_init925272b6b4282430111c3e89a50f1e0b.tex new file mode 100644 index 00000000..db3e16f9 --- /dev/null +++ b/sail_latex_riscv/valzext_rvfi_init925272b6b4282430111c3e89a50f1e0b.tex @@ -0,0 +1 @@ +ext_rvfi_init : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzext_veto_disable_cd10c2d1c5077060fa007c1628d7aaa8c.tex b/sail_latex_riscv/valzext_veto_disable_cd10c2d1c5077060fa007c1628d7aaa8c.tex new file mode 100644 index 00000000..1d66e7cd --- /dev/null +++ b/sail_latex_riscv/valzext_veto_disable_cd10c2d1c5077060fa007c1628d7aaa8c.tex @@ -0,0 +1 @@ +ext_veto_disable_C : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex b/sail_latex_riscv/valzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex new file mode 100644 index 00000000..df6e1cbc --- /dev/null +++ b/sail_latex_riscv/valzext_write_csrea3e63f4d0be7079660a260c43b112cd.tex @@ -0,0 +1 @@ +ext_write_CSR : (csreg, xlenbits) -> option(xlenbits) \ No newline at end of file diff --git a/sail_latex_riscv/valzext_write_fcsr8225c20959aaf9205d48c42ffe341a87.tex b/sail_latex_riscv/valzext_write_fcsr8225c20959aaf9205d48c42ffe341a87.tex new file mode 100644 index 00000000..90ca84e5 --- /dev/null +++ b/sail_latex_riscv/valzext_write_fcsr8225c20959aaf9205d48c42ffe341a87.tex @@ -0,0 +1 @@ +ext_write_fcsr : (bits(3), bits(5)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextend_value8ddb26f3f92f6848beaff0fbcaa992f6.tex b/sail_latex_riscv/valzextend_value8ddb26f3f92f6848beaff0fbcaa992f6.tex new file mode 100644 index 00000000..c2ab7869 --- /dev/null +++ b/sail_latex_riscv/valzextend_value8ddb26f3f92f6848beaff0fbcaa992f6.tex @@ -0,0 +1,2 @@ +extend_value : forall ('n : Int), (0 < 'n & 'n <= xlen_bytes). + (bool, MemoryOpResult(bits(8 * 'n))) -> MemoryOpResult(xlenbits) \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32add6570d62f364513d11456621384cd41a4.tex b/sail_latex_riscv/valzextern_f32add6570d62f364513d11456621384cd41a4.tex new file mode 100644 index 00000000..346a05ca --- /dev/null +++ b/sail_latex_riscv/valzextern_f32add6570d62f364513d11456621384cd41a4.tex @@ -0,0 +1 @@ +extern_f32Add : (bits_rm, bits_S, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32diva3f93b8d1944c9eb5853444ef6275b73.tex b/sail_latex_riscv/valzextern_f32diva3f93b8d1944c9eb5853444ef6275b73.tex new file mode 100644 index 00000000..2634b6a5 --- /dev/null +++ b/sail_latex_riscv/valzextern_f32diva3f93b8d1944c9eb5853444ef6275b73.tex @@ -0,0 +1 @@ +extern_f32Div : (bits_rm, bits_S, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32eq1152b8b8a8d02d885ad3651e36443f8b.tex b/sail_latex_riscv/valzextern_f32eq1152b8b8a8d02d885ad3651e36443f8b.tex new file mode 100644 index 00000000..0700db71 --- /dev/null +++ b/sail_latex_riscv/valzextern_f32eq1152b8b8a8d02d885ad3651e36443f8b.tex @@ -0,0 +1 @@ +extern_f32Eq : (bits_S, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32le97e1d493296eff955b8dd2b74525e2ad.tex b/sail_latex_riscv/valzextern_f32le97e1d493296eff955b8dd2b74525e2ad.tex new file mode 100644 index 00000000..3a4763a7 --- /dev/null +++ b/sail_latex_riscv/valzextern_f32le97e1d493296eff955b8dd2b74525e2ad.tex @@ -0,0 +1 @@ +extern_f32Le : (bits_S, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32lt76345a6740b5e66e208ded2a17434c50.tex b/sail_latex_riscv/valzextern_f32lt76345a6740b5e66e208ded2a17434c50.tex new file mode 100644 index 00000000..bf187b61 --- /dev/null +++ b/sail_latex_riscv/valzextern_f32lt76345a6740b5e66e208ded2a17434c50.tex @@ -0,0 +1 @@ +extern_f32Lt : (bits_S, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32mul3fa5520c02f9481c619db6b9185fc991.tex b/sail_latex_riscv/valzextern_f32mul3fa5520c02f9481c619db6b9185fc991.tex new file mode 100644 index 00000000..0737e59e --- /dev/null +++ b/sail_latex_riscv/valzextern_f32mul3fa5520c02f9481c619db6b9185fc991.tex @@ -0,0 +1 @@ +extern_f32Mul : (bits_rm, bits_S, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32muladd83ecaa2576af176cb966151d8adbd0ae.tex b/sail_latex_riscv/valzextern_f32muladd83ecaa2576af176cb966151d8adbd0ae.tex new file mode 100644 index 00000000..b70f2cb8 --- /dev/null +++ b/sail_latex_riscv/valzextern_f32muladd83ecaa2576af176cb966151d8adbd0ae.tex @@ -0,0 +1 @@ +extern_f32MulAdd : (bits_rm, bits_S, bits_S, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32sqrtf11b42be8c2478d6f003de6a9af154f6.tex b/sail_latex_riscv/valzextern_f32sqrtf11b42be8c2478d6f003de6a9af154f6.tex new file mode 100644 index 00000000..ef4e84b2 --- /dev/null +++ b/sail_latex_riscv/valzextern_f32sqrtf11b42be8c2478d6f003de6a9af154f6.tex @@ -0,0 +1 @@ +extern_f32Sqrt : (bits_rm, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32sub46595a3cbe22b28fcde81c3635052d96.tex b/sail_latex_riscv/valzextern_f32sub46595a3cbe22b28fcde81c3635052d96.tex new file mode 100644 index 00000000..91709714 --- /dev/null +++ b/sail_latex_riscv/valzextern_f32sub46595a3cbe22b28fcde81c3635052d96.tex @@ -0,0 +1 @@ +extern_f32Sub : (bits_rm, bits_S, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32tof64195ee529424460f0ea430364e6969b58.tex b/sail_latex_riscv/valzextern_f32tof64195ee529424460f0ea430364e6969b58.tex new file mode 100644 index 00000000..cb495f03 --- /dev/null +++ b/sail_latex_riscv/valzextern_f32tof64195ee529424460f0ea430364e6969b58.tex @@ -0,0 +1 @@ +extern_f32ToF64 : (bits_rm, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32toi326cf4b3bab68206b610e134ff8908ca89.tex b/sail_latex_riscv/valzextern_f32toi326cf4b3bab68206b610e134ff8908ca89.tex new file mode 100644 index 00000000..48e0177c --- /dev/null +++ b/sail_latex_riscv/valzextern_f32toi326cf4b3bab68206b610e134ff8908ca89.tex @@ -0,0 +1 @@ +extern_f32ToI32 : (bits_rm, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32toi640b3f54fe8e434e95ad11bc87f4692a8c.tex b/sail_latex_riscv/valzextern_f32toi640b3f54fe8e434e95ad11bc87f4692a8c.tex new file mode 100644 index 00000000..aa80a62f --- /dev/null +++ b/sail_latex_riscv/valzextern_f32toi640b3f54fe8e434e95ad11bc87f4692a8c.tex @@ -0,0 +1 @@ +extern_f32ToI64 : (bits_rm, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32toui3254cab07407e1a29139940b162c1c3d28.tex b/sail_latex_riscv/valzextern_f32toui3254cab07407e1a29139940b162c1c3d28.tex new file mode 100644 index 00000000..a2e4ad92 --- /dev/null +++ b/sail_latex_riscv/valzextern_f32toui3254cab07407e1a29139940b162c1c3d28.tex @@ -0,0 +1 @@ +extern_f32ToUi32 : (bits_rm, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f32toui6494114a44e0de80b91ab99de5cb70ae02.tex b/sail_latex_riscv/valzextern_f32toui6494114a44e0de80b91ab99de5cb70ae02.tex new file mode 100644 index 00000000..63585a75 --- /dev/null +++ b/sail_latex_riscv/valzextern_f32toui6494114a44e0de80b91ab99de5cb70ae02.tex @@ -0,0 +1 @@ +extern_f32ToUi64 : (bits_rm, bits_S) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64addeb106f14f2c0905dadf390a0565da932.tex b/sail_latex_riscv/valzextern_f64addeb106f14f2c0905dadf390a0565da932.tex new file mode 100644 index 00000000..d0da3ed1 --- /dev/null +++ b/sail_latex_riscv/valzextern_f64addeb106f14f2c0905dadf390a0565da932.tex @@ -0,0 +1 @@ +extern_f64Add : (bits_rm, bits_D, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64div5b9c0428c30d14b1844b77539325cd9e.tex b/sail_latex_riscv/valzextern_f64div5b9c0428c30d14b1844b77539325cd9e.tex new file mode 100644 index 00000000..fb37c7bb --- /dev/null +++ b/sail_latex_riscv/valzextern_f64div5b9c0428c30d14b1844b77539325cd9e.tex @@ -0,0 +1 @@ +extern_f64Div : (bits_rm, bits_D, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64eqb2180e00de7f0745336b1c04e9ead3f3.tex b/sail_latex_riscv/valzextern_f64eqb2180e00de7f0745336b1c04e9ead3f3.tex new file mode 100644 index 00000000..bec90e2a --- /dev/null +++ b/sail_latex_riscv/valzextern_f64eqb2180e00de7f0745336b1c04e9ead3f3.tex @@ -0,0 +1 @@ +extern_f64Eq : (bits_D, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64le607de75fdc830000d71db4eee82f8025.tex b/sail_latex_riscv/valzextern_f64le607de75fdc830000d71db4eee82f8025.tex new file mode 100644 index 00000000..7a805e5a --- /dev/null +++ b/sail_latex_riscv/valzextern_f64le607de75fdc830000d71db4eee82f8025.tex @@ -0,0 +1 @@ +extern_f64Le : (bits_D, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64lt9068248c1389b86f906917568fb33729.tex b/sail_latex_riscv/valzextern_f64lt9068248c1389b86f906917568fb33729.tex new file mode 100644 index 00000000..9aa32025 --- /dev/null +++ b/sail_latex_riscv/valzextern_f64lt9068248c1389b86f906917568fb33729.tex @@ -0,0 +1 @@ +extern_f64Lt : (bits_D, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64muladd15243cc8731c3e0a2ef0ef7f3ed15e68.tex b/sail_latex_riscv/valzextern_f64muladd15243cc8731c3e0a2ef0ef7f3ed15e68.tex new file mode 100644 index 00000000..9d3d42ee --- /dev/null +++ b/sail_latex_riscv/valzextern_f64muladd15243cc8731c3e0a2ef0ef7f3ed15e68.tex @@ -0,0 +1 @@ +extern_f64MulAdd : (bits_rm, bits_D, bits_D, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64mulf814ecd2e3d0ed473f76dcca74bd1c73.tex b/sail_latex_riscv/valzextern_f64mulf814ecd2e3d0ed473f76dcca74bd1c73.tex new file mode 100644 index 00000000..b92ac6f6 --- /dev/null +++ b/sail_latex_riscv/valzextern_f64mulf814ecd2e3d0ed473f76dcca74bd1c73.tex @@ -0,0 +1 @@ +extern_f64Mul : (bits_rm, bits_D, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64sqrta3145a122395bda30fb542d678fd4539.tex b/sail_latex_riscv/valzextern_f64sqrta3145a122395bda30fb542d678fd4539.tex new file mode 100644 index 00000000..f9a823f3 --- /dev/null +++ b/sail_latex_riscv/valzextern_f64sqrta3145a122395bda30fb542d678fd4539.tex @@ -0,0 +1 @@ +extern_f64Sqrt : (bits_rm, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64subd720cdc7595c5e294f7877ef74876c27.tex b/sail_latex_riscv/valzextern_f64subd720cdc7595c5e294f7877ef74876c27.tex new file mode 100644 index 00000000..523a00b0 --- /dev/null +++ b/sail_latex_riscv/valzextern_f64subd720cdc7595c5e294f7877ef74876c27.tex @@ -0,0 +1 @@ +extern_f64Sub : (bits_rm, bits_D, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64tof329e6bdb39c58bf46aad8078a255a69675.tex b/sail_latex_riscv/valzextern_f64tof329e6bdb39c58bf46aad8078a255a69675.tex new file mode 100644 index 00000000..1e540de6 --- /dev/null +++ b/sail_latex_riscv/valzextern_f64tof329e6bdb39c58bf46aad8078a255a69675.tex @@ -0,0 +1 @@ +extern_f64ToF32 : (bits_rm, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64toi328ccd500b2d8a0508350bd93919a71172.tex b/sail_latex_riscv/valzextern_f64toi328ccd500b2d8a0508350bd93919a71172.tex new file mode 100644 index 00000000..47ae8c3c --- /dev/null +++ b/sail_latex_riscv/valzextern_f64toi328ccd500b2d8a0508350bd93919a71172.tex @@ -0,0 +1 @@ +extern_f64ToI32 : (bits_rm, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64toi641dd890d7fbf7a24774c052a9c246250f.tex b/sail_latex_riscv/valzextern_f64toi641dd890d7fbf7a24774c052a9c246250f.tex new file mode 100644 index 00000000..fdb36df3 --- /dev/null +++ b/sail_latex_riscv/valzextern_f64toi641dd890d7fbf7a24774c052a9c246250f.tex @@ -0,0 +1 @@ +extern_f64ToI64 : (bits_rm, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64toui3201aa4791323c1c065734b1b292dfc483.tex b/sail_latex_riscv/valzextern_f64toui3201aa4791323c1c065734b1b292dfc483.tex new file mode 100644 index 00000000..4d93f0fe --- /dev/null +++ b/sail_latex_riscv/valzextern_f64toui3201aa4791323c1c065734b1b292dfc483.tex @@ -0,0 +1 @@ +extern_f64ToUi32 : (bits_rm, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_f64toui64941713ad89e209a4feb9e7b47c7194bb.tex b/sail_latex_riscv/valzextern_f64toui64941713ad89e209a4feb9e7b47c7194bb.tex new file mode 100644 index 00000000..a771e684 --- /dev/null +++ b/sail_latex_riscv/valzextern_f64toui64941713ad89e209a4feb9e7b47c7194bb.tex @@ -0,0 +1 @@ +extern_f64ToUi64 : (bits_rm, bits_D) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_i32tof32928758eb5e1cef38c85f3df1f2fa8faa.tex b/sail_latex_riscv/valzextern_i32tof32928758eb5e1cef38c85f3df1f2fa8faa.tex new file mode 100644 index 00000000..a4953d44 --- /dev/null +++ b/sail_latex_riscv/valzextern_i32tof32928758eb5e1cef38c85f3df1f2fa8faa.tex @@ -0,0 +1 @@ +extern_i32ToF32 : (bits_rm, bits_W) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_i32tof64fd00956ce74e2f05bee6c0c09b2fe4e9.tex b/sail_latex_riscv/valzextern_i32tof64fd00956ce74e2f05bee6c0c09b2fe4e9.tex new file mode 100644 index 00000000..c694ef9b --- /dev/null +++ b/sail_latex_riscv/valzextern_i32tof64fd00956ce74e2f05bee6c0c09b2fe4e9.tex @@ -0,0 +1 @@ +extern_i32ToF64 : (bits_rm, bits_W) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_i64tof3238824aafa28223d09bd70270bcc53a19.tex b/sail_latex_riscv/valzextern_i64tof3238824aafa28223d09bd70270bcc53a19.tex new file mode 100644 index 00000000..df3417bf --- /dev/null +++ b/sail_latex_riscv/valzextern_i64tof3238824aafa28223d09bd70270bcc53a19.tex @@ -0,0 +1 @@ +extern_i64ToF32 : (bits_rm, bits_L) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_i64tof64aed9270eafe2e670b0a96825020ff419.tex b/sail_latex_riscv/valzextern_i64tof64aed9270eafe2e670b0a96825020ff419.tex new file mode 100644 index 00000000..3b315a6f --- /dev/null +++ b/sail_latex_riscv/valzextern_i64tof64aed9270eafe2e670b0a96825020ff419.tex @@ -0,0 +1 @@ +extern_i64ToF64 : (bits_rm, bits_L) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_ui32tof320d34a36731fc04f9878fe858410678ad.tex b/sail_latex_riscv/valzextern_ui32tof320d34a36731fc04f9878fe858410678ad.tex new file mode 100644 index 00000000..1e372020 --- /dev/null +++ b/sail_latex_riscv/valzextern_ui32tof320d34a36731fc04f9878fe858410678ad.tex @@ -0,0 +1 @@ +extern_ui32ToF32 : (bits_rm, bits_WU) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_ui32tof64e2fa1dc20fc15cc4e3898f79cd2790c4.tex b/sail_latex_riscv/valzextern_ui32tof64e2fa1dc20fc15cc4e3898f79cd2790c4.tex new file mode 100644 index 00000000..e20dc3aa --- /dev/null +++ b/sail_latex_riscv/valzextern_ui32tof64e2fa1dc20fc15cc4e3898f79cd2790c4.tex @@ -0,0 +1 @@ +extern_ui32ToF64 : (bits_rm, bits_WU) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_ui64tof3222147d78d464deaed8427dd5e9a1f97d.tex b/sail_latex_riscv/valzextern_ui64tof3222147d78d464deaed8427dd5e9a1f97d.tex new file mode 100644 index 00000000..18f242e0 --- /dev/null +++ b/sail_latex_riscv/valzextern_ui64tof3222147d78d464deaed8427dd5e9a1f97d.tex @@ -0,0 +1 @@ +extern_ui64ToF32 : (bits_rm, bits_L) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzextern_ui64tof64b071761b350c914c21ca717b7ff70706.tex b/sail_latex_riscv/valzextern_ui64tof64b071761b350c914c21ca717b7ff70706.tex new file mode 100644 index 00000000..451edae6 --- /dev/null +++ b/sail_latex_riscv/valzextern_ui64tof64b071761b350c914c21ca717b7ff70706.tex @@ -0,0 +1 @@ +extern_ui64ToF64 : (bits_rm, bits_LU) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzexts8a10d418fac6a2072ef1dfede4580873.tex b/sail_latex_riscv/valzexts8a10d418fac6a2072ef1dfede4580873.tex new file mode 100644 index 00000000..e0676227 --- /dev/null +++ b/sail_latex_riscv/valzexts8a10d418fac6a2072ef1dfede4580873.tex @@ -0,0 +1 @@ +EXTS : forall ('n 'm : Int), 'm >= 'n. (implicit('m), bits('n)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_riscv/valzextstatus_of_bits9da79344bfec7cda3e374a5ba6b49e27.tex b/sail_latex_riscv/valzextstatus_of_bits9da79344bfec7cda3e374a5ba6b49e27.tex new file mode 100644 index 00000000..29b4a3db --- /dev/null +++ b/sail_latex_riscv/valzextstatus_of_bits9da79344bfec7cda3e374a5ba6b49e27.tex @@ -0,0 +1 @@ +extStatus_of_bits : ext_status -> ExtStatus \ No newline at end of file diff --git a/sail_latex_riscv/valzextstatus_of_num31bfbda5f90ad0f3cdbc5a0f1b63da2d.tex b/sail_latex_riscv/valzextstatus_of_num31bfbda5f90ad0f3cdbc5a0f1b63da2d.tex new file mode 100644 index 00000000..0ccb9b3e --- /dev/null +++ b/sail_latex_riscv/valzextstatus_of_num31bfbda5f90ad0f3cdbc5a0f1b63da2d.tex @@ -0,0 +1 @@ +ExtStatus_of_num : forall ('e : Int), (0 <= 'e & 'e <= 3). int('e) -> ExtStatus \ No newline at end of file diff --git a/sail_latex_riscv/valzextstatus_to_bits95f7e744a463eb9cfccacc81efa252ae.tex b/sail_latex_riscv/valzextstatus_to_bits95f7e744a463eb9cfccacc81efa252ae.tex new file mode 100644 index 00000000..3111fdf8 --- /dev/null +++ b/sail_latex_riscv/valzextstatus_to_bits95f7e744a463eb9cfccacc81efa252ae.tex @@ -0,0 +1 @@ +extStatus_to_bits : ExtStatus -> ext_status \ No newline at end of file diff --git a/sail_latex_riscv/valzextzdb77018947d632a113deb15d298290d4.tex b/sail_latex_riscv/valzextzdb77018947d632a113deb15d298290d4.tex new file mode 100644 index 00000000..6fa045e6 --- /dev/null +++ b/sail_latex_riscv/valzextzdb77018947d632a113deb15d298290d4.tex @@ -0,0 +1 @@ +EXTZ : forall ('n 'm : Int), 'm >= 'n. (implicit('m), bits('n)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_riscv/valzf_bin_op_d_of_num97322de52afcea7a7f630a9ec29b7900.tex b/sail_latex_riscv/valzf_bin_op_d_of_num97322de52afcea7a7f630a9ec29b7900.tex new file mode 100644 index 00000000..4698a3c3 --- /dev/null +++ b/sail_latex_riscv/valzf_bin_op_d_of_num97322de52afcea7a7f630a9ec29b7900.tex @@ -0,0 +1 @@ +f_bin_op_D_of_num : forall ('e : Int), (0 <= 'e & 'e <= 7). int('e) -> f_bin_op_D \ No newline at end of file diff --git a/sail_latex_riscv/valzf_bin_op_s_of_num66d590442d54517898ad2679db0d80bc.tex b/sail_latex_riscv/valzf_bin_op_s_of_num66d590442d54517898ad2679db0d80bc.tex new file mode 100644 index 00000000..ca3f4ab7 --- /dev/null +++ b/sail_latex_riscv/valzf_bin_op_s_of_num66d590442d54517898ad2679db0d80bc.tex @@ -0,0 +1 @@ +f_bin_op_S_of_num : forall ('e : Int), (0 <= 'e & 'e <= 7). int('e) -> f_bin_op_S \ No newline at end of file diff --git a/sail_latex_riscv/valzf_bin_rm_op_d_of_num4f1c6a877a7fdb6ce5cba8edac489378.tex b/sail_latex_riscv/valzf_bin_rm_op_d_of_num4f1c6a877a7fdb6ce5cba8edac489378.tex new file mode 100644 index 00000000..2133bc1a --- /dev/null +++ b/sail_latex_riscv/valzf_bin_rm_op_d_of_num4f1c6a877a7fdb6ce5cba8edac489378.tex @@ -0,0 +1 @@ +f_bin_rm_op_D_of_num : forall ('e : Int), (0 <= 'e & 'e <= 3). int('e) -> f_bin_rm_op_D \ No newline at end of file diff --git a/sail_latex_riscv/valzf_bin_rm_op_s_of_num425ba7f76e47ae16326c0417fe340273.tex b/sail_latex_riscv/valzf_bin_rm_op_s_of_num425ba7f76e47ae16326c0417fe340273.tex new file mode 100644 index 00000000..48b37c49 --- /dev/null +++ b/sail_latex_riscv/valzf_bin_rm_op_s_of_num425ba7f76e47ae16326c0417fe340273.tex @@ -0,0 +1 @@ +f_bin_rm_op_S_of_num : forall ('e : Int), (0 <= 'e & 'e <= 3). int('e) -> f_bin_rm_op_S \ No newline at end of file diff --git a/sail_latex_riscv/valzf_bin_rm_type_mnemonic_deb9e3f6f9179ea4b09697f358f9f6a0b.tex b/sail_latex_riscv/valzf_bin_rm_type_mnemonic_deb9e3f6f9179ea4b09697f358f9f6a0b.tex new file mode 100644 index 00000000..3a5cb912 --- /dev/null +++ b/sail_latex_riscv/valzf_bin_rm_type_mnemonic_deb9e3f6f9179ea4b09697f358f9f6a0b.tex @@ -0,0 +1 @@ +f_bin_rm_type_mnemonic_D : f_bin_rm_op_D <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzf_bin_rm_type_mnemonic_s2d0dda4f6d202d3b11b80b4a78a91df1.tex b/sail_latex_riscv/valzf_bin_rm_type_mnemonic_s2d0dda4f6d202d3b11b80b4a78a91df1.tex new file mode 100644 index 00000000..8b52c2a1 --- /dev/null +++ b/sail_latex_riscv/valzf_bin_rm_type_mnemonic_s2d0dda4f6d202d3b11b80b4a78a91df1.tex @@ -0,0 +1 @@ +f_bin_rm_type_mnemonic_S : f_bin_rm_op_S <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzf_bin_type_mnemonic_d4c3459a461182e50755d18d2795fe9de.tex b/sail_latex_riscv/valzf_bin_type_mnemonic_d4c3459a461182e50755d18d2795fe9de.tex new file mode 100644 index 00000000..42412ae9 --- /dev/null +++ b/sail_latex_riscv/valzf_bin_type_mnemonic_d4c3459a461182e50755d18d2795fe9de.tex @@ -0,0 +1 @@ +f_bin_type_mnemonic_D : f_bin_op_D <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzf_bin_type_mnemonic_s7707fb27bf62e8e8783b4425caefe10c.tex b/sail_latex_riscv/valzf_bin_type_mnemonic_s7707fb27bf62e8e8783b4425caefe10c.tex new file mode 100644 index 00000000..c42f02ea --- /dev/null +++ b/sail_latex_riscv/valzf_bin_type_mnemonic_s7707fb27bf62e8e8783b4425caefe10c.tex @@ -0,0 +1 @@ +f_bin_type_mnemonic_S : f_bin_op_S <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_nan_d970e43a6bafb89b645fab556a4ad623c.tex b/sail_latex_riscv/valzf_is_nan_d970e43a6bafb89b645fab556a4ad623c.tex new file mode 100644 index 00000000..c1b068c3 --- /dev/null +++ b/sail_latex_riscv/valzf_is_nan_d970e43a6bafb89b645fab556a4ad623c.tex @@ -0,0 +1 @@ +f_is_NaN_D : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_nan_s0d165c8ab9495379c496e3667f21236f.tex b/sail_latex_riscv/valzf_is_nan_s0d165c8ab9495379c496e3667f21236f.tex new file mode 100644 index 00000000..4c7f1bc1 --- /dev/null +++ b/sail_latex_riscv/valzf_is_nan_s0d165c8ab9495379c496e3667f21236f.tex @@ -0,0 +1 @@ +f_is_NaN_S : bits(32) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_neg_inf_d3f44c40462ec32ab41b8fa4dc4e6f998.tex b/sail_latex_riscv/valzf_is_neg_inf_d3f44c40462ec32ab41b8fa4dc4e6f998.tex new file mode 100644 index 00000000..38bd08ad --- /dev/null +++ b/sail_latex_riscv/valzf_is_neg_inf_d3f44c40462ec32ab41b8fa4dc4e6f998.tex @@ -0,0 +1 @@ +f_is_neg_inf_D : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_neg_inf_sf1e927a0ea24a891ce2c85c8d22d9613.tex b/sail_latex_riscv/valzf_is_neg_inf_sf1e927a0ea24a891ce2c85c8d22d9613.tex new file mode 100644 index 00000000..7fabe476 --- /dev/null +++ b/sail_latex_riscv/valzf_is_neg_inf_sf1e927a0ea24a891ce2c85c8d22d9613.tex @@ -0,0 +1 @@ +f_is_neg_inf_S : bits(32) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_neg_norm_d9b9e067af3304bb1fae5d1501327fd53.tex b/sail_latex_riscv/valzf_is_neg_norm_d9b9e067af3304bb1fae5d1501327fd53.tex new file mode 100644 index 00000000..670df663 --- /dev/null +++ b/sail_latex_riscv/valzf_is_neg_norm_d9b9e067af3304bb1fae5d1501327fd53.tex @@ -0,0 +1 @@ +f_is_neg_norm_D : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_neg_norm_s8bfccfb981e547ad5f5c42e4a17c2a1f.tex b/sail_latex_riscv/valzf_is_neg_norm_s8bfccfb981e547ad5f5c42e4a17c2a1f.tex new file mode 100644 index 00000000..84ebd925 --- /dev/null +++ b/sail_latex_riscv/valzf_is_neg_norm_s8bfccfb981e547ad5f5c42e4a17c2a1f.tex @@ -0,0 +1 @@ +f_is_neg_norm_S : bits(32) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_neg_subnorm_d808d9c9ea664491fe0b23b650d1e996c.tex b/sail_latex_riscv/valzf_is_neg_subnorm_d808d9c9ea664491fe0b23b650d1e996c.tex new file mode 100644 index 00000000..c1b4d15b --- /dev/null +++ b/sail_latex_riscv/valzf_is_neg_subnorm_d808d9c9ea664491fe0b23b650d1e996c.tex @@ -0,0 +1 @@ +f_is_neg_subnorm_D : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_neg_subnorm_sd8c8d47f6284f9e99142031238418d6e.tex b/sail_latex_riscv/valzf_is_neg_subnorm_sd8c8d47f6284f9e99142031238418d6e.tex new file mode 100644 index 00000000..2b0d1e8d --- /dev/null +++ b/sail_latex_riscv/valzf_is_neg_subnorm_sd8c8d47f6284f9e99142031238418d6e.tex @@ -0,0 +1 @@ +f_is_neg_subnorm_S : bits(32) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_neg_zzero_d7855947d702bd41cc96dbb033e17918f.tex b/sail_latex_riscv/valzf_is_neg_zzero_d7855947d702bd41cc96dbb033e17918f.tex new file mode 100644 index 00000000..11bc9881 --- /dev/null +++ b/sail_latex_riscv/valzf_is_neg_zzero_d7855947d702bd41cc96dbb033e17918f.tex @@ -0,0 +1 @@ +f_is_neg_zero_D : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_neg_zzero_s01b2d7b1def55db2428888908b29c669.tex b/sail_latex_riscv/valzf_is_neg_zzero_s01b2d7b1def55db2428888908b29c669.tex new file mode 100644 index 00000000..81cfef21 --- /dev/null +++ b/sail_latex_riscv/valzf_is_neg_zzero_s01b2d7b1def55db2428888908b29c669.tex @@ -0,0 +1 @@ +f_is_neg_zero_S : bits(32) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_pos_inf_ddc033c6bfe555dfe790113dec0ddb7e3.tex b/sail_latex_riscv/valzf_is_pos_inf_ddc033c6bfe555dfe790113dec0ddb7e3.tex new file mode 100644 index 00000000..5ca97d40 --- /dev/null +++ b/sail_latex_riscv/valzf_is_pos_inf_ddc033c6bfe555dfe790113dec0ddb7e3.tex @@ -0,0 +1 @@ +f_is_pos_inf_D : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_pos_inf_sf714fc249168edfd360262aca5e55c4d.tex b/sail_latex_riscv/valzf_is_pos_inf_sf714fc249168edfd360262aca5e55c4d.tex new file mode 100644 index 00000000..a205a09c --- /dev/null +++ b/sail_latex_riscv/valzf_is_pos_inf_sf714fc249168edfd360262aca5e55c4d.tex @@ -0,0 +1 @@ +f_is_pos_inf_S : bits(32) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_pos_norm_d6611be4e31c69209487c037c5336c370.tex b/sail_latex_riscv/valzf_is_pos_norm_d6611be4e31c69209487c037c5336c370.tex new file mode 100644 index 00000000..3c6122a2 --- /dev/null +++ b/sail_latex_riscv/valzf_is_pos_norm_d6611be4e31c69209487c037c5336c370.tex @@ -0,0 +1 @@ +f_is_pos_norm_D : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_pos_norm_s19872015fda671aa1dca05b90a2680c4.tex b/sail_latex_riscv/valzf_is_pos_norm_s19872015fda671aa1dca05b90a2680c4.tex new file mode 100644 index 00000000..27df8946 --- /dev/null +++ b/sail_latex_riscv/valzf_is_pos_norm_s19872015fda671aa1dca05b90a2680c4.tex @@ -0,0 +1 @@ +f_is_pos_norm_S : bits(32) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_pos_subnorm_d7e83f87299dae2035e33b7c97dd6be45.tex b/sail_latex_riscv/valzf_is_pos_subnorm_d7e83f87299dae2035e33b7c97dd6be45.tex new file mode 100644 index 00000000..be29a00b --- /dev/null +++ b/sail_latex_riscv/valzf_is_pos_subnorm_d7e83f87299dae2035e33b7c97dd6be45.tex @@ -0,0 +1 @@ +f_is_pos_subnorm_D : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_pos_subnorm_s4efdacb98629e85ea864b456e8377a98.tex b/sail_latex_riscv/valzf_is_pos_subnorm_s4efdacb98629e85ea864b456e8377a98.tex new file mode 100644 index 00000000..3c834d6a --- /dev/null +++ b/sail_latex_riscv/valzf_is_pos_subnorm_s4efdacb98629e85ea864b456e8377a98.tex @@ -0,0 +1 @@ +f_is_pos_subnorm_S : bits(32) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_pos_zzero_d7e379cb7f8f90c1af7e79d78e2a86f37.tex b/sail_latex_riscv/valzf_is_pos_zzero_d7e379cb7f8f90c1af7e79d78e2a86f37.tex new file mode 100644 index 00000000..0ad9f48d --- /dev/null +++ b/sail_latex_riscv/valzf_is_pos_zzero_d7e379cb7f8f90c1af7e79d78e2a86f37.tex @@ -0,0 +1 @@ +f_is_pos_zero_D : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_pos_zzero_s92eacf7245b38cd8fbe2b7411cc24794.tex b/sail_latex_riscv/valzf_is_pos_zzero_s92eacf7245b38cd8fbe2b7411cc24794.tex new file mode 100644 index 00000000..e13fbec3 --- /dev/null +++ b/sail_latex_riscv/valzf_is_pos_zzero_s92eacf7245b38cd8fbe2b7411cc24794.tex @@ -0,0 +1 @@ +f_is_pos_zero_S : bits(32) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_qnan_d5bbb21fc7537d62baacf94741f71226d.tex b/sail_latex_riscv/valzf_is_qnan_d5bbb21fc7537d62baacf94741f71226d.tex new file mode 100644 index 00000000..c1be5efc --- /dev/null +++ b/sail_latex_riscv/valzf_is_qnan_d5bbb21fc7537d62baacf94741f71226d.tex @@ -0,0 +1 @@ +f_is_QNaN_D : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_qnan_s36343ea7477dd88c6d9f512ad8587fd3.tex b/sail_latex_riscv/valzf_is_qnan_s36343ea7477dd88c6d9f512ad8587fd3.tex new file mode 100644 index 00000000..66646779 --- /dev/null +++ b/sail_latex_riscv/valzf_is_qnan_s36343ea7477dd88c6d9f512ad8587fd3.tex @@ -0,0 +1 @@ +f_is_QNaN_S : bits(32) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_snan_d3e7f4d132d4d3fe4846581a123c48b56.tex b/sail_latex_riscv/valzf_is_snan_d3e7f4d132d4d3fe4846581a123c48b56.tex new file mode 100644 index 00000000..75cc4f90 --- /dev/null +++ b/sail_latex_riscv/valzf_is_snan_d3e7f4d132d4d3fe4846581a123c48b56.tex @@ -0,0 +1 @@ +f_is_SNaN_D : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_is_snan_s4f74c8b27b066b5e2d6856d63c0d8113.tex b/sail_latex_riscv/valzf_is_snan_s4f74c8b27b066b5e2d6856d63c0d8113.tex new file mode 100644 index 00000000..b9c1ac8b --- /dev/null +++ b/sail_latex_riscv/valzf_is_snan_s4f74c8b27b066b5e2d6856d63c0d8113.tex @@ -0,0 +1 @@ +f_is_SNaN_S : bits(32) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzf_madd_op_d_of_num115462b951eadf3acf4b0a2bb11e801b.tex b/sail_latex_riscv/valzf_madd_op_d_of_num115462b951eadf3acf4b0a2bb11e801b.tex new file mode 100644 index 00000000..e2b8d5f7 --- /dev/null +++ b/sail_latex_riscv/valzf_madd_op_d_of_num115462b951eadf3acf4b0a2bb11e801b.tex @@ -0,0 +1 @@ +f_madd_op_D_of_num : forall ('e : Int), (0 <= 'e & 'e <= 3). int('e) -> f_madd_op_D \ No newline at end of file diff --git a/sail_latex_riscv/valzf_madd_op_s_of_num9bfe1beb29f1f97cf6b7643bd9febe9b.tex b/sail_latex_riscv/valzf_madd_op_s_of_num9bfe1beb29f1f97cf6b7643bd9febe9b.tex new file mode 100644 index 00000000..a4d7604a --- /dev/null +++ b/sail_latex_riscv/valzf_madd_op_s_of_num9bfe1beb29f1f97cf6b7643bd9febe9b.tex @@ -0,0 +1 @@ +f_madd_op_S_of_num : forall ('e : Int), (0 <= 'e & 'e <= 3). int('e) -> f_madd_op_S \ No newline at end of file diff --git a/sail_latex_riscv/valzf_madd_type_mnemonic_de10f87b5527cad531eb1f3e055843354.tex b/sail_latex_riscv/valzf_madd_type_mnemonic_de10f87b5527cad531eb1f3e055843354.tex new file mode 100644 index 00000000..a32cd136 --- /dev/null +++ b/sail_latex_riscv/valzf_madd_type_mnemonic_de10f87b5527cad531eb1f3e055843354.tex @@ -0,0 +1 @@ +f_madd_type_mnemonic_D : f_madd_op_D <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzf_madd_type_mnemonic_se8cab142783011d68d65bf9f55ceaf5f.tex b/sail_latex_riscv/valzf_madd_type_mnemonic_se8cab142783011d68d65bf9f55ceaf5f.tex new file mode 100644 index 00000000..92fe30b7 --- /dev/null +++ b/sail_latex_riscv/valzf_madd_type_mnemonic_se8cab142783011d68d65bf9f55ceaf5f.tex @@ -0,0 +1 @@ +f_madd_type_mnemonic_S : f_madd_op_S <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzf_un_op_d_of_num20c93bb1c359c6ff0f65b3c91dbe8c85.tex b/sail_latex_riscv/valzf_un_op_d_of_num20c93bb1c359c6ff0f65b3c91dbe8c85.tex new file mode 100644 index 00000000..22c5be58 --- /dev/null +++ b/sail_latex_riscv/valzf_un_op_d_of_num20c93bb1c359c6ff0f65b3c91dbe8c85.tex @@ -0,0 +1 @@ +f_un_op_D_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> f_un_op_D \ No newline at end of file diff --git a/sail_latex_riscv/valzf_un_op_s_of_num428b8623c493e45bc273b3e1a0c895e0.tex b/sail_latex_riscv/valzf_un_op_s_of_num428b8623c493e45bc273b3e1a0c895e0.tex new file mode 100644 index 00000000..39428d68 --- /dev/null +++ b/sail_latex_riscv/valzf_un_op_s_of_num428b8623c493e45bc273b3e1a0c895e0.tex @@ -0,0 +1 @@ +f_un_op_S_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> f_un_op_S \ No newline at end of file diff --git a/sail_latex_riscv/valzf_un_rm_op_d_of_num3c7528aaf2a777986f767617d6c66717.tex b/sail_latex_riscv/valzf_un_rm_op_d_of_num3c7528aaf2a777986f767617d6c66717.tex new file mode 100644 index 00000000..2cd909f8 --- /dev/null +++ b/sail_latex_riscv/valzf_un_rm_op_d_of_num3c7528aaf2a777986f767617d6c66717.tex @@ -0,0 +1 @@ +f_un_rm_op_D_of_num : forall ('e : Int), (0 <= 'e & 'e <= 10). int('e) -> f_un_rm_op_D \ No newline at end of file diff --git a/sail_latex_riscv/valzf_un_rm_op_s_of_numcf978158d6a6f45fe1893c4a9c122140.tex b/sail_latex_riscv/valzf_un_rm_op_s_of_numcf978158d6a6f45fe1893c4a9c122140.tex new file mode 100644 index 00000000..d931e19d --- /dev/null +++ b/sail_latex_riscv/valzf_un_rm_op_s_of_numcf978158d6a6f45fe1893c4a9c122140.tex @@ -0,0 +1 @@ +f_un_rm_op_S_of_num : forall ('e : Int), (0 <= 'e & 'e <= 8). int('e) -> f_un_rm_op_S \ No newline at end of file diff --git a/sail_latex_riscv/valzf_un_rm_type_mnemonic_d4a9ba98f21ea36db9609bd6233749d86.tex b/sail_latex_riscv/valzf_un_rm_type_mnemonic_d4a9ba98f21ea36db9609bd6233749d86.tex new file mode 100644 index 00000000..d5abbba2 --- /dev/null +++ b/sail_latex_riscv/valzf_un_rm_type_mnemonic_d4a9ba98f21ea36db9609bd6233749d86.tex @@ -0,0 +1 @@ +f_un_rm_type_mnemonic_D : f_un_rm_op_D <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzf_un_rm_type_mnemonic_s24ea00e2ecedf00b96871ba799645a81.tex b/sail_latex_riscv/valzf_un_rm_type_mnemonic_s24ea00e2ecedf00b96871ba799645a81.tex new file mode 100644 index 00000000..cf3d0965 --- /dev/null +++ b/sail_latex_riscv/valzf_un_rm_type_mnemonic_s24ea00e2ecedf00b96871ba799645a81.tex @@ -0,0 +1 @@ +f_un_rm_type_mnemonic_S : f_un_rm_op_S <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzf_un_type_mnemonic_d67aa9b49056aabdddaa065ba03ecbadb.tex b/sail_latex_riscv/valzf_un_type_mnemonic_d67aa9b49056aabdddaa065ba03ecbadb.tex new file mode 100644 index 00000000..c76e28de --- /dev/null +++ b/sail_latex_riscv/valzf_un_type_mnemonic_d67aa9b49056aabdddaa065ba03ecbadb.tex @@ -0,0 +1 @@ +f_un_type_mnemonic_D : f_un_op_D <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzf_un_type_mnemonic_s68f8c6b309ddb2dc8d9cab3341f41b29.tex b/sail_latex_riscv/valzf_un_type_mnemonic_s68f8c6b309ddb2dc8d9cab3341f41b29.tex new file mode 100644 index 00000000..a6a4239b --- /dev/null +++ b/sail_latex_riscv/valzf_un_type_mnemonic_s68f8c6b309ddb2dc8d9cab3341f41b29.tex @@ -0,0 +1 @@ +f_un_type_mnemonic_S : f_un_op_S <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzfastrepcheck592cc92c49a4599da60647f87c331420.tex b/sail_latex_riscv/valzfastrepcheck592cc92c49a4599da60647f87c331420.tex new file mode 100644 index 00000000..d251e657 --- /dev/null +++ b/sail_latex_riscv/valzfastrepcheck592cc92c49a4599da60647f87c331420.tex @@ -0,0 +1 @@ +fastRepCheck : (Capability, CapAddrBits) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex b/sail_latex_riscv/valzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex new file mode 100644 index 00000000..4dbd41ef --- /dev/null +++ b/sail_latex_riscv/valzfdiv_intd3535e930b3252acc5f18a9e4b34e63a.tex @@ -0,0 +1 @@ +fdiv_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_riscv/valzfence_bits39f0871d2c2e4d36bb4622567377397d.tex b/sail_latex_riscv/valzfence_bits39f0871d2c2e4d36bb4622567377397d.tex new file mode 100644 index 00000000..5112c34c --- /dev/null +++ b/sail_latex_riscv/valzfence_bits39f0871d2c2e4d36bb4622567377397d.tex @@ -0,0 +1 @@ +fence_bits : bitvector(4, dec) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzfeq_quiet_d0b6b5eb435e8b9c9bcf3b77e16fff044.tex b/sail_latex_riscv/valzfeq_quiet_d0b6b5eb435e8b9c9bcf3b77e16fff044.tex new file mode 100644 index 00000000..533a8e80 --- /dev/null +++ b/sail_latex_riscv/valzfeq_quiet_d0b6b5eb435e8b9c9bcf3b77e16fff044.tex @@ -0,0 +1 @@ +feq_quiet_D : (bits(64), bits(64)) -> (bool, bits(5)) \ No newline at end of file diff --git a/sail_latex_riscv/valzfeq_quiet_saed522b017dd40dd277d80aee28e4fe9.tex b/sail_latex_riscv/valzfeq_quiet_saed522b017dd40dd277d80aee28e4fe9.tex new file mode 100644 index 00000000..65a856ea --- /dev/null +++ b/sail_latex_riscv/valzfeq_quiet_saed522b017dd40dd277d80aee28e4fe9.tex @@ -0,0 +1 @@ +feq_quiet_S : (bits(32), bits(32)) -> (bool, bits(5)) \ No newline at end of file diff --git a/sail_latex_riscv/valzfetch5e1d71b1ad15beedbd2dacb5ddbcd2b6.tex b/sail_latex_riscv/valzfetch5e1d71b1ad15beedbd2dacb5ddbcd2b6.tex new file mode 100644 index 00000000..9118e970 --- /dev/null +++ b/sail_latex_riscv/valzfetch5e1d71b1ad15beedbd2dacb5ddbcd2b6.tex @@ -0,0 +1 @@ +fetch : unit -> FetchResult \ No newline at end of file diff --git a/sail_latex_riscv/valzfindpendinginterrupt0ed4e5cc6469ca27b20724b51027ab4c.tex b/sail_latex_riscv/valzfindpendinginterrupt0ed4e5cc6469ca27b20724b51027ab4c.tex new file mode 100644 index 00000000..92960fd8 --- /dev/null +++ b/sail_latex_riscv/valzfindpendinginterrupt0ed4e5cc6469ca27b20724b51027ab4c.tex @@ -0,0 +1 @@ +findPendingInterrupt : xlenbits -> option(InterruptType) \ No newline at end of file diff --git a/sail_latex_riscv/valzfle_dc504d6eb55e9a730eda7235ae654dd1c.tex b/sail_latex_riscv/valzfle_dc504d6eb55e9a730eda7235ae654dd1c.tex new file mode 100644 index 00000000..402ceac3 --- /dev/null +++ b/sail_latex_riscv/valzfle_dc504d6eb55e9a730eda7235ae654dd1c.tex @@ -0,0 +1 @@ +fle_D : (bits(64), bits(64), bool) -> (bool, bits(5)) \ No newline at end of file diff --git a/sail_latex_riscv/valzfle_s93e035a8ca13e7d64b965c7c750ae56d.tex b/sail_latex_riscv/valzfle_s93e035a8ca13e7d64b965c7c750ae56d.tex new file mode 100644 index 00000000..74033da2 --- /dev/null +++ b/sail_latex_riscv/valzfle_s93e035a8ca13e7d64b965c7c750ae56d.tex @@ -0,0 +1 @@ +fle_S : (bits(32), bits(32), bool) -> (bool, bits(5)) \ No newline at end of file diff --git a/sail_latex_riscv/valzflt_dc45e113a7fb9ece6e62166679b975f44.tex b/sail_latex_riscv/valzflt_dc45e113a7fb9ece6e62166679b975f44.tex new file mode 100644 index 00000000..76ceaa7c --- /dev/null +++ b/sail_latex_riscv/valzflt_dc45e113a7fb9ece6e62166679b975f44.tex @@ -0,0 +1 @@ +flt_D : (bits(64), bits(64), bool) -> (bool, bits(5)) \ No newline at end of file diff --git a/sail_latex_riscv/valzflt_sb42cf5853deeee1a9c0ed2ff1e36a52b.tex b/sail_latex_riscv/valzflt_sb42cf5853deeee1a9c0ed2ff1e36a52b.tex new file mode 100644 index 00000000..17cfd1ee --- /dev/null +++ b/sail_latex_riscv/valzflt_sb42cf5853deeee1a9c0ed2ff1e36a52b.tex @@ -0,0 +1 @@ +flt_S : (bits(32), bits(32), bool) -> (bool, bits(5)) \ No newline at end of file diff --git a/sail_latex_riscv/valzflush_tlb39155d346596461ed0e3ab611745b6738a.tex b/sail_latex_riscv/valzflush_tlb39155d346596461ed0e3ab611745b6738a.tex new file mode 100644 index 00000000..d69b16c8 --- /dev/null +++ b/sail_latex_riscv/valzflush_tlb39155d346596461ed0e3ab611745b6738a.tex @@ -0,0 +1 @@ +flush_TLB39 : (option(asid64), option(vaddr39)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzflush_tlb482377e6a21b0e61c1f15d8ef64c6ac044.tex b/sail_latex_riscv/valzflush_tlb482377e6a21b0e61c1f15d8ef64c6ac044.tex new file mode 100644 index 00000000..b0beae4c --- /dev/null +++ b/sail_latex_riscv/valzflush_tlb482377e6a21b0e61c1f15d8ef64c6ac044.tex @@ -0,0 +1 @@ +flush_TLB48 : (option(asid64), option(vaddr48)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzflush_tlb_entry8073b262f27cbbda50ac10a3cc21c463.tex b/sail_latex_riscv/valzflush_tlb_entry8073b262f27cbbda50ac10a3cc21c463.tex new file mode 100644 index 00000000..6cc0611c --- /dev/null +++ b/sail_latex_riscv/valzflush_tlb_entry8073b262f27cbbda50ac10a3cc21c463.tex @@ -0,0 +1,2 @@ +flush_TLB_Entry : forall ('asidlen 'valen 'palen 'ptelen : Int). + (TLB_Entry('asidlen, 'valen, 'palen, 'ptelen), option(bits('asidlen)), option(bits('valen))) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzflush_tlbf2c831dee428b5971141e383ef962e36.tex b/sail_latex_riscv/valzflush_tlbf2c831dee428b5971141e383ef962e36.tex new file mode 100644 index 00000000..25154113 --- /dev/null +++ b/sail_latex_riscv/valzflush_tlbf2c831dee428b5971141e383ef962e36.tex @@ -0,0 +1 @@ +flush_TLB : (option(xlenbits), option(xlenbits)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzfmake_de1abf4e676ae7d02ecd6d0037a7d77ee.tex b/sail_latex_riscv/valzfmake_de1abf4e676ae7d02ecd6d0037a7d77ee.tex new file mode 100644 index 00000000..7db996b7 --- /dev/null +++ b/sail_latex_riscv/valzfmake_de1abf4e676ae7d02ecd6d0037a7d77ee.tex @@ -0,0 +1 @@ +fmake_D : (bits(1), bits(11), bits(52)) -> bits(64) \ No newline at end of file diff --git a/sail_latex_riscv/valzfmake_sf09ffe3c3e52a17eb1e248d73c150f66.tex b/sail_latex_riscv/valzfmake_sf09ffe3c3e52a17eb1e248d73c150f66.tex new file mode 100644 index 00000000..f5a04dd4 --- /dev/null +++ b/sail_latex_riscv/valzfmake_sf09ffe3c3e52a17eb1e248d73c150f66.tex @@ -0,0 +1 @@ +fmake_S : (bits(1), bits(8), bits(23)) -> bits(32) \ No newline at end of file diff --git a/sail_latex_riscv/valzfmod_int7e215ca2b888f4e92201959fd40958a5.tex b/sail_latex_riscv/valzfmod_int7e215ca2b888f4e92201959fd40958a5.tex new file mode 100644 index 00000000..4a0c1688 --- /dev/null +++ b/sail_latex_riscv/valzfmod_int7e215ca2b888f4e92201959fd40958a5.tex @@ -0,0 +1 @@ +fmod_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_riscv/valzfreg_name4ac4601cc383d5edd878a00fc0bde952.tex b/sail_latex_riscv/valzfreg_name4ac4601cc383d5edd878a00fc0bde952.tex new file mode 100644 index 00000000..b71d8443 --- /dev/null +++ b/sail_latex_riscv/valzfreg_name4ac4601cc383d5edd878a00fc0bde952.tex @@ -0,0 +1 @@ +freg_name : bits(5) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzfreg_name_abi149ff973f4a58e634d652021d3e44de0.tex b/sail_latex_riscv/valzfreg_name_abi149ff973f4a58e634d652021d3e44de0.tex new file mode 100644 index 00000000..6e78bb9f --- /dev/null +++ b/sail_latex_riscv/valzfreg_name_abi149ff973f4a58e634d652021d3e44de0.tex @@ -0,0 +1 @@ +freg_name_abi : regidx <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzfregstr48009e974e6089e7ac15bb0f9271a481.tex b/sail_latex_riscv/valzfregstr48009e974e6089e7ac15bb0f9271a481.tex new file mode 100644 index 00000000..cb256d56 --- /dev/null +++ b/sail_latex_riscv/valzfregstr48009e974e6089e7ac15bb0f9271a481.tex @@ -0,0 +1 @@ +FRegStr : fregtype -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzfregval_from_freg24f4c96a7be559c758c7de5e3dfe669b.tex b/sail_latex_riscv/valzfregval_from_freg24f4c96a7be559c758c7de5e3dfe669b.tex new file mode 100644 index 00000000..8c580ae2 --- /dev/null +++ b/sail_latex_riscv/valzfregval_from_freg24f4c96a7be559c758c7de5e3dfe669b.tex @@ -0,0 +1 @@ +fregval_from_freg : fregtype -> flenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzfregval_into_fregc2bccb9e14fa0e7ca1dec382b998fa46.tex b/sail_latex_riscv/valzfregval_into_fregc2bccb9e14fa0e7ca1dec382b998fa46.tex new file mode 100644 index 00000000..f40f8473 --- /dev/null +++ b/sail_latex_riscv/valzfregval_into_fregc2bccb9e14fa0e7ca1dec382b998fa46.tex @@ -0,0 +1 @@ +fregval_into_freg : flenbits -> fregtype \ No newline at end of file diff --git a/sail_latex_riscv/valzfrm_mnemonic1efa3419adbb7f3793e39728661edbd6.tex b/sail_latex_riscv/valzfrm_mnemonic1efa3419adbb7f3793e39728661edbd6.tex new file mode 100644 index 00000000..b104cb2b --- /dev/null +++ b/sail_latex_riscv/valzfrm_mnemonic1efa3419adbb7f3793e39728661edbd6.tex @@ -0,0 +1 @@ +frm_mnemonic : rounding_mode <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzfsplit_d774cb8ca3d70fb4590f5725c3fd93ad0.tex b/sail_latex_riscv/valzfsplit_d774cb8ca3d70fb4590f5725c3fd93ad0.tex new file mode 100644 index 00000000..755ee7bc --- /dev/null +++ b/sail_latex_riscv/valzfsplit_d774cb8ca3d70fb4590f5725c3fd93ad0.tex @@ -0,0 +1 @@ +fsplit_D : bits(64) -> (bits(1), bits(11), bits(52)) \ No newline at end of file diff --git a/sail_latex_riscv/valzfsplit_s587b8f3a581d4f6ab15969163c75b5ff.tex b/sail_latex_riscv/valzfsplit_s587b8f3a581d4f6ab15969163c75b5ff.tex new file mode 100644 index 00000000..52fc3fa8 --- /dev/null +++ b/sail_latex_riscv/valzfsplit_s587b8f3a581d4f6ab15969163c75b5ff.tex @@ -0,0 +1 @@ +fsplit_S : bits(32) -> (bits(1), bits(8), bits(23)) \ No newline at end of file diff --git a/sail_latex_riscv/valzget_arch_pc874e1e50a5765cd3e317d37fa710a52d.tex b/sail_latex_riscv/valzget_arch_pc874e1e50a5765cd3e317d37fa710a52d.tex new file mode 100644 index 00000000..616309fd --- /dev/null +++ b/sail_latex_riscv/valzget_arch_pc874e1e50a5765cd3e317d37fa710a52d.tex @@ -0,0 +1 @@ +get_arch_pc : unit -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzget_cheri_mode_cap_addr267a231c94a9ae3cf08d67cb43590a2e.tex b/sail_latex_riscv/valzget_cheri_mode_cap_addr267a231c94a9ae3cf08d67cb43590a2e.tex new file mode 100644 index 00000000..81678b31 --- /dev/null +++ b/sail_latex_riscv/valzget_cheri_mode_cap_addr267a231c94a9ae3cf08d67cb43590a2e.tex @@ -0,0 +1 @@ +get_cheri_mode_cap_addr : (regidx, xlenbits) -> (Capability, xlenbits, capreg_idx) \ No newline at end of file diff --git a/sail_latex_riscv/valzget_config_print_instrcd725d09d3941c391aadf6b945a364c4.tex b/sail_latex_riscv/valzget_config_print_instrcd725d09d3941c391aadf6b945a364c4.tex new file mode 100644 index 00000000..74f312b6 --- /dev/null +++ b/sail_latex_riscv/valzget_config_print_instrcd725d09d3941c391aadf6b945a364c4.tex @@ -0,0 +1 @@ +get_config_print_instr : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzget_config_print_memae95e5785b79c4a3f0105a772bf99dca.tex b/sail_latex_riscv/valzget_config_print_memae95e5785b79c4a3f0105a772bf99dca.tex new file mode 100644 index 00000000..e10add8a --- /dev/null +++ b/sail_latex_riscv/valzget_config_print_memae95e5785b79c4a3f0105a772bf99dca.tex @@ -0,0 +1 @@ +get_config_print_mem : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzget_config_print_platform65eee2fe1a7d52174acea1de4e724e03.tex b/sail_latex_riscv/valzget_config_print_platform65eee2fe1a7d52174acea1de4e724e03.tex new file mode 100644 index 00000000..6e574937 --- /dev/null +++ b/sail_latex_riscv/valzget_config_print_platform65eee2fe1a7d52174acea1de4e724e03.tex @@ -0,0 +1 @@ +get_config_print_platform : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzget_config_print_rega14ad214dae5f2d46538a3770abc93e2.tex b/sail_latex_riscv/valzget_config_print_rega14ad214dae5f2d46538a3770abc93e2.tex new file mode 100644 index 00000000..87587dc8 --- /dev/null +++ b/sail_latex_riscv/valzget_config_print_rega14ad214dae5f2d46538a3770abc93e2.tex @@ -0,0 +1 @@ +get_config_print_reg : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzget_mstatus_sxl360b4b5f8d3130ad7ed7bb536d1d7019.tex b/sail_latex_riscv/valzget_mstatus_sxl360b4b5f8d3130ad7ed7bb536d1d7019.tex new file mode 100644 index 00000000..74148109 --- /dev/null +++ b/sail_latex_riscv/valzget_mstatus_sxl360b4b5f8d3130ad7ed7bb536d1d7019.tex @@ -0,0 +1 @@ +get_mstatus_SXL : Mstatus -> arch_xlen \ No newline at end of file diff --git a/sail_latex_riscv/valzget_mstatus_uxl7f41d7b1028a3b1a7e11b635a0524660.tex b/sail_latex_riscv/valzget_mstatus_uxl7f41d7b1028a3b1a7e11b635a0524660.tex new file mode 100644 index 00000000..9702c449 --- /dev/null +++ b/sail_latex_riscv/valzget_mstatus_uxl7f41d7b1028a3b1a7e11b635a0524660.tex @@ -0,0 +1 @@ +get_mstatus_UXL : Mstatus -> arch_xlen \ No newline at end of file diff --git a/sail_latex_riscv/valzget_mtvec134cdc828faab7bf9f19733fba43da2f.tex b/sail_latex_riscv/valzget_mtvec134cdc828faab7bf9f19733fba43da2f.tex new file mode 100644 index 00000000..cd4179d4 --- /dev/null +++ b/sail_latex_riscv/valzget_mtvec134cdc828faab7bf9f19733fba43da2f.tex @@ -0,0 +1 @@ +get_mtvec : unit -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzget_next_pc52098782da35f914abcd4b708363813b.tex b/sail_latex_riscv/valzget_next_pc52098782da35f914abcd4b708363813b.tex new file mode 100644 index 00000000..e3c0a588 --- /dev/null +++ b/sail_latex_riscv/valzget_next_pc52098782da35f914abcd4b708363813b.tex @@ -0,0 +1 @@ +get_next_pc : unit -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzget_slice_int3c313e973dc436aff309f66096377164.tex b/sail_latex_riscv/valzget_slice_int3c313e973dc436aff309f66096377164.tex new file mode 100644 index 00000000..2401b150 --- /dev/null +++ b/sail_latex_riscv/valzget_slice_int3c313e973dc436aff309f66096377164.tex @@ -0,0 +1 @@ +get_slice_int : forall ('w : Int). (int('w), int, int) -> bits('w) \ No newline at end of file diff --git a/sail_latex_riscv/valzget_sstatus_uxl1156c19b76a50f309373d09741dbfe73.tex b/sail_latex_riscv/valzget_sstatus_uxl1156c19b76a50f309373d09741dbfe73.tex new file mode 100644 index 00000000..c5b59566 --- /dev/null +++ b/sail_latex_riscv/valzget_sstatus_uxl1156c19b76a50f309373d09741dbfe73.tex @@ -0,0 +1 @@ +get_sstatus_UXL : Sstatus -> arch_xlen \ No newline at end of file diff --git a/sail_latex_riscv/valzget_stvec8e871a236060976d6c548af2b67478db.tex b/sail_latex_riscv/valzget_stvec8e871a236060976d6c548af2b67478db.tex new file mode 100644 index 00000000..adae178d --- /dev/null +++ b/sail_latex_riscv/valzget_stvec8e871a236060976d6c548af2b67478db.tex @@ -0,0 +1 @@ +get_stvec : unit -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzget_utvec375b7b6fc923ff7174c10f9b93b1b2cf.tex b/sail_latex_riscv/valzget_utvec375b7b6fc923ff7174c10f9b93b1b2cf.tex new file mode 100644 index 00000000..00fa084d --- /dev/null +++ b/sail_latex_riscv/valzget_utvec375b7b6fc923ff7174c10f9b93b1b2cf.tex @@ -0,0 +1 @@ +get_utvec : unit -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzget_xret_target26ce66652c1cd67f2e91b685c1d44e62.tex b/sail_latex_riscv/valzget_xret_target26ce66652c1cd67f2e91b685c1d44e62.tex new file mode 100644 index 00000000..12720227 --- /dev/null +++ b/sail_latex_riscv/valzget_xret_target26ce66652c1cd67f2e91b685c1d44e62.tex @@ -0,0 +1 @@ +get_xret_target : Privilege -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex b/sail_latex_riscv/valzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex new file mode 100644 index 00000000..c007d1d1 --- /dev/null +++ b/sail_latex_riscv/valzgetcapbase6e35c9ba8902471f4b873925840c53a4.tex @@ -0,0 +1 @@ +getCapBase : Capability -> CapAddrInt \ No newline at end of file diff --git a/sail_latex_riscv/valzgetcapbasebits475f0d31f4d2e3d821fa3069875fc752.tex b/sail_latex_riscv/valzgetcapbasebits475f0d31f4d2e3d821fa3069875fc752.tex new file mode 100644 index 00000000..b568fc30 --- /dev/null +++ b/sail_latex_riscv/valzgetcapbasebits475f0d31f4d2e3d821fa3069875fc752.tex @@ -0,0 +1 @@ +getCapBaseBits : Capability -> CapAddrBits \ No newline at end of file diff --git a/sail_latex_riscv/valzgetcapboundsbitscff2a996e27fb45794770bad0b82e1fe.tex b/sail_latex_riscv/valzgetcapboundsbitscff2a996e27fb45794770bad0b82e1fe.tex new file mode 100644 index 00000000..33c095c2 --- /dev/null +++ b/sail_latex_riscv/valzgetcapboundsbitscff2a996e27fb45794770bad0b82e1fe.tex @@ -0,0 +1 @@ +getCapBoundsBits : Capability -> (CapAddrBits, CapLenBits) \ No newline at end of file diff --git a/sail_latex_riscv/valzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex b/sail_latex_riscv/valzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex new file mode 100644 index 00000000..b81313ac --- /dev/null +++ b/sail_latex_riscv/valzgetcapboundsd43bce602e08447feaa9f5135ec44e2f.tex @@ -0,0 +1 @@ +getCapBounds : Capability -> (CapAddrInt, CapLen) \ No newline at end of file diff --git a/sail_latex_riscv/valzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex b/sail_latex_riscv/valzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex new file mode 100644 index 00000000..8238dece --- /dev/null +++ b/sail_latex_riscv/valzgetcapcursord3f4378a821667d421527b6e82da2a0f.tex @@ -0,0 +1 @@ +getCapCursor : Capability -> CapAddrInt \ No newline at end of file diff --git a/sail_latex_riscv/valzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex b/sail_latex_riscv/valzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex new file mode 100644 index 00000000..0a774f65 --- /dev/null +++ b/sail_latex_riscv/valzgetcapflags06024d55b7e2cd94f99830e3c12d9adf.tex @@ -0,0 +1 @@ +getCapFlags : Capability -> CapFlagsBits \ No newline at end of file diff --git a/sail_latex_riscv/valzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex b/sail_latex_riscv/valzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex new file mode 100644 index 00000000..a8fb0011 --- /dev/null +++ b/sail_latex_riscv/valzgetcaphardperms801568201da814b3b7b1126c01e5c34b.tex @@ -0,0 +1 @@ +getCapHardPerms : Capability -> bits(cap_hperms_width) \ No newline at end of file diff --git a/sail_latex_riscv/valzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex b/sail_latex_riscv/valzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex new file mode 100644 index 00000000..4405c72e --- /dev/null +++ b/sail_latex_riscv/valzgetcaplengthe378e6c1b52834806f3d0d380ea18090.tex @@ -0,0 +1 @@ +getCapLength : Capability -> CapLen \ No newline at end of file diff --git a/sail_latex_riscv/valzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex b/sail_latex_riscv/valzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex new file mode 100644 index 00000000..f108120c --- /dev/null +++ b/sail_latex_riscv/valzgetcapoffset9584da45b9f67a0838c0334ac7a14797.tex @@ -0,0 +1 @@ +getCapOffset : Capability -> CapAddrInt \ No newline at end of file diff --git a/sail_latex_riscv/valzgetcapoffsetbits4ee7332151f133f0a8370e45dc0808ca.tex b/sail_latex_riscv/valzgetcapoffsetbits4ee7332151f133f0a8370e45dc0808ca.tex new file mode 100644 index 00000000..61ec11a3 --- /dev/null +++ b/sail_latex_riscv/valzgetcapoffsetbits4ee7332151f133f0a8370e45dc0808ca.tex @@ -0,0 +1 @@ +getCapOffsetBits : Capability -> CapAddrBits \ No newline at end of file diff --git a/sail_latex_riscv/valzgetcapperms6aed04c1602f540bb5d604425f922d92.tex b/sail_latex_riscv/valzgetcapperms6aed04c1602f540bb5d604425f922d92.tex new file mode 100644 index 00000000..35b32336 --- /dev/null +++ b/sail_latex_riscv/valzgetcapperms6aed04c1602f540bb5d604425f922d92.tex @@ -0,0 +1 @@ +getCapPerms : Capability -> CapPermsBits \ No newline at end of file diff --git a/sail_latex_riscv/valzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex b/sail_latex_riscv/valzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex new file mode 100644 index 00000000..b9aaae07 --- /dev/null +++ b/sail_latex_riscv/valzgetcaptop94c52bdb95931df50575f8a40f8b9865.tex @@ -0,0 +1 @@ +getCapTop : Capability -> CapLen \ No newline at end of file diff --git a/sail_latex_riscv/valzgetcaptopbits5ee890f973b03f4c37ec6911afe96449.tex b/sail_latex_riscv/valzgetcaptopbits5ee890f973b03f4c37ec6911afe96449.tex new file mode 100644 index 00000000..3003766d --- /dev/null +++ b/sail_latex_riscv/valzgetcaptopbits5ee890f973b03f4c37ec6911afe96449.tex @@ -0,0 +1 @@ +getCapTopBits : Capability -> CapLenBits \ No newline at end of file diff --git a/sail_latex_riscv/valzgetpendingsetfe7aa2453fb185b904f0c1c2ec773ed8.tex b/sail_latex_riscv/valzgetpendingsetfe7aa2453fb185b904f0c1c2ec773ed8.tex new file mode 100644 index 00000000..cd9602c9 --- /dev/null +++ b/sail_latex_riscv/valzgetpendingsetfe7aa2453fb185b904f0c1c2ec773ed8.tex @@ -0,0 +1 @@ +getPendingSet : Privilege -> option((xlenbits, Privilege)) \ No newline at end of file diff --git a/sail_latex_riscv/valzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex b/sail_latex_riscv/valzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex new file mode 100644 index 00000000..4da98f69 --- /dev/null +++ b/sail_latex_riscv/valzgetrepresentablealignmentmaskdc533650b5133e10468f8840d3ad2739.tex @@ -0,0 +1 @@ +getRepresentableAlignmentMask : xlenbits -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex b/sail_latex_riscv/valzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex new file mode 100644 index 00000000..7e7409ab --- /dev/null +++ b/sail_latex_riscv/valzgetrepresentablelengthad3bb54ef850e37183b86b40599239a6.tex @@ -0,0 +1 @@ +getRepresentableLength : xlenbits -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzgprstr8a694e087c131a3070bde7e75ad3a570.tex b/sail_latex_riscv/valzgprstr8a694e087c131a3070bde7e75ad3a570.tex new file mode 100644 index 00000000..bff8e04d --- /dev/null +++ b/sail_latex_riscv/valzgprstr8a694e087c131a3070bde7e75ad3a570.tex @@ -0,0 +1 @@ +GPRstr : bits(5) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzgt_intef94a8c66f39b1f715cb72941ed95921.tex b/sail_latex_riscv/valzgt_intef94a8c66f39b1f715cb72941ed95921.tex new file mode 100644 index 00000000..fd5e09b1 --- /dev/null +++ b/sail_latex_riscv/valzgt_intef94a8c66f39b1f715cb72941ed95921.tex @@ -0,0 +1 @@ +gt_int : forall ('n 'm : Int). (int('n), int('m)) -> bool('n > 'm) \ No newline at end of file diff --git a/sail_latex_riscv/valzgteq_inte32033a8d137f46d187455cff7dbe40e.tex b/sail_latex_riscv/valzgteq_inte32033a8d137f46d187455cff7dbe40e.tex new file mode 100644 index 00000000..236c5717 --- /dev/null +++ b/sail_latex_riscv/valzgteq_inte32033a8d137f46d187455cff7dbe40e.tex @@ -0,0 +1 @@ +gteq_int : forall ('n 'm : Int). (int('n), int('m)) -> bool('n >= 'm) \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_cheri_cap_exceptionc1ff083ca6d0a739fb48243e22ff4898.tex b/sail_latex_riscv/valzhandle_cheri_cap_exceptionc1ff083ca6d0a739fb48243e22ff4898.tex new file mode 100644 index 00000000..c4778637 --- /dev/null +++ b/sail_latex_riscv/valzhandle_cheri_cap_exceptionc1ff083ca6d0a739fb48243e22ff4898.tex @@ -0,0 +1 @@ +handle_cheri_cap_exception : (CapEx, capreg_idx) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_cheri_pcc_exception3ca0178a61c5394ac2c49197cedda1c1.tex b/sail_latex_riscv/valzhandle_cheri_pcc_exception3ca0178a61c5394ac2c49197cedda1c1.tex new file mode 100644 index 00000000..18bd4c59 --- /dev/null +++ b/sail_latex_riscv/valzhandle_cheri_pcc_exception3ca0178a61c5394ac2c49197cedda1c1.tex @@ -0,0 +1 @@ +handle_cheri_pcc_exception : CapEx -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_cheri_reg_exceptionfad1b48ae08f4eb90d02a5d75771c894.tex b/sail_latex_riscv/valzhandle_cheri_reg_exceptionfad1b48ae08f4eb90d02a5d75771c894.tex new file mode 100644 index 00000000..b6a89211 --- /dev/null +++ b/sail_latex_riscv/valzhandle_cheri_reg_exceptionfad1b48ae08f4eb90d02a5d75771c894.tex @@ -0,0 +1 @@ +handle_cheri_reg_exception : (CapEx, regidx) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_exception5b7a94266182a8a2ef0291c83b256387.tex b/sail_latex_riscv/valzhandle_exception5b7a94266182a8a2ef0291c83b256387.tex new file mode 100644 index 00000000..9faffa2f --- /dev/null +++ b/sail_latex_riscv/valzhandle_exception5b7a94266182a8a2ef0291c83b256387.tex @@ -0,0 +1 @@ +handle_exception : ExceptionType -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_illegal5907526c9d8e4989ca440b67ea4948c3.tex b/sail_latex_riscv/valzhandle_illegal5907526c9d8e4989ca440b67ea4948c3.tex new file mode 100644 index 00000000..4c4cffd3 --- /dev/null +++ b/sail_latex_riscv/valzhandle_illegal5907526c9d8e4989ca440b67ea4948c3.tex @@ -0,0 +1 @@ +handle_illegal : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_interrupt9048a02caa891e49449f7a1f3f4e9ee4.tex b/sail_latex_riscv/valzhandle_interrupt9048a02caa891e49449f7a1f3f4e9ee4.tex new file mode 100644 index 00000000..04e7a258 --- /dev/null +++ b/sail_latex_riscv/valzhandle_interrupt9048a02caa891e49449f7a1f3f4e9ee4.tex @@ -0,0 +1 @@ +handle_interrupt : (InterruptType, Privilege) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_load_cap_via_capc983c32af845a3dec84f2d1241c33390.tex b/sail_latex_riscv/valzhandle_load_cap_via_capc983c32af845a3dec84f2d1241c33390.tex new file mode 100644 index 00000000..36097ce0 --- /dev/null +++ b/sail_latex_riscv/valzhandle_load_cap_via_capc983c32af845a3dec84f2d1241c33390.tex @@ -0,0 +1 @@ +handle_load_cap_via_cap : (regidx, capreg_idx, Capability, xlenbits) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_load_data_via_capf2827ba9c795213ba1703c9ae04ec80e.tex b/sail_latex_riscv/valzhandle_load_data_via_capf2827ba9c795213ba1703c9ae04ec80e.tex new file mode 100644 index 00000000..039e66f2 --- /dev/null +++ b/sail_latex_riscv/valzhandle_load_data_via_capf2827ba9c795213ba1703c9ae04ec80e.tex @@ -0,0 +1 @@ +handle_load_data_via_cap : (regidx, capreg_idx, Capability, xlenbits, bool, word_width) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_loadres_cap_via_capcff54276a28e84c26d372dc8f545b3f0.tex b/sail_latex_riscv/valzhandle_loadres_cap_via_capcff54276a28e84c26d372dc8f545b3f0.tex new file mode 100644 index 00000000..178dc327 --- /dev/null +++ b/sail_latex_riscv/valzhandle_loadres_cap_via_capcff54276a28e84c26d372dc8f545b3f0.tex @@ -0,0 +1 @@ +handle_loadres_cap_via_cap : (regidx, capreg_idx, Capability, xlenbits) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_loadres_data_via_cap08189f30ce7dd627d16d9228026d4005.tex b/sail_latex_riscv/valzhandle_loadres_data_via_cap08189f30ce7dd627d16d9228026d4005.tex new file mode 100644 index 00000000..3c59832d --- /dev/null +++ b/sail_latex_riscv/valzhandle_loadres_data_via_cap08189f30ce7dd627d16d9228026d4005.tex @@ -0,0 +1 @@ +handle_loadres_data_via_cap : (regidx, capreg_idx, Capability, xlenbits, word_width) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_mem_exceptionec2a0168c4f7affdb0652fb9992ac72e.tex b/sail_latex_riscv/valzhandle_mem_exceptionec2a0168c4f7affdb0652fb9992ac72e.tex new file mode 100644 index 00000000..5c109d35 --- /dev/null +++ b/sail_latex_riscv/valzhandle_mem_exceptionec2a0168c4f7affdb0652fb9992ac72e.tex @@ -0,0 +1 @@ +handle_mem_exception : (xlenbits, ExceptionType) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_store_cap_via_cap4d789b2f59a39e53239d073296e45c38.tex b/sail_latex_riscv/valzhandle_store_cap_via_cap4d789b2f59a39e53239d073296e45c38.tex new file mode 100644 index 00000000..dfc7efbb --- /dev/null +++ b/sail_latex_riscv/valzhandle_store_cap_via_cap4d789b2f59a39e53239d073296e45c38.tex @@ -0,0 +1 @@ +handle_store_cap_via_cap : (regidx, capreg_idx, Capability, xlenbits) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_store_cond_cap_via_capdfc2c7d93322ab0a720ded29c24438b2.tex b/sail_latex_riscv/valzhandle_store_cond_cap_via_capdfc2c7d93322ab0a720ded29c24438b2.tex new file mode 100644 index 00000000..e65bef4a --- /dev/null +++ b/sail_latex_riscv/valzhandle_store_cond_cap_via_capdfc2c7d93322ab0a720ded29c24438b2.tex @@ -0,0 +1 @@ +handle_store_cond_cap_via_cap : (regidx, capreg_idx, Capability, xlenbits) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_store_cond_data_via_cap90bf472704e0e0e2072d2afbb0123121.tex b/sail_latex_riscv/valzhandle_store_cond_data_via_cap90bf472704e0e0e2072d2afbb0123121.tex new file mode 100644 index 00000000..4c5040fc --- /dev/null +++ b/sail_latex_riscv/valzhandle_store_cond_data_via_cap90bf472704e0e0e2072d2afbb0123121.tex @@ -0,0 +1 @@ +handle_store_cond_data_via_cap : (regidx, capreg_idx, Capability, xlenbits, word_width) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_store_data_via_capa375706a8b6644ee610b608c6152f081.tex b/sail_latex_riscv/valzhandle_store_data_via_capa375706a8b6644ee610b608c6152f081.tex new file mode 100644 index 00000000..c6fac690 --- /dev/null +++ b/sail_latex_riscv/valzhandle_store_data_via_capa375706a8b6644ee610b608c6152f081.tex @@ -0,0 +1 @@ +handle_store_data_via_cap : (regidx, capreg_idx, Capability, xlenbits, word_width) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzhandle_trap_extension9480b0ad72ce05ffcdcc27185eb4525c.tex b/sail_latex_riscv/valzhandle_trap_extension9480b0ad72ce05ffcdcc27185eb4525c.tex new file mode 100644 index 00000000..fb1a92db --- /dev/null +++ b/sail_latex_riscv/valzhandle_trap_extension9480b0ad72ce05ffcdcc27185eb4525c.tex @@ -0,0 +1 @@ +handle_trap_extension : (Privilege, xlenbits, option(cheri_cause)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex b/sail_latex_riscv/valzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex new file mode 100644 index 00000000..a0375115 --- /dev/null +++ b/sail_latex_riscv/valzhasreservedotypee1cbb5365f130582a0df82f04b53cb52.tex @@ -0,0 +1 @@ +hasReservedOType : Capability -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhaveatomics63cb703b1e3f955440fac8b850da53f7.tex b/sail_latex_riscv/valzhaveatomics63cb703b1e3f955440fac8b850da53f7.tex new file mode 100644 index 00000000..8bf83b1b --- /dev/null +++ b/sail_latex_riscv/valzhaveatomics63cb703b1e3f955440fac8b850da53f7.tex @@ -0,0 +1 @@ +haveAtomics : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhavedextbb6a692871d46f160484ca963a3fffd0.tex b/sail_latex_riscv/valzhavedextbb6a692871d46f160484ca963a3fffd0.tex new file mode 100644 index 00000000..4f27e21e --- /dev/null +++ b/sail_latex_riscv/valzhavedextbb6a692871d46f160484ca963a3fffd0.tex @@ -0,0 +1 @@ +haveDExt : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhavefext496ba4ad5d47088bd723ab96ed6356d0.tex b/sail_latex_riscv/valzhavefext496ba4ad5d47088bd723ab96ed6356d0.tex new file mode 100644 index 00000000..6267817f --- /dev/null +++ b/sail_latex_riscv/valzhavefext496ba4ad5d47088bd723ab96ed6356d0.tex @@ -0,0 +1 @@ +haveFExt : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhavemuldivee13dcf875cf3974336f980d6be89b2a.tex b/sail_latex_riscv/valzhavemuldivee13dcf875cf3974336f980d6be89b2a.tex new file mode 100644 index 00000000..bd366482 --- /dev/null +++ b/sail_latex_riscv/valzhavemuldivee13dcf875cf3974336f980d6be89b2a.tex @@ -0,0 +1 @@ +haveMulDiv : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhavenext74060caf84942f39cfe17eb66bce56e4.tex b/sail_latex_riscv/valzhavenext74060caf84942f39cfe17eb66bce56e4.tex new file mode 100644 index 00000000..e8898ead --- /dev/null +++ b/sail_latex_riscv/valzhavenext74060caf84942f39cfe17eb66bce56e4.tex @@ -0,0 +1 @@ +haveNExt : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhavervcd1bab8584f566314057babec4a4bfcce.tex b/sail_latex_riscv/valzhavervcd1bab8584f566314057babec4a4bfcce.tex new file mode 100644 index 00000000..fc64fe6a --- /dev/null +++ b/sail_latex_riscv/valzhavervcd1bab8584f566314057babec4a4bfcce.tex @@ -0,0 +1 @@ +haveRVC : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhavesupmode3f08edf2b0386d18c650f34868f384db.tex b/sail_latex_riscv/valzhavesupmode3f08edf2b0386d18c650f34868f384db.tex new file mode 100644 index 00000000..7095f649 --- /dev/null +++ b/sail_latex_riscv/valzhavesupmode3f08edf2b0386d18c650f34868f384db.tex @@ -0,0 +1 @@ +haveSupMode : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhaveusrmode2e520828ead805e9613cc1f88f964861.tex b/sail_latex_riscv/valzhaveusrmode2e520828ead805e9613cc1f88f964861.tex new file mode 100644 index 00000000..5ed7f697 --- /dev/null +++ b/sail_latex_riscv/valzhaveusrmode2e520828ead805e9613cc1f88f964861.tex @@ -0,0 +1 @@ +haveUsrMode : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhavexcheri36112408abb05cceef19a84af1e5a22a.tex b/sail_latex_riscv/valzhavexcheri36112408abb05cceef19a84af1e5a22a.tex new file mode 100644 index 00000000..35582b57 --- /dev/null +++ b/sail_latex_riscv/valzhavexcheri36112408abb05cceef19a84af1e5a22a.tex @@ -0,0 +1 @@ +haveXcheri : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits6151f0f3396959dd9a279f1e74f7d7ec.tex b/sail_latex_riscv/valzhex_bits6151f0f3396959dd9a279f1e74f7d7ec.tex new file mode 100644 index 00000000..c908c79a --- /dev/null +++ b/sail_latex_riscv/valzhex_bits6151f0f3396959dd9a279f1e74f7d7ec.tex @@ -0,0 +1 @@ +hex_bits : forall ('n : Int). (int('n), bits('n)) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_1001007fc28a3cc2512c7863ca8f700d8b.tex b/sail_latex_riscv/valzhex_bits_1001007fc28a3cc2512c7863ca8f700d8b.tex new file mode 100644 index 00000000..247b94b5 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_1001007fc28a3cc2512c7863ca8f700d8b.tex @@ -0,0 +1 @@ +hex_bits_10 : bits(10) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_10_backwards3ea67a7e3b03c19fc3f62bce5d70adcf.tex b/sail_latex_riscv/valzhex_bits_10_backwards3ea67a7e3b03c19fc3f62bce5d70adcf.tex new file mode 100644 index 00000000..1a7145ad --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_10_backwards3ea67a7e3b03c19fc3f62bce5d70adcf.tex @@ -0,0 +1 @@ +hex_bits_10_backwards : string -> bits(10) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_10_backwards_matches40e05acb0a138e49841d114ad4d36956.tex b/sail_latex_riscv/valzhex_bits_10_backwards_matches40e05acb0a138e49841d114ad4d36956.tex new file mode 100644 index 00000000..8d22df7f --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_10_backwards_matches40e05acb0a138e49841d114ad4d36956.tex @@ -0,0 +1 @@ +hex_bits_10_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_10_forwards_matches5805c03590a8c87ee15c304ac5e14038.tex b/sail_latex_riscv/valzhex_bits_10_forwards_matches5805c03590a8c87ee15c304ac5e14038.tex new file mode 100644 index 00000000..68e517ba --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_10_forwards_matches5805c03590a8c87ee15c304ac5e14038.tex @@ -0,0 +1 @@ +hex_bits_10_forwards_matches : bits(10) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_10_forwardseca444da7d319d1932fce8e708381d1e.tex b/sail_latex_riscv/valzhex_bits_10_forwardseca444da7d319d1932fce8e708381d1e.tex new file mode 100644 index 00000000..4d0b5cb2 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_10_forwardseca444da7d319d1932fce8e708381d1e.tex @@ -0,0 +1 @@ +hex_bits_10_forwards : bits(10) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_10_matches_prefix1bc10569a97d5b943c4d0e1bee005436.tex b/sail_latex_riscv/valzhex_bits_10_matches_prefix1bc10569a97d5b943c4d0e1bee005436.tex new file mode 100644 index 00000000..9d01cf46 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_10_matches_prefix1bc10569a97d5b943c4d0e1bee005436.tex @@ -0,0 +1 @@ +hex_bits_10_matches_prefix : string -> option((bits(10), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_1196b03eaf6acc67335c0bb71c802e6a22.tex b/sail_latex_riscv/valzhex_bits_1196b03eaf6acc67335c0bb71c802e6a22.tex new file mode 100644 index 00000000..05317829 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_1196b03eaf6acc67335c0bb71c802e6a22.tex @@ -0,0 +1 @@ +hex_bits_11 : bits(11) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_11_backwards2baa8535235545b1d36570cd9bfa54d3.tex b/sail_latex_riscv/valzhex_bits_11_backwards2baa8535235545b1d36570cd9bfa54d3.tex new file mode 100644 index 00000000..5256bebd --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_11_backwards2baa8535235545b1d36570cd9bfa54d3.tex @@ -0,0 +1 @@ +hex_bits_11_backwards : string -> bits(11) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_11_backwards_matchesd1ccc1a72470b9d5d21bdc4ac13ff26b.tex b/sail_latex_riscv/valzhex_bits_11_backwards_matchesd1ccc1a72470b9d5d21bdc4ac13ff26b.tex new file mode 100644 index 00000000..7ee05c5c --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_11_backwards_matchesd1ccc1a72470b9d5d21bdc4ac13ff26b.tex @@ -0,0 +1 @@ +hex_bits_11_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_11_forwards_matchesc72e36f9e9259ad52cfd038ae9c0251f.tex b/sail_latex_riscv/valzhex_bits_11_forwards_matchesc72e36f9e9259ad52cfd038ae9c0251f.tex new file mode 100644 index 00000000..317fa917 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_11_forwards_matchesc72e36f9e9259ad52cfd038ae9c0251f.tex @@ -0,0 +1 @@ +hex_bits_11_forwards_matches : bits(11) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_11_forwardsa103ffbf0ab1e78130e8eca0e504aba5.tex b/sail_latex_riscv/valzhex_bits_11_forwardsa103ffbf0ab1e78130e8eca0e504aba5.tex new file mode 100644 index 00000000..17301cc4 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_11_forwardsa103ffbf0ab1e78130e8eca0e504aba5.tex @@ -0,0 +1 @@ +hex_bits_11_forwards : bits(11) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_11_matches_prefix5542021dd19d9d49c8135e0408dda5bf.tex b/sail_latex_riscv/valzhex_bits_11_matches_prefix5542021dd19d9d49c8135e0408dda5bf.tex new file mode 100644 index 00000000..d20dd1b2 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_11_matches_prefix5542021dd19d9d49c8135e0408dda5bf.tex @@ -0,0 +1 @@ +hex_bits_11_matches_prefix : string -> option((bits(11), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_125a4772f29c6286c50b66c991563e61c3.tex b/sail_latex_riscv/valzhex_bits_125a4772f29c6286c50b66c991563e61c3.tex new file mode 100644 index 00000000..dab33818 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_125a4772f29c6286c50b66c991563e61c3.tex @@ -0,0 +1 @@ +hex_bits_12 : bits(12) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_12_backwards3d80f810c3a0bfaf0d29151a18d72567.tex b/sail_latex_riscv/valzhex_bits_12_backwards3d80f810c3a0bfaf0d29151a18d72567.tex new file mode 100644 index 00000000..eac72ef3 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_12_backwards3d80f810c3a0bfaf0d29151a18d72567.tex @@ -0,0 +1 @@ +hex_bits_12_backwards : string -> bits(12) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_12_backwards_matches6a7e459d92157f0ba9dee2e4c7899300.tex b/sail_latex_riscv/valzhex_bits_12_backwards_matches6a7e459d92157f0ba9dee2e4c7899300.tex new file mode 100644 index 00000000..a12ccb5c --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_12_backwards_matches6a7e459d92157f0ba9dee2e4c7899300.tex @@ -0,0 +1 @@ +hex_bits_12_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_12_forwards_matches23afc09f193a32dea040a72b95ec91b2.tex b/sail_latex_riscv/valzhex_bits_12_forwards_matches23afc09f193a32dea040a72b95ec91b2.tex new file mode 100644 index 00000000..3558df50 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_12_forwards_matches23afc09f193a32dea040a72b95ec91b2.tex @@ -0,0 +1 @@ +hex_bits_12_forwards_matches : bits(12) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_12_forwardsfead99eab466bc9417dd261cbed56176.tex b/sail_latex_riscv/valzhex_bits_12_forwardsfead99eab466bc9417dd261cbed56176.tex new file mode 100644 index 00000000..3460e465 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_12_forwardsfead99eab466bc9417dd261cbed56176.tex @@ -0,0 +1 @@ +hex_bits_12_forwards : bits(12) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_13_backwards75db4a8adaa37e62b3ea51d810cbbf3b.tex b/sail_latex_riscv/valzhex_bits_13_backwards75db4a8adaa37e62b3ea51d810cbbf3b.tex new file mode 100644 index 00000000..f0a08bc5 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_13_backwards75db4a8adaa37e62b3ea51d810cbbf3b.tex @@ -0,0 +1 @@ +hex_bits_13_backwards : string -> bits(13) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_13_backwards_matches3380960c8e44f21f0eeafd0244600ee6.tex b/sail_latex_riscv/valzhex_bits_13_backwards_matches3380960c8e44f21f0eeafd0244600ee6.tex new file mode 100644 index 00000000..d1e10c3c --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_13_backwards_matches3380960c8e44f21f0eeafd0244600ee6.tex @@ -0,0 +1 @@ +hex_bits_13_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_13_forwards4a6f3d80543dcfc7821c2bf16e534c80.tex b/sail_latex_riscv/valzhex_bits_13_forwards4a6f3d80543dcfc7821c2bf16e534c80.tex new file mode 100644 index 00000000..162fceb1 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_13_forwards4a6f3d80543dcfc7821c2bf16e534c80.tex @@ -0,0 +1 @@ +hex_bits_13_forwards : bits(13) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_13_forwards_matches24cf47063279787f52ede006100876ff.tex b/sail_latex_riscv/valzhex_bits_13_forwards_matches24cf47063279787f52ede006100876ff.tex new file mode 100644 index 00000000..e63af23b --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_13_forwards_matches24cf47063279787f52ede006100876ff.tex @@ -0,0 +1 @@ +hex_bits_13_forwards_matches : bits(13) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_13_matches_prefix808dd1e0db4d0e2cbb2964dee566f987.tex b/sail_latex_riscv/valzhex_bits_13_matches_prefix808dd1e0db4d0e2cbb2964dee566f987.tex new file mode 100644 index 00000000..d2df009c --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_13_matches_prefix808dd1e0db4d0e2cbb2964dee566f987.tex @@ -0,0 +1 @@ +hex_bits_13_matches_prefix : string -> option((bits(13), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_13f2e19b07147e1bc75b3a752515303583.tex b/sail_latex_riscv/valzhex_bits_13f2e19b07147e1bc75b3a752515303583.tex new file mode 100644 index 00000000..756fe16f --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_13f2e19b07147e1bc75b3a752515303583.tex @@ -0,0 +1 @@ +hex_bits_13 : bits(13) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_1478f9a2bfac5b1844d4822c98afbb89d.tex b/sail_latex_riscv/valzhex_bits_1478f9a2bfac5b1844d4822c98afbb89d.tex new file mode 100644 index 00000000..d718ff05 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_1478f9a2bfac5b1844d4822c98afbb89d.tex @@ -0,0 +1 @@ +hex_bits_1 : bits(1) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_147ca431b3e814f7be996cd1b6ec3c0902.tex b/sail_latex_riscv/valzhex_bits_147ca431b3e814f7be996cd1b6ec3c0902.tex new file mode 100644 index 00000000..9b8e247e --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_147ca431b3e814f7be996cd1b6ec3c0902.tex @@ -0,0 +1 @@ +hex_bits_14 : bits(14) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_14_backwards825f2ad69791fa9a1bb2792ac85efc54.tex b/sail_latex_riscv/valzhex_bits_14_backwards825f2ad69791fa9a1bb2792ac85efc54.tex new file mode 100644 index 00000000..d8b9eccb --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_14_backwards825f2ad69791fa9a1bb2792ac85efc54.tex @@ -0,0 +1 @@ +hex_bits_14_backwards : string -> bits(14) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_14_backwards_matches7a9acb89282cc5c0ad18d89d22bf3cfa.tex b/sail_latex_riscv/valzhex_bits_14_backwards_matches7a9acb89282cc5c0ad18d89d22bf3cfa.tex new file mode 100644 index 00000000..ab416381 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_14_backwards_matches7a9acb89282cc5c0ad18d89d22bf3cfa.tex @@ -0,0 +1 @@ +hex_bits_14_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_14_forwards8f53488826326c38c678631a29ef042b.tex b/sail_latex_riscv/valzhex_bits_14_forwards8f53488826326c38c678631a29ef042b.tex new file mode 100644 index 00000000..2669ecc6 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_14_forwards8f53488826326c38c678631a29ef042b.tex @@ -0,0 +1 @@ +hex_bits_14_forwards : bits(14) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_14_forwards_matches229689dc85657ccebc6a0143fb21144e.tex b/sail_latex_riscv/valzhex_bits_14_forwards_matches229689dc85657ccebc6a0143fb21144e.tex new file mode 100644 index 00000000..df8da648 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_14_forwards_matches229689dc85657ccebc6a0143fb21144e.tex @@ -0,0 +1 @@ +hex_bits_14_forwards_matches : bits(14) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_14_matches_prefix43b0d69de97191b01d4d4ad6d99d2952.tex b/sail_latex_riscv/valzhex_bits_14_matches_prefix43b0d69de97191b01d4d4ad6d99d2952.tex new file mode 100644 index 00000000..3fe3000d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_14_matches_prefix43b0d69de97191b01d4d4ad6d99d2952.tex @@ -0,0 +1 @@ +hex_bits_14_matches_prefix : string -> option((bits(14), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_15073380baa5f552c999850321b1ecde51.tex b/sail_latex_riscv/valzhex_bits_15073380baa5f552c999850321b1ecde51.tex new file mode 100644 index 00000000..515f33be --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_15073380baa5f552c999850321b1ecde51.tex @@ -0,0 +1 @@ +hex_bits_15 : bits(15) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_15_backwards_matchesc6cd9235f40d6808371474280c964ff1.tex b/sail_latex_riscv/valzhex_bits_15_backwards_matchesc6cd9235f40d6808371474280c964ff1.tex new file mode 100644 index 00000000..65e03504 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_15_backwards_matchesc6cd9235f40d6808371474280c964ff1.tex @@ -0,0 +1 @@ +hex_bits_15_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_15_backwardscb4ce484e79dc8d005cf2bda729e7867.tex b/sail_latex_riscv/valzhex_bits_15_backwardscb4ce484e79dc8d005cf2bda729e7867.tex new file mode 100644 index 00000000..8aa624e5 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_15_backwardscb4ce484e79dc8d005cf2bda729e7867.tex @@ -0,0 +1 @@ +hex_bits_15_backwards : string -> bits(15) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_15_forwards6c990ff9d54de24c898e16e2e488b179.tex b/sail_latex_riscv/valzhex_bits_15_forwards6c990ff9d54de24c898e16e2e488b179.tex new file mode 100644 index 00000000..1de36075 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_15_forwards6c990ff9d54de24c898e16e2e488b179.tex @@ -0,0 +1 @@ +hex_bits_15_forwards : bits(15) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_15_forwards_matches923e93be7d0b466ae08582f59a3c9529.tex b/sail_latex_riscv/valzhex_bits_15_forwards_matches923e93be7d0b466ae08582f59a3c9529.tex new file mode 100644 index 00000000..4cf04f7b --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_15_forwards_matches923e93be7d0b466ae08582f59a3c9529.tex @@ -0,0 +1 @@ +hex_bits_15_forwards_matches : bits(15) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_15_matches_prefixa2a5a94154c4b4c6efd07c71b5146350.tex b/sail_latex_riscv/valzhex_bits_15_matches_prefixa2a5a94154c4b4c6efd07c71b5146350.tex new file mode 100644 index 00000000..cb087489 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_15_matches_prefixa2a5a94154c4b4c6efd07c71b5146350.tex @@ -0,0 +1 @@ +hex_bits_15_matches_prefix : string -> option((bits(15), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_167d95ad16536f8aabd412012ac1a3e03f.tex b/sail_latex_riscv/valzhex_bits_167d95ad16536f8aabd412012ac1a3e03f.tex new file mode 100644 index 00000000..7b4e6535 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_167d95ad16536f8aabd412012ac1a3e03f.tex @@ -0,0 +1 @@ +hex_bits_16 : bits(16) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_16_backwards8afef1c1c4af4f381f60fc4dc7267c9c.tex b/sail_latex_riscv/valzhex_bits_16_backwards8afef1c1c4af4f381f60fc4dc7267c9c.tex new file mode 100644 index 00000000..dcd8a982 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_16_backwards8afef1c1c4af4f381f60fc4dc7267c9c.tex @@ -0,0 +1 @@ +hex_bits_16_backwards : string -> bits(16) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_16_backwards_matches8ff37bbe35e588c9d66f041b5b32d8e0.tex b/sail_latex_riscv/valzhex_bits_16_backwards_matches8ff37bbe35e588c9d66f041b5b32d8e0.tex new file mode 100644 index 00000000..29499dfe --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_16_backwards_matches8ff37bbe35e588c9d66f041b5b32d8e0.tex @@ -0,0 +1 @@ +hex_bits_16_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_16_forwards7f61f6684c0758bacebc97ae288552c8.tex b/sail_latex_riscv/valzhex_bits_16_forwards7f61f6684c0758bacebc97ae288552c8.tex new file mode 100644 index 00000000..4b35bbcf --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_16_forwards7f61f6684c0758bacebc97ae288552c8.tex @@ -0,0 +1 @@ +hex_bits_16_forwards : bits(16) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_16_forwards_matches99127000f54090aaa9f0aeb2c20f4685.tex b/sail_latex_riscv/valzhex_bits_16_forwards_matches99127000f54090aaa9f0aeb2c20f4685.tex new file mode 100644 index 00000000..c3155251 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_16_forwards_matches99127000f54090aaa9f0aeb2c20f4685.tex @@ -0,0 +1 @@ +hex_bits_16_forwards_matches : bits(16) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_16_matches_prefix38bcd18ff44c77953c7f4f991dfa37b8.tex b/sail_latex_riscv/valzhex_bits_16_matches_prefix38bcd18ff44c77953c7f4f991dfa37b8.tex new file mode 100644 index 00000000..cca89043 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_16_matches_prefix38bcd18ff44c77953c7f4f991dfa37b8.tex @@ -0,0 +1 @@ +hex_bits_16_matches_prefix : string -> option((bits(16), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_17_backwards96076e6b0ee1d8c887acfae20a696145.tex b/sail_latex_riscv/valzhex_bits_17_backwards96076e6b0ee1d8c887acfae20a696145.tex new file mode 100644 index 00000000..076f5b90 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_17_backwards96076e6b0ee1d8c887acfae20a696145.tex @@ -0,0 +1 @@ +hex_bits_17_backwards : string -> bits(17) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_17_backwards_matchesd594e6fb2cf338d85aa8e3a859821359.tex b/sail_latex_riscv/valzhex_bits_17_backwards_matchesd594e6fb2cf338d85aa8e3a859821359.tex new file mode 100644 index 00000000..c4692acb --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_17_backwards_matchesd594e6fb2cf338d85aa8e3a859821359.tex @@ -0,0 +1 @@ +hex_bits_17_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_17_forwards1d1b1aacf0ce8d2f042cb60029feef84.tex b/sail_latex_riscv/valzhex_bits_17_forwards1d1b1aacf0ce8d2f042cb60029feef84.tex new file mode 100644 index 00000000..e6cac3a6 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_17_forwards1d1b1aacf0ce8d2f042cb60029feef84.tex @@ -0,0 +1 @@ +hex_bits_17_forwards : bits(17) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_17_forwards_matches45df8bfd52709ac4d9906f538498742e.tex b/sail_latex_riscv/valzhex_bits_17_forwards_matches45df8bfd52709ac4d9906f538498742e.tex new file mode 100644 index 00000000..f13c28fa --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_17_forwards_matches45df8bfd52709ac4d9906f538498742e.tex @@ -0,0 +1 @@ +hex_bits_17_forwards_matches : bits(17) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_17_matches_prefix02c803ee497f2adf656b9a546dc9d148.tex b/sail_latex_riscv/valzhex_bits_17_matches_prefix02c803ee497f2adf656b9a546dc9d148.tex new file mode 100644 index 00000000..4e093a73 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_17_matches_prefix02c803ee497f2adf656b9a546dc9d148.tex @@ -0,0 +1 @@ +hex_bits_17_matches_prefix : string -> option((bits(17), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_17d357434a9e9aecc580dae54ef5402fcf.tex b/sail_latex_riscv/valzhex_bits_17d357434a9e9aecc580dae54ef5402fcf.tex new file mode 100644 index 00000000..54a98c61 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_17d357434a9e9aecc580dae54ef5402fcf.tex @@ -0,0 +1 @@ +hex_bits_17 : bits(17) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_1819473bd89c251dd41ec313d06e46da0e.tex b/sail_latex_riscv/valzhex_bits_1819473bd89c251dd41ec313d06e46da0e.tex new file mode 100644 index 00000000..353894f0 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_1819473bd89c251dd41ec313d06e46da0e.tex @@ -0,0 +1 @@ +hex_bits_18 : bits(18) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_18_backwards0500c1a0187a21072c3255f60243909f.tex b/sail_latex_riscv/valzhex_bits_18_backwards0500c1a0187a21072c3255f60243909f.tex new file mode 100644 index 00000000..c52228e6 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_18_backwards0500c1a0187a21072c3255f60243909f.tex @@ -0,0 +1 @@ +hex_bits_18_backwards : string -> bits(18) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_18_backwards_matches72b528c9dd8e982607b88bd8ab46a37d.tex b/sail_latex_riscv/valzhex_bits_18_backwards_matches72b528c9dd8e982607b88bd8ab46a37d.tex new file mode 100644 index 00000000..02f29ac5 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_18_backwards_matches72b528c9dd8e982607b88bd8ab46a37d.tex @@ -0,0 +1 @@ +hex_bits_18_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_18_forwards47e61ad2851c0c0e789494a5e30c9e1c.tex b/sail_latex_riscv/valzhex_bits_18_forwards47e61ad2851c0c0e789494a5e30c9e1c.tex new file mode 100644 index 00000000..40e19b20 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_18_forwards47e61ad2851c0c0e789494a5e30c9e1c.tex @@ -0,0 +1 @@ +hex_bits_18_forwards : bits(18) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_18_forwards_matches6e035e739a1d5414f87357bc391d08b3.tex b/sail_latex_riscv/valzhex_bits_18_forwards_matches6e035e739a1d5414f87357bc391d08b3.tex new file mode 100644 index 00000000..e004725b --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_18_forwards_matches6e035e739a1d5414f87357bc391d08b3.tex @@ -0,0 +1 @@ +hex_bits_18_forwards_matches : bits(18) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_18_matches_prefix0123403473ed4dd9dbffc716d963c568.tex b/sail_latex_riscv/valzhex_bits_18_matches_prefix0123403473ed4dd9dbffc716d963c568.tex new file mode 100644 index 00000000..70fad3b3 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_18_matches_prefix0123403473ed4dd9dbffc716d963c568.tex @@ -0,0 +1 @@ +hex_bits_18_matches_prefix : string -> option((bits(18), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_1938ed2064ef7ce8152e6dfd8213383d7e.tex b/sail_latex_riscv/valzhex_bits_1938ed2064ef7ce8152e6dfd8213383d7e.tex new file mode 100644 index 00000000..42316429 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_1938ed2064ef7ce8152e6dfd8213383d7e.tex @@ -0,0 +1 @@ +hex_bits_19 : bits(19) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_19_backwards8a1ab4ffc6b6e5e3c0cf6702ec74b710.tex b/sail_latex_riscv/valzhex_bits_19_backwards8a1ab4ffc6b6e5e3c0cf6702ec74b710.tex new file mode 100644 index 00000000..b87a6b9a --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_19_backwards8a1ab4ffc6b6e5e3c0cf6702ec74b710.tex @@ -0,0 +1 @@ +hex_bits_19_backwards : string -> bits(19) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_19_backwards_matchesd823f57016d205b9df109966ee967db9.tex b/sail_latex_riscv/valzhex_bits_19_backwards_matchesd823f57016d205b9df109966ee967db9.tex new file mode 100644 index 00000000..ee8ab7c6 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_19_backwards_matchesd823f57016d205b9df109966ee967db9.tex @@ -0,0 +1 @@ +hex_bits_19_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_19_forwards_matches07c7d804aca651680480475ad9d45b66.tex b/sail_latex_riscv/valzhex_bits_19_forwards_matches07c7d804aca651680480475ad9d45b66.tex new file mode 100644 index 00000000..4aba26c1 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_19_forwards_matches07c7d804aca651680480475ad9d45b66.tex @@ -0,0 +1 @@ +hex_bits_19_forwards_matches : bits(19) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_19_forwardsc23db4c1e0ead6b3252ea4464c668ee1.tex b/sail_latex_riscv/valzhex_bits_19_forwardsc23db4c1e0ead6b3252ea4464c668ee1.tex new file mode 100644 index 00000000..3ec3d548 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_19_forwardsc23db4c1e0ead6b3252ea4464c668ee1.tex @@ -0,0 +1 @@ +hex_bits_19_forwards : bits(19) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_19_matches_prefix28d0e3106abb68242ac4e35ed75b7eea.tex b/sail_latex_riscv/valzhex_bits_19_matches_prefix28d0e3106abb68242ac4e35ed75b7eea.tex new file mode 100644 index 00000000..3e1d975a --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_19_matches_prefix28d0e3106abb68242ac4e35ed75b7eea.tex @@ -0,0 +1 @@ +hex_bits_19_matches_prefix : string -> option((bits(19), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_1_backwards90e5440bb0c40b9363498a8d972dba41.tex b/sail_latex_riscv/valzhex_bits_1_backwards90e5440bb0c40b9363498a8d972dba41.tex new file mode 100644 index 00000000..1420cd57 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_1_backwards90e5440bb0c40b9363498a8d972dba41.tex @@ -0,0 +1 @@ +hex_bits_1_backwards : string -> bits(1) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_1_backwards_matches3d78f15da2768104290b952c286f2f91.tex b/sail_latex_riscv/valzhex_bits_1_backwards_matches3d78f15da2768104290b952c286f2f91.tex new file mode 100644 index 00000000..538688f0 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_1_backwards_matches3d78f15da2768104290b952c286f2f91.tex @@ -0,0 +1 @@ +hex_bits_1_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_1_forwards_matches95bbf636d6fecebea6adab4fb1b42ac0.tex b/sail_latex_riscv/valzhex_bits_1_forwards_matches95bbf636d6fecebea6adab4fb1b42ac0.tex new file mode 100644 index 00000000..5c24195d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_1_forwards_matches95bbf636d6fecebea6adab4fb1b42ac0.tex @@ -0,0 +1 @@ +hex_bits_1_forwards_matches : bits(1) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_1_forwardsf283099d0fc824606ed0d57afc78de8a.tex b/sail_latex_riscv/valzhex_bits_1_forwardsf283099d0fc824606ed0d57afc78de8a.tex new file mode 100644 index 00000000..65717f53 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_1_forwardsf283099d0fc824606ed0d57afc78de8a.tex @@ -0,0 +1 @@ +hex_bits_1_forwards : bits(1) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_1_matches_prefixd812208f2aa5a7b3cf37c8de5c575662.tex b/sail_latex_riscv/valzhex_bits_1_matches_prefixd812208f2aa5a7b3cf37c8de5c575662.tex new file mode 100644 index 00000000..718e23da --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_1_matches_prefixd812208f2aa5a7b3cf37c8de5c575662.tex @@ -0,0 +1 @@ +hex_bits_1_matches_prefix : string -> option((bits(1), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_20073767bf3c4e755df8668de0f192df95.tex b/sail_latex_riscv/valzhex_bits_20073767bf3c4e755df8668de0f192df95.tex new file mode 100644 index 00000000..c2903d58 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_20073767bf3c4e755df8668de0f192df95.tex @@ -0,0 +1 @@ +hex_bits_20 : bits(20) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_20_backwards_matches8c546ae28d487f510dca7fe30ea629c5.tex b/sail_latex_riscv/valzhex_bits_20_backwards_matches8c546ae28d487f510dca7fe30ea629c5.tex new file mode 100644 index 00000000..1b7b1715 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_20_backwards_matches8c546ae28d487f510dca7fe30ea629c5.tex @@ -0,0 +1 @@ +hex_bits_20_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_20_backwardsed333b625b69d435d8e8df1b980d11ef.tex b/sail_latex_riscv/valzhex_bits_20_backwardsed333b625b69d435d8e8df1b980d11ef.tex new file mode 100644 index 00000000..5042c639 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_20_backwardsed333b625b69d435d8e8df1b980d11ef.tex @@ -0,0 +1 @@ +hex_bits_20_backwards : string -> bits(20) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_20_forwards00e9d80df23932a0cd55fe8e4cea5260.tex b/sail_latex_riscv/valzhex_bits_20_forwards00e9d80df23932a0cd55fe8e4cea5260.tex new file mode 100644 index 00000000..2adb2022 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_20_forwards00e9d80df23932a0cd55fe8e4cea5260.tex @@ -0,0 +1 @@ +hex_bits_20_forwards : bits(20) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_20_forwards_matchesde8955f96663b48788095ef74c50f0aa.tex b/sail_latex_riscv/valzhex_bits_20_forwards_matchesde8955f96663b48788095ef74c50f0aa.tex new file mode 100644 index 00000000..41afd88d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_20_forwards_matchesde8955f96663b48788095ef74c50f0aa.tex @@ -0,0 +1 @@ +hex_bits_20_forwards_matches : bits(20) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_20_matches_prefixdf9ef269745a9eb5e6b479b1935b64ab.tex b/sail_latex_riscv/valzhex_bits_20_matches_prefixdf9ef269745a9eb5e6b479b1935b64ab.tex new file mode 100644 index 00000000..76dcb0f0 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_20_matches_prefixdf9ef269745a9eb5e6b479b1935b64ab.tex @@ -0,0 +1 @@ +hex_bits_20_matches_prefix : string -> option((bits(20), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_215a399be0fd96b92fed46a34ed6d97e44.tex b/sail_latex_riscv/valzhex_bits_215a399be0fd96b92fed46a34ed6d97e44.tex new file mode 100644 index 00000000..706efda4 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_215a399be0fd96b92fed46a34ed6d97e44.tex @@ -0,0 +1 @@ +hex_bits_21 : bits(21) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_21_backwards_matches477a84c0bff49ab6511438197e40d9c3.tex b/sail_latex_riscv/valzhex_bits_21_backwards_matches477a84c0bff49ab6511438197e40d9c3.tex new file mode 100644 index 00000000..9430932d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_21_backwards_matches477a84c0bff49ab6511438197e40d9c3.tex @@ -0,0 +1 @@ +hex_bits_21_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_21_backwardsc44f7bb35fd47e4506558a2d7d995f8e.tex b/sail_latex_riscv/valzhex_bits_21_backwardsc44f7bb35fd47e4506558a2d7d995f8e.tex new file mode 100644 index 00000000..bf01c4bf --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_21_backwardsc44f7bb35fd47e4506558a2d7d995f8e.tex @@ -0,0 +1 @@ +hex_bits_21_backwards : string -> bits(21) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_21_forwards5d6372cc66bb45095acb2dbe03a6acfc.tex b/sail_latex_riscv/valzhex_bits_21_forwards5d6372cc66bb45095acb2dbe03a6acfc.tex new file mode 100644 index 00000000..1883bbd4 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_21_forwards5d6372cc66bb45095acb2dbe03a6acfc.tex @@ -0,0 +1 @@ +hex_bits_21_forwards : bits(21) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_21_forwards_matches05f5fa78d5ad49b7efae27025b546cb7.tex b/sail_latex_riscv/valzhex_bits_21_forwards_matches05f5fa78d5ad49b7efae27025b546cb7.tex new file mode 100644 index 00000000..8e6a73cd --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_21_forwards_matches05f5fa78d5ad49b7efae27025b546cb7.tex @@ -0,0 +1 @@ +hex_bits_21_forwards_matches : bits(21) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_21_matches_prefix159b58fe3bdaba7ade8041d986b2ecf6.tex b/sail_latex_riscv/valzhex_bits_21_matches_prefix159b58fe3bdaba7ade8041d986b2ecf6.tex new file mode 100644 index 00000000..1d847b39 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_21_matches_prefix159b58fe3bdaba7ade8041d986b2ecf6.tex @@ -0,0 +1 @@ +hex_bits_21_matches_prefix : string -> option((bits(21), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_228df71d429e9677759c4b9421597b9624.tex b/sail_latex_riscv/valzhex_bits_228df71d429e9677759c4b9421597b9624.tex new file mode 100644 index 00000000..b1bcdf90 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_228df71d429e9677759c4b9421597b9624.tex @@ -0,0 +1 @@ +hex_bits_22 : bits(22) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_22_backwards_matchesfd56758d4cd0fd6150ee51afa372c83b.tex b/sail_latex_riscv/valzhex_bits_22_backwards_matchesfd56758d4cd0fd6150ee51afa372c83b.tex new file mode 100644 index 00000000..3e09476f --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_22_backwards_matchesfd56758d4cd0fd6150ee51afa372c83b.tex @@ -0,0 +1 @@ +hex_bits_22_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_22_backwardsfbed1dd3d215529ff44a9e8165218968.tex b/sail_latex_riscv/valzhex_bits_22_backwardsfbed1dd3d215529ff44a9e8165218968.tex new file mode 100644 index 00000000..9980644f --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_22_backwardsfbed1dd3d215529ff44a9e8165218968.tex @@ -0,0 +1 @@ +hex_bits_22_backwards : string -> bits(22) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_22_forwards5f20df76cf594392e558c43103ffc6e4.tex b/sail_latex_riscv/valzhex_bits_22_forwards5f20df76cf594392e558c43103ffc6e4.tex new file mode 100644 index 00000000..62f68451 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_22_forwards5f20df76cf594392e558c43103ffc6e4.tex @@ -0,0 +1 @@ +hex_bits_22_forwards : bits(22) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_22_forwards_matches4fe97899c8181992923cd1daaa36d526.tex b/sail_latex_riscv/valzhex_bits_22_forwards_matches4fe97899c8181992923cd1daaa36d526.tex new file mode 100644 index 00000000..dc451829 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_22_forwards_matches4fe97899c8181992923cd1daaa36d526.tex @@ -0,0 +1 @@ +hex_bits_22_forwards_matches : bits(22) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_22_matches_prefix1a790a92ddf1d11e5f9d0ff8b4ca8b1c.tex b/sail_latex_riscv/valzhex_bits_22_matches_prefix1a790a92ddf1d11e5f9d0ff8b4ca8b1c.tex new file mode 100644 index 00000000..d5522c6a --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_22_matches_prefix1a790a92ddf1d11e5f9d0ff8b4ca8b1c.tex @@ -0,0 +1 @@ +hex_bits_22_matches_prefix : string -> option((bits(22), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_23418f7302c0b7161a092d463e4d8af7dc.tex b/sail_latex_riscv/valzhex_bits_23418f7302c0b7161a092d463e4d8af7dc.tex new file mode 100644 index 00000000..6aafb562 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_23418f7302c0b7161a092d463e4d8af7dc.tex @@ -0,0 +1 @@ +hex_bits_23 : bits(23) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_23_backwards2183795dfc2ff2f588be2709c2cd7639.tex b/sail_latex_riscv/valzhex_bits_23_backwards2183795dfc2ff2f588be2709c2cd7639.tex new file mode 100644 index 00000000..7c47c669 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_23_backwards2183795dfc2ff2f588be2709c2cd7639.tex @@ -0,0 +1 @@ +hex_bits_23_backwards : string -> bits(23) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_23_backwards_matchesa97370178cb502dd696426e4a347c318.tex b/sail_latex_riscv/valzhex_bits_23_backwards_matchesa97370178cb502dd696426e4a347c318.tex new file mode 100644 index 00000000..a39e0429 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_23_backwards_matchesa97370178cb502dd696426e4a347c318.tex @@ -0,0 +1 @@ +hex_bits_23_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_23_forwards_matchesb58b33da7b8d1a86392eabd6cc87b2c3.tex b/sail_latex_riscv/valzhex_bits_23_forwards_matchesb58b33da7b8d1a86392eabd6cc87b2c3.tex new file mode 100644 index 00000000..1230ddf3 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_23_forwards_matchesb58b33da7b8d1a86392eabd6cc87b2c3.tex @@ -0,0 +1 @@ +hex_bits_23_forwards_matches : bits(23) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_23_forwardsdd8792f3a53735041dd06c758d6e9f7e.tex b/sail_latex_riscv/valzhex_bits_23_forwardsdd8792f3a53735041dd06c758d6e9f7e.tex new file mode 100644 index 00000000..1fbcf040 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_23_forwardsdd8792f3a53735041dd06c758d6e9f7e.tex @@ -0,0 +1 @@ +hex_bits_23_forwards : bits(23) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_23_matches_prefix48403fc7c51b83fad5e40b0f6370b8fa.tex b/sail_latex_riscv/valzhex_bits_23_matches_prefix48403fc7c51b83fad5e40b0f6370b8fa.tex new file mode 100644 index 00000000..017d95b4 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_23_matches_prefix48403fc7c51b83fad5e40b0f6370b8fa.tex @@ -0,0 +1 @@ +hex_bits_23_matches_prefix : string -> option((bits(23), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_246fe29a7e07e79124e13aa086639a725a.tex b/sail_latex_riscv/valzhex_bits_246fe29a7e07e79124e13aa086639a725a.tex new file mode 100644 index 00000000..604cd9f6 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_246fe29a7e07e79124e13aa086639a725a.tex @@ -0,0 +1 @@ +hex_bits_24 : bits(24) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_24_backwards_matchesb2a483aa8b7cae87c37d98bc8b2a7345.tex b/sail_latex_riscv/valzhex_bits_24_backwards_matchesb2a483aa8b7cae87c37d98bc8b2a7345.tex new file mode 100644 index 00000000..9d2342e9 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_24_backwards_matchesb2a483aa8b7cae87c37d98bc8b2a7345.tex @@ -0,0 +1 @@ +hex_bits_24_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_24_backwardsa48c754c7049ebcb72d1fbba8bcfaadf.tex b/sail_latex_riscv/valzhex_bits_24_backwardsa48c754c7049ebcb72d1fbba8bcfaadf.tex new file mode 100644 index 00000000..978053f9 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_24_backwardsa48c754c7049ebcb72d1fbba8bcfaadf.tex @@ -0,0 +1 @@ +hex_bits_24_backwards : string -> bits(24) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_24_forwards_matchesf4dd0da48edd6a31433b0bae1bedc1f5.tex b/sail_latex_riscv/valzhex_bits_24_forwards_matchesf4dd0da48edd6a31433b0bae1bedc1f5.tex new file mode 100644 index 00000000..30f60b23 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_24_forwards_matchesf4dd0da48edd6a31433b0bae1bedc1f5.tex @@ -0,0 +1 @@ +hex_bits_24_forwards_matches : bits(24) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_24_forwardsdeaf00c9fe92ade0c2e92648a2b58039.tex b/sail_latex_riscv/valzhex_bits_24_forwardsdeaf00c9fe92ade0c2e92648a2b58039.tex new file mode 100644 index 00000000..c6905dd5 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_24_forwardsdeaf00c9fe92ade0c2e92648a2b58039.tex @@ -0,0 +1 @@ +hex_bits_24_forwards : bits(24) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_24_matches_prefix6ba2f72e46135bdb8c80c62ad4b58e8f.tex b/sail_latex_riscv/valzhex_bits_24_matches_prefix6ba2f72e46135bdb8c80c62ad4b58e8f.tex new file mode 100644 index 00000000..5b3642c9 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_24_matches_prefix6ba2f72e46135bdb8c80c62ad4b58e8f.tex @@ -0,0 +1 @@ +hex_bits_24_matches_prefix : string -> option((bits(24), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_25_backwards_matchese97e136616a70048191383b2a45471f6.tex b/sail_latex_riscv/valzhex_bits_25_backwards_matchese97e136616a70048191383b2a45471f6.tex new file mode 100644 index 00000000..687671f2 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_25_backwards_matchese97e136616a70048191383b2a45471f6.tex @@ -0,0 +1 @@ +hex_bits_25_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_25_backwardsb4f6ac6cc03e034620b7a4a11a89c5fc.tex b/sail_latex_riscv/valzhex_bits_25_backwardsb4f6ac6cc03e034620b7a4a11a89c5fc.tex new file mode 100644 index 00000000..b1c0a9ac --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_25_backwardsb4f6ac6cc03e034620b7a4a11a89c5fc.tex @@ -0,0 +1 @@ +hex_bits_25_backwards : string -> bits(25) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_25_forwards72bc0d414786f2c38ca3e1ba78cab739.tex b/sail_latex_riscv/valzhex_bits_25_forwards72bc0d414786f2c38ca3e1ba78cab739.tex new file mode 100644 index 00000000..2b7a8076 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_25_forwards72bc0d414786f2c38ca3e1ba78cab739.tex @@ -0,0 +1 @@ +hex_bits_25_forwards : bits(25) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_25_forwards_matches6d8831afa1ed150c2dca6afcd8d46fd1.tex b/sail_latex_riscv/valzhex_bits_25_forwards_matches6d8831afa1ed150c2dca6afcd8d46fd1.tex new file mode 100644 index 00000000..822e3c3c --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_25_forwards_matches6d8831afa1ed150c2dca6afcd8d46fd1.tex @@ -0,0 +1 @@ +hex_bits_25_forwards_matches : bits(25) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_25_matches_prefixa3fd9e9a9ab3f00e09575979dd9a94e8.tex b/sail_latex_riscv/valzhex_bits_25_matches_prefixa3fd9e9a9ab3f00e09575979dd9a94e8.tex new file mode 100644 index 00000000..e76939ac --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_25_matches_prefixa3fd9e9a9ab3f00e09575979dd9a94e8.tex @@ -0,0 +1 @@ +hex_bits_25_matches_prefix : string -> option((bits(25), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_25b2fb96ee1c2b78dcefb54132cd9af05a.tex b/sail_latex_riscv/valzhex_bits_25b2fb96ee1c2b78dcefb54132cd9af05a.tex new file mode 100644 index 00000000..45c7a452 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_25b2fb96ee1c2b78dcefb54132cd9af05a.tex @@ -0,0 +1 @@ +hex_bits_25 : bits(25) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_26663364c85fd29e21280b999b60cb2a55.tex b/sail_latex_riscv/valzhex_bits_26663364c85fd29e21280b999b60cb2a55.tex new file mode 100644 index 00000000..0ea5273d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_26663364c85fd29e21280b999b60cb2a55.tex @@ -0,0 +1 @@ +hex_bits_26 : bits(26) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_26_backwards_matches0ea73e31736f776e20958f45ec3e81bd.tex b/sail_latex_riscv/valzhex_bits_26_backwards_matches0ea73e31736f776e20958f45ec3e81bd.tex new file mode 100644 index 00000000..8c6bf7ff --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_26_backwards_matches0ea73e31736f776e20958f45ec3e81bd.tex @@ -0,0 +1 @@ +hex_bits_26_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_26_backwardsca9980b4fb1beb5e20216094b1b6b352.tex b/sail_latex_riscv/valzhex_bits_26_backwardsca9980b4fb1beb5e20216094b1b6b352.tex new file mode 100644 index 00000000..0a8fae20 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_26_backwardsca9980b4fb1beb5e20216094b1b6b352.tex @@ -0,0 +1 @@ +hex_bits_26_backwards : string -> bits(26) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_26_forwards5a6114b9bf479d01fa3a9e2beec5d91b.tex b/sail_latex_riscv/valzhex_bits_26_forwards5a6114b9bf479d01fa3a9e2beec5d91b.tex new file mode 100644 index 00000000..43bec9fb --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_26_forwards5a6114b9bf479d01fa3a9e2beec5d91b.tex @@ -0,0 +1 @@ +hex_bits_26_forwards : bits(26) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_26_forwards_matchesec5940b6c813530a4c8c509af6c000b6.tex b/sail_latex_riscv/valzhex_bits_26_forwards_matchesec5940b6c813530a4c8c509af6c000b6.tex new file mode 100644 index 00000000..afd0e32d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_26_forwards_matchesec5940b6c813530a4c8c509af6c000b6.tex @@ -0,0 +1 @@ +hex_bits_26_forwards_matches : bits(26) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_26_matches_prefix7b5176f43e479ddf2dec5f4a2011b98f.tex b/sail_latex_riscv/valzhex_bits_26_matches_prefix7b5176f43e479ddf2dec5f4a2011b98f.tex new file mode 100644 index 00000000..5f8fc2a3 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_26_matches_prefix7b5176f43e479ddf2dec5f4a2011b98f.tex @@ -0,0 +1 @@ +hex_bits_26_matches_prefix : string -> option((bits(26), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_270bd1024c2f2d5860abcddb1e5cdd513.tex b/sail_latex_riscv/valzhex_bits_270bd1024c2f2d5860abcddb1e5cdd513.tex new file mode 100644 index 00000000..fd7539f3 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_270bd1024c2f2d5860abcddb1e5cdd513.tex @@ -0,0 +1 @@ +hex_bits_2 : bits(2) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_27_backwards4d49d22a17608696fe779e708d0d5091.tex b/sail_latex_riscv/valzhex_bits_27_backwards4d49d22a17608696fe779e708d0d5091.tex new file mode 100644 index 00000000..3838c30a --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_27_backwards4d49d22a17608696fe779e708d0d5091.tex @@ -0,0 +1 @@ +hex_bits_27_backwards : string -> bits(27) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_27_backwards_matchesc36973ea671b22434d73ad552c3b36f1.tex b/sail_latex_riscv/valzhex_bits_27_backwards_matchesc36973ea671b22434d73ad552c3b36f1.tex new file mode 100644 index 00000000..b5c03708 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_27_backwards_matchesc36973ea671b22434d73ad552c3b36f1.tex @@ -0,0 +1 @@ +hex_bits_27_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_27_forwards_matches6867770d92d07d048cf22050458e9a6f.tex b/sail_latex_riscv/valzhex_bits_27_forwards_matches6867770d92d07d048cf22050458e9a6f.tex new file mode 100644 index 00000000..352bc674 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_27_forwards_matches6867770d92d07d048cf22050458e9a6f.tex @@ -0,0 +1 @@ +hex_bits_27_forwards_matches : bits(27) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_27_forwardsd1cadb067b94f8db9ac21a09b0a9c465.tex b/sail_latex_riscv/valzhex_bits_27_forwardsd1cadb067b94f8db9ac21a09b0a9c465.tex new file mode 100644 index 00000000..4e8812ea --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_27_forwardsd1cadb067b94f8db9ac21a09b0a9c465.tex @@ -0,0 +1 @@ +hex_bits_27_forwards : bits(27) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_27_matches_prefixdc708eca229898ef6aae7c4b60f3b806.tex b/sail_latex_riscv/valzhex_bits_27_matches_prefixdc708eca229898ef6aae7c4b60f3b806.tex new file mode 100644 index 00000000..80830f19 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_27_matches_prefixdc708eca229898ef6aae7c4b60f3b806.tex @@ -0,0 +1 @@ +hex_bits_27_matches_prefix : string -> option((bits(27), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_27b316c424414b7868c1946d3aa5df4022.tex b/sail_latex_riscv/valzhex_bits_27b316c424414b7868c1946d3aa5df4022.tex new file mode 100644 index 00000000..090bc48c --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_27b316c424414b7868c1946d3aa5df4022.tex @@ -0,0 +1 @@ +hex_bits_27 : bits(27) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_288d4243d5b924b9df9b04ff6f5779762e.tex b/sail_latex_riscv/valzhex_bits_288d4243d5b924b9df9b04ff6f5779762e.tex new file mode 100644 index 00000000..6af0ba86 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_288d4243d5b924b9df9b04ff6f5779762e.tex @@ -0,0 +1 @@ +hex_bits_28 : bits(28) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_28_backwards2c2d2daf166e3a6a7935d895391a113e.tex b/sail_latex_riscv/valzhex_bits_28_backwards2c2d2daf166e3a6a7935d895391a113e.tex new file mode 100644 index 00000000..2b41adb5 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_28_backwards2c2d2daf166e3a6a7935d895391a113e.tex @@ -0,0 +1 @@ +hex_bits_28_backwards : string -> bits(28) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_28_backwards_matches0baec25715c212015f55f72f54702da4.tex b/sail_latex_riscv/valzhex_bits_28_backwards_matches0baec25715c212015f55f72f54702da4.tex new file mode 100644 index 00000000..2724506d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_28_backwards_matches0baec25715c212015f55f72f54702da4.tex @@ -0,0 +1 @@ +hex_bits_28_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_28_forwards1cd2299af6ec5f9078eb9063e9f85a94.tex b/sail_latex_riscv/valzhex_bits_28_forwards1cd2299af6ec5f9078eb9063e9f85a94.tex new file mode 100644 index 00000000..43ea647e --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_28_forwards1cd2299af6ec5f9078eb9063e9f85a94.tex @@ -0,0 +1 @@ +hex_bits_28_forwards : bits(28) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_28_forwards_matchesc4d71e8f4caf976479bf0fd50de2a1f7.tex b/sail_latex_riscv/valzhex_bits_28_forwards_matchesc4d71e8f4caf976479bf0fd50de2a1f7.tex new file mode 100644 index 00000000..918ed14e --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_28_forwards_matchesc4d71e8f4caf976479bf0fd50de2a1f7.tex @@ -0,0 +1 @@ +hex_bits_28_forwards_matches : bits(28) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_28_matches_prefix70f347867a8aba96b2c10f78f8f7a372.tex b/sail_latex_riscv/valzhex_bits_28_matches_prefix70f347867a8aba96b2c10f78f8f7a372.tex new file mode 100644 index 00000000..285152d8 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_28_matches_prefix70f347867a8aba96b2c10f78f8f7a372.tex @@ -0,0 +1 @@ +hex_bits_28_matches_prefix : string -> option((bits(28), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_29_backwards388cf5f0a97b7aadfda6550d7d52cc35.tex b/sail_latex_riscv/valzhex_bits_29_backwards388cf5f0a97b7aadfda6550d7d52cc35.tex new file mode 100644 index 00000000..c7cfcdbc --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_29_backwards388cf5f0a97b7aadfda6550d7d52cc35.tex @@ -0,0 +1 @@ +hex_bits_29_backwards : string -> bits(29) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_29_backwards_matchese61c62311ca330ee022b0ce689f2bf7a.tex b/sail_latex_riscv/valzhex_bits_29_backwards_matchese61c62311ca330ee022b0ce689f2bf7a.tex new file mode 100644 index 00000000..d427145d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_29_backwards_matchese61c62311ca330ee022b0ce689f2bf7a.tex @@ -0,0 +1 @@ +hex_bits_29_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_29_forwards25570c63210d57bb228476e7b744cbc0.tex b/sail_latex_riscv/valzhex_bits_29_forwards25570c63210d57bb228476e7b744cbc0.tex new file mode 100644 index 00000000..28a14437 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_29_forwards25570c63210d57bb228476e7b744cbc0.tex @@ -0,0 +1 @@ +hex_bits_29_forwards : bits(29) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_29_forwards_matchesed84d3ffca269bb316dc98b23b11184a.tex b/sail_latex_riscv/valzhex_bits_29_forwards_matchesed84d3ffca269bb316dc98b23b11184a.tex new file mode 100644 index 00000000..4d0f6df4 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_29_forwards_matchesed84d3ffca269bb316dc98b23b11184a.tex @@ -0,0 +1 @@ +hex_bits_29_forwards_matches : bits(29) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_29_matches_prefix203fecad348616b1e04e6c54168376e2.tex b/sail_latex_riscv/valzhex_bits_29_matches_prefix203fecad348616b1e04e6c54168376e2.tex new file mode 100644 index 00000000..d323ef55 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_29_matches_prefix203fecad348616b1e04e6c54168376e2.tex @@ -0,0 +1 @@ +hex_bits_29_matches_prefix : string -> option((bits(29), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_29efa82370fcd77919b51fb03d70b237d5.tex b/sail_latex_riscv/valzhex_bits_29efa82370fcd77919b51fb03d70b237d5.tex new file mode 100644 index 00000000..9f5c824a --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_29efa82370fcd77919b51fb03d70b237d5.tex @@ -0,0 +1 @@ +hex_bits_29 : bits(29) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_2_backwards18d79d6a578203ebce0993a1703a4245.tex b/sail_latex_riscv/valzhex_bits_2_backwards18d79d6a578203ebce0993a1703a4245.tex new file mode 100644 index 00000000..7e3647fb --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_2_backwards18d79d6a578203ebce0993a1703a4245.tex @@ -0,0 +1 @@ +hex_bits_2_backwards : string -> bits(2) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_2_backwards_matches823cb41992ed3a26886d992e75e86734.tex b/sail_latex_riscv/valzhex_bits_2_backwards_matches823cb41992ed3a26886d992e75e86734.tex new file mode 100644 index 00000000..ac5c2e17 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_2_backwards_matches823cb41992ed3a26886d992e75e86734.tex @@ -0,0 +1 @@ +hex_bits_2_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_2_forwards72b197d3d92a10d7d05fb57812f597ab.tex b/sail_latex_riscv/valzhex_bits_2_forwards72b197d3d92a10d7d05fb57812f597ab.tex new file mode 100644 index 00000000..83c3d5bd --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_2_forwards72b197d3d92a10d7d05fb57812f597ab.tex @@ -0,0 +1 @@ +hex_bits_2_forwards : bits(2) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_2_forwards_matches7ab140c97f69659d3ab1d910b07425fb.tex b/sail_latex_riscv/valzhex_bits_2_forwards_matches7ab140c97f69659d3ab1d910b07425fb.tex new file mode 100644 index 00000000..597b13fb --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_2_forwards_matches7ab140c97f69659d3ab1d910b07425fb.tex @@ -0,0 +1 @@ +hex_bits_2_forwards_matches : bits(2) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_2_matches_prefix948a15ea9e341681f6b07cb073ac1114.tex b/sail_latex_riscv/valzhex_bits_2_matches_prefix948a15ea9e341681f6b07cb073ac1114.tex new file mode 100644 index 00000000..ff741698 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_2_matches_prefix948a15ea9e341681f6b07cb073ac1114.tex @@ -0,0 +1 @@ +hex_bits_2_matches_prefix : string -> option((bits(2), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_30_backwards3391751afa83c025b48e297fc4113f6e.tex b/sail_latex_riscv/valzhex_bits_30_backwards3391751afa83c025b48e297fc4113f6e.tex new file mode 100644 index 00000000..e82074fc --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_30_backwards3391751afa83c025b48e297fc4113f6e.tex @@ -0,0 +1 @@ +hex_bits_30_backwards : string -> bits(30) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_30_backwards_matches55c635ce0a1a3c012b3119662b49178c.tex b/sail_latex_riscv/valzhex_bits_30_backwards_matches55c635ce0a1a3c012b3119662b49178c.tex new file mode 100644 index 00000000..fdcb3b1c --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_30_backwards_matches55c635ce0a1a3c012b3119662b49178c.tex @@ -0,0 +1 @@ +hex_bits_30_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_30_forwards_matches3630c22b1e1e03c4f0e0de4c42a765db.tex b/sail_latex_riscv/valzhex_bits_30_forwards_matches3630c22b1e1e03c4f0e0de4c42a765db.tex new file mode 100644 index 00000000..19de3396 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_30_forwards_matches3630c22b1e1e03c4f0e0de4c42a765db.tex @@ -0,0 +1 @@ +hex_bits_30_forwards_matches : bits(30) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_30_forwardscea5ca246547b759f92507a3787c7a96.tex b/sail_latex_riscv/valzhex_bits_30_forwardscea5ca246547b759f92507a3787c7a96.tex new file mode 100644 index 00000000..4557845b --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_30_forwardscea5ca246547b759f92507a3787c7a96.tex @@ -0,0 +1 @@ +hex_bits_30_forwards : bits(30) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_30_matches_prefixbf5a6ef1a55049d8f6c26bfca65564f4.tex b/sail_latex_riscv/valzhex_bits_30_matches_prefixbf5a6ef1a55049d8f6c26bfca65564f4.tex new file mode 100644 index 00000000..7b15a3e2 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_30_matches_prefixbf5a6ef1a55049d8f6c26bfca65564f4.tex @@ -0,0 +1 @@ +hex_bits_30_matches_prefix : string -> option((bits(30), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_30cc6f2a56c4decf190e17ab7b80196c34.tex b/sail_latex_riscv/valzhex_bits_30cc6f2a56c4decf190e17ab7b80196c34.tex new file mode 100644 index 00000000..bcfea38c --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_30cc6f2a56c4decf190e17ab7b80196c34.tex @@ -0,0 +1 @@ +hex_bits_30 : bits(30) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_314eac40254c178573e1a2e3e8c866b4b9.tex b/sail_latex_riscv/valzhex_bits_314eac40254c178573e1a2e3e8c866b4b9.tex new file mode 100644 index 00000000..84735f65 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_314eac40254c178573e1a2e3e8c866b4b9.tex @@ -0,0 +1 @@ +hex_bits_31 : bits(31) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_31_backwards36aadfc7c167e0b19e4147eb55e51cba.tex b/sail_latex_riscv/valzhex_bits_31_backwards36aadfc7c167e0b19e4147eb55e51cba.tex new file mode 100644 index 00000000..2828f8d9 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_31_backwards36aadfc7c167e0b19e4147eb55e51cba.tex @@ -0,0 +1 @@ +hex_bits_31_backwards : string -> bits(31) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_31_backwards_matches68cc0d3844c92f7e0ebe6bcaa48a03ca.tex b/sail_latex_riscv/valzhex_bits_31_backwards_matches68cc0d3844c92f7e0ebe6bcaa48a03ca.tex new file mode 100644 index 00000000..b695a62e --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_31_backwards_matches68cc0d3844c92f7e0ebe6bcaa48a03ca.tex @@ -0,0 +1 @@ +hex_bits_31_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_31_forwards4963ea17f27efca42c2c3b70e3678a1f.tex b/sail_latex_riscv/valzhex_bits_31_forwards4963ea17f27efca42c2c3b70e3678a1f.tex new file mode 100644 index 00000000..8afd0d00 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_31_forwards4963ea17f27efca42c2c3b70e3678a1f.tex @@ -0,0 +1 @@ +hex_bits_31_forwards : bits(31) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_31_forwards_matches830a8b6e6851a2528701adaae04355bf.tex b/sail_latex_riscv/valzhex_bits_31_forwards_matches830a8b6e6851a2528701adaae04355bf.tex new file mode 100644 index 00000000..aa471268 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_31_forwards_matches830a8b6e6851a2528701adaae04355bf.tex @@ -0,0 +1 @@ +hex_bits_31_forwards_matches : bits(31) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_31_matches_prefixb56aff200a836c2c62dd85dd75e2e301.tex b/sail_latex_riscv/valzhex_bits_31_matches_prefixb56aff200a836c2c62dd85dd75e2e301.tex new file mode 100644 index 00000000..24581144 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_31_matches_prefixb56aff200a836c2c62dd85dd75e2e301.tex @@ -0,0 +1 @@ +hex_bits_31_matches_prefix : string -> option((bits(31), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_3297bfc3853730082de31dbfe87d09e9ff.tex b/sail_latex_riscv/valzhex_bits_3297bfc3853730082de31dbfe87d09e9ff.tex new file mode 100644 index 00000000..e07172d5 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_3297bfc3853730082de31dbfe87d09e9ff.tex @@ -0,0 +1 @@ +hex_bits_32 : bits(32) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_32_backwards_matchesc5862ab9ce54a89fb3d05c1a1e742ba8.tex b/sail_latex_riscv/valzhex_bits_32_backwards_matchesc5862ab9ce54a89fb3d05c1a1e742ba8.tex new file mode 100644 index 00000000..9862fcef --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_32_backwards_matchesc5862ab9ce54a89fb3d05c1a1e742ba8.tex @@ -0,0 +1 @@ +hex_bits_32_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_32_backwardse98f8968c64c820f7d6ab0adad242eea.tex b/sail_latex_riscv/valzhex_bits_32_backwardse98f8968c64c820f7d6ab0adad242eea.tex new file mode 100644 index 00000000..93872eaa --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_32_backwardse98f8968c64c820f7d6ab0adad242eea.tex @@ -0,0 +1 @@ +hex_bits_32_backwards : string -> bits(32) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_32_forwards0b8436c3566927b7a7b6bca8d7dd5251.tex b/sail_latex_riscv/valzhex_bits_32_forwards0b8436c3566927b7a7b6bca8d7dd5251.tex new file mode 100644 index 00000000..5ccc9539 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_32_forwards0b8436c3566927b7a7b6bca8d7dd5251.tex @@ -0,0 +1 @@ +hex_bits_32_forwards : bits(32) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_32_forwards_matches6b2dec12f42cfb341d5a812b57201577.tex b/sail_latex_riscv/valzhex_bits_32_forwards_matches6b2dec12f42cfb341d5a812b57201577.tex new file mode 100644 index 00000000..41b17b9e --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_32_forwards_matches6b2dec12f42cfb341d5a812b57201577.tex @@ -0,0 +1 @@ +hex_bits_32_forwards_matches : bits(32) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_32_matches_prefix164ead7d22300ab7799ffb9205a2b7a2.tex b/sail_latex_riscv/valzhex_bits_32_matches_prefix164ead7d22300ab7799ffb9205a2b7a2.tex new file mode 100644 index 00000000..fd5e5c7d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_32_matches_prefix164ead7d22300ab7799ffb9205a2b7a2.tex @@ -0,0 +1 @@ +hex_bits_32_matches_prefix : string -> option((bits(32), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_33_backwards_matchesa0efa80a7912e2204c7a08b11236c3ea.tex b/sail_latex_riscv/valzhex_bits_33_backwards_matchesa0efa80a7912e2204c7a08b11236c3ea.tex new file mode 100644 index 00000000..7a920ae2 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_33_backwards_matchesa0efa80a7912e2204c7a08b11236c3ea.tex @@ -0,0 +1 @@ +hex_bits_33_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_33_backwardscc814f008a05b1129f62004b8fa5c8e5.tex b/sail_latex_riscv/valzhex_bits_33_backwardscc814f008a05b1129f62004b8fa5c8e5.tex new file mode 100644 index 00000000..6009aecd --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_33_backwardscc814f008a05b1129f62004b8fa5c8e5.tex @@ -0,0 +1 @@ +hex_bits_33_backwards : string -> bits(33) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_33_forwards30b0334f0b6652dcc7d0b51e3609d45f.tex b/sail_latex_riscv/valzhex_bits_33_forwards30b0334f0b6652dcc7d0b51e3609d45f.tex new file mode 100644 index 00000000..77da0be5 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_33_forwards30b0334f0b6652dcc7d0b51e3609d45f.tex @@ -0,0 +1 @@ +hex_bits_33_forwards : bits(33) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_33_forwards_matches4b4b2c7ba9f6a4dd54548314428e59f6.tex b/sail_latex_riscv/valzhex_bits_33_forwards_matches4b4b2c7ba9f6a4dd54548314428e59f6.tex new file mode 100644 index 00000000..1903c88d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_33_forwards_matches4b4b2c7ba9f6a4dd54548314428e59f6.tex @@ -0,0 +1 @@ +hex_bits_33_forwards_matches : bits(33) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_33_matches_prefixfe32236f637b1e2c06fb0442b85daff6.tex b/sail_latex_riscv/valzhex_bits_33_matches_prefixfe32236f637b1e2c06fb0442b85daff6.tex new file mode 100644 index 00000000..2aacd61d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_33_matches_prefixfe32236f637b1e2c06fb0442b85daff6.tex @@ -0,0 +1 @@ +hex_bits_33_matches_prefix : string -> option((bits(33), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_33bf5a1dfcb81a2b69ce2e63f2b8ac8ba4.tex b/sail_latex_riscv/valzhex_bits_33bf5a1dfcb81a2b69ce2e63f2b8ac8ba4.tex new file mode 100644 index 00000000..4d82f6cd --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_33bf5a1dfcb81a2b69ce2e63f2b8ac8ba4.tex @@ -0,0 +1 @@ +hex_bits_33 : bits(33) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_3_backwards_matches952f17dffac18d98619e00bc97a700fc.tex b/sail_latex_riscv/valzhex_bits_3_backwards_matches952f17dffac18d98619e00bc97a700fc.tex new file mode 100644 index 00000000..7c2a6a77 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_3_backwards_matches952f17dffac18d98619e00bc97a700fc.tex @@ -0,0 +1 @@ +hex_bits_3_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_3_backwardsf853f7ad9bfed642772b10dafd6910d1.tex b/sail_latex_riscv/valzhex_bits_3_backwardsf853f7ad9bfed642772b10dafd6910d1.tex new file mode 100644 index 00000000..41742ca8 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_3_backwardsf853f7ad9bfed642772b10dafd6910d1.tex @@ -0,0 +1 @@ +hex_bits_3_backwards : string -> bits(3) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_3_forwards7bd80f2805155aa4c3a7525bb0bfd448.tex b/sail_latex_riscv/valzhex_bits_3_forwards7bd80f2805155aa4c3a7525bb0bfd448.tex new file mode 100644 index 00000000..ecf71778 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_3_forwards7bd80f2805155aa4c3a7525bb0bfd448.tex @@ -0,0 +1 @@ +hex_bits_3_forwards : bits(3) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_3_forwards_matchese79d3588a48711c3aab539462e1e83ad.tex b/sail_latex_riscv/valzhex_bits_3_forwards_matchese79d3588a48711c3aab539462e1e83ad.tex new file mode 100644 index 00000000..a3ca4d7c --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_3_forwards_matchese79d3588a48711c3aab539462e1e83ad.tex @@ -0,0 +1 @@ +hex_bits_3_forwards_matches : bits(3) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_3_matches_prefix0b670e4346265cc88b71be93bef14dae.tex b/sail_latex_riscv/valzhex_bits_3_matches_prefix0b670e4346265cc88b71be93bef14dae.tex new file mode 100644 index 00000000..811b2966 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_3_matches_prefix0b670e4346265cc88b71be93bef14dae.tex @@ -0,0 +1 @@ +hex_bits_3_matches_prefix : string -> option((bits(3), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_3aeb691402af5232353b21f4b29231f77.tex b/sail_latex_riscv/valzhex_bits_3aeb691402af5232353b21f4b29231f77.tex new file mode 100644 index 00000000..c2a958bf --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_3aeb691402af5232353b21f4b29231f77.tex @@ -0,0 +1 @@ +hex_bits_3 : bits(3) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_48_backwards57285976d132280592935deb245ad737.tex b/sail_latex_riscv/valzhex_bits_48_backwards57285976d132280592935deb245ad737.tex new file mode 100644 index 00000000..3129fc1f --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_48_backwards57285976d132280592935deb245ad737.tex @@ -0,0 +1 @@ +hex_bits_48_backwards : string -> bits(48) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_48_backwards_matches3765c7a672ed4a4188e6adcad2e1769c.tex b/sail_latex_riscv/valzhex_bits_48_backwards_matches3765c7a672ed4a4188e6adcad2e1769c.tex new file mode 100644 index 00000000..3718b0ab --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_48_backwards_matches3765c7a672ed4a4188e6adcad2e1769c.tex @@ -0,0 +1 @@ +hex_bits_48_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_48_forwards00cd6bb42ad747a155b252e7b9981df1.tex b/sail_latex_riscv/valzhex_bits_48_forwards00cd6bb42ad747a155b252e7b9981df1.tex new file mode 100644 index 00000000..7479eba3 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_48_forwards00cd6bb42ad747a155b252e7b9981df1.tex @@ -0,0 +1 @@ +hex_bits_48_forwards : bits(48) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_48_forwards_matchesf2b53432d5d61a0c6dbc5e249b95d790.tex b/sail_latex_riscv/valzhex_bits_48_forwards_matchesf2b53432d5d61a0c6dbc5e249b95d790.tex new file mode 100644 index 00000000..f69cf80c --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_48_forwards_matchesf2b53432d5d61a0c6dbc5e249b95d790.tex @@ -0,0 +1 @@ +hex_bits_48_forwards_matches : bits(48) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_48_matches_prefixcaea63593a204f4e52c03e2824ea453e.tex b/sail_latex_riscv/valzhex_bits_48_matches_prefixcaea63593a204f4e52c03e2824ea453e.tex new file mode 100644 index 00000000..91709199 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_48_matches_prefixcaea63593a204f4e52c03e2824ea453e.tex @@ -0,0 +1 @@ +hex_bits_48_matches_prefix : string -> option((bits(48), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_48bcd68487a0855653b3f1bd0b77874f47.tex b/sail_latex_riscv/valzhex_bits_48bcd68487a0855653b3f1bd0b77874f47.tex new file mode 100644 index 00000000..4dff6621 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_48bcd68487a0855653b3f1bd0b77874f47.tex @@ -0,0 +1 @@ +hex_bits_48 : bits(48) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_4_backwards_matches798cb282812c7bc9b083a091bb0b23ca.tex b/sail_latex_riscv/valzhex_bits_4_backwards_matches798cb282812c7bc9b083a091bb0b23ca.tex new file mode 100644 index 00000000..f415c471 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_4_backwards_matches798cb282812c7bc9b083a091bb0b23ca.tex @@ -0,0 +1 @@ +hex_bits_4_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_4_backwardsf22b435ac96c309eec82519c5c010323.tex b/sail_latex_riscv/valzhex_bits_4_backwardsf22b435ac96c309eec82519c5c010323.tex new file mode 100644 index 00000000..a14ed61f --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_4_backwardsf22b435ac96c309eec82519c5c010323.tex @@ -0,0 +1 @@ +hex_bits_4_backwards : string -> bits(4) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_4_forwards17651a29b8d01053a94a764e92e93964.tex b/sail_latex_riscv/valzhex_bits_4_forwards17651a29b8d01053a94a764e92e93964.tex new file mode 100644 index 00000000..018bd186 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_4_forwards17651a29b8d01053a94a764e92e93964.tex @@ -0,0 +1 @@ +hex_bits_4_forwards : bits(4) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_4_forwards_matchesc9b2af172c13a489fa870acdd673758a.tex b/sail_latex_riscv/valzhex_bits_4_forwards_matchesc9b2af172c13a489fa870acdd673758a.tex new file mode 100644 index 00000000..b868310f --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_4_forwards_matchesc9b2af172c13a489fa870acdd673758a.tex @@ -0,0 +1 @@ +hex_bits_4_forwards_matches : bits(4) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_4_matches_prefix7449c0ebcb161f55de6260595c0db150.tex b/sail_latex_riscv/valzhex_bits_4_matches_prefix7449c0ebcb161f55de6260595c0db150.tex new file mode 100644 index 00000000..a724fb41 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_4_matches_prefix7449c0ebcb161f55de6260595c0db150.tex @@ -0,0 +1 @@ +hex_bits_4_matches_prefix : string -> option((bits(4), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_4cc2b0d5d62eeaf81d463b3beb7b16ede.tex b/sail_latex_riscv/valzhex_bits_4cc2b0d5d62eeaf81d463b3beb7b16ede.tex new file mode 100644 index 00000000..c46fb71b --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_4cc2b0d5d62eeaf81d463b3beb7b16ede.tex @@ -0,0 +1 @@ +hex_bits_4 : bits(4) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_5_backwards79c47a53cbcc5ca893c439296fe2bd3f.tex b/sail_latex_riscv/valzhex_bits_5_backwards79c47a53cbcc5ca893c439296fe2bd3f.tex new file mode 100644 index 00000000..6df0e718 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_5_backwards79c47a53cbcc5ca893c439296fe2bd3f.tex @@ -0,0 +1 @@ +hex_bits_5_backwards : string -> bits(5) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_5_backwards_matchesf675096dc18dd61104842d90f51800a8.tex b/sail_latex_riscv/valzhex_bits_5_backwards_matchesf675096dc18dd61104842d90f51800a8.tex new file mode 100644 index 00000000..e179eae0 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_5_backwards_matchesf675096dc18dd61104842d90f51800a8.tex @@ -0,0 +1 @@ +hex_bits_5_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_5_forwards79911e0485d859b00a2fdcba8cff5318.tex b/sail_latex_riscv/valzhex_bits_5_forwards79911e0485d859b00a2fdcba8cff5318.tex new file mode 100644 index 00000000..787b7e7a --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_5_forwards79911e0485d859b00a2fdcba8cff5318.tex @@ -0,0 +1 @@ +hex_bits_5_forwards : bits(5) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_5_forwards_matches3e31f036e77b0ee1a3e8312b0067959b.tex b/sail_latex_riscv/valzhex_bits_5_forwards_matches3e31f036e77b0ee1a3e8312b0067959b.tex new file mode 100644 index 00000000..65816d50 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_5_forwards_matches3e31f036e77b0ee1a3e8312b0067959b.tex @@ -0,0 +1 @@ +hex_bits_5_forwards_matches : bits(5) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_5_matches_prefix998186306b8236e178fc5d664bda45c0.tex b/sail_latex_riscv/valzhex_bits_5_matches_prefix998186306b8236e178fc5d664bda45c0.tex new file mode 100644 index 00000000..fc87efcc --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_5_matches_prefix998186306b8236e178fc5d664bda45c0.tex @@ -0,0 +1 @@ +hex_bits_5_matches_prefix : string -> option((bits(5), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_5daa8fabe8bf4a20ba57e93cf91addd75.tex b/sail_latex_riscv/valzhex_bits_5daa8fabe8bf4a20ba57e93cf91addd75.tex new file mode 100644 index 00000000..8407fbd1 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_5daa8fabe8bf4a20ba57e93cf91addd75.tex @@ -0,0 +1 @@ +hex_bits_5 : bits(5) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_61cff7c3b87dd820982f77ae4876bbe56.tex b/sail_latex_riscv/valzhex_bits_61cff7c3b87dd820982f77ae4876bbe56.tex new file mode 100644 index 00000000..6569e4bc --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_61cff7c3b87dd820982f77ae4876bbe56.tex @@ -0,0 +1 @@ +hex_bits_6 : bits(6) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_6481d941ae17c8b68343a58c840ecca1cd.tex b/sail_latex_riscv/valzhex_bits_6481d941ae17c8b68343a58c840ecca1cd.tex new file mode 100644 index 00000000..d26b21c1 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_6481d941ae17c8b68343a58c840ecca1cd.tex @@ -0,0 +1 @@ +hex_bits_64 : bits(64) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_64_backwards_matches2ac7f320ee670e1403b866f7b48f9b95.tex b/sail_latex_riscv/valzhex_bits_64_backwards_matches2ac7f320ee670e1403b866f7b48f9b95.tex new file mode 100644 index 00000000..3d0b41b0 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_64_backwards_matches2ac7f320ee670e1403b866f7b48f9b95.tex @@ -0,0 +1 @@ +hex_bits_64_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_64_backwardsef9778c97dfbfdc25f03d089d5788d24.tex b/sail_latex_riscv/valzhex_bits_64_backwardsef9778c97dfbfdc25f03d089d5788d24.tex new file mode 100644 index 00000000..f3b016f4 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_64_backwardsef9778c97dfbfdc25f03d089d5788d24.tex @@ -0,0 +1 @@ +hex_bits_64_backwards : string -> bits(64) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_64_forwards7510d79394d351421610c028bea6e7a5.tex b/sail_latex_riscv/valzhex_bits_64_forwards7510d79394d351421610c028bea6e7a5.tex new file mode 100644 index 00000000..5482192d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_64_forwards7510d79394d351421610c028bea6e7a5.tex @@ -0,0 +1 @@ +hex_bits_64_forwards : bits(64) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_64_forwards_matches9b4aa7858f48288bd5ee715f31bb0cdb.tex b/sail_latex_riscv/valzhex_bits_64_forwards_matches9b4aa7858f48288bd5ee715f31bb0cdb.tex new file mode 100644 index 00000000..6691af0c --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_64_forwards_matches9b4aa7858f48288bd5ee715f31bb0cdb.tex @@ -0,0 +1 @@ +hex_bits_64_forwards_matches : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_64_matches_prefix72a39a7f0e633af539b7e5e9e8e13575.tex b/sail_latex_riscv/valzhex_bits_64_matches_prefix72a39a7f0e633af539b7e5e9e8e13575.tex new file mode 100644 index 00000000..61415f25 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_64_matches_prefix72a39a7f0e633af539b7e5e9e8e13575.tex @@ -0,0 +1 @@ +hex_bits_64_matches_prefix : string -> option((bits(64), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_6_backwards_matches4f038823a669140ed233992d9e5ddb69.tex b/sail_latex_riscv/valzhex_bits_6_backwards_matches4f038823a669140ed233992d9e5ddb69.tex new file mode 100644 index 00000000..a0097e31 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_6_backwards_matches4f038823a669140ed233992d9e5ddb69.tex @@ -0,0 +1 @@ +hex_bits_6_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_6_backwardsabaf13af56590b164adcda6b4fd1b52f.tex b/sail_latex_riscv/valzhex_bits_6_backwardsabaf13af56590b164adcda6b4fd1b52f.tex new file mode 100644 index 00000000..5fe0d2e7 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_6_backwardsabaf13af56590b164adcda6b4fd1b52f.tex @@ -0,0 +1 @@ +hex_bits_6_backwards : string -> bits(6) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_6_forwards3455f13508c617afbe64b39dede36554.tex b/sail_latex_riscv/valzhex_bits_6_forwards3455f13508c617afbe64b39dede36554.tex new file mode 100644 index 00000000..60ab2be7 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_6_forwards3455f13508c617afbe64b39dede36554.tex @@ -0,0 +1 @@ +hex_bits_6_forwards : bits(6) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_6_forwards_matchescaeea7989719fec9093c81797a7f4155.tex b/sail_latex_riscv/valzhex_bits_6_forwards_matchescaeea7989719fec9093c81797a7f4155.tex new file mode 100644 index 00000000..4357d3c5 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_6_forwards_matchescaeea7989719fec9093c81797a7f4155.tex @@ -0,0 +1 @@ +hex_bits_6_forwards_matches : bits(6) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_6_matches_prefixb8878485899ba2293890312e921ac156.tex b/sail_latex_riscv/valzhex_bits_6_matches_prefixb8878485899ba2293890312e921ac156.tex new file mode 100644 index 00000000..72bad777 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_6_matches_prefixb8878485899ba2293890312e921ac156.tex @@ -0,0 +1 @@ +hex_bits_6_matches_prefix : string -> option((bits(6), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_7_backwards33c217f9145eec45b693f09bca0d89ea.tex b/sail_latex_riscv/valzhex_bits_7_backwards33c217f9145eec45b693f09bca0d89ea.tex new file mode 100644 index 00000000..738a58c6 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_7_backwards33c217f9145eec45b693f09bca0d89ea.tex @@ -0,0 +1 @@ +hex_bits_7_backwards : string -> bits(7) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_7_backwards_matchescc985ebeb5f5adedc7e184499a8978db.tex b/sail_latex_riscv/valzhex_bits_7_backwards_matchescc985ebeb5f5adedc7e184499a8978db.tex new file mode 100644 index 00000000..9ace070b --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_7_backwards_matchescc985ebeb5f5adedc7e184499a8978db.tex @@ -0,0 +1 @@ +hex_bits_7_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_7_forwards9bd105e290f5b2e7d8bb2e10f49c067b.tex b/sail_latex_riscv/valzhex_bits_7_forwards9bd105e290f5b2e7d8bb2e10f49c067b.tex new file mode 100644 index 00000000..c30172c5 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_7_forwards9bd105e290f5b2e7d8bb2e10f49c067b.tex @@ -0,0 +1 @@ +hex_bits_7_forwards : bits(7) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_7_forwards_matches9d7aa1993e9d141c0950fe9e67734abc.tex b/sail_latex_riscv/valzhex_bits_7_forwards_matches9d7aa1993e9d141c0950fe9e67734abc.tex new file mode 100644 index 00000000..33913f1d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_7_forwards_matches9d7aa1993e9d141c0950fe9e67734abc.tex @@ -0,0 +1 @@ +hex_bits_7_forwards_matches : bits(7) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_7_matches_prefixfe0ccd9dca07ce0b4f7d3176ad3fc10c.tex b/sail_latex_riscv/valzhex_bits_7_matches_prefixfe0ccd9dca07ce0b4f7d3176ad3fc10c.tex new file mode 100644 index 00000000..fc494d25 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_7_matches_prefixfe0ccd9dca07ce0b4f7d3176ad3fc10c.tex @@ -0,0 +1 @@ +hex_bits_7_matches_prefix : string -> option((bits(7), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_7b8d1ab69e279cfbd7a9d7c59b1171b24.tex b/sail_latex_riscv/valzhex_bits_7b8d1ab69e279cfbd7a9d7c59b1171b24.tex new file mode 100644 index 00000000..078200ac --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_7b8d1ab69e279cfbd7a9d7c59b1171b24.tex @@ -0,0 +1 @@ +hex_bits_7 : bits(7) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_8_backwards8502ba5c5fdfe5404c185ff925d26a02.tex b/sail_latex_riscv/valzhex_bits_8_backwards8502ba5c5fdfe5404c185ff925d26a02.tex new file mode 100644 index 00000000..0a852425 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_8_backwards8502ba5c5fdfe5404c185ff925d26a02.tex @@ -0,0 +1 @@ +hex_bits_8_backwards : string -> bits(8) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_8_backwards_matchesa183109b599ae5e880adc653bde047ba.tex b/sail_latex_riscv/valzhex_bits_8_backwards_matchesa183109b599ae5e880adc653bde047ba.tex new file mode 100644 index 00000000..0d866948 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_8_backwards_matchesa183109b599ae5e880adc653bde047ba.tex @@ -0,0 +1 @@ +hex_bits_8_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_8_forwards168d310ff118fd3c7d7bc80f8de29d67.tex b/sail_latex_riscv/valzhex_bits_8_forwards168d310ff118fd3c7d7bc80f8de29d67.tex new file mode 100644 index 00000000..53f1991d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_8_forwards168d310ff118fd3c7d7bc80f8de29d67.tex @@ -0,0 +1 @@ +hex_bits_8_forwards : bits(8) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_8_forwards_matches0746becf5ca996196bfae6048bab9bb1.tex b/sail_latex_riscv/valzhex_bits_8_forwards_matches0746becf5ca996196bfae6048bab9bb1.tex new file mode 100644 index 00000000..df73ead5 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_8_forwards_matches0746becf5ca996196bfae6048bab9bb1.tex @@ -0,0 +1 @@ +hex_bits_8_forwards_matches : bits(8) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_8_matches_prefixf713d7df51d74309ab21b6aa029dbeed.tex b/sail_latex_riscv/valzhex_bits_8_matches_prefixf713d7df51d74309ab21b6aa029dbeed.tex new file mode 100644 index 00000000..b88848ba --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_8_matches_prefixf713d7df51d74309ab21b6aa029dbeed.tex @@ -0,0 +1 @@ +hex_bits_8_matches_prefix : string -> option((bits(8), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_8e02cd45b50bbc73ca04e08e3df697f5d.tex b/sail_latex_riscv/valzhex_bits_8e02cd45b50bbc73ca04e08e3df697f5d.tex new file mode 100644 index 00000000..65723cde --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_8e02cd45b50bbc73ca04e08e3df697f5d.tex @@ -0,0 +1 @@ +hex_bits_8 : bits(8) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_9_backwards90cddf73654805833800c2414c31ab0f.tex b/sail_latex_riscv/valzhex_bits_9_backwards90cddf73654805833800c2414c31ab0f.tex new file mode 100644 index 00000000..9713a395 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_9_backwards90cddf73654805833800c2414c31ab0f.tex @@ -0,0 +1 @@ +hex_bits_9_backwards : string -> bits(9) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_9_backwards_matches34e146fa5f101fa17110f57d272dec69.tex b/sail_latex_riscv/valzhex_bits_9_backwards_matches34e146fa5f101fa17110f57d272dec69.tex new file mode 100644 index 00000000..390f01a7 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_9_backwards_matches34e146fa5f101fa17110f57d272dec69.tex @@ -0,0 +1 @@ +hex_bits_9_backwards_matches : string -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_9_forwards5bc4abb19984f8188c037a8554a3ce15.tex b/sail_latex_riscv/valzhex_bits_9_forwards5bc4abb19984f8188c037a8554a3ce15.tex new file mode 100644 index 00000000..d5729de2 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_9_forwards5bc4abb19984f8188c037a8554a3ce15.tex @@ -0,0 +1 @@ +hex_bits_9_forwards : bits(9) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_9_forwards_matches73ffbf54790f1b1c63b0dc63773cd0c0.tex b/sail_latex_riscv/valzhex_bits_9_forwards_matches73ffbf54790f1b1c63b0dc63773cd0c0.tex new file mode 100644 index 00000000..caa033fa --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_9_forwards_matches73ffbf54790f1b1c63b0dc63773cd0c0.tex @@ -0,0 +1 @@ +hex_bits_9_forwards_matches : bits(9) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_9_matches_prefix693d173094578fcf50e2fb151d0c156e.tex b/sail_latex_riscv/valzhex_bits_9_matches_prefix693d173094578fcf50e2fb151d0c156e.tex new file mode 100644 index 00000000..7903fa08 --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_9_matches_prefix693d173094578fcf50e2fb151d0c156e.tex @@ -0,0 +1 @@ +hex_bits_9_matches_prefix : string -> option((bits(9), nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_bits_9eeceb6bd9aab72270435e4d9e8c5dc4c.tex b/sail_latex_riscv/valzhex_bits_9eeceb6bd9aab72270435e4d9e8c5dc4c.tex new file mode 100644 index 00000000..b3f9022d --- /dev/null +++ b/sail_latex_riscv/valzhex_bits_9eeceb6bd9aab72270435e4d9e8c5dc4c.tex @@ -0,0 +1 @@ +hex_bits_9 : bits(9) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhex_str47c735e2941ef5c87d4f7502a5e92a2a.tex b/sail_latex_riscv/valzhex_str47c735e2941ef5c87d4f7502a5e92a2a.tex new file mode 100644 index 00000000..cb910794 --- /dev/null +++ b/sail_latex_riscv/valzhex_str47c735e2941ef5c87d4f7502a5e92a2a.tex @@ -0,0 +1 @@ +hex_str : int -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzhtif_load7bc11b4853a5dae019f61722a0a6d6d7.tex b/sail_latex_riscv/valzhtif_load7bc11b4853a5dae019f61722a0a6d6d7.tex new file mode 100644 index 00000000..1e5abcea --- /dev/null +++ b/sail_latex_riscv/valzhtif_load7bc11b4853a5dae019f61722a0a6d6d7.tex @@ -0,0 +1 @@ +htif_load : forall ('n : Int), 'n > 0. (AccessType(ext_access_type), xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n)) \ No newline at end of file diff --git a/sail_latex_riscv/valzhtif_storeab9d062182e5f884583204ccd435221d.tex b/sail_latex_riscv/valzhtif_storeab9d062182e5f884583204ccd435221d.tex new file mode 100644 index 00000000..ad169dbe --- /dev/null +++ b/sail_latex_riscv/valzhtif_storeab9d062182e5f884583204ccd435221d.tex @@ -0,0 +1 @@ +htif_store : forall ('n : Int), (0 < 'n & 'n <= 8). (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzhtif_tick227711b74637bcd9c79730b4942f90fb.tex b/sail_latex_riscv/valzhtif_tick227711b74637bcd9c79730b4942f90fb.tex new file mode 100644 index 00000000..d6797674 --- /dev/null +++ b/sail_latex_riscv/valzhtif_tick227711b74637bcd9c79730b4942f90fb.tex @@ -0,0 +1 @@ +htif_tick : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzin32bitmode1fa9d4b065e1807e1dff8fc7b86cca8d.tex b/sail_latex_riscv/valzin32bitmode1fa9d4b065e1807e1dff8fc7b86cca8d.tex new file mode 100644 index 00000000..82f58100 --- /dev/null +++ b/sail_latex_riscv/valzin32bitmode1fa9d4b065e1807e1dff8fc7b86cca8d.tex @@ -0,0 +1 @@ +in32BitMode : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzincapboundsc6e70952d3c6507cf32d75b499b90335.tex b/sail_latex_riscv/valzincapboundsc6e70952d3c6507cf32d75b499b90335.tex new file mode 100644 index 00000000..4bf57f0e --- /dev/null +++ b/sail_latex_riscv/valzincapboundsc6e70952d3c6507cf32d75b499b90335.tex @@ -0,0 +1 @@ +inCapBounds : (Capability, CapAddrBits, CapLen) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzinccapoffsetc4735d243650e78b90bacb6efb419260.tex b/sail_latex_riscv/valzinccapoffsetc4735d243650e78b90bacb6efb419260.tex new file mode 100644 index 00000000..f235db0f --- /dev/null +++ b/sail_latex_riscv/valzinccapoffsetc4735d243650e78b90bacb6efb419260.tex @@ -0,0 +1 @@ +incCapOffset : (Capability, CapAddrBits) -> (bool, Capability) \ No newline at end of file diff --git a/sail_latex_riscv/valzinit_base_regs92fa12c31a7794db853235a9147b1c7b.tex b/sail_latex_riscv/valzinit_base_regs92fa12c31a7794db853235a9147b1c7b.tex new file mode 100644 index 00000000..18f4f9f0 --- /dev/null +++ b/sail_latex_riscv/valzinit_base_regs92fa12c31a7794db853235a9147b1c7b.tex @@ -0,0 +1 @@ +init_base_regs : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzinit_fdext_regs66a16bff324f831ac63cd022934bcc14.tex b/sail_latex_riscv/valzinit_fdext_regs66a16bff324f831ac63cd022934bcc14.tex new file mode 100644 index 00000000..f9457456 --- /dev/null +++ b/sail_latex_riscv/valzinit_fdext_regs66a16bff324f831ac63cd022934bcc14.tex @@ -0,0 +1 @@ +init_fdext_regs : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzinit_model2343c87c630c8dc589bf21c69bd047d3.tex b/sail_latex_riscv/valzinit_model2343c87c630c8dc589bf21c69bd047d3.tex new file mode 100644 index 00000000..3aea38b3 --- /dev/null +++ b/sail_latex_riscv/valzinit_model2343c87c630c8dc589bf21c69bd047d3.tex @@ -0,0 +1 @@ +init_model : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzinit_platform487cad4292d23a20d6a3d0b81157a250.tex b/sail_latex_riscv/valzinit_platform487cad4292d23a20d6a3d0b81157a250.tex new file mode 100644 index 00000000..0f2fee08 --- /dev/null +++ b/sail_latex_riscv/valzinit_platform487cad4292d23a20d6a3d0b81157a250.tex @@ -0,0 +1 @@ +init_platform : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzinit_pmp10ae24a767d242e86512a2c1a55970ef.tex b/sail_latex_riscv/valzinit_pmp10ae24a767d242e86512a2c1a55970ef.tex new file mode 100644 index 00000000..b5f15009 --- /dev/null +++ b/sail_latex_riscv/valzinit_pmp10ae24a767d242e86512a2c1a55970ef.tex @@ -0,0 +1 @@ +init_pmp : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzinit_sysc92898d1b2b72595dd36bce10e6a67fb.tex b/sail_latex_riscv/valzinit_sysc92898d1b2b72595dd36bce10e6a67fb.tex new file mode 100644 index 00000000..0bf3f229 --- /dev/null +++ b/sail_latex_riscv/valzinit_sysc92898d1b2b72595dd36bce10e6a67fb.tex @@ -0,0 +1 @@ +init_sys : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzinit_vmem811d98ebf1d4d536d0e4070a3b67fe03.tex b/sail_latex_riscv/valzinit_vmem811d98ebf1d4d536d0e4070a3b67fe03.tex new file mode 100644 index 00000000..c7ad548b --- /dev/null +++ b/sail_latex_riscv/valzinit_vmem811d98ebf1d4d536d0e4070a3b67fe03.tex @@ -0,0 +1 @@ +init_vmem : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzinit_vmem_sv390a83d23f548fedfc48c542ac764df587.tex b/sail_latex_riscv/valzinit_vmem_sv390a83d23f548fedfc48c542ac764df587.tex new file mode 100644 index 00000000..a685b62e --- /dev/null +++ b/sail_latex_riscv/valzinit_vmem_sv390a83d23f548fedfc48c542ac764df587.tex @@ -0,0 +1 @@ +init_vmem_sv39 : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzinit_vmem_sv487afaa3d38e7e9ff21a6cbfad52504311.tex b/sail_latex_riscv/valzinit_vmem_sv487afaa3d38e7e9ff21a6cbfad52504311.tex new file mode 100644 index 00000000..96d48ea6 --- /dev/null +++ b/sail_latex_riscv/valzinit_vmem_sv487afaa3d38e7e9ff21a6cbfad52504311.tex @@ -0,0 +1 @@ +init_vmem_sv48 : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzinitial_analysis58ef2bf9252095b4ead796191551d1ec.tex b/sail_latex_riscv/valzinitial_analysis58ef2bf9252095b4ead796191551d1ec.tex new file mode 100644 index 00000000..8710a6a5 --- /dev/null +++ b/sail_latex_riscv/valzinitial_analysis58ef2bf9252095b4ead796191551d1ec.tex @@ -0,0 +1 @@ +initial_analysis : ast -> (regfps, regfps, regfps, niafps, diafp, instruction_kind) \ No newline at end of file diff --git a/sail_latex_riscv/valzint_powerb0c5fc1a9fb0852260414607a93aeae6.tex b/sail_latex_riscv/valzint_powerb0c5fc1a9fb0852260414607a93aeae6.tex new file mode 100644 index 00000000..982dc808 --- /dev/null +++ b/sail_latex_riscv/valzint_powerb0c5fc1a9fb0852260414607a93aeae6.tex @@ -0,0 +1 @@ +int_power : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_riscv/valzint_to_capf8526cbe276f6bcb8e84d62c62d4f9a1.tex b/sail_latex_riscv/valzint_to_capf8526cbe276f6bcb8e84d62c62d4f9a1.tex new file mode 100644 index 00000000..d997f410 --- /dev/null +++ b/sail_latex_riscv/valzint_to_capf8526cbe276f6bcb8e84d62c62d4f9a1.tex @@ -0,0 +1 @@ +int_to_cap : CapAddrBits -> Capability \ No newline at end of file diff --git a/sail_latex_riscv/valzinternal_error92c3548c19282819d20d44565303aa89.tex b/sail_latex_riscv/valzinternal_error92c3548c19282819d20d44565303aa89.tex new file mode 100644 index 00000000..1a166d20 --- /dev/null +++ b/sail_latex_riscv/valzinternal_error92c3548c19282819d20d44565303aa89.tex @@ -0,0 +1 @@ +internal_error : forall ('a : Type). string -> 'a \ No newline at end of file diff --git a/sail_latex_riscv/valzinterrupttype_of_numbcca70e199dd805ea962d03dd661ceb8.tex b/sail_latex_riscv/valzinterrupttype_of_numbcca70e199dd805ea962d03dd661ceb8.tex new file mode 100644 index 00000000..8ddb2ca2 --- /dev/null +++ b/sail_latex_riscv/valzinterrupttype_of_numbcca70e199dd805ea962d03dd661ceb8.tex @@ -0,0 +1 @@ +InterruptType_of_num : forall ('e : Int), (0 <= 'e & 'e <= 8). int('e) -> InterruptType \ No newline at end of file diff --git a/sail_latex_riscv/valzinterrupttype_to_bits80d6193c8205e91dcda1e3a5b6126a81.tex b/sail_latex_riscv/valzinterrupttype_to_bits80d6193c8205e91dcda1e3a5b6126a81.tex new file mode 100644 index 00000000..04e0cb38 --- /dev/null +++ b/sail_latex_riscv/valzinterrupttype_to_bits80d6193c8205e91dcda1e3a5b6126a81.tex @@ -0,0 +1 @@ +interruptType_to_bits : InterruptType -> exc_code \ No newline at end of file diff --git a/sail_latex_riscv/valzinvalidatecap831c5555c31b163a19988faa291f9c20.tex b/sail_latex_riscv/valzinvalidatecap831c5555c31b163a19988faa291f9c20.tex new file mode 100644 index 00000000..2cde55a4 --- /dev/null +++ b/sail_latex_riscv/valzinvalidatecap831c5555c31b163a19988faa291f9c20.tex @@ -0,0 +1 @@ +invalidateCap : Capability -> Capability \ No newline at end of file diff --git a/sail_latex_riscv/valziop_of_numd466c8622bc5d10ff829fe51ba16e9a6.tex b/sail_latex_riscv/valziop_of_numd466c8622bc5d10ff829fe51ba16e9a6.tex new file mode 100644 index 00000000..c514b465 --- /dev/null +++ b/sail_latex_riscv/valziop_of_numd466c8622bc5d10ff829fe51ba16e9a6.tex @@ -0,0 +1 @@ +iop_of_num : forall ('e : Int), (0 <= 'e & 'e <= 5). int('e) -> iop \ No newline at end of file diff --git a/sail_latex_riscv/valzis_aligned_addr6fae0ea13237382ac6720d04123fd943.tex b/sail_latex_riscv/valzis_aligned_addr6fae0ea13237382ac6720d04123fd943.tex new file mode 100644 index 00000000..7860c217 --- /dev/null +++ b/sail_latex_riscv/valzis_aligned_addr6fae0ea13237382ac6720d04123fd943.tex @@ -0,0 +1 @@ +is_aligned_addr : forall ('n : Int). (xlenbits, int('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzis_csr_definedcd68bcdc8a87dceb6e3521cc036a67d0.tex b/sail_latex_riscv/valzis_csr_definedcd68bcdc8a87dceb6e3521cc036a67d0.tex new file mode 100644 index 00000000..480bf271 --- /dev/null +++ b/sail_latex_riscv/valzis_csr_definedcd68bcdc8a87dceb6e3521cc036a67d0.tex @@ -0,0 +1 @@ +is_CSR_defined : (csreg, Privilege) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzis_nonebebf4558161c4d567fb50f7df9e82374.tex b/sail_latex_riscv/valzis_nonebebf4558161c4d567fb50f7df9e82374.tex new file mode 100644 index 00000000..a2a9de9d --- /dev/null +++ b/sail_latex_riscv/valzis_nonebebf4558161c4d567fb50f7df9e82374.tex @@ -0,0 +1 @@ +is_none : forall ('a : Type). option('a) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzis_rv32d_or_rv64d3518fa18b37b3eaa9c4945d112044e98.tex b/sail_latex_riscv/valzis_rv32d_or_rv64d3518fa18b37b3eaa9c4945d112044e98.tex new file mode 100644 index 00000000..8e47fad5 --- /dev/null +++ b/sail_latex_riscv/valzis_rv32d_or_rv64d3518fa18b37b3eaa9c4945d112044e98.tex @@ -0,0 +1 @@ +is_RV32D_or_RV64D : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzis_rv32f_or_rv64f0479eeacd8ff6d333014b8d2bd493bf0.tex b/sail_latex_riscv/valzis_rv32f_or_rv64f0479eeacd8ff6d333014b8d2bd493bf0.tex new file mode 100644 index 00000000..fa6db0c5 --- /dev/null +++ b/sail_latex_riscv/valzis_rv32f_or_rv64f0479eeacd8ff6d333014b8d2bd493bf0.tex @@ -0,0 +1 @@ +is_RV32F_or_RV64F : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzis_rv64d2ec4297accd40afbaf8305bfa55a08ef.tex b/sail_latex_riscv/valzis_rv64d2ec4297accd40afbaf8305bfa55a08ef.tex new file mode 100644 index 00000000..c390a0c3 --- /dev/null +++ b/sail_latex_riscv/valzis_rv64d2ec4297accd40afbaf8305bfa55a08ef.tex @@ -0,0 +1 @@ +is_RV64D : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzis_rv64f294d3f4a32a15e369d15c34498a07034.tex b/sail_latex_riscv/valzis_rv64f294d3f4a32a15e369d15c34498a07034.tex new file mode 100644 index 00000000..a18902ab --- /dev/null +++ b/sail_latex_riscv/valzis_rv64f294d3f4a32a15e369d15c34498a07034.tex @@ -0,0 +1 @@ +is_RV64F : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex b/sail_latex_riscv/valzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex new file mode 100644 index 00000000..d2059f34 --- /dev/null +++ b/sail_latex_riscv/valzis_some1c925a3fbbb4ddc7f552b6fd691664ee.tex @@ -0,0 +1 @@ +is_some : forall ('a : Type). option('a) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valziscapsealeda9077bc28a9d2efcd12e42755a4de536.tex b/sail_latex_riscv/valziscapsealeda9077bc28a9d2efcd12e42755a4de536.tex new file mode 100644 index 00000000..5955e00a --- /dev/null +++ b/sail_latex_riscv/valziscapsealeda9077bc28a9d2efcd12e42755a4de536.tex @@ -0,0 +1 @@ +isCapSealed : Capability -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzisinvalidpte046e5b8d20df2f7ed228312986edeed3.tex b/sail_latex_riscv/valzisinvalidpte046e5b8d20df2f7ed228312986edeed3.tex new file mode 100644 index 00000000..57970b37 --- /dev/null +++ b/sail_latex_riscv/valzisinvalidpte046e5b8d20df2f7ed228312986edeed3.tex @@ -0,0 +1 @@ +isInvalidPTE : (pteAttribs, extPte) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzispteptrba43877f6dc42c078f937aa41c879446.tex b/sail_latex_riscv/valzispteptrba43877f6dc42c078f937aa41c879446.tex new file mode 100644 index 00000000..1553cfa2 --- /dev/null +++ b/sail_latex_riscv/valzispteptrba43877f6dc42c078f937aa41c879446.tex @@ -0,0 +1 @@ +isPTEPtr : (pteAttribs, extPte) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzisrvcd64dda5fc24513d78f480d3583dee004.tex b/sail_latex_riscv/valzisrvcd64dda5fc24513d78f480d3583dee004.tex new file mode 100644 index 00000000..0799b049 --- /dev/null +++ b/sail_latex_riscv/valzisrvcd64dda5fc24513d78f480d3583dee004.tex @@ -0,0 +1 @@ +isRVC : half -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzisvalidsv39addr6225e53e2f01610f83ab9bea1f3201bf.tex b/sail_latex_riscv/valzisvalidsv39addr6225e53e2f01610f83ab9bea1f3201bf.tex new file mode 100644 index 00000000..e1b67a28 --- /dev/null +++ b/sail_latex_riscv/valzisvalidsv39addr6225e53e2f01610f83ab9bea1f3201bf.tex @@ -0,0 +1 @@ +isValidSv39Addr : xlenbits -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzisvalidsv48addr5c09db742963fd3c2cd1457f6411e837.tex b/sail_latex_riscv/valzisvalidsv48addr5c09db742963fd3c2cd1457f6411e837.tex new file mode 100644 index 00000000..e9d5d062 --- /dev/null +++ b/sail_latex_riscv/valzisvalidsv48addr5c09db742963fd3c2cd1457f6411e837.tex @@ -0,0 +1 @@ +isValidSv48Addr : xlenbits -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzitype_mnemonicb2266da97e58b5824550ef451a0000db.tex b/sail_latex_riscv/valzitype_mnemonicb2266da97e58b5824550ef451a0000db.tex new file mode 100644 index 00000000..29d7df77 --- /dev/null +++ b/sail_latex_riscv/valzitype_mnemonicb2266da97e58b5824550ef451a0000db.tex @@ -0,0 +1 @@ +itype_mnemonic : iop <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_ccsr8248d36ab83d1808c1e3e0b64d88c1cf.tex b/sail_latex_riscv/valzlegalizze_ccsr8248d36ab83d1808c1e3e0b64d88c1cf.tex new file mode 100644 index 00000000..4e00f567 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_ccsr8248d36ab83d1808c1e3e0b64d88c1cf.tex @@ -0,0 +1 @@ +legalize_ccsr : (ccsr, xlenbits) -> ccsr \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_epccfd09ccf016c22f97fa9a6b5dfba65e84.tex b/sail_latex_riscv/valzlegalizze_epccfd09ccf016c22f97fa9a6b5dfba65e84.tex new file mode 100644 index 00000000..f19b8363 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_epccfd09ccf016c22f97fa9a6b5dfba65e84.tex @@ -0,0 +1 @@ +legalize_epcc : Capability -> Capability \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_mcounteren34ab1d8bf1d636c1c12eb9e0b743229f.tex b/sail_latex_riscv/valzlegalizze_mcounteren34ab1d8bf1d636c1c12eb9e0b743229f.tex new file mode 100644 index 00000000..cee98857 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_mcounteren34ab1d8bf1d636c1c12eb9e0b743229f.tex @@ -0,0 +1 @@ +legalize_mcounteren : (Counteren, xlenbits) -> Counteren \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_mcountinhibit83a4863cf81084082c5c66150150e695.tex b/sail_latex_riscv/valzlegalizze_mcountinhibit83a4863cf81084082c5c66150150e695.tex new file mode 100644 index 00000000..156d8d59 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_mcountinhibit83a4863cf81084082c5c66150150e695.tex @@ -0,0 +1 @@ +legalize_mcountinhibit : (Counterin, xlenbits) -> Counterin \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_medeleg4472d564e1553d1bbac6c6cbaeff95c9.tex b/sail_latex_riscv/valzlegalizze_medeleg4472d564e1553d1bbac6c6cbaeff95c9.tex new file mode 100644 index 00000000..8c4772ac --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_medeleg4472d564e1553d1bbac6c6cbaeff95c9.tex @@ -0,0 +1 @@ +legalize_medeleg : (Medeleg, xlenbits) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_mideleg301fb79c822ffefd5b20e289875da3e4.tex b/sail_latex_riscv/valzlegalizze_mideleg301fb79c822ffefd5b20e289875da3e4.tex new file mode 100644 index 00000000..5bba0dd6 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_mideleg301fb79c822ffefd5b20e289875da3e4.tex @@ -0,0 +1 @@ +legalize_mideleg : (Minterrupts, xlenbits) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_miea3d44a6b9220a2e1cbd134912a2b63af.tex b/sail_latex_riscv/valzlegalizze_miea3d44a6b9220a2e1cbd134912a2b63af.tex new file mode 100644 index 00000000..03d851c1 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_miea3d44a6b9220a2e1cbd134912a2b63af.tex @@ -0,0 +1 @@ +legalize_mie : (Minterrupts, xlenbits) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_mip6b35097c942aa7a4220cfbae774dd473.tex b/sail_latex_riscv/valzlegalizze_mip6b35097c942aa7a4220cfbae774dd473.tex new file mode 100644 index 00000000..7baf7ed9 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_mip6b35097c942aa7a4220cfbae774dd473.tex @@ -0,0 +1 @@ +legalize_mip : (Minterrupts, xlenbits) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_misad494764bfeb5d382d189645941a1bce6.tex b/sail_latex_riscv/valzlegalizze_misad494764bfeb5d382d189645941a1bce6.tex new file mode 100644 index 00000000..8b63f1a0 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_misad494764bfeb5d382d189645941a1bce6.tex @@ -0,0 +1 @@ +legalize_misa : (Misa, xlenbits) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_mstatus99091e0733640797e5a873808232271b.tex b/sail_latex_riscv/valzlegalizze_mstatus99091e0733640797e5a873808232271b.tex new file mode 100644 index 00000000..4916ae89 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_mstatus99091e0733640797e5a873808232271b.tex @@ -0,0 +1 @@ +legalize_mstatus : (Mstatus, xlenbits) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_satp1fbfb541ef401311caafca983cb812d6.tex b/sail_latex_riscv/valzlegalizze_satp1fbfb541ef401311caafca983cb812d6.tex new file mode 100644 index 00000000..7a6bc5a4 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_satp1fbfb541ef401311caafca983cb812d6.tex @@ -0,0 +1 @@ +legalize_satp : (Architecture, xlenbits, xlenbits) -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_satp32b15f7b0d2d9380033f3e1b09fe370a61.tex b/sail_latex_riscv/valzlegalizze_satp32b15f7b0d2d9380033f3e1b09fe370a61.tex new file mode 100644 index 00000000..3b50155c --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_satp32b15f7b0d2d9380033f3e1b09fe370a61.tex @@ -0,0 +1 @@ +legalize_satp32 : (Architecture, bits(32), bits(32)) -> bits(32) \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_satp64c07dfcb94af8010eb535b5f77fbb8614.tex b/sail_latex_riscv/valzlegalizze_satp64c07dfcb94af8010eb535b5f77fbb8614.tex new file mode 100644 index 00000000..246e8dbd --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_satp64c07dfcb94af8010eb535b5f77fbb8614.tex @@ -0,0 +1 @@ +legalize_satp64 : (Architecture, bits(64), bits(64)) -> bits(64) \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_scountereneb4feb895f759dc11e62dedd5be1c232.tex b/sail_latex_riscv/valzlegalizze_scountereneb4feb895f759dc11e62dedd5be1c232.tex new file mode 100644 index 00000000..3d4dbf45 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_scountereneb4feb895f759dc11e62dedd5be1c232.tex @@ -0,0 +1 @@ +legalize_scounteren : (Counteren, xlenbits) -> Counteren \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_sedelegd33e4c93e76af1c9ae6a7795974dbcc3.tex b/sail_latex_riscv/valzlegalizze_sedelegd33e4c93e76af1c9ae6a7795974dbcc3.tex new file mode 100644 index 00000000..03201c78 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_sedelegd33e4c93e76af1c9ae6a7795974dbcc3.tex @@ -0,0 +1 @@ +legalize_sedeleg : (Sedeleg, xlenbits) -> Sedeleg \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_sie49baa5a30e7d5365e2d6c1dc23c7686d.tex b/sail_latex_riscv/valzlegalizze_sie49baa5a30e7d5365e2d6c1dc23c7686d.tex new file mode 100644 index 00000000..9685ce2e --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_sie49baa5a30e7d5365e2d6c1dc23c7686d.tex @@ -0,0 +1 @@ +legalize_sie : (Minterrupts, Minterrupts, xlenbits) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_sip8870e10af087ca0981c61bf7bdfe8175.tex b/sail_latex_riscv/valzlegalizze_sip8870e10af087ca0981c61bf7bdfe8175.tex new file mode 100644 index 00000000..144fbc3c --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_sip8870e10af087ca0981c61bf7bdfe8175.tex @@ -0,0 +1 @@ +legalize_sip : (Minterrupts, Minterrupts, xlenbits) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_sstatus6838bd21db8615a2ed1602fc6dd7f8da.tex b/sail_latex_riscv/valzlegalizze_sstatus6838bd21db8615a2ed1602fc6dd7f8da.tex new file mode 100644 index 00000000..3dfd0a7e --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_sstatus6838bd21db8615a2ed1602fc6dd7f8da.tex @@ -0,0 +1 @@ +legalize_sstatus : (Mstatus, xlenbits) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_tccfd2d2ccb3d791b05f6d62114b5036cb9.tex b/sail_latex_riscv/valzlegalizze_tccfd2d2ccb3d791b05f6d62114b5036cb9.tex new file mode 100644 index 00000000..1d118176 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_tccfd2d2ccb3d791b05f6d62114b5036cb9.tex @@ -0,0 +1 @@ +legalize_tcc : (Capability, Capability) -> Capability \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_tvec4a108f656cfc40d55dcc9e2cd9614e5c.tex b/sail_latex_riscv/valzlegalizze_tvec4a108f656cfc40d55dcc9e2cd9614e5c.tex new file mode 100644 index 00000000..b6f8c76d --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_tvec4a108f656cfc40d55dcc9e2cd9614e5c.tex @@ -0,0 +1 @@ +legalize_tvec : (Mtvec, xlenbits) -> Mtvec \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_uie26bad63954765d654a99bf56da523d30.tex b/sail_latex_riscv/valzlegalizze_uie26bad63954765d654a99bf56da523d30.tex new file mode 100644 index 00000000..f8151d2b --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_uie26bad63954765d654a99bf56da523d30.tex @@ -0,0 +1 @@ +legalize_uie : (Sinterrupts, Sinterrupts, xlenbits) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_uipc8133dbe8104c4fd25f4a3933fa30bbb.tex b/sail_latex_riscv/valzlegalizze_uipc8133dbe8104c4fd25f4a3933fa30bbb.tex new file mode 100644 index 00000000..6b9fbf07 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_uipc8133dbe8104c4fd25f4a3933fa30bbb.tex @@ -0,0 +1 @@ +legalize_uip : (Sinterrupts, Sinterrupts, xlenbits) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_ustatusae91980d0571269b3dd8a4a779cb06c6.tex b/sail_latex_riscv/valzlegalizze_ustatusae91980d0571269b3dd8a4a779cb06c6.tex new file mode 100644 index 00000000..a926e99c --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_ustatusae91980d0571269b3dd8a4a779cb06c6.tex @@ -0,0 +1 @@ +legalize_ustatus : (Mstatus, xlenbits) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valzlegalizze_xepc8416dd9133f6232df0898ca0ae2784c2.tex b/sail_latex_riscv/valzlegalizze_xepc8416dd9133f6232df0898ca0ae2784c2.tex new file mode 100644 index 00000000..4f182516 --- /dev/null +++ b/sail_latex_riscv/valzlegalizze_xepc8416dd9133f6232df0898ca0ae2784c2.tex @@ -0,0 +1 @@ +legalize_xepc : xlenbits -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzlift_sie0866dcb30be948749bf6a401d4f6594e.tex b/sail_latex_riscv/valzlift_sie0866dcb30be948749bf6a401d4f6594e.tex new file mode 100644 index 00000000..706490f9 --- /dev/null +++ b/sail_latex_riscv/valzlift_sie0866dcb30be948749bf6a401d4f6594e.tex @@ -0,0 +1 @@ +lift_sie : (Minterrupts, Minterrupts, Sinterrupts) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlift_sip492375a8cff775f29029156b44dfe1bf.tex b/sail_latex_riscv/valzlift_sip492375a8cff775f29029156b44dfe1bf.tex new file mode 100644 index 00000000..2f76bb3e --- /dev/null +++ b/sail_latex_riscv/valzlift_sip492375a8cff775f29029156b44dfe1bf.tex @@ -0,0 +1 @@ +lift_sip : (Minterrupts, Minterrupts, Sinterrupts) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlift_sstatus8b6865e3f513094f03fd5bfc83d2ed77.tex b/sail_latex_riscv/valzlift_sstatus8b6865e3f513094f03fd5bfc83d2ed77.tex new file mode 100644 index 00000000..b6552f26 --- /dev/null +++ b/sail_latex_riscv/valzlift_sstatus8b6865e3f513094f03fd5bfc83d2ed77.tex @@ -0,0 +1 @@ +lift_sstatus : (Mstatus, Sstatus) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valzlift_uied44a5d7049b27cdb894913f74634a628.tex b/sail_latex_riscv/valzlift_uied44a5d7049b27cdb894913f74634a628.tex new file mode 100644 index 00000000..4c6b14e3 --- /dev/null +++ b/sail_latex_riscv/valzlift_uied44a5d7049b27cdb894913f74634a628.tex @@ -0,0 +1 @@ +lift_uie : (Sinterrupts, Sinterrupts, Uinterrupts) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlift_uipc541c535c8821c63ef55fd81254b1078.tex b/sail_latex_riscv/valzlift_uipc541c535c8821c63ef55fd81254b1078.tex new file mode 100644 index 00000000..c47b06ae --- /dev/null +++ b/sail_latex_riscv/valzlift_uipc541c535c8821c63ef55fd81254b1078.tex @@ -0,0 +1 @@ +lift_uip : (Sinterrupts, Sinterrupts, Uinterrupts) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlift_ustatus9f7d2e2291fdb3a746dca97290479c47.tex b/sail_latex_riscv/valzlift_ustatus9f7d2e2291fdb3a746dca97290479c47.tex new file mode 100644 index 00000000..c370f165 --- /dev/null +++ b/sail_latex_riscv/valzlift_ustatus9f7d2e2291fdb3a746dca97290479c47.tex @@ -0,0 +1 @@ +lift_ustatus : (Sstatus, Ustatus) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valzload_reservationca254f1d85cbf90f1662b9f77f637106.tex b/sail_latex_riscv/valzload_reservationca254f1d85cbf90f1662b9f77f637106.tex new file mode 100644 index 00000000..01163a70 --- /dev/null +++ b/sail_latex_riscv/valzload_reservationca254f1d85cbf90f1662b9f77f637106.tex @@ -0,0 +1 @@ +load_reservation : xlenbits -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzlookup_tlb39701cebd3fa43ee6815ecaa975a199f5b.tex b/sail_latex_riscv/valzlookup_tlb39701cebd3fa43ee6815ecaa975a199f5b.tex new file mode 100644 index 00000000..d4a86957 --- /dev/null +++ b/sail_latex_riscv/valzlookup_tlb39701cebd3fa43ee6815ecaa975a199f5b.tex @@ -0,0 +1 @@ +lookup_TLB39 : (asid64, vaddr39) -> option((nat, TLB39_Entry)) \ No newline at end of file diff --git a/sail_latex_riscv/valzlookup_tlb481be2085cbc29568c5c522b87bd854b70.tex b/sail_latex_riscv/valzlookup_tlb481be2085cbc29568c5c522b87bd854b70.tex new file mode 100644 index 00000000..10977fbd --- /dev/null +++ b/sail_latex_riscv/valzlookup_tlb481be2085cbc29568c5c522b87bd854b70.tex @@ -0,0 +1 @@ +lookup_TLB48 : (asid64, vaddr48) -> option((nat, TLB48_Entry)) \ No newline at end of file diff --git a/sail_latex_riscv/valzloop939222c31aec6e03415219d7c5a4ee7a.tex b/sail_latex_riscv/valzloop939222c31aec6e03415219d7c5a4ee7a.tex new file mode 100644 index 00000000..7810668a --- /dev/null +++ b/sail_latex_riscv/valzloop939222c31aec6e03415219d7c5a4ee7a.tex @@ -0,0 +1 @@ +loop : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzlower_mie31369302ff2457befa23f7f9d54a6b02.tex b/sail_latex_riscv/valzlower_mie31369302ff2457befa23f7f9d54a6b02.tex new file mode 100644 index 00000000..64548795 --- /dev/null +++ b/sail_latex_riscv/valzlower_mie31369302ff2457befa23f7f9d54a6b02.tex @@ -0,0 +1 @@ +lower_mie : (Minterrupts, Minterrupts) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlower_mip782f0e78d1db1ca14e49fae5b84aab3a.tex b/sail_latex_riscv/valzlower_mip782f0e78d1db1ca14e49fae5b84aab3a.tex new file mode 100644 index 00000000..65cbea02 --- /dev/null +++ b/sail_latex_riscv/valzlower_mip782f0e78d1db1ca14e49fae5b84aab3a.tex @@ -0,0 +1 @@ +lower_mip : (Minterrupts, Minterrupts) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlower_mstatuse71dfbedf80129bee76a841456768dd1.tex b/sail_latex_riscv/valzlower_mstatuse71dfbedf80129bee76a841456768dd1.tex new file mode 100644 index 00000000..6c5821c9 --- /dev/null +++ b/sail_latex_riscv/valzlower_mstatuse71dfbedf80129bee76a841456768dd1.tex @@ -0,0 +1 @@ +lower_mstatus : Mstatus -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valzlower_siea6b1bfe3227230c0b4c5a544f98a7636.tex b/sail_latex_riscv/valzlower_siea6b1bfe3227230c0b4c5a544f98a7636.tex new file mode 100644 index 00000000..587616f6 --- /dev/null +++ b/sail_latex_riscv/valzlower_siea6b1bfe3227230c0b4c5a544f98a7636.tex @@ -0,0 +1 @@ +lower_sie : (Sinterrupts, Sinterrupts) -> Uinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlower_sipfb2971a9ef35ea1e2a4c00f905ec894c.tex b/sail_latex_riscv/valzlower_sipfb2971a9ef35ea1e2a4c00f905ec894c.tex new file mode 100644 index 00000000..3ee011a1 --- /dev/null +++ b/sail_latex_riscv/valzlower_sipfb2971a9ef35ea1e2a4c00f905ec894c.tex @@ -0,0 +1 @@ +lower_sip : (Sinterrupts, Sinterrupts) -> Uinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzlower_sstatusee8227db3ac1f80e02871989d3ac7837.tex b/sail_latex_riscv/valzlower_sstatusee8227db3ac1f80e02871989d3ac7837.tex new file mode 100644 index 00000000..bfe5c648 --- /dev/null +++ b/sail_latex_riscv/valzlower_sstatusee8227db3ac1f80e02871989d3ac7837.tex @@ -0,0 +1 @@ +lower_sstatus : Sstatus -> Ustatus \ No newline at end of file diff --git a/sail_latex_riscv/valzlrsc_width_str1a32b7e5b18a83477d13203cd0eca601.tex b/sail_latex_riscv/valzlrsc_width_str1a32b7e5b18a83477d13203cd0eca601.tex new file mode 100644 index 00000000..f6722171 --- /dev/null +++ b/sail_latex_riscv/valzlrsc_width_str1a32b7e5b18a83477d13203cd0eca601.tex @@ -0,0 +1 @@ +lrsc_width_str : word_width -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzlt_int996a8b8c361a31bed6b5509ca6686e1a.tex b/sail_latex_riscv/valzlt_int996a8b8c361a31bed6b5509ca6686e1a.tex new file mode 100644 index 00000000..03401793 --- /dev/null +++ b/sail_latex_riscv/valzlt_int996a8b8c361a31bed6b5509ca6686e1a.tex @@ -0,0 +1 @@ +lt_int : forall ('n 'm : Int). (int('n), int('m)) -> bool('n < 'm) \ No newline at end of file diff --git a/sail_latex_riscv/valzlteq_intc80d1082e443aa434e39355e493ece1e.tex b/sail_latex_riscv/valzlteq_intc80d1082e443aa434e39355e493ece1e.tex new file mode 100644 index 00000000..4e580541 --- /dev/null +++ b/sail_latex_riscv/valzlteq_intc80d1082e443aa434e39355e493ece1e.tex @@ -0,0 +1 @@ +lteq_int : forall ('n 'm : Int). (int('n), int('m)) -> bool('n <= 'm) \ No newline at end of file diff --git a/sail_latex_riscv/valzmake_tlb_entry6b22aedb2f264f70f3e1bd2d5dd6f057.tex b/sail_latex_riscv/valzmake_tlb_entry6b22aedb2f264f70f3e1bd2d5dd6f057.tex new file mode 100644 index 00000000..fe0611d0 --- /dev/null +++ b/sail_latex_riscv/valzmake_tlb_entry6b22aedb2f264f70f3e1bd2d5dd6f057.tex @@ -0,0 +1,2 @@ +make_TLB_Entry : forall ('asidlen 'valen 'palen 'ptelen : Int), 'valen > 0. + (bits('asidlen), bool, bits('valen), bits('palen), bits('ptelen), nat, bits('palen), nat) -> TLB_Entry('asidlen, 'valen, 'palen, 'ptelen) \ No newline at end of file diff --git a/sail_latex_riscv/valzmatch_reservationedafe654d6b1fee1b351613706caf96e.tex b/sail_latex_riscv/valzmatch_reservationedafe654d6b1fee1b351613706caf96e.tex new file mode 100644 index 00000000..b8d972b0 --- /dev/null +++ b/sail_latex_riscv/valzmatch_reservationedafe654d6b1fee1b351613706caf96e.tex @@ -0,0 +1 @@ +match_reservation : xlenbits -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzmatch_tlb_entry15cb314356c461bfc7d1b30f45fecb98.tex b/sail_latex_riscv/valzmatch_tlb_entry15cb314356c461bfc7d1b30f45fecb98.tex new file mode 100644 index 00000000..19398f09 --- /dev/null +++ b/sail_latex_riscv/valzmatch_tlb_entry15cb314356c461bfc7d1b30f45fecb98.tex @@ -0,0 +1,2 @@ +match_TLB_Entry : forall ('asidlen 'valen 'palen 'ptelen : Int). + (TLB_Entry('asidlen, 'valen, 'palen, 'ptelen), bits('asidlen), bits('valen)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex b/sail_latex_riscv/valzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex new file mode 100644 index 00000000..577d6466 --- /dev/null +++ b/sail_latex_riscv/valzmax84a1c708b7c8789c33f72b5bb9ee31e8.tex @@ -0,0 +1 @@ +MAX : forall ('n : Int), 'n >= 0. int('n) -> int(2 ^ 'n - 1) \ No newline at end of file diff --git a/sail_latex_riscv/valzmax_inta8f95a0baf723be8373221a893afa8f3.tex b/sail_latex_riscv/valzmax_inta8f95a0baf723be8373221a893afa8f3.tex new file mode 100644 index 00000000..b5b89895 --- /dev/null +++ b/sail_latex_riscv/valzmax_inta8f95a0baf723be8373221a893afa8f3.tex @@ -0,0 +1 @@ +max_int : forall ('x 'y : Int). (int('x), int('y)) -> {'z, ('x >= 'y & 'z == 'x | 'x < 'y & 'z == 'y). int('z)} \ No newline at end of file diff --git a/sail_latex_riscv/valzmaybe_aq7807a00a0c8e402132f155781a4acc6b.tex b/sail_latex_riscv/valzmaybe_aq7807a00a0c8e402132f155781a4acc6b.tex new file mode 100644 index 00000000..54686779 --- /dev/null +++ b/sail_latex_riscv/valzmaybe_aq7807a00a0c8e402132f155781a4acc6b.tex @@ -0,0 +1 @@ +maybe_aq : bool <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzmaybe_i65644ebcc11e5b25fca853fb9aeea917.tex b/sail_latex_riscv/valzmaybe_i65644ebcc11e5b25fca853fb9aeea917.tex new file mode 100644 index 00000000..adebc646 --- /dev/null +++ b/sail_latex_riscv/valzmaybe_i65644ebcc11e5b25fca853fb9aeea917.tex @@ -0,0 +1 @@ +maybe_i : bool <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzmaybe_not_ud1aa0681e785549479247e44134e0663.tex b/sail_latex_riscv/valzmaybe_not_ud1aa0681e785549479247e44134e0663.tex new file mode 100644 index 00000000..6e3e9f3a --- /dev/null +++ b/sail_latex_riscv/valzmaybe_not_ud1aa0681e785549479247e44134e0663.tex @@ -0,0 +1 @@ +maybe_not_u : bool <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzmaybe_rl471fbde2d5b588b1be3bdbcbad1b5b40.tex b/sail_latex_riscv/valzmaybe_rl471fbde2d5b588b1be3bdbcbad1b5b40.tex new file mode 100644 index 00000000..261c52ba --- /dev/null +++ b/sail_latex_riscv/valzmaybe_rl471fbde2d5b588b1be3bdbcbad1b5b40.tex @@ -0,0 +1 @@ +maybe_rl : bool <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzmaybe_u271e5e54fd4c9b9e611d3ad0e98a3503.tex b/sail_latex_riscv/valzmaybe_u271e5e54fd4c9b9e611d3ad0e98a3503.tex new file mode 100644 index 00000000..67e96d96 --- /dev/null +++ b/sail_latex_riscv/valzmaybe_u271e5e54fd4c9b9e611d3ad0e98a3503.tex @@ -0,0 +1 @@ +maybe_u : bool <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzmem_read_cap518c2935d72d61e3ceee2abb80c9fce5.tex b/sail_latex_riscv/valzmem_read_cap518c2935d72d61e3ceee2abb80c9fce5.tex new file mode 100644 index 00000000..d36a305b --- /dev/null +++ b/sail_latex_riscv/valzmem_read_cap518c2935d72d61e3ceee2abb80c9fce5.tex @@ -0,0 +1 @@ +mem_read_cap : (xlenbits, bool, bool, bool) -> MemoryOpResult(Capability) \ No newline at end of file diff --git a/sail_latex_riscv/valzmem_read_metaa66233a97620233d3f80f4bf1a13c232.tex b/sail_latex_riscv/valzmem_read_metaa66233a97620233d3f80f4bf1a13c232.tex new file mode 100644 index 00000000..c0a4c696 --- /dev/null +++ b/sail_latex_riscv/valzmem_read_metaa66233a97620233d3f80f4bf1a13c232.tex @@ -0,0 +1,2 @@ +mem_read_meta : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (AccessType(ext_access_type), xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta)) \ No newline at end of file diff --git a/sail_latex_riscv/valzmem_readbc59b9b8e622af015b97ceb8dcd5c69e.tex b/sail_latex_riscv/valzmem_readbc59b9b8e622af015b97ceb8dcd5c69e.tex new file mode 100644 index 00000000..d0cab412 --- /dev/null +++ b/sail_latex_riscv/valzmem_readbc59b9b8e622af015b97ceb8dcd5c69e.tex @@ -0,0 +1,2 @@ +mem_read : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (AccessType(ext_access_type), xlenbits, int('n), bool, bool, bool) -> MemoryOpResult(bits(8 * 'n)) \ No newline at end of file diff --git a/sail_latex_riscv/valzmem_write_cap1a1d6143df72b48afdcbdae2e99e77f4.tex b/sail_latex_riscv/valzmem_write_cap1a1d6143df72b48afdcbdae2e99e77f4.tex new file mode 100644 index 00000000..79298bfe --- /dev/null +++ b/sail_latex_riscv/valzmem_write_cap1a1d6143df72b48afdcbdae2e99e77f4.tex @@ -0,0 +1 @@ +mem_write_cap : (xlenbits, Capability, bool, bool, bool) -> MemoryOpResult(bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzmem_write_ea_capaa2cfa0cf86165d13bd79024ad44b71d.tex b/sail_latex_riscv/valzmem_write_ea_capaa2cfa0cf86165d13bd79024ad44b71d.tex new file mode 100644 index 00000000..f46d8668 --- /dev/null +++ b/sail_latex_riscv/valzmem_write_ea_capaa2cfa0cf86165d13bd79024ad44b71d.tex @@ -0,0 +1 @@ +mem_write_ea_cap : (xlenbits, bool, bool, bool) -> MemoryOpResult(unit) \ No newline at end of file diff --git a/sail_latex_riscv/valzmem_write_eaf1486ee81ccf925e874de8977b0270e9.tex b/sail_latex_riscv/valzmem_write_eaf1486ee81ccf925e874de8977b0270e9.tex new file mode 100644 index 00000000..54f628c6 --- /dev/null +++ b/sail_latex_riscv/valzmem_write_eaf1486ee81ccf925e874de8977b0270e9.tex @@ -0,0 +1,2 @@ +mem_write_ea : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (xlenbits, int('n), bool, bool, bool) -> MemoryOpResult(unit) \ No newline at end of file diff --git a/sail_latex_riscv/valzmem_write_value_meta586f37dd78d9b5be2a948e83778e6186.tex b/sail_latex_riscv/valzmem_write_value_meta586f37dd78d9b5be2a948e83778e6186.tex new file mode 100644 index 00000000..370f6dcb --- /dev/null +++ b/sail_latex_riscv/valzmem_write_value_meta586f37dd78d9b5be2a948e83778e6186.tex @@ -0,0 +1,2 @@ +mem_write_value_meta : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (xlenbits, int('n), bits(8 * 'n), ext_access_type, mem_meta, bool, bool, bool) -> MemoryOpResult(bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzmem_write_valuec32f59efd2dcb7ea78ea4c9778bdf2e1.tex b/sail_latex_riscv/valzmem_write_valuec32f59efd2dcb7ea78ea4c9778bdf2e1.tex new file mode 100644 index 00000000..5996216b --- /dev/null +++ b/sail_latex_riscv/valzmem_write_valuec32f59efd2dcb7ea78ea4c9778bdf2e1.tex @@ -0,0 +1,2 @@ +mem_write_value : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (xlenbits, int('n), bits(8 * 'n), bool, bool, bool) -> MemoryOpResult(bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex b/sail_latex_riscv/valzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex new file mode 100644 index 00000000..589f7d22 --- /dev/null +++ b/sail_latex_riscv/valzmembitstocapability5eb6ab79951caec58164c1aecfc2f63f.tex @@ -0,0 +1 @@ +memBitsToCapability : (bool, CapBits) -> Capability \ No newline at end of file diff --git a/sail_latex_riscv/valzmemoryopresult_add_meta6f4337fb08e42f593b3375a2d1083593.tex b/sail_latex_riscv/valzmemoryopresult_add_meta6f4337fb08e42f593b3375a2d1083593.tex new file mode 100644 index 00000000..2515f697 --- /dev/null +++ b/sail_latex_riscv/valzmemoryopresult_add_meta6f4337fb08e42f593b3375a2d1083593.tex @@ -0,0 +1 @@ +MemoryOpResult_add_meta : forall ('t : Type). (MemoryOpResult('t), mem_meta) -> MemoryOpResult(('t, mem_meta)) \ No newline at end of file diff --git a/sail_latex_riscv/valzmemoryopresult_drop_metafa9388b5fdd8fbe880aa4e686c59bab1.tex b/sail_latex_riscv/valzmemoryopresult_drop_metafa9388b5fdd8fbe880aa4e686c59bab1.tex new file mode 100644 index 00000000..1aad2531 --- /dev/null +++ b/sail_latex_riscv/valzmemoryopresult_drop_metafa9388b5fdd8fbe880aa4e686c59bab1.tex @@ -0,0 +1 @@ +MemoryOpResult_drop_meta : forall ('t : Type). MemoryOpResult(('t, mem_meta)) -> MemoryOpResult('t) \ No newline at end of file diff --git a/sail_latex_riscv/valzmemr_tag8062b3657c5bfba8d529ea5c413abc36.tex b/sail_latex_riscv/valzmemr_tag8062b3657c5bfba8d529ea5c413abc36.tex new file mode 100644 index 00000000..d919c9a4 --- /dev/null +++ b/sail_latex_riscv/valzmemr_tag8062b3657c5bfba8d529ea5c413abc36.tex @@ -0,0 +1 @@ +MEMr_tag : bits(64) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzmemw_tag0a1745a5ee5b60705e9e4051c5099882.tex b/sail_latex_riscv/valzmemw_tag0a1745a5ee5b60705e9e4051c5099882.tex new file mode 100644 index 00000000..572a4f8b --- /dev/null +++ b/sail_latex_riscv/valzmemw_tag0a1745a5ee5b60705e9e4051c5099882.tex @@ -0,0 +1 @@ +MEMw_tag : (bits(64), bool) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzmin_instruction_bytesb10dab453fbe2e946cf3f20de7511e71.tex b/sail_latex_riscv/valzmin_instruction_bytesb10dab453fbe2e946cf3f20de7511e71.tex new file mode 100644 index 00000000..a33e43c9 --- /dev/null +++ b/sail_latex_riscv/valzmin_instruction_bytesb10dab453fbe2e946cf3f20de7511e71.tex @@ -0,0 +1 @@ +min_instruction_bytes : unit -> CapAddrInt \ No newline at end of file diff --git a/sail_latex_riscv/valzmin_intaf4626ab3b9c2d0b9494d7e8d265dd26.tex b/sail_latex_riscv/valzmin_intaf4626ab3b9c2d0b9494d7e8d265dd26.tex new file mode 100644 index 00000000..f0c178dd --- /dev/null +++ b/sail_latex_riscv/valzmin_intaf4626ab3b9c2d0b9494d7e8d265dd26.tex @@ -0,0 +1 @@ +min_int : forall ('x 'y : Int). (int('x), int('y)) -> {'z, ('x <= 'y & 'z == 'x | 'x > 'y & 'z == 'y). int('z)} \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_ccsre3234e42694bb21773ea7b0780c04af8.tex b/sail_latex_riscv/valzmk_ccsre3234e42694bb21773ea7b0780c04af8.tex new file mode 100644 index 00000000..a31b86b5 --- /dev/null +++ b/sail_latex_riscv/valzmk_ccsre3234e42694bb21773ea7b0780c04af8.tex @@ -0,0 +1 @@ +Mk_ccsr : bitvector(64, dec) -> ccsr \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_counterenf15701a312ca5765a184f9c5e5a93c32.tex b/sail_latex_riscv/valzmk_counterenf15701a312ca5765a184f9c5e5a93c32.tex new file mode 100644 index 00000000..41092f96 --- /dev/null +++ b/sail_latex_riscv/valzmk_counterenf15701a312ca5765a184f9c5e5a93c32.tex @@ -0,0 +1 @@ +Mk_Counteren : bitvector(32, dec) -> Counteren \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_counterin5d7512dddbfaeea7688a2e6a3c88ed68.tex b/sail_latex_riscv/valzmk_counterin5d7512dddbfaeea7688a2e6a3c88ed68.tex new file mode 100644 index 00000000..fcea611c --- /dev/null +++ b/sail_latex_riscv/valzmk_counterin5d7512dddbfaeea7688a2e6a3c88ed68.tex @@ -0,0 +1 @@ +Mk_Counterin : bitvector(32, dec) -> Counterin \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_ext_pte_bitsc4519926cf8a81ebbc7a7489bdaaf1ef.tex b/sail_latex_riscv/valzmk_ext_pte_bitsc4519926cf8a81ebbc7a7489bdaaf1ef.tex new file mode 100644 index 00000000..3435e65f --- /dev/null +++ b/sail_latex_riscv/valzmk_ext_pte_bitsc4519926cf8a81ebbc7a7489bdaaf1ef.tex @@ -0,0 +1 @@ +Mk_Ext_PTE_Bits : bitvector(10, dec) -> Ext_PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_fcsr9657e355ebbcf62f95e4a48aa5de149a.tex b/sail_latex_riscv/valzmk_fcsr9657e355ebbcf62f95e4a48aa5de149a.tex new file mode 100644 index 00000000..1cb4a1e4 --- /dev/null +++ b/sail_latex_riscv/valzmk_fcsr9657e355ebbcf62f95e4a48aa5de149a.tex @@ -0,0 +1 @@ +Mk_Fcsr : bitvector(32, dec) -> Fcsr \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_htif_cmde6729ad1ed1b5a3925de51048804de68.tex b/sail_latex_riscv/valzmk_htif_cmde6729ad1ed1b5a3925de51048804de68.tex new file mode 100644 index 00000000..ba0525b6 --- /dev/null +++ b/sail_latex_riscv/valzmk_htif_cmde6729ad1ed1b5a3925de51048804de68.tex @@ -0,0 +1 @@ +Mk_htif_cmd : bitvector(64, dec) -> htif_cmd \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_mcause0c621c96c15db1b801688d6c698bfddd.tex b/sail_latex_riscv/valzmk_mcause0c621c96c15db1b801688d6c698bfddd.tex new file mode 100644 index 00000000..d82cd946 --- /dev/null +++ b/sail_latex_riscv/valzmk_mcause0c621c96c15db1b801688d6c698bfddd.tex @@ -0,0 +1 @@ +Mk_Mcause : bitvector(64, dec) -> Mcause \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_medeleg3829c83ea6bb677825f964507254a95c.tex b/sail_latex_riscv/valzmk_medeleg3829c83ea6bb677825f964507254a95c.tex new file mode 100644 index 00000000..1634b5dc --- /dev/null +++ b/sail_latex_riscv/valzmk_medeleg3829c83ea6bb677825f964507254a95c.tex @@ -0,0 +1 @@ +Mk_Medeleg : bitvector(64, dec) -> Medeleg \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_minterruptsaf75f6e1eef17a71d4f11eede706901d.tex b/sail_latex_riscv/valzmk_minterruptsaf75f6e1eef17a71d4f11eede706901d.tex new file mode 100644 index 00000000..9b52bad4 --- /dev/null +++ b/sail_latex_riscv/valzmk_minterruptsaf75f6e1eef17a71d4f11eede706901d.tex @@ -0,0 +1 @@ +Mk_Minterrupts : bitvector(64, dec) -> Minterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_misa9e5f00faa0413197c9cc5f0f7791d5b7.tex b/sail_latex_riscv/valzmk_misa9e5f00faa0413197c9cc5f0f7791d5b7.tex new file mode 100644 index 00000000..b6a05392 --- /dev/null +++ b/sail_latex_riscv/valzmk_misa9e5f00faa0413197c9cc5f0f7791d5b7.tex @@ -0,0 +1 @@ +Mk_Misa : bitvector(64, dec) -> Misa \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_mstatus5db327fc42d9fe4de62eca1e3915bd06.tex b/sail_latex_riscv/valzmk_mstatus5db327fc42d9fe4de62eca1e3915bd06.tex new file mode 100644 index 00000000..bc70037a --- /dev/null +++ b/sail_latex_riscv/valzmk_mstatus5db327fc42d9fe4de62eca1e3915bd06.tex @@ -0,0 +1 @@ +Mk_Mstatus : bitvector(64, dec) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_mtvec60ead547a4a385f88360115e550b4ab2.tex b/sail_latex_riscv/valzmk_mtvec60ead547a4a385f88360115e550b4ab2.tex new file mode 100644 index 00000000..ca4125ed --- /dev/null +++ b/sail_latex_riscv/valzmk_mtvec60ead547a4a385f88360115e550b4ab2.tex @@ -0,0 +1 @@ +Mk_Mtvec : bitvector(64, dec) -> Mtvec \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_pmpcfg_ent3c5800ef8bd6fce928dfecddb43bbdaf.tex b/sail_latex_riscv/valzmk_pmpcfg_ent3c5800ef8bd6fce928dfecddb43bbdaf.tex new file mode 100644 index 00000000..262d2831 --- /dev/null +++ b/sail_latex_riscv/valzmk_pmpcfg_ent3c5800ef8bd6fce928dfecddb43bbdaf.tex @@ -0,0 +1 @@ +Mk_Pmpcfg_ent : bitvector(8, dec) -> Pmpcfg_ent \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_pte_bits2f40a3dc189d8feaf027fdaa7cd0c939.tex b/sail_latex_riscv/valzmk_pte_bits2f40a3dc189d8feaf027fdaa7cd0c939.tex new file mode 100644 index 00000000..1ee2fa45 --- /dev/null +++ b/sail_latex_riscv/valzmk_pte_bits2f40a3dc189d8feaf027fdaa7cd0c939.tex @@ -0,0 +1 @@ +Mk_PTE_Bits : bitvector(8, dec) -> PTE_Bits \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_satp322e54e0b7f463382f08c680a0164f0a0d.tex b/sail_latex_riscv/valzmk_satp322e54e0b7f463382f08c680a0164f0a0d.tex new file mode 100644 index 00000000..aa3e9d05 --- /dev/null +++ b/sail_latex_riscv/valzmk_satp322e54e0b7f463382f08c680a0164f0a0d.tex @@ -0,0 +1 @@ +Mk_Satp32 : bitvector(32, dec) -> Satp32 \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_satp64329969f3c15112d031d796680dc02dba.tex b/sail_latex_riscv/valzmk_satp64329969f3c15112d031d796680dc02dba.tex new file mode 100644 index 00000000..af62723a --- /dev/null +++ b/sail_latex_riscv/valzmk_satp64329969f3c15112d031d796680dc02dba.tex @@ -0,0 +1 @@ +Mk_Satp64 : bitvector(64, dec) -> Satp64 \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_sedeleg222d7d880065c377c672b48be0312b58.tex b/sail_latex_riscv/valzmk_sedeleg222d7d880065c377c672b48be0312b58.tex new file mode 100644 index 00000000..066f10a6 --- /dev/null +++ b/sail_latex_riscv/valzmk_sedeleg222d7d880065c377c672b48be0312b58.tex @@ -0,0 +1 @@ +Mk_Sedeleg : bitvector(64, dec) -> Sedeleg \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_sinterrupts50ead85256a5e42901dcc54cd50f0280.tex b/sail_latex_riscv/valzmk_sinterrupts50ead85256a5e42901dcc54cd50f0280.tex new file mode 100644 index 00000000..72f99045 --- /dev/null +++ b/sail_latex_riscv/valzmk_sinterrupts50ead85256a5e42901dcc54cd50f0280.tex @@ -0,0 +1 @@ +Mk_Sinterrupts : bitvector(64, dec) -> Sinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_sstatus103c07d81aa6bb97a5681c36b23d8d7f.tex b/sail_latex_riscv/valzmk_sstatus103c07d81aa6bb97a5681c36b23d8d7f.tex new file mode 100644 index 00000000..cb469268 --- /dev/null +++ b/sail_latex_riscv/valzmk_sstatus103c07d81aa6bb97a5681c36b23d8d7f.tex @@ -0,0 +1 @@ +Mk_Sstatus : bitvector(64, dec) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_sv32_paddr38cec8bc7eb5a8f367e53058939b7ee9.tex b/sail_latex_riscv/valzmk_sv32_paddr38cec8bc7eb5a8f367e53058939b7ee9.tex new file mode 100644 index 00000000..07f01eac --- /dev/null +++ b/sail_latex_riscv/valzmk_sv32_paddr38cec8bc7eb5a8f367e53058939b7ee9.tex @@ -0,0 +1 @@ +Mk_SV32_Paddr : bitvector(34, dec) -> SV32_Paddr \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_sv32_pte36c66a6cb6c5db181eeea4960a6a2882.tex b/sail_latex_riscv/valzmk_sv32_pte36c66a6cb6c5db181eeea4960a6a2882.tex new file mode 100644 index 00000000..6ac10de6 --- /dev/null +++ b/sail_latex_riscv/valzmk_sv32_pte36c66a6cb6c5db181eeea4960a6a2882.tex @@ -0,0 +1 @@ +Mk_SV32_PTE : bitvector(32, dec) -> SV32_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_sv32_vaddrd462eac178a4cd9186df0d708de0cabf.tex b/sail_latex_riscv/valzmk_sv32_vaddrd462eac178a4cd9186df0d708de0cabf.tex new file mode 100644 index 00000000..6f371209 --- /dev/null +++ b/sail_latex_riscv/valzmk_sv32_vaddrd462eac178a4cd9186df0d708de0cabf.tex @@ -0,0 +1 @@ +Mk_SV32_Vaddr : bitvector(32, dec) -> SV32_Vaddr \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_sv39_paddr9839b2830ababd96b40ec4ed4e215f85.tex b/sail_latex_riscv/valzmk_sv39_paddr9839b2830ababd96b40ec4ed4e215f85.tex new file mode 100644 index 00000000..1922d562 --- /dev/null +++ b/sail_latex_riscv/valzmk_sv39_paddr9839b2830ababd96b40ec4ed4e215f85.tex @@ -0,0 +1 @@ +Mk_SV39_Paddr : bitvector(56, dec) -> SV39_Paddr \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_sv39_pte72f20a67de4a391e796c728a1b1411bf.tex b/sail_latex_riscv/valzmk_sv39_pte72f20a67de4a391e796c728a1b1411bf.tex new file mode 100644 index 00000000..76144387 --- /dev/null +++ b/sail_latex_riscv/valzmk_sv39_pte72f20a67de4a391e796c728a1b1411bf.tex @@ -0,0 +1 @@ +Mk_SV39_PTE : bitvector(64, dec) -> SV39_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_sv39_vaddr6221e811d934736591eeb06d6df3537c.tex b/sail_latex_riscv/valzmk_sv39_vaddr6221e811d934736591eeb06d6df3537c.tex new file mode 100644 index 00000000..6e43d936 --- /dev/null +++ b/sail_latex_riscv/valzmk_sv39_vaddr6221e811d934736591eeb06d6df3537c.tex @@ -0,0 +1 @@ +Mk_SV39_Vaddr : bitvector(39, dec) -> SV39_Vaddr \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_sv48_paddr2e91c2bf0030c89b31d06021ef3c01eb.tex b/sail_latex_riscv/valzmk_sv48_paddr2e91c2bf0030c89b31d06021ef3c01eb.tex new file mode 100644 index 00000000..9a145617 --- /dev/null +++ b/sail_latex_riscv/valzmk_sv48_paddr2e91c2bf0030c89b31d06021ef3c01eb.tex @@ -0,0 +1 @@ +Mk_SV48_Paddr : bitvector(56, dec) -> SV48_Paddr \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_sv48_pte98d38b79a0d0a08a23bc295e90c40a75.tex b/sail_latex_riscv/valzmk_sv48_pte98d38b79a0d0a08a23bc295e90c40a75.tex new file mode 100644 index 00000000..730102f1 --- /dev/null +++ b/sail_latex_riscv/valzmk_sv48_pte98d38b79a0d0a08a23bc295e90c40a75.tex @@ -0,0 +1 @@ +Mk_SV48_PTE : bitvector(64, dec) -> SV48_PTE \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_sv48_vaddr1a3eef2a9372d3cb53334a8a4bf1eaf9.tex b/sail_latex_riscv/valzmk_sv48_vaddr1a3eef2a9372d3cb53334a8a4bf1eaf9.tex new file mode 100644 index 00000000..7e4b158a --- /dev/null +++ b/sail_latex_riscv/valzmk_sv48_vaddr1a3eef2a9372d3cb53334a8a4bf1eaf9.tex @@ -0,0 +1 @@ +Mk_SV48_Vaddr : bitvector(48, dec) -> SV48_Vaddr \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_uinterrupts22955e59610459ed7c6ad97089d22498.tex b/sail_latex_riscv/valzmk_uinterrupts22955e59610459ed7c6ad97089d22498.tex new file mode 100644 index 00000000..5546d0d7 --- /dev/null +++ b/sail_latex_riscv/valzmk_uinterrupts22955e59610459ed7c6ad97089d22498.tex @@ -0,0 +1 @@ +Mk_Uinterrupts : bitvector(64, dec) -> Uinterrupts \ No newline at end of file diff --git a/sail_latex_riscv/valzmk_ustatus6494ac5e1dcede8689e33b27d65d3204.tex b/sail_latex_riscv/valzmk_ustatus6494ac5e1dcede8689e33b27d65d3204.tex new file mode 100644 index 00000000..d819064f --- /dev/null +++ b/sail_latex_riscv/valzmk_ustatus6494ac5e1dcede8689e33b27d65d3204.tex @@ -0,0 +1 @@ +Mk_Ustatus : bitvector(64, dec) -> Ustatus \ No newline at end of file diff --git a/sail_latex_riscv/valzmmio_read910c976398a0cf73e8b4d12641a665c1.tex b/sail_latex_riscv/valzmmio_read910c976398a0cf73e8b4d12641a665c1.tex new file mode 100644 index 00000000..dc5e0be4 --- /dev/null +++ b/sail_latex_riscv/valzmmio_read910c976398a0cf73e8b4d12641a665c1.tex @@ -0,0 +1,2 @@ +mmio_read : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (AccessType(ext_access_type), xlenbits, int('n)) -> MemoryOpResult(bits(8 * 'n)) \ No newline at end of file diff --git a/sail_latex_riscv/valzmmio_writec1bd5fc64a027d200e43ae1730320ed7.tex b/sail_latex_riscv/valzmmio_writec1bd5fc64a027d200e43ae1730320ed7.tex new file mode 100644 index 00000000..e3b4a621 --- /dev/null +++ b/sail_latex_riscv/valzmmio_writec1bd5fc64a027d200e43ae1730320ed7.tex @@ -0,0 +1,2 @@ +mmio_write : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (xlenbits, int('n), bits(8 * 'n)) -> MemoryOpResult(bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzmul_mnemonic8e8a5c0cf101d49d6656287f35956c53.tex b/sail_latex_riscv/valzmul_mnemonic8e8a5c0cf101d49d6656287f35956c53.tex new file mode 100644 index 00000000..ca68654c --- /dev/null +++ b/sail_latex_riscv/valzmul_mnemonic8e8a5c0cf101d49d6656287f35956c53.tex @@ -0,0 +1 @@ +mul_mnemonic : (bool, bool, bool) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzmult_atomdbad478b99777b7676dde1f5a7900711.tex b/sail_latex_riscv/valzmult_atomdbad478b99777b7676dde1f5a7900711.tex new file mode 100644 index 00000000..6e0158b2 --- /dev/null +++ b/sail_latex_riscv/valzmult_atomdbad478b99777b7676dde1f5a7900711.tex @@ -0,0 +1 @@ +mult_atom : forall ('n 'm : Int). (int('n), int('m)) -> int('n * 'm) \ No newline at end of file diff --git a/sail_latex_riscv/valzmult_inte25d1b032a27b461f0eaf0c84be37a2b.tex b/sail_latex_riscv/valzmult_inte25d1b032a27b461f0eaf0c84be37a2b.tex new file mode 100644 index 00000000..97f71615 --- /dev/null +++ b/sail_latex_riscv/valzmult_inte25d1b032a27b461f0eaf0c84be37a2b.tex @@ -0,0 +1 @@ +mult_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_riscv/valzn_leading_spaces05ea6c2f03435a60412f4bef062a912a.tex b/sail_latex_riscv/valzn_leading_spaces05ea6c2f03435a60412f4bef062a912a.tex new file mode 100644 index 00000000..d32b41ef --- /dev/null +++ b/sail_latex_riscv/valzn_leading_spaces05ea6c2f03435a60412f4bef062a912a.tex @@ -0,0 +1 @@ +n_leading_spaces : string -> nat \ No newline at end of file diff --git a/sail_latex_riscv/valznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex b/sail_latex_riscv/valznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex new file mode 100644 index 00000000..a26b4c6e --- /dev/null +++ b/sail_latex_riscv/valznan_boxf593e1648915be3a65ed1e1cf0dc7712.tex @@ -0,0 +1 @@ +nan_box : bits(32) -> flenbits \ No newline at end of file diff --git a/sail_latex_riscv/valznan_unbox6971c840905d637f635a4793907fe38e.tex b/sail_latex_riscv/valznan_unbox6971c840905d637f635a4793907fe38e.tex new file mode 100644 index 00000000..52579da2 --- /dev/null +++ b/sail_latex_riscv/valznan_unbox6971c840905d637f635a4793907fe38e.tex @@ -0,0 +1 @@ +nan_unbox : flenbits -> bits(32) \ No newline at end of file diff --git a/sail_latex_riscv/valznegate_atomfefdbde89b468d9df54837e864426d70.tex b/sail_latex_riscv/valznegate_atomfefdbde89b468d9df54837e864426d70.tex new file mode 100644 index 00000000..92434174 --- /dev/null +++ b/sail_latex_riscv/valznegate_atomfefdbde89b468d9df54837e864426d70.tex @@ -0,0 +1 @@ +negate_atom : forall ('n : Int). int('n) -> int(- 'n) \ No newline at end of file diff --git a/sail_latex_riscv/valznegate_dc9622c2a4f7fec13696be94bec5ae96c.tex b/sail_latex_riscv/valznegate_dc9622c2a4f7fec13696be94bec5ae96c.tex new file mode 100644 index 00000000..782dc3bd --- /dev/null +++ b/sail_latex_riscv/valznegate_dc9622c2a4f7fec13696be94bec5ae96c.tex @@ -0,0 +1 @@ +negate_D : bits(64) -> bits(64) \ No newline at end of file diff --git a/sail_latex_riscv/valznegate_int42f776f84c124d77c3e367500082e43f.tex b/sail_latex_riscv/valznegate_int42f776f84c124d77c3e367500082e43f.tex new file mode 100644 index 00000000..a982439e --- /dev/null +++ b/sail_latex_riscv/valznegate_int42f776f84c124d77c3e367500082e43f.tex @@ -0,0 +1 @@ +negate_int : int -> int \ No newline at end of file diff --git a/sail_latex_riscv/valznegate_s602acdc6547e76adb79aa6072014fa3e.tex b/sail_latex_riscv/valznegate_s602acdc6547e76adb79aa6072014fa3e.tex new file mode 100644 index 00000000..fe2d7109 --- /dev/null +++ b/sail_latex_riscv/valznegate_s602acdc6547e76adb79aa6072014fa3e.tex @@ -0,0 +1 @@ +negate_S : bits(32) -> bits(32) \ No newline at end of file diff --git a/sail_latex_riscv/valzneq_anythingf220233154ca93d75c0323f604bb8d16.tex b/sail_latex_riscv/valzneq_anythingf220233154ca93d75c0323f604bb8d16.tex new file mode 100644 index 00000000..9ff01c44 --- /dev/null +++ b/sail_latex_riscv/valzneq_anythingf220233154ca93d75c0323f604bb8d16.tex @@ -0,0 +1 @@ +neq_anything : forall ('a : Type). ('a, 'a) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzneq_bits167748c906c068e62596c88540a84f42.tex b/sail_latex_riscv/valzneq_bits167748c906c068e62596c88540a84f42.tex new file mode 100644 index 00000000..e1cecec8 --- /dev/null +++ b/sail_latex_riscv/valzneq_bits167748c906c068e62596c88540a84f42.tex @@ -0,0 +1 @@ +neq_bits : forall ('n : Int). (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex b/sail_latex_riscv/valzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex new file mode 100644 index 00000000..f11545c3 --- /dev/null +++ b/sail_latex_riscv/valzneq_bool40d90a9f3b3bd9e0f1966f198535e779.tex @@ -0,0 +1 @@ +neq_bool : (bool, bool) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex b/sail_latex_riscv/valzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex new file mode 100644 index 00000000..0f7ab4f2 --- /dev/null +++ b/sail_latex_riscv/valzneq_int4fd2be7a83f27bec736b67bdbab1d8c6.tex @@ -0,0 +1 @@ +neq_int : forall ('n 'm : Int). (int('n), int('m)) -> bool('n != 'm) \ No newline at end of file diff --git a/sail_latex_riscv/valzneq_vecefa97ba9877d7fde3cd929d8ec7a401a.tex b/sail_latex_riscv/valzneq_vecefa97ba9877d7fde3cd929d8ec7a401a.tex new file mode 100644 index 00000000..380f9963 --- /dev/null +++ b/sail_latex_riscv/valzneq_vecefa97ba9877d7fde3cd929d8ec7a401a.tex @@ -0,0 +1 @@ +neq_vec : forall ('n : Int). (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valznot_bit3b618f3ab6887bbe967eaa12bf52b297.tex b/sail_latex_riscv/valznot_bit3b618f3ab6887bbe967eaa12bf52b297.tex new file mode 100644 index 00000000..d0a4ffc5 --- /dev/null +++ b/sail_latex_riscv/valznot_bit3b618f3ab6887bbe967eaa12bf52b297.tex @@ -0,0 +1 @@ +not_bit : bit -> bit \ No newline at end of file diff --git a/sail_latex_riscv/valznot_boole1dd3e44bc87a2a10d8e257004c2d36a.tex b/sail_latex_riscv/valznot_boole1dd3e44bc87a2a10d8e257004c2d36a.tex new file mode 100644 index 00000000..366513fd --- /dev/null +++ b/sail_latex_riscv/valznot_boole1dd3e44bc87a2a10d8e257004c2d36a.tex @@ -0,0 +1 @@ +not_bool : forall ('p : Bool). bool('p) -> bool(not('p)) \ No newline at end of file diff --git a/sail_latex_riscv/valznot_implementedde41164205ef21773733c511f05a2946.tex b/sail_latex_riscv/valznot_implementedde41164205ef21773733c511f05a2946.tex new file mode 100644 index 00000000..81c9c5b6 --- /dev/null +++ b/sail_latex_riscv/valznot_implementedde41164205ef21773733c511f05a2946.tex @@ -0,0 +1 @@ +not_implemented : forall ('a : Type). string -> 'a \ No newline at end of file diff --git a/sail_latex_riscv/valznot_vecfb45897f737be88160f5363827ef4a4b.tex b/sail_latex_riscv/valznot_vecfb45897f737be88160f5363827ef4a4b.tex new file mode 100644 index 00000000..b2481577 --- /dev/null +++ b/sail_latex_riscv/valznot_vecfb45897f737be88160f5363827ef4a4b.tex @@ -0,0 +1 @@ +not_vec : forall ('n : Int). bits('n) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valznotcbe861867f25b28c34f5ae99957794ed.tex b/sail_latex_riscv/valznotcbe861867f25b28c34f5ae99957794ed.tex new file mode 100644 index 00000000..2e5b12b4 --- /dev/null +++ b/sail_latex_riscv/valznotcbe861867f25b28c34f5ae99957794ed.tex @@ -0,0 +1 @@ +not : bool -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_a64_barrier_domainfd9b4ecf6f4c38bf5c7e299b7fb7b219.tex b/sail_latex_riscv/valznum_of_a64_barrier_domainfd9b4ecf6f4c38bf5c7e299b7fb7b219.tex new file mode 100644 index 00000000..4f07117f --- /dev/null +++ b/sail_latex_riscv/valznum_of_a64_barrier_domainfd9b4ecf6f4c38bf5c7e299b7fb7b219.tex @@ -0,0 +1 @@ +num_of_a64_barrier_domain : a64_barrier_domain -> {'e, (0 <= 'e & 'e <= 3). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_a64_barrier_typef15d849f5523574b740454d956b74505.tex b/sail_latex_riscv/valznum_of_a64_barrier_typef15d849f5523574b740454d956b74505.tex new file mode 100644 index 00000000..03b37e26 --- /dev/null +++ b/sail_latex_riscv/valznum_of_a64_barrier_typef15d849f5523574b740454d956b74505.tex @@ -0,0 +1 @@ +num_of_a64_barrier_type : a64_barrier_type -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_amoop3990788e22835bf2e0af928f223c3eba.tex b/sail_latex_riscv/valznum_of_amoop3990788e22835bf2e0af928f223c3eba.tex new file mode 100644 index 00000000..bfe3218e --- /dev/null +++ b/sail_latex_riscv/valznum_of_amoop3990788e22835bf2e0af928f223c3eba.tex @@ -0,0 +1 @@ +num_of_amoop : amoop -> {'e, (0 <= 'e & 'e <= 8). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_architecture1ae1fee7c4b64fc1c08b7336a9784f4a.tex b/sail_latex_riscv/valznum_of_architecture1ae1fee7c4b64fc1c08b7336a9784f4a.tex new file mode 100644 index 00000000..9c871a90 --- /dev/null +++ b/sail_latex_riscv/valznum_of_architecture1ae1fee7c4b64fc1c08b7336a9784f4a.tex @@ -0,0 +1 @@ +num_of_Architecture : Architecture -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_bop465de2d51df014a233592af62fc5056d.tex b/sail_latex_riscv/valznum_of_bop465de2d51df014a233592af62fc5056d.tex new file mode 100644 index 00000000..b3714051 --- /dev/null +++ b/sail_latex_riscv/valznum_of_bop465de2d51df014a233592af62fc5056d.tex @@ -0,0 +1 @@ +num_of_bop : bop -> {'e, (0 <= 'e & 'e <= 5). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_cache_op_kindbd96e6225a906fea23a868ff35718006.tex b/sail_latex_riscv/valznum_of_cache_op_kindbd96e6225a906fea23a868ff35718006.tex new file mode 100644 index 00000000..3100f6c9 --- /dev/null +++ b/sail_latex_riscv/valznum_of_cache_op_kindbd96e6225a906fea23a868ff35718006.tex @@ -0,0 +1 @@ +num_of_cache_op_kind : cache_op_kind -> {'e, (0 <= 'e & 'e <= 10). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_capexa430f3db535161473e26bac337cc3ffe.tex b/sail_latex_riscv/valznum_of_capexa430f3db535161473e26bac337cc3ffe.tex new file mode 100644 index 00000000..60bcf124 --- /dev/null +++ b/sail_latex_riscv/valznum_of_capexa430f3db535161473e26bac337cc3ffe.tex @@ -0,0 +1 @@ +num_of_CapEx : CapEx -> {'e, (0 <= 'e & 'e <= 23). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_clearregset49e10f200544574f819f7f660071e10b.tex b/sail_latex_riscv/valznum_of_clearregset49e10f200544574f819f7f660071e10b.tex new file mode 100644 index 00000000..90a394f5 --- /dev/null +++ b/sail_latex_riscv/valznum_of_clearregset49e10f200544574f819f7f660071e10b.tex @@ -0,0 +1 @@ +num_of_ClearRegSet : ClearRegSet -> {'e, (0 <= 'e & 'e <= 1). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex b/sail_latex_riscv/valznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex new file mode 100644 index 00000000..610c108e --- /dev/null +++ b/sail_latex_riscv/valznum_of_cptrcmpop261df9a3b627d5fc110f91fa10e6b254.tex @@ -0,0 +1 @@ +num_of_CPtrCmpOp : CPtrCmpOp -> {'e, (0 <= 'e & 'e <= 7). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_csropc21ef48aae10c4abc2e72f7386a31ce9.tex b/sail_latex_riscv/valznum_of_csropc21ef48aae10c4abc2e72f7386a31ce9.tex new file mode 100644 index 00000000..3a8dfea9 --- /dev/null +++ b/sail_latex_riscv/valznum_of_csropc21ef48aae10c4abc2e72f7386a31ce9.tex @@ -0,0 +1 @@ +num_of_csrop : csrop -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_exceptiontype13e59fd83201d81140ba0f6bbcbd1a7b.tex b/sail_latex_riscv/valznum_of_exceptiontype13e59fd83201d81140ba0f6bbcbd1a7b.tex new file mode 100644 index 00000000..5c297139 --- /dev/null +++ b/sail_latex_riscv/valznum_of_exceptiontype13e59fd83201d81140ba0f6bbcbd1a7b.tex @@ -0,0 +1 @@ +num_of_ExceptionType : ExceptionType -> {'n, (0 <= 'n & 'n < xlen). int('n)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_ext_access_typea973217ed477a3d18820058dd3b21729.tex b/sail_latex_riscv/valznum_of_ext_access_typea973217ed477a3d18820058dd3b21729.tex new file mode 100644 index 00000000..6be5726c --- /dev/null +++ b/sail_latex_riscv/valznum_of_ext_access_typea973217ed477a3d18820058dd3b21729.tex @@ -0,0 +1 @@ +num_of_ext_access_type : ext_access_type -> {'e, (0 <= 'e & 'e <= 1). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_ext_exc_type79451fb17925bed3ec8d5058c42d301d.tex b/sail_latex_riscv/valznum_of_ext_exc_type79451fb17925bed3ec8d5058c42d301d.tex new file mode 100644 index 00000000..93ad7caa --- /dev/null +++ b/sail_latex_riscv/valznum_of_ext_exc_type79451fb17925bed3ec8d5058c42d301d.tex @@ -0,0 +1 @@ +num_of_ext_exc_type : ext_exc_type -> {'n, (0 <= 'n & 'n < xlen). int('n)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_ext_ptw_error7daeb8fc5a17e215ccad3f2a24541927.tex b/sail_latex_riscv/valznum_of_ext_ptw_error7daeb8fc5a17e215ccad3f2a24541927.tex new file mode 100644 index 00000000..980d68da --- /dev/null +++ b/sail_latex_riscv/valznum_of_ext_ptw_error7daeb8fc5a17e215ccad3f2a24541927.tex @@ -0,0 +1 @@ +num_of_ext_ptw_error : ext_ptw_error -> {'e, (0 <= 'e & 'e <= 0). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_ext_ptw_fail785ab48a0d85159cd76e2d20768c9173.tex b/sail_latex_riscv/valznum_of_ext_ptw_fail785ab48a0d85159cd76e2d20768c9173.tex new file mode 100644 index 00000000..09ee11e8 --- /dev/null +++ b/sail_latex_riscv/valznum_of_ext_ptw_fail785ab48a0d85159cd76e2d20768c9173.tex @@ -0,0 +1 @@ +num_of_ext_ptw_fail : ext_ptw_fail -> {'e, (0 <= 'e & 'e <= 1). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_ext_ptw_lcfde46f3a7b817078010b5dc3a4f25be7.tex b/sail_latex_riscv/valznum_of_ext_ptw_lcfde46f3a7b817078010b5dc3a4f25be7.tex new file mode 100644 index 00000000..6e623e73 --- /dev/null +++ b/sail_latex_riscv/valznum_of_ext_ptw_lcfde46f3a7b817078010b5dc3a4f25be7.tex @@ -0,0 +1 @@ +num_of_ext_ptw_lc : ext_ptw_lc -> {'e, (0 <= 'e & 'e <= 1). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_ext_ptw_sc2a22418de077e3289633414d48a30bbe.tex b/sail_latex_riscv/valznum_of_ext_ptw_sc2a22418de077e3289633414d48a30bbe.tex new file mode 100644 index 00000000..54763899 --- /dev/null +++ b/sail_latex_riscv/valznum_of_ext_ptw_sc2a22418de077e3289633414d48a30bbe.tex @@ -0,0 +1 @@ +num_of_ext_ptw_sc : ext_ptw_sc -> {'e, (0 <= 'e & 'e <= 1). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_extstatus8d29ae3139c8c2d5d4fa7489689b6a41.tex b/sail_latex_riscv/valznum_of_extstatus8d29ae3139c8c2d5d4fa7489689b6a41.tex new file mode 100644 index 00000000..2119277e --- /dev/null +++ b/sail_latex_riscv/valznum_of_extstatus8d29ae3139c8c2d5d4fa7489689b6a41.tex @@ -0,0 +1 @@ +num_of_ExtStatus : ExtStatus -> {'e, (0 <= 'e & 'e <= 3). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_f_bin_op_dd209f84b003673fbf65e2d0267de89cd.tex b/sail_latex_riscv/valznum_of_f_bin_op_dd209f84b003673fbf65e2d0267de89cd.tex new file mode 100644 index 00000000..e76b86fc --- /dev/null +++ b/sail_latex_riscv/valznum_of_f_bin_op_dd209f84b003673fbf65e2d0267de89cd.tex @@ -0,0 +1 @@ +num_of_f_bin_op_D : f_bin_op_D -> {'e, (0 <= 'e & 'e <= 7). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_f_bin_op_s67646ca4512abf0a4d4b44cd4f5b13ca.tex b/sail_latex_riscv/valznum_of_f_bin_op_s67646ca4512abf0a4d4b44cd4f5b13ca.tex new file mode 100644 index 00000000..cfc00064 --- /dev/null +++ b/sail_latex_riscv/valznum_of_f_bin_op_s67646ca4512abf0a4d4b44cd4f5b13ca.tex @@ -0,0 +1 @@ +num_of_f_bin_op_S : f_bin_op_S -> {'e, (0 <= 'e & 'e <= 7). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_f_bin_rm_op_dc153c7dd1e01a91df37cddfd46dfd9da.tex b/sail_latex_riscv/valznum_of_f_bin_rm_op_dc153c7dd1e01a91df37cddfd46dfd9da.tex new file mode 100644 index 00000000..67a090aa --- /dev/null +++ b/sail_latex_riscv/valznum_of_f_bin_rm_op_dc153c7dd1e01a91df37cddfd46dfd9da.tex @@ -0,0 +1 @@ +num_of_f_bin_rm_op_D : f_bin_rm_op_D -> {'e, (0 <= 'e & 'e <= 3). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_f_bin_rm_op_s893f36c63d593d34b1cf67930090a6d2.tex b/sail_latex_riscv/valznum_of_f_bin_rm_op_s893f36c63d593d34b1cf67930090a6d2.tex new file mode 100644 index 00000000..3e1c6946 --- /dev/null +++ b/sail_latex_riscv/valznum_of_f_bin_rm_op_s893f36c63d593d34b1cf67930090a6d2.tex @@ -0,0 +1 @@ +num_of_f_bin_rm_op_S : f_bin_rm_op_S -> {'e, (0 <= 'e & 'e <= 3). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_f_madd_op_d37717f7c44daba9b30789132320443ff.tex b/sail_latex_riscv/valznum_of_f_madd_op_d37717f7c44daba9b30789132320443ff.tex new file mode 100644 index 00000000..fa1277c4 --- /dev/null +++ b/sail_latex_riscv/valznum_of_f_madd_op_d37717f7c44daba9b30789132320443ff.tex @@ -0,0 +1 @@ +num_of_f_madd_op_D : f_madd_op_D -> {'e, (0 <= 'e & 'e <= 3). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_f_madd_op_s775906828ed91e55055481dedc5d9da4.tex b/sail_latex_riscv/valznum_of_f_madd_op_s775906828ed91e55055481dedc5d9da4.tex new file mode 100644 index 00000000..5890b925 --- /dev/null +++ b/sail_latex_riscv/valznum_of_f_madd_op_s775906828ed91e55055481dedc5d9da4.tex @@ -0,0 +1 @@ +num_of_f_madd_op_S : f_madd_op_S -> {'e, (0 <= 'e & 'e <= 3). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_f_un_op_d6d388f339a377c4a985a55a3c728bb8f.tex b/sail_latex_riscv/valznum_of_f_un_op_d6d388f339a377c4a985a55a3c728bb8f.tex new file mode 100644 index 00000000..c300f089 --- /dev/null +++ b/sail_latex_riscv/valznum_of_f_un_op_d6d388f339a377c4a985a55a3c728bb8f.tex @@ -0,0 +1 @@ +num_of_f_un_op_D : f_un_op_D -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_f_un_op_se59a01770756c5c1ccc368187228ef32.tex b/sail_latex_riscv/valznum_of_f_un_op_se59a01770756c5c1ccc368187228ef32.tex new file mode 100644 index 00000000..37de3901 --- /dev/null +++ b/sail_latex_riscv/valznum_of_f_un_op_se59a01770756c5c1ccc368187228ef32.tex @@ -0,0 +1 @@ +num_of_f_un_op_S : f_un_op_S -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_f_un_rm_op_d6e3378f59faf04b5d017d7c996a625e0.tex b/sail_latex_riscv/valznum_of_f_un_rm_op_d6e3378f59faf04b5d017d7c996a625e0.tex new file mode 100644 index 00000000..9ac2522d --- /dev/null +++ b/sail_latex_riscv/valznum_of_f_un_rm_op_d6e3378f59faf04b5d017d7c996a625e0.tex @@ -0,0 +1 @@ +num_of_f_un_rm_op_D : f_un_rm_op_D -> {'e, (0 <= 'e & 'e <= 10). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_f_un_rm_op_se915d9a4f61459b98b43ab8bc6055666.tex b/sail_latex_riscv/valznum_of_f_un_rm_op_se915d9a4f61459b98b43ab8bc6055666.tex new file mode 100644 index 00000000..2ad3c689 --- /dev/null +++ b/sail_latex_riscv/valznum_of_f_un_rm_op_se915d9a4f61459b98b43ab8bc6055666.tex @@ -0,0 +1 @@ +num_of_f_un_rm_op_S : f_un_rm_op_S -> {'e, (0 <= 'e & 'e <= 8). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_interrupttype186751debed5f5a4e5f875749623071b.tex b/sail_latex_riscv/valznum_of_interrupttype186751debed5f5a4e5f875749623071b.tex new file mode 100644 index 00000000..8e7bea3f --- /dev/null +++ b/sail_latex_riscv/valznum_of_interrupttype186751debed5f5a4e5f875749623071b.tex @@ -0,0 +1 @@ +num_of_InterruptType : InterruptType -> {'e, (0 <= 'e & 'e <= 8). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_iop7e0f948724eaec1edf1ab6539e332d14.tex b/sail_latex_riscv/valznum_of_iop7e0f948724eaec1edf1ab6539e332d14.tex new file mode 100644 index 00000000..7bd01122 --- /dev/null +++ b/sail_latex_riscv/valznum_of_iop7e0f948724eaec1edf1ab6539e332d14.tex @@ -0,0 +1 @@ +num_of_iop : iop -> {'e, (0 <= 'e & 'e <= 5). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_pmpaddrmatch6db470099c3f03581d51f40437610a39.tex b/sail_latex_riscv/valznum_of_pmpaddrmatch6db470099c3f03581d51f40437610a39.tex new file mode 100644 index 00000000..1d63c43b --- /dev/null +++ b/sail_latex_riscv/valznum_of_pmpaddrmatch6db470099c3f03581d51f40437610a39.tex @@ -0,0 +1 @@ +num_of_pmpAddrMatch : pmpAddrMatch -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_pmpaddrmatchtypee330d16c3db664232af948049b8edeb9.tex b/sail_latex_riscv/valznum_of_pmpaddrmatchtypee330d16c3db664232af948049b8edeb9.tex new file mode 100644 index 00000000..88bdd56b --- /dev/null +++ b/sail_latex_riscv/valznum_of_pmpaddrmatchtypee330d16c3db664232af948049b8edeb9.tex @@ -0,0 +1 @@ +num_of_PmpAddrMatchType : PmpAddrMatchType -> {'e, (0 <= 'e & 'e <= 3). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_pmpmatch3a839a54108c809c88766e9119a0bce5.tex b/sail_latex_riscv/valznum_of_pmpmatch3a839a54108c809c88766e9119a0bce5.tex new file mode 100644 index 00000000..fb153a3c --- /dev/null +++ b/sail_latex_riscv/valznum_of_pmpmatch3a839a54108c809c88766e9119a0bce5.tex @@ -0,0 +1 @@ +num_of_pmpMatch : pmpMatch -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_privilege40c636ca569f6d4bb59a57bee3b2742d.tex b/sail_latex_riscv/valznum_of_privilege40c636ca569f6d4bb59a57bee3b2742d.tex new file mode 100644 index 00000000..6099cdcf --- /dev/null +++ b/sail_latex_riscv/valznum_of_privilege40c636ca569f6d4bb59a57bee3b2742d.tex @@ -0,0 +1 @@ +num_of_Privilege : Privilege -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_read_kind9f1d12d5627d7618c1e31c888906fc68.tex b/sail_latex_riscv/valznum_of_read_kind9f1d12d5627d7618c1e31c888906fc68.tex new file mode 100644 index 00000000..5fc33a25 --- /dev/null +++ b/sail_latex_riscv/valznum_of_read_kind9f1d12d5627d7618c1e31c888906fc68.tex @@ -0,0 +1 @@ +num_of_read_kind : read_kind -> {'e, (0 <= 'e & 'e <= 11). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_retiredc5322d8e56eb574c7eb3ebf89e0586af.tex b/sail_latex_riscv/valznum_of_retiredc5322d8e56eb574c7eb3ebf89e0586af.tex new file mode 100644 index 00000000..46277afa --- /dev/null +++ b/sail_latex_riscv/valznum_of_retiredc5322d8e56eb574c7eb3ebf89e0586af.tex @@ -0,0 +1 @@ +num_of_Retired : Retired -> {'e, (0 <= 'e & 'e <= 1). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_rop6b1530298b7a57e62b47f86bb5f1b15c.tex b/sail_latex_riscv/valznum_of_rop6b1530298b7a57e62b47f86bb5f1b15c.tex new file mode 100644 index 00000000..078502c8 --- /dev/null +++ b/sail_latex_riscv/valznum_of_rop6b1530298b7a57e62b47f86bb5f1b15c.tex @@ -0,0 +1 @@ +num_of_rop : rop -> {'e, (0 <= 'e & 'e <= 9). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_ropw2d1d1b64d2060822876c1a3c1d164870.tex b/sail_latex_riscv/valznum_of_ropw2d1d1b64d2060822876c1a3c1d164870.tex new file mode 100644 index 00000000..52c0ceb5 --- /dev/null +++ b/sail_latex_riscv/valznum_of_ropw2d1d1b64d2060822876c1a3c1d164870.tex @@ -0,0 +1 @@ +num_of_ropw : ropw -> {'e, (0 <= 'e & 'e <= 4). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_rounding_mode41a60e82308e6507de434c7dc6e17db8.tex b/sail_latex_riscv/valznum_of_rounding_mode41a60e82308e6507de434c7dc6e17db8.tex new file mode 100644 index 00000000..cd9aad91 --- /dev/null +++ b/sail_latex_riscv/valznum_of_rounding_mode41a60e82308e6507de434c7dc6e17db8.tex @@ -0,0 +1 @@ +num_of_rounding_mode : rounding_mode -> {'e, (0 <= 'e & 'e <= 5). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_satpmode714998a67cc48d1f59bc52de3d9a052f.tex b/sail_latex_riscv/valznum_of_satpmode714998a67cc48d1f59bc52de3d9a052f.tex new file mode 100644 index 00000000..c2e5e771 --- /dev/null +++ b/sail_latex_riscv/valznum_of_satpmode714998a67cc48d1f59bc52de3d9a052f.tex @@ -0,0 +1 @@ +num_of_SATPMode : SATPMode -> {'e, (0 <= 'e & 'e <= 3). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_sopfa04a24d46338146566ae6e8a80132f0.tex b/sail_latex_riscv/valznum_of_sopfa04a24d46338146566ae6e8a80132f0.tex new file mode 100644 index 00000000..1115b54c --- /dev/null +++ b/sail_latex_riscv/valznum_of_sopfa04a24d46338146566ae6e8a80132f0.tex @@ -0,0 +1 @@ +num_of_sop : sop -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_sopw352409ee6a8831f827129fc3d78cd4d6.tex b/sail_latex_riscv/valznum_of_sopw352409ee6a8831f827129fc3d78cd4d6.tex new file mode 100644 index 00000000..fce6ac8d --- /dev/null +++ b/sail_latex_riscv/valznum_of_sopw352409ee6a8831f827129fc3d78cd4d6.tex @@ -0,0 +1 @@ +num_of_sopw : sopw -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_trans_kind7086883ee37c97f3e6858f19cebb2163.tex b/sail_latex_riscv/valznum_of_trans_kind7086883ee37c97f3e6858f19cebb2163.tex new file mode 100644 index 00000000..991d7b5a --- /dev/null +++ b/sail_latex_riscv/valznum_of_trans_kind7086883ee37c97f3e6858f19cebb2163.tex @@ -0,0 +1 @@ +num_of_trans_kind : trans_kind -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_trapvectormode9673c0ba1b150ae7d0c789bf1ea8f4fe.tex b/sail_latex_riscv/valznum_of_trapvectormode9673c0ba1b150ae7d0c789bf1ea8f4fe.tex new file mode 100644 index 00000000..968c77f1 --- /dev/null +++ b/sail_latex_riscv/valznum_of_trapvectormode9673c0ba1b150ae7d0c789bf1ea8f4fe.tex @@ -0,0 +1 @@ +num_of_TrapVectorMode : TrapVectorMode -> {'e, (0 <= 'e & 'e <= 2). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_uop5155bc57344db1e0852d69264b07f354.tex b/sail_latex_riscv/valznum_of_uop5155bc57344db1e0852d69264b07f354.tex new file mode 100644 index 00000000..4ae2ccc1 --- /dev/null +++ b/sail_latex_riscv/valznum_of_uop5155bc57344db1e0852d69264b07f354.tex @@ -0,0 +1 @@ +num_of_uop : uop -> {'e, (0 <= 'e & 'e <= 1). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_word_width80798ebf687d8b1ac16aea948967912d.tex b/sail_latex_riscv/valznum_of_word_width80798ebf687d8b1ac16aea948967912d.tex new file mode 100644 index 00000000..bdceb00d --- /dev/null +++ b/sail_latex_riscv/valznum_of_word_width80798ebf687d8b1ac16aea948967912d.tex @@ -0,0 +1 @@ +num_of_word_width : word_width -> {'e, (0 <= 'e & 'e <= 3). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznum_of_write_kind056951dbaa3b47d3c25ba586d7093c91.tex b/sail_latex_riscv/valznum_of_write_kind056951dbaa3b47d3c25ba586d7093c91.tex new file mode 100644 index 00000000..ecd492df --- /dev/null +++ b/sail_latex_riscv/valznum_of_write_kind056951dbaa3b47d3c25ba586d7093c91.tex @@ -0,0 +1 @@ +num_of_write_kind : write_kind -> {'e, (0 <= 'e & 'e <= 10). int('e)} \ No newline at end of file diff --git a/sail_latex_riscv/valznvflag96f5e3b2efdbb80ea87eb99f361ac158.tex b/sail_latex_riscv/valznvflag96f5e3b2efdbb80ea87eb99f361ac158.tex new file mode 100644 index 00000000..b8958730 --- /dev/null +++ b/sail_latex_riscv/valznvflag96f5e3b2efdbb80ea87eb99f361ac158.tex @@ -0,0 +1 @@ +nvFlag : unit -> bits(5) \ No newline at end of file diff --git a/sail_latex_riscv/valznxflaga9ef0edc4edc03b79abaa230aaad20a6.tex b/sail_latex_riscv/valznxflaga9ef0edc4edc03b79abaa230aaad20a6.tex new file mode 100644 index 00000000..7d66a59b --- /dev/null +++ b/sail_latex_riscv/valznxflaga9ef0edc4edc03b79abaa230aaad20a6.tex @@ -0,0 +1 @@ +nxFlag : unit -> bits(5) \ No newline at end of file diff --git a/sail_latex_riscv/valzofflag1be1156688e569fa940a9118708be17d.tex b/sail_latex_riscv/valzofflag1be1156688e569fa940a9118708be17d.tex new file mode 100644 index 00000000..229f23e5 --- /dev/null +++ b/sail_latex_riscv/valzofflag1be1156688e569fa940a9118708be17d.tex @@ -0,0 +1 @@ +ofFlag : unit -> bits(5) \ No newline at end of file diff --git a/sail_latex_riscv/valzones26f94136f5db8afd4e9df1e512f7fdc5.tex b/sail_latex_riscv/valzones26f94136f5db8afd4e9df1e512f7fdc5.tex new file mode 100644 index 00000000..9554a081 --- /dev/null +++ b/sail_latex_riscv/valzones26f94136f5db8afd4e9df1e512f7fdc5.tex @@ -0,0 +1 @@ +ones : forall ('n : Int), 'n >= 0. implicit('n) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzopt_spc4aab1150dfed90f36fea1776963edbf0.tex b/sail_latex_riscv/valzopt_spc4aab1150dfed90f36fea1776963edbf0.tex new file mode 100644 index 00000000..8e465a91 --- /dev/null +++ b/sail_latex_riscv/valzopt_spc4aab1150dfed90f36fea1776963edbf0.tex @@ -0,0 +1 @@ +opt_spc : unit <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzopt_spc_backwards68e297450ccdf6f2339325379c27029f.tex b/sail_latex_riscv/valzopt_spc_backwards68e297450ccdf6f2339325379c27029f.tex new file mode 100644 index 00000000..c414f868 --- /dev/null +++ b/sail_latex_riscv/valzopt_spc_backwards68e297450ccdf6f2339325379c27029f.tex @@ -0,0 +1 @@ +opt_spc_backwards : string -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzopt_spc_forwards395c7cf20c474712cbbb7c80edd24bda.tex b/sail_latex_riscv/valzopt_spc_forwards395c7cf20c474712cbbb7c80edd24bda.tex new file mode 100644 index 00000000..a7d57e8f --- /dev/null +++ b/sail_latex_riscv/valzopt_spc_forwards395c7cf20c474712cbbb7c80edd24bda.tex @@ -0,0 +1 @@ +opt_spc_forwards : unit -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzopt_spc_matches_prefix495f7798e6650e2ff628a5b7715c161c.tex b/sail_latex_riscv/valzopt_spc_matches_prefix495f7798e6650e2ff628a5b7715c161c.tex new file mode 100644 index 00000000..533fec39 --- /dev/null +++ b/sail_latex_riscv/valzopt_spc_matches_prefix495f7798e6650e2ff628a5b7715c161c.tex @@ -0,0 +1 @@ +opt_spc_matches_prefix : string -> option((unit, nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzor_bool5f07f9d72d4d1495c45a3531c787546a.tex b/sail_latex_riscv/valzor_bool5f07f9d72d4d1495c45a3531c787546a.tex new file mode 100644 index 00000000..bd3bcb77 --- /dev/null +++ b/sail_latex_riscv/valzor_bool5f07f9d72d4d1495c45a3531c787546a.tex @@ -0,0 +1 @@ +or_bool : forall ('p 'q : Bool). (bool('p), bool('q)) -> bool(('p | 'q)) \ No newline at end of file diff --git a/sail_latex_riscv/valzor_vec467c7a3f74be27085fe1b2aa3651ffe7.tex b/sail_latex_riscv/valzor_vec467c7a3f74be27085fe1b2aa3651ffe7.tex new file mode 100644 index 00000000..45e50cce --- /dev/null +++ b/sail_latex_riscv/valzor_vec467c7a3f74be27085fe1b2aa3651ffe7.tex @@ -0,0 +1 @@ +or_vec : forall ('n : Int). (bits('n), bits('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzpc_alignment_mask1943267c124397815476842d08d3901e.tex b/sail_latex_riscv/valzpc_alignment_mask1943267c124397815476842d08d3901e.tex new file mode 100644 index 00000000..8fd0c27a --- /dev/null +++ b/sail_latex_riscv/valzpc_alignment_mask1943267c124397815476842d08d3901e.tex @@ -0,0 +1 @@ +pc_alignment_mask : unit -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex b/sail_latex_riscv/valzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex new file mode 100644 index 00000000..a69a2b58 --- /dev/null +++ b/sail_latex_riscv/valzpcc_access_system_regsc75c9194580770304d0d456839785b75.tex @@ -0,0 +1 @@ +pcc_access_system_regs : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzphys_mem_readdcad862ae3a42c22bfc78bad8e3328db.tex b/sail_latex_riscv/valzphys_mem_readdcad862ae3a42c22bfc78bad8e3328db.tex new file mode 100644 index 00000000..b80d2c06 --- /dev/null +++ b/sail_latex_riscv/valzphys_mem_readdcad862ae3a42c22bfc78bad8e3328db.tex @@ -0,0 +1,2 @@ +phys_mem_read : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (AccessType(ext_access_type), xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta)) \ No newline at end of file diff --git a/sail_latex_riscv/valzphys_mem_segments83ff72aa5aa998a329fa30de106aa0a7.tex b/sail_latex_riscv/valzphys_mem_segments83ff72aa5aa998a329fa30de106aa0a7.tex new file mode 100644 index 00000000..dbf8cb4c --- /dev/null +++ b/sail_latex_riscv/valzphys_mem_segments83ff72aa5aa998a329fa30de106aa0a7.tex @@ -0,0 +1 @@ +phys_mem_segments : unit -> list((xlenbits, xlenbits)) \ No newline at end of file diff --git a/sail_latex_riscv/valzphys_mem_writefae7815adda192bed56129eba4b7bb01.tex b/sail_latex_riscv/valzphys_mem_writefae7815adda192bed56129eba4b7bb01.tex new file mode 100644 index 00000000..2da027a1 --- /dev/null +++ b/sail_latex_riscv/valzphys_mem_writefae7815adda192bed56129eba4b7bb01.tex @@ -0,0 +1,2 @@ +phys_mem_write : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (write_kind, xlenbits, int('n), bits(8 * 'n), mem_meta) -> MemoryOpResult(bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzplain_vector_access792547dd734d4ff2e6078cbb88967469.tex b/sail_latex_riscv/valzplain_vector_access792547dd734d4ff2e6078cbb88967469.tex new file mode 100644 index 00000000..7dbd00bd --- /dev/null +++ b/sail_latex_riscv/valzplain_vector_access792547dd734d4ff2e6078cbb88967469.tex @@ -0,0 +1 @@ +plain_vector_access : forall ('n 'm : Int)('a : Type), (0 <= 'm & 'm < 'n). (vector('n, dec, 'a), int('m)) -> 'a \ No newline at end of file diff --git a/sail_latex_riscv/valzplain_vector_updateb31d67bfe51b1a6f79983347dfc57da0.tex b/sail_latex_riscv/valzplain_vector_updateb31d67bfe51b1a6f79983347dfc57da0.tex new file mode 100644 index 00000000..beb9b152 --- /dev/null +++ b/sail_latex_riscv/valzplain_vector_updateb31d67bfe51b1a6f79983347dfc57da0.tex @@ -0,0 +1,2 @@ +plain_vector_update : forall ('n 'm : Int)('a : Type), (0 <= 'm & 'm < 'n). + (vector('n, dec, 'a), int('m), 'a) -> vector('n, dec, 'a) \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_clint_base0196a3035036838f7fe4f78d61a1f9d8.tex b/sail_latex_riscv/valzplat_clint_base0196a3035036838f7fe4f78d61a1f9d8.tex new file mode 100644 index 00000000..49f55d7c --- /dev/null +++ b/sail_latex_riscv/valzplat_clint_base0196a3035036838f7fe4f78d61a1f9d8.tex @@ -0,0 +1 @@ +plat_clint_base : unit -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_clint_sizze8fb2ec94310f08d19d4c7c0476f57919.tex b/sail_latex_riscv/valzplat_clint_sizze8fb2ec94310f08d19d4c7c0476f57919.tex new file mode 100644 index 00000000..ef02c143 --- /dev/null +++ b/sail_latex_riscv/valzplat_clint_sizze8fb2ec94310f08d19d4c7c0476f57919.tex @@ -0,0 +1 @@ +plat_clint_size : unit -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_enable_dirty_update0b255805eb9610b556493bfe506416f2.tex b/sail_latex_riscv/valzplat_enable_dirty_update0b255805eb9610b556493bfe506416f2.tex new file mode 100644 index 00000000..75b6f38d --- /dev/null +++ b/sail_latex_riscv/valzplat_enable_dirty_update0b255805eb9610b556493bfe506416f2.tex @@ -0,0 +1 @@ +plat_enable_dirty_update : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_enable_misaligned_accesscb4191568185cb3901b1944164f65f6e.tex b/sail_latex_riscv/valzplat_enable_misaligned_accesscb4191568185cb3901b1944164f65f6e.tex new file mode 100644 index 00000000..7858067a --- /dev/null +++ b/sail_latex_riscv/valzplat_enable_misaligned_accesscb4191568185cb3901b1944164f65f6e.tex @@ -0,0 +1 @@ +plat_enable_misaligned_access : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_enable_pmpe3a19dd2b08d4a89664077b8a1cf0844.tex b/sail_latex_riscv/valzplat_enable_pmpe3a19dd2b08d4a89664077b8a1cf0844.tex new file mode 100644 index 00000000..b577754d --- /dev/null +++ b/sail_latex_riscv/valzplat_enable_pmpe3a19dd2b08d4a89664077b8a1cf0844.tex @@ -0,0 +1 @@ +plat_enable_pmp : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_htif_tohostf9ba2e7ae67de81976fbefc0304b89d1.tex b/sail_latex_riscv/valzplat_htif_tohostf9ba2e7ae67de81976fbefc0304b89d1.tex new file mode 100644 index 00000000..f3c1b12a --- /dev/null +++ b/sail_latex_riscv/valzplat_htif_tohostf9ba2e7ae67de81976fbefc0304b89d1.tex @@ -0,0 +1 @@ +plat_htif_tohost : unit -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_insns_per_tick0a43cf4e39e3447031fdc4fb6c22d20e.tex b/sail_latex_riscv/valzplat_insns_per_tick0a43cf4e39e3447031fdc4fb6c22d20e.tex new file mode 100644 index 00000000..2e51b552 --- /dev/null +++ b/sail_latex_riscv/valzplat_insns_per_tick0a43cf4e39e3447031fdc4fb6c22d20e.tex @@ -0,0 +1 @@ +plat_insns_per_tick : unit -> int \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_mtval_has_illegal_inst_bits49cda37cfdfffb5c464c6333bb83f0b0.tex b/sail_latex_riscv/valzplat_mtval_has_illegal_inst_bits49cda37cfdfffb5c464c6333bb83f0b0.tex new file mode 100644 index 00000000..b1afc8e2 --- /dev/null +++ b/sail_latex_riscv/valzplat_mtval_has_illegal_inst_bits49cda37cfdfffb5c464c6333bb83f0b0.tex @@ -0,0 +1 @@ +plat_mtval_has_illegal_inst_bits : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_ram_base0d7614688445a7408614bad359843641.tex b/sail_latex_riscv/valzplat_ram_base0d7614688445a7408614bad359843641.tex new file mode 100644 index 00000000..df6ca6ee --- /dev/null +++ b/sail_latex_riscv/valzplat_ram_base0d7614688445a7408614bad359843641.tex @@ -0,0 +1 @@ +plat_ram_base : unit -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_ram_sizze3e389712a74fd397e22555e7f548f008.tex b/sail_latex_riscv/valzplat_ram_sizze3e389712a74fd397e22555e7f548f008.tex new file mode 100644 index 00000000..d44ea860 --- /dev/null +++ b/sail_latex_riscv/valzplat_ram_sizze3e389712a74fd397e22555e7f548f008.tex @@ -0,0 +1 @@ +plat_ram_size : unit -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_rom_basebdbb354c7f3bb238fa08300023cbf0b5.tex b/sail_latex_riscv/valzplat_rom_basebdbb354c7f3bb238fa08300023cbf0b5.tex new file mode 100644 index 00000000..20920d90 --- /dev/null +++ b/sail_latex_riscv/valzplat_rom_basebdbb354c7f3bb238fa08300023cbf0b5.tex @@ -0,0 +1 @@ +plat_rom_base : unit -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_rom_sizze563dbbc4d715886f76fbde684ac8a500.tex b/sail_latex_riscv/valzplat_rom_sizze563dbbc4d715886f76fbde684ac8a500.tex new file mode 100644 index 00000000..f5d3658d --- /dev/null +++ b/sail_latex_riscv/valzplat_rom_sizze563dbbc4d715886f76fbde684ac8a500.tex @@ -0,0 +1 @@ +plat_rom_size : unit -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_term_readbc174c8d489d235edca54e912406e103.tex b/sail_latex_riscv/valzplat_term_readbc174c8d489d235edca54e912406e103.tex new file mode 100644 index 00000000..76941866 --- /dev/null +++ b/sail_latex_riscv/valzplat_term_readbc174c8d489d235edca54e912406e103.tex @@ -0,0 +1 @@ +plat_term_read : unit -> bits(8) \ No newline at end of file diff --git a/sail_latex_riscv/valzplat_term_write036fbb8469eac6f64f37bf65565a5f02.tex b/sail_latex_riscv/valzplat_term_write036fbb8469eac6f64f37bf65565a5f02.tex new file mode 100644 index 00000000..9783caff --- /dev/null +++ b/sail_latex_riscv/valzplat_term_write036fbb8469eac6f64f37bf65565a5f02.tex @@ -0,0 +1 @@ +plat_term_write : bits(8) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzplatform_wfi377b23f6619d58844892f179f2934ac6.tex b/sail_latex_riscv/valzplatform_wfi377b23f6619d58844892f179f2934ac6.tex new file mode 100644 index 00000000..26a3fe52 --- /dev/null +++ b/sail_latex_riscv/valzplatform_wfi377b23f6619d58844892f179f2934ac6.tex @@ -0,0 +1 @@ +platform_wfi : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzpmp_mem_readc45533831bda1c394396c536ba168b7a.tex b/sail_latex_riscv/valzpmp_mem_readc45533831bda1c394396c536ba168b7a.tex new file mode 100644 index 00000000..41dbf1ae --- /dev/null +++ b/sail_latex_riscv/valzpmp_mem_readc45533831bda1c394396c536ba168b7a.tex @@ -0,0 +1,2 @@ +pmp_mem_read : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (AccessType(ext_access_type), xlenbits, int('n), bool, bool, bool, bool) -> MemoryOpResult((bits(8 * 'n), mem_meta)) \ No newline at end of file diff --git a/sail_latex_riscv/valzpmp_mem_write4ae53a6de2384826cc3e765eccd350e8.tex b/sail_latex_riscv/valzpmp_mem_write4ae53a6de2384826cc3e765eccd350e8.tex new file mode 100644 index 00000000..1281306a --- /dev/null +++ b/sail_latex_riscv/valzpmp_mem_write4ae53a6de2384826cc3e765eccd350e8.tex @@ -0,0 +1,2 @@ +pmp_mem_write : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (write_kind, xlenbits, int('n), bits(8 * 'n), ext_access_type, mem_meta) -> MemoryOpResult(bool) \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpaddrmatch_of_num92a36380d4ab664cee1f4ee0143e390f.tex b/sail_latex_riscv/valzpmpaddrmatch_of_num92a36380d4ab664cee1f4ee0143e390f.tex new file mode 100644 index 00000000..041cdabe --- /dev/null +++ b/sail_latex_riscv/valzpmpaddrmatch_of_num92a36380d4ab664cee1f4ee0143e390f.tex @@ -0,0 +1 @@ +pmpAddrMatch_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> pmpAddrMatch \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpaddrmatchtype_of_bits8b4e245ce3d01f111a1f89404623ac98.tex b/sail_latex_riscv/valzpmpaddrmatchtype_of_bits8b4e245ce3d01f111a1f89404623ac98.tex new file mode 100644 index 00000000..a58b71e4 --- /dev/null +++ b/sail_latex_riscv/valzpmpaddrmatchtype_of_bits8b4e245ce3d01f111a1f89404623ac98.tex @@ -0,0 +1 @@ +pmpAddrMatchType_of_bits : bits(2) -> PmpAddrMatchType \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpaddrmatchtype_of_num05d549dd7f3bf4d35f3c38ea6a015bf3.tex b/sail_latex_riscv/valzpmpaddrmatchtype_of_num05d549dd7f3bf4d35f3c38ea6a015bf3.tex new file mode 100644 index 00000000..b2c84e5e --- /dev/null +++ b/sail_latex_riscv/valzpmpaddrmatchtype_of_num05d549dd7f3bf4d35f3c38ea6a015bf3.tex @@ -0,0 +1 @@ +PmpAddrMatchType_of_num : forall ('e : Int), (0 <= 'e & 'e <= 3). int('e) -> PmpAddrMatchType \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpaddrmatchtype_to_bitsd16d593c276e8bc21809612105ac8913.tex b/sail_latex_riscv/valzpmpaddrmatchtype_to_bitsd16d593c276e8bc21809612105ac8913.tex new file mode 100644 index 00000000..ccb56d29 --- /dev/null +++ b/sail_latex_riscv/valzpmpaddrmatchtype_to_bitsd16d593c276e8bc21809612105ac8913.tex @@ -0,0 +1 @@ +pmpAddrMatchType_to_bits : PmpAddrMatchType -> bits(2) \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpaddrranged0e482997ef7d22fddc89c097e038f0d.tex b/sail_latex_riscv/valzpmpaddrranged0e482997ef7d22fddc89c097e038f0d.tex new file mode 100644 index 00000000..af4b0c8a --- /dev/null +++ b/sail_latex_riscv/valzpmpaddrranged0e482997ef7d22fddc89c097e038f0d.tex @@ -0,0 +1 @@ +pmpAddrRange : (Pmpcfg_ent, xlenbits, xlenbits) -> pmp_addr_range \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpcheck818accaacf804d4474fe874d5c97929a.tex b/sail_latex_riscv/valzpmpcheck818accaacf804d4474fe874d5c97929a.tex new file mode 100644 index 00000000..27bcaf78 --- /dev/null +++ b/sail_latex_riscv/valzpmpcheck818accaacf804d4474fe874d5c97929a.tex @@ -0,0 +1,2 @@ +pmpCheck : forall ('n : Int), 'n > 0. + (xlenbits, int('n), AccessType(ext_access_type), Privilege) -> option(ExceptionType) \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpcheckperms43a47caab37d2bebaa37cc41235e7387.tex b/sail_latex_riscv/valzpmpcheckperms43a47caab37d2bebaa37cc41235e7387.tex new file mode 100644 index 00000000..bd0fce7a --- /dev/null +++ b/sail_latex_riscv/valzpmpcheckperms43a47caab37d2bebaa37cc41235e7387.tex @@ -0,0 +1 @@ +pmpCheckPerms : (Pmpcfg_ent, AccessType(ext_access_type), Privilege) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpcheckrwx6a81da10e740c25fedddbe430f079b7d.tex b/sail_latex_riscv/valzpmpcheckrwx6a81da10e740c25fedddbe430f079b7d.tex new file mode 100644 index 00000000..a35c5bc2 --- /dev/null +++ b/sail_latex_riscv/valzpmpcheckrwx6a81da10e740c25fedddbe430f079b7d.tex @@ -0,0 +1 @@ +pmpCheckRWX : (Pmpcfg_ent, AccessType(ext_access_type)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzpmplocked32d6273cc49a9c7a22cf1a063f7a3d9b.tex b/sail_latex_riscv/valzpmplocked32d6273cc49a9c7a22cf1a063f7a3d9b.tex new file mode 100644 index 00000000..aa283f9a --- /dev/null +++ b/sail_latex_riscv/valzpmplocked32d6273cc49a9c7a22cf1a063f7a3d9b.tex @@ -0,0 +1 @@ +pmpLocked : Pmpcfg_ent -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpmatch_of_num271d71ea451fba2032d2e5ea441d9f49.tex b/sail_latex_riscv/valzpmpmatch_of_num271d71ea451fba2032d2e5ea441d9f49.tex new file mode 100644 index 00000000..67cc7b1e --- /dev/null +++ b/sail_latex_riscv/valzpmpmatch_of_num271d71ea451fba2032d2e5ea441d9f49.tex @@ -0,0 +1 @@ +pmpMatch_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> pmpMatch \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpmatchaddr4db797384cb60b665d5b05ce2f54ea2f.tex b/sail_latex_riscv/valzpmpmatchaddr4db797384cb60b665d5b05ce2f54ea2f.tex new file mode 100644 index 00000000..55e4acc4 --- /dev/null +++ b/sail_latex_riscv/valzpmpmatchaddr4db797384cb60b665d5b05ce2f54ea2f.tex @@ -0,0 +1 @@ +pmpMatchAddr : (xlenbits, xlenbits, pmp_addr_range) -> pmpAddrMatch \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpmatchentryb540666374b1cccee76fe8eb4dc7362f.tex b/sail_latex_riscv/valzpmpmatchentryb540666374b1cccee76fe8eb4dc7362f.tex new file mode 100644 index 00000000..39231349 --- /dev/null +++ b/sail_latex_riscv/valzpmpmatchentryb540666374b1cccee76fe8eb4dc7362f.tex @@ -0,0 +1 @@ +pmpMatchEntry : (xlenbits, xlenbits, AccessType(ext_access_type), Privilege, Pmpcfg_ent, xlenbits, xlenbits) -> pmpMatch \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpreadcfgreg4f212865b80d1cf6286c5525466852bb.tex b/sail_latex_riscv/valzpmpreadcfgreg4f212865b80d1cf6286c5525466852bb.tex new file mode 100644 index 00000000..dcfec370 --- /dev/null +++ b/sail_latex_riscv/valzpmpreadcfgreg4f212865b80d1cf6286c5525466852bb.tex @@ -0,0 +1 @@ +pmpReadCfgReg : forall ('n : Int), (0 <= 'n & 'n < 4). int('n) -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzpmptorlockedc6616187f2e2905a9fb7c4ac60d52920.tex b/sail_latex_riscv/valzpmptorlockedc6616187f2e2905a9fb7c4ac60d52920.tex new file mode 100644 index 00000000..0c809110 --- /dev/null +++ b/sail_latex_riscv/valzpmptorlockedc6616187f2e2905a9fb7c4ac60d52920.tex @@ -0,0 +1 @@ +pmpTORLocked : Pmpcfg_ent -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpwriteaddr35a89b2e3be238e40992648bdf6c2e4c.tex b/sail_latex_riscv/valzpmpwriteaddr35a89b2e3be238e40992648bdf6c2e4c.tex new file mode 100644 index 00000000..1c5636b4 --- /dev/null +++ b/sail_latex_riscv/valzpmpwriteaddr35a89b2e3be238e40992648bdf6c2e4c.tex @@ -0,0 +1 @@ +pmpWriteAddr : (bool, bool, xlenbits, xlenbits) -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpwritecfg2cde3ea402426e32bb50a4bc91e0c983.tex b/sail_latex_riscv/valzpmpwritecfg2cde3ea402426e32bb50a4bc91e0c983.tex new file mode 100644 index 00000000..d6441067 --- /dev/null +++ b/sail_latex_riscv/valzpmpwritecfg2cde3ea402426e32bb50a4bc91e0c983.tex @@ -0,0 +1 @@ +pmpWriteCfg : (Pmpcfg_ent, bits(8)) -> Pmpcfg_ent \ No newline at end of file diff --git a/sail_latex_riscv/valzpmpwritecfgregf08572520295a822ab88e05e223953db.tex b/sail_latex_riscv/valzpmpwritecfgregf08572520295a822ab88e05e223953db.tex new file mode 100644 index 00000000..b9b8d253 --- /dev/null +++ b/sail_latex_riscv/valzpmpwritecfgregf08572520295a822ab88e05e223953db.tex @@ -0,0 +1 @@ +pmpWriteCfgReg : forall ('n : Int), (0 <= 'n & 'n < 4). (int('n), xlenbits) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzpow2e971ce2f9ebb899590551317286dfd1b.tex b/sail_latex_riscv/valzpow2e971ce2f9ebb899590551317286dfd1b.tex new file mode 100644 index 00000000..1e96e24d --- /dev/null +++ b/sail_latex_riscv/valzpow2e971ce2f9ebb899590551317286dfd1b.tex @@ -0,0 +1 @@ +pow2 : forall ('n : Int). int('n) -> int(2 ^ 'n) \ No newline at end of file diff --git a/sail_latex_riscv/valzprepare_trap_vector90a104f40adfa987d74a613f4061790f.tex b/sail_latex_riscv/valzprepare_trap_vector90a104f40adfa987d74a613f4061790f.tex new file mode 100644 index 00000000..674b176b --- /dev/null +++ b/sail_latex_riscv/valzprepare_trap_vector90a104f40adfa987d74a613f4061790f.tex @@ -0,0 +1 @@ +prepare_trap_vector : (Privilege, Mcause) -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzprepare_xret_target77691a306ebd6df5d988335f19693ba0.tex b/sail_latex_riscv/valzprepare_xret_target77691a306ebd6df5d988335f19693ba0.tex new file mode 100644 index 00000000..7c13adc1 --- /dev/null +++ b/sail_latex_riscv/valzprepare_xret_target77691a306ebd6df5d988335f19693ba0.tex @@ -0,0 +1 @@ +prepare_xret_target : Privilege -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzprerr_bits932899725108ebe483d3226f250f2b92.tex b/sail_latex_riscv/valzprerr_bits932899725108ebe483d3226f250f2b92.tex new file mode 100644 index 00000000..44097a2a --- /dev/null +++ b/sail_latex_riscv/valzprerr_bits932899725108ebe483d3226f250f2b92.tex @@ -0,0 +1 @@ +prerr_bits : forall ('n : Int). (string, bits('n)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzprerr_endline73ce57fcf6e847727670556577cb2de0.tex b/sail_latex_riscv/valzprerr_endline73ce57fcf6e847727670556577cb2de0.tex new file mode 100644 index 00000000..bfaafad2 --- /dev/null +++ b/sail_latex_riscv/valzprerr_endline73ce57fcf6e847727670556577cb2de0.tex @@ -0,0 +1 @@ +prerr_endline : string -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzprerr_int00b48f715fbb32df5901801dff63b643.tex b/sail_latex_riscv/valzprerr_int00b48f715fbb32df5901801dff63b643.tex new file mode 100644 index 00000000..0249ddb4 --- /dev/null +++ b/sail_latex_riscv/valzprerr_int00b48f715fbb32df5901801dff63b643.tex @@ -0,0 +1 @@ +prerr_int : (string, int) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzprint_bits30cf225474fbf3e575d7aa83aa309559.tex b/sail_latex_riscv/valzprint_bits30cf225474fbf3e575d7aa83aa309559.tex new file mode 100644 index 00000000..e2cebf75 --- /dev/null +++ b/sail_latex_riscv/valzprint_bits30cf225474fbf3e575d7aa83aa309559.tex @@ -0,0 +1 @@ +print_bits : forall ('n : Int). (string, bits('n)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzprint_endline03a43e2779561cb054d0761733c27e9b.tex b/sail_latex_riscv/valzprint_endline03a43e2779561cb054d0761733c27e9b.tex new file mode 100644 index 00000000..5421e009 --- /dev/null +++ b/sail_latex_riscv/valzprint_endline03a43e2779561cb054d0761733c27e9b.tex @@ -0,0 +1 @@ +print_endline : string -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzprint_insn34adb9871c343ddeeb08d9e768ad4c92.tex b/sail_latex_riscv/valzprint_insn34adb9871c343ddeeb08d9e768ad4c92.tex new file mode 100644 index 00000000..73e3cccd --- /dev/null +++ b/sail_latex_riscv/valzprint_insn34adb9871c343ddeeb08d9e768ad4c92.tex @@ -0,0 +1 @@ +print_insn : ast -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzprint_instr59f46726e427ed18b9d5d81c8247a576.tex b/sail_latex_riscv/valzprint_instr59f46726e427ed18b9d5d81c8247a576.tex new file mode 100644 index 00000000..75ed268d --- /dev/null +++ b/sail_latex_riscv/valzprint_instr59f46726e427ed18b9d5d81c8247a576.tex @@ -0,0 +1 @@ +print_instr : string -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzprint_intfb625bfb7a4021903513aeb4396bd878.tex b/sail_latex_riscv/valzprint_intfb625bfb7a4021903513aeb4396bd878.tex new file mode 100644 index 00000000..3d5a2a33 --- /dev/null +++ b/sail_latex_riscv/valzprint_intfb625bfb7a4021903513aeb4396bd878.tex @@ -0,0 +1 @@ +print_int : (string, int) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzprint_memb6cd54f21a6e2c7a036f86473d516264.tex b/sail_latex_riscv/valzprint_memb6cd54f21a6e2c7a036f86473d516264.tex new file mode 100644 index 00000000..c17477b6 --- /dev/null +++ b/sail_latex_riscv/valzprint_memb6cd54f21a6e2c7a036f86473d516264.tex @@ -0,0 +1 @@ +print_mem : string -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzprint_platform894b0df15559ad78744140d27df61719.tex b/sail_latex_riscv/valzprint_platform894b0df15559ad78744140d27df61719.tex new file mode 100644 index 00000000..684a5aef --- /dev/null +++ b/sail_latex_riscv/valzprint_platform894b0df15559ad78744140d27df61719.tex @@ -0,0 +1 @@ +print_platform : string -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzprint_reg1e86a2863e701cf481babd6538033417.tex b/sail_latex_riscv/valzprint_reg1e86a2863e701cf481babd6538033417.tex new file mode 100644 index 00000000..a373073a --- /dev/null +++ b/sail_latex_riscv/valzprint_reg1e86a2863e701cf481babd6538033417.tex @@ -0,0 +1 @@ +print_reg : string -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzprint_string4b7e44eb021c25878c749374ea5657f7.tex b/sail_latex_riscv/valzprint_string4b7e44eb021c25878c749374ea5657f7.tex new file mode 100644 index 00000000..8ebe4d7e --- /dev/null +++ b/sail_latex_riscv/valzprint_string4b7e44eb021c25878c749374ea5657f7.tex @@ -0,0 +1 @@ +print_string : (string, string) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzprintc9b8c9c569def1934362480628956c85.tex b/sail_latex_riscv/valzprintc9b8c9c569def1934362480628956c85.tex new file mode 100644 index 00000000..f9aea53c --- /dev/null +++ b/sail_latex_riscv/valzprintc9b8c9c569def1934362480628956c85.tex @@ -0,0 +1 @@ +print : string -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzprivilege_of_num84ee3b92a1b0c896120347634e28615d.tex b/sail_latex_riscv/valzprivilege_of_num84ee3b92a1b0c896120347634e28615d.tex new file mode 100644 index 00000000..9c103f72 --- /dev/null +++ b/sail_latex_riscv/valzprivilege_of_num84ee3b92a1b0c896120347634e28615d.tex @@ -0,0 +1 @@ +Privilege_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> Privilege \ No newline at end of file diff --git a/sail_latex_riscv/valzprivlevel_of_bitsf8754d7aa9d9aeada7d193ecf64e148c.tex b/sail_latex_riscv/valzprivlevel_of_bitsf8754d7aa9d9aeada7d193ecf64e148c.tex new file mode 100644 index 00000000..6920cd05 --- /dev/null +++ b/sail_latex_riscv/valzprivlevel_of_bitsf8754d7aa9d9aeada7d193ecf64e148c.tex @@ -0,0 +1 @@ +privLevel_of_bits : priv_level -> Privilege \ No newline at end of file diff --git a/sail_latex_riscv/valzprivlevel_to_bits4b6f72dec94db401093759e81957be6b.tex b/sail_latex_riscv/valzprivlevel_to_bits4b6f72dec94db401093759e81957be6b.tex new file mode 100644 index 00000000..b182fe3e --- /dev/null +++ b/sail_latex_riscv/valzprivlevel_to_bits4b6f72dec94db401093759e81957be6b.tex @@ -0,0 +1 @@ +privLevel_to_bits : Privilege -> priv_level \ No newline at end of file diff --git a/sail_latex_riscv/valzprivlevel_to_str130b731da9dd60ea89c77efcbbe0d598.tex b/sail_latex_riscv/valzprivlevel_to_str130b731da9dd60ea89c77efcbbe0d598.tex new file mode 100644 index 00000000..66247bee --- /dev/null +++ b/sail_latex_riscv/valzprivlevel_to_str130b731da9dd60ea89c77efcbbe0d598.tex @@ -0,0 +1 @@ +privLevel_to_str : Privilege -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzprocess_fload322b1b2657ee5e1571b2af7b0d3a6631b7.tex b/sail_latex_riscv/valzprocess_fload322b1b2657ee5e1571b2af7b0d3a6631b7.tex new file mode 100644 index 00000000..dc0a9c2e --- /dev/null +++ b/sail_latex_riscv/valzprocess_fload322b1b2657ee5e1571b2af7b0d3a6631b7.tex @@ -0,0 +1 @@ +process_fload32 : (regidx, xlenbits, MemoryOpResult(bits(32))) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzprocess_fload64aaf81fa4052296eb2993198993f6472c.tex b/sail_latex_riscv/valzprocess_fload64aaf81fa4052296eb2993198993f6472c.tex new file mode 100644 index 00000000..7be1745a --- /dev/null +++ b/sail_latex_riscv/valzprocess_fload64aaf81fa4052296eb2993198993f6472c.tex @@ -0,0 +1 @@ +process_fload64 : (regidx, xlenbits, MemoryOpResult(bits(64))) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzprocess_fstoree9440c013cfdcc23312bc61d5762f1d1.tex b/sail_latex_riscv/valzprocess_fstoree9440c013cfdcc23312bc61d5762f1d1.tex new file mode 100644 index 00000000..8f6ba432 --- /dev/null +++ b/sail_latex_riscv/valzprocess_fstoree9440c013cfdcc23312bc61d5762f1d1.tex @@ -0,0 +1 @@ +process_fstore : (xlenbits, MemoryOpResult(bool)) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzprocess_load7d9288eb90dd41d1aa3c47eda679c483.tex b/sail_latex_riscv/valzprocess_load7d9288eb90dd41d1aa3c47eda679c483.tex new file mode 100644 index 00000000..d56e5b89 --- /dev/null +++ b/sail_latex_riscv/valzprocess_load7d9288eb90dd41d1aa3c47eda679c483.tex @@ -0,0 +1,2 @@ +process_load : forall ('n : Int), (0 < 'n & 'n <= xlen_bytes). + (regidx, xlenbits, MemoryOpResult(bits(8 * 'n)), bool) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzprocess_loadres3acadfd67bd540642036cf41405a27c0.tex b/sail_latex_riscv/valzprocess_loadres3acadfd67bd540642036cf41405a27c0.tex new file mode 100644 index 00000000..a9a5c2bb --- /dev/null +++ b/sail_latex_riscv/valzprocess_loadres3acadfd67bd540642036cf41405a27c0.tex @@ -0,0 +1,2 @@ +process_loadres : forall ('n : Int), (0 < 'n & 'n <= xlen_bytes). + (regidx, xlenbits, MemoryOpResult(bits(8 * 'n)), bool) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzprocesspendingf31f33d163f06483630c9da88eafecaa.tex b/sail_latex_riscv/valzprocesspendingf31f33d163f06483630c9da88eafecaa.tex new file mode 100644 index 00000000..f9b29368 --- /dev/null +++ b/sail_latex_riscv/valzprocesspendingf31f33d163f06483630c9da88eafecaa.tex @@ -0,0 +1 @@ +processPending : (Minterrupts, Minterrupts, xlenbits, bool) -> interrupt_set \ No newline at end of file diff --git a/sail_latex_riscv/valzptw_error_to_stra1d14633b5815718af0734f3fe6896fb.tex b/sail_latex_riscv/valzptw_error_to_stra1d14633b5815718af0734f3fe6896fb.tex new file mode 100644 index 00000000..71ab424a --- /dev/null +++ b/sail_latex_riscv/valzptw_error_to_stra1d14633b5815718af0734f3fe6896fb.tex @@ -0,0 +1 @@ +ptw_error_to_str : PTW_Error -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzquot_round_zzeroa8d9d278dc91a14956dfe19d01766403.tex b/sail_latex_riscv/valzquot_round_zzeroa8d9d278dc91a14956dfe19d01766403.tex new file mode 100644 index 00000000..ac74d114 --- /dev/null +++ b/sail_latex_riscv/valzquot_round_zzeroa8d9d278dc91a14956dfe19d01766403.tex @@ -0,0 +1 @@ +quot_round_zero : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_riscv/valzrc_bits18d7e232c147203cdc9c7cd0ffbe7ec0.tex b/sail_latex_riscv/valzrc_bits18d7e232c147203cdc9c7cd0ffbe7ec0.tex new file mode 100644 index 00000000..7c5891d0 --- /dev/null +++ b/sail_latex_riscv/valzrc_bits18d7e232c147203cdc9c7cd0ffbe7ec0.tex @@ -0,0 +1 @@ +rC_bits : bits(5) -> regtype \ No newline at end of file diff --git a/sail_latex_riscv/valzrcda9d82cd736deb89a37d9ca089373805.tex b/sail_latex_riscv/valzrcda9d82cd736deb89a37d9ca089373805.tex new file mode 100644 index 00000000..d5c21ddf --- /dev/null +++ b/sail_latex_riscv/valzrcda9d82cd736deb89a37d9ca089373805.tex @@ -0,0 +1 @@ +rC : forall ('n : Int), (0 <= 'n & 'n < 32). regno('n) -> regtype \ No newline at end of file diff --git a/sail_latex_riscv/valzread_kind_of_flagsbdfde0c548450764d5ed916ca1cb98ac.tex b/sail_latex_riscv/valzread_kind_of_flagsbdfde0c548450764d5ed916ca1cb98ac.tex new file mode 100644 index 00000000..2e5995c6 --- /dev/null +++ b/sail_latex_riscv/valzread_kind_of_flagsbdfde0c548450764d5ed916ca1cb98ac.tex @@ -0,0 +1 @@ +read_kind_of_flags : (bool, bool, bool) -> option(read_kind) \ No newline at end of file diff --git a/sail_latex_riscv/valzread_kind_of_numd8fea9b1331732e205bdd70279e0ba47.tex b/sail_latex_riscv/valzread_kind_of_numd8fea9b1331732e205bdd70279e0ba47.tex new file mode 100644 index 00000000..2f79d8e5 --- /dev/null +++ b/sail_latex_riscv/valzread_kind_of_numd8fea9b1331732e205bdd70279e0ba47.tex @@ -0,0 +1 @@ +read_kind_of_num : forall ('e : Int), (0 <= 'e & 'e <= 11). int('e) -> read_kind \ No newline at end of file diff --git a/sail_latex_riscv/valzread_ram020d2ffaf84d982d4588177095c24b8e.tex b/sail_latex_riscv/valzread_ram020d2ffaf84d982d4588177095c24b8e.tex new file mode 100644 index 00000000..b5c7ec15 --- /dev/null +++ b/sail_latex_riscv/valzread_ram020d2ffaf84d982d4588177095c24b8e.tex @@ -0,0 +1,2 @@ +read_ram : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (read_kind, xlenbits, int('n), bool) -> (bits(8 * 'n), mem_meta) \ No newline at end of file diff --git a/sail_latex_riscv/valzreadcsr1a9ed1f2dac4690038fbe34a4617edca.tex b/sail_latex_riscv/valzreadcsr1a9ed1f2dac4690038fbe34a4617edca.tex new file mode 100644 index 00000000..16986ed9 --- /dev/null +++ b/sail_latex_riscv/valzreadcsr1a9ed1f2dac4690038fbe34a4617edca.tex @@ -0,0 +1 @@ +readCSR : csreg -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzreg_deref8bd1d78c61978d7074c7e0e5195e4bf7.tex b/sail_latex_riscv/valzreg_deref8bd1d78c61978d7074c7e0e5195e4bf7.tex new file mode 100644 index 00000000..01cc73eb --- /dev/null +++ b/sail_latex_riscv/valzreg_deref8bd1d78c61978d7074c7e0e5195e4bf7.tex @@ -0,0 +1 @@ +reg_deref : forall ('a : Type). register('a) -> 'a \ No newline at end of file diff --git a/sail_latex_riscv/valzreg_name_abi8c36e923dc671675cb54fb0175878a3f.tex b/sail_latex_riscv/valzreg_name_abi8c36e923dc671675cb54fb0175878a3f.tex new file mode 100644 index 00000000..1152160a --- /dev/null +++ b/sail_latex_riscv/valzreg_name_abi8c36e923dc671675cb54fb0175878a3f.tex @@ -0,0 +1 @@ +reg_name_abi : regidx -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzreg_namea3a934e14215c11bd841e5d2fb4f53e0.tex b/sail_latex_riscv/valzreg_namea3a934e14215c11bd841e5d2fb4f53e0.tex new file mode 100644 index 00000000..cd373442 --- /dev/null +++ b/sail_latex_riscv/valzreg_namea3a934e14215c11bd841e5d2fb4f53e0.tex @@ -0,0 +1 @@ +reg_name : bits(5) <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzregidx_to_regno46c7ee8e863ba355f36bf094aa680714.tex b/sail_latex_riscv/valzregidx_to_regno46c7ee8e863ba355f36bf094aa680714.tex new file mode 100644 index 00000000..ce851262 --- /dev/null +++ b/sail_latex_riscv/valzregidx_to_regno46c7ee8e863ba355f36bf094aa680714.tex @@ -0,0 +1 @@ +regidx_to_regno : bits(5) -> {'n, (0 <= 'n & 'n < 32). regno('n)} \ No newline at end of file diff --git a/sail_latex_riscv/valzregstrf07d744c662238e6879fb1aee407788d.tex b/sail_latex_riscv/valzregstrf07d744c662238e6879fb1aee407788d.tex new file mode 100644 index 00000000..7c5fcb81 --- /dev/null +++ b/sail_latex_riscv/valzregstrf07d744c662238e6879fb1aee407788d.tex @@ -0,0 +1 @@ +RegStr : Capability -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzregval_from_rega072b7983f1f9ac4a9021e76a911b9c9.tex b/sail_latex_riscv/valzregval_from_rega072b7983f1f9ac4a9021e76a911b9c9.tex new file mode 100644 index 00000000..304fa4c2 --- /dev/null +++ b/sail_latex_riscv/valzregval_from_rega072b7983f1f9ac4a9021e76a911b9c9.tex @@ -0,0 +1 @@ +regval_from_reg : regtype -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzregval_into_reg03a5bdeabb3e6169090e6ed21f1a84cb.tex b/sail_latex_riscv/valzregval_into_reg03a5bdeabb3e6169090e6ed21f1a84cb.tex new file mode 100644 index 00000000..b0f3231d --- /dev/null +++ b/sail_latex_riscv/valzregval_into_reg03a5bdeabb3e6169090e6ed21f1a84cb.tex @@ -0,0 +1 @@ +regval_into_reg : xlenbits -> regtype \ No newline at end of file diff --git a/sail_latex_riscv/valzrem_round_zzero90d115d6c3e756b94f7766d1b76fbb83.tex b/sail_latex_riscv/valzrem_round_zzero90d115d6c3e756b94f7766d1b76fbb83.tex new file mode 100644 index 00000000..1ff854e8 --- /dev/null +++ b/sail_latex_riscv/valzrem_round_zzero90d115d6c3e756b94f7766d1b76fbb83.tex @@ -0,0 +1 @@ +rem_round_zero : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_riscv/valzreplicate_bitsb29bdab6bb9437712accf2dc81ea3d3e.tex b/sail_latex_riscv/valzreplicate_bitsb29bdab6bb9437712accf2dc81ea3d3e.tex new file mode 100644 index 00000000..7ec5b77d --- /dev/null +++ b/sail_latex_riscv/valzreplicate_bitsb29bdab6bb9437712accf2dc81ea3d3e.tex @@ -0,0 +1 @@ +replicate_bits : forall ('n 'm : Int). (bits('n), int('m)) -> bits('n * 'm) \ No newline at end of file diff --git a/sail_latex_riscv/valzretire_instructionc9e2e6b25fd8f4e5a96cd82a0dd2a675.tex b/sail_latex_riscv/valzretire_instructionc9e2e6b25fd8f4e5a96cd82a0dd2a675.tex new file mode 100644 index 00000000..a93b1260 --- /dev/null +++ b/sail_latex_riscv/valzretire_instructionc9e2e6b25fd8f4e5a96cd82a0dd2a675.tex @@ -0,0 +1 @@ +retire_instruction : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzretired_of_num68ab3748534f762d814246f11fcf7c77.tex b/sail_latex_riscv/valzretired_of_num68ab3748534f762d814246f11fcf7c77.tex new file mode 100644 index 00000000..7725fb7d --- /dev/null +++ b/sail_latex_riscv/valzretired_of_num68ab3748534f762d814246f11fcf7c77.tex @@ -0,0 +1 @@ +Retired_of_num : forall ('e : Int), (0 <= 'e & 'e <= 1). int('e) -> Retired \ No newline at end of file diff --git a/sail_latex_riscv/valzrf_bits63ac239a90c8d4bdc4ca1b8375c08531.tex b/sail_latex_riscv/valzrf_bits63ac239a90c8d4bdc4ca1b8375c08531.tex new file mode 100644 index 00000000..cef561cd --- /dev/null +++ b/sail_latex_riscv/valzrf_bits63ac239a90c8d4bdc4ca1b8375c08531.tex @@ -0,0 +1 @@ +rF_bits : bits(5) -> flenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzrff2ed1bbacd3ac737af7186c6d8884885.tex b/sail_latex_riscv/valzrff2ed1bbacd3ac737af7186c6d8884885.tex new file mode 100644 index 00000000..53ea625a --- /dev/null +++ b/sail_latex_riscv/valzrff2ed1bbacd3ac737af7186c6d8884885.tex @@ -0,0 +1 @@ +rF : forall ('n : Int), (0 <= 'n & 'n < 32). regno('n) -> flenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32add558e9569237c3f82255e78eba6e4d963.tex b/sail_latex_riscv/valzriscv_f32add558e9569237c3f82255e78eba6e4d963.tex new file mode 100644 index 00000000..1e6d5a9f --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32add558e9569237c3f82255e78eba6e4d963.tex @@ -0,0 +1 @@ +riscv_f32Add : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32div86cc53dd9bb61e6f44380c708e0673ca.tex b/sail_latex_riscv/valzriscv_f32div86cc53dd9bb61e6f44380c708e0673ca.tex new file mode 100644 index 00000000..b6d78047 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32div86cc53dd9bb61e6f44380c708e0673ca.tex @@ -0,0 +1 @@ +riscv_f32Div : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32eqbb5f45f4706cd2893dcaf9d3d15d7b11.tex b/sail_latex_riscv/valzriscv_f32eqbb5f45f4706cd2893dcaf9d3d15d7b11.tex new file mode 100644 index 00000000..26aa10a8 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32eqbb5f45f4706cd2893dcaf9d3d15d7b11.tex @@ -0,0 +1 @@ +riscv_f32Eq : (bits_S, bits_S) -> (bits_fflags, bits_WU) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32le5580a4448a4b6b5ef89a7a80b6f5e23a.tex b/sail_latex_riscv/valzriscv_f32le5580a4448a4b6b5ef89a7a80b6f5e23a.tex new file mode 100644 index 00000000..b94c5f1a --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32le5580a4448a4b6b5ef89a7a80b6f5e23a.tex @@ -0,0 +1 @@ +riscv_f32Le : (bits_S, bits_S) -> (bits_fflags, bits_WU) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32lt4e30f0abd945d0950f5c75c3397e58b8.tex b/sail_latex_riscv/valzriscv_f32lt4e30f0abd945d0950f5c75c3397e58b8.tex new file mode 100644 index 00000000..86c2e075 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32lt4e30f0abd945d0950f5c75c3397e58b8.tex @@ -0,0 +1 @@ +riscv_f32Lt : (bits_S, bits_S) -> (bits_fflags, bits_WU) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32muladdc6b7d5aa910c0cf67022d34e7a745cd8.tex b/sail_latex_riscv/valzriscv_f32muladdc6b7d5aa910c0cf67022d34e7a745cd8.tex new file mode 100644 index 00000000..32a1d1b5 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32muladdc6b7d5aa910c0cf67022d34e7a745cd8.tex @@ -0,0 +1 @@ +riscv_f32MulAdd : (bits_rm, bits_S, bits_S, bits_S) -> (bits_fflags, bits_S) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32mulc9ec954a141b4f26110e9e3c2b42b73c.tex b/sail_latex_riscv/valzriscv_f32mulc9ec954a141b4f26110e9e3c2b42b73c.tex new file mode 100644 index 00000000..36de8fe0 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32mulc9ec954a141b4f26110e9e3c2b42b73c.tex @@ -0,0 +1 @@ +riscv_f32Mul : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32sqrtd0c4078227e28f52a7984b6a7f89ce8a.tex b/sail_latex_riscv/valzriscv_f32sqrtd0c4078227e28f52a7984b6a7f89ce8a.tex new file mode 100644 index 00000000..1cc413c5 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32sqrtd0c4078227e28f52a7984b6a7f89ce8a.tex @@ -0,0 +1 @@ +riscv_f32Sqrt : (bits_rm, bits_S) -> (bits_fflags, bits_S) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32sub247ea008998dd84d9a3c22db11127bea.tex b/sail_latex_riscv/valzriscv_f32sub247ea008998dd84d9a3c22db11127bea.tex new file mode 100644 index 00000000..bb563c26 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32sub247ea008998dd84d9a3c22db11127bea.tex @@ -0,0 +1 @@ +riscv_f32Sub : (bits_rm, bits_S, bits_S) -> (bits_fflags, bits_S) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32tof6463cfa807ac39aea5d45f7cb4ee2d9248.tex b/sail_latex_riscv/valzriscv_f32tof6463cfa807ac39aea5d45f7cb4ee2d9248.tex new file mode 100644 index 00000000..9c338dd8 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32tof6463cfa807ac39aea5d45f7cb4ee2d9248.tex @@ -0,0 +1 @@ +riscv_f32ToF64 : (bits_rm, bits_S) -> (bits_fflags, bits_D) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32toi32b5d471852e14b8b79d2ad8fd065ac832.tex b/sail_latex_riscv/valzriscv_f32toi32b5d471852e14b8b79d2ad8fd065ac832.tex new file mode 100644 index 00000000..5339d260 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32toi32b5d471852e14b8b79d2ad8fd065ac832.tex @@ -0,0 +1 @@ +riscv_f32ToI32 : (bits_rm, bits_S) -> (bits_fflags, bits_W) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32toi640208fd5f6c45fde93d3e7c63a2825d81.tex b/sail_latex_riscv/valzriscv_f32toi640208fd5f6c45fde93d3e7c63a2825d81.tex new file mode 100644 index 00000000..19700b58 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32toi640208fd5f6c45fde93d3e7c63a2825d81.tex @@ -0,0 +1 @@ +riscv_f32ToI64 : (bits_rm, bits_S) -> (bits_fflags, bits_L) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32toui329abf292f8a5b1458fd639f0b62a9b052.tex b/sail_latex_riscv/valzriscv_f32toui329abf292f8a5b1458fd639f0b62a9b052.tex new file mode 100644 index 00000000..c1c4afcc --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32toui329abf292f8a5b1458fd639f0b62a9b052.tex @@ -0,0 +1 @@ +riscv_f32ToUi32 : (bits_rm, bits_S) -> (bits_fflags, bits_WU) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f32toui6423479b6a7ca0f54a5c926da7d7620403.tex b/sail_latex_riscv/valzriscv_f32toui6423479b6a7ca0f54a5c926da7d7620403.tex new file mode 100644 index 00000000..d62256c5 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f32toui6423479b6a7ca0f54a5c926da7d7620403.tex @@ -0,0 +1 @@ +riscv_f32ToUi64 : (bits_rm, bits_S) -> (bits_fflags, bits_LU) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64add33e6272fa354fe4e7b1963d6545bc4f7.tex b/sail_latex_riscv/valzriscv_f64add33e6272fa354fe4e7b1963d6545bc4f7.tex new file mode 100644 index 00000000..4328d358 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64add33e6272fa354fe4e7b1963d6545bc4f7.tex @@ -0,0 +1 @@ +riscv_f64Add : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64divecc62207bb7fa437fcf66a19597ada83.tex b/sail_latex_riscv/valzriscv_f64divecc62207bb7fa437fcf66a19597ada83.tex new file mode 100644 index 00000000..1f6f0a6e --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64divecc62207bb7fa437fcf66a19597ada83.tex @@ -0,0 +1 @@ +riscv_f64Div : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64eq911a3686fab30a7dbcecd0d21d7bc788.tex b/sail_latex_riscv/valzriscv_f64eq911a3686fab30a7dbcecd0d21d7bc788.tex new file mode 100644 index 00000000..a21ed3e2 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64eq911a3686fab30a7dbcecd0d21d7bc788.tex @@ -0,0 +1 @@ +riscv_f64Eq : (bits_D, bits_D) -> (bits_fflags, bits_LU) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64leedff2d39af8855d31503064db9e49593.tex b/sail_latex_riscv/valzriscv_f64leedff2d39af8855d31503064db9e49593.tex new file mode 100644 index 00000000..c8f765ca --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64leedff2d39af8855d31503064db9e49593.tex @@ -0,0 +1 @@ +riscv_f64Le : (bits_D, bits_D) -> (bits_fflags, bits_LU) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64lt7fe1cae2d039f2771557eafe4cff0d62.tex b/sail_latex_riscv/valzriscv_f64lt7fe1cae2d039f2771557eafe4cff0d62.tex new file mode 100644 index 00000000..3a88d094 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64lt7fe1cae2d039f2771557eafe4cff0d62.tex @@ -0,0 +1 @@ +riscv_f64Lt : (bits_D, bits_D) -> (bits_fflags, bits_LU) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64mul1bf597fee8433219c830072b7c0b998e.tex b/sail_latex_riscv/valzriscv_f64mul1bf597fee8433219c830072b7c0b998e.tex new file mode 100644 index 00000000..c6633c3a --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64mul1bf597fee8433219c830072b7c0b998e.tex @@ -0,0 +1 @@ +riscv_f64Mul : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64muladdf20eb35780f2858aa3087b34aba2250a.tex b/sail_latex_riscv/valzriscv_f64muladdf20eb35780f2858aa3087b34aba2250a.tex new file mode 100644 index 00000000..7c2e387d --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64muladdf20eb35780f2858aa3087b34aba2250a.tex @@ -0,0 +1 @@ +riscv_f64MulAdd : (bits_rm, bits_D, bits_D, bits_D) -> (bits_fflags, bits_D) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64sqrta506b6089ecf799deb21b124eaf60f0c.tex b/sail_latex_riscv/valzriscv_f64sqrta506b6089ecf799deb21b124eaf60f0c.tex new file mode 100644 index 00000000..051e9ecd --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64sqrta506b6089ecf799deb21b124eaf60f0c.tex @@ -0,0 +1 @@ +riscv_f64Sqrt : (bits_rm, bits_D) -> (bits_fflags, bits_D) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64sub64a17c7e3b243ed3af4bc99790d41a9f.tex b/sail_latex_riscv/valzriscv_f64sub64a17c7e3b243ed3af4bc99790d41a9f.tex new file mode 100644 index 00000000..0912229a --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64sub64a17c7e3b243ed3af4bc99790d41a9f.tex @@ -0,0 +1 @@ +riscv_f64Sub : (bits_rm, bits_D, bits_D) -> (bits_fflags, bits_D) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64tof326b35917fadbed27b5d3cecd2f8762d01.tex b/sail_latex_riscv/valzriscv_f64tof326b35917fadbed27b5d3cecd2f8762d01.tex new file mode 100644 index 00000000..4a0ede3b --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64tof326b35917fadbed27b5d3cecd2f8762d01.tex @@ -0,0 +1 @@ +riscv_f64ToF32 : (bits_rm, bits_D) -> (bits_fflags, bits_S) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64toi32390e064989835e074118b56d834e6d48.tex b/sail_latex_riscv/valzriscv_f64toi32390e064989835e074118b56d834e6d48.tex new file mode 100644 index 00000000..2be1e6d7 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64toi32390e064989835e074118b56d834e6d48.tex @@ -0,0 +1 @@ +riscv_f64ToI32 : (bits_rm, bits_D) -> (bits_fflags, bits_W) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64toi64b279b582ab789b7d76bd4628cf864db9.tex b/sail_latex_riscv/valzriscv_f64toi64b279b582ab789b7d76bd4628cf864db9.tex new file mode 100644 index 00000000..2d03f8c7 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64toi64b279b582ab789b7d76bd4628cf864db9.tex @@ -0,0 +1 @@ +riscv_f64ToI64 : (bits_rm, bits_D) -> (bits_fflags, bits_L) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64toui32df8698a76aef244e4d021f6db07ed8aa.tex b/sail_latex_riscv/valzriscv_f64toui32df8698a76aef244e4d021f6db07ed8aa.tex new file mode 100644 index 00000000..710de4fc --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64toui32df8698a76aef244e4d021f6db07ed8aa.tex @@ -0,0 +1 @@ +riscv_f64ToUi32 : (bits_rm, bits_D) -> (bits_fflags, bits_WU) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_f64toui64a8c06df736f513b3e5ec73bfb9385733.tex b/sail_latex_riscv/valzriscv_f64toui64a8c06df736f513b3e5ec73bfb9385733.tex new file mode 100644 index 00000000..3f629063 --- /dev/null +++ b/sail_latex_riscv/valzriscv_f64toui64a8c06df736f513b3e5ec73bfb9385733.tex @@ -0,0 +1 @@ +riscv_f64ToUi64 : (bits_rm, bits_D) -> (bits_fflags, bits_LU) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_i32tof32262d900b5276fc61cfada0a2c080dd00.tex b/sail_latex_riscv/valzriscv_i32tof32262d900b5276fc61cfada0a2c080dd00.tex new file mode 100644 index 00000000..20d2ab1f --- /dev/null +++ b/sail_latex_riscv/valzriscv_i32tof32262d900b5276fc61cfada0a2c080dd00.tex @@ -0,0 +1 @@ +riscv_i32ToF32 : (bits_rm, bits_W) -> (bits_fflags, bits_S) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_i32tof64e97e000de9456cb796f52f30b64c9715.tex b/sail_latex_riscv/valzriscv_i32tof64e97e000de9456cb796f52f30b64c9715.tex new file mode 100644 index 00000000..559dff46 --- /dev/null +++ b/sail_latex_riscv/valzriscv_i32tof64e97e000de9456cb796f52f30b64c9715.tex @@ -0,0 +1 @@ +riscv_i32ToF64 : (bits_rm, bits_W) -> (bits_fflags, bits_D) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_i64tof329ea93669bfe183b3595b128f97eb0d64.tex b/sail_latex_riscv/valzriscv_i64tof329ea93669bfe183b3595b128f97eb0d64.tex new file mode 100644 index 00000000..2975ef19 --- /dev/null +++ b/sail_latex_riscv/valzriscv_i64tof329ea93669bfe183b3595b128f97eb0d64.tex @@ -0,0 +1 @@ +riscv_i64ToF32 : (bits_rm, bits_L) -> (bits_fflags, bits_S) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_i64tof645552b730328b5e488a5469c4d60ba48e.tex b/sail_latex_riscv/valzriscv_i64tof645552b730328b5e488a5469c4d60ba48e.tex new file mode 100644 index 00000000..7c15f0c0 --- /dev/null +++ b/sail_latex_riscv/valzriscv_i64tof645552b730328b5e488a5469c4d60ba48e.tex @@ -0,0 +1 @@ +riscv_i64ToF64 : (bits_rm, bits_L) -> (bits_fflags, bits_D) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_ui32tof3277c5e2e314e991c265ecd083fea05bf0.tex b/sail_latex_riscv/valzriscv_ui32tof3277c5e2e314e991c265ecd083fea05bf0.tex new file mode 100644 index 00000000..c77c48da --- /dev/null +++ b/sail_latex_riscv/valzriscv_ui32tof3277c5e2e314e991c265ecd083fea05bf0.tex @@ -0,0 +1 @@ +riscv_ui32ToF32 : (bits_rm, bits_WU) -> (bits_fflags, bits_S) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_ui32tof6485dd2d5d0818e64745a16c8bd2e6f3ad.tex b/sail_latex_riscv/valzriscv_ui32tof6485dd2d5d0818e64745a16c8bd2e6f3ad.tex new file mode 100644 index 00000000..a7d77f6d --- /dev/null +++ b/sail_latex_riscv/valzriscv_ui32tof6485dd2d5d0818e64745a16c8bd2e6f3ad.tex @@ -0,0 +1 @@ +riscv_ui32ToF64 : (bits_rm, bits_WU) -> (bits_fflags, bits_D) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_ui64tof32006c37b85131ebfdf4c65a0ecf2d321b.tex b/sail_latex_riscv/valzriscv_ui64tof32006c37b85131ebfdf4c65a0ecf2d321b.tex new file mode 100644 index 00000000..1df35aaa --- /dev/null +++ b/sail_latex_riscv/valzriscv_ui64tof32006c37b85131ebfdf4c65a0ecf2d321b.tex @@ -0,0 +1 @@ +riscv_ui64ToF32 : (bits_rm, bits_LU) -> (bits_fflags, bits_S) \ No newline at end of file diff --git a/sail_latex_riscv/valzriscv_ui64tof647831c3694f6a0849ff1899ade6b08220.tex b/sail_latex_riscv/valzriscv_ui64tof647831c3694f6a0849ff1899ade6b08220.tex new file mode 100644 index 00000000..c0dfdbdc --- /dev/null +++ b/sail_latex_riscv/valzriscv_ui64tof647831c3694f6a0849ff1899ade6b08220.tex @@ -0,0 +1 @@ +riscv_ui64ToF64 : (bits_rm, bits_LU) -> (bits_fflags, bits_D) \ No newline at end of file diff --git a/sail_latex_riscv/valzrop_of_numdb49159dd280dafb7370c6477b545c05.tex b/sail_latex_riscv/valzrop_of_numdb49159dd280dafb7370c6477b545c05.tex new file mode 100644 index 00000000..21c6ec6c --- /dev/null +++ b/sail_latex_riscv/valzrop_of_numdb49159dd280dafb7370c6477b545c05.tex @@ -0,0 +1 @@ +rop_of_num : forall ('e : Int), (0 <= 'e & 'e <= 9). int('e) -> rop \ No newline at end of file diff --git a/sail_latex_riscv/valzropw_of_numbc49d41e4663ce1e2313189dca74c7f1.tex b/sail_latex_riscv/valzropw_of_numbc49d41e4663ce1e2313189dca74c7f1.tex new file mode 100644 index 00000000..01e733c7 --- /dev/null +++ b/sail_latex_riscv/valzropw_of_numbc49d41e4663ce1e2313189dca74c7f1.tex @@ -0,0 +1 @@ +ropw_of_num : forall ('e : Int), (0 <= 'e & 'e <= 4). int('e) -> ropw \ No newline at end of file diff --git a/sail_latex_riscv/valzrounding_mode_of_num6135245be40748c506fabd0190282238.tex b/sail_latex_riscv/valzrounding_mode_of_num6135245be40748c506fabd0190282238.tex new file mode 100644 index 00000000..c34c7c57 --- /dev/null +++ b/sail_latex_riscv/valzrounding_mode_of_num6135245be40748c506fabd0190282238.tex @@ -0,0 +1 @@ +rounding_mode_of_num : forall ('e : Int), (0 <= 'e & 'e <= 5). int('e) -> rounding_mode \ No newline at end of file diff --git a/sail_latex_riscv/valzrtype_mnemonic539b9ad883876e5c6be9237e5c98ffbb.tex b/sail_latex_riscv/valzrtype_mnemonic539b9ad883876e5c6be9237e5c98ffbb.tex new file mode 100644 index 00000000..dc81cf61 --- /dev/null +++ b/sail_latex_riscv/valzrtype_mnemonic539b9ad883876e5c6be9237e5c98ffbb.tex @@ -0,0 +1 @@ +rtype_mnemonic : rop <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzrtypew_mnemonic72f42d5e018398fdfceb25edf2e10caf.tex b/sail_latex_riscv/valzrtypew_mnemonic72f42d5e018398fdfceb25edf2e10caf.tex new file mode 100644 index 00000000..283a1bc5 --- /dev/null +++ b/sail_latex_riscv/valzrtypew_mnemonic72f42d5e018398fdfceb25edf2e10caf.tex @@ -0,0 +1 @@ +rtypew_mnemonic : ropw <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzrvfi_readaee7411fcd70e67f9e6d2f7f9f563435.tex b/sail_latex_riscv/valzrvfi_readaee7411fcd70e67f9e6d2f7f9f563435.tex new file mode 100644 index 00000000..cca10db7 --- /dev/null +++ b/sail_latex_riscv/valzrvfi_readaee7411fcd70e67f9e6d2f7f9f563435.tex @@ -0,0 +1 @@ +rvfi_read : forall ('n : Int), 'n > 0. (xlenbits, int('n), MemoryOpResult(bits(8 * 'n))) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzrvfi_trap0d0ddd87deff120444aa8feac182c6ce.tex b/sail_latex_riscv/valzrvfi_trap0d0ddd87deff120444aa8feac182c6ce.tex new file mode 100644 index 00000000..f79d7f1b --- /dev/null +++ b/sail_latex_riscv/valzrvfi_trap0d0ddd87deff120444aa8feac182c6ce.tex @@ -0,0 +1 @@ +rvfi_trap : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex b/sail_latex_riscv/valzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex new file mode 100644 index 00000000..5233c922 --- /dev/null +++ b/sail_latex_riscv/valzrvfi_write8e76a07b5a6f2a7b76947099108996b1.tex @@ -0,0 +1 @@ +rvfi_write : forall ('n : Int), 'n > 0. (xlenbits, int('n), bits(8 * 'n)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzrvfi_wxed842ecfeb56ef18626194f2f22935f3.tex b/sail_latex_riscv/valzrvfi_wxed842ecfeb56ef18626194f2f22935f3.tex new file mode 100644 index 00000000..1bdd037a --- /dev/null +++ b/sail_latex_riscv/valzrvfi_wxed842ecfeb56ef18626194f2f22935f3.tex @@ -0,0 +1 @@ +rvfi_wX : forall ('n : Int), (0 <= 'n & 'n < 32). (regno('n), xlenbits) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzrx_bitsba4d35e6c426ac476fdbf36efdd5d0da.tex b/sail_latex_riscv/valzrx_bitsba4d35e6c426ac476fdbf36efdd5d0da.tex new file mode 100644 index 00000000..df2178b0 --- /dev/null +++ b/sail_latex_riscv/valzrx_bitsba4d35e6c426ac476fdbf36efdd5d0da.tex @@ -0,0 +1 @@ +rX_bits : bits(5) -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzrxa8aad9466d0653707390b940aa9282e7.tex b/sail_latex_riscv/valzrxa8aad9466d0653707390b940aa9282e7.tex new file mode 100644 index 00000000..ee41a62c --- /dev/null +++ b/sail_latex_riscv/valzrxa8aad9466d0653707390b940aa9282e7.tex @@ -0,0 +1 @@ +rX : forall ('n : Int), (0 <= 'n & 'n < 32). regno('n) -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzsail_arith_shiftrighta24f06e92ffcd84e26ed61085c833371.tex b/sail_latex_riscv/valzsail_arith_shiftrighta24f06e92ffcd84e26ed61085c833371.tex new file mode 100644 index 00000000..9d15bcf4 --- /dev/null +++ b/sail_latex_riscv/valzsail_arith_shiftrighta24f06e92ffcd84e26ed61085c833371.tex @@ -0,0 +1 @@ +sail_arith_shiftright : forall ('n : Int)('ord : Order). (bitvector('n, 'ord), int) -> bitvector('n, 'ord) \ No newline at end of file diff --git a/sail_latex_riscv/valzsail_maske146b73afc824e90813dd8234bfa3053.tex b/sail_latex_riscv/valzsail_maske146b73afc824e90813dd8234bfa3053.tex new file mode 100644 index 00000000..07d06344 --- /dev/null +++ b/sail_latex_riscv/valzsail_maske146b73afc824e90813dd8234bfa3053.tex @@ -0,0 +1 @@ +sail_mask : forall ('len 'v : Int), ('len >= 0 & 'v >= 0). (int('len), bits('v)) -> bits('len) \ No newline at end of file diff --git a/sail_latex_riscv/valzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex b/sail_latex_riscv/valzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex new file mode 100644 index 00000000..a8014f67 --- /dev/null +++ b/sail_latex_riscv/valzsail_ones0510f34656bd3d7b905b0ff315bf81d7.tex @@ -0,0 +1 @@ +sail_ones : forall ('n : Int), 'n >= 0. int('n) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzsail_shiftlefta7bc10407d10355c4e981688c9926084.tex b/sail_latex_riscv/valzsail_shiftlefta7bc10407d10355c4e981688c9926084.tex new file mode 100644 index 00000000..b4eb800b --- /dev/null +++ b/sail_latex_riscv/valzsail_shiftlefta7bc10407d10355c4e981688c9926084.tex @@ -0,0 +1 @@ +sail_shiftleft : forall ('n : Int)('ord : Order). (bitvector('n, 'ord), int) -> bitvector('n, 'ord) \ No newline at end of file diff --git a/sail_latex_riscv/valzsail_shiftrighte403ac5c2740b7767c2bdfe689082562.tex b/sail_latex_riscv/valzsail_shiftrighte403ac5c2740b7767c2bdfe689082562.tex new file mode 100644 index 00000000..1258f73f --- /dev/null +++ b/sail_latex_riscv/valzsail_shiftrighte403ac5c2740b7767c2bdfe689082562.tex @@ -0,0 +1 @@ +sail_shiftright : forall ('n : Int)('ord : Order). (bitvector('n, 'ord), int) -> bitvector('n, 'ord) \ No newline at end of file diff --git a/sail_latex_riscv/valzsail_sign_extendb66ac7c1aaedb0cb21bdf07e4518af5e.tex b/sail_latex_riscv/valzsail_sign_extendb66ac7c1aaedb0cb21bdf07e4518af5e.tex new file mode 100644 index 00000000..3b61d758 --- /dev/null +++ b/sail_latex_riscv/valzsail_sign_extendb66ac7c1aaedb0cb21bdf07e4518af5e.tex @@ -0,0 +1 @@ +sail_sign_extend : forall ('n 'm : Int), 'm >= 'n. (bits('n), int('m)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_riscv/valzsail_zzero_extend411875c18d3b332113845d17151890c2.tex b/sail_latex_riscv/valzsail_zzero_extend411875c18d3b332113845d17151890c2.tex new file mode 100644 index 00000000..48b6e74e --- /dev/null +++ b/sail_latex_riscv/valzsail_zzero_extend411875c18d3b332113845d17151890c2.tex @@ -0,0 +1 @@ +sail_zero_extend : forall ('n 'm : Int), 'm >= 'n. (bits('n), int('m)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_riscv/valzsail_zzeros174d4d4928427d9df9fa9749f1df5f96.tex b/sail_latex_riscv/valzsail_zzeros174d4d4928427d9df9fa9749f1df5f96.tex new file mode 100644 index 00000000..fee38a4b --- /dev/null +++ b/sail_latex_riscv/valzsail_zzeros174d4d4928427d9df9fa9749f1df5f96.tex @@ -0,0 +1 @@ +sail_zeros : forall ('n : Int), 'n >= 0. int('n) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzsatp64mode_of_bits11c1e0e3eda64d7361d8ec4950c9f1ea.tex b/sail_latex_riscv/valzsatp64mode_of_bits11c1e0e3eda64d7361d8ec4950c9f1ea.tex new file mode 100644 index 00000000..6ac0c4db --- /dev/null +++ b/sail_latex_riscv/valzsatp64mode_of_bits11c1e0e3eda64d7361d8ec4950c9f1ea.tex @@ -0,0 +1 @@ +satp64Mode_of_bits : (Architecture, satp_mode) -> option(SATPMode) \ No newline at end of file diff --git a/sail_latex_riscv/valzsatpmode_of_num09ad57622dbe0d0a7b111194f1a36856.tex b/sail_latex_riscv/valzsatpmode_of_num09ad57622dbe0d0a7b111194f1a36856.tex new file mode 100644 index 00000000..29198346 --- /dev/null +++ b/sail_latex_riscv/valzsatpmode_of_num09ad57622dbe0d0a7b111194f1a36856.tex @@ -0,0 +1 @@ +SATPMode_of_num : forall ('e : Int), (0 <= 'e & 'e <= 3). int('e) -> SATPMode \ No newline at end of file diff --git a/sail_latex_riscv/valzscr_name18d33d5c24513d7598c403423ce2f8e6.tex b/sail_latex_riscv/valzscr_name18d33d5c24513d7598c403423ce2f8e6.tex new file mode 100644 index 00000000..ae23fd9b --- /dev/null +++ b/sail_latex_riscv/valzscr_name18d33d5c24513d7598c403423ce2f8e6.tex @@ -0,0 +1 @@ +scr_name : screg -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzscr_name_map4b235a67e525de15ab35ff501d369c01.tex b/sail_latex_riscv/valzscr_name_map4b235a67e525de15ab35ff501d369c01.tex new file mode 100644 index 00000000..1aa42768 --- /dev/null +++ b/sail_latex_riscv/valzscr_name_map4b235a67e525de15ab35ff501d369c01.tex @@ -0,0 +1 @@ +scr_name_map : screg <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex b/sail_latex_riscv/valzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex new file mode 100644 index 00000000..b01f4ab3 --- /dev/null +++ b/sail_latex_riscv/valzsealcap2d2c6ffa10772e30f9bf6dea4aba0364.tex @@ -0,0 +1 @@ +sealCap : (Capability, bits(cap_otype_width)) -> Capability \ No newline at end of file diff --git a/sail_latex_riscv/valzselect_instr_or_fcsr_rm8a489b01095486a7dc41b6fb5b17b9a7.tex b/sail_latex_riscv/valzselect_instr_or_fcsr_rm8a489b01095486a7dc41b6fb5b17b9a7.tex new file mode 100644 index 00000000..0bd1006a --- /dev/null +++ b/sail_latex_riscv/valzselect_instr_or_fcsr_rm8a489b01095486a7dc41b6fb5b17b9a7.tex @@ -0,0 +1 @@ +select_instr_or_fcsr_rm : rounding_mode -> rounding_mode \ No newline at end of file diff --git a/sail_latex_riscv/valzsep43dac566d26bd3f7fb9088b8d09ca246.tex b/sail_latex_riscv/valzsep43dac566d26bd3f7fb9088b8d09ca246.tex new file mode 100644 index 00000000..36006c88 --- /dev/null +++ b/sail_latex_riscv/valzsep43dac566d26bd3f7fb9088b8d09ca246.tex @@ -0,0 +1 @@ +sep : unit <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzset_mstatus_sxl3c993e2659d94bb903dbbc607aa47f8c.tex b/sail_latex_riscv/valzset_mstatus_sxl3c993e2659d94bb903dbbc607aa47f8c.tex new file mode 100644 index 00000000..5fe440de --- /dev/null +++ b/sail_latex_riscv/valzset_mstatus_sxl3c993e2659d94bb903dbbc607aa47f8c.tex @@ -0,0 +1 @@ +set_mstatus_SXL : (Mstatus, arch_xlen) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valzset_mstatus_uxl030f4a70ceca0610271994fbfcb96d4d.tex b/sail_latex_riscv/valzset_mstatus_uxl030f4a70ceca0610271994fbfcb96d4d.tex new file mode 100644 index 00000000..f7065c96 --- /dev/null +++ b/sail_latex_riscv/valzset_mstatus_uxl030f4a70ceca0610271994fbfcb96d4d.tex @@ -0,0 +1 @@ +set_mstatus_UXL : (Mstatus, arch_xlen) -> Mstatus \ No newline at end of file diff --git a/sail_latex_riscv/valzset_mtvec628ceb1975fa7b69631fcc224f1bbbc0.tex b/sail_latex_riscv/valzset_mtvec628ceb1975fa7b69631fcc224f1bbbc0.tex new file mode 100644 index 00000000..0940d250 --- /dev/null +++ b/sail_latex_riscv/valzset_mtvec628ceb1975fa7b69631fcc224f1bbbc0.tex @@ -0,0 +1 @@ +set_mtvec : xlenbits -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzset_next_pc4a8ca0d1733a6630871f9f58d4ea2e08.tex b/sail_latex_riscv/valzset_next_pc4a8ca0d1733a6630871f9f58d4ea2e08.tex new file mode 100644 index 00000000..35365fcc --- /dev/null +++ b/sail_latex_riscv/valzset_next_pc4a8ca0d1733a6630871f9f58d4ea2e08.tex @@ -0,0 +1 @@ +set_next_pc : xlenbits -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzset_slice_bits5956200094c551f35973411fcc90a521.tex b/sail_latex_riscv/valzset_slice_bits5956200094c551f35973411fcc90a521.tex new file mode 100644 index 00000000..ef5ed054 --- /dev/null +++ b/sail_latex_riscv/valzset_slice_bits5956200094c551f35973411fcc90a521.tex @@ -0,0 +1 @@ +set_slice_bits : forall ('n 'm : Int). (implicit('n), int('m), bits('n), int, bits('m)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzset_slice_intf4b6b0ed3d8b3bb2f2e0d7a492959629.tex b/sail_latex_riscv/valzset_slice_intf4b6b0ed3d8b3bb2f2e0d7a492959629.tex new file mode 100644 index 00000000..edb9c5e7 --- /dev/null +++ b/sail_latex_riscv/valzset_slice_intf4b6b0ed3d8b3bb2f2e0d7a492959629.tex @@ -0,0 +1 @@ +set_slice_int : forall ('w : Int). (int('w), int, int, bits('w)) -> int \ No newline at end of file diff --git a/sail_latex_riscv/valzset_sstatus_uxl4d602a7109609248f9b54c8c905b4ad0.tex b/sail_latex_riscv/valzset_sstatus_uxl4d602a7109609248f9b54c8c905b4ad0.tex new file mode 100644 index 00000000..3766affd --- /dev/null +++ b/sail_latex_riscv/valzset_sstatus_uxl4d602a7109609248f9b54c8c905b4ad0.tex @@ -0,0 +1 @@ +set_sstatus_UXL : (Sstatus, arch_xlen) -> Sstatus \ No newline at end of file diff --git a/sail_latex_riscv/valzset_stvec0d8dcc20a4d9dd912d52b9252d2370a7.tex b/sail_latex_riscv/valzset_stvec0d8dcc20a4d9dd912d52b9252d2370a7.tex new file mode 100644 index 00000000..d32f2199 --- /dev/null +++ b/sail_latex_riscv/valzset_stvec0d8dcc20a4d9dd912d52b9252d2370a7.tex @@ -0,0 +1 @@ +set_stvec : xlenbits -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzset_utvec4e028b19c2b4db0c1c1a0a48f1c4a330.tex b/sail_latex_riscv/valzset_utvec4e028b19c2b4db0c1c1a0a48f1c4a330.tex new file mode 100644 index 00000000..c47f03fc --- /dev/null +++ b/sail_latex_riscv/valzset_utvec4e028b19c2b4db0c1c1a0a48f1c4a330.tex @@ -0,0 +1 @@ +set_utvec : xlenbits -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzset_xret_target81095db6e6bb6da6b746ed406dccd45e.tex b/sail_latex_riscv/valzset_xret_target81095db6e6bb6da6b746ed406dccd45e.tex new file mode 100644 index 00000000..ced63655 --- /dev/null +++ b/sail_latex_riscv/valzset_xret_target81095db6e6bb6da6b746ed406dccd45e.tex @@ -0,0 +1 @@ +set_xret_target : (Privilege, xlenbits) -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex b/sail_latex_riscv/valzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex new file mode 100644 index 00000000..20ce209f --- /dev/null +++ b/sail_latex_riscv/valzsetcapaddr35ad6dc7effb74b141243b59c9daceff.tex @@ -0,0 +1 @@ +setCapAddr : (Capability, CapAddrBits) -> (bool, Capability) \ No newline at end of file diff --git a/sail_latex_riscv/valzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex b/sail_latex_riscv/valzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex new file mode 100644 index 00000000..4d919e71 --- /dev/null +++ b/sail_latex_riscv/valzsetcapbounds7a50a538fe976a2bfbe0b9f81cc7642e.tex @@ -0,0 +1 @@ +setCapBounds : (Capability, CapAddrBits, CapLenBits) -> (bool, Capability) \ No newline at end of file diff --git a/sail_latex_riscv/valzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex b/sail_latex_riscv/valzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex new file mode 100644 index 00000000..879dd3d3 --- /dev/null +++ b/sail_latex_riscv/valzsetcapflags1cebd5e15eac27fc3dbd3e6dc534158a.tex @@ -0,0 +1 @@ +setCapFlags : (Capability, CapFlagsBits) -> Capability \ No newline at end of file diff --git a/sail_latex_riscv/valzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex b/sail_latex_riscv/valzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex new file mode 100644 index 00000000..264917ca --- /dev/null +++ b/sail_latex_riscv/valzsetcapoffset2da95070f2a3b53b97519f3b1f6a312a.tex @@ -0,0 +1 @@ +setCapOffset : (Capability, CapAddrBits) -> (bool, Capability) \ No newline at end of file diff --git a/sail_latex_riscv/valzsetcapoffsetornullc7b6ed6c2844187ec5b671dc1ca3eae0.tex b/sail_latex_riscv/valzsetcapoffsetornullc7b6ed6c2844187ec5b671dc1ca3eae0.tex new file mode 100644 index 00000000..f2ea74bb --- /dev/null +++ b/sail_latex_riscv/valzsetcapoffsetornullc7b6ed6c2844187ec5b671dc1ca3eae0.tex @@ -0,0 +1 @@ +setCapOffsetOrNull : (Capability, CapAddrBits) -> Capability \ No newline at end of file diff --git a/sail_latex_riscv/valzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex b/sail_latex_riscv/valzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex new file mode 100644 index 00000000..b4dde466 --- /dev/null +++ b/sail_latex_riscv/valzsetcappermsbb03905a9ed7e94e44018326fd80a0d0.tex @@ -0,0 +1 @@ +setCapPerms : (Capability, CapPermsBits) -> Capability \ No newline at end of file diff --git a/sail_latex_riscv/valzshift_bits_left0754e8b870e2a3ba46646c35dac7af10.tex b/sail_latex_riscv/valzshift_bits_left0754e8b870e2a3ba46646c35dac7af10.tex new file mode 100644 index 00000000..6eb7cdd1 --- /dev/null +++ b/sail_latex_riscv/valzshift_bits_left0754e8b870e2a3ba46646c35dac7af10.tex @@ -0,0 +1 @@ +shift_bits_left : forall ('n 'm : Int). (bits('n), bits('m)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzshift_bits_right281f5e6a28fe3c92d35fe5c78a0deb41.tex b/sail_latex_riscv/valzshift_bits_right281f5e6a28fe3c92d35fe5c78a0deb41.tex new file mode 100644 index 00000000..390b2b9d --- /dev/null +++ b/sail_latex_riscv/valzshift_bits_right281f5e6a28fe3c92d35fe5c78a0deb41.tex @@ -0,0 +1 @@ +shift_bits_right : forall ('n 'm : Int). (bits('n), bits('m)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzshift_right_arith32247e0e7505241d38fca8e6a3bcdfea9e.tex b/sail_latex_riscv/valzshift_right_arith32247e0e7505241d38fca8e6a3bcdfea9e.tex new file mode 100644 index 00000000..ab7953a7 --- /dev/null +++ b/sail_latex_riscv/valzshift_right_arith32247e0e7505241d38fca8e6a3bcdfea9e.tex @@ -0,0 +1 @@ +shift_right_arith32 : (bits(32), bits(5)) -> bits(32) \ No newline at end of file diff --git a/sail_latex_riscv/valzshift_right_arith642d6a56971daae2b1fdb862ebbbaf6a46.tex b/sail_latex_riscv/valzshift_right_arith642d6a56971daae2b1fdb862ebbbaf6a46.tex new file mode 100644 index 00000000..fbb70e6c --- /dev/null +++ b/sail_latex_riscv/valzshift_right_arith642d6a56971daae2b1fdb862ebbbaf6a46.tex @@ -0,0 +1 @@ +shift_right_arith64 : (bits(64), bits(6)) -> bits(64) \ No newline at end of file diff --git a/sail_latex_riscv/valzshiftiop_mnemonicbeafdfe24bd90ed73f232559498ac819.tex b/sail_latex_riscv/valzshiftiop_mnemonicbeafdfe24bd90ed73f232559498ac819.tex new file mode 100644 index 00000000..bd8d842c --- /dev/null +++ b/sail_latex_riscv/valzshiftiop_mnemonicbeafdfe24bd90ed73f232559498ac819.tex @@ -0,0 +1 @@ +shiftiop_mnemonic : sop <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzshiftiwop_mnemonic59f60b5dc1f36ebc6fe3d32d9df1d608.tex b/sail_latex_riscv/valzshiftiwop_mnemonic59f60b5dc1f36ebc6fe3d32d9df1d608.tex new file mode 100644 index 00000000..38fd2203 --- /dev/null +++ b/sail_latex_riscv/valzshiftiwop_mnemonic59f60b5dc1f36ebc6fe3d32d9df1d608.tex @@ -0,0 +1 @@ +shiftiwop_mnemonic : sopw <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzshiftl7827d0dcac29bd8258f158e7c1e77658.tex b/sail_latex_riscv/valzshiftl7827d0dcac29bd8258f158e7c1e77658.tex new file mode 100644 index 00000000..9d7e4aab --- /dev/null +++ b/sail_latex_riscv/valzshiftl7827d0dcac29bd8258f158e7c1e77658.tex @@ -0,0 +1 @@ +shiftl : forall ('m 'n : Int), 'n >= 0. (bits('m), int('n)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_riscv/valzshiftr173b7dba7206ed1b61a12344bdf9182a.tex b/sail_latex_riscv/valzshiftr173b7dba7206ed1b61a12344bdf9182a.tex new file mode 100644 index 00000000..a875e70b --- /dev/null +++ b/sail_latex_riscv/valzshiftr173b7dba7206ed1b61a12344bdf9182a.tex @@ -0,0 +1 @@ +shiftr : forall ('m 'n : Int), 'n >= 0. (bits('m), int('n)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_riscv/valzshiftw_mnemonice823d8fe4e9165665d0ca244aa353baa.tex b/sail_latex_riscv/valzshiftw_mnemonice823d8fe4e9165665d0ca244aa353baa.tex new file mode 100644 index 00000000..73bc7759 --- /dev/null +++ b/sail_latex_riscv/valzshiftw_mnemonice823d8fe4e9165665d0ca244aa353baa.tex @@ -0,0 +1 @@ +shiftw_mnemonic : sop <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzsigned36d2317f34f1dacb4e465e6e56b185e6.tex b/sail_latex_riscv/valzsigned36d2317f34f1dacb4e465e6e56b185e6.tex new file mode 100644 index 00000000..75b658cf --- /dev/null +++ b/sail_latex_riscv/valzsigned36d2317f34f1dacb4e465e6e56b185e6.tex @@ -0,0 +1 @@ +signed : forall ('n : Int), 'n > 0. bits('n) -> range(- (2 ^ ('n - 1)), 2 ^ ('n - 1) - 1) \ No newline at end of file diff --git a/sail_latex_riscv/valzsizze_bits40630770cee662892ab899654b7e2f0d.tex b/sail_latex_riscv/valzsizze_bits40630770cee662892ab899654b7e2f0d.tex new file mode 100644 index 00000000..62c2f79c --- /dev/null +++ b/sail_latex_riscv/valzsizze_bits40630770cee662892ab899654b7e2f0d.tex @@ -0,0 +1 @@ +size_bits : word_width <-> bitvector(2, dec) \ No newline at end of file diff --git a/sail_latex_riscv/valzsizze_mnemonic4114d3c8877e3689368588f52debea7b.tex b/sail_latex_riscv/valzsizze_mnemonic4114d3c8877e3689368588f52debea7b.tex new file mode 100644 index 00000000..32e92d7a --- /dev/null +++ b/sail_latex_riscv/valzsizze_mnemonic4114d3c8877e3689368588f52debea7b.tex @@ -0,0 +1 @@ +size_mnemonic : word_width <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzslice9979e992fd48f77a2c3fef7fbcce068e.tex b/sail_latex_riscv/valzslice9979e992fd48f77a2c3fef7fbcce068e.tex new file mode 100644 index 00000000..f7f53244 --- /dev/null +++ b/sail_latex_riscv/valzslice9979e992fd48f77a2c3fef7fbcce068e.tex @@ -0,0 +1 @@ +slice : forall ('n 'm 'o : Int), (0 <= 'm & 0 <= 'n). (bits('m), int('o), int('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex b/sail_latex_riscv/valzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex new file mode 100644 index 00000000..77bf7c81 --- /dev/null +++ b/sail_latex_riscv/valzslice_maske01cafc7448fbf1583dc5dd96b06c854.tex @@ -0,0 +1 @@ +slice_mask : forall ('n : Int), 'n >= 0. (implicit('n), int, int) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzsop_of_num788240d3b5d5ef8334c5920b24c291e9.tex b/sail_latex_riscv/valzsop_of_num788240d3b5d5ef8334c5920b24c291e9.tex new file mode 100644 index 00000000..40871c27 --- /dev/null +++ b/sail_latex_riscv/valzsop_of_num788240d3b5d5ef8334c5920b24c291e9.tex @@ -0,0 +1 @@ +sop_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> sop \ No newline at end of file diff --git a/sail_latex_riscv/valzsopw_of_num696c7b3c0b6fb9b9c9d699cd0a410ea3.tex b/sail_latex_riscv/valzsopw_of_num696c7b3c0b6fb9b9c9d699cd0a410ea3.tex new file mode 100644 index 00000000..093f3285 --- /dev/null +++ b/sail_latex_riscv/valzsopw_of_num696c7b3c0b6fb9b9c9d699cd0a410ea3.tex @@ -0,0 +1 @@ +sopw_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> sopw \ No newline at end of file diff --git a/sail_latex_riscv/valzspc_backwardsa712e20ab4070963924d2974cc8aa941.tex b/sail_latex_riscv/valzspc_backwardsa712e20ab4070963924d2974cc8aa941.tex new file mode 100644 index 00000000..278d1b6b --- /dev/null +++ b/sail_latex_riscv/valzspc_backwardsa712e20ab4070963924d2974cc8aa941.tex @@ -0,0 +1 @@ +spc_backwards : string -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzspc_forwardsabfa1efbce2d58c6d3e26c86435d3af4.tex b/sail_latex_riscv/valzspc_forwardsabfa1efbce2d58c6d3e26c86435d3af4.tex new file mode 100644 index 00000000..01fece80 --- /dev/null +++ b/sail_latex_riscv/valzspc_forwardsabfa1efbce2d58c6d3e26c86435d3af4.tex @@ -0,0 +1 @@ +spc_forwards : unit -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzspc_matches_prefix38c7965c7edeefb5fb2ccd6915f5bdbb.tex b/sail_latex_riscv/valzspc_matches_prefix38c7965c7edeefb5fb2ccd6915f5bdbb.tex new file mode 100644 index 00000000..2c1b13c9 --- /dev/null +++ b/sail_latex_riscv/valzspc_matches_prefix38c7965c7edeefb5fb2ccd6915f5bdbb.tex @@ -0,0 +1 @@ +spc_matches_prefix : string -> option((unit, nat)) \ No newline at end of file diff --git a/sail_latex_riscv/valzspca574d99b4c3d28e08386a1f673633994.tex b/sail_latex_riscv/valzspca574d99b4c3d28e08386a1f673633994.tex new file mode 100644 index 00000000..b2d22331 --- /dev/null +++ b/sail_latex_riscv/valzspca574d99b4c3d28e08386a1f673633994.tex @@ -0,0 +1 @@ +spc : unit <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzspeculate_conditionalc9cfcf9f8fbedbbbb1846b896e477d5c.tex b/sail_latex_riscv/valzspeculate_conditionalc9cfcf9f8fbedbbbb1846b896e477d5c.tex new file mode 100644 index 00000000..2219f43e --- /dev/null +++ b/sail_latex_riscv/valzspeculate_conditionalc9cfcf9f8fbedbbbb1846b896e477d5c.tex @@ -0,0 +1 @@ +speculate_conditional : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzstepb001f84c8bf78b78b44b98d2b7f1f7d7.tex b/sail_latex_riscv/valzstepb001f84c8bf78b78b44b98d2b7f1f7d7.tex new file mode 100644 index 00000000..283adbd8 --- /dev/null +++ b/sail_latex_riscv/valzstepb001f84c8bf78b78b44b98d2b7f1f7d7.tex @@ -0,0 +1 @@ +step : int -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzstring_appendca8a3ce55684edee6af875f28a1550b0.tex b/sail_latex_riscv/valzstring_appendca8a3ce55684edee6af875f28a1550b0.tex new file mode 100644 index 00000000..7658b0e8 --- /dev/null +++ b/sail_latex_riscv/valzstring_appendca8a3ce55684edee6af875f28a1550b0.tex @@ -0,0 +1 @@ +string_append : (string, string) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzstring_drop09d7231db4951d3343ee0356a8f98d4e.tex b/sail_latex_riscv/valzstring_drop09d7231db4951d3343ee0356a8f98d4e.tex new file mode 100644 index 00000000..290c29aa --- /dev/null +++ b/sail_latex_riscv/valzstring_drop09d7231db4951d3343ee0356a8f98d4e.tex @@ -0,0 +1 @@ +string_drop : (string, nat) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzstring_length138975cd51f6e879bf061905da0059f9.tex b/sail_latex_riscv/valzstring_length138975cd51f6e879bf061905da0059f9.tex new file mode 100644 index 00000000..711a600c --- /dev/null +++ b/sail_latex_riscv/valzstring_length138975cd51f6e879bf061905da0059f9.tex @@ -0,0 +1 @@ +string_length : string -> nat \ No newline at end of file diff --git a/sail_latex_riscv/valzstring_of_bit7313cdbf7b05129d4977581f9bb14794.tex b/sail_latex_riscv/valzstring_of_bit7313cdbf7b05129d4977581f9bb14794.tex new file mode 100644 index 00000000..4bb68894 --- /dev/null +++ b/sail_latex_riscv/valzstring_of_bit7313cdbf7b05129d4977581f9bb14794.tex @@ -0,0 +1 @@ +string_of_bit : bit -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzstring_of_bits43debe172d2009dbb056cb5252821d62.tex b/sail_latex_riscv/valzstring_of_bits43debe172d2009dbb056cb5252821d62.tex new file mode 100644 index 00000000..68eecb4b --- /dev/null +++ b/sail_latex_riscv/valzstring_of_bits43debe172d2009dbb056cb5252821d62.tex @@ -0,0 +1 @@ +string_of_bits : forall ('n : Int). bits('n) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex b/sail_latex_riscv/valzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex new file mode 100644 index 00000000..c4eb2fa9 --- /dev/null +++ b/sail_latex_riscv/valzstring_of_capexa149bb71f2b82372115d021ece4e6416.tex @@ -0,0 +1 @@ +string_of_capex : CapEx -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzstring_of_int03988e4e2d2976513793427ac823afbe.tex b/sail_latex_riscv/valzstring_of_int03988e4e2d2976513793427ac823afbe.tex new file mode 100644 index 00000000..69edce40 --- /dev/null +++ b/sail_latex_riscv/valzstring_of_int03988e4e2d2976513793427ac823afbe.tex @@ -0,0 +1 @@ +string_of_int : int -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzstring_startswith150dcce016e36e283e03e57c7aa7f479.tex b/sail_latex_riscv/valzstring_startswith150dcce016e36e283e03e57c7aa7f479.tex new file mode 100644 index 00000000..3405cd9c --- /dev/null +++ b/sail_latex_riscv/valzstring_startswith150dcce016e36e283e03e57c7aa7f479.tex @@ -0,0 +1 @@ +string_startswith : (string, string) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzstring_takef5fd0689e1a11681ccf5471f34195539.tex b/sail_latex_riscv/valzstring_takef5fd0689e1a11681ccf5471f34195539.tex new file mode 100644 index 00000000..42689b6b --- /dev/null +++ b/sail_latex_riscv/valzstring_takef5fd0689e1a11681ccf5471f34195539.tex @@ -0,0 +1 @@ +string_take : (string, nat) -> string \ No newline at end of file diff --git a/sail_latex_riscv/valzsub_atom328a68dfbab1a07c42d4e7b98eac766f.tex b/sail_latex_riscv/valzsub_atom328a68dfbab1a07c42d4e7b98eac766f.tex new file mode 100644 index 00000000..d7664a15 --- /dev/null +++ b/sail_latex_riscv/valzsub_atom328a68dfbab1a07c42d4e7b98eac766f.tex @@ -0,0 +1 @@ +sub_atom : forall ('n 'm : Int). (int('n), int('m)) -> int('n - 'm) \ No newline at end of file diff --git a/sail_latex_riscv/valzsub_bitsf0dc4fc3429d45517c523db21af72127.tex b/sail_latex_riscv/valzsub_bitsf0dc4fc3429d45517c523db21af72127.tex new file mode 100644 index 00000000..c3992272 --- /dev/null +++ b/sail_latex_riscv/valzsub_bitsf0dc4fc3429d45517c523db21af72127.tex @@ -0,0 +1 @@ +sub_bits : forall ('n : Int). (bits('n), bits('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzsub_intf17f348f33594e77fdc3ef8b6a46b569.tex b/sail_latex_riscv/valzsub_intf17f348f33594e77fdc3ef8b6a46b569.tex new file mode 100644 index 00000000..2cf1aebc --- /dev/null +++ b/sail_latex_riscv/valzsub_intf17f348f33594e77fdc3ef8b6a46b569.tex @@ -0,0 +1 @@ +sub_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_riscv/valzsub_nat1e51a6ef44b288dd12f7f69af44dfd3e.tex b/sail_latex_riscv/valzsub_nat1e51a6ef44b288dd12f7f69af44dfd3e.tex new file mode 100644 index 00000000..379f1121 --- /dev/null +++ b/sail_latex_riscv/valzsub_nat1e51a6ef44b288dd12f7f69af44dfd3e.tex @@ -0,0 +1 @@ +sub_nat : (nat, nat) -> nat \ No newline at end of file diff --git a/sail_latex_riscv/valzsub_vec326e0ba0bb00229be26645e2d44dbd83.tex b/sail_latex_riscv/valzsub_vec326e0ba0bb00229be26645e2d44dbd83.tex new file mode 100644 index 00000000..b62484d5 --- /dev/null +++ b/sail_latex_riscv/valzsub_vec326e0ba0bb00229be26645e2d44dbd83.tex @@ -0,0 +1 @@ +sub_vec : forall ('n : Int). (bits('n), bits('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzsub_vec_int5e6c04459782b1b8cc706ba2e4c8a435.tex b/sail_latex_riscv/valzsub_vec_int5e6c04459782b1b8cc706ba2e4c8a435.tex new file mode 100644 index 00000000..568790f9 --- /dev/null +++ b/sail_latex_riscv/valzsub_vec_int5e6c04459782b1b8cc706ba2e4c8a435.tex @@ -0,0 +1 @@ +sub_vec_int : forall ('n : Int). (bits('n), int) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzsubrange_bits6c497c14df4f4754bd345a6c56ca2aad.tex b/sail_latex_riscv/valzsubrange_bits6c497c14df4f4754bd345a6c56ca2aad.tex new file mode 100644 index 00000000..8ca82640 --- /dev/null +++ b/sail_latex_riscv/valzsubrange_bits6c497c14df4f4754bd345a6c56ca2aad.tex @@ -0,0 +1,2 @@ +subrange_bits : forall ('n 'm 'o : Int), (0 <= 'o & 'o <= 'm & 'm < 'n). + (bits('n), int('m), int('o)) -> bits('m - 'o + 1) \ No newline at end of file diff --git a/sail_latex_riscv/valzsys_enable_fdext3e294bd170189b70567069837e1534c5.tex b/sail_latex_riscv/valzsys_enable_fdext3e294bd170189b70567069837e1534c5.tex new file mode 100644 index 00000000..3bae59b4 --- /dev/null +++ b/sail_latex_riscv/valzsys_enable_fdext3e294bd170189b70567069837e1534c5.tex @@ -0,0 +1 @@ +sys_enable_fdext : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzsys_enable_rvc836db920a63cd54b635b109fb85bcb90.tex b/sail_latex_riscv/valzsys_enable_rvc836db920a63cd54b635b109fb85bcb90.tex new file mode 100644 index 00000000..e78a36d9 --- /dev/null +++ b/sail_latex_riscv/valzsys_enable_rvc836db920a63cd54b635b109fb85bcb90.tex @@ -0,0 +1 @@ +sys_enable_rvc : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzsys_enable_writable_misa83863aeddc0d69035dc46d6908595d89.tex b/sail_latex_riscv/valzsys_enable_writable_misa83863aeddc0d69035dc46d6908595d89.tex new file mode 100644 index 00000000..583d930b --- /dev/null +++ b/sail_latex_riscv/valzsys_enable_writable_misa83863aeddc0d69035dc46d6908595d89.tex @@ -0,0 +1 @@ +sys_enable_writable_misa : unit -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valztag_addr_to_addrec4cd9758dc545430904849bc06af049.tex b/sail_latex_riscv/valztag_addr_to_addrec4cd9758dc545430904849bc06af049.tex new file mode 100644 index 00000000..e3245620 --- /dev/null +++ b/sail_latex_riscv/valztag_addr_to_addrec4cd9758dc545430904849bc06af049.tex @@ -0,0 +1 @@ +tag_addr_to_addr : tagaddrbits -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valztdiv_int5e119ac7ab9ff04c8877846f345d1159.tex b/sail_latex_riscv/valztdiv_int5e119ac7ab9ff04c8877846f345d1159.tex new file mode 100644 index 00000000..7d77e1a1 --- /dev/null +++ b/sail_latex_riscv/valztdiv_int5e119ac7ab9ff04c8877846f345d1159.tex @@ -0,0 +1 @@ +tdiv_int : (int, int) -> int \ No newline at end of file diff --git a/sail_latex_riscv/valztick_clocka855f1c53aa2515a7a67cd69b5b3d663.tex b/sail_latex_riscv/valztick_clocka855f1c53aa2515a7a67cd69b5b3d663.tex new file mode 100644 index 00000000..2d406974 --- /dev/null +++ b/sail_latex_riscv/valztick_clocka855f1c53aa2515a7a67cd69b5b3d663.tex @@ -0,0 +1 @@ +tick_clock : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valztick_pc459868e2ecb79c51cd3817471ae33696.tex b/sail_latex_riscv/valztick_pc459868e2ecb79c51cd3817471ae33696.tex new file mode 100644 index 00000000..8bdf61af --- /dev/null +++ b/sail_latex_riscv/valztick_pc459868e2ecb79c51cd3817471ae33696.tex @@ -0,0 +1 @@ +tick_pc : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valztick_platformc49251d76e66d78fce3dd1f18a27869c.tex b/sail_latex_riscv/valztick_platformc49251d76e66d78fce3dd1f18a27869c.tex new file mode 100644 index 00000000..53097b5f --- /dev/null +++ b/sail_latex_riscv/valztick_platformc49251d76e66d78fce3dd1f18a27869c.tex @@ -0,0 +1 @@ +tick_platform : unit -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex b/sail_latex_riscv/valzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex new file mode 100644 index 00000000..e8880e05 --- /dev/null +++ b/sail_latex_riscv/valzto_bits9fb7c0bf64c9bfa589ae4882a09f2a40.tex @@ -0,0 +1 @@ +to_bits : forall ('l : Int), 'l >= 0. (int('l), int) -> bits('l) \ No newline at end of file diff --git a/sail_latex_riscv/valztrans_kind_of_num89fdff5348b6925bdad7af7bbcc092d6.tex b/sail_latex_riscv/valztrans_kind_of_num89fdff5348b6925bdad7af7bbcc092d6.tex new file mode 100644 index 00000000..86894049 --- /dev/null +++ b/sail_latex_riscv/valztrans_kind_of_num89fdff5348b6925bdad7af7bbcc092d6.tex @@ -0,0 +1 @@ +trans_kind_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> trans_kind \ No newline at end of file diff --git a/sail_latex_riscv/valztranslate39daa42428c4ec23bd5def028158b476c6.tex b/sail_latex_riscv/valztranslate39daa42428c4ec23bd5def028158b476c6.tex new file mode 100644 index 00000000..ad4c0c0f --- /dev/null +++ b/sail_latex_riscv/valztranslate39daa42428c4ec23bd5def028158b476c6.tex @@ -0,0 +1 @@ +translate39 : (asid64, paddr64, vaddr39, AccessType(ext_access_type), Privilege, bool, bool, nat, ext_ptw) -> TR_Result(paddr64, PTW_Error) \ No newline at end of file diff --git a/sail_latex_riscv/valztranslate488637bc30f662c37b22a80c3d053c14e5.tex b/sail_latex_riscv/valztranslate488637bc30f662c37b22a80c3d053c14e5.tex new file mode 100644 index 00000000..d1f709d5 --- /dev/null +++ b/sail_latex_riscv/valztranslate488637bc30f662c37b22a80c3d053c14e5.tex @@ -0,0 +1 @@ +translate48 : (asid64, paddr64, vaddr48, AccessType(ext_access_type), Privilege, bool, bool, nat, ext_ptw) -> TR_Result(paddr64, PTW_Error) \ No newline at end of file diff --git a/sail_latex_riscv/valztranslateaddr7dc6bd4ea43d006224000f7b68f6a187.tex b/sail_latex_riscv/valztranslateaddr7dc6bd4ea43d006224000f7b68f6a187.tex new file mode 100644 index 00000000..cbf67c36 --- /dev/null +++ b/sail_latex_riscv/valztranslateaddr7dc6bd4ea43d006224000f7b68f6a187.tex @@ -0,0 +1 @@ +translateAddr : (xlenbits, AccessType(ext_access_type)) -> TR_Result(xlenbits, ExceptionType) \ No newline at end of file diff --git a/sail_latex_riscv/valztranslationexceptionbd47ba58dcb6fcc0be14f6efdd551ad8.tex b/sail_latex_riscv/valztranslationexceptionbd47ba58dcb6fcc0be14f6efdd551ad8.tex new file mode 100644 index 00000000..e1dd543f --- /dev/null +++ b/sail_latex_riscv/valztranslationexceptionbd47ba58dcb6fcc0be14f6efdd551ad8.tex @@ -0,0 +1 @@ +translationException : (AccessType(ext_access_type), PTW_Error) -> ExceptionType \ No newline at end of file diff --git a/sail_latex_riscv/valztranslationmode51f0fd652f39ec2f6d4c16847f0d4345.tex b/sail_latex_riscv/valztranslationmode51f0fd652f39ec2f6d4c16847f0d4345.tex new file mode 100644 index 00000000..3031d2be --- /dev/null +++ b/sail_latex_riscv/valztranslationmode51f0fd652f39ec2f6d4c16847f0d4345.tex @@ -0,0 +1 @@ +translationMode : Privilege -> SATPMode \ No newline at end of file diff --git a/sail_latex_riscv/valztrap_handler0acf2ac9f6239ac64448b463d4df9cf4.tex b/sail_latex_riscv/valztrap_handler0acf2ac9f6239ac64448b463d4df9cf4.tex new file mode 100644 index 00000000..a5abed40 --- /dev/null +++ b/sail_latex_riscv/valztrap_handler0acf2ac9f6239ac64448b463d4df9cf4.tex @@ -0,0 +1 @@ +trap_handler : (Privilege, bool, exc_code, xlenbits, option(xlenbits), option(ext_exception)) -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valztrapvectormode_of_bits3ab887814163c96ab28aec41cb9b44f6.tex b/sail_latex_riscv/valztrapvectormode_of_bits3ab887814163c96ab28aec41cb9b44f6.tex new file mode 100644 index 00000000..0077790f --- /dev/null +++ b/sail_latex_riscv/valztrapvectormode_of_bits3ab887814163c96ab28aec41cb9b44f6.tex @@ -0,0 +1 @@ +trapVectorMode_of_bits : tv_mode -> TrapVectorMode \ No newline at end of file diff --git a/sail_latex_riscv/valztrapvectormode_of_num8f2938d16cb187b62f9cdbbb35278d48.tex b/sail_latex_riscv/valztrapvectormode_of_num8f2938d16cb187b62f9cdbbb35278d48.tex new file mode 100644 index 00000000..79cd2ce6 --- /dev/null +++ b/sail_latex_riscv/valztrapvectormode_of_num8f2938d16cb187b62f9cdbbb35278d48.tex @@ -0,0 +1 @@ +TrapVectorMode_of_num : forall ('e : Int), (0 <= 'e & 'e <= 2). int('e) -> TrapVectorMode \ No newline at end of file diff --git a/sail_latex_riscv/valztruncatea666e28ae0c8ca7327a2b3fcd1ed4ec7.tex b/sail_latex_riscv/valztruncatea666e28ae0c8ca7327a2b3fcd1ed4ec7.tex new file mode 100644 index 00000000..75765ea7 --- /dev/null +++ b/sail_latex_riscv/valztruncatea666e28ae0c8ca7327a2b3fcd1ed4ec7.tex @@ -0,0 +1 @@ +truncate : forall ('m 'n : Int), ('m >= 0 & 'm <= 'n). (bits('n), int('m)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_riscv/valztruncatelsb4d124c6ec672453343dc0b20d295e82d.tex b/sail_latex_riscv/valztruncatelsb4d124c6ec672453343dc0b20d295e82d.tex new file mode 100644 index 00000000..0718e5ba --- /dev/null +++ b/sail_latex_riscv/valztruncatelsb4d124c6ec672453343dc0b20d295e82d.tex @@ -0,0 +1 @@ +truncateLSB : forall ('m 'n : Int), ('m >= 0 & 'm <= 'n). (bits('n), int('m)) -> bits('m) \ No newline at end of file diff --git a/sail_latex_riscv/valztval0ee7d37a987a82754891fc591aec5852.tex b/sail_latex_riscv/valztval0ee7d37a987a82754891fc591aec5852.tex new file mode 100644 index 00000000..65a5efa3 --- /dev/null +++ b/sail_latex_riscv/valztval0ee7d37a987a82754891fc591aec5852.tex @@ -0,0 +1 @@ +tval : option(xlenbits) -> xlenbits \ No newline at end of file diff --git a/sail_latex_riscv/valztvec_addrc6c52b287eacbc1aca798406d1b08576.tex b/sail_latex_riscv/valztvec_addrc6c52b287eacbc1aca798406d1b08576.tex new file mode 100644 index 00000000..840c4c72 --- /dev/null +++ b/sail_latex_riscv/valztvec_addrc6c52b287eacbc1aca798406d1b08576.tex @@ -0,0 +1 @@ +tvec_addr : (Mtvec, Mcause) -> option(xlenbits) \ No newline at end of file diff --git a/sail_latex_riscv/valzufflagb3d552180ae10d9ed1b23a8e10ad2e9c.tex b/sail_latex_riscv/valzufflagb3d552180ae10d9ed1b23a8e10ad2e9c.tex new file mode 100644 index 00000000..86553cad --- /dev/null +++ b/sail_latex_riscv/valzufflagb3d552180ae10d9ed1b23a8e10ad2e9c.tex @@ -0,0 +1 @@ +ufFlag : unit -> bits(5) \ No newline at end of file diff --git a/sail_latex_riscv/valzunsealcap58689ae49a7317c60147327414a678d2.tex b/sail_latex_riscv/valzunsealcap58689ae49a7317c60147327414a678d2.tex new file mode 100644 index 00000000..915a917d --- /dev/null +++ b/sail_latex_riscv/valzunsealcap58689ae49a7317c60147327414a678d2.tex @@ -0,0 +1 @@ +unsealCap : Capability -> Capability \ No newline at end of file diff --git a/sail_latex_riscv/valzunsigned1010eda2cdd2666cd8fd0ddf82ac526f.tex b/sail_latex_riscv/valzunsigned1010eda2cdd2666cd8fd0ddf82ac526f.tex new file mode 100644 index 00000000..2bf99f64 --- /dev/null +++ b/sail_latex_riscv/valzunsigned1010eda2cdd2666cd8fd0ddf82ac526f.tex @@ -0,0 +1 @@ +unsigned : forall ('n : Int). bits('n) -> range(0, 2 ^ 'n - 1) \ No newline at end of file diff --git a/sail_latex_riscv/valzuop_of_num86c5f7f375d0126822beff686eb42370.tex b/sail_latex_riscv/valzuop_of_num86c5f7f375d0126822beff686eb42370.tex new file mode 100644 index 00000000..001384f9 --- /dev/null +++ b/sail_latex_riscv/valzuop_of_num86c5f7f375d0126822beff686eb42370.tex @@ -0,0 +1 @@ +uop_of_num : forall ('e : Int), (0 <= 'e & 'e <= 1). int('e) -> uop \ No newline at end of file diff --git a/sail_latex_riscv/valzupdate_pte_bitsd84d357c2799412dbae43ca95464282b.tex b/sail_latex_riscv/valzupdate_pte_bitsd84d357c2799412dbae43ca95464282b.tex new file mode 100644 index 00000000..8842e94d --- /dev/null +++ b/sail_latex_riscv/valzupdate_pte_bitsd84d357c2799412dbae43ca95464282b.tex @@ -0,0 +1 @@ +update_PTE_Bits : (PTE_Bits, AccessType(ext_access_type), extPte) -> option((PTE_Bits, extPte)) \ No newline at end of file diff --git a/sail_latex_riscv/valzupdate_softfloat_fflagsc33a686e24584b0b748b2ae8f801c505.tex b/sail_latex_riscv/valzupdate_softfloat_fflagsc33a686e24584b0b748b2ae8f801c505.tex new file mode 100644 index 00000000..abd91fbf --- /dev/null +++ b/sail_latex_riscv/valzupdate_softfloat_fflagsc33a686e24584b0b748b2ae8f801c505.tex @@ -0,0 +1 @@ +update_softfloat_fflags : bits(5) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzupdate_subrange_bitsb5ffe862b26310b45a779cd45bbf041e.tex b/sail_latex_riscv/valzupdate_subrange_bitsb5ffe862b26310b45a779cd45bbf041e.tex new file mode 100644 index 00000000..7757278d --- /dev/null +++ b/sail_latex_riscv/valzupdate_subrange_bitsb5ffe862b26310b45a779cd45bbf041e.tex @@ -0,0 +1,2 @@ +update_subrange_bits : forall ('n 'm 'o : Int), (0 <= 'o & 'o <= 'm & 'm < 'n). + (bits('n), int('m), int('o), bits('m - ('o - 1))) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzupdate_subrangea3cf2a13bfd32a2a89bc44a498800493.tex b/sail_latex_riscv/valzupdate_subrangea3cf2a13bfd32a2a89bc44a498800493.tex new file mode 100644 index 00000000..e00ccb3a --- /dev/null +++ b/sail_latex_riscv/valzupdate_subrangea3cf2a13bfd32a2a89bc44a498800493.tex @@ -0,0 +1 @@ +update_subrange : forall ('n 'm 'o : Int). (bits('n), int('m), int('o), bits('m - ('o - 1))) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzutype_mnemonic5740211feaadc8d830fd698383ea27eb.tex b/sail_latex_riscv/valzutype_mnemonic5740211feaadc8d830fd698383ea27eb.tex new file mode 100644 index 00000000..e2cb476a --- /dev/null +++ b/sail_latex_riscv/valzutype_mnemonic5740211feaadc8d830fd698383ea27eb.tex @@ -0,0 +1 @@ +utype_mnemonic : uop <-> string \ No newline at end of file diff --git a/sail_latex_riscv/valzvector_concate0e61f7c9864d8d335d1f5c434546f7c.tex b/sail_latex_riscv/valzvector_concate0e61f7c9864d8d335d1f5c434546f7c.tex new file mode 100644 index 00000000..f1832e91 --- /dev/null +++ b/sail_latex_riscv/valzvector_concate0e61f7c9864d8d335d1f5c434546f7c.tex @@ -0,0 +1 @@ +vector_concat : forall ('n 'm : Int)('a : Type). (vector('n, dec, 'a), vector('m, dec, 'a)) -> vector('n + 'm, dec, 'a) \ No newline at end of file diff --git a/sail_latex_riscv/valzvector_length9ee541b308cdfd9738d44bfb3dff4b46.tex b/sail_latex_riscv/valzvector_length9ee541b308cdfd9738d44bfb3dff4b46.tex new file mode 100644 index 00000000..ccbbb261 --- /dev/null +++ b/sail_latex_riscv/valzvector_length9ee541b308cdfd9738d44bfb3dff4b46.tex @@ -0,0 +1 @@ +vector_length : forall ('n : Int)('a : Type). vector('n, dec, 'a) -> int('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzwalk398233e1f75321f48773213830a045bfac.tex b/sail_latex_riscv/valzwalk398233e1f75321f48773213830a045bfac.tex new file mode 100644 index 00000000..a669d58c --- /dev/null +++ b/sail_latex_riscv/valzwalk398233e1f75321f48773213830a045bfac.tex @@ -0,0 +1 @@ +walk39 : (vaddr39, AccessType(ext_access_type), Privilege, bool, bool, paddr64, nat, bool, ext_ptw) -> PTW_Result(paddr64, SV39_PTE) \ No newline at end of file diff --git a/sail_latex_riscv/valzwalk486c4033235ca01e713873e89320a939ac.tex b/sail_latex_riscv/valzwalk486c4033235ca01e713873e89320a939ac.tex new file mode 100644 index 00000000..d353c8af --- /dev/null +++ b/sail_latex_riscv/valzwalk486c4033235ca01e713873e89320a939ac.tex @@ -0,0 +1 @@ +walk48 : (vaddr48, AccessType(ext_access_type), Privilege, bool, bool, paddr64, nat, bool, ext_ptw) -> PTW_Result(paddr64, SV48_PTE) \ No newline at end of file diff --git a/sail_latex_riscv/valzwc721d52ce2fe818d0148aaf1d5b6e2bec.tex b/sail_latex_riscv/valzwc721d52ce2fe818d0148aaf1d5b6e2bec.tex new file mode 100644 index 00000000..a01e8f70 --- /dev/null +++ b/sail_latex_riscv/valzwc721d52ce2fe818d0148aaf1d5b6e2bec.tex @@ -0,0 +1 @@ +wC : forall ('n : Int), (0 <= 'n & 'n < 32). (regno('n), regtype) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzwc_bitsb8b2d4f53308d4bb8d154a1f6664d336.tex b/sail_latex_riscv/valzwc_bitsb8b2d4f53308d4bb8d154a1f6664d336.tex new file mode 100644 index 00000000..074f6775 --- /dev/null +++ b/sail_latex_riscv/valzwc_bitsb8b2d4f53308d4bb8d154a1f6664d336.tex @@ -0,0 +1 @@ +wC_bits : (bits(5), regtype) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzwf_bits141c8aafc4ef81f118d39a00d8a5249d.tex b/sail_latex_riscv/valzwf_bits141c8aafc4ef81f118d39a00d8a5249d.tex new file mode 100644 index 00000000..7224c3b9 --- /dev/null +++ b/sail_latex_riscv/valzwf_bits141c8aafc4ef81f118d39a00d8a5249d.tex @@ -0,0 +1 @@ +wF_bits : (bits(5), flenbits) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzwfd3e403dd75784ce7e0cfdf609e32706e.tex b/sail_latex_riscv/valzwfd3e403dd75784ce7e0cfdf609e32706e.tex new file mode 100644 index 00000000..04505dcb --- /dev/null +++ b/sail_latex_riscv/valzwfd3e403dd75784ce7e0cfdf609e32706e.tex @@ -0,0 +1 @@ +wF : forall ('n : Int), (0 <= 'n & 'n < 32). (regno('n), flenbits) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzwithin_clintc139e042afc9910b6edf55c2c70f2e80.tex b/sail_latex_riscv/valzwithin_clintc139e042afc9910b6edf55c2c70f2e80.tex new file mode 100644 index 00000000..bbfb2681 --- /dev/null +++ b/sail_latex_riscv/valzwithin_clintc139e042afc9910b6edf55c2c70f2e80.tex @@ -0,0 +1 @@ +within_clint : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzwithin_htif_readable2f6131e40985c12d9270943521113c33.tex b/sail_latex_riscv/valzwithin_htif_readable2f6131e40985c12d9270943521113c33.tex new file mode 100644 index 00000000..324e3116 --- /dev/null +++ b/sail_latex_riscv/valzwithin_htif_readable2f6131e40985c12d9270943521113c33.tex @@ -0,0 +1 @@ +within_htif_readable : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzwithin_htif_writablec356d0ea372a60437fdf28745e5e9ae3.tex b/sail_latex_riscv/valzwithin_htif_writablec356d0ea372a60437fdf28745e5e9ae3.tex new file mode 100644 index 00000000..c4d0b8e8 --- /dev/null +++ b/sail_latex_riscv/valzwithin_htif_writablec356d0ea372a60437fdf28745e5e9ae3.tex @@ -0,0 +1 @@ +within_htif_writable : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzwithin_mmio_readable2afaf2bf016b6ead5a5708ec8508d184.tex b/sail_latex_riscv/valzwithin_mmio_readable2afaf2bf016b6ead5a5708ec8508d184.tex new file mode 100644 index 00000000..b292eb46 --- /dev/null +++ b/sail_latex_riscv/valzwithin_mmio_readable2afaf2bf016b6ead5a5708ec8508d184.tex @@ -0,0 +1 @@ +within_mmio_readable : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzwithin_mmio_writable310089204ce2d4e6a33811b1982373ad.tex b/sail_latex_riscv/valzwithin_mmio_writable310089204ce2d4e6a33811b1982373ad.tex new file mode 100644 index 00000000..82b29629 --- /dev/null +++ b/sail_latex_riscv/valzwithin_mmio_writable310089204ce2d4e6a33811b1982373ad.tex @@ -0,0 +1 @@ +within_mmio_writable : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). (xlenbits, int('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzwithin_phys_mem5b6233a64f93394cb594812a945dcbb2.tex b/sail_latex_riscv/valzwithin_phys_mem5b6233a64f93394cb594812a945dcbb2.tex new file mode 100644 index 00000000..31106a78 --- /dev/null +++ b/sail_latex_riscv/valzwithin_phys_mem5b6233a64f93394cb594812a945dcbb2.tex @@ -0,0 +1 @@ +within_phys_mem : forall ('n : Int), 'n <= max_mem_access. (xlenbits, int('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzword_width_bytes3499487c0f03a80d8659fa504a62261f.tex b/sail_latex_riscv/valzword_width_bytes3499487c0f03a80d8659fa504a62261f.tex new file mode 100644 index 00000000..6e1dd7c8 --- /dev/null +++ b/sail_latex_riscv/valzword_width_bytes3499487c0f03a80d8659fa504a62261f.tex @@ -0,0 +1 @@ +word_width_bytes : word_width -> {'s, 's in {1, 2, 4, 8}. int('s)} \ No newline at end of file diff --git a/sail_latex_riscv/valzword_width_of_num5022e9594f19a45eb3d8079a7a770a00.tex b/sail_latex_riscv/valzword_width_of_num5022e9594f19a45eb3d8079a7a770a00.tex new file mode 100644 index 00000000..3be72a7e --- /dev/null +++ b/sail_latex_riscv/valzword_width_of_num5022e9594f19a45eb3d8079a7a770a00.tex @@ -0,0 +1 @@ +word_width_of_num : forall ('e : Int), (0 <= 'e & 'e <= 3). int('e) -> word_width \ No newline at end of file diff --git a/sail_latex_riscv/valzwrite_fflagsf7610eb4597d886b515ad9553608a8d7.tex b/sail_latex_riscv/valzwrite_fflagsf7610eb4597d886b515ad9553608a8d7.tex new file mode 100644 index 00000000..7a8e7474 --- /dev/null +++ b/sail_latex_riscv/valzwrite_fflagsf7610eb4597d886b515ad9553608a8d7.tex @@ -0,0 +1 @@ +write_fflags : bits(5) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzwrite_kind_of_num3c6c37285ad605eea3332f170d5b12d9.tex b/sail_latex_riscv/valzwrite_kind_of_num3c6c37285ad605eea3332f170d5b12d9.tex new file mode 100644 index 00000000..c29fd2e8 --- /dev/null +++ b/sail_latex_riscv/valzwrite_kind_of_num3c6c37285ad605eea3332f170d5b12d9.tex @@ -0,0 +1 @@ +write_kind_of_num : forall ('e : Int), (0 <= 'e & 'e <= 10). int('e) -> write_kind \ No newline at end of file diff --git a/sail_latex_riscv/valzwrite_ram_ea38ee1d0d3a88b7ca22f44ac1921c34c8.tex b/sail_latex_riscv/valzwrite_ram_ea38ee1d0d3a88b7ca22f44ac1921c34c8.tex new file mode 100644 index 00000000..f9f87487 --- /dev/null +++ b/sail_latex_riscv/valzwrite_ram_ea38ee1d0d3a88b7ca22f44ac1921c34c8.tex @@ -0,0 +1 @@ +write_ram_ea : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). (write_kind, xlenbits, int('n)) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzwrite_ramaf59f53ca3a497b3b8d64cf319996fb8.tex b/sail_latex_riscv/valzwrite_ramaf59f53ca3a497b3b8d64cf319996fb8.tex new file mode 100644 index 00000000..d2a7d47a --- /dev/null +++ b/sail_latex_riscv/valzwrite_ramaf59f53ca3a497b3b8d64cf319996fb8.tex @@ -0,0 +1,2 @@ +write_ram : forall ('n : Int), (0 < 'n & 'n <= max_mem_access). + (write_kind, xlenbits, int('n), bits(8 * 'n), mem_meta) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzwrite_tlb39d07866694d7288e6a3cb2ac08a58c288.tex b/sail_latex_riscv/valzwrite_tlb39d07866694d7288e6a3cb2ac08a58c288.tex new file mode 100644 index 00000000..d406d554 --- /dev/null +++ b/sail_latex_riscv/valzwrite_tlb39d07866694d7288e6a3cb2ac08a58c288.tex @@ -0,0 +1 @@ +write_TLB39 : (nat, TLB39_Entry) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzwrite_tlb48c2deeba6fb9156609619ba23dcc84e5a.tex b/sail_latex_riscv/valzwrite_tlb48c2deeba6fb9156609619ba23dcc84e5a.tex new file mode 100644 index 00000000..b5ecd182 --- /dev/null +++ b/sail_latex_riscv/valzwrite_tlb48c2deeba6fb9156609619ba23dcc84e5a.tex @@ -0,0 +1 @@ +write_TLB48 : (nat, TLB48_Entry) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzwritecsr7af48520171f4dd0cd06c1b6876196a7.tex b/sail_latex_riscv/valzwritecsr7af48520171f4dd0cd06c1b6876196a7.tex new file mode 100644 index 00000000..740aa964 --- /dev/null +++ b/sail_latex_riscv/valzwritecsr7af48520171f4dd0cd06c1b6876196a7.tex @@ -0,0 +1 @@ +writeCSR : (csreg, xlenbits) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzwx0042b1ee0bdb45d47dcb45d5a9461882.tex b/sail_latex_riscv/valzwx0042b1ee0bdb45d47dcb45d5a9461882.tex new file mode 100644 index 00000000..d755be43 --- /dev/null +++ b/sail_latex_riscv/valzwx0042b1ee0bdb45d47dcb45d5a9461882.tex @@ -0,0 +1 @@ +wX : forall ('n : Int), (0 <= 'n & 'n < 32). (regno('n), xlenbits) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzwx_bitseb6ef5be72b31b8cb0f1595602665261.tex b/sail_latex_riscv/valzwx_bitseb6ef5be72b31b8cb0f1595602665261.tex new file mode 100644 index 00000000..c3021c0d --- /dev/null +++ b/sail_latex_riscv/valzwx_bitseb6ef5be72b31b8cb0f1595602665261.tex @@ -0,0 +1 @@ +wX_bits : (bits(5), xlenbits) -> unit \ No newline at end of file diff --git a/sail_latex_riscv/valzxor_vecdacd54acc32f073fb01d1c188177bc8c.tex b/sail_latex_riscv/valzxor_vecdacd54acc32f073fb01d1c188177bc8c.tex new file mode 100644 index 00000000..6a07449f --- /dev/null +++ b/sail_latex_riscv/valzxor_vecdacd54acc32f073fb01d1c188177bc8c.tex @@ -0,0 +1 @@ +xor_vec : forall ('n : Int). (bits('n), bits('n)) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/valzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex b/sail_latex_riscv/valzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex new file mode 100644 index 00000000..4248cb4d --- /dev/null +++ b/sail_latex_riscv/valzz8operatorz0zi_sz956bf0eb8f384ccc952f43b53c00f14d1.tex @@ -0,0 +1 @@ +operator <_s : forall ('n : Int), 'n > 0. (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex b/sail_latex_riscv/valzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex new file mode 100644 index 00000000..cbc11d56 --- /dev/null +++ b/sail_latex_riscv/valzz8operatorz0zi_uz975e6e2563e418725e99f2d020a6e269f.tex @@ -0,0 +1 @@ +operator <_u : forall ('n : Int). (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzz8operatorz0zizj_uz99c310fa9a514922f781c01ba7354f99f.tex b/sail_latex_riscv/valzz8operatorz0zizj_uz99c310fa9a514922f781c01ba7354f99f.tex new file mode 100644 index 00000000..4e1c2426 --- /dev/null +++ b/sail_latex_riscv/valzz8operatorz0zizj_uz99c310fa9a514922f781c01ba7354f99f.tex @@ -0,0 +1 @@ +operator <=_u : forall ('n : Int). (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex b/sail_latex_riscv/valzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex new file mode 100644 index 00000000..28d0949c --- /dev/null +++ b/sail_latex_riscv/valzz8operatorz0zkzj_sz904d1eed458afb5704c50166298da928d.tex @@ -0,0 +1 @@ +operator >=_s : forall ('n : Int), 'n > 0. (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex b/sail_latex_riscv/valzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex new file mode 100644 index 00000000..a3bf84fd --- /dev/null +++ b/sail_latex_riscv/valzz8operatorz0zkzj_uz932ccbf178c78f699a55ad5e4e3db033c.tex @@ -0,0 +1 @@ +operator >=_u : forall ('n : Int). (bits('n), bits('n)) -> bool \ No newline at end of file diff --git a/sail_latex_riscv/valzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex b/sail_latex_riscv/valzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex new file mode 100644 index 00000000..5ed1e1f4 --- /dev/null +++ b/sail_latex_riscv/valzzzeros_implicitce1dd4153c9a1823a9697c4472c43ebf.tex @@ -0,0 +1 @@ +zeros_implicit : forall ('n : Int), 'n >= 0. implicit('n) -> bits('n) \ No newline at end of file diff --git a/sail_latex_riscv/zGENERATED_FILES_DO_NOT_EDIT b/sail_latex_riscv/zGENERATED_FILES_DO_NOT_EDIT new file mode 100644 index 00000000..e69de29b