CHERI Specification for RISC-V Vector Extension

[andresag01]

Is there a specification describing how CHERI integrates with the RISC-V vector extension?

[andresag01]

The vector extension is mostly orthogonal to CHERI, but software may use vector to perform memcpy-like operations; these must work when CHERI is used. As discussed, the proposal is as follows:

• Extend vector register file with tags that are cleared at reset
• It is required that VLEN >= CLEN
  • There will be VLEN / CLEN tag bits associated with each vector register
• There are two new memory access (load and store) vector instructions that copy the tags from/to memory. The new load and store vector instructions:
  • Behave as unit-stride memory accesses
  • Respect the CHERI mode in PCC
  • Must atomically copy the tag and data in CLEN chunks
  • Perform sealing, tag, bounds, etc as usual on the authorising capability
  • Clear the tag of all capabilities if the load/store is not aligned to CLEN
  • Clear the tag of capabilities partially loaded/stored due to vstart and vector length
  • Do not support masking and fault-only-first
  • New instruction encodings are mnemonics are to be decided.
• Whole vector-vector move instructions (vmv<nr>r.v) copy the tags
• All other vector instructions clear the tag bits in all cases