Xtval capability index on ASR exception for RISC-V

[andresag01]

The Sail implementation of CSpecialRW checks that the ASR permission is set in PCC when accessing select CSRs/SCRs:

} else if (needASR & not(pcc_access_system_regs())) then {
  handle_cheri_cap_exception(CapEx_AccessSystemRegsViolation, 0b1 @ scr);
  RETIRE_FAIL
} else {

According to line 2 above, the “register” index written to Xtval is 0b1 @ scr when the ASR check fails. This is really strange for a a few reasons:

• The register index in Xtval is normally the register with the authorising capability that failed a check; 0b1 @ scr is something else!
• I was assuming the return value for ASR exceptions for the RISC-V CSR instructions is always PCC because that is the authorising capability. In any case, we would need 12 bits to encode into Xtval in this case if we were to follow the same pattern, but I think only some 5 bits are currently allocated to the register index.

Ideally we would make CSpecialRW also output PCC in ASR trap.

[arichardson]

I agree that this seems like a bug, PCC is the authorizing capability for this instruction so should be reported in tval.