diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index b834006e8a..5d34744bf2 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -32,6 +32,7 @@ #include "exec/tb-hash.h" #include "exec/tb-lookup.h" #include "exec/log.h" +#include "exec/log_instr.h" #include "qemu/main-loop.h" #if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) #include "hw/i386/apic.h" @@ -488,7 +489,12 @@ static inline void cpu_handle_debug_exception(CPUState *cpu) wp->flags &= ~BP_WATCHPOINT_HIT; } } - + /* Print the current (aborted) instruction. */ + if (qemu_log_instr_enabled(cpu->env_ptr)) { + qemu_log_instr_commit(cpu->env_ptr); + /* Add a "fake" instruction for the exception side effects. */ + qemu_log_instr(cpu->env_ptr, ~(target_ulong)0, "", 0); + } cc->debug_excp_handler(cpu); } @@ -532,6 +538,12 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret) if (replay_exception()) { CPUClass *cc = CPU_GET_CLASS(cpu); qemu_mutex_lock_iothread(); + if (qemu_log_instr_enabled(cpu->env_ptr)) { + /* Print the current (aborted) instruction. */ + qemu_log_instr_commit(cpu->env_ptr); + /* Add a "fake" instruction for the exception side effects. */ + qemu_log_instr(cpu->env_ptr, ~(target_ulong)0, "", 0); + } cc->do_interrupt(cpu); qemu_mutex_unlock_iothread(); cpu->exception_index = -1; diff --git a/accel/tcg/log_instr.c b/accel/tcg/log_instr.c index d454eeda7b..835aae1222 100644 --- a/accel/tcg/log_instr.c +++ b/accel/tcg/log_instr.c @@ -349,8 +349,12 @@ static void emit_text_entry(CPUArchState *env, cpu_log_instr_info_t *iinfo) rcu_read_lock(); logfile = qatomic_rcu_read(&qemu_logfile); if (logfile) { - target_disas_buf(logfile->fd, env_cpu(env), iinfo->insn_bytes, - sizeof(iinfo->insn_bytes), iinfo->pc, 1); + if (iinfo->insn_size < 1) { + fprintf(logfile->fd, "logging exception side effects\n"); + } else { + target_disas_buf(logfile->fd, env_cpu(env), iinfo->insn_bytes, + sizeof(iinfo->insn_bytes), iinfo->pc, 1); + } } rcu_read_unlock(); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4b2518543b..35966951a7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -892,8 +892,10 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, if (access_type == MMU_DATA_STORE) { cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; - } else { + } else if (access_type == MMU_DATA_LOAD) { cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; + } else { + cs->exception_index = RISCV_EXCP_INST_ACCESS_FAULT; } env->badaddr = addr; @@ -1188,7 +1190,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, void riscv_cpu_do_interrupt(CPUState *cs) { #if !defined(CONFIG_USER_ONLY) - RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; tcg_debug_assert(pc_is_current(env)); @@ -1222,10 +1223,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_LOAD_CAP_PAGE_FAULT: case RISCV_EXCP_STORE_AMO_CAP_PAGE_FAULT: #endif - log_inst = false; - /* fallthrough */ case RISCV_EXCP_INST_ADDR_MIS: case RISCV_EXCP_INST_ACCESS_FAULT: + log_inst = false; + /* fallthrough */ case RISCV_EXCP_LOAD_ADDR_MIS: case RISCV_EXCP_STORE_AMO_ADDR_MIS: case RISCV_EXCP_LOAD_ACCESS_FAULT: @@ -1277,7 +1278,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (unlikely(log_inst && qemu_loglevel_mask(CPU_LOG_INT))) { FILE* logf = qemu_log_lock(); - qemu_log("Trap (%s) was probably caused by: ", riscv_cpu_get_trap_name(cause, async)); + fprintf(logf, "Trap (%s) was probably caused by: ", riscv_cpu_get_trap_name(cause, async)); target_disas(logf, cs, PC_ADDR(env), /* Only one instr*/-1); qemu_log_unlock(logf); }