diff --git a/.gitignore b/.gitignore index 10f0849..ebc3864 100644 --- a/.gitignore +++ b/.gitignore @@ -1,8 +1,8 @@ -CHERI_Gen_Lemmas.thy -CHERI_Cap_Properties.thy -CHERI_Mem_Properties.thy -CHERI_Fetch_Properties.thy -CHERI_Invariant.thy +# CHERI_Gen_Lemmas.thy +# CHERI_Cap_Properties.thy +# CHERI_Mem_Properties.thy +# CHERI_Fetch_Properties.thy +# CHERI_Invariant.thy *.thy~ *.smt2 z3_problems diff --git a/CHERI_Cap_Properties.thy b/CHERI_Cap_Properties.thy new file mode 100644 index 0000000..78c4737 --- /dev/null +++ b/CHERI_Cap_Properties.thy @@ -0,0 +1,13864 @@ +section \Generated instruction monotonicity proofs\ + +theory CHERI_Cap_Properties +imports CHERI_Lemmas +begin + +context Morello_Instr_Write_Cap_Automaton +begin + +lemma traces_enabled_write_regs[traces_enabledI]: + "\c. c \ derivable_caps s \ system_reg_access s \ traces_enabled (write_reg CDBGDTR_EL0_ref c) s" + "\c. c \ derivable_caps s \ system_reg_access s \ traces_enabled (write_reg CDLR_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg CID_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg DDC_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg DDC_EL1_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg DDC_EL2_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg DDC_EL3_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg ELR_EL1_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg ELR_EL2_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg ELR_EL3_ref c) s" + "\v. system_reg_access s \ traces_enabled (write_reg MAIR_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MAIR_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MAIR_EL3_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAM0_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAM3_EL3_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMHCR_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMIDR_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM0_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM1_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM2_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM3_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM4_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM5_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM6_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM7_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPMV_EL2_ref v) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg PCC_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg RDDC_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg RSP_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg RTPIDR_EL0_ref c) s" + "\v. system_reg_access s \ traces_enabled (write_reg SCR_EL3_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg SCTLR_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg SCTLR_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg SCTLR_EL3_ref v) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg SP_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg SP_EL1_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg SP_EL2_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg SP_EL3_ref c) s" + "\v. system_reg_access s \ traces_enabled (write_reg TCR_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg TCR_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg TCR_EL3_ref v) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg TPIDRRO_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg TPIDR_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg TPIDR_EL1_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg TPIDR_EL2_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg TPIDR_EL3_ref c) s" + "\v. system_reg_access s \ traces_enabled (write_reg TTBR0_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg TTBR0_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg TTBR0_EL3_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg TTBR1_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg TTBR1_EL2_ref v) s" + "\c. c \ derivable_caps s \ system_reg_access s \ traces_enabled (write_reg VBAR_EL1_ref c) s" + "\c. c \ derivable_caps s \ system_reg_access s \ traces_enabled (write_reg VBAR_EL2_ref c) s" + "\c. c \ derivable_caps s \ system_reg_access s \ traces_enabled (write_reg VBAR_EL3_ref c) s" + "\v. system_reg_access s \ traces_enabled (write_reg VTCR_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg VTTBR_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAM1_EL1_0_62_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAM2_EL2_0_62_ref v) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R00_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R01_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R02_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R03_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R04_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R05_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R06_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R07_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R08_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R09_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R10_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R11_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R12_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R13_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R14_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R15_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R16_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R17_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R18_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R19_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R20_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R21_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R22_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R23_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R24_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R25_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R26_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R27_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R28_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R29_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R30_ref c) s" + by (intro traces_enabled_write_reg; auto simp: register_defs derivable_caps_def)+ + +lemma traces_enabled_read_regs[traces_enabledI]: + "system_reg_access s \ traces_enabled (read_reg CDBGDTR_EL0_ref) s" + "system_reg_access s \ traces_enabled (read_reg CDLR_EL0_ref) s" + "traces_enabled (read_reg CID_EL0_ref) s" + "traces_enabled (read_reg DDC_EL0_ref) s" + "traces_enabled (read_reg DDC_EL1_ref) s" + "traces_enabled (read_reg DDC_EL2_ref) s" + "traces_enabled (read_reg DDC_EL3_ref) s" + "traces_enabled (read_reg ELR_EL1_ref) s" + "traces_enabled (read_reg ELR_EL2_ref) s" + "traces_enabled (read_reg ELR_EL3_ref) s" + "traces_enabled (read_reg PCC_ref) s" + "traces_enabled (read_reg RDDC_EL0_ref) s" + "traces_enabled (read_reg RSP_EL0_ref) s" + "traces_enabled (read_reg RTPIDR_EL0_ref) s" + "traces_enabled (read_reg SP_EL0_ref) s" + "traces_enabled (read_reg SP_EL1_ref) s" + "traces_enabled (read_reg SP_EL2_ref) s" + "traces_enabled (read_reg SP_EL3_ref) s" + "traces_enabled (read_reg TPIDRRO_EL0_ref) s" + "traces_enabled (read_reg TPIDR_EL0_ref) s" + "traces_enabled (read_reg TPIDR_EL1_ref) s" + "traces_enabled (read_reg TPIDR_EL2_ref) s" + "traces_enabled (read_reg TPIDR_EL3_ref) s" + "system_reg_access s \ ex_traces \ traces_enabled (read_reg VBAR_EL1_ref) s" + "system_reg_access s \ ex_traces \ traces_enabled (read_reg VBAR_EL2_ref) s" + "system_reg_access s \ ex_traces \ traces_enabled (read_reg VBAR_EL3_ref) s" + "traces_enabled (read_reg R00_ref) s" + "traces_enabled (read_reg R01_ref) s" + "traces_enabled (read_reg R02_ref) s" + "traces_enabled (read_reg R03_ref) s" + "traces_enabled (read_reg R04_ref) s" + "traces_enabled (read_reg R05_ref) s" + "traces_enabled (read_reg R06_ref) s" + "traces_enabled (read_reg R07_ref) s" + "traces_enabled (read_reg R08_ref) s" + "traces_enabled (read_reg R09_ref) s" + "traces_enabled (read_reg R10_ref) s" + "traces_enabled (read_reg R11_ref) s" + "traces_enabled (read_reg R12_ref) s" + "traces_enabled (read_reg R13_ref) s" + "traces_enabled (read_reg R14_ref) s" + "traces_enabled (read_reg R15_ref) s" + "traces_enabled (read_reg R16_ref) s" + "traces_enabled (read_reg R17_ref) s" + "traces_enabled (read_reg R18_ref) s" + "traces_enabled (read_reg R19_ref) s" + "traces_enabled (read_reg R20_ref) s" + "traces_enabled (read_reg R21_ref) s" + "traces_enabled (read_reg R22_ref) s" + "traces_enabled (read_reg R23_ref) s" + "traces_enabled (read_reg R24_ref) s" + "traces_enabled (read_reg R25_ref) s" + "traces_enabled (read_reg R26_ref) s" + "traces_enabled (read_reg R27_ref) s" + "traces_enabled (read_reg R28_ref) s" + "traces_enabled (read_reg R29_ref) s" + "traces_enabled (read_reg R30_ref) s" + by (intro traces_enabled_read_reg; auto simp: register_defs)+ + + +lemmas non_cap_exp_traces_enabled[traces_enabledI] = non_cap_expI[THEN non_cap_exp_traces_enabledI] + + +lemma traces_enabled_R_read[traces_enabledI]: + "traces_enabled (R_read idx) s" + unfolding R_read_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_R_set[traces_enabledI]: + assumes "c__arg \ derivable_caps s" + shows "traces_enabled (R_set idx c__arg) s" + unfolding R_set_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_BranchTo[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (BranchTo target branch_type) s" + unfolding BranchTo_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_BranchToCapability[traces_enabledI]: + assumes "target \ derivable_caps s" + shows "traces_enabled (BranchToCapability target branch_type) s" + unfolding BranchToCapability_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CELR_set[traces_enabledI]: + assumes "value_name \ derivable_caps s" + shows "traces_enabled (CELR_set el value_name) s" + unfolding CELR_set_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CELR_set__1[traces_enabledI]: + assumes "value_name \ derivable_caps s" + shows "traces_enabled (CELR_set__1 value_name) s" + unfolding CELR_set__1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVBAR_read[traces_enabledI]: + assumes "{''VBAR_EL1'', ''VBAR_EL2'', ''VBAR_EL3''} \ accessible_regs s \ ex_traces" + shows "traces_enabled (CVBAR_read regime) s" + unfolding CVBAR_read_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVBAR_read__1[traces_enabledI]: + assumes "{''VBAR_EL1'', ''VBAR_EL2'', ''VBAR_EL3''} \ accessible_regs s \ ex_traces" + shows "traces_enabled (CVBAR_read__1 arg0) s" + unfolding CVBAR_read__1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ELR_set[traces_enabledI]: + "traces_enabled (ELR_set el value_name) s" + unfolding ELR_set_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ELR_set__1[traces_enabledI]: + "traces_enabled (ELR_set__1 value_name) s" + unfolding ELR_set__1_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_PCC_read[traces_enabledI]: + "traces_enabled (PCC_read arg0) s" + unfolding PCC_read_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_IsInRestricted[traces_enabledI]: + "traces_enabled (IsInRestricted arg0) s" + unfolding IsInRestricted_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_VBAR_read[traces_enabledI]: + assumes "{''VBAR_EL1'', ''VBAR_EL2'', ''VBAR_EL3''} \ accessible_regs s \ ex_traces" + shows "traces_enabled (VBAR_read regime) s" + unfolding VBAR_read_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VBAR_read__1[traces_enabledI]: + assumes "{''VBAR_EL1'', ''VBAR_EL2'', ''VBAR_EL3''} \ accessible_regs s \ ex_traces" + shows "traces_enabled (VBAR_read__1 arg0) s" + unfolding VBAR_read__1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_TakeException[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_TakeException target_el exception preferred_exception_return vect_offset__arg) s" + by (rule AArch64_TakeException_raises_isa_ex[THEN exp_raises_ex_traces_enabled], unfold AArch64_TakeException_def bind_assoc, traces_enabledI assms: assms elim: CapSetValue_exception_target_enabled_branch_target) + +lemma traces_enabled_AArch64_SystemAccessTrap[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_SystemAccessTrap target_el ec) s" + unfolding AArch64_SystemAccessTrap_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CapIsSystemAccessEnabled[traces_enabledI]: + "traces_enabled (CapIsSystemAccessEnabled arg0) s" + unfolding CapIsSystemAccessEnabled_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ACTLR_EL1_SysRegRead_56bd4d0367c16236[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ACTLR_EL1_SysRegRead_56bd4d0367c16236 el op0 op1 CRn op2 CRm) s" + unfolding ACTLR_EL1_SysRegRead_56bd4d0367c16236_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ACTLR_EL2_SysRegRead_ff23cef1b670b9c7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ACTLR_EL2_SysRegRead_ff23cef1b670b9c7 el op0 op1 CRn op2 CRm) s" + unfolding ACTLR_EL2_SysRegRead_ff23cef1b670b9c7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ACTLR_EL3_SysRegRead_397e6c0342e2936b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ACTLR_EL3_SysRegRead_397e6c0342e2936b el op0 op1 CRn op2 CRm) s" + unfolding ACTLR_EL3_SysRegRead_397e6c0342e2936b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR0_EL12_SysRegRead_2488de32a3f38621[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR0_EL12_SysRegRead_2488de32a3f38621 el op0 op1 CRn op2 CRm) s" + unfolding AFSR0_EL12_SysRegRead_2488de32a3f38621_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR0_EL1_SysRegRead_80a4a0472e0b9142[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR0_EL1_SysRegRead_80a4a0472e0b9142 el op0 op1 CRn op2 CRm) s" + unfolding AFSR0_EL1_SysRegRead_80a4a0472e0b9142_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR0_EL2_SysRegRead_07613e9c4b98061a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR0_EL2_SysRegRead_07613e9c4b98061a el op0 op1 CRn op2 CRm) s" + unfolding AFSR0_EL2_SysRegRead_07613e9c4b98061a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR0_EL3_SysRegRead_d2e69d7912ca200c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR0_EL3_SysRegRead_d2e69d7912ca200c el op0 op1 CRn op2 CRm) s" + unfolding AFSR0_EL3_SysRegRead_d2e69d7912ca200c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR1_EL12_SysRegRead_39bb62021df07ecc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR1_EL12_SysRegRead_39bb62021df07ecc el op0 op1 CRn op2 CRm) s" + unfolding AFSR1_EL12_SysRegRead_39bb62021df07ecc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR1_EL1_SysRegRead_495927b72173c55f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR1_EL1_SysRegRead_495927b72173c55f el op0 op1 CRn op2 CRm) s" + unfolding AFSR1_EL1_SysRegRead_495927b72173c55f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR1_EL2_SysRegRead_f7cb9a59387f268f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR1_EL2_SysRegRead_f7cb9a59387f268f el op0 op1 CRn op2 CRm) s" + unfolding AFSR1_EL2_SysRegRead_f7cb9a59387f268f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR1_EL3_SysRegRead_a2ad736ad599f2b2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR1_EL3_SysRegRead_a2ad736ad599f2b2 el op0 op1 CRn op2 CRm) s" + unfolding AFSR1_EL3_SysRegRead_a2ad736ad599f2b2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AIDR_EL1_SysRegRead_74ea31b1dc6f5c6f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AIDR_EL1_SysRegRead_74ea31b1dc6f5c6f el op0 op1 CRn op2 CRm) s" + unfolding AIDR_EL1_SysRegRead_74ea31b1dc6f5c6f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AMAIR_EL12_SysRegRead_87964a33cc1ad0ef[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AMAIR_EL12_SysRegRead_87964a33cc1ad0ef el op0 op1 CRn op2 CRm) s" + unfolding AMAIR_EL12_SysRegRead_87964a33cc1ad0ef_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AMAIR_EL1_SysRegRead_82d01d3808e04ca3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AMAIR_EL1_SysRegRead_82d01d3808e04ca3 el op0 op1 CRn op2 CRm) s" + unfolding AMAIR_EL1_SysRegRead_82d01d3808e04ca3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AMAIR_EL2_SysRegRead_3c316bb11b239640[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AMAIR_EL2_SysRegRead_3c316bb11b239640 el op0 op1 CRn op2 CRm) s" + unfolding AMAIR_EL2_SysRegRead_3c316bb11b239640_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AMAIR_EL3_SysRegRead_b1547f511477c529[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AMAIR_EL3_SysRegRead_b1547f511477c529 el op0 op1 CRn op2 CRm) s" + unfolding AMAIR_EL3_SysRegRead_b1547f511477c529_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CCSIDR_EL1_SysRegRead_210f94b423761d0b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CCSIDR_EL1_SysRegRead_210f94b423761d0b el op0 op1 CRn op2 CRm) s" + unfolding CCSIDR_EL1_SysRegRead_210f94b423761d0b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CCTLR_EL0_SysRegRead_3baa7e22d96a4ce4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CCTLR_EL0_SysRegRead_3baa7e22d96a4ce4 el op0 op1 CRn op2 CRm) s" + unfolding CCTLR_EL0_SysRegRead_3baa7e22d96a4ce4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CCTLR_EL12_SysRegRead_e8b17aabd47dc7a1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CCTLR_EL12_SysRegRead_e8b17aabd47dc7a1 el op0 op1 CRn op2 CRm) s" + unfolding CCTLR_EL12_SysRegRead_e8b17aabd47dc7a1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CCTLR_EL1_SysRegRead_de402a061eecb9b9[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CCTLR_EL1_SysRegRead_de402a061eecb9b9 el op0 op1 CRn op2 CRm) s" + unfolding CCTLR_EL1_SysRegRead_de402a061eecb9b9_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CCTLR_EL2_SysRegRead_fca4364f27bb9f9b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CCTLR_EL2_SysRegRead_fca4364f27bb9f9b el op0 op1 CRn op2 CRm) s" + unfolding CCTLR_EL2_SysRegRead_fca4364f27bb9f9b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CCTLR_EL3_SysRegRead_9121a22ebc361586[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CCTLR_EL3_SysRegRead_9121a22ebc361586 el op0 op1 CRn op2 CRm) s" + unfolding CCTLR_EL3_SysRegRead_9121a22ebc361586_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CHCR_EL2_SysRegRead_7d3c39a46321f1a2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CHCR_EL2_SysRegRead_7d3c39a46321f1a2 el op0 op1 CRn op2 CRm) s" + unfolding CHCR_EL2_SysRegRead_7d3c39a46321f1a2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CLIDR_EL1_SysRegRead_b403ddc99e97c3a8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CLIDR_EL1_SysRegRead_b403ddc99e97c3a8 el op0 op1 CRn op2 CRm) s" + unfolding CLIDR_EL1_SysRegRead_b403ddc99e97c3a8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTFRQ_EL0_SysRegRead_891ca00adf0c3783[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTFRQ_EL0_SysRegRead_891ca00adf0c3783 el op0 op1 CRn op2 CRm) s" + unfolding CNTFRQ_EL0_SysRegRead_891ca00adf0c3783_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHCTL_EL2_SysRegRead_5f510d633361c720[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHCTL_EL2_SysRegRead_5f510d633361c720 el op0 op1 CRn op2 CRm) s" + unfolding CNTHCTL_EL2_SysRegRead_5f510d633361c720_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHP_CTL_EL2_SysRegRead_7103e47839f2c66b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHP_CTL_EL2_SysRegRead_7103e47839f2c66b el op0 op1 CRn op2 CRm) s" + unfolding CNTHP_CTL_EL2_SysRegRead_7103e47839f2c66b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHP_CVAL_EL2_SysRegRead_e25a0257128c640b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHP_CVAL_EL2_SysRegRead_e25a0257128c640b el op0 op1 CRn op2 CRm) s" + unfolding CNTHP_CVAL_EL2_SysRegRead_e25a0257128c640b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHP_TVAL_EL2_SysRegRead_d110a1f1616c9f8f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHP_TVAL_EL2_SysRegRead_d110a1f1616c9f8f el op0 op1 CRn op2 CRm) s" + unfolding CNTHP_TVAL_EL2_SysRegRead_d110a1f1616c9f8f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHV_CTL_EL2_SysRegRead_bc429f3d6b52b800[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHV_CTL_EL2_SysRegRead_bc429f3d6b52b800 el op0 op1 CRn op2 CRm) s" + unfolding CNTHV_CTL_EL2_SysRegRead_bc429f3d6b52b800_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHV_CVAL_EL2_SysRegRead_2c78392b89702ca9[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHV_CVAL_EL2_SysRegRead_2c78392b89702ca9 el op0 op1 CRn op2 CRm) s" + unfolding CNTHV_CVAL_EL2_SysRegRead_2c78392b89702ca9_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHV_TVAL_EL2_SysRegRead_2464c0e91db55a22[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHV_TVAL_EL2_SysRegRead_2464c0e91db55a22 el op0 op1 CRn op2 CRm) s" + unfolding CNTHV_TVAL_EL2_SysRegRead_2464c0e91db55a22_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTKCTL_EL12_SysRegRead_c23def3111264258[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTKCTL_EL12_SysRegRead_c23def3111264258 el op0 op1 CRn op2 CRm) s" + unfolding CNTKCTL_EL12_SysRegRead_c23def3111264258_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTKCTL_EL1_SysRegRead_6a6cc900bc3c37df[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTKCTL_EL1_SysRegRead_6a6cc900bc3c37df el op0 op1 CRn op2 CRm) s" + unfolding CNTKCTL_EL1_SysRegRead_6a6cc900bc3c37df_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTPCT_EL0_SysRegRead_579be4c9ef4e6824[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTPCT_EL0_SysRegRead_579be4c9ef4e6824 el op0 op1 CRn op2 CRm) s" + unfolding CNTPCT_EL0_SysRegRead_579be4c9ef4e6824_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTPS_CTL_EL1_SysRegRead_e3bc6e5891147388[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTPS_CTL_EL1_SysRegRead_e3bc6e5891147388 el op0 op1 CRn op2 CRm) s" + unfolding CNTPS_CTL_EL1_SysRegRead_e3bc6e5891147388_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTPS_CVAL_EL1_SysRegRead_3e364bd573c45cae[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTPS_CVAL_EL1_SysRegRead_3e364bd573c45cae el op0 op1 CRn op2 CRm) s" + unfolding CNTPS_CVAL_EL1_SysRegRead_3e364bd573c45cae_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTPS_TVAL_EL1_SysRegRead_0784a7de0899eff0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTPS_TVAL_EL1_SysRegRead_0784a7de0899eff0 el op0 op1 CRn op2 CRm) s" + unfolding CNTPS_TVAL_EL1_SysRegRead_0784a7de0899eff0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTP_CTL_EL02_SysRegRead_9d9930274ff7fc36[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTP_CTL_EL02_SysRegRead_9d9930274ff7fc36 el op0 op1 CRn op2 CRm) s" + unfolding CNTP_CTL_EL02_SysRegRead_9d9930274ff7fc36_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTP_CTL_EL0_SysRegRead_47237e002d686ac6[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTP_CTL_EL0_SysRegRead_47237e002d686ac6 el op0 op1 CRn op2 CRm) s" + unfolding CNTP_CTL_EL0_SysRegRead_47237e002d686ac6_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTP_CVAL_EL02_SysRegRead_8377305437cbebb4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTP_CVAL_EL02_SysRegRead_8377305437cbebb4 el op0 op1 CRn op2 CRm) s" + unfolding CNTP_CVAL_EL02_SysRegRead_8377305437cbebb4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTP_CVAL_EL0_SysRegRead_4db28ae745612584[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTP_CVAL_EL0_SysRegRead_4db28ae745612584 el op0 op1 CRn op2 CRm) s" + unfolding CNTP_CVAL_EL0_SysRegRead_4db28ae745612584_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTP_TVAL_EL02_SysRegRead_6539005e4eb68283[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTP_TVAL_EL02_SysRegRead_6539005e4eb68283 el op0 op1 CRn op2 CRm) s" + unfolding CNTP_TVAL_EL02_SysRegRead_6539005e4eb68283_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTP_TVAL_EL0_SysRegRead_54cebb7fbc71b9db[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTP_TVAL_EL0_SysRegRead_54cebb7fbc71b9db el op0 op1 CRn op2 CRm) s" + unfolding CNTP_TVAL_EL0_SysRegRead_54cebb7fbc71b9db_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTVCT_EL0_SysRegRead_cd7c8aebed2715e6[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTVCT_EL0_SysRegRead_cd7c8aebed2715e6 el op0 op1 CRn op2 CRm) s" + unfolding CNTVCT_EL0_SysRegRead_cd7c8aebed2715e6_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTVOFF_EL2_SysRegRead_5ca7336b54f14c06[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTVOFF_EL2_SysRegRead_5ca7336b54f14c06 el op0 op1 CRn op2 CRm) s" + unfolding CNTVOFF_EL2_SysRegRead_5ca7336b54f14c06_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTV_CTL_EL02_SysRegRead_4188a8e2bc5c07aa[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTV_CTL_EL02_SysRegRead_4188a8e2bc5c07aa el op0 op1 CRn op2 CRm) s" + unfolding CNTV_CTL_EL02_SysRegRead_4188a8e2bc5c07aa_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTV_CTL_EL0_SysRegRead_bcb2d1b80bdb9c23[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTV_CTL_EL0_SysRegRead_bcb2d1b80bdb9c23 el op0 op1 CRn op2 CRm) s" + unfolding CNTV_CTL_EL0_SysRegRead_bcb2d1b80bdb9c23_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTV_CVAL_EL02_SysRegRead_abd2b9f314cb85b2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTV_CVAL_EL02_SysRegRead_abd2b9f314cb85b2 el op0 op1 CRn op2 CRm) s" + unfolding CNTV_CVAL_EL02_SysRegRead_abd2b9f314cb85b2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTV_CVAL_EL0_SysRegRead_54d5eb0bec99456f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTV_CVAL_EL0_SysRegRead_54d5eb0bec99456f el op0 op1 CRn op2 CRm) s" + unfolding CNTV_CVAL_EL0_SysRegRead_54d5eb0bec99456f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTV_TVAL_EL02_SysRegRead_f904ccdf39aea128[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTV_TVAL_EL02_SysRegRead_f904ccdf39aea128 el op0 op1 CRn op2 CRm) s" + unfolding CNTV_TVAL_EL02_SysRegRead_f904ccdf39aea128_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTV_TVAL_EL0_SysRegRead_919e73a694090e48[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTV_TVAL_EL0_SysRegRead_919e73a694090e48 el op0 op1 CRn op2 CRm) s" + unfolding CNTV_TVAL_EL0_SysRegRead_919e73a694090e48_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CONTEXTIDR_EL12_SysRegRead_2aa676fc0cfd631b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CONTEXTIDR_EL12_SysRegRead_2aa676fc0cfd631b el op0 op1 CRn op2 CRm) s" + unfolding CONTEXTIDR_EL12_SysRegRead_2aa676fc0cfd631b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CONTEXTIDR_EL1_SysRegRead_fa54232c55ea14e3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CONTEXTIDR_EL1_SysRegRead_fa54232c55ea14e3 el op0 op1 CRn op2 CRm) s" + unfolding CONTEXTIDR_EL1_SysRegRead_fa54232c55ea14e3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CONTEXTIDR_EL2_SysRegRead_f7bf9114ce3113a6[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CONTEXTIDR_EL2_SysRegRead_f7bf9114ce3113a6 el op0 op1 CRn op2 CRm) s" + unfolding CONTEXTIDR_EL2_SysRegRead_f7bf9114ce3113a6_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CPACR_EL12_SysRegRead_0f7867518c4e8e99[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CPACR_EL12_SysRegRead_0f7867518c4e8e99 el op0 op1 CRn op2 CRm) s" + unfolding CPACR_EL12_SysRegRead_0f7867518c4e8e99_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CPACR_EL1_SysRegRead_63b8f196f3ebba22[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CPACR_EL1_SysRegRead_63b8f196f3ebba22 el op0 op1 CRn op2 CRm) s" + unfolding CPACR_EL1_SysRegRead_63b8f196f3ebba22_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CPTR_EL2_SysRegRead_d80843789adc6a43[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CPTR_EL2_SysRegRead_d80843789adc6a43 el op0 op1 CRn op2 CRm) s" + unfolding CPTR_EL2_SysRegRead_d80843789adc6a43_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CPTR_EL3_SysRegRead_33cb1e5ec3c99661[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CPTR_EL3_SysRegRead_33cb1e5ec3c99661 el op0 op1 CRn op2 CRm) s" + unfolding CPTR_EL3_SysRegRead_33cb1e5ec3c99661_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CSCR_EL3_SysRegRead_3c6b19768f9cd209[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CSCR_EL3_SysRegRead_3c6b19768f9cd209 el op0 op1 CRn op2 CRm) s" + unfolding CSCR_EL3_SysRegRead_3c6b19768f9cd209_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CSSELR_EL1_SysRegRead_102b4cddc07c9121[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CSSELR_EL1_SysRegRead_102b4cddc07c9121 el op0 op1 CRn op2 CRm) s" + unfolding CSSELR_EL1_SysRegRead_102b4cddc07c9121_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CTR_EL0_SysRegRead_54ef8c769c3c6bba[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CTR_EL0_SysRegRead_54ef8c769c3c6bba el op0 op1 CRn op2 CRm) s" + unfolding CTR_EL0_SysRegRead_54ef8c769c3c6bba_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DACR32_EL2_SysRegRead_9571e2946627a596[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DACR32_EL2_SysRegRead_9571e2946627a596 el op0 op1 CRn op2 CRm) s" + unfolding DACR32_EL2_SysRegRead_9571e2946627a596_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DAIF_SysRegRead_198f3b46fcf6c8f0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DAIF_SysRegRead_198f3b46fcf6c8f0 el op0 op1 CRn op2 CRm) s" + unfolding DAIF_SysRegRead_198f3b46fcf6c8f0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGAUTHSTATUS_EL1_SysRegRead_6ade6e7a5265bcb7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGAUTHSTATUS_EL1_SysRegRead_6ade6e7a5265bcb7 el op0 op1 CRn op2 CRm) s" + unfolding DBGAUTHSTATUS_EL1_SysRegRead_6ade6e7a5265bcb7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_Halt[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "system_reg_access s" + shows "traces_enabled (Halt reason) s" + unfolding Halt_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGBCR_EL1_SysRegRead_2d021994672d40d3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGBCR_EL1_SysRegRead_2d021994672d40d3 el op0 op1 CRn op2 CRm) s" + unfolding DBGBCR_EL1_SysRegRead_2d021994672d40d3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGBVR_EL1_SysRegRead_dc4a8f61b400622f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGBVR_EL1_SysRegRead_dc4a8f61b400622f el op0 op1 CRn op2 CRm) s" + unfolding DBGBVR_EL1_SysRegRead_dc4a8f61b400622f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGCLAIMCLR_EL1_SysRegRead_72ae03c1d5f667da[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGCLAIMCLR_EL1_SysRegRead_72ae03c1d5f667da el op0 op1 CRn op2 CRm) s" + unfolding DBGCLAIMCLR_EL1_SysRegRead_72ae03c1d5f667da_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGCLAIMSET_EL1_SysRegRead_8557cf3b6272a9e8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGCLAIMSET_EL1_SysRegRead_8557cf3b6272a9e8 el op0 op1 CRn op2 CRm) s" + unfolding DBGCLAIMSET_EL1_SysRegRead_8557cf3b6272a9e8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGDTRRX_EL0_SysRegRead_e7b48d8296f3b86b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGDTRRX_EL0_SysRegRead_e7b48d8296f3b86b el op0 op1 CRn op2 CRm) s" + unfolding DBGDTRRX_EL0_SysRegRead_e7b48d8296f3b86b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGDTR_EL0_read__1[traces_enabledI]: + assumes "{''CDBGDTR_EL0''} \ accessible_regs s" + shows "traces_enabled (DBGDTR_EL0_read__1 arg0) s" + unfolding DBGDTR_EL0_read__1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGDTR_EL0_SysRegRead_537a006eb82c59aa[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGDTR_EL0_SysRegRead_537a006eb82c59aa el op0 op1 CRn op2 CRm) s" + unfolding DBGDTR_EL0_SysRegRead_537a006eb82c59aa_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGPRCR_EL1_SysRegRead_6b19d62af9619a21[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGPRCR_EL1_SysRegRead_6b19d62af9619a21 el op0 op1 CRn op2 CRm) s" + unfolding DBGPRCR_EL1_SysRegRead_6b19d62af9619a21_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGVCR32_EL2_SysRegRead_7986b2bdf8df010d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGVCR32_EL2_SysRegRead_7986b2bdf8df010d el op0 op1 CRn op2 CRm) s" + unfolding DBGVCR32_EL2_SysRegRead_7986b2bdf8df010d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGWCR_EL1_SysRegRead_03139d052b544b2f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGWCR_EL1_SysRegRead_03139d052b544b2f el op0 op1 CRn op2 CRm) s" + unfolding DBGWCR_EL1_SysRegRead_03139d052b544b2f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGWVR_EL1_SysRegRead_029de1005ef34888[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGWVR_EL1_SysRegRead_029de1005ef34888 el op0 op1 CRn op2 CRm) s" + unfolding DBGWVR_EL1_SysRegRead_029de1005ef34888_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DISR_EL1_SysRegRead_d06ce25101dac895[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DISR_EL1_SysRegRead_d06ce25101dac895 el op0 op1 CRn op2 CRm) s" + unfolding DISR_EL1_SysRegRead_d06ce25101dac895_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DLR_EL0_read[traces_enabledI]: + assumes "{''CDLR_EL0''} \ accessible_regs s" + shows "traces_enabled (DLR_EL0_read arg0) s" + unfolding DLR_EL0_read_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DLR_EL0_SysRegRead_75b9821e3e84ec13[traces_enabledI]: + "traces_enabled (DLR_EL0_SysRegRead_75b9821e3e84ec13 el op0 op1 CRn op2 CRm) s" + unfolding DLR_EL0_SysRegRead_75b9821e3e84ec13_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ELR_EL12_SysRegRead_e8215c0ae79859bb[traces_enabledI]: + "traces_enabled (ELR_EL12_SysRegRead_e8215c0ae79859bb el op0 op1 CRn op2 CRm) s" + unfolding ELR_EL12_SysRegRead_e8215c0ae79859bb_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ELR_EL1_SysRegRead_0d3f1ad1483e96c2[traces_enabledI]: + "traces_enabled (ELR_EL1_SysRegRead_0d3f1ad1483e96c2 el op0 op1 CRn op2 CRm) s" + unfolding ELR_EL1_SysRegRead_0d3f1ad1483e96c2_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ELR_EL2_SysRegRead_00b4dd4251404d91[traces_enabledI]: + "traces_enabled (ELR_EL2_SysRegRead_00b4dd4251404d91 el op0 op1 CRn op2 CRm) s" + unfolding ELR_EL2_SysRegRead_00b4dd4251404d91_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ELR_EL3_SysRegRead_a7a7cd4e7e805396[traces_enabledI]: + "traces_enabled (ELR_EL3_SysRegRead_a7a7cd4e7e805396 el op0 op1 CRn op2 CRm) s" + unfolding ELR_EL3_SysRegRead_a7a7cd4e7e805396_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ERRIDR_EL1_SysRegRead_41b56b8d34e51109[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERRIDR_EL1_SysRegRead_41b56b8d34e51109 el op0 op1 CRn op2 CRm) s" + unfolding ERRIDR_EL1_SysRegRead_41b56b8d34e51109_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ERRSELR_EL1_SysRegRead_1bcf942400e8d57f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERRSELR_EL1_SysRegRead_1bcf942400e8d57f el op0 op1 CRn op2 CRm) s" + unfolding ERRSELR_EL1_SysRegRead_1bcf942400e8d57f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ERXADDR_EL1_SysRegRead_7dea05bca757fc1d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERXADDR_EL1_SysRegRead_7dea05bca757fc1d el op0 op1 CRn op2 CRm) s" + unfolding ERXADDR_EL1_SysRegRead_7dea05bca757fc1d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ERXCTLR_EL1_SysRegRead_e46ed88d092db048[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERXCTLR_EL1_SysRegRead_e46ed88d092db048 el op0 op1 CRn op2 CRm) s" + unfolding ERXCTLR_EL1_SysRegRead_e46ed88d092db048_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ERXFR_EL1_SysRegRead_ed2a3c237ae67a43[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERXFR_EL1_SysRegRead_ed2a3c237ae67a43 el op0 op1 CRn op2 CRm) s" + unfolding ERXFR_EL1_SysRegRead_ed2a3c237ae67a43_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ERXMISC0_EL1_SysRegRead_a71a4de5f2444f19[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERXMISC0_EL1_SysRegRead_a71a4de5f2444f19 el op0 op1 CRn op2 CRm) s" + unfolding ERXMISC0_EL1_SysRegRead_a71a4de5f2444f19_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ERXMISC1_EL1_SysRegRead_bda613f8058b1fd8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERXMISC1_EL1_SysRegRead_bda613f8058b1fd8 el op0 op1 CRn op2 CRm) s" + unfolding ERXMISC1_EL1_SysRegRead_bda613f8058b1fd8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ERXSTATUS_EL1_SysRegRead_0ab2cfe6937b8b64[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERXSTATUS_EL1_SysRegRead_0ab2cfe6937b8b64 el op0 op1 CRn op2 CRm) s" + unfolding ERXSTATUS_EL1_SysRegRead_0ab2cfe6937b8b64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ESR_EL12_SysRegRead_207d3805d256851a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ESR_EL12_SysRegRead_207d3805d256851a el op0 op1 CRn op2 CRm) s" + unfolding ESR_EL12_SysRegRead_207d3805d256851a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ESR_EL1_SysRegRead_4894753806397624[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ESR_EL1_SysRegRead_4894753806397624 el op0 op1 CRn op2 CRm) s" + unfolding ESR_EL1_SysRegRead_4894753806397624_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ESR_EL2_SysRegRead_e0558cb255261414[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ESR_EL2_SysRegRead_e0558cb255261414 el op0 op1 CRn op2 CRm) s" + unfolding ESR_EL2_SysRegRead_e0558cb255261414_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ESR_EL3_SysRegRead_e0eabec0b099e366[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ESR_EL3_SysRegRead_e0eabec0b099e366 el op0 op1 CRn op2 CRm) s" + unfolding ESR_EL3_SysRegRead_e0eabec0b099e366_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FAR_EL12_SysRegRead_061fecffb03f9fc5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FAR_EL12_SysRegRead_061fecffb03f9fc5 el op0 op1 CRn op2 CRm) s" + unfolding FAR_EL12_SysRegRead_061fecffb03f9fc5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FAR_EL1_SysRegRead_136ac0cc65bd5f9d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FAR_EL1_SysRegRead_136ac0cc65bd5f9d el op0 op1 CRn op2 CRm) s" + unfolding FAR_EL1_SysRegRead_136ac0cc65bd5f9d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FAR_EL2_SysRegRead_d686d0a5577f0aae[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FAR_EL2_SysRegRead_d686d0a5577f0aae el op0 op1 CRn op2 CRm) s" + unfolding FAR_EL2_SysRegRead_d686d0a5577f0aae_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FAR_EL3_SysRegRead_d63ec2764f8ffe40[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FAR_EL3_SysRegRead_d63ec2764f8ffe40 el op0 op1 CRn op2 CRm) s" + unfolding FAR_EL3_SysRegRead_d63ec2764f8ffe40_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPCR_SysRegRead_4176e216195c5686[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FPCR_SysRegRead_4176e216195c5686 el op0 op1 CRn op2 CRm) s" + unfolding FPCR_SysRegRead_4176e216195c5686_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPEXC32_EL2_SysRegRead_7ee503337da57806[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FPEXC32_EL2_SysRegRead_7ee503337da57806 el op0 op1 CRn op2 CRm) s" + unfolding FPEXC32_EL2_SysRegRead_7ee503337da57806_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPSR_SysRegRead_c1fde5c387acaca1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FPSR_SysRegRead_c1fde5c387acaca1 el op0 op1 CRn op2 CRm) s" + unfolding FPSR_SysRegRead_c1fde5c387acaca1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_HACR_EL2_SysRegRead_07bc3864e8ed8264[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (HACR_EL2_SysRegRead_07bc3864e8ed8264 el op0 op1 CRn op2 CRm) s" + unfolding HACR_EL2_SysRegRead_07bc3864e8ed8264_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_HCR_EL2_SysRegRead_f76ecfdc85c5ff7c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (HCR_EL2_SysRegRead_f76ecfdc85c5ff7c el op0 op1 CRn op2 CRm) s" + unfolding HCR_EL2_SysRegRead_f76ecfdc85c5ff7c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_HPFAR_EL2_SysRegRead_4c322cee424dff18[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (HPFAR_EL2_SysRegRead_4c322cee424dff18 el op0 op1 CRn op2 CRm) s" + unfolding HPFAR_EL2_SysRegRead_4c322cee424dff18_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_HSTR_EL2_SysRegRead_680380b9028cf399[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (HSTR_EL2_SysRegRead_680380b9028cf399 el op0 op1 CRn op2 CRm) s" + unfolding HSTR_EL2_SysRegRead_680380b9028cf399_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_AP0R_EL1_SysRegRead_cac9b22dc3786a15[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_AP0R_EL1_SysRegRead_cac9b22dc3786a15 el op0 op1 CRn op2 CRm) s" + unfolding ICC_AP0R_EL1_SysRegRead_cac9b22dc3786a15_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_AP1R_EL1_SysRegRead_4127418c67790ba3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_AP1R_EL1_SysRegRead_4127418c67790ba3 el op0 op1 CRn op2 CRm) s" + unfolding ICC_AP1R_EL1_SysRegRead_4127418c67790ba3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_BPR0_EL1_SysRegRead_6ada10a9051248c2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_BPR0_EL1_SysRegRead_6ada10a9051248c2 el op0 op1 CRn op2 CRm) s" + unfolding ICC_BPR0_EL1_SysRegRead_6ada10a9051248c2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_BPR1_EL1_SysRegRead_c56bf88f1b4aee37[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_BPR1_EL1_SysRegRead_c56bf88f1b4aee37 el op0 op1 CRn op2 CRm) s" + unfolding ICC_BPR1_EL1_SysRegRead_c56bf88f1b4aee37_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_CTLR_EL1_SysRegRead_5754830bf787a1e2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_CTLR_EL1_SysRegRead_5754830bf787a1e2 el op0 op1 CRn op2 CRm) s" + unfolding ICC_CTLR_EL1_SysRegRead_5754830bf787a1e2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_CTLR_EL3_SysRegRead_aba1771445e9d51b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_CTLR_EL3_SysRegRead_aba1771445e9d51b el op0 op1 CRn op2 CRm) s" + unfolding ICC_CTLR_EL3_SysRegRead_aba1771445e9d51b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_HPPIR0_EL1_SysRegRead_221f9a6f32464de4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_HPPIR0_EL1_SysRegRead_221f9a6f32464de4 el op0 op1 CRn op2 CRm) s" + unfolding ICC_HPPIR0_EL1_SysRegRead_221f9a6f32464de4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_HPPIR1_EL1_SysRegRead_88ed0889f7d5a37a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_HPPIR1_EL1_SysRegRead_88ed0889f7d5a37a el op0 op1 CRn op2 CRm) s" + unfolding ICC_HPPIR1_EL1_SysRegRead_88ed0889f7d5a37a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_IAR0_EL1_SysRegRead_dcfaf70befc09037[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_IAR0_EL1_SysRegRead_dcfaf70befc09037 el op0 op1 CRn op2 CRm) s" + unfolding ICC_IAR0_EL1_SysRegRead_dcfaf70befc09037_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_IAR1_EL1_SysRegRead_9f370ba68fd3e44f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_IAR1_EL1_SysRegRead_9f370ba68fd3e44f el op0 op1 CRn op2 CRm) s" + unfolding ICC_IAR1_EL1_SysRegRead_9f370ba68fd3e44f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_IGRPEN0_EL1_SysRegRead_e575448f3c7e7a94[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_IGRPEN0_EL1_SysRegRead_e575448f3c7e7a94 el op0 op1 CRn op2 CRm) s" + unfolding ICC_IGRPEN0_EL1_SysRegRead_e575448f3c7e7a94_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_IGRPEN1_EL1_SysRegRead_3cfd0733ef9b6efa[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_IGRPEN1_EL1_SysRegRead_3cfd0733ef9b6efa el op0 op1 CRn op2 CRm) s" + unfolding ICC_IGRPEN1_EL1_SysRegRead_3cfd0733ef9b6efa_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_IGRPEN1_EL3_SysRegRead_d192d252016b4c8d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_IGRPEN1_EL3_SysRegRead_d192d252016b4c8d el op0 op1 CRn op2 CRm) s" + unfolding ICC_IGRPEN1_EL3_SysRegRead_d192d252016b4c8d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_PMR_EL1_SysRegRead_4ab2c9427488fbf4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_PMR_EL1_SysRegRead_4ab2c9427488fbf4 el op0 op1 CRn op2 CRm) s" + unfolding ICC_PMR_EL1_SysRegRead_4ab2c9427488fbf4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_RPR_EL1_SysRegRead_bea9edc41b26aab0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_RPR_EL1_SysRegRead_bea9edc41b26aab0 el op0 op1 CRn op2 CRm) s" + unfolding ICC_RPR_EL1_SysRegRead_bea9edc41b26aab0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_SRE_EL1_SysRegRead_7cf0aa9fc619dea4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_SRE_EL1_SysRegRead_7cf0aa9fc619dea4 el op0 op1 CRn op2 CRm) s" + unfolding ICC_SRE_EL1_SysRegRead_7cf0aa9fc619dea4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_SRE_EL2_SysRegRead_35c9349812c986fe[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_SRE_EL2_SysRegRead_35c9349812c986fe el op0 op1 CRn op2 CRm) s" + unfolding ICC_SRE_EL2_SysRegRead_35c9349812c986fe_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_SRE_EL3_SysRegRead_c7d421022a5f589d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_SRE_EL3_SysRegRead_c7d421022a5f589d el op0 op1 CRn op2 CRm) s" + unfolding ICC_SRE_EL3_SysRegRead_c7d421022a5f589d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_AP0R_EL2_SysRegRead_a38114229330a389[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_AP0R_EL2_SysRegRead_a38114229330a389 el op0 op1 CRn op2 CRm) s" + unfolding ICH_AP0R_EL2_SysRegRead_a38114229330a389_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_AP1R_EL2_SysRegRead_3ef1256520a6f18e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_AP1R_EL2_SysRegRead_3ef1256520a6f18e el op0 op1 CRn op2 CRm) s" + unfolding ICH_AP1R_EL2_SysRegRead_3ef1256520a6f18e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_EISR_EL2_SysRegRead_a45d99ec0ef64804[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_EISR_EL2_SysRegRead_a45d99ec0ef64804 el op0 op1 CRn op2 CRm) s" + unfolding ICH_EISR_EL2_SysRegRead_a45d99ec0ef64804_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_ELRSR_EL2_SysRegRead_93859a236e9efe6d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_ELRSR_EL2_SysRegRead_93859a236e9efe6d el op0 op1 CRn op2 CRm) s" + unfolding ICH_ELRSR_EL2_SysRegRead_93859a236e9efe6d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_HCR_EL2_SysRegRead_bd436f3e91661e3b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_HCR_EL2_SysRegRead_bd436f3e91661e3b el op0 op1 CRn op2 CRm) s" + unfolding ICH_HCR_EL2_SysRegRead_bd436f3e91661e3b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_LR_EL2_SysRegRead_f9d8d38c7064e389[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_LR_EL2_SysRegRead_f9d8d38c7064e389 el op0 op1 CRn op2 CRm) s" + unfolding ICH_LR_EL2_SysRegRead_f9d8d38c7064e389_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_MISR_EL2_SysRegRead_4e46f86d49bd21cd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_MISR_EL2_SysRegRead_4e46f86d49bd21cd el op0 op1 CRn op2 CRm) s" + unfolding ICH_MISR_EL2_SysRegRead_4e46f86d49bd21cd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_VMCR_EL2_SysRegRead_3c019711ec735507[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_VMCR_EL2_SysRegRead_3c019711ec735507 el op0 op1 CRn op2 CRm) s" + unfolding ICH_VMCR_EL2_SysRegRead_3c019711ec735507_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_VTR_EL2_SysRegRead_2ed82d00af03b344[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_VTR_EL2_SysRegRead_2ed82d00af03b344 el op0 op1 CRn op2 CRm) s" + unfolding ICH_VTR_EL2_SysRegRead_2ed82d00af03b344_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_AA64AFR0_EL1_SysRegRead_325547f3ac10431a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_AA64AFR0_EL1_SysRegRead_325547f3ac10431a el op0 op1 CRn op2 CRm) s" + unfolding ID_AA64AFR0_EL1_SysRegRead_325547f3ac10431a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_AA64AFR1_EL1_SysRegRead_99b67b76121ee706[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_AA64AFR1_EL1_SysRegRead_99b67b76121ee706 el op0 op1 CRn op2 CRm) s" + unfolding ID_AA64AFR1_EL1_SysRegRead_99b67b76121ee706_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_AA64DFR0_EL1_SysRegRead_c3e6b049dd70bbab[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_AA64DFR0_EL1_SysRegRead_c3e6b049dd70bbab el op0 op1 CRn op2 CRm) s" + unfolding ID_AA64DFR0_EL1_SysRegRead_c3e6b049dd70bbab_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_AA64DFR1_EL1_SysRegRead_2f066031859d7035[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_AA64DFR1_EL1_SysRegRead_2f066031859d7035 el op0 op1 CRn op2 CRm) s" + unfolding ID_AA64DFR1_EL1_SysRegRead_2f066031859d7035_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_AA64ISAR0_EL1_SysRegRead_d35f255c04eaab0f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_AA64ISAR0_EL1_SysRegRead_d35f255c04eaab0f el op0 op1 CRn op2 CRm) s" + unfolding ID_AA64ISAR0_EL1_SysRegRead_d35f255c04eaab0f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_AA64ISAR1_EL1_SysRegRead_1132f371c4707f61[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_AA64ISAR1_EL1_SysRegRead_1132f371c4707f61 el op0 op1 CRn op2 CRm) s" + unfolding ID_AA64ISAR1_EL1_SysRegRead_1132f371c4707f61_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_AA64MMFR0_EL1_SysRegRead_836c46ff67ac3f3d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_AA64MMFR0_EL1_SysRegRead_836c46ff67ac3f3d el op0 op1 CRn op2 CRm) s" + unfolding ID_AA64MMFR0_EL1_SysRegRead_836c46ff67ac3f3d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_AA64MMFR1_EL1_SysRegRead_3abbf4d2af8dd3be[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_AA64MMFR1_EL1_SysRegRead_3abbf4d2af8dd3be el op0 op1 CRn op2 CRm) s" + unfolding ID_AA64MMFR1_EL1_SysRegRead_3abbf4d2af8dd3be_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_AA64MMFR2_EL1_SysRegRead_1443648da3ca79dd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_AA64MMFR2_EL1_SysRegRead_1443648da3ca79dd el op0 op1 CRn op2 CRm) s" + unfolding ID_AA64MMFR2_EL1_SysRegRead_1443648da3ca79dd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_AA64PFR0_EL1_SysRegRead_fe78f914579c8717[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_AA64PFR0_EL1_SysRegRead_fe78f914579c8717 el op0 op1 CRn op2 CRm) s" + unfolding ID_AA64PFR0_EL1_SysRegRead_fe78f914579c8717_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_AA64PFR1_EL1_SysRegRead_3be470f3d1bff138[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_AA64PFR1_EL1_SysRegRead_3be470f3d1bff138 el op0 op1 CRn op2 CRm) s" + unfolding ID_AA64PFR1_EL1_SysRegRead_3be470f3d1bff138_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_AA64ZFR0_EL1_SysRegRead_70425f5143f66c9f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_AA64ZFR0_EL1_SysRegRead_70425f5143f66c9f el op0 op1 CRn op2 CRm) s" + unfolding ID_AA64ZFR0_EL1_SysRegRead_70425f5143f66c9f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_AFR0_EL1_SysRegRead_019e5ec822653217[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_AFR0_EL1_SysRegRead_019e5ec822653217 el op0 op1 CRn op2 CRm) s" + unfolding ID_AFR0_EL1_SysRegRead_019e5ec822653217_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_DFR0_EL1_SysRegRead_12146217191b4fee[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_DFR0_EL1_SysRegRead_12146217191b4fee el op0 op1 CRn op2 CRm) s" + unfolding ID_DFR0_EL1_SysRegRead_12146217191b4fee_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_ISAR0_EL1_SysRegRead_4e2f04c3a26dddb3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_ISAR0_EL1_SysRegRead_4e2f04c3a26dddb3 el op0 op1 CRn op2 CRm) s" + unfolding ID_ISAR0_EL1_SysRegRead_4e2f04c3a26dddb3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_ISAR1_EL1_SysRegRead_2f4500748023e22b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_ISAR1_EL1_SysRegRead_2f4500748023e22b el op0 op1 CRn op2 CRm) s" + unfolding ID_ISAR1_EL1_SysRegRead_2f4500748023e22b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_ISAR2_EL1_SysRegRead_1e8edaee6a0e9ef9[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_ISAR2_EL1_SysRegRead_1e8edaee6a0e9ef9 el op0 op1 CRn op2 CRm) s" + unfolding ID_ISAR2_EL1_SysRegRead_1e8edaee6a0e9ef9_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_ISAR3_EL1_SysRegRead_cf9a1aae39d73bdd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_ISAR3_EL1_SysRegRead_cf9a1aae39d73bdd el op0 op1 CRn op2 CRm) s" + unfolding ID_ISAR3_EL1_SysRegRead_cf9a1aae39d73bdd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_ISAR4_EL1_SysRegRead_9bffd9dcf4dd4ef4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_ISAR4_EL1_SysRegRead_9bffd9dcf4dd4ef4 el op0 op1 CRn op2 CRm) s" + unfolding ID_ISAR4_EL1_SysRegRead_9bffd9dcf4dd4ef4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_ISAR5_EL1_SysRegRead_f70928ed2f55c1f0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_ISAR5_EL1_SysRegRead_f70928ed2f55c1f0 el op0 op1 CRn op2 CRm) s" + unfolding ID_ISAR5_EL1_SysRegRead_f70928ed2f55c1f0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_ISAR6_EL1_SysRegRead_6ce3605912a2db6d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_ISAR6_EL1_SysRegRead_6ce3605912a2db6d el op0 op1 CRn op2 CRm) s" + unfolding ID_ISAR6_EL1_SysRegRead_6ce3605912a2db6d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_MMFR0_EL1_SysRegRead_b31c5faa39841084[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_MMFR0_EL1_SysRegRead_b31c5faa39841084 el op0 op1 CRn op2 CRm) s" + unfolding ID_MMFR0_EL1_SysRegRead_b31c5faa39841084_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_MMFR1_EL1_SysRegRead_b0f4bc0d71c9af14[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_MMFR1_EL1_SysRegRead_b0f4bc0d71c9af14 el op0 op1 CRn op2 CRm) s" + unfolding ID_MMFR1_EL1_SysRegRead_b0f4bc0d71c9af14_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_MMFR2_EL1_SysRegRead_b60501193094f759[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_MMFR2_EL1_SysRegRead_b60501193094f759 el op0 op1 CRn op2 CRm) s" + unfolding ID_MMFR2_EL1_SysRegRead_b60501193094f759_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_MMFR3_EL1_SysRegRead_dc45af19c356c392[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_MMFR3_EL1_SysRegRead_dc45af19c356c392 el op0 op1 CRn op2 CRm) s" + unfolding ID_MMFR3_EL1_SysRegRead_dc45af19c356c392_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_MMFR4_EL1_SysRegRead_237ae4b6fb487f3e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_MMFR4_EL1_SysRegRead_237ae4b6fb487f3e el op0 op1 CRn op2 CRm) s" + unfolding ID_MMFR4_EL1_SysRegRead_237ae4b6fb487f3e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_MMFR5_EL1_SysRegRead_00dc6140c3593f6a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_MMFR5_EL1_SysRegRead_00dc6140c3593f6a el op0 op1 CRn op2 CRm) s" + unfolding ID_MMFR5_EL1_SysRegRead_00dc6140c3593f6a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_PFR0_EL1_SysRegRead_ab73eb91d66cfece[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_PFR0_EL1_SysRegRead_ab73eb91d66cfece el op0 op1 CRn op2 CRm) s" + unfolding ID_PFR0_EL1_SysRegRead_ab73eb91d66cfece_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_PFR1_EL1_SysRegRead_264075958e26856b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_PFR1_EL1_SysRegRead_264075958e26856b el op0 op1 CRn op2 CRm) s" + unfolding ID_PFR1_EL1_SysRegRead_264075958e26856b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ID_PFR2_EL1_SysRegRead_8561b575e8dfcee0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ID_PFR2_EL1_SysRegRead_8561b575e8dfcee0 el op0 op1 CRn op2 CRm) s" + unfolding ID_PFR2_EL1_SysRegRead_8561b575e8dfcee0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_IFSR32_EL2_SysRegRead_3b41290786c143ba[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (IFSR32_EL2_SysRegRead_3b41290786c143ba el op0 op1 CRn op2 CRm) s" + unfolding IFSR32_EL2_SysRegRead_3b41290786c143ba_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ISR_EL1_SysRegRead_41b7dbf26b89e726[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ISR_EL1_SysRegRead_41b7dbf26b89e726 el op0 op1 CRn op2 CRm) s" + unfolding ISR_EL1_SysRegRead_41b7dbf26b89e726_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_LORC_EL1_SysRegRead_0067e90ee116c26f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (LORC_EL1_SysRegRead_0067e90ee116c26f el op0 op1 CRn op2 CRm) s" + unfolding LORC_EL1_SysRegRead_0067e90ee116c26f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_LOREA_EL1_SysRegRead_ec495c3c15ed4dbe[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (LOREA_EL1_SysRegRead_ec495c3c15ed4dbe el op0 op1 CRn op2 CRm) s" + unfolding LOREA_EL1_SysRegRead_ec495c3c15ed4dbe_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_LORID_EL1_SysRegRead_a063108cc96d4baa[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (LORID_EL1_SysRegRead_a063108cc96d4baa el op0 op1 CRn op2 CRm) s" + unfolding LORID_EL1_SysRegRead_a063108cc96d4baa_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_LORN_EL1_SysRegRead_da981b495b21c400[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (LORN_EL1_SysRegRead_da981b495b21c400 el op0 op1 CRn op2 CRm) s" + unfolding LORN_EL1_SysRegRead_da981b495b21c400_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_LORSA_EL1_SysRegRead_cdc08dda4115abc7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (LORSA_EL1_SysRegRead_cdc08dda4115abc7 el op0 op1 CRn op2 CRm) s" + unfolding LORSA_EL1_SysRegRead_cdc08dda4115abc7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MAIR_EL12_SysRegRead_ac3327848e47dda6[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MAIR_EL12_SysRegRead_ac3327848e47dda6 el op0 op1 CRn op2 CRm) s" + unfolding MAIR_EL12_SysRegRead_ac3327848e47dda6_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MAIR_EL1_SysRegRead_ee00b1441fc4a50d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MAIR_EL1_SysRegRead_ee00b1441fc4a50d el op0 op1 CRn op2 CRm) s" + unfolding MAIR_EL1_SysRegRead_ee00b1441fc4a50d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MAIR_EL2_SysRegRead_66c03f7cb594c1bd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MAIR_EL2_SysRegRead_66c03f7cb594c1bd el op0 op1 CRn op2 CRm) s" + unfolding MAIR_EL2_SysRegRead_66c03f7cb594c1bd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MAIR_EL3_SysRegRead_0eb4af28a4f9b45a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MAIR_EL3_SysRegRead_0eb4af28a4f9b45a el op0 op1 CRn op2 CRm) s" + unfolding MAIR_EL3_SysRegRead_0eb4af28a4f9b45a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MDCCINT_EL1_SysRegRead_12f1a0397d5a3729[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MDCCINT_EL1_SysRegRead_12f1a0397d5a3729 el op0 op1 CRn op2 CRm) s" + unfolding MDCCINT_EL1_SysRegRead_12f1a0397d5a3729_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MDCCSR_EL0_SysRegRead_1ca0d9105cd616c5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MDCCSR_EL0_SysRegRead_1ca0d9105cd616c5 el op0 op1 CRn op2 CRm) s" + unfolding MDCCSR_EL0_SysRegRead_1ca0d9105cd616c5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MDCR_EL2_SysRegRead_f2181c815a998208[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MDCR_EL2_SysRegRead_f2181c815a998208 el op0 op1 CRn op2 CRm) s" + unfolding MDCR_EL2_SysRegRead_f2181c815a998208_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MDCR_EL3_SysRegRead_229d5ee95c6e9850[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MDCR_EL3_SysRegRead_229d5ee95c6e9850 el op0 op1 CRn op2 CRm) s" + unfolding MDCR_EL3_SysRegRead_229d5ee95c6e9850_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MDRAR_EL1_SysRegRead_4c6f0d270d3fe56e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MDRAR_EL1_SysRegRead_4c6f0d270d3fe56e el op0 op1 CRn op2 CRm) s" + unfolding MDRAR_EL1_SysRegRead_4c6f0d270d3fe56e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MDSCR_EL1_SysRegRead_5184636ced539526[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MDSCR_EL1_SysRegRead_5184636ced539526 el op0 op1 CRn op2 CRm) s" + unfolding MDSCR_EL1_SysRegRead_5184636ced539526_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MIDR_EL1_SysRegRead_d49cc5f604ad167e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MIDR_EL1_SysRegRead_d49cc5f604ad167e el op0 op1 CRn op2 CRm) s" + unfolding MIDR_EL1_SysRegRead_d49cc5f604ad167e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAM0_EL1_SysRegRead_87af318fd5c9f9f7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAM0_EL1_SysRegRead_87af318fd5c9f9f7 el op0 op1 CRn op2 CRm) s" + unfolding MPAM0_EL1_SysRegRead_87af318fd5c9f9f7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAM1_EL12_SysRegRead_229a253b730e26d9[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAM1_EL12_SysRegRead_229a253b730e26d9 el op0 op1 CRn op2 CRm) s" + unfolding MPAM1_EL12_SysRegRead_229a253b730e26d9_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAM1_EL1_SysRegRead_770ea23b87b18d99[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAM1_EL1_SysRegRead_770ea23b87b18d99 el op0 op1 CRn op2 CRm) s" + unfolding MPAM1_EL1_SysRegRead_770ea23b87b18d99_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAM2_EL2_SysRegRead_10b60646fb381bea[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAM2_EL2_SysRegRead_10b60646fb381bea el op0 op1 CRn op2 CRm) s" + unfolding MPAM2_EL2_SysRegRead_10b60646fb381bea_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAM3_EL3_SysRegRead_989f38b07d8b4265[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAM3_EL3_SysRegRead_989f38b07d8b4265 el op0 op1 CRn op2 CRm) s" + unfolding MPAM3_EL3_SysRegRead_989f38b07d8b4265_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMHCR_EL2_SysRegRead_6ee5f61be808e32e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMHCR_EL2_SysRegRead_6ee5f61be808e32e el op0 op1 CRn op2 CRm) s" + unfolding MPAMHCR_EL2_SysRegRead_6ee5f61be808e32e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMIDR_EL1_SysRegRead_df4c57d831354b3c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMIDR_EL1_SysRegRead_df4c57d831354b3c el op0 op1 CRn op2 CRm) s" + unfolding MPAMIDR_EL1_SysRegRead_df4c57d831354b3c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM0_EL2_SysRegRead_d878a15f2ea1751d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM0_EL2_SysRegRead_d878a15f2ea1751d el op0 op1 CRn op2 CRm) s" + unfolding MPAMVPM0_EL2_SysRegRead_d878a15f2ea1751d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM1_EL2_SysRegRead_78ba55a3ef5fc5ba[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM1_EL2_SysRegRead_78ba55a3ef5fc5ba el op0 op1 CRn op2 CRm) s" + unfolding MPAMVPM1_EL2_SysRegRead_78ba55a3ef5fc5ba_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM2_EL2_SysRegRead_590d1577b5eb780d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM2_EL2_SysRegRead_590d1577b5eb780d el op0 op1 CRn op2 CRm) s" + unfolding MPAMVPM2_EL2_SysRegRead_590d1577b5eb780d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM3_EL2_SysRegRead_3d93a30deb34ea81[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM3_EL2_SysRegRead_3d93a30deb34ea81 el op0 op1 CRn op2 CRm) s" + unfolding MPAMVPM3_EL2_SysRegRead_3d93a30deb34ea81_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM4_EL2_SysRegRead_c4fa65dba541d8f3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM4_EL2_SysRegRead_c4fa65dba541d8f3 el op0 op1 CRn op2 CRm) s" + unfolding MPAMVPM4_EL2_SysRegRead_c4fa65dba541d8f3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM5_EL2_SysRegRead_0f596cf6a35cf124[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM5_EL2_SysRegRead_0f596cf6a35cf124 el op0 op1 CRn op2 CRm) s" + unfolding MPAMVPM5_EL2_SysRegRead_0f596cf6a35cf124_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM6_EL2_SysRegRead_c93ffeb6ea409c71[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM6_EL2_SysRegRead_c93ffeb6ea409c71 el op0 op1 CRn op2 CRm) s" + unfolding MPAMVPM6_EL2_SysRegRead_c93ffeb6ea409c71_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM7_EL2_SysRegRead_ef19c89f1fa31f3e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM7_EL2_SysRegRead_ef19c89f1fa31f3e el op0 op1 CRn op2 CRm) s" + unfolding MPAMVPM7_EL2_SysRegRead_ef19c89f1fa31f3e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPMV_EL2_SysRegRead_6de5731367257b91[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPMV_EL2_SysRegRead_6de5731367257b91 el op0 op1 CRn op2 CRm) s" + unfolding MPAMVPMV_EL2_SysRegRead_6de5731367257b91_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPIDR_EL1_SysRegRead_1a44c237fc7e90a0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPIDR_EL1_SysRegRead_1a44c237fc7e90a0 el op0 op1 CRn op2 CRm) s" + unfolding MPIDR_EL1_SysRegRead_1a44c237fc7e90a0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MVFR0_EL1_SysRegRead_982614cb681cfbbf[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MVFR0_EL1_SysRegRead_982614cb681cfbbf el op0 op1 CRn op2 CRm) s" + unfolding MVFR0_EL1_SysRegRead_982614cb681cfbbf_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MVFR1_EL1_SysRegRead_1964a95566ab0fcd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MVFR1_EL1_SysRegRead_1964a95566ab0fcd el op0 op1 CRn op2 CRm) s" + unfolding MVFR1_EL1_SysRegRead_1964a95566ab0fcd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MVFR2_EL1_SysRegRead_f6245ffc535897f2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MVFR2_EL1_SysRegRead_f6245ffc535897f2 el op0 op1 CRn op2 CRm) s" + unfolding MVFR2_EL1_SysRegRead_f6245ffc535897f2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_OSDLR_EL1_SysRegRead_4cb80c508c4cced4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (OSDLR_EL1_SysRegRead_4cb80c508c4cced4 el op0 op1 CRn op2 CRm) s" + unfolding OSDLR_EL1_SysRegRead_4cb80c508c4cced4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_OSDTRRX_EL1_SysRegRead_d4eb07360bc69d28[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (OSDTRRX_EL1_SysRegRead_d4eb07360bc69d28 el op0 op1 CRn op2 CRm) s" + unfolding OSDTRRX_EL1_SysRegRead_d4eb07360bc69d28_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_OSDTRTX_EL1_SysRegRead_008c22058272684f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (OSDTRTX_EL1_SysRegRead_008c22058272684f el op0 op1 CRn op2 CRm) s" + unfolding OSDTRTX_EL1_SysRegRead_008c22058272684f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_OSECCR_EL1_SysRegRead_264ab12a32fecc30[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (OSECCR_EL1_SysRegRead_264ab12a32fecc30 el op0 op1 CRn op2 CRm) s" + unfolding OSECCR_EL1_SysRegRead_264ab12a32fecc30_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_OSLSR_EL1_SysRegRead_d99062033a35ccbf[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (OSLSR_EL1_SysRegRead_d99062033a35ccbf el op0 op1 CRn op2 CRm) s" + unfolding OSLSR_EL1_SysRegRead_d99062033a35ccbf_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PAR_EL1_SysRegRead_888e7c84935ebac7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PAR_EL1_SysRegRead_888e7c84935ebac7 el op0 op1 CRn op2 CRm) s" + unfolding PAR_EL1_SysRegRead_888e7c84935ebac7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMBIDR_EL1_SysRegRead_306c3f68e41521a3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMBIDR_EL1_SysRegRead_306c3f68e41521a3 el op0 op1 CRn op2 CRm) s" + unfolding PMBIDR_EL1_SysRegRead_306c3f68e41521a3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMBLIMITR_EL1_SysRegRead_b7c18938ab0566dc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMBLIMITR_EL1_SysRegRead_b7c18938ab0566dc el op0 op1 CRn op2 CRm) s" + unfolding PMBLIMITR_EL1_SysRegRead_b7c18938ab0566dc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMBPTR_EL1_SysRegRead_fb82e1b6e480bd0a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMBPTR_EL1_SysRegRead_fb82e1b6e480bd0a el op0 op1 CRn op2 CRm) s" + unfolding PMBPTR_EL1_SysRegRead_fb82e1b6e480bd0a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMBSR_EL1_SysRegRead_87628bec330b9f53[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMBSR_EL1_SysRegRead_87628bec330b9f53 el op0 op1 CRn op2 CRm) s" + unfolding PMBSR_EL1_SysRegRead_87628bec330b9f53_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMCCFILTR_EL0_SysRegRead_349918c2333bfc1e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMCCFILTR_EL0_SysRegRead_349918c2333bfc1e el op0 op1 CRn op2 CRm) s" + unfolding PMCCFILTR_EL0_SysRegRead_349918c2333bfc1e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMCCNTR_EL0_SysRegRead_45fc425eff298404[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMCCNTR_EL0_SysRegRead_45fc425eff298404 el op0 op1 CRn op2 CRm) s" + unfolding PMCCNTR_EL0_SysRegRead_45fc425eff298404_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMCEID0_EL0_SysRegRead_1364a10a0c913d82[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMCEID0_EL0_SysRegRead_1364a10a0c913d82 el op0 op1 CRn op2 CRm) s" + unfolding PMCEID0_EL0_SysRegRead_1364a10a0c913d82_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMCEID1_EL0_SysRegRead_2db7a3b96735d30a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMCEID1_EL0_SysRegRead_2db7a3b96735d30a el op0 op1 CRn op2 CRm) s" + unfolding PMCEID1_EL0_SysRegRead_2db7a3b96735d30a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMCNTENCLR_EL0_SysRegRead_5ac431b885c9c5e4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMCNTENCLR_EL0_SysRegRead_5ac431b885c9c5e4 el op0 op1 CRn op2 CRm) s" + unfolding PMCNTENCLR_EL0_SysRegRead_5ac431b885c9c5e4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMCNTENSET_EL0_SysRegRead_848c3aa603193fb7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMCNTENSET_EL0_SysRegRead_848c3aa603193fb7 el op0 op1 CRn op2 CRm) s" + unfolding PMCNTENSET_EL0_SysRegRead_848c3aa603193fb7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMCR_EL0_SysRegRead_9a03e454327a1718[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMCR_EL0_SysRegRead_9a03e454327a1718 el op0 op1 CRn op2 CRm) s" + unfolding PMCR_EL0_SysRegRead_9a03e454327a1718_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMEVCNTR_EL0_SysRegRead_e0380ad70bc25a0c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMEVCNTR_EL0_SysRegRead_e0380ad70bc25a0c el op0 op1 CRn op2 CRm) s" + unfolding PMEVCNTR_EL0_SysRegRead_e0380ad70bc25a0c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMEVTYPER_EL0_SysRegRead_b05172ff9d10dad4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMEVTYPER_EL0_SysRegRead_b05172ff9d10dad4 el op0 op1 CRn op2 CRm) s" + unfolding PMEVTYPER_EL0_SysRegRead_b05172ff9d10dad4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMINTENCLR_EL1_SysRegRead_43b8f4d9b40b2620[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMINTENCLR_EL1_SysRegRead_43b8f4d9b40b2620 el op0 op1 CRn op2 CRm) s" + unfolding PMINTENCLR_EL1_SysRegRead_43b8f4d9b40b2620_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMINTENSET_EL1_SysRegRead_a3d4464c2051ff23[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMINTENSET_EL1_SysRegRead_a3d4464c2051ff23 el op0 op1 CRn op2 CRm) s" + unfolding PMINTENSET_EL1_SysRegRead_a3d4464c2051ff23_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMOVSCLR_EL0_SysRegRead_300e5dfb491e58fa[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMOVSCLR_EL0_SysRegRead_300e5dfb491e58fa el op0 op1 CRn op2 CRm) s" + unfolding PMOVSCLR_EL0_SysRegRead_300e5dfb491e58fa_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMOVSSET_EL0_SysRegRead_e3c0657a6c8b11c8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMOVSSET_EL0_SysRegRead_e3c0657a6c8b11c8 el op0 op1 CRn op2 CRm) s" + unfolding PMOVSSET_EL0_SysRegRead_e3c0657a6c8b11c8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSCR_EL12_SysRegRead_624c386ea3cce853[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSCR_EL12_SysRegRead_624c386ea3cce853 el op0 op1 CRn op2 CRm) s" + unfolding PMSCR_EL12_SysRegRead_624c386ea3cce853_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSCR_EL1_SysRegRead_39ffc554ca37b155[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSCR_EL1_SysRegRead_39ffc554ca37b155 el op0 op1 CRn op2 CRm) s" + unfolding PMSCR_EL1_SysRegRead_39ffc554ca37b155_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSCR_EL2_SysRegRead_11330bd80566814a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSCR_EL2_SysRegRead_11330bd80566814a el op0 op1 CRn op2 CRm) s" + unfolding PMSCR_EL2_SysRegRead_11330bd80566814a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSELR_EL0_SysRegRead_540b592cb875b32f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSELR_EL0_SysRegRead_540b592cb875b32f el op0 op1 CRn op2 CRm) s" + unfolding PMSELR_EL0_SysRegRead_540b592cb875b32f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSEVFR_EL1_SysRegRead_9e9a58f73d629d59[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSEVFR_EL1_SysRegRead_9e9a58f73d629d59 el op0 op1 CRn op2 CRm) s" + unfolding PMSEVFR_EL1_SysRegRead_9e9a58f73d629d59_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSFCR_EL1_SysRegRead_30b07ff27088a488[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSFCR_EL1_SysRegRead_30b07ff27088a488 el op0 op1 CRn op2 CRm) s" + unfolding PMSFCR_EL1_SysRegRead_30b07ff27088a488_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSICR_EL1_SysRegRead_1b4bf4bb07470e4c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSICR_EL1_SysRegRead_1b4bf4bb07470e4c el op0 op1 CRn op2 CRm) s" + unfolding PMSICR_EL1_SysRegRead_1b4bf4bb07470e4c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSIDR_EL1_SysRegRead_062cecff79d24b4d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSIDR_EL1_SysRegRead_062cecff79d24b4d el op0 op1 CRn op2 CRm) s" + unfolding PMSIDR_EL1_SysRegRead_062cecff79d24b4d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSIRR_EL1_SysRegRead_b565329ce30ac491[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSIRR_EL1_SysRegRead_b565329ce30ac491 el op0 op1 CRn op2 CRm) s" + unfolding PMSIRR_EL1_SysRegRead_b565329ce30ac491_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSLATFR_EL1_SysRegRead_f82542fec2521a41[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSLATFR_EL1_SysRegRead_f82542fec2521a41 el op0 op1 CRn op2 CRm) s" + unfolding PMSLATFR_EL1_SysRegRead_f82542fec2521a41_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMUSERENR_EL0_SysRegRead_7efca1a4be376eb7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMUSERENR_EL0_SysRegRead_7efca1a4be376eb7 el op0 op1 CRn op2 CRm) s" + unfolding PMUSERENR_EL0_SysRegRead_7efca1a4be376eb7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMXEVCNTR_EL0_SysRegRead_193921f886161922[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMXEVCNTR_EL0_SysRegRead_193921f886161922 el op0 op1 CRn op2 CRm) s" + unfolding PMXEVCNTR_EL0_SysRegRead_193921f886161922_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMXEVTYPER_EL0_SysRegRead_a34d7cb6f32074c5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMXEVTYPER_EL0_SysRegRead_a34d7cb6f32074c5 el op0 op1 CRn op2 CRm) s" + unfolding PMXEVTYPER_EL0_SysRegRead_a34d7cb6f32074c5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_REVIDR_EL1_SysRegRead_06ac796f098a1e84[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (REVIDR_EL1_SysRegRead_06ac796f098a1e84 el op0 op1 CRn op2 CRm) s" + unfolding REVIDR_EL1_SysRegRead_06ac796f098a1e84_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RMR_EL1_SysRegRead_69f4933c1a574580[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RMR_EL1_SysRegRead_69f4933c1a574580 el op0 op1 CRn op2 CRm) s" + unfolding RMR_EL1_SysRegRead_69f4933c1a574580_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RMR_EL2_SysRegRead_75749340e0828f00[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RMR_EL2_SysRegRead_75749340e0828f00 el op0 op1 CRn op2 CRm) s" + unfolding RMR_EL2_SysRegRead_75749340e0828f00_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RMR_EL3_SysRegRead_fa5f18c3b20f8894[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RMR_EL3_SysRegRead_fa5f18c3b20f8894 el op0 op1 CRn op2 CRm) s" + unfolding RMR_EL3_SysRegRead_fa5f18c3b20f8894_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RSP_EL0_SysRegRead_b64c62bd96d973e3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RSP_EL0_SysRegRead_b64c62bd96d973e3 el op0 op1 CRn op2 CRm) s" + unfolding RSP_EL0_SysRegRead_b64c62bd96d973e3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RTPIDR_EL0_SysRegRead_0ce5a74dba936523[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RTPIDR_EL0_SysRegRead_0ce5a74dba936523 el op0 op1 CRn op2 CRm) s" + unfolding RTPIDR_EL0_SysRegRead_0ce5a74dba936523_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RVBAR_EL1_SysRegRead_48a958c9250293d1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RVBAR_EL1_SysRegRead_48a958c9250293d1 el op0 op1 CRn op2 CRm) s" + unfolding RVBAR_EL1_SysRegRead_48a958c9250293d1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RVBAR_EL2_SysRegRead_2fb802203150f4cc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RVBAR_EL2_SysRegRead_2fb802203150f4cc el op0 op1 CRn op2 CRm) s" + unfolding RVBAR_EL2_SysRegRead_2fb802203150f4cc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RVBAR_EL3_SysRegRead_000d1ea4b77ffa21[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RVBAR_EL3_SysRegRead_000d1ea4b77ffa21 el op0 op1 CRn op2 CRm) s" + unfolding RVBAR_EL3_SysRegRead_000d1ea4b77ffa21_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S3_op1_CCn_CCm_op2_SysRegRead_d72a7245384bbc0e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S3_op1_CCn_CCm_op2_SysRegRead_d72a7245384bbc0e el op0 op1 CRn op2 CRm) s" + unfolding S3_op1_CCn_CCm_op2_SysRegRead_d72a7245384bbc0e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCR_EL3_SysRegRead_082a69b26890132d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCR_EL3_SysRegRead_082a69b26890132d el op0 op1 CRn op2 CRm) s" + unfolding SCR_EL3_SysRegRead_082a69b26890132d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCTLR_EL12_SysRegRead_81ba00bca4ce39dc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCTLR_EL12_SysRegRead_81ba00bca4ce39dc el op0 op1 CRn op2 CRm) s" + unfolding SCTLR_EL12_SysRegRead_81ba00bca4ce39dc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCTLR_EL1_SysRegRead_cc5fb072b0cb85eb[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCTLR_EL1_SysRegRead_cc5fb072b0cb85eb el op0 op1 CRn op2 CRm) s" + unfolding SCTLR_EL1_SysRegRead_cc5fb072b0cb85eb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCTLR_EL2_SysRegRead_3cc208f3abf97e34[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCTLR_EL2_SysRegRead_3cc208f3abf97e34 el op0 op1 CRn op2 CRm) s" + unfolding SCTLR_EL2_SysRegRead_3cc208f3abf97e34_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCTLR_EL3_SysRegRead_9c537c9c01007c3e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCTLR_EL3_SysRegRead_9c537c9c01007c3e el op0 op1 CRn op2 CRm) s" + unfolding SCTLR_EL3_SysRegRead_9c537c9c01007c3e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCXTNUM_EL0_read[traces_enabledI]: + "traces_enabled (SCXTNUM_EL0_read arg0) s" + unfolding SCXTNUM_EL0_read_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_SCXTNUM_EL0_SysRegRead_ee5b769fc7f044cc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCXTNUM_EL0_SysRegRead_ee5b769fc7f044cc el op0 op1 CRn op2 CRm) s" + unfolding SCXTNUM_EL0_SysRegRead_ee5b769fc7f044cc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCXTNUM_EL12_SysRegRead_d31f345333a78d48[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCXTNUM_EL12_SysRegRead_d31f345333a78d48 el op0 op1 CRn op2 CRm) s" + unfolding SCXTNUM_EL12_SysRegRead_d31f345333a78d48_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCXTNUM_EL1_SysRegRead_dd27b7ad05ded1ab[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCXTNUM_EL1_SysRegRead_dd27b7ad05ded1ab el op0 op1 CRn op2 CRm) s" + unfolding SCXTNUM_EL1_SysRegRead_dd27b7ad05ded1ab_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCXTNUM_EL2_SysRegRead_421b17f19f5fdd2a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCXTNUM_EL2_SysRegRead_421b17f19f5fdd2a el op0 op1 CRn op2 CRm) s" + unfolding SCXTNUM_EL2_SysRegRead_421b17f19f5fdd2a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCXTNUM_EL3_SysRegRead_5f15a3b4da1bd4bb[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCXTNUM_EL3_SysRegRead_5f15a3b4da1bd4bb el op0 op1 CRn op2 CRm) s" + unfolding SCXTNUM_EL3_SysRegRead_5f15a3b4da1bd4bb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SDER32_EL3_SysRegRead_e21f871563c7e34e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SDER32_EL3_SysRegRead_e21f871563c7e34e el op0 op1 CRn op2 CRm) s" + unfolding SDER32_EL3_SysRegRead_e21f871563c7e34e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SPSel_SysRegRead_ac7632fd1580b15b[traces_enabledI]: + "traces_enabled (SPSel_SysRegRead_ac7632fd1580b15b el op0 op1 CRn op2 CRm) s" + unfolding SPSel_SysRegRead_ac7632fd1580b15b_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_SP_EL0_SysRegRead_4b07157e43cd0456[traces_enabledI]: + "traces_enabled (SP_EL0_SysRegRead_4b07157e43cd0456 el op0 op1 CRn op2 CRm) s" + unfolding SP_EL0_SysRegRead_4b07157e43cd0456_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_SP_EL1_SysRegRead_44ac23d2a7608550[traces_enabledI]: + "traces_enabled (SP_EL1_SysRegRead_44ac23d2a7608550 el op0 op1 CRn op2 CRm) s" + unfolding SP_EL1_SysRegRead_44ac23d2a7608550_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_SP_EL2_SysRegRead_9c4b7d596526b300[traces_enabledI]: + "traces_enabled (SP_EL2_SysRegRead_9c4b7d596526b300 el op0 op1 CRn op2 CRm) s" + unfolding SP_EL2_SysRegRead_9c4b7d596526b300_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_TCR_EL12_SysRegRead_cefcc3f131a70a7f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TCR_EL12_SysRegRead_cefcc3f131a70a7f el op0 op1 CRn op2 CRm) s" + unfolding TCR_EL12_SysRegRead_cefcc3f131a70a7f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TCR_EL1_SysRegRead_fbe255888fba9865[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TCR_EL1_SysRegRead_fbe255888fba9865 el op0 op1 CRn op2 CRm) s" + unfolding TCR_EL1_SysRegRead_fbe255888fba9865_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TCR_EL2_SysRegRead_3467687df9c2aec1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TCR_EL2_SysRegRead_3467687df9c2aec1 el op0 op1 CRn op2 CRm) s" + unfolding TCR_EL2_SysRegRead_3467687df9c2aec1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TCR_EL3_SysRegRead_7da88d4a232f9451[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TCR_EL3_SysRegRead_7da88d4a232f9451 el op0 op1 CRn op2 CRm) s" + unfolding TCR_EL3_SysRegRead_7da88d4a232f9451_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TPIDRRO_EL0_SysRegRead_3dc5dc323922fcfa[traces_enabledI]: + "traces_enabled (TPIDRRO_EL0_SysRegRead_3dc5dc323922fcfa el op0 op1 CRn op2 CRm) s" + unfolding TPIDRRO_EL0_SysRegRead_3dc5dc323922fcfa_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_TPIDR_EL0_SysRegRead_7b944c4fc3d3f60f[traces_enabledI]: + "traces_enabled (TPIDR_EL0_SysRegRead_7b944c4fc3d3f60f el op0 op1 CRn op2 CRm) s" + unfolding TPIDR_EL0_SysRegRead_7b944c4fc3d3f60f_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_TPIDR_EL1_SysRegRead_8db91ea8b9abc411[traces_enabledI]: + "traces_enabled (TPIDR_EL1_SysRegRead_8db91ea8b9abc411 el op0 op1 CRn op2 CRm) s" + unfolding TPIDR_EL1_SysRegRead_8db91ea8b9abc411_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_TPIDR_EL2_SysRegRead_fc4633f7449b5b4a[traces_enabledI]: + "traces_enabled (TPIDR_EL2_SysRegRead_fc4633f7449b5b4a el op0 op1 CRn op2 CRm) s" + unfolding TPIDR_EL2_SysRegRead_fc4633f7449b5b4a_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_TPIDR_EL3_SysRegRead_c6069d62b310a137[traces_enabledI]: + "traces_enabled (TPIDR_EL3_SysRegRead_c6069d62b310a137 el op0 op1 CRn op2 CRm) s" + unfolding TPIDR_EL3_SysRegRead_c6069d62b310a137_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_TTBR0_EL12_SysRegRead_73f9bd4d027badee[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR0_EL12_SysRegRead_73f9bd4d027badee el op0 op1 CRn op2 CRm) s" + unfolding TTBR0_EL12_SysRegRead_73f9bd4d027badee_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TTBR0_EL1_SysRegRead_2e8a6c25b2e4759a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR0_EL1_SysRegRead_2e8a6c25b2e4759a el op0 op1 CRn op2 CRm) s" + unfolding TTBR0_EL1_SysRegRead_2e8a6c25b2e4759a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TTBR0_EL2_SysRegRead_8d4de9e080477354[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR0_EL2_SysRegRead_8d4de9e080477354 el op0 op1 CRn op2 CRm) s" + unfolding TTBR0_EL2_SysRegRead_8d4de9e080477354_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TTBR0_EL3_SysRegRead_a46e35edfe45a273[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR0_EL3_SysRegRead_a46e35edfe45a273 el op0 op1 CRn op2 CRm) s" + unfolding TTBR0_EL3_SysRegRead_a46e35edfe45a273_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TTBR1_EL12_SysRegRead_bfbc2899eb278d2b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR1_EL12_SysRegRead_bfbc2899eb278d2b el op0 op1 CRn op2 CRm) s" + unfolding TTBR1_EL12_SysRegRead_bfbc2899eb278d2b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TTBR1_EL1_SysRegRead_2cb2fb59089165c5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR1_EL1_SysRegRead_2cb2fb59089165c5 el op0 op1 CRn op2 CRm) s" + unfolding TTBR1_EL1_SysRegRead_2cb2fb59089165c5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TTBR1_EL2_SysRegRead_08cd28a9b17bc317[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR1_EL2_SysRegRead_08cd28a9b17bc317 el op0 op1 CRn op2 CRm) s" + unfolding TTBR1_EL2_SysRegRead_08cd28a9b17bc317_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VBAR_EL12_SysRegRead_2ad4e02fbe99cf3d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VBAR_EL12_SysRegRead_2ad4e02fbe99cf3d el op0 op1 CRn op2 CRm) s" + unfolding VBAR_EL12_SysRegRead_2ad4e02fbe99cf3d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VBAR_EL1_SysRegRead_4d14cb3b6fe16ab6[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VBAR_EL1_SysRegRead_4d14cb3b6fe16ab6 el op0 op1 CRn op2 CRm) s" + unfolding VBAR_EL1_SysRegRead_4d14cb3b6fe16ab6_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VBAR_EL2_SysRegRead_1f6b3c94ccfecacf[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VBAR_EL2_SysRegRead_1f6b3c94ccfecacf el op0 op1 CRn op2 CRm) s" + unfolding VBAR_EL2_SysRegRead_1f6b3c94ccfecacf_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VBAR_EL3_SysRegRead_32f42cb574998654[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VBAR_EL3_SysRegRead_32f42cb574998654 el op0 op1 CRn op2 CRm) s" + unfolding VBAR_EL3_SysRegRead_32f42cb574998654_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VDISR_EL2_SysRegRead_14dff4ad4ae8c3a2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VDISR_EL2_SysRegRead_14dff4ad4ae8c3a2 el op0 op1 CRn op2 CRm) s" + unfolding VDISR_EL2_SysRegRead_14dff4ad4ae8c3a2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VMPIDR_EL2_SysRegRead_49b7c13dd1b0804c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VMPIDR_EL2_SysRegRead_49b7c13dd1b0804c el op0 op1 CRn op2 CRm) s" + unfolding VMPIDR_EL2_SysRegRead_49b7c13dd1b0804c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VPIDR_EL2_SysRegRead_f6520cd6a1f62bd8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VPIDR_EL2_SysRegRead_f6520cd6a1f62bd8 el op0 op1 CRn op2 CRm) s" + unfolding VPIDR_EL2_SysRegRead_f6520cd6a1f62bd8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VSESR_EL2_SysRegRead_401c063e57574698[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VSESR_EL2_SysRegRead_401c063e57574698 el op0 op1 CRn op2 CRm) s" + unfolding VSESR_EL2_SysRegRead_401c063e57574698_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VTCR_EL2_SysRegRead_5c8ea980dc5cc1d1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VTCR_EL2_SysRegRead_5c8ea980dc5cc1d1 el op0 op1 CRn op2 CRm) s" + unfolding VTCR_EL2_SysRegRead_5c8ea980dc5cc1d1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VTTBR_EL2_SysRegRead_2fbbdccc9485564d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VTTBR_EL2_SysRegRead_2fbbdccc9485564d el op0 op1 CRn op2 CRm) s" + unfolding VTTBR_EL2_SysRegRead_2fbbdccc9485564d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_AutoGen_SysRegRead[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_AutoGen_SysRegRead el op0 op1 CRn op2 CRm) s" + by (unfold AArch64_AutoGen_SysRegRead_def, traces_enabledI intro: assms[THEN subset_trans[rotated]]) + +lemma traces_enabled_AArch64_SysRegRead[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_SysRegRead op0 op1 crn crm op2) s" + unfolding AArch64_SysRegRead_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34 el op0 op1 CRn op2 CRm) s" + unfolding CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CDLR_EL0_CapSysRegRead_619c852c71c0978d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CDLR_EL0_CapSysRegRead_619c852c71c0978d el op0 op1 CRn op2 CRm) s" + unfolding CDLR_EL0_CapSysRegRead_619c852c71c0978d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CELR_EL12_CapSysRegRead_4bf271777fe55d1c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CELR_EL12_CapSysRegRead_4bf271777fe55d1c el op0 op1 CRn op2 CRm) s" + unfolding CELR_EL12_CapSysRegRead_4bf271777fe55d1c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CELR_EL1_CapSysRegRead_da9869d2314a30d5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CELR_EL1_CapSysRegRead_da9869d2314a30d5 el op0 op1 CRn op2 CRm) s" + unfolding CELR_EL1_CapSysRegRead_da9869d2314a30d5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CELR_EL2_CapSysRegRead_a9e9661da428a6d4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CELR_EL2_CapSysRegRead_a9e9661da428a6d4 el op0 op1 CRn op2 CRm) s" + unfolding CELR_EL2_CapSysRegRead_a9e9661da428a6d4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CELR_EL3_CapSysRegRead_d0424a232c45967e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CELR_EL3_CapSysRegRead_d0424a232c45967e el op0 op1 CRn op2 CRm) s" + unfolding CELR_EL3_CapSysRegRead_d0424a232c45967e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CID_EL0_CapSysRegRead_d560f6b1104266f1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CID_EL0_CapSysRegRead_d560f6b1104266f1 el op0 op1 CRn op2 CRm) s" + unfolding CID_EL0_CapSysRegRead_d560f6b1104266f1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CSP_EL0_CapSysRegRead_e5b1ba121f8be4da[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CSP_EL0_CapSysRegRead_e5b1ba121f8be4da el op0 op1 CRn op2 CRm) s" + unfolding CSP_EL0_CapSysRegRead_e5b1ba121f8be4da_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb el op0 op1 CRn op2 CRm) s" + unfolding CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CSP_EL2_CapSysRegRead_9b50d2f92d5520da[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CSP_EL2_CapSysRegRead_9b50d2f92d5520da el op0 op1 CRn op2 CRm) s" + unfolding CSP_EL2_CapSysRegRead_9b50d2f92d5520da_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc el op0 op1 CRn op2 CRm) s" + unfolding CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CTPIDR_EL0_CapSysRegRead_84b933ea55a77369[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CTPIDR_EL0_CapSysRegRead_84b933ea55a77369 el op0 op1 CRn op2 CRm) s" + unfolding CTPIDR_EL0_CapSysRegRead_84b933ea55a77369_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CTPIDR_EL1_CapSysRegRead_016308c12b886084[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CTPIDR_EL1_CapSysRegRead_016308c12b886084 el op0 op1 CRn op2 CRm) s" + unfolding CTPIDR_EL1_CapSysRegRead_016308c12b886084_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544 el op0 op1 CRn op2 CRm) s" + unfolding CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449 el op0 op1 CRn op2 CRm) s" + unfolding CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVBAR_EL12_CapSysRegRead_845c94ac498ff593[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CVBAR_EL12_CapSysRegRead_845c94ac498ff593 el op0 op1 CRn op2 CRm) s" + unfolding CVBAR_EL12_CapSysRegRead_845c94ac498ff593_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVBAR_EL1_CapSysRegRead_c42109445741a0d0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CVBAR_EL1_CapSysRegRead_c42109445741a0d0 el op0 op1 CRn op2 CRm) s" + unfolding CVBAR_EL1_CapSysRegRead_c42109445741a0d0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVBAR_EL2_CapSysRegRead_537232bbd7d69e00[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CVBAR_EL2_CapSysRegRead_537232bbd7d69e00 el op0 op1 CRn op2 CRm) s" + unfolding CVBAR_EL2_CapSysRegRead_537232bbd7d69e00_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1 el op0 op1 CRn op2 CRm) s" + unfolding CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DDC_CapSysRegRead_eabc4ea34a10a962[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DDC_CapSysRegRead_eabc4ea34a10a962 el op0 op1 CRn op2 CRm) s" + unfolding DDC_CapSysRegRead_eabc4ea34a10a962_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DDC_EL0_CapSysRegRead_e02bc676dce7fb51[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DDC_EL0_CapSysRegRead_e02bc676dce7fb51 el op0 op1 CRn op2 CRm) s" + unfolding DDC_EL0_CapSysRegRead_e02bc676dce7fb51_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DDC_EL1_CapSysRegRead_08f46354e9afc01e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DDC_EL1_CapSysRegRead_08f46354e9afc01e el op0 op1 CRn op2 CRm) s" + unfolding DDC_EL1_CapSysRegRead_08f46354e9afc01e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DDC_EL2_CapSysRegRead_6d2409222a719403[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DDC_EL2_CapSysRegRead_6d2409222a719403 el op0 op1 CRn op2 CRm) s" + unfolding DDC_EL2_CapSysRegRead_6d2409222a719403_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RCSP_EL0_CapSysRegRead_6a9b29b9027548c3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RCSP_EL0_CapSysRegRead_6a9b29b9027548c3 el op0 op1 CRn op2 CRm) s" + unfolding RCSP_EL0_CapSysRegRead_6a9b29b9027548c3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7 el op0 op1 CRn op2 CRm) s" + unfolding RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RDDC_EL0_CapSysRegRead_c188e736aa7b9beb[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RDDC_EL0_CapSysRegRead_c188e736aa7b9beb el op0 op1 CRn op2 CRm) s" + unfolding RDDC_EL0_CapSysRegRead_c188e736aa7b9beb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_AutoGen_CapSysRegRead[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_AutoGen_CapSysRegRead el op0 op1 CRn op2 CRm) s" + unfolding AArch64_AutoGen_CapSysRegRead_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DDC_read[traces_enabledI]: + "traces_enabled (DDC_read arg0) s" + unfolding DDC_read_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_AArch64_CapSysRegRead[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CapSysRegRead op0 op1 crn crm op2) s" + unfolding AArch64_CapSysRegRead_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ACTLR_EL1_SysRegWrite_338051dbe9bdf650[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ACTLR_EL1_SysRegWrite_338051dbe9bdf650 el op0 op1 CRn op2 CRm val_name) s" + unfolding ACTLR_EL1_SysRegWrite_338051dbe9bdf650_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ACTLR_EL2_SysRegWrite_416ec7c6fadd122d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ACTLR_EL2_SysRegWrite_416ec7c6fadd122d el op0 op1 CRn op2 CRm val_name) s" + unfolding ACTLR_EL2_SysRegWrite_416ec7c6fadd122d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ACTLR_EL3_SysRegWrite_c797d5a80525afa4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ACTLR_EL3_SysRegWrite_c797d5a80525afa4 el op0 op1 CRn op2 CRm val_name) s" + unfolding ACTLR_EL3_SysRegWrite_c797d5a80525afa4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR0_EL12_SysRegWrite_9fafb4f6dbddd904[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR0_EL12_SysRegWrite_9fafb4f6dbddd904 el op0 op1 CRn op2 CRm val_name) s" + unfolding AFSR0_EL12_SysRegWrite_9fafb4f6dbddd904_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR0_EL1_SysRegWrite_04474930979e1c86[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR0_EL1_SysRegWrite_04474930979e1c86 el op0 op1 CRn op2 CRm val_name) s" + unfolding AFSR0_EL1_SysRegWrite_04474930979e1c86_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR0_EL2_SysRegWrite_2f9da4789f5b4073[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR0_EL2_SysRegWrite_2f9da4789f5b4073 el op0 op1 CRn op2 CRm val_name) s" + unfolding AFSR0_EL2_SysRegWrite_2f9da4789f5b4073_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR0_EL3_SysRegWrite_e615501306210a25[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR0_EL3_SysRegWrite_e615501306210a25 el op0 op1 CRn op2 CRm val_name) s" + unfolding AFSR0_EL3_SysRegWrite_e615501306210a25_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR1_EL12_SysRegWrite_9dbf207cccd92d9d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR1_EL12_SysRegWrite_9dbf207cccd92d9d el op0 op1 CRn op2 CRm val_name) s" + unfolding AFSR1_EL12_SysRegWrite_9dbf207cccd92d9d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR1_EL1_SysRegWrite_6690138c9fdd136c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR1_EL1_SysRegWrite_6690138c9fdd136c el op0 op1 CRn op2 CRm val_name) s" + unfolding AFSR1_EL1_SysRegWrite_6690138c9fdd136c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR1_EL2_SysRegWrite_c0ebc4cc65472544[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR1_EL2_SysRegWrite_c0ebc4cc65472544 el op0 op1 CRn op2 CRm val_name) s" + unfolding AFSR1_EL2_SysRegWrite_c0ebc4cc65472544_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AFSR1_EL3_SysRegWrite_d776cc264803f49e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AFSR1_EL3_SysRegWrite_d776cc264803f49e el op0 op1 CRn op2 CRm val_name) s" + unfolding AFSR1_EL3_SysRegWrite_d776cc264803f49e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AMAIR_EL12_SysRegWrite_9c44aba2de7c2ff8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AMAIR_EL12_SysRegWrite_9c44aba2de7c2ff8 el op0 op1 CRn op2 CRm val_name) s" + unfolding AMAIR_EL12_SysRegWrite_9c44aba2de7c2ff8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AMAIR_EL1_SysRegWrite_0d9c3d92d9a71703[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AMAIR_EL1_SysRegWrite_0d9c3d92d9a71703 el op0 op1 CRn op2 CRm val_name) s" + unfolding AMAIR_EL1_SysRegWrite_0d9c3d92d9a71703_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AMAIR_EL2_SysRegWrite_9345da970d78b298[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AMAIR_EL2_SysRegWrite_9345da970d78b298 el op0 op1 CRn op2 CRm val_name) s" + unfolding AMAIR_EL2_SysRegWrite_9345da970d78b298_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AMAIR_EL3_SysRegWrite_622c473bfedac80a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AMAIR_EL3_SysRegWrite_622c473bfedac80a el op0 op1 CRn op2 CRm val_name) s" + unfolding AMAIR_EL3_SysRegWrite_622c473bfedac80a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CCTLR_EL0_SysRegWrite_a4d8c57cb436292b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CCTLR_EL0_SysRegWrite_a4d8c57cb436292b el op0 op1 CRn op2 CRm val_name) s" + unfolding CCTLR_EL0_SysRegWrite_a4d8c57cb436292b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CCTLR_EL12_SysRegWrite_c7d9d6463096d910[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CCTLR_EL12_SysRegWrite_c7d9d6463096d910 el op0 op1 CRn op2 CRm val_name) s" + unfolding CCTLR_EL12_SysRegWrite_c7d9d6463096d910_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CCTLR_EL1_SysRegWrite_dc20ad2a867ac9bf[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CCTLR_EL1_SysRegWrite_dc20ad2a867ac9bf el op0 op1 CRn op2 CRm val_name) s" + unfolding CCTLR_EL1_SysRegWrite_dc20ad2a867ac9bf_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CCTLR_EL2_SysRegWrite_65620c8ccb1113a5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CCTLR_EL2_SysRegWrite_65620c8ccb1113a5 el op0 op1 CRn op2 CRm val_name) s" + unfolding CCTLR_EL2_SysRegWrite_65620c8ccb1113a5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CCTLR_EL3_SysRegWrite_f5e936c8846e6fc7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CCTLR_EL3_SysRegWrite_f5e936c8846e6fc7 el op0 op1 CRn op2 CRm val_name) s" + unfolding CCTLR_EL3_SysRegWrite_f5e936c8846e6fc7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CHCR_EL2_SysRegWrite_dadda8ecf053e448[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CHCR_EL2_SysRegWrite_dadda8ecf053e448 el op0 op1 CRn op2 CRm val_name) s" + unfolding CHCR_EL2_SysRegWrite_dadda8ecf053e448_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTFRQ_EL0_SysRegWrite_0fac77f077759456[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTFRQ_EL0_SysRegWrite_0fac77f077759456 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTFRQ_EL0_SysRegWrite_0fac77f077759456_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHCTL_EL2_SysRegWrite_eb0cbec9f9398e0e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHCTL_EL2_SysRegWrite_eb0cbec9f9398e0e el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTHCTL_EL2_SysRegWrite_eb0cbec9f9398e0e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHP_CTL_EL2_SysRegWrite_92034fc54290a7b8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHP_CTL_EL2_SysRegWrite_92034fc54290a7b8 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTHP_CTL_EL2_SysRegWrite_92034fc54290a7b8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHP_CVAL_EL2_SysRegWrite_36de219faded7cbc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHP_CVAL_EL2_SysRegWrite_36de219faded7cbc el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTHP_CVAL_EL2_SysRegWrite_36de219faded7cbc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHP_TVAL_EL2_SysRegWrite_877bbf4f78f810b9[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHP_TVAL_EL2_SysRegWrite_877bbf4f78f810b9 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTHP_TVAL_EL2_SysRegWrite_877bbf4f78f810b9_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHV_CTL_EL2_SysRegWrite_ecc786a588fc8ab9[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHV_CTL_EL2_SysRegWrite_ecc786a588fc8ab9 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTHV_CTL_EL2_SysRegWrite_ecc786a588fc8ab9_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHV_CVAL_EL2_SysRegWrite_b3d7c631e2b3eaab[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHV_CVAL_EL2_SysRegWrite_b3d7c631e2b3eaab el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTHV_CVAL_EL2_SysRegWrite_b3d7c631e2b3eaab_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTHV_TVAL_EL2_SysRegWrite_e215d12d330397f1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTHV_TVAL_EL2_SysRegWrite_e215d12d330397f1 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTHV_TVAL_EL2_SysRegWrite_e215d12d330397f1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTKCTL_EL12_SysRegWrite_518123f17a6402e4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTKCTL_EL12_SysRegWrite_518123f17a6402e4 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTKCTL_EL12_SysRegWrite_518123f17a6402e4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTKCTL_EL1_SysRegWrite_9a7be69aa33bb9c2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTKCTL_EL1_SysRegWrite_9a7be69aa33bb9c2 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTKCTL_EL1_SysRegWrite_9a7be69aa33bb9c2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTPS_CTL_EL1_SysRegWrite_a0625fd9f7b035a8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTPS_CTL_EL1_SysRegWrite_a0625fd9f7b035a8 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTPS_CTL_EL1_SysRegWrite_a0625fd9f7b035a8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTPS_CVAL_EL1_SysRegWrite_f09243080b7c260d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTPS_CVAL_EL1_SysRegWrite_f09243080b7c260d el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTPS_CVAL_EL1_SysRegWrite_f09243080b7c260d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTPS_TVAL_EL1_SysRegWrite_a9b16e60037fa746[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTPS_TVAL_EL1_SysRegWrite_a9b16e60037fa746 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTPS_TVAL_EL1_SysRegWrite_a9b16e60037fa746_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTP_CTL_EL02_SysRegWrite_99a9da3e2454714e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTP_CTL_EL02_SysRegWrite_99a9da3e2454714e el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTP_CTL_EL02_SysRegWrite_99a9da3e2454714e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTP_CTL_EL0_SysRegWrite_137f81090c1357e6[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTP_CTL_EL0_SysRegWrite_137f81090c1357e6 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTP_CTL_EL0_SysRegWrite_137f81090c1357e6_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTP_CVAL_EL02_SysRegWrite_2b3e9ccfce186a4f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTP_CVAL_EL02_SysRegWrite_2b3e9ccfce186a4f el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTP_CVAL_EL02_SysRegWrite_2b3e9ccfce186a4f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTP_CVAL_EL0_SysRegWrite_d54c08ee0cf9aaf7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTP_CVAL_EL0_SysRegWrite_d54c08ee0cf9aaf7 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTP_CVAL_EL0_SysRegWrite_d54c08ee0cf9aaf7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTP_TVAL_EL02_SysRegWrite_caa9f2aa73cb6b96[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTP_TVAL_EL02_SysRegWrite_caa9f2aa73cb6b96 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTP_TVAL_EL02_SysRegWrite_caa9f2aa73cb6b96_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTP_TVAL_EL0_SysRegWrite_d7441eec23c3d524[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTP_TVAL_EL0_SysRegWrite_d7441eec23c3d524 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTP_TVAL_EL0_SysRegWrite_d7441eec23c3d524_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTVOFF_EL2_SysRegWrite_621ada4cfda60bcb[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTVOFF_EL2_SysRegWrite_621ada4cfda60bcb el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTVOFF_EL2_SysRegWrite_621ada4cfda60bcb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTV_CTL_EL02_SysRegWrite_d6cac9cc52dd8fec[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTV_CTL_EL02_SysRegWrite_d6cac9cc52dd8fec el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTV_CTL_EL02_SysRegWrite_d6cac9cc52dd8fec_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTV_CTL_EL0_SysRegWrite_e9fd22bae4b06064[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTV_CTL_EL0_SysRegWrite_e9fd22bae4b06064 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTV_CTL_EL0_SysRegWrite_e9fd22bae4b06064_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTV_CVAL_EL02_SysRegWrite_7548964ed28b5abb[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTV_CVAL_EL02_SysRegWrite_7548964ed28b5abb el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTV_CVAL_EL02_SysRegWrite_7548964ed28b5abb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTV_CVAL_EL0_SysRegWrite_f237c5c94ec92951[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTV_CVAL_EL0_SysRegWrite_f237c5c94ec92951 el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTV_CVAL_EL0_SysRegWrite_f237c5c94ec92951_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTV_TVAL_EL02_SysRegWrite_dc97f79a5f74078f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTV_TVAL_EL02_SysRegWrite_dc97f79a5f74078f el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTV_TVAL_EL02_SysRegWrite_dc97f79a5f74078f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CNTV_TVAL_EL0_SysRegWrite_903191acca729cda[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CNTV_TVAL_EL0_SysRegWrite_903191acca729cda el op0 op1 CRn op2 CRm val_name) s" + unfolding CNTV_TVAL_EL0_SysRegWrite_903191acca729cda_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CONTEXTIDR_EL12_SysRegWrite_33154953ae1b01d5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CONTEXTIDR_EL12_SysRegWrite_33154953ae1b01d5 el op0 op1 CRn op2 CRm val_name) s" + unfolding CONTEXTIDR_EL12_SysRegWrite_33154953ae1b01d5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CONTEXTIDR_EL1_SysRegWrite_5408e4e72af4e23d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CONTEXTIDR_EL1_SysRegWrite_5408e4e72af4e23d el op0 op1 CRn op2 CRm val_name) s" + unfolding CONTEXTIDR_EL1_SysRegWrite_5408e4e72af4e23d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CONTEXTIDR_EL2_SysRegWrite_27187b6dc7c5a748[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CONTEXTIDR_EL2_SysRegWrite_27187b6dc7c5a748 el op0 op1 CRn op2 CRm val_name) s" + unfolding CONTEXTIDR_EL2_SysRegWrite_27187b6dc7c5a748_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CPACR_EL12_SysRegWrite_637092a999939f8b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CPACR_EL12_SysRegWrite_637092a999939f8b el op0 op1 CRn op2 CRm val_name) s" + unfolding CPACR_EL12_SysRegWrite_637092a999939f8b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CPACR_EL1_SysRegWrite_00878a1f3e87823c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CPACR_EL1_SysRegWrite_00878a1f3e87823c el op0 op1 CRn op2 CRm val_name) s" + unfolding CPACR_EL1_SysRegWrite_00878a1f3e87823c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CPTR_EL2_SysRegWrite_5a082f460b1b2308[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CPTR_EL2_SysRegWrite_5a082f460b1b2308 el op0 op1 CRn op2 CRm val_name) s" + unfolding CPTR_EL2_SysRegWrite_5a082f460b1b2308_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CPTR_EL3_SysRegWrite_879d4b1bad53408b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CPTR_EL3_SysRegWrite_879d4b1bad53408b el op0 op1 CRn op2 CRm val_name) s" + unfolding CPTR_EL3_SysRegWrite_879d4b1bad53408b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CSCR_EL3_SysRegWrite_22b95c83b04d6c91[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CSCR_EL3_SysRegWrite_22b95c83b04d6c91 el op0 op1 CRn op2 CRm val_name) s" + unfolding CSCR_EL3_SysRegWrite_22b95c83b04d6c91_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CSSELR_EL1_SysRegWrite_1f9e1e0300c8783c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CSSELR_EL1_SysRegWrite_1f9e1e0300c8783c el op0 op1 CRn op2 CRm val_name) s" + unfolding CSSELR_EL1_SysRegWrite_1f9e1e0300c8783c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DACR32_EL2_SysRegWrite_a8bad0131817f121[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DACR32_EL2_SysRegWrite_a8bad0131817f121 el op0 op1 CRn op2 CRm val_name) s" + unfolding DACR32_EL2_SysRegWrite_a8bad0131817f121_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DAIF_SysRegWrite_3d31f214debf624b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DAIF_SysRegWrite_3d31f214debf624b el op0 op1 CRn op2 CRm val_name) s" + unfolding DAIF_SysRegWrite_3d31f214debf624b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGBCR_EL1_SysRegWrite_6730f3e3839510c5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGBCR_EL1_SysRegWrite_6730f3e3839510c5 el op0 op1 CRn op2 CRm val_name) s" + unfolding DBGBCR_EL1_SysRegWrite_6730f3e3839510c5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b el op0 op1 CRn op2 CRm val_name) s" + unfolding DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGCLAIMCLR_EL1_SysRegWrite_2a099a67767e57cf[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGCLAIMCLR_EL1_SysRegWrite_2a099a67767e57cf el op0 op1 CRn op2 CRm val_name) s" + unfolding DBGCLAIMCLR_EL1_SysRegWrite_2a099a67767e57cf_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGCLAIMSET_EL1_SysRegWrite_90e355b6a5730770[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGCLAIMSET_EL1_SysRegWrite_90e355b6a5730770 el op0 op1 CRn op2 CRm val_name) s" + unfolding DBGCLAIMSET_EL1_SysRegWrite_90e355b6a5730770_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGDTRTX_EL0_SysRegWrite_057e8c91e001a69f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGDTRTX_EL0_SysRegWrite_057e8c91e001a69f el op0 op1 CRn op2 CRm val_name) s" + unfolding DBGDTRTX_EL0_SysRegWrite_057e8c91e001a69f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGDTR_EL0_write[traces_enabledI]: + assumes "system_reg_access s" + shows "traces_enabled (DBGDTR_EL0_write val_name) s" + unfolding DBGDTR_EL0_write_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGDTR_EL0_SysRegWrite_c7246a22e06c7729[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGDTR_EL0_SysRegWrite_c7246a22e06c7729 el op0 op1 CRn op2 CRm val_name) s" + unfolding DBGDTR_EL0_SysRegWrite_c7246a22e06c7729_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGPRCR_EL1_SysRegWrite_710b60256172548e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGPRCR_EL1_SysRegWrite_710b60256172548e el op0 op1 CRn op2 CRm val_name) s" + unfolding DBGPRCR_EL1_SysRegWrite_710b60256172548e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGVCR32_EL2_SysRegWrite_769fbfe4fa51a4e5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGVCR32_EL2_SysRegWrite_769fbfe4fa51a4e5 el op0 op1 CRn op2 CRm val_name) s" + unfolding DBGVCR32_EL2_SysRegWrite_769fbfe4fa51a4e5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGWCR_EL1_SysRegWrite_6bda3acb5910d354[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGWCR_EL1_SysRegWrite_6bda3acb5910d354 el op0 op1 CRn op2 CRm val_name) s" + unfolding DBGWCR_EL1_SysRegWrite_6bda3acb5910d354_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DBGWVR_EL1_SysRegWrite_745b296ee53305ea[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DBGWVR_EL1_SysRegWrite_745b296ee53305ea el op0 op1 CRn op2 CRm val_name) s" + unfolding DBGWVR_EL1_SysRegWrite_745b296ee53305ea_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DISR_EL1_SysRegWrite_64517664b9260065[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DISR_EL1_SysRegWrite_64517664b9260065 el op0 op1 CRn op2 CRm val_name) s" + unfolding DISR_EL1_SysRegWrite_64517664b9260065_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DLR_EL0_write[traces_enabledI]: + assumes "system_reg_access s" + shows "traces_enabled (DLR_EL0_write val_name) s" + unfolding DLR_EL0_write_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DLR_EL0_SysRegWrite_a2d10a509fed3a63[traces_enabledI]: + "traces_enabled (DLR_EL0_SysRegWrite_a2d10a509fed3a63 el op0 op1 CRn op2 CRm val_name) s" + unfolding DLR_EL0_SysRegWrite_a2d10a509fed3a63_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ELR_EL12_SysRegWrite_6720e93c266dadea[traces_enabledI]: + "traces_enabled (ELR_EL12_SysRegWrite_6720e93c266dadea el op0 op1 CRn op2 CRm val_name) s" + unfolding ELR_EL12_SysRegWrite_6720e93c266dadea_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ELR_EL1_SysRegWrite_b6bd589b2dd79575[traces_enabledI]: + "traces_enabled (ELR_EL1_SysRegWrite_b6bd589b2dd79575 el op0 op1 CRn op2 CRm val_name) s" + unfolding ELR_EL1_SysRegWrite_b6bd589b2dd79575_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ELR_EL2_SysRegWrite_9f4ca59c1a88f1a9[traces_enabledI]: + "traces_enabled (ELR_EL2_SysRegWrite_9f4ca59c1a88f1a9 el op0 op1 CRn op2 CRm val_name) s" + unfolding ELR_EL2_SysRegWrite_9f4ca59c1a88f1a9_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ELR_EL3_SysRegWrite_8cd0b0c7f61ee7aa[traces_enabledI]: + "traces_enabled (ELR_EL3_SysRegWrite_8cd0b0c7f61ee7aa el op0 op1 CRn op2 CRm val_name) s" + unfolding ELR_EL3_SysRegWrite_8cd0b0c7f61ee7aa_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ERRSELR_EL1_SysRegWrite_551535eed30e26f9[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERRSELR_EL1_SysRegWrite_551535eed30e26f9 el op0 op1 CRn op2 CRm val_name) s" + unfolding ERRSELR_EL1_SysRegWrite_551535eed30e26f9_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ERXADDR_EL1_SysRegWrite_8a1eabc2959662e8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERXADDR_EL1_SysRegWrite_8a1eabc2959662e8 el op0 op1 CRn op2 CRm val_name) s" + unfolding ERXADDR_EL1_SysRegWrite_8a1eabc2959662e8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ERXCTLR_EL1_SysRegWrite_acca1e102ba86b42[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERXCTLR_EL1_SysRegWrite_acca1e102ba86b42 el op0 op1 CRn op2 CRm val_name) s" + unfolding ERXCTLR_EL1_SysRegWrite_acca1e102ba86b42_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ERXMISC0_EL1_SysRegWrite_822ceca9b10b2621[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERXMISC0_EL1_SysRegWrite_822ceca9b10b2621 el op0 op1 CRn op2 CRm val_name) s" + unfolding ERXMISC0_EL1_SysRegWrite_822ceca9b10b2621_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ERXMISC1_EL1_SysRegWrite_9a9ef77b5fd82587[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERXMISC1_EL1_SysRegWrite_9a9ef77b5fd82587 el op0 op1 CRn op2 CRm val_name) s" + unfolding ERXMISC1_EL1_SysRegWrite_9a9ef77b5fd82587_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ERXSTATUS_EL1_SysRegWrite_f0798b4207ec0193[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ERXSTATUS_EL1_SysRegWrite_f0798b4207ec0193 el op0 op1 CRn op2 CRm val_name) s" + unfolding ERXSTATUS_EL1_SysRegWrite_f0798b4207ec0193_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ESR_EL12_SysRegWrite_2b2d6012ba438548[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ESR_EL12_SysRegWrite_2b2d6012ba438548 el op0 op1 CRn op2 CRm val_name) s" + unfolding ESR_EL12_SysRegWrite_2b2d6012ba438548_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ESR_EL1_SysRegWrite_a8ce40896bd70a6b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ESR_EL1_SysRegWrite_a8ce40896bd70a6b el op0 op1 CRn op2 CRm val_name) s" + unfolding ESR_EL1_SysRegWrite_a8ce40896bd70a6b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ESR_EL2_SysRegWrite_a10e84e3bd1020c8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ESR_EL2_SysRegWrite_a10e84e3bd1020c8 el op0 op1 CRn op2 CRm val_name) s" + unfolding ESR_EL2_SysRegWrite_a10e84e3bd1020c8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ESR_EL3_SysRegWrite_195a2e1a5b40464e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ESR_EL3_SysRegWrite_195a2e1a5b40464e el op0 op1 CRn op2 CRm val_name) s" + unfolding ESR_EL3_SysRegWrite_195a2e1a5b40464e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FAR_EL12_SysRegWrite_78f825940e556299[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FAR_EL12_SysRegWrite_78f825940e556299 el op0 op1 CRn op2 CRm val_name) s" + unfolding FAR_EL12_SysRegWrite_78f825940e556299_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FAR_EL1_SysRegWrite_fc0bd224b62cc089[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FAR_EL1_SysRegWrite_fc0bd224b62cc089 el op0 op1 CRn op2 CRm val_name) s" + unfolding FAR_EL1_SysRegWrite_fc0bd224b62cc089_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FAR_EL2_SysRegWrite_6370aabce83a1613[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FAR_EL2_SysRegWrite_6370aabce83a1613 el op0 op1 CRn op2 CRm val_name) s" + unfolding FAR_EL2_SysRegWrite_6370aabce83a1613_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FAR_EL3_SysRegWrite_397cfda85a093e9d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FAR_EL3_SysRegWrite_397cfda85a093e9d el op0 op1 CRn op2 CRm val_name) s" + unfolding FAR_EL3_SysRegWrite_397cfda85a093e9d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPCR_SysRegWrite_4f255cf55390cebb[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FPCR_SysRegWrite_4f255cf55390cebb el op0 op1 CRn op2 CRm val_name) s" + unfolding FPCR_SysRegWrite_4f255cf55390cebb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPEXC32_EL2_SysRegWrite_9f180ead5c4d6735[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FPEXC32_EL2_SysRegWrite_9f180ead5c4d6735 el op0 op1 CRn op2 CRm val_name) s" + unfolding FPEXC32_EL2_SysRegWrite_9f180ead5c4d6735_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPSR_SysRegWrite_413aed98a94900de[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FPSR_SysRegWrite_413aed98a94900de el op0 op1 CRn op2 CRm val_name) s" + unfolding FPSR_SysRegWrite_413aed98a94900de_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_HACR_EL2_SysRegWrite_5b2ca32fcb39ecab[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (HACR_EL2_SysRegWrite_5b2ca32fcb39ecab el op0 op1 CRn op2 CRm val_name) s" + unfolding HACR_EL2_SysRegWrite_5b2ca32fcb39ecab_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_HCR_EL2_SysRegWrite_6fc18e07a17fd5a2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (HCR_EL2_SysRegWrite_6fc18e07a17fd5a2 el op0 op1 CRn op2 CRm val_name) s" + unfolding HCR_EL2_SysRegWrite_6fc18e07a17fd5a2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_HPFAR_EL2_SysRegWrite_20417eccdd6b4768[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (HPFAR_EL2_SysRegWrite_20417eccdd6b4768 el op0 op1 CRn op2 CRm val_name) s" + unfolding HPFAR_EL2_SysRegWrite_20417eccdd6b4768_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_HSTR_EL2_SysRegWrite_391a605c0bfb9d1e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (HSTR_EL2_SysRegWrite_391a605c0bfb9d1e el op0 op1 CRn op2 CRm val_name) s" + unfolding HSTR_EL2_SysRegWrite_391a605c0bfb9d1e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_AP0R_EL1_SysRegWrite_949897f971748acc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_AP0R_EL1_SysRegWrite_949897f971748acc el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_AP0R_EL1_SysRegWrite_949897f971748acc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_AP1R_EL1_SysRegWrite_55167410f7650dea[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_AP1R_EL1_SysRegWrite_55167410f7650dea el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_AP1R_EL1_SysRegWrite_55167410f7650dea_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_ASGI1R_EL1_SysRegWrite_c163c25adc1b1354[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_ASGI1R_EL1_SysRegWrite_c163c25adc1b1354 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_ASGI1R_EL1_SysRegWrite_c163c25adc1b1354_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_BPR0_EL1_SysRegWrite_10028206553f3655[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_BPR0_EL1_SysRegWrite_10028206553f3655 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_BPR0_EL1_SysRegWrite_10028206553f3655_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_BPR1_EL1_SysRegWrite_a633b2e9f3626d9b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_BPR1_EL1_SysRegWrite_a633b2e9f3626d9b el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_BPR1_EL1_SysRegWrite_a633b2e9f3626d9b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_CTLR_EL1_SysRegWrite_8ec3f4b67393eba8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_CTLR_EL1_SysRegWrite_8ec3f4b67393eba8 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_CTLR_EL1_SysRegWrite_8ec3f4b67393eba8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_CTLR_EL3_SysRegWrite_ecc8b41b177c53e8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_CTLR_EL3_SysRegWrite_ecc8b41b177c53e8 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_CTLR_EL3_SysRegWrite_ecc8b41b177c53e8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_DIR_EL1_SysRegWrite_77fadeda7efde9c5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_DIR_EL1_SysRegWrite_77fadeda7efde9c5 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_DIR_EL1_SysRegWrite_77fadeda7efde9c5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_EOIR0_EL1_SysRegWrite_9c0fae08cd7a2444[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_EOIR0_EL1_SysRegWrite_9c0fae08cd7a2444 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_EOIR0_EL1_SysRegWrite_9c0fae08cd7a2444_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_EOIR1_EL1_SysRegWrite_f065db56e179bf6e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_EOIR1_EL1_SysRegWrite_f065db56e179bf6e el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_EOIR1_EL1_SysRegWrite_f065db56e179bf6e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_IGRPEN0_EL1_SysRegWrite_b94e4d10f7a33382[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_IGRPEN0_EL1_SysRegWrite_b94e4d10f7a33382 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_IGRPEN0_EL1_SysRegWrite_b94e4d10f7a33382_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_IGRPEN1_EL1_SysRegWrite_c36dfa556252f6b4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_IGRPEN1_EL1_SysRegWrite_c36dfa556252f6b4 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_IGRPEN1_EL1_SysRegWrite_c36dfa556252f6b4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_IGRPEN1_EL3_SysRegWrite_6f1db000a53b40ca[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_IGRPEN1_EL3_SysRegWrite_6f1db000a53b40ca el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_IGRPEN1_EL3_SysRegWrite_6f1db000a53b40ca_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_PMR_EL1_SysRegWrite_8bb2caa31e7d5e1b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_PMR_EL1_SysRegWrite_8bb2caa31e7d5e1b el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_PMR_EL1_SysRegWrite_8bb2caa31e7d5e1b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_SGI0R_EL1_SysRegWrite_ba6d1066ea6fbbb7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_SGI0R_EL1_SysRegWrite_ba6d1066ea6fbbb7 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_SGI0R_EL1_SysRegWrite_ba6d1066ea6fbbb7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_SGI1R_EL1_SysRegWrite_0da31fe6c2e1b098[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_SGI1R_EL1_SysRegWrite_0da31fe6c2e1b098 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_SGI1R_EL1_SysRegWrite_0da31fe6c2e1b098_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_SRE_EL1_SysRegWrite_d2efb75caa67d019[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_SRE_EL1_SysRegWrite_d2efb75caa67d019 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_SRE_EL1_SysRegWrite_d2efb75caa67d019_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_SRE_EL2_SysRegWrite_39c314f677b8ec2e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_SRE_EL2_SysRegWrite_39c314f677b8ec2e el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_SRE_EL2_SysRegWrite_39c314f677b8ec2e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICC_SRE_EL3_SysRegWrite_c0af2dd58a7e1d22[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICC_SRE_EL3_SysRegWrite_c0af2dd58a7e1d22 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICC_SRE_EL3_SysRegWrite_c0af2dd58a7e1d22_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_AP0R_EL2_SysRegWrite_9517857bb550d699[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_AP0R_EL2_SysRegWrite_9517857bb550d699 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICH_AP0R_EL2_SysRegWrite_9517857bb550d699_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_AP1R_EL2_SysRegWrite_20f46016b54a3395[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_AP1R_EL2_SysRegWrite_20f46016b54a3395 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICH_AP1R_EL2_SysRegWrite_20f46016b54a3395_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_HCR_EL2_SysRegWrite_2fea52a15cd7dbe5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_HCR_EL2_SysRegWrite_2fea52a15cd7dbe5 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICH_HCR_EL2_SysRegWrite_2fea52a15cd7dbe5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_LR_EL2_SysRegWrite_8b291f94259261d2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_LR_EL2_SysRegWrite_8b291f94259261d2 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICH_LR_EL2_SysRegWrite_8b291f94259261d2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ICH_VMCR_EL2_SysRegWrite_86a315374f6b5205[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ICH_VMCR_EL2_SysRegWrite_86a315374f6b5205 el op0 op1 CRn op2 CRm val_name) s" + unfolding ICH_VMCR_EL2_SysRegWrite_86a315374f6b5205_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_IFSR32_EL2_SysRegWrite_6ce25b2b11e30403[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (IFSR32_EL2_SysRegWrite_6ce25b2b11e30403 el op0 op1 CRn op2 CRm val_name) s" + unfolding IFSR32_EL2_SysRegWrite_6ce25b2b11e30403_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_LORC_EL1_SysRegWrite_7100b979c23fc52e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (LORC_EL1_SysRegWrite_7100b979c23fc52e el op0 op1 CRn op2 CRm val_name) s" + unfolding LORC_EL1_SysRegWrite_7100b979c23fc52e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_LOREA_EL1_SysRegWrite_2d068511b7f5ce7b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (LOREA_EL1_SysRegWrite_2d068511b7f5ce7b el op0 op1 CRn op2 CRm val_name) s" + unfolding LOREA_EL1_SysRegWrite_2d068511b7f5ce7b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_LORN_EL1_SysRegWrite_bde03c74e878b099[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (LORN_EL1_SysRegWrite_bde03c74e878b099 el op0 op1 CRn op2 CRm val_name) s" + unfolding LORN_EL1_SysRegWrite_bde03c74e878b099_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_LORSA_EL1_SysRegWrite_9ba633e967136731[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (LORSA_EL1_SysRegWrite_9ba633e967136731 el op0 op1 CRn op2 CRm val_name) s" + unfolding LORSA_EL1_SysRegWrite_9ba633e967136731_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MAIR_EL12_SysRegWrite_da2526ed2008ed50[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MAIR_EL12_SysRegWrite_da2526ed2008ed50 el op0 op1 CRn op2 CRm val_name) s" + unfolding MAIR_EL12_SysRegWrite_da2526ed2008ed50_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MAIR_EL1_SysRegWrite_45d8150aaf31e3b9[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MAIR_EL1_SysRegWrite_45d8150aaf31e3b9 el op0 op1 CRn op2 CRm val_name) s" + unfolding MAIR_EL1_SysRegWrite_45d8150aaf31e3b9_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MAIR_EL2_SysRegWrite_4e3422c1776528f5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MAIR_EL2_SysRegWrite_4e3422c1776528f5 el op0 op1 CRn op2 CRm val_name) s" + unfolding MAIR_EL2_SysRegWrite_4e3422c1776528f5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MAIR_EL3_SysRegWrite_d15af780e0b4e771[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MAIR_EL3_SysRegWrite_d15af780e0b4e771 el op0 op1 CRn op2 CRm val_name) s" + unfolding MAIR_EL3_SysRegWrite_d15af780e0b4e771_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MDCCINT_EL1_SysRegWrite_1e6a37984aec7145[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MDCCINT_EL1_SysRegWrite_1e6a37984aec7145 el op0 op1 CRn op2 CRm val_name) s" + unfolding MDCCINT_EL1_SysRegWrite_1e6a37984aec7145_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MDCR_EL2_SysRegWrite_3f12005c8c459bf3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MDCR_EL2_SysRegWrite_3f12005c8c459bf3 el op0 op1 CRn op2 CRm val_name) s" + unfolding MDCR_EL2_SysRegWrite_3f12005c8c459bf3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MDCR_EL3_SysRegWrite_37dff5fa83ad16ed[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MDCR_EL3_SysRegWrite_37dff5fa83ad16ed el op0 op1 CRn op2 CRm val_name) s" + unfolding MDCR_EL3_SysRegWrite_37dff5fa83ad16ed_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MDSCR_EL1_SysRegWrite_94ddb1e46aff4dfa[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MDSCR_EL1_SysRegWrite_94ddb1e46aff4dfa el op0 op1 CRn op2 CRm val_name) s" + unfolding MDSCR_EL1_SysRegWrite_94ddb1e46aff4dfa_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAM0_EL1_SysRegWrite_88f6c0c61a59ac23[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAM0_EL1_SysRegWrite_88f6c0c61a59ac23 el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAM0_EL1_SysRegWrite_88f6c0c61a59ac23_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAM2_EL2_write[traces_enabledI]: + assumes "system_reg_access s" + shows "traces_enabled (MPAM2_EL2_write val_name) s" + unfolding MPAM2_EL2_write_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAM1_EL1_write[traces_enabledI]: + assumes "system_reg_access s" + shows "traces_enabled (MPAM1_EL1_write val_name) s" + unfolding MPAM1_EL1_write_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAM1_EL12_SysRegWrite_2cbbb0edf5787671[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAM1_EL12_SysRegWrite_2cbbb0edf5787671 el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAM1_EL12_SysRegWrite_2cbbb0edf5787671_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAM1_EL1_SysRegWrite_cd02720a3298b1c6[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAM1_EL1_SysRegWrite_cd02720a3298b1c6 el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAM1_EL1_SysRegWrite_cd02720a3298b1c6_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAM2_EL2_SysRegWrite_d6bae8d18aebb554[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAM2_EL2_SysRegWrite_d6bae8d18aebb554 el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAM2_EL2_SysRegWrite_d6bae8d18aebb554_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAM3_EL3_SysRegWrite_bb55d8a9d90e05e3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAM3_EL3_SysRegWrite_bb55d8a9d90e05e3 el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAM3_EL3_SysRegWrite_bb55d8a9d90e05e3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMHCR_EL2_SysRegWrite_e38755d6111336b8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMHCR_EL2_SysRegWrite_e38755d6111336b8 el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAMHCR_EL2_SysRegWrite_e38755d6111336b8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM0_EL2_SysRegWrite_c00108111630aa84[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM0_EL2_SysRegWrite_c00108111630aa84 el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAMVPM0_EL2_SysRegWrite_c00108111630aa84_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM1_EL2_SysRegWrite_81a739cc4bd1cd46[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM1_EL2_SysRegWrite_81a739cc4bd1cd46 el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAMVPM1_EL2_SysRegWrite_81a739cc4bd1cd46_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM2_EL2_SysRegWrite_20a1b54bc18980b1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM2_EL2_SysRegWrite_20a1b54bc18980b1 el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAMVPM2_EL2_SysRegWrite_20a1b54bc18980b1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM3_EL2_SysRegWrite_d2a71d8e23cc67af[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM3_EL2_SysRegWrite_d2a71d8e23cc67af el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAMVPM3_EL2_SysRegWrite_d2a71d8e23cc67af_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM4_EL2_SysRegWrite_2d0a10731399829d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM4_EL2_SysRegWrite_2d0a10731399829d el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAMVPM4_EL2_SysRegWrite_2d0a10731399829d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM5_EL2_SysRegWrite_ec98ca57d40ac9ec[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM5_EL2_SysRegWrite_ec98ca57d40ac9ec el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAMVPM5_EL2_SysRegWrite_ec98ca57d40ac9ec_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM6_EL2_SysRegWrite_0934853fee68e9bd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM6_EL2_SysRegWrite_0934853fee68e9bd el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAMVPM6_EL2_SysRegWrite_0934853fee68e9bd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPM7_EL2_SysRegWrite_dfb7f68750df7012[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPM7_EL2_SysRegWrite_dfb7f68750df7012 el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAMVPM7_EL2_SysRegWrite_dfb7f68750df7012_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MPAMVPMV_EL2_SysRegWrite_abd8d27e91fadf85[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MPAMVPMV_EL2_SysRegWrite_abd8d27e91fadf85 el op0 op1 CRn op2 CRm val_name) s" + unfolding MPAMVPMV_EL2_SysRegWrite_abd8d27e91fadf85_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_OSDLR_EL1_SysRegWrite_591fd96d91652c64[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (OSDLR_EL1_SysRegWrite_591fd96d91652c64 el op0 op1 CRn op2 CRm val_name) s" + unfolding OSDLR_EL1_SysRegWrite_591fd96d91652c64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_OSDTRRX_EL1_SysRegWrite_6dc5d8521b60df8a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (OSDTRRX_EL1_SysRegWrite_6dc5d8521b60df8a el op0 op1 CRn op2 CRm val_name) s" + unfolding OSDTRRX_EL1_SysRegWrite_6dc5d8521b60df8a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_OSDTRTX_EL1_SysRegWrite_9ba0c4a85d0c1de5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (OSDTRTX_EL1_SysRegWrite_9ba0c4a85d0c1de5 el op0 op1 CRn op2 CRm val_name) s" + unfolding OSDTRTX_EL1_SysRegWrite_9ba0c4a85d0c1de5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_OSECCR_EL1_SysRegWrite_cabf381bfb822732[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (OSECCR_EL1_SysRegWrite_cabf381bfb822732 el op0 op1 CRn op2 CRm val_name) s" + unfolding OSECCR_EL1_SysRegWrite_cabf381bfb822732_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_OSLAR_EL1_SysRegWrite_582d77c57653b2c4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (OSLAR_EL1_SysRegWrite_582d77c57653b2c4 el op0 op1 CRn op2 CRm val_name) s" + unfolding OSLAR_EL1_SysRegWrite_582d77c57653b2c4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PAR_EL1_SysRegWrite_aa92c70a4b5d5873[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PAR_EL1_SysRegWrite_aa92c70a4b5d5873 el op0 op1 CRn op2 CRm val_name) s" + unfolding PAR_EL1_SysRegWrite_aa92c70a4b5d5873_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMBLIMITR_EL1_SysRegWrite_ddfe2ba603df6628[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMBLIMITR_EL1_SysRegWrite_ddfe2ba603df6628 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMBLIMITR_EL1_SysRegWrite_ddfe2ba603df6628_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMBPTR_EL1_SysRegWrite_32441d8a7a2b9601[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMBPTR_EL1_SysRegWrite_32441d8a7a2b9601 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMBPTR_EL1_SysRegWrite_32441d8a7a2b9601_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMBSR_EL1_SysRegWrite_ff19dc948509312f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMBSR_EL1_SysRegWrite_ff19dc948509312f el op0 op1 CRn op2 CRm val_name) s" + unfolding PMBSR_EL1_SysRegWrite_ff19dc948509312f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMCCFILTR_EL0_SysRegWrite_42277f001664525c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMCCFILTR_EL0_SysRegWrite_42277f001664525c el op0 op1 CRn op2 CRm val_name) s" + unfolding PMCCFILTR_EL0_SysRegWrite_42277f001664525c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMCCNTR_EL0_SysRegWrite_1d21e0789830cbf9[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMCCNTR_EL0_SysRegWrite_1d21e0789830cbf9 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMCCNTR_EL0_SysRegWrite_1d21e0789830cbf9_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMCNTENCLR_EL0_SysRegWrite_bf2c4fae1a891e1b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMCNTENCLR_EL0_SysRegWrite_bf2c4fae1a891e1b el op0 op1 CRn op2 CRm val_name) s" + unfolding PMCNTENCLR_EL0_SysRegWrite_bf2c4fae1a891e1b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMCNTENSET_EL0_SysRegWrite_227af2773d320cb1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMCNTENSET_EL0_SysRegWrite_227af2773d320cb1 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMCNTENSET_EL0_SysRegWrite_227af2773d320cb1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMCR_EL0_SysRegWrite_87ae64466e09f89a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMCR_EL0_SysRegWrite_87ae64466e09f89a el op0 op1 CRn op2 CRm val_name) s" + unfolding PMCR_EL0_SysRegWrite_87ae64466e09f89a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMEVCNTR_EL0_SysRegWrite_c197579331ed9cbb[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMEVCNTR_EL0_SysRegWrite_c197579331ed9cbb el op0 op1 CRn op2 CRm val_name) s" + unfolding PMEVCNTR_EL0_SysRegWrite_c197579331ed9cbb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMEVTYPER_EL0_SysRegWrite_3e6ae16cd645ec0d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMEVTYPER_EL0_SysRegWrite_3e6ae16cd645ec0d el op0 op1 CRn op2 CRm val_name) s" + unfolding PMEVTYPER_EL0_SysRegWrite_3e6ae16cd645ec0d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMINTENCLR_EL1_SysRegWrite_1ebd7bf3738fe872[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMINTENCLR_EL1_SysRegWrite_1ebd7bf3738fe872 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMINTENCLR_EL1_SysRegWrite_1ebd7bf3738fe872_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMINTENSET_EL1_SysRegWrite_dd2481ad892e3441[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMINTENSET_EL1_SysRegWrite_dd2481ad892e3441 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMINTENSET_EL1_SysRegWrite_dd2481ad892e3441_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMOVSCLR_EL0_SysRegWrite_9dfa73cda394af99[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMOVSCLR_EL0_SysRegWrite_9dfa73cda394af99 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMOVSCLR_EL0_SysRegWrite_9dfa73cda394af99_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMOVSSET_EL0_SysRegWrite_cfbbfe3b81fe4290[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMOVSSET_EL0_SysRegWrite_cfbbfe3b81fe4290 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMOVSSET_EL0_SysRegWrite_cfbbfe3b81fe4290_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSCR_EL12_SysRegWrite_fef9a94f50c2763b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSCR_EL12_SysRegWrite_fef9a94f50c2763b el op0 op1 CRn op2 CRm val_name) s" + unfolding PMSCR_EL12_SysRegWrite_fef9a94f50c2763b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSCR_EL1_SysRegWrite_9798a89ab6804fe0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSCR_EL1_SysRegWrite_9798a89ab6804fe0 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMSCR_EL1_SysRegWrite_9798a89ab6804fe0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSCR_EL2_SysRegWrite_02cd14dd325ed94b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSCR_EL2_SysRegWrite_02cd14dd325ed94b el op0 op1 CRn op2 CRm val_name) s" + unfolding PMSCR_EL2_SysRegWrite_02cd14dd325ed94b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSELR_EL0_SysRegWrite_18613307de8564a3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSELR_EL0_SysRegWrite_18613307de8564a3 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMSELR_EL0_SysRegWrite_18613307de8564a3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSEVFR_EL1_SysRegWrite_6524c56cd8a10057[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSEVFR_EL1_SysRegWrite_6524c56cd8a10057 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMSEVFR_EL1_SysRegWrite_6524c56cd8a10057_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSFCR_EL1_SysRegWrite_44d58271848f0db1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSFCR_EL1_SysRegWrite_44d58271848f0db1 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMSFCR_EL1_SysRegWrite_44d58271848f0db1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSICR_EL1_SysRegWrite_1e74423ea1c96ae7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSICR_EL1_SysRegWrite_1e74423ea1c96ae7 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMSICR_EL1_SysRegWrite_1e74423ea1c96ae7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSIRR_EL1_SysRegWrite_bb25878486c35a36[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSIRR_EL1_SysRegWrite_bb25878486c35a36 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMSIRR_EL1_SysRegWrite_bb25878486c35a36_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSLATFR_EL1_SysRegWrite_5c8b43a6a65c8272[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSLATFR_EL1_SysRegWrite_5c8b43a6a65c8272 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMSLATFR_EL1_SysRegWrite_5c8b43a6a65c8272_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMSWINC_EL0_SysRegWrite_cce1d915b163d5e3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMSWINC_EL0_SysRegWrite_cce1d915b163d5e3 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMSWINC_EL0_SysRegWrite_cce1d915b163d5e3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMUSERENR_EL0_SysRegWrite_e7535626e3360c36[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMUSERENR_EL0_SysRegWrite_e7535626e3360c36 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMUSERENR_EL0_SysRegWrite_e7535626e3360c36_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMXEVCNTR_EL0_SysRegWrite_20b0a6df43a7d4ef[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMXEVCNTR_EL0_SysRegWrite_20b0a6df43a7d4ef el op0 op1 CRn op2 CRm val_name) s" + unfolding PMXEVCNTR_EL0_SysRegWrite_20b0a6df43a7d4ef_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_PMXEVTYPER_EL0_SysRegWrite_82fb55a6e723e983[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (PMXEVTYPER_EL0_SysRegWrite_82fb55a6e723e983 el op0 op1 CRn op2 CRm val_name) s" + unfolding PMXEVTYPER_EL0_SysRegWrite_82fb55a6e723e983_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RMR_EL1_SysRegWrite_0ae19f794f511c7a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RMR_EL1_SysRegWrite_0ae19f794f511c7a el op0 op1 CRn op2 CRm val_name) s" + unfolding RMR_EL1_SysRegWrite_0ae19f794f511c7a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RMR_EL2_SysRegWrite_df7b9a989e2495d2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RMR_EL2_SysRegWrite_df7b9a989e2495d2 el op0 op1 CRn op2 CRm val_name) s" + unfolding RMR_EL2_SysRegWrite_df7b9a989e2495d2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RMR_EL3_SysRegWrite_2849130fc457929e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RMR_EL3_SysRegWrite_2849130fc457929e el op0 op1 CRn op2 CRm val_name) s" + unfolding RMR_EL3_SysRegWrite_2849130fc457929e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RSP_EL0_SysRegWrite_5b2edb6edd27507d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RSP_EL0_SysRegWrite_5b2edb6edd27507d el op0 op1 CRn op2 CRm val_name) s" + unfolding RSP_EL0_SysRegWrite_5b2edb6edd27507d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RTPIDR_EL0_SysRegWrite_74d55919bd0ab5f3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RTPIDR_EL0_SysRegWrite_74d55919bd0ab5f3 el op0 op1 CRn op2 CRm val_name) s" + unfolding RTPIDR_EL0_SysRegWrite_74d55919bd0ab5f3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S3_op1_CCn_CCm_op2_SysRegWrite_22dd63287f599042[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S3_op1_CCn_CCm_op2_SysRegWrite_22dd63287f599042 el op0 op1 CRn op2 CRm val_name) s" + unfolding S3_op1_CCn_CCm_op2_SysRegWrite_22dd63287f599042_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCR_EL3_SysRegWrite_020d082781fa9b72[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCR_EL3_SysRegWrite_020d082781fa9b72 el op0 op1 CRn op2 CRm val_name) s" + unfolding SCR_EL3_SysRegWrite_020d082781fa9b72_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCTLR_EL12_SysRegWrite_302de25977d2a0ca[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCTLR_EL12_SysRegWrite_302de25977d2a0ca el op0 op1 CRn op2 CRm val_name) s" + unfolding SCTLR_EL12_SysRegWrite_302de25977d2a0ca_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCTLR_EL1_SysRegWrite_711b0546c662c54d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCTLR_EL1_SysRegWrite_711b0546c662c54d el op0 op1 CRn op2 CRm val_name) s" + unfolding SCTLR_EL1_SysRegWrite_711b0546c662c54d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCTLR_EL2_SysRegWrite_ff61a6f00288b28a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCTLR_EL2_SysRegWrite_ff61a6f00288b28a el op0 op1 CRn op2 CRm val_name) s" + unfolding SCTLR_EL2_SysRegWrite_ff61a6f00288b28a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCTLR_EL3_SysRegWrite_5b7cc79e5ea93a8f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCTLR_EL3_SysRegWrite_5b7cc79e5ea93a8f el op0 op1 CRn op2 CRm val_name) s" + unfolding SCTLR_EL3_SysRegWrite_5b7cc79e5ea93a8f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCXTNUM_EL0_write[traces_enabledI]: + "traces_enabled (SCXTNUM_EL0_write val_name) s" + unfolding SCXTNUM_EL0_write_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_SCXTNUM_EL0_SysRegWrite_9dbee2793d69c02e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCXTNUM_EL0_SysRegWrite_9dbee2793d69c02e el op0 op1 CRn op2 CRm val_name) s" + unfolding SCXTNUM_EL0_SysRegWrite_9dbee2793d69c02e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCXTNUM_EL12_SysRegWrite_ba74367909393c9b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCXTNUM_EL12_SysRegWrite_ba74367909393c9b el op0 op1 CRn op2 CRm val_name) s" + unfolding SCXTNUM_EL12_SysRegWrite_ba74367909393c9b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCXTNUM_EL1_SysRegWrite_6467f6f26a31cece[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCXTNUM_EL1_SysRegWrite_6467f6f26a31cece el op0 op1 CRn op2 CRm val_name) s" + unfolding SCXTNUM_EL1_SysRegWrite_6467f6f26a31cece_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCXTNUM_EL2_SysRegWrite_2fcbb6503badb23c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCXTNUM_EL2_SysRegWrite_2fcbb6503badb23c el op0 op1 CRn op2 CRm val_name) s" + unfolding SCXTNUM_EL2_SysRegWrite_2fcbb6503badb23c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SCXTNUM_EL3_SysRegWrite_b39fe9ab09a67ecd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SCXTNUM_EL3_SysRegWrite_b39fe9ab09a67ecd el op0 op1 CRn op2 CRm val_name) s" + unfolding SCXTNUM_EL3_SysRegWrite_b39fe9ab09a67ecd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SDER32_EL3_SysRegWrite_69011ff5e95ac923[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SDER32_EL3_SysRegWrite_69011ff5e95ac923 el op0 op1 CRn op2 CRm val_name) s" + unfolding SDER32_EL3_SysRegWrite_69011ff5e95ac923_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SPSel_SysRegWrite_c849e120e8533c8c[traces_enabledI]: + "traces_enabled (SPSel_SysRegWrite_c849e120e8533c8c el op0 op1 CRn op2 CRm val_name) s" + unfolding SPSel_SysRegWrite_c849e120e8533c8c_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_SP_EL0_SysRegWrite_78f870c69d82f9e2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SP_EL0_SysRegWrite_78f870c69d82f9e2 el op0 op1 CRn op2 CRm val_name) s" + unfolding SP_EL0_SysRegWrite_78f870c69d82f9e2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SP_EL1_SysRegWrite_84ae51cf4bf77caa[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SP_EL1_SysRegWrite_84ae51cf4bf77caa el op0 op1 CRn op2 CRm val_name) s" + unfolding SP_EL1_SysRegWrite_84ae51cf4bf77caa_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SP_EL2_SysRegWrite_a29ffeac6d3856e5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (SP_EL2_SysRegWrite_a29ffeac6d3856e5 el op0 op1 CRn op2 CRm val_name) s" + unfolding SP_EL2_SysRegWrite_a29ffeac6d3856e5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TCR_EL12_SysRegWrite_64a7f44c6ddaa0f8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TCR_EL12_SysRegWrite_64a7f44c6ddaa0f8 el op0 op1 CRn op2 CRm val_name) s" + unfolding TCR_EL12_SysRegWrite_64a7f44c6ddaa0f8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TCR_EL1_SysRegWrite_c27e6fc190bb0f0b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TCR_EL1_SysRegWrite_c27e6fc190bb0f0b el op0 op1 CRn op2 CRm val_name) s" + unfolding TCR_EL1_SysRegWrite_c27e6fc190bb0f0b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TCR_EL2_SysRegWrite_5e38279a245750c4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TCR_EL2_SysRegWrite_5e38279a245750c4 el op0 op1 CRn op2 CRm val_name) s" + unfolding TCR_EL2_SysRegWrite_5e38279a245750c4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TCR_EL3_SysRegWrite_3b3587015a3d20f4[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TCR_EL3_SysRegWrite_3b3587015a3d20f4 el op0 op1 CRn op2 CRm val_name) s" + unfolding TCR_EL3_SysRegWrite_3b3587015a3d20f4_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TPIDRRO_EL0_SysRegWrite_20bedffb2581e57d[traces_enabledI]: + "traces_enabled (TPIDRRO_EL0_SysRegWrite_20bedffb2581e57d el op0 op1 CRn op2 CRm val_name) s" + unfolding TPIDRRO_EL0_SysRegWrite_20bedffb2581e57d_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_TPIDR_EL0_SysRegWrite_6b1ef76c828f0bf5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TPIDR_EL0_SysRegWrite_6b1ef76c828f0bf5 el op0 op1 CRn op2 CRm val_name) s" + unfolding TPIDR_EL0_SysRegWrite_6b1ef76c828f0bf5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TPIDR_EL1_SysRegWrite_566127c19bf948d1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TPIDR_EL1_SysRegWrite_566127c19bf948d1 el op0 op1 CRn op2 CRm val_name) s" + unfolding TPIDR_EL1_SysRegWrite_566127c19bf948d1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TPIDR_EL2_SysRegWrite_adfab02a898d4b19[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TPIDR_EL2_SysRegWrite_adfab02a898d4b19 el op0 op1 CRn op2 CRm val_name) s" + unfolding TPIDR_EL2_SysRegWrite_adfab02a898d4b19_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TPIDR_EL3_SysRegWrite_08e0e9cc5d3f6f5c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TPIDR_EL3_SysRegWrite_08e0e9cc5d3f6f5c el op0 op1 CRn op2 CRm val_name) s" + unfolding TPIDR_EL3_SysRegWrite_08e0e9cc5d3f6f5c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TTBR0_EL12_SysRegWrite_fd9df8519bfad5c0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR0_EL12_SysRegWrite_fd9df8519bfad5c0 el op0 op1 CRn op2 CRm val_name) s" + unfolding TTBR0_EL12_SysRegWrite_fd9df8519bfad5c0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TTBR0_EL1_SysRegWrite_8a149790a79e2eab[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR0_EL1_SysRegWrite_8a149790a79e2eab el op0 op1 CRn op2 CRm val_name) s" + unfolding TTBR0_EL1_SysRegWrite_8a149790a79e2eab_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TTBR0_EL2_SysRegWrite_7cd39d4a24a70e7f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR0_EL2_SysRegWrite_7cd39d4a24a70e7f el op0 op1 CRn op2 CRm val_name) s" + unfolding TTBR0_EL2_SysRegWrite_7cd39d4a24a70e7f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TTBR0_EL3_SysRegWrite_7e091a8effc9ee7f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR0_EL3_SysRegWrite_7e091a8effc9ee7f el op0 op1 CRn op2 CRm val_name) s" + unfolding TTBR0_EL3_SysRegWrite_7e091a8effc9ee7f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TTBR1_EL12_SysRegWrite_4fbeb1f28c2e8107[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR1_EL12_SysRegWrite_4fbeb1f28c2e8107 el op0 op1 CRn op2 CRm val_name) s" + unfolding TTBR1_EL12_SysRegWrite_4fbeb1f28c2e8107_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TTBR1_EL1_SysRegWrite_89690e4d3c87217b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR1_EL1_SysRegWrite_89690e4d3c87217b el op0 op1 CRn op2 CRm val_name) s" + unfolding TTBR1_EL1_SysRegWrite_89690e4d3c87217b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TTBR1_EL2_SysRegWrite_59fad32bc548b47a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TTBR1_EL2_SysRegWrite_59fad32bc548b47a el op0 op1 CRn op2 CRm val_name) s" + unfolding TTBR1_EL2_SysRegWrite_59fad32bc548b47a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VBAR_EL12_SysRegWrite_a20f8f7f07b5cf7a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VBAR_EL12_SysRegWrite_a20f8f7f07b5cf7a el op0 op1 CRn op2 CRm val_name) s" + unfolding VBAR_EL12_SysRegWrite_a20f8f7f07b5cf7a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VBAR_EL1_SysRegWrite_29ba7540e032fce6[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VBAR_EL1_SysRegWrite_29ba7540e032fce6 el op0 op1 CRn op2 CRm val_name) s" + unfolding VBAR_EL1_SysRegWrite_29ba7540e032fce6_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VBAR_EL2_SysRegWrite_d5657e8591e8e22a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VBAR_EL2_SysRegWrite_d5657e8591e8e22a el op0 op1 CRn op2 CRm val_name) s" + unfolding VBAR_EL2_SysRegWrite_d5657e8591e8e22a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VBAR_EL3_SysRegWrite_1da603c27eb5f668[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VBAR_EL3_SysRegWrite_1da603c27eb5f668 el op0 op1 CRn op2 CRm val_name) s" + unfolding VBAR_EL3_SysRegWrite_1da603c27eb5f668_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VDISR_EL2_SysRegWrite_8b2c23874e253f64[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VDISR_EL2_SysRegWrite_8b2c23874e253f64 el op0 op1 CRn op2 CRm val_name) s" + unfolding VDISR_EL2_SysRegWrite_8b2c23874e253f64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VMPIDR_EL2_SysRegWrite_c153d7c8b5628bd5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VMPIDR_EL2_SysRegWrite_c153d7c8b5628bd5 el op0 op1 CRn op2 CRm val_name) s" + unfolding VMPIDR_EL2_SysRegWrite_c153d7c8b5628bd5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VPIDR_EL2_SysRegWrite_0dbf139af5a73d1f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VPIDR_EL2_SysRegWrite_0dbf139af5a73d1f el op0 op1 CRn op2 CRm val_name) s" + unfolding VPIDR_EL2_SysRegWrite_0dbf139af5a73d1f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VSESR_EL2_SysRegWrite_e989f4bcf0ae8aa6[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VSESR_EL2_SysRegWrite_e989f4bcf0ae8aa6 el op0 op1 CRn op2 CRm val_name) s" + unfolding VSESR_EL2_SysRegWrite_e989f4bcf0ae8aa6_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VTCR_EL2_SysRegWrite_d49abb8b3aa0eff3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VTCR_EL2_SysRegWrite_d49abb8b3aa0eff3 el op0 op1 CRn op2 CRm val_name) s" + unfolding VTCR_EL2_SysRegWrite_d49abb8b3aa0eff3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VTTBR_EL2_SysRegWrite_5198ee0e793550a5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VTTBR_EL2_SysRegWrite_5198ee0e793550a5 el op0 op1 CRn op2 CRm val_name) s" + unfolding VTTBR_EL2_SysRegWrite_5198ee0e793550a5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_AutoGen_SysRegWrite[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_AutoGen_SysRegWrite el op0 op1 CRn op2 CRm val_name) s" + unfolding AArch64_AutoGen_SysRegWrite_def bind_assoc + by (traces_enabled_step intro: assms)+ + +lemma traces_enabled_C_set[traces_enabledI]: + assumes "value_name \ derivable_caps s" + shows "traces_enabled (C_set n value_name) s" + unfolding C_set_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_ResetGeneralRegisters[traces_enabledI]: + "traces_enabled (AArch64_ResetGeneralRegisters arg0) s" + unfolding AArch64_ResetGeneralRegisters_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_AArch64_SysRegWrite[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "(op0 = 3 \ op1 \ {0, 4, 6} \ op2 = 2 \ crn = 12 \ crm = 0) \ no_system_reg_access" + shows "traces_enabled (AArch64_SysRegWrite op0 op1 crn crm op2 val) s" + unfolding AArch64_SysRegWrite_def bind_assoc + by (traces_enabledI assms: assms Run_AArch64_AutoGen_SysRegWrite_RMR_EL_system_reg_access[OF _ inv_sysreg_trace_assms]; blast) + +lemma traces_enabled_CDBGDTR_EL0_CapSysRegWrite_336052f10e4a36b7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CDBGDTR_EL0_CapSysRegWrite_336052f10e4a36b7 el op0 op1 CRn op2 CRm val_name) s" + unfolding CDBGDTR_EL0_CapSysRegWrite_336052f10e4a36b7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CDLR_EL0_CapSysRegWrite_2763be7daadf3c03[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CDLR_EL0_CapSysRegWrite_2763be7daadf3c03 el op0 op1 CRn op2 CRm val_name) s" + unfolding CDLR_EL0_CapSysRegWrite_2763be7daadf3c03_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CELR_EL12_CapSysRegWrite_a1507df00ba9d725[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CELR_EL12_CapSysRegWrite_a1507df00ba9d725 el op0 op1 CRn op2 CRm val_name) s" + unfolding CELR_EL12_CapSysRegWrite_a1507df00ba9d725_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CELR_EL1_CapSysRegWrite_33a9b4f0fad89fe8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CELR_EL1_CapSysRegWrite_33a9b4f0fad89fe8 el op0 op1 CRn op2 CRm val_name) s" + unfolding CELR_EL1_CapSysRegWrite_33a9b4f0fad89fe8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CELR_EL2_CapSysRegWrite_8d32fe1dd5ad0417[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CELR_EL2_CapSysRegWrite_8d32fe1dd5ad0417 el op0 op1 CRn op2 CRm val_name) s" + unfolding CELR_EL2_CapSysRegWrite_8d32fe1dd5ad0417_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CELR_EL3_CapSysRegWrite_55e82fec5d907003[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CELR_EL3_CapSysRegWrite_55e82fec5d907003 el op0 op1 CRn op2 CRm val_name) s" + unfolding CELR_EL3_CapSysRegWrite_55e82fec5d907003_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CID_EL0_CapSysRegWrite_8c1c5cf69181759f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CID_EL0_CapSysRegWrite_8c1c5cf69181759f el op0 op1 CRn op2 CRm val_name) s" + unfolding CID_EL0_CapSysRegWrite_8c1c5cf69181759f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CSP_EL0_CapSysRegWrite_ee1d127810ef0f04[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CSP_EL0_CapSysRegWrite_ee1d127810ef0f04 el op0 op1 CRn op2 CRm val_name) s" + unfolding CSP_EL0_CapSysRegWrite_ee1d127810ef0f04_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CSP_EL1_CapSysRegWrite_f4579d836810c21a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CSP_EL1_CapSysRegWrite_f4579d836810c21a el op0 op1 CRn op2 CRm val_name) s" + unfolding CSP_EL1_CapSysRegWrite_f4579d836810c21a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CSP_EL2_CapSysRegWrite_59c69d74679ef283[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CSP_EL2_CapSysRegWrite_59c69d74679ef283 el op0 op1 CRn op2 CRm val_name) s" + unfolding CSP_EL2_CapSysRegWrite_59c69d74679ef283_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CTPIDRRO_EL0_CapSysRegWrite_e64109ff95ad4800[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CTPIDRRO_EL0_CapSysRegWrite_e64109ff95ad4800 el op0 op1 CRn op2 CRm val_name) s" + unfolding CTPIDRRO_EL0_CapSysRegWrite_e64109ff95ad4800_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CTPIDR_EL0_CapSysRegWrite_8f94c4d256adadf0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CTPIDR_EL0_CapSysRegWrite_8f94c4d256adadf0 el op0 op1 CRn op2 CRm val_name) s" + unfolding CTPIDR_EL0_CapSysRegWrite_8f94c4d256adadf0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CTPIDR_EL1_CapSysRegWrite_3190df090d2d128f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CTPIDR_EL1_CapSysRegWrite_3190df090d2d128f el op0 op1 CRn op2 CRm val_name) s" + unfolding CTPIDR_EL1_CapSysRegWrite_3190df090d2d128f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CTPIDR_EL2_CapSysRegWrite_a740113e578c9b32[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CTPIDR_EL2_CapSysRegWrite_a740113e578c9b32 el op0 op1 CRn op2 CRm val_name) s" + unfolding CTPIDR_EL2_CapSysRegWrite_a740113e578c9b32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CTPIDR_EL3_CapSysRegWrite_376b7d525b15b21b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CTPIDR_EL3_CapSysRegWrite_376b7d525b15b21b el op0 op1 CRn op2 CRm val_name) s" + unfolding CTPIDR_EL3_CapSysRegWrite_376b7d525b15b21b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVBAR_EL12_CapSysRegWrite_3fd157cf974c31e5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CVBAR_EL12_CapSysRegWrite_3fd157cf974c31e5 el op0 op1 CRn op2 CRm val_name) s" + unfolding CVBAR_EL12_CapSysRegWrite_3fd157cf974c31e5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVBAR_EL1_CapSysRegWrite_bbad0575f41fce2f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CVBAR_EL1_CapSysRegWrite_bbad0575f41fce2f el op0 op1 CRn op2 CRm val_name) s" + unfolding CVBAR_EL1_CapSysRegWrite_bbad0575f41fce2f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVBAR_EL2_CapSysRegWrite_2a412e2b2c0a0a2b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CVBAR_EL2_CapSysRegWrite_2a412e2b2c0a0a2b el op0 op1 CRn op2 CRm val_name) s" + unfolding CVBAR_EL2_CapSysRegWrite_2a412e2b2c0a0a2b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVBAR_EL3_CapSysRegWrite_f3c8bbee84b292db[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (CVBAR_EL3_CapSysRegWrite_f3c8bbee84b292db el op0 op1 CRn op2 CRm val_name) s" + unfolding CVBAR_EL3_CapSysRegWrite_f3c8bbee84b292db_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DDC_CapSysRegWrite_9bc98e4e82148914[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (DDC_CapSysRegWrite_9bc98e4e82148914 el op0 op1 CRn op2 CRm val_name) s" + unfolding DDC_CapSysRegWrite_9bc98e4e82148914_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DDC_EL0_CapSysRegWrite_1a928678ff9b43a6[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (DDC_EL0_CapSysRegWrite_1a928678ff9b43a6 el op0 op1 CRn op2 CRm val_name) s" + unfolding DDC_EL0_CapSysRegWrite_1a928678ff9b43a6_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DDC_EL1_CapSysRegWrite_e7ecb5b1f0c49d28[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (DDC_EL1_CapSysRegWrite_e7ecb5b1f0c49d28 el op0 op1 CRn op2 CRm val_name) s" + unfolding DDC_EL1_CapSysRegWrite_e7ecb5b1f0c49d28_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DDC_EL2_CapSysRegWrite_b4142a2dcadf2a34[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (DDC_EL2_CapSysRegWrite_b4142a2dcadf2a34 el op0 op1 CRn op2 CRm val_name) s" + unfolding DDC_EL2_CapSysRegWrite_b4142a2dcadf2a34_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RCSP_EL0_CapSysRegWrite_d8f83400674fbeeb[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (RCSP_EL0_CapSysRegWrite_d8f83400674fbeeb el op0 op1 CRn op2 CRm val_name) s" + unfolding RCSP_EL0_CapSysRegWrite_d8f83400674fbeeb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RCTPIDR_EL0_CapSysRegWrite_27f7c47e137c72f8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (RCTPIDR_EL0_CapSysRegWrite_27f7c47e137c72f8 el op0 op1 CRn op2 CRm val_name) s" + unfolding RCTPIDR_EL0_CapSysRegWrite_27f7c47e137c72f8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RDDC_EL0_CapSysRegWrite_c528d1b2eb785ad7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (RDDC_EL0_CapSysRegWrite_c528d1b2eb785ad7 el op0 op1 CRn op2 CRm val_name) s" + unfolding RDDC_EL0_CapSysRegWrite_c528d1b2eb785ad7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_AutoGen_CapSysRegWrite[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (AArch64_AutoGen_CapSysRegWrite el op0 op1 CRn op2 CRm val_name) s" + unfolding AArch64_AutoGen_CapSysRegWrite_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DDC_set[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "value_name \ derivable_caps s" + shows "traces_enabled (DDC_set value_name) s" + unfolding DDC_set_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CapSysRegWrite[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (AArch64_CapSysRegWrite op0 op1 crn crm op2 val_name) s" + unfolding AArch64_CapSysRegWrite_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ALLE1IS_SysOpsWrite_8b81b55e2116aad3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ALLE1IS_SysOpsWrite_8b81b55e2116aad3 el op0 op1 CRn op2 CRm val_name) s" + unfolding ALLE1IS_SysOpsWrite_8b81b55e2116aad3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ALLE1_SysOpsWrite_69364bedc72cbe96[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ALLE1_SysOpsWrite_69364bedc72cbe96 el op0 op1 CRn op2 CRm val_name) s" + unfolding ALLE1_SysOpsWrite_69364bedc72cbe96_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_UndefinedFault[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_UndefinedFault arg0) s" + unfolding AArch64_UndefinedFault_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_UndefinedFault[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (UndefinedFault arg0) s" + unfolding UndefinedFault_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TLBI_ALLE2IS[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TLBI_ALLE2IS arg0) s" + unfolding TLBI_ALLE2IS_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ALLE2IS_SysOpsWrite_3a173239947b2c25[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ALLE2IS_SysOpsWrite_3a173239947b2c25 el op0 op1 CRn op2 CRm val_name) s" + unfolding ALLE2IS_SysOpsWrite_3a173239947b2c25_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TLBI_ALLE2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TLBI_ALLE2 arg0) s" + unfolding TLBI_ALLE2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ALLE2_SysOpsWrite_19c7b5110a5efe1d[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ALLE2_SysOpsWrite_19c7b5110a5efe1d el op0 op1 CRn op2 CRm val_name) s" + unfolding ALLE2_SysOpsWrite_19c7b5110a5efe1d_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ALLE3IS_SysOpsWrite_e64b79b4c41910fb[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ALLE3IS_SysOpsWrite_e64b79b4c41910fb el op0 op1 CRn op2 CRm val_name) s" + unfolding ALLE3IS_SysOpsWrite_e64b79b4c41910fb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ALLE3_SysOpsWrite_5835ce2f987f3d36[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ALLE3_SysOpsWrite_5835ce2f987f3d36 el op0 op1 CRn op2 CRm val_name) s" + unfolding ALLE3_SysOpsWrite_5835ce2f987f3d36_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ASIDE1IS_SysOpsWrite_5a5dff91f113e41e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ASIDE1IS_SysOpsWrite_5a5dff91f113e41e el op0 op1 CRn op2 CRm val_name) s" + unfolding ASIDE1IS_SysOpsWrite_5a5dff91f113e41e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ASIDE1_SysOpsWrite_7ba7a3df395925e0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ASIDE1_SysOpsWrite_7ba7a3df395925e0 el op0 op1 CRn op2 CRm val_name) s" + unfolding ASIDE1_SysOpsWrite_7ba7a3df395925e0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_CISW[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_CISW val_name) s" + unfolding DC_CISW_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CISW_SysOpsWrite_5321b1c3157dccce[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CISW_SysOpsWrite_5321b1c3157dccce el op0 op1 CRn op2 CRm val_name) s" + unfolding CISW_SysOpsWrite_5321b1c3157dccce_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_BreakpointException[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_BreakpointException fault) s" + unfolding AArch64_BreakpointException_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_DataAbort[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_DataAbort vaddress fault) s" + unfolding AArch64_DataAbort_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_InstructionAbort[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_InstructionAbort vaddress fault) s" + unfolding AArch64_InstructionAbort_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_WatchpointException[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_WatchpointException vaddress fault) s" + unfolding AArch64_WatchpointException_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_Abort[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_Abort vaddress fault) s" + unfolding AArch64_Abort_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CheckBreakpoint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckBreakpoint vaddress size__arg) s" + unfolding AArch64_CheckBreakpoint_def bind_assoc + by (traces_enabledI assms: assms elim: Run_and_HaltOnBreakpointOrWatchpoint_system_reg_access) + +lemma traces_enabled_AArch64_CheckWatchpoint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckWatchpoint vaddress acctype iswrite size__arg) s" + unfolding AArch64_CheckWatchpoint_def bind_assoc + by (traces_enabledI assms: assms elim: Run_and_HaltOnBreakpointOrWatchpoint_system_reg_access) + +lemma traces_enabled_AArch64_CheckDebug[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckDebug vaddress acctype iswrite size__arg) s" + unfolding AArch64_CheckDebug_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_TranslateAddressWithTag[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_TranslateAddressWithTag vaddress acctype iswrite wasaligned size__arg iswritevalidcap) s" + unfolding AArch64_TranslateAddressWithTag_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_TranslateAddress[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_TranslateAddress vaddress acctype iswrite wasaligned size__arg) s" + unfolding AArch64_TranslateAddress_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_CIVAC[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_CIVAC val_name) s" + unfolding DC_CIVAC_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VAddress[traces_enabledI]: + "traces_enabled (VAddress addr) s" + unfolding VAddress_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_MorelloCheckForCMO[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "cval \ derivable_caps s" + shows "traces_enabled (MorelloCheckForCMO cval requested_perms acctype) s" + unfolding MorelloCheckForCMO_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_CIVAC0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_CIVAC0 val_name__arg) s" + unfolding DC_CIVAC0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CIVAC_SysOpsWrite_47ad60ecb930d217[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CIVAC_SysOpsWrite_47ad60ecb930d217 el op0 op1 CRn op2 CRm val_name) s" + unfolding CIVAC_SysOpsWrite_47ad60ecb930d217_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_CSW[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_CSW val_name) s" + unfolding DC_CSW_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CSW_SysOpsWrite_9544819da3ebaa1b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CSW_SysOpsWrite_9544819da3ebaa1b el op0 op1 CRn op2 CRm val_name) s" + unfolding CSW_SysOpsWrite_9544819da3ebaa1b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_CVAC[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_CVAC val_name) s" + unfolding DC_CVAC_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_CVAC0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_CVAC0 val_name__arg) s" + unfolding DC_CVAC0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVAC_SysOpsWrite_c7d2e911c691cc6b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CVAC_SysOpsWrite_c7d2e911c691cc6b el op0 op1 CRn op2 CRm val_name) s" + unfolding CVAC_SysOpsWrite_c7d2e911c691cc6b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_CVAP[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_CVAP val_name) s" + unfolding DC_CVAP_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_CVADP[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_CVADP val_name) s" + unfolding DC_CVADP_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVADP_SysOpsWrite_9953ef108c01d34a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CVADP_SysOpsWrite_9953ef108c01d34a el op0 op1 CRn op2 CRm val_name) s" + unfolding CVADP_SysOpsWrite_9953ef108c01d34a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVAP_SysOpsWrite_a43f75867888e74a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CVAP_SysOpsWrite_a43f75867888e74a el op0 op1 CRn op2 CRm val_name) s" + unfolding CVAP_SysOpsWrite_a43f75867888e74a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_CVAU[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_CVAU val_name) s" + unfolding DC_CVAU_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_CVAU0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_CVAU0 val_name__arg) s" + unfolding DC_CVAU0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVAU_SysOpsWrite_4a72bbc98a17973c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CVAU_SysOpsWrite_4a72bbc98a17973c el op0 op1 CRn op2 CRm val_name) s" + unfolding CVAU_SysOpsWrite_4a72bbc98a17973c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_IC_IALLUIS[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (IC_IALLUIS arg0) s" + unfolding IC_IALLUIS_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_IALLUIS_SysOpsWrite_9a906c8365100aff[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (IALLUIS_SysOpsWrite_9a906c8365100aff el op0 op1 CRn op2 CRm val_name) s" + unfolding IALLUIS_SysOpsWrite_9a906c8365100aff_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_IC_IALLU[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (IC_IALLU arg0) s" + unfolding IC_IALLU_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_IALLU_SysOpsWrite_81563797a4921929[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (IALLU_SysOpsWrite_81563797a4921929 el op0 op1 CRn op2 CRm val_name) s" + unfolding IALLU_SysOpsWrite_81563797a4921929_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_IPAS2E1IS_SysOpsWrite_ed4be1feae90b987[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (IPAS2E1IS_SysOpsWrite_ed4be1feae90b987 el op0 op1 CRn op2 CRm val_name) s" + unfolding IPAS2E1IS_SysOpsWrite_ed4be1feae90b987_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_IPAS2E1_SysOpsWrite_a65fef0d99f9428f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (IPAS2E1_SysOpsWrite_a65fef0d99f9428f el op0 op1 CRn op2 CRm val_name) s" + unfolding IPAS2E1_SysOpsWrite_a65fef0d99f9428f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_IPAS2LE1IS_SysOpsWrite_5a72848dfefa19f3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (IPAS2LE1IS_SysOpsWrite_5a72848dfefa19f3 el op0 op1 CRn op2 CRm val_name) s" + unfolding IPAS2LE1IS_SysOpsWrite_5a72848dfefa19f3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_IPAS2LE1_SysOpsWrite_10ca7ac6abdfed50[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (IPAS2LE1_SysOpsWrite_10ca7ac6abdfed50 el op0 op1 CRn op2 CRm val_name) s" + unfolding IPAS2LE1_SysOpsWrite_10ca7ac6abdfed50_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_ISW[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_ISW val_name) s" + unfolding DC_ISW_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ISW_SysOpsWrite_d5fceb001aa0aa7a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ISW_SysOpsWrite_d5fceb001aa0aa7a el op0 op1 CRn op2 CRm val_name) s" + unfolding ISW_SysOpsWrite_d5fceb001aa0aa7a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_IVAC[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_IVAC val_name) s" + unfolding DC_IVAC_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_IVAC0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_IVAC0 val_name__arg) s" + unfolding DC_IVAC0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_IVAC_SysOpsWrite_41b93e0e56e4f107[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (IVAC_SysOpsWrite_41b93e0e56e4f107 el op0 op1 CRn op2 CRm val_name) s" + unfolding IVAC_SysOpsWrite_41b93e0e56e4f107_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_IC_IVAU[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (IC_IVAU val_name) s" + unfolding IC_IVAU_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_IVAU_SysOpsWrite_2dfe97b748dd324e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (IVAU_SysOpsWrite_2dfe97b748dd324e el op0 op1 CRn op2 CRm val_name) s" + unfolding IVAU_SysOpsWrite_2dfe97b748dd324e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RCTX_SysOpsWrite_bcc8cd10f2e68999[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RCTX_SysOpsWrite_bcc8cd10f2e68999 el op0 op1 CRn op2 CRm val_name) s" + unfolding RCTX_SysOpsWrite_bcc8cd10f2e68999_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RCTX_SysOpsWrite_c287513d0d3e8e92[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RCTX_SysOpsWrite_c287513d0d3e8e92 el op0 op1 CRn op2 CRm val_name) s" + unfolding RCTX_SysOpsWrite_c287513d0d3e8e92_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_RCTX_SysOpsWrite_d614ec87236c038f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (RCTX_SysOpsWrite_d614ec87236c038f el op0 op1 CRn op2 CRm val_name) s" + unfolding RCTX_SysOpsWrite_d614ec87236c038f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_AT_S1Ex[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_AT_S1Ex val_name el iswrite) s" + unfolding AArch64_AT_S1Ex_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_AT_S12Ex[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_AT_S12Ex val_name el iswrite) s" + unfolding AArch64_AT_S12Ex_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S12E0R[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S12E0R val_name) s" + unfolding AT_S12E0R_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S1E0R[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S1E0R val_name) s" + unfolding AT_S1E0R_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S12E0R_SysOpsWrite_4df3d544cba811b7[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S12E0R_SysOpsWrite_4df3d544cba811b7 el op0 op1 CRn op2 CRm val_name) s" + unfolding S12E0R_SysOpsWrite_4df3d544cba811b7_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S12E0W[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S12E0W val_name) s" + unfolding AT_S12E0W_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S1E0W[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S1E0W val_name) s" + unfolding AT_S1E0W_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S12E0W_SysOpsWrite_1dbb37d4af097406[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S12E0W_SysOpsWrite_1dbb37d4af097406 el op0 op1 CRn op2 CRm val_name) s" + unfolding S12E0W_SysOpsWrite_1dbb37d4af097406_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S12E1R[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S12E1R val_name) s" + unfolding AT_S12E1R_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S1E1R[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S1E1R val_name) s" + unfolding AT_S1E1R_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S12E1R_SysOpsWrite_e44276c8f24d398f[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S12E1R_SysOpsWrite_e44276c8f24d398f el op0 op1 CRn op2 CRm val_name) s" + unfolding S12E1R_SysOpsWrite_e44276c8f24d398f_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S12E1W[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S12E1W val_name) s" + unfolding AT_S12E1W_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S1E1W[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S1E1W val_name) s" + unfolding AT_S1E1W_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S12E1W_SysOpsWrite_c8b72d75cad90601[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S12E1W_SysOpsWrite_c8b72d75cad90601 el op0 op1 CRn op2 CRm val_name) s" + unfolding S12E1W_SysOpsWrite_c8b72d75cad90601_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S1E0R_SysOpsWrite_0a1e21ea5b4c8722[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S1E0R_SysOpsWrite_0a1e21ea5b4c8722 el op0 op1 CRn op2 CRm val_name) s" + unfolding S1E0R_SysOpsWrite_0a1e21ea5b4c8722_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S1E0W_SysOpsWrite_d102d49fd92af65a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S1E0W_SysOpsWrite_d102d49fd92af65a el op0 op1 CRn op2 CRm val_name) s" + unfolding S1E0W_SysOpsWrite_d102d49fd92af65a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S1E1RP[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S1E1RP val_name) s" + unfolding AT_S1E1RP_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S1E1RP_SysOpsWrite_4a6b1f71ee0182ab[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S1E1RP_SysOpsWrite_4a6b1f71ee0182ab el op0 op1 CRn op2 CRm val_name) s" + unfolding S1E1RP_SysOpsWrite_4a6b1f71ee0182ab_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S1E1R_SysOpsWrite_018a577644c5d23c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S1E1R_SysOpsWrite_018a577644c5d23c el op0 op1 CRn op2 CRm val_name) s" + unfolding S1E1R_SysOpsWrite_018a577644c5d23c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S1E1WP[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S1E1WP val_name) s" + unfolding AT_S1E1WP_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S1E1WP_SysOpsWrite_bb1ddb9112effe2a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S1E1WP_SysOpsWrite_bb1ddb9112effe2a el op0 op1 CRn op2 CRm val_name) s" + unfolding S1E1WP_SysOpsWrite_bb1ddb9112effe2a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S1E1W_SysOpsWrite_df64f2f63c0911fd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S1E1W_SysOpsWrite_df64f2f63c0911fd el op0 op1 CRn op2 CRm val_name) s" + unfolding S1E1W_SysOpsWrite_df64f2f63c0911fd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S1E2R[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S1E2R val_name) s" + unfolding AT_S1E2R_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S1E2R_SysOpsWrite_5e865a96c06417c8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S1E2R_SysOpsWrite_5e865a96c06417c8 el op0 op1 CRn op2 CRm val_name) s" + unfolding S1E2R_SysOpsWrite_5e865a96c06417c8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S1E2W[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S1E2W val_name) s" + unfolding AT_S1E2W_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S1E2W_SysOpsWrite_1649806418453f02[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S1E2W_SysOpsWrite_1649806418453f02 el op0 op1 CRn op2 CRm val_name) s" + unfolding S1E2W_SysOpsWrite_1649806418453f02_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S1E3R[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S1E3R val_name) s" + unfolding AT_S1E3R_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S1E3R_SysOpsWrite_6476f20e79e358be[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S1E3R_SysOpsWrite_6476f20e79e358be el op0 op1 CRn op2 CRm val_name) s" + unfolding S1E3R_SysOpsWrite_6476f20e79e358be_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AT_S1E3W[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AT_S1E3W val_name) s" + unfolding AT_S1E3W_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S1E3W_SysOpsWrite_e92e083e28fa4dd0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S1E3W_SysOpsWrite_e92e083e28fa4dd0 el op0 op1 CRn op2 CRm val_name) s" + unfolding S1E3W_SysOpsWrite_e92e083e28fa4dd0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_S1_op1_Cn_Cm_op2_SysOpsWrite_d6b17d94c0df44bc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (S1_op1_Cn_Cm_op2_SysOpsWrite_d6b17d94c0df44bc el op0 op1 CRn op2 CRm val_name) s" + unfolding S1_op1_Cn_Cm_op2_SysOpsWrite_d6b17d94c0df44bc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VAAE1IS_SysOpsWrite_c22cd5a1dc8e7320[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VAAE1IS_SysOpsWrite_c22cd5a1dc8e7320 el op0 op1 CRn op2 CRm val_name) s" + unfolding VAAE1IS_SysOpsWrite_c22cd5a1dc8e7320_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VAAE1_SysOpsWrite_8498b4db5afbed38[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VAAE1_SysOpsWrite_8498b4db5afbed38 el op0 op1 CRn op2 CRm val_name) s" + unfolding VAAE1_SysOpsWrite_8498b4db5afbed38_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VAALE1IS_SysOpsWrite_5c8056a5b649fe2e[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VAALE1IS_SysOpsWrite_5c8056a5b649fe2e el op0 op1 CRn op2 CRm val_name) s" + unfolding VAALE1IS_SysOpsWrite_5c8056a5b649fe2e_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VAALE1_SysOpsWrite_d3bec3a19881fb1c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VAALE1_SysOpsWrite_d3bec3a19881fb1c el op0 op1 CRn op2 CRm val_name) s" + unfolding VAALE1_SysOpsWrite_d3bec3a19881fb1c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VAE1IS_SysOpsWrite_5eac1ac5cb4e76ff[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VAE1IS_SysOpsWrite_5eac1ac5cb4e76ff el op0 op1 CRn op2 CRm val_name) s" + unfolding VAE1IS_SysOpsWrite_5eac1ac5cb4e76ff_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VAE1_SysOpsWrite_09dbfc0bf1b19b11[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VAE1_SysOpsWrite_09dbfc0bf1b19b11 el op0 op1 CRn op2 CRm val_name) s" + unfolding VAE1_SysOpsWrite_09dbfc0bf1b19b11_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TLBI_VAE2IS[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TLBI_VAE2IS val_name) s" + unfolding TLBI_VAE2IS_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VAE2IS_SysOpsWrite_f81411101129df7b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VAE2IS_SysOpsWrite_f81411101129df7b el op0 op1 CRn op2 CRm val_name) s" + unfolding VAE2IS_SysOpsWrite_f81411101129df7b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TLBI_VAE2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TLBI_VAE2 val_name) s" + unfolding TLBI_VAE2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VAE2_SysOpsWrite_78002df18993a4b5[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VAE2_SysOpsWrite_78002df18993a4b5 el op0 op1 CRn op2 CRm val_name) s" + unfolding VAE2_SysOpsWrite_78002df18993a4b5_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VAE3IS_SysOpsWrite_7dc759c51bb69ced[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VAE3IS_SysOpsWrite_7dc759c51bb69ced el op0 op1 CRn op2 CRm val_name) s" + unfolding VAE3IS_SysOpsWrite_7dc759c51bb69ced_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VAE3_SysOpsWrite_90b5c3b60d3bd152[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VAE3_SysOpsWrite_90b5c3b60d3bd152 el op0 op1 CRn op2 CRm val_name) s" + unfolding VAE3_SysOpsWrite_90b5c3b60d3bd152_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VALE1IS_SysOpsWrite_7bb7ad05a900b833[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VALE1IS_SysOpsWrite_7bb7ad05a900b833 el op0 op1 CRn op2 CRm val_name) s" + unfolding VALE1IS_SysOpsWrite_7bb7ad05a900b833_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VALE1_SysOpsWrite_c1766c627b3960ca[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VALE1_SysOpsWrite_c1766c627b3960ca el op0 op1 CRn op2 CRm val_name) s" + unfolding VALE1_SysOpsWrite_c1766c627b3960ca_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TLBI_VALE2IS[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TLBI_VALE2IS val_name) s" + unfolding TLBI_VALE2IS_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VALE2IS_SysOpsWrite_a1084cefbce599af[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VALE2IS_SysOpsWrite_a1084cefbce599af el op0 op1 CRn op2 CRm val_name) s" + unfolding VALE2IS_SysOpsWrite_a1084cefbce599af_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_TLBI_VALE2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (TLBI_VALE2 val_name) s" + unfolding TLBI_VALE2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VALE2_SysOpsWrite_dce4b2b057d036da[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VALE2_SysOpsWrite_dce4b2b057d036da el op0 op1 CRn op2 CRm val_name) s" + unfolding VALE2_SysOpsWrite_dce4b2b057d036da_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VALE3IS_SysOpsWrite_8b70cb86db2abfcd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VALE3IS_SysOpsWrite_8b70cb86db2abfcd el op0 op1 CRn op2 CRm val_name) s" + unfolding VALE3IS_SysOpsWrite_8b70cb86db2abfcd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VALE3_SysOpsWrite_df1f91b1bea42ec8[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VALE3_SysOpsWrite_df1f91b1bea42ec8 el op0 op1 CRn op2 CRm val_name) s" + unfolding VALE3_SysOpsWrite_df1f91b1bea42ec8_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VMALLE1IS_SysOpsWrite_08cfba716c4ca8db[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VMALLE1IS_SysOpsWrite_08cfba716c4ca8db el op0 op1 CRn op2 CRm val_name) s" + unfolding VMALLE1IS_SysOpsWrite_08cfba716c4ca8db_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VMALLE1_SysOpsWrite_c64f2572b311d9b9[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VMALLE1_SysOpsWrite_c64f2572b311d9b9 el op0 op1 CRn op2 CRm val_name) s" + unfolding VMALLE1_SysOpsWrite_c64f2572b311d9b9_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VMALLS12E1IS_SysOpsWrite_92a1ba1461a19d4c[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VMALLS12E1IS_SysOpsWrite_92a1ba1461a19d4c el op0 op1 CRn op2 CRm val_name) s" + unfolding VMALLS12E1IS_SysOpsWrite_92a1ba1461a19d4c_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VMALLS12E1_SysOpsWrite_8f5c303094061f20[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VMALLS12E1_SysOpsWrite_8f5c303094061f20 el op0 op1 CRn op2 CRm val_name) s" + unfolding VMALLS12E1_SysOpsWrite_8f5c303094061f20_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_ZVA[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_ZVA val_name) s" + unfolding DC_ZVA_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DC_ZVA0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_ZVA0 val_name__arg) s" + unfolding DC_ZVA0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ZVA_SysOpsWrite_b40574bff0ba4354[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ZVA_SysOpsWrite_b40574bff0ba4354 el op0 op1 CRn op2 CRm val_name) s" + unfolding ZVA_SysOpsWrite_b40574bff0ba4354_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_AutoGen_SysOpsWrite[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_AutoGen_SysOpsWrite el op0 op1 CRn op2 CRm val_name) s" + unfolding AArch64_AutoGen_SysOpsWrite_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_SysInstr[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_SysInstr op0 op1 crn crm op2 val_name) s" + unfolding AArch64_SysInstr_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_SysInstrWithResult[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_SysInstrWithResult op0 op1 crn crm op2) s" + unfolding AArch64_SysInstrWithResult_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_FPTrappedException[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_FPTrappedException is_ase element accumulated_exceptions) s" + unfolding AArch64_FPTrappedException_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPProcessException[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FPProcessException exception fpcr) s" + unfolding FPProcessException_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPRoundBase[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FPRoundBase arg0 arg1 arg2 arg3 arg4 :: 'N::len word M) s" + unfolding FPRoundBase_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPRound[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FPRound N op fpcr__arg rounding :: 'N::len word M) s" + unfolding FPRound_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPRound__1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FPRound__1 N op fpcr :: 'N::len word M) s" + unfolding FPRound__1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FixedToFP[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op) \ {16, 32, 64}" + shows "traces_enabled (FixedToFP N op fbits is_unsigned fpcr rounding :: 'N::len word M) s" + unfolding FixedToFP_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPProcessNaN[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op) \ {16, 32, 64}" + shows "traces_enabled (FPProcessNaN fptype op fpcr :: 'N::len word M) s" + unfolding FPProcessNaN_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPProcessNaNs[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1) \ {16, 32, 64}" and "int (size op2) = int (size op1)" + shows "traces_enabled (FPProcessNaNs type1 type2 op1 op2 fpcr) s" + unfolding FPProcessNaNs_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPUnpackBase[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size fpval) \ {16, 32, 64}" + shows "traces_enabled (FPUnpackBase fpval fpcr) s" + unfolding FPUnpackBase_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPUnpack[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size fpval) \ {16, 32, 64}" + shows "traces_enabled (FPUnpack fpval fpcr__arg) s" + unfolding FPUnpack_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPAdd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1) \ {16, 32, 64}" and "int (size op2) = int (size op1)" + shows "traces_enabled (FPAdd op1 op2 fpcr :: 'N::len word M) s" + unfolding FPAdd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPCompare[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1) \ {16, 32, 64}" and "int (size op2) = int (size op1)" + shows "traces_enabled (FPCompare op1 op2 signal_nans fpcr) s" + unfolding FPCompare_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPCompareEQ[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1) \ {16, 32, 64}" and "int (size op2) = int (size op1)" + shows "traces_enabled (FPCompareEQ op1 op2 fpcr) s" + unfolding FPCompareEQ_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPCompareGE[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1) \ {16, 32, 64}" and "int (size op2) = int (size op1)" + shows "traces_enabled (FPCompareGE op1 op2 fpcr) s" + unfolding FPCompareGE_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPCompareGT[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1) \ {16, 32, 64}" and "int (size op2) = int (size op1)" + shows "traces_enabled (FPCompareGT op1 op2 fpcr) s" + unfolding FPCompareGT_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPRoundCV[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FPRoundCV N op fpcr__arg rounding :: 'N::len word M) s" + unfolding FPRoundCV_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPUnpackCV[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size fpval) \ {16, 32, 64}" + shows "traces_enabled (FPUnpackCV fpval fpcr__arg) s" + unfolding FPUnpackCV_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPConvert[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op) \ {16, 32, 64}" + shows "traces_enabled (FPConvert l__604 op fpcr rounding :: 'M::len word M) s" + unfolding FPConvert_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPConvert__1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op) \ {16, 32, 64}" + shows "traces_enabled (FPConvert__1 M op fpcr :: 'M::len word M) s" + unfolding FPConvert__1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPDiv[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1) \ {16, 32, 64}" and "int (size op2) = int (size op1)" + shows "traces_enabled (FPDiv op1 op2 fpcr :: 'N::len word M) s" + unfolding FPDiv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPMax[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1) \ {16, 32, 64}" and "int (size op2) = int (size op1)" + shows "traces_enabled (FPMax op1 op2 fpcr :: 'N::len word M) s" + unfolding FPMax_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPMaxNum[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1__arg) \ {16, 32, 64}" and "int (size op2__arg) = int (size op1__arg)" + shows "traces_enabled (FPMaxNum op1__arg op2__arg fpcr :: 'N::len word M) s" + unfolding FPMaxNum_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPMin[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1) \ {16, 32, 64}" and "int (size op2) = int (size op1)" + shows "traces_enabled (FPMin op1 op2 fpcr :: 'N::len word M) s" + unfolding FPMin_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPMinNum[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1__arg) \ {16, 32, 64}" and "int (size op2__arg) = int (size op1__arg)" + shows "traces_enabled (FPMinNum op1__arg op2__arg fpcr :: 'N::len word M) s" + unfolding FPMinNum_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPMul[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1) \ {16, 32, 64}" and "int (size op2) = int (size op1)" + shows "traces_enabled (FPMul op1 op2 fpcr :: 'N::len word M) s" + unfolding FPMul_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPProcessNaNs3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1) \ {16, 32, 64}" and "int (size op3) = int (size op1)" and "int (size op2) = int (size op1)" + shows "traces_enabled (FPProcessNaNs3 type1 type2 type3 op1 op2 op3 fpcr) s" + unfolding FPProcessNaNs3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPMulAdd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size addend) \ {16, 32, 64}" and "int (size op2) = int (size addend)" and "int (size op1) = int (size addend)" + shows "traces_enabled (FPMulAdd addend op1 op2 fpcr :: 'N::len word M) s" + unfolding FPMulAdd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPMulX[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1) \ {16, 32, 64}" and "int (size op2) = int (size op1)" + shows "traces_enabled (FPMulX op1 op2 fpcr :: 'N::len word M) s" + unfolding FPMulX_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPRecipEstimate[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size operand) \ {16, 32, 64}" + shows "traces_enabled (FPRecipEstimate operand fpcr :: 'N::len word M) s" + unfolding FPRecipEstimate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPRecpX[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op) \ {16, 32, 64}" + shows "traces_enabled (FPRecpX l__583 op fpcr :: 'N::len word M) s" + unfolding FPRecpX_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPRoundInt[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op) \ {16, 32, 64}" + shows "traces_enabled (FPRoundInt op fpcr rounding exact :: 'N::len word M) s" + unfolding FPRoundInt_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPRSqrtEstimate[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size operand) \ {16, 32, 64}" + shows "traces_enabled (FPRSqrtEstimate operand fpcr :: 'N::len word M) s" + unfolding FPRSqrtEstimate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPSqrt[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op) \ {16, 32, 64}" + shows "traces_enabled (FPSqrt op fpcr :: 'N::len word M) s" + unfolding FPSqrt_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPSub[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1) \ {16, 32, 64}" and "int (size op2) = int (size op1)" + shows "traces_enabled (FPSub op1 op2 fpcr :: 'N::len word M) s" + unfolding FPSub_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPToFixed[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op) \ {16, 32, 64}" + shows "traces_enabled (FPToFixed M op fbits is_unsigned fpcr rounding :: 'M::len word M) s" + unfolding FPToFixed_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_BranchXToCapability[traces_enabledI]: + assumes "target__arg \ derivable_caps s" + shows "traces_enabled (BranchXToCapability target__arg branch_type) s" + unfolding BranchXToCapability_def bind_assoc + by (traces_enabledI assms: assms intro: enabled_branch_target_set_0th derivable_enabled_branch_target) + +lemma traces_enabled_BranchToOffset[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (BranchToOffset offset branch_type) s" + unfolding BranchToOffset_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_X_set[traces_enabledI]: + assumes "LENGTH('a) \ {32, 64}" + shows "traces_enabled (X_set width n (value_name :: 'a::len word)) s" + unfolding X_set_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_X_read[traces_enabledI]: + "traces_enabled (X_read width n :: 'width::len word M) s" + unfolding X_read_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_C_read[traces_enabledI]: + "traces_enabled (C_read n) s" + unfolding C_read_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_SP_set[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "LENGTH('a) \ {32, 64}" + shows "traces_enabled (SP_set width (value_name :: 'a::len word)) s" + unfolding SP_set_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_SP_read[traces_enabledI]: + "traces_enabled (SP_read width :: 'width::len word M) s" + unfolding SP_read_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_CSP_set[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "value_name \ derivable_caps s" + shows "traces_enabled (CSP_set value_name) s" + unfolding CSP_set_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CSP_read[traces_enabledI]: + "traces_enabled (CSP_read arg0) s" + unfolding CSP_read_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_PC_read[traces_enabledI]: + "traces_enabled (PC_read arg0) s" + unfolding PC_read_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_AArch64_SPAlignmentFault[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_SPAlignmentFault arg0) s" + unfolding AArch64_SPAlignmentFault_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CheckSPAlignment[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CheckSPAlignment arg0) s" + unfolding CheckSPAlignment_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_BaseReg_read[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (BaseReg_read n is_prefetch) s" + unfolding BaseReg_read_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_BaseReg_read__1[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (BaseReg_read__1 n) s" + unfolding BaseReg_read__1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AltBaseReg_read[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (AltBaseReg_read n is_prefetch) s" + unfolding AltBaseReg_read_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AltBaseReg_read__1[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (AltBaseReg_read__1 n) s" + unfolding AltBaseReg_read__1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_BaseReg_set[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "VA_derivable address s" + shows "traces_enabled (BaseReg_set n address) s" + unfolding BaseReg_set_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ELR_read[traces_enabledI]: + "traces_enabled (ELR_read el) s" + unfolding ELR_read_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ELR_read__1[traces_enabledI]: + "traces_enabled (ELR_read__1 arg0) s" + unfolding ELR_read__1_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_CELR_read[traces_enabledI]: + "traces_enabled (CELR_read el) s" + unfolding CELR_read_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_CELR_read__1[traces_enabledI]: + "traces_enabled (CELR_read__1 arg0) s" + unfolding CELR_read__1_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_AArch64_CheckSystemAccess[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckSystemAccess op0 op1 crn crm op2 rt read) s" + unfolding AArch64_CheckSystemAccess_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CheckAlignment[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckAlignment address alignment acctype iswrite) s" + unfolding AArch64_CheckAlignment_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_MemSingle_read[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_MemSingle_read address size__arg acctype wasaligned :: 'size_times_p8::len word M) s" + unfolding AArch64_MemSingle_read_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_MemSingle_set[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_MemSingle_set address size__arg acctype wasaligned value_name) s" + unfolding AArch64_MemSingle_set_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CheckLoadTagsPermission[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CheckLoadTagsPermission desc acctype) s" + unfolding CheckLoadTagsPermission_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CheckStoreTagsPermission[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CheckStoreTagsPermission desc acctype) s" + unfolding CheckStoreTagsPermission_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_TaggedMemSingle[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_TaggedMemSingle address size__arg acctype wasaligned) s" + unfolding AArch64_TaggedMemSingle_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_TaggedMemSingle__1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "Capability_of_tag_word (tags !! 0) (ucast data) \ derivable_caps s" and "sz = 32 \ Capability_of_tag_word (tags !! 1) (Word.slice 128 data) \ derivable_caps s" + shows "traces_enabled (AArch64_TaggedMemSingle__1 addr sz acctype wasaligned (tags :: 't::len word) (data :: 'd::len word)) s" + unfolding AArch64_TaggedMemSingle__1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CheckCapabilityAlignment[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CheckCapabilityAlignment address acctype iswrite) s" + unfolding CheckCapabilityAlignment_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CapabilityTag[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CapabilityTag address acctype) s" + unfolding AArch64_CapabilityTag_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CapabilityTag_set[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "tag = 0" + shows "traces_enabled (AArch64_CapabilityTag_set address acctype tag) s" + unfolding AArch64_CapabilityTag_set_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_Mem_read0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (Mem_read0 address size__arg acctype :: 'size_times_p8::len word M) s" + unfolding Mem_read0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_Mem_set0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (Mem_set0 address size__arg acctype value_name__arg) s" + unfolding Mem_set0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CheckCapabilityStorePairAlignment[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CheckCapabilityStorePairAlignment address acctype iswrite) s" + unfolding CheckCapabilityStorePairAlignment_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MemC_read[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MemC_read address acctype) s" + unfolding MemC_read_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MemC_set[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "value_name \ derivable_caps s" + shows "traces_enabled (MemC_set address acctype value_name) s" + unfolding MemC_set_def bind_assoc + by (traces_enabledI assms: assms simp: update_subrange_vec_dec_test_bit) + +lemma traces_enabled_MemCP__1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "value1_name \ derivable_caps s" and "value2_name \ derivable_caps s" + shows "traces_enabled (MemCP__1 address acctype value1_name value2_name) s" + unfolding MemCP__1_def bind_assoc + by (traces_enabledI assms: assms simp: update_subrange_vec_dec_test_bit update_subrange_vec_dec_word_cat_cap_pair slice_128_cat_cap_pair) + +lemma traces_enabled_AArch64_TranslateAddressForAtomicAccess[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_TranslateAddressForAtomicAccess address sizeinbits) s" + unfolding AArch64_TranslateAddressForAtomicAccess_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CheckCapability[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CheckCapability c__arg address size__arg requested_perms acctype) s" + unfolding CheckCapability_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VACheckAddress[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (VACheckAddress base addr64 size__arg requested_perms acctype) s" + unfolding VACheckAddress_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MemAtomicCompareAndSwap[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (MemAtomicCompareAndSwap base expectedvalue newvalue__arg ldacctype stacctype :: 'size::len word M) s" + unfolding MemAtomicCompareAndSwap_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MemAtomic[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (MemAtomic base op value_name ldacctype stacctype :: 'size::len word M) s" + unfolding MemAtomic_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CapSquashPostLoadCap[traces_enabledI]: + "traces_enabled (CapSquashPostLoadCap data__arg addr) s" + unfolding CapSquashPostLoadCap_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_MemAtomicCompareAndSwapC[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "expectedcap \ derivable_caps s" and "newcap \ derivable_caps s" + shows "traces_enabled (MemAtomicCompareAndSwapC vaddr address expectedcap newcap ldacctype stacctype) s" + unfolding MemAtomicCompareAndSwapC_def bind_assoc + by (traces_enabledI assms: assms simp: update_subrange_vec_dec_test_bit) + +lemma traces_enabled_MemAtomicC[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "value_name \ derivable_caps s" + shows "traces_enabled (MemAtomicC address op value_name ldacctype stacctype) s" + unfolding MemAtomicC_def bind_assoc + by (traces_enabledI assms: assms simp: update_subrange_vec_dec_test_bit) + +lemma traces_enabled_AArch64_SetExclusiveMonitors[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_SetExclusiveMonitors address size__arg) s" + unfolding AArch64_SetExclusiveMonitors_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_ExclusiveMonitorsPass[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_ExclusiveMonitorsPass address size__arg) s" + unfolding AArch64_ExclusiveMonitorsPass_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPRecipStepFused[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1__arg) \ {16, 32, 64}" and "int (size op2) = int (size op1__arg)" + shows "traces_enabled (FPRecipStepFused op1__arg op2 :: 'N::len word M) s" + unfolding FPRecipStepFused_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FPRSqrtStepFused[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size op1__arg) \ {16, 32, 64}" and "int (size op2) = int (size op1__arg)" + shows "traces_enabled (FPRSqrtStepFused op1__arg op2 :: 'N::len word M) s" + unfolding FPRSqrtStepFused_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CallSecureMonitor[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CallSecureMonitor immediate) s" + unfolding AArch64_CallSecureMonitor_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CallHypervisor[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CallHypervisor immediate) s" + unfolding AArch64_CallHypervisor_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CallSupervisor[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CallSupervisor immediate) s" + unfolding AArch64_CallSupervisor_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CheckForSMCUndefOrTrap[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckForSMCUndefOrTrap imm) s" + unfolding AArch64_CheckForSMCUndefOrTrap_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_WFxTrap[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_WFxTrap target_el is_wfe) s" + unfolding AArch64_WFxTrap_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CheckForWFxTrap[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckForWFxTrap target_el is_wfe) s" + unfolding AArch64_CheckForWFxTrap_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_AdvSIMDFPAccessTrap[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_AdvSIMDFPAccessTrap target_el) s" + unfolding AArch64_AdvSIMDFPAccessTrap_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CheckFPAdvSIMDTrap[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckFPAdvSIMDTrap arg0) s" + unfolding AArch64_CheckFPAdvSIMDTrap_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CheckFPAdvSIMDEnabled[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckFPAdvSIMDEnabled arg0) s" + unfolding AArch64_CheckFPAdvSIMDEnabled_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CheckFPAdvSIMDEnabled64[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CheckFPAdvSIMDEnabled64 arg0) s" + unfolding CheckFPAdvSIMDEnabled64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CapabilityAccessTrap[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CapabilityAccessTrap target_el) s" + unfolding CapabilityAccessTrap_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CheckCapabilitiesEnabled[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CheckCapabilitiesEnabled arg0) s" + unfolding CheckCapabilitiesEnabled_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_SoftwareBreakpoint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_SoftwareBreakpoint immediate) s" + unfolding AArch64_SoftwareBreakpoint_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_ExceptionReturnToCapability[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "new_pcc__arg \ derivable_caps s" + shows "traces_enabled (AArch64_ExceptionReturnToCapability new_pcc__arg spsr) s" + unfolding AArch64_ExceptionReturnToCapability_def bind_assoc + by (traces_enabledI assms: assms intro: derivable_enabled_branch_target) + +lemma traces_enabled_ExtendReg[traces_enabledI]: + "traces_enabled (ExtendReg N reg exttype shift :: 'N::len word M) s" + unfolding ExtendReg_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ShiftReg[traces_enabledI]: + assumes "amount \ 0" + shows "traces_enabled (ShiftReg N reg shiftype amount :: 'N::len word M) s" + unfolding ShiftReg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ReduceCombine[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int (size lo) \ {8, 16, 32, 64}" and "int (size hi) = int (size lo)" + shows "traces_enabled (ReduceCombine op lo hi :: 'esize::len word M) s" + unfolding ReduceCombine_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_Reduce16[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "esize \ {8, 16}" and "int LENGTH('esize) = esize" + shows "traces_enabled (Reduce16 op input esize :: 'esize::len word M) s" + unfolding Reduce16_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_Reduce32[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "esize \ {8, 16, 32}" and "int LENGTH('esize) = esize" + shows "traces_enabled (Reduce32 op input esize :: 'esize::len word M) s" + unfolding Reduce32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_Reduce64[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "esize \ {8, 16, 32, 64}" and "int LENGTH('esize) = esize" + shows "traces_enabled (Reduce64 op input esize :: 'esize::len word M) s" + unfolding Reduce64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_Reduce128[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "esize \ {8, 16, 32, 64}" and "int LENGTH('esize) = esize" + shows "traces_enabled (Reduce128 op input esize :: 'esize::len word M) s" + unfolding Reduce128_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_Reduce256[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "esize \ {8, 16, 32, 64}" and "int LENGTH('esize) = esize" + shows "traces_enabled (Reduce256 op input esize :: 'esize::len word M) s" + unfolding Reduce256_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_Reduce512[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "esize \ {8, 16, 32, 64}" and "int LENGTH('esize) = esize" + shows "traces_enabled (Reduce512 op input esize :: 'esize::len word M) s" + unfolding Reduce512_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_Reduce1024[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "esize \ {8, 16, 32, 64}" and "int LENGTH('esize) = esize" + shows "traces_enabled (Reduce1024 op input esize :: 'esize::len word M) s" + unfolding Reduce1024_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_Reduce2048[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "esize \ {8, 16, 32, 64}" and "int LENGTH('esize) = esize" + shows "traces_enabled (Reduce2048 op input esize :: 'esize::len word M) s" + unfolding Reduce2048_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_Reduce[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "esize \ {8, 16, 32, 64}" and "nat esize \ size input" and "LENGTH('esize) = nat esize" + shows "traces_enabled (Reduce op input esize :: 'esize::len word M) s" + unfolding Reduce_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DCPSInstruction[traces_enabledI]: + "traces_enabled (DCPSInstruction target_el) s" + unfolding DCPSInstruction_def bind_assoc + by (traces_enabledI simp: HaveCapabilitiesExt_def) + +lemma traces_enabled_DRPSInstruction[traces_enabledI]: + "traces_enabled (DRPSInstruction arg0) s" + unfolding DRPSInstruction_def bind_assoc + by (traces_enabledI simp: HaveCapabilitiesExt_def) + +lemma traces_enabled_VACheckPerm[traces_enabledI]: + "traces_enabled (VACheckPerm base requested_perms) s" + unfolding VACheckPerm_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_CAP_DC_CIVAC[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "cval \ derivable_caps s" + shows "traces_enabled (CAP_DC_CIVAC cval) s" + unfolding CAP_DC_CIVAC_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CAP_DC_CVAC[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "cval \ derivable_caps s" + shows "traces_enabled (CAP_DC_CVAC cval) s" + unfolding CAP_DC_CVAC_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CAP_DC_CVADP[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "cval \ derivable_caps s" + shows "traces_enabled (CAP_DC_CVADP cval) s" + unfolding CAP_DC_CVADP_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CAP_DC_CVAP[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "cval \ derivable_caps s" + shows "traces_enabled (CAP_DC_CVAP cval) s" + unfolding CAP_DC_CVAP_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CAP_DC_CVAU[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "cval \ derivable_caps s" + shows "traces_enabled (CAP_DC_CVAU cval) s" + unfolding CAP_DC_CVAU_def bind_assoc + by (traces_enabledI assms: assms intro: traces_enabled_bind) + +lemma traces_enabled_CAP_DC_IVAC[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "cval \ derivable_caps s" + shows "traces_enabled (CAP_DC_IVAC cval) s" + unfolding CAP_DC_IVAC_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CAP_DC_ZVA[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "cval \ derivable_caps s" + shows "traces_enabled (CAP_DC_ZVA cval) s" + unfolding CAP_DC_ZVA_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CAP_IC_IVAU[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "cval \ derivable_caps s" + shows "traces_enabled (CAP_IC_IVAU cval) s" + unfolding CAP_IC_IVAU_def bind_assoc + by (traces_enabledI assms: assms intro: traces_enabled_bind) + +lemma traces_enabled_AArch64_SysInstrWithCapability[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (AArch64_SysInstrWithCapability op0 op1 crn crm op2 val_name) s" + unfolding AArch64_SysInstrWithCapability_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_Step_PC[traces_enabledI]: + "traces_enabled (Step_PC arg0) s" + unfolding Step_PC_def bind_assoc + by (traces_enabledI elim: BranchTaken_or_PCC_accessible) + +lemma traces_enabled_execute_ADD_C_CIS_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_ADD_C_CIS_C d imm n) s" + unfolding execute_ADD_C_CIS_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ADD_C_CIS_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ADD_C_CIS_C A sh imm12 Cn Cd) s" + unfolding decode_ADD_C_CIS_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ADD_C_CRI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "shift \ {0, 1, 2, 3, 4, 5, 6, 7}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_ADD_C_CRI_C d extend_type m n shift) s" + unfolding execute_ADD_C_CRI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ADD_C_CRI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ADD_C_CRI_C Rm option_name imm3 Cn Cd) s" + unfolding decode_ADD_C_CRI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ADRDP_C_ID_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_ADRDP_C_ID_C P d imm) s" + unfolding execute_ADRDP_C_ID_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ADRDP_C_ID_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ADRDP_C_ID_C op immlo P immhi Rd) s" + unfolding decode_ADRDP_C_ID_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ADRP_C_IP_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_ADRP_C_IP_C P d imm) s" + unfolding execute_ADRP_C_IP_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ADRP_C_IP_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ADRP_C_IP_C op immlo P immhi Rd) s" + unfolding decode_ADRP_C_IP_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ADRP_C_I_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_ADRP_C_I_C P d imm) s" + unfolding execute_ADRP_C_I_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ADRP_C_I_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ADRP_C_I_C op immlo P immhi Rd) s" + unfolding decode_ADRP_C_I_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ADR_C_I_C[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_ADR_C_I_C d imm) s" + unfolding execute_ADR_C_I_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ADR_C_I_C[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ADR_C_I_C op immlo P immhi Rd) s" + unfolding decode_ADR_C_I_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDARB_R_R_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ALDARB_R_R_B acctype datasize n regsize t__arg) s" + unfolding execute_ALDARB_R_R_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDARB_R_R_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDARB_R_R_B L Rn Rt) s" + unfolding decode_ALDARB_R_R_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDAR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "AltBaseRegAuth n \ load_auths" + shows "traces_enabled (execute_ALDAR_C_R_C acctype n t__arg) s" + unfolding execute_ALDAR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDAR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "AltBaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_ALDAR_C_R_C L Rn Ct) s" + unfolding decode_ALDAR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDAR_R_R_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ALDAR_R_R_32 acctype datasize n regsize t__arg) s" + unfolding execute_ALDAR_R_R_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDAR_R_R_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDAR_R_R_32 L Rn Rt) s" + unfolding decode_ALDAR_R_R_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRB_R_RRB_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift = 0" and "l__550 = 0" and "regsize = 32" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDRB_R_RRB_B extend_type m n regsize l__550 shift t__arg) s" + unfolding execute_ALDRB_R_RRB_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRB_R_RRB_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRB_R_RRB_B L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDRB_R_RRB_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRB_R_RUI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ALDRB_R_RUI_B datasize n offset regsize t__arg) s" + unfolding execute_ALDRB_R_RUI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRB_R_RUI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRB_R_RUI_B L imm9 op Rn Rt) s" + unfolding decode_ALDRB_R_RUI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRH_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 1}" and "l__549 = 1" and "regsize = 32" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDRH_R_RRB_32 extend_type m n regsize l__549 shift t__arg) s" + unfolding execute_ALDRH_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRH_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRH_R_RRB_32 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDRH_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRSB_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift = 0" and "l__545 = 0" and "regsize = 32" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDRSB_R_RRB_32 extend_type m n regsize l__545 shift t__arg) s" + unfolding execute_ALDRSB_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRSB_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRSB_R_RRB_32 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDRSB_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRSB_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift = 0" and "l__546 = 0" and "regsize = 64" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDRSB_R_RRB_64 extend_type m n regsize l__546 shift t__arg) s" + unfolding execute_ALDRSB_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRSB_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRSB_R_RRB_64 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDRSB_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRSH_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 1}" and "l__543 = 1" and "regsize = 32" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDRSH_R_RRB_32 extend_type m n regsize l__543 shift t__arg) s" + unfolding execute_ALDRSH_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRSH_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRSH_R_RRB_32 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDRSH_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRSH_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 1}" and "l__544 = 1" and "regsize = 64" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDRSH_R_RRB_64 extend_type m n regsize l__544 shift t__arg) s" + unfolding execute_ALDRSH_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRSH_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRSH_R_RRB_64 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDRSH_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "\invokes_indirect_caps" and "AltBaseRegAuth n \ load_auths" + shows "traces_enabled (execute_ALDR_C_RRB_C extend_type m n shift t__arg) s" + unfolding execute_ALDR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "AltBaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_ALDR_C_RRB_C Rm sign sz S L Rn Ct) s" + unfolding decode_ALDR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_C_RUI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "AltBaseRegAuth n \ load_auths" + shows "traces_enabled (execute_ALDR_C_RUI_C n offset t__arg) s" + unfolding execute_ALDR_C_RUI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_C_RUI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "AltBaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_ALDR_C_RUI_C L imm9 op Rn Ct) s" + unfolding decode_ALDR_C_RUI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 2}" and "l__548 = 2" and "regsize = 32" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDR_R_RRB_32 extend_type m n regsize l__548 shift t__arg) s" + unfolding execute_ALDR_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDR_R_RRB_32 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDR_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 3}" and "l__547 = 3" and "regsize = 64" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDR_R_RRB_64 extend_type m n regsize l__547 shift t__arg) s" + unfolding execute_ALDR_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDR_R_RRB_64 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDR_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_R_RUI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ALDR_R_RUI_32 datasize n offset regsize t__arg) s" + unfolding execute_ALDR_R_RUI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_R_RUI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDR_R_RUI_32 L imm9 op Rn Rt) s" + unfolding decode_ALDR_R_RUI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_R_RUI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 64" and "0 \ n" and "n \ 31" and "datasize = 64" + shows "traces_enabled (execute_ALDR_R_RUI_64 datasize n offset regsize t__arg) s" + unfolding execute_ALDR_R_RUI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_R_RUI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDR_R_RUI_64 L imm9 op Rn Rt) s" + unfolding decode_ALDR_R_RUI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_V_RRB_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 3}" and "l__542 = 3" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDR_V_RRB_D extend_type m n l__542 shift t__arg) s" + unfolding execute_ALDR_V_RRB_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_V_RRB_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDR_V_RRB_D L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDR_V_RRB_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_V_RRB_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 2}" and "l__541 = 2" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDR_V_RRB_S extend_type m n l__541 shift t__arg) s" + unfolding execute_ALDR_V_RRB_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_V_RRB_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDR_V_RRB_S L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDR_V_RRB_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURB_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ALDURB_R_RI_32 datasize n offset regsize t__arg) s" + unfolding execute_ALDURB_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURB_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURB_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURB_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURH_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 16" + shows "traces_enabled (execute_ALDURH_R_RI_32 datasize n offset regsize t__arg) s" + unfolding execute_ALDURH_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURH_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURH_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURH_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURSB_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ALDURSB_R_RI_32 datasize n offset regsize t__arg) s" + unfolding execute_ALDURSB_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURSB_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURSB_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURSB_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURSB_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 64" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ALDURSB_R_RI_64 datasize n offset regsize t__arg) s" + unfolding execute_ALDURSB_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURSB_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURSB_R_RI_64 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURSB_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURSH_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 16" + shows "traces_enabled (execute_ALDURSH_R_RI_32 datasize n offset regsize t__arg) s" + unfolding execute_ALDURSH_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURSH_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURSH_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURSH_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURSH_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 64" and "0 \ n" and "n \ 31" and "datasize = 16" + shows "traces_enabled (execute_ALDURSH_R_RI_64 datasize n offset regsize t__arg) s" + unfolding execute_ALDURSH_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURSH_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURSH_R_RI_64 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURSH_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURSW_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 64" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ALDURSW_R_RI_64 datasize n offset regsize t__arg) s" + unfolding execute_ALDURSW_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURSW_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURSW_R_RI_64 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURSW_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "AltBaseRegAuth n \ load_auths" + shows "traces_enabled (execute_ALDUR_C_RI_C n offset t__arg) s" + unfolding execute_ALDUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "AltBaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_ALDUR_C_RI_C op1 V imm9 op2 Rn Ct) s" + unfolding decode_ALDUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ALDUR_R_RI_32 datasize n offset regsize t__arg) s" + unfolding execute_ALDUR_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 64" and "0 \ n" and "n \ 31" and "datasize = 64" + shows "traces_enabled (execute_ALDUR_R_RI_64 datasize n offset regsize t__arg) s" + unfolding execute_ALDUR_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_R_RI_64 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_V_RI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ALDUR_V_RI_B datasize n offset t__arg) s" + unfolding execute_ALDUR_V_RI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_V_RI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_V_RI_B op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_V_RI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_V_RI_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 64" + shows "traces_enabled (execute_ALDUR_V_RI_D datasize n offset t__arg) s" + unfolding execute_ALDUR_V_RI_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_V_RI_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_V_RI_D op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_V_RI_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_V_RI_H[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 16" + shows "traces_enabled (execute_ALDUR_V_RI_H datasize n offset t__arg) s" + unfolding execute_ALDUR_V_RI_H_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_V_RI_H[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_V_RI_H op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_V_RI_H_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_V_RI_Q[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 128" + shows "traces_enabled (execute_ALDUR_V_RI_Q datasize n offset t__arg) s" + unfolding execute_ALDUR_V_RI_Q_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_V_RI_Q[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_V_RI_Q op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_V_RI_Q_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_V_RI_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ALDUR_V_RI_S datasize n offset t__arg) s" + unfolding execute_ALDUR_V_RI_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_V_RI_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_V_RI_S op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_V_RI_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALIGND_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" and "0 \ align" and "align \ 63" + shows "traces_enabled (execute_ALIGND_C_CI_C align d n) s" + unfolding execute_ALIGND_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALIGND_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALIGND_C_CI_C imm6 U Cn Cd) s" + unfolding decode_ALIGND_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALIGNU_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" and "0 \ align" and "align \ 63" + shows "traces_enabled (execute_ALIGNU_C_CI_C align d n) s" + unfolding execute_ALIGNU_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALIGNU_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALIGNU_C_CI_C imm6 U Cn Cd) s" + unfolding decode_ALIGNU_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTLRB_R_R_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ASTLRB_R_R_B acctype datasize n t__arg) s" + unfolding execute_ASTLRB_R_R_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTLRB_R_R_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTLRB_R_R_B L Rn Rt) s" + unfolding decode_ASTLRB_R_R_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTLR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_ASTLR_C_R_C acctype n t__arg) s" + unfolding execute_ASTLR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTLR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTLR_C_R_C L Rn Ct) s" + unfolding decode_ASTLR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTLR_R_R_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ASTLR_R_R_32 acctype datasize n t__arg) s" + unfolding execute_ASTLR_R_R_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTLR_R_R_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTLR_R_R_32 L Rn Rt) s" + unfolding decode_ASTLR_R_R_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTRB_R_RRB_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift = 0" and "l__556 = 0" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTRB_R_RRB_B extend_type m n l__556 shift t__arg) s" + unfolding execute_ASTRB_R_RRB_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTRB_R_RRB_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTRB_R_RRB_B L Rm sign sz S opc Rn Rt) s" + unfolding decode_ASTRB_R_RRB_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTRB_R_RUI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ASTRB_R_RUI_B datasize n offset t__arg) s" + unfolding execute_ASTRB_R_RUI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTRB_R_RUI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTRB_R_RUI_B L imm9 op Rn Rt) s" + unfolding decode_ASTRB_R_RUI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTRH_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 1}" and "l__555 = 1" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTRH_R_RRB_32 extend_type m n l__555 shift t__arg) s" + unfolding execute_ASTRH_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTRH_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTRH_R_RRB_32 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ASTRH_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTR_C_RRB_C extend_type m n shift t__arg) s" + unfolding execute_ASTR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_C_RRB_C Rm sign sz S L Rn Ct) s" + unfolding decode_ASTR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_C_RUI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_ASTR_C_RUI_C n offset t__arg) s" + unfolding execute_ASTR_C_RUI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_C_RUI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_C_RUI_C L imm9 op Rn Ct) s" + unfolding decode_ASTR_C_RUI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 2}" and "l__554 = 2" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTR_R_RRB_32 extend_type m n l__554 shift t__arg) s" + unfolding execute_ASTR_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_R_RRB_32 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ASTR_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 3}" and "l__553 = 3" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTR_R_RRB_64 extend_type m n l__553 shift t__arg) s" + unfolding execute_ASTR_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_R_RRB_64 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ASTR_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_R_RUI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ASTR_R_RUI_32 datasize n offset t__arg) s" + unfolding execute_ASTR_R_RUI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_R_RUI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_R_RUI_32 L imm9 op Rn Rt) s" + unfolding decode_ASTR_R_RUI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_R_RUI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 64" + shows "traces_enabled (execute_ASTR_R_RUI_64 datasize n offset t__arg) s" + unfolding execute_ASTR_R_RUI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_R_RUI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_R_RUI_64 L imm9 op Rn Rt) s" + unfolding decode_ASTR_R_RUI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_V_RRB_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 3}" and "l__552 = 3" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTR_V_RRB_D extend_type m n l__552 shift t__arg) s" + unfolding execute_ASTR_V_RRB_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_V_RRB_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_V_RRB_D L Rm sign sz S opc Rn Rt) s" + unfolding decode_ASTR_V_RRB_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_V_RRB_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 2}" and "l__551 = 2" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTR_V_RRB_S extend_type m n l__551 shift t__arg) s" + unfolding execute_ASTR_V_RRB_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_V_RRB_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_V_RRB_S L Rm sign sz S opc Rn Rt) s" + unfolding decode_ASTR_V_RRB_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTURB_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ASTURB_R_RI_32 datasize n offset t__arg) s" + unfolding execute_ASTURB_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTURB_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTURB_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTURB_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTURH_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 16" + shows "traces_enabled (execute_ASTURH_R_RI_32 datasize n offset t__arg) s" + unfolding execute_ASTURH_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTURH_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTURH_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTURH_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_ASTUR_C_RI_C n offset t__arg) s" + unfolding execute_ASTUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_C_RI_C op1 V imm9 op2 Rn Ct) s" + unfolding decode_ASTUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ASTUR_R_RI_32 datasize n offset t__arg) s" + unfolding execute_ASTUR_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 64" + shows "traces_enabled (execute_ASTUR_R_RI_64 datasize n offset t__arg) s" + unfolding execute_ASTUR_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_R_RI_64 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_V_RI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ASTUR_V_RI_B datasize n offset t__arg) s" + unfolding execute_ASTUR_V_RI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_V_RI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_V_RI_B op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_V_RI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_V_RI_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 64" + shows "traces_enabled (execute_ASTUR_V_RI_D datasize n offset t__arg) s" + unfolding execute_ASTUR_V_RI_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_V_RI_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_V_RI_D op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_V_RI_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_V_RI_H[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 16" + shows "traces_enabled (execute_ASTUR_V_RI_H datasize n offset t__arg) s" + unfolding execute_ASTUR_V_RI_H_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_V_RI_H[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_V_RI_H op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_V_RI_H_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_V_RI_Q[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 128" + shows "traces_enabled (execute_ASTUR_V_RI_Q datasize n offset t__arg) s" + unfolding execute_ASTUR_V_RI_Q_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_V_RI_Q[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_V_RI_Q op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_V_RI_Q_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_V_RI_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ASTUR_V_RI_S datasize n offset t__arg) s" + unfolding execute_ASTUR_V_RI_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_V_RI_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_V_RI_S op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_V_RI_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BICFLGS_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_BICFLGS_C_CI_C d mask__arg n) s" + unfolding execute_BICFLGS_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_BICFLGS_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_BICFLGS_C_CI_C imm8 Cn Cd) s" + unfolding decode_BICFLGS_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BICFLGS_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_BICFLGS_C_CR_C d m n) s" + unfolding execute_BICFLGS_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_BICFLGS_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_BICFLGS_C_CR_C Rm opc Cn Cd) s" + unfolding decode_BICFLGS_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BLRR_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "n \ invoked_regs" + shows "traces_enabled (execute_BLRR_C_C branch_type n) s" + unfolding execute_BLRR_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_BLRR_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cn \ invoked_regs" + shows "traces_enabled (decode_BLRR_C_C opc Cn) s" + unfolding decode_BLRR_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BLRS_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "n \ invoked_regs" + shows "traces_enabled (execute_BLRS_C_C branch_type n) s" + unfolding execute_BLRS_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_BLRS_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cn \ invoked_regs" + shows "traces_enabled (decode_BLRS_C_C opc Cn) s" + unfolding decode_BLRS_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BLRS_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "m \ invoked_regs" and "n \ invoked_regs" + shows "traces_enabled (execute_BLRS_C_C_C branch_type m n) s" + unfolding execute_BLRS_C_C_C_def bind_assoc + by (traces_enabledI assms: assms intro: enabled_branch_target_CapUnseal_if_clear elim: branch_sealed_pair_enabled_pcc traces_enabled_C_set_29_branch_sealed_pair) + +lemma traces_enabled_decode_BLRS_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cm \ invoked_regs" and "uint Cn \ invoked_regs" + shows "traces_enabled (decode_BLRS_C_C_C Cm opc Cn) s" + unfolding decode_BLRS_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BLR_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "n = 29 \ 29 \ invoked_indirect_regs" and "RegAuth n \ load_auths" and "is_indirect_branch" + shows "traces_enabled (execute_BLR_CI_C branch_type n offset) s" + unfolding execute_BLR_CI_C_def bind_assoc + by (traces_enabledI assms: assms intro: traces_enabled_C_set_if_sentry elim: enabled_branch_target_CapUnseal_mem_cap enabled_branch_target_CapSquashPostLoadCap Run_CSP_or_C_read_invoked_indirect_caps) + +lemma traces_enabled_decode_BLR_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cn = 29 \ 29 \ invoked_indirect_regs" and "RegAuth (uint Cn) \ load_auths" and "is_indirect_branch" + shows "traces_enabled (decode_BLR_CI_C imm7 Cn) s" + unfolding decode_BLR_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BLR_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "n \ invoked_regs" + shows "traces_enabled (execute_BLR_C_C branch_type n) s" + unfolding execute_BLR_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_BLR_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cn \ invoked_regs" + shows "traces_enabled (decode_BLR_C_C opc Cn) s" + unfolding decode_BLR_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BRR_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "n \ invoked_regs" + shows "traces_enabled (execute_BRR_C_C branch_type n) s" + unfolding execute_BRR_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_BRR_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cn \ invoked_regs" + shows "traces_enabled (decode_BRR_C_C opc Cn) s" + unfolding decode_BRR_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BRS_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "n \ invoked_regs" + shows "traces_enabled (execute_BRS_C_C branch_type n) s" + unfolding execute_BRS_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_BRS_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cn \ invoked_regs" + shows "traces_enabled (decode_BRS_C_C opc Cn) s" + unfolding decode_BRS_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BRS_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "m \ invoked_regs" and "n \ invoked_regs" + shows "traces_enabled (execute_BRS_C_C_C branch_type m n) s" + unfolding execute_BRS_C_C_C_def bind_assoc + by (traces_enabledI assms: assms intro: enabled_branch_target_CapUnseal_if_clear elim: branch_sealed_pair_enabled_pcc traces_enabled_C_set_29_branch_sealed_pair) + +lemma traces_enabled_decode_BRS_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cm \ invoked_regs" and "uint Cn \ invoked_regs" + shows "traces_enabled (decode_BRS_C_C_C Cm opc Cn) s" + unfolding decode_BRS_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BR_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "n = 29 \ 29 \ invoked_indirect_regs" and "RegAuth n \ load_auths" and "is_indirect_branch" + shows "traces_enabled (execute_BR_CI_C branch_type n offset) s" + unfolding execute_BR_CI_C_def bind_assoc + by (traces_enabledI assms: assms intro: traces_enabled_C_set_if_sentry elim: enabled_branch_target_CapUnseal_mem_cap enabled_branch_target_CapSquashPostLoadCap Run_CSP_or_C_read_invoked_indirect_caps) + +lemma traces_enabled_decode_BR_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cn = 29 \ 29 \ invoked_indirect_regs" and "RegAuth (uint Cn) \ load_auths" and "is_indirect_branch" + shows "traces_enabled (decode_BR_CI_C imm7 Cn) s" + unfolding decode_BR_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BR_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "n \ invoked_regs" + shows "traces_enabled (execute_BR_C_C branch_type n) s" + unfolding execute_BR_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_BR_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cn \ invoked_regs" + shows "traces_enabled (decode_BR_C_C opc Cn) s" + unfolding decode_BR_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BUILD_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_BUILD_C_C_C d m n) s" + unfolding execute_BUILD_C_C_C_def bind_assoc + by (traces_enabledI assms: assms elim: CapIsSubSetOf_WithTagSet_derivable Run_or_boolM_E Run_bindE simp: CapIsBaseAboveLimit_get_base_leq_get_limit) + +lemma traces_enabled_decode_BUILD_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_BUILD_C_C_C Cm opc Cn Cd) s" + unfolding decode_BUILD_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BX___C[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (execute_BX___C branch_type) s" + unfolding execute_BX___C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_BX___C[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_BX___C opc) s" + unfolding decode_BX___C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CASAL_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_CASAL_C_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_CASAL_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CASAL_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_CASAL_C_R_C L Cs R Rn Ct) s" + unfolding decode_CASAL_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CASA_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_CASA_C_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_CASA_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CASA_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_CASA_C_R_C L Cs R Rn Ct) s" + unfolding decode_CASA_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CASL_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_CASL_C_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_CASL_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CASL_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_CASL_C_R_C L Cs R Rn Ct) s" + unfolding decode_CASL_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CAS_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_CAS_C_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_CAS_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CAS_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_CAS_C_R_C L Cs R Rn Ct) s" + unfolding decode_CAS_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CFHI_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CFHI_R_C_C d n) s" + unfolding execute_CFHI_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CFHI_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CFHI_R_C_C opc Cn Rd) s" + unfolding decode_CFHI_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CHKEQ___CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_CHKEQ___CC_C m n) s" + unfolding execute_CHKEQ___CC_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CHKEQ___CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CHKEQ___CC_C Cm opc Cn) s" + unfolding decode_CHKEQ___CC_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CHKSLD_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_CHKSLD_C_C n) s" + unfolding execute_CHKSLD_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CHKSLD_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CHKSLD_C_C opc Cn) s" + unfolding decode_CHKSLD_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CHKSSU_C_CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CHKSSU_C_CC_C d m n) s" + unfolding execute_CHKSSU_C_CC_C_def bind_assoc + by (traces_enabledI assms: assms elim: CapIsSubSetOf_CapUnseal_derivable Run_and_boolM_E) + +lemma traces_enabled_decode_CHKSSU_C_CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CHKSSU_C_CC_C Cm opc Cn Cd) s" + unfolding decode_CHKSSU_C_CC_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CHKSS___CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_CHKSS___CC_C m n) s" + unfolding execute_CHKSS___CC_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CHKSS___CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CHKSS___CC_C Cm opc Cn) s" + unfolding decode_CHKSS___CC_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CHKTGD_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_CHKTGD_C_C n) s" + unfolding execute_CHKTGD_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CHKTGD_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CHKTGD_C_C opc Cn) s" + unfolding decode_CHKTGD_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CLRPERM_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CLRPERM_C_CI_C d imm n) s" + unfolding execute_CLRPERM_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CLRPERM_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CLRPERM_C_CI_C perm__arg Cn Cd) s" + unfolding decode_CLRPERM_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CLRPERM_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CLRPERM_C_CR_C d m n) s" + unfolding execute_CLRPERM_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CLRPERM_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CLRPERM_C_CR_C Rm Cn Cd) s" + unfolding decode_CLRPERM_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CLRTAG_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CLRTAG_C_C_C d n) s" + unfolding execute_CLRTAG_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CLRTAG_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CLRTAG_C_C_C opc Cn Cd) s" + unfolding decode_CLRTAG_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CPYTYPE_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CPYTYPE_C_C_C d m n) s" + unfolding execute_CPYTYPE_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CPYTYPE_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CPYTYPE_C_C_C Cm opc Cn Cd) s" + unfolding decode_CPYTYPE_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CPYVALUE_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CPYVALUE_C_C_C d m n) s" + unfolding execute_CPYVALUE_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CPYVALUE_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CPYVALUE_C_C_C Cm opc Cn Cd) s" + unfolding decode_CPYVALUE_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CPY_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CPY_C_C_C d n) s" + unfolding execute_CPY_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CPY_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CPY_C_C_C opc Cn Cd) s" + unfolding decode_CPY_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CSEAL_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CSEAL_C_C_C d m n) s" + unfolding execute_CSEAL_C_C_C_def bind_assoc + by (traces_enabledI assms: assms elim: Run_and_boolM_E CapIsInBounds_cursor_in_mem_region) + +lemma traces_enabled_decode_CSEAL_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CSEAL_C_C_C Cm opc Cn Cd) s" + unfolding decode_CSEAL_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CSEL_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CSEL_C_CI_C cond d m n) s" + unfolding execute_CSEL_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CSEL_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CSEL_C_CI_C Cm cond Cn Cd) s" + unfolding decode_CSEL_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CTHI_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CTHI_C_CR_C d m n) s" + unfolding execute_CTHI_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CTHI_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CTHI_C_CR_C Rm opc Cn Cd) s" + unfolding decode_CTHI_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CVTDZ_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CVTDZ_C_R_C d n) s" + unfolding execute_CVTDZ_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CVTDZ_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CVTDZ_C_R_C opc Rn Cd) s" + unfolding decode_CVTDZ_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CVTD_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CVTD_C_R_C d n) s" + unfolding execute_CVTD_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CVTD_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CVTD_C_R_C opc Rn Cd) s" + unfolding decode_CVTD_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CVTD_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CVTD_R_C_C d n) s" + unfolding execute_CVTD_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CVTD_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CVTD_R_C_C opc Cn Rd) s" + unfolding decode_CVTD_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CVTPZ_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CVTPZ_C_R_C d n) s" + unfolding execute_CVTPZ_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CVTPZ_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CVTPZ_C_R_C opc Rn Cd) s" + unfolding decode_CVTPZ_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CVTP_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CVTP_C_R_C d n) s" + unfolding execute_CVTP_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CVTP_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CVTP_C_R_C opc Rn Cd) s" + unfolding decode_CVTP_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CVTP_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CVTP_R_C_C d n) s" + unfolding execute_CVTP_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CVTP_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CVTP_R_C_C opc Cn Rd) s" + unfolding decode_CVTP_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CVTZ_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CVTZ_C_CR_C d m n) s" + unfolding execute_CVTZ_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CVTZ_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CVTZ_C_CR_C Rm Cn Cd) s" + unfolding decode_CVTZ_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CVT_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CVT_C_CR_C d m n) s" + unfolding execute_CVT_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CVT_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CVT_C_CR_C Rm Cn Cd) s" + unfolding decode_CVT_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CVT_R_CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_CVT_R_CC_C d m n) s" + unfolding execute_CVT_R_CC_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CVT_R_CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_CVT_R_CC_C Cm Cn Rd) s" + unfolding decode_CVT_R_CC_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_EORFLGS_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_EORFLGS_C_CI_C d mask__arg n) s" + unfolding execute_EORFLGS_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_EORFLGS_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_EORFLGS_C_CI_C imm8 Cn Cd) s" + unfolding decode_EORFLGS_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_EORFLGS_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_EORFLGS_C_CR_C d m n) s" + unfolding execute_EORFLGS_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_EORFLGS_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_EORFLGS_C_CR_C Rm opc Cn Cd) s" + unfolding decode_EORFLGS_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_GCBASE_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_GCBASE_R_C_C d n) s" + unfolding execute_GCBASE_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_GCBASE_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_GCBASE_R_C_C opc Cn Rd) s" + unfolding decode_GCBASE_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_GCFLGS_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_GCFLGS_R_C_C d n) s" + unfolding execute_GCFLGS_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_GCFLGS_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_GCFLGS_R_C_C opc Cn Rd) s" + unfolding decode_GCFLGS_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_GCLEN_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_GCLEN_R_C_C d n) s" + unfolding execute_GCLEN_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_GCLEN_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_GCLEN_R_C_C opc Cn Rd) s" + unfolding decode_GCLEN_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_GCLIM_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_GCLIM_R_C_C d n) s" + unfolding execute_GCLIM_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_GCLIM_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_GCLIM_R_C_C opc Cn Rd) s" + unfolding decode_GCLIM_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_GCOFF_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_GCOFF_R_C_C d n) s" + unfolding execute_GCOFF_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_GCOFF_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_GCOFF_R_C_C opc Cn Rd) s" + unfolding decode_GCOFF_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_GCPERM_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_GCPERM_R_C_C d n) s" + unfolding execute_GCPERM_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_GCPERM_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_GCPERM_R_C_C opc Cn Rd) s" + unfolding decode_GCPERM_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_GCSEAL_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_GCSEAL_R_C_C d n) s" + unfolding execute_GCSEAL_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_GCSEAL_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_GCSEAL_R_C_C opc Cn Rd) s" + unfolding decode_GCSEAL_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_GCTAG_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_GCTAG_R_C_C d n) s" + unfolding execute_GCTAG_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_GCTAG_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_GCTAG_R_C_C opc Cn Rd) s" + unfolding decode_GCTAG_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_GCTYPE_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_GCTYPE_R_C_C d n) s" + unfolding execute_GCTYPE_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_GCTYPE_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_GCTYPE_R_C_C opc Cn Rd) s" + unfolding decode_GCTYPE_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_GCVALUE_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_GCVALUE_R_C_C d n) s" + unfolding execute_GCVALUE_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_GCVALUE_R_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_GCVALUE_R_C_C opc Cn Rd) s" + unfolding decode_GCVALUE_R_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDAPR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDAPR_C_R_C acctype n t__arg) s" + unfolding execute_LDAPR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDAPR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDAPR_C_R_C Rn Ct) s" + unfolding decode_LDAPR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDAR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDAR_C_R_C acctype n t__arg) s" + unfolding execute_LDAR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDAR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDAR_C_R_C L Rn Ct) s" + unfolding decode_LDAR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDAXP_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDAXP_C_R_C acctype n t__arg t2) s" + unfolding execute_LDAXP_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDAXP_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDAXP_C_R_C L Ct2 Rn Ct) s" + unfolding decode_LDAXP_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDAXR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDAXR_C_R_C acctype n t__arg) s" + unfolding execute_LDAXR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDAXR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDAXR_C_R_C L Rn Ct) s" + unfolding decode_LDAXR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDCT_R_R[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDCT_R_R n t__arg) s" + unfolding execute_LDCT_R_R_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDCT_R_R[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDCT_R_R opc Rn Rt) s" + unfolding decode_LDCT_R_R_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDNP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDNP_C_RIB_C acctype n offset t__arg t2) s" + unfolding execute_LDNP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDNP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDNP_C_RIB_C L imm7 Ct2 Rn Ct) s" + unfolding decode_LDNP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDPBLR_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "t__arg = 29 \ n \ invoked_indirect_regs" and "RegAuth n \ load_auths" and "t__arg \ 29 \ \invokes_indirect_caps" and "is_indirect_branch" + shows "traces_enabled (execute_LDPBLR_C_C_C branch_type n t__arg) s" + unfolding execute_LDPBLR_C_C_C_def bind_assoc + by (traces_enabledI assms: assms elim: traces_enabled_C_set_mem_cap[where n = t__arg] traces_enabled_C_set_mem_cap[where n = 29] enabled_branch_target_CapUnseal_mem_cap enabled_branch_target_CapSquashPostLoadCap) + +lemma traces_enabled_decode_LDPBLR_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Ct = 29 \ uint Cn \ invoked_indirect_regs" and "RegAuth (uint Cn) \ load_auths" and "uint Ct \ 29 \ \invokes_indirect_caps" and "is_indirect_branch" + shows "traces_enabled (decode_LDPBLR_C_C_C opc Cn Ct) s" + unfolding decode_LDPBLR_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDPBR_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "t__arg = 29 \ n \ invoked_indirect_regs" and "RegAuth n \ load_auths" and "t__arg \ 29 \ \invokes_indirect_caps" and "is_indirect_branch" + shows "traces_enabled (execute_LDPBR_C_C_C branch_type n t__arg) s" + unfolding execute_LDPBR_C_C_C_def bind_assoc + by (traces_enabledI assms: assms elim: traces_enabled_C_set_mem_cap enabled_branch_target_CapUnseal_mem_cap enabled_branch_target_CapSquashPostLoadCap) + +lemma traces_enabled_decode_LDPBR_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Ct = 29 \ uint Cn \ invoked_indirect_regs" and "RegAuth (uint Cn) \ load_auths" and "uint Ct \ 29 \ \invokes_indirect_caps" and "is_indirect_branch" + shows "traces_enabled (decode_LDPBR_C_C_C opc Cn Ct) s" + unfolding decode_LDPBR_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDP_CC_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDP_CC_RIAW_C acctype n offset t__arg t2) s" + unfolding execute_LDP_CC_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDP_CC_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDP_CC_RIAW_C L imm7 Ct2 Rn Ct) s" + unfolding decode_LDP_CC_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDP_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDP_C_RIBW_C acctype n offset t__arg t2) s" + unfolding execute_LDP_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDP_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDP_C_RIBW_C L imm7 Ct2 Rn Ct) s" + unfolding decode_LDP_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDP_C_RIB_C acctype n offset t__arg t2) s" + unfolding execute_LDP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDP_C_RIB_C L imm7 Ct2 Rn Ct) s" + unfolding decode_LDP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDR_C_I_C[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "\invokes_indirect_caps" and "PCCAuth \ load_auths" + shows "traces_enabled (execute_LDR_C_I_C offset t__arg) s" + unfolding execute_LDR_C_I_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDR_C_I_C[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "\invokes_indirect_caps" and "PCCAuth \ load_auths" + shows "traces_enabled (decode_LDR_C_I_C imm17 Ct) s" + unfolding decode_LDR_C_I_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDR_C_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDR_C_RIAW_C n offset t__arg) s" + unfolding execute_LDR_C_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDR_C_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDR_C_RIAW_C opc imm9 Rn Ct) s" + unfolding decode_LDR_C_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDR_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDR_C_RIBW_C n offset t__arg) s" + unfolding execute_LDR_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDR_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDR_C_RIBW_C opc imm9 Rn Ct) s" + unfolding decode_LDR_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDR_C_RRB_C extend_type m n shift t__arg) s" + unfolding execute_LDR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDR_C_RRB_C opc Rm sign sz S Rn Ct) s" + unfolding decode_LDR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDR_C_RUIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDR_C_RUIB_C n offset t__arg) s" + unfolding execute_LDR_C_RUIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDR_C_RUIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDR_C_RUIB_C L imm12 Rn Ct) s" + unfolding decode_LDR_C_RUIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDTR_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDTR_C_RIB_C n offset t__arg) s" + unfolding execute_LDTR_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDTR_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDTR_C_RIB_C opc imm9 Rn Ct) s" + unfolding decode_LDTR_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDUR_C_RI_C n offset t__arg) s" + unfolding execute_LDUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDUR_C_RI_C opc imm9 Rn Ct) s" + unfolding decode_LDUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDXP_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDXP_C_R_C acctype n t__arg t2) s" + unfolding execute_LDXP_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDXP_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDXP_C_R_C L Ct2 Rn Ct) s" + unfolding decode_LDXP_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDXR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDXR_C_R_C acctype n t__arg) s" + unfolding execute_LDXR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDXR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDXR_C_R_C L Rn Ct) s" + unfolding decode_LDXR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_MRS_C_I_C[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "sys_op2 \ {0, 1, 2, 3, 4, 5, 6, 7}" and "sys_op1 \ {0, 1, 2, 3, 4, 5, 6, 7}" and "sys_op0 \ {2, 3}" and "0 \ sys_crn" and "sys_crn \ 15" and "0 \ sys_crm" and "sys_crm \ 15" + shows "traces_enabled (execute_MRS_C_I_C sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg) s" + unfolding execute_MRS_C_I_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_MRS_C_I_C[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_MRS_C_I_C L o0 op1 CRn CRm op2 Ct) s" + unfolding decode_MRS_C_I_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_MSR_C_I_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "sys_op2 \ {0, 1, 2, 3, 4, 5, 6, 7}" and "sys_op1 \ {0, 1, 2, 3, 4, 5, 6, 7}" and "sys_op0 \ {2, 3}" and "0 \ sys_crn" and "sys_crn \ 15" and "0 \ sys_crm" and "sys_crm \ 15" + shows "traces_enabled (execute_MSR_C_I_C sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg) s" + unfolding execute_MSR_C_I_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_MSR_C_I_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_MSR_C_I_C L o0 op1 CRn CRm op2 Ct) s" + unfolding decode_MSR_C_I_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ORRFLGS_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_ORRFLGS_C_CI_C d mask__arg n) s" + unfolding execute_ORRFLGS_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ORRFLGS_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ORRFLGS_C_CI_C imm8 Cn Cd) s" + unfolding decode_ORRFLGS_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ORRFLGS_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_ORRFLGS_C_CR_C d m n) s" + unfolding execute_ORRFLGS_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ORRFLGS_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ORRFLGS_C_CR_C Rm opc Cn Cd) s" + unfolding decode_ORRFLGS_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_RETR_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "n \ invoked_regs" + shows "traces_enabled (execute_RETR_C_C branch_type n) s" + unfolding execute_RETR_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_RETR_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cn \ invoked_regs" + shows "traces_enabled (decode_RETR_C_C opc Cn) s" + unfolding decode_RETR_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_RETS_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "n \ invoked_regs" + shows "traces_enabled (execute_RETS_C_C branch_type n) s" + unfolding execute_RETS_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_RETS_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cn \ invoked_regs" + shows "traces_enabled (decode_RETS_C_C opc Cn) s" + unfolding decode_RETS_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_RETS_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "m \ invoked_regs" and "n \ invoked_regs" + shows "traces_enabled (execute_RETS_C_C_C branch_type m n) s" + unfolding execute_RETS_C_C_C_def bind_assoc + by (traces_enabledI assms: assms intro: enabled_branch_target_CapUnseal_if_clear elim: branch_sealed_pair_enabled_pcc traces_enabled_C_set_29_branch_sealed_pair) + +lemma traces_enabled_decode_RETS_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cm \ invoked_regs" and "uint Cn \ invoked_regs" + shows "traces_enabled (decode_RETS_C_C_C Cm opc Cn) s" + unfolding decode_RETS_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_RET_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "n \ invoked_regs" + shows "traces_enabled (execute_RET_C_C branch_type n) s" + unfolding execute_RET_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_RET_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cn \ invoked_regs" + shows "traces_enabled (decode_RET_C_C opc Cn) s" + unfolding decode_RET_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_RRLEN_R_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_RRLEN_R_R_C d n) s" + unfolding execute_RRLEN_R_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_RRLEN_R_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_RRLEN_R_R_C opc Rn Rd) s" + unfolding decode_RRLEN_R_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_RRMASK_R_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_RRMASK_R_R_C d n) s" + unfolding execute_RRMASK_R_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_RRMASK_R_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_RRMASK_R_R_C opc Rn Rd) s" + unfolding decode_RRMASK_R_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SCBNDSE_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_SCBNDSE_C_CR_C d m n) s" + unfolding execute_SCBNDSE_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SCBNDSE_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_SCBNDSE_C_CR_C Rm opc Cn Cd) s" + unfolding decode_SCBNDSE_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SCBNDS_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" and "length__arg \ 2^64" + shows "traces_enabled (execute_SCBNDS_C_CI_C d length__arg n) s" + unfolding execute_SCBNDS_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SCBNDS_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_SCBNDS_C_CI_C imm6 S Cn Cd) s" + unfolding decode_SCBNDS_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SCBNDS_C_CI_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" and "length__arg \ 2^64" + shows "traces_enabled (execute_SCBNDS_C_CI_S d length__arg n) s" + unfolding execute_SCBNDS_C_CI_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SCBNDS_C_CI_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_SCBNDS_C_CI_S imm6 S Cn Cd) s" + unfolding decode_SCBNDS_C_CI_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SCBNDS_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_SCBNDS_C_CR_C d m n) s" + unfolding execute_SCBNDS_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SCBNDS_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_SCBNDS_C_CR_C Rm opc Cn Cd) s" + unfolding decode_SCBNDS_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SCFLGS_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_SCFLGS_C_CR_C d m n) s" + unfolding execute_SCFLGS_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SCFLGS_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_SCFLGS_C_CR_C Rm Cn Cd) s" + unfolding decode_SCFLGS_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SCOFF_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_SCOFF_C_CR_C d m n) s" + unfolding execute_SCOFF_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SCOFF_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_SCOFF_C_CR_C Rm opc Cn Cd) s" + unfolding decode_SCOFF_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SCTAG_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_SCTAG_C_CR_C d m n) s" + unfolding execute_SCTAG_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms elim: and_exp_SystemAccessEnabled_TagSettingEnabledE[where thesis = "(if a then x else y) \ derivable_caps s" and a = a for a x y s]) + +lemma traces_enabled_decode_SCTAG_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_SCTAG_C_CR_C Rm Cn Cd) s" + unfolding decode_SCTAG_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SCVALUE_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_SCVALUE_C_CR_C d m n) s" + unfolding execute_SCVALUE_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SCVALUE_C_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_SCVALUE_C_CR_C Rm opc Cn Cd) s" + unfolding decode_SCVALUE_C_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SEAL_C_CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_SEAL_C_CC_C d m n) s" + unfolding execute_SEAL_C_CC_C_def bind_assoc + by (traces_enabledI assms: assms simp: Run_and_boolM_True_iff elim: CapIsInBounds_cursor_in_mem_region) + +lemma traces_enabled_decode_SEAL_C_CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_SEAL_C_CC_C Cm opc Cn Cd) s" + unfolding decode_SEAL_C_CC_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SEAL_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "f \ {0, 1, 2, 3}" + shows "traces_enabled (execute_SEAL_C_CI_C d f n) s" + unfolding execute_SEAL_C_CI_C_def bind_assoc + by (traces_enabledI assms: assms intro: CapSetObjectType_sentry_derivable) + +lemma traces_enabled_decode_SEAL_C_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_SEAL_C_CI_C form Cn Cd) s" + unfolding decode_SEAL_C_CI_C_def bind_assoc + by (cases form rule: exhaustive_2_word) (use assms in \auto intro: traces_enabled_execute_SEAL_C_CI_C\) + +lemma traces_enabled_execute_STCT_R_R[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STCT_R_R n t__arg) s" + unfolding execute_STCT_R_R_def bind_assoc + by (traces_enabledI assms: assms elim: and_SystemAccessEnabled_TagSettingEnabledE[where thesis = "(if a then x else y) = z" and a = a for a x y z]) + +lemma traces_enabled_decode_STCT_R_R[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STCT_R_R opc Rn Rt) s" + unfolding decode_STCT_R_R_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STLR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STLR_C_R_C acctype n t__arg) s" + unfolding execute_STLR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STLR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STLR_C_R_C L Rn Ct) s" + unfolding decode_STLR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STLXP_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STLXP_R_CR_C acctype n s__arg t__arg t2) s" + unfolding execute_STLXP_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STLXP_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STLXP_R_CR_C L Rs Ct2 Rn Ct) s" + unfolding decode_STLXP_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STLXR_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STLXR_R_CR_C acctype n s__arg t__arg) s" + unfolding execute_STLXR_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STLXR_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STLXR_R_CR_C L Rs Rn Ct) s" + unfolding decode_STLXR_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STNP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STNP_C_RIB_C acctype n offset t__arg t2) s" + unfolding execute_STNP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STNP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STNP_C_RIB_C L imm7 Ct2 Rn Ct) s" + unfolding decode_STNP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STP_CC_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STP_CC_RIAW_C acctype n offset t__arg t2) s" + unfolding execute_STP_CC_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STP_CC_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STP_CC_RIAW_C L imm7 Ct2 Rn Ct) s" + unfolding decode_STP_CC_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STP_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STP_C_RIBW_C acctype n offset t__arg t2) s" + unfolding execute_STP_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STP_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STP_C_RIBW_C L imm7 Ct2 Rn Ct) s" + unfolding decode_STP_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STP_C_RIB_C acctype n offset t__arg t2) s" + unfolding execute_STP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STP_C_RIB_C L imm7 Ct2 Rn Ct) s" + unfolding decode_STP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STR_C_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STR_C_RIAW_C n offset t__arg) s" + unfolding execute_STR_C_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STR_C_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STR_C_RIAW_C opc imm9 Rn Ct) s" + unfolding decode_STR_C_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STR_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STR_C_RIBW_C n offset t__arg) s" + unfolding execute_STR_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STR_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STR_C_RIBW_C opc imm9 Rn Ct) s" + unfolding decode_STR_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_STR_C_RRB_C extend_type m n shift t__arg) s" + unfolding execute_STR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STR_C_RRB_C opc Rm sign sz S Rn Ct) s" + unfolding decode_STR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STR_C_RUIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STR_C_RUIB_C n offset t__arg) s" + unfolding execute_STR_C_RUIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STR_C_RUIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STR_C_RUIB_C L imm12 Rn Ct) s" + unfolding decode_STR_C_RUIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STTR_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STTR_C_RIB_C n offset t__arg) s" + unfolding execute_STTR_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STTR_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STTR_C_RIB_C opc imm9 Rn Ct) s" + unfolding decode_STTR_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STUR_C_RI_C n offset t__arg) s" + unfolding execute_STUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STUR_C_RI_C opc imm9 Rn Ct) s" + unfolding decode_STUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STXP_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STXP_R_CR_C acctype n s__arg t__arg t2) s" + unfolding execute_STXP_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STXP_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STXP_R_CR_C L Rs Ct2 Rn Ct) s" + unfolding decode_STXP_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STXR_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STXR_R_CR_C acctype n s__arg t__arg) s" + unfolding execute_STXR_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STXR_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STXR_R_CR_C L Rs Rn Ct) s" + unfolding decode_STXR_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SUBS_R_CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_SUBS_R_CC_C d m n) s" + unfolding execute_SUBS_R_CC_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SUBS_R_CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_SUBS_R_CC_C Cm Cn Rd) s" + unfolding decode_SUBS_R_CC_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SUB_C_CIS_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_SUB_C_CIS_C d imm n) s" + unfolding execute_SUB_C_CIS_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SUB_C_CIS_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_SUB_C_CIS_C A sh imm12 Cn Cd) s" + unfolding decode_SUB_C_CIS_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SWPAL_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_SWPAL_CC_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_SWPAL_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SWPAL_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_SWPAL_CC_R_C A R Cs Rn Ct) s" + unfolding decode_SWPAL_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SWPA_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_SWPA_CC_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_SWPA_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SWPA_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_SWPA_CC_R_C A R Cs Rn Ct) s" + unfolding decode_SWPA_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SWPL_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_SWPL_CC_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_SWPL_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SWPL_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_SWPL_CC_R_C A R Cs Rn Ct) s" + unfolding decode_SWPL_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SWP_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_SWP_CC_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_SWP_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SWP_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_SWP_CC_R_C A R Cs Rn Ct) s" + unfolding decode_SWP_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_UNSEAL_C_CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_UNSEAL_C_CC_C d m n) s" + unfolding execute_UNSEAL_C_CC_C_def bind_assoc + by (traces_enabledI assms: assms intro: CapUnseal_check_global_derivable simp: Run_and_boolM_True_iff) + +lemma traces_enabled_decode_UNSEAL_C_CC_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_UNSEAL_C_CC_C Cm opc Cn Cd) s" + unfolding decode_UNSEAL_C_CC_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n neg) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd Rd Rn b__0 U b__1) s" + unfolding decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd Rd Rn b__0 U) s" + unfolding decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_arithmetic_add_sub_carry[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_arithmetic_add_sub_carry d (datasize :: 'datasize::len itself) m n setflags sub_op) s" + unfolding execute_aarch64_instrs_integer_arithmetic_add_sub_carry_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_adc_aarch64_instrs_integer_arithmetic_add_sub_carry[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_adc_aarch64_instrs_integer_arithmetic_add_sub_carry Rd Rn Rm S op b__0) s" + unfolding decode_adc_aarch64_instrs_integer_arithmetic_add_sub_carry_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_adcs_aarch64_instrs_integer_arithmetic_add_sub_carry[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_adcs_aarch64_instrs_integer_arithmetic_add_sub_carry Rd Rn Rm S op b__0) s" + unfolding decode_adcs_aarch64_instrs_integer_arithmetic_add_sub_carry_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "shift \ {0, 1, 2, 3, 4, 5, 6, 7}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_arithmetic_add_sub_extendedreg d (datasize :: 'datasize::len itself) extend_type m n setflags shift sub_op) s" + unfolding execute_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_add_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_add_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg Rd Rn imm3 option_name Rm S op b__0) s" + unfolding decode_add_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_arithmetic_add_sub_immediate[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "datasize \ {32, 64}" and "0 \ d" and "d \ 31" and "int (size imm) = datasize" + shows "traces_enabled (execute_aarch64_instrs_integer_arithmetic_add_sub_immediate d datasize imm n setflags sub_op) s" + unfolding execute_aarch64_instrs_integer_arithmetic_add_sub_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_add_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_add_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate Rd Rn imm12 sh S op b__0) s" + unfolding decode_add_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ shift_amount" and "shift_amount \ 63" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg d (datasize :: 'datasize::len itself) m n setflags shift_amount shift_type sub_op) s" + unfolding execute_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_add_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_add_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg Rd Rn imm6 Rm shift S op b__0) s" + unfolding decode_add_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n sub_op) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd Rd Rn Rm b__0 U b__1) s" + unfolding decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd Rd Rn Rm b__0 U) s" + unfolding decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "l__40 \ {8, 16, 32, 64}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow d datasize elements l__40 m n part round__arg sub_op) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_addhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_addhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_addhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_reduce_add_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_reduce_add_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op) s" + unfolding execute_aarch64_instrs_vector_reduce_add_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_addp_advsimd_pair_aarch64_instrs_vector_reduce_add_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_addp_advsimd_pair_aarch64_instrs_vector_reduce_add_sisd Rd Rn b__0) s" + unfolding decode_addp_advsimd_pair_aarch64_instrs_vector_reduce_add_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "l__179 \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair d l__179 elements (esize :: 'esize::len itself) m n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_addp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_addp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair Rd Rn Rm b__0 b__1) s" + unfolding decode_addp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_adds_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_adds_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg Rd Rn imm3 option_name Rm S op b__0) s" + unfolding decode_adds_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_adds_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_adds_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate Rd Rn imm12 sh S op b__0) s" + unfolding decode_adds_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_adds_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_adds_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg Rd Rn imm6 Rm shift S op b__0) s" + unfolding decode_adds_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_reduce_add_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_reduce_add_simd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op) s" + unfolding execute_aarch64_instrs_vector_reduce_add_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_addv_advsimd_aarch64_instrs_vector_reduce_add_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_addv_advsimd_aarch64_instrs_vector_reduce_add_simd Rd Rn b__0 b__1) s" + unfolding decode_addv_advsimd_aarch64_instrs_vector_reduce_add_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_aes_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_aes_round d decrypt n) s" + unfolding execute_aarch64_instrs_vector_crypto_aes_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_aesd_advsimd_aarch64_instrs_vector_crypto_aes_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_aesd_advsimd_aarch64_instrs_vector_crypto_aes_round Rd Rn D) s" + unfolding decode_aesd_advsimd_aarch64_instrs_vector_crypto_aes_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_aese_advsimd_aarch64_instrs_vector_crypto_aes_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_aese_advsimd_aarch64_instrs_vector_crypto_aes_round Rd Rn D) s" + unfolding decode_aese_advsimd_aarch64_instrs_vector_crypto_aes_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_aes_mix[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_aes_mix d decrypt n) s" + unfolding execute_aarch64_instrs_vector_crypto_aes_mix_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_aesimc_advsimd_aarch64_instrs_vector_crypto_aes_mix[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_aesimc_advsimd_aarch64_instrs_vector_crypto_aes_mix Rd Rn D) s" + unfolding decode_aesimc_advsimd_aarch64_instrs_vector_crypto_aes_mix_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_aesmc_advsimd_aarch64_instrs_vector_crypto_aes_mix[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_aesmc_advsimd_aarch64_instrs_vector_crypto_aes_mix Rd Rn D) s" + unfolding decode_aesmc_advsimd_aarch64_instrs_vector_crypto_aes_mix_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr d (datasize :: 'datasize::len itself) invert m n op) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_and_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_and_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0) s" + unfolding decode_and_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_logical_immediate[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "datasize \ {32, 64}" and "0 \ d" and "d \ 31" and "int (size imm) = datasize" + shows "traces_enabled (execute_aarch64_instrs_integer_logical_immediate d datasize imm n op setflags) s" + unfolding execute_aarch64_instrs_integer_logical_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_and_log_imm_aarch64_instrs_integer_logical_immediate[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_and_log_imm_aarch64_instrs_integer_logical_immediate Rd Rn imms immr N opc b__0) s" + unfolding decode_and_log_imm_aarch64_instrs_integer_logical_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_logical_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ shift_amount" and "shift_amount \ 63" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_logical_shiftedreg d (datasize :: 'datasize::len itself) invert m n op setflags shift_amount shift_type) s" + unfolding execute_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_and_log_shift_aarch64_instrs_integer_logical_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_and_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0) s" + unfolding decode_and_log_shift_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ands_log_imm_aarch64_instrs_integer_logical_immediate[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ands_log_imm_aarch64_instrs_integer_logical_immediate Rd Rn imms immr N opc b__0) s" + unfolding decode_ands_log_imm_aarch64_instrs_integer_logical_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ands_log_shift_aarch64_instrs_integer_logical_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ands_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0) s" + unfolding decode_ands_log_shift_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_shift_variable[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_shift_variable d (datasize :: 'datasize::len itself) m n shift_type) s" + unfolding execute_aarch64_instrs_integer_shift_variable_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_asrv_aarch64_instrs_integer_shift_variable[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_asrv_aarch64_instrs_integer_shift_variable Rd Rn op2 Rm b__0) s" + unfolding decode_asrv_aarch64_instrs_integer_shift_variable_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_branch_conditional_cond[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (execute_aarch64_instrs_branch_conditional_cond condition offset) s" + unfolding execute_aarch64_instrs_branch_conditional_cond_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_b_cond_aarch64_instrs_branch_conditional_cond[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_b_cond_aarch64_instrs_branch_conditional_cond cond imm19) s" + unfolding decode_b_cond_aarch64_instrs_branch_conditional_cond_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_branch_unconditional_immediate[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (execute_aarch64_instrs_branch_unconditional_immediate branch_type offset) s" + unfolding execute_aarch64_instrs_branch_unconditional_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_b_uncond_aarch64_instrs_branch_unconditional_immediate[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_b_uncond_aarch64_instrs_branch_unconditional_immediate imm26 op) s" + unfolding decode_b_uncond_aarch64_instrs_branch_unconditional_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha3_bcax[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" and "0 \ a" and "a \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha3_bcax a d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha3_bcax_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_bcax_advsimd_aarch64_instrs_vector_crypto_sha3_bcax[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_bcax_advsimd_aarch64_instrs_vector_crypto_sha3_bcax Rd Rn Ra Rm) s" + unfolding decode_bcax_advsimd_aarch64_instrs_vector_crypto_sha3_bcax_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_bitfield[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "datasize \ {32, 64}" and "0 \ d" and "d \ 31" and "0 \ S" and "S \ 63" and "0 \ R" and "R \ 63" and "int (size wmask) = datasize" and "int (size tmask) = datasize" + shows "traces_enabled (execute_aarch64_instrs_integer_bitfield R S d datasize extend__arg inzero n tmask wmask) s" + unfolding execute_aarch64_instrs_integer_bitfield_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_bfm_aarch64_instrs_integer_bitfield[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_bfm_aarch64_instrs_integer_bitfield Rd Rn imms immr N opc b__0) s" + unfolding decode_bfm_aarch64_instrs_integer_bitfield_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_logical[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ rd" and "rd \ 31" and "datasize \ {64, 128}" and "int (size imm) = datasize" + shows "traces_enabled (execute_aarch64_instrs_vector_logical datasize imm operation rd) s" + unfolding execute_aarch64_instrs_vector_logical_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_bic_advsimd_imm_aarch64_instrs_vector_logical[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_bic_advsimd_imm_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0) s" + unfolding decode_bic_advsimd_imm_aarch64_instrs_vector_logical_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_bic_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_bic_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0) s" + unfolding decode_bic_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_bic_log_shift_aarch64_instrs_integer_logical_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_bic_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0) s" + unfolding decode_bic_log_shift_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_bics_aarch64_instrs_integer_logical_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_bics_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0) s" + unfolding decode_bics_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor d (datasize :: 'datasize::len itself) m n op) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_bif_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_bif_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0) s" + unfolding decode_bif_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_bit_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_bit_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0) s" + unfolding decode_bit_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_bl_aarch64_instrs_branch_unconditional_immediate[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_bl_aarch64_instrs_branch_unconditional_immediate imm26 op) s" + unfolding decode_bl_aarch64_instrs_branch_unconditional_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_branch_unconditional_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_aarch64_instrs_branch_unconditional_register branch_type n) s" + unfolding execute_aarch64_instrs_branch_unconditional_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_blr_aarch64_instrs_branch_unconditional_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_blr_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z) s" + unfolding decode_blr_aarch64_instrs_branch_unconditional_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_blra_aarch64_instrs_branch_unconditional_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_blra_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z) s" + unfolding decode_blra_aarch64_instrs_branch_unconditional_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_br_aarch64_instrs_branch_unconditional_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_br_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z) s" + unfolding decode_br_aarch64_instrs_branch_unconditional_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_bra_aarch64_instrs_branch_unconditional_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_bra_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z) s" + unfolding decode_bra_aarch64_instrs_branch_unconditional_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_system_exceptions_debug_breakpoint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (execute_aarch64_instrs_system_exceptions_debug_breakpoint comment) s" + unfolding execute_aarch64_instrs_system_exceptions_debug_breakpoint_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint imm16) s" + unfolding decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_bsl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_bsl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0) s" + unfolding decode_bsl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_atomicops_cas_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_atomicops_cas_single (datasize :: 'datasize::len itself) ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg) s" + unfolding execute_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cas_aarch64_instrs_memory_atomicops_cas_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_cas_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs L b__0) s" + unfolding decode_cas_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_casb_aarch64_instrs_memory_atomicops_cas_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_casb_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs L b__0) s" + unfolding decode_casb_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cash_aarch64_instrs_memory_atomicops_cas_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_cash_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs L b__0) s" + unfolding decode_cash_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_atomicops_cas_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "l__38 \ {32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_atomicops_cas_pair l__38 ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg) s" + unfolding execute_aarch64_instrs_memory_atomicops_cas_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_casp_aarch64_instrs_memory_atomicops_cas_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_casp_aarch64_instrs_memory_atomicops_cas_pair Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_casp_aarch64_instrs_memory_atomicops_cas_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_branch_conditional_compare[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "int LENGTH('datasize) \ {32, 64}" + shows "traces_enabled (execute_aarch64_instrs_branch_conditional_compare (datasize :: 'datasize::len itself) iszero__arg offset t__arg) s" + unfolding execute_aarch64_instrs_branch_conditional_compare_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cbnz_aarch64_instrs_branch_conditional_compare[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_cbnz_aarch64_instrs_branch_conditional_compare Rt imm19 op b__0) s" + unfolding decode_cbnz_aarch64_instrs_branch_conditional_compare_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cbz_aarch64_instrs_branch_conditional_compare[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_cbz_aarch64_instrs_branch_conditional_compare Rt imm19 op b__0) s" + unfolding decode_cbz_aarch64_instrs_branch_conditional_compare_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_conditional_compare_immediate[traces_enabledI]: + assumes "0 \ n" and "n \ 31" and "datasize \ {32, 64}" and "int (size imm) = datasize" + shows "traces_enabled (execute_aarch64_instrs_integer_conditional_compare_immediate condition datasize flags__arg imm n sub_op) s" + unfolding execute_aarch64_instrs_integer_conditional_compare_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ccmn_imm_aarch64_instrs_integer_conditional_compare_immediate[traces_enabledI]: + "traces_enabled (decode_ccmn_imm_aarch64_instrs_integer_conditional_compare_immediate nzcv Rn cond imm5 op b__0) s" + unfolding decode_ccmn_imm_aarch64_instrs_integer_conditional_compare_immediate_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_execute_aarch64_instrs_integer_conditional_compare_register[traces_enabledI]: + assumes "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {32, 64}" + shows "traces_enabled (execute_aarch64_instrs_integer_conditional_compare_register condition (datasize :: 'datasize::len itself) flags__arg m n sub_op) s" + unfolding execute_aarch64_instrs_integer_conditional_compare_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ccmn_reg_aarch64_instrs_integer_conditional_compare_register[traces_enabledI]: + "traces_enabled (decode_ccmn_reg_aarch64_instrs_integer_conditional_compare_register nzcv Rn cond Rm op b__0) s" + unfolding decode_ccmn_reg_aarch64_instrs_integer_conditional_compare_register_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_decode_ccmp_imm_aarch64_instrs_integer_conditional_compare_immediate[traces_enabledI]: + "traces_enabled (decode_ccmp_imm_aarch64_instrs_integer_conditional_compare_immediate nzcv Rn cond imm5 op b__0) s" + unfolding decode_ccmp_imm_aarch64_instrs_integer_conditional_compare_immediate_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_decode_ccmp_reg_aarch64_instrs_integer_conditional_compare_register[traces_enabledI]: + "traces_enabled (decode_ccmp_reg_aarch64_instrs_integer_conditional_compare_register nzcv Rn cond Rm op b__0) s" + unfolding decode_ccmp_reg_aarch64_instrs_integer_conditional_compare_register_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_clsz[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_clsz countop d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_clsz_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cls_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cls_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz Rd Rn b__0 U b__1) s" + unfolding decode_cls_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_arithmetic_cnt[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_arithmetic_cnt d (datasize :: 'datasize::len itself) n opcode) s" + unfolding execute_aarch64_instrs_integer_arithmetic_cnt_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cls_int_aarch64_instrs_integer_arithmetic_cnt[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_cls_int_aarch64_instrs_integer_arithmetic_cnt Rd Rn op b__0) s" + unfolding decode_cls_int_aarch64_instrs_integer_arithmetic_cnt_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_clz_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_clz_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz Rd Rn b__0 U b__1) s" + unfolding decode_clz_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_clz_int_aarch64_instrs_integer_arithmetic_cnt[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_clz_int_aarch64_instrs_integer_arithmetic_cnt Rd Rn op b__0) s" + unfolding decode_clz_int_aarch64_instrs_integer_arithmetic_cnt_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd and_test d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd Rd Rn Rm b__0 U b__1) s" + unfolding decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd Rd Rn Rm b__0 U) s" + unfolding decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1) s" + unfolding decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U) s" + unfolding decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd cmp_eq d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1) s" + unfolding decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U) s" + unfolding decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1) s" + unfolding decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U) s" + unfolding decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1) s" + unfolding decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U) s" + unfolding decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1) s" + unfolding decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U) s" + unfolding decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1) s" + unfolding decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U) s" + unfolding decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1) s" + unfolding decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U) s" + unfolding decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1) s" + unfolding decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U) s" + unfolding decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_simd Rd Rn b__0 b__1) s" + unfolding decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd Rd Rn b__0) s" + unfolding decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd Rd Rn Rm b__0 U b__1) s" + unfolding decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd Rd Rn Rm b__0 U) s" + unfolding decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_cnt[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "esize = 8" and "elements \ {8, 16}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_cnt d (datasize :: 'datasize::len itself) elements esize n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_cnt_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cnt_advsimd_aarch64_instrs_vector_arithmetic_unary_cnt[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_cnt_advsimd_aarch64_instrs_vector_arithmetic_unary_cnt Rd Rn size__arg b__0) s" + unfolding decode_cnt_advsimd_aarch64_instrs_vector_arithmetic_unary_cnt_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_crc[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "l__155 \ {8, 16, 32, 64}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_crc crc32c d m n l__155) s" + unfolding execute_aarch64_instrs_integer_crc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_crc32_aarch64_instrs_integer_crc[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_crc32_aarch64_instrs_integer_crc Rd Rn b__0 C Rm sf) s" + unfolding decode_crc32_aarch64_instrs_integer_crc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_crc32c_aarch64_instrs_integer_crc[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_crc32c_aarch64_instrs_integer_crc Rd Rn b__0 C Rm sf) s" + unfolding decode_crc32c_aarch64_instrs_integer_crc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_conditional_select[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_conditional_select condition d (datasize :: 'datasize::len itself) else_inc else_inv m n) s" + unfolding execute_aarch64_instrs_integer_conditional_select_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_csel_aarch64_instrs_integer_conditional_select[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_csel_aarch64_instrs_integer_conditional_select Rd Rn o2 cond Rm op b__0) s" + unfolding decode_csel_aarch64_instrs_integer_conditional_select_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_csinc_aarch64_instrs_integer_conditional_select[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_csinc_aarch64_instrs_integer_conditional_select Rd Rn o2 cond Rm op b__0) s" + unfolding decode_csinc_aarch64_instrs_integer_conditional_select_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_csinv_aarch64_instrs_integer_conditional_select[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_csinv_aarch64_instrs_integer_conditional_select Rd Rn o2 cond Rm op b__0) s" + unfolding decode_csinv_aarch64_instrs_integer_conditional_select_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_csneg_aarch64_instrs_integer_conditional_select[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_csneg_aarch64_instrs_integer_conditional_select Rd Rn o2 cond Rm op b__0) s" + unfolding decode_csneg_aarch64_instrs_integer_conditional_select_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_system_exceptions_debug_exception[traces_enabledI]: + "traces_enabled (execute_aarch64_instrs_system_exceptions_debug_exception target_level) s" + unfolding execute_aarch64_instrs_system_exceptions_debug_exception_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_decode_dcps1_aarch64_instrs_system_exceptions_debug_exception[traces_enabledI]: + "traces_enabled (decode_dcps1_aarch64_instrs_system_exceptions_debug_exception LL imm16) s" + unfolding decode_dcps1_aarch64_instrs_system_exceptions_debug_exception_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_decode_dcps2_aarch64_instrs_system_exceptions_debug_exception[traces_enabledI]: + "traces_enabled (decode_dcps2_aarch64_instrs_system_exceptions_debug_exception LL imm16) s" + unfolding decode_dcps2_aarch64_instrs_system_exceptions_debug_exception_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_decode_dcps3_aarch64_instrs_system_exceptions_debug_exception[traces_enabledI]: + "traces_enabled (decode_dcps3_aarch64_instrs_system_exceptions_debug_exception LL imm16) s" + unfolding decode_dcps3_aarch64_instrs_system_exceptions_debug_exception_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_execute_aarch64_instrs_branch_unconditional_dret[traces_enabledI]: + "traces_enabled (execute_aarch64_instrs_branch_unconditional_dret arg0) s" + unfolding execute_aarch64_instrs_branch_unconditional_dret_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_decode_drps_aarch64_instrs_branch_unconditional_dret[traces_enabledI]: + "traces_enabled (decode_drps_aarch64_instrs_branch_unconditional_dret arg0) s" + unfolding decode_drps_aarch64_instrs_branch_unconditional_dret_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_execute_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('idxdsize) \ {64, 128}" and "int LENGTH('esize) \ {8, 16, 32, 64, 128, 256}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg n) s" + unfolding execute_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_simd Rd Rn b__0 b__1) s" + unfolding decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd Rd Rn b__0) s" + unfolding decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_transfer_integer_dup[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64, 128, 256}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_transfer_integer_dup d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n) s" + unfolding execute_aarch64_instrs_vector_transfer_integer_dup_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_dup_advsimd_gen_aarch64_instrs_vector_transfer_integer_dup[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_dup_advsimd_gen_aarch64_instrs_vector_transfer_integer_dup Rd Rn b__0 b__1) s" + unfolding decode_dup_advsimd_gen_aarch64_instrs_vector_transfer_integer_dup_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_eon_aarch64_instrs_integer_logical_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_eon_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0) s" + unfolding decode_eon_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha3_eor3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" and "0 \ a" and "a \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha3_eor3 a d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha3_eor3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_eor3_advsimd_aarch64_instrs_vector_crypto_sha3_eor3[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_eor3_advsimd_aarch64_instrs_vector_crypto_sha3_eor3 Rd Rn Ra Rm) s" + unfolding decode_eor3_advsimd_aarch64_instrs_vector_crypto_sha3_eor3_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_eor_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_eor_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0) s" + unfolding decode_eor_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_eor_log_imm_aarch64_instrs_integer_logical_immediate[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_eor_log_imm_aarch64_instrs_integer_logical_immediate Rd Rn imms immr N opc b__0) s" + unfolding decode_eor_log_imm_aarch64_instrs_integer_logical_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_eor_log_shift_aarch64_instrs_integer_logical_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_eor_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0) s" + unfolding decode_eor_log_shift_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_branch_unconditional_eret[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (execute_aarch64_instrs_branch_unconditional_eret arg0) s" + unfolding execute_aarch64_instrs_branch_unconditional_eret_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_eret_aarch64_instrs_branch_unconditional_eret[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_eret_aarch64_instrs_branch_unconditional_eret op4 Rn M A) s" + unfolding decode_eret_aarch64_instrs_branch_unconditional_eret_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ereta_aarch64_instrs_branch_unconditional_eret[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ereta_aarch64_instrs_branch_unconditional_eret op4 Rn M A) s" + unfolding decode_ereta_aarch64_instrs_branch_unconditional_eret_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_system_hints[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (execute_aarch64_instrs_system_hints op) s" + by (cases op; simp; traces_enabledI assms: assms) + +lemma traces_enabled_decode_esb_aarch64_instrs_system_hints[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_esb_aarch64_instrs_system_hints op2 CRm) s" + unfolding decode_esb_aarch64_instrs_system_hints_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_transfer_vector_extract[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "l__47 \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_transfer_vector_extract d l__47 m n position) s" + unfolding execute_aarch64_instrs_vector_transfer_vector_extract_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ext_advsimd_aarch64_instrs_vector_transfer_vector_extract[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ext_advsimd_aarch64_instrs_vector_transfer_vector_extract Rd Rn imm4 Rm b__0) s" + unfolding decode_ext_advsimd_aarch64_instrs_vector_transfer_vector_extract_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_ins_ext_extract_immediate[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ lsb__arg" and "lsb__arg \ 63" and "l__36 \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_ins_ext_extract_immediate d l__36 lsb__arg m n) s" + unfolding execute_aarch64_instrs_integer_ins_ext_extract_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_extr_aarch64_instrs_integer_ins_ext_extract_immediate[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_extr_aarch64_instrs_integer_ins_ext_extract_immediate Rd Rn imms Rm N b__0) s" + unfolding decode_extr_aarch64_instrs_integer_ins_ext_extract_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd abs__arg d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd Rd Rn Rm U b__0) s" + unfolding decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd Rd Rn Rm) s" + unfolding decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd Rd Rn Rm b__0 U b__1) s" + unfolding decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_sisd Rd Rn Rm b__0) s" + unfolding decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n neg) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float Rd Rn b__0 U b__1) s" + unfolding decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16 Rd Rn U b__0) s" + unfolding decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_arithmetic_unary[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_float_arithmetic_unary d (datasize :: 'datasize::len itself) fpop n) s" + unfolding execute_aarch64_instrs_float_arithmetic_unary_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fabs_float_aarch64_instrs_float_arithmetic_unary[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fabs_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0) s" + unfolding decode_fabs_float_aarch64_instrs_float_arithmetic_unary_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd abs__arg cmp d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0) s" + unfolding decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U) s" + unfolding decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1) s" + unfolding decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U) s" + unfolding decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0) s" + unfolding decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U) s" + unfolding decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1) s" + unfolding decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U) s" + unfolding decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "l__163 \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16 d l__163 elements (esize :: 'esize::len itself) m n pair) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp Rd Rn Rm b__0 U b__1) s" + unfolding decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16 Rd Rn Rm U b__0) s" + unfolding decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_arithmetic_add_sub[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_float_arithmetic_add_sub d (datasize :: 'datasize::len itself) m n sub_op) s" + unfolding execute_aarch64_instrs_float_arithmetic_add_sub_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fadd_float_aarch64_instrs_float_arithmetic_add_sub[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fadd_float_aarch64_instrs_float_arithmetic_add_sub Rd Rn op Rm b__0) s" + unfolding decode_fadd_float_aarch64_instrs_float_arithmetic_add_sub_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_reduce_fp16_add_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_reduce_fp16_add_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op) s" + unfolding execute_aarch64_instrs_vector_reduce_fp16_add_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_add_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_add_sisd Rd Rn sz) s" + unfolding decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_add_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp_add_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp_add_sisd Rd Rn b__0) s" + unfolding decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp_add_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp Rd Rn Rm b__0 U b__1) s" + unfolding decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16 Rd Rn Rm U b__0) s" + unfolding decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_compare_cond[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_float_compare_cond condition (datasize :: 'datasize::len itself) flags__arg m n signal_all_nans) s" + unfolding execute_aarch64_instrs_float_compare_cond_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fccmp_float_aarch64_instrs_float_compare_cond[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fccmp_float_aarch64_instrs_float_compare_cond nzcv op Rn cond Rm b__0) s" + unfolding decode_fccmp_float_aarch64_instrs_float_compare_cond_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fccmpe_float_aarch64_instrs_float_compare_cond[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fccmpe_float_aarch64_instrs_float_compare_cond nzcv op Rn cond Rm b__0) s" + unfolding decode_fccmpe_float_aarch64_instrs_float_compare_cond_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0) s" + unfolding decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U) s" + unfolding decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1) s" + unfolding decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U) s" + unfolding decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1) s" + unfolding decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U) s" + unfolding decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0) s" + unfolding decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U) s" + unfolding decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0) s" + unfolding decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U) s" + unfolding decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1) s" + unfolding decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U) s" + unfolding decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1) s" + unfolding decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U) s" + unfolding decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0) s" + unfolding decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U) s" + unfolding decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0) s" + unfolding decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U) s" + unfolding decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1) s" + unfolding decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U) s" + unfolding decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1) s" + unfolding decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U) s" + unfolding decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0) s" + unfolding decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U) s" + unfolding decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1) s" + unfolding decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U) s" + unfolding decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0) s" + unfolding decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U) s" + unfolding decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_simd Rd Rn b__0 b__1) s" + unfolding decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_sisd Rd Rn b__0) s" + unfolding decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_simd Rd Rn b__0) s" + unfolding decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd Rd Rn) s" + unfolding decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_compare_uncond[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_float_compare_uncond cmp_with_zero (datasize :: 'datasize::len itself) m n signal_all_nans) s" + unfolding execute_aarch64_instrs_float_compare_uncond_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmp_float_aarch64_instrs_float_compare_uncond[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmp_float_aarch64_instrs_float_compare_uncond opc Rn Rm b__0) s" + unfolding decode_fcmp_float_aarch64_instrs_float_compare_uncond_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcmpe_float_aarch64_instrs_float_compare_uncond[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcmpe_float_aarch64_instrs_float_compare_uncond opc Rn Rm b__0) s" + unfolding decode_fcmpe_float_aarch64_instrs_float_compare_uncond_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_move_fp_select[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_float_move_fp_select condition d (datasize :: 'datasize::len itself) m n) s" + unfolding execute_aarch64_instrs_float_move_fp_select_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcsel_float_aarch64_instrs_float_move_fp_select[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcsel_float_aarch64_instrs_float_move_fp_select Rd Rn cond Rm b__0) s" + unfolding decode_fcsel_float_aarch64_instrs_float_move_fp_select_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_convert_fp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "int LENGTH('srcsize) \ {16, 32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('dstsize) \ {16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_float_convert_fp d (dstsize :: 'dstsize::len itself) n (srcsize :: 'srcsize::len itself)) s" + unfolding execute_aarch64_instrs_float_convert_fp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvt_float_aarch64_instrs_float_convert_fp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvt_float_aarch64_instrs_float_convert_fp Rd Rn b__0 b__1) s" + unfolding decode_fcvt_float_aarch64_instrs_float_convert_fp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n rounding is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd Rd Rn b__0 U b__1) s" + unfolding decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd Rd Rn b__0 U) s" + unfolding decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd Rd Rn U b__0) s" + unfolding decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd Rd Rn U) s" + unfolding decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "int LENGTH('intsize) \ {32, 64}" and "int LENGTH('fltsize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_float_convert_int d (fltsize :: 'fltsize::len itself) (intsize :: 'intsize::len itself) n op part rounding is_unsigned) s" + unfolding execute_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtas_float_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtas_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_fcvtas_float_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd Rd Rn b__0 U b__1) s" + unfolding decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd Rd Rn b__0 U) s" + unfolding decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd Rd Rn U b__0) s" + unfolding decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd Rd Rn U) s" + unfolding decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtau_float_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtau_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_fcvtau_float_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_float_widen[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "l__177 \ {16, 32}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_float_widen d datasize elements l__177 n part) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_float_widen_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtl_advsimd_aarch64_instrs_vector_arithmetic_unary_float_widen[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtl_advsimd_aarch64_instrs_vector_arithmetic_unary_float_widen Rd Rn b__0 Q) s" + unfolding decode_fcvtl_advsimd_aarch64_instrs_vector_arithmetic_unary_float_widen_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n rounding is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U) s" + unfolding decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0) s" + unfolding decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U) s" + unfolding decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtms_float_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtms_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_fcvtms_float_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U) s" + unfolding decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0) s" + unfolding decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U) s" + unfolding decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtmu_float_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtmu_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_fcvtmu_float_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_float_narrow[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "l__202 \ {16, 32}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_float_narrow d datasize elements l__202 n part) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_float_narrow_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_narrow[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_narrow Rd Rn b__0 Q) s" + unfolding decode_fcvtn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_narrow_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U) s" + unfolding decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0) s" + unfolding decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U) s" + unfolding decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtns_float_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtns_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_fcvtns_float_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U) s" + unfolding decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0) s" + unfolding decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U) s" + unfolding decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtnu_float_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtnu_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_fcvtnu_float_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U) s" + unfolding decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0) s" + unfolding decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U) s" + unfolding decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtps_float_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtps_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_fcvtps_float_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U) s" + unfolding decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0) s" + unfolding decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U) s" + unfolding decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtpu_float_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtpu_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_fcvtpu_float_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "esize = 32" and "elements \ {1, 2}" and "l__53 \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd d l__53 elements esize n part) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_simd Rd Rn sz Q) s" + unfolding decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd Rd Rn sz) s" + unfolding decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_shift_conv_float_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_shift_conv_float_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) fracbits n rounding is_unsigned) s" + unfolding execute_aarch64_instrs_vector_shift_conv_float_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd Rd Rn immb b__0 U b__1) s" + unfolding decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd Rd Rn immb b__0 U) s" + unfolding decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U) s" + unfolding decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0) s" + unfolding decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U) s" + unfolding decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_convert_fix[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('intsize) \ {32, 64}" and "1 \ fracbits" and "fracbits \ 64" and "int LENGTH('fltsize) \ {16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_float_convert_fix d (fltsize :: 'fltsize::len itself) fracbits (intsize :: 'intsize::len itself) n op rounding is_unsigned) s" + unfolding execute_aarch64_instrs_float_convert_fix_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzs_float_fix_aarch64_instrs_float_convert_fix[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzs_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1) s" + unfolding decode_fcvtzs_float_fix_aarch64_instrs_float_convert_fix_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzs_float_int_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzs_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_fcvtzs_float_int_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd Rd Rn immb b__0 U b__1) s" + unfolding decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd Rd Rn immb b__0 U) s" + unfolding decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U) s" + unfolding decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0) s" + unfolding decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U) s" + unfolding decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzu_float_fix_aarch64_instrs_float_convert_fix[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzu_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1) s" + unfolding decode_fcvtzu_float_fix_aarch64_instrs_float_convert_fix_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fcvtzu_float_int_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fcvtzu_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_fcvtzu_float_int_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div Rd Rn Rm b__0 b__1) s" + unfolding decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16 Rd Rn Rm b__0) s" + unfolding decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_arithmetic_div[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_float_arithmetic_div d (datasize :: 'datasize::len itself) m n) s" + unfolding execute_aarch64_instrs_float_arithmetic_div_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fdiv_float_aarch64_instrs_float_arithmetic_div[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fdiv_float_aarch64_instrs_float_arithmetic_div Rd Rn Rm b__0) s" + unfolding decode_fdiv_float_aarch64_instrs_float_arithmetic_div_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fjcvtzs_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fjcvtzs_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_fjcvtzs_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_arithmetic_mul_add_sub[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {16, 32, 64}" and "0 \ d" and "d \ 31" and "0 \ a" and "a \ 31" + shows "traces_enabled (execute_aarch64_instrs_float_arithmetic_mul_add_sub a d (datasize :: 'datasize::len itself) m n op1_neg opa_neg) s" + unfolding execute_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0) s" + unfolding decode_fmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "l__401 \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 d l__401 elements (esize :: 'esize::len itself) m minimum n pair) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0) s" + unfolding decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1) s" + unfolding decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_arithmetic_max_min[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_float_arithmetic_max_min d (datasize :: 'datasize::len itself) m n operation) s" + unfolding execute_aarch64_instrs_float_arithmetic_max_min_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmax_float_aarch64_instrs_float_arithmetic_max_min[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmax_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0) s" + unfolding decode_fmax_float_aarch64_instrs_float_arithmetic_max_min_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "l__435 \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 d l__435 elements (esize :: 'esize::len itself) m minimum n pair) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0) s" + unfolding decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1) s" + unfolding decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxnm_float_aarch64_instrs_float_arithmetic_max_min[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxnm_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0) s" + unfolding decode_fmaxnm_float_aarch64_instrs_float_arithmetic_max_min_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_reduce_fp16_maxnm_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_reduce_fp16_maxnm_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op) s" + unfolding execute_aarch64_instrs_vector_reduce_fp16_maxnm_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd Rd Rn sz o1) s" + unfolding decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd Rd Rn b__0 o1) s" + unfolding decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0) s" + unfolding decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1) s" + unfolding decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_reduce_fp16_maxnm_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_reduce_fp16_maxnm_simd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op) s" + unfolding execute_aarch64_instrs_vector_reduce_fp16_maxnm_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd Rd Rn o1 b__0) s" + unfolding decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd Rd Rn b__0 o1 b__1) s" + unfolding decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_reduce_fp16_max_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_reduce_fp16_max_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op) s" + unfolding execute_aarch64_instrs_vector_reduce_fp16_max_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd Rd Rn sz o1) s" + unfolding decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd Rd Rn b__0 o1) s" + unfolding decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0) s" + unfolding decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1) s" + unfolding decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_reduce_fp16_max_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_reduce_fp16_max_simd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op) s" + unfolding execute_aarch64_instrs_vector_reduce_fp16_max_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd Rd Rn o1 b__0) s" + unfolding decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd Rd Rn b__0 o1 b__1) s" + unfolding decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0) s" + unfolding decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1) s" + unfolding decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmin_float_aarch64_instrs_float_arithmetic_max_min[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmin_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0) s" + unfolding decode_fmin_float_aarch64_instrs_float_arithmetic_max_min_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0) s" + unfolding decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1) s" + unfolding decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminnm_float_aarch64_instrs_float_arithmetic_max_min[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminnm_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0) s" + unfolding decode_fminnm_float_aarch64_instrs_float_arithmetic_max_min_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd Rd Rn sz o1) s" + unfolding decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd Rd Rn b__0 o1) s" + unfolding decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0) s" + unfolding decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1) s" + unfolding decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd Rd Rn o1 b__0) s" + unfolding decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd Rd Rn b__0 o1 b__1) s" + unfolding decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd Rd Rn sz o1) s" + unfolding decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd Rd Rn b__0 o1) s" + unfolding decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0) s" + unfolding decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1) s" + unfolding decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd Rd Rn o1 b__0) s" + unfolding decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd Rd Rn b__0 o1 b__1) s" + unfolding decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "index__arg \ {0, 1, 2, 3, 4, 5, 6, 7}" and "int LENGTH('idxdsize) \ {64, 128}" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n sub_op) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd Rd Rn b__0 o2 Rm M L b__1) s" + unfolding decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd Rd Rn b__0 o2 Rm M L) s" + unfolding decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd Rd Rn b__0 o2 Rm M L b__1 b__2) s" + unfolding decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd Rd Rn b__0 o2 Rm M L b__1) s" + unfolding decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n sub_op) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused Rd Rn Rm a b__0) s" + unfolding decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused Rd Rn Rm b__0 op b__1) s" + unfolding decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd Rd Rn b__0 o2 Rm M L b__1) s" + unfolding decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd Rd Rn b__0 o2 Rm M L) s" + unfolding decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd Rd Rn b__0 o2 Rm M L b__1 b__2) s" + unfolding decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd Rd Rn b__0 o2 Rm M L b__1) s" + unfolding decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused Rd Rn Rm a b__0) s" + unfolding decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused Rd Rn Rm b__0 op b__1) s" + unfolding decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_fp16_movi[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ rd" and "rd \ 31" and "datasize \ {64, 128}" and "int (size imm) = datasize" + shows "traces_enabled (execute_aarch64_instrs_vector_fp16_movi datasize imm rd) s" + unfolding execute_aarch64_instrs_vector_fp16_movi_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmov_advsimd_aarch64_instrs_vector_fp16_movi[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmov_advsimd_aarch64_instrs_vector_fp16_movi Rd h g f e d c__arg b a b__0) s" + unfolding decode_fmov_advsimd_aarch64_instrs_vector_fp16_movi_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmov_advsimd_aarch64_instrs_vector_logical[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmov_advsimd_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0) s" + unfolding decode_fmov_advsimd_aarch64_instrs_vector_logical_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmov_float_aarch64_instrs_float_arithmetic_unary[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmov_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0) s" + unfolding decode_fmov_float_aarch64_instrs_float_arithmetic_unary_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmov_float_gen_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_fmov_float_gen_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_fmov_float_gen_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_move_fp_imm[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "datasize \ {16, 32, 64}" and "0 \ d" and "d \ 31" and "int (size imm) = datasize" + shows "traces_enabled (execute_aarch64_instrs_float_move_fp_imm d datasize imm) s" + unfolding execute_aarch64_instrs_float_move_fp_imm_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmov_float_imm_aarch64_instrs_float_move_fp_imm[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmov_float_imm_aarch64_instrs_float_move_fp_imm Rd imm8 b__0) s" + unfolding decode_fmov_float_imm_aarch64_instrs_float_move_fp_imm_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0) s" + unfolding decode_fmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "index__arg \ {0, 1, 2, 3, 4, 5, 6, 7}" and "int LENGTH('idxdsize) \ {64, 128}" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m mulx_op n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd Rd Rn b__0 Rm M L U b__1) s" + unfolding decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd Rd Rn b__0 Rm M L U) s" + unfolding decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd Rd Rn b__0 Rm M L b__1 U b__2) s" + unfolding decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd Rd Rn b__0 Rm M L b__1 U) s" + unfolding decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product Rd Rn Rm b__0) s" + unfolding decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_product[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_product Rd Rn Rm b__0 b__1) s" + unfolding decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_product_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_arithmetic_mul_product[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_float_arithmetic_mul_product d (datasize :: 'datasize::len itself) m n negated) s" + unfolding execute_aarch64_instrs_float_arithmetic_mul_product_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmul_float_aarch64_instrs_float_arithmetic_mul_product[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmul_float_aarch64_instrs_float_arithmetic_mul_product Rd Rn op Rm b__0) s" + unfolding decode_fmul_float_aarch64_instrs_float_arithmetic_mul_product_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd Rd Rn b__0 Rm M L U b__1) s" + unfolding decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd Rd Rn b__0 Rm M L U) s" + unfolding decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd Rd Rn b__0 Rm M L b__1 U b__2) s" + unfolding decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd Rd Rn b__0 Rm M L b__1 U) s" + unfolding decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_simd Rd Rn Rm b__0) s" + unfolding decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd Rd Rn Rm) s" + unfolding decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_simd Rd Rn Rm b__0 b__1) s" + unfolding decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_sisd Rd Rn Rm b__0) s" + unfolding decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float Rd Rn b__0 U b__1) s" + unfolding decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16 Rd Rn U b__0) s" + unfolding decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fneg_float_aarch64_instrs_float_arithmetic_unary[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fneg_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0) s" + unfolding decode_fneg_float_aarch64_instrs_float_arithmetic_unary_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fnmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fnmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0) s" + unfolding decode_fnmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fnmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fnmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0) s" + unfolding decode_fnmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fnmul_float_aarch64_instrs_float_arithmetic_mul_product[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fnmul_float_aarch64_instrs_float_arithmetic_mul_product Rd Rn op Rm b__0) s" + unfolding decode_fnmul_float_aarch64_instrs_float_arithmetic_mul_product_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_simd Rd Rn b__0 b__1) s" + unfolding decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_sisd Rd Rn b__0) s" + unfolding decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_simd Rd Rn b__0) s" + unfolding decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd Rd Rn) s" + unfolding decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_simd Rd Rn Rm b__0) s" + unfolding decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd Rd Rn Rm) s" + unfolding decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_simd Rd Rn Rm b__0 b__1) s" + unfolding decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_sisd Rd Rn Rm b__0) s" + unfolding decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "elements = 1" and "int LENGTH('datasize) \ {16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx Rd Rn b__0) s" + unfolding decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16 Rd Rn) s" + unfolding decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_fp16_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_fp16_round d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) exact n rounding) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0) s" + unfolding decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_float_arithmetic_round_frint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_float_arithmetic_round_frint d (datasize :: 'datasize::len itself) exact n rounding) s" + unfolding execute_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frinta_float_aarch64_instrs_float_arithmetic_round_frint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frinta_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M) s" + unfolding decode_frinta_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0) s" + unfolding decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frinti_float_aarch64_instrs_float_arithmetic_round_frint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frinti_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M) s" + unfolding decode_frinti_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0) s" + unfolding decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintm_float_aarch64_instrs_float_arithmetic_round_frint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintm_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M) s" + unfolding decode_frintm_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0) s" + unfolding decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintn_float_aarch64_instrs_float_arithmetic_round_frint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintn_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M) s" + unfolding decode_frintn_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0) s" + unfolding decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintp_float_aarch64_instrs_float_arithmetic_round_frint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintp_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M) s" + unfolding decode_frintp_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0) s" + unfolding decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintx_float_aarch64_instrs_float_arithmetic_round_frint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintx_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M) s" + unfolding decode_frintx_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1) s" + unfolding decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0) s" + unfolding decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frintz_float_aarch64_instrs_float_arithmetic_round_frint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frintz_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M) s" + unfolding decode_frintz_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_simd Rd Rn b__0 b__1) s" + unfolding decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_sisd Rd Rn b__0) s" + unfolding decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_simd Rd Rn b__0) s" + unfolding decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd Rd Rn) s" + unfolding decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_simd Rd Rn Rm b__0) s" + unfolding decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd Rd Rn Rm) s" + unfolding decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_simd Rd Rn Rm b__0 b__1) s" + unfolding decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_sisd Rd Rn Rm b__0) s" + unfolding decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt Rd Rn b__0 b__1) s" + unfolding decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16 Rd Rn b__0) s" + unfolding decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fsqrt_float_aarch64_instrs_float_arithmetic_unary[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fsqrt_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0) s" + unfolding decode_fsqrt_float_aarch64_instrs_float_arithmetic_unary_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd abs__arg d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd Rd Rn Rm U b__0) s" + unfolding decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd Rd Rn Rm b__0 U b__1) s" + unfolding decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_fsub_float_aarch64_instrs_float_arithmetic_add_sub[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_fsub_float_aarch64_instrs_float_arithmetic_add_sub Rd Rn op Rm b__0) s" + unfolding decode_fsub_float_aarch64_instrs_float_arithmetic_add_sub_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_hint_aarch64_instrs_system_hints[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_hint_aarch64_instrs_system_hints op2 CRm) s" + unfolding decode_hint_aarch64_instrs_system_hints_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_system_exceptions_debug_halt[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "system_reg_access s" + shows "traces_enabled (execute_aarch64_instrs_system_exceptions_debug_halt arg0) s" + unfolding execute_aarch64_instrs_system_exceptions_debug_halt_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_hlt_aarch64_instrs_system_exceptions_debug_halt[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_hlt_aarch64_instrs_system_exceptions_debug_halt imm16) s" + unfolding decode_hlt_aarch64_instrs_system_exceptions_debug_halt_def bind_assoc + by (traces_enabledI assms: assms elim: Run_or_not_HaltingAllowed_system_reg_access) + +lemma traces_enabled_execute_aarch64_instrs_system_exceptions_runtime_hvc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (execute_aarch64_instrs_system_exceptions_runtime_hvc imm) s" + unfolding execute_aarch64_instrs_system_exceptions_runtime_hvc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc imm16) s" + unfolding decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_transfer_vector_insert[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('idxdsize) \ {64, 128}" and "int LENGTH('esize) \ {8, 16, 32, 64, 128, 256}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_transfer_vector_insert d dst_index (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) n src_index) s" + unfolding execute_aarch64_instrs_vector_transfer_vector_insert_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ins_advsimd_elt_aarch64_instrs_vector_transfer_vector_insert[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ins_advsimd_elt_aarch64_instrs_vector_transfer_vector_insert Rd Rn imm4 imm5) s" + unfolding decode_ins_advsimd_elt_aarch64_instrs_vector_transfer_vector_insert_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_transfer_integer_insert[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64, 128, 256}" and "datasize = 128" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_transfer_integer_insert d datasize (esize :: 'esize::len itself) index__arg n) s" + unfolding execute_aarch64_instrs_vector_transfer_integer_insert_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ins_advsimd_gen_aarch64_instrs_vector_transfer_integer_insert[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ins_advsimd_gen_aarch64_instrs_vector_transfer_integer_insert Rd Rn b__0) s" + unfolding decode_ins_advsimd_gen_aarch64_instrs_vector_transfer_integer_insert_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "selem \ {1, 2, 3, 4}" and "rpt \ {1, 2, 3, 4}" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" + shows "traces_enabled (execute_aarch64_instrs_memory_vector_multiple_no_wb (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m memop n rpt selem t__arg wback) s" + unfolding execute_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "selem \ {1, 2, 3, 4}" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" + shows "traces_enabled (execute_aarch64_instrs_memory_vector_single_no_wb (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) index__arg m memop n replicate__arg selem t__arg wback) s" + unfolding execute_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_atomicops_ld (datasize :: 'datasize::len itself) ldacctype n op (regsize :: 'regsize::len itself) s__arg stacctype t__arg) s" + unfolding execute_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldadd_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldadd_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldadd_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaddb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaddb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldaddb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaddh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaddh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldaddh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_ordered_rcpc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_ordered_rcpc acctype (datasize :: 'datasize::len itself) n (regsize :: 'regsize::len itself) t__arg) s" + unfolding execute_aarch64_instrs_memory_ordered_rcpc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldapr_aarch64_instrs_memory_ordered_rcpc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldapr_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs b__0) s" + unfolding decode_ldapr_aarch64_instrs_memory_ordered_rcpc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaprb_aarch64_instrs_memory_ordered_rcpc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaprb_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs b__0) s" + unfolding decode_ldaprb_aarch64_instrs_memory_ordered_rcpc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaprh_aarch64_instrs_memory_ordered_rcpc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaprh_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs b__0) s" + unfolding decode_ldaprh_aarch64_instrs_memory_ordered_rcpc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_ordered acctype (datasize :: 'datasize::len itself) memop n (regsize :: 'regsize::len itself) t__arg) s" + unfolding execute_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldar_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldar_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldar_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldarb_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldarb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldarb_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldarh_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldarh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldarh_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_exclusive_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "elsize \ {32, 64}" and "l__197 \ {32, 64, 128}" + shows "traces_enabled (execute_aarch64_instrs_memory_exclusive_pair acctype l__197 elsize memop n pair (regsize :: 'regsize::len itself) s__arg t__arg t2) s" + unfolding execute_aarch64_instrs_memory_exclusive_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaxp_aarch64_instrs_memory_exclusive_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldaxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "elsize \ {8, 16, 32, 64}" and "l__532 \ {8, 16, 32, 64, 128}" + shows "traces_enabled (execute_aarch64_instrs_memory_exclusive_single acctype l__532 elsize memop n pair (regsize :: 'regsize::len itself) s__arg t__arg t2) s" + unfolding execute_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaxr_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldaxr_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaxrb_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldaxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaxrh_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldaxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldclr_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldclr_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldclr_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldclrb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldclrb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldclrb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldclrh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldclrh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldclrh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldeor_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldeor_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldeor_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldeorb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldeorb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldeorb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldeorh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldeorh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldeorh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldlar_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldlar_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldlar_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldlarb_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldlarb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldlarb_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldlarh_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldlarh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldlarh_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_pair_simdfp_no_alloc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "int LENGTH('datasize) \ {32, 64, 128, 256}" and "\postindex" and "\wback" + shows "traces_enabled (execute_aarch64_instrs_memory_pair_simdfp_no_alloc acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback) s" + unfolding execute_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_pair_general_no_alloc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "int LENGTH('datasize) \ {32, 64}" and "\wback" + shows "traces_enabled (execute_aarch64_instrs_memory_pair_general_no_alloc acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback) s" + unfolding execute_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_pair_simdfp_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "int LENGTH('datasize) \ {32, 64, 128, 256}" and "memop \ MemOp_PREFETCH" + shows "traces_enabled (execute_aarch64_instrs_memory_pair_simdfp_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback) s" + unfolding execute_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_pair_general_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "int LENGTH('datasize) \ {32, 64}" and "memop \ MemOp_PREFETCH" + shows "traces_enabled (execute_aarch64_instrs_memory_pair_general_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex is_signed t__arg t2 wback__arg) s" + unfolding execute_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldp_gen_aarch64_instrs_memory_pair_general_offset[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldp_gen_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldp_gen_aarch64_instrs_memory_pair_general_offset_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldpsw_aarch64_instrs_memory_pair_general_offset[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldpsw_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldpsw_aarch64_instrs_memory_pair_general_offset_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128, 256, 512, 1024}" and "memop \ MemOp_PREFETCH" + shows "traces_enabled (execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg wback) s" + unfolding execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "int LENGTH('regsize) \ {32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64}" and "memop \ MemOp_PREFETCH" + shows "traces_enabled (execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg) s" + unfolding execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_literal_simdfp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "l__44 \ {4, 8, 16}" + shows "traces_enabled (execute_aarch64_instrs_memory_literal_simdfp offset l__44 t__arg) s" + unfolding execute_aarch64_instrs_memory_literal_simdfp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp Rt imm19 opc) s" + unfolding decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_literal_general[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "l__200 \ {4, 8}" + shows "traces_enabled (execute_aarch64_instrs_memory_literal_general memop offset is_signed l__200 t__arg) s" + unfolding execute_aarch64_instrs_memory_literal_general_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_lit_gen_aarch64_instrs_memory_literal_general[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_lit_gen_aarch64_instrs_memory_literal_general Rt imm19 opc) s" + unfolding decode_ldr_lit_gen_aarch64_instrs_memory_literal_general_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_simdfp_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "shift \ {0, 1, 2, 3, 4, 5, 6, 7}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128, 256, 512, 1024}" and "memop \ MemOp_PREFETCH" + shows "traces_enabled (execute_aarch64_instrs_memory_single_simdfp_register acctype (datasize :: 'datasize::len itself) extend_type m memop n postindex shift t__arg wback) s" + unfolding execute_aarch64_instrs_memory_single_simdfp_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "shift \ {0, 1, 2, 3}" and "int LENGTH('regsize) \ {32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64}" and "\wback__arg" + shows "traces_enabled (execute_aarch64_instrs_memory_single_general_register acctype (datasize :: 'datasize::len itself) extend_type m memop n postindex (regsize :: 'regsize::len itself) shift is_signed t__arg wback__arg) s" + unfolding execute_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrb_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldrb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrh_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldrh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsb_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldrsb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsh_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldrsh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsw_lit_aarch64_instrs_memory_literal_general[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsw_lit_aarch64_instrs_memory_literal_general Rt imm19 opc) s" + unfolding decode_ldrsw_lit_aarch64_instrs_memory_literal_general_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsw_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsw_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldrsw_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldset_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldset_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldset_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsetb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsetb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsetb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldseth_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldseth_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldseth_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsmax_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsmax_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsmax_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsmin_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsmin_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsmin_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsminb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsminb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsminb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsminh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsminh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsminh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "int LENGTH('regsize) \ {32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64}" and "\wback__arg" + shows "traces_enabled (execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg) s" + unfolding execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldumax_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldumax_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldumax_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldumaxb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldumaxb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldumaxb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldumaxh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldumaxh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldumaxh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldumin_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldumin_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldumin_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_lduminb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_lduminb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_lduminb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_lduminh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_lduminh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_lduminh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128, 256, 512, 1024}" and "\wback" + shows "traces_enabled (execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg wback) s" + unfolding execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "int LENGTH('regsize) \ {32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64}" and "\wback__arg" + shows "traces_enabled (execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg) s" + unfolding execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldxp_aarch64_instrs_memory_exclusive_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldxr_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldxr_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldxrb_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldxrh_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_lslv_aarch64_instrs_integer_shift_variable[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_lslv_aarch64_instrs_integer_shift_variable Rd Rn op2 Rm b__0) s" + unfolding decode_lslv_aarch64_instrs_integer_shift_variable_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_lsrv_aarch64_instrs_integer_shift_variable[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_lsrv_aarch64_instrs_integer_shift_variable Rd Rn op2 Rm b__0) s" + unfolding decode_lsrv_aarch64_instrs_integer_shift_variable_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('destsize) \ {32, 64}" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" and "0 \ a" and "a \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub a d (datasize :: 'datasize::len itself) (destsize :: 'destsize::len itself) m n sub_op) s" + unfolding execute_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_madd_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_madd_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub Rd Rn Ra o0 Rm b__0) s" + unfolding decode_madd_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "index__arg \ {0, 1, 2, 3, 4, 5, 6, 7}" and "int LENGTH('idxdsize) \ {64, 128}" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n sub_op) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_mla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_mla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int Rd Rn b__0 o2 Rm M L b__1 b__2) s" + unfolding decode_mla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n sub_op) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_mla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_mla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum Rd Rn Rm b__0 U b__1) s" + unfolding decode_mla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_mls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_mls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int Rd Rn b__0 o2 Rm M L b__1 b__2) s" + unfolding decode_mls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_mls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_mls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum Rd Rn Rm b__0 U b__1) s" + unfolding decode_mls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_movi_advsimd_aarch64_instrs_vector_logical[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_movi_advsimd_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0) s" + unfolding decode_movi_advsimd_aarch64_instrs_vector_logical_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_ins_ext_insert_movewide[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ pos" and "pos \ 63" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_ins_ext_insert_movewide d (datasize :: 'datasize::len itself) imm opcode pos) s" + unfolding execute_aarch64_instrs_integer_ins_ext_insert_movewide_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_movk_aarch64_instrs_integer_ins_ext_insert_movewide[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_movk_aarch64_instrs_integer_ins_ext_insert_movewide Rd imm16 hw opc b__0) s" + unfolding decode_movk_aarch64_instrs_integer_ins_ext_insert_movewide_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_movn_aarch64_instrs_integer_ins_ext_insert_movewide[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_movn_aarch64_instrs_integer_ins_ext_insert_movewide Rd imm16 hw opc b__0) s" + unfolding decode_movn_aarch64_instrs_integer_ins_ext_insert_movewide_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_movz_aarch64_instrs_integer_ins_ext_insert_movewide[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_movz_aarch64_instrs_integer_ins_ext_insert_movewide Rd imm16 hw opc b__0) s" + unfolding decode_movz_aarch64_instrs_integer_ins_ext_insert_movewide_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_system_register_system[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "(\read \ sys_op0 = 3 \ sys_op1 \ {0, 4, 6} \ sys_op2 = 2 \ sys_crn = 12 \ sys_crm = 0) \ no_system_reg_access" + shows "traces_enabled (execute_aarch64_instrs_system_register_system read sys_crm sys_crn sys_op0 sys_op1 sys_op2 t) s" + unfolding execute_aarch64_instrs_system_register_system_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_mrs_aarch64_instrs_system_register_system[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "(L \ 1 \ uint o0 = 1 \ uint op1 \ {0, 4, 6} \ uint op2 = 2 \ uint CRn = 12 \ uint CRm = 0) \ no_system_reg_access" + shows "traces_enabled (decode_mrs_aarch64_instrs_system_register_system Rt op2 CRm CRn op1 o0 L) s" + unfolding decode_mrs_aarch64_instrs_system_register_system_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_system_register_cpsr[traces_enabledI]: + "traces_enabled (execute_aarch64_instrs_system_register_cpsr field operand) s" + by (cases field; simp; traces_enabledI) + +lemma traces_enabled_decode_msr_imm_aarch64_instrs_system_register_cpsr[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_msr_imm_aarch64_instrs_system_register_cpsr op2 CRm op1) s" + unfolding decode_msr_imm_aarch64_instrs_system_register_cpsr_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_msr_reg_aarch64_instrs_system_register_system[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "(L \ 1 \ uint o0 = 1 \ uint op1 \ {0, 4, 6} \ uint op2 = 2 \ uint CRn = 12 \ uint CRm = 0) \ no_system_reg_access" + shows "traces_enabled (decode_msr_reg_aarch64_instrs_system_register_system Rt op2 CRm CRn op1 o0 L) s" + unfolding decode_msr_reg_aarch64_instrs_system_register_system_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_msub_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_msub_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub Rd Rn Ra o0 Rm b__0) s" + unfolding decode_msub_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_int[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "index__arg \ {0, 1, 2, 3, 4, 5, 6, 7}" and "int LENGTH('idxdsize) \ {64, 128}" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_int d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_element_mul_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_mul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_int[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_mul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_int Rd Rn b__0 Rm M L b__1 b__2) s" + unfolding decode_mul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "l__55 \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product d (datasize :: 'datasize::len itself) elements l__55 m n poly) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_mul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_mul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product Rd Rn Rm b__0 U b__1) s" + unfolding decode_mul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_mvni_advsimd_aarch64_instrs_vector_logical[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_mvni_advsimd_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0) s" + unfolding decode_mvni_advsimd_aarch64_instrs_vector_logical_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd Rd Rn b__0 U b__1) s" + unfolding decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd Rd Rn b__0 U) s" + unfolding decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_nop_aarch64_instrs_system_hints[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_nop_aarch64_instrs_system_hints op2 CRm) s" + unfolding decode_nop_aarch64_instrs_system_hints_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_not[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "esize = 8" and "elements \ {8, 16}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_not d (datasize :: 'datasize::len itself) elements esize n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_not_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_not_advsimd_aarch64_instrs_vector_arithmetic_unary_not[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_not_advsimd_aarch64_instrs_vector_arithmetic_unary_not Rd Rn b__0) s" + unfolding decode_not_advsimd_aarch64_instrs_vector_arithmetic_unary_not_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_orn_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_orn_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0) s" + unfolding decode_orn_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_orn_log_shift_aarch64_instrs_integer_logical_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_orn_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0) s" + unfolding decode_orn_log_shift_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_orr_advsimd_imm_aarch64_instrs_vector_logical[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_orr_advsimd_imm_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0) s" + unfolding decode_orr_advsimd_imm_aarch64_instrs_vector_logical_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_orr_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_orr_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0) s" + unfolding decode_orr_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_orr_log_imm_aarch64_instrs_integer_logical_immediate[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_orr_log_imm_aarch64_instrs_integer_logical_immediate Rd Rn imms immr N opc b__0) s" + unfolding decode_orr_log_imm_aarch64_instrs_integer_logical_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_orr_log_shift_aarch64_instrs_integer_logical_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_orr_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0) s" + unfolding decode_orr_log_shift_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_pmul_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_pmul_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product Rd Rn Rm b__0 U b__1) s" + unfolding decode_pmul_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "l__379 \ {8, 16, 32, 64}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly d datasize elements l__379 m n part) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_pmull_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_pmull_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly Rd Rn Rm b__0 Q) s" + unfolding decode_pmull_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "int LENGTH('regsize) \ {32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64}" and "\wback__arg" + shows "traces_enabled (execute_aarch64_instrs_memory_single_general_immediate_unsigned acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg) s" + unfolding execute_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_prfm_lit_aarch64_instrs_memory_literal_general[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_prfm_lit_aarch64_instrs_memory_literal_general Rt imm19 opc) s" + unfolding decode_prfm_lit_aarch64_instrs_memory_literal_general_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_prfm_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_prfm_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_prfm_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_psb_aarch64_instrs_system_hints[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_psb_aarch64_instrs_system_hints op2 CRm) s" + unfolding decode_psb_aarch64_instrs_system_hints_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_raddhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_raddhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_raddhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha3_rax1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha3_rax1 d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha3_rax1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_rax1_advsimd_aarch64_instrs_vector_crypto_sha3_rax1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_rax1_advsimd_aarch64_instrs_vector_crypto_sha3_rax1 Rd Rn Rm) s" + unfolding decode_rax1_advsimd_aarch64_instrs_vector_crypto_sha3_rax1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_arithmetic_rbit[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_arithmetic_rbit d (datasize :: 'datasize::len itself) n) s" + unfolding execute_aarch64_instrs_integer_arithmetic_rbit_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_rbit_int_aarch64_instrs_integer_arithmetic_rbit[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_rbit_int_aarch64_instrs_integer_arithmetic_rbit Rd Rn b__0) s" + unfolding decode_rbit_int_aarch64_instrs_integer_arithmetic_rbit_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ret_aarch64_instrs_branch_unconditional_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ret_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z) s" + unfolding decode_ret_aarch64_instrs_branch_unconditional_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_reta_aarch64_instrs_branch_unconditional_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_reta_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z) s" + unfolding decode_reta_aarch64_instrs_branch_unconditional_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_rev[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_rev containers d (datasize :: 'datasize::len itself) elements_per_container (esize :: 'esize::len itself) n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_rev_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_rev16_advsimd_aarch64_instrs_vector_arithmetic_unary_rev[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_rev16_advsimd_aarch64_instrs_vector_arithmetic_unary_rev Rd Rn o0 b__0 U b__1) s" + unfolding decode_rev16_advsimd_aarch64_instrs_vector_arithmetic_unary_rev_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_arithmetic_rev[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" and "container_size \ {16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_integer_arithmetic_rev container_size d (datasize :: 'datasize::len itself) n) s" + unfolding execute_aarch64_instrs_integer_arithmetic_rev_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_rev16_int_aarch64_instrs_integer_arithmetic_rev[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_rev16_int_aarch64_instrs_integer_arithmetic_rev Rd Rn opc b__0) s" + unfolding decode_rev16_int_aarch64_instrs_integer_arithmetic_rev_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_rev32_advsimd_aarch64_instrs_vector_arithmetic_unary_rev[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_rev32_advsimd_aarch64_instrs_vector_arithmetic_unary_rev Rd Rn o0 b__0 U b__1) s" + unfolding decode_rev32_advsimd_aarch64_instrs_vector_arithmetic_unary_rev_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_rev32_int_aarch64_instrs_integer_arithmetic_rev[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_rev32_int_aarch64_instrs_integer_arithmetic_rev Rd Rn opc b__0) s" + unfolding decode_rev32_int_aarch64_instrs_integer_arithmetic_rev_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_rev64_advsimd_aarch64_instrs_vector_arithmetic_unary_rev[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_rev64_advsimd_aarch64_instrs_vector_arithmetic_unary_rev Rd Rn o0 b__0 U b__1) s" + unfolding decode_rev64_advsimd_aarch64_instrs_vector_arithmetic_unary_rev_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_rev_aarch64_instrs_integer_arithmetic_rev[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_rev_aarch64_instrs_integer_arithmetic_rev Rd Rn opc b__0) s" + unfolding decode_rev_aarch64_instrs_integer_arithmetic_rev_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_rorv_aarch64_instrs_integer_shift_variable[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_rorv_aarch64_instrs_integer_shift_variable Rd Rn op2 Rm b__0) s" + unfolding decode_rorv_aarch64_instrs_integer_shift_variable_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_shift_right_narrow_logical[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "l__473 \ {4, 8, 16, 32, 64}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_shift_right_narrow_logical d datasize elements l__473 n part round__arg shift) s" + unfolding execute_aarch64_instrs_vector_shift_right_narrow_logical_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_rshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_rshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical Rd Rn op immb b__0 Q) s" + unfolding decode_rshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_rsubhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_rsubhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_rsubhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_diff[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_diff accumulate d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_saba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_saba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1) s" + unfolding decode_saba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_disparate_diff[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "l__469 \ {8, 16, 32, 64}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_disparate_diff accumulate d datasize elements l__469 m n part is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q) s" + unfolding decode_sabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1) s" + unfolding decode_sabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q) s" + unfolding decode_sabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_add_pairwise[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "l__169 \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_add_pairwise acc d (datasize :: 'datasize::len itself) elements l__169 n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1) s" + unfolding decode_sadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "l__316 \ {8, 16, 32, 64}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long d datasize elements l__316 m n part sub_op is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_saddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_saddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_saddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_saddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_saddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1) s" + unfolding decode_saddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_reduce_add_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "l__159 \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_reduce_add_long d (datasize :: 'datasize::len itself) elements l__159 n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_reduce_add_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_saddlv_advsimd_aarch64_instrs_vector_reduce_add_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_saddlv_advsimd_aarch64_instrs_vector_reduce_add_long Rd Rn b__0 U b__1) s" + unfolding decode_saddlv_advsimd_aarch64_instrs_vector_reduce_add_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "l__478 \ {8, 16, 32, 64}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide d datasize elements l__478 m n part sub_op is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_saddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_saddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_saddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sbc_aarch64_instrs_integer_arithmetic_add_sub_carry[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sbc_aarch64_instrs_integer_arithmetic_add_sub_carry Rd Rn Rm S op b__0) s" + unfolding decode_sbc_aarch64_instrs_integer_arithmetic_add_sub_carry_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sbcs_aarch64_instrs_integer_arithmetic_add_sub_carry[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sbcs_aarch64_instrs_integer_arithmetic_add_sub_carry Rd Rn Rm S op b__0) s" + unfolding decode_sbcs_aarch64_instrs_integer_arithmetic_add_sub_carry_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sbfm_aarch64_instrs_integer_bitfield[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sbfm_aarch64_instrs_integer_bitfield Rd Rn imms immr N opc b__0) s" + unfolding decode_sbfm_aarch64_instrs_integer_bitfield_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_shift_conv_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_shift_conv_int_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) fracbits n rounding is_unsigned) s" + unfolding execute_aarch64_instrs_vector_shift_conv_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd Rd Rn immb b__0 U b__1) s" + unfolding decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd Rd Rn immb b__0 U) s" + unfolding decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {16, 32, 64}" and "int LENGTH('datasize) \ {16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd Rd Rn b__0 U b__1) s" + unfolding decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd Rd Rn b__0 U) s" + unfolding decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd Rd Rn U b__0) s" + unfolding decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd Rd Rn U) s" + unfolding decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_scvtf_float_fix_aarch64_instrs_float_convert_fix[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_scvtf_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1) s" + unfolding decode_scvtf_float_fix_aarch64_instrs_float_convert_fix_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_scvtf_float_int_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_scvtf_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_scvtf_float_int_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_arithmetic_div[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_arithmetic_div d (datasize :: 'datasize::len itself) m n is_unsigned) s" + unfolding execute_aarch64_instrs_integer_arithmetic_div_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sdiv_aarch64_instrs_integer_arithmetic_div[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sdiv_aarch64_instrs_integer_arithmetic_div Rd Rn o1 Rm b__0) s" + unfolding decode_sdiv_aarch64_instrs_integer_arithmetic_div_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_element_dotp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "index__arg \ {0, 1, 2, 3}" and "l__375 \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_element_dotp d (datasize :: 'datasize::len itself) elements l__375 index__arg m n is_signed) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_element_dotp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sdot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sdot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp Rd Rn H Rm M L b__0 U b__1) s" + unfolding decode_sdot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "l__165 \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp d (datasize :: 'datasize::len itself) elements l__165 m n is_signed) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sdot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sdot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp Rd Rn Rm b__0 U b__1) s" + unfolding decode_sdot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sev_aarch64_instrs_system_hints[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sev_aarch64_instrs_system_hints op2 CRm) s" + unfolding decode_sev_aarch64_instrs_system_hints_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sevl_aarch64_instrs_system_hints[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sevl_aarch64_instrs_system_hints op2 CRm) s" + unfolding decode_sevl_aarch64_instrs_system_hints_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha1c_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha1c_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose Rd Rn Rm) s" + unfolding decode_sha1c_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha2op_sha1_hash[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha2op_sha1_hash d n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha2op_sha1_hash_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha1h_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_hash[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha1h_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_hash Rd Rn) s" + unfolding decode_sha1h_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_hash_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha1m_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha1m_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority Rd Rn Rm) s" + unfolding decode_sha1m_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha1p_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha1p_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity Rd Rn Rm) s" + unfolding decode_sha1p_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha3op_sha1_sched0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha3op_sha1_sched0 d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha3op_sha1_sched0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha1su0_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_sched0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha1su0_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_sched0 Rd Rn Rm) s" + unfolding decode_sha1su0_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_sched0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha2op_sha1_sched1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha2op_sha1_sched1 d n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha2op_sha1_sched1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha1su1_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_sched1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha1su1_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_sched1 Rd Rn) s" + unfolding decode_sha1su1_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_sched1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha3op_sha256_hash[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha3op_sha256_hash d m n part1) s" + unfolding execute_aarch64_instrs_vector_crypto_sha3op_sha256_hash_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha256h2_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha256h2_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash Rd Rn P Rm) s" + unfolding decode_sha256h2_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha256h_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha256h_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash Rd Rn P Rm) s" + unfolding decode_sha256h_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha2op_sha256_sched0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha2op_sha256_sched0 d n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha2op_sha256_sched0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha256su0_advsimd_aarch64_instrs_vector_crypto_sha2op_sha256_sched0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha256su0_advsimd_aarch64_instrs_vector_crypto_sha2op_sha256_sched0 Rd Rn) s" + unfolding decode_sha256su0_advsimd_aarch64_instrs_vector_crypto_sha2op_sha256_sched0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha3op_sha256_sched1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha3op_sha256_sched1 d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha3op_sha256_sched1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha256su1_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_sched1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha256su1_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_sched1 Rd Rn Rm) s" + unfolding decode_sha256su1_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_sched1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha512_sha512h2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha512_sha512h2 d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha512_sha512h2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha512h2_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha512h2_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h2 Rd Rn Rm) s" + unfolding decode_sha512h2_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha512_sha512h[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha512_sha512h d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha512_sha512h_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha512h_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha512h_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h Rd Rn Rm) s" + unfolding decode_sha512h_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha512_sha512su0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha512_sha512su0 d n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha512_sha512su0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha512su0_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha512su0_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su0 Rd Rn) s" + unfolding decode_sha512su0_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha512_sha512su1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha512_sha512su1 d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha512_sha512su1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sha512su1_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sha512su1_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su1 Rd Rn Rm) s" + unfolding decode_sha512su1_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_shadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_shadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating Rd Rn Rm b__0 U b__1) s" + unfolding decode_shadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_shift_left_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_shift_left_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n shift) s" + unfolding execute_aarch64_instrs_vector_shift_left_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_shl_advsimd_aarch64_instrs_vector_shift_left_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_shl_advsimd_aarch64_instrs_vector_shift_left_simd Rd Rn immb b__0 b__1) s" + unfolding decode_shl_advsimd_aarch64_instrs_vector_shift_left_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_shl_advsimd_aarch64_instrs_vector_shift_left_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_shl_advsimd_aarch64_instrs_vector_shift_left_sisd Rd Rn immb immh) s" + unfolding decode_shl_advsimd_aarch64_instrs_vector_shift_left_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_shift[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "shift \ {8, 16, 32, 64}" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "l__49 \ {8, 16, 32, 64}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_shift d datasize elements l__49 n part shift is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_shift_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_shll_advsimd_aarch64_instrs_vector_arithmetic_unary_shift[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_shll_advsimd_aarch64_instrs_vector_arithmetic_unary_shift Rd Rn b__0 Q) s" + unfolding decode_shll_advsimd_aarch64_instrs_vector_arithmetic_unary_shift_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_shrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_shrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical Rd Rn op immb b__0 Q) s" + unfolding decode_shrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_shsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_shsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int Rd Rn Rm b__0 U b__1) s" + unfolding decode_shsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_shift_left_insert_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_shift_left_insert_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n shift) s" + unfolding execute_aarch64_instrs_vector_shift_left_insert_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_simd Rd Rn immb b__0 b__1) s" + unfolding decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_sisd Rd Rn immb immh) s" + unfolding decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sm3_sm3partw1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sm3_sm3partw1 d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sm3_sm3partw1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sm3partw1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sm3partw1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw1 Rd Rn Rm) s" + unfolding decode_sm3partw1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sm3_sm3partw2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sm3_sm3partw2 d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sm3_sm3partw2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sm3partw2_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw2[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sm3partw2_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw2 Rd Rn Rm) s" + unfolding decode_sm3partw2_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw2_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sm3_sm3ss1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" and "0 \ a" and "a \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sm3_sm3ss1 a d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sm3_sm3ss1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sm3ss1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3ss1[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sm3ss1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3ss1 Rd Rn Ra Rm) s" + unfolding decode_sm3ss1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3ss1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sm3_sm3tt1a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "i \ {0, 1, 2, 3}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sm3_sm3tt1a d i m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sm3_sm3tt1a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sm3tt1a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sm3tt1a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1a Rd Rn imm2 Rm) s" + unfolding decode_sm3tt1a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sm3_sm3tt1b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "i \ {0, 1, 2, 3}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sm3_sm3tt1b d i m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sm3_sm3tt1b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sm3tt1b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sm3tt1b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1b Rd Rn imm2 Rm) s" + unfolding decode_sm3tt1b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sm3_sm3tt2a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "i \ {0, 1, 2, 3}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sm3_sm3tt2a d i m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sm3_sm3tt2a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sm3tt2a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2a[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sm3tt2a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2a Rd Rn imm2 Rm) s" + unfolding decode_sm3tt2a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2a_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sm3_sm3tt2b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "i \ {0, 1, 2, 3}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sm3_sm3tt2b d i m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sm3_sm3tt2b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sm3tt2b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2b[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sm3tt2b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2b Rd Rn imm2 Rm) s" + unfolding decode_sm3tt2b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2b_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sm4_sm4enc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sm4_sm4enc d n) s" + unfolding execute_aarch64_instrs_vector_crypto_sm4_sm4enc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sm4e_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sm4e_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enc Rd Rn) s" + unfolding decode_sm4e_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sm4_sm4enckey[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sm4_sm4enckey d m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sm4_sm4enckey_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sm4ekey_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enckey[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sm4ekey_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enckey Rd Rn Rm) s" + unfolding decode_sm4ekey_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enckey_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_arithmetic_mul_widening_32_64[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "destsize = 64" and "datasize = 32" and "0 \ d" and "d \ 31" and "0 \ a" and "a \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_arithmetic_mul_widening_32_64 a d datasize destsize m n sub_op is_unsigned) s" + unfolding execute_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_smaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64 Rd Rn Ra o0 Rm U) s" + unfolding decode_smaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m minimum n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_smax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1) s" + unfolding decode_smax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "l__193 \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair d l__193 elements (esize :: 'esize::len itself) m minimum n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_smaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1) s" + unfolding decode_smaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_reduce_int_max[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_reduce_int_max d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) min__arg n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_reduce_int_max_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smaxv_advsimd_aarch64_instrs_vector_reduce_int_max[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_smaxv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1) s" + unfolding decode_smaxv_advsimd_aarch64_instrs_vector_reduce_int_max_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_system_exceptions_runtime_smc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (execute_aarch64_instrs_system_exceptions_runtime_smc imm) s" + unfolding execute_aarch64_instrs_system_exceptions_runtime_smc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smc_aarch64_instrs_system_exceptions_runtime_smc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_smc_aarch64_instrs_system_exceptions_runtime_smc imm16) s" + unfolding decode_smc_aarch64_instrs_system_exceptions_runtime_smc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_smin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1) s" + unfolding decode_smin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1) s" + unfolding decode_sminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sminv_advsimd_aarch64_instrs_vector_reduce_int_max[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sminv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1) s" + unfolding decode_sminv_advsimd_aarch64_instrs_vector_reduce_int_max_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "index__arg \ {0, 1, 2, 3, 4, 5, 6, 7}" and "int LENGTH('idxdsize) \ {64, 128}" and "l__185 \ {8, 16, 32, 64}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long d datasize elements l__185 (idxdsize :: 'idxdsize::len itself) index__arg m n part sub_op is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_smlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q) s" + unfolding decode_smlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "l__537 \ {8, 16, 32, 64}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum d datasize elements l__537 m n part sub_op is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_smlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_smlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_smlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q) s" + unfolding decode_smlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_smlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_smlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_transfer_integer_move_signed[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('idxdsize) \ {64, 128}" and "int LENGTH('esize) \ {8, 16, 32}" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_transfer_integer_move_signed d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg n) s" + unfolding execute_aarch64_instrs_vector_transfer_integer_move_signed_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smov_advsimd_aarch64_instrs_vector_transfer_integer_move_signed[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_smov_advsimd_aarch64_instrs_vector_transfer_integer_move_signed Rd Rn b__0 b__1) s" + unfolding decode_smov_advsimd_aarch64_instrs_vector_transfer_integer_move_signed_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_smsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64 Rd Rn Ra o0 Rm U) s" + unfolding decode_smsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi d datasize m n is_unsigned) s" + unfolding execute_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_smulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi Rd Rn Ra Rm U) s" + unfolding decode_smulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "index__arg \ {0, 1, 2, 3, 4, 5, 6, 7}" and "int LENGTH('idxdsize) \ {64, 128}" and "l__173 \ {8, 16, 32, 64}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_long d datasize elements l__173 (idxdsize :: 'idxdsize::len itself) index__arg m n part is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_element_mul_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_smull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long Rd Rn b__0 Rm M L b__1 U Q) s" + unfolding decode_smull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "l__189 \ {8, 16, 32, 64}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product d datasize elements l__189 m n part is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_smull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_smull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product Rd Rn Rm b__0 U Q) s" + unfolding decode_smull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n neg) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd Rd Rn b__0 U b__1) s" + unfolding decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd Rd Rn b__0 U) s" + unfolding decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd Rd Rn Rm b__0 U b__1) s" + unfolding decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd Rd Rn Rm b__0 U) s" + unfolding decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "index__arg \ {0, 1, 2, 3, 4, 5, 6, 7}" and "int LENGTH('idxdsize) \ {64, 128}" and "l__404 \ {8, 16, 32, 64}" and "l__403 \ {8, 16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd d l__403 elements l__404 (idxdsize :: 'idxdsize::len itself) index__arg m n part sub_op) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd Rd Rn b__0 o2 Rm M L b__1 Q) s" + unfolding decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd Rd Rn b__0 o2 Rm M L b__1) s" + unfolding decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "l__438 \ {8, 16, 32, 64}" and "l__437 \ {8, 16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd d l__437 elements l__438 m n part sub_op) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd Rd Rn o1 Rm b__0 Q) s" + unfolding decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd Rd Rn o1 Rm b__0) s" + unfolding decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd Rd Rn b__0 o2 Rm M L b__1 Q) s" + unfolding decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd Rd Rn b__0 o2 Rm M L b__1) s" + unfolding decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd Rd Rn o1 Rm b__0 Q) s" + unfolding decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd Rd Rn o1 Rm b__0) s" + unfolding decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "index__arg \ {0, 1, 2, 3, 4, 5, 6, 7}" and "int LENGTH('idxdsize) \ {64, 128}" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n round__arg) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd Rd Rn b__0 op Rm M L b__1 b__2) s" + unfolding decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd Rd Rn b__0 op Rm M L b__1) s" + unfolding decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n rounding) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd Rd Rn Rm b__0 U b__1) s" + unfolding decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd Rd Rn Rm b__0 U) s" + unfolding decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "index__arg \ {0, 1, 2, 3, 4, 5, 6, 7}" and "int LENGTH('idxdsize) \ {64, 128}" and "l__124 \ {8, 16, 32, 64}" and "l__123 \ {8, 16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd d l__123 elements l__124 (idxdsize :: 'idxdsize::len itself) index__arg m n part) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_simd Rd Rn b__0 Rm M L b__1 Q) s" + unfolding decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd Rd Rn b__0 Rm M L b__1) s" + unfolding decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "l__60 \ {8, 16, 32, 64}" and "l__59 \ {8, 16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd d l__59 elements l__60 m n part) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_simd Rd Rn Rm b__0 Q) s" + unfolding decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd Rd Rn Rm b__0) s" + unfolding decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd Rd Rn b__0 U b__1) s" + unfolding decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd Rd Rn b__0 U) s" + unfolding decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "index__arg \ {0, 1, 2, 3, 4, 5, 6, 7}" and "int LENGTH('idxdsize) \ {64, 128}" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n rounding sub_op) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd Rd Rn b__0 S Rm M L b__1 b__2) s" + unfolding decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd Rd Rn b__0 S Rm M L b__1) s" + unfolding decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n rounding sub_op) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd Rd Rn S Rm b__0 b__1) s" + unfolding decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd Rd Rn S Rm b__0) s" + unfolding decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd Rd Rn b__0 S Rm M L b__1 b__2) s" + unfolding decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd Rd Rn b__0 S Rm M L b__1) s" + unfolding decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd Rd Rn S Rm b__0 b__1) s" + unfolding decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd Rd Rn S Rm b__0) s" + unfolding decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd Rd Rn b__0 op Rm M L b__1 b__2) s" + unfolding decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd Rd Rn b__0 op Rm M L b__1) s" + unfolding decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd Rd Rn Rm b__0 U b__1) s" + unfolding decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd Rd Rn Rm b__0 U) s" + unfolding decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n rounding saturating is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1) s" + unfolding decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U) s" + unfolding decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "l__326 \ {4, 8, 16, 32, 64}" and "l__325 \ {4, 8, 16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_shift_right_narrow_uniform_sisd d l__325 elements l__326 n part round__arg shift is_unsigned) s" + unfolding execute_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q) s" + unfolding decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U) s" + unfolding decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "l__483 \ {4, 8, 16, 32, 64}" and "l__482 \ {4, 8, 16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd d l__482 elements l__483 n part round__arg shift) s" + unfolding execute_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd Rd Rn op immb b__0 Q) s" + unfolding decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd Rd Rn op immb b__0) s" + unfolding decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_shift_left_sat_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {4, 8, 16, 32, 64}" and "int LENGTH('datasize) \ {4, 8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_shift_left_sat_sisd d (datasize :: 'datasize::len itself) dst_unsigned elements (esize :: 'esize::len itself) n shift src_unsigned) s" + unfolding execute_aarch64_instrs_vector_shift_left_sat_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd Rd Rn op immb b__0 U b__1) s" + unfolding decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd Rd Rn op immb b__0 U) s" + unfolding decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1) s" + unfolding decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U) s" + unfolding decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_simd Rd Rn op immb b__0 U b__1) s" + unfolding decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_sisd Rd Rn op immb b__0 U) s" + unfolding decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q) s" + unfolding decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U) s" + unfolding decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd Rd Rn op immb b__0 Q) s" + unfolding decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd Rd Rn op immb b__0) s" + unfolding decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd Rd Rn Rm b__0 U b__1) s" + unfolding decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd Rd Rn Rm b__0 U) s" + unfolding decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "l__92 \ {8, 16, 32, 64}" and "l__91 \ {8, 16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd d l__91 elements l__92 n part is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd Rd Rn b__0 U Q) s" + unfolding decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd Rd Rn b__0 U) s" + unfolding decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "l__5 \ {8, 16, 32, 64}" and "l__4 \ {8, 16, 32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd d l__4 elements l__5 n part) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_simd Rd Rn b__0 Q) s" + unfolding decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd Rd Rn b__0) s" + unfolding decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_srhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_srhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding Rd Rn Rm b__0 U b__1) s" + unfolding decode_srhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_shift_right_insert_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_shift_right_insert_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n shift) s" + unfolding execute_aarch64_instrs_vector_shift_right_insert_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_simd Rd Rn immb b__0 b__1) s" + unfolding decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_sisd Rd Rn immb immh) s" + unfolding decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1) s" + unfolding decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U) s" + unfolding decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_shift_right_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_shift_right_sisd accumulate d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n round__arg shift is_unsigned) s" + unfolding execute_aarch64_instrs_vector_shift_right_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_srshr_advsimd_aarch64_instrs_vector_shift_right_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_srshr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1) s" + unfolding decode_srshr_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_srshr_advsimd_aarch64_instrs_vector_shift_right_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_srshr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U) s" + unfolding decode_srshr_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_srsra_advsimd_aarch64_instrs_vector_shift_right_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_srsra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1) s" + unfolding decode_srsra_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_srsra_advsimd_aarch64_instrs_vector_shift_right_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_srsra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U) s" + unfolding decode_srsra_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1) s" + unfolding decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U) s" + unfolding decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_shift_left_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "l__320 \ {4, 8, 16, 32, 64}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_shift_left_long d datasize elements l__320 n part shift is_unsigned) s" + unfolding execute_aarch64_instrs_vector_shift_left_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sshll_advsimd_aarch64_instrs_vector_shift_left_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sshll_advsimd_aarch64_instrs_vector_shift_left_long Rd Rn immb b__0 U Q) s" + unfolding decode_sshll_advsimd_aarch64_instrs_vector_shift_left_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sshr_advsimd_aarch64_instrs_vector_shift_right_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sshr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1) s" + unfolding decode_sshr_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sshr_advsimd_aarch64_instrs_vector_shift_right_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sshr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U) s" + unfolding decode_sshr_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ssra_advsimd_aarch64_instrs_vector_shift_right_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ssra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1) s" + unfolding decode_ssra_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ssra_advsimd_aarch64_instrs_vector_shift_right_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ssra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U) s" + unfolding decode_ssra_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ssubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ssubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_ssubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ssubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ssubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_ssubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_atomicops_st (datasize :: 'datasize::len itself) ldacctype n op s__arg stacctype) s" + unfolding execute_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stadd_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stadd_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stadd_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_staddb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_staddb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_staddb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_staddh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_staddh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_staddh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stclr_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stclr_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stclr_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stclrb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stclrb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stclrb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stclrh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stclrh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stclrh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_steor_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_steor_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_steor_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_steorb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_steorb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_steorb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_steorh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_steorh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_steorh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stllr_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stllr_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stllr_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stllrb_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stllrb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stllrb_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stllrh_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stllrh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stllrh_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlr_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlr_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlr_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlrb_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlrb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlrb_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlrh_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlrh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlrh_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlxp_aarch64_instrs_memory_exclusive_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlxr_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlxr_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlxrb_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlxrh_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stp_gen_aarch64_instrs_memory_pair_general_offset[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stp_gen_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stp_gen_aarch64_instrs_memory_pair_general_offset_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_reg_gen_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_reg_gen_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_str_reg_gen_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strb_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_strb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strh_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_strh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stset_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stset_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stset_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsetb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsetb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsetb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stseth_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stseth_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stseth_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsmax_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsmax_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsmax_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsmaxb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsmaxb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsmaxb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsmaxh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsmaxh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsmaxh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsmin_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsmin_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsmin_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsminb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsminb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsminb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsminh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsminh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsminh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stumax_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stumax_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stumax_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stumaxb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stumaxb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stumaxb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stumaxh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stumaxh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stumaxh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stumin_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stumin_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stumin_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stuminb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stuminb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stuminb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stuminh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stuminh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stuminh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stxp_aarch64_instrs_memory_exclusive_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stxr_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stxr_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stxrb_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stxrh_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sub_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sub_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg Rd Rn imm3 option_name Rm S op b__0) s" + unfolding decode_sub_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sub_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sub_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate Rd Rn imm12 sh S op b__0) s" + unfolding decode_sub_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sub_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sub_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg Rd Rn imm6 Rm shift S op b__0) s" + unfolding decode_sub_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd Rd Rn Rm b__0 U b__1) s" + unfolding decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd Rd Rn Rm b__0 U) s" + unfolding decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_subhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_subhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_subhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_subs_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_subs_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg Rd Rn imm3 option_name Rm S op b__0) s" + unfolding decode_subs_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_subs_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_subs_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate Rd Rn imm12 sh S op b__0) s" + unfolding decode_subs_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_subs_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_subs_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg Rd Rn imm6 Rm shift S op b__0) s" + unfolding decode_subs_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n is_unsigned) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd Rd Rn b__0 U b__1) s" + unfolding decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd Rd Rn b__0 U) s" + unfolding decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_system_exceptions_runtime_svc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (execute_aarch64_instrs_system_exceptions_runtime_svc imm) s" + unfolding execute_aarch64_instrs_system_exceptions_runtime_svc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_svc_aarch64_instrs_system_exceptions_runtime_svc[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_svc_aarch64_instrs_system_exceptions_runtime_svc imm16) s" + unfolding decode_svc_aarch64_instrs_system_exceptions_runtime_svc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_atomicops_swp[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_atomicops_swp (datasize :: 'datasize::len itself) ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg) s" + unfolding execute_aarch64_instrs_memory_atomicops_swp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_swp_aarch64_instrs_memory_atomicops_swp[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_swp_aarch64_instrs_memory_atomicops_swp Rt Rn Rs R A b__0) s" + unfolding decode_swp_aarch64_instrs_memory_atomicops_swp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_swpb_aarch64_instrs_memory_atomicops_swp[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_swpb_aarch64_instrs_memory_atomicops_swp Rt Rn Rs R A b__0) s" + unfolding decode_swpb_aarch64_instrs_memory_atomicops_swp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_swph_aarch64_instrs_memory_atomicops_swp[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_swph_aarch64_instrs_memory_atomicops_swp Rt Rn Rs R A b__0) s" + unfolding decode_swph_aarch64_instrs_memory_atomicops_swp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_system_sysops[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "sys_op2 \ {0, 1, 2, 3, 4, 5, 6, 7}" and "sys_op1 \ {0, 1, 2, 3, 4, 5, 6, 7}" and "sys_op0 = 1" and "0 \ sys_crn" and "sys_crn \ 15" and "0 \ sys_crm" and "sys_crm \ 15" + shows "traces_enabled (execute_aarch64_instrs_system_sysops has_result sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg) s" + unfolding execute_aarch64_instrs_system_sysops_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sys_aarch64_instrs_system_sysops[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sys_aarch64_instrs_system_sysops Rt op2 CRm CRn op1 L) s" + unfolding decode_sys_aarch64_instrs_system_sysops_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sysl_aarch64_instrs_system_sysops[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sysl_aarch64_instrs_system_sysops Rt op2 CRm CRn op1 L) s" + unfolding decode_sysl_aarch64_instrs_system_sysops_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_transfer_vector_table[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "l__181 \ {1, 2, 3, 4}" and "0 \ n__arg" and "n__arg \ 31" and "0 \ m" and "m \ 31" and "elements \ {8, 16}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_transfer_vector_table d (datasize :: 'datasize::len itself) elements is_tbl m n__arg l__181) s" + unfolding execute_aarch64_instrs_vector_transfer_vector_table_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_tbl_advsimd_aarch64_instrs_vector_transfer_vector_table[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_tbl_advsimd_aarch64_instrs_vector_transfer_vector_table Rd Rn op len Rm b__0) s" + unfolding decode_tbl_advsimd_aarch64_instrs_vector_transfer_vector_table_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_branch_conditional_test[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "int LENGTH('datasize) \ {32, 64}" and "0 \ bit_pos" and "bit_pos \ 63" + shows "traces_enabled (execute_aarch64_instrs_branch_conditional_test bit_pos bit_val (datasize :: 'datasize::len itself) offset t__arg) s" + unfolding execute_aarch64_instrs_branch_conditional_test_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_tbnz_aarch64_instrs_branch_conditional_test[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_tbnz_aarch64_instrs_branch_conditional_test Rt imm14 b40 op b__0) s" + unfolding decode_tbnz_aarch64_instrs_branch_conditional_test_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_tbx_advsimd_aarch64_instrs_vector_transfer_vector_table[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_tbx_advsimd_aarch64_instrs_vector_transfer_vector_table Rd Rn op len Rm b__0) s" + unfolding decode_tbx_advsimd_aarch64_instrs_vector_transfer_vector_table_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_tbz_aarch64_instrs_branch_conditional_test[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_tbz_aarch64_instrs_branch_conditional_test Rt imm14 b40 op b__0) s" + unfolding decode_tbz_aarch64_instrs_branch_conditional_test_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_transfer_vector_permute_transpose[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_transfer_vector_permute_transpose d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) m n pairs part) s" + unfolding execute_aarch64_instrs_vector_transfer_vector_permute_transpose_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_trn1_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_trn1_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose Rd Rn op Rm b__0 b__1) s" + unfolding decode_trn1_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_trn2_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_trn2_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose Rd Rn op Rm b__0 b__1) s" + unfolding decode_trn2_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uaba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uaba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1) s" + unfolding decode_uaba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q) s" + unfolding decode_uabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1) s" + unfolding decode_uabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q) s" + unfolding decode_uabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1) s" + unfolding decode_uadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uaddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uaddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_uaddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uaddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uaddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1) s" + unfolding decode_uaddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uaddlv_advsimd_aarch64_instrs_vector_reduce_add_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uaddlv_advsimd_aarch64_instrs_vector_reduce_add_long Rd Rn b__0 U b__1) s" + unfolding decode_uaddlv_advsimd_aarch64_instrs_vector_reduce_add_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uaddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uaddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_uaddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ubfm_aarch64_instrs_integer_bitfield[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ubfm_aarch64_instrs_integer_bitfield Rd Rn imms immr N opc b__0) s" + unfolding decode_ubfm_aarch64_instrs_integer_bitfield_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd Rd Rn immb b__0 U b__1) s" + unfolding decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd Rd Rn immb b__0 U) s" + unfolding decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd Rd Rn b__0 U b__1) s" + unfolding decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd Rd Rn b__0 U) s" + unfolding decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd Rd Rn U b__0) s" + unfolding decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd Rd Rn U) s" + unfolding decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ucvtf_float_fix_aarch64_instrs_float_convert_fix[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ucvtf_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1) s" + unfolding decode_ucvtf_float_fix_aarch64_instrs_float_convert_fix_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ucvtf_float_int_aarch64_instrs_float_convert_int[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ucvtf_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0) s" + unfolding decode_ucvtf_float_int_aarch64_instrs_float_convert_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_udiv_aarch64_instrs_integer_arithmetic_div[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_udiv_aarch64_instrs_integer_arithmetic_div Rd Rn o1 Rm b__0) s" + unfolding decode_udiv_aarch64_instrs_integer_arithmetic_div_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_udot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_udot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp Rd Rn H Rm M L b__0 U b__1) s" + unfolding decode_udot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_udot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_udot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp Rd Rn Rm b__0 U b__1) s" + unfolding decode_udot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating Rd Rn Rm b__0 U b__1) s" + unfolding decode_uhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uhsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uhsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int Rd Rn Rm b__0 U b__1) s" + unfolding decode_uhsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_umaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64 Rd Rn Ra o0 Rm U) s" + unfolding decode_umaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_umax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1) s" + unfolding decode_umax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_umaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1) s" + unfolding decode_umaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umaxv_advsimd_aarch64_instrs_vector_reduce_int_max[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_umaxv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1) s" + unfolding decode_umaxv_advsimd_aarch64_instrs_vector_reduce_int_max_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_umin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1) s" + unfolding decode_umin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1) s" + unfolding decode_uminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uminv_advsimd_aarch64_instrs_vector_reduce_int_max[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uminv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1) s" + unfolding decode_uminv_advsimd_aarch64_instrs_vector_reduce_int_max_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_umlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q) s" + unfolding decode_umlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_umlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_umlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_umlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q) s" + unfolding decode_umlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_umlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_umlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_transfer_integer_move_unsigned[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('idxdsize) \ {64, 128}" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {32, 64}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_transfer_integer_move_unsigned d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg n) s" + unfolding execute_aarch64_instrs_vector_transfer_integer_move_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umov_advsimd_aarch64_instrs_vector_transfer_integer_move_unsigned[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_umov_advsimd_aarch64_instrs_vector_transfer_integer_move_unsigned Rd Rn b__0 b__1) s" + unfolding decode_umov_advsimd_aarch64_instrs_vector_transfer_integer_move_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_umsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64 Rd Rn Ra o0 Rm U) s" + unfolding decode_umsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi[traces_enabledI]: + assumes "{''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_umulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi Rd Rn Ra Rm U) s" + unfolding decode_umulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_umull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long Rd Rn b__0 Rm M L b__1 U Q) s" + unfolding decode_umull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_umull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_umull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product Rd Rn Rm b__0 U Q) s" + unfolding decode_umull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd Rd Rn Rm b__0 U b__1) s" + unfolding decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd Rd Rn Rm b__0 U) s" + unfolding decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1) s" + unfolding decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U) s" + unfolding decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q) s" + unfolding decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U) s" + unfolding decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd Rd Rn op immb b__0 U b__1) s" + unfolding decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd Rd Rn op immb b__0 U) s" + unfolding decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1) s" + unfolding decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U) s" + unfolding decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q) s" + unfolding decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U) s" + unfolding decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd Rd Rn Rm b__0 U b__1) s" + unfolding decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd Rd Rn Rm b__0 U) s" + unfolding decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd Rd Rn b__0 U Q) s" + unfolding decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd Rd Rn b__0 U) s" + unfolding decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_special_recip_int[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_special_recip_int d (datasize :: 'datasize::len itself) elements n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_special_recip_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_urecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_int[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_urecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_int Rd Rn sz b__0) s" + unfolding decode_urecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_urhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_urhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding Rd Rn Rm b__0 U b__1) s" + unfolding decode_urhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1) s" + unfolding decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U) s" + unfolding decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_urshr_advsimd_aarch64_instrs_vector_shift_right_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_urshr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1) s" + unfolding decode_urshr_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_urshr_advsimd_aarch64_instrs_vector_shift_right_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_urshr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U) s" + unfolding decode_urshr_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int d (datasize :: 'datasize::len itself) elements n) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ursqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ursqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int Rd Rn sz b__0) s" + unfolding decode_ursqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ursra_advsimd_aarch64_instrs_vector_shift_right_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ursra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1) s" + unfolding decode_ursra_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ursra_advsimd_aarch64_instrs_vector_shift_right_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ursra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U) s" + unfolding decode_ursra_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1) s" + unfolding decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U) s" + unfolding decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ushll_advsimd_aarch64_instrs_vector_shift_left_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ushll_advsimd_aarch64_instrs_vector_shift_left_long Rd Rn immb b__0 U Q) s" + unfolding decode_ushll_advsimd_aarch64_instrs_vector_shift_left_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ushr_advsimd_aarch64_instrs_vector_shift_right_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ushr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1) s" + unfolding decode_ushr_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ushr_advsimd_aarch64_instrs_vector_shift_right_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ushr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U) s" + unfolding decode_ushr_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd Rd Rn b__0 U b__1) s" + unfolding decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd Rd Rn b__0 U) s" + unfolding decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_usra_advsimd_aarch64_instrs_vector_shift_right_simd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_usra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1) s" + unfolding decode_usra_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_usra_advsimd_aarch64_instrs_vector_shift_right_sisd[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_usra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U) s" + unfolding decode_usra_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_usubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_usubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_usubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_usubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_usubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q) s" + unfolding decode_usubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_transfer_vector_permute_unzip[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "l__195 \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_transfer_vector_permute_unzip d l__195 elements (esize :: 'esize::len itself) m n part) s" + unfolding execute_aarch64_instrs_vector_transfer_vector_permute_unzip_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uzp1_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uzp1_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip Rd Rn op Rm b__0 b__1) s" + unfolding decode_uzp1_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_uzp2_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_uzp2_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip Rd Rn op Rm b__0 b__1) s" + unfolding decode_uzp2_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_wfe_aarch64_instrs_system_hints[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_wfe_aarch64_instrs_system_hints op2 CRm) s" + unfolding decode_wfe_aarch64_instrs_system_hints_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_wfi_aarch64_instrs_system_hints[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_wfi_aarch64_instrs_system_hints op2 CRm) s" + unfolding decode_wfi_aarch64_instrs_system_hints_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_crypto_sha3_xar[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_crypto_sha3_xar d imm6 m n) s" + unfolding execute_aarch64_instrs_vector_crypto_sha3_xar_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_xar_advsimd_aarch64_instrs_vector_crypto_sha3_xar[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_xar_advsimd_aarch64_instrs_vector_crypto_sha3_xar Rd Rn imm6 Rm) s" + unfolding decode_xar_advsimd_aarch64_instrs_vector_crypto_sha3_xar_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_arithmetic_unary_extract_nosat[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "l__0 \ {8, 16, 32, 64}" and "datasize = 64" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_arithmetic_unary_extract_nosat d datasize elements l__0 n part) s" + unfolding execute_aarch64_instrs_vector_arithmetic_unary_extract_nosat_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_xtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_nosat[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_xtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_nosat Rd Rn b__0 Q) s" + unfolding decode_xtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_nosat_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_yield_aarch64_instrs_system_hints[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_yield_aarch64_instrs_system_hints op2 CRm) s" + unfolding decode_yield_aarch64_instrs_system_hints_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_vector_transfer_vector_permute_zip[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "part \ {0, 1}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" and "0 \ d" and "d \ 31" + shows "traces_enabled (execute_aarch64_instrs_vector_transfer_vector_permute_zip d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) m n pairs part) s" + unfolding execute_aarch64_instrs_vector_transfer_vector_permute_zip_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_zip1_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_zip1_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip Rd Rn op Rm b__0 b__1) s" + unfolding decode_zip1_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_zip2_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_zip2_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip Rd Rn op Rm b__0 b__1) s" + unfolding decode_zip2_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DecodeA64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "instr_exp_assms (DecodeA64 pc opcode)" and "no_system_reg_access" + shows "traces_enabled (DecodeA64 pc opcode) s" + using assms(2) + by (unfold DecodeA64_def, elim instr_exp_assms_traces_enabled_ifE instr_exp_assms_traces_enabled_letE) (solves \traces_enabledI assms: assms(1) intro: assms(3) simp: instr_exp_assms_def invocation_instr_exp_assms_write_ThisInstrAbstract_iff load_instr_exp_assms_write_ThisInstrAbstract_iff\)+ + +end + +end diff --git a/CHERI_Fetch_Properties.thy b/CHERI_Fetch_Properties.thy new file mode 100644 index 0000000..0b6ab0d --- /dev/null +++ b/CHERI_Fetch_Properties.thy @@ -0,0 +1,371 @@ +section \Generated instruction fetch proofs\ + +theory CHERI_Fetch_Properties +imports CHERI_Mem_Properties +begin + +context Morello_Fetch_Write_Cap_Automaton +begin + +lemma traces_enabled_write_regs[traces_enabledI]: + "\c. c \ derivable_caps s \ system_reg_access s \ traces_enabled (write_reg CDBGDTR_EL0_ref c) s" + "\c. c \ derivable_caps s \ system_reg_access s \ traces_enabled (write_reg CDLR_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg CID_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg DDC_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg DDC_EL1_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg DDC_EL2_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg DDC_EL3_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg ELR_EL1_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg ELR_EL2_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg ELR_EL3_ref c) s" + "\v. system_reg_access s \ traces_enabled (write_reg MAIR_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MAIR_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MAIR_EL3_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAM0_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAM3_EL3_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMHCR_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMIDR_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM0_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM1_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM2_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM3_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM4_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM5_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM6_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPM7_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAMVPMV_EL2_ref v) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg PCC_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg RDDC_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg RSP_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg RTPIDR_EL0_ref c) s" + "\v. system_reg_access s \ traces_enabled (write_reg SCR_EL3_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg SCTLR_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg SCTLR_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg SCTLR_EL3_ref v) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg SP_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg SP_EL1_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg SP_EL2_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg SP_EL3_ref c) s" + "\v. system_reg_access s \ traces_enabled (write_reg TCR_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg TCR_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg TCR_EL3_ref v) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg TPIDRRO_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg TPIDR_EL0_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg TPIDR_EL1_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg TPIDR_EL2_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg TPIDR_EL3_ref c) s" + "\v. system_reg_access s \ traces_enabled (write_reg TTBR0_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg TTBR0_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg TTBR0_EL3_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg TTBR1_EL1_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg TTBR1_EL2_ref v) s" + "\c. c \ derivable_caps s \ system_reg_access s \ traces_enabled (write_reg VBAR_EL1_ref c) s" + "\c. c \ derivable_caps s \ system_reg_access s \ traces_enabled (write_reg VBAR_EL2_ref c) s" + "\c. c \ derivable_caps s \ system_reg_access s \ traces_enabled (write_reg VBAR_EL3_ref c) s" + "\v. system_reg_access s \ traces_enabled (write_reg VTCR_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg VTTBR_EL2_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAM1_EL1_0_62_ref v) s" + "\v. system_reg_access s \ traces_enabled (write_reg MPAM2_EL2_0_62_ref v) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R00_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R01_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R02_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R03_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R04_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R05_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R06_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R07_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R08_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R09_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R10_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R11_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R12_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R13_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R14_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R15_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R16_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R17_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R18_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R19_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R20_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R21_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R22_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R23_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R24_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R25_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R26_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R27_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R28_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R29_ref c) s" + "\c. c \ derivable_caps s \ traces_enabled (write_reg R30_ref c) s" + by (intro traces_enabled_write_reg; auto simp: register_defs derivable_caps_def)+ + +lemma traces_enabled_read_regs[traces_enabledI]: + "system_reg_access s \ traces_enabled (read_reg CDBGDTR_EL0_ref) s" + "system_reg_access s \ traces_enabled (read_reg CDLR_EL0_ref) s" + "traces_enabled (read_reg CID_EL0_ref) s" + "traces_enabled (read_reg DDC_EL0_ref) s" + "traces_enabled (read_reg DDC_EL1_ref) s" + "traces_enabled (read_reg DDC_EL2_ref) s" + "traces_enabled (read_reg DDC_EL3_ref) s" + "traces_enabled (read_reg ELR_EL1_ref) s" + "traces_enabled (read_reg ELR_EL2_ref) s" + "traces_enabled (read_reg ELR_EL3_ref) s" + "traces_enabled (read_reg PCC_ref) s" + "traces_enabled (read_reg RDDC_EL0_ref) s" + "traces_enabled (read_reg RSP_EL0_ref) s" + "traces_enabled (read_reg RTPIDR_EL0_ref) s" + "traces_enabled (read_reg SP_EL0_ref) s" + "traces_enabled (read_reg SP_EL1_ref) s" + "traces_enabled (read_reg SP_EL2_ref) s" + "traces_enabled (read_reg SP_EL3_ref) s" + "traces_enabled (read_reg TPIDRRO_EL0_ref) s" + "traces_enabled (read_reg TPIDR_EL0_ref) s" + "traces_enabled (read_reg TPIDR_EL1_ref) s" + "traces_enabled (read_reg TPIDR_EL2_ref) s" + "traces_enabled (read_reg TPIDR_EL3_ref) s" + "system_reg_access s \ ex_traces \ traces_enabled (read_reg VBAR_EL1_ref) s" + "system_reg_access s \ ex_traces \ traces_enabled (read_reg VBAR_EL2_ref) s" + "system_reg_access s \ ex_traces \ traces_enabled (read_reg VBAR_EL3_ref) s" + "traces_enabled (read_reg R00_ref) s" + "traces_enabled (read_reg R01_ref) s" + "traces_enabled (read_reg R02_ref) s" + "traces_enabled (read_reg R03_ref) s" + "traces_enabled (read_reg R04_ref) s" + "traces_enabled (read_reg R05_ref) s" + "traces_enabled (read_reg R06_ref) s" + "traces_enabled (read_reg R07_ref) s" + "traces_enabled (read_reg R08_ref) s" + "traces_enabled (read_reg R09_ref) s" + "traces_enabled (read_reg R10_ref) s" + "traces_enabled (read_reg R11_ref) s" + "traces_enabled (read_reg R12_ref) s" + "traces_enabled (read_reg R13_ref) s" + "traces_enabled (read_reg R14_ref) s" + "traces_enabled (read_reg R15_ref) s" + "traces_enabled (read_reg R16_ref) s" + "traces_enabled (read_reg R17_ref) s" + "traces_enabled (read_reg R18_ref) s" + "traces_enabled (read_reg R19_ref) s" + "traces_enabled (read_reg R20_ref) s" + "traces_enabled (read_reg R21_ref) s" + "traces_enabled (read_reg R22_ref) s" + "traces_enabled (read_reg R23_ref) s" + "traces_enabled (read_reg R24_ref) s" + "traces_enabled (read_reg R25_ref) s" + "traces_enabled (read_reg R26_ref) s" + "traces_enabled (read_reg R27_ref) s" + "traces_enabled (read_reg R28_ref) s" + "traces_enabled (read_reg R29_ref) s" + "traces_enabled (read_reg R30_ref) s" + by (intro traces_enabled_read_reg; auto simp: register_defs)+ + + +lemmas non_cap_exp_traces_enabled[traces_enabledI] = non_cap_expI[THEN non_cap_exp_traces_enabledI] + + +lemma traces_enabled_BranchTo[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (BranchTo target branch_type) s" + unfolding BranchTo_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_BranchToCapability[traces_enabledI]: + assumes "target \ derivable_caps s" + shows "traces_enabled (BranchToCapability target branch_type) s" + unfolding BranchToCapability_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CELR_set[traces_enabledI]: + assumes "value_name \ derivable_caps s" + shows "traces_enabled (CELR_set el value_name) s" + unfolding CELR_set_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CELR_set__1[traces_enabledI]: + assumes "value_name \ derivable_caps s" + shows "traces_enabled (CELR_set__1 value_name) s" + unfolding CELR_set__1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVBAR_read[traces_enabledI]: + assumes "{''VBAR_EL1'', ''VBAR_EL2'', ''VBAR_EL3''} \ accessible_regs s \ ex_traces" + shows "traces_enabled (CVBAR_read regime) s" + unfolding CVBAR_read_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CVBAR_read__1[traces_enabledI]: + assumes "{''VBAR_EL1'', ''VBAR_EL2'', ''VBAR_EL3''} \ accessible_regs s \ ex_traces" + shows "traces_enabled (CVBAR_read__1 arg0) s" + unfolding CVBAR_read__1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ELR_set[traces_enabledI]: + "traces_enabled (ELR_set el value_name) s" + unfolding ELR_set_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_ELR_set__1[traces_enabledI]: + "traces_enabled (ELR_set__1 value_name) s" + unfolding ELR_set__1_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_PCC_read[traces_enabledI]: + "traces_enabled (PCC_read arg0) s" + unfolding PCC_read_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_IsInRestricted[traces_enabledI]: + "traces_enabled (IsInRestricted arg0) s" + unfolding IsInRestricted_def bind_assoc + by (traces_enabledI) + +lemma traces_enabled_VBAR_read[traces_enabledI]: + assumes "{''VBAR_EL1'', ''VBAR_EL2'', ''VBAR_EL3''} \ accessible_regs s \ ex_traces" + shows "traces_enabled (VBAR_read regime) s" + unfolding VBAR_read_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_VBAR_read__1[traces_enabledI]: + assumes "{''VBAR_EL1'', ''VBAR_EL2'', ''VBAR_EL3''} \ accessible_regs s \ ex_traces" + shows "traces_enabled (VBAR_read__1 arg0) s" + unfolding VBAR_read__1_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_TakeException[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_TakeException target_el exception preferred_exception_return vect_offset__arg) s" + by (rule AArch64_TakeException_raises_isa_ex[THEN exp_raises_ex_traces_enabled], unfold AArch64_TakeException_def bind_assoc, traces_enabledI assms: assms elim: CapSetValue_exception_target_enabled_branch_target) + +lemma traces_enabled_Halt[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "system_reg_access s" + shows "traces_enabled (Halt reason) s" + unfolding Halt_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_BreakpointException[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_BreakpointException fault) s" + unfolding AArch64_BreakpointException_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_DataAbort[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_DataAbort vaddress fault) s" + unfolding AArch64_DataAbort_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_InstructionAbort[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_InstructionAbort vaddress fault) s" + unfolding AArch64_InstructionAbort_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_WatchpointException[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_WatchpointException vaddress fault) s" + unfolding AArch64_WatchpointException_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_Abort[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_Abort vaddress fault) s" + unfolding AArch64_Abort_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CheckBreakpoint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckBreakpoint vaddress size__arg) s" + unfolding AArch64_CheckBreakpoint_def bind_assoc + by (traces_enabledI assms: assms elim: Run_and_HaltOnBreakpointOrWatchpoint_system_reg_access) + +lemma traces_enabled_AArch64_CheckWatchpoint[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckWatchpoint vaddress acctype iswrite size__arg) s" + unfolding AArch64_CheckWatchpoint_def bind_assoc + by (traces_enabledI assms: assms elim: Run_and_HaltOnBreakpointOrWatchpoint_system_reg_access) + +lemma traces_enabled_AArch64_CheckDebug[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckDebug vaddress acctype iswrite size__arg) s" + unfolding AArch64_CheckDebug_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_TranslateAddressWithTag[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_TranslateAddressWithTag vaddress acctype iswrite wasaligned size__arg iswritevalidcap) s" + unfolding AArch64_TranslateAddressWithTag_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_TranslateAddress[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_TranslateAddress vaddress acctype iswrite wasaligned size__arg) s" + unfolding AArch64_TranslateAddress_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_MemSingle_read[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_MemSingle_read address size__arg acctype wasaligned :: 'size_times_p8::len word M) s" + unfolding AArch64_MemSingle_read_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CheckCapability[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CheckCapability c__arg address size__arg requested_perms acctype) s" + unfolding CheckCapability_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CheckIllegalState[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckIllegalState arg0) s" + unfolding AArch64_CheckIllegalState_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_PCAlignmentFault[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_PCAlignmentFault arg0) s" + unfolding AArch64_PCAlignmentFault_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_CheckPCAlignment[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_CheckPCAlignment arg0) s" + unfolding AArch64_CheckPCAlignment_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_CheckPCCCapability[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (CheckPCCCapability arg0) s" + unfolding CheckPCCCapability_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_FetchNextInstr[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FetchNextInstr arg0) s" + unfolding FetchNextInstr_def bind_assoc + by (traces_enabledI assms: assms) + +end + +context Morello_Fetch_Mem_Automaton +begin + +lemmas non_cap_exp_traces_enabled[traces_enabledI] = non_cap_expI[THEN non_cap_exp_traces_enabledI] + +lemmas non_mem_exp_traces_enabled[traces_enabledI] = non_mem_expI[THEN non_mem_exp_traces_enabledI] + + +lemma traces_enabled_AArch64_MemSingle_read[traces_enabledI]: + assumes "translate_address (unat address) \ None \ load_enabled s acctype (unat address) size__arg False" + shows "traces_enabled (AArch64_MemSingle_read address size__arg acctype wasaligned :: 'size_times_p8::len word M) s" + unfolding AArch64_MemSingle_read_def bind_assoc + by (traces_enabledI assms: assms simp: exp_fails_if_then_else) + +lemma traces_enabled_FetchNextInstr[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (FetchNextInstr arg0) s" + unfolding FetchNextInstr_def CheckPCCCapability_def bind_assoc + by (traces_enabledI assms: assms elim: CheckCapability_load_enabled intro: derivable_or_invokedI1) + +end + +end diff --git a/CHERI_Gen_Lemmas.thy b/CHERI_Gen_Lemmas.thy new file mode 100644 index 0000000..787d233 --- /dev/null +++ b/CHERI_Gen_Lemmas.thy @@ -0,0 +1,21162 @@ +section \Generated helper lemmas\ + +theory CHERI_Gen_Lemmas +imports CHERI_Instantiation +begin + +declare register_defs[simp_rules_add subset_assms_simp] + +lemma exp_fails_ReservedEncoding[simp]: + "exp_fails (ReservedEncoding arg0)" + unfolding ReservedEncoding_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_EndOfInstruction[simp]: + "exp_fails (EndOfInstruction arg0)" + unfolding EndOfInstruction_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_Unreachable[simp]: + "exp_fails (Unreachable arg0)" + unfolding Unreachable_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_MaybeZeroRegisterUppers[simp]: + "exp_fails (AArch64_MaybeZeroRegisterUppers arg0)" + unfolding AArch64_MaybeZeroRegisterUppers_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_TakeException[simp]: + "exp_fails (AArch64_TakeException target_el exception preferred_exception_return vect_offset__arg)" + unfolding AArch64_TakeException_def bind_assoc + by (auto elim!: Run_bindE) + +lemma exp_fails_AArch64_SystemAccessTrap[simp]: + "exp_fails (AArch64_SystemAccessTrap target_el ec)" + unfolding AArch64_SystemAccessTrap_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_UndefinedFault[simp]: + "exp_fails (AArch64_UndefinedFault arg0)" + unfolding AArch64_UndefinedFault_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_UndefinedFault[simp]: + "exp_fails (UndefinedFault arg0)" + unfolding UndefinedFault_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_BreakpointException[simp]: + "exp_fails (AArch64_BreakpointException fault)" + unfolding AArch64_BreakpointException_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_DataAbort[simp]: + "exp_fails (AArch64_DataAbort vaddress fault)" + unfolding AArch64_DataAbort_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_InstructionAbort[simp]: + "exp_fails (AArch64_InstructionAbort vaddress fault)" + unfolding AArch64_InstructionAbort_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_WatchpointException[simp]: + "exp_fails (AArch64_WatchpointException vaddress fault)" + unfolding AArch64_WatchpointException_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_Abort[simp]: + "exp_fails (AArch64_Abort vaddress fault)" + unfolding AArch64_Abort_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_SysInstrWithResult[simp]: + "exp_fails (AArch64_SysInstrWithResult op0 op1 crn crm op2)" + unfolding AArch64_SysInstrWithResult_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_FPTrappedException[simp]: + "exp_fails (AArch64_FPTrappedException is_ase element accumulated_exceptions)" + unfolding AArch64_FPTrappedException_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_SPAlignmentFault[simp]: + "exp_fails (AArch64_SPAlignmentFault arg0)" + unfolding AArch64_SPAlignmentFault_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_CallSecureMonitor[simp]: + "exp_fails (AArch64_CallSecureMonitor immediate)" + unfolding AArch64_CallSecureMonitor_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_CallHypervisor[simp]: + "exp_fails (AArch64_CallHypervisor immediate)" + unfolding AArch64_CallHypervisor_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_CallSupervisor[simp]: + "exp_fails (AArch64_CallSupervisor immediate)" + unfolding AArch64_CallSupervisor_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_WFxTrap[simp]: + "exp_fails (AArch64_WFxTrap target_el is_wfe)" + unfolding AArch64_WFxTrap_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_AdvSIMDFPAccessTrap[simp]: + "exp_fails (AArch64_AdvSIMDFPAccessTrap target_el)" + unfolding AArch64_AdvSIMDFPAccessTrap_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_CapabilityAccessTrap[simp]: + "exp_fails (CapabilityAccessTrap target_el)" + unfolding CapabilityAccessTrap_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_TakePhysicalIRQException[simp]: + "exp_fails (AArch64_TakePhysicalIRQException arg0)" + unfolding AArch64_TakePhysicalIRQException_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_SoftwareBreakpoint[simp]: + "exp_fails (AArch64_SoftwareBreakpoint immediate)" + unfolding AArch64_SoftwareBreakpoint_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_AArch64_PCAlignmentFault[simp]: + "exp_fails (AArch64_PCAlignmentFault arg0)" + unfolding AArch64_PCAlignmentFault_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_execute_aarch64_instrs_system_exceptions_debug_breakpoint[simp]: + "exp_fails (execute_aarch64_instrs_system_exceptions_debug_breakpoint comment)" + unfolding execute_aarch64_instrs_system_exceptions_debug_breakpoint_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint[simp]: + "exp_fails (decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint imm16)" + unfolding decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_execute_aarch64_instrs_system_exceptions_runtime_hvc[simp]: + "exp_fails (execute_aarch64_instrs_system_exceptions_runtime_hvc imm)" + unfolding execute_aarch64_instrs_system_exceptions_runtime_hvc_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc[simp]: + "exp_fails (decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc imm16)" + unfolding decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_execute_aarch64_instrs_system_exceptions_runtime_smc[simp]: + "exp_fails (execute_aarch64_instrs_system_exceptions_runtime_smc imm)" + unfolding execute_aarch64_instrs_system_exceptions_runtime_smc_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_decode_smc_aarch64_instrs_system_exceptions_runtime_smc[simp]: + "exp_fails (decode_smc_aarch64_instrs_system_exceptions_runtime_smc imm16)" + unfolding decode_smc_aarch64_instrs_system_exceptions_runtime_smc_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_execute_aarch64_instrs_system_exceptions_runtime_svc[simp]: + "exp_fails (execute_aarch64_instrs_system_exceptions_runtime_svc imm)" + unfolding execute_aarch64_instrs_system_exceptions_runtime_svc_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + +lemma exp_fails_decode_svc_aarch64_instrs_system_exceptions_runtime_svc[simp]: + "exp_fails (decode_svc_aarch64_instrs_system_exceptions_runtime_svc imm16)" + unfolding decode_svc_aarch64_instrs_system_exceptions_runtime_svc_def bind_assoc + by (auto elim!: Run_bindE Run_ifE Run_letE) + + +lemma no_reg_writes_to_ReservedEncoding[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ReservedEncoding arg0)" + by (unfold ReservedEncoding_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_UNKNOWN_integer[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (UNKNOWN_integer arg0)" + by (unfold UNKNOWN_integer_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_UNKNOWN_boolean[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (UNKNOWN_boolean arg0)" + by (unfold UNKNOWN_boolean_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_GetVerbosity[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (GetVerbosity arg0)" + by (unfold GetVerbosity_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_EndOfInstruction[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (EndOfInstruction arg0)" + by (unfold EndOfInstruction_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IMPDEF_boolean_map[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IMPDEF_boolean_map x)" + by (unfold IMPDEF_boolean_map_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IMPDEF_boolean[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IMPDEF_boolean x)" + by (unfold IMPDEF_boolean_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IMPDEF_integer_map[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IMPDEF_integer_map x)" + by (unfold IMPDEF_integer_map_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IMPDEF_integer[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IMPDEF_integer x)" + by (unfold IMPDEF_integer_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_EL2Enabled[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (EL2Enabled arg0)" + by (unfold EL2Enabled_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_getISR[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (getISR arg0)" + by (unfold getISR_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ConditionHolds[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ConditionHolds cond)" + by (unfold ConditionHolds_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_Constraint[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_Constraint arg0)" + by (unfold undefined_Constraint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ConstrainUnpredictable[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ConstrainUnpredictable which)" + by (cases which; simp; no_reg_writes_toI) + +lemma no_reg_writes_to_ConstrainUnpredictableBool[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ConstrainUnpredictableBool which)" + by (unfold ConstrainUnpredictableBool_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_UsingAArch32[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (UsingAArch32 arg0)" + by (unfold UsingAArch32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch32_CurrentCond[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch32_CurrentCond arg0)" + by (unfold AArch32_CurrentCond_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ConditionSyndrome[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ConditionSyndrome arg0)" + by (unfold ConditionSyndrome_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_Exception[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_Exception arg0)" + by (unfold undefined_Exception_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_ExceptionRecord[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_ExceptionRecord arg0)" + by (unfold undefined_ExceptionRecord_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ExceptionSyndrome[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ExceptionSyndrome exceptype)" + by (unfold ExceptionSyndrome_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Unreachable[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (Unreachable arg0)" + by (unfold Unreachable_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ThisInstr[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ThisInstr arg0)" + by (unfold ThisInstr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_SystemAccessTrapSyndrome[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_SystemAccessTrapSyndrome instr__arg ec)" + by (unfold AArch64_SystemAccessTrapSyndrome_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELStateUsingAArch32K[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ELStateUsingAArch32K el secure)" + by (unfold ELStateUsingAArch32K_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELStateUsingAArch32[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ELStateUsingAArch32 el secure)" + by (unfold ELStateUsingAArch32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCR_GEN_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SCR_GEN_read arg0)" + by (unfold SCR_GEN_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsSecureBelowEL3[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsSecureBelowEL3 arg0)" + by (unfold IsSecureBelowEL3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELUsingAArch32[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ELUsingAArch32 el)" + by (unfold ELUsingAArch32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_R_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (R_read idx)" + by (unfold R_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_R_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (R_set idx c__arg)" + by (unfold R_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_ExceptionClass[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_ExceptionClass exceptype target_el)" + by (unfold AArch64_ExceptionClass_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELIsInHost[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ELIsInHost el)" + by (unfold ELIsInHost_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S1TranslationRegime[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (S1TranslationRegime el)" + by (unfold S1TranslationRegime_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S1TranslationRegime__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (S1TranslationRegime__1 arg0)" + by (unfold S1TranslationRegime__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ESR_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ESR_set regime value_name)" + by (unfold ESR_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ESR_set__1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ESR_set__1 value_name)" + by (unfold ESR_set__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FAR_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FAR_set regime value_name)" + by (unfold FAR_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_ReportException[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_ReportException exception target_el)" + by (unfold AArch64_ReportException_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AddrTop[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AddrTop address el)" + by (unfold AddrTop_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsInHost[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsInHost arg0)" + by (unfold IsInHost_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_BranchAddr[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_BranchAddr vaddress)" + by (unfold AArch64_BranchAddr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_BranchType[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_BranchType arg0)" + by (unfold undefined_BranchType_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapGetTop[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapGetTop c__arg)" + by (unfold CapGetTop_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapGetBounds[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapGetBounds c__arg)" + by (unfold CapGetBounds_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapBoundsEqual[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapBoundsEqual a b)" + by (unfold CapBoundsEqual_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapIsRepresentable[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapIsRepresentable c__arg address)" + by (unfold CapIsRepresentable_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapSetValue[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapSetValue c__arg v)" + by (unfold CapSetValue_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_BranchTo[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (BranchTo target branch_type)" + by (unfold BranchTo_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_BranchAddr[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (BranchAddr c__arg el)" + by (unfold BranchAddr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_BranchToCapability[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (BranchToCapability target branch_type)" + by (unfold BranchToCapability_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CCTLR_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CCTLR_read el)" + by (unfold CCTLR_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CCTLR_read__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CCTLR_read__1 arg0)" + by (unfold CCTLR_read__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CELR_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CELR_set el value_name)" + by (unfold CELR_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CELR_set__1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CELR_set__1 value_name)" + by (unfold CELR_set__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVBAR_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CVBAR_read regime)" + by (unfold CVBAR_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVBAR_read__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CVBAR_read__1 arg0)" + by (unfold CVBAR_read__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELR_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ELR_set el value_name)" + by (unfold ELR_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELR_set__1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ELR_set__1 value_name)" + by (unfold ELR_set__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveSSBSExt[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveSSBSExt arg0)" + by (unfold HaveSSBSExt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_GetPSRFromPSTATE[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (GetPSRFromPSTATE arg0)" + by (unfold GetPSRFromPSTATE_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveRASExt[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveRASExt arg0)" + by (unfold HaveRASExt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveIESB[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveIESB arg0)" + by (unfold HaveIESB_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsAccessToCapabilitiesDisabledAtEL3[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsAccessToCapabilitiesDisabledAtEL3 arg0)" + by (unfold IsAccessToCapabilitiesDisabledAtEL3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsSecure[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsSecure arg0)" + by (unfold IsSecure_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsAccessToCapabilitiesDisabledAtEL2[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsAccessToCapabilitiesDisabledAtEL2 arg0)" + by (unfold IsAccessToCapabilitiesDisabledAtEL2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsAccessToCapabilitiesDisabledAtEL1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsAccessToCapabilitiesDisabledAtEL1 arg0)" + by (unfold IsAccessToCapabilitiesDisabledAtEL1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsAccessToCapabilitiesDisabledAtEL0[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsAccessToCapabilitiesDisabledAtEL0 arg0)" + by (unfold IsAccessToCapabilitiesDisabledAtEL0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsAccessToCapabilitiesEnabledAtEL[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsAccessToCapabilitiesEnabledAtEL el)" + by (unfold IsAccessToCapabilitiesEnabledAtEL_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Halted[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (Halted arg0)" + by (unfold Halted_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PCC_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (PCC_read arg0)" + by (unfold PCC_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsInRestricted[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsInRestricted arg0)" + by (unfold IsInRestricted_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCTLR_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SCTLR_read regime)" + by (unfold SCTLR_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCTLR_read__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SCTLR_read__1 arg0)" + by (unfold SCTLR_read__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SPSR_set value_name)" + by (unfold SPSR_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VBAR_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (VBAR_read regime)" + by (unfold VBAR_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VBAR_read__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (VBAR_read__1 arg0)" + by (unfold VBAR_read__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_MaybeZeroRegisterUppers[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_MaybeZeroRegisterUppers arg0)" + by (unfold AArch64_MaybeZeroRegisterUppers_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_TakeException[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_TakeException target_el exception preferred_exception_return vect_offset__arg)" + by (unfold AArch64_TakeException_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ThisInstrAddr[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ThisInstrAddr N)" + by (unfold ThisInstrAddr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_SystemAccessTrap[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_SystemAccessTrap target_el ec)" + by (unfold AArch64_SystemAccessTrap_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapIsSystemAccessEnabled[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapIsSystemAccessEnabled arg0)" + by (unfold CapIsSystemAccessEnabled_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TargetELForCapabilityExceptions[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (TargetELForCapabilityExceptions arg0)" + by (unfold TargetELForCapabilityExceptions_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ACTLR_EL1_SysRegRead_56bd4d0367c16236[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ACTLR_EL1_SysRegRead_56bd4d0367c16236 el op0 op1 CRn op2 CRm)" + by (unfold ACTLR_EL1_SysRegRead_56bd4d0367c16236_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ACTLR_EL2_SysRegRead_ff23cef1b670b9c7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ACTLR_EL2_SysRegRead_ff23cef1b670b9c7 el op0 op1 CRn op2 CRm)" + by (unfold ACTLR_EL2_SysRegRead_ff23cef1b670b9c7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ACTLR_EL3_SysRegRead_397e6c0342e2936b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ACTLR_EL3_SysRegRead_397e6c0342e2936b el op0 op1 CRn op2 CRm)" + by (unfold ACTLR_EL3_SysRegRead_397e6c0342e2936b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR0_EL12_SysRegRead_2488de32a3f38621[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR0_EL12_SysRegRead_2488de32a3f38621 el op0 op1 CRn op2 CRm)" + by (unfold AFSR0_EL12_SysRegRead_2488de32a3f38621_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR0_EL1_SysRegRead_80a4a0472e0b9142[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR0_EL1_SysRegRead_80a4a0472e0b9142 el op0 op1 CRn op2 CRm)" + by (unfold AFSR0_EL1_SysRegRead_80a4a0472e0b9142_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR0_EL2_SysRegRead_07613e9c4b98061a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR0_EL2_SysRegRead_07613e9c4b98061a el op0 op1 CRn op2 CRm)" + by (unfold AFSR0_EL2_SysRegRead_07613e9c4b98061a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR0_EL3_SysRegRead_d2e69d7912ca200c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR0_EL3_SysRegRead_d2e69d7912ca200c el op0 op1 CRn op2 CRm)" + by (unfold AFSR0_EL3_SysRegRead_d2e69d7912ca200c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR1_EL12_SysRegRead_39bb62021df07ecc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR1_EL12_SysRegRead_39bb62021df07ecc el op0 op1 CRn op2 CRm)" + by (unfold AFSR1_EL12_SysRegRead_39bb62021df07ecc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR1_EL1_SysRegRead_495927b72173c55f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR1_EL1_SysRegRead_495927b72173c55f el op0 op1 CRn op2 CRm)" + by (unfold AFSR1_EL1_SysRegRead_495927b72173c55f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR1_EL2_SysRegRead_f7cb9a59387f268f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR1_EL2_SysRegRead_f7cb9a59387f268f el op0 op1 CRn op2 CRm)" + by (unfold AFSR1_EL2_SysRegRead_f7cb9a59387f268f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR1_EL3_SysRegRead_a2ad736ad599f2b2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR1_EL3_SysRegRead_a2ad736ad599f2b2 el op0 op1 CRn op2 CRm)" + by (unfold AFSR1_EL3_SysRegRead_a2ad736ad599f2b2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AIDR_EL1_SysRegRead_74ea31b1dc6f5c6f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AIDR_EL1_SysRegRead_74ea31b1dc6f5c6f el op0 op1 CRn op2 CRm)" + by (unfold AIDR_EL1_SysRegRead_74ea31b1dc6f5c6f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AMAIR_EL12_SysRegRead_87964a33cc1ad0ef[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AMAIR_EL12_SysRegRead_87964a33cc1ad0ef el op0 op1 CRn op2 CRm)" + by (unfold AMAIR_EL12_SysRegRead_87964a33cc1ad0ef_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AMAIR_EL1_SysRegRead_82d01d3808e04ca3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AMAIR_EL1_SysRegRead_82d01d3808e04ca3 el op0 op1 CRn op2 CRm)" + by (unfold AMAIR_EL1_SysRegRead_82d01d3808e04ca3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AMAIR_EL2_SysRegRead_3c316bb11b239640[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AMAIR_EL2_SysRegRead_3c316bb11b239640 el op0 op1 CRn op2 CRm)" + by (unfold AMAIR_EL2_SysRegRead_3c316bb11b239640_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AMAIR_EL3_SysRegRead_b1547f511477c529[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AMAIR_EL3_SysRegRead_b1547f511477c529 el op0 op1 CRn op2 CRm)" + by (unfold AMAIR_EL3_SysRegRead_b1547f511477c529_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CCSIDR_EL1_SysRegRead_210f94b423761d0b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CCSIDR_EL1_SysRegRead_210f94b423761d0b el op0 op1 CRn op2 CRm)" + by (unfold CCSIDR_EL1_SysRegRead_210f94b423761d0b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CCTLR_EL0_SysRegRead_3baa7e22d96a4ce4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CCTLR_EL0_SysRegRead_3baa7e22d96a4ce4 el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL0_SysRegRead_3baa7e22d96a4ce4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CCTLR_EL12_SysRegRead_e8b17aabd47dc7a1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CCTLR_EL12_SysRegRead_e8b17aabd47dc7a1 el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL12_SysRegRead_e8b17aabd47dc7a1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CCTLR_EL1_SysRegRead_de402a061eecb9b9[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CCTLR_EL1_SysRegRead_de402a061eecb9b9 el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL1_SysRegRead_de402a061eecb9b9_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CCTLR_EL2_SysRegRead_fca4364f27bb9f9b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CCTLR_EL2_SysRegRead_fca4364f27bb9f9b el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL2_SysRegRead_fca4364f27bb9f9b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CCTLR_EL3_SysRegRead_9121a22ebc361586[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CCTLR_EL3_SysRegRead_9121a22ebc361586 el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL3_SysRegRead_9121a22ebc361586_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CHCR_EL2_SysRegRead_7d3c39a46321f1a2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CHCR_EL2_SysRegRead_7d3c39a46321f1a2 el op0 op1 CRn op2 CRm)" + by (unfold CHCR_EL2_SysRegRead_7d3c39a46321f1a2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CLIDR_EL1_SysRegRead_b403ddc99e97c3a8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CLIDR_EL1_SysRegRead_b403ddc99e97c3a8 el op0 op1 CRn op2 CRm)" + by (unfold CLIDR_EL1_SysRegRead_b403ddc99e97c3a8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTFRQ_EL0_SysRegRead_891ca00adf0c3783[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTFRQ_EL0_SysRegRead_891ca00adf0c3783 el op0 op1 CRn op2 CRm)" + by (unfold CNTFRQ_EL0_SysRegRead_891ca00adf0c3783_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHCTL_EL2_SysRegRead_5f510d633361c720[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHCTL_EL2_SysRegRead_5f510d633361c720 el op0 op1 CRn op2 CRm)" + by (unfold CNTHCTL_EL2_SysRegRead_5f510d633361c720_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHP_CTL_EL2_SysRegRead_7103e47839f2c66b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHP_CTL_EL2_SysRegRead_7103e47839f2c66b el op0 op1 CRn op2 CRm)" + by (unfold CNTHP_CTL_EL2_SysRegRead_7103e47839f2c66b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHP_CVAL_EL2_SysRegRead_e25a0257128c640b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHP_CVAL_EL2_SysRegRead_e25a0257128c640b el op0 op1 CRn op2 CRm)" + by (unfold CNTHP_CVAL_EL2_SysRegRead_e25a0257128c640b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHP_TVAL_EL2_SysRegRead_d110a1f1616c9f8f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHP_TVAL_EL2_SysRegRead_d110a1f1616c9f8f el op0 op1 CRn op2 CRm)" + by (unfold CNTHP_TVAL_EL2_SysRegRead_d110a1f1616c9f8f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHV_CTL_EL2_SysRegRead_bc429f3d6b52b800[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHV_CTL_EL2_SysRegRead_bc429f3d6b52b800 el op0 op1 CRn op2 CRm)" + by (unfold CNTHV_CTL_EL2_SysRegRead_bc429f3d6b52b800_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHV_CVAL_EL2_SysRegRead_2c78392b89702ca9[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHV_CVAL_EL2_SysRegRead_2c78392b89702ca9 el op0 op1 CRn op2 CRm)" + by (unfold CNTHV_CVAL_EL2_SysRegRead_2c78392b89702ca9_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHV_TVAL_EL2_SysRegRead_2464c0e91db55a22[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHV_TVAL_EL2_SysRegRead_2464c0e91db55a22 el op0 op1 CRn op2 CRm)" + by (unfold CNTHV_TVAL_EL2_SysRegRead_2464c0e91db55a22_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTKCTL_EL12_SysRegRead_c23def3111264258[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTKCTL_EL12_SysRegRead_c23def3111264258 el op0 op1 CRn op2 CRm)" + by (unfold CNTKCTL_EL12_SysRegRead_c23def3111264258_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTKCTL_EL1_SysRegRead_6a6cc900bc3c37df[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTKCTL_EL1_SysRegRead_6a6cc900bc3c37df el op0 op1 CRn op2 CRm)" + by (unfold CNTKCTL_EL1_SysRegRead_6a6cc900bc3c37df_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTPCT_EL0_SysRegRead_579be4c9ef4e6824[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTPCT_EL0_SysRegRead_579be4c9ef4e6824 el op0 op1 CRn op2 CRm)" + by (unfold CNTPCT_EL0_SysRegRead_579be4c9ef4e6824_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTPS_CTL_EL1_SysRegRead_e3bc6e5891147388[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTPS_CTL_EL1_SysRegRead_e3bc6e5891147388 el op0 op1 CRn op2 CRm)" + by (unfold CNTPS_CTL_EL1_SysRegRead_e3bc6e5891147388_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTPS_CVAL_EL1_SysRegRead_3e364bd573c45cae[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTPS_CVAL_EL1_SysRegRead_3e364bd573c45cae el op0 op1 CRn op2 CRm)" + by (unfold CNTPS_CVAL_EL1_SysRegRead_3e364bd573c45cae_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTPS_TVAL_EL1_SysRegRead_0784a7de0899eff0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTPS_TVAL_EL1_SysRegRead_0784a7de0899eff0 el op0 op1 CRn op2 CRm)" + by (unfold CNTPS_TVAL_EL1_SysRegRead_0784a7de0899eff0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTP_CTL_EL02_SysRegRead_9d9930274ff7fc36[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTP_CTL_EL02_SysRegRead_9d9930274ff7fc36 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_CTL_EL02_SysRegRead_9d9930274ff7fc36_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTP_CTL_EL0_SysRegRead_47237e002d686ac6[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTP_CTL_EL0_SysRegRead_47237e002d686ac6 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_CTL_EL0_SysRegRead_47237e002d686ac6_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTP_CVAL_EL02_SysRegRead_8377305437cbebb4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTP_CVAL_EL02_SysRegRead_8377305437cbebb4 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_CVAL_EL02_SysRegRead_8377305437cbebb4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTP_CVAL_EL0_SysRegRead_4db28ae745612584[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTP_CVAL_EL0_SysRegRead_4db28ae745612584 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_CVAL_EL0_SysRegRead_4db28ae745612584_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTP_TVAL_EL02_SysRegRead_6539005e4eb68283[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTP_TVAL_EL02_SysRegRead_6539005e4eb68283 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_TVAL_EL02_SysRegRead_6539005e4eb68283_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTP_TVAL_EL0_SysRegRead_54cebb7fbc71b9db[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTP_TVAL_EL0_SysRegRead_54cebb7fbc71b9db el op0 op1 CRn op2 CRm)" + by (unfold CNTP_TVAL_EL0_SysRegRead_54cebb7fbc71b9db_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTVCT_EL0_SysRegRead_cd7c8aebed2715e6[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTVCT_EL0_SysRegRead_cd7c8aebed2715e6 el op0 op1 CRn op2 CRm)" + by (unfold CNTVCT_EL0_SysRegRead_cd7c8aebed2715e6_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTVOFF_EL2_SysRegRead_5ca7336b54f14c06[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTVOFF_EL2_SysRegRead_5ca7336b54f14c06 el op0 op1 CRn op2 CRm)" + by (unfold CNTVOFF_EL2_SysRegRead_5ca7336b54f14c06_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTV_CTL_EL02_SysRegRead_4188a8e2bc5c07aa[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTV_CTL_EL02_SysRegRead_4188a8e2bc5c07aa el op0 op1 CRn op2 CRm)" + by (unfold CNTV_CTL_EL02_SysRegRead_4188a8e2bc5c07aa_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTV_CTL_EL0_SysRegRead_bcb2d1b80bdb9c23[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTV_CTL_EL0_SysRegRead_bcb2d1b80bdb9c23 el op0 op1 CRn op2 CRm)" + by (unfold CNTV_CTL_EL0_SysRegRead_bcb2d1b80bdb9c23_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTV_CVAL_EL02_SysRegRead_abd2b9f314cb85b2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTV_CVAL_EL02_SysRegRead_abd2b9f314cb85b2 el op0 op1 CRn op2 CRm)" + by (unfold CNTV_CVAL_EL02_SysRegRead_abd2b9f314cb85b2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTV_CVAL_EL0_SysRegRead_54d5eb0bec99456f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTV_CVAL_EL0_SysRegRead_54d5eb0bec99456f el op0 op1 CRn op2 CRm)" + by (unfold CNTV_CVAL_EL0_SysRegRead_54d5eb0bec99456f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTV_TVAL_EL02_SysRegRead_f904ccdf39aea128[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTV_TVAL_EL02_SysRegRead_f904ccdf39aea128 el op0 op1 CRn op2 CRm)" + by (unfold CNTV_TVAL_EL02_SysRegRead_f904ccdf39aea128_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTV_TVAL_EL0_SysRegRead_919e73a694090e48[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTV_TVAL_EL0_SysRegRead_919e73a694090e48 el op0 op1 CRn op2 CRm)" + by (unfold CNTV_TVAL_EL0_SysRegRead_919e73a694090e48_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CONTEXTIDR_EL12_SysRegRead_2aa676fc0cfd631b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CONTEXTIDR_EL12_SysRegRead_2aa676fc0cfd631b el op0 op1 CRn op2 CRm)" + by (unfold CONTEXTIDR_EL12_SysRegRead_2aa676fc0cfd631b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CONTEXTIDR_EL1_SysRegRead_fa54232c55ea14e3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CONTEXTIDR_EL1_SysRegRead_fa54232c55ea14e3 el op0 op1 CRn op2 CRm)" + by (unfold CONTEXTIDR_EL1_SysRegRead_fa54232c55ea14e3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CONTEXTIDR_EL2_SysRegRead_f7bf9114ce3113a6[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CONTEXTIDR_EL2_SysRegRead_f7bf9114ce3113a6 el op0 op1 CRn op2 CRm)" + by (unfold CONTEXTIDR_EL2_SysRegRead_f7bf9114ce3113a6_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CPACR_EL12_SysRegRead_0f7867518c4e8e99[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CPACR_EL12_SysRegRead_0f7867518c4e8e99 el op0 op1 CRn op2 CRm)" + by (unfold CPACR_EL12_SysRegRead_0f7867518c4e8e99_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CPACR_EL1_SysRegRead_63b8f196f3ebba22[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CPACR_EL1_SysRegRead_63b8f196f3ebba22 el op0 op1 CRn op2 CRm)" + by (unfold CPACR_EL1_SysRegRead_63b8f196f3ebba22_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CPTR_EL2_SysRegRead_d80843789adc6a43[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CPTR_EL2_SysRegRead_d80843789adc6a43 el op0 op1 CRn op2 CRm)" + by (unfold CPTR_EL2_SysRegRead_d80843789adc6a43_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CPTR_EL3_SysRegRead_33cb1e5ec3c99661[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CPTR_EL3_SysRegRead_33cb1e5ec3c99661 el op0 op1 CRn op2 CRm)" + by (unfold CPTR_EL3_SysRegRead_33cb1e5ec3c99661_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CSCR_EL3_SysRegRead_3c6b19768f9cd209[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CSCR_EL3_SysRegRead_3c6b19768f9cd209 el op0 op1 CRn op2 CRm)" + by (unfold CSCR_EL3_SysRegRead_3c6b19768f9cd209_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CSSELR_EL1_SysRegRead_102b4cddc07c9121[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CSSELR_EL1_SysRegRead_102b4cddc07c9121 el op0 op1 CRn op2 CRm)" + by (unfold CSSELR_EL1_SysRegRead_102b4cddc07c9121_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CTR_EL0_SysRegRead_54ef8c769c3c6bba[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CTR_EL0_SysRegRead_54ef8c769c3c6bba el op0 op1 CRn op2 CRm)" + by (unfold CTR_EL0_SysRegRead_54ef8c769c3c6bba_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CurrentEL_SysRegRead_ac5b30a86a6a5003[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CurrentEL_SysRegRead_ac5b30a86a6a5003 el op0 op1 CRn op2 CRm)" + by (unfold CurrentEL_SysRegRead_ac5b30a86a6a5003_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DACR32_EL2_SysRegRead_9571e2946627a596[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DACR32_EL2_SysRegRead_9571e2946627a596 el op0 op1 CRn op2 CRm)" + by (unfold DACR32_EL2_SysRegRead_9571e2946627a596_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DAIF_SysRegRead_198f3b46fcf6c8f0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DAIF_SysRegRead_198f3b46fcf6c8f0 el op0 op1 CRn op2 CRm)" + by (unfold DAIF_SysRegRead_198f3b46fcf6c8f0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGAUTHSTATUS_EL1_SysRegRead_6ade6e7a5265bcb7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGAUTHSTATUS_EL1_SysRegRead_6ade6e7a5265bcb7 el op0 op1 CRn op2 CRm)" + by (unfold DBGAUTHSTATUS_EL1_SysRegRead_6ade6e7a5265bcb7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ExternalInvasiveDebugEnabled[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ExternalInvasiveDebugEnabled arg0)" + by (unfold ExternalInvasiveDebugEnabled_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ExternalSecureInvasiveDebugEnabled[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ExternalSecureInvasiveDebugEnabled arg0)" + by (unfold ExternalSecureInvasiveDebugEnabled_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_UpdateEDSCRFields[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (UpdateEDSCRFields arg0)" + by (unfold UpdateEDSCRFields_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Halt[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Halt reason)" + by (unfold Halt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DoubleLockStatus[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DoubleLockStatus arg0)" + by (unfold DoubleLockStatus_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaltingAllowed[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaltingAllowed arg0)" + by (unfold HaltingAllowed_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGBCR_EL1_SysRegRead_2d021994672d40d3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGBCR_EL1_SysRegRead_2d021994672d40d3 el op0 op1 CRn op2 CRm)" + by (unfold DBGBCR_EL1_SysRegRead_2d021994672d40d3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGBVR_EL1_SysRegRead_dc4a8f61b400622f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGBVR_EL1_SysRegRead_dc4a8f61b400622f el op0 op1 CRn op2 CRm)" + by (unfold DBGBVR_EL1_SysRegRead_dc4a8f61b400622f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGCLAIMCLR_EL1_SysRegRead_72ae03c1d5f667da[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGCLAIMCLR_EL1_SysRegRead_72ae03c1d5f667da el op0 op1 CRn op2 CRm)" + by (unfold DBGCLAIMCLR_EL1_SysRegRead_72ae03c1d5f667da_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGCLAIMSET_EL1_SysRegRead_8557cf3b6272a9e8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGCLAIMSET_EL1_SysRegRead_8557cf3b6272a9e8 el op0 op1 CRn op2 CRm)" + by (unfold DBGCLAIMSET_EL1_SysRegRead_8557cf3b6272a9e8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGDTRRX_EL0_SysRegRead_e7b48d8296f3b86b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGDTRRX_EL0_SysRegRead_e7b48d8296f3b86b el op0 op1 CRn op2 CRm)" + by (unfold DBGDTRRX_EL0_SysRegRead_e7b48d8296f3b86b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGDTR_EL0_read__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DBGDTR_EL0_read__1 arg0)" + by (unfold DBGDTR_EL0_read__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGDTR_EL0_SysRegRead_537a006eb82c59aa[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGDTR_EL0_SysRegRead_537a006eb82c59aa el op0 op1 CRn op2 CRm)" + by (unfold DBGDTR_EL0_SysRegRead_537a006eb82c59aa_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGPRCR_EL1_SysRegRead_6b19d62af9619a21[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGPRCR_EL1_SysRegRead_6b19d62af9619a21 el op0 op1 CRn op2 CRm)" + by (unfold DBGPRCR_EL1_SysRegRead_6b19d62af9619a21_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGVCR32_EL2_SysRegRead_7986b2bdf8df010d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGVCR32_EL2_SysRegRead_7986b2bdf8df010d el op0 op1 CRn op2 CRm)" + by (unfold DBGVCR32_EL2_SysRegRead_7986b2bdf8df010d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGWCR_EL1_SysRegRead_03139d052b544b2f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGWCR_EL1_SysRegRead_03139d052b544b2f el op0 op1 CRn op2 CRm)" + by (unfold DBGWCR_EL1_SysRegRead_03139d052b544b2f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGWVR_EL1_SysRegRead_029de1005ef34888[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGWVR_EL1_SysRegRead_029de1005ef34888 el op0 op1 CRn op2 CRm)" + by (unfold DBGWVR_EL1_SysRegRead_029de1005ef34888_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DCZID_EL0_SysRegRead_dedd61ba7cee2913[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DCZID_EL0_SysRegRead_dedd61ba7cee2913 el op0 op1 CRn op2 CRm)" + by (unfold DCZID_EL0_SysRegRead_dedd61ba7cee2913_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DISR_EL1_SysRegRead_d06ce25101dac895[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DISR_EL1_SysRegRead_d06ce25101dac895 el op0 op1 CRn op2 CRm)" + by (unfold DISR_EL1_SysRegRead_d06ce25101dac895_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DLR_EL0_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DLR_EL0_read arg0)" + by (unfold DLR_EL0_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DLR_EL0_SysRegRead_75b9821e3e84ec13[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DLR_EL0_SysRegRead_75b9821e3e84ec13 el op0 op1 CRn op2 CRm)" + by (unfold DLR_EL0_SysRegRead_75b9821e3e84ec13_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DSPSR_EL0_SysRegRead_888dc1fa37424d3d[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DSPSR_EL0_SysRegRead_888dc1fa37424d3d el op0 op1 CRn op2 CRm)" + by (unfold DSPSR_EL0_SysRegRead_888dc1fa37424d3d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELR_EL12_SysRegRead_e8215c0ae79859bb[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ELR_EL12_SysRegRead_e8215c0ae79859bb el op0 op1 CRn op2 CRm)" + by (unfold ELR_EL12_SysRegRead_e8215c0ae79859bb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELR_EL1_SysRegRead_0d3f1ad1483e96c2[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ELR_EL1_SysRegRead_0d3f1ad1483e96c2 el op0 op1 CRn op2 CRm)" + by (unfold ELR_EL1_SysRegRead_0d3f1ad1483e96c2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELR_EL2_SysRegRead_00b4dd4251404d91[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ELR_EL2_SysRegRead_00b4dd4251404d91 el op0 op1 CRn op2 CRm)" + by (unfold ELR_EL2_SysRegRead_00b4dd4251404d91_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELR_EL3_SysRegRead_a7a7cd4e7e805396[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ELR_EL3_SysRegRead_a7a7cd4e7e805396 el op0 op1 CRn op2 CRm)" + by (unfold ELR_EL3_SysRegRead_a7a7cd4e7e805396_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERRIDR_EL1_SysRegRead_41b56b8d34e51109[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERRIDR_EL1_SysRegRead_41b56b8d34e51109 el op0 op1 CRn op2 CRm)" + by (unfold ERRIDR_EL1_SysRegRead_41b56b8d34e51109_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERRSELR_EL1_SysRegRead_1bcf942400e8d57f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERRSELR_EL1_SysRegRead_1bcf942400e8d57f el op0 op1 CRn op2 CRm)" + by (unfold ERRSELR_EL1_SysRegRead_1bcf942400e8d57f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERXADDR_EL1_SysRegRead_7dea05bca757fc1d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERXADDR_EL1_SysRegRead_7dea05bca757fc1d el op0 op1 CRn op2 CRm)" + by (unfold ERXADDR_EL1_SysRegRead_7dea05bca757fc1d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERXCTLR_EL1_SysRegRead_e46ed88d092db048[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERXCTLR_EL1_SysRegRead_e46ed88d092db048 el op0 op1 CRn op2 CRm)" + by (unfold ERXCTLR_EL1_SysRegRead_e46ed88d092db048_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERXFR_EL1_SysRegRead_ed2a3c237ae67a43[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERXFR_EL1_SysRegRead_ed2a3c237ae67a43 el op0 op1 CRn op2 CRm)" + by (unfold ERXFR_EL1_SysRegRead_ed2a3c237ae67a43_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERXMISC0_EL1_SysRegRead_a71a4de5f2444f19[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERXMISC0_EL1_SysRegRead_a71a4de5f2444f19 el op0 op1 CRn op2 CRm)" + by (unfold ERXMISC0_EL1_SysRegRead_a71a4de5f2444f19_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERXMISC1_EL1_SysRegRead_bda613f8058b1fd8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERXMISC1_EL1_SysRegRead_bda613f8058b1fd8 el op0 op1 CRn op2 CRm)" + by (unfold ERXMISC1_EL1_SysRegRead_bda613f8058b1fd8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERXSTATUS_EL1_SysRegRead_0ab2cfe6937b8b64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERXSTATUS_EL1_SysRegRead_0ab2cfe6937b8b64 el op0 op1 CRn op2 CRm)" + by (unfold ERXSTATUS_EL1_SysRegRead_0ab2cfe6937b8b64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ESR_EL12_SysRegRead_207d3805d256851a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ESR_EL12_SysRegRead_207d3805d256851a el op0 op1 CRn op2 CRm)" + by (unfold ESR_EL12_SysRegRead_207d3805d256851a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ESR_EL1_SysRegRead_4894753806397624[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ESR_EL1_SysRegRead_4894753806397624 el op0 op1 CRn op2 CRm)" + by (unfold ESR_EL1_SysRegRead_4894753806397624_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ESR_EL2_SysRegRead_e0558cb255261414[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ESR_EL2_SysRegRead_e0558cb255261414 el op0 op1 CRn op2 CRm)" + by (unfold ESR_EL2_SysRegRead_e0558cb255261414_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ESR_EL3_SysRegRead_e0eabec0b099e366[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ESR_EL3_SysRegRead_e0eabec0b099e366 el op0 op1 CRn op2 CRm)" + by (unfold ESR_EL3_SysRegRead_e0eabec0b099e366_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FAR_EL12_SysRegRead_061fecffb03f9fc5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FAR_EL12_SysRegRead_061fecffb03f9fc5 el op0 op1 CRn op2 CRm)" + by (unfold FAR_EL12_SysRegRead_061fecffb03f9fc5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FAR_EL1_SysRegRead_136ac0cc65bd5f9d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FAR_EL1_SysRegRead_136ac0cc65bd5f9d el op0 op1 CRn op2 CRm)" + by (unfold FAR_EL1_SysRegRead_136ac0cc65bd5f9d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FAR_EL2_SysRegRead_d686d0a5577f0aae[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FAR_EL2_SysRegRead_d686d0a5577f0aae el op0 op1 CRn op2 CRm)" + by (unfold FAR_EL2_SysRegRead_d686d0a5577f0aae_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FAR_EL3_SysRegRead_d63ec2764f8ffe40[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FAR_EL3_SysRegRead_d63ec2764f8ffe40 el op0 op1 CRn op2 CRm)" + by (unfold FAR_EL3_SysRegRead_d63ec2764f8ffe40_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPCR_SysRegRead_4176e216195c5686[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPCR_SysRegRead_4176e216195c5686 el op0 op1 CRn op2 CRm)" + by (unfold FPCR_SysRegRead_4176e216195c5686_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPEXC32_EL2_SysRegRead_7ee503337da57806[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPEXC32_EL2_SysRegRead_7ee503337da57806 el op0 op1 CRn op2 CRm)" + by (unfold FPEXC32_EL2_SysRegRead_7ee503337da57806_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPSR_SysRegRead_c1fde5c387acaca1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPSR_SysRegRead_c1fde5c387acaca1 el op0 op1 CRn op2 CRm)" + by (unfold FPSR_SysRegRead_c1fde5c387acaca1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HACR_EL2_SysRegRead_07bc3864e8ed8264[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (HACR_EL2_SysRegRead_07bc3864e8ed8264 el op0 op1 CRn op2 CRm)" + by (unfold HACR_EL2_SysRegRead_07bc3864e8ed8264_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HCR_EL2_SysRegRead_f76ecfdc85c5ff7c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (HCR_EL2_SysRegRead_f76ecfdc85c5ff7c el op0 op1 CRn op2 CRm)" + by (unfold HCR_EL2_SysRegRead_f76ecfdc85c5ff7c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HPFAR_EL2_SysRegRead_4c322cee424dff18[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (HPFAR_EL2_SysRegRead_4c322cee424dff18 el op0 op1 CRn op2 CRm)" + by (unfold HPFAR_EL2_SysRegRead_4c322cee424dff18_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HSTR_EL2_SysRegRead_680380b9028cf399[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (HSTR_EL2_SysRegRead_680380b9028cf399 el op0 op1 CRn op2 CRm)" + by (unfold HSTR_EL2_SysRegRead_680380b9028cf399_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_SRE_EL1_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ICC_SRE_EL1_read arg0)" + by (unfold ICC_SRE_EL1_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_AP0R_EL1_SysRegRead_cac9b22dc3786a15[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_AP0R_EL1_SysRegRead_cac9b22dc3786a15 el op0 op1 CRn op2 CRm)" + by (unfold ICC_AP0R_EL1_SysRegRead_cac9b22dc3786a15_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_AP1R_EL1_SysRegRead_4127418c67790ba3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_AP1R_EL1_SysRegRead_4127418c67790ba3 el op0 op1 CRn op2 CRm)" + by (unfold ICC_AP1R_EL1_SysRegRead_4127418c67790ba3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_BPR0_EL1_SysRegRead_6ada10a9051248c2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_BPR0_EL1_SysRegRead_6ada10a9051248c2 el op0 op1 CRn op2 CRm)" + by (unfold ICC_BPR0_EL1_SysRegRead_6ada10a9051248c2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_BPR1_EL1_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ICC_BPR1_EL1_read arg0)" + by (unfold ICC_BPR1_EL1_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_BPR1_EL1_SysRegRead_c56bf88f1b4aee37[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_BPR1_EL1_SysRegRead_c56bf88f1b4aee37 el op0 op1 CRn op2 CRm)" + by (unfold ICC_BPR1_EL1_SysRegRead_c56bf88f1b4aee37_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_CTLR_EL1_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ICC_CTLR_EL1_read arg0)" + by (unfold ICC_CTLR_EL1_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_CTLR_EL1_SysRegRead_5754830bf787a1e2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_CTLR_EL1_SysRegRead_5754830bf787a1e2 el op0 op1 CRn op2 CRm)" + by (unfold ICC_CTLR_EL1_SysRegRead_5754830bf787a1e2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_CTLR_EL3_SysRegRead_aba1771445e9d51b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_CTLR_EL3_SysRegRead_aba1771445e9d51b el op0 op1 CRn op2 CRm)" + by (unfold ICC_CTLR_EL3_SysRegRead_aba1771445e9d51b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_HPPIR0_EL1_SysRegRead_221f9a6f32464de4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_HPPIR0_EL1_SysRegRead_221f9a6f32464de4 el op0 op1 CRn op2 CRm)" + by (unfold ICC_HPPIR0_EL1_SysRegRead_221f9a6f32464de4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_HPPIR1_EL1_SysRegRead_88ed0889f7d5a37a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_HPPIR1_EL1_SysRegRead_88ed0889f7d5a37a el op0 op1 CRn op2 CRm)" + by (unfold ICC_HPPIR1_EL1_SysRegRead_88ed0889f7d5a37a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_IAR0_EL1_SysRegRead_dcfaf70befc09037[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_IAR0_EL1_SysRegRead_dcfaf70befc09037 el op0 op1 CRn op2 CRm)" + by (unfold ICC_IAR0_EL1_SysRegRead_dcfaf70befc09037_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_IAR1_EL1_SysRegRead_9f370ba68fd3e44f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_IAR1_EL1_SysRegRead_9f370ba68fd3e44f el op0 op1 CRn op2 CRm)" + by (unfold ICC_IAR1_EL1_SysRegRead_9f370ba68fd3e44f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_IGRPEN0_EL1_SysRegRead_e575448f3c7e7a94[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_IGRPEN0_EL1_SysRegRead_e575448f3c7e7a94 el op0 op1 CRn op2 CRm)" + by (unfold ICC_IGRPEN0_EL1_SysRegRead_e575448f3c7e7a94_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_IGRPEN1_EL1_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ICC_IGRPEN1_EL1_read arg0)" + by (unfold ICC_IGRPEN1_EL1_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_IGRPEN1_EL1_SysRegRead_3cfd0733ef9b6efa[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_IGRPEN1_EL1_SysRegRead_3cfd0733ef9b6efa el op0 op1 CRn op2 CRm)" + by (unfold ICC_IGRPEN1_EL1_SysRegRead_3cfd0733ef9b6efa_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_IGRPEN1_EL3_SysRegRead_d192d252016b4c8d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_IGRPEN1_EL3_SysRegRead_d192d252016b4c8d el op0 op1 CRn op2 CRm)" + by (unfold ICC_IGRPEN1_EL3_SysRegRead_d192d252016b4c8d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_PMR_EL1_SysRegRead_4ab2c9427488fbf4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_PMR_EL1_SysRegRead_4ab2c9427488fbf4 el op0 op1 CRn op2 CRm)" + by (unfold ICC_PMR_EL1_SysRegRead_4ab2c9427488fbf4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_RPR_EL1_SysRegRead_bea9edc41b26aab0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_RPR_EL1_SysRegRead_bea9edc41b26aab0 el op0 op1 CRn op2 CRm)" + by (unfold ICC_RPR_EL1_SysRegRead_bea9edc41b26aab0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_SRE_EL1_SysRegRead_7cf0aa9fc619dea4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_SRE_EL1_SysRegRead_7cf0aa9fc619dea4 el op0 op1 CRn op2 CRm)" + by (unfold ICC_SRE_EL1_SysRegRead_7cf0aa9fc619dea4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_SRE_EL2_SysRegRead_35c9349812c986fe[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_SRE_EL2_SysRegRead_35c9349812c986fe el op0 op1 CRn op2 CRm)" + by (unfold ICC_SRE_EL2_SysRegRead_35c9349812c986fe_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_SRE_EL3_SysRegRead_c7d421022a5f589d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_SRE_EL3_SysRegRead_c7d421022a5f589d el op0 op1 CRn op2 CRm)" + by (unfold ICC_SRE_EL3_SysRegRead_c7d421022a5f589d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_AP0R_EL2_SysRegRead_a38114229330a389[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_AP0R_EL2_SysRegRead_a38114229330a389 el op0 op1 CRn op2 CRm)" + by (unfold ICH_AP0R_EL2_SysRegRead_a38114229330a389_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_AP1R_EL2_SysRegRead_3ef1256520a6f18e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_AP1R_EL2_SysRegRead_3ef1256520a6f18e el op0 op1 CRn op2 CRm)" + by (unfold ICH_AP1R_EL2_SysRegRead_3ef1256520a6f18e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_EISR_EL2_SysRegRead_a45d99ec0ef64804[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_EISR_EL2_SysRegRead_a45d99ec0ef64804 el op0 op1 CRn op2 CRm)" + by (unfold ICH_EISR_EL2_SysRegRead_a45d99ec0ef64804_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_ELRSR_EL2_SysRegRead_93859a236e9efe6d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_ELRSR_EL2_SysRegRead_93859a236e9efe6d el op0 op1 CRn op2 CRm)" + by (unfold ICH_ELRSR_EL2_SysRegRead_93859a236e9efe6d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_HCR_EL2_SysRegRead_bd436f3e91661e3b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_HCR_EL2_SysRegRead_bd436f3e91661e3b el op0 op1 CRn op2 CRm)" + by (unfold ICH_HCR_EL2_SysRegRead_bd436f3e91661e3b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_LR_EL2_SysRegRead_f9d8d38c7064e389[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_LR_EL2_SysRegRead_f9d8d38c7064e389 el op0 op1 CRn op2 CRm)" + by (unfold ICH_LR_EL2_SysRegRead_f9d8d38c7064e389_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_MISR_EL2_SysRegRead_4e46f86d49bd21cd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_MISR_EL2_SysRegRead_4e46f86d49bd21cd el op0 op1 CRn op2 CRm)" + by (unfold ICH_MISR_EL2_SysRegRead_4e46f86d49bd21cd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_VMCR_EL2_SysRegRead_3c019711ec735507[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_VMCR_EL2_SysRegRead_3c019711ec735507 el op0 op1 CRn op2 CRm)" + by (unfold ICH_VMCR_EL2_SysRegRead_3c019711ec735507_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_VTR_EL2_SysRegRead_2ed82d00af03b344[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_VTR_EL2_SysRegRead_2ed82d00af03b344 el op0 op1 CRn op2 CRm)" + by (unfold ICH_VTR_EL2_SysRegRead_2ed82d00af03b344_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_AA64AFR0_EL1_SysRegRead_325547f3ac10431a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_AA64AFR0_EL1_SysRegRead_325547f3ac10431a el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64AFR0_EL1_SysRegRead_325547f3ac10431a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_AA64AFR1_EL1_SysRegRead_99b67b76121ee706[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_AA64AFR1_EL1_SysRegRead_99b67b76121ee706 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64AFR1_EL1_SysRegRead_99b67b76121ee706_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_AA64DFR0_EL1_SysRegRead_c3e6b049dd70bbab[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_AA64DFR0_EL1_SysRegRead_c3e6b049dd70bbab el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64DFR0_EL1_SysRegRead_c3e6b049dd70bbab_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_AA64DFR1_EL1_SysRegRead_2f066031859d7035[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_AA64DFR1_EL1_SysRegRead_2f066031859d7035 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64DFR1_EL1_SysRegRead_2f066031859d7035_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_AA64ISAR0_EL1_SysRegRead_d35f255c04eaab0f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_AA64ISAR0_EL1_SysRegRead_d35f255c04eaab0f el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64ISAR0_EL1_SysRegRead_d35f255c04eaab0f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_AA64ISAR1_EL1_SysRegRead_1132f371c4707f61[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_AA64ISAR1_EL1_SysRegRead_1132f371c4707f61 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64ISAR1_EL1_SysRegRead_1132f371c4707f61_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_AA64MMFR0_EL1_SysRegRead_836c46ff67ac3f3d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_AA64MMFR0_EL1_SysRegRead_836c46ff67ac3f3d el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64MMFR0_EL1_SysRegRead_836c46ff67ac3f3d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_AA64MMFR1_EL1_SysRegRead_3abbf4d2af8dd3be[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_AA64MMFR1_EL1_SysRegRead_3abbf4d2af8dd3be el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64MMFR1_EL1_SysRegRead_3abbf4d2af8dd3be_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_AA64MMFR2_EL1_SysRegRead_1443648da3ca79dd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_AA64MMFR2_EL1_SysRegRead_1443648da3ca79dd el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64MMFR2_EL1_SysRegRead_1443648da3ca79dd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_AA64PFR0_EL1_SysRegRead_fe78f914579c8717[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_AA64PFR0_EL1_SysRegRead_fe78f914579c8717 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64PFR0_EL1_SysRegRead_fe78f914579c8717_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_AA64PFR1_EL1_SysRegRead_3be470f3d1bff138[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_AA64PFR1_EL1_SysRegRead_3be470f3d1bff138 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64PFR1_EL1_SysRegRead_3be470f3d1bff138_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_AA64ZFR0_EL1_SysRegRead_70425f5143f66c9f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_AA64ZFR0_EL1_SysRegRead_70425f5143f66c9f el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64ZFR0_EL1_SysRegRead_70425f5143f66c9f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_AFR0_EL1_SysRegRead_019e5ec822653217[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_AFR0_EL1_SysRegRead_019e5ec822653217 el op0 op1 CRn op2 CRm)" + by (unfold ID_AFR0_EL1_SysRegRead_019e5ec822653217_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_DFR0_EL1_SysRegRead_12146217191b4fee[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_DFR0_EL1_SysRegRead_12146217191b4fee el op0 op1 CRn op2 CRm)" + by (unfold ID_DFR0_EL1_SysRegRead_12146217191b4fee_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_ISAR0_EL1_SysRegRead_4e2f04c3a26dddb3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_ISAR0_EL1_SysRegRead_4e2f04c3a26dddb3 el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR0_EL1_SysRegRead_4e2f04c3a26dddb3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_ISAR1_EL1_SysRegRead_2f4500748023e22b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_ISAR1_EL1_SysRegRead_2f4500748023e22b el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR1_EL1_SysRegRead_2f4500748023e22b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_ISAR2_EL1_SysRegRead_1e8edaee6a0e9ef9[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_ISAR2_EL1_SysRegRead_1e8edaee6a0e9ef9 el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR2_EL1_SysRegRead_1e8edaee6a0e9ef9_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_ISAR3_EL1_SysRegRead_cf9a1aae39d73bdd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_ISAR3_EL1_SysRegRead_cf9a1aae39d73bdd el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR3_EL1_SysRegRead_cf9a1aae39d73bdd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_ISAR4_EL1_SysRegRead_9bffd9dcf4dd4ef4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_ISAR4_EL1_SysRegRead_9bffd9dcf4dd4ef4 el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR4_EL1_SysRegRead_9bffd9dcf4dd4ef4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_ISAR5_EL1_SysRegRead_f70928ed2f55c1f0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_ISAR5_EL1_SysRegRead_f70928ed2f55c1f0 el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR5_EL1_SysRegRead_f70928ed2f55c1f0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_ISAR6_EL1_SysRegRead_6ce3605912a2db6d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_ISAR6_EL1_SysRegRead_6ce3605912a2db6d el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR6_EL1_SysRegRead_6ce3605912a2db6d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_MMFR0_EL1_SysRegRead_b31c5faa39841084[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_MMFR0_EL1_SysRegRead_b31c5faa39841084 el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR0_EL1_SysRegRead_b31c5faa39841084_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_MMFR1_EL1_SysRegRead_b0f4bc0d71c9af14[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_MMFR1_EL1_SysRegRead_b0f4bc0d71c9af14 el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR1_EL1_SysRegRead_b0f4bc0d71c9af14_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_MMFR2_EL1_SysRegRead_b60501193094f759[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_MMFR2_EL1_SysRegRead_b60501193094f759 el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR2_EL1_SysRegRead_b60501193094f759_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_MMFR3_EL1_SysRegRead_dc45af19c356c392[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_MMFR3_EL1_SysRegRead_dc45af19c356c392 el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR3_EL1_SysRegRead_dc45af19c356c392_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_MMFR4_EL1_SysRegRead_237ae4b6fb487f3e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_MMFR4_EL1_SysRegRead_237ae4b6fb487f3e el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR4_EL1_SysRegRead_237ae4b6fb487f3e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_MMFR5_EL1_SysRegRead_00dc6140c3593f6a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_MMFR5_EL1_SysRegRead_00dc6140c3593f6a el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR5_EL1_SysRegRead_00dc6140c3593f6a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_PFR0_EL1_SysRegRead_ab73eb91d66cfece[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_PFR0_EL1_SysRegRead_ab73eb91d66cfece el op0 op1 CRn op2 CRm)" + by (unfold ID_PFR0_EL1_SysRegRead_ab73eb91d66cfece_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_PFR1_EL1_SysRegRead_264075958e26856b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_PFR1_EL1_SysRegRead_264075958e26856b el op0 op1 CRn op2 CRm)" + by (unfold ID_PFR1_EL1_SysRegRead_264075958e26856b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ID_PFR2_EL1_SysRegRead_8561b575e8dfcee0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ID_PFR2_EL1_SysRegRead_8561b575e8dfcee0 el op0 op1 CRn op2 CRm)" + by (unfold ID_PFR2_EL1_SysRegRead_8561b575e8dfcee0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IFSR32_EL2_SysRegRead_3b41290786c143ba[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (IFSR32_EL2_SysRegRead_3b41290786c143ba el op0 op1 CRn op2 CRm)" + by (unfold IFSR32_EL2_SysRegRead_3b41290786c143ba_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ISR_EL1_SysRegRead_41b7dbf26b89e726[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ISR_EL1_SysRegRead_41b7dbf26b89e726 el op0 op1 CRn op2 CRm)" + by (unfold ISR_EL1_SysRegRead_41b7dbf26b89e726_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_LORC_EL1_SysRegRead_0067e90ee116c26f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (LORC_EL1_SysRegRead_0067e90ee116c26f el op0 op1 CRn op2 CRm)" + by (unfold LORC_EL1_SysRegRead_0067e90ee116c26f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_LOREA_EL1_SysRegRead_ec495c3c15ed4dbe[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (LOREA_EL1_SysRegRead_ec495c3c15ed4dbe el op0 op1 CRn op2 CRm)" + by (unfold LOREA_EL1_SysRegRead_ec495c3c15ed4dbe_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_LORID_EL1_SysRegRead_a063108cc96d4baa[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (LORID_EL1_SysRegRead_a063108cc96d4baa el op0 op1 CRn op2 CRm)" + by (unfold LORID_EL1_SysRegRead_a063108cc96d4baa_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_LORN_EL1_SysRegRead_da981b495b21c400[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (LORN_EL1_SysRegRead_da981b495b21c400 el op0 op1 CRn op2 CRm)" + by (unfold LORN_EL1_SysRegRead_da981b495b21c400_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_LORSA_EL1_SysRegRead_cdc08dda4115abc7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (LORSA_EL1_SysRegRead_cdc08dda4115abc7 el op0 op1 CRn op2 CRm)" + by (unfold LORSA_EL1_SysRegRead_cdc08dda4115abc7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MAIR_EL12_SysRegRead_ac3327848e47dda6[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MAIR_EL12_SysRegRead_ac3327848e47dda6 el op0 op1 CRn op2 CRm)" + by (unfold MAIR_EL12_SysRegRead_ac3327848e47dda6_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MAIR_EL1_SysRegRead_ee00b1441fc4a50d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MAIR_EL1_SysRegRead_ee00b1441fc4a50d el op0 op1 CRn op2 CRm)" + by (unfold MAIR_EL1_SysRegRead_ee00b1441fc4a50d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MAIR_EL2_SysRegRead_66c03f7cb594c1bd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MAIR_EL2_SysRegRead_66c03f7cb594c1bd el op0 op1 CRn op2 CRm)" + by (unfold MAIR_EL2_SysRegRead_66c03f7cb594c1bd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MAIR_EL3_SysRegRead_0eb4af28a4f9b45a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MAIR_EL3_SysRegRead_0eb4af28a4f9b45a el op0 op1 CRn op2 CRm)" + by (unfold MAIR_EL3_SysRegRead_0eb4af28a4f9b45a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MDCCINT_EL1_SysRegRead_12f1a0397d5a3729[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MDCCINT_EL1_SysRegRead_12f1a0397d5a3729 el op0 op1 CRn op2 CRm)" + by (unfold MDCCINT_EL1_SysRegRead_12f1a0397d5a3729_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MDCCSR_EL0_SysRegRead_1ca0d9105cd616c5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MDCCSR_EL0_SysRegRead_1ca0d9105cd616c5 el op0 op1 CRn op2 CRm)" + by (unfold MDCCSR_EL0_SysRegRead_1ca0d9105cd616c5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MDCR_EL2_SysRegRead_f2181c815a998208[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MDCR_EL2_SysRegRead_f2181c815a998208 el op0 op1 CRn op2 CRm)" + by (unfold MDCR_EL2_SysRegRead_f2181c815a998208_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MDCR_EL3_SysRegRead_229d5ee95c6e9850[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MDCR_EL3_SysRegRead_229d5ee95c6e9850 el op0 op1 CRn op2 CRm)" + by (unfold MDCR_EL3_SysRegRead_229d5ee95c6e9850_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MDRAR_EL1_SysRegRead_4c6f0d270d3fe56e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MDRAR_EL1_SysRegRead_4c6f0d270d3fe56e el op0 op1 CRn op2 CRm)" + by (unfold MDRAR_EL1_SysRegRead_4c6f0d270d3fe56e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MDSCR_EL1_SysRegRead_5184636ced539526[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MDSCR_EL1_SysRegRead_5184636ced539526 el op0 op1 CRn op2 CRm)" + by (unfold MDSCR_EL1_SysRegRead_5184636ced539526_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MIDR_EL1_SysRegRead_d49cc5f604ad167e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MIDR_EL1_SysRegRead_d49cc5f604ad167e el op0 op1 CRn op2 CRm)" + by (unfold MIDR_EL1_SysRegRead_d49cc5f604ad167e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM2_EL2_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (MPAM2_EL2_read arg0)" + by (unfold MPAM2_EL2_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM0_EL1_SysRegRead_87af318fd5c9f9f7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAM0_EL1_SysRegRead_87af318fd5c9f9f7 el op0 op1 CRn op2 CRm)" + by (unfold MPAM0_EL1_SysRegRead_87af318fd5c9f9f7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM1_EL1_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (MPAM1_EL1_read arg0)" + by (unfold MPAM1_EL1_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM1_EL12_SysRegRead_229a253b730e26d9[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAM1_EL12_SysRegRead_229a253b730e26d9 el op0 op1 CRn op2 CRm)" + by (unfold MPAM1_EL12_SysRegRead_229a253b730e26d9_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM1_EL1_SysRegRead_770ea23b87b18d99[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAM1_EL1_SysRegRead_770ea23b87b18d99 el op0 op1 CRn op2 CRm)" + by (unfold MPAM1_EL1_SysRegRead_770ea23b87b18d99_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM2_EL2_SysRegRead_10b60646fb381bea[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAM2_EL2_SysRegRead_10b60646fb381bea el op0 op1 CRn op2 CRm)" + by (unfold MPAM2_EL2_SysRegRead_10b60646fb381bea_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM3_EL3_SysRegRead_989f38b07d8b4265[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAM3_EL3_SysRegRead_989f38b07d8b4265 el op0 op1 CRn op2 CRm)" + by (unfold MPAM3_EL3_SysRegRead_989f38b07d8b4265_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMHCR_EL2_SysRegRead_6ee5f61be808e32e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMHCR_EL2_SysRegRead_6ee5f61be808e32e el op0 op1 CRn op2 CRm)" + by (unfold MPAMHCR_EL2_SysRegRead_6ee5f61be808e32e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMIDR_EL1_SysRegRead_df4c57d831354b3c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMIDR_EL1_SysRegRead_df4c57d831354b3c el op0 op1 CRn op2 CRm)" + by (unfold MPAMIDR_EL1_SysRegRead_df4c57d831354b3c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM0_EL2_SysRegRead_d878a15f2ea1751d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM0_EL2_SysRegRead_d878a15f2ea1751d el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM0_EL2_SysRegRead_d878a15f2ea1751d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM1_EL2_SysRegRead_78ba55a3ef5fc5ba[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM1_EL2_SysRegRead_78ba55a3ef5fc5ba el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM1_EL2_SysRegRead_78ba55a3ef5fc5ba_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM2_EL2_SysRegRead_590d1577b5eb780d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM2_EL2_SysRegRead_590d1577b5eb780d el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM2_EL2_SysRegRead_590d1577b5eb780d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM3_EL2_SysRegRead_3d93a30deb34ea81[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM3_EL2_SysRegRead_3d93a30deb34ea81 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM3_EL2_SysRegRead_3d93a30deb34ea81_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM4_EL2_SysRegRead_c4fa65dba541d8f3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM4_EL2_SysRegRead_c4fa65dba541d8f3 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM4_EL2_SysRegRead_c4fa65dba541d8f3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM5_EL2_SysRegRead_0f596cf6a35cf124[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM5_EL2_SysRegRead_0f596cf6a35cf124 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM5_EL2_SysRegRead_0f596cf6a35cf124_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM6_EL2_SysRegRead_c93ffeb6ea409c71[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM6_EL2_SysRegRead_c93ffeb6ea409c71 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM6_EL2_SysRegRead_c93ffeb6ea409c71_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM7_EL2_SysRegRead_ef19c89f1fa31f3e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM7_EL2_SysRegRead_ef19c89f1fa31f3e el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM7_EL2_SysRegRead_ef19c89f1fa31f3e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPMV_EL2_SysRegRead_6de5731367257b91[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPMV_EL2_SysRegRead_6de5731367257b91 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPMV_EL2_SysRegRead_6de5731367257b91_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPIDR_EL1_SysRegRead_1a44c237fc7e90a0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPIDR_EL1_SysRegRead_1a44c237fc7e90a0 el op0 op1 CRn op2 CRm)" + by (unfold MPIDR_EL1_SysRegRead_1a44c237fc7e90a0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MVFR0_EL1_SysRegRead_982614cb681cfbbf[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MVFR0_EL1_SysRegRead_982614cb681cfbbf el op0 op1 CRn op2 CRm)" + by (unfold MVFR0_EL1_SysRegRead_982614cb681cfbbf_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MVFR1_EL1_SysRegRead_1964a95566ab0fcd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MVFR1_EL1_SysRegRead_1964a95566ab0fcd el op0 op1 CRn op2 CRm)" + by (unfold MVFR1_EL1_SysRegRead_1964a95566ab0fcd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MVFR2_EL1_SysRegRead_f6245ffc535897f2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MVFR2_EL1_SysRegRead_f6245ffc535897f2 el op0 op1 CRn op2 CRm)" + by (unfold MVFR2_EL1_SysRegRead_f6245ffc535897f2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_NZCV_SysRegRead_00499c04100376d9[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (NZCV_SysRegRead_00499c04100376d9 el op0 op1 CRn op2 CRm)" + by (unfold NZCV_SysRegRead_00499c04100376d9_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveDoubleLock[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveDoubleLock arg0)" + by (unfold HaveDoubleLock_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_OSDLR_EL1_SysRegRead_4cb80c508c4cced4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (OSDLR_EL1_SysRegRead_4cb80c508c4cced4 el op0 op1 CRn op2 CRm)" + by (unfold OSDLR_EL1_SysRegRead_4cb80c508c4cced4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_OSDTRRX_EL1_SysRegRead_d4eb07360bc69d28[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (OSDTRRX_EL1_SysRegRead_d4eb07360bc69d28 el op0 op1 CRn op2 CRm)" + by (unfold OSDTRRX_EL1_SysRegRead_d4eb07360bc69d28_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_OSDTRTX_EL1_SysRegRead_008c22058272684f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (OSDTRTX_EL1_SysRegRead_008c22058272684f el op0 op1 CRn op2 CRm)" + by (unfold OSDTRTX_EL1_SysRegRead_008c22058272684f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_OSECCR_EL1_SysRegRead_264ab12a32fecc30[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (OSECCR_EL1_SysRegRead_264ab12a32fecc30 el op0 op1 CRn op2 CRm)" + by (unfold OSECCR_EL1_SysRegRead_264ab12a32fecc30_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_OSLSR_EL1_SysRegRead_d99062033a35ccbf[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (OSLSR_EL1_SysRegRead_d99062033a35ccbf el op0 op1 CRn op2 CRm)" + by (unfold OSLSR_EL1_SysRegRead_d99062033a35ccbf_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PAN_SysRegRead_36ab36abf6da91e0[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (PAN_SysRegRead_36ab36abf6da91e0 el op0 op1 CRn op2 CRm)" + by (unfold PAN_SysRegRead_36ab36abf6da91e0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PAR_EL1_SysRegRead_888e7c84935ebac7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PAR_EL1_SysRegRead_888e7c84935ebac7 el op0 op1 CRn op2 CRm)" + by (unfold PAR_EL1_SysRegRead_888e7c84935ebac7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMBIDR_EL1_SysRegRead_306c3f68e41521a3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMBIDR_EL1_SysRegRead_306c3f68e41521a3 el op0 op1 CRn op2 CRm)" + by (unfold PMBIDR_EL1_SysRegRead_306c3f68e41521a3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMBLIMITR_EL1_SysRegRead_b7c18938ab0566dc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMBLIMITR_EL1_SysRegRead_b7c18938ab0566dc el op0 op1 CRn op2 CRm)" + by (unfold PMBLIMITR_EL1_SysRegRead_b7c18938ab0566dc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMBPTR_EL1_SysRegRead_fb82e1b6e480bd0a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMBPTR_EL1_SysRegRead_fb82e1b6e480bd0a el op0 op1 CRn op2 CRm)" + by (unfold PMBPTR_EL1_SysRegRead_fb82e1b6e480bd0a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMBSR_EL1_SysRegRead_87628bec330b9f53[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMBSR_EL1_SysRegRead_87628bec330b9f53 el op0 op1 CRn op2 CRm)" + by (unfold PMBSR_EL1_SysRegRead_87628bec330b9f53_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMCCFILTR_EL0_SysRegRead_349918c2333bfc1e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMCCFILTR_EL0_SysRegRead_349918c2333bfc1e el op0 op1 CRn op2 CRm)" + by (unfold PMCCFILTR_EL0_SysRegRead_349918c2333bfc1e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMCCNTR_EL0_SysRegRead_45fc425eff298404[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMCCNTR_EL0_SysRegRead_45fc425eff298404 el op0 op1 CRn op2 CRm)" + by (unfold PMCCNTR_EL0_SysRegRead_45fc425eff298404_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMCEID0_EL0_SysRegRead_1364a10a0c913d82[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMCEID0_EL0_SysRegRead_1364a10a0c913d82 el op0 op1 CRn op2 CRm)" + by (unfold PMCEID0_EL0_SysRegRead_1364a10a0c913d82_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMCEID1_EL0_SysRegRead_2db7a3b96735d30a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMCEID1_EL0_SysRegRead_2db7a3b96735d30a el op0 op1 CRn op2 CRm)" + by (unfold PMCEID1_EL0_SysRegRead_2db7a3b96735d30a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMCNTENCLR_EL0_SysRegRead_5ac431b885c9c5e4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMCNTENCLR_EL0_SysRegRead_5ac431b885c9c5e4 el op0 op1 CRn op2 CRm)" + by (unfold PMCNTENCLR_EL0_SysRegRead_5ac431b885c9c5e4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMCNTENSET_EL0_SysRegRead_848c3aa603193fb7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMCNTENSET_EL0_SysRegRead_848c3aa603193fb7 el op0 op1 CRn op2 CRm)" + by (unfold PMCNTENSET_EL0_SysRegRead_848c3aa603193fb7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMCR_EL0_SysRegRead_9a03e454327a1718[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMCR_EL0_SysRegRead_9a03e454327a1718 el op0 op1 CRn op2 CRm)" + by (unfold PMCR_EL0_SysRegRead_9a03e454327a1718_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMEVCNTR_EL0_SysRegRead_e0380ad70bc25a0c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMEVCNTR_EL0_SysRegRead_e0380ad70bc25a0c el op0 op1 CRn op2 CRm)" + by (unfold PMEVCNTR_EL0_SysRegRead_e0380ad70bc25a0c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMEVTYPER_EL0_SysRegRead_b05172ff9d10dad4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMEVTYPER_EL0_SysRegRead_b05172ff9d10dad4 el op0 op1 CRn op2 CRm)" + by (unfold PMEVTYPER_EL0_SysRegRead_b05172ff9d10dad4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMINTENCLR_EL1_SysRegRead_43b8f4d9b40b2620[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMINTENCLR_EL1_SysRegRead_43b8f4d9b40b2620 el op0 op1 CRn op2 CRm)" + by (unfold PMINTENCLR_EL1_SysRegRead_43b8f4d9b40b2620_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMINTENSET_EL1_SysRegRead_a3d4464c2051ff23[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMINTENSET_EL1_SysRegRead_a3d4464c2051ff23 el op0 op1 CRn op2 CRm)" + by (unfold PMINTENSET_EL1_SysRegRead_a3d4464c2051ff23_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMOVSCLR_EL0_SysRegRead_300e5dfb491e58fa[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMOVSCLR_EL0_SysRegRead_300e5dfb491e58fa el op0 op1 CRn op2 CRm)" + by (unfold PMOVSCLR_EL0_SysRegRead_300e5dfb491e58fa_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMOVSSET_EL0_SysRegRead_e3c0657a6c8b11c8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMOVSSET_EL0_SysRegRead_e3c0657a6c8b11c8 el op0 op1 CRn op2 CRm)" + by (unfold PMOVSSET_EL0_SysRegRead_e3c0657a6c8b11c8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSCR_EL12_SysRegRead_624c386ea3cce853[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSCR_EL12_SysRegRead_624c386ea3cce853 el op0 op1 CRn op2 CRm)" + by (unfold PMSCR_EL12_SysRegRead_624c386ea3cce853_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSCR_EL1_SysRegRead_39ffc554ca37b155[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSCR_EL1_SysRegRead_39ffc554ca37b155 el op0 op1 CRn op2 CRm)" + by (unfold PMSCR_EL1_SysRegRead_39ffc554ca37b155_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSCR_EL2_SysRegRead_11330bd80566814a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSCR_EL2_SysRegRead_11330bd80566814a el op0 op1 CRn op2 CRm)" + by (unfold PMSCR_EL2_SysRegRead_11330bd80566814a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSELR_EL0_SysRegRead_540b592cb875b32f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSELR_EL0_SysRegRead_540b592cb875b32f el op0 op1 CRn op2 CRm)" + by (unfold PMSELR_EL0_SysRegRead_540b592cb875b32f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSEVFR_EL1_SysRegRead_9e9a58f73d629d59[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSEVFR_EL1_SysRegRead_9e9a58f73d629d59 el op0 op1 CRn op2 CRm)" + by (unfold PMSEVFR_EL1_SysRegRead_9e9a58f73d629d59_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSFCR_EL1_SysRegRead_30b07ff27088a488[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSFCR_EL1_SysRegRead_30b07ff27088a488 el op0 op1 CRn op2 CRm)" + by (unfold PMSFCR_EL1_SysRegRead_30b07ff27088a488_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSICR_EL1_SysRegRead_1b4bf4bb07470e4c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSICR_EL1_SysRegRead_1b4bf4bb07470e4c el op0 op1 CRn op2 CRm)" + by (unfold PMSICR_EL1_SysRegRead_1b4bf4bb07470e4c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSIDR_EL1_SysRegRead_062cecff79d24b4d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSIDR_EL1_SysRegRead_062cecff79d24b4d el op0 op1 CRn op2 CRm)" + by (unfold PMSIDR_EL1_SysRegRead_062cecff79d24b4d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSIRR_EL1_SysRegRead_b565329ce30ac491[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSIRR_EL1_SysRegRead_b565329ce30ac491 el op0 op1 CRn op2 CRm)" + by (unfold PMSIRR_EL1_SysRegRead_b565329ce30ac491_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSLATFR_EL1_SysRegRead_f82542fec2521a41[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSLATFR_EL1_SysRegRead_f82542fec2521a41 el op0 op1 CRn op2 CRm)" + by (unfold PMSLATFR_EL1_SysRegRead_f82542fec2521a41_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMUSERENR_EL0_SysRegRead_7efca1a4be376eb7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMUSERENR_EL0_SysRegRead_7efca1a4be376eb7 el op0 op1 CRn op2 CRm)" + by (unfold PMUSERENR_EL0_SysRegRead_7efca1a4be376eb7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMXEVCNTR_EL0_SysRegRead_193921f886161922[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMXEVCNTR_EL0_SysRegRead_193921f886161922 el op0 op1 CRn op2 CRm)" + by (unfold PMXEVCNTR_EL0_SysRegRead_193921f886161922_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMXEVTYPER_EL0_SysRegRead_a34d7cb6f32074c5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMXEVTYPER_EL0_SysRegRead_a34d7cb6f32074c5 el op0 op1 CRn op2 CRm)" + by (unfold PMXEVTYPER_EL0_SysRegRead_a34d7cb6f32074c5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_REVIDR_EL1_SysRegRead_06ac796f098a1e84[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (REVIDR_EL1_SysRegRead_06ac796f098a1e84 el op0 op1 CRn op2 CRm)" + by (unfold REVIDR_EL1_SysRegRead_06ac796f098a1e84_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RMR_EL1_SysRegRead_69f4933c1a574580[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RMR_EL1_SysRegRead_69f4933c1a574580 el op0 op1 CRn op2 CRm)" + by (unfold RMR_EL1_SysRegRead_69f4933c1a574580_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RMR_EL2_SysRegRead_75749340e0828f00[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RMR_EL2_SysRegRead_75749340e0828f00 el op0 op1 CRn op2 CRm)" + by (unfold RMR_EL2_SysRegRead_75749340e0828f00_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RMR_EL3_SysRegRead_fa5f18c3b20f8894[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RMR_EL3_SysRegRead_fa5f18c3b20f8894 el op0 op1 CRn op2 CRm)" + by (unfold RMR_EL3_SysRegRead_fa5f18c3b20f8894_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RSP_EL0_SysRegRead_b64c62bd96d973e3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RSP_EL0_SysRegRead_b64c62bd96d973e3 el op0 op1 CRn op2 CRm)" + by (unfold RSP_EL0_SysRegRead_b64c62bd96d973e3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RTPIDR_EL0_SysRegRead_0ce5a74dba936523[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RTPIDR_EL0_SysRegRead_0ce5a74dba936523 el op0 op1 CRn op2 CRm)" + by (unfold RTPIDR_EL0_SysRegRead_0ce5a74dba936523_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RVBAR_EL1_SysRegRead_48a958c9250293d1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RVBAR_EL1_SysRegRead_48a958c9250293d1 el op0 op1 CRn op2 CRm)" + by (unfold RVBAR_EL1_SysRegRead_48a958c9250293d1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RVBAR_EL2_SysRegRead_2fb802203150f4cc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RVBAR_EL2_SysRegRead_2fb802203150f4cc el op0 op1 CRn op2 CRm)" + by (unfold RVBAR_EL2_SysRegRead_2fb802203150f4cc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RVBAR_EL3_SysRegRead_000d1ea4b77ffa21[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RVBAR_EL3_SysRegRead_000d1ea4b77ffa21 el op0 op1 CRn op2 CRm)" + by (unfold RVBAR_EL3_SysRegRead_000d1ea4b77ffa21_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S3_op1_CCn_CCm_op2_SysRegRead_d72a7245384bbc0e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S3_op1_CCn_CCm_op2_SysRegRead_d72a7245384bbc0e el op0 op1 CRn op2 CRm)" + by (unfold S3_op1_CCn_CCm_op2_SysRegRead_d72a7245384bbc0e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCR_EL3_SysRegRead_082a69b26890132d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCR_EL3_SysRegRead_082a69b26890132d el op0 op1 CRn op2 CRm)" + by (unfold SCR_EL3_SysRegRead_082a69b26890132d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCTLR_EL12_SysRegRead_81ba00bca4ce39dc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCTLR_EL12_SysRegRead_81ba00bca4ce39dc el op0 op1 CRn op2 CRm)" + by (unfold SCTLR_EL12_SysRegRead_81ba00bca4ce39dc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCTLR_EL1_SysRegRead_cc5fb072b0cb85eb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCTLR_EL1_SysRegRead_cc5fb072b0cb85eb el op0 op1 CRn op2 CRm)" + by (unfold SCTLR_EL1_SysRegRead_cc5fb072b0cb85eb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCTLR_EL2_SysRegRead_3cc208f3abf97e34[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCTLR_EL2_SysRegRead_3cc208f3abf97e34 el op0 op1 CRn op2 CRm)" + by (unfold SCTLR_EL2_SysRegRead_3cc208f3abf97e34_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCTLR_EL3_SysRegRead_9c537c9c01007c3e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCTLR_EL3_SysRegRead_9c537c9c01007c3e el op0 op1 CRn op2 CRm)" + by (unfold SCTLR_EL3_SysRegRead_9c537c9c01007c3e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCXTNUM_EL0_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SCXTNUM_EL0_read arg0)" + by (unfold SCXTNUM_EL0_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCXTNUM_EL0_SysRegRead_ee5b769fc7f044cc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCXTNUM_EL0_SysRegRead_ee5b769fc7f044cc el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL0_SysRegRead_ee5b769fc7f044cc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCXTNUM_EL12_SysRegRead_d31f345333a78d48[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCXTNUM_EL12_SysRegRead_d31f345333a78d48 el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL12_SysRegRead_d31f345333a78d48_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCXTNUM_EL1_SysRegRead_dd27b7ad05ded1ab[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCXTNUM_EL1_SysRegRead_dd27b7ad05ded1ab el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL1_SysRegRead_dd27b7ad05ded1ab_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCXTNUM_EL2_SysRegRead_421b17f19f5fdd2a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCXTNUM_EL2_SysRegRead_421b17f19f5fdd2a el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL2_SysRegRead_421b17f19f5fdd2a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCXTNUM_EL3_SysRegRead_5f15a3b4da1bd4bb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCXTNUM_EL3_SysRegRead_5f15a3b4da1bd4bb el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL3_SysRegRead_5f15a3b4da1bd4bb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SDER32_EL3_SysRegRead_e21f871563c7e34e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SDER32_EL3_SysRegRead_e21f871563c7e34e el op0 op1 CRn op2 CRm)" + by (unfold SDER32_EL3_SysRegRead_e21f871563c7e34e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_EL12_SysRegRead_a8511792ae31e865[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SPSR_EL12_SysRegRead_a8511792ae31e865 el op0 op1 CRn op2 CRm)" + by (unfold SPSR_EL12_SysRegRead_a8511792ae31e865_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_EL1_SysRegRead_32354aa2884c2edd[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SPSR_EL1_SysRegRead_32354aa2884c2edd el op0 op1 CRn op2 CRm)" + by (unfold SPSR_EL1_SysRegRead_32354aa2884c2edd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_EL2_SysRegRead_63ec64f2f805090d[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SPSR_EL2_SysRegRead_63ec64f2f805090d el op0 op1 CRn op2 CRm)" + by (unfold SPSR_EL2_SysRegRead_63ec64f2f805090d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_EL3_SysRegRead_fca96fc0dc593061[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SPSR_EL3_SysRegRead_fca96fc0dc593061 el op0 op1 CRn op2 CRm)" + by (unfold SPSR_EL3_SysRegRead_fca96fc0dc593061_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_abt_SysRegRead_7ed396e0808f79f6[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SPSR_abt_SysRegRead_7ed396e0808f79f6 el op0 op1 CRn op2 CRm)" + by (unfold SPSR_abt_SysRegRead_7ed396e0808f79f6_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_fiq_SysRegRead_390457aa85161af4[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SPSR_fiq_SysRegRead_390457aa85161af4 el op0 op1 CRn op2 CRm)" + by (unfold SPSR_fiq_SysRegRead_390457aa85161af4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_irq_SysRegRead_8593f29eadca9d64[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SPSR_irq_SysRegRead_8593f29eadca9d64 el op0 op1 CRn op2 CRm)" + by (unfold SPSR_irq_SysRegRead_8593f29eadca9d64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_und_SysRegRead_89a3b7c63cd43460[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SPSR_und_SysRegRead_89a3b7c63cd43460 el op0 op1 CRn op2 CRm)" + by (unfold SPSR_und_SysRegRead_89a3b7c63cd43460_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSel_SysRegRead_ac7632fd1580b15b[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SPSel_SysRegRead_ac7632fd1580b15b el op0 op1 CRn op2 CRm)" + by (unfold SPSel_SysRegRead_ac7632fd1580b15b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SP_EL0_SysRegRead_4b07157e43cd0456[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SP_EL0_SysRegRead_4b07157e43cd0456 el op0 op1 CRn op2 CRm)" + by (unfold SP_EL0_SysRegRead_4b07157e43cd0456_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SP_EL1_SysRegRead_44ac23d2a7608550[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SP_EL1_SysRegRead_44ac23d2a7608550 el op0 op1 CRn op2 CRm)" + by (unfold SP_EL1_SysRegRead_44ac23d2a7608550_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SP_EL2_SysRegRead_9c4b7d596526b300[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SP_EL2_SysRegRead_9c4b7d596526b300 el op0 op1 CRn op2 CRm)" + by (unfold SP_EL2_SysRegRead_9c4b7d596526b300_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SSBS_SysRegRead_05419031832511d1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SSBS_SysRegRead_05419031832511d1 el op0 op1 CRn op2 CRm)" + by (unfold SSBS_SysRegRead_05419031832511d1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TCR_EL12_SysRegRead_cefcc3f131a70a7f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TCR_EL12_SysRegRead_cefcc3f131a70a7f el op0 op1 CRn op2 CRm)" + by (unfold TCR_EL12_SysRegRead_cefcc3f131a70a7f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TCR_EL1_SysRegRead_fbe255888fba9865[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TCR_EL1_SysRegRead_fbe255888fba9865 el op0 op1 CRn op2 CRm)" + by (unfold TCR_EL1_SysRegRead_fbe255888fba9865_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TCR_EL2_SysRegRead_3467687df9c2aec1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TCR_EL2_SysRegRead_3467687df9c2aec1 el op0 op1 CRn op2 CRm)" + by (unfold TCR_EL2_SysRegRead_3467687df9c2aec1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TCR_EL3_SysRegRead_7da88d4a232f9451[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TCR_EL3_SysRegRead_7da88d4a232f9451 el op0 op1 CRn op2 CRm)" + by (unfold TCR_EL3_SysRegRead_7da88d4a232f9451_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TPIDRRO_EL0_SysRegRead_3dc5dc323922fcfa[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (TPIDRRO_EL0_SysRegRead_3dc5dc323922fcfa el op0 op1 CRn op2 CRm)" + by (unfold TPIDRRO_EL0_SysRegRead_3dc5dc323922fcfa_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TPIDR_EL0_SysRegRead_7b944c4fc3d3f60f[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (TPIDR_EL0_SysRegRead_7b944c4fc3d3f60f el op0 op1 CRn op2 CRm)" + by (unfold TPIDR_EL0_SysRegRead_7b944c4fc3d3f60f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TPIDR_EL1_SysRegRead_8db91ea8b9abc411[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (TPIDR_EL1_SysRegRead_8db91ea8b9abc411 el op0 op1 CRn op2 CRm)" + by (unfold TPIDR_EL1_SysRegRead_8db91ea8b9abc411_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TPIDR_EL2_SysRegRead_fc4633f7449b5b4a[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (TPIDR_EL2_SysRegRead_fc4633f7449b5b4a el op0 op1 CRn op2 CRm)" + by (unfold TPIDR_EL2_SysRegRead_fc4633f7449b5b4a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TPIDR_EL3_SysRegRead_c6069d62b310a137[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (TPIDR_EL3_SysRegRead_c6069d62b310a137 el op0 op1 CRn op2 CRm)" + by (unfold TPIDR_EL3_SysRegRead_c6069d62b310a137_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR0_EL12_SysRegRead_73f9bd4d027badee[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR0_EL12_SysRegRead_73f9bd4d027badee el op0 op1 CRn op2 CRm)" + by (unfold TTBR0_EL12_SysRegRead_73f9bd4d027badee_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR0_EL1_SysRegRead_2e8a6c25b2e4759a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR0_EL1_SysRegRead_2e8a6c25b2e4759a el op0 op1 CRn op2 CRm)" + by (unfold TTBR0_EL1_SysRegRead_2e8a6c25b2e4759a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR0_EL2_SysRegRead_8d4de9e080477354[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR0_EL2_SysRegRead_8d4de9e080477354 el op0 op1 CRn op2 CRm)" + by (unfold TTBR0_EL2_SysRegRead_8d4de9e080477354_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR0_EL3_SysRegRead_a46e35edfe45a273[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR0_EL3_SysRegRead_a46e35edfe45a273 el op0 op1 CRn op2 CRm)" + by (unfold TTBR0_EL3_SysRegRead_a46e35edfe45a273_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR1_EL12_SysRegRead_bfbc2899eb278d2b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR1_EL12_SysRegRead_bfbc2899eb278d2b el op0 op1 CRn op2 CRm)" + by (unfold TTBR1_EL12_SysRegRead_bfbc2899eb278d2b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR1_EL1_SysRegRead_2cb2fb59089165c5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR1_EL1_SysRegRead_2cb2fb59089165c5 el op0 op1 CRn op2 CRm)" + by (unfold TTBR1_EL1_SysRegRead_2cb2fb59089165c5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR1_EL2_SysRegRead_08cd28a9b17bc317[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR1_EL2_SysRegRead_08cd28a9b17bc317 el op0 op1 CRn op2 CRm)" + by (unfold TTBR1_EL2_SysRegRead_08cd28a9b17bc317_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_UAO_SysRegRead_297f45f7f70ec250[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (UAO_SysRegRead_297f45f7f70ec250 el op0 op1 CRn op2 CRm)" + by (unfold UAO_SysRegRead_297f45f7f70ec250_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VBAR_EL12_SysRegRead_2ad4e02fbe99cf3d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VBAR_EL12_SysRegRead_2ad4e02fbe99cf3d el op0 op1 CRn op2 CRm)" + by (unfold VBAR_EL12_SysRegRead_2ad4e02fbe99cf3d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VBAR_EL1_SysRegRead_4d14cb3b6fe16ab6[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VBAR_EL1_SysRegRead_4d14cb3b6fe16ab6 el op0 op1 CRn op2 CRm)" + by (unfold VBAR_EL1_SysRegRead_4d14cb3b6fe16ab6_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VBAR_EL2_SysRegRead_1f6b3c94ccfecacf[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VBAR_EL2_SysRegRead_1f6b3c94ccfecacf el op0 op1 CRn op2 CRm)" + by (unfold VBAR_EL2_SysRegRead_1f6b3c94ccfecacf_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VBAR_EL3_SysRegRead_32f42cb574998654[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VBAR_EL3_SysRegRead_32f42cb574998654 el op0 op1 CRn op2 CRm)" + by (unfold VBAR_EL3_SysRegRead_32f42cb574998654_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VDISR_EL2_SysRegRead_14dff4ad4ae8c3a2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VDISR_EL2_SysRegRead_14dff4ad4ae8c3a2 el op0 op1 CRn op2 CRm)" + by (unfold VDISR_EL2_SysRegRead_14dff4ad4ae8c3a2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VMPIDR_EL2_SysRegRead_49b7c13dd1b0804c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VMPIDR_EL2_SysRegRead_49b7c13dd1b0804c el op0 op1 CRn op2 CRm)" + by (unfold VMPIDR_EL2_SysRegRead_49b7c13dd1b0804c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VPIDR_EL2_SysRegRead_f6520cd6a1f62bd8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VPIDR_EL2_SysRegRead_f6520cd6a1f62bd8 el op0 op1 CRn op2 CRm)" + by (unfold VPIDR_EL2_SysRegRead_f6520cd6a1f62bd8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VSESR_EL2_SysRegRead_401c063e57574698[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VSESR_EL2_SysRegRead_401c063e57574698 el op0 op1 CRn op2 CRm)" + by (unfold VSESR_EL2_SysRegRead_401c063e57574698_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VTCR_EL2_SysRegRead_5c8ea980dc5cc1d1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VTCR_EL2_SysRegRead_5c8ea980dc5cc1d1 el op0 op1 CRn op2 CRm)" + by (unfold VTCR_EL2_SysRegRead_5c8ea980dc5cc1d1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VTTBR_EL2_SysRegRead_2fbbdccc9485564d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VTTBR_EL2_SysRegRead_2fbbdccc9485564d el op0 op1 CRn op2 CRm)" + by (unfold VTTBR_EL2_SysRegRead_2fbbdccc9485564d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_AutoGen_SysRegRead[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_AutoGen_SysRegRead el op0 op1 CRn op2 CRm)" + by (unfold AArch64_AutoGen_SysRegRead_def bind_assoc, no_reg_writes_toI intro: no_reg_writes_to_if_no_asm) + +lemma no_reg_writes_to_AArch64_SysRegRead[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_SysRegRead op0 op1 crn crm op2)" + by (unfold AArch64_SysRegRead_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34 el op0 op1 CRn op2 CRm)" + by (unfold CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CDLR_EL0_CapSysRegRead_619c852c71c0978d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CDLR_EL0_CapSysRegRead_619c852c71c0978d el op0 op1 CRn op2 CRm)" + by (unfold CDLR_EL0_CapSysRegRead_619c852c71c0978d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CELR_EL12_CapSysRegRead_4bf271777fe55d1c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CELR_EL12_CapSysRegRead_4bf271777fe55d1c el op0 op1 CRn op2 CRm)" + by (unfold CELR_EL12_CapSysRegRead_4bf271777fe55d1c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CELR_EL1_CapSysRegRead_da9869d2314a30d5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CELR_EL1_CapSysRegRead_da9869d2314a30d5 el op0 op1 CRn op2 CRm)" + by (unfold CELR_EL1_CapSysRegRead_da9869d2314a30d5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CELR_EL2_CapSysRegRead_a9e9661da428a6d4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CELR_EL2_CapSysRegRead_a9e9661da428a6d4 el op0 op1 CRn op2 CRm)" + by (unfold CELR_EL2_CapSysRegRead_a9e9661da428a6d4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CELR_EL3_CapSysRegRead_d0424a232c45967e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CELR_EL3_CapSysRegRead_d0424a232c45967e el op0 op1 CRn op2 CRm)" + by (unfold CELR_EL3_CapSysRegRead_d0424a232c45967e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CID_EL0_CapSysRegRead_d560f6b1104266f1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CID_EL0_CapSysRegRead_d560f6b1104266f1 el op0 op1 CRn op2 CRm)" + by (unfold CID_EL0_CapSysRegRead_d560f6b1104266f1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CSP_EL0_CapSysRegRead_e5b1ba121f8be4da[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CSP_EL0_CapSysRegRead_e5b1ba121f8be4da el op0 op1 CRn op2 CRm)" + by (unfold CSP_EL0_CapSysRegRead_e5b1ba121f8be4da_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb el op0 op1 CRn op2 CRm)" + by (unfold CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CSP_EL2_CapSysRegRead_9b50d2f92d5520da[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CSP_EL2_CapSysRegRead_9b50d2f92d5520da el op0 op1 CRn op2 CRm)" + by (unfold CSP_EL2_CapSysRegRead_9b50d2f92d5520da_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc el op0 op1 CRn op2 CRm)" + by (unfold CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CTPIDR_EL0_CapSysRegRead_84b933ea55a77369[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CTPIDR_EL0_CapSysRegRead_84b933ea55a77369 el op0 op1 CRn op2 CRm)" + by (unfold CTPIDR_EL0_CapSysRegRead_84b933ea55a77369_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CTPIDR_EL1_CapSysRegRead_016308c12b886084[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CTPIDR_EL1_CapSysRegRead_016308c12b886084 el op0 op1 CRn op2 CRm)" + by (unfold CTPIDR_EL1_CapSysRegRead_016308c12b886084_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544 el op0 op1 CRn op2 CRm)" + by (unfold CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449 el op0 op1 CRn op2 CRm)" + by (unfold CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVBAR_EL12_CapSysRegRead_845c94ac498ff593[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CVBAR_EL12_CapSysRegRead_845c94ac498ff593 el op0 op1 CRn op2 CRm)" + by (unfold CVBAR_EL12_CapSysRegRead_845c94ac498ff593_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVBAR_EL1_CapSysRegRead_c42109445741a0d0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CVBAR_EL1_CapSysRegRead_c42109445741a0d0 el op0 op1 CRn op2 CRm)" + by (unfold CVBAR_EL1_CapSysRegRead_c42109445741a0d0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVBAR_EL2_CapSysRegRead_537232bbd7d69e00[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CVBAR_EL2_CapSysRegRead_537232bbd7d69e00 el op0 op1 CRn op2 CRm)" + by (unfold CVBAR_EL2_CapSysRegRead_537232bbd7d69e00_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1 el op0 op1 CRn op2 CRm)" + by (unfold CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DDC_CapSysRegRead_eabc4ea34a10a962[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DDC_CapSysRegRead_eabc4ea34a10a962 el op0 op1 CRn op2 CRm)" + by (unfold DDC_CapSysRegRead_eabc4ea34a10a962_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DDC_EL0_CapSysRegRead_e02bc676dce7fb51[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DDC_EL0_CapSysRegRead_e02bc676dce7fb51 el op0 op1 CRn op2 CRm)" + by (unfold DDC_EL0_CapSysRegRead_e02bc676dce7fb51_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DDC_EL1_CapSysRegRead_08f46354e9afc01e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DDC_EL1_CapSysRegRead_08f46354e9afc01e el op0 op1 CRn op2 CRm)" + by (unfold DDC_EL1_CapSysRegRead_08f46354e9afc01e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DDC_EL2_CapSysRegRead_6d2409222a719403[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DDC_EL2_CapSysRegRead_6d2409222a719403 el op0 op1 CRn op2 CRm)" + by (unfold DDC_EL2_CapSysRegRead_6d2409222a719403_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RCSP_EL0_CapSysRegRead_6a9b29b9027548c3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RCSP_EL0_CapSysRegRead_6a9b29b9027548c3 el op0 op1 CRn op2 CRm)" + by (unfold RCSP_EL0_CapSysRegRead_6a9b29b9027548c3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7 el op0 op1 CRn op2 CRm)" + by (unfold RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RDDC_EL0_CapSysRegRead_c188e736aa7b9beb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RDDC_EL0_CapSysRegRead_c188e736aa7b9beb el op0 op1 CRn op2 CRm)" + by (unfold RDDC_EL0_CapSysRegRead_c188e736aa7b9beb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_AutoGen_CapSysRegRead[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_AutoGen_CapSysRegRead el op0 op1 CRn op2 CRm)" + by (unfold AArch64_AutoGen_CapSysRegRead_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DDC_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DDC_read arg0)" + by (unfold DDC_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CapSysRegRead[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CapSysRegRead op0 op1 crn crm op2)" + by (unfold AArch64_CapSysRegRead_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ACTLR_EL1_SysRegWrite_338051dbe9bdf650[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ACTLR_EL1_SysRegWrite_338051dbe9bdf650 el op0 op1 CRn op2 CRm val_name)" + by (unfold ACTLR_EL1_SysRegWrite_338051dbe9bdf650_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ACTLR_EL2_SysRegWrite_416ec7c6fadd122d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ACTLR_EL2_SysRegWrite_416ec7c6fadd122d el op0 op1 CRn op2 CRm val_name)" + by (unfold ACTLR_EL2_SysRegWrite_416ec7c6fadd122d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ACTLR_EL3_SysRegWrite_c797d5a80525afa4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ACTLR_EL3_SysRegWrite_c797d5a80525afa4 el op0 op1 CRn op2 CRm val_name)" + by (unfold ACTLR_EL3_SysRegWrite_c797d5a80525afa4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR0_EL12_SysRegWrite_9fafb4f6dbddd904[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR0_EL12_SysRegWrite_9fafb4f6dbddd904 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR0_EL12_SysRegWrite_9fafb4f6dbddd904_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR0_EL1_SysRegWrite_04474930979e1c86[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR0_EL1_SysRegWrite_04474930979e1c86 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR0_EL1_SysRegWrite_04474930979e1c86_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR0_EL2_SysRegWrite_2f9da4789f5b4073[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR0_EL2_SysRegWrite_2f9da4789f5b4073 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR0_EL2_SysRegWrite_2f9da4789f5b4073_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR0_EL3_SysRegWrite_e615501306210a25[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR0_EL3_SysRegWrite_e615501306210a25 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR0_EL3_SysRegWrite_e615501306210a25_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR1_EL12_SysRegWrite_9dbf207cccd92d9d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR1_EL12_SysRegWrite_9dbf207cccd92d9d el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR1_EL12_SysRegWrite_9dbf207cccd92d9d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR1_EL1_SysRegWrite_6690138c9fdd136c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR1_EL1_SysRegWrite_6690138c9fdd136c el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR1_EL1_SysRegWrite_6690138c9fdd136c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR1_EL2_SysRegWrite_c0ebc4cc65472544[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR1_EL2_SysRegWrite_c0ebc4cc65472544 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR1_EL2_SysRegWrite_c0ebc4cc65472544_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AFSR1_EL3_SysRegWrite_d776cc264803f49e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AFSR1_EL3_SysRegWrite_d776cc264803f49e el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR1_EL3_SysRegWrite_d776cc264803f49e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AMAIR_EL12_SysRegWrite_9c44aba2de7c2ff8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AMAIR_EL12_SysRegWrite_9c44aba2de7c2ff8 el op0 op1 CRn op2 CRm val_name)" + by (unfold AMAIR_EL12_SysRegWrite_9c44aba2de7c2ff8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AMAIR_EL1_SysRegWrite_0d9c3d92d9a71703[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AMAIR_EL1_SysRegWrite_0d9c3d92d9a71703 el op0 op1 CRn op2 CRm val_name)" + by (unfold AMAIR_EL1_SysRegWrite_0d9c3d92d9a71703_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AMAIR_EL2_SysRegWrite_9345da970d78b298[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AMAIR_EL2_SysRegWrite_9345da970d78b298 el op0 op1 CRn op2 CRm val_name)" + by (unfold AMAIR_EL2_SysRegWrite_9345da970d78b298_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AMAIR_EL3_SysRegWrite_622c473bfedac80a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AMAIR_EL3_SysRegWrite_622c473bfedac80a el op0 op1 CRn op2 CRm val_name)" + by (unfold AMAIR_EL3_SysRegWrite_622c473bfedac80a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CCTLR_EL0_SysRegWrite_a4d8c57cb436292b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CCTLR_EL0_SysRegWrite_a4d8c57cb436292b el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL0_SysRegWrite_a4d8c57cb436292b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CCTLR_EL12_SysRegWrite_c7d9d6463096d910[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CCTLR_EL12_SysRegWrite_c7d9d6463096d910 el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL12_SysRegWrite_c7d9d6463096d910_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CCTLR_EL1_SysRegWrite_dc20ad2a867ac9bf[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CCTLR_EL1_SysRegWrite_dc20ad2a867ac9bf el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL1_SysRegWrite_dc20ad2a867ac9bf_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CCTLR_EL2_SysRegWrite_65620c8ccb1113a5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CCTLR_EL2_SysRegWrite_65620c8ccb1113a5 el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL2_SysRegWrite_65620c8ccb1113a5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CCTLR_EL3_SysRegWrite_f5e936c8846e6fc7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CCTLR_EL3_SysRegWrite_f5e936c8846e6fc7 el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL3_SysRegWrite_f5e936c8846e6fc7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CHCR_EL2_SysRegWrite_dadda8ecf053e448[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CHCR_EL2_SysRegWrite_dadda8ecf053e448 el op0 op1 CRn op2 CRm val_name)" + by (unfold CHCR_EL2_SysRegWrite_dadda8ecf053e448_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTFRQ_EL0_SysRegWrite_0fac77f077759456[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTFRQ_EL0_SysRegWrite_0fac77f077759456 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTFRQ_EL0_SysRegWrite_0fac77f077759456_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHCTL_EL2_SysRegWrite_eb0cbec9f9398e0e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHCTL_EL2_SysRegWrite_eb0cbec9f9398e0e el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHCTL_EL2_SysRegWrite_eb0cbec9f9398e0e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHP_CTL_EL2_SysRegWrite_92034fc54290a7b8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHP_CTL_EL2_SysRegWrite_92034fc54290a7b8 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHP_CTL_EL2_SysRegWrite_92034fc54290a7b8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHP_CVAL_EL2_SysRegWrite_36de219faded7cbc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHP_CVAL_EL2_SysRegWrite_36de219faded7cbc el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHP_CVAL_EL2_SysRegWrite_36de219faded7cbc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHP_TVAL_EL2_SysRegWrite_877bbf4f78f810b9[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHP_TVAL_EL2_SysRegWrite_877bbf4f78f810b9 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHP_TVAL_EL2_SysRegWrite_877bbf4f78f810b9_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHV_CTL_EL2_SysRegWrite_ecc786a588fc8ab9[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHV_CTL_EL2_SysRegWrite_ecc786a588fc8ab9 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHV_CTL_EL2_SysRegWrite_ecc786a588fc8ab9_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHV_CVAL_EL2_SysRegWrite_b3d7c631e2b3eaab[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHV_CVAL_EL2_SysRegWrite_b3d7c631e2b3eaab el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHV_CVAL_EL2_SysRegWrite_b3d7c631e2b3eaab_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTHV_TVAL_EL2_SysRegWrite_e215d12d330397f1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTHV_TVAL_EL2_SysRegWrite_e215d12d330397f1 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHV_TVAL_EL2_SysRegWrite_e215d12d330397f1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTKCTL_EL12_SysRegWrite_518123f17a6402e4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTKCTL_EL12_SysRegWrite_518123f17a6402e4 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTKCTL_EL12_SysRegWrite_518123f17a6402e4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTKCTL_EL1_SysRegWrite_9a7be69aa33bb9c2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTKCTL_EL1_SysRegWrite_9a7be69aa33bb9c2 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTKCTL_EL1_SysRegWrite_9a7be69aa33bb9c2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTPS_CTL_EL1_SysRegWrite_a0625fd9f7b035a8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTPS_CTL_EL1_SysRegWrite_a0625fd9f7b035a8 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTPS_CTL_EL1_SysRegWrite_a0625fd9f7b035a8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTPS_CVAL_EL1_SysRegWrite_f09243080b7c260d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTPS_CVAL_EL1_SysRegWrite_f09243080b7c260d el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTPS_CVAL_EL1_SysRegWrite_f09243080b7c260d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTPS_TVAL_EL1_SysRegWrite_a9b16e60037fa746[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTPS_TVAL_EL1_SysRegWrite_a9b16e60037fa746 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTPS_TVAL_EL1_SysRegWrite_a9b16e60037fa746_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTP_CTL_EL02_SysRegWrite_99a9da3e2454714e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTP_CTL_EL02_SysRegWrite_99a9da3e2454714e el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_CTL_EL02_SysRegWrite_99a9da3e2454714e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTP_CTL_EL0_SysRegWrite_137f81090c1357e6[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTP_CTL_EL0_SysRegWrite_137f81090c1357e6 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_CTL_EL0_SysRegWrite_137f81090c1357e6_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTP_CVAL_EL02_SysRegWrite_2b3e9ccfce186a4f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTP_CVAL_EL02_SysRegWrite_2b3e9ccfce186a4f el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_CVAL_EL02_SysRegWrite_2b3e9ccfce186a4f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTP_CVAL_EL0_SysRegWrite_d54c08ee0cf9aaf7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTP_CVAL_EL0_SysRegWrite_d54c08ee0cf9aaf7 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_CVAL_EL0_SysRegWrite_d54c08ee0cf9aaf7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTP_TVAL_EL02_SysRegWrite_caa9f2aa73cb6b96[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTP_TVAL_EL02_SysRegWrite_caa9f2aa73cb6b96 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_TVAL_EL02_SysRegWrite_caa9f2aa73cb6b96_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTP_TVAL_EL0_SysRegWrite_d7441eec23c3d524[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTP_TVAL_EL0_SysRegWrite_d7441eec23c3d524 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_TVAL_EL0_SysRegWrite_d7441eec23c3d524_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTVOFF_EL2_SysRegWrite_621ada4cfda60bcb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTVOFF_EL2_SysRegWrite_621ada4cfda60bcb el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTVOFF_EL2_SysRegWrite_621ada4cfda60bcb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTV_CTL_EL02_SysRegWrite_d6cac9cc52dd8fec[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTV_CTL_EL02_SysRegWrite_d6cac9cc52dd8fec el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_CTL_EL02_SysRegWrite_d6cac9cc52dd8fec_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTV_CTL_EL0_SysRegWrite_e9fd22bae4b06064[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTV_CTL_EL0_SysRegWrite_e9fd22bae4b06064 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_CTL_EL0_SysRegWrite_e9fd22bae4b06064_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTV_CVAL_EL02_SysRegWrite_7548964ed28b5abb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTV_CVAL_EL02_SysRegWrite_7548964ed28b5abb el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_CVAL_EL02_SysRegWrite_7548964ed28b5abb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTV_CVAL_EL0_SysRegWrite_f237c5c94ec92951[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTV_CVAL_EL0_SysRegWrite_f237c5c94ec92951 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_CVAL_EL0_SysRegWrite_f237c5c94ec92951_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTV_TVAL_EL02_SysRegWrite_dc97f79a5f74078f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTV_TVAL_EL02_SysRegWrite_dc97f79a5f74078f el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_TVAL_EL02_SysRegWrite_dc97f79a5f74078f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CNTV_TVAL_EL0_SysRegWrite_903191acca729cda[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CNTV_TVAL_EL0_SysRegWrite_903191acca729cda el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_TVAL_EL0_SysRegWrite_903191acca729cda_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CONTEXTIDR_EL12_SysRegWrite_33154953ae1b01d5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CONTEXTIDR_EL12_SysRegWrite_33154953ae1b01d5 el op0 op1 CRn op2 CRm val_name)" + by (unfold CONTEXTIDR_EL12_SysRegWrite_33154953ae1b01d5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CONTEXTIDR_EL1_SysRegWrite_5408e4e72af4e23d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CONTEXTIDR_EL1_SysRegWrite_5408e4e72af4e23d el op0 op1 CRn op2 CRm val_name)" + by (unfold CONTEXTIDR_EL1_SysRegWrite_5408e4e72af4e23d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CONTEXTIDR_EL2_SysRegWrite_27187b6dc7c5a748[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CONTEXTIDR_EL2_SysRegWrite_27187b6dc7c5a748 el op0 op1 CRn op2 CRm val_name)" + by (unfold CONTEXTIDR_EL2_SysRegWrite_27187b6dc7c5a748_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CPACR_EL12_SysRegWrite_637092a999939f8b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CPACR_EL12_SysRegWrite_637092a999939f8b el op0 op1 CRn op2 CRm val_name)" + by (unfold CPACR_EL12_SysRegWrite_637092a999939f8b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CPACR_EL1_SysRegWrite_00878a1f3e87823c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CPACR_EL1_SysRegWrite_00878a1f3e87823c el op0 op1 CRn op2 CRm val_name)" + by (unfold CPACR_EL1_SysRegWrite_00878a1f3e87823c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CPTR_EL2_SysRegWrite_5a082f460b1b2308[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CPTR_EL2_SysRegWrite_5a082f460b1b2308 el op0 op1 CRn op2 CRm val_name)" + by (unfold CPTR_EL2_SysRegWrite_5a082f460b1b2308_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CPTR_EL3_SysRegWrite_879d4b1bad53408b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CPTR_EL3_SysRegWrite_879d4b1bad53408b el op0 op1 CRn op2 CRm val_name)" + by (unfold CPTR_EL3_SysRegWrite_879d4b1bad53408b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CSCR_EL3_SysRegWrite_22b95c83b04d6c91[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CSCR_EL3_SysRegWrite_22b95c83b04d6c91 el op0 op1 CRn op2 CRm val_name)" + by (unfold CSCR_EL3_SysRegWrite_22b95c83b04d6c91_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CSSELR_EL1_SysRegWrite_1f9e1e0300c8783c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CSSELR_EL1_SysRegWrite_1f9e1e0300c8783c el op0 op1 CRn op2 CRm val_name)" + by (unfold CSSELR_EL1_SysRegWrite_1f9e1e0300c8783c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DACR32_EL2_SysRegWrite_a8bad0131817f121[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DACR32_EL2_SysRegWrite_a8bad0131817f121 el op0 op1 CRn op2 CRm val_name)" + by (unfold DACR32_EL2_SysRegWrite_a8bad0131817f121_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DAIF_SysRegWrite_3d31f214debf624b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DAIF_SysRegWrite_3d31f214debf624b el op0 op1 CRn op2 CRm val_name)" + by (unfold DAIF_SysRegWrite_3d31f214debf624b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGBCR_EL1_SysRegWrite_6730f3e3839510c5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGBCR_EL1_SysRegWrite_6730f3e3839510c5 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGBCR_EL1_SysRegWrite_6730f3e3839510c5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGCLAIMCLR_EL1_SysRegWrite_2a099a67767e57cf[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGCLAIMCLR_EL1_SysRegWrite_2a099a67767e57cf el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGCLAIMCLR_EL1_SysRegWrite_2a099a67767e57cf_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGCLAIMSET_EL1_SysRegWrite_90e355b6a5730770[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGCLAIMSET_EL1_SysRegWrite_90e355b6a5730770 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGCLAIMSET_EL1_SysRegWrite_90e355b6a5730770_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGDTRTX_EL0_SysRegWrite_057e8c91e001a69f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGDTRTX_EL0_SysRegWrite_057e8c91e001a69f el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGDTRTX_EL0_SysRegWrite_057e8c91e001a69f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGDTR_EL0_write[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGDTR_EL0_write val_name)" + by (unfold DBGDTR_EL0_write_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGDTR_EL0_SysRegWrite_c7246a22e06c7729[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGDTR_EL0_SysRegWrite_c7246a22e06c7729 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGDTR_EL0_SysRegWrite_c7246a22e06c7729_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGPRCR_EL1_SysRegWrite_710b60256172548e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGPRCR_EL1_SysRegWrite_710b60256172548e el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGPRCR_EL1_SysRegWrite_710b60256172548e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGVCR32_EL2_SysRegWrite_769fbfe4fa51a4e5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGVCR32_EL2_SysRegWrite_769fbfe4fa51a4e5 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGVCR32_EL2_SysRegWrite_769fbfe4fa51a4e5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGWCR_EL1_SysRegWrite_6bda3acb5910d354[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGWCR_EL1_SysRegWrite_6bda3acb5910d354 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGWCR_EL1_SysRegWrite_6bda3acb5910d354_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DBGWVR_EL1_SysRegWrite_745b296ee53305ea[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DBGWVR_EL1_SysRegWrite_745b296ee53305ea el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGWVR_EL1_SysRegWrite_745b296ee53305ea_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DISR_EL1_SysRegWrite_64517664b9260065[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DISR_EL1_SysRegWrite_64517664b9260065 el op0 op1 CRn op2 CRm val_name)" + by (unfold DISR_EL1_SysRegWrite_64517664b9260065_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DLR_EL0_write[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DLR_EL0_write val_name)" + by (unfold DLR_EL0_write_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DLR_EL0_SysRegWrite_a2d10a509fed3a63[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DLR_EL0_SysRegWrite_a2d10a509fed3a63 el op0 op1 CRn op2 CRm val_name)" + by (unfold DLR_EL0_SysRegWrite_a2d10a509fed3a63_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DSPSR_EL0_SysRegWrite_6d6dabfcb332ec05[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DSPSR_EL0_SysRegWrite_6d6dabfcb332ec05 el op0 op1 CRn op2 CRm val_name)" + by (unfold DSPSR_EL0_SysRegWrite_6d6dabfcb332ec05_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELR_EL12_SysRegWrite_6720e93c266dadea[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ELR_EL12_SysRegWrite_6720e93c266dadea el op0 op1 CRn op2 CRm val_name)" + by (unfold ELR_EL12_SysRegWrite_6720e93c266dadea_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELR_EL1_SysRegWrite_b6bd589b2dd79575[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ELR_EL1_SysRegWrite_b6bd589b2dd79575 el op0 op1 CRn op2 CRm val_name)" + by (unfold ELR_EL1_SysRegWrite_b6bd589b2dd79575_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELR_EL2_SysRegWrite_9f4ca59c1a88f1a9[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ELR_EL2_SysRegWrite_9f4ca59c1a88f1a9 el op0 op1 CRn op2 CRm val_name)" + by (unfold ELR_EL2_SysRegWrite_9f4ca59c1a88f1a9_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELR_EL3_SysRegWrite_8cd0b0c7f61ee7aa[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ELR_EL3_SysRegWrite_8cd0b0c7f61ee7aa el op0 op1 CRn op2 CRm val_name)" + by (unfold ELR_EL3_SysRegWrite_8cd0b0c7f61ee7aa_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERRSELR_EL1_SysRegWrite_551535eed30e26f9[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERRSELR_EL1_SysRegWrite_551535eed30e26f9 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERRSELR_EL1_SysRegWrite_551535eed30e26f9_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERXADDR_EL1_SysRegWrite_8a1eabc2959662e8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERXADDR_EL1_SysRegWrite_8a1eabc2959662e8 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXADDR_EL1_SysRegWrite_8a1eabc2959662e8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERXCTLR_EL1_SysRegWrite_acca1e102ba86b42[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERXCTLR_EL1_SysRegWrite_acca1e102ba86b42 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXCTLR_EL1_SysRegWrite_acca1e102ba86b42_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERXMISC0_EL1_SysRegWrite_822ceca9b10b2621[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERXMISC0_EL1_SysRegWrite_822ceca9b10b2621 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXMISC0_EL1_SysRegWrite_822ceca9b10b2621_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERXMISC1_EL1_SysRegWrite_9a9ef77b5fd82587[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERXMISC1_EL1_SysRegWrite_9a9ef77b5fd82587 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXMISC1_EL1_SysRegWrite_9a9ef77b5fd82587_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ERXSTATUS_EL1_SysRegWrite_f0798b4207ec0193[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ERXSTATUS_EL1_SysRegWrite_f0798b4207ec0193 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXSTATUS_EL1_SysRegWrite_f0798b4207ec0193_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ESR_EL12_SysRegWrite_2b2d6012ba438548[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ESR_EL12_SysRegWrite_2b2d6012ba438548 el op0 op1 CRn op2 CRm val_name)" + by (unfold ESR_EL12_SysRegWrite_2b2d6012ba438548_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ESR_EL1_SysRegWrite_a8ce40896bd70a6b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ESR_EL1_SysRegWrite_a8ce40896bd70a6b el op0 op1 CRn op2 CRm val_name)" + by (unfold ESR_EL1_SysRegWrite_a8ce40896bd70a6b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ESR_EL2_SysRegWrite_a10e84e3bd1020c8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ESR_EL2_SysRegWrite_a10e84e3bd1020c8 el op0 op1 CRn op2 CRm val_name)" + by (unfold ESR_EL2_SysRegWrite_a10e84e3bd1020c8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ESR_EL3_SysRegWrite_195a2e1a5b40464e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ESR_EL3_SysRegWrite_195a2e1a5b40464e el op0 op1 CRn op2 CRm val_name)" + by (unfold ESR_EL3_SysRegWrite_195a2e1a5b40464e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FAR_EL12_SysRegWrite_78f825940e556299[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FAR_EL12_SysRegWrite_78f825940e556299 el op0 op1 CRn op2 CRm val_name)" + by (unfold FAR_EL12_SysRegWrite_78f825940e556299_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FAR_EL1_SysRegWrite_fc0bd224b62cc089[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FAR_EL1_SysRegWrite_fc0bd224b62cc089 el op0 op1 CRn op2 CRm val_name)" + by (unfold FAR_EL1_SysRegWrite_fc0bd224b62cc089_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FAR_EL2_SysRegWrite_6370aabce83a1613[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FAR_EL2_SysRegWrite_6370aabce83a1613 el op0 op1 CRn op2 CRm val_name)" + by (unfold FAR_EL2_SysRegWrite_6370aabce83a1613_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FAR_EL3_SysRegWrite_397cfda85a093e9d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FAR_EL3_SysRegWrite_397cfda85a093e9d el op0 op1 CRn op2 CRm val_name)" + by (unfold FAR_EL3_SysRegWrite_397cfda85a093e9d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPCR_SysRegWrite_4f255cf55390cebb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPCR_SysRegWrite_4f255cf55390cebb el op0 op1 CRn op2 CRm val_name)" + by (unfold FPCR_SysRegWrite_4f255cf55390cebb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPEXC32_EL2_SysRegWrite_9f180ead5c4d6735[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPEXC32_EL2_SysRegWrite_9f180ead5c4d6735 el op0 op1 CRn op2 CRm val_name)" + by (unfold FPEXC32_EL2_SysRegWrite_9f180ead5c4d6735_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPSR_SysRegWrite_413aed98a94900de[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPSR_SysRegWrite_413aed98a94900de el op0 op1 CRn op2 CRm val_name)" + by (unfold FPSR_SysRegWrite_413aed98a94900de_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HACR_EL2_SysRegWrite_5b2ca32fcb39ecab[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (HACR_EL2_SysRegWrite_5b2ca32fcb39ecab el op0 op1 CRn op2 CRm val_name)" + by (unfold HACR_EL2_SysRegWrite_5b2ca32fcb39ecab_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HCR_EL2_SysRegWrite_6fc18e07a17fd5a2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (HCR_EL2_SysRegWrite_6fc18e07a17fd5a2 el op0 op1 CRn op2 CRm val_name)" + by (unfold HCR_EL2_SysRegWrite_6fc18e07a17fd5a2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HPFAR_EL2_SysRegWrite_20417eccdd6b4768[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (HPFAR_EL2_SysRegWrite_20417eccdd6b4768 el op0 op1 CRn op2 CRm val_name)" + by (unfold HPFAR_EL2_SysRegWrite_20417eccdd6b4768_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HSTR_EL2_SysRegWrite_391a605c0bfb9d1e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (HSTR_EL2_SysRegWrite_391a605c0bfb9d1e el op0 op1 CRn op2 CRm val_name)" + by (unfold HSTR_EL2_SysRegWrite_391a605c0bfb9d1e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_AP0R_EL1_SysRegWrite_949897f971748acc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_AP0R_EL1_SysRegWrite_949897f971748acc el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_AP0R_EL1_SysRegWrite_949897f971748acc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_AP1R_EL1_SysRegWrite_55167410f7650dea[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_AP1R_EL1_SysRegWrite_55167410f7650dea el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_AP1R_EL1_SysRegWrite_55167410f7650dea_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_ASGI1R_EL1_SysRegWrite_c163c25adc1b1354[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_ASGI1R_EL1_SysRegWrite_c163c25adc1b1354 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_ASGI1R_EL1_SysRegWrite_c163c25adc1b1354_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_BPR0_EL1_SysRegWrite_10028206553f3655[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_BPR0_EL1_SysRegWrite_10028206553f3655 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_BPR0_EL1_SysRegWrite_10028206553f3655_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_BPR1_EL1_write[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_BPR1_EL1_write val_name)" + by (unfold ICC_BPR1_EL1_write_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_BPR1_EL1_SysRegWrite_a633b2e9f3626d9b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_BPR1_EL1_SysRegWrite_a633b2e9f3626d9b el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_BPR1_EL1_SysRegWrite_a633b2e9f3626d9b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_CTLR_EL1_write[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_CTLR_EL1_write val_name)" + by (unfold ICC_CTLR_EL1_write_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_CTLR_EL1_SysRegWrite_8ec3f4b67393eba8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_CTLR_EL1_SysRegWrite_8ec3f4b67393eba8 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_CTLR_EL1_SysRegWrite_8ec3f4b67393eba8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_CTLR_EL3_SysRegWrite_ecc8b41b177c53e8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_CTLR_EL3_SysRegWrite_ecc8b41b177c53e8 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_CTLR_EL3_SysRegWrite_ecc8b41b177c53e8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_DIR_EL1_SysRegWrite_77fadeda7efde9c5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_DIR_EL1_SysRegWrite_77fadeda7efde9c5 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_DIR_EL1_SysRegWrite_77fadeda7efde9c5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_EOIR0_EL1_SysRegWrite_9c0fae08cd7a2444[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_EOIR0_EL1_SysRegWrite_9c0fae08cd7a2444 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_EOIR0_EL1_SysRegWrite_9c0fae08cd7a2444_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_EOIR1_EL1_SysRegWrite_f065db56e179bf6e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_EOIR1_EL1_SysRegWrite_f065db56e179bf6e el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_EOIR1_EL1_SysRegWrite_f065db56e179bf6e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_IGRPEN0_EL1_SysRegWrite_b94e4d10f7a33382[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_IGRPEN0_EL1_SysRegWrite_b94e4d10f7a33382 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_IGRPEN0_EL1_SysRegWrite_b94e4d10f7a33382_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_IGRPEN1_EL1_write[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_IGRPEN1_EL1_write val_name)" + by (unfold ICC_IGRPEN1_EL1_write_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_IGRPEN1_EL1_SysRegWrite_c36dfa556252f6b4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_IGRPEN1_EL1_SysRegWrite_c36dfa556252f6b4 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_IGRPEN1_EL1_SysRegWrite_c36dfa556252f6b4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_IGRPEN1_EL3_SysRegWrite_6f1db000a53b40ca[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_IGRPEN1_EL3_SysRegWrite_6f1db000a53b40ca el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_IGRPEN1_EL3_SysRegWrite_6f1db000a53b40ca_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_PMR_EL1_SysRegWrite_8bb2caa31e7d5e1b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_PMR_EL1_SysRegWrite_8bb2caa31e7d5e1b el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_PMR_EL1_SysRegWrite_8bb2caa31e7d5e1b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_SGI0R_EL1_SysRegWrite_ba6d1066ea6fbbb7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_SGI0R_EL1_SysRegWrite_ba6d1066ea6fbbb7 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SGI0R_EL1_SysRegWrite_ba6d1066ea6fbbb7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_SGI1R_EL1_SysRegWrite_0da31fe6c2e1b098[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_SGI1R_EL1_SysRegWrite_0da31fe6c2e1b098 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SGI1R_EL1_SysRegWrite_0da31fe6c2e1b098_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_SRE_EL1_write[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_SRE_EL1_write val_name)" + by (unfold ICC_SRE_EL1_write_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_SRE_EL1_SysRegWrite_d2efb75caa67d019[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_SRE_EL1_SysRegWrite_d2efb75caa67d019 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SRE_EL1_SysRegWrite_d2efb75caa67d019_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_SRE_EL2_SysRegWrite_39c314f677b8ec2e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_SRE_EL2_SysRegWrite_39c314f677b8ec2e el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SRE_EL2_SysRegWrite_39c314f677b8ec2e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICC_SRE_EL3_SysRegWrite_c0af2dd58a7e1d22[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICC_SRE_EL3_SysRegWrite_c0af2dd58a7e1d22 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SRE_EL3_SysRegWrite_c0af2dd58a7e1d22_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_AP0R_EL2_SysRegWrite_9517857bb550d699[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_AP0R_EL2_SysRegWrite_9517857bb550d699 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_AP0R_EL2_SysRegWrite_9517857bb550d699_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_AP1R_EL2_SysRegWrite_20f46016b54a3395[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_AP1R_EL2_SysRegWrite_20f46016b54a3395 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_AP1R_EL2_SysRegWrite_20f46016b54a3395_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_HCR_EL2_SysRegWrite_2fea52a15cd7dbe5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_HCR_EL2_SysRegWrite_2fea52a15cd7dbe5 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_HCR_EL2_SysRegWrite_2fea52a15cd7dbe5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_LR_EL2_SysRegWrite_8b291f94259261d2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_LR_EL2_SysRegWrite_8b291f94259261d2 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_LR_EL2_SysRegWrite_8b291f94259261d2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ICH_VMCR_EL2_SysRegWrite_86a315374f6b5205[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ICH_VMCR_EL2_SysRegWrite_86a315374f6b5205 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_VMCR_EL2_SysRegWrite_86a315374f6b5205_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IFSR32_EL2_SysRegWrite_6ce25b2b11e30403[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (IFSR32_EL2_SysRegWrite_6ce25b2b11e30403 el op0 op1 CRn op2 CRm val_name)" + by (unfold IFSR32_EL2_SysRegWrite_6ce25b2b11e30403_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_LORC_EL1_SysRegWrite_7100b979c23fc52e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (LORC_EL1_SysRegWrite_7100b979c23fc52e el op0 op1 CRn op2 CRm val_name)" + by (unfold LORC_EL1_SysRegWrite_7100b979c23fc52e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_LOREA_EL1_SysRegWrite_2d068511b7f5ce7b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (LOREA_EL1_SysRegWrite_2d068511b7f5ce7b el op0 op1 CRn op2 CRm val_name)" + by (unfold LOREA_EL1_SysRegWrite_2d068511b7f5ce7b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_LORN_EL1_SysRegWrite_bde03c74e878b099[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (LORN_EL1_SysRegWrite_bde03c74e878b099 el op0 op1 CRn op2 CRm val_name)" + by (unfold LORN_EL1_SysRegWrite_bde03c74e878b099_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_LORSA_EL1_SysRegWrite_9ba633e967136731[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (LORSA_EL1_SysRegWrite_9ba633e967136731 el op0 op1 CRn op2 CRm val_name)" + by (unfold LORSA_EL1_SysRegWrite_9ba633e967136731_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MAIR_EL12_SysRegWrite_da2526ed2008ed50[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MAIR_EL12_SysRegWrite_da2526ed2008ed50 el op0 op1 CRn op2 CRm val_name)" + by (unfold MAIR_EL12_SysRegWrite_da2526ed2008ed50_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MAIR_EL1_SysRegWrite_45d8150aaf31e3b9[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MAIR_EL1_SysRegWrite_45d8150aaf31e3b9 el op0 op1 CRn op2 CRm val_name)" + by (unfold MAIR_EL1_SysRegWrite_45d8150aaf31e3b9_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MAIR_EL2_SysRegWrite_4e3422c1776528f5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MAIR_EL2_SysRegWrite_4e3422c1776528f5 el op0 op1 CRn op2 CRm val_name)" + by (unfold MAIR_EL2_SysRegWrite_4e3422c1776528f5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MAIR_EL3_SysRegWrite_d15af780e0b4e771[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MAIR_EL3_SysRegWrite_d15af780e0b4e771 el op0 op1 CRn op2 CRm val_name)" + by (unfold MAIR_EL3_SysRegWrite_d15af780e0b4e771_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MDCCINT_EL1_SysRegWrite_1e6a37984aec7145[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MDCCINT_EL1_SysRegWrite_1e6a37984aec7145 el op0 op1 CRn op2 CRm val_name)" + by (unfold MDCCINT_EL1_SysRegWrite_1e6a37984aec7145_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MDCR_EL2_SysRegWrite_3f12005c8c459bf3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MDCR_EL2_SysRegWrite_3f12005c8c459bf3 el op0 op1 CRn op2 CRm val_name)" + by (unfold MDCR_EL2_SysRegWrite_3f12005c8c459bf3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MDCR_EL3_SysRegWrite_37dff5fa83ad16ed[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MDCR_EL3_SysRegWrite_37dff5fa83ad16ed el op0 op1 CRn op2 CRm val_name)" + by (unfold MDCR_EL3_SysRegWrite_37dff5fa83ad16ed_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MDSCR_EL1_SysRegWrite_94ddb1e46aff4dfa[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MDSCR_EL1_SysRegWrite_94ddb1e46aff4dfa el op0 op1 CRn op2 CRm val_name)" + by (unfold MDSCR_EL1_SysRegWrite_94ddb1e46aff4dfa_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM0_EL1_SysRegWrite_88f6c0c61a59ac23[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAM0_EL1_SysRegWrite_88f6c0c61a59ac23 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM0_EL1_SysRegWrite_88f6c0c61a59ac23_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM2_EL2_write[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAM2_EL2_write val_name)" + by (unfold MPAM2_EL2_write_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM1_EL1_write[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAM1_EL1_write val_name)" + by (unfold MPAM1_EL1_write_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM1_EL12_SysRegWrite_2cbbb0edf5787671[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAM1_EL12_SysRegWrite_2cbbb0edf5787671 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM1_EL12_SysRegWrite_2cbbb0edf5787671_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM1_EL1_SysRegWrite_cd02720a3298b1c6[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAM1_EL1_SysRegWrite_cd02720a3298b1c6 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM1_EL1_SysRegWrite_cd02720a3298b1c6_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM2_EL2_SysRegWrite_d6bae8d18aebb554[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAM2_EL2_SysRegWrite_d6bae8d18aebb554 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM2_EL2_SysRegWrite_d6bae8d18aebb554_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAM3_EL3_SysRegWrite_bb55d8a9d90e05e3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAM3_EL3_SysRegWrite_bb55d8a9d90e05e3 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM3_EL3_SysRegWrite_bb55d8a9d90e05e3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMHCR_EL2_SysRegWrite_e38755d6111336b8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMHCR_EL2_SysRegWrite_e38755d6111336b8 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMHCR_EL2_SysRegWrite_e38755d6111336b8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM0_EL2_SysRegWrite_c00108111630aa84[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM0_EL2_SysRegWrite_c00108111630aa84 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM0_EL2_SysRegWrite_c00108111630aa84_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM1_EL2_SysRegWrite_81a739cc4bd1cd46[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM1_EL2_SysRegWrite_81a739cc4bd1cd46 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM1_EL2_SysRegWrite_81a739cc4bd1cd46_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM2_EL2_SysRegWrite_20a1b54bc18980b1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM2_EL2_SysRegWrite_20a1b54bc18980b1 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM2_EL2_SysRegWrite_20a1b54bc18980b1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM3_EL2_SysRegWrite_d2a71d8e23cc67af[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM3_EL2_SysRegWrite_d2a71d8e23cc67af el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM3_EL2_SysRegWrite_d2a71d8e23cc67af_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM4_EL2_SysRegWrite_2d0a10731399829d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM4_EL2_SysRegWrite_2d0a10731399829d el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM4_EL2_SysRegWrite_2d0a10731399829d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM5_EL2_SysRegWrite_ec98ca57d40ac9ec[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM5_EL2_SysRegWrite_ec98ca57d40ac9ec el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM5_EL2_SysRegWrite_ec98ca57d40ac9ec_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM6_EL2_SysRegWrite_0934853fee68e9bd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM6_EL2_SysRegWrite_0934853fee68e9bd el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM6_EL2_SysRegWrite_0934853fee68e9bd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPM7_EL2_SysRegWrite_dfb7f68750df7012[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPM7_EL2_SysRegWrite_dfb7f68750df7012 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM7_EL2_SysRegWrite_dfb7f68750df7012_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMVPMV_EL2_SysRegWrite_abd8d27e91fadf85[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MPAMVPMV_EL2_SysRegWrite_abd8d27e91fadf85 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPMV_EL2_SysRegWrite_abd8d27e91fadf85_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_NZCV_SysRegWrite_a047a536d32ae853[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (NZCV_SysRegWrite_a047a536d32ae853 el op0 op1 CRn op2 CRm val_name)" + by (unfold NZCV_SysRegWrite_a047a536d32ae853_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_OSDLR_EL1_SysRegWrite_591fd96d91652c64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (OSDLR_EL1_SysRegWrite_591fd96d91652c64 el op0 op1 CRn op2 CRm val_name)" + by (unfold OSDLR_EL1_SysRegWrite_591fd96d91652c64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_OSDTRRX_EL1_SysRegWrite_6dc5d8521b60df8a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (OSDTRRX_EL1_SysRegWrite_6dc5d8521b60df8a el op0 op1 CRn op2 CRm val_name)" + by (unfold OSDTRRX_EL1_SysRegWrite_6dc5d8521b60df8a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_OSDTRTX_EL1_SysRegWrite_9ba0c4a85d0c1de5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (OSDTRTX_EL1_SysRegWrite_9ba0c4a85d0c1de5 el op0 op1 CRn op2 CRm val_name)" + by (unfold OSDTRTX_EL1_SysRegWrite_9ba0c4a85d0c1de5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_OSECCR_EL1_SysRegWrite_cabf381bfb822732[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (OSECCR_EL1_SysRegWrite_cabf381bfb822732 el op0 op1 CRn op2 CRm val_name)" + by (unfold OSECCR_EL1_SysRegWrite_cabf381bfb822732_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_OSLAR_EL1_SysRegWrite_582d77c57653b2c4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (OSLAR_EL1_SysRegWrite_582d77c57653b2c4 el op0 op1 CRn op2 CRm val_name)" + by (unfold OSLAR_EL1_SysRegWrite_582d77c57653b2c4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PAN_SysRegWrite_aedbb13e40f0add0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PAN_SysRegWrite_aedbb13e40f0add0 el op0 op1 CRn op2 CRm val_name)" + by (unfold PAN_SysRegWrite_aedbb13e40f0add0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PAR_EL1_SysRegWrite_aa92c70a4b5d5873[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PAR_EL1_SysRegWrite_aa92c70a4b5d5873 el op0 op1 CRn op2 CRm val_name)" + by (unfold PAR_EL1_SysRegWrite_aa92c70a4b5d5873_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMBLIMITR_EL1_SysRegWrite_ddfe2ba603df6628[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMBLIMITR_EL1_SysRegWrite_ddfe2ba603df6628 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMBLIMITR_EL1_SysRegWrite_ddfe2ba603df6628_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMBPTR_EL1_SysRegWrite_32441d8a7a2b9601[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMBPTR_EL1_SysRegWrite_32441d8a7a2b9601 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMBPTR_EL1_SysRegWrite_32441d8a7a2b9601_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMBSR_EL1_SysRegWrite_ff19dc948509312f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMBSR_EL1_SysRegWrite_ff19dc948509312f el op0 op1 CRn op2 CRm val_name)" + by (unfold PMBSR_EL1_SysRegWrite_ff19dc948509312f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMCCFILTR_EL0_SysRegWrite_42277f001664525c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMCCFILTR_EL0_SysRegWrite_42277f001664525c el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCCFILTR_EL0_SysRegWrite_42277f001664525c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMCCNTR_EL0_SysRegWrite_1d21e0789830cbf9[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMCCNTR_EL0_SysRegWrite_1d21e0789830cbf9 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCCNTR_EL0_SysRegWrite_1d21e0789830cbf9_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMCNTENCLR_EL0_SysRegWrite_bf2c4fae1a891e1b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMCNTENCLR_EL0_SysRegWrite_bf2c4fae1a891e1b el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCNTENCLR_EL0_SysRegWrite_bf2c4fae1a891e1b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMCNTENSET_EL0_SysRegWrite_227af2773d320cb1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMCNTENSET_EL0_SysRegWrite_227af2773d320cb1 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCNTENSET_EL0_SysRegWrite_227af2773d320cb1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMCR_EL0_SysRegWrite_87ae64466e09f89a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMCR_EL0_SysRegWrite_87ae64466e09f89a el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCR_EL0_SysRegWrite_87ae64466e09f89a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMEVCNTR_EL0_SysRegWrite_c197579331ed9cbb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMEVCNTR_EL0_SysRegWrite_c197579331ed9cbb el op0 op1 CRn op2 CRm val_name)" + by (unfold PMEVCNTR_EL0_SysRegWrite_c197579331ed9cbb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMEVTYPER_EL0_SysRegWrite_3e6ae16cd645ec0d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMEVTYPER_EL0_SysRegWrite_3e6ae16cd645ec0d el op0 op1 CRn op2 CRm val_name)" + by (unfold PMEVTYPER_EL0_SysRegWrite_3e6ae16cd645ec0d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMINTENCLR_EL1_SysRegWrite_1ebd7bf3738fe872[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMINTENCLR_EL1_SysRegWrite_1ebd7bf3738fe872 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMINTENCLR_EL1_SysRegWrite_1ebd7bf3738fe872_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMINTENSET_EL1_SysRegWrite_dd2481ad892e3441[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMINTENSET_EL1_SysRegWrite_dd2481ad892e3441 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMINTENSET_EL1_SysRegWrite_dd2481ad892e3441_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMOVSCLR_EL0_SysRegWrite_9dfa73cda394af99[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMOVSCLR_EL0_SysRegWrite_9dfa73cda394af99 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMOVSCLR_EL0_SysRegWrite_9dfa73cda394af99_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMOVSSET_EL0_SysRegWrite_cfbbfe3b81fe4290[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMOVSSET_EL0_SysRegWrite_cfbbfe3b81fe4290 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMOVSSET_EL0_SysRegWrite_cfbbfe3b81fe4290_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSCR_EL12_SysRegWrite_fef9a94f50c2763b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSCR_EL12_SysRegWrite_fef9a94f50c2763b el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSCR_EL12_SysRegWrite_fef9a94f50c2763b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSCR_EL1_SysRegWrite_9798a89ab6804fe0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSCR_EL1_SysRegWrite_9798a89ab6804fe0 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSCR_EL1_SysRegWrite_9798a89ab6804fe0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSCR_EL2_SysRegWrite_02cd14dd325ed94b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSCR_EL2_SysRegWrite_02cd14dd325ed94b el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSCR_EL2_SysRegWrite_02cd14dd325ed94b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSELR_EL0_SysRegWrite_18613307de8564a3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSELR_EL0_SysRegWrite_18613307de8564a3 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSELR_EL0_SysRegWrite_18613307de8564a3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSEVFR_EL1_SysRegWrite_6524c56cd8a10057[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSEVFR_EL1_SysRegWrite_6524c56cd8a10057 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSEVFR_EL1_SysRegWrite_6524c56cd8a10057_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSFCR_EL1_SysRegWrite_44d58271848f0db1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSFCR_EL1_SysRegWrite_44d58271848f0db1 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSFCR_EL1_SysRegWrite_44d58271848f0db1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSICR_EL1_SysRegWrite_1e74423ea1c96ae7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSICR_EL1_SysRegWrite_1e74423ea1c96ae7 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSICR_EL1_SysRegWrite_1e74423ea1c96ae7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSIRR_EL1_SysRegWrite_bb25878486c35a36[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSIRR_EL1_SysRegWrite_bb25878486c35a36 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSIRR_EL1_SysRegWrite_bb25878486c35a36_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSLATFR_EL1_SysRegWrite_5c8b43a6a65c8272[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSLATFR_EL1_SysRegWrite_5c8b43a6a65c8272 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSLATFR_EL1_SysRegWrite_5c8b43a6a65c8272_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMSWINC_EL0_SysRegWrite_cce1d915b163d5e3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMSWINC_EL0_SysRegWrite_cce1d915b163d5e3 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSWINC_EL0_SysRegWrite_cce1d915b163d5e3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMUSERENR_EL0_SysRegWrite_e7535626e3360c36[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMUSERENR_EL0_SysRegWrite_e7535626e3360c36 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMUSERENR_EL0_SysRegWrite_e7535626e3360c36_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMXEVCNTR_EL0_SysRegWrite_20b0a6df43a7d4ef[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMXEVCNTR_EL0_SysRegWrite_20b0a6df43a7d4ef el op0 op1 CRn op2 CRm val_name)" + by (unfold PMXEVCNTR_EL0_SysRegWrite_20b0a6df43a7d4ef_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PMXEVTYPER_EL0_SysRegWrite_82fb55a6e723e983[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (PMXEVTYPER_EL0_SysRegWrite_82fb55a6e723e983 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMXEVTYPER_EL0_SysRegWrite_82fb55a6e723e983_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RMR_EL1_SysRegWrite_0ae19f794f511c7a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RMR_EL1_SysRegWrite_0ae19f794f511c7a el op0 op1 CRn op2 CRm val_name)" + by (unfold RMR_EL1_SysRegWrite_0ae19f794f511c7a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RMR_EL2_SysRegWrite_df7b9a989e2495d2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RMR_EL2_SysRegWrite_df7b9a989e2495d2 el op0 op1 CRn op2 CRm val_name)" + by (unfold RMR_EL2_SysRegWrite_df7b9a989e2495d2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RMR_EL3_SysRegWrite_2849130fc457929e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RMR_EL3_SysRegWrite_2849130fc457929e el op0 op1 CRn op2 CRm val_name)" + by (unfold RMR_EL3_SysRegWrite_2849130fc457929e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RSP_EL0_SysRegWrite_5b2edb6edd27507d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RSP_EL0_SysRegWrite_5b2edb6edd27507d el op0 op1 CRn op2 CRm val_name)" + by (unfold RSP_EL0_SysRegWrite_5b2edb6edd27507d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RTPIDR_EL0_SysRegWrite_74d55919bd0ab5f3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RTPIDR_EL0_SysRegWrite_74d55919bd0ab5f3 el op0 op1 CRn op2 CRm val_name)" + by (unfold RTPIDR_EL0_SysRegWrite_74d55919bd0ab5f3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S3_op1_CCn_CCm_op2_SysRegWrite_22dd63287f599042[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S3_op1_CCn_CCm_op2_SysRegWrite_22dd63287f599042 el op0 op1 CRn op2 CRm val_name)" + by (unfold S3_op1_CCn_CCm_op2_SysRegWrite_22dd63287f599042_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCR_EL3_SysRegWrite_020d082781fa9b72[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCR_EL3_SysRegWrite_020d082781fa9b72 el op0 op1 CRn op2 CRm val_name)" + by (unfold SCR_EL3_SysRegWrite_020d082781fa9b72_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCTLR_EL12_SysRegWrite_302de25977d2a0ca[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCTLR_EL12_SysRegWrite_302de25977d2a0ca el op0 op1 CRn op2 CRm val_name)" + by (unfold SCTLR_EL12_SysRegWrite_302de25977d2a0ca_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCTLR_EL1_SysRegWrite_711b0546c662c54d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCTLR_EL1_SysRegWrite_711b0546c662c54d el op0 op1 CRn op2 CRm val_name)" + by (unfold SCTLR_EL1_SysRegWrite_711b0546c662c54d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCTLR_EL2_SysRegWrite_ff61a6f00288b28a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCTLR_EL2_SysRegWrite_ff61a6f00288b28a el op0 op1 CRn op2 CRm val_name)" + by (unfold SCTLR_EL2_SysRegWrite_ff61a6f00288b28a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCTLR_EL3_SysRegWrite_5b7cc79e5ea93a8f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCTLR_EL3_SysRegWrite_5b7cc79e5ea93a8f el op0 op1 CRn op2 CRm val_name)" + by (unfold SCTLR_EL3_SysRegWrite_5b7cc79e5ea93a8f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCXTNUM_EL0_write[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCXTNUM_EL0_write val_name)" + by (unfold SCXTNUM_EL0_write_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCXTNUM_EL0_SysRegWrite_9dbee2793d69c02e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCXTNUM_EL0_SysRegWrite_9dbee2793d69c02e el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL0_SysRegWrite_9dbee2793d69c02e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCXTNUM_EL12_SysRegWrite_ba74367909393c9b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCXTNUM_EL12_SysRegWrite_ba74367909393c9b el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL12_SysRegWrite_ba74367909393c9b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCXTNUM_EL1_SysRegWrite_6467f6f26a31cece[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCXTNUM_EL1_SysRegWrite_6467f6f26a31cece el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL1_SysRegWrite_6467f6f26a31cece_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCXTNUM_EL2_SysRegWrite_2fcbb6503badb23c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCXTNUM_EL2_SysRegWrite_2fcbb6503badb23c el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL2_SysRegWrite_2fcbb6503badb23c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SCXTNUM_EL3_SysRegWrite_b39fe9ab09a67ecd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SCXTNUM_EL3_SysRegWrite_b39fe9ab09a67ecd el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL3_SysRegWrite_b39fe9ab09a67ecd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SDER32_EL3_SysRegWrite_69011ff5e95ac923[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SDER32_EL3_SysRegWrite_69011ff5e95ac923 el op0 op1 CRn op2 CRm val_name)" + by (unfold SDER32_EL3_SysRegWrite_69011ff5e95ac923_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_EL12_SysRegWrite_cabdb902efd62924[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SPSR_EL12_SysRegWrite_cabdb902efd62924 el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_EL12_SysRegWrite_cabdb902efd62924_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_EL1_SysRegWrite_c3a982c3130dcaea[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SPSR_EL1_SysRegWrite_c3a982c3130dcaea el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_EL1_SysRegWrite_c3a982c3130dcaea_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_EL2_SysRegWrite_1d65bd974e988727[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SPSR_EL2_SysRegWrite_1d65bd974e988727 el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_EL2_SysRegWrite_1d65bd974e988727_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_EL3_SysRegWrite_7b0326ec9be492f4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SPSR_EL3_SysRegWrite_7b0326ec9be492f4 el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_EL3_SysRegWrite_7b0326ec9be492f4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_abt_SysRegWrite_ecb9f412e44a217b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SPSR_abt_SysRegWrite_ecb9f412e44a217b el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_abt_SysRegWrite_ecb9f412e44a217b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_fiq_SysRegWrite_760097483f6eab5e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SPSR_fiq_SysRegWrite_760097483f6eab5e el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_fiq_SysRegWrite_760097483f6eab5e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_irq_SysRegWrite_d42335013c288fbe[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SPSR_irq_SysRegWrite_d42335013c288fbe el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_irq_SysRegWrite_d42335013c288fbe_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_und_SysRegWrite_76485ab5b58e2a80[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SPSR_und_SysRegWrite_76485ab5b58e2a80 el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_und_SysRegWrite_76485ab5b58e2a80_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSel_SysRegWrite_c849e120e8533c8c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SPSel_SysRegWrite_c849e120e8533c8c el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSel_SysRegWrite_c849e120e8533c8c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SP_EL0_SysRegWrite_78f870c69d82f9e2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SP_EL0_SysRegWrite_78f870c69d82f9e2 el op0 op1 CRn op2 CRm val_name)" + by (unfold SP_EL0_SysRegWrite_78f870c69d82f9e2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SP_EL1_SysRegWrite_84ae51cf4bf77caa[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SP_EL1_SysRegWrite_84ae51cf4bf77caa el op0 op1 CRn op2 CRm val_name)" + by (unfold SP_EL1_SysRegWrite_84ae51cf4bf77caa_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SP_EL2_SysRegWrite_a29ffeac6d3856e5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SP_EL2_SysRegWrite_a29ffeac6d3856e5 el op0 op1 CRn op2 CRm val_name)" + by (unfold SP_EL2_SysRegWrite_a29ffeac6d3856e5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SSBS_SysRegWrite_e080097cffcde083[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SSBS_SysRegWrite_e080097cffcde083 el op0 op1 CRn op2 CRm val_name)" + by (unfold SSBS_SysRegWrite_e080097cffcde083_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TCR_EL12_SysRegWrite_64a7f44c6ddaa0f8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TCR_EL12_SysRegWrite_64a7f44c6ddaa0f8 el op0 op1 CRn op2 CRm val_name)" + by (unfold TCR_EL12_SysRegWrite_64a7f44c6ddaa0f8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TCR_EL1_SysRegWrite_c27e6fc190bb0f0b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TCR_EL1_SysRegWrite_c27e6fc190bb0f0b el op0 op1 CRn op2 CRm val_name)" + by (unfold TCR_EL1_SysRegWrite_c27e6fc190bb0f0b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TCR_EL2_SysRegWrite_5e38279a245750c4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TCR_EL2_SysRegWrite_5e38279a245750c4 el op0 op1 CRn op2 CRm val_name)" + by (unfold TCR_EL2_SysRegWrite_5e38279a245750c4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TCR_EL3_SysRegWrite_3b3587015a3d20f4[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TCR_EL3_SysRegWrite_3b3587015a3d20f4 el op0 op1 CRn op2 CRm val_name)" + by (unfold TCR_EL3_SysRegWrite_3b3587015a3d20f4_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TPIDRRO_EL0_SysRegWrite_20bedffb2581e57d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TPIDRRO_EL0_SysRegWrite_20bedffb2581e57d el op0 op1 CRn op2 CRm val_name)" + by (unfold TPIDRRO_EL0_SysRegWrite_20bedffb2581e57d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TPIDR_EL0_SysRegWrite_6b1ef76c828f0bf5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TPIDR_EL0_SysRegWrite_6b1ef76c828f0bf5 el op0 op1 CRn op2 CRm val_name)" + by (unfold TPIDR_EL0_SysRegWrite_6b1ef76c828f0bf5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TPIDR_EL1_SysRegWrite_566127c19bf948d1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TPIDR_EL1_SysRegWrite_566127c19bf948d1 el op0 op1 CRn op2 CRm val_name)" + by (unfold TPIDR_EL1_SysRegWrite_566127c19bf948d1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TPIDR_EL2_SysRegWrite_adfab02a898d4b19[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TPIDR_EL2_SysRegWrite_adfab02a898d4b19 el op0 op1 CRn op2 CRm val_name)" + by (unfold TPIDR_EL2_SysRegWrite_adfab02a898d4b19_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TPIDR_EL3_SysRegWrite_08e0e9cc5d3f6f5c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TPIDR_EL3_SysRegWrite_08e0e9cc5d3f6f5c el op0 op1 CRn op2 CRm val_name)" + by (unfold TPIDR_EL3_SysRegWrite_08e0e9cc5d3f6f5c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR0_EL12_SysRegWrite_fd9df8519bfad5c0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR0_EL12_SysRegWrite_fd9df8519bfad5c0 el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR0_EL12_SysRegWrite_fd9df8519bfad5c0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR0_EL1_SysRegWrite_8a149790a79e2eab[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR0_EL1_SysRegWrite_8a149790a79e2eab el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR0_EL1_SysRegWrite_8a149790a79e2eab_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR0_EL2_SysRegWrite_7cd39d4a24a70e7f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR0_EL2_SysRegWrite_7cd39d4a24a70e7f el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR0_EL2_SysRegWrite_7cd39d4a24a70e7f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR0_EL3_SysRegWrite_7e091a8effc9ee7f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR0_EL3_SysRegWrite_7e091a8effc9ee7f el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR0_EL3_SysRegWrite_7e091a8effc9ee7f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR1_EL12_SysRegWrite_4fbeb1f28c2e8107[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR1_EL12_SysRegWrite_4fbeb1f28c2e8107 el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR1_EL12_SysRegWrite_4fbeb1f28c2e8107_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR1_EL1_SysRegWrite_89690e4d3c87217b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR1_EL1_SysRegWrite_89690e4d3c87217b el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR1_EL1_SysRegWrite_89690e4d3c87217b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TTBR1_EL2_SysRegWrite_59fad32bc548b47a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TTBR1_EL2_SysRegWrite_59fad32bc548b47a el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR1_EL2_SysRegWrite_59fad32bc548b47a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_UAO_SysRegWrite_594f371263b733f0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (UAO_SysRegWrite_594f371263b733f0 el op0 op1 CRn op2 CRm val_name)" + by (unfold UAO_SysRegWrite_594f371263b733f0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VBAR_EL12_SysRegWrite_a20f8f7f07b5cf7a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VBAR_EL12_SysRegWrite_a20f8f7f07b5cf7a el op0 op1 CRn op2 CRm val_name)" + by (unfold VBAR_EL12_SysRegWrite_a20f8f7f07b5cf7a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VBAR_EL1_SysRegWrite_29ba7540e032fce6[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VBAR_EL1_SysRegWrite_29ba7540e032fce6 el op0 op1 CRn op2 CRm val_name)" + by (unfold VBAR_EL1_SysRegWrite_29ba7540e032fce6_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VBAR_EL2_SysRegWrite_d5657e8591e8e22a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VBAR_EL2_SysRegWrite_d5657e8591e8e22a el op0 op1 CRn op2 CRm val_name)" + by (unfold VBAR_EL2_SysRegWrite_d5657e8591e8e22a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VBAR_EL3_SysRegWrite_1da603c27eb5f668[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VBAR_EL3_SysRegWrite_1da603c27eb5f668 el op0 op1 CRn op2 CRm val_name)" + by (unfold VBAR_EL3_SysRegWrite_1da603c27eb5f668_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VDISR_EL2_SysRegWrite_8b2c23874e253f64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VDISR_EL2_SysRegWrite_8b2c23874e253f64 el op0 op1 CRn op2 CRm val_name)" + by (unfold VDISR_EL2_SysRegWrite_8b2c23874e253f64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VMPIDR_EL2_SysRegWrite_c153d7c8b5628bd5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VMPIDR_EL2_SysRegWrite_c153d7c8b5628bd5 el op0 op1 CRn op2 CRm val_name)" + by (unfold VMPIDR_EL2_SysRegWrite_c153d7c8b5628bd5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VPIDR_EL2_SysRegWrite_0dbf139af5a73d1f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VPIDR_EL2_SysRegWrite_0dbf139af5a73d1f el op0 op1 CRn op2 CRm val_name)" + by (unfold VPIDR_EL2_SysRegWrite_0dbf139af5a73d1f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VSESR_EL2_SysRegWrite_e989f4bcf0ae8aa6[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VSESR_EL2_SysRegWrite_e989f4bcf0ae8aa6 el op0 op1 CRn op2 CRm val_name)" + by (unfold VSESR_EL2_SysRegWrite_e989f4bcf0ae8aa6_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VTCR_EL2_SysRegWrite_d49abb8b3aa0eff3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VTCR_EL2_SysRegWrite_d49abb8b3aa0eff3 el op0 op1 CRn op2 CRm val_name)" + by (unfold VTCR_EL2_SysRegWrite_d49abb8b3aa0eff3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VTTBR_EL2_SysRegWrite_5198ee0e793550a5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VTTBR_EL2_SysRegWrite_5198ee0e793550a5 el op0 op1 CRn op2 CRm val_name)" + by (unfold VTTBR_EL2_SysRegWrite_5198ee0e793550a5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_AutoGen_SysRegWrite[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_AutoGen_SysRegWrite el op0 op1 CRn op2 CRm val_name)" + by (unfold AArch64_AutoGen_SysRegWrite_def bind_assoc, no_reg_writes_toI intro: no_reg_writes_to_if_no_asm) + +lemma no_reg_writes_to_AArch64_IMPDEFResets[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_IMPDEFResets arg0)" + by (unfold AArch64_IMPDEFResets_def bind_assoc, no_reg_writes_toI intro: no_reg_writes_to_bindI_ignore_left) + +lemma no_reg_writes_to_AArch64_AutoGen_ArchitectureReset[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_AutoGen_ArchitectureReset cold)" + by (unfold AArch64_AutoGen_ArchitectureReset_def bind_assoc, no_reg_writes_toI intro: no_reg_writes_to_bindI_ignore_left) + +lemma no_reg_writes_to_AArch64_ResetControlRegisters[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_ResetControlRegisters cold)" + by (unfold AArch64_ResetControlRegisters_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_C_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (C_set n value_name)" + by (unfold C_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_ResetGeneralRegisters[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_ResetGeneralRegisters arg0)" + by (unfold AArch64_ResetGeneralRegisters_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_V_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (V_set width n value_name)" + by (unfold V_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_ResetSIMDFPRegisters[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_ResetSIMDFPRegisters arg0)" + by (unfold AArch64_ResetSIMDFPRegisters_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_ResetSpecialRegisters[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_ResetSpecialRegisters arg0)" + by (unfold AArch64_ResetSpecialRegisters_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PAMax[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (PAMax arg0)" + by (unfold PAMax_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_TakeReset[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_TakeReset cold_reset)" + by (unfold AArch64_TakeReset_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TakeReset[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TakeReset cold)" + by (unfold TakeReset_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_SysRegWrite[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_SysRegWrite op0 op1 crn crm op2 val_name)" + by (unfold AArch64_SysRegWrite_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CDBGDTR_EL0_CapSysRegWrite_336052f10e4a36b7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CDBGDTR_EL0_CapSysRegWrite_336052f10e4a36b7 el op0 op1 CRn op2 CRm val_name)" + by (unfold CDBGDTR_EL0_CapSysRegWrite_336052f10e4a36b7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CDLR_EL0_CapSysRegWrite_2763be7daadf3c03[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CDLR_EL0_CapSysRegWrite_2763be7daadf3c03 el op0 op1 CRn op2 CRm val_name)" + by (unfold CDLR_EL0_CapSysRegWrite_2763be7daadf3c03_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CELR_EL12_CapSysRegWrite_a1507df00ba9d725[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CELR_EL12_CapSysRegWrite_a1507df00ba9d725 el op0 op1 CRn op2 CRm val_name)" + by (unfold CELR_EL12_CapSysRegWrite_a1507df00ba9d725_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CELR_EL1_CapSysRegWrite_33a9b4f0fad89fe8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CELR_EL1_CapSysRegWrite_33a9b4f0fad89fe8 el op0 op1 CRn op2 CRm val_name)" + by (unfold CELR_EL1_CapSysRegWrite_33a9b4f0fad89fe8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CELR_EL2_CapSysRegWrite_8d32fe1dd5ad0417[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CELR_EL2_CapSysRegWrite_8d32fe1dd5ad0417 el op0 op1 CRn op2 CRm val_name)" + by (unfold CELR_EL2_CapSysRegWrite_8d32fe1dd5ad0417_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CELR_EL3_CapSysRegWrite_55e82fec5d907003[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CELR_EL3_CapSysRegWrite_55e82fec5d907003 el op0 op1 CRn op2 CRm val_name)" + by (unfold CELR_EL3_CapSysRegWrite_55e82fec5d907003_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CID_EL0_CapSysRegWrite_8c1c5cf69181759f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CID_EL0_CapSysRegWrite_8c1c5cf69181759f el op0 op1 CRn op2 CRm val_name)" + by (unfold CID_EL0_CapSysRegWrite_8c1c5cf69181759f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CSP_EL0_CapSysRegWrite_ee1d127810ef0f04[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CSP_EL0_CapSysRegWrite_ee1d127810ef0f04 el op0 op1 CRn op2 CRm val_name)" + by (unfold CSP_EL0_CapSysRegWrite_ee1d127810ef0f04_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CSP_EL1_CapSysRegWrite_f4579d836810c21a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CSP_EL1_CapSysRegWrite_f4579d836810c21a el op0 op1 CRn op2 CRm val_name)" + by (unfold CSP_EL1_CapSysRegWrite_f4579d836810c21a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CSP_EL2_CapSysRegWrite_59c69d74679ef283[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CSP_EL2_CapSysRegWrite_59c69d74679ef283 el op0 op1 CRn op2 CRm val_name)" + by (unfold CSP_EL2_CapSysRegWrite_59c69d74679ef283_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CTPIDRRO_EL0_CapSysRegWrite_e64109ff95ad4800[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CTPIDRRO_EL0_CapSysRegWrite_e64109ff95ad4800 el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDRRO_EL0_CapSysRegWrite_e64109ff95ad4800_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CTPIDR_EL0_CapSysRegWrite_8f94c4d256adadf0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CTPIDR_EL0_CapSysRegWrite_8f94c4d256adadf0 el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDR_EL0_CapSysRegWrite_8f94c4d256adadf0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CTPIDR_EL1_CapSysRegWrite_3190df090d2d128f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CTPIDR_EL1_CapSysRegWrite_3190df090d2d128f el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDR_EL1_CapSysRegWrite_3190df090d2d128f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CTPIDR_EL2_CapSysRegWrite_a740113e578c9b32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CTPIDR_EL2_CapSysRegWrite_a740113e578c9b32 el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDR_EL2_CapSysRegWrite_a740113e578c9b32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CTPIDR_EL3_CapSysRegWrite_376b7d525b15b21b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CTPIDR_EL3_CapSysRegWrite_376b7d525b15b21b el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDR_EL3_CapSysRegWrite_376b7d525b15b21b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVBAR_EL12_CapSysRegWrite_3fd157cf974c31e5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CVBAR_EL12_CapSysRegWrite_3fd157cf974c31e5 el op0 op1 CRn op2 CRm val_name)" + by (unfold CVBAR_EL12_CapSysRegWrite_3fd157cf974c31e5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVBAR_EL1_CapSysRegWrite_bbad0575f41fce2f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CVBAR_EL1_CapSysRegWrite_bbad0575f41fce2f el op0 op1 CRn op2 CRm val_name)" + by (unfold CVBAR_EL1_CapSysRegWrite_bbad0575f41fce2f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVBAR_EL2_CapSysRegWrite_2a412e2b2c0a0a2b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CVBAR_EL2_CapSysRegWrite_2a412e2b2c0a0a2b el op0 op1 CRn op2 CRm val_name)" + by (unfold CVBAR_EL2_CapSysRegWrite_2a412e2b2c0a0a2b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVBAR_EL3_CapSysRegWrite_f3c8bbee84b292db[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CVBAR_EL3_CapSysRegWrite_f3c8bbee84b292db el op0 op1 CRn op2 CRm val_name)" + by (unfold CVBAR_EL3_CapSysRegWrite_f3c8bbee84b292db_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DDC_CapSysRegWrite_9bc98e4e82148914[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DDC_CapSysRegWrite_9bc98e4e82148914 el op0 op1 CRn op2 CRm val_name)" + by (unfold DDC_CapSysRegWrite_9bc98e4e82148914_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DDC_EL0_CapSysRegWrite_1a928678ff9b43a6[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DDC_EL0_CapSysRegWrite_1a928678ff9b43a6 el op0 op1 CRn op2 CRm val_name)" + by (unfold DDC_EL0_CapSysRegWrite_1a928678ff9b43a6_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DDC_EL1_CapSysRegWrite_e7ecb5b1f0c49d28[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DDC_EL1_CapSysRegWrite_e7ecb5b1f0c49d28 el op0 op1 CRn op2 CRm val_name)" + by (unfold DDC_EL1_CapSysRegWrite_e7ecb5b1f0c49d28_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DDC_EL2_CapSysRegWrite_b4142a2dcadf2a34[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DDC_EL2_CapSysRegWrite_b4142a2dcadf2a34 el op0 op1 CRn op2 CRm val_name)" + by (unfold DDC_EL2_CapSysRegWrite_b4142a2dcadf2a34_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RCSP_EL0_CapSysRegWrite_d8f83400674fbeeb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RCSP_EL0_CapSysRegWrite_d8f83400674fbeeb el op0 op1 CRn op2 CRm val_name)" + by (unfold RCSP_EL0_CapSysRegWrite_d8f83400674fbeeb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RCTPIDR_EL0_CapSysRegWrite_27f7c47e137c72f8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RCTPIDR_EL0_CapSysRegWrite_27f7c47e137c72f8 el op0 op1 CRn op2 CRm val_name)" + by (unfold RCTPIDR_EL0_CapSysRegWrite_27f7c47e137c72f8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RDDC_EL0_CapSysRegWrite_c528d1b2eb785ad7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RDDC_EL0_CapSysRegWrite_c528d1b2eb785ad7 el op0 op1 CRn op2 CRm val_name)" + by (unfold RDDC_EL0_CapSysRegWrite_c528d1b2eb785ad7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_AutoGen_CapSysRegWrite[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_AutoGen_CapSysRegWrite el op0 op1 CRn op2 CRm val_name)" + by (unfold AArch64_AutoGen_CapSysRegWrite_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DDC_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DDC_set value_name)" + by (unfold DDC_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CapSysRegWrite[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CapSysRegWrite op0 op1 crn crm op2 val_name)" + by (unfold AArch64_CapSysRegWrite_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ALLE1IS_SysOpsWrite_8b81b55e2116aad3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ALLE1IS_SysOpsWrite_8b81b55e2116aad3 el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE1IS_SysOpsWrite_8b81b55e2116aad3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ALLE1_SysOpsWrite_69364bedc72cbe96[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ALLE1_SysOpsWrite_69364bedc72cbe96 el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE1_SysOpsWrite_69364bedc72cbe96_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_UndefinedFault[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_UndefinedFault arg0)" + by (unfold AArch64_UndefinedFault_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_UndefinedFault[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (UndefinedFault arg0)" + by (unfold UndefinedFault_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TLBI_ALLE2IS[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TLBI_ALLE2IS arg0)" + by (unfold TLBI_ALLE2IS_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ALLE2IS_SysOpsWrite_3a173239947b2c25[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ALLE2IS_SysOpsWrite_3a173239947b2c25 el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE2IS_SysOpsWrite_3a173239947b2c25_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TLBI_ALLE2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TLBI_ALLE2 arg0)" + by (unfold TLBI_ALLE2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ALLE2_SysOpsWrite_19c7b5110a5efe1d[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ALLE2_SysOpsWrite_19c7b5110a5efe1d el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE2_SysOpsWrite_19c7b5110a5efe1d_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ALLE3IS_SysOpsWrite_e64b79b4c41910fb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ALLE3IS_SysOpsWrite_e64b79b4c41910fb el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE3IS_SysOpsWrite_e64b79b4c41910fb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ALLE3_SysOpsWrite_5835ce2f987f3d36[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ALLE3_SysOpsWrite_5835ce2f987f3d36 el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE3_SysOpsWrite_5835ce2f987f3d36_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ASIDE1IS_SysOpsWrite_5a5dff91f113e41e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ASIDE1IS_SysOpsWrite_5a5dff91f113e41e el op0 op1 CRn op2 CRm val_name)" + by (unfold ASIDE1IS_SysOpsWrite_5a5dff91f113e41e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ASIDE1_SysOpsWrite_7ba7a3df395925e0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ASIDE1_SysOpsWrite_7ba7a3df395925e0 el op0 op1 CRn op2 CRm val_name)" + by (unfold ASIDE1_SysOpsWrite_7ba7a3df395925e0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_CISW[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_CISW val_name)" + by (unfold DC_CISW_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CISW_SysOpsWrite_5321b1c3157dccce[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CISW_SysOpsWrite_5321b1c3157dccce el op0 op1 CRn op2 CRm val_name)" + by (unfold CISW_SysOpsWrite_5321b1c3157dccce_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_EncodeLDFSC[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (EncodeLDFSC statuscode level)" + by (unfold EncodeLDFSC_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsExternalAbort[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsExternalAbort statuscode)" + by (unfold IsExternalAbort_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsExternalAbort__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsExternalAbort__1 fault)" + by (unfold IsExternalAbort__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsExternalSyncAbort[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsExternalSyncAbort statuscode)" + by (unfold IsExternalSyncAbort_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsExternalSyncAbort__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsExternalSyncAbort__1 fault)" + by (unfold IsExternalSyncAbort__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsSecondStage[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsSecondStage fault)" + by (unfold IsSecondStage_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_FaultSyndrome[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_FaultSyndrome d_side fault)" + by (unfold AArch64_FaultSyndrome_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IPAValid[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IPAValid fault)" + by (unfold IPAValid_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_AbortSyndrome[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_AbortSyndrome exceptype fault vaddress)" + by (unfold AArch64_AbortSyndrome_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_BreakpointException[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_BreakpointException fault)" + by (unfold AArch64_BreakpointException_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_DataAbort[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_DataAbort vaddress fault)" + by (unfold AArch64_DataAbort_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_InstructionAbort[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_InstructionAbort vaddress fault)" + by (unfold AArch64_InstructionAbort_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_WatchpointException[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_WatchpointException vaddress fault)" + by (unfold AArch64_WatchpointException_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsDebugException[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsDebugException fault)" + by (unfold IsDebugException_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_Abort[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_Abort vaddress fault)" + by (unfold AArch64_Abort_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ConstrainUnpredictableBits[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ConstrainUnpredictableBits width which)" + by (unfold ConstrainUnpredictableBits_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ConstrainUnpredictableInteger[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ConstrainUnpredictableInteger low high which)" + by (unfold ConstrainUnpredictableInteger_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Have16bitVMID[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (Have16bitVMID arg0)" + by (unfold Have16bitVMID_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_BreakpointValueMatch[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_BreakpointValueMatch n__arg vaddress linked_to)" + by (unfold AArch64_BreakpointValueMatch_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CheckValidStateMatch[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CheckValidStateMatch SSC__arg HMC__arg PxC__arg isbreakpnt)" + by (unfold CheckValidStateMatch_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_StateMatch[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_StateMatch SSC__arg HMC__arg PxC__arg linked__arg LBN isbreakpnt ispriv)" + by (unfold AArch64_StateMatch_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_BreakpointMatch[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_BreakpointMatch n vaddress size__arg)" + by (unfold AArch64_BreakpointMatch_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_AccType[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_AccType arg0)" + by (unfold undefined_AccType_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_Fault[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_Fault arg0)" + by (unfold undefined_Fault_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_FaultRecord[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_FaultRecord arg0)" + by (unfold undefined_FaultRecord_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CreateFaultRecord[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_CreateFaultRecord statuscode ipaddress level acctype write extflag errortype secondstage s2fs1walk)" + by (unfold AArch64_CreateFaultRecord_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_DebugFault[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_DebugFault acctype iswrite)" + by (unfold AArch64_DebugFault_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_NoFault[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_NoFault arg0)" + by (unfold AArch64_NoFault_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaltOnBreakpointOrWatchpoint[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaltOnBreakpointOrWatchpoint arg0)" + by (unfold HaltOnBreakpointOrWatchpoint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CheckBreakpoint[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CheckBreakpoint vaddress size__arg)" + by (unfold AArch64_CheckBreakpoint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_AccessUsesEL[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_AccessUsesEL acctype)" + by (unfold AArch64_AccessUsesEL_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_AccessIsPrivileged[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_AccessIsPrivileged acctype)" + by (unfold AArch64_AccessIsPrivileged_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_WatchpointByteMatch[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_WatchpointByteMatch n vaddress)" + by (unfold AArch64_WatchpointByteMatch_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_WatchpointMatch[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_WatchpointMatch n vaddress size__arg ispriv iswrite)" + by (unfold AArch64_WatchpointMatch_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CheckWatchpoint[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CheckWatchpoint vaddress acctype iswrite size__arg)" + by (unfold AArch64_CheckWatchpoint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_GenerateDebugExceptionsFrom[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_GenerateDebugExceptionsFrom from secure mask__arg)" + by (unfold AArch64_GenerateDebugExceptionsFrom_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_GenerateDebugExceptions[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_GenerateDebugExceptions arg0)" + by (unfold AArch64_GenerateDebugExceptions_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CheckDebug[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CheckDebug vaddress acctype iswrite size__arg)" + by (unfold AArch64_CheckDebug_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_AddressSizeFault[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage s2fs1walk)" + by (unfold AArch64_AddressSizeFault_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HasS2Translation[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HasS2Translation arg0)" + by (unfold HasS2Translation_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_IsStageOneEnabled[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_IsStageOneEnabled acctype)" + by (unfold AArch64_IsStageOneEnabled_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_FullAddress[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_FullAddress arg0)" + by (unfold undefined_FullAddress_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_DeviceType[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_DeviceType arg0)" + by (unfold undefined_DeviceType_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_MemAttrHints[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_MemAttrHints arg0)" + by (unfold undefined_MemAttrHints_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_MemType[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_MemType arg0)" + by (unfold undefined_MemType_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_MemoryAttributes[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_MemoryAttributes arg0)" + by (unfold undefined_MemoryAttributes_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_AddressDescriptor[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_AddressDescriptor arg0)" + by (unfold undefined_AddressDescriptor_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_FirstStageTranslateWithTag[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_FirstStageTranslateWithTag vaddress acctype iswrite wasaligned size__arg iswritevalidcap)" + by (unfold AArch64_FirstStageTranslateWithTag_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_FullTranslateWithTag[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_FullTranslateWithTag vaddress acctype iswrite wasaligned size__arg iswritevalidcap__arg)" + by (unfold AArch64_FullTranslateWithTag_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_TranslateAddressWithTag[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_TranslateAddressWithTag vaddress acctype iswrite wasaligned size__arg iswritevalidcap)" + by (unfold AArch64_TranslateAddressWithTag_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_TranslateAddress[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_TranslateAddress vaddress acctype iswrite wasaligned size__arg)" + by (unfold AArch64_TranslateAddress_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_CIVAC[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_CIVAC val_name)" + by (unfold DC_CIVAC_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapIsRangeInBounds[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapIsRangeInBounds c__arg start_address length__arg)" + by (unfold CapIsRangeInBounds_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapabilityFault[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapabilityFault faulttype acctype iswrite)" + by (unfold CapabilityFault_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsInC64[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsInC64 arg0)" + by (unfold IsInC64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_VirtualAddressType[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_VirtualAddressType arg0)" + by (unfold undefined_VirtualAddressType_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_VirtualAddress[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_VirtualAddress arg0)" + by (unfold undefined_VirtualAddress_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAFromBits64[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (VAFromBits64 b)" + by (unfold VAFromBits64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAFromCapability[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (VAFromCapability c__arg)" + by (unfold VAFromCapability_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAToCapability[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (VAToCapability v)" + by (unfold VAToCapability_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapGetBase[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapGetBase c__arg)" + by (unfold CapGetBase_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAToBits64[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (VAToBits64 v)" + by (unfold VAToBits64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAddress[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (VAddress addr)" + by (unfold VAddress_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MorelloCheckForCMO[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MorelloCheckForCMO cval requested_perms acctype)" + by (unfold MorelloCheckForCMO_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_CIVAC0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_CIVAC0 val_name__arg)" + by (unfold DC_CIVAC0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CIVAC_SysOpsWrite_47ad60ecb930d217[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CIVAC_SysOpsWrite_47ad60ecb930d217 el op0 op1 CRn op2 CRm val_name)" + by (unfold CIVAC_SysOpsWrite_47ad60ecb930d217_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_CSW[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_CSW val_name)" + by (unfold DC_CSW_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CSW_SysOpsWrite_9544819da3ebaa1b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CSW_SysOpsWrite_9544819da3ebaa1b el op0 op1 CRn op2 CRm val_name)" + by (unfold CSW_SysOpsWrite_9544819da3ebaa1b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_CVAC[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_CVAC val_name)" + by (unfold DC_CVAC_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_CVAC0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_CVAC0 val_name__arg)" + by (unfold DC_CVAC0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVAC_SysOpsWrite_c7d2e911c691cc6b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CVAC_SysOpsWrite_c7d2e911c691cc6b el op0 op1 CRn op2 CRm val_name)" + by (unfold CVAC_SysOpsWrite_c7d2e911c691cc6b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_CVAP[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_CVAP val_name)" + by (unfold DC_CVAP_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_CVADP[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_CVADP val_name)" + by (unfold DC_CVADP_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVADP_SysOpsWrite_9953ef108c01d34a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CVADP_SysOpsWrite_9953ef108c01d34a el op0 op1 CRn op2 CRm val_name)" + by (unfold CVADP_SysOpsWrite_9953ef108c01d34a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVAP_SysOpsWrite_a43f75867888e74a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CVAP_SysOpsWrite_a43f75867888e74a el op0 op1 CRn op2 CRm val_name)" + by (unfold CVAP_SysOpsWrite_a43f75867888e74a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_CVAU[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_CVAU val_name)" + by (unfold DC_CVAU_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_CVAU0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_CVAU0 val_name__arg)" + by (unfold DC_CVAU0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CVAU_SysOpsWrite_4a72bbc98a17973c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CVAU_SysOpsWrite_4a72bbc98a17973c el op0 op1 CRn op2 CRm val_name)" + by (unfold CVAU_SysOpsWrite_4a72bbc98a17973c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IC_IALLUIS[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (IC_IALLUIS arg0)" + by (unfold IC_IALLUIS_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IALLUIS_SysOpsWrite_9a906c8365100aff[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (IALLUIS_SysOpsWrite_9a906c8365100aff el op0 op1 CRn op2 CRm val_name)" + by (unfold IALLUIS_SysOpsWrite_9a906c8365100aff_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IC_IALLU[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (IC_IALLU arg0)" + by (unfold IC_IALLU_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IALLU_SysOpsWrite_81563797a4921929[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (IALLU_SysOpsWrite_81563797a4921929 el op0 op1 CRn op2 CRm val_name)" + by (unfold IALLU_SysOpsWrite_81563797a4921929_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IPAS2E1IS_SysOpsWrite_ed4be1feae90b987[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (IPAS2E1IS_SysOpsWrite_ed4be1feae90b987 el op0 op1 CRn op2 CRm val_name)" + by (unfold IPAS2E1IS_SysOpsWrite_ed4be1feae90b987_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IPAS2E1_SysOpsWrite_a65fef0d99f9428f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (IPAS2E1_SysOpsWrite_a65fef0d99f9428f el op0 op1 CRn op2 CRm val_name)" + by (unfold IPAS2E1_SysOpsWrite_a65fef0d99f9428f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IPAS2LE1IS_SysOpsWrite_5a72848dfefa19f3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (IPAS2LE1IS_SysOpsWrite_5a72848dfefa19f3 el op0 op1 CRn op2 CRm val_name)" + by (unfold IPAS2LE1IS_SysOpsWrite_5a72848dfefa19f3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IPAS2LE1_SysOpsWrite_10ca7ac6abdfed50[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (IPAS2LE1_SysOpsWrite_10ca7ac6abdfed50 el op0 op1 CRn op2 CRm val_name)" + by (unfold IPAS2LE1_SysOpsWrite_10ca7ac6abdfed50_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_ISW[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_ISW val_name)" + by (unfold DC_ISW_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ISW_SysOpsWrite_d5fceb001aa0aa7a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ISW_SysOpsWrite_d5fceb001aa0aa7a el op0 op1 CRn op2 CRm val_name)" + by (unfold ISW_SysOpsWrite_d5fceb001aa0aa7a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_IVAC[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_IVAC val_name)" + by (unfold DC_IVAC_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_IVAC0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_IVAC0 val_name__arg)" + by (unfold DC_IVAC0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IVAC_SysOpsWrite_41b93e0e56e4f107[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (IVAC_SysOpsWrite_41b93e0e56e4f107 el op0 op1 CRn op2 CRm val_name)" + by (unfold IVAC_SysOpsWrite_41b93e0e56e4f107_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IC_IVAU[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (IC_IVAU val_name)" + by (unfold IC_IVAU_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IVAU_SysOpsWrite_2dfe97b748dd324e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (IVAU_SysOpsWrite_2dfe97b748dd324e el op0 op1 CRn op2 CRm val_name)" + by (unfold IVAU_SysOpsWrite_2dfe97b748dd324e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RCTX_SysOpsWrite_bcc8cd10f2e68999[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RCTX_SysOpsWrite_bcc8cd10f2e68999 el op0 op1 CRn op2 CRm val_name)" + by (unfold RCTX_SysOpsWrite_bcc8cd10f2e68999_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RCTX_SysOpsWrite_c287513d0d3e8e92[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RCTX_SysOpsWrite_c287513d0d3e8e92 el op0 op1 CRn op2 CRm val_name)" + by (unfold RCTX_SysOpsWrite_c287513d0d3e8e92_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RCTX_SysOpsWrite_d614ec87236c038f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RCTX_SysOpsWrite_d614ec87236c038f el op0 op1 CRn op2 CRm val_name)" + by (unfold RCTX_SysOpsWrite_d614ec87236c038f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_PARFaultStatus[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_PARFaultStatus fault)" + by (unfold AArch64_PARFaultStatus_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PARAttrsDecode[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (PARAttrsDecode memattrs)" + by (unfold PARAttrsDecode_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PARShareabilityDecode[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (PARShareabilityDecode memattrs)" + by (unfold PARShareabilityDecode_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_EncodePAR[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_EncodePAR addrdesc)" + by (unfold AArch64_EncodePAR_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_FirstStageTranslate[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_FirstStageTranslate vaddress acctype iswrite wasaligned size__arg)" + by (unfold AArch64_FirstStageTranslate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RESTORE_EL[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (RESTORE_EL arg0)" + by (unfold RESTORE_EL_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SAVE_EL[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SAVE_EL new_exception_level)" + by (unfold SAVE_EL_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_AT_S1Ex[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_AT_S1Ex val_name el iswrite)" + by (unfold AArch64_AT_S1Ex_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_FullTranslate[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_FullTranslate vaddress acctype iswrite wasaligned size__arg)" + by (unfold AArch64_FullTranslate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_AT_S12Ex[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_AT_S12Ex val_name el iswrite)" + by (unfold AArch64_AT_S12Ex_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S12E0R[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S12E0R val_name)" + by (unfold AT_S12E0R_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S1E0R[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S1E0R val_name)" + by (unfold AT_S1E0R_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S12E0R_SysOpsWrite_4df3d544cba811b7[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S12E0R_SysOpsWrite_4df3d544cba811b7 el op0 op1 CRn op2 CRm val_name)" + by (unfold S12E0R_SysOpsWrite_4df3d544cba811b7_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S12E0W[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S12E0W val_name)" + by (unfold AT_S12E0W_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S1E0W[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S1E0W val_name)" + by (unfold AT_S1E0W_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S12E0W_SysOpsWrite_1dbb37d4af097406[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S12E0W_SysOpsWrite_1dbb37d4af097406 el op0 op1 CRn op2 CRm val_name)" + by (unfold S12E0W_SysOpsWrite_1dbb37d4af097406_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S12E1R[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S12E1R val_name)" + by (unfold AT_S12E1R_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S1E1R[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S1E1R val_name)" + by (unfold AT_S1E1R_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S12E1R_SysOpsWrite_e44276c8f24d398f[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S12E1R_SysOpsWrite_e44276c8f24d398f el op0 op1 CRn op2 CRm val_name)" + by (unfold S12E1R_SysOpsWrite_e44276c8f24d398f_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S12E1W[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S12E1W val_name)" + by (unfold AT_S12E1W_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S1E1W[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S1E1W val_name)" + by (unfold AT_S1E1W_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S12E1W_SysOpsWrite_c8b72d75cad90601[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S12E1W_SysOpsWrite_c8b72d75cad90601 el op0 op1 CRn op2 CRm val_name)" + by (unfold S12E1W_SysOpsWrite_c8b72d75cad90601_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S1E0R_SysOpsWrite_0a1e21ea5b4c8722[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S1E0R_SysOpsWrite_0a1e21ea5b4c8722 el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E0R_SysOpsWrite_0a1e21ea5b4c8722_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S1E0W_SysOpsWrite_d102d49fd92af65a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S1E0W_SysOpsWrite_d102d49fd92af65a el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E0W_SysOpsWrite_d102d49fd92af65a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S1E1RP[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S1E1RP val_name)" + by (unfold AT_S1E1RP_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S1E1RP_SysOpsWrite_4a6b1f71ee0182ab[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S1E1RP_SysOpsWrite_4a6b1f71ee0182ab el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E1RP_SysOpsWrite_4a6b1f71ee0182ab_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S1E1R_SysOpsWrite_018a577644c5d23c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S1E1R_SysOpsWrite_018a577644c5d23c el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E1R_SysOpsWrite_018a577644c5d23c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S1E1WP[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S1E1WP val_name)" + by (unfold AT_S1E1WP_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S1E1WP_SysOpsWrite_bb1ddb9112effe2a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S1E1WP_SysOpsWrite_bb1ddb9112effe2a el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E1WP_SysOpsWrite_bb1ddb9112effe2a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S1E1W_SysOpsWrite_df64f2f63c0911fd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S1E1W_SysOpsWrite_df64f2f63c0911fd el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E1W_SysOpsWrite_df64f2f63c0911fd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S1E2R[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S1E2R val_name)" + by (unfold AT_S1E2R_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S1E2R_SysOpsWrite_5e865a96c06417c8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S1E2R_SysOpsWrite_5e865a96c06417c8 el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E2R_SysOpsWrite_5e865a96c06417c8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S1E2W[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S1E2W val_name)" + by (unfold AT_S1E2W_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S1E2W_SysOpsWrite_1649806418453f02[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S1E2W_SysOpsWrite_1649806418453f02 el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E2W_SysOpsWrite_1649806418453f02_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S1E3R[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S1E3R val_name)" + by (unfold AT_S1E3R_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S1E3R_SysOpsWrite_6476f20e79e358be[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S1E3R_SysOpsWrite_6476f20e79e358be el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E3R_SysOpsWrite_6476f20e79e358be_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AT_S1E3W[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AT_S1E3W val_name)" + by (unfold AT_S1E3W_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S1E3W_SysOpsWrite_e92e083e28fa4dd0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S1E3W_SysOpsWrite_e92e083e28fa4dd0 el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E3W_SysOpsWrite_e92e083e28fa4dd0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_S1_op1_Cn_Cm_op2_SysOpsWrite_d6b17d94c0df44bc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (S1_op1_Cn_Cm_op2_SysOpsWrite_d6b17d94c0df44bc el op0 op1 CRn op2 CRm val_name)" + by (unfold S1_op1_Cn_Cm_op2_SysOpsWrite_d6b17d94c0df44bc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAAE1IS_SysOpsWrite_c22cd5a1dc8e7320[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VAAE1IS_SysOpsWrite_c22cd5a1dc8e7320 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAAE1IS_SysOpsWrite_c22cd5a1dc8e7320_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAAE1_SysOpsWrite_8498b4db5afbed38[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VAAE1_SysOpsWrite_8498b4db5afbed38 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAAE1_SysOpsWrite_8498b4db5afbed38_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAALE1IS_SysOpsWrite_5c8056a5b649fe2e[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VAALE1IS_SysOpsWrite_5c8056a5b649fe2e el op0 op1 CRn op2 CRm val_name)" + by (unfold VAALE1IS_SysOpsWrite_5c8056a5b649fe2e_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAALE1_SysOpsWrite_d3bec3a19881fb1c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VAALE1_SysOpsWrite_d3bec3a19881fb1c el op0 op1 CRn op2 CRm val_name)" + by (unfold VAALE1_SysOpsWrite_d3bec3a19881fb1c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAE1IS_SysOpsWrite_5eac1ac5cb4e76ff[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VAE1IS_SysOpsWrite_5eac1ac5cb4e76ff el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE1IS_SysOpsWrite_5eac1ac5cb4e76ff_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAE1_SysOpsWrite_09dbfc0bf1b19b11[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VAE1_SysOpsWrite_09dbfc0bf1b19b11 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE1_SysOpsWrite_09dbfc0bf1b19b11_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TLBI_VAE2IS[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TLBI_VAE2IS val_name)" + by (unfold TLBI_VAE2IS_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAE2IS_SysOpsWrite_f81411101129df7b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VAE2IS_SysOpsWrite_f81411101129df7b el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE2IS_SysOpsWrite_f81411101129df7b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TLBI_VAE2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TLBI_VAE2 val_name)" + by (unfold TLBI_VAE2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAE2_SysOpsWrite_78002df18993a4b5[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VAE2_SysOpsWrite_78002df18993a4b5 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE2_SysOpsWrite_78002df18993a4b5_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAE3IS_SysOpsWrite_7dc759c51bb69ced[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VAE3IS_SysOpsWrite_7dc759c51bb69ced el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE3IS_SysOpsWrite_7dc759c51bb69ced_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAE3_SysOpsWrite_90b5c3b60d3bd152[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VAE3_SysOpsWrite_90b5c3b60d3bd152 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE3_SysOpsWrite_90b5c3b60d3bd152_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VALE1IS_SysOpsWrite_7bb7ad05a900b833[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VALE1IS_SysOpsWrite_7bb7ad05a900b833 el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE1IS_SysOpsWrite_7bb7ad05a900b833_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VALE1_SysOpsWrite_c1766c627b3960ca[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VALE1_SysOpsWrite_c1766c627b3960ca el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE1_SysOpsWrite_c1766c627b3960ca_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TLBI_VALE2IS[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TLBI_VALE2IS val_name)" + by (unfold TLBI_VALE2IS_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VALE2IS_SysOpsWrite_a1084cefbce599af[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VALE2IS_SysOpsWrite_a1084cefbce599af el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE2IS_SysOpsWrite_a1084cefbce599af_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_TLBI_VALE2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (TLBI_VALE2 val_name)" + by (unfold TLBI_VALE2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VALE2_SysOpsWrite_dce4b2b057d036da[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VALE2_SysOpsWrite_dce4b2b057d036da el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE2_SysOpsWrite_dce4b2b057d036da_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VALE3IS_SysOpsWrite_8b70cb86db2abfcd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VALE3IS_SysOpsWrite_8b70cb86db2abfcd el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE3IS_SysOpsWrite_8b70cb86db2abfcd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VALE3_SysOpsWrite_df1f91b1bea42ec8[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VALE3_SysOpsWrite_df1f91b1bea42ec8 el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE3_SysOpsWrite_df1f91b1bea42ec8_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VMALLE1IS_SysOpsWrite_08cfba716c4ca8db[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VMALLE1IS_SysOpsWrite_08cfba716c4ca8db el op0 op1 CRn op2 CRm val_name)" + by (unfold VMALLE1IS_SysOpsWrite_08cfba716c4ca8db_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VMALLE1_SysOpsWrite_c64f2572b311d9b9[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VMALLE1_SysOpsWrite_c64f2572b311d9b9 el op0 op1 CRn op2 CRm val_name)" + by (unfold VMALLE1_SysOpsWrite_c64f2572b311d9b9_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VMALLS12E1IS_SysOpsWrite_92a1ba1461a19d4c[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VMALLS12E1IS_SysOpsWrite_92a1ba1461a19d4c el op0 op1 CRn op2 CRm val_name)" + by (unfold VMALLS12E1IS_SysOpsWrite_92a1ba1461a19d4c_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VMALLS12E1_SysOpsWrite_8f5c303094061f20[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VMALLS12E1_SysOpsWrite_8f5c303094061f20 el op0 op1 CRn op2 CRm val_name)" + by (unfold VMALLS12E1_SysOpsWrite_8f5c303094061f20_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_MPAMinfo[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_MPAMinfo arg0)" + by (unfold undefined_MPAMinfo_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DefaultMPAMinfo[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DefaultMPAMinfo secure)" + by (unfold DefaultMPAMinfo_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveMPAMExt[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveMPAMExt arg0)" + by (unfold HaveMPAMExt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMisEnabled[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (MPAMisEnabled arg0)" + by (unfold MPAMisEnabled_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_mapvpmw[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (mapvpmw vpartid)" + by (unfold mapvpmw_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MAP_vPARTID[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (MAP_vPARTID vpartid)" + by (unfold MAP_vPARTID_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MPAMisVirtual[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (MPAMisVirtual el)" + by (unfold MPAMisVirtual_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_getMPAM_PARTID[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (getMPAM_PARTID MPAMn InD)" + by (unfold getMPAM_PARTID_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_genPARTID[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (genPARTID el InD)" + by (unfold genPARTID_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_getMPAM_PMG[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (getMPAM_PMG MPAMn InD)" + by (unfold getMPAM_PMG_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_genPMG[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (genPMG el InD partid_err)" + by (unfold genPMG_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_genMPAM[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (genMPAM el InD secure)" + by (unfold genMPAM_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_GenMPAMcurEL[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (GenMPAMcurEL InD)" + by (unfold GenMPAMcurEL_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_AccessDescriptor[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_AccessDescriptor arg0)" + by (unfold undefined_AccessDescriptor_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CreateAccessDescriptor[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CreateAccessDescriptor acctype)" + by (unfold CreateAccessDescriptor_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_ZVA[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_ZVA val_name)" + by (unfold DC_ZVA_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DC_ZVA0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DC_ZVA0 val_name__arg)" + by (unfold DC_ZVA0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ZVA_SysOpsWrite_b40574bff0ba4354[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ZVA_SysOpsWrite_b40574bff0ba4354 el op0 op1 CRn op2 CRm val_name)" + by (unfold ZVA_SysOpsWrite_b40574bff0ba4354_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_AutoGen_SysOpsWrite[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_AutoGen_SysOpsWrite el op0 op1 CRn op2 CRm val_name)" + by (unfold AArch64_AutoGen_SysOpsWrite_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_SysInstr[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_SysInstr op0 op1 crn crm op2 val_name)" + by (unfold AArch64_SysInstr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_SysInstrWithResult[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_SysInstrWithResult op0 op1 crn crm op2)" + by (unfold AArch64_SysInstrWithResult_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_MBReqDomain[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_MBReqDomain arg0)" + by (unfold undefined_MBReqDomain_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_MBReqTypes[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_MBReqTypes arg0)" + by (unfold undefined_MBReqTypes_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_PrefetchHint[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_PrefetchHint arg0)" + by (unfold undefined_PrefetchHint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_FPRounding[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_FPRounding arg0)" + by (unfold undefined_FPRounding_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_FPType[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_FPType arg0)" + by (unfold undefined_FPType_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_UNKNOWN_VirtualAddressType[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (UNKNOWN_VirtualAddressType arg0)" + by (unfold UNKNOWN_VirtualAddressType_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_ExtendType[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_ExtendType arg0)" + by (unfold undefined_ExtendType_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_FPMaxMinOp[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_FPMaxMinOp arg0)" + by (unfold undefined_FPMaxMinOp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_FPUnaryOp[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_FPUnaryOp arg0)" + by (unfold undefined_FPUnaryOp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_FPConvOp[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_FPConvOp arg0)" + by (unfold undefined_FPConvOp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_MoveWideOp[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_MoveWideOp arg0)" + by (unfold undefined_MoveWideOp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_ShiftType[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_ShiftType arg0)" + by (unfold undefined_ShiftType_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_LogicalOp[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_LogicalOp arg0)" + by (unfold undefined_LogicalOp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_MemOp[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_MemOp arg0)" + by (unfold undefined_MemOp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_MemAtomicOp[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_MemAtomicOp arg0)" + by (unfold undefined_MemAtomicOp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_SystemHintOp[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_SystemHintOp arg0)" + by (unfold undefined_SystemHintOp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_PSTATEField[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_PSTATEField arg0)" + by (unfold undefined_PSTATEField_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_VBitOp[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_VBitOp arg0)" + by (unfold undefined_VBitOp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_CompareOp[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_CompareOp arg0)" + by (unfold undefined_CompareOp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_undefined_ImmediateOp[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (undefined_ImmediateOp arg0)" + by (unfold undefined_ImmediateOp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SetThisInstr[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29''} \ no_reg_writes_to Rs (SetThisInstr opcode)" + by (unfold SetThisInstr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_LowestSetBit[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (LowestSetBit x)" + by (unfold LowestSetBit_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HighestSetBit[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HighestSetBit x)" + by (unfold HighestSetBit_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Elem_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (Elem_read vector_name e size__arg)" + by (unfold Elem_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Elem_set[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (Elem_set vector_name__arg e size__arg value_name)" + by (unfold Elem_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_BigEndian[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (BigEndian arg0)" + by (unfold BigEndian_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_EffectiveTGEN[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (EffectiveTGEN address el)" + by (unfold EffectiveTGEN_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELFromSPSR[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ELFromSPSR spsr)" + by (unfold ELFromSPSR_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELUsingAArch32K[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ELUsingAArch32K el)" + by (unfold ELUsingAArch32K_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IllegalExceptionReturn[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IllegalExceptionReturn spsr)" + by (unfold IllegalExceptionReturn_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DebugTargetFrom[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DebugTargetFrom secure)" + by (unfold DebugTargetFrom_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Restarting[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (Restarting arg0)" + by (unfold Restarting_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DebugExceptionReturnSS[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DebugExceptionReturnSS spsr)" + by (unfold DebugExceptionReturnSS_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SetPSTATEFromPSR[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SetPSTATEFromPSR spsr__arg)" + by (unfold SetPSTATEFromPSR_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SendEventLocal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SendEventLocal arg0)" + by (unfold SendEventLocal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ClearEventRegister[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ClearEventRegister arg0)" + by (unfold ClearEventRegister_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsEventRegisterSet[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsEventRegisterSet arg0)" + by (unfold IsEventRegisterSet_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_WaitForEvent[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (WaitForEvent arg0)" + by (unfold WaitForEvent_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_BitReverse[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (BitReverse data)" + by (unfold BitReverse_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveAESExt[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveAESExt arg0)" + by (unfold HaveAESExt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveBit128PMULLExt[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveBit128PMULLExt arg0)" + by (unfold HaveBit128PMULLExt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveSHA1Ext[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveSHA1Ext arg0)" + by (unfold HaveSHA1Ext_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveSHA256Ext[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveSHA256Ext arg0)" + by (unfold HaveSHA256Ext_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveSHA512Ext[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveSHA512Ext arg0)" + by (unfold HaveSHA512Ext_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveSHA3Ext[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveSHA3Ext arg0)" + by (unfold HaveSHA3Ext_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveSM3Ext[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveSM3Ext arg0)" + by (unfold HaveSM3Ext_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveSM4Ext[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveSM4Ext arg0)" + by (unfold HaveSM4Ext_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ROL[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ROL x shift)" + by (unfold ROL_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AESSubBytes[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AESSubBytes op)" + by (unfold AESSubBytes_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AESInvSubBytes[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AESInvSubBytes op)" + by (unfold AESInvSubBytes_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AESMixColumns[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AESMixColumns op)" + by (unfold AESMixColumns_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AESInvMixColumns[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AESInvMixColumns op)" + by (unfold AESInvMixColumns_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SHA256hash[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SHA256hash X__arg Y__arg W part1)" + by (unfold SHA256hash_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RecipEstimate[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (RecipEstimate a__arg)" + by (unfold RecipEstimate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_UnsignedRecipEstimate[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (UnsignedRecipEstimate operand)" + by (unfold UnsignedRecipEstimate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_RecipSqrtEstimate[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (RecipSqrtEstimate a__arg)" + by (unfold RecipSqrtEstimate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_UnsignedRSqrtEstimate[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (UnsignedRSqrtEstimate operand)" + by (unfold UnsignedRSqrtEstimate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SignedSatQ[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SignedSatQ i N)" + by (unfold SignedSatQ_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_UnsignedSatQ__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (UnsignedSatQ__1 i N M)" + by (unfold UnsignedSatQ__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_UnsignedSatQ[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (UnsignedSatQ i N)" + by (unfold UnsignedSatQ_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SatQ[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SatQ i N is_unsigned)" + by (unfold SatQ_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AdvSIMDExpandImm[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AdvSIMDExpandImm op cmode imm8)" + by (unfold AdvSIMDExpandImm_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPInfinity[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (FPInfinity l__634 sign)" + by (unfold FPInfinity_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPMaxNormal[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (FPMaxNormal l__631 sign)" + by (unfold FPMaxNormal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_FPTrappedException[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_FPTrappedException is_ase element accumulated_exceptions)" + by (unfold AArch64_FPTrappedException_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPProcessException[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPProcessException exception fpcr)" + by (unfold FPProcessException_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPZero[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (FPZero l__628 sign)" + by (unfold FPZero_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPRoundBase[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPRoundBase arg0 arg1 arg2 arg3 arg4)" + by (unfold FPRoundBase_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPDecodeRounding[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (FPDecodeRounding rmode)" + by (unfold FPDecodeRounding_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPRoundingMode[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (FPRoundingMode fpcr)" + by (unfold FPRoundingMode_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPRound[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPRound N op fpcr__arg rounding)" + by (unfold FPRound_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPRound__1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPRound__1 N op fpcr)" + by (unfold FPRound__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FixedToFP[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FixedToFP N op fbits is_unsigned fpcr rounding)" + by (unfold FixedToFP_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPAbs[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (FPAbs op)" + by (unfold FPAbs_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPDefaultNaN[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (FPDefaultNaN l__616)" + by (unfold FPDefaultNaN_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPProcessNaN[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPProcessNaN fptype op fpcr)" + by (unfold FPProcessNaN_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPProcessNaNs[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPProcessNaNs type1 type2 op1 op2 fpcr)" + by (unfold FPProcessNaNs_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPUnpackBase[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPUnpackBase fpval fpcr)" + by (unfold FPUnpackBase_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPUnpack[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPUnpack fpval fpcr__arg)" + by (unfold FPUnpack_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPAdd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPAdd op1 op2 fpcr)" + by (unfold FPAdd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPCompare[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPCompare op1 op2 signal_nans fpcr)" + by (unfold FPCompare_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPCompareEQ[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPCompareEQ op1 op2 fpcr)" + by (unfold FPCompareEQ_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPCompareGE[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPCompareGE op1 op2 fpcr)" + by (unfold FPCompareGE_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPCompareGT[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPCompareGT op1 op2 fpcr)" + by (unfold FPCompareGT_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPConvertNaN[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (FPConvertNaN M op)" + by (unfold FPConvertNaN_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPRoundCV[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPRoundCV N op fpcr__arg rounding)" + by (unfold FPRoundCV_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPUnpackCV[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPUnpackCV fpval fpcr__arg)" + by (unfold FPUnpackCV_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPConvert[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPConvert l__604 op fpcr rounding)" + by (unfold FPConvert_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPConvert__1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPConvert__1 M op fpcr)" + by (unfold FPConvert__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPDiv[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPDiv op1 op2 fpcr)" + by (unfold FPDiv_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPMax[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPMax op1 op2 fpcr)" + by (unfold FPMax_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPMaxNum[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPMaxNum op1__arg op2__arg fpcr)" + by (unfold FPMaxNum_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPMin[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPMin op1 op2 fpcr)" + by (unfold FPMin_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPMinNum[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPMinNum op1__arg op2__arg fpcr)" + by (unfold FPMinNum_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPMul[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPMul op1 op2 fpcr)" + by (unfold FPMul_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPProcessNaNs3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPProcessNaNs3 type1 type2 type3 op1 op2 op3 fpcr)" + by (unfold FPProcessNaNs3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPMulAdd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPMulAdd addend op1 op2 fpcr)" + by (unfold FPMulAdd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPTwo[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (FPTwo l__601 sign)" + by (unfold FPTwo_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPMulX[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPMulX op1 op2 fpcr)" + by (unfold FPMulX_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPNeg[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (FPNeg op)" + by (unfold FPNeg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPOnePointFive[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (FPOnePointFive l__595 sign)" + by (unfold FPOnePointFive_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPRecipEstimate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPRecipEstimate operand fpcr)" + by (unfold FPRecipEstimate_def bind_assoc, no_reg_writes_toI intro: no_reg_writes_to_if_no_asm) + +lemma no_reg_writes_to_FPRecpX[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPRecpX l__583 op fpcr)" + by (unfold FPRecpX_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPRoundInt[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPRoundInt op fpcr rounding exact)" + by (unfold FPRoundInt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPRSqrtEstimate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPRSqrtEstimate operand fpcr)" + by (unfold FPRSqrtEstimate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPSqrt[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPSqrt op fpcr)" + by (unfold FPSqrt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPSub[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPSub op1 op2 fpcr)" + by (unfold FPSub_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPToFixed[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPToFixed M op fbits is_unsigned fpcr rounding)" + by (unfold FPToFixed_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VFPExpandImm[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (VFPExpandImm l__571 imm8)" + by (unfold VFPExpandImm_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_BranchXToCapability[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (BranchXToCapability target__arg branch_type)" + by (unfold BranchXToCapability_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapIsRepresentableFast[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapIsRepresentableFast c__arg increment_name__arg)" + by (unfold CapIsRepresentableFast_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapAdd[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapAdd c__arg increment_name)" + by (unfold CapAdd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapAdd__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapAdd__1 c__arg increment_name)" + by (unfold CapAdd__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_BranchToOffset[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (BranchToOffset offset branch_type)" + by (unfold BranchToOffset_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SPSR_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SPSR_read arg0)" + by (unfold SPSR_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_HaveSBExt[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (HaveSBExt arg0)" + by (unfold HaveSBExt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_X_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (X_set width n value_name)" + by (unfold X_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_X_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (X_read width n)" + by (unfold X_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_C_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (C_read n)" + by (unfold C_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SP_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SP_set width value_name)" + by (unfold SP_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SP_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (SP_read width)" + by (unfold SP_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CSP_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CSP_set value_name)" + by (unfold CSP_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CSP_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CSP_read arg0)" + by (unfold CSP_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_V_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (V_read width n)" + by (unfold V_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Vpart_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (Vpart_read width n part)" + by (unfold Vpart_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Vpart_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Vpart_set width n part value_name)" + by (unfold Vpart_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_PC_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (PC_read arg0)" + by (unfold PC_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_SPAlignmentFault[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_SPAlignmentFault arg0)" + by (unfold AArch64_SPAlignmentFault_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CheckSPAlignment[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CheckSPAlignment arg0)" + by (unfold CheckSPAlignment_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_BaseReg_read[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (BaseReg_read n is_prefetch)" + by (unfold BaseReg_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_BaseReg_read__1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (BaseReg_read__1 n)" + by (unfold BaseReg_read__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AltBaseReg_read[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AltBaseReg_read n is_prefetch)" + by (unfold AltBaseReg_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AltBaseReg_read__1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AltBaseReg_read__1 n)" + by (unfold AltBaseReg_read__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_BaseReg_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (BaseReg_set n address)" + by (unfold BaseReg_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FAR_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (FAR_read regime)" + by (unfold FAR_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FAR_read__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (FAR_read__1 arg0)" + by (unfold FAR_read__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELR_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ELR_read el)" + by (unfold ELR_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ELR_read__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ELR_read__1 arg0)" + by (unfold ELR_read__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CELR_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CELR_read el)" + by (unfold CELR_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CELR_read__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CELR_read__1 arg0)" + by (unfold CELR_read__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ESR_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ESR_read regime)" + by (unfold ESR_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ESR_read__1[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ESR_read__1 arg0)" + by (unfold ESR_read__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CPACR_read[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CPACR_read arg0)" + by (unfold CPACR_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CheckSystemAccess[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CheckSystemAccess op0 op1 crn crm op2 rt read)" + by (unfold AArch64_CheckSystemAccess_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_SysInstrInputIsCapability[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_SysInstrInputIsCapability op0 op1 crn crm op2)" + by (unfold AArch64_SysInstrInputIsCapability_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_AlignmentFault[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_AlignmentFault acctype iswrite secondstage)" + by (unfold AArch64_AlignmentFault_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CheckAlignment[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CheckAlignment address alignment acctype iswrite)" + by (unfold AArch64_CheckAlignment_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_MemSingle_read[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_MemSingle_read address size__arg acctype wasaligned)" + by (unfold AArch64_MemSingle_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_MemSingle_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_MemSingle_set address size__arg acctype wasaligned value_name)" + by (unfold AArch64_MemSingle_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CapabilityPagePermissionFault[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_CapabilityPagePermissionFault acctype secondstage is_store)" + by (unfold AArch64_CapabilityPagePermissionFault_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CheckLoadTagsPermission[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CheckLoadTagsPermission desc acctype)" + by (unfold CheckLoadTagsPermission_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CheckStoreTagsPermission[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CheckStoreTagsPermission desc acctype)" + by (unfold CheckStoreTagsPermission_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_TaggedMemSingle[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_TaggedMemSingle address size__arg acctype wasaligned)" + by (unfold AArch64_TaggedMemSingle_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_TaggedMemSingle__1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_TaggedMemSingle__1 address size__arg acctype wasaligned tags value_name)" + by (unfold AArch64_TaggedMemSingle__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CheckCapabilityAlignment[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CheckCapabilityAlignment address acctype iswrite)" + by (unfold CheckCapabilityAlignment_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CapabilityTag[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CapabilityTag address acctype)" + by (unfold AArch64_CapabilityTag_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CapabilityTag_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CapabilityTag_set address acctype tag)" + by (unfold AArch64_CapabilityTag_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Mem_read0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Mem_read0 address size__arg acctype)" + by (unfold Mem_read0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Mem_set0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Mem_set0 address size__arg acctype value_name__arg)" + by (unfold Mem_set0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CheckCapabilityStorePairAlignment[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CheckCapabilityStorePairAlignment address acctype iswrite)" + by (unfold CheckCapabilityStorePairAlignment_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapabilityFromData[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapabilityFromData size__arg tag data)" + by (unfold CapabilityFromData_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MemC_read[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MemC_read address acctype)" + by (unfold MemC_read_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MemC_set[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MemC_set address acctype value_name)" + by (unfold MemC_set_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MemCP__1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MemCP__1 address acctype value1_name value2_name)" + by (unfold MemCP__1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_TranslateAddressForAtomicAccess[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_TranslateAddressForAtomicAccess address sizeinbits)" + by (unfold AArch64_TranslateAddressForAtomicAccess_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CheckCapability[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CheckCapability c__arg address size__arg requested_perms acctype)" + by (unfold CheckCapability_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VACheckAddress[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (VACheckAddress base addr64 size__arg requested_perms acctype)" + by (unfold VACheckAddress_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MemAtomicCompareAndSwap[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MemAtomicCompareAndSwap base expectedvalue newvalue__arg ldacctype stacctype)" + by (unfold MemAtomicCompareAndSwap_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MemAtomic[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MemAtomic base op value_name ldacctype stacctype)" + by (unfold MemAtomic_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapSquashPostLoadCap[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapSquashPostLoadCap data__arg addr)" + by (unfold CapSquashPostLoadCap_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MemAtomicCompareAndSwapC[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MemAtomicCompareAndSwapC vaddr address expectedcap newcap ldacctype stacctype)" + by (unfold MemAtomicCompareAndSwapC_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_MemAtomicC[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (MemAtomicC address op value_name ldacctype stacctype)" + by (unfold MemAtomicC_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_SetExclusiveMonitors[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_SetExclusiveMonitors address size__arg)" + by (unfold AArch64_SetExclusiveMonitors_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_ExclusiveMonitorsPass[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_ExclusiveMonitorsPass address size__arg)" + by (unfold AArch64_ExclusiveMonitorsPass_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPRecipStepFused[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPRecipStepFused op1__arg op2)" + by (unfold FPRecipStepFused_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FPRSqrtStepFused[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FPRSqrtStepFused op1__arg op2)" + by (unfold FPRSqrtStepFused_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_ReportDeferredSError[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (AArch64_ReportDeferredSError syndrome)" + by (unfold AArch64_ReportDeferredSError_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ExternalDebugInterruptsDisabled[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ExternalDebugInterruptsDisabled target)" + by (unfold ExternalDebugInterruptsDisabled_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_ESBOperation[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_ESBOperation arg0)" + by (unfold AArch64_ESBOperation_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_vESBOperation[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_vESBOperation arg0)" + by (unfold AArch64_vESBOperation_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DebugTarget[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DebugTarget arg0)" + by (unfold DebugTarget_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_SSAdvance[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (SSAdvance arg0)" + by (unfold SSAdvance_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_NextInstrAddr[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (NextInstrAddr N)" + by (unfold NextInstrAddr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CallSecureMonitor[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CallSecureMonitor immediate)" + by (unfold AArch64_CallSecureMonitor_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CallHypervisor[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CallHypervisor immediate)" + by (unfold AArch64_CallHypervisor_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CallSupervisor[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CallSupervisor immediate)" + by (unfold AArch64_CallSupervisor_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CheckIllegalState[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CheckIllegalState arg0)" + by (unfold AArch64_CheckIllegalState_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CheckForSMCUndefOrTrap[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CheckForSMCUndefOrTrap imm)" + by (unfold AArch64_CheckForSMCUndefOrTrap_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_WFxTrap[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_WFxTrap target_el is_wfe)" + by (unfold AArch64_WFxTrap_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CheckForWFxTrap[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CheckForWFxTrap target_el is_wfe)" + by (unfold AArch64_CheckForWFxTrap_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_AdvSIMDFPAccessTrap[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_AdvSIMDFPAccessTrap target_el)" + by (unfold AArch64_AdvSIMDFPAccessTrap_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CheckFPAdvSIMDTrap[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CheckFPAdvSIMDTrap arg0)" + by (unfold AArch64_CheckFPAdvSIMDTrap_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CheckFPAdvSIMDEnabled[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CheckFPAdvSIMDEnabled arg0)" + by (unfold AArch64_CheckFPAdvSIMDEnabled_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CheckFPAdvSIMDEnabled64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CheckFPAdvSIMDEnabled64 arg0)" + by (unfold CheckFPAdvSIMDEnabled64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapabilityAccessTrap[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CapabilityAccessTrap target_el)" + by (unfold CapabilityAccessTrap_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CheckCapabilitiesEnabled[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CheckCapabilitiesEnabled arg0)" + by (unfold CheckCapabilitiesEnabled_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_IsTagSettingDisabled[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (IsTagSettingDisabled arg0)" + by (unfold IsTagSettingDisabled_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_TakePhysicalIRQException[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_TakePhysicalIRQException arg0)" + by (unfold AArch64_TakePhysicalIRQException_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_SoftwareBreakpoint[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_SoftwareBreakpoint immediate)" + by (unfold AArch64_SoftwareBreakpoint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_PCAlignmentFault[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_PCAlignmentFault arg0)" + by (unfold AArch64_PCAlignmentFault_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_CheckPCAlignment[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_CheckPCAlignment arg0)" + by (unfold AArch64_CheckPCAlignment_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CheckPCCCapability[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CheckPCCCapability arg0)" + by (unfold CheckPCCCapability_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_ExceptionReturnToCapability[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_ExceptionReturnToCapability new_pcc__arg spsr)" + by (unfold AArch64_ExceptionReturnToCapability_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DecodeRegExtend[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DecodeRegExtend op)" + by (unfold DecodeRegExtend_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ExtendReg[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ExtendReg N reg exttype shift)" + by (unfold ExtendReg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DecodeBitMasks[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DecodeBitMasks M immN imms immr immediate)" + by (unfold DecodeBitMasks_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DecodeShift[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (DecodeShift op)" + by (unfold DecodeShift_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ShiftReg[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (ShiftReg N reg shiftype amount)" + by (unfold ShiftReg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Prefetch[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (Prefetch address prfop)" + by (unfold Prefetch_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_ReduceCombine[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (ReduceCombine op lo hi)" + by (unfold ReduceCombine_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Reduce16[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Reduce16 op input esize)" + by (unfold Reduce16_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Reduce32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Reduce32 op input esize)" + by (unfold Reduce32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Reduce64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Reduce64 op input esize)" + by (unfold Reduce64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Reduce128[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Reduce128 op input esize)" + by (unfold Reduce128_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Reduce256[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Reduce256 op input esize)" + by (unfold Reduce256_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Reduce512[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Reduce512 op input esize)" + by (unfold Reduce512_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Reduce1024[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Reduce1024 op input esize)" + by (unfold Reduce1024_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Reduce2048[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Reduce2048 op input esize)" + by (unfold Reduce2048_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Reduce[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Reduce op input esize)" + by (unfold Reduce_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DCPSInstruction[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DCPSInstruction target_el)" + by (unfold DCPSInstruction_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_DRPSInstruction[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (DRPSInstruction arg0)" + by (unfold DRPSInstruction_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapSetBounds[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapSetBounds c__arg req_len exact)" + by (unfold CapSetBounds_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapGetRepresentableMask[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapGetRepresentableMask len)" + by (unfold CapGetRepresentableMask_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapIsBaseAboveLimit[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapIsBaseAboveLimit c__arg)" + by (unfold CapIsBaseAboveLimit_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapIsSubSetOf[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapIsSubSetOf a b)" + by (unfold CapIsSubSetOf_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapGetOffset[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapGetOffset c__arg)" + by (unfold CapGetOffset_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapGetLength[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapGetLength c__arg)" + by (unfold CapGetLength_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapIsInBounds[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapIsInBounds c__arg)" + by (unfold CapIsInBounds_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CapSetOffset[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (CapSetOffset c__arg offset)" + by (unfold CapSetOffset_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VACheckPerm[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (VACheckPerm base requested_perms)" + by (unfold VACheckPerm_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_VAAdd[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (VAAdd v offset)" + by (unfold VAAdd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CAP_DC_CIVAC[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CAP_DC_CIVAC cval)" + by (unfold CAP_DC_CIVAC_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CAP_DC_CVAC[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CAP_DC_CVAC cval)" + by (unfold CAP_DC_CVAC_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CAP_DC_CVADP[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CAP_DC_CVADP cval)" + by (unfold CAP_DC_CVADP_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CAP_DC_CVAP[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CAP_DC_CVAP cval)" + by (unfold CAP_DC_CVAP_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CAP_DC_CVAU[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CAP_DC_CVAU cval)" + by (unfold CAP_DC_CVAU_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CAP_DC_IVAC[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CAP_DC_IVAC cval)" + by (unfold CAP_DC_IVAC_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CAP_DC_ZVA[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CAP_DC_ZVA cval)" + by (unfold CAP_DC_ZVA_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_CAP_IC_IVAU[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (CAP_IC_IVAU cval)" + by (unfold CAP_IC_IVAU_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_AArch64_SysInstrWithCapability[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (AArch64_SysInstrWithCapability op0 op1 crn crm op2 val_name)" + by (unfold AArch64_SysInstrWithCapability_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_FetchNextInstr[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (FetchNextInstr arg0)" + by (unfold FetchNextInstr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_Step_PC[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (Step_PC arg0)" + by (unfold Step_PC_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ADD_C_CIS_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ADD_C_CIS_C d imm n)" + by (unfold execute_ADD_C_CIS_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ADD_C_CIS_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ADD_C_CIS_C A sh imm12 Cn Cd)" + by (unfold decode_ADD_C_CIS_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ADD_C_CRI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ADD_C_CRI_C d extend_type m n shift)" + by (unfold execute_ADD_C_CRI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ADD_C_CRI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ADD_C_CRI_C Rm option_name imm3 Cn Cd)" + by (unfold decode_ADD_C_CRI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ADRDP_C_ID_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ADRDP_C_ID_C P d imm)" + by (unfold execute_ADRDP_C_ID_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ADRDP_C_ID_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ADRDP_C_ID_C op immlo P immhi Rd)" + by (unfold decode_ADRDP_C_ID_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ADRP_C_IP_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ADRP_C_IP_C P d imm)" + by (unfold execute_ADRP_C_IP_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ADRP_C_IP_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ADRP_C_IP_C op immlo P immhi Rd)" + by (unfold decode_ADRP_C_IP_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ADRP_C_I_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ADRP_C_I_C P d imm)" + by (unfold execute_ADRP_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ADRP_C_I_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ADRP_C_I_C op immlo P immhi Rd)" + by (unfold decode_ADRP_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ADR_C_I_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ADR_C_I_C d imm)" + by (unfold execute_ADR_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ADR_C_I_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ADR_C_I_C op immlo P immhi Rd)" + by (unfold decode_ADR_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDARB_R_R_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDARB_R_R_B acctype datasize n regsize t__arg)" + by (unfold execute_ALDARB_R_R_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDARB_R_R_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDARB_R_R_B L Rn Rt)" + by (unfold decode_ALDARB_R_R_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDAR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDAR_C_R_C acctype n t__arg)" + by (unfold execute_ALDAR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDAR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDAR_C_R_C L Rn Ct)" + by (unfold decode_ALDAR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDAR_R_R_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDAR_R_R_32 acctype datasize n regsize t__arg)" + by (unfold execute_ALDAR_R_R_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDAR_R_R_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDAR_R_R_32 L Rn Rt)" + by (unfold decode_ALDAR_R_R_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDRB_R_RRB_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDRB_R_RRB_B extend_type m n regsize l__550 shift t__arg)" + by (unfold execute_ALDRB_R_RRB_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDRB_R_RRB_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDRB_R_RRB_B L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDRB_R_RRB_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDRB_R_RUI_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDRB_R_RUI_B datasize n offset regsize t__arg)" + by (unfold execute_ALDRB_R_RUI_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDRB_R_RUI_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDRB_R_RUI_B L imm9 op Rn Rt)" + by (unfold decode_ALDRB_R_RUI_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDRH_R_RRB_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDRH_R_RRB_32 extend_type m n regsize l__549 shift t__arg)" + by (unfold execute_ALDRH_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDRH_R_RRB_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDRH_R_RRB_32 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDRH_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDRSB_R_RRB_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDRSB_R_RRB_32 extend_type m n regsize l__545 shift t__arg)" + by (unfold execute_ALDRSB_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDRSB_R_RRB_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDRSB_R_RRB_32 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDRSB_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDRSB_R_RRB_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDRSB_R_RRB_64 extend_type m n regsize l__546 shift t__arg)" + by (unfold execute_ALDRSB_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDRSB_R_RRB_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDRSB_R_RRB_64 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDRSB_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDRSH_R_RRB_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDRSH_R_RRB_32 extend_type m n regsize l__543 shift t__arg)" + by (unfold execute_ALDRSH_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDRSH_R_RRB_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDRSH_R_RRB_32 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDRSH_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDRSH_R_RRB_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDRSH_R_RRB_64 extend_type m n regsize l__544 shift t__arg)" + by (unfold execute_ALDRSH_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDRSH_R_RRB_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDRSH_R_RRB_64 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDRSH_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDR_C_RRB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDR_C_RRB_C extend_type m n shift t__arg)" + by (unfold execute_ALDR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDR_C_RRB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDR_C_RRB_C Rm sign sz S L Rn Ct)" + by (unfold decode_ALDR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDR_C_RUI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDR_C_RUI_C n offset t__arg)" + by (unfold execute_ALDR_C_RUI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDR_C_RUI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDR_C_RUI_C L imm9 op Rn Ct)" + by (unfold decode_ALDR_C_RUI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDR_R_RRB_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDR_R_RRB_32 extend_type m n regsize l__548 shift t__arg)" + by (unfold execute_ALDR_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDR_R_RRB_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDR_R_RRB_32 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDR_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDR_R_RRB_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDR_R_RRB_64 extend_type m n regsize l__547 shift t__arg)" + by (unfold execute_ALDR_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDR_R_RRB_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDR_R_RRB_64 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDR_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDR_R_RUI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDR_R_RUI_32 datasize n offset regsize t__arg)" + by (unfold execute_ALDR_R_RUI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDR_R_RUI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDR_R_RUI_32 L imm9 op Rn Rt)" + by (unfold decode_ALDR_R_RUI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDR_R_RUI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDR_R_RUI_64 datasize n offset regsize t__arg)" + by (unfold execute_ALDR_R_RUI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDR_R_RUI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDR_R_RUI_64 L imm9 op Rn Rt)" + by (unfold decode_ALDR_R_RUI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDR_V_RRB_D[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDR_V_RRB_D extend_type m n l__542 shift t__arg)" + by (unfold execute_ALDR_V_RRB_D_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDR_V_RRB_D[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDR_V_RRB_D L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDR_V_RRB_D_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDR_V_RRB_S[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDR_V_RRB_S extend_type m n l__541 shift t__arg)" + by (unfold execute_ALDR_V_RRB_S_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDR_V_RRB_S[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDR_V_RRB_S L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDR_V_RRB_S_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDURB_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDURB_R_RI_32 datasize n offset regsize t__arg)" + by (unfold execute_ALDURB_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDURB_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDURB_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURB_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDURH_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDURH_R_RI_32 datasize n offset regsize t__arg)" + by (unfold execute_ALDURH_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDURH_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDURH_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURH_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDURSB_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDURSB_R_RI_32 datasize n offset regsize t__arg)" + by (unfold execute_ALDURSB_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDURSB_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDURSB_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURSB_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDURSB_R_RI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDURSB_R_RI_64 datasize n offset regsize t__arg)" + by (unfold execute_ALDURSB_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDURSB_R_RI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDURSB_R_RI_64 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURSB_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDURSH_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDURSH_R_RI_32 datasize n offset regsize t__arg)" + by (unfold execute_ALDURSH_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDURSH_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDURSH_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURSH_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDURSH_R_RI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDURSH_R_RI_64 datasize n offset regsize t__arg)" + by (unfold execute_ALDURSH_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDURSH_R_RI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDURSH_R_RI_64 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURSH_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDURSW_R_RI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDURSW_R_RI_64 datasize n offset regsize t__arg)" + by (unfold execute_ALDURSW_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDURSW_R_RI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDURSW_R_RI_64 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURSW_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDUR_C_RI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDUR_C_RI_C n offset t__arg)" + by (unfold execute_ALDUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDUR_C_RI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDUR_C_RI_C op1 V imm9 op2 Rn Ct)" + by (unfold decode_ALDUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDUR_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDUR_R_RI_32 datasize n offset regsize t__arg)" + by (unfold execute_ALDUR_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDUR_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDUR_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDUR_R_RI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDUR_R_RI_64 datasize n offset regsize t__arg)" + by (unfold execute_ALDUR_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDUR_R_RI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDUR_R_RI_64 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDUR_V_RI_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDUR_V_RI_B datasize n offset t__arg)" + by (unfold execute_ALDUR_V_RI_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDUR_V_RI_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDUR_V_RI_B op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_V_RI_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDUR_V_RI_D[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDUR_V_RI_D datasize n offset t__arg)" + by (unfold execute_ALDUR_V_RI_D_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDUR_V_RI_D[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDUR_V_RI_D op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_V_RI_D_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDUR_V_RI_H[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDUR_V_RI_H datasize n offset t__arg)" + by (unfold execute_ALDUR_V_RI_H_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDUR_V_RI_H[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDUR_V_RI_H op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_V_RI_H_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDUR_V_RI_Q[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDUR_V_RI_Q datasize n offset t__arg)" + by (unfold execute_ALDUR_V_RI_Q_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDUR_V_RI_Q[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDUR_V_RI_Q op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_V_RI_Q_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALDUR_V_RI_S[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALDUR_V_RI_S datasize n offset t__arg)" + by (unfold execute_ALDUR_V_RI_S_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALDUR_V_RI_S[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALDUR_V_RI_S op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_V_RI_S_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALIGND_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALIGND_C_CI_C align d n)" + by (unfold execute_ALIGND_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALIGND_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALIGND_C_CI_C imm6 U Cn Cd)" + by (unfold decode_ALIGND_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ALIGNU_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ALIGNU_C_CI_C align d n)" + by (unfold execute_ALIGNU_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ALIGNU_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ALIGNU_C_CI_C imm6 U Cn Cd)" + by (unfold decode_ALIGNU_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTLRB_R_R_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTLRB_R_R_B acctype datasize n t__arg)" + by (unfold execute_ASTLRB_R_R_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTLRB_R_R_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTLRB_R_R_B L Rn Rt)" + by (unfold decode_ASTLRB_R_R_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTLR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTLR_C_R_C acctype n t__arg)" + by (unfold execute_ASTLR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTLR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTLR_C_R_C L Rn Ct)" + by (unfold decode_ASTLR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTLR_R_R_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTLR_R_R_32 acctype datasize n t__arg)" + by (unfold execute_ASTLR_R_R_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTLR_R_R_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTLR_R_R_32 L Rn Rt)" + by (unfold decode_ASTLR_R_R_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTRB_R_RRB_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTRB_R_RRB_B extend_type m n l__556 shift t__arg)" + by (unfold execute_ASTRB_R_RRB_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTRB_R_RRB_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTRB_R_RRB_B L Rm sign sz S opc Rn Rt)" + by (unfold decode_ASTRB_R_RRB_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTRB_R_RUI_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTRB_R_RUI_B datasize n offset t__arg)" + by (unfold execute_ASTRB_R_RUI_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTRB_R_RUI_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTRB_R_RUI_B L imm9 op Rn Rt)" + by (unfold decode_ASTRB_R_RUI_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTRH_R_RRB_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTRH_R_RRB_32 extend_type m n l__555 shift t__arg)" + by (unfold execute_ASTRH_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTRH_R_RRB_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTRH_R_RRB_32 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ASTRH_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTR_C_RRB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTR_C_RRB_C extend_type m n shift t__arg)" + by (unfold execute_ASTR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTR_C_RRB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTR_C_RRB_C Rm sign sz S L Rn Ct)" + by (unfold decode_ASTR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTR_C_RUI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTR_C_RUI_C n offset t__arg)" + by (unfold execute_ASTR_C_RUI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTR_C_RUI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTR_C_RUI_C L imm9 op Rn Ct)" + by (unfold decode_ASTR_C_RUI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTR_R_RRB_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTR_R_RRB_32 extend_type m n l__554 shift t__arg)" + by (unfold execute_ASTR_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTR_R_RRB_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTR_R_RRB_32 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ASTR_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTR_R_RRB_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTR_R_RRB_64 extend_type m n l__553 shift t__arg)" + by (unfold execute_ASTR_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTR_R_RRB_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTR_R_RRB_64 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ASTR_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTR_R_RUI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTR_R_RUI_32 datasize n offset t__arg)" + by (unfold execute_ASTR_R_RUI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTR_R_RUI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTR_R_RUI_32 L imm9 op Rn Rt)" + by (unfold decode_ASTR_R_RUI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTR_R_RUI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTR_R_RUI_64 datasize n offset t__arg)" + by (unfold execute_ASTR_R_RUI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTR_R_RUI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTR_R_RUI_64 L imm9 op Rn Rt)" + by (unfold decode_ASTR_R_RUI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTR_V_RRB_D[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTR_V_RRB_D extend_type m n l__552 shift t__arg)" + by (unfold execute_ASTR_V_RRB_D_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTR_V_RRB_D[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTR_V_RRB_D L Rm sign sz S opc Rn Rt)" + by (unfold decode_ASTR_V_RRB_D_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTR_V_RRB_S[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTR_V_RRB_S extend_type m n l__551 shift t__arg)" + by (unfold execute_ASTR_V_RRB_S_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTR_V_RRB_S[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTR_V_RRB_S L Rm sign sz S opc Rn Rt)" + by (unfold decode_ASTR_V_RRB_S_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTURB_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTURB_R_RI_32 datasize n offset t__arg)" + by (unfold execute_ASTURB_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTURB_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTURB_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTURB_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTURH_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTURH_R_RI_32 datasize n offset t__arg)" + by (unfold execute_ASTURH_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTURH_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTURH_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTURH_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTUR_C_RI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTUR_C_RI_C n offset t__arg)" + by (unfold execute_ASTUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTUR_C_RI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTUR_C_RI_C op1 V imm9 op2 Rn Ct)" + by (unfold decode_ASTUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTUR_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTUR_R_RI_32 datasize n offset t__arg)" + by (unfold execute_ASTUR_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTUR_R_RI_32[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTUR_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTUR_R_RI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTUR_R_RI_64 datasize n offset t__arg)" + by (unfold execute_ASTUR_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTUR_R_RI_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTUR_R_RI_64 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTUR_V_RI_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTUR_V_RI_B datasize n offset t__arg)" + by (unfold execute_ASTUR_V_RI_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTUR_V_RI_B[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTUR_V_RI_B op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_V_RI_B_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTUR_V_RI_D[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTUR_V_RI_D datasize n offset t__arg)" + by (unfold execute_ASTUR_V_RI_D_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTUR_V_RI_D[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTUR_V_RI_D op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_V_RI_D_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTUR_V_RI_H[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTUR_V_RI_H datasize n offset t__arg)" + by (unfold execute_ASTUR_V_RI_H_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTUR_V_RI_H[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTUR_V_RI_H op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_V_RI_H_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTUR_V_RI_Q[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTUR_V_RI_Q datasize n offset t__arg)" + by (unfold execute_ASTUR_V_RI_Q_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTUR_V_RI_Q[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTUR_V_RI_Q op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_V_RI_Q_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ASTUR_V_RI_S[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ASTUR_V_RI_S datasize n offset t__arg)" + by (unfold execute_ASTUR_V_RI_S_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ASTUR_V_RI_S[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ASTUR_V_RI_S op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_V_RI_S_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BICFLGS_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BICFLGS_C_CI_C d mask__arg n)" + by (unfold execute_BICFLGS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BICFLGS_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BICFLGS_C_CI_C imm8 Cn Cd)" + by (unfold decode_BICFLGS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BICFLGS_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BICFLGS_C_CR_C d m n)" + by (unfold execute_BICFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BICFLGS_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BICFLGS_C_CR_C Rm opc Cn Cd)" + by (unfold decode_BICFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BLRR_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BLRR_C_C branch_type n)" + by (unfold execute_BLRR_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BLRR_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BLRR_C_C opc Cn)" + by (unfold decode_BLRR_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BLRS_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BLRS_C_C branch_type n)" + by (unfold execute_BLRS_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BLRS_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BLRS_C_C opc Cn)" + by (unfold decode_BLRS_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BLRS_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BLRS_C_C_C branch_type m n)" + by (unfold execute_BLRS_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BLRS_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BLRS_C_C_C Cm opc Cn)" + by (unfold decode_BLRS_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BLR_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BLR_CI_C branch_type n offset)" + by (unfold execute_BLR_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BLR_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BLR_CI_C imm7 Cn)" + by (unfold decode_BLR_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BLR_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BLR_C_C branch_type n)" + by (unfold execute_BLR_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BLR_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BLR_C_C opc Cn)" + by (unfold decode_BLR_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BRR_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BRR_C_C branch_type n)" + by (unfold execute_BRR_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BRR_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BRR_C_C opc Cn)" + by (unfold decode_BRR_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BRS_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BRS_C_C branch_type n)" + by (unfold execute_BRS_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BRS_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BRS_C_C opc Cn)" + by (unfold decode_BRS_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BRS_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BRS_C_C_C branch_type m n)" + by (unfold execute_BRS_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BRS_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BRS_C_C_C Cm opc Cn)" + by (unfold decode_BRS_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BR_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BR_CI_C branch_type n offset)" + by (unfold execute_BR_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BR_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BR_CI_C imm7 Cn)" + by (unfold decode_BR_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BR_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BR_C_C branch_type n)" + by (unfold execute_BR_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BR_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BR_C_C opc Cn)" + by (unfold decode_BR_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BUILD_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BUILD_C_C_C d m n)" + by (unfold execute_BUILD_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BUILD_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BUILD_C_C_C Cm opc Cn Cd)" + by (unfold decode_BUILD_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_BX___C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_BX___C branch_type)" + by (unfold execute_BX___C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_BX___C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_BX___C opc)" + by (unfold decode_BX___C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CASAL_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CASAL_C_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_CASAL_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CASAL_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CASAL_C_R_C L Cs R Rn Ct)" + by (unfold decode_CASAL_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CASA_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CASA_C_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_CASA_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CASA_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CASA_C_R_C L Cs R Rn Ct)" + by (unfold decode_CASA_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CASL_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CASL_C_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_CASL_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CASL_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CASL_C_R_C L Cs R Rn Ct)" + by (unfold decode_CASL_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CAS_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CAS_C_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_CAS_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CAS_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CAS_C_R_C L Cs R Rn Ct)" + by (unfold decode_CAS_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CFHI_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CFHI_R_C_C d n)" + by (unfold execute_CFHI_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CFHI_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CFHI_R_C_C opc Cn Rd)" + by (unfold decode_CFHI_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CHKEQ___CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CHKEQ___CC_C m n)" + by (unfold execute_CHKEQ___CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CHKEQ___CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CHKEQ___CC_C Cm opc Cn)" + by (unfold decode_CHKEQ___CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CHKSLD_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CHKSLD_C_C n)" + by (unfold execute_CHKSLD_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CHKSLD_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CHKSLD_C_C opc Cn)" + by (unfold decode_CHKSLD_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CHKSSU_C_CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CHKSSU_C_CC_C d m n)" + by (unfold execute_CHKSSU_C_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CHKSSU_C_CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CHKSSU_C_CC_C Cm opc Cn Cd)" + by (unfold decode_CHKSSU_C_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CHKSS___CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CHKSS___CC_C m n)" + by (unfold execute_CHKSS___CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CHKSS___CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CHKSS___CC_C Cm opc Cn)" + by (unfold decode_CHKSS___CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CHKTGD_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CHKTGD_C_C n)" + by (unfold execute_CHKTGD_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CHKTGD_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CHKTGD_C_C opc Cn)" + by (unfold decode_CHKTGD_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CLRPERM_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CLRPERM_C_CI_C d imm n)" + by (unfold execute_CLRPERM_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CLRPERM_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CLRPERM_C_CI_C perm__arg Cn Cd)" + by (unfold decode_CLRPERM_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CLRPERM_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CLRPERM_C_CR_C d m n)" + by (unfold execute_CLRPERM_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CLRPERM_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CLRPERM_C_CR_C Rm Cn Cd)" + by (unfold decode_CLRPERM_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CLRTAG_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CLRTAG_C_C_C d n)" + by (unfold execute_CLRTAG_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CLRTAG_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CLRTAG_C_C_C opc Cn Cd)" + by (unfold decode_CLRTAG_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CPYTYPE_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CPYTYPE_C_C_C d m n)" + by (unfold execute_CPYTYPE_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CPYTYPE_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CPYTYPE_C_C_C Cm opc Cn Cd)" + by (unfold decode_CPYTYPE_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CPYVALUE_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CPYVALUE_C_C_C d m n)" + by (unfold execute_CPYVALUE_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CPYVALUE_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CPYVALUE_C_C_C Cm opc Cn Cd)" + by (unfold decode_CPYVALUE_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CPY_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CPY_C_C_C d n)" + by (unfold execute_CPY_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CPY_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CPY_C_C_C opc Cn Cd)" + by (unfold decode_CPY_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CSEAL_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CSEAL_C_C_C d m n)" + by (unfold execute_CSEAL_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CSEAL_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CSEAL_C_C_C Cm opc Cn Cd)" + by (unfold decode_CSEAL_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CSEL_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CSEL_C_CI_C cond d m n)" + by (unfold execute_CSEL_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CSEL_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CSEL_C_CI_C Cm cond Cn Cd)" + by (unfold decode_CSEL_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CTHI_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CTHI_C_CR_C d m n)" + by (unfold execute_CTHI_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CTHI_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CTHI_C_CR_C Rm opc Cn Cd)" + by (unfold decode_CTHI_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CVTDZ_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CVTDZ_C_R_C d n)" + by (unfold execute_CVTDZ_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CVTDZ_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CVTDZ_C_R_C opc Rn Cd)" + by (unfold decode_CVTDZ_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CVTD_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CVTD_C_R_C d n)" + by (unfold execute_CVTD_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CVTD_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CVTD_C_R_C opc Rn Cd)" + by (unfold decode_CVTD_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CVTD_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CVTD_R_C_C d n)" + by (unfold execute_CVTD_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CVTD_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CVTD_R_C_C opc Cn Rd)" + by (unfold decode_CVTD_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CVTPZ_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CVTPZ_C_R_C d n)" + by (unfold execute_CVTPZ_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CVTPZ_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CVTPZ_C_R_C opc Rn Cd)" + by (unfold decode_CVTPZ_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CVTP_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CVTP_C_R_C d n)" + by (unfold execute_CVTP_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CVTP_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CVTP_C_R_C opc Rn Cd)" + by (unfold decode_CVTP_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CVTP_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CVTP_R_C_C d n)" + by (unfold execute_CVTP_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CVTP_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CVTP_R_C_C opc Cn Rd)" + by (unfold decode_CVTP_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CVTZ_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CVTZ_C_CR_C d m n)" + by (unfold execute_CVTZ_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CVTZ_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CVTZ_C_CR_C Rm Cn Cd)" + by (unfold decode_CVTZ_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CVT_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CVT_C_CR_C d m n)" + by (unfold execute_CVT_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CVT_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CVT_C_CR_C Rm Cn Cd)" + by (unfold decode_CVT_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_CVT_R_CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_CVT_R_CC_C d m n)" + by (unfold execute_CVT_R_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_CVT_R_CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_CVT_R_CC_C Cm Cn Rd)" + by (unfold decode_CVT_R_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_EORFLGS_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_EORFLGS_C_CI_C d mask__arg n)" + by (unfold execute_EORFLGS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_EORFLGS_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_EORFLGS_C_CI_C imm8 Cn Cd)" + by (unfold decode_EORFLGS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_EORFLGS_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_EORFLGS_C_CR_C d m n)" + by (unfold execute_EORFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_EORFLGS_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_EORFLGS_C_CR_C Rm opc Cn Cd)" + by (unfold decode_EORFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_GCBASE_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_GCBASE_R_C_C d n)" + by (unfold execute_GCBASE_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_GCBASE_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_GCBASE_R_C_C opc Cn Rd)" + by (unfold decode_GCBASE_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_GCFLGS_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_GCFLGS_R_C_C d n)" + by (unfold execute_GCFLGS_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_GCFLGS_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_GCFLGS_R_C_C opc Cn Rd)" + by (unfold decode_GCFLGS_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_GCLEN_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_GCLEN_R_C_C d n)" + by (unfold execute_GCLEN_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_GCLEN_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_GCLEN_R_C_C opc Cn Rd)" + by (unfold decode_GCLEN_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_GCLIM_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_GCLIM_R_C_C d n)" + by (unfold execute_GCLIM_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_GCLIM_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_GCLIM_R_C_C opc Cn Rd)" + by (unfold decode_GCLIM_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_GCOFF_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_GCOFF_R_C_C d n)" + by (unfold execute_GCOFF_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_GCOFF_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_GCOFF_R_C_C opc Cn Rd)" + by (unfold decode_GCOFF_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_GCPERM_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_GCPERM_R_C_C d n)" + by (unfold execute_GCPERM_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_GCPERM_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_GCPERM_R_C_C opc Cn Rd)" + by (unfold decode_GCPERM_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_GCSEAL_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_GCSEAL_R_C_C d n)" + by (unfold execute_GCSEAL_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_GCSEAL_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_GCSEAL_R_C_C opc Cn Rd)" + by (unfold decode_GCSEAL_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_GCTAG_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_GCTAG_R_C_C d n)" + by (unfold execute_GCTAG_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_GCTAG_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_GCTAG_R_C_C opc Cn Rd)" + by (unfold decode_GCTAG_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_GCTYPE_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_GCTYPE_R_C_C d n)" + by (unfold execute_GCTYPE_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_GCTYPE_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_GCTYPE_R_C_C opc Cn Rd)" + by (unfold decode_GCTYPE_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_GCVALUE_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_GCVALUE_R_C_C d n)" + by (unfold execute_GCVALUE_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_GCVALUE_R_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_GCVALUE_R_C_C opc Cn Rd)" + by (unfold decode_GCVALUE_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDAPR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDAPR_C_R_C acctype n t__arg)" + by (unfold execute_LDAPR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDAPR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDAPR_C_R_C Rn Ct)" + by (unfold decode_LDAPR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDAR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDAR_C_R_C acctype n t__arg)" + by (unfold execute_LDAR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDAR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDAR_C_R_C L Rn Ct)" + by (unfold decode_LDAR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDAXP_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDAXP_C_R_C acctype n t__arg t2)" + by (unfold execute_LDAXP_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDAXP_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDAXP_C_R_C L Ct2 Rn Ct)" + by (unfold decode_LDAXP_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDAXR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDAXR_C_R_C acctype n t__arg)" + by (unfold execute_LDAXR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDAXR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDAXR_C_R_C L Rn Ct)" + by (unfold decode_LDAXR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDCT_R_R[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDCT_R_R n t__arg)" + by (unfold execute_LDCT_R_R_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDCT_R_R[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDCT_R_R opc Rn Rt)" + by (unfold decode_LDCT_R_R_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDNP_C_RIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDNP_C_RIB_C acctype n offset t__arg t2)" + by (unfold execute_LDNP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDNP_C_RIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDNP_C_RIB_C L imm7 Ct2 Rn Ct)" + by (unfold decode_LDNP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDPBLR_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDPBLR_C_C_C branch_type n t__arg)" + by (unfold execute_LDPBLR_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDPBLR_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDPBLR_C_C_C opc Cn Ct)" + by (unfold decode_LDPBLR_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDPBR_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDPBR_C_C_C branch_type n t__arg)" + by (unfold execute_LDPBR_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDPBR_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDPBR_C_C_C opc Cn Ct)" + by (unfold decode_LDPBR_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDP_CC_RIAW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDP_CC_RIAW_C acctype n offset t__arg t2)" + by (unfold execute_LDP_CC_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDP_CC_RIAW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDP_CC_RIAW_C L imm7 Ct2 Rn Ct)" + by (unfold decode_LDP_CC_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDP_C_RIBW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDP_C_RIBW_C acctype n offset t__arg t2)" + by (unfold execute_LDP_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDP_C_RIBW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDP_C_RIBW_C L imm7 Ct2 Rn Ct)" + by (unfold decode_LDP_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDP_C_RIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDP_C_RIB_C acctype n offset t__arg t2)" + by (unfold execute_LDP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDP_C_RIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDP_C_RIB_C L imm7 Ct2 Rn Ct)" + by (unfold decode_LDP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDR_C_I_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDR_C_I_C offset t__arg)" + by (unfold execute_LDR_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDR_C_I_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDR_C_I_C imm17 Ct)" + by (unfold decode_LDR_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDR_C_RIAW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDR_C_RIAW_C n offset t__arg)" + by (unfold execute_LDR_C_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDR_C_RIAW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDR_C_RIAW_C opc imm9 Rn Ct)" + by (unfold decode_LDR_C_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDR_C_RIBW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDR_C_RIBW_C n offset t__arg)" + by (unfold execute_LDR_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDR_C_RIBW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDR_C_RIBW_C opc imm9 Rn Ct)" + by (unfold decode_LDR_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDR_C_RRB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDR_C_RRB_C extend_type m n shift t__arg)" + by (unfold execute_LDR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDR_C_RRB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDR_C_RRB_C opc Rm sign sz S Rn Ct)" + by (unfold decode_LDR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDR_C_RUIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDR_C_RUIB_C n offset t__arg)" + by (unfold execute_LDR_C_RUIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDR_C_RUIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDR_C_RUIB_C L imm12 Rn Ct)" + by (unfold decode_LDR_C_RUIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDTR_C_RIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDTR_C_RIB_C n offset t__arg)" + by (unfold execute_LDTR_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDTR_C_RIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDTR_C_RIB_C opc imm9 Rn Ct)" + by (unfold decode_LDTR_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDUR_C_RI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDUR_C_RI_C n offset t__arg)" + by (unfold execute_LDUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDUR_C_RI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDUR_C_RI_C opc imm9 Rn Ct)" + by (unfold decode_LDUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDXP_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDXP_C_R_C acctype n t__arg t2)" + by (unfold execute_LDXP_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDXP_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDXP_C_R_C L Ct2 Rn Ct)" + by (unfold decode_LDXP_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_LDXR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_LDXR_C_R_C acctype n t__arg)" + by (unfold execute_LDXR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_LDXR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_LDXR_C_R_C L Rn Ct)" + by (unfold decode_LDXR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_MRS_C_I_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_MRS_C_I_C sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg)" + by (unfold execute_MRS_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_MRS_C_I_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_MRS_C_I_C L o0 op1 CRn CRm op2 Ct)" + by (unfold decode_MRS_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_MSR_C_I_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_MSR_C_I_C sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg)" + by (unfold execute_MSR_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_MSR_C_I_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_MSR_C_I_C L o0 op1 CRn CRm op2 Ct)" + by (unfold decode_MSR_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ORRFLGS_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ORRFLGS_C_CI_C d mask__arg n)" + by (unfold execute_ORRFLGS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ORRFLGS_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ORRFLGS_C_CI_C imm8 Cn Cd)" + by (unfold decode_ORRFLGS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_ORRFLGS_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_ORRFLGS_C_CR_C d m n)" + by (unfold execute_ORRFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ORRFLGS_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ORRFLGS_C_CR_C Rm opc Cn Cd)" + by (unfold decode_ORRFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_RETR_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_RETR_C_C branch_type n)" + by (unfold execute_RETR_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_RETR_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_RETR_C_C opc Cn)" + by (unfold decode_RETR_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_RETS_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_RETS_C_C branch_type n)" + by (unfold execute_RETS_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_RETS_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_RETS_C_C opc Cn)" + by (unfold decode_RETS_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_RETS_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_RETS_C_C_C branch_type m n)" + by (unfold execute_RETS_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_RETS_C_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_RETS_C_C_C Cm opc Cn)" + by (unfold decode_RETS_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_RET_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_RET_C_C branch_type n)" + by (unfold execute_RET_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_RET_C_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_RET_C_C opc Cn)" + by (unfold decode_RET_C_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_RRLEN_R_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_RRLEN_R_R_C d n)" + by (unfold execute_RRLEN_R_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_RRLEN_R_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_RRLEN_R_R_C opc Rn Rd)" + by (unfold decode_RRLEN_R_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_RRMASK_R_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_RRMASK_R_R_C d n)" + by (unfold execute_RRMASK_R_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_RRMASK_R_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_RRMASK_R_R_C opc Rn Rd)" + by (unfold decode_RRMASK_R_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SCBNDSE_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SCBNDSE_C_CR_C d m n)" + by (unfold execute_SCBNDSE_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SCBNDSE_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SCBNDSE_C_CR_C Rm opc Cn Cd)" + by (unfold decode_SCBNDSE_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SCBNDS_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SCBNDS_C_CI_C d length__arg n)" + by (unfold execute_SCBNDS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SCBNDS_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SCBNDS_C_CI_C imm6 S Cn Cd)" + by (unfold decode_SCBNDS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SCBNDS_C_CI_S[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SCBNDS_C_CI_S d length__arg n)" + by (unfold execute_SCBNDS_C_CI_S_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SCBNDS_C_CI_S[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SCBNDS_C_CI_S imm6 S Cn Cd)" + by (unfold decode_SCBNDS_C_CI_S_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SCBNDS_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SCBNDS_C_CR_C d m n)" + by (unfold execute_SCBNDS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SCBNDS_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SCBNDS_C_CR_C Rm opc Cn Cd)" + by (unfold decode_SCBNDS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SCFLGS_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SCFLGS_C_CR_C d m n)" + by (unfold execute_SCFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SCFLGS_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SCFLGS_C_CR_C Rm Cn Cd)" + by (unfold decode_SCFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SCOFF_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SCOFF_C_CR_C d m n)" + by (unfold execute_SCOFF_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SCOFF_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SCOFF_C_CR_C Rm opc Cn Cd)" + by (unfold decode_SCOFF_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SCTAG_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SCTAG_C_CR_C d m n)" + by (unfold execute_SCTAG_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SCTAG_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SCTAG_C_CR_C Rm Cn Cd)" + by (unfold decode_SCTAG_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SCVALUE_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SCVALUE_C_CR_C d m n)" + by (unfold execute_SCVALUE_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SCVALUE_C_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SCVALUE_C_CR_C Rm opc Cn Cd)" + by (unfold decode_SCVALUE_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SEAL_C_CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SEAL_C_CC_C d m n)" + by (unfold execute_SEAL_C_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SEAL_C_CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SEAL_C_CC_C Cm opc Cn Cd)" + by (unfold decode_SEAL_C_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SEAL_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SEAL_C_CI_C d f n)" + by (unfold execute_SEAL_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SEAL_C_CI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SEAL_C_CI_C form Cn Cd)" + by (unfold decode_SEAL_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STCT_R_R[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STCT_R_R n t__arg)" + by (unfold execute_STCT_R_R_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STCT_R_R[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STCT_R_R opc Rn Rt)" + by (unfold decode_STCT_R_R_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STLR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STLR_C_R_C acctype n t__arg)" + by (unfold execute_STLR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STLR_C_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STLR_C_R_C L Rn Ct)" + by (unfold decode_STLR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STLXP_R_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STLXP_R_CR_C acctype n s__arg t__arg t2)" + by (unfold execute_STLXP_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STLXP_R_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STLXP_R_CR_C L Rs__arg Ct2 Rn Ct)" + by (unfold decode_STLXP_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STLXR_R_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STLXR_R_CR_C acctype n s__arg t__arg)" + by (unfold execute_STLXR_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STLXR_R_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STLXR_R_CR_C L Rs__arg Rn Ct)" + by (unfold decode_STLXR_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STNP_C_RIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STNP_C_RIB_C acctype n offset t__arg t2)" + by (unfold execute_STNP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STNP_C_RIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STNP_C_RIB_C L imm7 Ct2 Rn Ct)" + by (unfold decode_STNP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STP_CC_RIAW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STP_CC_RIAW_C acctype n offset t__arg t2)" + by (unfold execute_STP_CC_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STP_CC_RIAW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STP_CC_RIAW_C L imm7 Ct2 Rn Ct)" + by (unfold decode_STP_CC_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STP_C_RIBW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STP_C_RIBW_C acctype n offset t__arg t2)" + by (unfold execute_STP_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STP_C_RIBW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STP_C_RIBW_C L imm7 Ct2 Rn Ct)" + by (unfold decode_STP_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STP_C_RIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STP_C_RIB_C acctype n offset t__arg t2)" + by (unfold execute_STP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STP_C_RIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STP_C_RIB_C L imm7 Ct2 Rn Ct)" + by (unfold decode_STP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STR_C_RIAW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STR_C_RIAW_C n offset t__arg)" + by (unfold execute_STR_C_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STR_C_RIAW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STR_C_RIAW_C opc imm9 Rn Ct)" + by (unfold decode_STR_C_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STR_C_RIBW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STR_C_RIBW_C n offset t__arg)" + by (unfold execute_STR_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STR_C_RIBW_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STR_C_RIBW_C opc imm9 Rn Ct)" + by (unfold decode_STR_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STR_C_RRB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STR_C_RRB_C extend_type m n shift t__arg)" + by (unfold execute_STR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STR_C_RRB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STR_C_RRB_C opc Rm sign sz S Rn Ct)" + by (unfold decode_STR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STR_C_RUIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STR_C_RUIB_C n offset t__arg)" + by (unfold execute_STR_C_RUIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STR_C_RUIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STR_C_RUIB_C L imm12 Rn Ct)" + by (unfold decode_STR_C_RUIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STTR_C_RIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STTR_C_RIB_C n offset t__arg)" + by (unfold execute_STTR_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STTR_C_RIB_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STTR_C_RIB_C opc imm9 Rn Ct)" + by (unfold decode_STTR_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STUR_C_RI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STUR_C_RI_C n offset t__arg)" + by (unfold execute_STUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STUR_C_RI_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STUR_C_RI_C opc imm9 Rn Ct)" + by (unfold decode_STUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STXP_R_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STXP_R_CR_C acctype n s__arg t__arg t2)" + by (unfold execute_STXP_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STXP_R_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STXP_R_CR_C L Rs__arg Ct2 Rn Ct)" + by (unfold decode_STXP_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_STXR_R_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_STXR_R_CR_C acctype n s__arg t__arg)" + by (unfold execute_STXR_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_STXR_R_CR_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_STXR_R_CR_C L Rs__arg Rn Ct)" + by (unfold decode_STXR_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SUBS_R_CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SUBS_R_CC_C d m n)" + by (unfold execute_SUBS_R_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SUBS_R_CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SUBS_R_CC_C Cm Cn Rd)" + by (unfold decode_SUBS_R_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SUB_C_CIS_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SUB_C_CIS_C d imm n)" + by (unfold execute_SUB_C_CIS_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SUB_C_CIS_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SUB_C_CIS_C A sh imm12 Cn Cd)" + by (unfold decode_SUB_C_CIS_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SWPAL_CC_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SWPAL_CC_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_SWPAL_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SWPAL_CC_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SWPAL_CC_R_C A R Cs Rn Ct)" + by (unfold decode_SWPAL_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SWPA_CC_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SWPA_CC_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_SWPA_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SWPA_CC_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SWPA_CC_R_C A R Cs Rn Ct)" + by (unfold decode_SWPA_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SWPL_CC_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SWPL_CC_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_SWPL_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SWPL_CC_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SWPL_CC_R_C A R Cs Rn Ct)" + by (unfold decode_SWPL_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_SWP_CC_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_SWP_CC_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_SWP_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_SWP_CC_R_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_SWP_CC_R_C A R Cs Rn Ct)" + by (unfold decode_SWP_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_UNSEAL_C_CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_UNSEAL_C_CC_C d m n)" + by (unfold execute_UNSEAL_C_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_UNSEAL_C_CC_C[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_UNSEAL_C_CC_C Cm opc Cn Cd)" + by (unfold decode_UNSEAL_C_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n neg)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd Rd Rn b__0 U b__1)" + by (unfold decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd Rd Rn b__0 U)" + by (unfold decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_arithmetic_add_sub_carry[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_arithmetic_add_sub_carry d (datasize :: 'datasize::len itself) m n setflags sub_op)" + by (unfold execute_aarch64_instrs_integer_arithmetic_add_sub_carry_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_adc_aarch64_instrs_integer_arithmetic_add_sub_carry[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_adc_aarch64_instrs_integer_arithmetic_add_sub_carry Rd Rn Rm S op b__0)" + by (unfold decode_adc_aarch64_instrs_integer_arithmetic_add_sub_carry_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_adcs_aarch64_instrs_integer_arithmetic_add_sub_carry[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_adcs_aarch64_instrs_integer_arithmetic_add_sub_carry Rd Rn Rm S op b__0)" + by (unfold decode_adcs_aarch64_instrs_integer_arithmetic_add_sub_carry_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_arithmetic_add_sub_extendedreg d (datasize :: 'datasize::len itself) extend_type m n setflags shift sub_op)" + by (unfold execute_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_add_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_add_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg Rd Rn imm3 option_name Rm S op b__0)" + by (unfold decode_add_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_arithmetic_add_sub_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_arithmetic_add_sub_immediate d datasize imm n setflags sub_op)" + by (unfold execute_aarch64_instrs_integer_arithmetic_add_sub_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_add_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_add_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate Rd Rn imm12 sh S op b__0)" + by (unfold decode_add_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg d (datasize :: 'datasize::len itself) m n setflags shift_amount shift_type sub_op)" + by (unfold execute_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_add_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_add_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg Rd Rn imm6 Rm shift S op b__0)" + by (unfold decode_add_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd Rd Rn Rm b__0 U)" + by (unfold decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow d datasize elements l__40 m n part round__arg sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_addhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_addhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_addhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_reduce_add_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_add_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_add_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_addp_advsimd_pair_aarch64_instrs_vector_reduce_add_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_addp_advsimd_pair_aarch64_instrs_vector_reduce_add_sisd Rd Rn b__0)" + by (unfold decode_addp_advsimd_pair_aarch64_instrs_vector_reduce_add_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair d l__179 elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_addp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_addp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair Rd Rn Rm b__0 b__1)" + by (unfold decode_addp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_adds_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_adds_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg Rd Rn imm3 option_name Rm S op b__0)" + by (unfold decode_adds_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_adds_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_adds_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate Rd Rn imm12 sh S op b__0)" + by (unfold decode_adds_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_adds_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_adds_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg Rd Rn imm6 Rm shift S op b__0)" + by (unfold decode_adds_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_reduce_add_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_add_simd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_add_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_addv_advsimd_aarch64_instrs_vector_reduce_add_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_addv_advsimd_aarch64_instrs_vector_reduce_add_simd Rd Rn b__0 b__1)" + by (unfold decode_addv_advsimd_aarch64_instrs_vector_reduce_add_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_aes_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_aes_round d decrypt n)" + by (unfold execute_aarch64_instrs_vector_crypto_aes_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_aesd_advsimd_aarch64_instrs_vector_crypto_aes_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_aesd_advsimd_aarch64_instrs_vector_crypto_aes_round Rd Rn D)" + by (unfold decode_aesd_advsimd_aarch64_instrs_vector_crypto_aes_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_aese_advsimd_aarch64_instrs_vector_crypto_aes_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_aese_advsimd_aarch64_instrs_vector_crypto_aes_round Rd Rn D)" + by (unfold decode_aese_advsimd_aarch64_instrs_vector_crypto_aes_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_aes_mix[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_aes_mix d decrypt n)" + by (unfold execute_aarch64_instrs_vector_crypto_aes_mix_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_aesimc_advsimd_aarch64_instrs_vector_crypto_aes_mix[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_aesimc_advsimd_aarch64_instrs_vector_crypto_aes_mix Rd Rn D)" + by (unfold decode_aesimc_advsimd_aarch64_instrs_vector_crypto_aes_mix_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_aesmc_advsimd_aarch64_instrs_vector_crypto_aes_mix[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_aesmc_advsimd_aarch64_instrs_vector_crypto_aes_mix Rd Rn D)" + by (unfold decode_aesmc_advsimd_aarch64_instrs_vector_crypto_aes_mix_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr d (datasize :: 'datasize::len itself) invert m n op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_and_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_and_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0)" + by (unfold decode_and_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_logical_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_logical_immediate d datasize imm n op setflags)" + by (unfold execute_aarch64_instrs_integer_logical_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_and_log_imm_aarch64_instrs_integer_logical_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_and_log_imm_aarch64_instrs_integer_logical_immediate Rd Rn imms immr N opc b__0)" + by (unfold decode_and_log_imm_aarch64_instrs_integer_logical_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_logical_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_logical_shiftedreg d (datasize :: 'datasize::len itself) invert m n op setflags shift_amount shift_type)" + by (unfold execute_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_and_log_shift_aarch64_instrs_integer_logical_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_and_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_and_log_shift_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ands_log_imm_aarch64_instrs_integer_logical_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ands_log_imm_aarch64_instrs_integer_logical_immediate Rd Rn imms immr N opc b__0)" + by (unfold decode_ands_log_imm_aarch64_instrs_integer_logical_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ands_log_shift_aarch64_instrs_integer_logical_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ands_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_ands_log_shift_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_shift_variable[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_shift_variable d (datasize :: 'datasize::len itself) m n shift_type)" + by (unfold execute_aarch64_instrs_integer_shift_variable_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_asrv_aarch64_instrs_integer_shift_variable[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_asrv_aarch64_instrs_integer_shift_variable Rd Rn op2 Rm b__0)" + by (unfold decode_asrv_aarch64_instrs_integer_shift_variable_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_branch_conditional_cond[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_branch_conditional_cond condition offset)" + by (unfold execute_aarch64_instrs_branch_conditional_cond_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_b_cond_aarch64_instrs_branch_conditional_cond[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_b_cond_aarch64_instrs_branch_conditional_cond cond imm19)" + by (unfold decode_b_cond_aarch64_instrs_branch_conditional_cond_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_branch_unconditional_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_branch_unconditional_immediate branch_type offset)" + by (unfold execute_aarch64_instrs_branch_unconditional_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_b_uncond_aarch64_instrs_branch_unconditional_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_b_uncond_aarch64_instrs_branch_unconditional_immediate imm26 op)" + by (unfold decode_b_uncond_aarch64_instrs_branch_unconditional_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3_bcax[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3_bcax a d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3_bcax_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_bcax_advsimd_aarch64_instrs_vector_crypto_sha3_bcax[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_bcax_advsimd_aarch64_instrs_vector_crypto_sha3_bcax Rd Rn Ra Rm)" + by (unfold decode_bcax_advsimd_aarch64_instrs_vector_crypto_sha3_bcax_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_bitfield[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_bitfield R S d datasize extend__arg inzero n tmask wmask)" + by (unfold execute_aarch64_instrs_integer_bitfield_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_bfm_aarch64_instrs_integer_bitfield[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_bfm_aarch64_instrs_integer_bitfield Rd Rn imms immr N opc b__0)" + by (unfold decode_bfm_aarch64_instrs_integer_bitfield_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_logical[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_logical datasize imm operation rd)" + by (unfold execute_aarch64_instrs_vector_logical_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_bic_advsimd_imm_aarch64_instrs_vector_logical[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_bic_advsimd_imm_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_bic_advsimd_imm_aarch64_instrs_vector_logical_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_bic_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_bic_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0)" + by (unfold decode_bic_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_bic_log_shift_aarch64_instrs_integer_logical_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_bic_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_bic_log_shift_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_bics_aarch64_instrs_integer_logical_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_bics_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_bics_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor d (datasize :: 'datasize::len itself) m n op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_bif_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_bif_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0)" + by (unfold decode_bif_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_bit_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_bit_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0)" + by (unfold decode_bit_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_bl_aarch64_instrs_branch_unconditional_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_bl_aarch64_instrs_branch_unconditional_immediate imm26 op)" + by (unfold decode_bl_aarch64_instrs_branch_unconditional_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_branch_unconditional_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_branch_unconditional_register branch_type n)" + by (unfold execute_aarch64_instrs_branch_unconditional_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_blr_aarch64_instrs_branch_unconditional_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_blr_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)" + by (unfold decode_blr_aarch64_instrs_branch_unconditional_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_blra_aarch64_instrs_branch_unconditional_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_blra_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)" + by (unfold decode_blra_aarch64_instrs_branch_unconditional_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_br_aarch64_instrs_branch_unconditional_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_br_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)" + by (unfold decode_br_aarch64_instrs_branch_unconditional_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_bra_aarch64_instrs_branch_unconditional_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_bra_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)" + by (unfold decode_bra_aarch64_instrs_branch_unconditional_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_system_exceptions_debug_breakpoint[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_system_exceptions_debug_breakpoint comment)" + by (unfold execute_aarch64_instrs_system_exceptions_debug_breakpoint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint imm16)" + by (unfold decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_bsl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_bsl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0)" + by (unfold decode_bsl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_atomicops_cas_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_atomicops_cas_single (datasize :: 'datasize::len itself) ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg)" + by (unfold execute_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cas_aarch64_instrs_memory_atomicops_cas_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cas_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs__arg L b__0)" + by (unfold decode_cas_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_casb_aarch64_instrs_memory_atomicops_cas_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_casb_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs__arg L b__0)" + by (unfold decode_casb_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cash_aarch64_instrs_memory_atomicops_cas_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cash_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs__arg L b__0)" + by (unfold decode_cash_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_atomicops_cas_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_atomicops_cas_pair l__38 ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg)" + by (unfold execute_aarch64_instrs_memory_atomicops_cas_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_casp_aarch64_instrs_memory_atomicops_cas_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_casp_aarch64_instrs_memory_atomicops_cas_pair Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_casp_aarch64_instrs_memory_atomicops_cas_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_branch_conditional_compare[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_branch_conditional_compare (datasize :: 'datasize::len itself) iszero__arg offset t__arg)" + by (unfold execute_aarch64_instrs_branch_conditional_compare_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cbnz_aarch64_instrs_branch_conditional_compare[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cbnz_aarch64_instrs_branch_conditional_compare Rt imm19 op b__0)" + by (unfold decode_cbnz_aarch64_instrs_branch_conditional_compare_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cbz_aarch64_instrs_branch_conditional_compare[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cbz_aarch64_instrs_branch_conditional_compare Rt imm19 op b__0)" + by (unfold decode_cbz_aarch64_instrs_branch_conditional_compare_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_conditional_compare_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_conditional_compare_immediate condition datasize flags__arg imm n sub_op)" + by (unfold execute_aarch64_instrs_integer_conditional_compare_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ccmn_imm_aarch64_instrs_integer_conditional_compare_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ccmn_imm_aarch64_instrs_integer_conditional_compare_immediate nzcv Rn cond imm5 op b__0)" + by (unfold decode_ccmn_imm_aarch64_instrs_integer_conditional_compare_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_conditional_compare_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_conditional_compare_register condition (datasize :: 'datasize::len itself) flags__arg m n sub_op)" + by (unfold execute_aarch64_instrs_integer_conditional_compare_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ccmn_reg_aarch64_instrs_integer_conditional_compare_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ccmn_reg_aarch64_instrs_integer_conditional_compare_register nzcv Rn cond Rm op b__0)" + by (unfold decode_ccmn_reg_aarch64_instrs_integer_conditional_compare_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ccmp_imm_aarch64_instrs_integer_conditional_compare_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ccmp_imm_aarch64_instrs_integer_conditional_compare_immediate nzcv Rn cond imm5 op b__0)" + by (unfold decode_ccmp_imm_aarch64_instrs_integer_conditional_compare_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ccmp_reg_aarch64_instrs_integer_conditional_compare_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ccmp_reg_aarch64_instrs_integer_conditional_compare_register nzcv Rn cond Rm op b__0)" + by (unfold decode_ccmp_reg_aarch64_instrs_integer_conditional_compare_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_clsz[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_clsz countop d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_clsz_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cls_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cls_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz Rd Rn b__0 U b__1)" + by (unfold decode_cls_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_arithmetic_cnt[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_arithmetic_cnt d (datasize :: 'datasize::len itself) n opcode)" + by (unfold execute_aarch64_instrs_integer_arithmetic_cnt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cls_int_aarch64_instrs_integer_arithmetic_cnt[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cls_int_aarch64_instrs_integer_arithmetic_cnt Rd Rn op b__0)" + by (unfold decode_cls_int_aarch64_instrs_integer_arithmetic_cnt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_clz_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_clz_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz Rd Rn b__0 U b__1)" + by (unfold decode_clz_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_clz_int_aarch64_instrs_integer_arithmetic_cnt[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_clz_int_aarch64_instrs_integer_arithmetic_cnt Rd Rn op b__0)" + by (unfold decode_clz_int_aarch64_instrs_integer_arithmetic_cnt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd and_test d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd Rd Rn Rm b__0 U)" + by (unfold decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd cmp_eq d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1)" + by (unfold decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U)" + by (unfold decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1)" + by (unfold decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U)" + by (unfold decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1)" + by (unfold decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U)" + by (unfold decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1)" + by (unfold decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U)" + by (unfold decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_simd Rd Rn b__0 b__1)" + by (unfold decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd Rd Rn b__0)" + by (unfold decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd Rd Rn Rm b__0 U)" + by (unfold decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_cnt[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_cnt d (datasize :: 'datasize::len itself) elements esize n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cnt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_cnt_advsimd_aarch64_instrs_vector_arithmetic_unary_cnt[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_cnt_advsimd_aarch64_instrs_vector_arithmetic_unary_cnt Rd Rn size__arg b__0)" + by (unfold decode_cnt_advsimd_aarch64_instrs_vector_arithmetic_unary_cnt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_crc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_crc crc32c d m n l__155)" + by (unfold execute_aarch64_instrs_integer_crc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_crc32_aarch64_instrs_integer_crc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_crc32_aarch64_instrs_integer_crc Rd Rn b__0 C Rm sf)" + by (unfold decode_crc32_aarch64_instrs_integer_crc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_crc32c_aarch64_instrs_integer_crc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_crc32c_aarch64_instrs_integer_crc Rd Rn b__0 C Rm sf)" + by (unfold decode_crc32c_aarch64_instrs_integer_crc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_conditional_select[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_conditional_select condition d (datasize :: 'datasize::len itself) else_inc else_inv m n)" + by (unfold execute_aarch64_instrs_integer_conditional_select_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_csel_aarch64_instrs_integer_conditional_select[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_csel_aarch64_instrs_integer_conditional_select Rd Rn o2 cond Rm op b__0)" + by (unfold decode_csel_aarch64_instrs_integer_conditional_select_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_csinc_aarch64_instrs_integer_conditional_select[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_csinc_aarch64_instrs_integer_conditional_select Rd Rn o2 cond Rm op b__0)" + by (unfold decode_csinc_aarch64_instrs_integer_conditional_select_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_csinv_aarch64_instrs_integer_conditional_select[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_csinv_aarch64_instrs_integer_conditional_select Rd Rn o2 cond Rm op b__0)" + by (unfold decode_csinv_aarch64_instrs_integer_conditional_select_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_csneg_aarch64_instrs_integer_conditional_select[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_csneg_aarch64_instrs_integer_conditional_select Rd Rn o2 cond Rm op b__0)" + by (unfold decode_csneg_aarch64_instrs_integer_conditional_select_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_system_exceptions_debug_exception[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_system_exceptions_debug_exception target_level)" + by (unfold execute_aarch64_instrs_system_exceptions_debug_exception_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_dcps1_aarch64_instrs_system_exceptions_debug_exception[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_dcps1_aarch64_instrs_system_exceptions_debug_exception LL imm16)" + by (unfold decode_dcps1_aarch64_instrs_system_exceptions_debug_exception_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_dcps2_aarch64_instrs_system_exceptions_debug_exception[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_dcps2_aarch64_instrs_system_exceptions_debug_exception LL imm16)" + by (unfold decode_dcps2_aarch64_instrs_system_exceptions_debug_exception_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_dcps3_aarch64_instrs_system_exceptions_debug_exception[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_dcps3_aarch64_instrs_system_exceptions_debug_exception LL imm16)" + by (unfold decode_dcps3_aarch64_instrs_system_exceptions_debug_exception_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_system_barriers_dmb[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (execute_aarch64_instrs_system_barriers_dmb domain types)" + by (unfold execute_aarch64_instrs_system_barriers_dmb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_dmb_aarch64_instrs_system_barriers_dmb[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (decode_dmb_aarch64_instrs_system_barriers_dmb Rt opc CRm CRn op1 op0 L)" + by (unfold decode_dmb_aarch64_instrs_system_barriers_dmb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_branch_unconditional_dret[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_branch_unconditional_dret arg0)" + by (unfold execute_aarch64_instrs_branch_unconditional_dret_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_drps_aarch64_instrs_branch_unconditional_dret[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_drps_aarch64_instrs_branch_unconditional_dret arg0)" + by (unfold decode_drps_aarch64_instrs_branch_unconditional_dret_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_system_barriers_dsb[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (execute_aarch64_instrs_system_barriers_dsb domain types)" + by (unfold execute_aarch64_instrs_system_barriers_dsb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_dsb_aarch64_instrs_system_barriers_dsb[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (decode_dsb_aarch64_instrs_system_barriers_dsb Rt opc CRm CRn op1 op0 L)" + by (unfold decode_dsb_aarch64_instrs_system_barriers_dsb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg n)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_simd Rd Rn b__0 b__1)" + by (unfold decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd Rd Rn b__0)" + by (unfold decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_transfer_integer_dup[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_integer_dup d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_transfer_integer_dup_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_dup_advsimd_gen_aarch64_instrs_vector_transfer_integer_dup[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_dup_advsimd_gen_aarch64_instrs_vector_transfer_integer_dup Rd Rn b__0 b__1)" + by (unfold decode_dup_advsimd_gen_aarch64_instrs_vector_transfer_integer_dup_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_eon_aarch64_instrs_integer_logical_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_eon_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_eon_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3_eor3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3_eor3 a d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3_eor3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_eor3_advsimd_aarch64_instrs_vector_crypto_sha3_eor3[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_eor3_advsimd_aarch64_instrs_vector_crypto_sha3_eor3 Rd Rn Ra Rm)" + by (unfold decode_eor3_advsimd_aarch64_instrs_vector_crypto_sha3_eor3_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_eor_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_eor_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0)" + by (unfold decode_eor_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_eor_log_imm_aarch64_instrs_integer_logical_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_eor_log_imm_aarch64_instrs_integer_logical_immediate Rd Rn imms immr N opc b__0)" + by (unfold decode_eor_log_imm_aarch64_instrs_integer_logical_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_eor_log_shift_aarch64_instrs_integer_logical_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_eor_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_eor_log_shift_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_branch_unconditional_eret[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_branch_unconditional_eret arg0)" + by (unfold execute_aarch64_instrs_branch_unconditional_eret_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_eret_aarch64_instrs_branch_unconditional_eret[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_eret_aarch64_instrs_branch_unconditional_eret op4 Rn M A)" + by (unfold decode_eret_aarch64_instrs_branch_unconditional_eret_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ereta_aarch64_instrs_branch_unconditional_eret[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ereta_aarch64_instrs_branch_unconditional_eret op4 Rn M A)" + by (unfold decode_ereta_aarch64_instrs_branch_unconditional_eret_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_system_hints[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_system_hints op)" + by (cases op; simp; no_reg_writes_toI) + +lemma no_reg_writes_to_decode_esb_aarch64_instrs_system_hints[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_esb_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_esb_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_extract[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_extract d l__47 m n position)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_extract_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ext_advsimd_aarch64_instrs_vector_transfer_vector_extract[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ext_advsimd_aarch64_instrs_vector_transfer_vector_extract Rd Rn imm4 Rm b__0)" + by (unfold decode_ext_advsimd_aarch64_instrs_vector_transfer_vector_extract_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_ins_ext_extract_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_ins_ext_extract_immediate d l__36 lsb__arg m n)" + by (unfold execute_aarch64_instrs_integer_ins_ext_extract_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_extr_aarch64_instrs_integer_ins_ext_extract_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_extr_aarch64_instrs_integer_ins_ext_extract_immediate Rd Rn imms Rm N b__0)" + by (unfold decode_extr_aarch64_instrs_integer_ins_ext_extract_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd abs__arg d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd Rd Rn Rm U b__0)" + by (unfold decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd Rd Rn Rm)" + by (unfold decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_sisd Rd Rn Rm b__0)" + by (unfold decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n neg)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float Rd Rn b__0 U b__1)" + by (unfold decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16 Rd Rn U b__0)" + by (unfold decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_unary[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_unary d (datasize :: 'datasize::len itself) fpop n)" + by (unfold execute_aarch64_instrs_float_arithmetic_unary_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fabs_float_aarch64_instrs_float_arithmetic_unary[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fabs_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0)" + by (unfold decode_fabs_float_aarch64_instrs_float_arithmetic_unary_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd abs__arg cmp d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16 d l__163 elements (esize :: 'esize::len itself) m n pair)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp Rd Rn Rm b__0 U b__1)" + by (unfold decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16 Rd Rn Rm U b__0)" + by (unfold decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_add_sub[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_add_sub d (datasize :: 'datasize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_float_arithmetic_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fadd_float_aarch64_instrs_float_arithmetic_add_sub[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fadd_float_aarch64_instrs_float_arithmetic_add_sub Rd Rn op Rm b__0)" + by (unfold decode_fadd_float_aarch64_instrs_float_arithmetic_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_reduce_fp16_add_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_fp16_add_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_add_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_add_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_add_sisd Rd Rn sz)" + by (unfold decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_add_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp_add_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp_add_sisd Rd Rn b__0)" + by (unfold decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp_add_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp Rd Rn Rm b__0 U b__1)" + by (unfold decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16 Rd Rn Rm U b__0)" + by (unfold decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_compare_cond[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_compare_cond condition (datasize :: 'datasize::len itself) flags__arg m n signal_all_nans)" + by (unfold execute_aarch64_instrs_float_compare_cond_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fccmp_float_aarch64_instrs_float_compare_cond[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fccmp_float_aarch64_instrs_float_compare_cond nzcv op Rn cond Rm b__0)" + by (unfold decode_fccmp_float_aarch64_instrs_float_compare_cond_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fccmpe_float_aarch64_instrs_float_compare_cond[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fccmpe_float_aarch64_instrs_float_compare_cond nzcv op Rn cond Rm b__0)" + by (unfold decode_fccmpe_float_aarch64_instrs_float_compare_cond_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0)" + by (unfold decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U)" + by (unfold decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0)" + by (unfold decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U)" + by (unfold decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0)" + by (unfold decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U)" + by (unfold decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0)" + by (unfold decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U)" + by (unfold decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_simd Rd Rn b__0 b__1)" + by (unfold decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_sisd Rd Rn b__0)" + by (unfold decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_simd Rd Rn b__0)" + by (unfold decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd Rd Rn)" + by (unfold decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_compare_uncond[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_compare_uncond cmp_with_zero (datasize :: 'datasize::len itself) m n signal_all_nans)" + by (unfold execute_aarch64_instrs_float_compare_uncond_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmp_float_aarch64_instrs_float_compare_uncond[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmp_float_aarch64_instrs_float_compare_uncond opc Rn Rm b__0)" + by (unfold decode_fcmp_float_aarch64_instrs_float_compare_uncond_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcmpe_float_aarch64_instrs_float_compare_uncond[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcmpe_float_aarch64_instrs_float_compare_uncond opc Rn Rm b__0)" + by (unfold decode_fcmpe_float_aarch64_instrs_float_compare_uncond_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_move_fp_select[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_move_fp_select condition d (datasize :: 'datasize::len itself) m n)" + by (unfold execute_aarch64_instrs_float_move_fp_select_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcsel_float_aarch64_instrs_float_move_fp_select[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcsel_float_aarch64_instrs_float_move_fp_select Rd Rn cond Rm b__0)" + by (unfold decode_fcsel_float_aarch64_instrs_float_move_fp_select_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_convert_fp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_convert_fp d (dstsize :: 'dstsize::len itself) n (srcsize :: 'srcsize::len itself))" + by (unfold execute_aarch64_instrs_float_convert_fp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvt_float_aarch64_instrs_float_convert_fp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvt_float_aarch64_instrs_float_convert_fp Rd Rn b__0 b__1)" + by (unfold decode_fcvt_float_aarch64_instrs_float_convert_fp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n rounding is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd Rd Rn b__0 U b__1)" + by (unfold decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd Rd Rn b__0 U)" + by (unfold decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd Rd Rn U b__0)" + by (unfold decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd Rd Rn U)" + by (unfold decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_convert_int d (fltsize :: 'fltsize::len itself) (intsize :: 'intsize::len itself) n op part rounding is_unsigned)" + by (unfold execute_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtas_float_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtas_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtas_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd Rd Rn b__0 U b__1)" + by (unfold decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd Rd Rn b__0 U)" + by (unfold decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd Rd Rn U b__0)" + by (unfold decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd Rd Rn U)" + by (unfold decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtau_float_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtau_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtau_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_float_widen[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_float_widen d datasize elements l__177 n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_float_widen_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtl_advsimd_aarch64_instrs_vector_arithmetic_unary_float_widen[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtl_advsimd_aarch64_instrs_vector_arithmetic_unary_float_widen Rd Rn b__0 Q)" + by (unfold decode_fcvtl_advsimd_aarch64_instrs_vector_arithmetic_unary_float_widen_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n rounding is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtms_float_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtms_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtms_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtmu_float_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtmu_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtmu_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_float_narrow[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_float_narrow d datasize elements l__202 n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_float_narrow_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_narrow[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_narrow Rd Rn b__0 Q)" + by (unfold decode_fcvtn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_narrow_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtns_float_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtns_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtns_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtnu_float_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtnu_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtnu_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtps_float_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtps_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtps_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtpu_float_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtpu_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtpu_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd d l__53 elements esize n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_simd Rd Rn sz Q)" + by (unfold decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd Rd Rn sz)" + by (unfold decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_shift_conv_float_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_conv_float_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) fracbits n rounding is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_conv_float_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd Rd Rn immb b__0 U b__1)" + by (unfold decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd Rd Rn immb b__0 U)" + by (unfold decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_convert_fix[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_convert_fix d (fltsize :: 'fltsize::len itself) fracbits (intsize :: 'intsize::len itself) n op rounding is_unsigned)" + by (unfold execute_aarch64_instrs_float_convert_fix_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzs_float_fix_aarch64_instrs_float_convert_fix[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzs_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1)" + by (unfold decode_fcvtzs_float_fix_aarch64_instrs_float_convert_fix_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzs_float_int_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzs_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtzs_float_int_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd Rd Rn immb b__0 U b__1)" + by (unfold decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd Rd Rn immb b__0 U)" + by (unfold decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzu_float_fix_aarch64_instrs_float_convert_fix[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzu_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1)" + by (unfold decode_fcvtzu_float_fix_aarch64_instrs_float_convert_fix_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fcvtzu_float_int_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fcvtzu_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtzu_float_int_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div Rd Rn Rm b__0 b__1)" + by (unfold decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16 Rd Rn Rm b__0)" + by (unfold decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_div[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_div d (datasize :: 'datasize::len itself) m n)" + by (unfold execute_aarch64_instrs_float_arithmetic_div_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fdiv_float_aarch64_instrs_float_arithmetic_div[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fdiv_float_aarch64_instrs_float_arithmetic_div Rd Rn Rm b__0)" + by (unfold decode_fdiv_float_aarch64_instrs_float_arithmetic_div_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fjcvtzs_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fjcvtzs_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fjcvtzs_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_mul_add_sub[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_mul_add_sub a d (datasize :: 'datasize::len itself) m n op1_neg opa_neg)" + by (unfold execute_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0)" + by (unfold decode_fmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 d l__401 elements (esize :: 'esize::len itself) m minimum n pair)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0)" + by (unfold decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_max_min[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_max_min d (datasize :: 'datasize::len itself) m n operation)" + by (unfold execute_aarch64_instrs_float_arithmetic_max_min_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmax_float_aarch64_instrs_float_arithmetic_max_min[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmax_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0)" + by (unfold decode_fmax_float_aarch64_instrs_float_arithmetic_max_min_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 d l__435 elements (esize :: 'esize::len itself) m minimum n pair)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0)" + by (unfold decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxnm_float_aarch64_instrs_float_arithmetic_max_min[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxnm_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0)" + by (unfold decode_fmaxnm_float_aarch64_instrs_float_arithmetic_max_min_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_reduce_fp16_maxnm_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_fp16_maxnm_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_maxnm_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd Rd Rn sz o1)" + by (unfold decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd Rd Rn b__0 o1)" + by (unfold decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0)" + by (unfold decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_reduce_fp16_maxnm_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_fp16_maxnm_simd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_maxnm_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd Rd Rn o1 b__0)" + by (unfold decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd Rd Rn b__0 o1 b__1)" + by (unfold decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_reduce_fp16_max_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_fp16_max_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_max_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd Rd Rn sz o1)" + by (unfold decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd Rd Rn b__0 o1)" + by (unfold decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0)" + by (unfold decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_reduce_fp16_max_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_fp16_max_simd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_max_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd Rd Rn o1 b__0)" + by (unfold decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd Rd Rn b__0 o1 b__1)" + by (unfold decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0)" + by (unfold decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmin_float_aarch64_instrs_float_arithmetic_max_min[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmin_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0)" + by (unfold decode_fmin_float_aarch64_instrs_float_arithmetic_max_min_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0)" + by (unfold decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminnm_float_aarch64_instrs_float_arithmetic_max_min[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminnm_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0)" + by (unfold decode_fminnm_float_aarch64_instrs_float_arithmetic_max_min_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd Rd Rn sz o1)" + by (unfold decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd Rd Rn b__0 o1)" + by (unfold decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0)" + by (unfold decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd Rd Rn o1 b__0)" + by (unfold decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd Rd Rn b__0 o1 b__1)" + by (unfold decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd Rd Rn sz o1)" + by (unfold decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd Rd Rn b__0 o1)" + by (unfold decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0)" + by (unfold decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd Rd Rn o1 b__0)" + by (unfold decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd Rd Rn b__0 o1 b__1)" + by (unfold decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd Rd Rn b__0 o2 Rm M L)" + by (unfold decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd Rd Rn b__0 o2 Rm M L b__1 b__2)" + by (unfold decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused Rd Rn Rm a b__0)" + by (unfold decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused Rd Rn Rm b__0 op b__1)" + by (unfold decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd Rd Rn b__0 o2 Rm M L)" + by (unfold decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd Rd Rn b__0 o2 Rm M L b__1 b__2)" + by (unfold decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused Rd Rn Rm a b__0)" + by (unfold decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused Rd Rn Rm b__0 op b__1)" + by (unfold decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_fp16_movi[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_fp16_movi datasize imm rd)" + by (unfold execute_aarch64_instrs_vector_fp16_movi_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmov_advsimd_aarch64_instrs_vector_fp16_movi[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmov_advsimd_aarch64_instrs_vector_fp16_movi Rd h g f e d c__arg b a b__0)" + by (unfold decode_fmov_advsimd_aarch64_instrs_vector_fp16_movi_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmov_advsimd_aarch64_instrs_vector_logical[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmov_advsimd_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_fmov_advsimd_aarch64_instrs_vector_logical_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmov_float_aarch64_instrs_float_arithmetic_unary[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmov_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0)" + by (unfold decode_fmov_float_aarch64_instrs_float_arithmetic_unary_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmov_float_gen_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmov_float_gen_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fmov_float_gen_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_move_fp_imm[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_move_fp_imm d datasize imm)" + by (unfold execute_aarch64_instrs_float_move_fp_imm_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmov_float_imm_aarch64_instrs_float_move_fp_imm[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmov_float_imm_aarch64_instrs_float_move_fp_imm Rd imm8 b__0)" + by (unfold decode_fmov_float_imm_aarch64_instrs_float_move_fp_imm_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0)" + by (unfold decode_fmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m mulx_op n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd Rd Rn b__0 Rm M L U b__1)" + by (unfold decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd Rd Rn b__0 Rm M L U)" + by (unfold decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd Rd Rn b__0 Rm M L b__1 U b__2)" + by (unfold decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd Rd Rn b__0 Rm M L b__1 U)" + by (unfold decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product Rd Rn Rm b__0)" + by (unfold decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_product[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_product Rd Rn Rm b__0 b__1)" + by (unfold decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_product_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_mul_product[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_mul_product d (datasize :: 'datasize::len itself) m n negated)" + by (unfold execute_aarch64_instrs_float_arithmetic_mul_product_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmul_float_aarch64_instrs_float_arithmetic_mul_product[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmul_float_aarch64_instrs_float_arithmetic_mul_product Rd Rn op Rm b__0)" + by (unfold decode_fmul_float_aarch64_instrs_float_arithmetic_mul_product_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd Rd Rn b__0 Rm M L U b__1)" + by (unfold decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd Rd Rn b__0 Rm M L U)" + by (unfold decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd Rd Rn b__0 Rm M L b__1 U b__2)" + by (unfold decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd Rd Rn b__0 Rm M L b__1 U)" + by (unfold decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_simd Rd Rn Rm b__0)" + by (unfold decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd Rd Rn Rm)" + by (unfold decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_simd Rd Rn Rm b__0 b__1)" + by (unfold decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_sisd Rd Rn Rm b__0)" + by (unfold decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float Rd Rn b__0 U b__1)" + by (unfold decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16 Rd Rn U b__0)" + by (unfold decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fneg_float_aarch64_instrs_float_arithmetic_unary[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fneg_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0)" + by (unfold decode_fneg_float_aarch64_instrs_float_arithmetic_unary_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fnmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fnmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0)" + by (unfold decode_fnmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fnmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fnmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0)" + by (unfold decode_fnmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fnmul_float_aarch64_instrs_float_arithmetic_mul_product[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fnmul_float_aarch64_instrs_float_arithmetic_mul_product Rd Rn op Rm b__0)" + by (unfold decode_fnmul_float_aarch64_instrs_float_arithmetic_mul_product_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_simd Rd Rn b__0 b__1)" + by (unfold decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_sisd Rd Rn b__0)" + by (unfold decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_simd Rd Rn b__0)" + by (unfold decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd Rd Rn)" + by (unfold decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_simd Rd Rn Rm b__0)" + by (unfold decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd Rd Rn Rm)" + by (unfold decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_simd Rd Rn Rm b__0 b__1)" + by (unfold decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_sisd Rd Rn Rm b__0)" + by (unfold decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx Rd Rn b__0)" + by (unfold decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16 Rd Rn)" + by (unfold decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_fp16_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_fp16_round d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) exact n rounding)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_round_frint[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_round_frint d (datasize :: 'datasize::len itself) exact n rounding)" + by (unfold execute_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frinta_float_aarch64_instrs_float_arithmetic_round_frint[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frinta_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frinta_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frinti_float_aarch64_instrs_float_arithmetic_round_frint[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frinti_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frinti_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintm_float_aarch64_instrs_float_arithmetic_round_frint[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintm_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintm_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintn_float_aarch64_instrs_float_arithmetic_round_frint[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintn_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintn_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintp_float_aarch64_instrs_float_arithmetic_round_frint[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintp_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintp_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintx_float_aarch64_instrs_float_arithmetic_round_frint[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintx_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintx_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frintz_float_aarch64_instrs_float_arithmetic_round_frint[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frintz_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintz_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_simd Rd Rn b__0 b__1)" + by (unfold decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_sisd Rd Rn b__0)" + by (unfold decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_simd Rd Rn b__0)" + by (unfold decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd Rd Rn)" + by (unfold decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_simd Rd Rn Rm b__0)" + by (unfold decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd Rd Rn Rm)" + by (unfold decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_simd Rd Rn Rm b__0 b__1)" + by (unfold decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_sisd Rd Rn Rm b__0)" + by (unfold decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt Rd Rn b__0 b__1)" + by (unfold decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16 Rd Rn b__0)" + by (unfold decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fsqrt_float_aarch64_instrs_float_arithmetic_unary[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fsqrt_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0)" + by (unfold decode_fsqrt_float_aarch64_instrs_float_arithmetic_unary_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd abs__arg d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd Rd Rn Rm U b__0)" + by (unfold decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_fsub_float_aarch64_instrs_float_arithmetic_add_sub[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_fsub_float_aarch64_instrs_float_arithmetic_add_sub Rd Rn op Rm b__0)" + by (unfold decode_fsub_float_aarch64_instrs_float_arithmetic_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_hint_aarch64_instrs_system_hints[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_hint_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_hint_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_system_exceptions_debug_halt[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_system_exceptions_debug_halt arg0)" + by (unfold execute_aarch64_instrs_system_exceptions_debug_halt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_hlt_aarch64_instrs_system_exceptions_debug_halt[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_hlt_aarch64_instrs_system_exceptions_debug_halt imm16)" + by (unfold decode_hlt_aarch64_instrs_system_exceptions_debug_halt_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_system_exceptions_runtime_hvc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_system_exceptions_runtime_hvc imm)" + by (unfold execute_aarch64_instrs_system_exceptions_runtime_hvc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc imm16)" + by (unfold decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_insert[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_insert d dst_index (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) n src_index)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_insert_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ins_advsimd_elt_aarch64_instrs_vector_transfer_vector_insert[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ins_advsimd_elt_aarch64_instrs_vector_transfer_vector_insert Rd Rn imm4 imm5)" + by (unfold decode_ins_advsimd_elt_aarch64_instrs_vector_transfer_vector_insert_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_transfer_integer_insert[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_integer_insert d datasize (esize :: 'esize::len itself) index__arg n)" + by (unfold execute_aarch64_instrs_vector_transfer_integer_insert_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ins_advsimd_gen_aarch64_instrs_vector_transfer_integer_insert[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ins_advsimd_gen_aarch64_instrs_vector_transfer_integer_insert Rd Rn b__0)" + by (unfold decode_ins_advsimd_gen_aarch64_instrs_vector_transfer_integer_insert_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_vector_multiple_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_vector_multiple_no_wb (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m memop n rpt selem t__arg wback)" + by (unfold execute_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_vector_single_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_vector_single_no_wb (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) index__arg m memop n replicate__arg selem t__arg wback)" + by (unfold execute_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_atomicops_ld (datasize :: 'datasize::len itself) ldacctype n op (regsize :: 'regsize::len itself) s__arg stacctype t__arg)" + by (unfold execute_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldadd_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldadd_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldadd_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldaddb_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldaddb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldaddb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldaddh_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldaddh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldaddh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_ordered_rcpc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_ordered_rcpc acctype (datasize :: 'datasize::len itself) n (regsize :: 'regsize::len itself) t__arg)" + by (unfold execute_aarch64_instrs_memory_ordered_rcpc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldapr_aarch64_instrs_memory_ordered_rcpc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldapr_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs__arg b__0)" + by (unfold decode_ldapr_aarch64_instrs_memory_ordered_rcpc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldaprb_aarch64_instrs_memory_ordered_rcpc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldaprb_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs__arg b__0)" + by (unfold decode_ldaprb_aarch64_instrs_memory_ordered_rcpc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldaprh_aarch64_instrs_memory_ordered_rcpc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldaprh_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs__arg b__0)" + by (unfold decode_ldaprh_aarch64_instrs_memory_ordered_rcpc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_ordered[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_ordered acctype (datasize :: 'datasize::len itself) memop n (regsize :: 'regsize::len itself) t__arg)" + by (unfold execute_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldar_aarch64_instrs_memory_ordered[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldar_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldar_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldarb_aarch64_instrs_memory_ordered[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldarb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldarb_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldarh_aarch64_instrs_memory_ordered[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldarh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldarh_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_exclusive_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_exclusive_pair acctype l__197 elsize memop n pair (regsize :: 'regsize::len itself) s__arg t__arg t2)" + by (unfold execute_aarch64_instrs_memory_exclusive_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldaxp_aarch64_instrs_memory_exclusive_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldaxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldaxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_exclusive_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_exclusive_single acctype l__532 elsize memop n pair (regsize :: 'regsize::len itself) s__arg t__arg t2)" + by (unfold execute_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldaxr_aarch64_instrs_memory_exclusive_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldaxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldaxr_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldaxrb_aarch64_instrs_memory_exclusive_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldaxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldaxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldaxrh_aarch64_instrs_memory_exclusive_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldaxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldaxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldclr_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldclr_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldclr_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldclrb_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldclrb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldclrb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldclrh_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldclrh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldclrh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldeor_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldeor_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldeor_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldeorb_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldeorb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldeorb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldeorh_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldeorh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldeorh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldlar_aarch64_instrs_memory_ordered[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldlar_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldlar_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldlarb_aarch64_instrs_memory_ordered[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldlarb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldlarb_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldlarh_aarch64_instrs_memory_ordered[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldlarh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldlarh_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_pair_simdfp_no_alloc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_pair_simdfp_no_alloc acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback)" + by (unfold execute_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_pair_general_no_alloc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_pair_general_no_alloc acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback)" + by (unfold execute_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_pair_simdfp_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_pair_simdfp_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback)" + by (unfold execute_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_pair_general_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_pair_general_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex is_signed t__arg t2 wback__arg)" + by (unfold execute_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldp_gen_aarch64_instrs_memory_pair_general_offset[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldp_gen_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldp_gen_aarch64_instrs_memory_pair_general_offset_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldpsw_aarch64_instrs_memory_pair_general_offset[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldpsw_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldpsw_aarch64_instrs_memory_pair_general_offset_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg wback)" + by (unfold execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg)" + by (unfold execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_literal_simdfp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_literal_simdfp offset l__44 t__arg)" + by (unfold execute_aarch64_instrs_memory_literal_simdfp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp Rt imm19 opc)" + by (unfold decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_literal_general[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_literal_general memop offset is_signed l__200 t__arg)" + by (unfold execute_aarch64_instrs_memory_literal_general_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldr_lit_gen_aarch64_instrs_memory_literal_general[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldr_lit_gen_aarch64_instrs_memory_literal_general Rt imm19 opc)" + by (unfold decode_ldr_lit_gen_aarch64_instrs_memory_literal_general_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_single_simdfp_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_simdfp_register acctype (datasize :: 'datasize::len itself) extend_type m memop n postindex shift t__arg wback)" + by (unfold execute_aarch64_instrs_memory_single_simdfp_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_single_general_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_general_register acctype (datasize :: 'datasize::len itself) extend_type m memop n postindex (regsize :: 'regsize::len itself) shift is_signed t__arg wback__arg)" + by (unfold execute_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrb_reg_aarch64_instrs_memory_single_general_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldrb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrh_reg_aarch64_instrs_memory_single_general_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldrh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrsb_reg_aarch64_instrs_memory_single_general_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrsb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldrsb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrsh_reg_aarch64_instrs_memory_single_general_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrsh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldrsh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrsw_lit_aarch64_instrs_memory_literal_general[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrsw_lit_aarch64_instrs_memory_literal_general Rt imm19 opc)" + by (unfold decode_ldrsw_lit_aarch64_instrs_memory_literal_general_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldrsw_reg_aarch64_instrs_memory_single_general_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldrsw_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldrsw_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldset_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldset_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldset_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldsetb_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldsetb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsetb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldseth_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldseth_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldseth_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldsmax_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldsmax_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsmax_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldsmin_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldsmin_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsmin_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldsminb_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldsminb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsminb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldsminh_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldsminh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsminh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg)" + by (unfold execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldumax_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldumax_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldumax_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldumaxb_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldumaxb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldumaxb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldumaxh_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldumaxh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldumaxh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldumin_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldumin_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldumin_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_lduminb_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_lduminb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_lduminb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_lduminh_aarch64_instrs_memory_atomicops_ld[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_lduminh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_lduminh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg wback)" + by (unfold execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg)" + by (unfold execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldxp_aarch64_instrs_memory_exclusive_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldxr_aarch64_instrs_memory_exclusive_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldxr_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldxrb_aarch64_instrs_memory_exclusive_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ldxrh_aarch64_instrs_memory_exclusive_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ldxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_lslv_aarch64_instrs_integer_shift_variable[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_lslv_aarch64_instrs_integer_shift_variable Rd Rn op2 Rm b__0)" + by (unfold decode_lslv_aarch64_instrs_integer_shift_variable_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_lsrv_aarch64_instrs_integer_shift_variable[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_lsrv_aarch64_instrs_integer_shift_variable Rd Rn op2 Rm b__0)" + by (unfold decode_lsrv_aarch64_instrs_integer_shift_variable_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub a d (datasize :: 'datasize::len itself) (destsize :: 'destsize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_madd_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_madd_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub Rd Rn Ra o0 Rm b__0)" + by (unfold decode_madd_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_mla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_mla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int Rd Rn b__0 o2 Rm M L b__1 b__2)" + by (unfold decode_mla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_mla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_mla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum Rd Rn Rm b__0 U b__1)" + by (unfold decode_mla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_mls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_mls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int Rd Rn b__0 o2 Rm M L b__1 b__2)" + by (unfold decode_mls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_mls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_mls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum Rd Rn Rm b__0 U b__1)" + by (unfold decode_mls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_movi_advsimd_aarch64_instrs_vector_logical[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_movi_advsimd_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_movi_advsimd_aarch64_instrs_vector_logical_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_ins_ext_insert_movewide[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_ins_ext_insert_movewide d (datasize :: 'datasize::len itself) imm opcode pos)" + by (unfold execute_aarch64_instrs_integer_ins_ext_insert_movewide_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_movk_aarch64_instrs_integer_ins_ext_insert_movewide[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_movk_aarch64_instrs_integer_ins_ext_insert_movewide Rd imm16 hw opc b__0)" + by (unfold decode_movk_aarch64_instrs_integer_ins_ext_insert_movewide_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_movn_aarch64_instrs_integer_ins_ext_insert_movewide[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_movn_aarch64_instrs_integer_ins_ext_insert_movewide Rd imm16 hw opc b__0)" + by (unfold decode_movn_aarch64_instrs_integer_ins_ext_insert_movewide_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_movz_aarch64_instrs_integer_ins_ext_insert_movewide[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_movz_aarch64_instrs_integer_ins_ext_insert_movewide Rd imm16 hw opc b__0)" + by (unfold decode_movz_aarch64_instrs_integer_ins_ext_insert_movewide_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_system_register_system[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_system_register_system read sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg)" + by (unfold execute_aarch64_instrs_system_register_system_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_mrs_aarch64_instrs_system_register_system[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_mrs_aarch64_instrs_system_register_system Rt op2 CRm CRn op1 o0 L)" + by (unfold decode_mrs_aarch64_instrs_system_register_system_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_system_register_cpsr[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_system_register_cpsr field operand)" + by (cases field; simp; no_reg_writes_toI) + +lemma no_reg_writes_to_decode_msr_imm_aarch64_instrs_system_register_cpsr[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_msr_imm_aarch64_instrs_system_register_cpsr op2 CRm op1)" + by (unfold decode_msr_imm_aarch64_instrs_system_register_cpsr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_msr_reg_aarch64_instrs_system_register_system[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_msr_reg_aarch64_instrs_system_register_system Rt op2 CRm CRn op1 o0 L)" + by (unfold decode_msr_reg_aarch64_instrs_system_register_system_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_msub_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_msub_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub Rd Rn Ra o0 Rm b__0)" + by (unfold decode_msub_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_int d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_mul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_mul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_int Rd Rn b__0 Rm M L b__1 b__2)" + by (unfold decode_mul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product d (datasize :: 'datasize::len itself) elements l__55 m n poly)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_mul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_mul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product Rd Rn Rm b__0 U b__1)" + by (unfold decode_mul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_mvni_advsimd_aarch64_instrs_vector_logical[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_mvni_advsimd_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_mvni_advsimd_aarch64_instrs_vector_logical_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd Rd Rn b__0 U b__1)" + by (unfold decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd Rd Rn b__0 U)" + by (unfold decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_nop_aarch64_instrs_system_hints[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_nop_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_nop_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_not[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_not d (datasize :: 'datasize::len itself) elements esize n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_not_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_not_advsimd_aarch64_instrs_vector_arithmetic_unary_not[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_not_advsimd_aarch64_instrs_vector_arithmetic_unary_not Rd Rn b__0)" + by (unfold decode_not_advsimd_aarch64_instrs_vector_arithmetic_unary_not_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_orn_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_orn_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0)" + by (unfold decode_orn_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_orn_log_shift_aarch64_instrs_integer_logical_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_orn_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_orn_log_shift_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_orr_advsimd_imm_aarch64_instrs_vector_logical[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_orr_advsimd_imm_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_orr_advsimd_imm_aarch64_instrs_vector_logical_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_orr_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_orr_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0)" + by (unfold decode_orr_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_orr_log_imm_aarch64_instrs_integer_logical_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_orr_log_imm_aarch64_instrs_integer_logical_immediate Rd Rn imms immr N opc b__0)" + by (unfold decode_orr_log_imm_aarch64_instrs_integer_logical_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_orr_log_shift_aarch64_instrs_integer_logical_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_orr_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_orr_log_shift_aarch64_instrs_integer_logical_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_pmul_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_pmul_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product Rd Rn Rm b__0 U b__1)" + by (unfold decode_pmul_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly d datasize elements l__379 m n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_pmull_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_pmull_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly Rd Rn Rm b__0 Q)" + by (unfold decode_pmull_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_single_general_immediate_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_general_immediate_unsigned acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg)" + by (unfold execute_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_prfm_lit_aarch64_instrs_memory_literal_general[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_prfm_lit_aarch64_instrs_memory_literal_general Rt imm19 opc)" + by (unfold decode_prfm_lit_aarch64_instrs_memory_literal_general_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_prfm_reg_aarch64_instrs_memory_single_general_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_prfm_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_prfm_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_psb_aarch64_instrs_system_hints[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_psb_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_psb_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_raddhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_raddhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_raddhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3_rax1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3_rax1 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3_rax1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_rax1_advsimd_aarch64_instrs_vector_crypto_sha3_rax1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_rax1_advsimd_aarch64_instrs_vector_crypto_sha3_rax1 Rd Rn Rm)" + by (unfold decode_rax1_advsimd_aarch64_instrs_vector_crypto_sha3_rax1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_arithmetic_rbit[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_arithmetic_rbit d (datasize :: 'datasize::len itself) n)" + by (unfold execute_aarch64_instrs_integer_arithmetic_rbit_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_rbit_int_aarch64_instrs_integer_arithmetic_rbit[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_rbit_int_aarch64_instrs_integer_arithmetic_rbit Rd Rn b__0)" + by (unfold decode_rbit_int_aarch64_instrs_integer_arithmetic_rbit_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ret_aarch64_instrs_branch_unconditional_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ret_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)" + by (unfold decode_ret_aarch64_instrs_branch_unconditional_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_reta_aarch64_instrs_branch_unconditional_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_reta_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)" + by (unfold decode_reta_aarch64_instrs_branch_unconditional_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_rev[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_rev containers d (datasize :: 'datasize::len itself) elements_per_container (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_rev_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_rev16_advsimd_aarch64_instrs_vector_arithmetic_unary_rev[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_rev16_advsimd_aarch64_instrs_vector_arithmetic_unary_rev Rd Rn o0 b__0 U b__1)" + by (unfold decode_rev16_advsimd_aarch64_instrs_vector_arithmetic_unary_rev_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_arithmetic_rev[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_arithmetic_rev container_size d (datasize :: 'datasize::len itself) n)" + by (unfold execute_aarch64_instrs_integer_arithmetic_rev_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_rev16_int_aarch64_instrs_integer_arithmetic_rev[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_rev16_int_aarch64_instrs_integer_arithmetic_rev Rd Rn opc b__0)" + by (unfold decode_rev16_int_aarch64_instrs_integer_arithmetic_rev_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_rev32_advsimd_aarch64_instrs_vector_arithmetic_unary_rev[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_rev32_advsimd_aarch64_instrs_vector_arithmetic_unary_rev Rd Rn o0 b__0 U b__1)" + by (unfold decode_rev32_advsimd_aarch64_instrs_vector_arithmetic_unary_rev_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_rev32_int_aarch64_instrs_integer_arithmetic_rev[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_rev32_int_aarch64_instrs_integer_arithmetic_rev Rd Rn opc b__0)" + by (unfold decode_rev32_int_aarch64_instrs_integer_arithmetic_rev_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_rev64_advsimd_aarch64_instrs_vector_arithmetic_unary_rev[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_rev64_advsimd_aarch64_instrs_vector_arithmetic_unary_rev Rd Rn o0 b__0 U b__1)" + by (unfold decode_rev64_advsimd_aarch64_instrs_vector_arithmetic_unary_rev_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_rev_aarch64_instrs_integer_arithmetic_rev[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_rev_aarch64_instrs_integer_arithmetic_rev Rd Rn opc b__0)" + by (unfold decode_rev_aarch64_instrs_integer_arithmetic_rev_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_rorv_aarch64_instrs_integer_shift_variable[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_rorv_aarch64_instrs_integer_shift_variable Rd Rn op2 Rm b__0)" + by (unfold decode_rorv_aarch64_instrs_integer_shift_variable_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_shift_right_narrow_logical[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_right_narrow_logical d datasize elements l__473 n part round__arg shift)" + by (unfold execute_aarch64_instrs_vector_shift_right_narrow_logical_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_rshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_rshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical Rd Rn op immb b__0 Q)" + by (unfold decode_rshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_rsubhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_rsubhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_rsubhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_diff[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_diff accumulate d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_saba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_saba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1)" + by (unfold decode_saba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_diff[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_diff accumulate d datasize elements l__469 m n part is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q)" + by (unfold decode_sabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1)" + by (unfold decode_sabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q)" + by (unfold decode_sabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_add_pairwise[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_add_pairwise acc d (datasize :: 'datasize::len itself) elements l__169 n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1)" + by (unfold decode_sadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long d datasize elements l__316 m n part sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_saddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_saddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_saddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_saddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_saddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1)" + by (unfold decode_saddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_reduce_add_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_add_long d (datasize :: 'datasize::len itself) elements l__159 n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_reduce_add_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_saddlv_advsimd_aarch64_instrs_vector_reduce_add_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_saddlv_advsimd_aarch64_instrs_vector_reduce_add_long Rd Rn b__0 U b__1)" + by (unfold decode_saddlv_advsimd_aarch64_instrs_vector_reduce_add_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide d datasize elements l__478 m n part sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_saddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_saddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_saddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_system_barriers_sb[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (execute_aarch64_instrs_system_barriers_sb arg0)" + by (unfold execute_aarch64_instrs_system_barriers_sb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sb_aarch64_instrs_system_barriers_sb[no_reg_writes_toI, simp]: + "no_reg_writes_to Rs (decode_sb_aarch64_instrs_system_barriers_sb Rt opc CRm CRn op1 op0 L)" + by (unfold decode_sb_aarch64_instrs_system_barriers_sb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sbc_aarch64_instrs_integer_arithmetic_add_sub_carry[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sbc_aarch64_instrs_integer_arithmetic_add_sub_carry Rd Rn Rm S op b__0)" + by (unfold decode_sbc_aarch64_instrs_integer_arithmetic_add_sub_carry_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sbcs_aarch64_instrs_integer_arithmetic_add_sub_carry[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sbcs_aarch64_instrs_integer_arithmetic_add_sub_carry Rd Rn Rm S op b__0)" + by (unfold decode_sbcs_aarch64_instrs_integer_arithmetic_add_sub_carry_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sbfm_aarch64_instrs_integer_bitfield[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sbfm_aarch64_instrs_integer_bitfield Rd Rn imms immr N opc b__0)" + by (unfold decode_sbfm_aarch64_instrs_integer_bitfield_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_shift_conv_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_conv_int_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) fracbits n rounding is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd Rd Rn immb b__0 U b__1)" + by (unfold decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd Rd Rn immb b__0 U)" + by (unfold decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd Rd Rn b__0 U b__1)" + by (unfold decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd Rd Rn b__0 U)" + by (unfold decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd Rd Rn U b__0)" + by (unfold decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd Rd Rn U)" + by (unfold decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_scvtf_float_fix_aarch64_instrs_float_convert_fix[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_scvtf_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1)" + by (unfold decode_scvtf_float_fix_aarch64_instrs_float_convert_fix_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_scvtf_float_int_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_scvtf_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_scvtf_float_int_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_arithmetic_div[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_arithmetic_div d (datasize :: 'datasize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_integer_arithmetic_div_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sdiv_aarch64_instrs_integer_arithmetic_div[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sdiv_aarch64_instrs_integer_arithmetic_div Rd Rn o1 Rm b__0)" + by (unfold decode_sdiv_aarch64_instrs_integer_arithmetic_div_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_dotp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_dotp d (datasize :: 'datasize::len itself) elements l__375 index__arg m n is_signed)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_dotp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sdot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sdot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp Rd Rn H Rm M L b__0 U b__1)" + by (unfold decode_sdot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp d (datasize :: 'datasize::len itself) elements l__165 m n is_signed)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sdot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sdot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp Rd Rn Rm b__0 U b__1)" + by (unfold decode_sdot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sev_aarch64_instrs_system_hints[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sev_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_sev_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sevl_aarch64_instrs_system_hints[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sevl_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_sevl_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha1c_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha1c_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose Rd Rn Rm)" + by (unfold decode_sha1c_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha2op_sha1_hash[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha2op_sha1_hash d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha2op_sha1_hash_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha1h_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_hash[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha1h_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_hash Rd Rn)" + by (unfold decode_sha1h_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_hash_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha1m_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha1m_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority Rd Rn Rm)" + by (unfold decode_sha1m_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha1p_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha1p_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity Rd Rn Rm)" + by (unfold decode_sha1p_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3op_sha1_sched0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3op_sha1_sched0 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha1_sched0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha1su0_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_sched0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha1su0_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_sched0 Rd Rn Rm)" + by (unfold decode_sha1su0_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_sched0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha2op_sha1_sched1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha2op_sha1_sched1 d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha2op_sha1_sched1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha1su1_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_sched1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha1su1_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_sched1 Rd Rn)" + by (unfold decode_sha1su1_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_sched1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3op_sha256_hash[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3op_sha256_hash d m n part1)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha256_hash_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha256h2_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha256h2_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash Rd Rn P Rm)" + by (unfold decode_sha256h2_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha256h_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha256h_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash Rd Rn P Rm)" + by (unfold decode_sha256h_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha2op_sha256_sched0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha2op_sha256_sched0 d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha2op_sha256_sched0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha256su0_advsimd_aarch64_instrs_vector_crypto_sha2op_sha256_sched0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha256su0_advsimd_aarch64_instrs_vector_crypto_sha2op_sha256_sched0 Rd Rn)" + by (unfold decode_sha256su0_advsimd_aarch64_instrs_vector_crypto_sha2op_sha256_sched0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3op_sha256_sched1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3op_sha256_sched1 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha256_sched1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha256su1_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_sched1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha256su1_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_sched1 Rd Rn Rm)" + by (unfold decode_sha256su1_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_sched1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha512_sha512h2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha512_sha512h2 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha512_sha512h2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha512h2_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha512h2_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h2 Rd Rn Rm)" + by (unfold decode_sha512h2_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha512_sha512h[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha512_sha512h d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha512_sha512h_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha512h_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha512h_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h Rd Rn Rm)" + by (unfold decode_sha512h_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha512_sha512su0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha512_sha512su0 d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha512_sha512su0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha512su0_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su0[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha512su0_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su0 Rd Rn)" + by (unfold decode_sha512su0_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su0_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha512_sha512su1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha512_sha512su1 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha512_sha512su1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sha512su1_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sha512su1_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su1 Rd Rn Rm)" + by (unfold decode_sha512su1_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_shadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_shadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating Rd Rn Rm b__0 U b__1)" + by (unfold decode_shadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_shift_left_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_left_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n shift)" + by (unfold execute_aarch64_instrs_vector_shift_left_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_shl_advsimd_aarch64_instrs_vector_shift_left_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_shl_advsimd_aarch64_instrs_vector_shift_left_simd Rd Rn immb b__0 b__1)" + by (unfold decode_shl_advsimd_aarch64_instrs_vector_shift_left_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_shl_advsimd_aarch64_instrs_vector_shift_left_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_shl_advsimd_aarch64_instrs_vector_shift_left_sisd Rd Rn immb immh)" + by (unfold decode_shl_advsimd_aarch64_instrs_vector_shift_left_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_shift[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_shift d datasize elements l__49 n part shift is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_shift_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_shll_advsimd_aarch64_instrs_vector_arithmetic_unary_shift[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_shll_advsimd_aarch64_instrs_vector_arithmetic_unary_shift Rd Rn b__0 Q)" + by (unfold decode_shll_advsimd_aarch64_instrs_vector_arithmetic_unary_shift_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_shrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_shrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical Rd Rn op immb b__0 Q)" + by (unfold decode_shrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_shsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_shsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int Rd Rn Rm b__0 U b__1)" + by (unfold decode_shsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_shift_left_insert_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_left_insert_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n shift)" + by (unfold execute_aarch64_instrs_vector_shift_left_insert_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_simd Rd Rn immb b__0 b__1)" + by (unfold decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_sisd Rd Rn immb immh)" + by (unfold decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3partw1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3partw1 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3partw1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sm3partw1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sm3partw1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw1 Rd Rn Rm)" + by (unfold decode_sm3partw1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3partw2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3partw2 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3partw2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sm3partw2_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw2[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sm3partw2_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw2 Rd Rn Rm)" + by (unfold decode_sm3partw2_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw2_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3ss1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3ss1 a d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3ss1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sm3ss1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3ss1[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sm3ss1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3ss1 Rd Rn Ra Rm)" + by (unfold decode_sm3ss1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3ss1_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3tt1a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3tt1a d i m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3tt1a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sm3tt1a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sm3tt1a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1a Rd Rn imm2 Rm)" + by (unfold decode_sm3tt1a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3tt1b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3tt1b d i m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3tt1b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sm3tt1b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sm3tt1b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1b Rd Rn imm2 Rm)" + by (unfold decode_sm3tt1b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3tt2a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3tt2a d i m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3tt2a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sm3tt2a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2a[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sm3tt2a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2a Rd Rn imm2 Rm)" + by (unfold decode_sm3tt2a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2a_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3tt2b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3tt2b d i m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3tt2b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sm3tt2b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2b[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sm3tt2b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2b Rd Rn imm2 Rm)" + by (unfold decode_sm3tt2b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2b_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm4_sm4enc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm4_sm4enc d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm4_sm4enc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sm4e_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sm4e_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enc Rd Rn)" + by (unfold decode_sm4e_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm4_sm4enckey[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm4_sm4enckey d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm4_sm4enckey_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sm4ekey_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enckey[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sm4ekey_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enckey Rd Rn Rm)" + by (unfold decode_sm4ekey_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enckey_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_arithmetic_mul_widening_32_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_arithmetic_mul_widening_32_64 a d datasize destsize m n sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64 Rd Rn Ra o0 Rm U)" + by (unfold decode_smaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m minimum n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_smax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair d l__193 elements (esize :: 'esize::len itself) m minimum n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_smaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_reduce_int_max[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_int_max d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) min__arg n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_reduce_int_max_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smaxv_advsimd_aarch64_instrs_vector_reduce_int_max[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smaxv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1)" + by (unfold decode_smaxv_advsimd_aarch64_instrs_vector_reduce_int_max_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_system_exceptions_runtime_smc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_system_exceptions_runtime_smc imm)" + by (unfold execute_aarch64_instrs_system_exceptions_runtime_smc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smc_aarch64_instrs_system_exceptions_runtime_smc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smc_aarch64_instrs_system_exceptions_runtime_smc imm16)" + by (unfold decode_smc_aarch64_instrs_system_exceptions_runtime_smc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_smin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_sminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sminv_advsimd_aarch64_instrs_vector_reduce_int_max[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sminv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1)" + by (unfold decode_sminv_advsimd_aarch64_instrs_vector_reduce_int_max_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long d datasize elements l__185 (idxdsize :: 'idxdsize::len itself) index__arg m n part sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q)" + by (unfold decode_smlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum d datasize elements l__537 m n part sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_smlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q)" + by (unfold decode_smlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_smlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_transfer_integer_move_signed[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_integer_move_signed d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg n)" + by (unfold execute_aarch64_instrs_vector_transfer_integer_move_signed_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smov_advsimd_aarch64_instrs_vector_transfer_integer_move_signed[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smov_advsimd_aarch64_instrs_vector_transfer_integer_move_signed Rd Rn b__0 b__1)" + by (unfold decode_smov_advsimd_aarch64_instrs_vector_transfer_integer_move_signed_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64 Rd Rn Ra o0 Rm U)" + by (unfold decode_smsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi d datasize m n is_unsigned)" + by (unfold execute_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi Rd Rn Ra Rm U)" + by (unfold decode_smulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_long d datasize elements l__173 (idxdsize :: 'idxdsize::len itself) index__arg m n part is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long Rd Rn b__0 Rm M L b__1 U Q)" + by (unfold decode_smull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product d datasize elements l__189 m n part is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_smull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_smull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product Rd Rn Rm b__0 U Q)" + by (unfold decode_smull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n neg)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd Rd Rn b__0 U b__1)" + by (unfold decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd Rd Rn b__0 U)" + by (unfold decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd d l__403 elements l__404 (idxdsize :: 'idxdsize::len itself) index__arg m n part sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd Rd Rn b__0 o2 Rm M L b__1 Q)" + by (unfold decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd d l__437 elements l__438 m n part sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd Rd Rn o1 Rm b__0 Q)" + by (unfold decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd Rd Rn o1 Rm b__0)" + by (unfold decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd Rd Rn b__0 o2 Rm M L b__1 Q)" + by (unfold decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd Rd Rn o1 Rm b__0 Q)" + by (unfold decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd Rd Rn o1 Rm b__0)" + by (unfold decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n round__arg)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd Rd Rn b__0 op Rm M L b__1 b__2)" + by (unfold decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd Rd Rn b__0 op Rm M L b__1)" + by (unfold decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n rounding)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd d l__123 elements l__124 (idxdsize :: 'idxdsize::len itself) index__arg m n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_simd Rd Rn b__0 Rm M L b__1 Q)" + by (unfold decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd Rd Rn b__0 Rm M L b__1)" + by (unfold decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd d l__59 elements l__60 m n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_simd Rd Rn Rm b__0 Q)" + by (unfold decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd Rd Rn Rm b__0)" + by (unfold decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd Rd Rn b__0 U b__1)" + by (unfold decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd Rd Rn b__0 U)" + by (unfold decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n rounding sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd Rd Rn b__0 S Rm M L b__1 b__2)" + by (unfold decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd Rd Rn b__0 S Rm M L b__1)" + by (unfold decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n rounding sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd Rd Rn S Rm b__0 b__1)" + by (unfold decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd Rd Rn S Rm b__0)" + by (unfold decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd Rd Rn b__0 S Rm M L b__1 b__2)" + by (unfold decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd Rd Rn b__0 S Rm M L b__1)" + by (unfold decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd Rd Rn S Rm b__0 b__1)" + by (unfold decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd Rd Rn S Rm b__0)" + by (unfold decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd Rd Rn b__0 op Rm M L b__1 b__2)" + by (unfold decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd Rd Rn b__0 op Rm M L b__1)" + by (unfold decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n rounding saturating is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_right_narrow_uniform_sisd d l__325 elements l__326 n part round__arg shift is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q)" + by (unfold decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U)" + by (unfold decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd d l__482 elements l__483 n part round__arg shift)" + by (unfold execute_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd Rd Rn op immb b__0 Q)" + by (unfold decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd Rd Rn op immb b__0)" + by (unfold decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_shift_left_sat_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_left_sat_sisd d (datasize :: 'datasize::len itself) dst_unsigned elements (esize :: 'esize::len itself) n shift src_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_left_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd Rd Rn op immb b__0 U b__1)" + by (unfold decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd Rd Rn op immb b__0 U)" + by (unfold decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_simd Rd Rn op immb b__0 U b__1)" + by (unfold decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_sisd Rd Rn op immb b__0 U)" + by (unfold decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q)" + by (unfold decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U)" + by (unfold decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd Rd Rn op immb b__0 Q)" + by (unfold decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd Rd Rn op immb b__0)" + by (unfold decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd d l__91 elements l__92 n part is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd Rd Rn b__0 U Q)" + by (unfold decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd Rd Rn b__0 U)" + by (unfold decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd d l__4 elements l__5 n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_simd Rd Rn b__0 Q)" + by (unfold decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd Rd Rn b__0)" + by (unfold decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_srhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_srhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding Rd Rn Rm b__0 U b__1)" + by (unfold decode_srhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_shift_right_insert_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_right_insert_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n shift)" + by (unfold execute_aarch64_instrs_vector_shift_right_insert_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_simd Rd Rn immb b__0 b__1)" + by (unfold decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_sisd Rd Rn immb immh)" + by (unfold decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_shift_right_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_right_sisd accumulate d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n round__arg shift is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_srshr_advsimd_aarch64_instrs_vector_shift_right_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_srshr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_srshr_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_srshr_advsimd_aarch64_instrs_vector_shift_right_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_srshr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_srshr_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_srsra_advsimd_aarch64_instrs_vector_shift_right_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_srsra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_srsra_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_srsra_advsimd_aarch64_instrs_vector_shift_right_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_srsra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_srsra_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_shift_left_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_left_long d datasize elements l__320 n part shift is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_left_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sshll_advsimd_aarch64_instrs_vector_shift_left_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sshll_advsimd_aarch64_instrs_vector_shift_left_long Rd Rn immb b__0 U Q)" + by (unfold decode_sshll_advsimd_aarch64_instrs_vector_shift_left_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sshr_advsimd_aarch64_instrs_vector_shift_right_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sshr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_sshr_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sshr_advsimd_aarch64_instrs_vector_shift_right_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sshr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_sshr_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ssra_advsimd_aarch64_instrs_vector_shift_right_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ssra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_ssra_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ssra_advsimd_aarch64_instrs_vector_shift_right_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ssra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_ssra_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ssubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ssubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_ssubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ssubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ssubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_ssubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_atomicops_st (datasize :: 'datasize::len itself) ldacctype n op s__arg stacctype)" + by (unfold execute_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stadd_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stadd_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stadd_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_staddb_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_staddb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_staddb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_staddh_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_staddh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_staddh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stclr_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stclr_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stclr_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stclrb_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stclrb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stclrb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stclrh_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stclrh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stclrh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_steor_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_steor_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_steor_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_steorb_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_steorb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_steorb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_steorh_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_steorh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_steorh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stllr_aarch64_instrs_memory_ordered[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stllr_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stllr_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stllrb_aarch64_instrs_memory_ordered[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stllrb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stllrb_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stllrh_aarch64_instrs_memory_ordered[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stllrh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stllrh_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stlr_aarch64_instrs_memory_ordered[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stlr_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlr_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stlrb_aarch64_instrs_memory_ordered[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stlrb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlrb_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stlrh_aarch64_instrs_memory_ordered[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stlrh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlrh_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stlxp_aarch64_instrs_memory_exclusive_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stlxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stlxr_aarch64_instrs_memory_exclusive_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stlxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlxr_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stlxrb_aarch64_instrs_memory_exclusive_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stlxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stlxrh_aarch64_instrs_memory_exclusive_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stlxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stp_gen_aarch64_instrs_memory_pair_general_offset[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stp_gen_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stp_gen_aarch64_instrs_memory_pair_general_offset_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_str_reg_gen_aarch64_instrs_memory_single_general_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_str_reg_gen_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_str_reg_gen_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_strb_reg_aarch64_instrs_memory_single_general_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_strb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_strb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_strh_reg_aarch64_instrs_memory_single_general_register[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_strh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_strh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stset_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stset_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stset_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stsetb_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stsetb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsetb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stseth_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stseth_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stseth_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stsmax_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stsmax_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsmax_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stsmaxb_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stsmaxb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsmaxb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stsmaxh_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stsmaxh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsmaxh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stsmin_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stsmin_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsmin_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stsminb_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stsminb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsminb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stsminh_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stsminh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsminh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stumax_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stumax_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stumax_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stumaxb_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stumaxb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stumaxb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stumaxh_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stumaxh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stumaxh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stumin_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stumin_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stumin_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stuminb_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stuminb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stuminb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stuminh_aarch64_instrs_memory_atomicops_st[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stuminh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stuminh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stxp_aarch64_instrs_memory_exclusive_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stxr_aarch64_instrs_memory_exclusive_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stxr_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stxrb_aarch64_instrs_memory_exclusive_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_stxrh_aarch64_instrs_memory_exclusive_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_stxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sub_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sub_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg Rd Rn imm3 option_name Rm S op b__0)" + by (unfold decode_sub_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sub_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sub_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate Rd Rn imm12 sh S op b__0)" + by (unfold decode_sub_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sub_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sub_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg Rd Rn imm6 Rm shift S op b__0)" + by (unfold decode_sub_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_subhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_subhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_subhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_subs_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_subs_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg Rd Rn imm3 option_name Rm S op b__0)" + by (unfold decode_subs_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_subs_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_subs_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate Rd Rn imm12 sh S op b__0)" + by (unfold decode_subs_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_subs_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_subs_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg Rd Rn imm6 Rm shift S op b__0)" + by (unfold decode_subs_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd Rd Rn b__0 U b__1)" + by (unfold decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd Rd Rn b__0 U)" + by (unfold decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_system_exceptions_runtime_svc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_system_exceptions_runtime_svc imm)" + by (unfold execute_aarch64_instrs_system_exceptions_runtime_svc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_svc_aarch64_instrs_system_exceptions_runtime_svc[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_svc_aarch64_instrs_system_exceptions_runtime_svc imm16)" + by (unfold decode_svc_aarch64_instrs_system_exceptions_runtime_svc_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_memory_atomicops_swp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_memory_atomicops_swp (datasize :: 'datasize::len itself) ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg)" + by (unfold execute_aarch64_instrs_memory_atomicops_swp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_swp_aarch64_instrs_memory_atomicops_swp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_swp_aarch64_instrs_memory_atomicops_swp Rt Rn Rs__arg R A b__0)" + by (unfold decode_swp_aarch64_instrs_memory_atomicops_swp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_swpb_aarch64_instrs_memory_atomicops_swp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_swpb_aarch64_instrs_memory_atomicops_swp Rt Rn Rs__arg R A b__0)" + by (unfold decode_swpb_aarch64_instrs_memory_atomicops_swp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_swph_aarch64_instrs_memory_atomicops_swp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_swph_aarch64_instrs_memory_atomicops_swp Rt Rn Rs__arg R A b__0)" + by (unfold decode_swph_aarch64_instrs_memory_atomicops_swp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_system_sysops[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_system_sysops has_result sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg)" + by (unfold execute_aarch64_instrs_system_sysops_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sys_aarch64_instrs_system_sysops[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sys_aarch64_instrs_system_sysops Rt op2 CRm CRn op1 L)" + by (unfold decode_sys_aarch64_instrs_system_sysops_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_sysl_aarch64_instrs_system_sysops[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_sysl_aarch64_instrs_system_sysops Rt op2 CRm CRn op1 L)" + by (unfold decode_sysl_aarch64_instrs_system_sysops_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_table[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_table d (datasize :: 'datasize::len itself) elements is_tbl m n__arg l__181)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_table_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_tbl_advsimd_aarch64_instrs_vector_transfer_vector_table[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_tbl_advsimd_aarch64_instrs_vector_transfer_vector_table Rd Rn op len Rm b__0)" + by (unfold decode_tbl_advsimd_aarch64_instrs_vector_transfer_vector_table_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_branch_conditional_test[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_branch_conditional_test bit_pos bit_val (datasize :: 'datasize::len itself) offset t__arg)" + by (unfold execute_aarch64_instrs_branch_conditional_test_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_tbnz_aarch64_instrs_branch_conditional_test[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_tbnz_aarch64_instrs_branch_conditional_test Rt imm14 b40 op b__0)" + by (unfold decode_tbnz_aarch64_instrs_branch_conditional_test_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_tbx_advsimd_aarch64_instrs_vector_transfer_vector_table[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_tbx_advsimd_aarch64_instrs_vector_transfer_vector_table Rd Rn op len Rm b__0)" + by (unfold decode_tbx_advsimd_aarch64_instrs_vector_transfer_vector_table_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_tbz_aarch64_instrs_branch_conditional_test[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_tbz_aarch64_instrs_branch_conditional_test Rt imm14 b40 op b__0)" + by (unfold decode_tbz_aarch64_instrs_branch_conditional_test_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_permute_transpose[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_permute_transpose d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) m n pairs part)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_permute_transpose_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_trn1_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_trn1_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose Rd Rn op Rm b__0 b__1)" + by (unfold decode_trn1_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_trn2_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_trn2_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose Rd Rn op Rm b__0 b__1)" + by (unfold decode_trn2_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uaba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uaba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1)" + by (unfold decode_uaba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q)" + by (unfold decode_uabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1)" + by (unfold decode_uabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q)" + by (unfold decode_uabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1)" + by (unfold decode_uadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uaddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uaddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_uaddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uaddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uaddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1)" + by (unfold decode_uaddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uaddlv_advsimd_aarch64_instrs_vector_reduce_add_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uaddlv_advsimd_aarch64_instrs_vector_reduce_add_long Rd Rn b__0 U b__1)" + by (unfold decode_uaddlv_advsimd_aarch64_instrs_vector_reduce_add_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uaddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uaddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_uaddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ubfm_aarch64_instrs_integer_bitfield[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ubfm_aarch64_instrs_integer_bitfield Rd Rn imms immr N opc b__0)" + by (unfold decode_ubfm_aarch64_instrs_integer_bitfield_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd Rd Rn immb b__0 U b__1)" + by (unfold decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd Rd Rn immb b__0 U)" + by (unfold decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd Rd Rn b__0 U b__1)" + by (unfold decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd Rd Rn b__0 U)" + by (unfold decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd Rd Rn U b__0)" + by (unfold decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd Rd Rn U)" + by (unfold decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ucvtf_float_fix_aarch64_instrs_float_convert_fix[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ucvtf_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1)" + by (unfold decode_ucvtf_float_fix_aarch64_instrs_float_convert_fix_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ucvtf_float_int_aarch64_instrs_float_convert_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ucvtf_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_ucvtf_float_int_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_udiv_aarch64_instrs_integer_arithmetic_div[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_udiv_aarch64_instrs_integer_arithmetic_div Rd Rn o1 Rm b__0)" + by (unfold decode_udiv_aarch64_instrs_integer_arithmetic_div_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_udot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_udot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp Rd Rn H Rm M L b__0 U b__1)" + by (unfold decode_udot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_udot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_udot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp Rd Rn Rm b__0 U b__1)" + by (unfold decode_udot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating Rd Rn Rm b__0 U b__1)" + by (unfold decode_uhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uhsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uhsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int Rd Rn Rm b__0 U b__1)" + by (unfold decode_uhsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64 Rd Rn Ra o0 Rm U)" + by (unfold decode_umaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_umax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_umaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umaxv_advsimd_aarch64_instrs_vector_reduce_int_max[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umaxv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1)" + by (unfold decode_umaxv_advsimd_aarch64_instrs_vector_reduce_int_max_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_umin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_uminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uminv_advsimd_aarch64_instrs_vector_reduce_int_max[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uminv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1)" + by (unfold decode_uminv_advsimd_aarch64_instrs_vector_reduce_int_max_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q)" + by (unfold decode_umlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_umlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q)" + by (unfold decode_umlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_umlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_transfer_integer_move_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_integer_move_unsigned d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg n)" + by (unfold execute_aarch64_instrs_vector_transfer_integer_move_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umov_advsimd_aarch64_instrs_vector_transfer_integer_move_unsigned[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umov_advsimd_aarch64_instrs_vector_transfer_integer_move_unsigned Rd Rn b__0 b__1)" + by (unfold decode_umov_advsimd_aarch64_instrs_vector_transfer_integer_move_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64 Rd Rn Ra o0 Rm U)" + by (unfold decode_umsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi Rd Rn Ra Rm U)" + by (unfold decode_umulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long Rd Rn b__0 Rm M L b__1 U Q)" + by (unfold decode_umull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_umull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_umull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product Rd Rn Rm b__0 U Q)" + by (unfold decode_umull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd Rd Rn Rm b__0 U)" + by (unfold decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q)" + by (unfold decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U)" + by (unfold decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd Rd Rn op immb b__0 U b__1)" + by (unfold decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd Rd Rn op immb b__0 U)" + by (unfold decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q)" + by (unfold decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U)" + by (unfold decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd Rd Rn Rm b__0 U)" + by (unfold decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd Rd Rn b__0 U Q)" + by (unfold decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd Rd Rn b__0 U)" + by (unfold decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_special_recip_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_special_recip_int d (datasize :: 'datasize::len itself) elements n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_recip_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_urecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_urecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_int Rd Rn sz b__0)" + by (unfold decode_urecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_urhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_urhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding Rd Rn Rm b__0 U b__1)" + by (unfold decode_urhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_urshr_advsimd_aarch64_instrs_vector_shift_right_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_urshr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_urshr_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_urshr_advsimd_aarch64_instrs_vector_shift_right_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_urshr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_urshr_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int d (datasize :: 'datasize::len itself) elements n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ursqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ursqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int Rd Rn sz b__0)" + by (unfold decode_ursqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ursra_advsimd_aarch64_instrs_vector_shift_right_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ursra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_ursra_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ursra_advsimd_aarch64_instrs_vector_shift_right_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ursra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_ursra_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ushll_advsimd_aarch64_instrs_vector_shift_left_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ushll_advsimd_aarch64_instrs_vector_shift_left_long Rd Rn immb b__0 U Q)" + by (unfold decode_ushll_advsimd_aarch64_instrs_vector_shift_left_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ushr_advsimd_aarch64_instrs_vector_shift_right_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ushr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_ushr_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_ushr_advsimd_aarch64_instrs_vector_shift_right_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_ushr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_ushr_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd Rd Rn b__0 U b__1)" + by (unfold decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd Rd Rn b__0 U)" + by (unfold decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_usra_advsimd_aarch64_instrs_vector_shift_right_simd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_usra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_usra_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_usra_advsimd_aarch64_instrs_vector_shift_right_sisd[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_usra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_usra_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_usubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_usubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_usubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_usubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_usubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_usubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_permute_unzip[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_permute_unzip d l__195 elements (esize :: 'esize::len itself) m n part)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_permute_unzip_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uzp1_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uzp1_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip Rd Rn op Rm b__0 b__1)" + by (unfold decode_uzp1_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_uzp2_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_uzp2_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip Rd Rn op Rm b__0 b__1)" + by (unfold decode_uzp2_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_wfe_aarch64_instrs_system_hints[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_wfe_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_wfe_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_wfi_aarch64_instrs_system_hints[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_wfi_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_wfi_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3_xar[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3_xar d imm6 m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3_xar_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_xar_advsimd_aarch64_instrs_vector_crypto_sha3_xar[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_xar_advsimd_aarch64_instrs_vector_crypto_sha3_xar Rd Rn imm6 Rm)" + by (unfold decode_xar_advsimd_aarch64_instrs_vector_crypto_sha3_xar_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_extract_nosat[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_extract_nosat d datasize elements l__0 n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_extract_nosat_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_xtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_nosat[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_xtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_nosat Rd Rn b__0 Q)" + by (unfold decode_xtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_nosat_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_yield_aarch64_instrs_system_hints[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_yield_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_yield_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_permute_zip[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_permute_zip d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) m n pairs part)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_permute_zip_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_zip1_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_zip1_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip Rd Rn op Rm b__0 b__1)" + by (unfold decode_zip1_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip_def bind_assoc, no_reg_writes_toI) + +lemma no_reg_writes_to_decode_zip2_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip[no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''_R29'', ''__ThisInstrAbstract''} \ no_reg_writes_to Rs (decode_zip2_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip Rd Rn op Rm b__0 b__1)" + by (unfold decode_zip2_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_TakeException[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_TakeException target_el exception preferred_exception_return vect_offset__arg)" + by (auto simp: runs_no_reg_writes_to_def) + +lemma runs_no_reg_writes_to_AArch64_SystemAccessTrap[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_SystemAccessTrap target_el ec)" + by (unfold AArch64_SystemAccessTrap_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ACTLR_EL1_SysRegRead_56bd4d0367c16236[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ACTLR_EL1_SysRegRead_56bd4d0367c16236 el op0 op1 CRn op2 CRm)" + by (unfold ACTLR_EL1_SysRegRead_56bd4d0367c16236_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ACTLR_EL2_SysRegRead_ff23cef1b670b9c7[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ACTLR_EL2_SysRegRead_ff23cef1b670b9c7 el op0 op1 CRn op2 CRm)" + by (unfold ACTLR_EL2_SysRegRead_ff23cef1b670b9c7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ACTLR_EL3_SysRegRead_397e6c0342e2936b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ACTLR_EL3_SysRegRead_397e6c0342e2936b el op0 op1 CRn op2 CRm)" + by (unfold ACTLR_EL3_SysRegRead_397e6c0342e2936b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR0_EL12_SysRegRead_2488de32a3f38621[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AFSR0_EL12_SysRegRead_2488de32a3f38621 el op0 op1 CRn op2 CRm)" + by (unfold AFSR0_EL12_SysRegRead_2488de32a3f38621_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR0_EL1_SysRegRead_80a4a0472e0b9142[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AFSR0_EL1_SysRegRead_80a4a0472e0b9142 el op0 op1 CRn op2 CRm)" + by (unfold AFSR0_EL1_SysRegRead_80a4a0472e0b9142_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR0_EL2_SysRegRead_07613e9c4b98061a[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AFSR0_EL2_SysRegRead_07613e9c4b98061a el op0 op1 CRn op2 CRm)" + by (unfold AFSR0_EL2_SysRegRead_07613e9c4b98061a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR0_EL3_SysRegRead_d2e69d7912ca200c[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AFSR0_EL3_SysRegRead_d2e69d7912ca200c el op0 op1 CRn op2 CRm)" + by (unfold AFSR0_EL3_SysRegRead_d2e69d7912ca200c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR1_EL12_SysRegRead_39bb62021df07ecc[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AFSR1_EL12_SysRegRead_39bb62021df07ecc el op0 op1 CRn op2 CRm)" + by (unfold AFSR1_EL12_SysRegRead_39bb62021df07ecc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR1_EL1_SysRegRead_495927b72173c55f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AFSR1_EL1_SysRegRead_495927b72173c55f el op0 op1 CRn op2 CRm)" + by (unfold AFSR1_EL1_SysRegRead_495927b72173c55f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR1_EL2_SysRegRead_f7cb9a59387f268f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AFSR1_EL2_SysRegRead_f7cb9a59387f268f el op0 op1 CRn op2 CRm)" + by (unfold AFSR1_EL2_SysRegRead_f7cb9a59387f268f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR1_EL3_SysRegRead_a2ad736ad599f2b2[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AFSR1_EL3_SysRegRead_a2ad736ad599f2b2 el op0 op1 CRn op2 CRm)" + by (unfold AFSR1_EL3_SysRegRead_a2ad736ad599f2b2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AIDR_EL1_SysRegRead_74ea31b1dc6f5c6f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AIDR_EL1_SysRegRead_74ea31b1dc6f5c6f el op0 op1 CRn op2 CRm)" + by (unfold AIDR_EL1_SysRegRead_74ea31b1dc6f5c6f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AMAIR_EL12_SysRegRead_87964a33cc1ad0ef[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AMAIR_EL12_SysRegRead_87964a33cc1ad0ef el op0 op1 CRn op2 CRm)" + by (unfold AMAIR_EL12_SysRegRead_87964a33cc1ad0ef_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AMAIR_EL1_SysRegRead_82d01d3808e04ca3[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AMAIR_EL1_SysRegRead_82d01d3808e04ca3 el op0 op1 CRn op2 CRm)" + by (unfold AMAIR_EL1_SysRegRead_82d01d3808e04ca3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AMAIR_EL2_SysRegRead_3c316bb11b239640[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AMAIR_EL2_SysRegRead_3c316bb11b239640 el op0 op1 CRn op2 CRm)" + by (unfold AMAIR_EL2_SysRegRead_3c316bb11b239640_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AMAIR_EL3_SysRegRead_b1547f511477c529[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AMAIR_EL3_SysRegRead_b1547f511477c529 el op0 op1 CRn op2 CRm)" + by (unfold AMAIR_EL3_SysRegRead_b1547f511477c529_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CCSIDR_EL1_SysRegRead_210f94b423761d0b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CCSIDR_EL1_SysRegRead_210f94b423761d0b el op0 op1 CRn op2 CRm)" + by (unfold CCSIDR_EL1_SysRegRead_210f94b423761d0b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CCTLR_EL0_SysRegRead_3baa7e22d96a4ce4[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CCTLR_EL0_SysRegRead_3baa7e22d96a4ce4 el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL0_SysRegRead_3baa7e22d96a4ce4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CCTLR_EL12_SysRegRead_e8b17aabd47dc7a1[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CCTLR_EL12_SysRegRead_e8b17aabd47dc7a1 el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL12_SysRegRead_e8b17aabd47dc7a1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CCTLR_EL1_SysRegRead_de402a061eecb9b9[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CCTLR_EL1_SysRegRead_de402a061eecb9b9 el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL1_SysRegRead_de402a061eecb9b9_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CCTLR_EL2_SysRegRead_fca4364f27bb9f9b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CCTLR_EL2_SysRegRead_fca4364f27bb9f9b el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL2_SysRegRead_fca4364f27bb9f9b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CCTLR_EL3_SysRegRead_9121a22ebc361586[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CCTLR_EL3_SysRegRead_9121a22ebc361586 el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL3_SysRegRead_9121a22ebc361586_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CHCR_EL2_SysRegRead_7d3c39a46321f1a2[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CHCR_EL2_SysRegRead_7d3c39a46321f1a2 el op0 op1 CRn op2 CRm)" + by (unfold CHCR_EL2_SysRegRead_7d3c39a46321f1a2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CLIDR_EL1_SysRegRead_b403ddc99e97c3a8[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CLIDR_EL1_SysRegRead_b403ddc99e97c3a8 el op0 op1 CRn op2 CRm)" + by (unfold CLIDR_EL1_SysRegRead_b403ddc99e97c3a8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTFRQ_EL0_SysRegRead_891ca00adf0c3783[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTFRQ_EL0_SysRegRead_891ca00adf0c3783 el op0 op1 CRn op2 CRm)" + by (unfold CNTFRQ_EL0_SysRegRead_891ca00adf0c3783_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHCTL_EL2_SysRegRead_5f510d633361c720[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTHCTL_EL2_SysRegRead_5f510d633361c720 el op0 op1 CRn op2 CRm)" + by (unfold CNTHCTL_EL2_SysRegRead_5f510d633361c720_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHP_CTL_EL2_SysRegRead_7103e47839f2c66b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTHP_CTL_EL2_SysRegRead_7103e47839f2c66b el op0 op1 CRn op2 CRm)" + by (unfold CNTHP_CTL_EL2_SysRegRead_7103e47839f2c66b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHP_CVAL_EL2_SysRegRead_e25a0257128c640b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTHP_CVAL_EL2_SysRegRead_e25a0257128c640b el op0 op1 CRn op2 CRm)" + by (unfold CNTHP_CVAL_EL2_SysRegRead_e25a0257128c640b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHP_TVAL_EL2_SysRegRead_d110a1f1616c9f8f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTHP_TVAL_EL2_SysRegRead_d110a1f1616c9f8f el op0 op1 CRn op2 CRm)" + by (unfold CNTHP_TVAL_EL2_SysRegRead_d110a1f1616c9f8f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHV_CTL_EL2_SysRegRead_bc429f3d6b52b800[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTHV_CTL_EL2_SysRegRead_bc429f3d6b52b800 el op0 op1 CRn op2 CRm)" + by (unfold CNTHV_CTL_EL2_SysRegRead_bc429f3d6b52b800_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHV_CVAL_EL2_SysRegRead_2c78392b89702ca9[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTHV_CVAL_EL2_SysRegRead_2c78392b89702ca9 el op0 op1 CRn op2 CRm)" + by (unfold CNTHV_CVAL_EL2_SysRegRead_2c78392b89702ca9_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHV_TVAL_EL2_SysRegRead_2464c0e91db55a22[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTHV_TVAL_EL2_SysRegRead_2464c0e91db55a22 el op0 op1 CRn op2 CRm)" + by (unfold CNTHV_TVAL_EL2_SysRegRead_2464c0e91db55a22_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTKCTL_EL12_SysRegRead_c23def3111264258[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTKCTL_EL12_SysRegRead_c23def3111264258 el op0 op1 CRn op2 CRm)" + by (unfold CNTKCTL_EL12_SysRegRead_c23def3111264258_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTKCTL_EL1_SysRegRead_6a6cc900bc3c37df[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTKCTL_EL1_SysRegRead_6a6cc900bc3c37df el op0 op1 CRn op2 CRm)" + by (unfold CNTKCTL_EL1_SysRegRead_6a6cc900bc3c37df_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTPCT_EL0_SysRegRead_579be4c9ef4e6824[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTPCT_EL0_SysRegRead_579be4c9ef4e6824 el op0 op1 CRn op2 CRm)" + by (unfold CNTPCT_EL0_SysRegRead_579be4c9ef4e6824_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTPS_CTL_EL1_SysRegRead_e3bc6e5891147388[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTPS_CTL_EL1_SysRegRead_e3bc6e5891147388 el op0 op1 CRn op2 CRm)" + by (unfold CNTPS_CTL_EL1_SysRegRead_e3bc6e5891147388_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTPS_CVAL_EL1_SysRegRead_3e364bd573c45cae[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTPS_CVAL_EL1_SysRegRead_3e364bd573c45cae el op0 op1 CRn op2 CRm)" + by (unfold CNTPS_CVAL_EL1_SysRegRead_3e364bd573c45cae_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTPS_TVAL_EL1_SysRegRead_0784a7de0899eff0[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTPS_TVAL_EL1_SysRegRead_0784a7de0899eff0 el op0 op1 CRn op2 CRm)" + by (unfold CNTPS_TVAL_EL1_SysRegRead_0784a7de0899eff0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTP_CTL_EL02_SysRegRead_9d9930274ff7fc36[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTP_CTL_EL02_SysRegRead_9d9930274ff7fc36 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_CTL_EL02_SysRegRead_9d9930274ff7fc36_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTP_CTL_EL0_SysRegRead_47237e002d686ac6[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTP_CTL_EL0_SysRegRead_47237e002d686ac6 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_CTL_EL0_SysRegRead_47237e002d686ac6_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTP_CVAL_EL02_SysRegRead_8377305437cbebb4[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTP_CVAL_EL02_SysRegRead_8377305437cbebb4 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_CVAL_EL02_SysRegRead_8377305437cbebb4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTP_CVAL_EL0_SysRegRead_4db28ae745612584[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTP_CVAL_EL0_SysRegRead_4db28ae745612584 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_CVAL_EL0_SysRegRead_4db28ae745612584_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTP_TVAL_EL02_SysRegRead_6539005e4eb68283[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTP_TVAL_EL02_SysRegRead_6539005e4eb68283 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_TVAL_EL02_SysRegRead_6539005e4eb68283_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTP_TVAL_EL0_SysRegRead_54cebb7fbc71b9db[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTP_TVAL_EL0_SysRegRead_54cebb7fbc71b9db el op0 op1 CRn op2 CRm)" + by (unfold CNTP_TVAL_EL0_SysRegRead_54cebb7fbc71b9db_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTVCT_EL0_SysRegRead_cd7c8aebed2715e6[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTVCT_EL0_SysRegRead_cd7c8aebed2715e6 el op0 op1 CRn op2 CRm)" + by (unfold CNTVCT_EL0_SysRegRead_cd7c8aebed2715e6_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTVOFF_EL2_SysRegRead_5ca7336b54f14c06[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTVOFF_EL2_SysRegRead_5ca7336b54f14c06 el op0 op1 CRn op2 CRm)" + by (unfold CNTVOFF_EL2_SysRegRead_5ca7336b54f14c06_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTV_CTL_EL02_SysRegRead_4188a8e2bc5c07aa[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTV_CTL_EL02_SysRegRead_4188a8e2bc5c07aa el op0 op1 CRn op2 CRm)" + by (unfold CNTV_CTL_EL02_SysRegRead_4188a8e2bc5c07aa_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTV_CTL_EL0_SysRegRead_bcb2d1b80bdb9c23[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTV_CTL_EL0_SysRegRead_bcb2d1b80bdb9c23 el op0 op1 CRn op2 CRm)" + by (unfold CNTV_CTL_EL0_SysRegRead_bcb2d1b80bdb9c23_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTV_CVAL_EL02_SysRegRead_abd2b9f314cb85b2[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTV_CVAL_EL02_SysRegRead_abd2b9f314cb85b2 el op0 op1 CRn op2 CRm)" + by (unfold CNTV_CVAL_EL02_SysRegRead_abd2b9f314cb85b2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTV_CVAL_EL0_SysRegRead_54d5eb0bec99456f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTV_CVAL_EL0_SysRegRead_54d5eb0bec99456f el op0 op1 CRn op2 CRm)" + by (unfold CNTV_CVAL_EL0_SysRegRead_54d5eb0bec99456f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTV_TVAL_EL02_SysRegRead_f904ccdf39aea128[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTV_TVAL_EL02_SysRegRead_f904ccdf39aea128 el op0 op1 CRn op2 CRm)" + by (unfold CNTV_TVAL_EL02_SysRegRead_f904ccdf39aea128_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTV_TVAL_EL0_SysRegRead_919e73a694090e48[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CNTV_TVAL_EL0_SysRegRead_919e73a694090e48 el op0 op1 CRn op2 CRm)" + by (unfold CNTV_TVAL_EL0_SysRegRead_919e73a694090e48_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CONTEXTIDR_EL12_SysRegRead_2aa676fc0cfd631b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CONTEXTIDR_EL12_SysRegRead_2aa676fc0cfd631b el op0 op1 CRn op2 CRm)" + by (unfold CONTEXTIDR_EL12_SysRegRead_2aa676fc0cfd631b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CONTEXTIDR_EL1_SysRegRead_fa54232c55ea14e3[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CONTEXTIDR_EL1_SysRegRead_fa54232c55ea14e3 el op0 op1 CRn op2 CRm)" + by (unfold CONTEXTIDR_EL1_SysRegRead_fa54232c55ea14e3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CONTEXTIDR_EL2_SysRegRead_f7bf9114ce3113a6[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CONTEXTIDR_EL2_SysRegRead_f7bf9114ce3113a6 el op0 op1 CRn op2 CRm)" + by (unfold CONTEXTIDR_EL2_SysRegRead_f7bf9114ce3113a6_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CPACR_EL12_SysRegRead_0f7867518c4e8e99[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CPACR_EL12_SysRegRead_0f7867518c4e8e99 el op0 op1 CRn op2 CRm)" + by (unfold CPACR_EL12_SysRegRead_0f7867518c4e8e99_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CPACR_EL1_SysRegRead_63b8f196f3ebba22[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CPACR_EL1_SysRegRead_63b8f196f3ebba22 el op0 op1 CRn op2 CRm)" + by (unfold CPACR_EL1_SysRegRead_63b8f196f3ebba22_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CPTR_EL2_SysRegRead_d80843789adc6a43[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CPTR_EL2_SysRegRead_d80843789adc6a43 el op0 op1 CRn op2 CRm)" + by (unfold CPTR_EL2_SysRegRead_d80843789adc6a43_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CPTR_EL3_SysRegRead_33cb1e5ec3c99661[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CPTR_EL3_SysRegRead_33cb1e5ec3c99661 el op0 op1 CRn op2 CRm)" + by (unfold CPTR_EL3_SysRegRead_33cb1e5ec3c99661_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CSCR_EL3_SysRegRead_3c6b19768f9cd209[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CSCR_EL3_SysRegRead_3c6b19768f9cd209 el op0 op1 CRn op2 CRm)" + by (unfold CSCR_EL3_SysRegRead_3c6b19768f9cd209_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CSSELR_EL1_SysRegRead_102b4cddc07c9121[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CSSELR_EL1_SysRegRead_102b4cddc07c9121 el op0 op1 CRn op2 CRm)" + by (unfold CSSELR_EL1_SysRegRead_102b4cddc07c9121_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CTR_EL0_SysRegRead_54ef8c769c3c6bba[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CTR_EL0_SysRegRead_54ef8c769c3c6bba el op0 op1 CRn op2 CRm)" + by (unfold CTR_EL0_SysRegRead_54ef8c769c3c6bba_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DACR32_EL2_SysRegRead_9571e2946627a596[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DACR32_EL2_SysRegRead_9571e2946627a596 el op0 op1 CRn op2 CRm)" + by (unfold DACR32_EL2_SysRegRead_9571e2946627a596_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DAIF_SysRegRead_198f3b46fcf6c8f0[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DAIF_SysRegRead_198f3b46fcf6c8f0 el op0 op1 CRn op2 CRm)" + by (unfold DAIF_SysRegRead_198f3b46fcf6c8f0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGAUTHSTATUS_EL1_SysRegRead_6ade6e7a5265bcb7[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DBGAUTHSTATUS_EL1_SysRegRead_6ade6e7a5265bcb7 el op0 op1 CRn op2 CRm)" + by (unfold DBGAUTHSTATUS_EL1_SysRegRead_6ade6e7a5265bcb7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGBCR_EL1_SysRegRead_2d021994672d40d3[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGBCR_EL1_SysRegRead_2d021994672d40d3 el op0 op1 CRn op2 CRm)" + by (unfold DBGBCR_EL1_SysRegRead_2d021994672d40d3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGBVR_EL1_SysRegRead_dc4a8f61b400622f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGBVR_EL1_SysRegRead_dc4a8f61b400622f el op0 op1 CRn op2 CRm)" + by (unfold DBGBVR_EL1_SysRegRead_dc4a8f61b400622f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGCLAIMCLR_EL1_SysRegRead_72ae03c1d5f667da[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DBGCLAIMCLR_EL1_SysRegRead_72ae03c1d5f667da el op0 op1 CRn op2 CRm)" + by (unfold DBGCLAIMCLR_EL1_SysRegRead_72ae03c1d5f667da_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGCLAIMSET_EL1_SysRegRead_8557cf3b6272a9e8[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DBGCLAIMSET_EL1_SysRegRead_8557cf3b6272a9e8 el op0 op1 CRn op2 CRm)" + by (unfold DBGCLAIMSET_EL1_SysRegRead_8557cf3b6272a9e8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGDTRRX_EL0_SysRegRead_e7b48d8296f3b86b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DBGDTRRX_EL0_SysRegRead_e7b48d8296f3b86b el op0 op1 CRn op2 CRm)" + by (unfold DBGDTRRX_EL0_SysRegRead_e7b48d8296f3b86b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGDTR_EL0_SysRegRead_537a006eb82c59aa[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DBGDTR_EL0_SysRegRead_537a006eb82c59aa el op0 op1 CRn op2 CRm)" + by (unfold DBGDTR_EL0_SysRegRead_537a006eb82c59aa_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGPRCR_EL1_SysRegRead_6b19d62af9619a21[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DBGPRCR_EL1_SysRegRead_6b19d62af9619a21 el op0 op1 CRn op2 CRm)" + by (unfold DBGPRCR_EL1_SysRegRead_6b19d62af9619a21_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGVCR32_EL2_SysRegRead_7986b2bdf8df010d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DBGVCR32_EL2_SysRegRead_7986b2bdf8df010d el op0 op1 CRn op2 CRm)" + by (unfold DBGVCR32_EL2_SysRegRead_7986b2bdf8df010d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGWCR_EL1_SysRegRead_03139d052b544b2f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGWCR_EL1_SysRegRead_03139d052b544b2f el op0 op1 CRn op2 CRm)" + by (unfold DBGWCR_EL1_SysRegRead_03139d052b544b2f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGWVR_EL1_SysRegRead_029de1005ef34888[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGWVR_EL1_SysRegRead_029de1005ef34888 el op0 op1 CRn op2 CRm)" + by (unfold DBGWVR_EL1_SysRegRead_029de1005ef34888_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DISR_EL1_SysRegRead_d06ce25101dac895[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DISR_EL1_SysRegRead_d06ce25101dac895 el op0 op1 CRn op2 CRm)" + by (unfold DISR_EL1_SysRegRead_d06ce25101dac895_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERRIDR_EL1_SysRegRead_41b56b8d34e51109[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ERRIDR_EL1_SysRegRead_41b56b8d34e51109 el op0 op1 CRn op2 CRm)" + by (unfold ERRIDR_EL1_SysRegRead_41b56b8d34e51109_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERRSELR_EL1_SysRegRead_1bcf942400e8d57f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ERRSELR_EL1_SysRegRead_1bcf942400e8d57f el op0 op1 CRn op2 CRm)" + by (unfold ERRSELR_EL1_SysRegRead_1bcf942400e8d57f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERXADDR_EL1_SysRegRead_7dea05bca757fc1d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ERXADDR_EL1_SysRegRead_7dea05bca757fc1d el op0 op1 CRn op2 CRm)" + by (unfold ERXADDR_EL1_SysRegRead_7dea05bca757fc1d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERXCTLR_EL1_SysRegRead_e46ed88d092db048[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ERXCTLR_EL1_SysRegRead_e46ed88d092db048 el op0 op1 CRn op2 CRm)" + by (unfold ERXCTLR_EL1_SysRegRead_e46ed88d092db048_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERXFR_EL1_SysRegRead_ed2a3c237ae67a43[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ERXFR_EL1_SysRegRead_ed2a3c237ae67a43 el op0 op1 CRn op2 CRm)" + by (unfold ERXFR_EL1_SysRegRead_ed2a3c237ae67a43_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERXMISC0_EL1_SysRegRead_a71a4de5f2444f19[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ERXMISC0_EL1_SysRegRead_a71a4de5f2444f19 el op0 op1 CRn op2 CRm)" + by (unfold ERXMISC0_EL1_SysRegRead_a71a4de5f2444f19_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERXMISC1_EL1_SysRegRead_bda613f8058b1fd8[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ERXMISC1_EL1_SysRegRead_bda613f8058b1fd8 el op0 op1 CRn op2 CRm)" + by (unfold ERXMISC1_EL1_SysRegRead_bda613f8058b1fd8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERXSTATUS_EL1_SysRegRead_0ab2cfe6937b8b64[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ERXSTATUS_EL1_SysRegRead_0ab2cfe6937b8b64 el op0 op1 CRn op2 CRm)" + by (unfold ERXSTATUS_EL1_SysRegRead_0ab2cfe6937b8b64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ESR_EL12_SysRegRead_207d3805d256851a[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ESR_EL12_SysRegRead_207d3805d256851a el op0 op1 CRn op2 CRm)" + by (unfold ESR_EL12_SysRegRead_207d3805d256851a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ESR_EL1_SysRegRead_4894753806397624[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ESR_EL1_SysRegRead_4894753806397624 el op0 op1 CRn op2 CRm)" + by (unfold ESR_EL1_SysRegRead_4894753806397624_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ESR_EL2_SysRegRead_e0558cb255261414[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ESR_EL2_SysRegRead_e0558cb255261414 el op0 op1 CRn op2 CRm)" + by (unfold ESR_EL2_SysRegRead_e0558cb255261414_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ESR_EL3_SysRegRead_e0eabec0b099e366[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ESR_EL3_SysRegRead_e0eabec0b099e366 el op0 op1 CRn op2 CRm)" + by (unfold ESR_EL3_SysRegRead_e0eabec0b099e366_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FAR_EL12_SysRegRead_061fecffb03f9fc5[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (FAR_EL12_SysRegRead_061fecffb03f9fc5 el op0 op1 CRn op2 CRm)" + by (unfold FAR_EL12_SysRegRead_061fecffb03f9fc5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FAR_EL1_SysRegRead_136ac0cc65bd5f9d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (FAR_EL1_SysRegRead_136ac0cc65bd5f9d el op0 op1 CRn op2 CRm)" + by (unfold FAR_EL1_SysRegRead_136ac0cc65bd5f9d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FAR_EL2_SysRegRead_d686d0a5577f0aae[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (FAR_EL2_SysRegRead_d686d0a5577f0aae el op0 op1 CRn op2 CRm)" + by (unfold FAR_EL2_SysRegRead_d686d0a5577f0aae_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FAR_EL3_SysRegRead_d63ec2764f8ffe40[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (FAR_EL3_SysRegRead_d63ec2764f8ffe40 el op0 op1 CRn op2 CRm)" + by (unfold FAR_EL3_SysRegRead_d63ec2764f8ffe40_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPCR_SysRegRead_4176e216195c5686[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (FPCR_SysRegRead_4176e216195c5686 el op0 op1 CRn op2 CRm)" + by (unfold FPCR_SysRegRead_4176e216195c5686_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPEXC32_EL2_SysRegRead_7ee503337da57806[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (FPEXC32_EL2_SysRegRead_7ee503337da57806 el op0 op1 CRn op2 CRm)" + by (unfold FPEXC32_EL2_SysRegRead_7ee503337da57806_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPSR_SysRegRead_c1fde5c387acaca1[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (FPSR_SysRegRead_c1fde5c387acaca1 el op0 op1 CRn op2 CRm)" + by (unfold FPSR_SysRegRead_c1fde5c387acaca1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_HACR_EL2_SysRegRead_07bc3864e8ed8264[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (HACR_EL2_SysRegRead_07bc3864e8ed8264 el op0 op1 CRn op2 CRm)" + by (unfold HACR_EL2_SysRegRead_07bc3864e8ed8264_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_HCR_EL2_SysRegRead_f76ecfdc85c5ff7c[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (HCR_EL2_SysRegRead_f76ecfdc85c5ff7c el op0 op1 CRn op2 CRm)" + by (unfold HCR_EL2_SysRegRead_f76ecfdc85c5ff7c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_HPFAR_EL2_SysRegRead_4c322cee424dff18[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (HPFAR_EL2_SysRegRead_4c322cee424dff18 el op0 op1 CRn op2 CRm)" + by (unfold HPFAR_EL2_SysRegRead_4c322cee424dff18_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_HSTR_EL2_SysRegRead_680380b9028cf399[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (HSTR_EL2_SysRegRead_680380b9028cf399 el op0 op1 CRn op2 CRm)" + by (unfold HSTR_EL2_SysRegRead_680380b9028cf399_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_AP0R_EL1_SysRegRead_cac9b22dc3786a15[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_AP0R_EL1_SysRegRead_cac9b22dc3786a15 el op0 op1 CRn op2 CRm)" + by (unfold ICC_AP0R_EL1_SysRegRead_cac9b22dc3786a15_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_AP1R_EL1_SysRegRead_4127418c67790ba3[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_AP1R_EL1_SysRegRead_4127418c67790ba3 el op0 op1 CRn op2 CRm)" + by (unfold ICC_AP1R_EL1_SysRegRead_4127418c67790ba3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_BPR0_EL1_SysRegRead_6ada10a9051248c2[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_BPR0_EL1_SysRegRead_6ada10a9051248c2 el op0 op1 CRn op2 CRm)" + by (unfold ICC_BPR0_EL1_SysRegRead_6ada10a9051248c2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_BPR1_EL1_SysRegRead_c56bf88f1b4aee37[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_BPR1_EL1_SysRegRead_c56bf88f1b4aee37 el op0 op1 CRn op2 CRm)" + by (unfold ICC_BPR1_EL1_SysRegRead_c56bf88f1b4aee37_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_CTLR_EL1_SysRegRead_5754830bf787a1e2[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_CTLR_EL1_SysRegRead_5754830bf787a1e2 el op0 op1 CRn op2 CRm)" + by (unfold ICC_CTLR_EL1_SysRegRead_5754830bf787a1e2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_CTLR_EL3_SysRegRead_aba1771445e9d51b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_CTLR_EL3_SysRegRead_aba1771445e9d51b el op0 op1 CRn op2 CRm)" + by (unfold ICC_CTLR_EL3_SysRegRead_aba1771445e9d51b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_HPPIR0_EL1_SysRegRead_221f9a6f32464de4[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_HPPIR0_EL1_SysRegRead_221f9a6f32464de4 el op0 op1 CRn op2 CRm)" + by (unfold ICC_HPPIR0_EL1_SysRegRead_221f9a6f32464de4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_HPPIR1_EL1_SysRegRead_88ed0889f7d5a37a[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_HPPIR1_EL1_SysRegRead_88ed0889f7d5a37a el op0 op1 CRn op2 CRm)" + by (unfold ICC_HPPIR1_EL1_SysRegRead_88ed0889f7d5a37a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_IAR0_EL1_SysRegRead_dcfaf70befc09037[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_IAR0_EL1_SysRegRead_dcfaf70befc09037 el op0 op1 CRn op2 CRm)" + by (unfold ICC_IAR0_EL1_SysRegRead_dcfaf70befc09037_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_IAR1_EL1_SysRegRead_9f370ba68fd3e44f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_IAR1_EL1_SysRegRead_9f370ba68fd3e44f el op0 op1 CRn op2 CRm)" + by (unfold ICC_IAR1_EL1_SysRegRead_9f370ba68fd3e44f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_IGRPEN0_EL1_SysRegRead_e575448f3c7e7a94[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_IGRPEN0_EL1_SysRegRead_e575448f3c7e7a94 el op0 op1 CRn op2 CRm)" + by (unfold ICC_IGRPEN0_EL1_SysRegRead_e575448f3c7e7a94_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_IGRPEN1_EL1_SysRegRead_3cfd0733ef9b6efa[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_IGRPEN1_EL1_SysRegRead_3cfd0733ef9b6efa el op0 op1 CRn op2 CRm)" + by (unfold ICC_IGRPEN1_EL1_SysRegRead_3cfd0733ef9b6efa_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_IGRPEN1_EL3_SysRegRead_d192d252016b4c8d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_IGRPEN1_EL3_SysRegRead_d192d252016b4c8d el op0 op1 CRn op2 CRm)" + by (unfold ICC_IGRPEN1_EL3_SysRegRead_d192d252016b4c8d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_PMR_EL1_SysRegRead_4ab2c9427488fbf4[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_PMR_EL1_SysRegRead_4ab2c9427488fbf4 el op0 op1 CRn op2 CRm)" + by (unfold ICC_PMR_EL1_SysRegRead_4ab2c9427488fbf4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_RPR_EL1_SysRegRead_bea9edc41b26aab0[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_RPR_EL1_SysRegRead_bea9edc41b26aab0 el op0 op1 CRn op2 CRm)" + by (unfold ICC_RPR_EL1_SysRegRead_bea9edc41b26aab0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_SRE_EL1_SysRegRead_7cf0aa9fc619dea4[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_SRE_EL1_SysRegRead_7cf0aa9fc619dea4 el op0 op1 CRn op2 CRm)" + by (unfold ICC_SRE_EL1_SysRegRead_7cf0aa9fc619dea4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_SRE_EL2_SysRegRead_35c9349812c986fe[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_SRE_EL2_SysRegRead_35c9349812c986fe el op0 op1 CRn op2 CRm)" + by (unfold ICC_SRE_EL2_SysRegRead_35c9349812c986fe_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_SRE_EL3_SysRegRead_c7d421022a5f589d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICC_SRE_EL3_SysRegRead_c7d421022a5f589d el op0 op1 CRn op2 CRm)" + by (unfold ICC_SRE_EL3_SysRegRead_c7d421022a5f589d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_AP0R_EL2_SysRegRead_a38114229330a389[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICH_AP0R_EL2_SysRegRead_a38114229330a389 el op0 op1 CRn op2 CRm)" + by (unfold ICH_AP0R_EL2_SysRegRead_a38114229330a389_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_AP1R_EL2_SysRegRead_3ef1256520a6f18e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICH_AP1R_EL2_SysRegRead_3ef1256520a6f18e el op0 op1 CRn op2 CRm)" + by (unfold ICH_AP1R_EL2_SysRegRead_3ef1256520a6f18e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_EISR_EL2_SysRegRead_a45d99ec0ef64804[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICH_EISR_EL2_SysRegRead_a45d99ec0ef64804 el op0 op1 CRn op2 CRm)" + by (unfold ICH_EISR_EL2_SysRegRead_a45d99ec0ef64804_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_ELRSR_EL2_SysRegRead_93859a236e9efe6d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICH_ELRSR_EL2_SysRegRead_93859a236e9efe6d el op0 op1 CRn op2 CRm)" + by (unfold ICH_ELRSR_EL2_SysRegRead_93859a236e9efe6d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_HCR_EL2_SysRegRead_bd436f3e91661e3b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICH_HCR_EL2_SysRegRead_bd436f3e91661e3b el op0 op1 CRn op2 CRm)" + by (unfold ICH_HCR_EL2_SysRegRead_bd436f3e91661e3b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_LR_EL2_SysRegRead_f9d8d38c7064e389[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICH_LR_EL2_SysRegRead_f9d8d38c7064e389 el op0 op1 CRn op2 CRm)" + by (unfold ICH_LR_EL2_SysRegRead_f9d8d38c7064e389_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_MISR_EL2_SysRegRead_4e46f86d49bd21cd[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICH_MISR_EL2_SysRegRead_4e46f86d49bd21cd el op0 op1 CRn op2 CRm)" + by (unfold ICH_MISR_EL2_SysRegRead_4e46f86d49bd21cd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_VMCR_EL2_SysRegRead_3c019711ec735507[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICH_VMCR_EL2_SysRegRead_3c019711ec735507 el op0 op1 CRn op2 CRm)" + by (unfold ICH_VMCR_EL2_SysRegRead_3c019711ec735507_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_VTR_EL2_SysRegRead_2ed82d00af03b344[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ICH_VTR_EL2_SysRegRead_2ed82d00af03b344 el op0 op1 CRn op2 CRm)" + by (unfold ICH_VTR_EL2_SysRegRead_2ed82d00af03b344_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_AA64AFR0_EL1_SysRegRead_325547f3ac10431a[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_AA64AFR0_EL1_SysRegRead_325547f3ac10431a el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64AFR0_EL1_SysRegRead_325547f3ac10431a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_AA64AFR1_EL1_SysRegRead_99b67b76121ee706[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_AA64AFR1_EL1_SysRegRead_99b67b76121ee706 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64AFR1_EL1_SysRegRead_99b67b76121ee706_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_AA64DFR0_EL1_SysRegRead_c3e6b049dd70bbab[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_AA64DFR0_EL1_SysRegRead_c3e6b049dd70bbab el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64DFR0_EL1_SysRegRead_c3e6b049dd70bbab_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_AA64DFR1_EL1_SysRegRead_2f066031859d7035[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_AA64DFR1_EL1_SysRegRead_2f066031859d7035 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64DFR1_EL1_SysRegRead_2f066031859d7035_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_AA64ISAR0_EL1_SysRegRead_d35f255c04eaab0f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_AA64ISAR0_EL1_SysRegRead_d35f255c04eaab0f el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64ISAR0_EL1_SysRegRead_d35f255c04eaab0f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_AA64ISAR1_EL1_SysRegRead_1132f371c4707f61[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_AA64ISAR1_EL1_SysRegRead_1132f371c4707f61 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64ISAR1_EL1_SysRegRead_1132f371c4707f61_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_AA64MMFR0_EL1_SysRegRead_836c46ff67ac3f3d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_AA64MMFR0_EL1_SysRegRead_836c46ff67ac3f3d el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64MMFR0_EL1_SysRegRead_836c46ff67ac3f3d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_AA64MMFR1_EL1_SysRegRead_3abbf4d2af8dd3be[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_AA64MMFR1_EL1_SysRegRead_3abbf4d2af8dd3be el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64MMFR1_EL1_SysRegRead_3abbf4d2af8dd3be_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_AA64MMFR2_EL1_SysRegRead_1443648da3ca79dd[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_AA64MMFR2_EL1_SysRegRead_1443648da3ca79dd el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64MMFR2_EL1_SysRegRead_1443648da3ca79dd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_AA64PFR0_EL1_SysRegRead_fe78f914579c8717[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_AA64PFR0_EL1_SysRegRead_fe78f914579c8717 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64PFR0_EL1_SysRegRead_fe78f914579c8717_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_AA64PFR1_EL1_SysRegRead_3be470f3d1bff138[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_AA64PFR1_EL1_SysRegRead_3be470f3d1bff138 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64PFR1_EL1_SysRegRead_3be470f3d1bff138_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_AA64ZFR0_EL1_SysRegRead_70425f5143f66c9f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_AA64ZFR0_EL1_SysRegRead_70425f5143f66c9f el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64ZFR0_EL1_SysRegRead_70425f5143f66c9f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_AFR0_EL1_SysRegRead_019e5ec822653217[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_AFR0_EL1_SysRegRead_019e5ec822653217 el op0 op1 CRn op2 CRm)" + by (unfold ID_AFR0_EL1_SysRegRead_019e5ec822653217_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_DFR0_EL1_SysRegRead_12146217191b4fee[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_DFR0_EL1_SysRegRead_12146217191b4fee el op0 op1 CRn op2 CRm)" + by (unfold ID_DFR0_EL1_SysRegRead_12146217191b4fee_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_ISAR0_EL1_SysRegRead_4e2f04c3a26dddb3[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_ISAR0_EL1_SysRegRead_4e2f04c3a26dddb3 el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR0_EL1_SysRegRead_4e2f04c3a26dddb3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_ISAR1_EL1_SysRegRead_2f4500748023e22b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_ISAR1_EL1_SysRegRead_2f4500748023e22b el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR1_EL1_SysRegRead_2f4500748023e22b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_ISAR2_EL1_SysRegRead_1e8edaee6a0e9ef9[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_ISAR2_EL1_SysRegRead_1e8edaee6a0e9ef9 el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR2_EL1_SysRegRead_1e8edaee6a0e9ef9_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_ISAR3_EL1_SysRegRead_cf9a1aae39d73bdd[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_ISAR3_EL1_SysRegRead_cf9a1aae39d73bdd el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR3_EL1_SysRegRead_cf9a1aae39d73bdd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_ISAR4_EL1_SysRegRead_9bffd9dcf4dd4ef4[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_ISAR4_EL1_SysRegRead_9bffd9dcf4dd4ef4 el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR4_EL1_SysRegRead_9bffd9dcf4dd4ef4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_ISAR5_EL1_SysRegRead_f70928ed2f55c1f0[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_ISAR5_EL1_SysRegRead_f70928ed2f55c1f0 el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR5_EL1_SysRegRead_f70928ed2f55c1f0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_ISAR6_EL1_SysRegRead_6ce3605912a2db6d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_ISAR6_EL1_SysRegRead_6ce3605912a2db6d el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR6_EL1_SysRegRead_6ce3605912a2db6d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_MMFR0_EL1_SysRegRead_b31c5faa39841084[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_MMFR0_EL1_SysRegRead_b31c5faa39841084 el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR0_EL1_SysRegRead_b31c5faa39841084_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_MMFR1_EL1_SysRegRead_b0f4bc0d71c9af14[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_MMFR1_EL1_SysRegRead_b0f4bc0d71c9af14 el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR1_EL1_SysRegRead_b0f4bc0d71c9af14_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_MMFR2_EL1_SysRegRead_b60501193094f759[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_MMFR2_EL1_SysRegRead_b60501193094f759 el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR2_EL1_SysRegRead_b60501193094f759_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_MMFR3_EL1_SysRegRead_dc45af19c356c392[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_MMFR3_EL1_SysRegRead_dc45af19c356c392 el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR3_EL1_SysRegRead_dc45af19c356c392_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_MMFR4_EL1_SysRegRead_237ae4b6fb487f3e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_MMFR4_EL1_SysRegRead_237ae4b6fb487f3e el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR4_EL1_SysRegRead_237ae4b6fb487f3e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_MMFR5_EL1_SysRegRead_00dc6140c3593f6a[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_MMFR5_EL1_SysRegRead_00dc6140c3593f6a el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR5_EL1_SysRegRead_00dc6140c3593f6a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_PFR0_EL1_SysRegRead_ab73eb91d66cfece[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_PFR0_EL1_SysRegRead_ab73eb91d66cfece el op0 op1 CRn op2 CRm)" + by (unfold ID_PFR0_EL1_SysRegRead_ab73eb91d66cfece_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_PFR1_EL1_SysRegRead_264075958e26856b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_PFR1_EL1_SysRegRead_264075958e26856b el op0 op1 CRn op2 CRm)" + by (unfold ID_PFR1_EL1_SysRegRead_264075958e26856b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ID_PFR2_EL1_SysRegRead_8561b575e8dfcee0[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ID_PFR2_EL1_SysRegRead_8561b575e8dfcee0 el op0 op1 CRn op2 CRm)" + by (unfold ID_PFR2_EL1_SysRegRead_8561b575e8dfcee0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_IFSR32_EL2_SysRegRead_3b41290786c143ba[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (IFSR32_EL2_SysRegRead_3b41290786c143ba el op0 op1 CRn op2 CRm)" + by (unfold IFSR32_EL2_SysRegRead_3b41290786c143ba_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ISR_EL1_SysRegRead_41b7dbf26b89e726[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ISR_EL1_SysRegRead_41b7dbf26b89e726 el op0 op1 CRn op2 CRm)" + by (unfold ISR_EL1_SysRegRead_41b7dbf26b89e726_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_LORC_EL1_SysRegRead_0067e90ee116c26f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (LORC_EL1_SysRegRead_0067e90ee116c26f el op0 op1 CRn op2 CRm)" + by (unfold LORC_EL1_SysRegRead_0067e90ee116c26f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_LOREA_EL1_SysRegRead_ec495c3c15ed4dbe[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (LOREA_EL1_SysRegRead_ec495c3c15ed4dbe el op0 op1 CRn op2 CRm)" + by (unfold LOREA_EL1_SysRegRead_ec495c3c15ed4dbe_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_LORID_EL1_SysRegRead_a063108cc96d4baa[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (LORID_EL1_SysRegRead_a063108cc96d4baa el op0 op1 CRn op2 CRm)" + by (unfold LORID_EL1_SysRegRead_a063108cc96d4baa_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_LORN_EL1_SysRegRead_da981b495b21c400[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (LORN_EL1_SysRegRead_da981b495b21c400 el op0 op1 CRn op2 CRm)" + by (unfold LORN_EL1_SysRegRead_da981b495b21c400_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_LORSA_EL1_SysRegRead_cdc08dda4115abc7[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (LORSA_EL1_SysRegRead_cdc08dda4115abc7 el op0 op1 CRn op2 CRm)" + by (unfold LORSA_EL1_SysRegRead_cdc08dda4115abc7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MAIR_EL12_SysRegRead_ac3327848e47dda6[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MAIR_EL12_SysRegRead_ac3327848e47dda6 el op0 op1 CRn op2 CRm)" + by (unfold MAIR_EL12_SysRegRead_ac3327848e47dda6_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MAIR_EL1_SysRegRead_ee00b1441fc4a50d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MAIR_EL1_SysRegRead_ee00b1441fc4a50d el op0 op1 CRn op2 CRm)" + by (unfold MAIR_EL1_SysRegRead_ee00b1441fc4a50d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MAIR_EL2_SysRegRead_66c03f7cb594c1bd[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MAIR_EL2_SysRegRead_66c03f7cb594c1bd el op0 op1 CRn op2 CRm)" + by (unfold MAIR_EL2_SysRegRead_66c03f7cb594c1bd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MAIR_EL3_SysRegRead_0eb4af28a4f9b45a[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MAIR_EL3_SysRegRead_0eb4af28a4f9b45a el op0 op1 CRn op2 CRm)" + by (unfold MAIR_EL3_SysRegRead_0eb4af28a4f9b45a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MDCCINT_EL1_SysRegRead_12f1a0397d5a3729[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MDCCINT_EL1_SysRegRead_12f1a0397d5a3729 el op0 op1 CRn op2 CRm)" + by (unfold MDCCINT_EL1_SysRegRead_12f1a0397d5a3729_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MDCCSR_EL0_SysRegRead_1ca0d9105cd616c5[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MDCCSR_EL0_SysRegRead_1ca0d9105cd616c5 el op0 op1 CRn op2 CRm)" + by (unfold MDCCSR_EL0_SysRegRead_1ca0d9105cd616c5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MDCR_EL2_SysRegRead_f2181c815a998208[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MDCR_EL2_SysRegRead_f2181c815a998208 el op0 op1 CRn op2 CRm)" + by (unfold MDCR_EL2_SysRegRead_f2181c815a998208_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MDCR_EL3_SysRegRead_229d5ee95c6e9850[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MDCR_EL3_SysRegRead_229d5ee95c6e9850 el op0 op1 CRn op2 CRm)" + by (unfold MDCR_EL3_SysRegRead_229d5ee95c6e9850_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MDRAR_EL1_SysRegRead_4c6f0d270d3fe56e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MDRAR_EL1_SysRegRead_4c6f0d270d3fe56e el op0 op1 CRn op2 CRm)" + by (unfold MDRAR_EL1_SysRegRead_4c6f0d270d3fe56e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MDSCR_EL1_SysRegRead_5184636ced539526[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MDSCR_EL1_SysRegRead_5184636ced539526 el op0 op1 CRn op2 CRm)" + by (unfold MDSCR_EL1_SysRegRead_5184636ced539526_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MIDR_EL1_SysRegRead_d49cc5f604ad167e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MIDR_EL1_SysRegRead_d49cc5f604ad167e el op0 op1 CRn op2 CRm)" + by (unfold MIDR_EL1_SysRegRead_d49cc5f604ad167e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAM0_EL1_SysRegRead_87af318fd5c9f9f7[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAM0_EL1_SysRegRead_87af318fd5c9f9f7 el op0 op1 CRn op2 CRm)" + by (unfold MPAM0_EL1_SysRegRead_87af318fd5c9f9f7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAM1_EL12_SysRegRead_229a253b730e26d9[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAM1_EL12_SysRegRead_229a253b730e26d9 el op0 op1 CRn op2 CRm)" + by (unfold MPAM1_EL12_SysRegRead_229a253b730e26d9_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAM1_EL1_SysRegRead_770ea23b87b18d99[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAM1_EL1_SysRegRead_770ea23b87b18d99 el op0 op1 CRn op2 CRm)" + by (unfold MPAM1_EL1_SysRegRead_770ea23b87b18d99_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAM2_EL2_SysRegRead_10b60646fb381bea[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAM2_EL2_SysRegRead_10b60646fb381bea el op0 op1 CRn op2 CRm)" + by (unfold MPAM2_EL2_SysRegRead_10b60646fb381bea_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAM3_EL3_SysRegRead_989f38b07d8b4265[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAM3_EL3_SysRegRead_989f38b07d8b4265 el op0 op1 CRn op2 CRm)" + by (unfold MPAM3_EL3_SysRegRead_989f38b07d8b4265_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMHCR_EL2_SysRegRead_6ee5f61be808e32e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAMHCR_EL2_SysRegRead_6ee5f61be808e32e el op0 op1 CRn op2 CRm)" + by (unfold MPAMHCR_EL2_SysRegRead_6ee5f61be808e32e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMIDR_EL1_SysRegRead_df4c57d831354b3c[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAMIDR_EL1_SysRegRead_df4c57d831354b3c el op0 op1 CRn op2 CRm)" + by (unfold MPAMIDR_EL1_SysRegRead_df4c57d831354b3c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM0_EL2_SysRegRead_d878a15f2ea1751d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAMVPM0_EL2_SysRegRead_d878a15f2ea1751d el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM0_EL2_SysRegRead_d878a15f2ea1751d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM1_EL2_SysRegRead_78ba55a3ef5fc5ba[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAMVPM1_EL2_SysRegRead_78ba55a3ef5fc5ba el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM1_EL2_SysRegRead_78ba55a3ef5fc5ba_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM2_EL2_SysRegRead_590d1577b5eb780d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAMVPM2_EL2_SysRegRead_590d1577b5eb780d el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM2_EL2_SysRegRead_590d1577b5eb780d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM3_EL2_SysRegRead_3d93a30deb34ea81[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAMVPM3_EL2_SysRegRead_3d93a30deb34ea81 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM3_EL2_SysRegRead_3d93a30deb34ea81_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM4_EL2_SysRegRead_c4fa65dba541d8f3[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAMVPM4_EL2_SysRegRead_c4fa65dba541d8f3 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM4_EL2_SysRegRead_c4fa65dba541d8f3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM5_EL2_SysRegRead_0f596cf6a35cf124[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAMVPM5_EL2_SysRegRead_0f596cf6a35cf124 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM5_EL2_SysRegRead_0f596cf6a35cf124_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM6_EL2_SysRegRead_c93ffeb6ea409c71[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAMVPM6_EL2_SysRegRead_c93ffeb6ea409c71 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM6_EL2_SysRegRead_c93ffeb6ea409c71_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM7_EL2_SysRegRead_ef19c89f1fa31f3e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAMVPM7_EL2_SysRegRead_ef19c89f1fa31f3e el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM7_EL2_SysRegRead_ef19c89f1fa31f3e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPMV_EL2_SysRegRead_6de5731367257b91[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPAMVPMV_EL2_SysRegRead_6de5731367257b91 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPMV_EL2_SysRegRead_6de5731367257b91_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPIDR_EL1_SysRegRead_1a44c237fc7e90a0[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MPIDR_EL1_SysRegRead_1a44c237fc7e90a0 el op0 op1 CRn op2 CRm)" + by (unfold MPIDR_EL1_SysRegRead_1a44c237fc7e90a0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MVFR0_EL1_SysRegRead_982614cb681cfbbf[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MVFR0_EL1_SysRegRead_982614cb681cfbbf el op0 op1 CRn op2 CRm)" + by (unfold MVFR0_EL1_SysRegRead_982614cb681cfbbf_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MVFR1_EL1_SysRegRead_1964a95566ab0fcd[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MVFR1_EL1_SysRegRead_1964a95566ab0fcd el op0 op1 CRn op2 CRm)" + by (unfold MVFR1_EL1_SysRegRead_1964a95566ab0fcd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MVFR2_EL1_SysRegRead_f6245ffc535897f2[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MVFR2_EL1_SysRegRead_f6245ffc535897f2 el op0 op1 CRn op2 CRm)" + by (unfold MVFR2_EL1_SysRegRead_f6245ffc535897f2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_OSDLR_EL1_SysRegRead_4cb80c508c4cced4[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (OSDLR_EL1_SysRegRead_4cb80c508c4cced4 el op0 op1 CRn op2 CRm)" + by (unfold OSDLR_EL1_SysRegRead_4cb80c508c4cced4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_OSDTRRX_EL1_SysRegRead_d4eb07360bc69d28[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (OSDTRRX_EL1_SysRegRead_d4eb07360bc69d28 el op0 op1 CRn op2 CRm)" + by (unfold OSDTRRX_EL1_SysRegRead_d4eb07360bc69d28_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_OSDTRTX_EL1_SysRegRead_008c22058272684f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (OSDTRTX_EL1_SysRegRead_008c22058272684f el op0 op1 CRn op2 CRm)" + by (unfold OSDTRTX_EL1_SysRegRead_008c22058272684f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_OSECCR_EL1_SysRegRead_264ab12a32fecc30[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (OSECCR_EL1_SysRegRead_264ab12a32fecc30 el op0 op1 CRn op2 CRm)" + by (unfold OSECCR_EL1_SysRegRead_264ab12a32fecc30_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_OSLSR_EL1_SysRegRead_d99062033a35ccbf[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (OSLSR_EL1_SysRegRead_d99062033a35ccbf el op0 op1 CRn op2 CRm)" + by (unfold OSLSR_EL1_SysRegRead_d99062033a35ccbf_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PAR_EL1_SysRegRead_888e7c84935ebac7[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PAR_EL1_SysRegRead_888e7c84935ebac7 el op0 op1 CRn op2 CRm)" + by (unfold PAR_EL1_SysRegRead_888e7c84935ebac7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMBIDR_EL1_SysRegRead_306c3f68e41521a3[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMBIDR_EL1_SysRegRead_306c3f68e41521a3 el op0 op1 CRn op2 CRm)" + by (unfold PMBIDR_EL1_SysRegRead_306c3f68e41521a3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMBLIMITR_EL1_SysRegRead_b7c18938ab0566dc[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMBLIMITR_EL1_SysRegRead_b7c18938ab0566dc el op0 op1 CRn op2 CRm)" + by (unfold PMBLIMITR_EL1_SysRegRead_b7c18938ab0566dc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMBPTR_EL1_SysRegRead_fb82e1b6e480bd0a[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMBPTR_EL1_SysRegRead_fb82e1b6e480bd0a el op0 op1 CRn op2 CRm)" + by (unfold PMBPTR_EL1_SysRegRead_fb82e1b6e480bd0a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMBSR_EL1_SysRegRead_87628bec330b9f53[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMBSR_EL1_SysRegRead_87628bec330b9f53 el op0 op1 CRn op2 CRm)" + by (unfold PMBSR_EL1_SysRegRead_87628bec330b9f53_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMCCFILTR_EL0_SysRegRead_349918c2333bfc1e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMCCFILTR_EL0_SysRegRead_349918c2333bfc1e el op0 op1 CRn op2 CRm)" + by (unfold PMCCFILTR_EL0_SysRegRead_349918c2333bfc1e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMCCNTR_EL0_SysRegRead_45fc425eff298404[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMCCNTR_EL0_SysRegRead_45fc425eff298404 el op0 op1 CRn op2 CRm)" + by (unfold PMCCNTR_EL0_SysRegRead_45fc425eff298404_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMCEID0_EL0_SysRegRead_1364a10a0c913d82[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMCEID0_EL0_SysRegRead_1364a10a0c913d82 el op0 op1 CRn op2 CRm)" + by (unfold PMCEID0_EL0_SysRegRead_1364a10a0c913d82_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMCEID1_EL0_SysRegRead_2db7a3b96735d30a[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMCEID1_EL0_SysRegRead_2db7a3b96735d30a el op0 op1 CRn op2 CRm)" + by (unfold PMCEID1_EL0_SysRegRead_2db7a3b96735d30a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMCNTENCLR_EL0_SysRegRead_5ac431b885c9c5e4[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMCNTENCLR_EL0_SysRegRead_5ac431b885c9c5e4 el op0 op1 CRn op2 CRm)" + by (unfold PMCNTENCLR_EL0_SysRegRead_5ac431b885c9c5e4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMCNTENSET_EL0_SysRegRead_848c3aa603193fb7[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMCNTENSET_EL0_SysRegRead_848c3aa603193fb7 el op0 op1 CRn op2 CRm)" + by (unfold PMCNTENSET_EL0_SysRegRead_848c3aa603193fb7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMCR_EL0_SysRegRead_9a03e454327a1718[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMCR_EL0_SysRegRead_9a03e454327a1718 el op0 op1 CRn op2 CRm)" + by (unfold PMCR_EL0_SysRegRead_9a03e454327a1718_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMEVCNTR_EL0_SysRegRead_e0380ad70bc25a0c[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMEVCNTR_EL0_SysRegRead_e0380ad70bc25a0c el op0 op1 CRn op2 CRm)" + by (unfold PMEVCNTR_EL0_SysRegRead_e0380ad70bc25a0c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMEVTYPER_EL0_SysRegRead_b05172ff9d10dad4[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMEVTYPER_EL0_SysRegRead_b05172ff9d10dad4 el op0 op1 CRn op2 CRm)" + by (unfold PMEVTYPER_EL0_SysRegRead_b05172ff9d10dad4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMINTENCLR_EL1_SysRegRead_43b8f4d9b40b2620[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMINTENCLR_EL1_SysRegRead_43b8f4d9b40b2620 el op0 op1 CRn op2 CRm)" + by (unfold PMINTENCLR_EL1_SysRegRead_43b8f4d9b40b2620_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMINTENSET_EL1_SysRegRead_a3d4464c2051ff23[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMINTENSET_EL1_SysRegRead_a3d4464c2051ff23 el op0 op1 CRn op2 CRm)" + by (unfold PMINTENSET_EL1_SysRegRead_a3d4464c2051ff23_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMOVSCLR_EL0_SysRegRead_300e5dfb491e58fa[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMOVSCLR_EL0_SysRegRead_300e5dfb491e58fa el op0 op1 CRn op2 CRm)" + by (unfold PMOVSCLR_EL0_SysRegRead_300e5dfb491e58fa_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMOVSSET_EL0_SysRegRead_e3c0657a6c8b11c8[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMOVSSET_EL0_SysRegRead_e3c0657a6c8b11c8 el op0 op1 CRn op2 CRm)" + by (unfold PMOVSSET_EL0_SysRegRead_e3c0657a6c8b11c8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSCR_EL12_SysRegRead_624c386ea3cce853[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMSCR_EL12_SysRegRead_624c386ea3cce853 el op0 op1 CRn op2 CRm)" + by (unfold PMSCR_EL12_SysRegRead_624c386ea3cce853_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSCR_EL1_SysRegRead_39ffc554ca37b155[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMSCR_EL1_SysRegRead_39ffc554ca37b155 el op0 op1 CRn op2 CRm)" + by (unfold PMSCR_EL1_SysRegRead_39ffc554ca37b155_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSCR_EL2_SysRegRead_11330bd80566814a[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMSCR_EL2_SysRegRead_11330bd80566814a el op0 op1 CRn op2 CRm)" + by (unfold PMSCR_EL2_SysRegRead_11330bd80566814a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSELR_EL0_SysRegRead_540b592cb875b32f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMSELR_EL0_SysRegRead_540b592cb875b32f el op0 op1 CRn op2 CRm)" + by (unfold PMSELR_EL0_SysRegRead_540b592cb875b32f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSEVFR_EL1_SysRegRead_9e9a58f73d629d59[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMSEVFR_EL1_SysRegRead_9e9a58f73d629d59 el op0 op1 CRn op2 CRm)" + by (unfold PMSEVFR_EL1_SysRegRead_9e9a58f73d629d59_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSFCR_EL1_SysRegRead_30b07ff27088a488[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMSFCR_EL1_SysRegRead_30b07ff27088a488 el op0 op1 CRn op2 CRm)" + by (unfold PMSFCR_EL1_SysRegRead_30b07ff27088a488_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSICR_EL1_SysRegRead_1b4bf4bb07470e4c[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMSICR_EL1_SysRegRead_1b4bf4bb07470e4c el op0 op1 CRn op2 CRm)" + by (unfold PMSICR_EL1_SysRegRead_1b4bf4bb07470e4c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSIDR_EL1_SysRegRead_062cecff79d24b4d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMSIDR_EL1_SysRegRead_062cecff79d24b4d el op0 op1 CRn op2 CRm)" + by (unfold PMSIDR_EL1_SysRegRead_062cecff79d24b4d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSIRR_EL1_SysRegRead_b565329ce30ac491[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMSIRR_EL1_SysRegRead_b565329ce30ac491 el op0 op1 CRn op2 CRm)" + by (unfold PMSIRR_EL1_SysRegRead_b565329ce30ac491_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSLATFR_EL1_SysRegRead_f82542fec2521a41[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMSLATFR_EL1_SysRegRead_f82542fec2521a41 el op0 op1 CRn op2 CRm)" + by (unfold PMSLATFR_EL1_SysRegRead_f82542fec2521a41_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMUSERENR_EL0_SysRegRead_7efca1a4be376eb7[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMUSERENR_EL0_SysRegRead_7efca1a4be376eb7 el op0 op1 CRn op2 CRm)" + by (unfold PMUSERENR_EL0_SysRegRead_7efca1a4be376eb7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMXEVCNTR_EL0_SysRegRead_193921f886161922[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMXEVCNTR_EL0_SysRegRead_193921f886161922 el op0 op1 CRn op2 CRm)" + by (unfold PMXEVCNTR_EL0_SysRegRead_193921f886161922_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMXEVTYPER_EL0_SysRegRead_a34d7cb6f32074c5[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (PMXEVTYPER_EL0_SysRegRead_a34d7cb6f32074c5 el op0 op1 CRn op2 CRm)" + by (unfold PMXEVTYPER_EL0_SysRegRead_a34d7cb6f32074c5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_REVIDR_EL1_SysRegRead_06ac796f098a1e84[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (REVIDR_EL1_SysRegRead_06ac796f098a1e84 el op0 op1 CRn op2 CRm)" + by (unfold REVIDR_EL1_SysRegRead_06ac796f098a1e84_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RMR_EL1_SysRegRead_69f4933c1a574580[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RMR_EL1_SysRegRead_69f4933c1a574580 el op0 op1 CRn op2 CRm)" + by (unfold RMR_EL1_SysRegRead_69f4933c1a574580_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RMR_EL2_SysRegRead_75749340e0828f00[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RMR_EL2_SysRegRead_75749340e0828f00 el op0 op1 CRn op2 CRm)" + by (unfold RMR_EL2_SysRegRead_75749340e0828f00_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RMR_EL3_SysRegRead_fa5f18c3b20f8894[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RMR_EL3_SysRegRead_fa5f18c3b20f8894 el op0 op1 CRn op2 CRm)" + by (unfold RMR_EL3_SysRegRead_fa5f18c3b20f8894_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RSP_EL0_SysRegRead_b64c62bd96d973e3[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RSP_EL0_SysRegRead_b64c62bd96d973e3 el op0 op1 CRn op2 CRm)" + by (unfold RSP_EL0_SysRegRead_b64c62bd96d973e3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RTPIDR_EL0_SysRegRead_0ce5a74dba936523[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RTPIDR_EL0_SysRegRead_0ce5a74dba936523 el op0 op1 CRn op2 CRm)" + by (unfold RTPIDR_EL0_SysRegRead_0ce5a74dba936523_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RVBAR_EL1_SysRegRead_48a958c9250293d1[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RVBAR_EL1_SysRegRead_48a958c9250293d1 el op0 op1 CRn op2 CRm)" + by (unfold RVBAR_EL1_SysRegRead_48a958c9250293d1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RVBAR_EL2_SysRegRead_2fb802203150f4cc[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RVBAR_EL2_SysRegRead_2fb802203150f4cc el op0 op1 CRn op2 CRm)" + by (unfold RVBAR_EL2_SysRegRead_2fb802203150f4cc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RVBAR_EL3_SysRegRead_000d1ea4b77ffa21[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RVBAR_EL3_SysRegRead_000d1ea4b77ffa21 el op0 op1 CRn op2 CRm)" + by (unfold RVBAR_EL3_SysRegRead_000d1ea4b77ffa21_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S3_op1_CCn_CCm_op2_SysRegRead_d72a7245384bbc0e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (S3_op1_CCn_CCm_op2_SysRegRead_d72a7245384bbc0e el op0 op1 CRn op2 CRm)" + by (unfold S3_op1_CCn_CCm_op2_SysRegRead_d72a7245384bbc0e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCR_EL3_SysRegRead_082a69b26890132d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (SCR_EL3_SysRegRead_082a69b26890132d el op0 op1 CRn op2 CRm)" + by (unfold SCR_EL3_SysRegRead_082a69b26890132d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCTLR_EL12_SysRegRead_81ba00bca4ce39dc[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (SCTLR_EL12_SysRegRead_81ba00bca4ce39dc el op0 op1 CRn op2 CRm)" + by (unfold SCTLR_EL12_SysRegRead_81ba00bca4ce39dc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCTLR_EL1_SysRegRead_cc5fb072b0cb85eb[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (SCTLR_EL1_SysRegRead_cc5fb072b0cb85eb el op0 op1 CRn op2 CRm)" + by (unfold SCTLR_EL1_SysRegRead_cc5fb072b0cb85eb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCTLR_EL2_SysRegRead_3cc208f3abf97e34[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (SCTLR_EL2_SysRegRead_3cc208f3abf97e34 el op0 op1 CRn op2 CRm)" + by (unfold SCTLR_EL2_SysRegRead_3cc208f3abf97e34_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCTLR_EL3_SysRegRead_9c537c9c01007c3e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (SCTLR_EL3_SysRegRead_9c537c9c01007c3e el op0 op1 CRn op2 CRm)" + by (unfold SCTLR_EL3_SysRegRead_9c537c9c01007c3e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCXTNUM_EL0_SysRegRead_ee5b769fc7f044cc[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (SCXTNUM_EL0_SysRegRead_ee5b769fc7f044cc el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL0_SysRegRead_ee5b769fc7f044cc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCXTNUM_EL12_SysRegRead_d31f345333a78d48[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (SCXTNUM_EL12_SysRegRead_d31f345333a78d48 el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL12_SysRegRead_d31f345333a78d48_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCXTNUM_EL1_SysRegRead_dd27b7ad05ded1ab[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (SCXTNUM_EL1_SysRegRead_dd27b7ad05ded1ab el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL1_SysRegRead_dd27b7ad05ded1ab_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCXTNUM_EL2_SysRegRead_421b17f19f5fdd2a[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (SCXTNUM_EL2_SysRegRead_421b17f19f5fdd2a el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL2_SysRegRead_421b17f19f5fdd2a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCXTNUM_EL3_SysRegRead_5f15a3b4da1bd4bb[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (SCXTNUM_EL3_SysRegRead_5f15a3b4da1bd4bb el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL3_SysRegRead_5f15a3b4da1bd4bb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SDER32_EL3_SysRegRead_e21f871563c7e34e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (SDER32_EL3_SysRegRead_e21f871563c7e34e el op0 op1 CRn op2 CRm)" + by (unfold SDER32_EL3_SysRegRead_e21f871563c7e34e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TCR_EL12_SysRegRead_cefcc3f131a70a7f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TCR_EL12_SysRegRead_cefcc3f131a70a7f el op0 op1 CRn op2 CRm)" + by (unfold TCR_EL12_SysRegRead_cefcc3f131a70a7f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TCR_EL1_SysRegRead_fbe255888fba9865[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TCR_EL1_SysRegRead_fbe255888fba9865 el op0 op1 CRn op2 CRm)" + by (unfold TCR_EL1_SysRegRead_fbe255888fba9865_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TCR_EL2_SysRegRead_3467687df9c2aec1[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TCR_EL2_SysRegRead_3467687df9c2aec1 el op0 op1 CRn op2 CRm)" + by (unfold TCR_EL2_SysRegRead_3467687df9c2aec1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TCR_EL3_SysRegRead_7da88d4a232f9451[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TCR_EL3_SysRegRead_7da88d4a232f9451 el op0 op1 CRn op2 CRm)" + by (unfold TCR_EL3_SysRegRead_7da88d4a232f9451_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR0_EL12_SysRegRead_73f9bd4d027badee[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TTBR0_EL12_SysRegRead_73f9bd4d027badee el op0 op1 CRn op2 CRm)" + by (unfold TTBR0_EL12_SysRegRead_73f9bd4d027badee_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR0_EL1_SysRegRead_2e8a6c25b2e4759a[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TTBR0_EL1_SysRegRead_2e8a6c25b2e4759a el op0 op1 CRn op2 CRm)" + by (unfold TTBR0_EL1_SysRegRead_2e8a6c25b2e4759a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR0_EL2_SysRegRead_8d4de9e080477354[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TTBR0_EL2_SysRegRead_8d4de9e080477354 el op0 op1 CRn op2 CRm)" + by (unfold TTBR0_EL2_SysRegRead_8d4de9e080477354_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR0_EL3_SysRegRead_a46e35edfe45a273[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TTBR0_EL3_SysRegRead_a46e35edfe45a273 el op0 op1 CRn op2 CRm)" + by (unfold TTBR0_EL3_SysRegRead_a46e35edfe45a273_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR1_EL12_SysRegRead_bfbc2899eb278d2b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TTBR1_EL12_SysRegRead_bfbc2899eb278d2b el op0 op1 CRn op2 CRm)" + by (unfold TTBR1_EL12_SysRegRead_bfbc2899eb278d2b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR1_EL1_SysRegRead_2cb2fb59089165c5[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TTBR1_EL1_SysRegRead_2cb2fb59089165c5 el op0 op1 CRn op2 CRm)" + by (unfold TTBR1_EL1_SysRegRead_2cb2fb59089165c5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR1_EL2_SysRegRead_08cd28a9b17bc317[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TTBR1_EL2_SysRegRead_08cd28a9b17bc317 el op0 op1 CRn op2 CRm)" + by (unfold TTBR1_EL2_SysRegRead_08cd28a9b17bc317_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VBAR_EL12_SysRegRead_2ad4e02fbe99cf3d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VBAR_EL12_SysRegRead_2ad4e02fbe99cf3d el op0 op1 CRn op2 CRm)" + by (unfold VBAR_EL12_SysRegRead_2ad4e02fbe99cf3d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VBAR_EL1_SysRegRead_4d14cb3b6fe16ab6[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VBAR_EL1_SysRegRead_4d14cb3b6fe16ab6 el op0 op1 CRn op2 CRm)" + by (unfold VBAR_EL1_SysRegRead_4d14cb3b6fe16ab6_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VBAR_EL2_SysRegRead_1f6b3c94ccfecacf[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VBAR_EL2_SysRegRead_1f6b3c94ccfecacf el op0 op1 CRn op2 CRm)" + by (unfold VBAR_EL2_SysRegRead_1f6b3c94ccfecacf_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VBAR_EL3_SysRegRead_32f42cb574998654[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VBAR_EL3_SysRegRead_32f42cb574998654 el op0 op1 CRn op2 CRm)" + by (unfold VBAR_EL3_SysRegRead_32f42cb574998654_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VDISR_EL2_SysRegRead_14dff4ad4ae8c3a2[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VDISR_EL2_SysRegRead_14dff4ad4ae8c3a2 el op0 op1 CRn op2 CRm)" + by (unfold VDISR_EL2_SysRegRead_14dff4ad4ae8c3a2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VMPIDR_EL2_SysRegRead_49b7c13dd1b0804c[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VMPIDR_EL2_SysRegRead_49b7c13dd1b0804c el op0 op1 CRn op2 CRm)" + by (unfold VMPIDR_EL2_SysRegRead_49b7c13dd1b0804c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VPIDR_EL2_SysRegRead_f6520cd6a1f62bd8[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VPIDR_EL2_SysRegRead_f6520cd6a1f62bd8 el op0 op1 CRn op2 CRm)" + by (unfold VPIDR_EL2_SysRegRead_f6520cd6a1f62bd8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VSESR_EL2_SysRegRead_401c063e57574698[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VSESR_EL2_SysRegRead_401c063e57574698 el op0 op1 CRn op2 CRm)" + by (unfold VSESR_EL2_SysRegRead_401c063e57574698_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VTCR_EL2_SysRegRead_5c8ea980dc5cc1d1[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VTCR_EL2_SysRegRead_5c8ea980dc5cc1d1 el op0 op1 CRn op2 CRm)" + by (unfold VTCR_EL2_SysRegRead_5c8ea980dc5cc1d1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VTTBR_EL2_SysRegRead_2fbbdccc9485564d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VTTBR_EL2_SysRegRead_2fbbdccc9485564d el op0 op1 CRn op2 CRm)" + by (unfold VTTBR_EL2_SysRegRead_2fbbdccc9485564d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_AutoGen_SysRegRead[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_AutoGen_SysRegRead el op0 op1 CRn op2 CRm)" + by (unfold AArch64_AutoGen_SysRegRead_def bind_assoc, no_reg_writes_toI intro: runs_no_reg_writes_to_if_no_asm) + +lemma runs_no_reg_writes_to_AArch64_SysRegRead[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_SysRegRead op0 op1 crn crm op2)" + by (unfold AArch64_SysRegRead_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34 el op0 op1 CRn op2 CRm)" + by (unfold CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CDLR_EL0_CapSysRegRead_619c852c71c0978d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CDLR_EL0_CapSysRegRead_619c852c71c0978d el op0 op1 CRn op2 CRm)" + by (unfold CDLR_EL0_CapSysRegRead_619c852c71c0978d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CELR_EL12_CapSysRegRead_4bf271777fe55d1c[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CELR_EL12_CapSysRegRead_4bf271777fe55d1c el op0 op1 CRn op2 CRm)" + by (unfold CELR_EL12_CapSysRegRead_4bf271777fe55d1c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CELR_EL1_CapSysRegRead_da9869d2314a30d5[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CELR_EL1_CapSysRegRead_da9869d2314a30d5 el op0 op1 CRn op2 CRm)" + by (unfold CELR_EL1_CapSysRegRead_da9869d2314a30d5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CELR_EL2_CapSysRegRead_a9e9661da428a6d4[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CELR_EL2_CapSysRegRead_a9e9661da428a6d4 el op0 op1 CRn op2 CRm)" + by (unfold CELR_EL2_CapSysRegRead_a9e9661da428a6d4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CELR_EL3_CapSysRegRead_d0424a232c45967e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CELR_EL3_CapSysRegRead_d0424a232c45967e el op0 op1 CRn op2 CRm)" + by (unfold CELR_EL3_CapSysRegRead_d0424a232c45967e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CID_EL0_CapSysRegRead_d560f6b1104266f1[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CID_EL0_CapSysRegRead_d560f6b1104266f1 el op0 op1 CRn op2 CRm)" + by (unfold CID_EL0_CapSysRegRead_d560f6b1104266f1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CSP_EL0_CapSysRegRead_e5b1ba121f8be4da[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CSP_EL0_CapSysRegRead_e5b1ba121f8be4da el op0 op1 CRn op2 CRm)" + by (unfold CSP_EL0_CapSysRegRead_e5b1ba121f8be4da_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb el op0 op1 CRn op2 CRm)" + by (unfold CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CSP_EL2_CapSysRegRead_9b50d2f92d5520da[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CSP_EL2_CapSysRegRead_9b50d2f92d5520da el op0 op1 CRn op2 CRm)" + by (unfold CSP_EL2_CapSysRegRead_9b50d2f92d5520da_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc el op0 op1 CRn op2 CRm)" + by (unfold CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CTPIDR_EL0_CapSysRegRead_84b933ea55a77369[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CTPIDR_EL0_CapSysRegRead_84b933ea55a77369 el op0 op1 CRn op2 CRm)" + by (unfold CTPIDR_EL0_CapSysRegRead_84b933ea55a77369_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CTPIDR_EL1_CapSysRegRead_016308c12b886084[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CTPIDR_EL1_CapSysRegRead_016308c12b886084 el op0 op1 CRn op2 CRm)" + by (unfold CTPIDR_EL1_CapSysRegRead_016308c12b886084_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544 el op0 op1 CRn op2 CRm)" + by (unfold CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449 el op0 op1 CRn op2 CRm)" + by (unfold CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CVBAR_EL12_CapSysRegRead_845c94ac498ff593[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CVBAR_EL12_CapSysRegRead_845c94ac498ff593 el op0 op1 CRn op2 CRm)" + by (unfold CVBAR_EL12_CapSysRegRead_845c94ac498ff593_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CVBAR_EL1_CapSysRegRead_c42109445741a0d0[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CVBAR_EL1_CapSysRegRead_c42109445741a0d0 el op0 op1 CRn op2 CRm)" + by (unfold CVBAR_EL1_CapSysRegRead_c42109445741a0d0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CVBAR_EL2_CapSysRegRead_537232bbd7d69e00[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CVBAR_EL2_CapSysRegRead_537232bbd7d69e00 el op0 op1 CRn op2 CRm)" + by (unfold CVBAR_EL2_CapSysRegRead_537232bbd7d69e00_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1 el op0 op1 CRn op2 CRm)" + by (unfold CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DDC_CapSysRegRead_eabc4ea34a10a962[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DDC_CapSysRegRead_eabc4ea34a10a962 el op0 op1 CRn op2 CRm)" + by (unfold DDC_CapSysRegRead_eabc4ea34a10a962_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DDC_EL0_CapSysRegRead_e02bc676dce7fb51[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DDC_EL0_CapSysRegRead_e02bc676dce7fb51 el op0 op1 CRn op2 CRm)" + by (unfold DDC_EL0_CapSysRegRead_e02bc676dce7fb51_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DDC_EL1_CapSysRegRead_08f46354e9afc01e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DDC_EL1_CapSysRegRead_08f46354e9afc01e el op0 op1 CRn op2 CRm)" + by (unfold DDC_EL1_CapSysRegRead_08f46354e9afc01e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DDC_EL2_CapSysRegRead_6d2409222a719403[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DDC_EL2_CapSysRegRead_6d2409222a719403 el op0 op1 CRn op2 CRm)" + by (unfold DDC_EL2_CapSysRegRead_6d2409222a719403_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RCSP_EL0_CapSysRegRead_6a9b29b9027548c3[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RCSP_EL0_CapSysRegRead_6a9b29b9027548c3 el op0 op1 CRn op2 CRm)" + by (unfold RCSP_EL0_CapSysRegRead_6a9b29b9027548c3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7 el op0 op1 CRn op2 CRm)" + by (unfold RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RDDC_EL0_CapSysRegRead_c188e736aa7b9beb[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RDDC_EL0_CapSysRegRead_c188e736aa7b9beb el op0 op1 CRn op2 CRm)" + by (unfold RDDC_EL0_CapSysRegRead_c188e736aa7b9beb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_AutoGen_CapSysRegRead[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_AutoGen_CapSysRegRead el op0 op1 CRn op2 CRm)" + by (unfold AArch64_AutoGen_CapSysRegRead_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_CapSysRegRead[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_CapSysRegRead op0 op1 crn crm op2)" + by (unfold AArch64_CapSysRegRead_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ACTLR_EL1_SysRegWrite_338051dbe9bdf650[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ACTLR_EL1_SysRegWrite_338051dbe9bdf650 el op0 op1 CRn op2 CRm val_name)" + by (unfold ACTLR_EL1_SysRegWrite_338051dbe9bdf650_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ACTLR_EL2_SysRegWrite_416ec7c6fadd122d[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ACTLR_EL2_SysRegWrite_416ec7c6fadd122d el op0 op1 CRn op2 CRm val_name)" + by (unfold ACTLR_EL2_SysRegWrite_416ec7c6fadd122d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ACTLR_EL3_SysRegWrite_c797d5a80525afa4[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ACTLR_EL3_SysRegWrite_c797d5a80525afa4 el op0 op1 CRn op2 CRm val_name)" + by (unfold ACTLR_EL3_SysRegWrite_c797d5a80525afa4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR0_EL12_SysRegWrite_9fafb4f6dbddd904[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AFSR0_EL12_SysRegWrite_9fafb4f6dbddd904 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR0_EL12_SysRegWrite_9fafb4f6dbddd904_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR0_EL1_SysRegWrite_04474930979e1c86[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AFSR0_EL1_SysRegWrite_04474930979e1c86 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR0_EL1_SysRegWrite_04474930979e1c86_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR0_EL2_SysRegWrite_2f9da4789f5b4073[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AFSR0_EL2_SysRegWrite_2f9da4789f5b4073 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR0_EL2_SysRegWrite_2f9da4789f5b4073_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR0_EL3_SysRegWrite_e615501306210a25[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AFSR0_EL3_SysRegWrite_e615501306210a25 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR0_EL3_SysRegWrite_e615501306210a25_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR1_EL12_SysRegWrite_9dbf207cccd92d9d[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AFSR1_EL12_SysRegWrite_9dbf207cccd92d9d el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR1_EL12_SysRegWrite_9dbf207cccd92d9d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR1_EL1_SysRegWrite_6690138c9fdd136c[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AFSR1_EL1_SysRegWrite_6690138c9fdd136c el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR1_EL1_SysRegWrite_6690138c9fdd136c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR1_EL2_SysRegWrite_c0ebc4cc65472544[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AFSR1_EL2_SysRegWrite_c0ebc4cc65472544 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR1_EL2_SysRegWrite_c0ebc4cc65472544_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AFSR1_EL3_SysRegWrite_d776cc264803f49e[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AFSR1_EL3_SysRegWrite_d776cc264803f49e el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR1_EL3_SysRegWrite_d776cc264803f49e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AMAIR_EL12_SysRegWrite_9c44aba2de7c2ff8[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AMAIR_EL12_SysRegWrite_9c44aba2de7c2ff8 el op0 op1 CRn op2 CRm val_name)" + by (unfold AMAIR_EL12_SysRegWrite_9c44aba2de7c2ff8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AMAIR_EL1_SysRegWrite_0d9c3d92d9a71703[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AMAIR_EL1_SysRegWrite_0d9c3d92d9a71703 el op0 op1 CRn op2 CRm val_name)" + by (unfold AMAIR_EL1_SysRegWrite_0d9c3d92d9a71703_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AMAIR_EL2_SysRegWrite_9345da970d78b298[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AMAIR_EL2_SysRegWrite_9345da970d78b298 el op0 op1 CRn op2 CRm val_name)" + by (unfold AMAIR_EL2_SysRegWrite_9345da970d78b298_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AMAIR_EL3_SysRegWrite_622c473bfedac80a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AMAIR_EL3_SysRegWrite_622c473bfedac80a el op0 op1 CRn op2 CRm val_name)" + by (unfold AMAIR_EL3_SysRegWrite_622c473bfedac80a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CCTLR_EL0_SysRegWrite_a4d8c57cb436292b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CCTLR_EL0_SysRegWrite_a4d8c57cb436292b el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL0_SysRegWrite_a4d8c57cb436292b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CCTLR_EL12_SysRegWrite_c7d9d6463096d910[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CCTLR_EL12_SysRegWrite_c7d9d6463096d910 el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL12_SysRegWrite_c7d9d6463096d910_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CCTLR_EL1_SysRegWrite_dc20ad2a867ac9bf[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CCTLR_EL1_SysRegWrite_dc20ad2a867ac9bf el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL1_SysRegWrite_dc20ad2a867ac9bf_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CCTLR_EL2_SysRegWrite_65620c8ccb1113a5[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CCTLR_EL2_SysRegWrite_65620c8ccb1113a5 el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL2_SysRegWrite_65620c8ccb1113a5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CCTLR_EL3_SysRegWrite_f5e936c8846e6fc7[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CCTLR_EL3_SysRegWrite_f5e936c8846e6fc7 el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL3_SysRegWrite_f5e936c8846e6fc7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CHCR_EL2_SysRegWrite_dadda8ecf053e448[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CHCR_EL2_SysRegWrite_dadda8ecf053e448 el op0 op1 CRn op2 CRm val_name)" + by (unfold CHCR_EL2_SysRegWrite_dadda8ecf053e448_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTFRQ_EL0_SysRegWrite_0fac77f077759456[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTFRQ_EL0_SysRegWrite_0fac77f077759456 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTFRQ_EL0_SysRegWrite_0fac77f077759456_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHCTL_EL2_SysRegWrite_eb0cbec9f9398e0e[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTHCTL_EL2_SysRegWrite_eb0cbec9f9398e0e el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHCTL_EL2_SysRegWrite_eb0cbec9f9398e0e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHP_CTL_EL2_SysRegWrite_92034fc54290a7b8[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTHP_CTL_EL2_SysRegWrite_92034fc54290a7b8 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHP_CTL_EL2_SysRegWrite_92034fc54290a7b8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHP_CVAL_EL2_SysRegWrite_36de219faded7cbc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTHP_CVAL_EL2_SysRegWrite_36de219faded7cbc el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHP_CVAL_EL2_SysRegWrite_36de219faded7cbc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHP_TVAL_EL2_SysRegWrite_877bbf4f78f810b9[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTHP_TVAL_EL2_SysRegWrite_877bbf4f78f810b9 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHP_TVAL_EL2_SysRegWrite_877bbf4f78f810b9_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHV_CTL_EL2_SysRegWrite_ecc786a588fc8ab9[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTHV_CTL_EL2_SysRegWrite_ecc786a588fc8ab9 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHV_CTL_EL2_SysRegWrite_ecc786a588fc8ab9_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHV_CVAL_EL2_SysRegWrite_b3d7c631e2b3eaab[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTHV_CVAL_EL2_SysRegWrite_b3d7c631e2b3eaab el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHV_CVAL_EL2_SysRegWrite_b3d7c631e2b3eaab_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTHV_TVAL_EL2_SysRegWrite_e215d12d330397f1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTHV_TVAL_EL2_SysRegWrite_e215d12d330397f1 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHV_TVAL_EL2_SysRegWrite_e215d12d330397f1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTKCTL_EL12_SysRegWrite_518123f17a6402e4[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTKCTL_EL12_SysRegWrite_518123f17a6402e4 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTKCTL_EL12_SysRegWrite_518123f17a6402e4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTKCTL_EL1_SysRegWrite_9a7be69aa33bb9c2[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTKCTL_EL1_SysRegWrite_9a7be69aa33bb9c2 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTKCTL_EL1_SysRegWrite_9a7be69aa33bb9c2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTPS_CTL_EL1_SysRegWrite_a0625fd9f7b035a8[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTPS_CTL_EL1_SysRegWrite_a0625fd9f7b035a8 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTPS_CTL_EL1_SysRegWrite_a0625fd9f7b035a8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTPS_CVAL_EL1_SysRegWrite_f09243080b7c260d[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTPS_CVAL_EL1_SysRegWrite_f09243080b7c260d el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTPS_CVAL_EL1_SysRegWrite_f09243080b7c260d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTPS_TVAL_EL1_SysRegWrite_a9b16e60037fa746[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTPS_TVAL_EL1_SysRegWrite_a9b16e60037fa746 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTPS_TVAL_EL1_SysRegWrite_a9b16e60037fa746_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTP_CTL_EL02_SysRegWrite_99a9da3e2454714e[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTP_CTL_EL02_SysRegWrite_99a9da3e2454714e el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_CTL_EL02_SysRegWrite_99a9da3e2454714e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTP_CTL_EL0_SysRegWrite_137f81090c1357e6[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTP_CTL_EL0_SysRegWrite_137f81090c1357e6 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_CTL_EL0_SysRegWrite_137f81090c1357e6_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTP_CVAL_EL02_SysRegWrite_2b3e9ccfce186a4f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTP_CVAL_EL02_SysRegWrite_2b3e9ccfce186a4f el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_CVAL_EL02_SysRegWrite_2b3e9ccfce186a4f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTP_CVAL_EL0_SysRegWrite_d54c08ee0cf9aaf7[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTP_CVAL_EL0_SysRegWrite_d54c08ee0cf9aaf7 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_CVAL_EL0_SysRegWrite_d54c08ee0cf9aaf7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTP_TVAL_EL02_SysRegWrite_caa9f2aa73cb6b96[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTP_TVAL_EL02_SysRegWrite_caa9f2aa73cb6b96 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_TVAL_EL02_SysRegWrite_caa9f2aa73cb6b96_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTP_TVAL_EL0_SysRegWrite_d7441eec23c3d524[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTP_TVAL_EL0_SysRegWrite_d7441eec23c3d524 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_TVAL_EL0_SysRegWrite_d7441eec23c3d524_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTVOFF_EL2_SysRegWrite_621ada4cfda60bcb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTVOFF_EL2_SysRegWrite_621ada4cfda60bcb el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTVOFF_EL2_SysRegWrite_621ada4cfda60bcb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTV_CTL_EL02_SysRegWrite_d6cac9cc52dd8fec[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTV_CTL_EL02_SysRegWrite_d6cac9cc52dd8fec el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_CTL_EL02_SysRegWrite_d6cac9cc52dd8fec_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTV_CTL_EL0_SysRegWrite_e9fd22bae4b06064[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTV_CTL_EL0_SysRegWrite_e9fd22bae4b06064 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_CTL_EL0_SysRegWrite_e9fd22bae4b06064_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTV_CVAL_EL02_SysRegWrite_7548964ed28b5abb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTV_CVAL_EL02_SysRegWrite_7548964ed28b5abb el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_CVAL_EL02_SysRegWrite_7548964ed28b5abb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTV_CVAL_EL0_SysRegWrite_f237c5c94ec92951[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTV_CVAL_EL0_SysRegWrite_f237c5c94ec92951 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_CVAL_EL0_SysRegWrite_f237c5c94ec92951_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTV_TVAL_EL02_SysRegWrite_dc97f79a5f74078f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTV_TVAL_EL02_SysRegWrite_dc97f79a5f74078f el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_TVAL_EL02_SysRegWrite_dc97f79a5f74078f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CNTV_TVAL_EL0_SysRegWrite_903191acca729cda[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CNTV_TVAL_EL0_SysRegWrite_903191acca729cda el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_TVAL_EL0_SysRegWrite_903191acca729cda_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CONTEXTIDR_EL12_SysRegWrite_33154953ae1b01d5[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CONTEXTIDR_EL12_SysRegWrite_33154953ae1b01d5 el op0 op1 CRn op2 CRm val_name)" + by (unfold CONTEXTIDR_EL12_SysRegWrite_33154953ae1b01d5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CONTEXTIDR_EL1_SysRegWrite_5408e4e72af4e23d[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CONTEXTIDR_EL1_SysRegWrite_5408e4e72af4e23d el op0 op1 CRn op2 CRm val_name)" + by (unfold CONTEXTIDR_EL1_SysRegWrite_5408e4e72af4e23d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CONTEXTIDR_EL2_SysRegWrite_27187b6dc7c5a748[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CONTEXTIDR_EL2_SysRegWrite_27187b6dc7c5a748 el op0 op1 CRn op2 CRm val_name)" + by (unfold CONTEXTIDR_EL2_SysRegWrite_27187b6dc7c5a748_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CPACR_EL12_SysRegWrite_637092a999939f8b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CPACR_EL12_SysRegWrite_637092a999939f8b el op0 op1 CRn op2 CRm val_name)" + by (unfold CPACR_EL12_SysRegWrite_637092a999939f8b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CPACR_EL1_SysRegWrite_00878a1f3e87823c[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CPACR_EL1_SysRegWrite_00878a1f3e87823c el op0 op1 CRn op2 CRm val_name)" + by (unfold CPACR_EL1_SysRegWrite_00878a1f3e87823c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CPTR_EL2_SysRegWrite_5a082f460b1b2308[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CPTR_EL2_SysRegWrite_5a082f460b1b2308 el op0 op1 CRn op2 CRm val_name)" + by (unfold CPTR_EL2_SysRegWrite_5a082f460b1b2308_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CPTR_EL3_SysRegWrite_879d4b1bad53408b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CPTR_EL3_SysRegWrite_879d4b1bad53408b el op0 op1 CRn op2 CRm val_name)" + by (unfold CPTR_EL3_SysRegWrite_879d4b1bad53408b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CSCR_EL3_SysRegWrite_22b95c83b04d6c91[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CSCR_EL3_SysRegWrite_22b95c83b04d6c91 el op0 op1 CRn op2 CRm val_name)" + by (unfold CSCR_EL3_SysRegWrite_22b95c83b04d6c91_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CSSELR_EL1_SysRegWrite_1f9e1e0300c8783c[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CSSELR_EL1_SysRegWrite_1f9e1e0300c8783c el op0 op1 CRn op2 CRm val_name)" + by (unfold CSSELR_EL1_SysRegWrite_1f9e1e0300c8783c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DACR32_EL2_SysRegWrite_a8bad0131817f121[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DACR32_EL2_SysRegWrite_a8bad0131817f121 el op0 op1 CRn op2 CRm val_name)" + by (unfold DACR32_EL2_SysRegWrite_a8bad0131817f121_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DAIF_SysRegWrite_3d31f214debf624b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DAIF_SysRegWrite_3d31f214debf624b el op0 op1 CRn op2 CRm val_name)" + by (unfold DAIF_SysRegWrite_3d31f214debf624b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGBCR_EL1_SysRegWrite_6730f3e3839510c5[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGBCR_EL1_SysRegWrite_6730f3e3839510c5 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGBCR_EL1_SysRegWrite_6730f3e3839510c5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGCLAIMCLR_EL1_SysRegWrite_2a099a67767e57cf[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGCLAIMCLR_EL1_SysRegWrite_2a099a67767e57cf el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGCLAIMCLR_EL1_SysRegWrite_2a099a67767e57cf_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGCLAIMSET_EL1_SysRegWrite_90e355b6a5730770[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGCLAIMSET_EL1_SysRegWrite_90e355b6a5730770 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGCLAIMSET_EL1_SysRegWrite_90e355b6a5730770_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGDTRTX_EL0_SysRegWrite_057e8c91e001a69f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGDTRTX_EL0_SysRegWrite_057e8c91e001a69f el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGDTRTX_EL0_SysRegWrite_057e8c91e001a69f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGDTR_EL0_SysRegWrite_c7246a22e06c7729[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGDTR_EL0_SysRegWrite_c7246a22e06c7729 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGDTR_EL0_SysRegWrite_c7246a22e06c7729_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGPRCR_EL1_SysRegWrite_710b60256172548e[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGPRCR_EL1_SysRegWrite_710b60256172548e el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGPRCR_EL1_SysRegWrite_710b60256172548e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGVCR32_EL2_SysRegWrite_769fbfe4fa51a4e5[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGVCR32_EL2_SysRegWrite_769fbfe4fa51a4e5 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGVCR32_EL2_SysRegWrite_769fbfe4fa51a4e5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGWCR_EL1_SysRegWrite_6bda3acb5910d354[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGWCR_EL1_SysRegWrite_6bda3acb5910d354 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGWCR_EL1_SysRegWrite_6bda3acb5910d354_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DBGWVR_EL1_SysRegWrite_745b296ee53305ea[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DBGWVR_EL1_SysRegWrite_745b296ee53305ea el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGWVR_EL1_SysRegWrite_745b296ee53305ea_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DISR_EL1_SysRegWrite_64517664b9260065[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DISR_EL1_SysRegWrite_64517664b9260065 el op0 op1 CRn op2 CRm val_name)" + by (unfold DISR_EL1_SysRegWrite_64517664b9260065_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERRSELR_EL1_SysRegWrite_551535eed30e26f9[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ERRSELR_EL1_SysRegWrite_551535eed30e26f9 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERRSELR_EL1_SysRegWrite_551535eed30e26f9_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERXADDR_EL1_SysRegWrite_8a1eabc2959662e8[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ERXADDR_EL1_SysRegWrite_8a1eabc2959662e8 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXADDR_EL1_SysRegWrite_8a1eabc2959662e8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERXCTLR_EL1_SysRegWrite_acca1e102ba86b42[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ERXCTLR_EL1_SysRegWrite_acca1e102ba86b42 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXCTLR_EL1_SysRegWrite_acca1e102ba86b42_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERXMISC0_EL1_SysRegWrite_822ceca9b10b2621[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ERXMISC0_EL1_SysRegWrite_822ceca9b10b2621 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXMISC0_EL1_SysRegWrite_822ceca9b10b2621_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERXMISC1_EL1_SysRegWrite_9a9ef77b5fd82587[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ERXMISC1_EL1_SysRegWrite_9a9ef77b5fd82587 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXMISC1_EL1_SysRegWrite_9a9ef77b5fd82587_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ERXSTATUS_EL1_SysRegWrite_f0798b4207ec0193[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ERXSTATUS_EL1_SysRegWrite_f0798b4207ec0193 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXSTATUS_EL1_SysRegWrite_f0798b4207ec0193_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ESR_EL12_SysRegWrite_2b2d6012ba438548[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ESR_EL12_SysRegWrite_2b2d6012ba438548 el op0 op1 CRn op2 CRm val_name)" + by (unfold ESR_EL12_SysRegWrite_2b2d6012ba438548_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ESR_EL1_SysRegWrite_a8ce40896bd70a6b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ESR_EL1_SysRegWrite_a8ce40896bd70a6b el op0 op1 CRn op2 CRm val_name)" + by (unfold ESR_EL1_SysRegWrite_a8ce40896bd70a6b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ESR_EL2_SysRegWrite_a10e84e3bd1020c8[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ESR_EL2_SysRegWrite_a10e84e3bd1020c8 el op0 op1 CRn op2 CRm val_name)" + by (unfold ESR_EL2_SysRegWrite_a10e84e3bd1020c8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ESR_EL3_SysRegWrite_195a2e1a5b40464e[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ESR_EL3_SysRegWrite_195a2e1a5b40464e el op0 op1 CRn op2 CRm val_name)" + by (unfold ESR_EL3_SysRegWrite_195a2e1a5b40464e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FAR_EL12_SysRegWrite_78f825940e556299[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FAR_EL12_SysRegWrite_78f825940e556299 el op0 op1 CRn op2 CRm val_name)" + by (unfold FAR_EL12_SysRegWrite_78f825940e556299_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FAR_EL1_SysRegWrite_fc0bd224b62cc089[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FAR_EL1_SysRegWrite_fc0bd224b62cc089 el op0 op1 CRn op2 CRm val_name)" + by (unfold FAR_EL1_SysRegWrite_fc0bd224b62cc089_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FAR_EL2_SysRegWrite_6370aabce83a1613[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FAR_EL2_SysRegWrite_6370aabce83a1613 el op0 op1 CRn op2 CRm val_name)" + by (unfold FAR_EL2_SysRegWrite_6370aabce83a1613_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FAR_EL3_SysRegWrite_397cfda85a093e9d[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FAR_EL3_SysRegWrite_397cfda85a093e9d el op0 op1 CRn op2 CRm val_name)" + by (unfold FAR_EL3_SysRegWrite_397cfda85a093e9d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPCR_SysRegWrite_4f255cf55390cebb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPCR_SysRegWrite_4f255cf55390cebb el op0 op1 CRn op2 CRm val_name)" + by (unfold FPCR_SysRegWrite_4f255cf55390cebb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPEXC32_EL2_SysRegWrite_9f180ead5c4d6735[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPEXC32_EL2_SysRegWrite_9f180ead5c4d6735 el op0 op1 CRn op2 CRm val_name)" + by (unfold FPEXC32_EL2_SysRegWrite_9f180ead5c4d6735_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPSR_SysRegWrite_413aed98a94900de[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPSR_SysRegWrite_413aed98a94900de el op0 op1 CRn op2 CRm val_name)" + by (unfold FPSR_SysRegWrite_413aed98a94900de_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_HACR_EL2_SysRegWrite_5b2ca32fcb39ecab[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (HACR_EL2_SysRegWrite_5b2ca32fcb39ecab el op0 op1 CRn op2 CRm val_name)" + by (unfold HACR_EL2_SysRegWrite_5b2ca32fcb39ecab_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_HCR_EL2_SysRegWrite_6fc18e07a17fd5a2[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (HCR_EL2_SysRegWrite_6fc18e07a17fd5a2 el op0 op1 CRn op2 CRm val_name)" + by (unfold HCR_EL2_SysRegWrite_6fc18e07a17fd5a2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_HPFAR_EL2_SysRegWrite_20417eccdd6b4768[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (HPFAR_EL2_SysRegWrite_20417eccdd6b4768 el op0 op1 CRn op2 CRm val_name)" + by (unfold HPFAR_EL2_SysRegWrite_20417eccdd6b4768_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_HSTR_EL2_SysRegWrite_391a605c0bfb9d1e[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (HSTR_EL2_SysRegWrite_391a605c0bfb9d1e el op0 op1 CRn op2 CRm val_name)" + by (unfold HSTR_EL2_SysRegWrite_391a605c0bfb9d1e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_AP0R_EL1_SysRegWrite_949897f971748acc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_AP0R_EL1_SysRegWrite_949897f971748acc el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_AP0R_EL1_SysRegWrite_949897f971748acc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_AP1R_EL1_SysRegWrite_55167410f7650dea[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_AP1R_EL1_SysRegWrite_55167410f7650dea el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_AP1R_EL1_SysRegWrite_55167410f7650dea_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_ASGI1R_EL1_SysRegWrite_c163c25adc1b1354[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_ASGI1R_EL1_SysRegWrite_c163c25adc1b1354 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_ASGI1R_EL1_SysRegWrite_c163c25adc1b1354_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_BPR0_EL1_SysRegWrite_10028206553f3655[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_BPR0_EL1_SysRegWrite_10028206553f3655 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_BPR0_EL1_SysRegWrite_10028206553f3655_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_BPR1_EL1_SysRegWrite_a633b2e9f3626d9b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_BPR1_EL1_SysRegWrite_a633b2e9f3626d9b el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_BPR1_EL1_SysRegWrite_a633b2e9f3626d9b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_CTLR_EL1_SysRegWrite_8ec3f4b67393eba8[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_CTLR_EL1_SysRegWrite_8ec3f4b67393eba8 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_CTLR_EL1_SysRegWrite_8ec3f4b67393eba8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_CTLR_EL3_SysRegWrite_ecc8b41b177c53e8[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_CTLR_EL3_SysRegWrite_ecc8b41b177c53e8 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_CTLR_EL3_SysRegWrite_ecc8b41b177c53e8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_DIR_EL1_SysRegWrite_77fadeda7efde9c5[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_DIR_EL1_SysRegWrite_77fadeda7efde9c5 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_DIR_EL1_SysRegWrite_77fadeda7efde9c5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_EOIR0_EL1_SysRegWrite_9c0fae08cd7a2444[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_EOIR0_EL1_SysRegWrite_9c0fae08cd7a2444 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_EOIR0_EL1_SysRegWrite_9c0fae08cd7a2444_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_EOIR1_EL1_SysRegWrite_f065db56e179bf6e[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_EOIR1_EL1_SysRegWrite_f065db56e179bf6e el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_EOIR1_EL1_SysRegWrite_f065db56e179bf6e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_IGRPEN0_EL1_SysRegWrite_b94e4d10f7a33382[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_IGRPEN0_EL1_SysRegWrite_b94e4d10f7a33382 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_IGRPEN0_EL1_SysRegWrite_b94e4d10f7a33382_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_IGRPEN1_EL1_SysRegWrite_c36dfa556252f6b4[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_IGRPEN1_EL1_SysRegWrite_c36dfa556252f6b4 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_IGRPEN1_EL1_SysRegWrite_c36dfa556252f6b4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_IGRPEN1_EL3_SysRegWrite_6f1db000a53b40ca[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_IGRPEN1_EL3_SysRegWrite_6f1db000a53b40ca el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_IGRPEN1_EL3_SysRegWrite_6f1db000a53b40ca_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_PMR_EL1_SysRegWrite_8bb2caa31e7d5e1b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_PMR_EL1_SysRegWrite_8bb2caa31e7d5e1b el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_PMR_EL1_SysRegWrite_8bb2caa31e7d5e1b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_SGI0R_EL1_SysRegWrite_ba6d1066ea6fbbb7[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_SGI0R_EL1_SysRegWrite_ba6d1066ea6fbbb7 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SGI0R_EL1_SysRegWrite_ba6d1066ea6fbbb7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_SGI1R_EL1_SysRegWrite_0da31fe6c2e1b098[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_SGI1R_EL1_SysRegWrite_0da31fe6c2e1b098 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SGI1R_EL1_SysRegWrite_0da31fe6c2e1b098_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_SRE_EL1_SysRegWrite_d2efb75caa67d019[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_SRE_EL1_SysRegWrite_d2efb75caa67d019 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SRE_EL1_SysRegWrite_d2efb75caa67d019_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_SRE_EL2_SysRegWrite_39c314f677b8ec2e[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_SRE_EL2_SysRegWrite_39c314f677b8ec2e el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SRE_EL2_SysRegWrite_39c314f677b8ec2e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICC_SRE_EL3_SysRegWrite_c0af2dd58a7e1d22[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICC_SRE_EL3_SysRegWrite_c0af2dd58a7e1d22 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SRE_EL3_SysRegWrite_c0af2dd58a7e1d22_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_AP0R_EL2_SysRegWrite_9517857bb550d699[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICH_AP0R_EL2_SysRegWrite_9517857bb550d699 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_AP0R_EL2_SysRegWrite_9517857bb550d699_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_AP1R_EL2_SysRegWrite_20f46016b54a3395[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICH_AP1R_EL2_SysRegWrite_20f46016b54a3395 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_AP1R_EL2_SysRegWrite_20f46016b54a3395_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_HCR_EL2_SysRegWrite_2fea52a15cd7dbe5[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICH_HCR_EL2_SysRegWrite_2fea52a15cd7dbe5 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_HCR_EL2_SysRegWrite_2fea52a15cd7dbe5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_LR_EL2_SysRegWrite_8b291f94259261d2[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICH_LR_EL2_SysRegWrite_8b291f94259261d2 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_LR_EL2_SysRegWrite_8b291f94259261d2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ICH_VMCR_EL2_SysRegWrite_86a315374f6b5205[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ICH_VMCR_EL2_SysRegWrite_86a315374f6b5205 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_VMCR_EL2_SysRegWrite_86a315374f6b5205_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_IFSR32_EL2_SysRegWrite_6ce25b2b11e30403[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (IFSR32_EL2_SysRegWrite_6ce25b2b11e30403 el op0 op1 CRn op2 CRm val_name)" + by (unfold IFSR32_EL2_SysRegWrite_6ce25b2b11e30403_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_LORC_EL1_SysRegWrite_7100b979c23fc52e[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (LORC_EL1_SysRegWrite_7100b979c23fc52e el op0 op1 CRn op2 CRm val_name)" + by (unfold LORC_EL1_SysRegWrite_7100b979c23fc52e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_LOREA_EL1_SysRegWrite_2d068511b7f5ce7b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (LOREA_EL1_SysRegWrite_2d068511b7f5ce7b el op0 op1 CRn op2 CRm val_name)" + by (unfold LOREA_EL1_SysRegWrite_2d068511b7f5ce7b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_LORN_EL1_SysRegWrite_bde03c74e878b099[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (LORN_EL1_SysRegWrite_bde03c74e878b099 el op0 op1 CRn op2 CRm val_name)" + by (unfold LORN_EL1_SysRegWrite_bde03c74e878b099_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_LORSA_EL1_SysRegWrite_9ba633e967136731[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (LORSA_EL1_SysRegWrite_9ba633e967136731 el op0 op1 CRn op2 CRm val_name)" + by (unfold LORSA_EL1_SysRegWrite_9ba633e967136731_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MAIR_EL12_SysRegWrite_da2526ed2008ed50[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MAIR_EL12_SysRegWrite_da2526ed2008ed50 el op0 op1 CRn op2 CRm val_name)" + by (unfold MAIR_EL12_SysRegWrite_da2526ed2008ed50_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MAIR_EL1_SysRegWrite_45d8150aaf31e3b9[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MAIR_EL1_SysRegWrite_45d8150aaf31e3b9 el op0 op1 CRn op2 CRm val_name)" + by (unfold MAIR_EL1_SysRegWrite_45d8150aaf31e3b9_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MAIR_EL2_SysRegWrite_4e3422c1776528f5[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MAIR_EL2_SysRegWrite_4e3422c1776528f5 el op0 op1 CRn op2 CRm val_name)" + by (unfold MAIR_EL2_SysRegWrite_4e3422c1776528f5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MAIR_EL3_SysRegWrite_d15af780e0b4e771[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MAIR_EL3_SysRegWrite_d15af780e0b4e771 el op0 op1 CRn op2 CRm val_name)" + by (unfold MAIR_EL3_SysRegWrite_d15af780e0b4e771_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MDCCINT_EL1_SysRegWrite_1e6a37984aec7145[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MDCCINT_EL1_SysRegWrite_1e6a37984aec7145 el op0 op1 CRn op2 CRm val_name)" + by (unfold MDCCINT_EL1_SysRegWrite_1e6a37984aec7145_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MDCR_EL2_SysRegWrite_3f12005c8c459bf3[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MDCR_EL2_SysRegWrite_3f12005c8c459bf3 el op0 op1 CRn op2 CRm val_name)" + by (unfold MDCR_EL2_SysRegWrite_3f12005c8c459bf3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MDCR_EL3_SysRegWrite_37dff5fa83ad16ed[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MDCR_EL3_SysRegWrite_37dff5fa83ad16ed el op0 op1 CRn op2 CRm val_name)" + by (unfold MDCR_EL3_SysRegWrite_37dff5fa83ad16ed_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MDSCR_EL1_SysRegWrite_94ddb1e46aff4dfa[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MDSCR_EL1_SysRegWrite_94ddb1e46aff4dfa el op0 op1 CRn op2 CRm val_name)" + by (unfold MDSCR_EL1_SysRegWrite_94ddb1e46aff4dfa_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAM0_EL1_SysRegWrite_88f6c0c61a59ac23[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAM0_EL1_SysRegWrite_88f6c0c61a59ac23 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM0_EL1_SysRegWrite_88f6c0c61a59ac23_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAM1_EL12_SysRegWrite_2cbbb0edf5787671[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAM1_EL12_SysRegWrite_2cbbb0edf5787671 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM1_EL12_SysRegWrite_2cbbb0edf5787671_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAM1_EL1_SysRegWrite_cd02720a3298b1c6[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAM1_EL1_SysRegWrite_cd02720a3298b1c6 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM1_EL1_SysRegWrite_cd02720a3298b1c6_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAM2_EL2_SysRegWrite_d6bae8d18aebb554[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAM2_EL2_SysRegWrite_d6bae8d18aebb554 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM2_EL2_SysRegWrite_d6bae8d18aebb554_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAM3_EL3_SysRegWrite_bb55d8a9d90e05e3[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAM3_EL3_SysRegWrite_bb55d8a9d90e05e3 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM3_EL3_SysRegWrite_bb55d8a9d90e05e3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMHCR_EL2_SysRegWrite_e38755d6111336b8[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAMHCR_EL2_SysRegWrite_e38755d6111336b8 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMHCR_EL2_SysRegWrite_e38755d6111336b8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM0_EL2_SysRegWrite_c00108111630aa84[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAMVPM0_EL2_SysRegWrite_c00108111630aa84 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM0_EL2_SysRegWrite_c00108111630aa84_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM1_EL2_SysRegWrite_81a739cc4bd1cd46[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAMVPM1_EL2_SysRegWrite_81a739cc4bd1cd46 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM1_EL2_SysRegWrite_81a739cc4bd1cd46_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM2_EL2_SysRegWrite_20a1b54bc18980b1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAMVPM2_EL2_SysRegWrite_20a1b54bc18980b1 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM2_EL2_SysRegWrite_20a1b54bc18980b1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM3_EL2_SysRegWrite_d2a71d8e23cc67af[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAMVPM3_EL2_SysRegWrite_d2a71d8e23cc67af el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM3_EL2_SysRegWrite_d2a71d8e23cc67af_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM4_EL2_SysRegWrite_2d0a10731399829d[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAMVPM4_EL2_SysRegWrite_2d0a10731399829d el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM4_EL2_SysRegWrite_2d0a10731399829d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM5_EL2_SysRegWrite_ec98ca57d40ac9ec[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAMVPM5_EL2_SysRegWrite_ec98ca57d40ac9ec el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM5_EL2_SysRegWrite_ec98ca57d40ac9ec_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM6_EL2_SysRegWrite_0934853fee68e9bd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAMVPM6_EL2_SysRegWrite_0934853fee68e9bd el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM6_EL2_SysRegWrite_0934853fee68e9bd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPM7_EL2_SysRegWrite_dfb7f68750df7012[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAMVPM7_EL2_SysRegWrite_dfb7f68750df7012 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM7_EL2_SysRegWrite_dfb7f68750df7012_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MPAMVPMV_EL2_SysRegWrite_abd8d27e91fadf85[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MPAMVPMV_EL2_SysRegWrite_abd8d27e91fadf85 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPMV_EL2_SysRegWrite_abd8d27e91fadf85_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_OSDLR_EL1_SysRegWrite_591fd96d91652c64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (OSDLR_EL1_SysRegWrite_591fd96d91652c64 el op0 op1 CRn op2 CRm val_name)" + by (unfold OSDLR_EL1_SysRegWrite_591fd96d91652c64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_OSDTRRX_EL1_SysRegWrite_6dc5d8521b60df8a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (OSDTRRX_EL1_SysRegWrite_6dc5d8521b60df8a el op0 op1 CRn op2 CRm val_name)" + by (unfold OSDTRRX_EL1_SysRegWrite_6dc5d8521b60df8a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_OSDTRTX_EL1_SysRegWrite_9ba0c4a85d0c1de5[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (OSDTRTX_EL1_SysRegWrite_9ba0c4a85d0c1de5 el op0 op1 CRn op2 CRm val_name)" + by (unfold OSDTRTX_EL1_SysRegWrite_9ba0c4a85d0c1de5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_OSECCR_EL1_SysRegWrite_cabf381bfb822732[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (OSECCR_EL1_SysRegWrite_cabf381bfb822732 el op0 op1 CRn op2 CRm val_name)" + by (unfold OSECCR_EL1_SysRegWrite_cabf381bfb822732_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_OSLAR_EL1_SysRegWrite_582d77c57653b2c4[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (OSLAR_EL1_SysRegWrite_582d77c57653b2c4 el op0 op1 CRn op2 CRm val_name)" + by (unfold OSLAR_EL1_SysRegWrite_582d77c57653b2c4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PAR_EL1_SysRegWrite_aa92c70a4b5d5873[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PAR_EL1_SysRegWrite_aa92c70a4b5d5873 el op0 op1 CRn op2 CRm val_name)" + by (unfold PAR_EL1_SysRegWrite_aa92c70a4b5d5873_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMBLIMITR_EL1_SysRegWrite_ddfe2ba603df6628[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMBLIMITR_EL1_SysRegWrite_ddfe2ba603df6628 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMBLIMITR_EL1_SysRegWrite_ddfe2ba603df6628_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMBPTR_EL1_SysRegWrite_32441d8a7a2b9601[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMBPTR_EL1_SysRegWrite_32441d8a7a2b9601 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMBPTR_EL1_SysRegWrite_32441d8a7a2b9601_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMBSR_EL1_SysRegWrite_ff19dc948509312f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMBSR_EL1_SysRegWrite_ff19dc948509312f el op0 op1 CRn op2 CRm val_name)" + by (unfold PMBSR_EL1_SysRegWrite_ff19dc948509312f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMCCFILTR_EL0_SysRegWrite_42277f001664525c[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMCCFILTR_EL0_SysRegWrite_42277f001664525c el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCCFILTR_EL0_SysRegWrite_42277f001664525c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMCCNTR_EL0_SysRegWrite_1d21e0789830cbf9[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMCCNTR_EL0_SysRegWrite_1d21e0789830cbf9 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCCNTR_EL0_SysRegWrite_1d21e0789830cbf9_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMCNTENCLR_EL0_SysRegWrite_bf2c4fae1a891e1b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMCNTENCLR_EL0_SysRegWrite_bf2c4fae1a891e1b el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCNTENCLR_EL0_SysRegWrite_bf2c4fae1a891e1b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMCNTENSET_EL0_SysRegWrite_227af2773d320cb1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMCNTENSET_EL0_SysRegWrite_227af2773d320cb1 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCNTENSET_EL0_SysRegWrite_227af2773d320cb1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMCR_EL0_SysRegWrite_87ae64466e09f89a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMCR_EL0_SysRegWrite_87ae64466e09f89a el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCR_EL0_SysRegWrite_87ae64466e09f89a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMEVCNTR_EL0_SysRegWrite_c197579331ed9cbb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMEVCNTR_EL0_SysRegWrite_c197579331ed9cbb el op0 op1 CRn op2 CRm val_name)" + by (unfold PMEVCNTR_EL0_SysRegWrite_c197579331ed9cbb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMEVTYPER_EL0_SysRegWrite_3e6ae16cd645ec0d[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMEVTYPER_EL0_SysRegWrite_3e6ae16cd645ec0d el op0 op1 CRn op2 CRm val_name)" + by (unfold PMEVTYPER_EL0_SysRegWrite_3e6ae16cd645ec0d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMINTENCLR_EL1_SysRegWrite_1ebd7bf3738fe872[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMINTENCLR_EL1_SysRegWrite_1ebd7bf3738fe872 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMINTENCLR_EL1_SysRegWrite_1ebd7bf3738fe872_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMINTENSET_EL1_SysRegWrite_dd2481ad892e3441[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMINTENSET_EL1_SysRegWrite_dd2481ad892e3441 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMINTENSET_EL1_SysRegWrite_dd2481ad892e3441_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMOVSCLR_EL0_SysRegWrite_9dfa73cda394af99[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMOVSCLR_EL0_SysRegWrite_9dfa73cda394af99 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMOVSCLR_EL0_SysRegWrite_9dfa73cda394af99_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMOVSSET_EL0_SysRegWrite_cfbbfe3b81fe4290[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMOVSSET_EL0_SysRegWrite_cfbbfe3b81fe4290 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMOVSSET_EL0_SysRegWrite_cfbbfe3b81fe4290_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSCR_EL12_SysRegWrite_fef9a94f50c2763b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMSCR_EL12_SysRegWrite_fef9a94f50c2763b el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSCR_EL12_SysRegWrite_fef9a94f50c2763b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSCR_EL1_SysRegWrite_9798a89ab6804fe0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMSCR_EL1_SysRegWrite_9798a89ab6804fe0 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSCR_EL1_SysRegWrite_9798a89ab6804fe0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSCR_EL2_SysRegWrite_02cd14dd325ed94b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMSCR_EL2_SysRegWrite_02cd14dd325ed94b el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSCR_EL2_SysRegWrite_02cd14dd325ed94b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSELR_EL0_SysRegWrite_18613307de8564a3[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMSELR_EL0_SysRegWrite_18613307de8564a3 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSELR_EL0_SysRegWrite_18613307de8564a3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSEVFR_EL1_SysRegWrite_6524c56cd8a10057[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMSEVFR_EL1_SysRegWrite_6524c56cd8a10057 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSEVFR_EL1_SysRegWrite_6524c56cd8a10057_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSFCR_EL1_SysRegWrite_44d58271848f0db1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMSFCR_EL1_SysRegWrite_44d58271848f0db1 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSFCR_EL1_SysRegWrite_44d58271848f0db1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSICR_EL1_SysRegWrite_1e74423ea1c96ae7[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMSICR_EL1_SysRegWrite_1e74423ea1c96ae7 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSICR_EL1_SysRegWrite_1e74423ea1c96ae7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSIRR_EL1_SysRegWrite_bb25878486c35a36[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMSIRR_EL1_SysRegWrite_bb25878486c35a36 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSIRR_EL1_SysRegWrite_bb25878486c35a36_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSLATFR_EL1_SysRegWrite_5c8b43a6a65c8272[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMSLATFR_EL1_SysRegWrite_5c8b43a6a65c8272 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSLATFR_EL1_SysRegWrite_5c8b43a6a65c8272_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMSWINC_EL0_SysRegWrite_cce1d915b163d5e3[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMSWINC_EL0_SysRegWrite_cce1d915b163d5e3 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSWINC_EL0_SysRegWrite_cce1d915b163d5e3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMUSERENR_EL0_SysRegWrite_e7535626e3360c36[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMUSERENR_EL0_SysRegWrite_e7535626e3360c36 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMUSERENR_EL0_SysRegWrite_e7535626e3360c36_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMXEVCNTR_EL0_SysRegWrite_20b0a6df43a7d4ef[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMXEVCNTR_EL0_SysRegWrite_20b0a6df43a7d4ef el op0 op1 CRn op2 CRm val_name)" + by (unfold PMXEVCNTR_EL0_SysRegWrite_20b0a6df43a7d4ef_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_PMXEVTYPER_EL0_SysRegWrite_82fb55a6e723e983[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (PMXEVTYPER_EL0_SysRegWrite_82fb55a6e723e983 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMXEVTYPER_EL0_SysRegWrite_82fb55a6e723e983_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RMR_EL1_SysRegWrite_0ae19f794f511c7a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (RMR_EL1_SysRegWrite_0ae19f794f511c7a el op0 op1 CRn op2 CRm val_name)" + by (unfold RMR_EL1_SysRegWrite_0ae19f794f511c7a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RMR_EL2_SysRegWrite_df7b9a989e2495d2[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (RMR_EL2_SysRegWrite_df7b9a989e2495d2 el op0 op1 CRn op2 CRm val_name)" + by (unfold RMR_EL2_SysRegWrite_df7b9a989e2495d2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RMR_EL3_SysRegWrite_2849130fc457929e[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (RMR_EL3_SysRegWrite_2849130fc457929e el op0 op1 CRn op2 CRm val_name)" + by (unfold RMR_EL3_SysRegWrite_2849130fc457929e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RSP_EL0_SysRegWrite_5b2edb6edd27507d[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (RSP_EL0_SysRegWrite_5b2edb6edd27507d el op0 op1 CRn op2 CRm val_name)" + by (unfold RSP_EL0_SysRegWrite_5b2edb6edd27507d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RTPIDR_EL0_SysRegWrite_74d55919bd0ab5f3[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (RTPIDR_EL0_SysRegWrite_74d55919bd0ab5f3 el op0 op1 CRn op2 CRm val_name)" + by (unfold RTPIDR_EL0_SysRegWrite_74d55919bd0ab5f3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S3_op1_CCn_CCm_op2_SysRegWrite_22dd63287f599042[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S3_op1_CCn_CCm_op2_SysRegWrite_22dd63287f599042 el op0 op1 CRn op2 CRm val_name)" + by (unfold S3_op1_CCn_CCm_op2_SysRegWrite_22dd63287f599042_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCR_EL3_SysRegWrite_020d082781fa9b72[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (SCR_EL3_SysRegWrite_020d082781fa9b72 el op0 op1 CRn op2 CRm val_name)" + by (unfold SCR_EL3_SysRegWrite_020d082781fa9b72_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCTLR_EL12_SysRegWrite_302de25977d2a0ca[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (SCTLR_EL12_SysRegWrite_302de25977d2a0ca el op0 op1 CRn op2 CRm val_name)" + by (unfold SCTLR_EL12_SysRegWrite_302de25977d2a0ca_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCTLR_EL1_SysRegWrite_711b0546c662c54d[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (SCTLR_EL1_SysRegWrite_711b0546c662c54d el op0 op1 CRn op2 CRm val_name)" + by (unfold SCTLR_EL1_SysRegWrite_711b0546c662c54d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCTLR_EL2_SysRegWrite_ff61a6f00288b28a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (SCTLR_EL2_SysRegWrite_ff61a6f00288b28a el op0 op1 CRn op2 CRm val_name)" + by (unfold SCTLR_EL2_SysRegWrite_ff61a6f00288b28a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCTLR_EL3_SysRegWrite_5b7cc79e5ea93a8f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (SCTLR_EL3_SysRegWrite_5b7cc79e5ea93a8f el op0 op1 CRn op2 CRm val_name)" + by (unfold SCTLR_EL3_SysRegWrite_5b7cc79e5ea93a8f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCXTNUM_EL0_SysRegWrite_9dbee2793d69c02e[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (SCXTNUM_EL0_SysRegWrite_9dbee2793d69c02e el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL0_SysRegWrite_9dbee2793d69c02e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCXTNUM_EL12_SysRegWrite_ba74367909393c9b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (SCXTNUM_EL12_SysRegWrite_ba74367909393c9b el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL12_SysRegWrite_ba74367909393c9b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCXTNUM_EL1_SysRegWrite_6467f6f26a31cece[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (SCXTNUM_EL1_SysRegWrite_6467f6f26a31cece el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL1_SysRegWrite_6467f6f26a31cece_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCXTNUM_EL2_SysRegWrite_2fcbb6503badb23c[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (SCXTNUM_EL2_SysRegWrite_2fcbb6503badb23c el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL2_SysRegWrite_2fcbb6503badb23c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SCXTNUM_EL3_SysRegWrite_b39fe9ab09a67ecd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (SCXTNUM_EL3_SysRegWrite_b39fe9ab09a67ecd el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL3_SysRegWrite_b39fe9ab09a67ecd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_SDER32_EL3_SysRegWrite_69011ff5e95ac923[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (SDER32_EL3_SysRegWrite_69011ff5e95ac923 el op0 op1 CRn op2 CRm val_name)" + by (unfold SDER32_EL3_SysRegWrite_69011ff5e95ac923_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TCR_EL12_SysRegWrite_64a7f44c6ddaa0f8[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (TCR_EL12_SysRegWrite_64a7f44c6ddaa0f8 el op0 op1 CRn op2 CRm val_name)" + by (unfold TCR_EL12_SysRegWrite_64a7f44c6ddaa0f8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TCR_EL1_SysRegWrite_c27e6fc190bb0f0b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (TCR_EL1_SysRegWrite_c27e6fc190bb0f0b el op0 op1 CRn op2 CRm val_name)" + by (unfold TCR_EL1_SysRegWrite_c27e6fc190bb0f0b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TCR_EL2_SysRegWrite_5e38279a245750c4[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (TCR_EL2_SysRegWrite_5e38279a245750c4 el op0 op1 CRn op2 CRm val_name)" + by (unfold TCR_EL2_SysRegWrite_5e38279a245750c4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TCR_EL3_SysRegWrite_3b3587015a3d20f4[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (TCR_EL3_SysRegWrite_3b3587015a3d20f4 el op0 op1 CRn op2 CRm val_name)" + by (unfold TCR_EL3_SysRegWrite_3b3587015a3d20f4_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR0_EL12_SysRegWrite_fd9df8519bfad5c0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (TTBR0_EL12_SysRegWrite_fd9df8519bfad5c0 el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR0_EL12_SysRegWrite_fd9df8519bfad5c0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR0_EL1_SysRegWrite_8a149790a79e2eab[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (TTBR0_EL1_SysRegWrite_8a149790a79e2eab el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR0_EL1_SysRegWrite_8a149790a79e2eab_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR0_EL2_SysRegWrite_7cd39d4a24a70e7f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (TTBR0_EL2_SysRegWrite_7cd39d4a24a70e7f el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR0_EL2_SysRegWrite_7cd39d4a24a70e7f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR0_EL3_SysRegWrite_7e091a8effc9ee7f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (TTBR0_EL3_SysRegWrite_7e091a8effc9ee7f el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR0_EL3_SysRegWrite_7e091a8effc9ee7f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR1_EL12_SysRegWrite_4fbeb1f28c2e8107[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (TTBR1_EL12_SysRegWrite_4fbeb1f28c2e8107 el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR1_EL12_SysRegWrite_4fbeb1f28c2e8107_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR1_EL1_SysRegWrite_89690e4d3c87217b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (TTBR1_EL1_SysRegWrite_89690e4d3c87217b el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR1_EL1_SysRegWrite_89690e4d3c87217b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TTBR1_EL2_SysRegWrite_59fad32bc548b47a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (TTBR1_EL2_SysRegWrite_59fad32bc548b47a el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR1_EL2_SysRegWrite_59fad32bc548b47a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VBAR_EL12_SysRegWrite_a20f8f7f07b5cf7a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (VBAR_EL12_SysRegWrite_a20f8f7f07b5cf7a el op0 op1 CRn op2 CRm val_name)" + by (unfold VBAR_EL12_SysRegWrite_a20f8f7f07b5cf7a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VBAR_EL1_SysRegWrite_29ba7540e032fce6[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (VBAR_EL1_SysRegWrite_29ba7540e032fce6 el op0 op1 CRn op2 CRm val_name)" + by (unfold VBAR_EL1_SysRegWrite_29ba7540e032fce6_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VBAR_EL2_SysRegWrite_d5657e8591e8e22a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (VBAR_EL2_SysRegWrite_d5657e8591e8e22a el op0 op1 CRn op2 CRm val_name)" + by (unfold VBAR_EL2_SysRegWrite_d5657e8591e8e22a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VBAR_EL3_SysRegWrite_1da603c27eb5f668[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (VBAR_EL3_SysRegWrite_1da603c27eb5f668 el op0 op1 CRn op2 CRm val_name)" + by (unfold VBAR_EL3_SysRegWrite_1da603c27eb5f668_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VDISR_EL2_SysRegWrite_8b2c23874e253f64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (VDISR_EL2_SysRegWrite_8b2c23874e253f64 el op0 op1 CRn op2 CRm val_name)" + by (unfold VDISR_EL2_SysRegWrite_8b2c23874e253f64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VMPIDR_EL2_SysRegWrite_c153d7c8b5628bd5[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (VMPIDR_EL2_SysRegWrite_c153d7c8b5628bd5 el op0 op1 CRn op2 CRm val_name)" + by (unfold VMPIDR_EL2_SysRegWrite_c153d7c8b5628bd5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VPIDR_EL2_SysRegWrite_0dbf139af5a73d1f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (VPIDR_EL2_SysRegWrite_0dbf139af5a73d1f el op0 op1 CRn op2 CRm val_name)" + by (unfold VPIDR_EL2_SysRegWrite_0dbf139af5a73d1f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VSESR_EL2_SysRegWrite_e989f4bcf0ae8aa6[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (VSESR_EL2_SysRegWrite_e989f4bcf0ae8aa6 el op0 op1 CRn op2 CRm val_name)" + by (unfold VSESR_EL2_SysRegWrite_e989f4bcf0ae8aa6_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VTCR_EL2_SysRegWrite_d49abb8b3aa0eff3[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (VTCR_EL2_SysRegWrite_d49abb8b3aa0eff3 el op0 op1 CRn op2 CRm val_name)" + by (unfold VTCR_EL2_SysRegWrite_d49abb8b3aa0eff3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VTTBR_EL2_SysRegWrite_5198ee0e793550a5[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (VTTBR_EL2_SysRegWrite_5198ee0e793550a5 el op0 op1 CRn op2 CRm val_name)" + by (unfold VTTBR_EL2_SysRegWrite_5198ee0e793550a5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_AutoGen_SysRegWrite[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_AutoGen_SysRegWrite el op0 op1 CRn op2 CRm val_name)" + by (unfold AArch64_AutoGen_SysRegWrite_def bind_assoc, no_reg_writes_toI intro: runs_no_reg_writes_to_if_no_asm) + +lemma runs_no_reg_writes_to_CDBGDTR_EL0_CapSysRegWrite_336052f10e4a36b7[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CDBGDTR_EL0_CapSysRegWrite_336052f10e4a36b7 el op0 op1 CRn op2 CRm val_name)" + by (unfold CDBGDTR_EL0_CapSysRegWrite_336052f10e4a36b7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CDLR_EL0_CapSysRegWrite_2763be7daadf3c03[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CDLR_EL0_CapSysRegWrite_2763be7daadf3c03 el op0 op1 CRn op2 CRm val_name)" + by (unfold CDLR_EL0_CapSysRegWrite_2763be7daadf3c03_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CELR_EL12_CapSysRegWrite_a1507df00ba9d725[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CELR_EL12_CapSysRegWrite_a1507df00ba9d725 el op0 op1 CRn op2 CRm val_name)" + by (unfold CELR_EL12_CapSysRegWrite_a1507df00ba9d725_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CELR_EL1_CapSysRegWrite_33a9b4f0fad89fe8[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CELR_EL1_CapSysRegWrite_33a9b4f0fad89fe8 el op0 op1 CRn op2 CRm val_name)" + by (unfold CELR_EL1_CapSysRegWrite_33a9b4f0fad89fe8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CELR_EL2_CapSysRegWrite_8d32fe1dd5ad0417[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CELR_EL2_CapSysRegWrite_8d32fe1dd5ad0417 el op0 op1 CRn op2 CRm val_name)" + by (unfold CELR_EL2_CapSysRegWrite_8d32fe1dd5ad0417_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CELR_EL3_CapSysRegWrite_55e82fec5d907003[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CELR_EL3_CapSysRegWrite_55e82fec5d907003 el op0 op1 CRn op2 CRm val_name)" + by (unfold CELR_EL3_CapSysRegWrite_55e82fec5d907003_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CID_EL0_CapSysRegWrite_8c1c5cf69181759f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CID_EL0_CapSysRegWrite_8c1c5cf69181759f el op0 op1 CRn op2 CRm val_name)" + by (unfold CID_EL0_CapSysRegWrite_8c1c5cf69181759f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CSP_EL0_CapSysRegWrite_ee1d127810ef0f04[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CSP_EL0_CapSysRegWrite_ee1d127810ef0f04 el op0 op1 CRn op2 CRm val_name)" + by (unfold CSP_EL0_CapSysRegWrite_ee1d127810ef0f04_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CSP_EL1_CapSysRegWrite_f4579d836810c21a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CSP_EL1_CapSysRegWrite_f4579d836810c21a el op0 op1 CRn op2 CRm val_name)" + by (unfold CSP_EL1_CapSysRegWrite_f4579d836810c21a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CSP_EL2_CapSysRegWrite_59c69d74679ef283[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CSP_EL2_CapSysRegWrite_59c69d74679ef283 el op0 op1 CRn op2 CRm val_name)" + by (unfold CSP_EL2_CapSysRegWrite_59c69d74679ef283_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CTPIDRRO_EL0_CapSysRegWrite_e64109ff95ad4800[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CTPIDRRO_EL0_CapSysRegWrite_e64109ff95ad4800 el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDRRO_EL0_CapSysRegWrite_e64109ff95ad4800_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CTPIDR_EL0_CapSysRegWrite_8f94c4d256adadf0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CTPIDR_EL0_CapSysRegWrite_8f94c4d256adadf0 el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDR_EL0_CapSysRegWrite_8f94c4d256adadf0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CTPIDR_EL1_CapSysRegWrite_3190df090d2d128f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CTPIDR_EL1_CapSysRegWrite_3190df090d2d128f el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDR_EL1_CapSysRegWrite_3190df090d2d128f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CTPIDR_EL2_CapSysRegWrite_a740113e578c9b32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CTPIDR_EL2_CapSysRegWrite_a740113e578c9b32 el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDR_EL2_CapSysRegWrite_a740113e578c9b32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CTPIDR_EL3_CapSysRegWrite_376b7d525b15b21b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CTPIDR_EL3_CapSysRegWrite_376b7d525b15b21b el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDR_EL3_CapSysRegWrite_376b7d525b15b21b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CVBAR_EL12_CapSysRegWrite_3fd157cf974c31e5[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CVBAR_EL12_CapSysRegWrite_3fd157cf974c31e5 el op0 op1 CRn op2 CRm val_name)" + by (unfold CVBAR_EL12_CapSysRegWrite_3fd157cf974c31e5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CVBAR_EL1_CapSysRegWrite_bbad0575f41fce2f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CVBAR_EL1_CapSysRegWrite_bbad0575f41fce2f el op0 op1 CRn op2 CRm val_name)" + by (unfold CVBAR_EL1_CapSysRegWrite_bbad0575f41fce2f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CVBAR_EL2_CapSysRegWrite_2a412e2b2c0a0a2b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CVBAR_EL2_CapSysRegWrite_2a412e2b2c0a0a2b el op0 op1 CRn op2 CRm val_name)" + by (unfold CVBAR_EL2_CapSysRegWrite_2a412e2b2c0a0a2b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CVBAR_EL3_CapSysRegWrite_f3c8bbee84b292db[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CVBAR_EL3_CapSysRegWrite_f3c8bbee84b292db el op0 op1 CRn op2 CRm val_name)" + by (unfold CVBAR_EL3_CapSysRegWrite_f3c8bbee84b292db_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DDC_CapSysRegWrite_9bc98e4e82148914[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DDC_CapSysRegWrite_9bc98e4e82148914 el op0 op1 CRn op2 CRm val_name)" + by (unfold DDC_CapSysRegWrite_9bc98e4e82148914_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DDC_EL0_CapSysRegWrite_1a928678ff9b43a6[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DDC_EL0_CapSysRegWrite_1a928678ff9b43a6 el op0 op1 CRn op2 CRm val_name)" + by (unfold DDC_EL0_CapSysRegWrite_1a928678ff9b43a6_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DDC_EL1_CapSysRegWrite_e7ecb5b1f0c49d28[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DDC_EL1_CapSysRegWrite_e7ecb5b1f0c49d28 el op0 op1 CRn op2 CRm val_name)" + by (unfold DDC_EL1_CapSysRegWrite_e7ecb5b1f0c49d28_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DDC_EL2_CapSysRegWrite_b4142a2dcadf2a34[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DDC_EL2_CapSysRegWrite_b4142a2dcadf2a34 el op0 op1 CRn op2 CRm val_name)" + by (unfold DDC_EL2_CapSysRegWrite_b4142a2dcadf2a34_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RCSP_EL0_CapSysRegWrite_d8f83400674fbeeb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (RCSP_EL0_CapSysRegWrite_d8f83400674fbeeb el op0 op1 CRn op2 CRm val_name)" + by (unfold RCSP_EL0_CapSysRegWrite_d8f83400674fbeeb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RCTPIDR_EL0_CapSysRegWrite_27f7c47e137c72f8[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (RCTPIDR_EL0_CapSysRegWrite_27f7c47e137c72f8 el op0 op1 CRn op2 CRm val_name)" + by (unfold RCTPIDR_EL0_CapSysRegWrite_27f7c47e137c72f8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RDDC_EL0_CapSysRegWrite_c528d1b2eb785ad7[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (RDDC_EL0_CapSysRegWrite_c528d1b2eb785ad7 el op0 op1 CRn op2 CRm val_name)" + by (unfold RDDC_EL0_CapSysRegWrite_c528d1b2eb785ad7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_AutoGen_CapSysRegWrite[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_AutoGen_CapSysRegWrite el op0 op1 CRn op2 CRm val_name)" + by (unfold AArch64_AutoGen_CapSysRegWrite_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_CapSysRegWrite[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_CapSysRegWrite op0 op1 crn crm op2 val_name)" + by (unfold AArch64_CapSysRegWrite_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ALLE1IS_SysOpsWrite_8b81b55e2116aad3[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ALLE1IS_SysOpsWrite_8b81b55e2116aad3 el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE1IS_SysOpsWrite_8b81b55e2116aad3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ALLE1_SysOpsWrite_69364bedc72cbe96[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ALLE1_SysOpsWrite_69364bedc72cbe96 el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE1_SysOpsWrite_69364bedc72cbe96_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_UndefinedFault[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_UndefinedFault arg0)" + by (unfold AArch64_UndefinedFault_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_UndefinedFault[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (UndefinedFault arg0)" + by (unfold UndefinedFault_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TLBI_ALLE2IS[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TLBI_ALLE2IS arg0)" + by (unfold TLBI_ALLE2IS_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ALLE2IS_SysOpsWrite_3a173239947b2c25[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ALLE2IS_SysOpsWrite_3a173239947b2c25 el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE2IS_SysOpsWrite_3a173239947b2c25_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TLBI_ALLE2[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TLBI_ALLE2 arg0)" + by (unfold TLBI_ALLE2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ALLE2_SysOpsWrite_19c7b5110a5efe1d[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ALLE2_SysOpsWrite_19c7b5110a5efe1d el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE2_SysOpsWrite_19c7b5110a5efe1d_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ALLE3IS_SysOpsWrite_e64b79b4c41910fb[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ALLE3IS_SysOpsWrite_e64b79b4c41910fb el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE3IS_SysOpsWrite_e64b79b4c41910fb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ALLE3_SysOpsWrite_5835ce2f987f3d36[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ALLE3_SysOpsWrite_5835ce2f987f3d36 el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE3_SysOpsWrite_5835ce2f987f3d36_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ASIDE1IS_SysOpsWrite_5a5dff91f113e41e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ASIDE1IS_SysOpsWrite_5a5dff91f113e41e el op0 op1 CRn op2 CRm val_name)" + by (unfold ASIDE1IS_SysOpsWrite_5a5dff91f113e41e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ASIDE1_SysOpsWrite_7ba7a3df395925e0[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ASIDE1_SysOpsWrite_7ba7a3df395925e0 el op0 op1 CRn op2 CRm val_name)" + by (unfold ASIDE1_SysOpsWrite_7ba7a3df395925e0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_CISW[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DC_CISW val_name)" + by (unfold DC_CISW_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CISW_SysOpsWrite_5321b1c3157dccce[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CISW_SysOpsWrite_5321b1c3157dccce el op0 op1 CRn op2 CRm val_name)" + by (unfold CISW_SysOpsWrite_5321b1c3157dccce_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_BreakpointException[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_BreakpointException fault)" + by (unfold AArch64_BreakpointException_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_DataAbort[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_DataAbort vaddress fault)" + by (unfold AArch64_DataAbort_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_InstructionAbort[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_InstructionAbort vaddress fault)" + by (unfold AArch64_InstructionAbort_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_WatchpointException[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_WatchpointException vaddress fault)" + by (unfold AArch64_WatchpointException_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_Abort[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_Abort vaddress fault)" + by (unfold AArch64_Abort_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_CIVAC[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DC_CIVAC val_name)" + by (unfold DC_CIVAC_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MorelloCheckForCMO[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (MorelloCheckForCMO cval requested_perms acctype)" + by (unfold MorelloCheckForCMO_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_CIVAC0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DC_CIVAC0 val_name__arg)" + by (unfold DC_CIVAC0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CIVAC_SysOpsWrite_47ad60ecb930d217[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CIVAC_SysOpsWrite_47ad60ecb930d217 el op0 op1 CRn op2 CRm val_name)" + by (unfold CIVAC_SysOpsWrite_47ad60ecb930d217_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_CSW[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DC_CSW val_name)" + by (unfold DC_CSW_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CSW_SysOpsWrite_9544819da3ebaa1b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CSW_SysOpsWrite_9544819da3ebaa1b el op0 op1 CRn op2 CRm val_name)" + by (unfold CSW_SysOpsWrite_9544819da3ebaa1b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_CVAC[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DC_CVAC val_name)" + by (unfold DC_CVAC_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_CVAC0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DC_CVAC0 val_name__arg)" + by (unfold DC_CVAC0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CVAC_SysOpsWrite_c7d2e911c691cc6b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CVAC_SysOpsWrite_c7d2e911c691cc6b el op0 op1 CRn op2 CRm val_name)" + by (unfold CVAC_SysOpsWrite_c7d2e911c691cc6b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_CVAP[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DC_CVAP val_name)" + by (unfold DC_CVAP_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_CVADP[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DC_CVADP val_name)" + by (unfold DC_CVADP_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CVADP_SysOpsWrite_9953ef108c01d34a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CVADP_SysOpsWrite_9953ef108c01d34a el op0 op1 CRn op2 CRm val_name)" + by (unfold CVADP_SysOpsWrite_9953ef108c01d34a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CVAP_SysOpsWrite_a43f75867888e74a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CVAP_SysOpsWrite_a43f75867888e74a el op0 op1 CRn op2 CRm val_name)" + by (unfold CVAP_SysOpsWrite_a43f75867888e74a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_CVAU[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DC_CVAU val_name)" + by (unfold DC_CVAU_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_CVAU0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DC_CVAU0 val_name__arg)" + by (unfold DC_CVAU0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CVAU_SysOpsWrite_4a72bbc98a17973c[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CVAU_SysOpsWrite_4a72bbc98a17973c el op0 op1 CRn op2 CRm val_name)" + by (unfold CVAU_SysOpsWrite_4a72bbc98a17973c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_IC_IALLUIS[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (IC_IALLUIS arg0)" + by (unfold IC_IALLUIS_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_IALLUIS_SysOpsWrite_9a906c8365100aff[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (IALLUIS_SysOpsWrite_9a906c8365100aff el op0 op1 CRn op2 CRm val_name)" + by (unfold IALLUIS_SysOpsWrite_9a906c8365100aff_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_IC_IALLU[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (IC_IALLU arg0)" + by (unfold IC_IALLU_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_IALLU_SysOpsWrite_81563797a4921929[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (IALLU_SysOpsWrite_81563797a4921929 el op0 op1 CRn op2 CRm val_name)" + by (unfold IALLU_SysOpsWrite_81563797a4921929_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_IPAS2E1IS_SysOpsWrite_ed4be1feae90b987[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (IPAS2E1IS_SysOpsWrite_ed4be1feae90b987 el op0 op1 CRn op2 CRm val_name)" + by (unfold IPAS2E1IS_SysOpsWrite_ed4be1feae90b987_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_IPAS2E1_SysOpsWrite_a65fef0d99f9428f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (IPAS2E1_SysOpsWrite_a65fef0d99f9428f el op0 op1 CRn op2 CRm val_name)" + by (unfold IPAS2E1_SysOpsWrite_a65fef0d99f9428f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_IPAS2LE1IS_SysOpsWrite_5a72848dfefa19f3[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (IPAS2LE1IS_SysOpsWrite_5a72848dfefa19f3 el op0 op1 CRn op2 CRm val_name)" + by (unfold IPAS2LE1IS_SysOpsWrite_5a72848dfefa19f3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_IPAS2LE1_SysOpsWrite_10ca7ac6abdfed50[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (IPAS2LE1_SysOpsWrite_10ca7ac6abdfed50 el op0 op1 CRn op2 CRm val_name)" + by (unfold IPAS2LE1_SysOpsWrite_10ca7ac6abdfed50_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_ISW[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DC_ISW val_name)" + by (unfold DC_ISW_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ISW_SysOpsWrite_d5fceb001aa0aa7a[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ISW_SysOpsWrite_d5fceb001aa0aa7a el op0 op1 CRn op2 CRm val_name)" + by (unfold ISW_SysOpsWrite_d5fceb001aa0aa7a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_IVAC[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DC_IVAC val_name)" + by (unfold DC_IVAC_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_IVAC0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (DC_IVAC0 val_name__arg)" + by (unfold DC_IVAC0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_IVAC_SysOpsWrite_41b93e0e56e4f107[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (IVAC_SysOpsWrite_41b93e0e56e4f107 el op0 op1 CRn op2 CRm val_name)" + by (unfold IVAC_SysOpsWrite_41b93e0e56e4f107_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_IC_IVAU[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (IC_IVAU val_name)" + by (unfold IC_IVAU_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_IVAU_SysOpsWrite_2dfe97b748dd324e[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (IVAU_SysOpsWrite_2dfe97b748dd324e el op0 op1 CRn op2 CRm val_name)" + by (unfold IVAU_SysOpsWrite_2dfe97b748dd324e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RCTX_SysOpsWrite_bcc8cd10f2e68999[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RCTX_SysOpsWrite_bcc8cd10f2e68999 el op0 op1 CRn op2 CRm val_name)" + by (unfold RCTX_SysOpsWrite_bcc8cd10f2e68999_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RCTX_SysOpsWrite_c287513d0d3e8e92[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RCTX_SysOpsWrite_c287513d0d3e8e92 el op0 op1 CRn op2 CRm val_name)" + by (unfold RCTX_SysOpsWrite_c287513d0d3e8e92_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_RCTX_SysOpsWrite_d614ec87236c038f[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (RCTX_SysOpsWrite_d614ec87236c038f el op0 op1 CRn op2 CRm val_name)" + by (unfold RCTX_SysOpsWrite_d614ec87236c038f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_AT_S1Ex[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_AT_S1Ex val_name el iswrite)" + by (unfold AArch64_AT_S1Ex_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_AT_S12Ex[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_AT_S12Ex val_name el iswrite)" + by (unfold AArch64_AT_S12Ex_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S12E0R[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S12E0R val_name)" + by (unfold AT_S12E0R_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S1E0R[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S1E0R val_name)" + by (unfold AT_S1E0R_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S12E0R_SysOpsWrite_4df3d544cba811b7[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S12E0R_SysOpsWrite_4df3d544cba811b7 el op0 op1 CRn op2 CRm val_name)" + by (unfold S12E0R_SysOpsWrite_4df3d544cba811b7_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S12E0W[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S12E0W val_name)" + by (unfold AT_S12E0W_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S1E0W[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S1E0W val_name)" + by (unfold AT_S1E0W_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S12E0W_SysOpsWrite_1dbb37d4af097406[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S12E0W_SysOpsWrite_1dbb37d4af097406 el op0 op1 CRn op2 CRm val_name)" + by (unfold S12E0W_SysOpsWrite_1dbb37d4af097406_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S12E1R[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S12E1R val_name)" + by (unfold AT_S12E1R_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S1E1R[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S1E1R val_name)" + by (unfold AT_S1E1R_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S12E1R_SysOpsWrite_e44276c8f24d398f[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S12E1R_SysOpsWrite_e44276c8f24d398f el op0 op1 CRn op2 CRm val_name)" + by (unfold S12E1R_SysOpsWrite_e44276c8f24d398f_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S12E1W[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S12E1W val_name)" + by (unfold AT_S12E1W_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S1E1W[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S1E1W val_name)" + by (unfold AT_S1E1W_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S12E1W_SysOpsWrite_c8b72d75cad90601[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S12E1W_SysOpsWrite_c8b72d75cad90601 el op0 op1 CRn op2 CRm val_name)" + by (unfold S12E1W_SysOpsWrite_c8b72d75cad90601_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S1E0R_SysOpsWrite_0a1e21ea5b4c8722[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S1E0R_SysOpsWrite_0a1e21ea5b4c8722 el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E0R_SysOpsWrite_0a1e21ea5b4c8722_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S1E0W_SysOpsWrite_d102d49fd92af65a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S1E0W_SysOpsWrite_d102d49fd92af65a el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E0W_SysOpsWrite_d102d49fd92af65a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S1E1RP[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S1E1RP val_name)" + by (unfold AT_S1E1RP_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S1E1RP_SysOpsWrite_4a6b1f71ee0182ab[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S1E1RP_SysOpsWrite_4a6b1f71ee0182ab el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E1RP_SysOpsWrite_4a6b1f71ee0182ab_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S1E1R_SysOpsWrite_018a577644c5d23c[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S1E1R_SysOpsWrite_018a577644c5d23c el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E1R_SysOpsWrite_018a577644c5d23c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S1E1WP[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S1E1WP val_name)" + by (unfold AT_S1E1WP_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S1E1WP_SysOpsWrite_bb1ddb9112effe2a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S1E1WP_SysOpsWrite_bb1ddb9112effe2a el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E1WP_SysOpsWrite_bb1ddb9112effe2a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S1E1W_SysOpsWrite_df64f2f63c0911fd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S1E1W_SysOpsWrite_df64f2f63c0911fd el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E1W_SysOpsWrite_df64f2f63c0911fd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S1E2R[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S1E2R val_name)" + by (unfold AT_S1E2R_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S1E2R_SysOpsWrite_5e865a96c06417c8[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S1E2R_SysOpsWrite_5e865a96c06417c8 el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E2R_SysOpsWrite_5e865a96c06417c8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S1E2W[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S1E2W val_name)" + by (unfold AT_S1E2W_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S1E2W_SysOpsWrite_1649806418453f02[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S1E2W_SysOpsWrite_1649806418453f02 el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E2W_SysOpsWrite_1649806418453f02_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S1E3R[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S1E3R val_name)" + by (unfold AT_S1E3R_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S1E3R_SysOpsWrite_6476f20e79e358be[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S1E3R_SysOpsWrite_6476f20e79e358be el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E3R_SysOpsWrite_6476f20e79e358be_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AT_S1E3W[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AT_S1E3W val_name)" + by (unfold AT_S1E3W_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S1E3W_SysOpsWrite_e92e083e28fa4dd0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (S1E3W_SysOpsWrite_e92e083e28fa4dd0 el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E3W_SysOpsWrite_e92e083e28fa4dd0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_S1_op1_Cn_Cm_op2_SysOpsWrite_d6b17d94c0df44bc[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (S1_op1_Cn_Cm_op2_SysOpsWrite_d6b17d94c0df44bc el op0 op1 CRn op2 CRm val_name)" + by (unfold S1_op1_Cn_Cm_op2_SysOpsWrite_d6b17d94c0df44bc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VAAE1IS_SysOpsWrite_c22cd5a1dc8e7320[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VAAE1IS_SysOpsWrite_c22cd5a1dc8e7320 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAAE1IS_SysOpsWrite_c22cd5a1dc8e7320_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VAAE1_SysOpsWrite_8498b4db5afbed38[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VAAE1_SysOpsWrite_8498b4db5afbed38 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAAE1_SysOpsWrite_8498b4db5afbed38_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VAALE1IS_SysOpsWrite_5c8056a5b649fe2e[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VAALE1IS_SysOpsWrite_5c8056a5b649fe2e el op0 op1 CRn op2 CRm val_name)" + by (unfold VAALE1IS_SysOpsWrite_5c8056a5b649fe2e_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VAALE1_SysOpsWrite_d3bec3a19881fb1c[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VAALE1_SysOpsWrite_d3bec3a19881fb1c el op0 op1 CRn op2 CRm val_name)" + by (unfold VAALE1_SysOpsWrite_d3bec3a19881fb1c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VAE1IS_SysOpsWrite_5eac1ac5cb4e76ff[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VAE1IS_SysOpsWrite_5eac1ac5cb4e76ff el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE1IS_SysOpsWrite_5eac1ac5cb4e76ff_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VAE1_SysOpsWrite_09dbfc0bf1b19b11[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VAE1_SysOpsWrite_09dbfc0bf1b19b11 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE1_SysOpsWrite_09dbfc0bf1b19b11_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TLBI_VAE2IS[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TLBI_VAE2IS val_name)" + by (unfold TLBI_VAE2IS_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VAE2IS_SysOpsWrite_f81411101129df7b[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VAE2IS_SysOpsWrite_f81411101129df7b el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE2IS_SysOpsWrite_f81411101129df7b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TLBI_VAE2[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TLBI_VAE2 val_name)" + by (unfold TLBI_VAE2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VAE2_SysOpsWrite_78002df18993a4b5[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VAE2_SysOpsWrite_78002df18993a4b5 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE2_SysOpsWrite_78002df18993a4b5_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VAE3IS_SysOpsWrite_7dc759c51bb69ced[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VAE3IS_SysOpsWrite_7dc759c51bb69ced el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE3IS_SysOpsWrite_7dc759c51bb69ced_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VAE3_SysOpsWrite_90b5c3b60d3bd152[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VAE3_SysOpsWrite_90b5c3b60d3bd152 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE3_SysOpsWrite_90b5c3b60d3bd152_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VALE1IS_SysOpsWrite_7bb7ad05a900b833[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VALE1IS_SysOpsWrite_7bb7ad05a900b833 el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE1IS_SysOpsWrite_7bb7ad05a900b833_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VALE1_SysOpsWrite_c1766c627b3960ca[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VALE1_SysOpsWrite_c1766c627b3960ca el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE1_SysOpsWrite_c1766c627b3960ca_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TLBI_VALE2IS[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TLBI_VALE2IS val_name)" + by (unfold TLBI_VALE2IS_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VALE2IS_SysOpsWrite_a1084cefbce599af[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VALE2IS_SysOpsWrite_a1084cefbce599af el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE2IS_SysOpsWrite_a1084cefbce599af_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_TLBI_VALE2[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (TLBI_VALE2 val_name)" + by (unfold TLBI_VALE2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VALE2_SysOpsWrite_dce4b2b057d036da[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VALE2_SysOpsWrite_dce4b2b057d036da el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE2_SysOpsWrite_dce4b2b057d036da_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VALE3IS_SysOpsWrite_8b70cb86db2abfcd[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VALE3IS_SysOpsWrite_8b70cb86db2abfcd el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE3IS_SysOpsWrite_8b70cb86db2abfcd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VALE3_SysOpsWrite_df1f91b1bea42ec8[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VALE3_SysOpsWrite_df1f91b1bea42ec8 el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE3_SysOpsWrite_df1f91b1bea42ec8_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VMALLE1IS_SysOpsWrite_08cfba716c4ca8db[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VMALLE1IS_SysOpsWrite_08cfba716c4ca8db el op0 op1 CRn op2 CRm val_name)" + by (unfold VMALLE1IS_SysOpsWrite_08cfba716c4ca8db_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VMALLE1_SysOpsWrite_c64f2572b311d9b9[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VMALLE1_SysOpsWrite_c64f2572b311d9b9 el op0 op1 CRn op2 CRm val_name)" + by (unfold VMALLE1_SysOpsWrite_c64f2572b311d9b9_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VMALLS12E1IS_SysOpsWrite_92a1ba1461a19d4c[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VMALLS12E1IS_SysOpsWrite_92a1ba1461a19d4c el op0 op1 CRn op2 CRm val_name)" + by (unfold VMALLS12E1IS_SysOpsWrite_92a1ba1461a19d4c_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VMALLS12E1_SysOpsWrite_8f5c303094061f20[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VMALLS12E1_SysOpsWrite_8f5c303094061f20 el op0 op1 CRn op2 CRm val_name)" + by (unfold VMALLS12E1_SysOpsWrite_8f5c303094061f20_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_ZVA[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DC_ZVA val_name)" + by (unfold DC_ZVA_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_DC_ZVA0[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (DC_ZVA0 val_name__arg)" + by (unfold DC_ZVA0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ZVA_SysOpsWrite_b40574bff0ba4354[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (ZVA_SysOpsWrite_b40574bff0ba4354 el op0 op1 CRn op2 CRm val_name)" + by (unfold ZVA_SysOpsWrite_b40574bff0ba4354_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_AutoGen_SysOpsWrite[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_AutoGen_SysOpsWrite el op0 op1 CRn op2 CRm val_name)" + by (unfold AArch64_AutoGen_SysOpsWrite_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_SysInstr[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_SysInstr op0 op1 crn crm op2 val_name)" + by (unfold AArch64_SysInstr_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_SysInstrWithResult[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_SysInstrWithResult op0 op1 crn crm op2)" + by (unfold AArch64_SysInstrWithResult_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_FPTrappedException[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_FPTrappedException is_ase element accumulated_exceptions)" + by (unfold AArch64_FPTrappedException_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPProcessException[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPProcessException exception fpcr)" + by (unfold FPProcessException_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPRoundBase[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPRoundBase arg0 arg1 arg2 arg3 arg4)" + by (unfold FPRoundBase_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPRound[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPRound N op fpcr__arg rounding)" + by (unfold FPRound_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPRound__1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPRound__1 N op fpcr)" + by (unfold FPRound__1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FixedToFP[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FixedToFP N op fbits is_unsigned fpcr rounding)" + by (unfold FixedToFP_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPProcessNaN[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPProcessNaN fptype op fpcr)" + by (unfold FPProcessNaN_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPProcessNaNs[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPProcessNaNs type1 type2 op1 op2 fpcr)" + by (unfold FPProcessNaNs_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPUnpackBase[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPUnpackBase fpval fpcr)" + by (unfold FPUnpackBase_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPUnpack[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPUnpack fpval fpcr__arg)" + by (unfold FPUnpack_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPAdd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPAdd op1 op2 fpcr)" + by (unfold FPAdd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPCompare[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPCompare op1 op2 signal_nans fpcr)" + by (unfold FPCompare_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPCompareEQ[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPCompareEQ op1 op2 fpcr)" + by (unfold FPCompareEQ_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPCompareGE[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPCompareGE op1 op2 fpcr)" + by (unfold FPCompareGE_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPCompareGT[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPCompareGT op1 op2 fpcr)" + by (unfold FPCompareGT_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPRoundCV[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPRoundCV N op fpcr__arg rounding)" + by (unfold FPRoundCV_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPUnpackCV[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPUnpackCV fpval fpcr__arg)" + by (unfold FPUnpackCV_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPConvert[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPConvert l__604 op fpcr rounding)" + by (unfold FPConvert_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPConvert__1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPConvert__1 M op fpcr)" + by (unfold FPConvert__1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPDiv[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPDiv op1 op2 fpcr)" + by (unfold FPDiv_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPMax[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPMax op1 op2 fpcr)" + by (unfold FPMax_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPMaxNum[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPMaxNum op1__arg op2__arg fpcr)" + by (unfold FPMaxNum_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPMin[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPMin op1 op2 fpcr)" + by (unfold FPMin_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPMinNum[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPMinNum op1__arg op2__arg fpcr)" + by (unfold FPMinNum_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPMul[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPMul op1 op2 fpcr)" + by (unfold FPMul_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPProcessNaNs3[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPProcessNaNs3 type1 type2 type3 op1 op2 op3 fpcr)" + by (unfold FPProcessNaNs3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPMulAdd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPMulAdd addend op1 op2 fpcr)" + by (unfold FPMulAdd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPMulX[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPMulX op1 op2 fpcr)" + by (unfold FPMulX_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPRecipEstimate[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPRecipEstimate operand fpcr)" + by (unfold FPRecipEstimate_def bind_assoc, no_reg_writes_toI intro: runs_no_reg_writes_to_if_no_asm) + +lemma runs_no_reg_writes_to_FPRecpX[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPRecpX l__583 op fpcr)" + by (unfold FPRecpX_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPRoundInt[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPRoundInt op fpcr rounding exact)" + by (unfold FPRoundInt_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPRSqrtEstimate[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPRSqrtEstimate operand fpcr)" + by (unfold FPRSqrtEstimate_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPSqrt[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPSqrt op fpcr)" + by (unfold FPSqrt_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPSub[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPSub op1 op2 fpcr)" + by (unfold FPSub_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPToFixed[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPToFixed M op fbits is_unsigned fpcr rounding)" + by (unfold FPToFixed_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_SPAlignmentFault[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_SPAlignmentFault arg0)" + by (unfold AArch64_SPAlignmentFault_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CheckSPAlignment[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CheckSPAlignment arg0)" + by (unfold CheckSPAlignment_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_BaseReg_read[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (BaseReg_read n is_prefetch)" + by (unfold BaseReg_read_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_BaseReg_read__1[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (BaseReg_read__1 n)" + by (unfold BaseReg_read__1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AltBaseReg_read[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AltBaseReg_read n is_prefetch)" + by (unfold AltBaseReg_read_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AltBaseReg_read__1[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AltBaseReg_read__1 n)" + by (unfold AltBaseReg_read__1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_CheckSystemAccess[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_CheckSystemAccess op0 op1 crn crm op2 rt read)" + by (unfold AArch64_CheckSystemAccess_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_CheckAlignment[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_CheckAlignment address alignment acctype iswrite)" + by (unfold AArch64_CheckAlignment_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_MemSingle_read[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_MemSingle_read address size__arg acctype wasaligned)" + by (unfold AArch64_MemSingle_read_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_MemSingle_set[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_MemSingle_set address size__arg acctype wasaligned value_name)" + by (unfold AArch64_MemSingle_set_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CheckLoadTagsPermission[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CheckLoadTagsPermission desc acctype)" + by (unfold CheckLoadTagsPermission_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CheckStoreTagsPermission[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CheckStoreTagsPermission desc acctype)" + by (unfold CheckStoreTagsPermission_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_TaggedMemSingle[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_TaggedMemSingle address size__arg acctype wasaligned)" + by (unfold AArch64_TaggedMemSingle_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_TaggedMemSingle__1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_TaggedMemSingle__1 address size__arg acctype wasaligned tags value_name)" + by (unfold AArch64_TaggedMemSingle__1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CheckCapabilityAlignment[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CheckCapabilityAlignment address acctype iswrite)" + by (unfold CheckCapabilityAlignment_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_CapabilityTag[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_CapabilityTag address acctype)" + by (unfold AArch64_CapabilityTag_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_CapabilityTag_set[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_CapabilityTag_set address acctype tag)" + by (unfold AArch64_CapabilityTag_set_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_Mem_read0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (Mem_read0 address size__arg acctype)" + by (unfold Mem_read0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_Mem_set0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (Mem_set0 address size__arg acctype value_name__arg)" + by (unfold Mem_set0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CheckCapabilityStorePairAlignment[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CheckCapabilityStorePairAlignment address acctype iswrite)" + by (unfold CheckCapabilityStorePairAlignment_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MemC_read[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MemC_read address acctype)" + by (unfold MemC_read_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MemC_set[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MemC_set address acctype value_name)" + by (unfold MemC_set_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MemCP__1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MemCP__1 address acctype value1_name value2_name)" + by (unfold MemCP__1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_TranslateAddressForAtomicAccess[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_TranslateAddressForAtomicAccess address sizeinbits)" + by (unfold AArch64_TranslateAddressForAtomicAccess_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CheckCapability[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CheckCapability c__arg address size__arg requested_perms acctype)" + by (unfold CheckCapability_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_VACheckAddress[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (VACheckAddress base addr64 size__arg requested_perms acctype)" + by (unfold VACheckAddress_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MemAtomicCompareAndSwap[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MemAtomicCompareAndSwap base expectedvalue newvalue__arg ldacctype stacctype)" + by (unfold MemAtomicCompareAndSwap_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MemAtomic[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MemAtomic base op value_name ldacctype stacctype)" + by (unfold MemAtomic_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MemAtomicCompareAndSwapC[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MemAtomicCompareAndSwapC vaddr address expectedcap newcap ldacctype stacctype)" + by (unfold MemAtomicCompareAndSwapC_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_MemAtomicC[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (MemAtomicC address op value_name ldacctype stacctype)" + by (unfold MemAtomicC_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_ExclusiveMonitorsPass[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_ExclusiveMonitorsPass address size__arg)" + by (unfold AArch64_ExclusiveMonitorsPass_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPRecipStepFused[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPRecipStepFused op1__arg op2)" + by (unfold FPRecipStepFused_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FPRSqrtStepFused[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FPRSqrtStepFused op1__arg op2)" + by (unfold FPRSqrtStepFused_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_CallSecureMonitor[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_CallSecureMonitor immediate)" + by (simp add: runs_no_reg_writes_to_def) + +lemma runs_no_reg_writes_to_AArch64_CallHypervisor[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_CallHypervisor immediate)" + by (simp add: runs_no_reg_writes_to_def) + +lemma runs_no_reg_writes_to_AArch64_CallSupervisor[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_CallSupervisor immediate)" + by (simp add: runs_no_reg_writes_to_def) + +lemma runs_no_reg_writes_to_AArch64_CheckIllegalState[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_CheckIllegalState arg0)" + by (unfold AArch64_CheckIllegalState_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_CheckForSMCUndefOrTrap[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_CheckForSMCUndefOrTrap imm)" + by (unfold AArch64_CheckForSMCUndefOrTrap_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_WFxTrap[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_WFxTrap target_el is_wfe)" + by (unfold AArch64_WFxTrap_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_CheckForWFxTrap[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_CheckForWFxTrap target_el is_wfe)" + by (unfold AArch64_CheckForWFxTrap_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_AdvSIMDFPAccessTrap[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_AdvSIMDFPAccessTrap target_el)" + by (unfold AArch64_AdvSIMDFPAccessTrap_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_CheckFPAdvSIMDTrap[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_CheckFPAdvSIMDTrap arg0)" + by (unfold AArch64_CheckFPAdvSIMDTrap_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_CheckFPAdvSIMDEnabled[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_CheckFPAdvSIMDEnabled arg0)" + by (unfold AArch64_CheckFPAdvSIMDEnabled_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CheckFPAdvSIMDEnabled64[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CheckFPAdvSIMDEnabled64 arg0)" + by (unfold CheckFPAdvSIMDEnabled64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CapabilityAccessTrap[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CapabilityAccessTrap target_el)" + by (unfold CapabilityAccessTrap_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CheckCapabilitiesEnabled[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CheckCapabilitiesEnabled arg0)" + by (unfold CheckCapabilitiesEnabled_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_TakePhysicalIRQException[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_TakePhysicalIRQException arg0)" + by (unfold AArch64_TakePhysicalIRQException_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_SoftwareBreakpoint[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_SoftwareBreakpoint immediate)" + by (unfold AArch64_SoftwareBreakpoint_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_PCAlignmentFault[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_PCAlignmentFault arg0)" + by (unfold AArch64_PCAlignmentFault_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_CheckPCAlignment[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (AArch64_CheckPCAlignment arg0)" + by (unfold AArch64_CheckPCAlignment_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CheckPCCCapability[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CheckPCCCapability arg0)" + by (unfold CheckPCCCapability_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_ReduceCombine[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (ReduceCombine op lo hi)" + by (unfold ReduceCombine_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_Reduce16[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (Reduce16 op input esize)" + by (unfold Reduce16_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_Reduce32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (Reduce32 op input esize)" + by (unfold Reduce32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_Reduce64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (Reduce64 op input esize)" + by (unfold Reduce64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_Reduce128[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (Reduce128 op input esize)" + by (unfold Reduce128_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_Reduce256[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (Reduce256 op input esize)" + by (unfold Reduce256_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_Reduce512[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (Reduce512 op input esize)" + by (unfold Reduce512_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_Reduce1024[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (Reduce1024 op input esize)" + by (unfold Reduce1024_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_Reduce2048[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (Reduce2048 op input esize)" + by (unfold Reduce2048_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_Reduce[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (Reduce op input esize)" + by (unfold Reduce_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CAP_DC_CIVAC[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CAP_DC_CIVAC cval)" + by (unfold CAP_DC_CIVAC_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CAP_DC_CVAC[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CAP_DC_CVAC cval)" + by (unfold CAP_DC_CVAC_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CAP_DC_CVADP[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CAP_DC_CVADP cval)" + by (unfold CAP_DC_CVADP_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CAP_DC_CVAP[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CAP_DC_CVAP cval)" + by (unfold CAP_DC_CVAP_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CAP_DC_CVAU[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CAP_DC_CVAU cval)" + by (unfold CAP_DC_CVAU_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CAP_DC_IVAC[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CAP_DC_IVAC cval)" + by (unfold CAP_DC_IVAC_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CAP_DC_ZVA[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (CAP_DC_ZVA cval)" + by (unfold CAP_DC_ZVA_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_CAP_IC_IVAU[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (CAP_IC_IVAU cval)" + by (unfold CAP_IC_IVAU_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_AArch64_SysInstrWithCapability[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (AArch64_SysInstrWithCapability op0 op1 crn crm op2 val_name)" + by (unfold AArch64_SysInstrWithCapability_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_FetchNextInstr[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (FetchNextInstr arg0)" + by (unfold FetchNextInstr_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ADD_C_CIS_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ADD_C_CIS_C d imm n)" + by (unfold execute_ADD_C_CIS_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ADD_C_CIS_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ADD_C_CIS_C A sh imm12 Cn Cd)" + by (unfold decode_ADD_C_CIS_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ADD_C_CRI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ADD_C_CRI_C d extend_type m n shift)" + by (unfold execute_ADD_C_CRI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ADD_C_CRI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ADD_C_CRI_C Rm option_name imm3 Cn Cd)" + by (unfold decode_ADD_C_CRI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDARB_R_R_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDARB_R_R_B acctype datasize n regsize t__arg)" + by (unfold execute_ALDARB_R_R_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDARB_R_R_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDARB_R_R_B L Rn Rt)" + by (unfold decode_ALDARB_R_R_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDAR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDAR_C_R_C acctype n t__arg)" + by (unfold execute_ALDAR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDAR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDAR_C_R_C L Rn Ct)" + by (unfold decode_ALDAR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDAR_R_R_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDAR_R_R_32 acctype datasize n regsize t__arg)" + by (unfold execute_ALDAR_R_R_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDAR_R_R_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDAR_R_R_32 L Rn Rt)" + by (unfold decode_ALDAR_R_R_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDRB_R_RRB_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDRB_R_RRB_B extend_type m n regsize l__550 shift t__arg)" + by (unfold execute_ALDRB_R_RRB_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDRB_R_RRB_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDRB_R_RRB_B L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDRB_R_RRB_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDRB_R_RUI_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDRB_R_RUI_B datasize n offset regsize t__arg)" + by (unfold execute_ALDRB_R_RUI_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDRB_R_RUI_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDRB_R_RUI_B L imm9 op Rn Rt)" + by (unfold decode_ALDRB_R_RUI_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDRH_R_RRB_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDRH_R_RRB_32 extend_type m n regsize l__549 shift t__arg)" + by (unfold execute_ALDRH_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDRH_R_RRB_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDRH_R_RRB_32 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDRH_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDRSB_R_RRB_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDRSB_R_RRB_32 extend_type m n regsize l__545 shift t__arg)" + by (unfold execute_ALDRSB_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDRSB_R_RRB_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDRSB_R_RRB_32 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDRSB_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDRSB_R_RRB_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDRSB_R_RRB_64 extend_type m n regsize l__546 shift t__arg)" + by (unfold execute_ALDRSB_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDRSB_R_RRB_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDRSB_R_RRB_64 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDRSB_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDRSH_R_RRB_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDRSH_R_RRB_32 extend_type m n regsize l__543 shift t__arg)" + by (unfold execute_ALDRSH_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDRSH_R_RRB_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDRSH_R_RRB_32 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDRSH_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDRSH_R_RRB_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDRSH_R_RRB_64 extend_type m n regsize l__544 shift t__arg)" + by (unfold execute_ALDRSH_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDRSH_R_RRB_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDRSH_R_RRB_64 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDRSH_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDR_C_RRB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDR_C_RRB_C extend_type m n shift t__arg)" + by (unfold execute_ALDR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDR_C_RRB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDR_C_RRB_C Rm sign sz S L Rn Ct)" + by (unfold decode_ALDR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDR_C_RUI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDR_C_RUI_C n offset t__arg)" + by (unfold execute_ALDR_C_RUI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDR_C_RUI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDR_C_RUI_C L imm9 op Rn Ct)" + by (unfold decode_ALDR_C_RUI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDR_R_RRB_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDR_R_RRB_32 extend_type m n regsize l__548 shift t__arg)" + by (unfold execute_ALDR_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDR_R_RRB_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDR_R_RRB_32 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDR_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDR_R_RRB_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDR_R_RRB_64 extend_type m n regsize l__547 shift t__arg)" + by (unfold execute_ALDR_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDR_R_RRB_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDR_R_RRB_64 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDR_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDR_R_RUI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDR_R_RUI_32 datasize n offset regsize t__arg)" + by (unfold execute_ALDR_R_RUI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDR_R_RUI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDR_R_RUI_32 L imm9 op Rn Rt)" + by (unfold decode_ALDR_R_RUI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDR_R_RUI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDR_R_RUI_64 datasize n offset regsize t__arg)" + by (unfold execute_ALDR_R_RUI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDR_R_RUI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDR_R_RUI_64 L imm9 op Rn Rt)" + by (unfold decode_ALDR_R_RUI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDR_V_RRB_D[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDR_V_RRB_D extend_type m n l__542 shift t__arg)" + by (unfold execute_ALDR_V_RRB_D_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDR_V_RRB_D[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDR_V_RRB_D L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDR_V_RRB_D_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDR_V_RRB_S[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDR_V_RRB_S extend_type m n l__541 shift t__arg)" + by (unfold execute_ALDR_V_RRB_S_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDR_V_RRB_S[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDR_V_RRB_S L Rm sign sz S opc Rn Rt)" + by (unfold decode_ALDR_V_RRB_S_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDURB_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDURB_R_RI_32 datasize n offset regsize t__arg)" + by (unfold execute_ALDURB_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDURB_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDURB_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURB_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDURH_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDURH_R_RI_32 datasize n offset regsize t__arg)" + by (unfold execute_ALDURH_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDURH_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDURH_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURH_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDURSB_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDURSB_R_RI_32 datasize n offset regsize t__arg)" + by (unfold execute_ALDURSB_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDURSB_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDURSB_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURSB_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDURSB_R_RI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDURSB_R_RI_64 datasize n offset regsize t__arg)" + by (unfold execute_ALDURSB_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDURSB_R_RI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDURSB_R_RI_64 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURSB_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDURSH_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDURSH_R_RI_32 datasize n offset regsize t__arg)" + by (unfold execute_ALDURSH_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDURSH_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDURSH_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURSH_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDURSH_R_RI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDURSH_R_RI_64 datasize n offset regsize t__arg)" + by (unfold execute_ALDURSH_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDURSH_R_RI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDURSH_R_RI_64 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURSH_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDURSW_R_RI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDURSW_R_RI_64 datasize n offset regsize t__arg)" + by (unfold execute_ALDURSW_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDURSW_R_RI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDURSW_R_RI_64 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDURSW_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDUR_C_RI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDUR_C_RI_C n offset t__arg)" + by (unfold execute_ALDUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDUR_C_RI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDUR_C_RI_C op1 V imm9 op2 Rn Ct)" + by (unfold decode_ALDUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDUR_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDUR_R_RI_32 datasize n offset regsize t__arg)" + by (unfold execute_ALDUR_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDUR_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDUR_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDUR_R_RI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDUR_R_RI_64 datasize n offset regsize t__arg)" + by (unfold execute_ALDUR_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDUR_R_RI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDUR_R_RI_64 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDUR_V_RI_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDUR_V_RI_B datasize n offset t__arg)" + by (unfold execute_ALDUR_V_RI_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDUR_V_RI_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDUR_V_RI_B op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_V_RI_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDUR_V_RI_D[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDUR_V_RI_D datasize n offset t__arg)" + by (unfold execute_ALDUR_V_RI_D_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDUR_V_RI_D[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDUR_V_RI_D op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_V_RI_D_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDUR_V_RI_H[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDUR_V_RI_H datasize n offset t__arg)" + by (unfold execute_ALDUR_V_RI_H_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDUR_V_RI_H[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDUR_V_RI_H op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_V_RI_H_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDUR_V_RI_Q[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDUR_V_RI_Q datasize n offset t__arg)" + by (unfold execute_ALDUR_V_RI_Q_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDUR_V_RI_Q[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDUR_V_RI_Q op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_V_RI_Q_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALDUR_V_RI_S[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALDUR_V_RI_S datasize n offset t__arg)" + by (unfold execute_ALDUR_V_RI_S_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALDUR_V_RI_S[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALDUR_V_RI_S op1 V imm9 op2 Rn Rt)" + by (unfold decode_ALDUR_V_RI_S_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALIGND_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALIGND_C_CI_C align d n)" + by (unfold execute_ALIGND_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALIGND_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALIGND_C_CI_C imm6 U Cn Cd)" + by (unfold decode_ALIGND_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ALIGNU_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ALIGNU_C_CI_C align d n)" + by (unfold execute_ALIGNU_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ALIGNU_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ALIGNU_C_CI_C imm6 U Cn Cd)" + by (unfold decode_ALIGNU_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTLRB_R_R_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTLRB_R_R_B acctype datasize n t__arg)" + by (unfold execute_ASTLRB_R_R_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTLRB_R_R_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTLRB_R_R_B L Rn Rt)" + by (unfold decode_ASTLRB_R_R_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTLR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTLR_C_R_C acctype n t__arg)" + by (unfold execute_ASTLR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTLR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTLR_C_R_C L Rn Ct)" + by (unfold decode_ASTLR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTLR_R_R_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTLR_R_R_32 acctype datasize n t__arg)" + by (unfold execute_ASTLR_R_R_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTLR_R_R_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTLR_R_R_32 L Rn Rt)" + by (unfold decode_ASTLR_R_R_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTRB_R_RRB_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTRB_R_RRB_B extend_type m n l__556 shift t__arg)" + by (unfold execute_ASTRB_R_RRB_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTRB_R_RRB_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTRB_R_RRB_B L Rm sign sz S opc Rn Rt)" + by (unfold decode_ASTRB_R_RRB_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTRB_R_RUI_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTRB_R_RUI_B datasize n offset t__arg)" + by (unfold execute_ASTRB_R_RUI_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTRB_R_RUI_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTRB_R_RUI_B L imm9 op Rn Rt)" + by (unfold decode_ASTRB_R_RUI_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTRH_R_RRB_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTRH_R_RRB_32 extend_type m n l__555 shift t__arg)" + by (unfold execute_ASTRH_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTRH_R_RRB_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTRH_R_RRB_32 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ASTRH_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTR_C_RRB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTR_C_RRB_C extend_type m n shift t__arg)" + by (unfold execute_ASTR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTR_C_RRB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTR_C_RRB_C Rm sign sz S L Rn Ct)" + by (unfold decode_ASTR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTR_C_RUI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTR_C_RUI_C n offset t__arg)" + by (unfold execute_ASTR_C_RUI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTR_C_RUI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTR_C_RUI_C L imm9 op Rn Ct)" + by (unfold decode_ASTR_C_RUI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTR_R_RRB_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTR_R_RRB_32 extend_type m n l__554 shift t__arg)" + by (unfold execute_ASTR_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTR_R_RRB_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTR_R_RRB_32 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ASTR_R_RRB_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTR_R_RRB_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTR_R_RRB_64 extend_type m n l__553 shift t__arg)" + by (unfold execute_ASTR_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTR_R_RRB_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTR_R_RRB_64 L Rm sign sz S opc Rn Rt)" + by (unfold decode_ASTR_R_RRB_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTR_R_RUI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTR_R_RUI_32 datasize n offset t__arg)" + by (unfold execute_ASTR_R_RUI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTR_R_RUI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTR_R_RUI_32 L imm9 op Rn Rt)" + by (unfold decode_ASTR_R_RUI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTR_R_RUI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTR_R_RUI_64 datasize n offset t__arg)" + by (unfold execute_ASTR_R_RUI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTR_R_RUI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTR_R_RUI_64 L imm9 op Rn Rt)" + by (unfold decode_ASTR_R_RUI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTR_V_RRB_D[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTR_V_RRB_D extend_type m n l__552 shift t__arg)" + by (unfold execute_ASTR_V_RRB_D_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTR_V_RRB_D[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTR_V_RRB_D L Rm sign sz S opc Rn Rt)" + by (unfold decode_ASTR_V_RRB_D_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTR_V_RRB_S[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTR_V_RRB_S extend_type m n l__551 shift t__arg)" + by (unfold execute_ASTR_V_RRB_S_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTR_V_RRB_S[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTR_V_RRB_S L Rm sign sz S opc Rn Rt)" + by (unfold decode_ASTR_V_RRB_S_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTURB_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTURB_R_RI_32 datasize n offset t__arg)" + by (unfold execute_ASTURB_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTURB_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTURB_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTURB_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTURH_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTURH_R_RI_32 datasize n offset t__arg)" + by (unfold execute_ASTURH_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTURH_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTURH_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTURH_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTUR_C_RI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTUR_C_RI_C n offset t__arg)" + by (unfold execute_ASTUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTUR_C_RI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTUR_C_RI_C op1 V imm9 op2 Rn Ct)" + by (unfold decode_ASTUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTUR_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTUR_R_RI_32 datasize n offset t__arg)" + by (unfold execute_ASTUR_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTUR_R_RI_32[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTUR_R_RI_32 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_R_RI_32_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTUR_R_RI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTUR_R_RI_64 datasize n offset t__arg)" + by (unfold execute_ASTUR_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTUR_R_RI_64[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTUR_R_RI_64 op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_R_RI_64_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTUR_V_RI_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTUR_V_RI_B datasize n offset t__arg)" + by (unfold execute_ASTUR_V_RI_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTUR_V_RI_B[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTUR_V_RI_B op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_V_RI_B_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTUR_V_RI_D[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTUR_V_RI_D datasize n offset t__arg)" + by (unfold execute_ASTUR_V_RI_D_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTUR_V_RI_D[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTUR_V_RI_D op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_V_RI_D_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTUR_V_RI_H[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTUR_V_RI_H datasize n offset t__arg)" + by (unfold execute_ASTUR_V_RI_H_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTUR_V_RI_H[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTUR_V_RI_H op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_V_RI_H_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTUR_V_RI_Q[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTUR_V_RI_Q datasize n offset t__arg)" + by (unfold execute_ASTUR_V_RI_Q_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTUR_V_RI_Q[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTUR_V_RI_Q op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_V_RI_Q_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ASTUR_V_RI_S[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ASTUR_V_RI_S datasize n offset t__arg)" + by (unfold execute_ASTUR_V_RI_S_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ASTUR_V_RI_S[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ASTUR_V_RI_S op1 V imm9 op2 Rn Rt)" + by (unfold decode_ASTUR_V_RI_S_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_BICFLGS_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_BICFLGS_C_CI_C d mask__arg n)" + by (unfold execute_BICFLGS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_BICFLGS_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_BICFLGS_C_CI_C imm8 Cn Cd)" + by (unfold decode_BICFLGS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_BICFLGS_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_BICFLGS_C_CR_C d m n)" + by (unfold execute_BICFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_BICFLGS_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_BICFLGS_C_CR_C Rm opc Cn Cd)" + by (unfold decode_BICFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_BUILD_C_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_BUILD_C_C_C d m n)" + by (unfold execute_BUILD_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_BUILD_C_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_BUILD_C_C_C Cm opc Cn Cd)" + by (unfold decode_BUILD_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CASAL_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CASAL_C_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_CASAL_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CASAL_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CASAL_C_R_C L Cs R Rn Ct)" + by (unfold decode_CASAL_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CASA_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CASA_C_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_CASA_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CASA_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CASA_C_R_C L Cs R Rn Ct)" + by (unfold decode_CASA_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CASL_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CASL_C_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_CASL_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CASL_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CASL_C_R_C L Cs R Rn Ct)" + by (unfold decode_CASL_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CAS_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CAS_C_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_CAS_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CAS_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CAS_C_R_C L Cs R Rn Ct)" + by (unfold decode_CAS_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CFHI_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CFHI_R_C_C d n)" + by (unfold execute_CFHI_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CFHI_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CFHI_R_C_C opc Cn Rd)" + by (unfold decode_CFHI_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CHKEQ___CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CHKEQ___CC_C m n)" + by (unfold execute_CHKEQ___CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CHKEQ___CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CHKEQ___CC_C Cm opc Cn)" + by (unfold decode_CHKEQ___CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CHKSLD_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CHKSLD_C_C n)" + by (unfold execute_CHKSLD_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CHKSLD_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CHKSLD_C_C opc Cn)" + by (unfold decode_CHKSLD_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CHKSSU_C_CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CHKSSU_C_CC_C d m n)" + by (unfold execute_CHKSSU_C_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CHKSSU_C_CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CHKSSU_C_CC_C Cm opc Cn Cd)" + by (unfold decode_CHKSSU_C_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CHKSS___CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CHKSS___CC_C m n)" + by (unfold execute_CHKSS___CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CHKSS___CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CHKSS___CC_C Cm opc Cn)" + by (unfold decode_CHKSS___CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CHKTGD_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CHKTGD_C_C n)" + by (unfold execute_CHKTGD_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CHKTGD_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CHKTGD_C_C opc Cn)" + by (unfold decode_CHKTGD_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CLRPERM_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CLRPERM_C_CI_C d imm n)" + by (unfold execute_CLRPERM_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CLRPERM_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CLRPERM_C_CI_C perm__arg Cn Cd)" + by (unfold decode_CLRPERM_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CLRPERM_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CLRPERM_C_CR_C d m n)" + by (unfold execute_CLRPERM_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CLRPERM_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CLRPERM_C_CR_C Rm Cn Cd)" + by (unfold decode_CLRPERM_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CLRTAG_C_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CLRTAG_C_C_C d n)" + by (unfold execute_CLRTAG_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CLRTAG_C_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CLRTAG_C_C_C opc Cn Cd)" + by (unfold decode_CLRTAG_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CPYTYPE_C_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CPYTYPE_C_C_C d m n)" + by (unfold execute_CPYTYPE_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CPYTYPE_C_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CPYTYPE_C_C_C Cm opc Cn Cd)" + by (unfold decode_CPYTYPE_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CPYVALUE_C_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CPYVALUE_C_C_C d m n)" + by (unfold execute_CPYVALUE_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CPYVALUE_C_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CPYVALUE_C_C_C Cm opc Cn Cd)" + by (unfold decode_CPYVALUE_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CPY_C_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CPY_C_C_C d n)" + by (unfold execute_CPY_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CPY_C_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CPY_C_C_C opc Cn Cd)" + by (unfold decode_CPY_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CSEAL_C_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CSEAL_C_C_C d m n)" + by (unfold execute_CSEAL_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CSEAL_C_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CSEAL_C_C_C Cm opc Cn Cd)" + by (unfold decode_CSEAL_C_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CSEL_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CSEL_C_CI_C cond d m n)" + by (unfold execute_CSEL_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CSEL_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CSEL_C_CI_C Cm cond Cn Cd)" + by (unfold decode_CSEL_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CTHI_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CTHI_C_CR_C d m n)" + by (unfold execute_CTHI_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CTHI_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CTHI_C_CR_C Rm opc Cn Cd)" + by (unfold decode_CTHI_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CVTDZ_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CVTDZ_C_R_C d n)" + by (unfold execute_CVTDZ_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CVTDZ_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CVTDZ_C_R_C opc Rn Cd)" + by (unfold decode_CVTDZ_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CVTD_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CVTD_C_R_C d n)" + by (unfold execute_CVTD_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CVTD_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CVTD_C_R_C opc Rn Cd)" + by (unfold decode_CVTD_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CVTD_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CVTD_R_C_C d n)" + by (unfold execute_CVTD_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CVTD_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CVTD_R_C_C opc Cn Rd)" + by (unfold decode_CVTD_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CVTPZ_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CVTPZ_C_R_C d n)" + by (unfold execute_CVTPZ_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CVTPZ_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CVTPZ_C_R_C opc Rn Cd)" + by (unfold decode_CVTPZ_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CVTP_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CVTP_C_R_C d n)" + by (unfold execute_CVTP_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CVTP_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CVTP_C_R_C opc Rn Cd)" + by (unfold decode_CVTP_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CVTP_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CVTP_R_C_C d n)" + by (unfold execute_CVTP_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CVTP_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CVTP_R_C_C opc Cn Rd)" + by (unfold decode_CVTP_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CVTZ_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CVTZ_C_CR_C d m n)" + by (unfold execute_CVTZ_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CVTZ_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CVTZ_C_CR_C Rm Cn Cd)" + by (unfold decode_CVTZ_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CVT_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CVT_C_CR_C d m n)" + by (unfold execute_CVT_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CVT_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CVT_C_CR_C Rm Cn Cd)" + by (unfold decode_CVT_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_CVT_R_CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_CVT_R_CC_C d m n)" + by (unfold execute_CVT_R_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_CVT_R_CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_CVT_R_CC_C Cm Cn Rd)" + by (unfold decode_CVT_R_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_EORFLGS_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_EORFLGS_C_CI_C d mask__arg n)" + by (unfold execute_EORFLGS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_EORFLGS_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_EORFLGS_C_CI_C imm8 Cn Cd)" + by (unfold decode_EORFLGS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_EORFLGS_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_EORFLGS_C_CR_C d m n)" + by (unfold execute_EORFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_EORFLGS_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_EORFLGS_C_CR_C Rm opc Cn Cd)" + by (unfold decode_EORFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_GCBASE_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_GCBASE_R_C_C d n)" + by (unfold execute_GCBASE_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_GCBASE_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_GCBASE_R_C_C opc Cn Rd)" + by (unfold decode_GCBASE_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_GCFLGS_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_GCFLGS_R_C_C d n)" + by (unfold execute_GCFLGS_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_GCFLGS_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_GCFLGS_R_C_C opc Cn Rd)" + by (unfold decode_GCFLGS_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_GCLEN_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_GCLEN_R_C_C d n)" + by (unfold execute_GCLEN_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_GCLEN_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_GCLEN_R_C_C opc Cn Rd)" + by (unfold decode_GCLEN_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_GCLIM_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_GCLIM_R_C_C d n)" + by (unfold execute_GCLIM_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_GCLIM_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_GCLIM_R_C_C opc Cn Rd)" + by (unfold decode_GCLIM_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_GCOFF_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_GCOFF_R_C_C d n)" + by (unfold execute_GCOFF_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_GCOFF_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_GCOFF_R_C_C opc Cn Rd)" + by (unfold decode_GCOFF_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_GCPERM_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_GCPERM_R_C_C d n)" + by (unfold execute_GCPERM_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_GCPERM_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_GCPERM_R_C_C opc Cn Rd)" + by (unfold decode_GCPERM_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_GCSEAL_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_GCSEAL_R_C_C d n)" + by (unfold execute_GCSEAL_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_GCSEAL_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_GCSEAL_R_C_C opc Cn Rd)" + by (unfold decode_GCSEAL_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_GCTAG_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_GCTAG_R_C_C d n)" + by (unfold execute_GCTAG_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_GCTAG_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_GCTAG_R_C_C opc Cn Rd)" + by (unfold decode_GCTAG_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_GCTYPE_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_GCTYPE_R_C_C d n)" + by (unfold execute_GCTYPE_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_GCTYPE_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_GCTYPE_R_C_C opc Cn Rd)" + by (unfold decode_GCTYPE_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_GCVALUE_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_GCVALUE_R_C_C d n)" + by (unfold execute_GCVALUE_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_GCVALUE_R_C_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_GCVALUE_R_C_C opc Cn Rd)" + by (unfold decode_GCVALUE_R_C_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDAPR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDAPR_C_R_C acctype n t__arg)" + by (unfold execute_LDAPR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDAPR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDAPR_C_R_C Rn Ct)" + by (unfold decode_LDAPR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDAR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDAR_C_R_C acctype n t__arg)" + by (unfold execute_LDAR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDAR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDAR_C_R_C L Rn Ct)" + by (unfold decode_LDAR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDAXP_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDAXP_C_R_C acctype n t__arg t2)" + by (unfold execute_LDAXP_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDAXP_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDAXP_C_R_C L Ct2 Rn Ct)" + by (unfold decode_LDAXP_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDAXR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDAXR_C_R_C acctype n t__arg)" + by (unfold execute_LDAXR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDAXR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDAXR_C_R_C L Rn Ct)" + by (unfold decode_LDAXR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDCT_R_R[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDCT_R_R n t__arg)" + by (unfold execute_LDCT_R_R_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDCT_R_R[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDCT_R_R opc Rn Rt)" + by (unfold decode_LDCT_R_R_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDNP_C_RIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDNP_C_RIB_C acctype n offset t__arg t2)" + by (unfold execute_LDNP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDNP_C_RIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDNP_C_RIB_C L imm7 Ct2 Rn Ct)" + by (unfold decode_LDNP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDP_CC_RIAW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDP_CC_RIAW_C acctype n offset t__arg t2)" + by (unfold execute_LDP_CC_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDP_CC_RIAW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDP_CC_RIAW_C L imm7 Ct2 Rn Ct)" + by (unfold decode_LDP_CC_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDP_C_RIBW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDP_C_RIBW_C acctype n offset t__arg t2)" + by (unfold execute_LDP_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDP_C_RIBW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDP_C_RIBW_C L imm7 Ct2 Rn Ct)" + by (unfold decode_LDP_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDP_C_RIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDP_C_RIB_C acctype n offset t__arg t2)" + by (unfold execute_LDP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDP_C_RIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDP_C_RIB_C L imm7 Ct2 Rn Ct)" + by (unfold decode_LDP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDR_C_I_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDR_C_I_C offset t__arg)" + by (unfold execute_LDR_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDR_C_I_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDR_C_I_C imm17 Ct)" + by (unfold decode_LDR_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDR_C_RIAW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDR_C_RIAW_C n offset t__arg)" + by (unfold execute_LDR_C_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDR_C_RIAW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDR_C_RIAW_C opc imm9 Rn Ct)" + by (unfold decode_LDR_C_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDR_C_RIBW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDR_C_RIBW_C n offset t__arg)" + by (unfold execute_LDR_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDR_C_RIBW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDR_C_RIBW_C opc imm9 Rn Ct)" + by (unfold decode_LDR_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDR_C_RRB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDR_C_RRB_C extend_type m n shift t__arg)" + by (unfold execute_LDR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDR_C_RRB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDR_C_RRB_C opc Rm sign sz S Rn Ct)" + by (unfold decode_LDR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDR_C_RUIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDR_C_RUIB_C n offset t__arg)" + by (unfold execute_LDR_C_RUIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDR_C_RUIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDR_C_RUIB_C L imm12 Rn Ct)" + by (unfold decode_LDR_C_RUIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDTR_C_RIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDTR_C_RIB_C n offset t__arg)" + by (unfold execute_LDTR_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDTR_C_RIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDTR_C_RIB_C opc imm9 Rn Ct)" + by (unfold decode_LDTR_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDUR_C_RI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDUR_C_RI_C n offset t__arg)" + by (unfold execute_LDUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDUR_C_RI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDUR_C_RI_C opc imm9 Rn Ct)" + by (unfold decode_LDUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDXP_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDXP_C_R_C acctype n t__arg t2)" + by (unfold execute_LDXP_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDXP_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDXP_C_R_C L Ct2 Rn Ct)" + by (unfold decode_LDXP_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_LDXR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_LDXR_C_R_C acctype n t__arg)" + by (unfold execute_LDXR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_LDXR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_LDXR_C_R_C L Rn Ct)" + by (unfold decode_LDXR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_MRS_C_I_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_MRS_C_I_C sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg)" + by (unfold execute_MRS_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_MRS_C_I_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_MRS_C_I_C L o0 op1 CRn CRm op2 Ct)" + by (unfold decode_MRS_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_MSR_C_I_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_MSR_C_I_C sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg)" + by (unfold execute_MSR_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_MSR_C_I_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_MSR_C_I_C L o0 op1 CRn CRm op2 Ct)" + by (unfold decode_MSR_C_I_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ORRFLGS_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ORRFLGS_C_CI_C d mask__arg n)" + by (unfold execute_ORRFLGS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ORRFLGS_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ORRFLGS_C_CI_C imm8 Cn Cd)" + by (unfold decode_ORRFLGS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_ORRFLGS_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_ORRFLGS_C_CR_C d m n)" + by (unfold execute_ORRFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ORRFLGS_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ORRFLGS_C_CR_C Rm opc Cn Cd)" + by (unfold decode_ORRFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_RRLEN_R_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_RRLEN_R_R_C d n)" + by (unfold execute_RRLEN_R_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_RRLEN_R_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_RRLEN_R_R_C opc Rn Rd)" + by (unfold decode_RRLEN_R_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_RRMASK_R_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_RRMASK_R_R_C d n)" + by (unfold execute_RRMASK_R_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_RRMASK_R_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_RRMASK_R_R_C opc Rn Rd)" + by (unfold decode_RRMASK_R_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SCBNDSE_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SCBNDSE_C_CR_C d m n)" + by (unfold execute_SCBNDSE_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SCBNDSE_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SCBNDSE_C_CR_C Rm opc Cn Cd)" + by (unfold decode_SCBNDSE_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SCBNDS_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SCBNDS_C_CI_C d length__arg n)" + by (unfold execute_SCBNDS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SCBNDS_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SCBNDS_C_CI_C imm6 S Cn Cd)" + by (unfold decode_SCBNDS_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SCBNDS_C_CI_S[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SCBNDS_C_CI_S d length__arg n)" + by (unfold execute_SCBNDS_C_CI_S_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SCBNDS_C_CI_S[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SCBNDS_C_CI_S imm6 S Cn Cd)" + by (unfold decode_SCBNDS_C_CI_S_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SCBNDS_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SCBNDS_C_CR_C d m n)" + by (unfold execute_SCBNDS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SCBNDS_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SCBNDS_C_CR_C Rm opc Cn Cd)" + by (unfold decode_SCBNDS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SCFLGS_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SCFLGS_C_CR_C d m n)" + by (unfold execute_SCFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SCFLGS_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SCFLGS_C_CR_C Rm Cn Cd)" + by (unfold decode_SCFLGS_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SCOFF_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SCOFF_C_CR_C d m n)" + by (unfold execute_SCOFF_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SCOFF_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SCOFF_C_CR_C Rm opc Cn Cd)" + by (unfold decode_SCOFF_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SCTAG_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SCTAG_C_CR_C d m n)" + by (unfold execute_SCTAG_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SCTAG_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SCTAG_C_CR_C Rm Cn Cd)" + by (unfold decode_SCTAG_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SCVALUE_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SCVALUE_C_CR_C d m n)" + by (unfold execute_SCVALUE_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SCVALUE_C_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SCVALUE_C_CR_C Rm opc Cn Cd)" + by (unfold decode_SCVALUE_C_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SEAL_C_CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SEAL_C_CC_C d m n)" + by (unfold execute_SEAL_C_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SEAL_C_CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SEAL_C_CC_C Cm opc Cn Cd)" + by (unfold decode_SEAL_C_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SEAL_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SEAL_C_CI_C d f n)" + by (unfold execute_SEAL_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SEAL_C_CI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SEAL_C_CI_C form Cn Cd)" + by (unfold decode_SEAL_C_CI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STCT_R_R[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STCT_R_R n t__arg)" + by (unfold execute_STCT_R_R_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STCT_R_R[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STCT_R_R opc Rn Rt)" + by (unfold decode_STCT_R_R_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STLR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STLR_C_R_C acctype n t__arg)" + by (unfold execute_STLR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STLR_C_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STLR_C_R_C L Rn Ct)" + by (unfold decode_STLR_C_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STLXP_R_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STLXP_R_CR_C acctype n s__arg t__arg t2)" + by (unfold execute_STLXP_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STLXP_R_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STLXP_R_CR_C L Rs__arg Ct2 Rn Ct)" + by (unfold decode_STLXP_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STLXR_R_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STLXR_R_CR_C acctype n s__arg t__arg)" + by (unfold execute_STLXR_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STLXR_R_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STLXR_R_CR_C L Rs__arg Rn Ct)" + by (unfold decode_STLXR_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STNP_C_RIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STNP_C_RIB_C acctype n offset t__arg t2)" + by (unfold execute_STNP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STNP_C_RIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STNP_C_RIB_C L imm7 Ct2 Rn Ct)" + by (unfold decode_STNP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STP_CC_RIAW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STP_CC_RIAW_C acctype n offset t__arg t2)" + by (unfold execute_STP_CC_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STP_CC_RIAW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STP_CC_RIAW_C L imm7 Ct2 Rn Ct)" + by (unfold decode_STP_CC_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STP_C_RIBW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STP_C_RIBW_C acctype n offset t__arg t2)" + by (unfold execute_STP_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STP_C_RIBW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STP_C_RIBW_C L imm7 Ct2 Rn Ct)" + by (unfold decode_STP_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STP_C_RIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STP_C_RIB_C acctype n offset t__arg t2)" + by (unfold execute_STP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STP_C_RIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STP_C_RIB_C L imm7 Ct2 Rn Ct)" + by (unfold decode_STP_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STR_C_RIAW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STR_C_RIAW_C n offset t__arg)" + by (unfold execute_STR_C_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STR_C_RIAW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STR_C_RIAW_C opc imm9 Rn Ct)" + by (unfold decode_STR_C_RIAW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STR_C_RIBW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STR_C_RIBW_C n offset t__arg)" + by (unfold execute_STR_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STR_C_RIBW_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STR_C_RIBW_C opc imm9 Rn Ct)" + by (unfold decode_STR_C_RIBW_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STR_C_RRB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STR_C_RRB_C extend_type m n shift t__arg)" + by (unfold execute_STR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STR_C_RRB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STR_C_RRB_C opc Rm sign sz S Rn Ct)" + by (unfold decode_STR_C_RRB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STR_C_RUIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STR_C_RUIB_C n offset t__arg)" + by (unfold execute_STR_C_RUIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STR_C_RUIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STR_C_RUIB_C L imm12 Rn Ct)" + by (unfold decode_STR_C_RUIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STTR_C_RIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STTR_C_RIB_C n offset t__arg)" + by (unfold execute_STTR_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STTR_C_RIB_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STTR_C_RIB_C opc imm9 Rn Ct)" + by (unfold decode_STTR_C_RIB_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STUR_C_RI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STUR_C_RI_C n offset t__arg)" + by (unfold execute_STUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STUR_C_RI_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STUR_C_RI_C opc imm9 Rn Ct)" + by (unfold decode_STUR_C_RI_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STXP_R_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STXP_R_CR_C acctype n s__arg t__arg t2)" + by (unfold execute_STXP_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STXP_R_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STXP_R_CR_C L Rs__arg Ct2 Rn Ct)" + by (unfold decode_STXP_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_STXR_R_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_STXR_R_CR_C acctype n s__arg t__arg)" + by (unfold execute_STXR_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_STXR_R_CR_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_STXR_R_CR_C L Rs__arg Rn Ct)" + by (unfold decode_STXR_R_CR_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SUBS_R_CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SUBS_R_CC_C d m n)" + by (unfold execute_SUBS_R_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SUBS_R_CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SUBS_R_CC_C Cm Cn Rd)" + by (unfold decode_SUBS_R_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SUB_C_CIS_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SUB_C_CIS_C d imm n)" + by (unfold execute_SUB_C_CIS_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SUB_C_CIS_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SUB_C_CIS_C A sh imm12 Cn Cd)" + by (unfold decode_SUB_C_CIS_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SWPAL_CC_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SWPAL_CC_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_SWPAL_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SWPAL_CC_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SWPAL_CC_R_C A R Cs Rn Ct)" + by (unfold decode_SWPAL_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SWPA_CC_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SWPA_CC_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_SWPA_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SWPA_CC_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SWPA_CC_R_C A R Cs Rn Ct)" + by (unfold decode_SWPA_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SWPL_CC_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SWPL_CC_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_SWPL_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SWPL_CC_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SWPL_CC_R_C A R Cs Rn Ct)" + by (unfold decode_SWPL_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_SWP_CC_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_SWP_CC_R_C ldacctype n s__arg stacctype t__arg)" + by (unfold execute_SWP_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_SWP_CC_R_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_SWP_CC_R_C A R Cs Rn Ct)" + by (unfold decode_SWP_CC_R_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_UNSEAL_C_CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_UNSEAL_C_CC_C d m n)" + by (unfold execute_UNSEAL_C_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_UNSEAL_C_CC_C[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_UNSEAL_C_CC_C Cm opc Cn Cd)" + by (unfold decode_UNSEAL_C_CC_C_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n neg)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd Rd Rn b__0 U b__1)" + by (unfold decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd Rd Rn b__0 U)" + by (unfold decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd Rd Rn Rm b__0 U)" + by (unfold decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow d datasize elements l__40 m n part round__arg sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_addhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_addhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_addhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_reduce_add_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_add_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_add_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_addp_advsimd_pair_aarch64_instrs_vector_reduce_add_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_addp_advsimd_pair_aarch64_instrs_vector_reduce_add_sisd Rd Rn b__0)" + by (unfold decode_addp_advsimd_pair_aarch64_instrs_vector_reduce_add_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair d l__179 elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_addp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_addp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair Rd Rn Rm b__0 b__1)" + by (unfold decode_addp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_reduce_add_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_add_simd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_add_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_addv_advsimd_aarch64_instrs_vector_reduce_add_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_addv_advsimd_aarch64_instrs_vector_reduce_add_simd Rd Rn b__0 b__1)" + by (unfold decode_addv_advsimd_aarch64_instrs_vector_reduce_add_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_aes_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_aes_round d decrypt n)" + by (unfold execute_aarch64_instrs_vector_crypto_aes_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_aesd_advsimd_aarch64_instrs_vector_crypto_aes_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_aesd_advsimd_aarch64_instrs_vector_crypto_aes_round Rd Rn D)" + by (unfold decode_aesd_advsimd_aarch64_instrs_vector_crypto_aes_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_aese_advsimd_aarch64_instrs_vector_crypto_aes_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_aese_advsimd_aarch64_instrs_vector_crypto_aes_round Rd Rn D)" + by (unfold decode_aese_advsimd_aarch64_instrs_vector_crypto_aes_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_aes_mix[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_aes_mix d decrypt n)" + by (unfold execute_aarch64_instrs_vector_crypto_aes_mix_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_aesimc_advsimd_aarch64_instrs_vector_crypto_aes_mix[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_aesimc_advsimd_aarch64_instrs_vector_crypto_aes_mix Rd Rn D)" + by (unfold decode_aesimc_advsimd_aarch64_instrs_vector_crypto_aes_mix_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_aesmc_advsimd_aarch64_instrs_vector_crypto_aes_mix[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_aesmc_advsimd_aarch64_instrs_vector_crypto_aes_mix Rd Rn D)" + by (unfold decode_aesmc_advsimd_aarch64_instrs_vector_crypto_aes_mix_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr d (datasize :: 'datasize::len itself) invert m n op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_and_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_and_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0)" + by (unfold decode_and_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3_bcax[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3_bcax a d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3_bcax_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_bcax_advsimd_aarch64_instrs_vector_crypto_sha3_bcax[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_bcax_advsimd_aarch64_instrs_vector_crypto_sha3_bcax Rd Rn Ra Rm)" + by (unfold decode_bcax_advsimd_aarch64_instrs_vector_crypto_sha3_bcax_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_logical[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_logical datasize imm operation rd)" + by (unfold execute_aarch64_instrs_vector_logical_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_bic_advsimd_imm_aarch64_instrs_vector_logical[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_bic_advsimd_imm_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_bic_advsimd_imm_aarch64_instrs_vector_logical_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_bic_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_bic_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0)" + by (unfold decode_bic_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor d (datasize :: 'datasize::len itself) m n op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_bif_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_bif_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0)" + by (unfold decode_bif_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_bit_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_bit_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0)" + by (unfold decode_bit_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_system_exceptions_debug_breakpoint[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (execute_aarch64_instrs_system_exceptions_debug_breakpoint comment)" + by (unfold execute_aarch64_instrs_system_exceptions_debug_breakpoint_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint imm16)" + by (unfold decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_bsl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_bsl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0)" + by (unfold decode_bsl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_atomicops_cas_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_atomicops_cas_single (datasize :: 'datasize::len itself) ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg)" + by (unfold execute_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cas_aarch64_instrs_memory_atomicops_cas_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cas_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs__arg L b__0)" + by (unfold decode_cas_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_casb_aarch64_instrs_memory_atomicops_cas_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_casb_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs__arg L b__0)" + by (unfold decode_casb_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cash_aarch64_instrs_memory_atomicops_cas_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cash_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs__arg L b__0)" + by (unfold decode_cash_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_atomicops_cas_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_atomicops_cas_pair l__38 ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg)" + by (unfold execute_aarch64_instrs_memory_atomicops_cas_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_casp_aarch64_instrs_memory_atomicops_cas_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_casp_aarch64_instrs_memory_atomicops_cas_pair Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_casp_aarch64_instrs_memory_atomicops_cas_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_clsz[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_clsz countop d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_clsz_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cls_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cls_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz Rd Rn b__0 U b__1)" + by (unfold decode_cls_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_clz_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_clz_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz Rd Rn b__0 U b__1)" + by (unfold decode_clz_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd and_test d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd Rd Rn Rm b__0 U)" + by (unfold decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd cmp_eq d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1)" + by (unfold decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U)" + by (unfold decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1)" + by (unfold decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U)" + by (unfold decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1)" + by (unfold decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U)" + by (unfold decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1)" + by (unfold decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U)" + by (unfold decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_simd Rd Rn b__0 b__1)" + by (unfold decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd Rd Rn b__0)" + by (unfold decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd Rd Rn Rm b__0 U)" + by (unfold decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_cnt[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_cnt d (datasize :: 'datasize::len itself) elements esize n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cnt_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_cnt_advsimd_aarch64_instrs_vector_arithmetic_unary_cnt[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_cnt_advsimd_aarch64_instrs_vector_arithmetic_unary_cnt Rd Rn size__arg b__0)" + by (unfold decode_cnt_advsimd_aarch64_instrs_vector_arithmetic_unary_cnt_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg n)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_simd Rd Rn b__0 b__1)" + by (unfold decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd Rd Rn b__0)" + by (unfold decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_transfer_integer_dup[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_integer_dup d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_transfer_integer_dup_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_dup_advsimd_gen_aarch64_instrs_vector_transfer_integer_dup[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_dup_advsimd_gen_aarch64_instrs_vector_transfer_integer_dup Rd Rn b__0 b__1)" + by (unfold decode_dup_advsimd_gen_aarch64_instrs_vector_transfer_integer_dup_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3_eor3[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3_eor3 a d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3_eor3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_eor3_advsimd_aarch64_instrs_vector_crypto_sha3_eor3[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_eor3_advsimd_aarch64_instrs_vector_crypto_sha3_eor3 Rd Rn Ra Rm)" + by (unfold decode_eor3_advsimd_aarch64_instrs_vector_crypto_sha3_eor3_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_eor_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_eor_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0)" + by (unfold decode_eor_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_system_hints[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_system_hints op)" + by (cases op; simp; no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_esb_aarch64_instrs_system_hints[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_esb_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_esb_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_extract[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_extract d l__47 m n position)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_extract_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ext_advsimd_aarch64_instrs_vector_transfer_vector_extract[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ext_advsimd_aarch64_instrs_vector_transfer_vector_extract Rd Rn imm4 Rm b__0)" + by (unfold decode_ext_advsimd_aarch64_instrs_vector_transfer_vector_extract_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd abs__arg d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd Rd Rn Rm U b__0)" + by (unfold decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd Rd Rn Rm)" + by (unfold decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_sisd Rd Rn Rm b__0)" + by (unfold decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n neg)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float Rd Rn b__0 U b__1)" + by (unfold decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16 Rd Rn U b__0)" + by (unfold decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_unary[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_unary d (datasize :: 'datasize::len itself) fpop n)" + by (unfold execute_aarch64_instrs_float_arithmetic_unary_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fabs_float_aarch64_instrs_float_arithmetic_unary[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fabs_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0)" + by (unfold decode_fabs_float_aarch64_instrs_float_arithmetic_unary_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd abs__arg cmp d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16 d l__163 elements (esize :: 'esize::len itself) m n pair)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp Rd Rn Rm b__0 U b__1)" + by (unfold decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16 Rd Rn Rm U b__0)" + by (unfold decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_add_sub[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_add_sub d (datasize :: 'datasize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_float_arithmetic_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fadd_float_aarch64_instrs_float_arithmetic_add_sub[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fadd_float_aarch64_instrs_float_arithmetic_add_sub Rd Rn op Rm b__0)" + by (unfold decode_fadd_float_aarch64_instrs_float_arithmetic_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_reduce_fp16_add_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_fp16_add_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_add_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_add_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_add_sisd Rd Rn sz)" + by (unfold decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_add_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp_add_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp_add_sisd Rd Rn b__0)" + by (unfold decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp_add_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp Rd Rn Rm b__0 U b__1)" + by (unfold decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16 Rd Rn Rm U b__0)" + by (unfold decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_compare_cond[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_compare_cond condition (datasize :: 'datasize::len itself) flags__arg m n signal_all_nans)" + by (unfold execute_aarch64_instrs_float_compare_cond_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fccmp_float_aarch64_instrs_float_compare_cond[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fccmp_float_aarch64_instrs_float_compare_cond nzcv op Rn cond Rm b__0)" + by (unfold decode_fccmp_float_aarch64_instrs_float_compare_cond_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fccmpe_float_aarch64_instrs_float_compare_cond[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fccmpe_float_aarch64_instrs_float_compare_cond nzcv op Rn cond Rm b__0)" + by (unfold decode_fccmpe_float_aarch64_instrs_float_compare_cond_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0)" + by (unfold decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U)" + by (unfold decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0)" + by (unfold decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U)" + by (unfold decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0)" + by (unfold decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U)" + by (unfold decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0)" + by (unfold decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U)" + by (unfold decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_simd Rd Rn b__0 b__1)" + by (unfold decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_sisd Rd Rn b__0)" + by (unfold decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_simd Rd Rn b__0)" + by (unfold decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd Rd Rn)" + by (unfold decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_compare_uncond[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_compare_uncond cmp_with_zero (datasize :: 'datasize::len itself) m n signal_all_nans)" + by (unfold execute_aarch64_instrs_float_compare_uncond_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmp_float_aarch64_instrs_float_compare_uncond[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmp_float_aarch64_instrs_float_compare_uncond opc Rn Rm b__0)" + by (unfold decode_fcmp_float_aarch64_instrs_float_compare_uncond_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcmpe_float_aarch64_instrs_float_compare_uncond[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcmpe_float_aarch64_instrs_float_compare_uncond opc Rn Rm b__0)" + by (unfold decode_fcmpe_float_aarch64_instrs_float_compare_uncond_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_move_fp_select[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_move_fp_select condition d (datasize :: 'datasize::len itself) m n)" + by (unfold execute_aarch64_instrs_float_move_fp_select_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcsel_float_aarch64_instrs_float_move_fp_select[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcsel_float_aarch64_instrs_float_move_fp_select Rd Rn cond Rm b__0)" + by (unfold decode_fcsel_float_aarch64_instrs_float_move_fp_select_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_convert_fp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_convert_fp d (dstsize :: 'dstsize::len itself) n (srcsize :: 'srcsize::len itself))" + by (unfold execute_aarch64_instrs_float_convert_fp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvt_float_aarch64_instrs_float_convert_fp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvt_float_aarch64_instrs_float_convert_fp Rd Rn b__0 b__1)" + by (unfold decode_fcvt_float_aarch64_instrs_float_convert_fp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n rounding is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd Rd Rn b__0 U b__1)" + by (unfold decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd Rd Rn b__0 U)" + by (unfold decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd Rd Rn U b__0)" + by (unfold decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd Rd Rn U)" + by (unfold decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_convert_int d (fltsize :: 'fltsize::len itself) (intsize :: 'intsize::len itself) n op part rounding is_unsigned)" + by (unfold execute_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtas_float_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtas_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtas_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd Rd Rn b__0 U b__1)" + by (unfold decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd Rd Rn b__0 U)" + by (unfold decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd Rd Rn U b__0)" + by (unfold decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd Rd Rn U)" + by (unfold decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtau_float_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtau_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtau_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_float_widen[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_float_widen d datasize elements l__177 n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_float_widen_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtl_advsimd_aarch64_instrs_vector_arithmetic_unary_float_widen[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtl_advsimd_aarch64_instrs_vector_arithmetic_unary_float_widen Rd Rn b__0 Q)" + by (unfold decode_fcvtl_advsimd_aarch64_instrs_vector_arithmetic_unary_float_widen_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n rounding is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtms_float_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtms_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtms_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtmu_float_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtmu_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtmu_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_float_narrow[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_float_narrow d datasize elements l__202 n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_float_narrow_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_narrow[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_narrow Rd Rn b__0 Q)" + by (unfold decode_fcvtn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_narrow_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtns_float_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtns_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtns_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtnu_float_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtnu_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtnu_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtps_float_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtps_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtps_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtpu_float_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtpu_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtpu_float_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd d l__53 elements esize n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_simd Rd Rn sz Q)" + by (unfold decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd Rd Rn sz)" + by (unfold decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_shift_conv_float_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_conv_float_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) fracbits n rounding is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_conv_float_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd Rd Rn immb b__0 U b__1)" + by (unfold decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd Rd Rn immb b__0 U)" + by (unfold decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_convert_fix[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_convert_fix d (fltsize :: 'fltsize::len itself) fracbits (intsize :: 'intsize::len itself) n op rounding is_unsigned)" + by (unfold execute_aarch64_instrs_float_convert_fix_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzs_float_fix_aarch64_instrs_float_convert_fix[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzs_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1)" + by (unfold decode_fcvtzs_float_fix_aarch64_instrs_float_convert_fix_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzs_float_int_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzs_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtzs_float_int_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd Rd Rn immb b__0 U b__1)" + by (unfold decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd Rd Rn immb b__0 U)" + by (unfold decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzu_float_fix_aarch64_instrs_float_convert_fix[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzu_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1)" + by (unfold decode_fcvtzu_float_fix_aarch64_instrs_float_convert_fix_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fcvtzu_float_int_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fcvtzu_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtzu_float_int_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div Rd Rn Rm b__0 b__1)" + by (unfold decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16 Rd Rn Rm b__0)" + by (unfold decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_div[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_div d (datasize :: 'datasize::len itself) m n)" + by (unfold execute_aarch64_instrs_float_arithmetic_div_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fdiv_float_aarch64_instrs_float_arithmetic_div[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fdiv_float_aarch64_instrs_float_arithmetic_div Rd Rn Rm b__0)" + by (unfold decode_fdiv_float_aarch64_instrs_float_arithmetic_div_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fjcvtzs_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fjcvtzs_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fjcvtzs_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_mul_add_sub[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_mul_add_sub a d (datasize :: 'datasize::len itself) m n op1_neg opa_neg)" + by (unfold execute_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0)" + by (unfold decode_fmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 d l__401 elements (esize :: 'esize::len itself) m minimum n pair)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0)" + by (unfold decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_max_min[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_max_min d (datasize :: 'datasize::len itself) m n operation)" + by (unfold execute_aarch64_instrs_float_arithmetic_max_min_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmax_float_aarch64_instrs_float_arithmetic_max_min[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmax_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0)" + by (unfold decode_fmax_float_aarch64_instrs_float_arithmetic_max_min_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 d l__435 elements (esize :: 'esize::len itself) m minimum n pair)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0)" + by (unfold decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxnm_float_aarch64_instrs_float_arithmetic_max_min[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxnm_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0)" + by (unfold decode_fmaxnm_float_aarch64_instrs_float_arithmetic_max_min_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_reduce_fp16_maxnm_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_fp16_maxnm_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_maxnm_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd Rd Rn sz o1)" + by (unfold decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd Rd Rn b__0 o1)" + by (unfold decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0)" + by (unfold decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_reduce_fp16_maxnm_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_fp16_maxnm_simd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_maxnm_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd Rd Rn o1 b__0)" + by (unfold decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd Rd Rn b__0 o1 b__1)" + by (unfold decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_reduce_fp16_max_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_fp16_max_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_max_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd Rd Rn sz o1)" + by (unfold decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd Rd Rn b__0 o1)" + by (unfold decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0)" + by (unfold decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_reduce_fp16_max_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_fp16_max_simd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_max_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd Rd Rn o1 b__0)" + by (unfold decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd Rd Rn b__0 o1 b__1)" + by (unfold decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0)" + by (unfold decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmin_float_aarch64_instrs_float_arithmetic_max_min[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmin_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0)" + by (unfold decode_fmin_float_aarch64_instrs_float_arithmetic_max_min_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0)" + by (unfold decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminnm_float_aarch64_instrs_float_arithmetic_max_min[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminnm_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0)" + by (unfold decode_fminnm_float_aarch64_instrs_float_arithmetic_max_min_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd Rd Rn sz o1)" + by (unfold decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd Rd Rn b__0 o1)" + by (unfold decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0)" + by (unfold decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd Rd Rn o1 b__0)" + by (unfold decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd Rd Rn b__0 o1 b__1)" + by (unfold decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd Rd Rn sz o1)" + by (unfold decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd Rd Rn b__0 o1)" + by (unfold decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0)" + by (unfold decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd Rd Rn o1 b__0)" + by (unfold decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd Rd Rn b__0 o1 b__1)" + by (unfold decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd Rd Rn b__0 o2 Rm M L)" + by (unfold decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd Rd Rn b__0 o2 Rm M L b__1 b__2)" + by (unfold decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused Rd Rn Rm a b__0)" + by (unfold decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused Rd Rn Rm b__0 op b__1)" + by (unfold decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd Rd Rn b__0 o2 Rm M L)" + by (unfold decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd Rd Rn b__0 o2 Rm M L b__1 b__2)" + by (unfold decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused Rd Rn Rm a b__0)" + by (unfold decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused Rd Rn Rm b__0 op b__1)" + by (unfold decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_fp16_movi[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_fp16_movi datasize imm rd)" + by (unfold execute_aarch64_instrs_vector_fp16_movi_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmov_advsimd_aarch64_instrs_vector_fp16_movi[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmov_advsimd_aarch64_instrs_vector_fp16_movi Rd h g f e d c__arg b a b__0)" + by (unfold decode_fmov_advsimd_aarch64_instrs_vector_fp16_movi_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmov_advsimd_aarch64_instrs_vector_logical[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmov_advsimd_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_fmov_advsimd_aarch64_instrs_vector_logical_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmov_float_aarch64_instrs_float_arithmetic_unary[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmov_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0)" + by (unfold decode_fmov_float_aarch64_instrs_float_arithmetic_unary_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmov_float_gen_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmov_float_gen_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fmov_float_gen_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_move_fp_imm[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_move_fp_imm d datasize imm)" + by (unfold execute_aarch64_instrs_float_move_fp_imm_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmov_float_imm_aarch64_instrs_float_move_fp_imm[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmov_float_imm_aarch64_instrs_float_move_fp_imm Rd imm8 b__0)" + by (unfold decode_fmov_float_imm_aarch64_instrs_float_move_fp_imm_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0)" + by (unfold decode_fmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m mulx_op n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd Rd Rn b__0 Rm M L U b__1)" + by (unfold decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd Rd Rn b__0 Rm M L U)" + by (unfold decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd Rd Rn b__0 Rm M L b__1 U b__2)" + by (unfold decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd Rd Rn b__0 Rm M L b__1 U)" + by (unfold decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product Rd Rn Rm b__0)" + by (unfold decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_product[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_product Rd Rn Rm b__0 b__1)" + by (unfold decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_product_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_mul_product[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_mul_product d (datasize :: 'datasize::len itself) m n negated)" + by (unfold execute_aarch64_instrs_float_arithmetic_mul_product_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmul_float_aarch64_instrs_float_arithmetic_mul_product[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmul_float_aarch64_instrs_float_arithmetic_mul_product Rd Rn op Rm b__0)" + by (unfold decode_fmul_float_aarch64_instrs_float_arithmetic_mul_product_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd Rd Rn b__0 Rm M L U b__1)" + by (unfold decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd Rd Rn b__0 Rm M L U)" + by (unfold decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd Rd Rn b__0 Rm M L b__1 U b__2)" + by (unfold decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd Rd Rn b__0 Rm M L b__1 U)" + by (unfold decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_simd Rd Rn Rm b__0)" + by (unfold decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd Rd Rn Rm)" + by (unfold decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_simd Rd Rn Rm b__0 b__1)" + by (unfold decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_sisd Rd Rn Rm b__0)" + by (unfold decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float Rd Rn b__0 U b__1)" + by (unfold decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16 Rd Rn U b__0)" + by (unfold decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fneg_float_aarch64_instrs_float_arithmetic_unary[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fneg_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0)" + by (unfold decode_fneg_float_aarch64_instrs_float_arithmetic_unary_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fnmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fnmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0)" + by (unfold decode_fnmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fnmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fnmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0)" + by (unfold decode_fnmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fnmul_float_aarch64_instrs_float_arithmetic_mul_product[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fnmul_float_aarch64_instrs_float_arithmetic_mul_product Rd Rn op Rm b__0)" + by (unfold decode_fnmul_float_aarch64_instrs_float_arithmetic_mul_product_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_simd Rd Rn b__0 b__1)" + by (unfold decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_sisd Rd Rn b__0)" + by (unfold decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_simd Rd Rn b__0)" + by (unfold decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd Rd Rn)" + by (unfold decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_simd Rd Rn Rm b__0)" + by (unfold decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd Rd Rn Rm)" + by (unfold decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_simd Rd Rn Rm b__0 b__1)" + by (unfold decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_sisd Rd Rn Rm b__0)" + by (unfold decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx Rd Rn b__0)" + by (unfold decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16 Rd Rn)" + by (unfold decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_fp16_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_fp16_round d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) exact n rounding)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_float_arithmetic_round_frint[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_float_arithmetic_round_frint d (datasize :: 'datasize::len itself) exact n rounding)" + by (unfold execute_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frinta_float_aarch64_instrs_float_arithmetic_round_frint[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frinta_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frinta_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frinti_float_aarch64_instrs_float_arithmetic_round_frint[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frinti_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frinti_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintm_float_aarch64_instrs_float_arithmetic_round_frint[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintm_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintm_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintn_float_aarch64_instrs_float_arithmetic_round_frint[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintn_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintn_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintp_float_aarch64_instrs_float_arithmetic_round_frint[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintp_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintp_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintx_float_aarch64_instrs_float_arithmetic_round_frint[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintx_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintx_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frintz_float_aarch64_instrs_float_arithmetic_round_frint[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frintz_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintz_float_aarch64_instrs_float_arithmetic_round_frint_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_simd Rd Rn b__0 b__1)" + by (unfold decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_sisd Rd Rn b__0)" + by (unfold decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_simd Rd Rn b__0)" + by (unfold decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd Rd Rn)" + by (unfold decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_simd Rd Rn Rm b__0)" + by (unfold decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd Rd Rn Rm)" + by (unfold decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_simd Rd Rn Rm b__0 b__1)" + by (unfold decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_sisd Rd Rn Rm b__0)" + by (unfold decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt Rd Rn b__0 b__1)" + by (unfold decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16 Rd Rn b__0)" + by (unfold decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fsqrt_float_aarch64_instrs_float_arithmetic_unary[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fsqrt_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0)" + by (unfold decode_fsqrt_float_aarch64_instrs_float_arithmetic_unary_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd abs__arg d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd Rd Rn Rm U b__0)" + by (unfold decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_fsub_float_aarch64_instrs_float_arithmetic_add_sub[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_fsub_float_aarch64_instrs_float_arithmetic_add_sub Rd Rn op Rm b__0)" + by (unfold decode_fsub_float_aarch64_instrs_float_arithmetic_add_sub_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_hint_aarch64_instrs_system_hints[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_hint_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_hint_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_system_exceptions_runtime_hvc[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (execute_aarch64_instrs_system_exceptions_runtime_hvc imm)" + by (unfold execute_aarch64_instrs_system_exceptions_runtime_hvc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc imm16)" + by (unfold decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_insert[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_insert d dst_index (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) n src_index)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_insert_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ins_advsimd_elt_aarch64_instrs_vector_transfer_vector_insert[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ins_advsimd_elt_aarch64_instrs_vector_transfer_vector_insert Rd Rn imm4 imm5)" + by (unfold decode_ins_advsimd_elt_aarch64_instrs_vector_transfer_vector_insert_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_transfer_integer_insert[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_integer_insert d datasize (esize :: 'esize::len itself) index__arg n)" + by (unfold execute_aarch64_instrs_vector_transfer_integer_insert_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ins_advsimd_gen_aarch64_instrs_vector_transfer_integer_insert[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ins_advsimd_gen_aarch64_instrs_vector_transfer_integer_insert Rd Rn b__0)" + by (unfold decode_ins_advsimd_gen_aarch64_instrs_vector_transfer_integer_insert_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_vector_multiple_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_vector_multiple_no_wb (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m memop n rpt selem t__arg wback)" + by (unfold execute_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_vector_single_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_vector_single_no_wb (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) index__arg m memop n replicate__arg selem t__arg wback)" + by (unfold execute_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_atomicops_ld (datasize :: 'datasize::len itself) ldacctype n op (regsize :: 'regsize::len itself) s__arg stacctype t__arg)" + by (unfold execute_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldadd_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldadd_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldadd_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldaddb_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldaddb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldaddb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldaddh_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldaddh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldaddh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_ordered_rcpc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_ordered_rcpc acctype (datasize :: 'datasize::len itself) n (regsize :: 'regsize::len itself) t__arg)" + by (unfold execute_aarch64_instrs_memory_ordered_rcpc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldapr_aarch64_instrs_memory_ordered_rcpc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldapr_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs__arg b__0)" + by (unfold decode_ldapr_aarch64_instrs_memory_ordered_rcpc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldaprb_aarch64_instrs_memory_ordered_rcpc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldaprb_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs__arg b__0)" + by (unfold decode_ldaprb_aarch64_instrs_memory_ordered_rcpc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldaprh_aarch64_instrs_memory_ordered_rcpc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldaprh_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs__arg b__0)" + by (unfold decode_ldaprh_aarch64_instrs_memory_ordered_rcpc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_ordered[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_ordered acctype (datasize :: 'datasize::len itself) memop n (regsize :: 'regsize::len itself) t__arg)" + by (unfold execute_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldar_aarch64_instrs_memory_ordered[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldar_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldar_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldarb_aarch64_instrs_memory_ordered[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldarb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldarb_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldarh_aarch64_instrs_memory_ordered[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldarh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldarh_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_exclusive_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_exclusive_pair acctype l__197 elsize memop n pair (regsize :: 'regsize::len itself) s__arg t__arg t2)" + by (unfold execute_aarch64_instrs_memory_exclusive_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldaxp_aarch64_instrs_memory_exclusive_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldaxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldaxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_exclusive_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_exclusive_single acctype l__532 elsize memop n pair (regsize :: 'regsize::len itself) s__arg t__arg t2)" + by (unfold execute_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldaxr_aarch64_instrs_memory_exclusive_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldaxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldaxr_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldaxrb_aarch64_instrs_memory_exclusive_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldaxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldaxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldaxrh_aarch64_instrs_memory_exclusive_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldaxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldaxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldclr_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldclr_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldclr_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldclrb_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldclrb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldclrb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldclrh_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldclrh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldclrh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldeor_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldeor_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldeor_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldeorb_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldeorb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldeorb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldeorh_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldeorh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldeorh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldlar_aarch64_instrs_memory_ordered[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldlar_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldlar_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldlarb_aarch64_instrs_memory_ordered[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldlarb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldlarb_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldlarh_aarch64_instrs_memory_ordered[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldlarh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldlarh_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_pair_simdfp_no_alloc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_pair_simdfp_no_alloc acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback)" + by (unfold execute_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_pair_general_no_alloc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_pair_general_no_alloc acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback)" + by (unfold execute_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_pair_simdfp_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_pair_simdfp_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback)" + by (unfold execute_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_pair_general_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_pair_general_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex is_signed t__arg t2 wback__arg)" + by (unfold execute_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldp_gen_aarch64_instrs_memory_pair_general_offset[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldp_gen_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldp_gen_aarch64_instrs_memory_pair_general_offset_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldpsw_aarch64_instrs_memory_pair_general_offset[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldpsw_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldpsw_aarch64_instrs_memory_pair_general_offset_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg wback)" + by (unfold execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg)" + by (unfold execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_literal_simdfp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_literal_simdfp offset l__44 t__arg)" + by (unfold execute_aarch64_instrs_memory_literal_simdfp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp Rt imm19 opc)" + by (unfold decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_literal_general[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_literal_general memop offset is_signed l__200 t__arg)" + by (unfold execute_aarch64_instrs_memory_literal_general_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldr_lit_gen_aarch64_instrs_memory_literal_general[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldr_lit_gen_aarch64_instrs_memory_literal_general Rt imm19 opc)" + by (unfold decode_ldr_lit_gen_aarch64_instrs_memory_literal_general_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_single_simdfp_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_simdfp_register acctype (datasize :: 'datasize::len itself) extend_type m memop n postindex shift t__arg wback)" + by (unfold execute_aarch64_instrs_memory_single_simdfp_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_single_general_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_general_register acctype (datasize :: 'datasize::len itself) extend_type m memop n postindex (regsize :: 'regsize::len itself) shift is_signed t__arg wback__arg)" + by (unfold execute_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrb_reg_aarch64_instrs_memory_single_general_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldrb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrh_reg_aarch64_instrs_memory_single_general_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldrh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrsb_reg_aarch64_instrs_memory_single_general_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrsb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldrsb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrsh_reg_aarch64_instrs_memory_single_general_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrsh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldrsh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrsw_lit_aarch64_instrs_memory_literal_general[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrsw_lit_aarch64_instrs_memory_literal_general Rt imm19 opc)" + by (unfold decode_ldrsw_lit_aarch64_instrs_memory_literal_general_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldrsw_reg_aarch64_instrs_memory_single_general_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldrsw_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_ldrsw_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldset_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldset_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldset_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldsetb_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldsetb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsetb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldseth_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldseth_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldseth_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldsmax_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldsmax_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsmax_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldsmin_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldsmin_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsmin_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldsminb_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldsminb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsminb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldsminh_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldsminh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldsminh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg)" + by (unfold execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldumax_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldumax_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldumax_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldumaxb_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldumaxb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldumaxb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldumaxh_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldumaxh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldumaxh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldumin_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldumin_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_ldumin_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_lduminb_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_lduminb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_lduminb_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_lduminh_aarch64_instrs_memory_atomicops_ld[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_lduminh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs__arg R A b__0)" + by (unfold decode_lduminh_aarch64_instrs_memory_atomicops_ld_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg wback)" + by (unfold execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg)" + by (unfold execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldxp_aarch64_instrs_memory_exclusive_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldxr_aarch64_instrs_memory_exclusive_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldxr_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldxrb_aarch64_instrs_memory_exclusive_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ldxrh_aarch64_instrs_memory_exclusive_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ldxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_ldxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_mla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_mla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int Rd Rn b__0 o2 Rm M L b__1 b__2)" + by (unfold decode_mla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_mla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_mla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum Rd Rn Rm b__0 U b__1)" + by (unfold decode_mla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_mls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_mls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int Rd Rn b__0 o2 Rm M L b__1 b__2)" + by (unfold decode_mls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_mls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_mls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum Rd Rn Rm b__0 U b__1)" + by (unfold decode_mls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_movi_advsimd_aarch64_instrs_vector_logical[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_movi_advsimd_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_movi_advsimd_aarch64_instrs_vector_logical_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_msr_imm_aarch64_instrs_system_register_cpsr[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_msr_imm_aarch64_instrs_system_register_cpsr op2 CRm op1)" + by (unfold decode_msr_imm_aarch64_instrs_system_register_cpsr_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_int d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_mul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_mul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_int Rd Rn b__0 Rm M L b__1 b__2)" + by (unfold decode_mul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product d (datasize :: 'datasize::len itself) elements l__55 m n poly)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_mul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_mul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product Rd Rn Rm b__0 U b__1)" + by (unfold decode_mul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_mvni_advsimd_aarch64_instrs_vector_logical[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_mvni_advsimd_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_mvni_advsimd_aarch64_instrs_vector_logical_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd Rd Rn b__0 U b__1)" + by (unfold decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd Rd Rn b__0 U)" + by (unfold decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_nop_aarch64_instrs_system_hints[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_nop_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_nop_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_not[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_not d (datasize :: 'datasize::len itself) elements esize n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_not_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_not_advsimd_aarch64_instrs_vector_arithmetic_unary_not[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_not_advsimd_aarch64_instrs_vector_arithmetic_unary_not Rd Rn b__0)" + by (unfold decode_not_advsimd_aarch64_instrs_vector_arithmetic_unary_not_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_orn_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_orn_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0)" + by (unfold decode_orn_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_orr_advsimd_imm_aarch64_instrs_vector_logical[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_orr_advsimd_imm_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_orr_advsimd_imm_aarch64_instrs_vector_logical_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_orr_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_orr_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0)" + by (unfold decode_orr_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_pmul_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_pmul_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product Rd Rn Rm b__0 U b__1)" + by (unfold decode_pmul_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly d datasize elements l__379 m n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_pmull_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_pmull_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly Rd Rn Rm b__0 Q)" + by (unfold decode_pmull_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_single_general_immediate_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_single_general_immediate_unsigned acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg)" + by (unfold execute_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_prfm_lit_aarch64_instrs_memory_literal_general[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_prfm_lit_aarch64_instrs_memory_literal_general Rt imm19 opc)" + by (unfold decode_prfm_lit_aarch64_instrs_memory_literal_general_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_prfm_reg_aarch64_instrs_memory_single_general_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_prfm_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_prfm_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_psb_aarch64_instrs_system_hints[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_psb_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_psb_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_raddhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_raddhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_raddhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3_rax1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3_rax1 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3_rax1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_rax1_advsimd_aarch64_instrs_vector_crypto_sha3_rax1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_rax1_advsimd_aarch64_instrs_vector_crypto_sha3_rax1 Rd Rn Rm)" + by (unfold decode_rax1_advsimd_aarch64_instrs_vector_crypto_sha3_rax1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_rev[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_rev containers d (datasize :: 'datasize::len itself) elements_per_container (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_rev_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_rev16_advsimd_aarch64_instrs_vector_arithmetic_unary_rev[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_rev16_advsimd_aarch64_instrs_vector_arithmetic_unary_rev Rd Rn o0 b__0 U b__1)" + by (unfold decode_rev16_advsimd_aarch64_instrs_vector_arithmetic_unary_rev_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_rev32_advsimd_aarch64_instrs_vector_arithmetic_unary_rev[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_rev32_advsimd_aarch64_instrs_vector_arithmetic_unary_rev Rd Rn o0 b__0 U b__1)" + by (unfold decode_rev32_advsimd_aarch64_instrs_vector_arithmetic_unary_rev_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_rev64_advsimd_aarch64_instrs_vector_arithmetic_unary_rev[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_rev64_advsimd_aarch64_instrs_vector_arithmetic_unary_rev Rd Rn o0 b__0 U b__1)" + by (unfold decode_rev64_advsimd_aarch64_instrs_vector_arithmetic_unary_rev_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_shift_right_narrow_logical[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_right_narrow_logical d datasize elements l__473 n part round__arg shift)" + by (unfold execute_aarch64_instrs_vector_shift_right_narrow_logical_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_rshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_rshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical Rd Rn op immb b__0 Q)" + by (unfold decode_rshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_rsubhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_rsubhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_rsubhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_diff[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_diff accumulate d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_saba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_saba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1)" + by (unfold decode_saba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_diff[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_diff accumulate d datasize elements l__469 m n part is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q)" + by (unfold decode_sabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1)" + by (unfold decode_sabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q)" + by (unfold decode_sabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_add_pairwise[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_add_pairwise acc d (datasize :: 'datasize::len itself) elements l__169 n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1)" + by (unfold decode_sadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long d datasize elements l__316 m n part sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_saddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_saddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_saddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_saddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_saddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1)" + by (unfold decode_saddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_reduce_add_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_add_long d (datasize :: 'datasize::len itself) elements l__159 n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_reduce_add_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_saddlv_advsimd_aarch64_instrs_vector_reduce_add_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_saddlv_advsimd_aarch64_instrs_vector_reduce_add_long Rd Rn b__0 U b__1)" + by (unfold decode_saddlv_advsimd_aarch64_instrs_vector_reduce_add_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide d datasize elements l__478 m n part sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_saddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_saddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_saddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_shift_conv_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_conv_int_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) fracbits n rounding is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd Rd Rn immb b__0 U b__1)" + by (unfold decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd Rd Rn immb b__0 U)" + by (unfold decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd Rd Rn b__0 U b__1)" + by (unfold decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd Rd Rn b__0 U)" + by (unfold decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd Rd Rn U b__0)" + by (unfold decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd Rd Rn U)" + by (unfold decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_scvtf_float_fix_aarch64_instrs_float_convert_fix[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_scvtf_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1)" + by (unfold decode_scvtf_float_fix_aarch64_instrs_float_convert_fix_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_scvtf_float_int_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_scvtf_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_scvtf_float_int_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_dotp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_dotp d (datasize :: 'datasize::len itself) elements l__375 index__arg m n is_signed)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_dotp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sdot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sdot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp Rd Rn H Rm M L b__0 U b__1)" + by (unfold decode_sdot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp d (datasize :: 'datasize::len itself) elements l__165 m n is_signed)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sdot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sdot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp Rd Rn Rm b__0 U b__1)" + by (unfold decode_sdot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sev_aarch64_instrs_system_hints[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sev_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_sev_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sevl_aarch64_instrs_system_hints[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sevl_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_sevl_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha1c_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha1c_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose Rd Rn Rm)" + by (unfold decode_sha1c_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha2op_sha1_hash[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha2op_sha1_hash d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha2op_sha1_hash_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha1h_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_hash[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha1h_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_hash Rd Rn)" + by (unfold decode_sha1h_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_hash_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha1m_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha1m_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority Rd Rn Rm)" + by (unfold decode_sha1m_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha1p_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha1p_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity Rd Rn Rm)" + by (unfold decode_sha1p_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3op_sha1_sched0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3op_sha1_sched0 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha1_sched0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha1su0_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_sched0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha1su0_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_sched0 Rd Rn Rm)" + by (unfold decode_sha1su0_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_sched0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha2op_sha1_sched1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha2op_sha1_sched1 d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha2op_sha1_sched1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha1su1_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_sched1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha1su1_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_sched1 Rd Rn)" + by (unfold decode_sha1su1_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_sched1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3op_sha256_hash[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3op_sha256_hash d m n part1)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha256_hash_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha256h2_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha256h2_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash Rd Rn P Rm)" + by (unfold decode_sha256h2_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha256h_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha256h_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash Rd Rn P Rm)" + by (unfold decode_sha256h_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha2op_sha256_sched0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha2op_sha256_sched0 d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha2op_sha256_sched0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha256su0_advsimd_aarch64_instrs_vector_crypto_sha2op_sha256_sched0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha256su0_advsimd_aarch64_instrs_vector_crypto_sha2op_sha256_sched0 Rd Rn)" + by (unfold decode_sha256su0_advsimd_aarch64_instrs_vector_crypto_sha2op_sha256_sched0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3op_sha256_sched1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3op_sha256_sched1 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha256_sched1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha256su1_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_sched1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha256su1_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_sched1 Rd Rn Rm)" + by (unfold decode_sha256su1_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_sched1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha512_sha512h2[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha512_sha512h2 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha512_sha512h2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha512h2_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h2[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha512h2_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h2 Rd Rn Rm)" + by (unfold decode_sha512h2_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha512_sha512h[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha512_sha512h d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha512_sha512h_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha512h_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha512h_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h Rd Rn Rm)" + by (unfold decode_sha512h_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha512_sha512su0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha512_sha512su0 d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha512_sha512su0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha512su0_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su0[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha512su0_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su0 Rd Rn)" + by (unfold decode_sha512su0_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su0_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha512_sha512su1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha512_sha512su1 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha512_sha512su1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sha512su1_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sha512su1_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su1 Rd Rn Rm)" + by (unfold decode_sha512su1_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_shadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_shadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating Rd Rn Rm b__0 U b__1)" + by (unfold decode_shadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_shift_left_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_left_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n shift)" + by (unfold execute_aarch64_instrs_vector_shift_left_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_shl_advsimd_aarch64_instrs_vector_shift_left_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_shl_advsimd_aarch64_instrs_vector_shift_left_simd Rd Rn immb b__0 b__1)" + by (unfold decode_shl_advsimd_aarch64_instrs_vector_shift_left_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_shl_advsimd_aarch64_instrs_vector_shift_left_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_shl_advsimd_aarch64_instrs_vector_shift_left_sisd Rd Rn immb immh)" + by (unfold decode_shl_advsimd_aarch64_instrs_vector_shift_left_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_shift[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_shift d datasize elements l__49 n part shift is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_shift_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_shll_advsimd_aarch64_instrs_vector_arithmetic_unary_shift[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_shll_advsimd_aarch64_instrs_vector_arithmetic_unary_shift Rd Rn b__0 Q)" + by (unfold decode_shll_advsimd_aarch64_instrs_vector_arithmetic_unary_shift_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_shrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_shrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical Rd Rn op immb b__0 Q)" + by (unfold decode_shrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_shsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_shsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int Rd Rn Rm b__0 U b__1)" + by (unfold decode_shsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_shift_left_insert_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_left_insert_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n shift)" + by (unfold execute_aarch64_instrs_vector_shift_left_insert_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_simd Rd Rn immb b__0 b__1)" + by (unfold decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_sisd Rd Rn immb immh)" + by (unfold decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3partw1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3partw1 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3partw1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sm3partw1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sm3partw1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw1 Rd Rn Rm)" + by (unfold decode_sm3partw1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3partw2[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3partw2 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3partw2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sm3partw2_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw2[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sm3partw2_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw2 Rd Rn Rm)" + by (unfold decode_sm3partw2_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw2_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3ss1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3ss1 a d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3ss1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sm3ss1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3ss1[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sm3ss1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3ss1 Rd Rn Ra Rm)" + by (unfold decode_sm3ss1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3ss1_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3tt1a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3tt1a d i m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3tt1a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sm3tt1a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sm3tt1a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1a Rd Rn imm2 Rm)" + by (unfold decode_sm3tt1a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3tt1b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3tt1b d i m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3tt1b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sm3tt1b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sm3tt1b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1b Rd Rn imm2 Rm)" + by (unfold decode_sm3tt1b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3tt2a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3tt2a d i m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3tt2a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sm3tt2a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2a[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sm3tt2a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2a Rd Rn imm2 Rm)" + by (unfold decode_sm3tt2a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2a_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm3_sm3tt2b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm3_sm3tt2b d i m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3tt2b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sm3tt2b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2b[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sm3tt2b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2b Rd Rn imm2 Rm)" + by (unfold decode_sm3tt2b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2b_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm4_sm4enc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm4_sm4enc d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm4_sm4enc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sm4e_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sm4e_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enc Rd Rn)" + by (unfold decode_sm4e_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sm4_sm4enckey[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sm4_sm4enckey d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm4_sm4enckey_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sm4ekey_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enckey[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sm4ekey_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enckey Rd Rn Rm)" + by (unfold decode_sm4ekey_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enckey_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m minimum n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_smax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_smax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_smax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair d l__193 elements (esize :: 'esize::len itself) m minimum n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_smaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_smaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_smaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_reduce_int_max[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_reduce_int_max d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) min__arg n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_reduce_int_max_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_smaxv_advsimd_aarch64_instrs_vector_reduce_int_max[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_smaxv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1)" + by (unfold decode_smaxv_advsimd_aarch64_instrs_vector_reduce_int_max_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_system_exceptions_runtime_smc[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (execute_aarch64_instrs_system_exceptions_runtime_smc imm)" + by (unfold execute_aarch64_instrs_system_exceptions_runtime_smc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_smc_aarch64_instrs_system_exceptions_runtime_smc[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (decode_smc_aarch64_instrs_system_exceptions_runtime_smc imm16)" + by (unfold decode_smc_aarch64_instrs_system_exceptions_runtime_smc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_smin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_smin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_smin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_sminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sminv_advsimd_aarch64_instrs_vector_reduce_int_max[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sminv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1)" + by (unfold decode_sminv_advsimd_aarch64_instrs_vector_reduce_int_max_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long d datasize elements l__185 (idxdsize :: 'idxdsize::len itself) index__arg m n part sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_smlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_smlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q)" + by (unfold decode_smlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum d datasize elements l__537 m n part sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_smlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_smlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_smlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_smlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_smlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q)" + by (unfold decode_smlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_smlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_smlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_smlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_transfer_integer_move_signed[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_integer_move_signed d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg n)" + by (unfold execute_aarch64_instrs_vector_transfer_integer_move_signed_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_smov_advsimd_aarch64_instrs_vector_transfer_integer_move_signed[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_smov_advsimd_aarch64_instrs_vector_transfer_integer_move_signed Rd Rn b__0 b__1)" + by (unfold decode_smov_advsimd_aarch64_instrs_vector_transfer_integer_move_signed_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_long d datasize elements l__173 (idxdsize :: 'idxdsize::len itself) index__arg m n part is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_smull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_smull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long Rd Rn b__0 Rm M L b__1 U Q)" + by (unfold decode_smull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product d datasize elements l__189 m n part is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_smull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_smull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product Rd Rn Rm b__0 U Q)" + by (unfold decode_smull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n neg)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd Rd Rn b__0 U b__1)" + by (unfold decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd Rd Rn b__0 U)" + by (unfold decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd d l__403 elements l__404 (idxdsize :: 'idxdsize::len itself) index__arg m n part sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd Rd Rn b__0 o2 Rm M L b__1 Q)" + by (unfold decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd d l__437 elements l__438 m n part sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd Rd Rn o1 Rm b__0 Q)" + by (unfold decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd Rd Rn o1 Rm b__0)" + by (unfold decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd Rd Rn b__0 o2 Rm M L b__1 Q)" + by (unfold decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd Rd Rn o1 Rm b__0 Q)" + by (unfold decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd Rd Rn o1 Rm b__0)" + by (unfold decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n round__arg)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd Rd Rn b__0 op Rm M L b__1 b__2)" + by (unfold decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd Rd Rn b__0 op Rm M L b__1)" + by (unfold decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n rounding)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd d l__123 elements l__124 (idxdsize :: 'idxdsize::len itself) index__arg m n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_simd Rd Rn b__0 Rm M L b__1 Q)" + by (unfold decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd Rd Rn b__0 Rm M L b__1)" + by (unfold decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd d l__59 elements l__60 m n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_simd Rd Rn Rm b__0 Q)" + by (unfold decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd Rd Rn Rm b__0)" + by (unfold decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd Rd Rn b__0 U b__1)" + by (unfold decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd Rd Rn b__0 U)" + by (unfold decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n rounding sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd Rd Rn b__0 S Rm M L b__1 b__2)" + by (unfold decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd Rd Rn b__0 S Rm M L b__1)" + by (unfold decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n rounding sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd Rd Rn S Rm b__0 b__1)" + by (unfold decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd Rd Rn S Rm b__0)" + by (unfold decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd Rd Rn b__0 S Rm M L b__1 b__2)" + by (unfold decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd Rd Rn b__0 S Rm M L b__1)" + by (unfold decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd Rd Rn S Rm b__0 b__1)" + by (unfold decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd Rd Rn S Rm b__0)" + by (unfold decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd Rd Rn b__0 op Rm M L b__1 b__2)" + by (unfold decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd Rd Rn b__0 op Rm M L b__1)" + by (unfold decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n rounding saturating is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_right_narrow_uniform_sisd d l__325 elements l__326 n part round__arg shift is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q)" + by (unfold decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U)" + by (unfold decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd d l__482 elements l__483 n part round__arg shift)" + by (unfold execute_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd Rd Rn op immb b__0 Q)" + by (unfold decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd Rd Rn op immb b__0)" + by (unfold decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_shift_left_sat_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_left_sat_sisd d (datasize :: 'datasize::len itself) dst_unsigned elements (esize :: 'esize::len itself) n shift src_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_left_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd Rd Rn op immb b__0 U b__1)" + by (unfold decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd Rd Rn op immb b__0 U)" + by (unfold decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_simd Rd Rn op immb b__0 U b__1)" + by (unfold decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_sisd Rd Rn op immb b__0 U)" + by (unfold decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q)" + by (unfold decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U)" + by (unfold decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd Rd Rn op immb b__0 Q)" + by (unfold decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd Rd Rn op immb b__0)" + by (unfold decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd d l__91 elements l__92 n part is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd Rd Rn b__0 U Q)" + by (unfold decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd Rd Rn b__0 U)" + by (unfold decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd d l__4 elements l__5 n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_simd Rd Rn b__0 Q)" + by (unfold decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd Rd Rn b__0)" + by (unfold decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_srhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_srhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding Rd Rn Rm b__0 U b__1)" + by (unfold decode_srhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_shift_right_insert_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_right_insert_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n shift)" + by (unfold execute_aarch64_instrs_vector_shift_right_insert_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_simd Rd Rn immb b__0 b__1)" + by (unfold decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_sisd Rd Rn immb immh)" + by (unfold decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_shift_right_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_right_sisd accumulate d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n round__arg shift is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_srshr_advsimd_aarch64_instrs_vector_shift_right_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_srshr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_srshr_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_srshr_advsimd_aarch64_instrs_vector_shift_right_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_srshr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_srshr_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_srsra_advsimd_aarch64_instrs_vector_shift_right_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_srsra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_srsra_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_srsra_advsimd_aarch64_instrs_vector_shift_right_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_srsra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_srsra_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_shift_left_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_shift_left_long d datasize elements l__320 n part shift is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_left_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sshll_advsimd_aarch64_instrs_vector_shift_left_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sshll_advsimd_aarch64_instrs_vector_shift_left_long Rd Rn immb b__0 U Q)" + by (unfold decode_sshll_advsimd_aarch64_instrs_vector_shift_left_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sshr_advsimd_aarch64_instrs_vector_shift_right_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sshr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_sshr_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sshr_advsimd_aarch64_instrs_vector_shift_right_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sshr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_sshr_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ssra_advsimd_aarch64_instrs_vector_shift_right_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ssra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_ssra_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ssra_advsimd_aarch64_instrs_vector_shift_right_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ssra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_ssra_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ssubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ssubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_ssubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ssubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ssubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_ssubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)" + by (unfold decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)" + by (unfold decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)" + by (unfold decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)" + by (unfold decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_atomicops_st (datasize :: 'datasize::len itself) ldacctype n op s__arg stacctype)" + by (unfold execute_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stadd_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stadd_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stadd_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_staddb_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_staddb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_staddb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_staddh_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_staddh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_staddh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stclr_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stclr_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stclr_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stclrb_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stclrb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stclrb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stclrh_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stclrh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stclrh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_steor_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_steor_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_steor_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_steorb_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_steorb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_steorb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_steorh_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_steorh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_steorh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stllr_aarch64_instrs_memory_ordered[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stllr_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stllr_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stllrb_aarch64_instrs_memory_ordered[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stllrb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stllrb_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stllrh_aarch64_instrs_memory_ordered[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stllrh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stllrh_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stlr_aarch64_instrs_memory_ordered[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stlr_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlr_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stlrb_aarch64_instrs_memory_ordered[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stlrb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlrb_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stlrh_aarch64_instrs_memory_ordered[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stlrh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlrh_aarch64_instrs_memory_ordered_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stlxp_aarch64_instrs_memory_exclusive_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stlxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stlxr_aarch64_instrs_memory_exclusive_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stlxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlxr_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stlxrb_aarch64_instrs_memory_exclusive_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stlxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stlxrh_aarch64_instrs_memory_exclusive_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stlxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stlxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stp_gen_aarch64_instrs_memory_pair_general_offset[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stp_gen_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stp_gen_aarch64_instrs_memory_pair_general_offset_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0)" + by (unfold decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_str_reg_gen_aarch64_instrs_memory_single_general_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_str_reg_gen_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_str_reg_gen_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_strb_reg_aarch64_instrs_memory_single_general_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_strb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_strb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)" + by (unfold decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)" + by (unfold decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_strh_reg_aarch64_instrs_memory_single_general_register[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_strh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)" + by (unfold decode_strh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stset_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stset_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stset_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stsetb_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stsetb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsetb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stseth_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stseth_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stseth_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stsmax_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stsmax_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsmax_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stsmaxb_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stsmaxb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsmaxb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stsmaxh_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stsmaxh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsmaxh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stsmin_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stsmin_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsmin_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stsminb_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stsminb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsminb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stsminh_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stsminh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stsminh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)" + by (unfold decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stumax_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stumax_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stumax_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stumaxb_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stumaxb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stumaxb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stumaxh_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stumaxh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stumaxh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stumin_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stumin_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stumin_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stuminb_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stuminb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stuminb_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stuminh_aarch64_instrs_memory_atomicops_st[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stuminh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs__arg R A V b__0)" + by (unfold decode_stuminh_aarch64_instrs_memory_atomicops_st_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)" + by (unfold decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stxp_aarch64_instrs_memory_exclusive_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stxr_aarch64_instrs_memory_exclusive_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stxr_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stxrb_aarch64_instrs_memory_exclusive_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_stxrh_aarch64_instrs_memory_exclusive_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_stxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs__arg L b__0)" + by (unfold decode_stxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_subhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_subhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_subhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd Rd Rn b__0 U b__1)" + by (unfold decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd Rd Rn b__0 U)" + by (unfold decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_system_exceptions_runtime_svc[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (execute_aarch64_instrs_system_exceptions_runtime_svc imm)" + by (unfold execute_aarch64_instrs_system_exceptions_runtime_svc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_svc_aarch64_instrs_system_exceptions_runtime_svc[runs_no_reg_writes_toI, simp]: + "runs_no_reg_writes_to Rs (decode_svc_aarch64_instrs_system_exceptions_runtime_svc imm16)" + by (unfold decode_svc_aarch64_instrs_system_exceptions_runtime_svc_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_memory_atomicops_swp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_memory_atomicops_swp (datasize :: 'datasize::len itself) ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg)" + by (unfold execute_aarch64_instrs_memory_atomicops_swp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_swp_aarch64_instrs_memory_atomicops_swp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_swp_aarch64_instrs_memory_atomicops_swp Rt Rn Rs__arg R A b__0)" + by (unfold decode_swp_aarch64_instrs_memory_atomicops_swp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_swpb_aarch64_instrs_memory_atomicops_swp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_swpb_aarch64_instrs_memory_atomicops_swp Rt Rn Rs__arg R A b__0)" + by (unfold decode_swpb_aarch64_instrs_memory_atomicops_swp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_swph_aarch64_instrs_memory_atomicops_swp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_swph_aarch64_instrs_memory_atomicops_swp Rt Rn Rs__arg R A b__0)" + by (unfold decode_swph_aarch64_instrs_memory_atomicops_swp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_system_sysops[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_system_sysops has_result sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg)" + by (unfold execute_aarch64_instrs_system_sysops_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sys_aarch64_instrs_system_sysops[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sys_aarch64_instrs_system_sysops Rt op2 CRm CRn op1 L)" + by (unfold decode_sys_aarch64_instrs_system_sysops_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_sysl_aarch64_instrs_system_sysops[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_sysl_aarch64_instrs_system_sysops Rt op2 CRm CRn op1 L)" + by (unfold decode_sysl_aarch64_instrs_system_sysops_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_table[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_table d (datasize :: 'datasize::len itself) elements is_tbl m n__arg l__181)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_table_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_tbl_advsimd_aarch64_instrs_vector_transfer_vector_table[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_tbl_advsimd_aarch64_instrs_vector_transfer_vector_table Rd Rn op len Rm b__0)" + by (unfold decode_tbl_advsimd_aarch64_instrs_vector_transfer_vector_table_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_tbx_advsimd_aarch64_instrs_vector_transfer_vector_table[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_tbx_advsimd_aarch64_instrs_vector_transfer_vector_table Rd Rn op len Rm b__0)" + by (unfold decode_tbx_advsimd_aarch64_instrs_vector_transfer_vector_table_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_permute_transpose[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_permute_transpose d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) m n pairs part)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_permute_transpose_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_trn1_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_trn1_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose Rd Rn op Rm b__0 b__1)" + by (unfold decode_trn1_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_trn2_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_trn2_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose Rd Rn op Rm b__0 b__1)" + by (unfold decode_trn2_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uaba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uaba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1)" + by (unfold decode_uaba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q)" + by (unfold decode_uabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1)" + by (unfold decode_uabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q)" + by (unfold decode_uabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1)" + by (unfold decode_uadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uaddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uaddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_uaddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uaddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uaddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1)" + by (unfold decode_uaddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uaddlv_advsimd_aarch64_instrs_vector_reduce_add_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uaddlv_advsimd_aarch64_instrs_vector_reduce_add_long Rd Rn b__0 U b__1)" + by (unfold decode_uaddlv_advsimd_aarch64_instrs_vector_reduce_add_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uaddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uaddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_uaddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd Rd Rn immb b__0 U b__1)" + by (unfold decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd Rd Rn immb b__0 U)" + by (unfold decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd Rd Rn b__0 U b__1)" + by (unfold decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd Rd Rn b__0 U)" + by (unfold decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd Rd Rn U b__0)" + by (unfold decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd Rd Rn U)" + by (unfold decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ucvtf_float_fix_aarch64_instrs_float_convert_fix[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ucvtf_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1)" + by (unfold decode_ucvtf_float_fix_aarch64_instrs_float_convert_fix_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ucvtf_float_int_aarch64_instrs_float_convert_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ucvtf_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_ucvtf_float_int_aarch64_instrs_float_convert_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_udot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_udot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp Rd Rn H Rm M L b__0 U b__1)" + by (unfold decode_udot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_udot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_udot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp Rd Rn Rm b__0 U b__1)" + by (unfold decode_udot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating Rd Rn Rm b__0 U b__1)" + by (unfold decode_uhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uhsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uhsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int Rd Rn Rm b__0 U b__1)" + by (unfold decode_uhsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_umax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_umax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_umax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_umaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_umaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_umaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_umaxv_advsimd_aarch64_instrs_vector_reduce_int_max[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_umaxv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1)" + by (unfold decode_umaxv_advsimd_aarch64_instrs_vector_reduce_int_max_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_umin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_umin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_umin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_uminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uminv_advsimd_aarch64_instrs_vector_reduce_int_max[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uminv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1)" + by (unfold decode_uminv_advsimd_aarch64_instrs_vector_reduce_int_max_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_umlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_umlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q)" + by (unfold decode_umlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_umlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_umlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_umlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_umlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_umlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q)" + by (unfold decode_umlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_umlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_umlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_umlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_transfer_integer_move_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_integer_move_unsigned d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg n)" + by (unfold execute_aarch64_instrs_vector_transfer_integer_move_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_umov_advsimd_aarch64_instrs_vector_transfer_integer_move_unsigned[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_umov_advsimd_aarch64_instrs_vector_transfer_integer_move_unsigned Rd Rn b__0 b__1)" + by (unfold decode_umov_advsimd_aarch64_instrs_vector_transfer_integer_move_unsigned_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_umull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_umull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long Rd Rn b__0 Rm M L b__1 U Q)" + by (unfold decode_umull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_umull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_umull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product Rd Rn Rm b__0 U Q)" + by (unfold decode_umull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd Rd Rn Rm b__0 U)" + by (unfold decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q)" + by (unfold decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U)" + by (unfold decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd Rd Rn op immb b__0 U b__1)" + by (unfold decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd Rd Rn op immb b__0 U)" + by (unfold decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q)" + by (unfold decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U)" + by (unfold decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd Rd Rn Rm b__0 U)" + by (unfold decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd Rd Rn b__0 U Q)" + by (unfold decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd Rd Rn b__0 U)" + by (unfold decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_special_recip_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_special_recip_int d (datasize :: 'datasize::len itself) elements n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_recip_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_urecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_urecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_int Rd Rn sz b__0)" + by (unfold decode_urecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_urhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_urhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding Rd Rn Rm b__0 U b__1)" + by (unfold decode_urhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_urshr_advsimd_aarch64_instrs_vector_shift_right_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_urshr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_urshr_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_urshr_advsimd_aarch64_instrs_vector_shift_right_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_urshr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_urshr_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int d (datasize :: 'datasize::len itself) elements n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ursqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ursqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int Rd Rn sz b__0)" + by (unfold decode_ursqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ursra_advsimd_aarch64_instrs_vector_shift_right_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ursra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_ursra_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ursra_advsimd_aarch64_instrs_vector_shift_right_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ursra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_ursra_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ushll_advsimd_aarch64_instrs_vector_shift_left_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ushll_advsimd_aarch64_instrs_vector_shift_left_long Rd Rn immb b__0 U Q)" + by (unfold decode_ushll_advsimd_aarch64_instrs_vector_shift_left_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ushr_advsimd_aarch64_instrs_vector_shift_right_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ushr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_ushr_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_ushr_advsimd_aarch64_instrs_vector_shift_right_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_ushr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_ushr_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd Rd Rn b__0 U b__1)" + by (unfold decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd Rd Rn b__0 U)" + by (unfold decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_usra_advsimd_aarch64_instrs_vector_shift_right_simd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_usra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_usra_advsimd_aarch64_instrs_vector_shift_right_simd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_usra_advsimd_aarch64_instrs_vector_shift_right_sisd[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_usra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_usra_advsimd_aarch64_instrs_vector_shift_right_sisd_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_usubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_usubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_usubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_usubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_usubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_usubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_permute_unzip[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_permute_unzip d l__195 elements (esize :: 'esize::len itself) m n part)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_permute_unzip_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uzp1_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uzp1_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip Rd Rn op Rm b__0 b__1)" + by (unfold decode_uzp1_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_uzp2_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_uzp2_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip Rd Rn op Rm b__0 b__1)" + by (unfold decode_uzp2_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_wfe_aarch64_instrs_system_hints[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_wfe_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_wfe_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_wfi_aarch64_instrs_system_hints[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_wfi_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_wfi_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_crypto_sha3_xar[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_crypto_sha3_xar d imm6 m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3_xar_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_xar_advsimd_aarch64_instrs_vector_crypto_sha3_xar[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_xar_advsimd_aarch64_instrs_vector_crypto_sha3_xar Rd Rn imm6 Rm)" + by (unfold decode_xar_advsimd_aarch64_instrs_vector_crypto_sha3_xar_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_arithmetic_unary_extract_nosat[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_arithmetic_unary_extract_nosat d datasize elements l__0 n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_extract_nosat_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_xtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_nosat[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_xtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_nosat Rd Rn b__0 Q)" + by (unfold decode_xtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_nosat_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_yield_aarch64_instrs_system_hints[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_yield_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_yield_aarch64_instrs_system_hints_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_execute_aarch64_instrs_vector_transfer_vector_permute_zip[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (execute_aarch64_instrs_vector_transfer_vector_permute_zip d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) m n pairs part)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_permute_zip_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_zip1_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_zip1_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip Rd Rn op Rm b__0 b__1)" + by (unfold decode_zip1_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip_def bind_assoc, no_reg_writes_toI) + +lemma runs_no_reg_writes_to_decode_zip2_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip[runs_no_reg_writes_toI, simp]: + "Rs \ {''DBGEN'', ''DCZID_EL0'', ''EDSCR'', ''PCC'', ''_R29'', ''__ThisInstrAbstract''} \ runs_no_reg_writes_to Rs (decode_zip2_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip Rd Rn op Rm b__0 b__1)" + by (unfold decode_zip2_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip_def bind_assoc, no_reg_writes_toI) + + +context Morello_Axiom_Automaton +begin + +lemma non_cap_regsI[intro, simp]: + "non_cap_reg ACTLR_EL1_ref" + "non_cap_reg ACTLR_EL2_ref" + "non_cap_reg ACTLR_EL3_ref" + "non_cap_reg AFSR0_EL1_ref" + "non_cap_reg AFSR0_EL2_ref" + "non_cap_reg AFSR0_EL3_ref" + "non_cap_reg AFSR1_EL1_ref" + "non_cap_reg AFSR1_EL2_ref" + "non_cap_reg AFSR1_EL3_ref" + "non_cap_reg AIDR_EL1_ref" + "non_cap_reg AMAIR_EL1_ref" + "non_cap_reg AMAIR_EL2_ref" + "non_cap_reg AMAIR_EL3_ref" + "non_cap_reg CCSIDR_EL1_ref" + "non_cap_reg CCTLR_EL0_ref" + "non_cap_reg CCTLR_EL1_ref" + "non_cap_reg CCTLR_EL2_ref" + "non_cap_reg CCTLR_EL3_ref" + "non_cap_reg CHCR_EL2_ref" + "non_cap_reg CLIDR_EL1_ref" + "non_cap_reg CNTFRQ_EL0_ref" + "non_cap_reg CNTHCTL_EL2_ref" + "non_cap_reg CNTHPS_CTL_EL2_ref" + "non_cap_reg CNTHPS_CVAL_EL2_ref" + "non_cap_reg CNTHPS_TVAL_EL2_ref" + "non_cap_reg CNTHP_CTL_EL2_ref" + "non_cap_reg CNTHP_CVAL_EL2_ref" + "non_cap_reg CNTHP_TVAL_EL2_ref" + "non_cap_reg CNTHVS_CTL_EL2_ref" + "non_cap_reg CNTHVS_CVAL_EL2_ref" + "non_cap_reg CNTHVS_TVAL_EL2_ref" + "non_cap_reg CNTHV_CTL_EL2_ref" + "non_cap_reg CNTHV_CVAL_EL2_ref" + "non_cap_reg CNTHV_TVAL_EL2_ref" + "non_cap_reg CNTKCTL_EL1_ref" + "non_cap_reg CNTPCT_EL0_ref" + "non_cap_reg CNTPS_CTL_EL1_ref" + "non_cap_reg CNTPS_CVAL_EL1_ref" + "non_cap_reg CNTPS_TVAL_EL1_ref" + "non_cap_reg CNTP_CTL_EL0_ref" + "non_cap_reg CNTP_CVAL_EL0_ref" + "non_cap_reg CNTP_TVAL_EL0_ref" + "non_cap_reg CNTVCT_EL0_ref" + "non_cap_reg CNTVOFF_EL2_ref" + "non_cap_reg CNTV_CTL_EL0_ref" + "non_cap_reg CNTV_CVAL_EL0_ref" + "non_cap_reg CNTV_TVAL_EL0_ref" + "non_cap_reg CONTEXTIDR_EL1_ref" + "non_cap_reg CONTEXTIDR_EL2_ref" + "non_cap_reg CPACR_EL1_ref" + "non_cap_reg CPTR_EL2_ref" + "non_cap_reg CPTR_EL3_ref" + "non_cap_reg CSCR_EL3_ref" + "non_cap_reg CSSELR_EL1_ref" + "non_cap_reg CTR_EL0_ref" + "non_cap_reg DACR32_EL2_ref" + "non_cap_reg DBGAUTHSTATUS_EL1_ref" + "non_cap_reg DBGBCR_EL1_ref" + "non_cap_reg DBGBVR_EL1_ref" + "non_cap_reg DBGCLAIMCLR_EL1_ref" + "non_cap_reg DBGCLAIMSET_EL1_ref" + "non_cap_reg DBGDTRRX_EL0_ref" + "non_cap_reg DBGDTRTX_EL0_ref" + "non_cap_reg DBGEN_ref" + "non_cap_reg DBGPRCR_EL1_ref" + "non_cap_reg DBGVCR32_EL2_ref" + "non_cap_reg DBGWCR_EL1_ref" + "non_cap_reg DBGWVR_EL1_ref" + "non_cap_reg DCZID_EL0_ref" + "non_cap_reg DISR_EL1_ref" + "non_cap_reg DSPSR_EL0_ref" + "non_cap_reg EDSCR_ref" + "non_cap_reg ERRIDR_EL1_ref" + "non_cap_reg ERRSELR_EL1_ref" + "non_cap_reg ERXADDR_EL1_ref" + "non_cap_reg ERXCTLR_EL1_ref" + "non_cap_reg ERXFR_EL1_ref" + "non_cap_reg ERXMISC0_EL1_ref" + "non_cap_reg ERXMISC1_EL1_ref" + "non_cap_reg ERXSTATUS_EL1_ref" + "non_cap_reg ESR_EL1_ref" + "non_cap_reg ESR_EL2_ref" + "non_cap_reg ESR_EL3_ref" + "non_cap_reg EventRegister_ref" + "non_cap_reg FAR_EL1_ref" + "non_cap_reg FAR_EL2_ref" + "non_cap_reg FAR_EL3_ref" + "non_cap_reg FPCR_ref" + "non_cap_reg FPEXC32_EL2_ref" + "non_cap_reg FPSR_ref" + "non_cap_reg HACR_EL2_ref" + "non_cap_reg HCR_EL2_ref" + "non_cap_reg HPFAR_EL2_ref" + "non_cap_reg HSTR_EL2_ref" + "non_cap_reg ICC_AP0R_EL1_ref" + "non_cap_reg ICC_AP1R_EL1_ref" + "non_cap_reg ICC_AP1R_EL1_NS_ref" + "non_cap_reg ICC_AP1R_EL1_S_ref" + "non_cap_reg ICC_ASGI1R_EL1_ref" + "non_cap_reg ICC_BPR0_EL1_ref" + "non_cap_reg ICC_BPR1_EL1_NS_ref" + "non_cap_reg ICC_BPR1_EL1_S_ref" + "non_cap_reg ICC_CTLR_EL1_NS_ref" + "non_cap_reg ICC_CTLR_EL1_S_ref" + "non_cap_reg ICC_CTLR_EL3_ref" + "non_cap_reg ICC_DIR_EL1_ref" + "non_cap_reg ICC_EOIR0_EL1_ref" + "non_cap_reg ICC_EOIR1_EL1_ref" + "non_cap_reg ICC_HPPIR0_EL1_ref" + "non_cap_reg ICC_HPPIR1_EL1_ref" + "non_cap_reg ICC_IAR0_EL1_ref" + "non_cap_reg ICC_IAR1_EL1_ref" + "non_cap_reg ICC_IGRPEN0_EL1_ref" + "non_cap_reg ICC_IGRPEN1_EL1_NS_ref" + "non_cap_reg ICC_IGRPEN1_EL1_S_ref" + "non_cap_reg ICC_IGRPEN1_EL3_ref" + "non_cap_reg ICC_PMR_EL1_ref" + "non_cap_reg ICC_RPR_EL1_ref" + "non_cap_reg ICC_SGI0R_EL1_ref" + "non_cap_reg ICC_SGI1R_EL1_ref" + "non_cap_reg ICC_SRE_EL1_NS_ref" + "non_cap_reg ICC_SRE_EL1_S_ref" + "non_cap_reg ICC_SRE_EL2_ref" + "non_cap_reg ICC_SRE_EL3_ref" + "non_cap_reg ICH_AP0R_EL2_ref" + "non_cap_reg ICH_AP1R_EL2_ref" + "non_cap_reg ICH_EISR_EL2_ref" + "non_cap_reg ICH_ELRSR_EL2_ref" + "non_cap_reg ICH_HCR_EL2_ref" + "non_cap_reg ICH_LR_EL2_ref" + "non_cap_reg ICH_MISR_EL2_ref" + "non_cap_reg ICH_VMCR_EL2_ref" + "non_cap_reg ICH_VTR_EL2_ref" + "non_cap_reg ICV_AP0R_EL1_ref" + "non_cap_reg ICV_AP1R_EL1_ref" + "non_cap_reg ICV_BPR0_EL1_ref" + "non_cap_reg ICV_BPR1_EL1_ref" + "non_cap_reg ICV_CTLR_EL1_ref" + "non_cap_reg ICV_DIR_EL1_ref" + "non_cap_reg ICV_EOIR0_EL1_ref" + "non_cap_reg ICV_EOIR1_EL1_ref" + "non_cap_reg ICV_HPPIR0_EL1_ref" + "non_cap_reg ICV_HPPIR1_EL1_ref" + "non_cap_reg ICV_IAR0_EL1_ref" + "non_cap_reg ICV_IAR1_EL1_ref" + "non_cap_reg ICV_IGRPEN0_EL1_ref" + "non_cap_reg ICV_IGRPEN1_EL1_ref" + "non_cap_reg ICV_PMR_EL1_ref" + "non_cap_reg ICV_RPR_EL1_ref" + "non_cap_reg ID_AA64AFR0_EL1_ref" + "non_cap_reg ID_AA64AFR1_EL1_ref" + "non_cap_reg ID_AA64DFR0_EL1_ref" + "non_cap_reg ID_AA64DFR1_EL1_ref" + "non_cap_reg ID_AA64ISAR0_EL1_ref" + "non_cap_reg ID_AA64ISAR1_EL1_ref" + "non_cap_reg ID_AA64MMFR0_EL1_ref" + "non_cap_reg ID_AA64MMFR1_EL1_ref" + "non_cap_reg ID_AA64MMFR2_EL1_ref" + "non_cap_reg ID_AA64PFR0_EL1_ref" + "non_cap_reg ID_AA64PFR1_EL1_ref" + "non_cap_reg ID_AA64ZFR0_EL1_ref" + "non_cap_reg ID_AFR0_EL1_ref" + "non_cap_reg ID_DFR0_EL1_ref" + "non_cap_reg ID_ISAR0_EL1_ref" + "non_cap_reg ID_ISAR1_EL1_ref" + "non_cap_reg ID_ISAR2_EL1_ref" + "non_cap_reg ID_ISAR3_EL1_ref" + "non_cap_reg ID_ISAR4_EL1_ref" + "non_cap_reg ID_ISAR5_EL1_ref" + "non_cap_reg ID_ISAR6_EL1_ref" + "non_cap_reg ID_MMFR0_EL1_ref" + "non_cap_reg ID_MMFR1_EL1_ref" + "non_cap_reg ID_MMFR2_EL1_ref" + "non_cap_reg ID_MMFR3_EL1_ref" + "non_cap_reg ID_MMFR4_EL1_ref" + "non_cap_reg ID_MMFR5_EL1_ref" + "non_cap_reg ID_PFR0_EL1_ref" + "non_cap_reg ID_PFR1_EL1_ref" + "non_cap_reg ID_PFR2_EL1_ref" + "non_cap_reg IFSR32_EL2_ref" + "non_cap_reg ISR_EL1_ref" + "non_cap_reg LORC_EL1_ref" + "non_cap_reg LOREA_EL1_ref" + "non_cap_reg LORID_EL1_ref" + "non_cap_reg LORN_EL1_ref" + "non_cap_reg LORSA_EL1_ref" + "non_cap_reg MAIR_EL1_ref" + "non_cap_reg MAIR_EL2_ref" + "non_cap_reg MAIR_EL3_ref" + "non_cap_reg MDCCINT_EL1_ref" + "non_cap_reg MDCCSR_EL0_ref" + "non_cap_reg MDCR_EL2_ref" + "non_cap_reg MDCR_EL3_ref" + "non_cap_reg MDRAR_EL1_ref" + "non_cap_reg MDSCR_EL1_ref" + "non_cap_reg MIDR_EL1_ref" + "non_cap_reg MPAM0_EL1_ref" + "non_cap_reg MPAM3_EL3_ref" + "non_cap_reg MPAMHCR_EL2_ref" + "non_cap_reg MPAMIDR_EL1_ref" + "non_cap_reg MPAMVPM0_EL2_ref" + "non_cap_reg MPAMVPM1_EL2_ref" + "non_cap_reg MPAMVPM2_EL2_ref" + "non_cap_reg MPAMVPM3_EL2_ref" + "non_cap_reg MPAMVPM4_EL2_ref" + "non_cap_reg MPAMVPM5_EL2_ref" + "non_cap_reg MPAMVPM6_EL2_ref" + "non_cap_reg MPAMVPM7_EL2_ref" + "non_cap_reg MPAMVPMV_EL2_ref" + "non_cap_reg MPIDR_EL1_ref" + "non_cap_reg MVFR0_EL1_ref" + "non_cap_reg MVFR1_EL1_ref" + "non_cap_reg MVFR2_EL1_ref" + "non_cap_reg OSDLR_EL1_ref" + "non_cap_reg OSDTRRX_EL1_ref" + "non_cap_reg OSDTRTX_EL1_ref" + "non_cap_reg OSECCR_EL1_ref" + "non_cap_reg OSLAR_EL1_ref" + "non_cap_reg OSLSR_EL1_ref" + "non_cap_reg PAR_EL1_ref" + "non_cap_reg PMBIDR_EL1_ref" + "non_cap_reg PMBLIMITR_EL1_ref" + "non_cap_reg PMBPTR_EL1_ref" + "non_cap_reg PMBSR_EL1_ref" + "non_cap_reg PMCCFILTR_EL0_ref" + "non_cap_reg PMCCNTR_EL0_ref" + "non_cap_reg PMCEID0_EL0_ref" + "non_cap_reg PMCEID1_EL0_ref" + "non_cap_reg PMCNTENCLR_EL0_ref" + "non_cap_reg PMCNTENSET_EL0_ref" + "non_cap_reg PMCR_EL0_ref" + "non_cap_reg PMEVCNTR_EL0_ref" + "non_cap_reg PMEVTYPER_EL0_ref" + "non_cap_reg PMINTENCLR_EL1_ref" + "non_cap_reg PMINTENSET_EL1_ref" + "non_cap_reg PMOVSCLR_EL0_ref" + "non_cap_reg PMOVSSET_EL0_ref" + "non_cap_reg PMSCR_EL1_ref" + "non_cap_reg PMSCR_EL2_ref" + "non_cap_reg PMSELR_EL0_ref" + "non_cap_reg PMSEVFR_EL1_ref" + "non_cap_reg PMSFCR_EL1_ref" + "non_cap_reg PMSICR_EL1_ref" + "non_cap_reg PMSIDR_EL1_ref" + "non_cap_reg PMSIRR_EL1_ref" + "non_cap_reg PMSLATFR_EL1_ref" + "non_cap_reg PMSWINC_EL0_ref" + "non_cap_reg PMUSERENR_EL0_ref" + "non_cap_reg PMXEVCNTR_EL0_ref" + "non_cap_reg PMXEVTYPER_EL0_ref" + "non_cap_reg PSTATE_ref" + "non_cap_reg REVIDR_EL1_ref" + "non_cap_reg RMR_EL1_ref" + "non_cap_reg RMR_EL2_ref" + "non_cap_reg RMR_EL3_ref" + "non_cap_reg RVBAR_EL1_ref" + "non_cap_reg RVBAR_EL2_ref" + "non_cap_reg RVBAR_EL3_ref" + "non_cap_reg S3_op1_Cn_Cm_op2_ref" + "non_cap_reg SCR_EL3_ref" + "non_cap_reg SCTLR_EL1_ref" + "non_cap_reg SCTLR_EL2_ref" + "non_cap_reg SCTLR_EL3_ref" + "non_cap_reg SCXTNUM_EL1_ref" + "non_cap_reg SCXTNUM_EL2_ref" + "non_cap_reg SCXTNUM_EL3_ref" + "non_cap_reg SDER32_EL3_ref" + "non_cap_reg SPIDEN_ref" + "non_cap_reg SPSR_EL1_ref" + "non_cap_reg SPSR_EL2_ref" + "non_cap_reg SPSR_EL3_ref" + "non_cap_reg SPSR_abt_ref" + "non_cap_reg SPSR_fiq_ref" + "non_cap_reg SPSR_irq_ref" + "non_cap_reg SPSR_und_ref" + "non_cap_reg TCR_EL1_ref" + "non_cap_reg TCR_EL2_ref" + "non_cap_reg TCR_EL3_ref" + "non_cap_reg TTBR0_EL1_ref" + "non_cap_reg TTBR0_EL2_ref" + "non_cap_reg TTBR0_EL3_ref" + "non_cap_reg TTBR1_EL1_ref" + "non_cap_reg TTBR1_EL2_ref" + "non_cap_reg VDISR_EL2_ref" + "non_cap_reg VMPIDR_EL2_ref" + "non_cap_reg VPIDR_EL2_ref" + "non_cap_reg VSESR_EL2_ref" + "non_cap_reg VTCR_EL2_ref" + "non_cap_reg VTTBR_EL2_ref" + "non_cap_reg MPAM1_EL1_0_62_ref" + "non_cap_reg MPAM2_EL2_0_62_ref" + "non_cap_reg PC_ref" + "non_cap_reg V_ref" + "non_cap_reg BranchTaken_ref" + "non_cap_reg ThisInstr_ref" + "non_cap_reg ThisInstrAbstract_ref" + "non_cap_reg saved_exception_level_ref" + by (auto simp: non_cap_reg_def register_defs) + +lemma non_cap_exp_read_non_cap_regs[non_cap_expI]: + "non_cap_exp (read_reg ACTLR_EL1_ref)" + "non_cap_exp (read_reg ACTLR_EL2_ref)" + "non_cap_exp (read_reg ACTLR_EL3_ref)" + "non_cap_exp (read_reg AFSR0_EL1_ref)" + "non_cap_exp (read_reg AFSR0_EL2_ref)" + "non_cap_exp (read_reg AFSR0_EL3_ref)" + "non_cap_exp (read_reg AFSR1_EL1_ref)" + "non_cap_exp (read_reg AFSR1_EL2_ref)" + "non_cap_exp (read_reg AFSR1_EL3_ref)" + "non_cap_exp (read_reg AIDR_EL1_ref)" + "non_cap_exp (read_reg AMAIR_EL1_ref)" + "non_cap_exp (read_reg AMAIR_EL2_ref)" + "non_cap_exp (read_reg AMAIR_EL3_ref)" + "non_cap_exp (read_reg CCSIDR_EL1_ref)" + "non_cap_exp (read_reg CCTLR_EL0_ref)" + "non_cap_exp (read_reg CCTLR_EL1_ref)" + "non_cap_exp (read_reg CCTLR_EL2_ref)" + "non_cap_exp (read_reg CCTLR_EL3_ref)" + "non_cap_exp (read_reg CHCR_EL2_ref)" + "non_cap_exp (read_reg CLIDR_EL1_ref)" + "non_cap_exp (read_reg CNTFRQ_EL0_ref)" + "non_cap_exp (read_reg CNTHCTL_EL2_ref)" + "non_cap_exp (read_reg CNTHPS_CTL_EL2_ref)" + "non_cap_exp (read_reg CNTHPS_CVAL_EL2_ref)" + "non_cap_exp (read_reg CNTHPS_TVAL_EL2_ref)" + "non_cap_exp (read_reg CNTHP_CTL_EL2_ref)" + "non_cap_exp (read_reg CNTHP_CVAL_EL2_ref)" + "non_cap_exp (read_reg CNTHP_TVAL_EL2_ref)" + "non_cap_exp (read_reg CNTHVS_CTL_EL2_ref)" + "non_cap_exp (read_reg CNTHVS_CVAL_EL2_ref)" + "non_cap_exp (read_reg CNTHVS_TVAL_EL2_ref)" + "non_cap_exp (read_reg CNTHV_CTL_EL2_ref)" + "non_cap_exp (read_reg CNTHV_CVAL_EL2_ref)" + "non_cap_exp (read_reg CNTHV_TVAL_EL2_ref)" + "non_cap_exp (read_reg CNTKCTL_EL1_ref)" + "non_cap_exp (read_reg CNTPCT_EL0_ref)" + "non_cap_exp (read_reg CNTPS_CTL_EL1_ref)" + "non_cap_exp (read_reg CNTPS_CVAL_EL1_ref)" + "non_cap_exp (read_reg CNTPS_TVAL_EL1_ref)" + "non_cap_exp (read_reg CNTP_CTL_EL0_ref)" + "non_cap_exp (read_reg CNTP_CVAL_EL0_ref)" + "non_cap_exp (read_reg CNTP_TVAL_EL0_ref)" + "non_cap_exp (read_reg CNTVCT_EL0_ref)" + "non_cap_exp (read_reg CNTVOFF_EL2_ref)" + "non_cap_exp (read_reg CNTV_CTL_EL0_ref)" + "non_cap_exp (read_reg CNTV_CVAL_EL0_ref)" + "non_cap_exp (read_reg CNTV_TVAL_EL0_ref)" + "non_cap_exp (read_reg CONTEXTIDR_EL1_ref)" + "non_cap_exp (read_reg CONTEXTIDR_EL2_ref)" + "non_cap_exp (read_reg CPACR_EL1_ref)" + "non_cap_exp (read_reg CPTR_EL2_ref)" + "non_cap_exp (read_reg CPTR_EL3_ref)" + "non_cap_exp (read_reg CSCR_EL3_ref)" + "non_cap_exp (read_reg CSSELR_EL1_ref)" + "non_cap_exp (read_reg CTR_EL0_ref)" + "non_cap_exp (read_reg DACR32_EL2_ref)" + "non_cap_exp (read_reg DBGAUTHSTATUS_EL1_ref)" + "non_cap_exp (read_reg DBGBCR_EL1_ref)" + "non_cap_exp (read_reg DBGBVR_EL1_ref)" + "non_cap_exp (read_reg DBGCLAIMCLR_EL1_ref)" + "non_cap_exp (read_reg DBGCLAIMSET_EL1_ref)" + "non_cap_exp (read_reg DBGDTRRX_EL0_ref)" + "non_cap_exp (read_reg DBGDTRTX_EL0_ref)" + "non_cap_exp (read_reg DBGEN_ref)" + "non_cap_exp (read_reg DBGPRCR_EL1_ref)" + "non_cap_exp (read_reg DBGVCR32_EL2_ref)" + "non_cap_exp (read_reg DBGWCR_EL1_ref)" + "non_cap_exp (read_reg DBGWVR_EL1_ref)" + "non_cap_exp (read_reg DCZID_EL0_ref)" + "non_cap_exp (read_reg DISR_EL1_ref)" + "non_cap_exp (read_reg DSPSR_EL0_ref)" + "non_cap_exp (read_reg EDSCR_ref)" + "non_cap_exp (read_reg ERRIDR_EL1_ref)" + "non_cap_exp (read_reg ERRSELR_EL1_ref)" + "non_cap_exp (read_reg ERXADDR_EL1_ref)" + "non_cap_exp (read_reg ERXCTLR_EL1_ref)" + "non_cap_exp (read_reg ERXFR_EL1_ref)" + "non_cap_exp (read_reg ERXMISC0_EL1_ref)" + "non_cap_exp (read_reg ERXMISC1_EL1_ref)" + "non_cap_exp (read_reg ERXSTATUS_EL1_ref)" + "non_cap_exp (read_reg ESR_EL1_ref)" + "non_cap_exp (read_reg ESR_EL2_ref)" + "non_cap_exp (read_reg ESR_EL3_ref)" + "non_cap_exp (read_reg EventRegister_ref)" + "non_cap_exp (read_reg FAR_EL1_ref)" + "non_cap_exp (read_reg FAR_EL2_ref)" + "non_cap_exp (read_reg FAR_EL3_ref)" + "non_cap_exp (read_reg FPCR_ref)" + "non_cap_exp (read_reg FPEXC32_EL2_ref)" + "non_cap_exp (read_reg FPSR_ref)" + "non_cap_exp (read_reg HACR_EL2_ref)" + "non_cap_exp (read_reg HCR_EL2_ref)" + "non_cap_exp (read_reg HPFAR_EL2_ref)" + "non_cap_exp (read_reg HSTR_EL2_ref)" + "non_cap_exp (read_reg ICC_AP0R_EL1_ref)" + "non_cap_exp (read_reg ICC_AP1R_EL1_ref)" + "non_cap_exp (read_reg ICC_AP1R_EL1_NS_ref)" + "non_cap_exp (read_reg ICC_AP1R_EL1_S_ref)" + "non_cap_exp (read_reg ICC_ASGI1R_EL1_ref)" + "non_cap_exp (read_reg ICC_BPR0_EL1_ref)" + "non_cap_exp (read_reg ICC_BPR1_EL1_NS_ref)" + "non_cap_exp (read_reg ICC_BPR1_EL1_S_ref)" + "non_cap_exp (read_reg ICC_CTLR_EL1_NS_ref)" + "non_cap_exp (read_reg ICC_CTLR_EL1_S_ref)" + "non_cap_exp (read_reg ICC_CTLR_EL3_ref)" + "non_cap_exp (read_reg ICC_DIR_EL1_ref)" + "non_cap_exp (read_reg ICC_EOIR0_EL1_ref)" + "non_cap_exp (read_reg ICC_EOIR1_EL1_ref)" + "non_cap_exp (read_reg ICC_HPPIR0_EL1_ref)" + "non_cap_exp (read_reg ICC_HPPIR1_EL1_ref)" + "non_cap_exp (read_reg ICC_IAR0_EL1_ref)" + "non_cap_exp (read_reg ICC_IAR1_EL1_ref)" + "non_cap_exp (read_reg ICC_IGRPEN0_EL1_ref)" + "non_cap_exp (read_reg ICC_IGRPEN1_EL1_NS_ref)" + "non_cap_exp (read_reg ICC_IGRPEN1_EL1_S_ref)" + "non_cap_exp (read_reg ICC_IGRPEN1_EL3_ref)" + "non_cap_exp (read_reg ICC_PMR_EL1_ref)" + "non_cap_exp (read_reg ICC_RPR_EL1_ref)" + "non_cap_exp (read_reg ICC_SGI0R_EL1_ref)" + "non_cap_exp (read_reg ICC_SGI1R_EL1_ref)" + "non_cap_exp (read_reg ICC_SRE_EL1_NS_ref)" + "non_cap_exp (read_reg ICC_SRE_EL1_S_ref)" + "non_cap_exp (read_reg ICC_SRE_EL2_ref)" + "non_cap_exp (read_reg ICC_SRE_EL3_ref)" + "non_cap_exp (read_reg ICH_AP0R_EL2_ref)" + "non_cap_exp (read_reg ICH_AP1R_EL2_ref)" + "non_cap_exp (read_reg ICH_EISR_EL2_ref)" + "non_cap_exp (read_reg ICH_ELRSR_EL2_ref)" + "non_cap_exp (read_reg ICH_HCR_EL2_ref)" + "non_cap_exp (read_reg ICH_LR_EL2_ref)" + "non_cap_exp (read_reg ICH_MISR_EL2_ref)" + "non_cap_exp (read_reg ICH_VMCR_EL2_ref)" + "non_cap_exp (read_reg ICH_VTR_EL2_ref)" + "non_cap_exp (read_reg ICV_AP0R_EL1_ref)" + "non_cap_exp (read_reg ICV_AP1R_EL1_ref)" + "non_cap_exp (read_reg ICV_BPR0_EL1_ref)" + "non_cap_exp (read_reg ICV_BPR1_EL1_ref)" + "non_cap_exp (read_reg ICV_CTLR_EL1_ref)" + "non_cap_exp (read_reg ICV_DIR_EL1_ref)" + "non_cap_exp (read_reg ICV_EOIR0_EL1_ref)" + "non_cap_exp (read_reg ICV_EOIR1_EL1_ref)" + "non_cap_exp (read_reg ICV_HPPIR0_EL1_ref)" + "non_cap_exp (read_reg ICV_HPPIR1_EL1_ref)" + "non_cap_exp (read_reg ICV_IAR0_EL1_ref)" + "non_cap_exp (read_reg ICV_IAR1_EL1_ref)" + "non_cap_exp (read_reg ICV_IGRPEN0_EL1_ref)" + "non_cap_exp (read_reg ICV_IGRPEN1_EL1_ref)" + "non_cap_exp (read_reg ICV_PMR_EL1_ref)" + "non_cap_exp (read_reg ICV_RPR_EL1_ref)" + "non_cap_exp (read_reg ID_AA64AFR0_EL1_ref)" + "non_cap_exp (read_reg ID_AA64AFR1_EL1_ref)" + "non_cap_exp (read_reg ID_AA64DFR0_EL1_ref)" + "non_cap_exp (read_reg ID_AA64DFR1_EL1_ref)" + "non_cap_exp (read_reg ID_AA64ISAR0_EL1_ref)" + "non_cap_exp (read_reg ID_AA64ISAR1_EL1_ref)" + "non_cap_exp (read_reg ID_AA64MMFR0_EL1_ref)" + "non_cap_exp (read_reg ID_AA64MMFR1_EL1_ref)" + "non_cap_exp (read_reg ID_AA64MMFR2_EL1_ref)" + "non_cap_exp (read_reg ID_AA64PFR0_EL1_ref)" + "non_cap_exp (read_reg ID_AA64PFR1_EL1_ref)" + "non_cap_exp (read_reg ID_AA64ZFR0_EL1_ref)" + "non_cap_exp (read_reg ID_AFR0_EL1_ref)" + "non_cap_exp (read_reg ID_DFR0_EL1_ref)" + "non_cap_exp (read_reg ID_ISAR0_EL1_ref)" + "non_cap_exp (read_reg ID_ISAR1_EL1_ref)" + "non_cap_exp (read_reg ID_ISAR2_EL1_ref)" + "non_cap_exp (read_reg ID_ISAR3_EL1_ref)" + "non_cap_exp (read_reg ID_ISAR4_EL1_ref)" + "non_cap_exp (read_reg ID_ISAR5_EL1_ref)" + "non_cap_exp (read_reg ID_ISAR6_EL1_ref)" + "non_cap_exp (read_reg ID_MMFR0_EL1_ref)" + "non_cap_exp (read_reg ID_MMFR1_EL1_ref)" + "non_cap_exp (read_reg ID_MMFR2_EL1_ref)" + "non_cap_exp (read_reg ID_MMFR3_EL1_ref)" + "non_cap_exp (read_reg ID_MMFR4_EL1_ref)" + "non_cap_exp (read_reg ID_MMFR5_EL1_ref)" + "non_cap_exp (read_reg ID_PFR0_EL1_ref)" + "non_cap_exp (read_reg ID_PFR1_EL1_ref)" + "non_cap_exp (read_reg ID_PFR2_EL1_ref)" + "non_cap_exp (read_reg IFSR32_EL2_ref)" + "non_cap_exp (read_reg ISR_EL1_ref)" + "non_cap_exp (read_reg LORC_EL1_ref)" + "non_cap_exp (read_reg LOREA_EL1_ref)" + "non_cap_exp (read_reg LORID_EL1_ref)" + "non_cap_exp (read_reg LORN_EL1_ref)" + "non_cap_exp (read_reg LORSA_EL1_ref)" + "non_cap_exp (read_reg MAIR_EL1_ref)" + "non_cap_exp (read_reg MAIR_EL2_ref)" + "non_cap_exp (read_reg MAIR_EL3_ref)" + "non_cap_exp (read_reg MDCCINT_EL1_ref)" + "non_cap_exp (read_reg MDCCSR_EL0_ref)" + "non_cap_exp (read_reg MDCR_EL2_ref)" + "non_cap_exp (read_reg MDCR_EL3_ref)" + "non_cap_exp (read_reg MDRAR_EL1_ref)" + "non_cap_exp (read_reg MDSCR_EL1_ref)" + "non_cap_exp (read_reg MIDR_EL1_ref)" + "non_cap_exp (read_reg MPAM0_EL1_ref)" + "non_cap_exp (read_reg MPAM3_EL3_ref)" + "non_cap_exp (read_reg MPAMHCR_EL2_ref)" + "non_cap_exp (read_reg MPAMIDR_EL1_ref)" + "non_cap_exp (read_reg MPAMVPM0_EL2_ref)" + "non_cap_exp (read_reg MPAMVPM1_EL2_ref)" + "non_cap_exp (read_reg MPAMVPM2_EL2_ref)" + "non_cap_exp (read_reg MPAMVPM3_EL2_ref)" + "non_cap_exp (read_reg MPAMVPM4_EL2_ref)" + "non_cap_exp (read_reg MPAMVPM5_EL2_ref)" + "non_cap_exp (read_reg MPAMVPM6_EL2_ref)" + "non_cap_exp (read_reg MPAMVPM7_EL2_ref)" + "non_cap_exp (read_reg MPAMVPMV_EL2_ref)" + "non_cap_exp (read_reg MPIDR_EL1_ref)" + "non_cap_exp (read_reg MVFR0_EL1_ref)" + "non_cap_exp (read_reg MVFR1_EL1_ref)" + "non_cap_exp (read_reg MVFR2_EL1_ref)" + "non_cap_exp (read_reg OSDLR_EL1_ref)" + "non_cap_exp (read_reg OSDTRRX_EL1_ref)" + "non_cap_exp (read_reg OSDTRTX_EL1_ref)" + "non_cap_exp (read_reg OSECCR_EL1_ref)" + "non_cap_exp (read_reg OSLAR_EL1_ref)" + "non_cap_exp (read_reg OSLSR_EL1_ref)" + "non_cap_exp (read_reg PAR_EL1_ref)" + "non_cap_exp (read_reg PMBIDR_EL1_ref)" + "non_cap_exp (read_reg PMBLIMITR_EL1_ref)" + "non_cap_exp (read_reg PMBPTR_EL1_ref)" + "non_cap_exp (read_reg PMBSR_EL1_ref)" + "non_cap_exp (read_reg PMCCFILTR_EL0_ref)" + "non_cap_exp (read_reg PMCCNTR_EL0_ref)" + "non_cap_exp (read_reg PMCEID0_EL0_ref)" + "non_cap_exp (read_reg PMCEID1_EL0_ref)" + "non_cap_exp (read_reg PMCNTENCLR_EL0_ref)" + "non_cap_exp (read_reg PMCNTENSET_EL0_ref)" + "non_cap_exp (read_reg PMCR_EL0_ref)" + "non_cap_exp (read_reg PMEVCNTR_EL0_ref)" + "non_cap_exp (read_reg PMEVTYPER_EL0_ref)" + "non_cap_exp (read_reg PMINTENCLR_EL1_ref)" + "non_cap_exp (read_reg PMINTENSET_EL1_ref)" + "non_cap_exp (read_reg PMOVSCLR_EL0_ref)" + "non_cap_exp (read_reg PMOVSSET_EL0_ref)" + "non_cap_exp (read_reg PMSCR_EL1_ref)" + "non_cap_exp (read_reg PMSCR_EL2_ref)" + "non_cap_exp (read_reg PMSELR_EL0_ref)" + "non_cap_exp (read_reg PMSEVFR_EL1_ref)" + "non_cap_exp (read_reg PMSFCR_EL1_ref)" + "non_cap_exp (read_reg PMSICR_EL1_ref)" + "non_cap_exp (read_reg PMSIDR_EL1_ref)" + "non_cap_exp (read_reg PMSIRR_EL1_ref)" + "non_cap_exp (read_reg PMSLATFR_EL1_ref)" + "non_cap_exp (read_reg PMSWINC_EL0_ref)" + "non_cap_exp (read_reg PMUSERENR_EL0_ref)" + "non_cap_exp (read_reg PMXEVCNTR_EL0_ref)" + "non_cap_exp (read_reg PMXEVTYPER_EL0_ref)" + "non_cap_exp (read_reg PSTATE_ref)" + "non_cap_exp (read_reg REVIDR_EL1_ref)" + "non_cap_exp (read_reg RMR_EL1_ref)" + "non_cap_exp (read_reg RMR_EL2_ref)" + "non_cap_exp (read_reg RMR_EL3_ref)" + "non_cap_exp (read_reg RVBAR_EL1_ref)" + "non_cap_exp (read_reg RVBAR_EL2_ref)" + "non_cap_exp (read_reg RVBAR_EL3_ref)" + "non_cap_exp (read_reg S3_op1_Cn_Cm_op2_ref)" + "non_cap_exp (read_reg SCR_EL3_ref)" + "non_cap_exp (read_reg SCTLR_EL1_ref)" + "non_cap_exp (read_reg SCTLR_EL2_ref)" + "non_cap_exp (read_reg SCTLR_EL3_ref)" + "non_cap_exp (read_reg SCXTNUM_EL1_ref)" + "non_cap_exp (read_reg SCXTNUM_EL2_ref)" + "non_cap_exp (read_reg SCXTNUM_EL3_ref)" + "non_cap_exp (read_reg SDER32_EL3_ref)" + "non_cap_exp (read_reg SPIDEN_ref)" + "non_cap_exp (read_reg SPSR_EL1_ref)" + "non_cap_exp (read_reg SPSR_EL2_ref)" + "non_cap_exp (read_reg SPSR_EL3_ref)" + "non_cap_exp (read_reg SPSR_abt_ref)" + "non_cap_exp (read_reg SPSR_fiq_ref)" + "non_cap_exp (read_reg SPSR_irq_ref)" + "non_cap_exp (read_reg SPSR_und_ref)" + "non_cap_exp (read_reg TCR_EL1_ref)" + "non_cap_exp (read_reg TCR_EL2_ref)" + "non_cap_exp (read_reg TCR_EL3_ref)" + "non_cap_exp (read_reg TTBR0_EL1_ref)" + "non_cap_exp (read_reg TTBR0_EL2_ref)" + "non_cap_exp (read_reg TTBR0_EL3_ref)" + "non_cap_exp (read_reg TTBR1_EL1_ref)" + "non_cap_exp (read_reg TTBR1_EL2_ref)" + "non_cap_exp (read_reg VDISR_EL2_ref)" + "non_cap_exp (read_reg VMPIDR_EL2_ref)" + "non_cap_exp (read_reg VPIDR_EL2_ref)" + "non_cap_exp (read_reg VSESR_EL2_ref)" + "non_cap_exp (read_reg VTCR_EL2_ref)" + "non_cap_exp (read_reg VTTBR_EL2_ref)" + "non_cap_exp (read_reg MPAM1_EL1_0_62_ref)" + "non_cap_exp (read_reg MPAM2_EL2_0_62_ref)" + "non_cap_exp (read_reg PC_ref)" + "non_cap_exp (read_reg V_ref)" + "non_cap_exp (read_reg BranchTaken_ref)" + "non_cap_exp (read_reg ThisInstr_ref)" + "non_cap_exp (read_reg ThisInstrAbstract_ref)" + "non_cap_exp (read_reg saved_exception_level_ref)" + by (intro non_cap_exp_read_non_cap_reg non_cap_regsI; auto simp: register_defs)+ + +lemma non_cap_exp_write_non_cap_regs[non_cap_expI]: + "\v. non_cap_exp (write_reg ACTLR_EL1_ref v)" + "\v. non_cap_exp (write_reg ACTLR_EL2_ref v)" + "\v. non_cap_exp (write_reg ACTLR_EL3_ref v)" + "\v. non_cap_exp (write_reg AFSR0_EL1_ref v)" + "\v. non_cap_exp (write_reg AFSR0_EL2_ref v)" + "\v. non_cap_exp (write_reg AFSR0_EL3_ref v)" + "\v. non_cap_exp (write_reg AFSR1_EL1_ref v)" + "\v. non_cap_exp (write_reg AFSR1_EL2_ref v)" + "\v. non_cap_exp (write_reg AFSR1_EL3_ref v)" + "\v. non_cap_exp (write_reg AIDR_EL1_ref v)" + "\v. non_cap_exp (write_reg AMAIR_EL1_ref v)" + "\v. non_cap_exp (write_reg AMAIR_EL2_ref v)" + "\v. non_cap_exp (write_reg AMAIR_EL3_ref v)" + "\v. non_cap_exp (write_reg CCSIDR_EL1_ref v)" + "\v. non_cap_exp (write_reg CCTLR_EL0_ref v)" + "\v. non_cap_exp (write_reg CCTLR_EL1_ref v)" + "\v. non_cap_exp (write_reg CCTLR_EL2_ref v)" + "\v. non_cap_exp (write_reg CCTLR_EL3_ref v)" + "\v. non_cap_exp (write_reg CHCR_EL2_ref v)" + "\v. non_cap_exp (write_reg CLIDR_EL1_ref v)" + "\v. non_cap_exp (write_reg CNTFRQ_EL0_ref v)" + "\v. non_cap_exp (write_reg CNTHCTL_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTHPS_CTL_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTHPS_CVAL_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTHPS_TVAL_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTHP_CTL_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTHP_CVAL_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTHP_TVAL_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTHVS_CTL_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTHVS_CVAL_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTHVS_TVAL_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTHV_CTL_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTHV_CVAL_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTHV_TVAL_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTKCTL_EL1_ref v)" + "\v. non_cap_exp (write_reg CNTPCT_EL0_ref v)" + "\v. non_cap_exp (write_reg CNTPS_CTL_EL1_ref v)" + "\v. non_cap_exp (write_reg CNTPS_CVAL_EL1_ref v)" + "\v. non_cap_exp (write_reg CNTPS_TVAL_EL1_ref v)" + "\v. non_cap_exp (write_reg CNTP_CTL_EL0_ref v)" + "\v. non_cap_exp (write_reg CNTP_CVAL_EL0_ref v)" + "\v. non_cap_exp (write_reg CNTP_TVAL_EL0_ref v)" + "\v. non_cap_exp (write_reg CNTVCT_EL0_ref v)" + "\v. non_cap_exp (write_reg CNTVOFF_EL2_ref v)" + "\v. non_cap_exp (write_reg CNTV_CTL_EL0_ref v)" + "\v. non_cap_exp (write_reg CNTV_CVAL_EL0_ref v)" + "\v. non_cap_exp (write_reg CNTV_TVAL_EL0_ref v)" + "\v. non_cap_exp (write_reg CONTEXTIDR_EL1_ref v)" + "\v. non_cap_exp (write_reg CONTEXTIDR_EL2_ref v)" + "\v. non_cap_exp (write_reg CPACR_EL1_ref v)" + "\v. non_cap_exp (write_reg CPTR_EL2_ref v)" + "\v. non_cap_exp (write_reg CPTR_EL3_ref v)" + "\v. non_cap_exp (write_reg CSCR_EL3_ref v)" + "\v. non_cap_exp (write_reg CSSELR_EL1_ref v)" + "\v. non_cap_exp (write_reg CTR_EL0_ref v)" + "\v. non_cap_exp (write_reg DACR32_EL2_ref v)" + "\v. non_cap_exp (write_reg DBGAUTHSTATUS_EL1_ref v)" + "\v. non_cap_exp (write_reg DBGBCR_EL1_ref v)" + "\v. non_cap_exp (write_reg DBGBVR_EL1_ref v)" + "\v. non_cap_exp (write_reg DBGCLAIMCLR_EL1_ref v)" + "\v. non_cap_exp (write_reg DBGCLAIMSET_EL1_ref v)" + "\v. non_cap_exp (write_reg DBGDTRRX_EL0_ref v)" + "\v. non_cap_exp (write_reg DBGDTRTX_EL0_ref v)" + "\v. non_cap_exp (write_reg DBGEN_ref v)" + "\v. non_cap_exp (write_reg DBGPRCR_EL1_ref v)" + "\v. non_cap_exp (write_reg DBGVCR32_EL2_ref v)" + "\v. non_cap_exp (write_reg DBGWCR_EL1_ref v)" + "\v. non_cap_exp (write_reg DBGWVR_EL1_ref v)" + "\v. non_cap_exp (write_reg DCZID_EL0_ref v)" + "\v. non_cap_exp (write_reg DISR_EL1_ref v)" + "\v. non_cap_exp (write_reg DSPSR_EL0_ref v)" + "\v. non_cap_exp (write_reg EDSCR_ref v)" + "\v. non_cap_exp (write_reg ERRIDR_EL1_ref v)" + "\v. non_cap_exp (write_reg ERRSELR_EL1_ref v)" + "\v. non_cap_exp (write_reg ERXADDR_EL1_ref v)" + "\v. non_cap_exp (write_reg ERXCTLR_EL1_ref v)" + "\v. non_cap_exp (write_reg ERXFR_EL1_ref v)" + "\v. non_cap_exp (write_reg ERXMISC0_EL1_ref v)" + "\v. non_cap_exp (write_reg ERXMISC1_EL1_ref v)" + "\v. non_cap_exp (write_reg ERXSTATUS_EL1_ref v)" + "\v. non_cap_exp (write_reg ESR_EL1_ref v)" + "\v. non_cap_exp (write_reg ESR_EL2_ref v)" + "\v. non_cap_exp (write_reg ESR_EL3_ref v)" + "\v. non_cap_exp (write_reg EventRegister_ref v)" + "\v. non_cap_exp (write_reg FAR_EL1_ref v)" + "\v. non_cap_exp (write_reg FAR_EL2_ref v)" + "\v. non_cap_exp (write_reg FAR_EL3_ref v)" + "\v. non_cap_exp (write_reg FPCR_ref v)" + "\v. non_cap_exp (write_reg FPEXC32_EL2_ref v)" + "\v. non_cap_exp (write_reg FPSR_ref v)" + "\v. non_cap_exp (write_reg HACR_EL2_ref v)" + "\v. non_cap_exp (write_reg HCR_EL2_ref v)" + "\v. non_cap_exp (write_reg HPFAR_EL2_ref v)" + "\v. non_cap_exp (write_reg HSTR_EL2_ref v)" + "\v. non_cap_exp (write_reg ICC_AP0R_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_AP1R_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_AP1R_EL1_NS_ref v)" + "\v. non_cap_exp (write_reg ICC_AP1R_EL1_S_ref v)" + "\v. non_cap_exp (write_reg ICC_ASGI1R_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_BPR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_BPR1_EL1_NS_ref v)" + "\v. non_cap_exp (write_reg ICC_BPR1_EL1_S_ref v)" + "\v. non_cap_exp (write_reg ICC_CTLR_EL1_NS_ref v)" + "\v. non_cap_exp (write_reg ICC_CTLR_EL1_S_ref v)" + "\v. non_cap_exp (write_reg ICC_CTLR_EL3_ref v)" + "\v. non_cap_exp (write_reg ICC_DIR_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_EOIR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_EOIR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_HPPIR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_HPPIR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_IAR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_IAR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_IGRPEN0_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_IGRPEN1_EL1_NS_ref v)" + "\v. non_cap_exp (write_reg ICC_IGRPEN1_EL1_S_ref v)" + "\v. non_cap_exp (write_reg ICC_IGRPEN1_EL3_ref v)" + "\v. non_cap_exp (write_reg ICC_PMR_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_RPR_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_SGI0R_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_SGI1R_EL1_ref v)" + "\v. non_cap_exp (write_reg ICC_SRE_EL1_NS_ref v)" + "\v. non_cap_exp (write_reg ICC_SRE_EL1_S_ref v)" + "\v. non_cap_exp (write_reg ICC_SRE_EL2_ref v)" + "\v. non_cap_exp (write_reg ICC_SRE_EL3_ref v)" + "\v. non_cap_exp (write_reg ICH_AP0R_EL2_ref v)" + "\v. non_cap_exp (write_reg ICH_AP1R_EL2_ref v)" + "\v. non_cap_exp (write_reg ICH_EISR_EL2_ref v)" + "\v. non_cap_exp (write_reg ICH_ELRSR_EL2_ref v)" + "\v. non_cap_exp (write_reg ICH_HCR_EL2_ref v)" + "\v. non_cap_exp (write_reg ICH_LR_EL2_ref v)" + "\v. non_cap_exp (write_reg ICH_MISR_EL2_ref v)" + "\v. non_cap_exp (write_reg ICH_VMCR_EL2_ref v)" + "\v. non_cap_exp (write_reg ICH_VTR_EL2_ref v)" + "\v. non_cap_exp (write_reg ICV_AP0R_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_AP1R_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_BPR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_BPR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_CTLR_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_DIR_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_EOIR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_EOIR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_HPPIR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_HPPIR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_IAR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_IAR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_IGRPEN0_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_IGRPEN1_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_PMR_EL1_ref v)" + "\v. non_cap_exp (write_reg ICV_RPR_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_AA64AFR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_AA64AFR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_AA64DFR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_AA64DFR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_AA64ISAR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_AA64ISAR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_AA64MMFR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_AA64MMFR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_AA64MMFR2_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_AA64PFR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_AA64PFR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_AA64ZFR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_AFR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_DFR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_ISAR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_ISAR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_ISAR2_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_ISAR3_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_ISAR4_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_ISAR5_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_ISAR6_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_MMFR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_MMFR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_MMFR2_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_MMFR3_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_MMFR4_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_MMFR5_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_PFR0_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_PFR1_EL1_ref v)" + "\v. non_cap_exp (write_reg ID_PFR2_EL1_ref v)" + "\v. non_cap_exp (write_reg IFSR32_EL2_ref v)" + "\v. non_cap_exp (write_reg ISR_EL1_ref v)" + "\v. non_cap_exp (write_reg LORC_EL1_ref v)" + "\v. non_cap_exp (write_reg LOREA_EL1_ref v)" + "\v. non_cap_exp (write_reg LORID_EL1_ref v)" + "\v. non_cap_exp (write_reg LORN_EL1_ref v)" + "\v. non_cap_exp (write_reg LORSA_EL1_ref v)" + "\v. non_cap_exp (write_reg MDCCINT_EL1_ref v)" + "\v. non_cap_exp (write_reg MDCCSR_EL0_ref v)" + "\v. non_cap_exp (write_reg MDCR_EL2_ref v)" + "\v. non_cap_exp (write_reg MDCR_EL3_ref v)" + "\v. non_cap_exp (write_reg MDRAR_EL1_ref v)" + "\v. non_cap_exp (write_reg MDSCR_EL1_ref v)" + "\v. non_cap_exp (write_reg MIDR_EL1_ref v)" + "\v. non_cap_exp (write_reg MPIDR_EL1_ref v)" + "\v. non_cap_exp (write_reg MVFR0_EL1_ref v)" + "\v. non_cap_exp (write_reg MVFR1_EL1_ref v)" + "\v. non_cap_exp (write_reg MVFR2_EL1_ref v)" + "\v. non_cap_exp (write_reg OSDLR_EL1_ref v)" + "\v. non_cap_exp (write_reg OSDTRRX_EL1_ref v)" + "\v. non_cap_exp (write_reg OSDTRTX_EL1_ref v)" + "\v. non_cap_exp (write_reg OSECCR_EL1_ref v)" + "\v. non_cap_exp (write_reg OSLAR_EL1_ref v)" + "\v. non_cap_exp (write_reg OSLSR_EL1_ref v)" + "\v. non_cap_exp (write_reg PAR_EL1_ref v)" + "\v. non_cap_exp (write_reg PMBIDR_EL1_ref v)" + "\v. non_cap_exp (write_reg PMBLIMITR_EL1_ref v)" + "\v. non_cap_exp (write_reg PMBPTR_EL1_ref v)" + "\v. non_cap_exp (write_reg PMBSR_EL1_ref v)" + "\v. non_cap_exp (write_reg PMCCFILTR_EL0_ref v)" + "\v. non_cap_exp (write_reg PMCCNTR_EL0_ref v)" + "\v. non_cap_exp (write_reg PMCEID0_EL0_ref v)" + "\v. non_cap_exp (write_reg PMCEID1_EL0_ref v)" + "\v. non_cap_exp (write_reg PMCNTENCLR_EL0_ref v)" + "\v. non_cap_exp (write_reg PMCNTENSET_EL0_ref v)" + "\v. non_cap_exp (write_reg PMCR_EL0_ref v)" + "\v. non_cap_exp (write_reg PMEVCNTR_EL0_ref v)" + "\v. non_cap_exp (write_reg PMEVTYPER_EL0_ref v)" + "\v. non_cap_exp (write_reg PMINTENCLR_EL1_ref v)" + "\v. non_cap_exp (write_reg PMINTENSET_EL1_ref v)" + "\v. non_cap_exp (write_reg PMOVSCLR_EL0_ref v)" + "\v. non_cap_exp (write_reg PMOVSSET_EL0_ref v)" + "\v. non_cap_exp (write_reg PMSCR_EL1_ref v)" + "\v. non_cap_exp (write_reg PMSCR_EL2_ref v)" + "\v. non_cap_exp (write_reg PMSELR_EL0_ref v)" + "\v. non_cap_exp (write_reg PMSEVFR_EL1_ref v)" + "\v. non_cap_exp (write_reg PMSFCR_EL1_ref v)" + "\v. non_cap_exp (write_reg PMSICR_EL1_ref v)" + "\v. non_cap_exp (write_reg PMSIDR_EL1_ref v)" + "\v. non_cap_exp (write_reg PMSIRR_EL1_ref v)" + "\v. non_cap_exp (write_reg PMSLATFR_EL1_ref v)" + "\v. non_cap_exp (write_reg PMSWINC_EL0_ref v)" + "\v. non_cap_exp (write_reg PMUSERENR_EL0_ref v)" + "\v. non_cap_exp (write_reg PMXEVCNTR_EL0_ref v)" + "\v. non_cap_exp (write_reg PMXEVTYPER_EL0_ref v)" + "\v. non_cap_exp (write_reg PSTATE_ref v)" + "\v. non_cap_exp (write_reg REVIDR_EL1_ref v)" + "\v. non_cap_exp (write_reg RMR_EL1_ref v)" + "\v. non_cap_exp (write_reg RMR_EL2_ref v)" + "\v. non_cap_exp (write_reg RMR_EL3_ref v)" + "\v. non_cap_exp (write_reg RVBAR_EL1_ref v)" + "\v. non_cap_exp (write_reg RVBAR_EL2_ref v)" + "\v. non_cap_exp (write_reg RVBAR_EL3_ref v)" + "\v. non_cap_exp (write_reg S3_op1_Cn_Cm_op2_ref v)" + "\v. non_cap_exp (write_reg SCXTNUM_EL1_ref v)" + "\v. non_cap_exp (write_reg SCXTNUM_EL2_ref v)" + "\v. non_cap_exp (write_reg SCXTNUM_EL3_ref v)" + "\v. non_cap_exp (write_reg SDER32_EL3_ref v)" + "\v. non_cap_exp (write_reg SPIDEN_ref v)" + "\v. non_cap_exp (write_reg SPSR_EL1_ref v)" + "\v. non_cap_exp (write_reg SPSR_EL2_ref v)" + "\v. non_cap_exp (write_reg SPSR_EL3_ref v)" + "\v. non_cap_exp (write_reg SPSR_abt_ref v)" + "\v. non_cap_exp (write_reg SPSR_fiq_ref v)" + "\v. non_cap_exp (write_reg SPSR_irq_ref v)" + "\v. non_cap_exp (write_reg SPSR_und_ref v)" + "\v. non_cap_exp (write_reg VDISR_EL2_ref v)" + "\v. non_cap_exp (write_reg VMPIDR_EL2_ref v)" + "\v. non_cap_exp (write_reg VPIDR_EL2_ref v)" + "\v. non_cap_exp (write_reg VSESR_EL2_ref v)" + "\v. non_cap_exp (write_reg PC_ref v)" + "\v. non_cap_exp (write_reg V_ref v)" + "\v. non_cap_exp (write_reg BranchTaken_ref v)" + "\v. non_cap_exp (write_reg ThisInstr_ref v)" + "\v. non_cap_exp (write_reg ThisInstrAbstract_ref v)" + "\v. non_cap_exp (write_reg saved_exception_level_ref v)" + by (intro non_cap_exp_write_non_cap_reg non_cap_regsI; auto simp: register_defs)+ + +lemma non_cap_exp_ReservedEncoding[non_cap_expI]: + "non_cap_exp (ReservedEncoding arg0)" + by (unfold ReservedEncoding_def, non_cap_expI) + +lemma non_cap_exp_UNKNOWN_integer[non_cap_expI]: + "non_cap_exp (UNKNOWN_integer arg0)" + by (unfold UNKNOWN_integer_def, non_cap_expI) + +lemma non_cap_exp_UNKNOWN_boolean[non_cap_expI]: + "non_cap_exp (UNKNOWN_boolean arg0)" + by (unfold UNKNOWN_boolean_def, non_cap_expI) + +lemma non_cap_exp_GetVerbosity[non_cap_expI]: + "non_cap_exp (GetVerbosity arg0)" + by (unfold GetVerbosity_def, non_cap_expI) + +lemma non_cap_exp_EndOfInstruction[non_cap_expI]: + "non_cap_exp (EndOfInstruction arg0)" + by (unfold EndOfInstruction_def, non_cap_expI) + +lemma non_cap_exp_IMPDEF_boolean_map[non_cap_expI]: + "non_cap_exp (IMPDEF_boolean_map x)" + by (unfold IMPDEF_boolean_map_def, non_cap_expI) + +lemma non_cap_exp_IMPDEF_boolean[non_cap_expI]: + "non_cap_exp (IMPDEF_boolean x)" + by (unfold IMPDEF_boolean_def, non_cap_expI) + +lemma non_cap_exp_IMPDEF_integer_map[non_cap_expI]: + "non_cap_exp (IMPDEF_integer_map x)" + by (unfold IMPDEF_integer_map_def, non_cap_expI) + +lemma non_cap_exp_IMPDEF_integer[non_cap_expI]: + "non_cap_exp (IMPDEF_integer x)" + by (unfold IMPDEF_integer_def, non_cap_expI) + +lemma non_cap_exp_EL2Enabled[non_cap_expI]: + "non_cap_exp (EL2Enabled arg0)" + by (unfold EL2Enabled_def, non_cap_expI) + +lemma non_cap_exp_getISR[non_cap_expI]: + "non_cap_exp (getISR arg0)" + by (unfold getISR_def, non_cap_expI) + +lemma non_cap_exp_ConditionHolds[non_cap_expI]: + "non_cap_exp (ConditionHolds cond)" + by (unfold ConditionHolds_def, non_cap_expI) + +lemma non_cap_exp_undefined_Constraint[non_cap_expI]: + "non_cap_exp (undefined_Constraint arg0)" + by (unfold undefined_Constraint_def, non_cap_expI) + +lemma non_cap_exp_ConstrainUnpredictable[non_cap_expI]: + "non_cap_exp (ConstrainUnpredictable which)" + by (cases which; simp; non_cap_expI) + +lemma non_cap_exp_ConstrainUnpredictableBool[non_cap_expI]: + "non_cap_exp (ConstrainUnpredictableBool which)" + by (unfold ConstrainUnpredictableBool_def, non_cap_expI) + +lemma non_cap_exp_UsingAArch32[non_cap_expI]: + "non_cap_exp (UsingAArch32 arg0)" + by (unfold UsingAArch32_def, non_cap_expI) + +lemma non_cap_exp_UNKNOWN_bits[non_cap_expI]: + "non_cap_exp (UNKNOWN_bits n)" + by (unfold UNKNOWN_bits_def, non_cap_expI) + +lemma non_cap_exp_AArch32_CurrentCond[non_cap_expI]: + "non_cap_exp (AArch32_CurrentCond arg0)" + by (unfold AArch32_CurrentCond_def, non_cap_expI) + +lemma non_cap_exp_ConditionSyndrome[non_cap_expI]: + "non_cap_exp (ConditionSyndrome arg0)" + by (unfold ConditionSyndrome_def, non_cap_expI) + +lemma non_cap_exp_undefined_Exception[non_cap_expI]: + "non_cap_exp (undefined_Exception arg0)" + by (unfold undefined_Exception_def, non_cap_expI) + +lemma non_cap_exp_undefined_ExceptionRecord[non_cap_expI]: + "non_cap_exp (undefined_ExceptionRecord arg0)" + by (unfold undefined_ExceptionRecord_def, non_cap_expI) + +lemma non_cap_exp_ExceptionSyndrome[non_cap_expI]: + "non_cap_exp (ExceptionSyndrome exceptype)" + by (unfold ExceptionSyndrome_def, non_cap_expI) + +lemma non_cap_exp_Unreachable[non_cap_expI]: + "non_cap_exp (Unreachable arg0)" + by (unfold Unreachable_def, non_cap_expI) + +lemma non_cap_exp_ThisInstr[non_cap_expI]: + "non_cap_exp (ThisInstr arg0)" + by (unfold ThisInstr_def, non_cap_expI) + +lemma non_cap_exp_AArch64_SystemAccessTrapSyndrome[non_cap_expI]: + "non_cap_exp (AArch64_SystemAccessTrapSyndrome instr__arg ec)" + by (unfold AArch64_SystemAccessTrapSyndrome_def, non_cap_expI) + +lemma non_cap_exp_ELStateUsingAArch32K[non_cap_expI]: + "non_cap_exp (ELStateUsingAArch32K el secure)" + by (unfold ELStateUsingAArch32K_def, non_cap_expI) + +lemma non_cap_exp_ELStateUsingAArch32[non_cap_expI]: + "non_cap_exp (ELStateUsingAArch32 el secure)" + by (unfold ELStateUsingAArch32_def, non_cap_expI) + +lemma non_cap_exp_SCR_GEN_read[non_cap_expI]: + "non_cap_exp (SCR_GEN_read arg0)" + by (unfold SCR_GEN_read_def, non_cap_expI) + +lemma non_cap_exp_IsSecureBelowEL3[non_cap_expI]: + "non_cap_exp (IsSecureBelowEL3 arg0)" + by (unfold IsSecureBelowEL3_def, non_cap_expI) + +lemma non_cap_exp_ELUsingAArch32[non_cap_expI]: + "non_cap_exp (ELUsingAArch32 el)" + by (unfold ELUsingAArch32_def, non_cap_expI) + +lemma non_cap_exp_AArch64_ExceptionClass[non_cap_expI]: + "non_cap_exp (AArch64_ExceptionClass exceptype target_el)" + by (unfold AArch64_ExceptionClass_def, non_cap_expI) + +lemma non_cap_exp_ELIsInHost[non_cap_expI]: + "non_cap_exp (ELIsInHost el)" + by (unfold ELIsInHost_def, non_cap_expI) + +lemma non_cap_exp_S1TranslationRegime[non_cap_expI]: + "non_cap_exp (S1TranslationRegime el)" + by (unfold S1TranslationRegime_def, non_cap_expI) + +lemma non_cap_exp_S1TranslationRegime__1[non_cap_expI]: + "non_cap_exp (S1TranslationRegime__1 arg0)" + by (unfold S1TranslationRegime__1_def, non_cap_expI) + +lemma non_cap_exp_ESR_set[non_cap_expI]: + "non_cap_exp (ESR_set regime value_name)" + by (unfold ESR_set_def, non_cap_expI) + +lemma non_cap_exp_ESR_set__1[non_cap_expI]: + "non_cap_exp (ESR_set__1 value_name)" + by (unfold ESR_set__1_def, non_cap_expI) + +lemma non_cap_exp_FAR_set[non_cap_expI]: + "non_cap_exp (FAR_set regime value_name)" + by (unfold FAR_set_def, non_cap_expI) + +lemma non_cap_exp_AArch64_ReportException[non_cap_expI]: + "non_cap_exp (AArch64_ReportException exception target_el)" + by (unfold AArch64_ReportException_def, non_cap_expI) + +lemma non_cap_exp_AddrTop[non_cap_expI]: + "non_cap_exp (AddrTop address el)" + by (unfold AddrTop_def, non_cap_expI) + +lemma non_cap_exp_IsInHost[non_cap_expI]: + "non_cap_exp (IsInHost arg0)" + by (unfold IsInHost_def, non_cap_expI) + +lemma non_cap_exp_AArch64_BranchAddr[non_cap_expI]: + "non_cap_exp (AArch64_BranchAddr vaddress)" + by (unfold AArch64_BranchAddr_def, non_cap_expI) + +lemma non_cap_exp_undefined_BranchType[non_cap_expI]: + "non_cap_exp (undefined_BranchType arg0)" + by (unfold undefined_BranchType_def, non_cap_expI) + +lemma non_cap_exp_CapGetTop[non_cap_expI]: + "non_cap_exp (CapGetTop c__arg)" + by (unfold CapGetTop_def, non_cap_expI) + +lemma non_cap_exp_CapGetBounds[non_cap_expI]: + "non_cap_exp (CapGetBounds c__arg)" + by (unfold CapGetBounds_def, non_cap_expI) + +lemma non_cap_exp_CapBoundsEqual[non_cap_expI]: + "non_cap_exp (CapBoundsEqual a b)" + by (unfold CapBoundsEqual_def, non_cap_expI) + +lemma non_cap_exp_CapIsRepresentable[non_cap_expI]: + "non_cap_exp (CapIsRepresentable c__arg address)" + by (unfold CapIsRepresentable_def, non_cap_expI) + +lemma non_cap_exp_CapSetValue[non_cap_expI]: + "non_cap_exp (CapSetValue c__arg v)" + by (unfold CapSetValue_def, non_cap_expI) + +lemma non_cap_exp_BranchAddr[non_cap_expI]: + "non_cap_exp (BranchAddr c__arg el)" + by (unfold BranchAddr_def, non_cap_expI) + +lemma non_cap_exp_CCTLR_read[non_cap_expI]: + "non_cap_exp (CCTLR_read el)" + by (unfold CCTLR_read_def, non_cap_expI) + +lemma non_cap_exp_CCTLR_read__1[non_cap_expI]: + "non_cap_exp (CCTLR_read__1 arg0)" + by (unfold CCTLR_read__1_def, non_cap_expI) + +lemma non_cap_exp_HaveSSBSExt[non_cap_expI]: + "non_cap_exp (HaveSSBSExt arg0)" + by (unfold HaveSSBSExt_def, non_cap_expI) + +lemma non_cap_exp_GetPSRFromPSTATE[non_cap_expI]: + "non_cap_exp (GetPSRFromPSTATE arg0)" + by (unfold GetPSRFromPSTATE_def, non_cap_expI) + +lemma non_cap_exp_HaveRASExt[non_cap_expI]: + "non_cap_exp (HaveRASExt arg0)" + by (unfold HaveRASExt_def, non_cap_expI) + +lemma non_cap_exp_HaveIESB[non_cap_expI]: + "non_cap_exp (HaveIESB arg0)" + by (unfold HaveIESB_def, non_cap_expI) + +lemma non_cap_exp_IsAccessToCapabilitiesDisabledAtEL3[non_cap_expI]: + "non_cap_exp (IsAccessToCapabilitiesDisabledAtEL3 arg0)" + by (unfold IsAccessToCapabilitiesDisabledAtEL3_def, non_cap_expI) + +lemma non_cap_exp_IsSecure[non_cap_expI]: + "non_cap_exp (IsSecure arg0)" + by (unfold IsSecure_def, non_cap_expI) + +lemma non_cap_exp_IsAccessToCapabilitiesDisabledAtEL2[non_cap_expI]: + "non_cap_exp (IsAccessToCapabilitiesDisabledAtEL2 arg0)" + by (unfold IsAccessToCapabilitiesDisabledAtEL2_def, non_cap_expI) + +lemma non_cap_exp_IsAccessToCapabilitiesDisabledAtEL1[non_cap_expI]: + "non_cap_exp (IsAccessToCapabilitiesDisabledAtEL1 arg0)" + by (unfold IsAccessToCapabilitiesDisabledAtEL1_def, non_cap_expI) + +lemma non_cap_exp_IsAccessToCapabilitiesDisabledAtEL0[non_cap_expI]: + "non_cap_exp (IsAccessToCapabilitiesDisabledAtEL0 arg0)" + by (unfold IsAccessToCapabilitiesDisabledAtEL0_def, non_cap_expI) + +lemma non_cap_exp_IsAccessToCapabilitiesEnabledAtEL[non_cap_expI]: + "non_cap_exp (IsAccessToCapabilitiesEnabledAtEL el)" + by (unfold IsAccessToCapabilitiesEnabledAtEL_def, non_cap_expI) + +lemma non_cap_exp_Halted[non_cap_expI]: + "non_cap_exp (Halted arg0)" + by (unfold Halted_def, non_cap_expI) + +lemma non_cap_exp_SCTLR_read[non_cap_expI]: + "non_cap_exp (SCTLR_read regime)" + by (unfold SCTLR_read_def, non_cap_expI) + +lemma non_cap_exp_SCTLR_read__1[non_cap_expI]: + "non_cap_exp (SCTLR_read__1 arg0)" + by (unfold SCTLR_read__1_def, non_cap_expI) + +lemma non_cap_exp_SPSR_set[non_cap_expI]: + "non_cap_exp (SPSR_set value_name)" + by (unfold SPSR_set_def, non_cap_expI) + +lemma non_cap_exp_AArch64_MaybeZeroRegisterUppers[non_cap_expI]: + "non_cap_exp (AArch64_MaybeZeroRegisterUppers arg0)" + by (unfold AArch64_MaybeZeroRegisterUppers_def, non_cap_expI) + +lemma non_cap_exp_ThisInstrAddr[non_cap_expI]: + "non_cap_exp (ThisInstrAddr N)" + by (unfold ThisInstrAddr_def, non_cap_expI) + +lemma non_cap_exp_TargetELForCapabilityExceptions[non_cap_expI]: + "non_cap_exp (TargetELForCapabilityExceptions arg0)" + by (unfold TargetELForCapabilityExceptions_def, non_cap_expI) + +lemma non_cap_exp_CurrentEL_SysRegRead_ac5b30a86a6a5003[non_cap_expI]: + "non_cap_exp (CurrentEL_SysRegRead_ac5b30a86a6a5003 el op0 op1 CRn op2 CRm)" + by (unfold CurrentEL_SysRegRead_ac5b30a86a6a5003_def, non_cap_expI) + +lemma non_cap_exp_ExternalInvasiveDebugEnabled[non_cap_expI]: + "non_cap_exp (ExternalInvasiveDebugEnabled arg0)" + by (unfold ExternalInvasiveDebugEnabled_def, non_cap_expI) + +lemma non_cap_exp_ExternalSecureInvasiveDebugEnabled[non_cap_expI]: + "non_cap_exp (ExternalSecureInvasiveDebugEnabled arg0)" + by (unfold ExternalSecureInvasiveDebugEnabled_def, non_cap_expI) + +lemma non_cap_exp_UpdateEDSCRFields[non_cap_expI]: + "non_cap_exp (UpdateEDSCRFields arg0)" + by (unfold UpdateEDSCRFields_def, non_cap_expI) + +lemma non_cap_exp_DoubleLockStatus[non_cap_expI]: + "non_cap_exp (DoubleLockStatus arg0)" + by (unfold DoubleLockStatus_def, non_cap_expI) + +lemma non_cap_exp_HaltingAllowed[non_cap_expI]: + "non_cap_exp (HaltingAllowed arg0)" + by (unfold HaltingAllowed_def, non_cap_expI) + +lemma non_cap_exp_DCZID_EL0_SysRegRead_dedd61ba7cee2913[non_cap_expI]: + "non_cap_exp (DCZID_EL0_SysRegRead_dedd61ba7cee2913 el op0 op1 CRn op2 CRm)" + by (unfold DCZID_EL0_SysRegRead_dedd61ba7cee2913_def, non_cap_expI) + +lemma non_cap_exp_DSPSR_EL0_SysRegRead_888dc1fa37424d3d[non_cap_expI]: + "non_cap_exp (DSPSR_EL0_SysRegRead_888dc1fa37424d3d el op0 op1 CRn op2 CRm)" + by (unfold DSPSR_EL0_SysRegRead_888dc1fa37424d3d_def, non_cap_expI) + +lemma non_cap_exp_ICC_SRE_EL1_read[non_cap_expI]: + "non_cap_exp (ICC_SRE_EL1_read arg0)" + by (unfold ICC_SRE_EL1_read_def, non_cap_expI) + +lemma non_cap_exp_ICC_BPR1_EL1_read[non_cap_expI]: + "non_cap_exp (ICC_BPR1_EL1_read arg0)" + by (unfold ICC_BPR1_EL1_read_def, non_cap_expI) + +lemma non_cap_exp_ICC_CTLR_EL1_read[non_cap_expI]: + "non_cap_exp (ICC_CTLR_EL1_read arg0)" + by (unfold ICC_CTLR_EL1_read_def, non_cap_expI) + +lemma non_cap_exp_ICC_IGRPEN1_EL1_read[non_cap_expI]: + "non_cap_exp (ICC_IGRPEN1_EL1_read arg0)" + by (unfold ICC_IGRPEN1_EL1_read_def, non_cap_expI) + +lemma non_cap_exp_MPAM2_EL2_read[non_cap_expI]: + "non_cap_exp (MPAM2_EL2_read arg0)" + by (unfold MPAM2_EL2_read_def, non_cap_expI) + +lemma non_cap_exp_MPAM1_EL1_read[non_cap_expI]: + "non_cap_exp (MPAM1_EL1_read arg0)" + by (unfold MPAM1_EL1_read_def, non_cap_expI) + +lemma non_cap_exp_NZCV_SysRegRead_00499c04100376d9[non_cap_expI]: + "non_cap_exp (NZCV_SysRegRead_00499c04100376d9 el op0 op1 CRn op2 CRm)" + by (unfold NZCV_SysRegRead_00499c04100376d9_def, non_cap_expI) + +lemma non_cap_exp_HaveDoubleLock[non_cap_expI]: + "non_cap_exp (HaveDoubleLock arg0)" + by (unfold HaveDoubleLock_def, non_cap_expI) + +lemma non_cap_exp_PAN_SysRegRead_36ab36abf6da91e0[non_cap_expI]: + "non_cap_exp (PAN_SysRegRead_36ab36abf6da91e0 el op0 op1 CRn op2 CRm)" + by (unfold PAN_SysRegRead_36ab36abf6da91e0_def, non_cap_expI) + +lemma non_cap_exp_SPSR_EL12_SysRegRead_a8511792ae31e865[non_cap_expI]: + "non_cap_exp (SPSR_EL12_SysRegRead_a8511792ae31e865 el op0 op1 CRn op2 CRm)" + by (unfold SPSR_EL12_SysRegRead_a8511792ae31e865_def, non_cap_expI) + +lemma non_cap_exp_SPSR_EL1_SysRegRead_32354aa2884c2edd[non_cap_expI]: + "non_cap_exp (SPSR_EL1_SysRegRead_32354aa2884c2edd el op0 op1 CRn op2 CRm)" + by (unfold SPSR_EL1_SysRegRead_32354aa2884c2edd_def, non_cap_expI) + +lemma non_cap_exp_SPSR_EL2_SysRegRead_63ec64f2f805090d[non_cap_expI]: + "non_cap_exp (SPSR_EL2_SysRegRead_63ec64f2f805090d el op0 op1 CRn op2 CRm)" + by (unfold SPSR_EL2_SysRegRead_63ec64f2f805090d_def, non_cap_expI) + +lemma non_cap_exp_SPSR_EL3_SysRegRead_fca96fc0dc593061[non_cap_expI]: + "non_cap_exp (SPSR_EL3_SysRegRead_fca96fc0dc593061 el op0 op1 CRn op2 CRm)" + by (unfold SPSR_EL3_SysRegRead_fca96fc0dc593061_def, non_cap_expI) + +lemma non_cap_exp_SPSR_abt_SysRegRead_7ed396e0808f79f6[non_cap_expI]: + "non_cap_exp (SPSR_abt_SysRegRead_7ed396e0808f79f6 el op0 op1 CRn op2 CRm)" + by (unfold SPSR_abt_SysRegRead_7ed396e0808f79f6_def, non_cap_expI) + +lemma non_cap_exp_SPSR_fiq_SysRegRead_390457aa85161af4[non_cap_expI]: + "non_cap_exp (SPSR_fiq_SysRegRead_390457aa85161af4 el op0 op1 CRn op2 CRm)" + by (unfold SPSR_fiq_SysRegRead_390457aa85161af4_def, non_cap_expI) + +lemma non_cap_exp_SPSR_irq_SysRegRead_8593f29eadca9d64[non_cap_expI]: + "non_cap_exp (SPSR_irq_SysRegRead_8593f29eadca9d64 el op0 op1 CRn op2 CRm)" + by (unfold SPSR_irq_SysRegRead_8593f29eadca9d64_def, non_cap_expI) + +lemma non_cap_exp_SPSR_und_SysRegRead_89a3b7c63cd43460[non_cap_expI]: + "non_cap_exp (SPSR_und_SysRegRead_89a3b7c63cd43460 el op0 op1 CRn op2 CRm)" + by (unfold SPSR_und_SysRegRead_89a3b7c63cd43460_def, non_cap_expI) + +lemma non_cap_exp_SSBS_SysRegRead_05419031832511d1[non_cap_expI]: + "non_cap_exp (SSBS_SysRegRead_05419031832511d1 el op0 op1 CRn op2 CRm)" + by (unfold SSBS_SysRegRead_05419031832511d1_def, non_cap_expI) + +lemma non_cap_exp_UAO_SysRegRead_297f45f7f70ec250[non_cap_expI]: + "non_cap_exp (UAO_SysRegRead_297f45f7f70ec250 el op0 op1 CRn op2 CRm)" + by (unfold UAO_SysRegRead_297f45f7f70ec250_def, non_cap_expI) + +lemma non_cap_exp_DSPSR_EL0_SysRegWrite_6d6dabfcb332ec05[non_cap_expI]: + "non_cap_exp (DSPSR_EL0_SysRegWrite_6d6dabfcb332ec05 el op0 op1 CRn op2 CRm val_name)" + by (unfold DSPSR_EL0_SysRegWrite_6d6dabfcb332ec05_def, non_cap_expI) + +lemma non_cap_exp_ICC_BPR1_EL1_write[non_cap_expI]: + "non_cap_exp (ICC_BPR1_EL1_write val_name)" + by (unfold ICC_BPR1_EL1_write_def, non_cap_expI) + +lemma non_cap_exp_ICC_CTLR_EL1_write[non_cap_expI]: + "non_cap_exp (ICC_CTLR_EL1_write val_name)" + by (unfold ICC_CTLR_EL1_write_def, non_cap_expI) + +lemma non_cap_exp_ICC_IGRPEN1_EL1_write[non_cap_expI]: + "non_cap_exp (ICC_IGRPEN1_EL1_write val_name)" + by (unfold ICC_IGRPEN1_EL1_write_def, non_cap_expI) + +lemma non_cap_exp_ICC_SRE_EL1_write[non_cap_expI]: + "non_cap_exp (ICC_SRE_EL1_write val_name)" + by (unfold ICC_SRE_EL1_write_def, non_cap_expI) + +lemma non_cap_exp_NZCV_SysRegWrite_a047a536d32ae853[non_cap_expI]: + "non_cap_exp (NZCV_SysRegWrite_a047a536d32ae853 el op0 op1 CRn op2 CRm val_name)" + by (unfold NZCV_SysRegWrite_a047a536d32ae853_def, non_cap_expI) + +lemma non_cap_exp_PAN_SysRegWrite_aedbb13e40f0add0[non_cap_expI]: + "non_cap_exp (PAN_SysRegWrite_aedbb13e40f0add0 el op0 op1 CRn op2 CRm val_name)" + by (unfold PAN_SysRegWrite_aedbb13e40f0add0_def, non_cap_expI) + +lemma non_cap_exp_SPSR_EL12_SysRegWrite_cabdb902efd62924[non_cap_expI]: + "non_cap_exp (SPSR_EL12_SysRegWrite_cabdb902efd62924 el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_EL12_SysRegWrite_cabdb902efd62924_def, non_cap_expI) + +lemma non_cap_exp_SPSR_EL1_SysRegWrite_c3a982c3130dcaea[non_cap_expI]: + "non_cap_exp (SPSR_EL1_SysRegWrite_c3a982c3130dcaea el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_EL1_SysRegWrite_c3a982c3130dcaea_def, non_cap_expI) + +lemma non_cap_exp_SPSR_EL2_SysRegWrite_1d65bd974e988727[non_cap_expI]: + "non_cap_exp (SPSR_EL2_SysRegWrite_1d65bd974e988727 el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_EL2_SysRegWrite_1d65bd974e988727_def, non_cap_expI) + +lemma non_cap_exp_SPSR_EL3_SysRegWrite_7b0326ec9be492f4[non_cap_expI]: + "non_cap_exp (SPSR_EL3_SysRegWrite_7b0326ec9be492f4 el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_EL3_SysRegWrite_7b0326ec9be492f4_def, non_cap_expI) + +lemma non_cap_exp_SPSR_abt_SysRegWrite_ecb9f412e44a217b[non_cap_expI]: + "non_cap_exp (SPSR_abt_SysRegWrite_ecb9f412e44a217b el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_abt_SysRegWrite_ecb9f412e44a217b_def, non_cap_expI) + +lemma non_cap_exp_SPSR_fiq_SysRegWrite_760097483f6eab5e[non_cap_expI]: + "non_cap_exp (SPSR_fiq_SysRegWrite_760097483f6eab5e el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_fiq_SysRegWrite_760097483f6eab5e_def, non_cap_expI) + +lemma non_cap_exp_SPSR_irq_SysRegWrite_d42335013c288fbe[non_cap_expI]: + "non_cap_exp (SPSR_irq_SysRegWrite_d42335013c288fbe el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_irq_SysRegWrite_d42335013c288fbe_def, non_cap_expI) + +lemma non_cap_exp_SPSR_und_SysRegWrite_76485ab5b58e2a80[non_cap_expI]: + "non_cap_exp (SPSR_und_SysRegWrite_76485ab5b58e2a80 el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSR_und_SysRegWrite_76485ab5b58e2a80_def, non_cap_expI) + +lemma non_cap_exp_SSBS_SysRegWrite_e080097cffcde083[non_cap_expI]: + "non_cap_exp (SSBS_SysRegWrite_e080097cffcde083 el op0 op1 CRn op2 CRm val_name)" + by (unfold SSBS_SysRegWrite_e080097cffcde083_def, non_cap_expI) + +lemma non_cap_exp_UAO_SysRegWrite_594f371263b733f0[non_cap_expI]: + "non_cap_exp (UAO_SysRegWrite_594f371263b733f0 el op0 op1 CRn op2 CRm val_name)" + by (unfold UAO_SysRegWrite_594f371263b733f0_def, non_cap_expI) + +lemma non_cap_exp_V_set[non_cap_expI]: + "non_cap_exp (V_set width n value_name)" + by (unfold V_set_def, non_cap_expI) + +lemma non_cap_exp_AArch64_ResetSIMDFPRegisters[non_cap_expI]: + "non_cap_exp (AArch64_ResetSIMDFPRegisters arg0)" + by (unfold AArch64_ResetSIMDFPRegisters_def, non_cap_expI) + +lemma non_cap_exp_PAMax[non_cap_expI]: + "non_cap_exp (PAMax arg0)" + by (unfold PAMax_def, non_cap_expI) + +lemma non_cap_exp_EncodeLDFSC[non_cap_expI]: + "non_cap_exp (EncodeLDFSC statuscode level)" + by (unfold EncodeLDFSC_def, non_cap_expI) + +lemma non_cap_exp_IsExternalAbort[non_cap_expI]: + "non_cap_exp (IsExternalAbort statuscode)" + by (unfold IsExternalAbort_def, non_cap_expI) + +lemma non_cap_exp_IsExternalAbort__1[non_cap_expI]: + "non_cap_exp (IsExternalAbort__1 fault)" + by (unfold IsExternalAbort__1_def, non_cap_expI) + +lemma non_cap_exp_IsExternalSyncAbort[non_cap_expI]: + "non_cap_exp (IsExternalSyncAbort statuscode)" + by (unfold IsExternalSyncAbort_def, non_cap_expI) + +lemma non_cap_exp_IsExternalSyncAbort__1[non_cap_expI]: + "non_cap_exp (IsExternalSyncAbort__1 fault)" + by (unfold IsExternalSyncAbort__1_def, non_cap_expI) + +lemma non_cap_exp_IsSecondStage[non_cap_expI]: + "non_cap_exp (IsSecondStage fault)" + by (unfold IsSecondStage_def, non_cap_expI) + +lemma non_cap_exp_AArch64_FaultSyndrome[non_cap_expI]: + "non_cap_exp (AArch64_FaultSyndrome d_side fault)" + by (unfold AArch64_FaultSyndrome_def, non_cap_expI) + +lemma non_cap_exp_IPAValid[non_cap_expI]: + "non_cap_exp (IPAValid fault)" + by (unfold IPAValid_def, non_cap_expI) + +lemma non_cap_exp_AArch64_AbortSyndrome[non_cap_expI]: + "non_cap_exp (AArch64_AbortSyndrome exceptype fault vaddress)" + by (unfold AArch64_AbortSyndrome_def, non_cap_expI) + +lemma non_cap_exp_IsDebugException[non_cap_expI]: + "non_cap_exp (IsDebugException fault)" + by (unfold IsDebugException_def, non_cap_expI) + +lemma non_cap_exp_ConstrainUnpredictableBits[non_cap_expI]: + "non_cap_exp (ConstrainUnpredictableBits width which)" + by (unfold ConstrainUnpredictableBits_def, non_cap_expI) + +lemma non_cap_exp_ConstrainUnpredictableInteger[non_cap_expI]: + "non_cap_exp (ConstrainUnpredictableInteger low high which)" + by (unfold ConstrainUnpredictableInteger_def, non_cap_expI) + +lemma non_cap_exp_Have16bitVMID[non_cap_expI]: + "non_cap_exp (Have16bitVMID arg0)" + by (unfold Have16bitVMID_def, non_cap_expI) + +lemma non_cap_exp_AArch64_BreakpointValueMatch[non_cap_expI]: + "non_cap_exp (AArch64_BreakpointValueMatch n__arg vaddress linked_to)" + by (unfold AArch64_BreakpointValueMatch_def, non_cap_expI) + +lemma non_cap_exp_CheckValidStateMatch[non_cap_expI]: + "non_cap_exp (CheckValidStateMatch SSC__arg HMC__arg PxC__arg isbreakpnt)" + by (unfold CheckValidStateMatch_def, non_cap_expI) + +lemma non_cap_exp_AArch64_StateMatch[non_cap_expI]: + "non_cap_exp (AArch64_StateMatch SSC__arg HMC__arg PxC__arg linked__arg LBN isbreakpnt ispriv)" + by (unfold AArch64_StateMatch_def, non_cap_expI) + +lemma non_cap_exp_AArch64_BreakpointMatch[non_cap_expI]: + "non_cap_exp (AArch64_BreakpointMatch n vaddress size__arg)" + by (unfold AArch64_BreakpointMatch_def, non_cap_expI) + +lemma non_cap_exp_undefined_AccType[non_cap_expI]: + "non_cap_exp (undefined_AccType arg0)" + by (unfold undefined_AccType_def, non_cap_expI) + +lemma non_cap_exp_undefined_Fault[non_cap_expI]: + "non_cap_exp (undefined_Fault arg0)" + by (unfold undefined_Fault_def, non_cap_expI) + +lemma non_cap_exp_undefined_FaultRecord[non_cap_expI]: + "non_cap_exp (undefined_FaultRecord arg0)" + by (unfold undefined_FaultRecord_def, non_cap_expI) + +lemma non_cap_exp_AArch64_CreateFaultRecord[non_cap_expI]: + "non_cap_exp (AArch64_CreateFaultRecord statuscode ipaddress level acctype write extflag errortype secondstage s2fs1walk)" + by (unfold AArch64_CreateFaultRecord_def, non_cap_expI) + +lemma non_cap_exp_AArch64_DebugFault[non_cap_expI]: + "non_cap_exp (AArch64_DebugFault acctype iswrite)" + by (unfold AArch64_DebugFault_def, non_cap_expI) + +lemma non_cap_exp_AArch64_NoFault[non_cap_expI]: + "non_cap_exp (AArch64_NoFault arg0)" + by (unfold AArch64_NoFault_def, non_cap_expI) + +lemma non_cap_exp_HaltOnBreakpointOrWatchpoint[non_cap_expI]: + "non_cap_exp (HaltOnBreakpointOrWatchpoint arg0)" + by (unfold HaltOnBreakpointOrWatchpoint_def, non_cap_expI) + +lemma non_cap_exp_AArch64_AccessUsesEL[non_cap_expI]: + "non_cap_exp (AArch64_AccessUsesEL acctype)" + by (unfold AArch64_AccessUsesEL_def, non_cap_expI) + +lemma non_cap_exp_AArch64_AccessIsPrivileged[non_cap_expI]: + "non_cap_exp (AArch64_AccessIsPrivileged acctype)" + by (unfold AArch64_AccessIsPrivileged_def, non_cap_expI) + +lemma non_cap_exp_AArch64_WatchpointByteMatch[non_cap_expI]: + "non_cap_exp (AArch64_WatchpointByteMatch n vaddress)" + by (unfold AArch64_WatchpointByteMatch_def, non_cap_expI) + +lemma non_cap_exp_AArch64_WatchpointMatch[non_cap_expI]: + "non_cap_exp (AArch64_WatchpointMatch n vaddress size__arg ispriv iswrite)" + by (unfold AArch64_WatchpointMatch_def, non_cap_expI) + +lemma non_cap_exp_AArch64_GenerateDebugExceptionsFrom[non_cap_expI]: + "non_cap_exp (AArch64_GenerateDebugExceptionsFrom from secure mask__arg)" + by (unfold AArch64_GenerateDebugExceptionsFrom_def, non_cap_expI) + +lemma non_cap_exp_AArch64_GenerateDebugExceptions[non_cap_expI]: + "non_cap_exp (AArch64_GenerateDebugExceptions arg0)" + by (unfold AArch64_GenerateDebugExceptions_def, non_cap_expI) + +lemma non_cap_exp_AArch64_AddressSizeFault[non_cap_expI]: + "non_cap_exp (AArch64_AddressSizeFault ipaddress level acctype iswrite secondstage s2fs1walk)" + by (unfold AArch64_AddressSizeFault_def, non_cap_expI) + +lemma non_cap_exp_HasS2Translation[non_cap_expI]: + "non_cap_exp (HasS2Translation arg0)" + by (unfold HasS2Translation_def, non_cap_expI) + +lemma non_cap_exp_AArch64_IsStageOneEnabled[non_cap_expI]: + "non_cap_exp (AArch64_IsStageOneEnabled acctype)" + by (unfold AArch64_IsStageOneEnabled_def, non_cap_expI) + +lemma non_cap_exp_undefined_FullAddress[non_cap_expI]: + "non_cap_exp (undefined_FullAddress arg0)" + by (unfold undefined_FullAddress_def, non_cap_expI) + +lemma non_cap_exp_undefined_DeviceType[non_cap_expI]: + "non_cap_exp (undefined_DeviceType arg0)" + by (unfold undefined_DeviceType_def, non_cap_expI) + +lemma non_cap_exp_undefined_MemAttrHints[non_cap_expI]: + "non_cap_exp (undefined_MemAttrHints arg0)" + by (unfold undefined_MemAttrHints_def, non_cap_expI) + +lemma non_cap_exp_undefined_MemType[non_cap_expI]: + "non_cap_exp (undefined_MemType arg0)" + by (unfold undefined_MemType_def, non_cap_expI) + +lemma non_cap_exp_undefined_MemoryAttributes[non_cap_expI]: + "non_cap_exp (undefined_MemoryAttributes arg0)" + by (unfold undefined_MemoryAttributes_def, non_cap_expI) + +lemma non_cap_exp_undefined_AddressDescriptor[non_cap_expI]: + "non_cap_exp (undefined_AddressDescriptor arg0)" + by (unfold undefined_AddressDescriptor_def, non_cap_expI) + +lemma non_cap_exp_AArch64_FirstStageTranslateWithTag[non_cap_expI]: + "non_cap_exp (AArch64_FirstStageTranslateWithTag vaddress acctype iswrite wasaligned size__arg iswritevalidcap)" + by (unfold AArch64_FirstStageTranslateWithTag_def, non_cap_expI) + +lemma non_cap_exp_AArch64_FullTranslateWithTag[non_cap_expI]: + "non_cap_exp (AArch64_FullTranslateWithTag vaddress acctype iswrite wasaligned size__arg iswritevalidcap__arg)" + by (unfold AArch64_FullTranslateWithTag_def, non_cap_expI) + +lemma non_cap_exp_CapIsRangeInBounds[non_cap_expI]: + "non_cap_exp (CapIsRangeInBounds c__arg start_address length__arg)" + by (unfold CapIsRangeInBounds_def, non_cap_expI) + +lemma non_cap_exp_CapabilityFault[non_cap_expI]: + "non_cap_exp (CapabilityFault faulttype acctype iswrite)" + by (unfold CapabilityFault_def, non_cap_expI) + +lemma non_cap_exp_IsInC64[non_cap_expI]: + "non_cap_exp (IsInC64 arg0)" + by (unfold IsInC64_def, non_cap_expI) + +lemma non_cap_exp_undefined_VirtualAddressType[non_cap_expI]: + "non_cap_exp (undefined_VirtualAddressType arg0)" + by (unfold undefined_VirtualAddressType_def, non_cap_expI) + +lemma non_cap_exp_undefined_VirtualAddress[non_cap_expI]: + "non_cap_exp (undefined_VirtualAddress arg0)" + by (unfold undefined_VirtualAddress_def, non_cap_expI) + +lemma non_cap_exp_VAFromBits64[non_cap_expI]: + "non_cap_exp (VAFromBits64 b)" + by (unfold VAFromBits64_def, non_cap_expI) + +lemma non_cap_exp_VAFromCapability[non_cap_expI]: + "non_cap_exp (VAFromCapability c__arg)" + by (unfold VAFromCapability_def, non_cap_expI) + +lemma non_cap_exp_VAToCapability[non_cap_expI]: + "non_cap_exp (VAToCapability v)" + by (unfold VAToCapability_def, non_cap_expI) + +lemma non_cap_exp_CapGetBase[non_cap_expI]: + "non_cap_exp (CapGetBase c__arg)" + by (unfold CapGetBase_def, non_cap_expI) + +lemma non_cap_exp_VAToBits64[non_cap_expI]: + "non_cap_exp (VAToBits64 v)" + by (unfold VAToBits64_def, non_cap_expI) + +lemma non_cap_exp_AArch64_PARFaultStatus[non_cap_expI]: + "non_cap_exp (AArch64_PARFaultStatus fault)" + by (unfold AArch64_PARFaultStatus_def, non_cap_expI) + +lemma non_cap_exp_PARAttrsDecode[non_cap_expI]: + "non_cap_exp (PARAttrsDecode memattrs)" + by (unfold PARAttrsDecode_def, non_cap_expI) + +lemma non_cap_exp_PARShareabilityDecode[non_cap_expI]: + "non_cap_exp (PARShareabilityDecode memattrs)" + by (unfold PARShareabilityDecode_def, non_cap_expI) + +lemma non_cap_exp_AArch64_EncodePAR[non_cap_expI]: + "non_cap_exp (AArch64_EncodePAR addrdesc)" + by (unfold AArch64_EncodePAR_def, non_cap_expI) + +lemma non_cap_exp_AArch64_FirstStageTranslate[non_cap_expI]: + "non_cap_exp (AArch64_FirstStageTranslate vaddress acctype iswrite wasaligned size__arg)" + by (unfold AArch64_FirstStageTranslate_def, non_cap_expI) + +lemma non_cap_exp_RESTORE_EL[non_cap_expI]: + "non_cap_exp (RESTORE_EL arg0)" + by (unfold RESTORE_EL_def, non_cap_expI) + +lemma non_cap_exp_SAVE_EL[non_cap_expI]: + "non_cap_exp (SAVE_EL new_exception_level)" + by (unfold SAVE_EL_def, non_cap_expI) + +lemma non_cap_exp_AArch64_FullTranslate[non_cap_expI]: + "non_cap_exp (AArch64_FullTranslate vaddress acctype iswrite wasaligned size__arg)" + by (unfold AArch64_FullTranslate_def, non_cap_expI) + +lemma non_cap_exp_undefined_MPAMinfo[non_cap_expI]: + "non_cap_exp (undefined_MPAMinfo arg0)" + by (unfold undefined_MPAMinfo_def, non_cap_expI) + +lemma non_cap_exp_DefaultMPAMinfo[non_cap_expI]: + "non_cap_exp (DefaultMPAMinfo secure)" + by (unfold DefaultMPAMinfo_def, non_cap_expI) + +lemma non_cap_exp_HaveMPAMExt[non_cap_expI]: + "non_cap_exp (HaveMPAMExt arg0)" + by (unfold HaveMPAMExt_def, non_cap_expI) + +lemma non_cap_exp_MPAMisEnabled[non_cap_expI]: + "non_cap_exp (MPAMisEnabled arg0)" + by (unfold MPAMisEnabled_def, non_cap_expI) + +lemma non_cap_exp_mapvpmw[non_cap_expI]: + "non_cap_exp (mapvpmw vpartid)" + by (unfold mapvpmw_def, non_cap_expI) + +lemma non_cap_exp_MAP_vPARTID[non_cap_expI]: + "non_cap_exp (MAP_vPARTID vpartid)" + by (unfold MAP_vPARTID_def, non_cap_expI) + +lemma non_cap_exp_MPAMisVirtual[non_cap_expI]: + "non_cap_exp (MPAMisVirtual el)" + by (unfold MPAMisVirtual_def, non_cap_expI) + +lemma non_cap_exp_getMPAM_PARTID[non_cap_expI]: + "non_cap_exp (getMPAM_PARTID MPAMn InD)" + by (unfold getMPAM_PARTID_def, non_cap_expI) + +lemma non_cap_exp_genPARTID[non_cap_expI]: + "non_cap_exp (genPARTID el InD)" + by (unfold genPARTID_def, non_cap_expI) + +lemma non_cap_exp_getMPAM_PMG[non_cap_expI]: + "non_cap_exp (getMPAM_PMG MPAMn InD)" + by (unfold getMPAM_PMG_def, non_cap_expI) + +lemma non_cap_exp_genPMG[non_cap_expI]: + "non_cap_exp (genPMG el InD partid_err)" + by (unfold genPMG_def, non_cap_expI) + +lemma non_cap_exp_genMPAM[non_cap_expI]: + "non_cap_exp (genMPAM el InD secure)" + by (unfold genMPAM_def, non_cap_expI) + +lemma non_cap_exp_GenMPAMcurEL[non_cap_expI]: + "non_cap_exp (GenMPAMcurEL InD)" + by (unfold GenMPAMcurEL_def, non_cap_expI) + +lemma non_cap_exp_undefined_AccessDescriptor[non_cap_expI]: + "non_cap_exp (undefined_AccessDescriptor arg0)" + by (unfold undefined_AccessDescriptor_def, non_cap_expI) + +lemma non_cap_exp_CreateAccessDescriptor[non_cap_expI]: + "non_cap_exp (CreateAccessDescriptor acctype)" + by (unfold CreateAccessDescriptor_def, non_cap_expI) + +lemma non_cap_exp_undefined_MBReqDomain[non_cap_expI]: + "non_cap_exp (undefined_MBReqDomain arg0)" + by (unfold undefined_MBReqDomain_def, non_cap_expI) + +lemma non_cap_exp_undefined_MBReqTypes[non_cap_expI]: + "non_cap_exp (undefined_MBReqTypes arg0)" + by (unfold undefined_MBReqTypes_def, non_cap_expI) + +lemma non_cap_exp_undefined_PrefetchHint[non_cap_expI]: + "non_cap_exp (undefined_PrefetchHint arg0)" + by (unfold undefined_PrefetchHint_def, non_cap_expI) + +lemma non_cap_exp_undefined_FPRounding[non_cap_expI]: + "non_cap_exp (undefined_FPRounding arg0)" + by (unfold undefined_FPRounding_def, non_cap_expI) + +lemma non_cap_exp_undefined_FPType[non_cap_expI]: + "non_cap_exp (undefined_FPType arg0)" + by (unfold undefined_FPType_def, non_cap_expI) + +lemma non_cap_exp_UNKNOWN_VirtualAddressType[non_cap_expI]: + "non_cap_exp (UNKNOWN_VirtualAddressType arg0)" + by (unfold UNKNOWN_VirtualAddressType_def, non_cap_expI) + +lemma non_cap_exp_undefined_ExtendType[non_cap_expI]: + "non_cap_exp (undefined_ExtendType arg0)" + by (unfold undefined_ExtendType_def, non_cap_expI) + +lemma non_cap_exp_undefined_FPMaxMinOp[non_cap_expI]: + "non_cap_exp (undefined_FPMaxMinOp arg0)" + by (unfold undefined_FPMaxMinOp_def, non_cap_expI) + +lemma non_cap_exp_undefined_FPUnaryOp[non_cap_expI]: + "non_cap_exp (undefined_FPUnaryOp arg0)" + by (unfold undefined_FPUnaryOp_def, non_cap_expI) + +lemma non_cap_exp_undefined_FPConvOp[non_cap_expI]: + "non_cap_exp (undefined_FPConvOp arg0)" + by (unfold undefined_FPConvOp_def, non_cap_expI) + +lemma non_cap_exp_undefined_MoveWideOp[non_cap_expI]: + "non_cap_exp (undefined_MoveWideOp arg0)" + by (unfold undefined_MoveWideOp_def, non_cap_expI) + +lemma non_cap_exp_undefined_ShiftType[non_cap_expI]: + "non_cap_exp (undefined_ShiftType arg0)" + by (unfold undefined_ShiftType_def, non_cap_expI) + +lemma non_cap_exp_undefined_LogicalOp[non_cap_expI]: + "non_cap_exp (undefined_LogicalOp arg0)" + by (unfold undefined_LogicalOp_def, non_cap_expI) + +lemma non_cap_exp_undefined_MemOp[non_cap_expI]: + "non_cap_exp (undefined_MemOp arg0)" + by (unfold undefined_MemOp_def, non_cap_expI) + +lemma non_cap_exp_undefined_MemAtomicOp[non_cap_expI]: + "non_cap_exp (undefined_MemAtomicOp arg0)" + by (unfold undefined_MemAtomicOp_def, non_cap_expI) + +lemma non_cap_exp_undefined_SystemHintOp[non_cap_expI]: + "non_cap_exp (undefined_SystemHintOp arg0)" + by (unfold undefined_SystemHintOp_def, non_cap_expI) + +lemma non_cap_exp_undefined_PSTATEField[non_cap_expI]: + "non_cap_exp (undefined_PSTATEField arg0)" + by (unfold undefined_PSTATEField_def, non_cap_expI) + +lemma non_cap_exp_undefined_VBitOp[non_cap_expI]: + "non_cap_exp (undefined_VBitOp arg0)" + by (unfold undefined_VBitOp_def, non_cap_expI) + +lemma non_cap_exp_undefined_CompareOp[non_cap_expI]: + "non_cap_exp (undefined_CompareOp arg0)" + by (unfold undefined_CompareOp_def, non_cap_expI) + +lemma non_cap_exp_undefined_ImmediateOp[non_cap_expI]: + "non_cap_exp (undefined_ImmediateOp arg0)" + by (unfold undefined_ImmediateOp_def, non_cap_expI) + +lemma non_cap_exp_SetThisInstr[non_cap_expI]: + "non_cap_exp (SetThisInstr opcode)" + by (unfold SetThisInstr_def, non_cap_expI) + +lemma non_cap_exp_LowestSetBit[non_cap_expI]: + "non_cap_exp (LowestSetBit x)" + by (unfold LowestSetBit_def, non_cap_expI) + +lemma non_cap_exp_HighestSetBit[non_cap_expI]: + "non_cap_exp (HighestSetBit x)" + by (unfold HighestSetBit_def, non_cap_expI) + +lemma non_cap_exp_Elem_read[non_cap_expI]: + "non_cap_exp (Elem_read vector_name e size__arg)" + by (unfold Elem_read_def, non_cap_expI) + +lemma non_cap_exp_Elem_set[non_cap_expI]: + "non_cap_exp (Elem_set vector_name__arg e size__arg value_name)" + by (unfold Elem_set_def, non_cap_expI) + +lemma non_cap_exp_BigEndian[non_cap_expI]: + "non_cap_exp (BigEndian arg0)" + by (unfold BigEndian_def, non_cap_expI) + +lemma non_cap_exp_EffectiveTGEN[non_cap_expI]: + "non_cap_exp (EffectiveTGEN address el)" + by (unfold EffectiveTGEN_def, non_cap_expI) + +lemma non_cap_exp_ELFromSPSR[non_cap_expI]: + "non_cap_exp (ELFromSPSR spsr)" + by (unfold ELFromSPSR_def, non_cap_expI) + +lemma non_cap_exp_ELUsingAArch32K[non_cap_expI]: + "non_cap_exp (ELUsingAArch32K el)" + by (unfold ELUsingAArch32K_def, non_cap_expI) + +lemma non_cap_exp_IllegalExceptionReturn[non_cap_expI]: + "non_cap_exp (IllegalExceptionReturn spsr)" + by (unfold IllegalExceptionReturn_def, non_cap_expI) + +lemma non_cap_exp_DebugTargetFrom[non_cap_expI]: + "non_cap_exp (DebugTargetFrom secure)" + by (unfold DebugTargetFrom_def, non_cap_expI) + +lemma non_cap_exp_Restarting[non_cap_expI]: + "non_cap_exp (Restarting arg0)" + by (unfold Restarting_def, non_cap_expI) + +lemma non_cap_exp_DebugExceptionReturnSS[non_cap_expI]: + "non_cap_exp (DebugExceptionReturnSS spsr)" + by (unfold DebugExceptionReturnSS_def, non_cap_expI) + +lemma non_cap_exp_SetPSTATEFromPSR[non_cap_expI]: + "non_cap_exp (SetPSTATEFromPSR spsr__arg)" + by (unfold SetPSTATEFromPSR_def, non_cap_expI) + +lemma non_cap_exp_SendEventLocal[non_cap_expI]: + "non_cap_exp (SendEventLocal arg0)" + by (unfold SendEventLocal_def, non_cap_expI) + +lemma non_cap_exp_ClearEventRegister[non_cap_expI]: + "non_cap_exp (ClearEventRegister arg0)" + by (unfold ClearEventRegister_def, non_cap_expI) + +lemma non_cap_exp_IsEventRegisterSet[non_cap_expI]: + "non_cap_exp (IsEventRegisterSet arg0)" + by (unfold IsEventRegisterSet_def, non_cap_expI) + +lemma non_cap_exp_WaitForEvent[non_cap_expI]: + "non_cap_exp (WaitForEvent arg0)" + by (unfold WaitForEvent_def, non_cap_expI) + +lemma non_cap_exp_BitReverse[non_cap_expI]: + "non_cap_exp (BitReverse data)" + by (unfold BitReverse_def, non_cap_expI) + +lemma non_cap_exp_HaveAESExt[non_cap_expI]: + "non_cap_exp (HaveAESExt arg0)" + by (unfold HaveAESExt_def, non_cap_expI) + +lemma non_cap_exp_HaveBit128PMULLExt[non_cap_expI]: + "non_cap_exp (HaveBit128PMULLExt arg0)" + by (unfold HaveBit128PMULLExt_def, non_cap_expI) + +lemma non_cap_exp_HaveSHA1Ext[non_cap_expI]: + "non_cap_exp (HaveSHA1Ext arg0)" + by (unfold HaveSHA1Ext_def, non_cap_expI) + +lemma non_cap_exp_HaveSHA256Ext[non_cap_expI]: + "non_cap_exp (HaveSHA256Ext arg0)" + by (unfold HaveSHA256Ext_def, non_cap_expI) + +lemma non_cap_exp_HaveSHA512Ext[non_cap_expI]: + "non_cap_exp (HaveSHA512Ext arg0)" + by (unfold HaveSHA512Ext_def, non_cap_expI) + +lemma non_cap_exp_HaveSHA3Ext[non_cap_expI]: + "non_cap_exp (HaveSHA3Ext arg0)" + by (unfold HaveSHA3Ext_def, non_cap_expI) + +lemma non_cap_exp_HaveSM3Ext[non_cap_expI]: + "non_cap_exp (HaveSM3Ext arg0)" + by (unfold HaveSM3Ext_def, non_cap_expI) + +lemma non_cap_exp_HaveSM4Ext[non_cap_expI]: + "non_cap_exp (HaveSM4Ext arg0)" + by (unfold HaveSM4Ext_def, non_cap_expI) + +lemma non_cap_exp_ROL[non_cap_expI]: + "non_cap_exp (ROL x shift)" + by (unfold ROL_def, non_cap_expI) + +lemma non_cap_exp_AESSubBytes[non_cap_expI]: + "non_cap_exp (AESSubBytes op)" + by (unfold AESSubBytes_def, non_cap_expI) + +lemma non_cap_exp_AESInvSubBytes[non_cap_expI]: + "non_cap_exp (AESInvSubBytes op)" + by (unfold AESInvSubBytes_def, non_cap_expI) + +lemma non_cap_exp_AESMixColumns[non_cap_expI]: + "non_cap_exp (AESMixColumns op)" + by (unfold AESMixColumns_def, non_cap_expI) + +lemma non_cap_exp_AESInvMixColumns[non_cap_expI]: + "non_cap_exp (AESInvMixColumns op)" + by (unfold AESInvMixColumns_def, non_cap_expI) + +lemma non_cap_exp_SHA256hash[non_cap_expI]: + "non_cap_exp (SHA256hash X__arg Y__arg W part1)" + by (unfold SHA256hash_def, non_cap_expI) + +lemma non_cap_exp_RecipEstimate[non_cap_expI]: + "non_cap_exp (RecipEstimate a__arg)" + by (unfold RecipEstimate_def, non_cap_expI) + +lemma non_cap_exp_UnsignedRecipEstimate[non_cap_expI]: + "non_cap_exp (UnsignedRecipEstimate operand)" + by (unfold UnsignedRecipEstimate_def, non_cap_expI) + +lemma non_cap_exp_RecipSqrtEstimate[non_cap_expI]: + "non_cap_exp (RecipSqrtEstimate a__arg)" + by (unfold RecipSqrtEstimate_def, non_cap_expI) + +lemma non_cap_exp_UnsignedRSqrtEstimate[non_cap_expI]: + "non_cap_exp (UnsignedRSqrtEstimate operand)" + by (unfold UnsignedRSqrtEstimate_def, non_cap_expI) + +lemma non_cap_exp_SignedSatQ[non_cap_expI]: + "non_cap_exp (SignedSatQ i N)" + by (unfold SignedSatQ_def, non_cap_expI) + +lemma non_cap_exp_UnsignedSatQ__1[non_cap_expI]: + "non_cap_exp (UnsignedSatQ__1 i N M)" + by (unfold UnsignedSatQ__1_def, non_cap_expI) + +lemma non_cap_exp_UnsignedSatQ[non_cap_expI]: + "non_cap_exp (UnsignedSatQ i N)" + by (unfold UnsignedSatQ_def, non_cap_expI) + +lemma non_cap_exp_SatQ[non_cap_expI]: + "non_cap_exp (SatQ i N is_unsigned)" + by (unfold SatQ_def, non_cap_expI) + +lemma non_cap_exp_AdvSIMDExpandImm[non_cap_expI]: + "non_cap_exp (AdvSIMDExpandImm op cmode imm8)" + by (unfold AdvSIMDExpandImm_def, non_cap_expI) + +lemma non_cap_exp_FPInfinity[non_cap_expI]: + "non_cap_exp (FPInfinity l__634 sign)" + by (unfold FPInfinity_def, non_cap_expI) + +lemma non_cap_exp_FPMaxNormal[non_cap_expI]: + "non_cap_exp (FPMaxNormal l__631 sign)" + by (unfold FPMaxNormal_def, non_cap_expI) + +lemma non_cap_exp_FPZero[non_cap_expI]: + "non_cap_exp (FPZero l__628 sign)" + by (unfold FPZero_def, non_cap_expI) + +lemma non_cap_exp_FPDecodeRounding[non_cap_expI]: + "non_cap_exp (FPDecodeRounding rmode)" + by (unfold FPDecodeRounding_def, non_cap_expI) + +lemma non_cap_exp_FPRoundingMode[non_cap_expI]: + "non_cap_exp (FPRoundingMode fpcr)" + by (unfold FPRoundingMode_def, non_cap_expI) + +lemma non_cap_exp_FPAbs[non_cap_expI]: + "non_cap_exp (FPAbs op)" + by (unfold FPAbs_def, non_cap_expI) + +lemma non_cap_exp_FPDefaultNaN[non_cap_expI]: + "non_cap_exp (FPDefaultNaN l__616)" + by (unfold FPDefaultNaN_def, non_cap_expI) + +lemma non_cap_exp_FPConvertNaN[non_cap_expI]: + "non_cap_exp (FPConvertNaN M op)" + by (unfold FPConvertNaN_def, non_cap_expI) + +lemma non_cap_exp_FPTwo[non_cap_expI]: + "non_cap_exp (FPTwo l__601 sign)" + by (unfold FPTwo_def, non_cap_expI) + +lemma non_cap_exp_FPNeg[non_cap_expI]: + "non_cap_exp (FPNeg op)" + by (unfold FPNeg_def, non_cap_expI) + +lemma non_cap_exp_FPOnePointFive[non_cap_expI]: + "non_cap_exp (FPOnePointFive l__595 sign)" + by (unfold FPOnePointFive_def, non_cap_expI) + +lemma non_cap_exp_VFPExpandImm[non_cap_expI]: + "non_cap_exp (VFPExpandImm l__571 imm8)" + by (unfold VFPExpandImm_def, non_cap_expI) + +lemma non_cap_exp_CapIsRepresentableFast[non_cap_expI]: + "non_cap_exp (CapIsRepresentableFast c__arg increment_name__arg)" + by (unfold CapIsRepresentableFast_def, non_cap_expI) + +lemma non_cap_exp_CapAdd[non_cap_expI]: + "non_cap_exp (CapAdd c__arg increment_name)" + by (unfold CapAdd_def, non_cap_expI) + +lemma non_cap_exp_CapAdd__1[non_cap_expI]: + "non_cap_exp (CapAdd__1 c__arg increment_name)" + by (unfold CapAdd__1_def, non_cap_expI) + +lemma non_cap_exp_SPSR_read[non_cap_expI]: + "non_cap_exp (SPSR_read arg0)" + by (unfold SPSR_read_def, non_cap_expI) + +lemma non_cap_exp_HaveSBExt[non_cap_expI]: + "non_cap_exp (HaveSBExt arg0)" + by (unfold HaveSBExt_def, non_cap_expI) + +lemma non_cap_exp_V_read[non_cap_expI]: + "non_cap_exp (V_read width n)" + by (unfold V_read_def, non_cap_expI) + +lemma non_cap_exp_Vpart_read[non_cap_expI]: + "non_cap_exp (Vpart_read width n part)" + by (unfold Vpart_read_def, non_cap_expI) + +lemma non_cap_exp_Vpart_set[non_cap_expI]: + "non_cap_exp (Vpart_set width n part value_name)" + by (unfold Vpart_set_def, non_cap_expI) + +lemma non_cap_exp_FAR_read[non_cap_expI]: + "non_cap_exp (FAR_read regime)" + by (unfold FAR_read_def, non_cap_expI) + +lemma non_cap_exp_FAR_read__1[non_cap_expI]: + "non_cap_exp (FAR_read__1 arg0)" + by (unfold FAR_read__1_def, non_cap_expI) + +lemma non_cap_exp_ESR_read[non_cap_expI]: + "non_cap_exp (ESR_read regime)" + by (unfold ESR_read_def, non_cap_expI) + +lemma non_cap_exp_ESR_read__1[non_cap_expI]: + "non_cap_exp (ESR_read__1 arg0)" + by (unfold ESR_read__1_def, non_cap_expI) + +lemma non_cap_exp_CPACR_read[non_cap_expI]: + "non_cap_exp (CPACR_read arg0)" + by (unfold CPACR_read_def, non_cap_expI) + +lemma non_cap_exp_AArch64_SysInstrInputIsCapability[non_cap_expI]: + "non_cap_exp (AArch64_SysInstrInputIsCapability op0 op1 crn crm op2)" + by (unfold AArch64_SysInstrInputIsCapability_def, non_cap_expI) + +lemma non_cap_exp_AArch64_AlignmentFault[non_cap_expI]: + "non_cap_exp (AArch64_AlignmentFault acctype iswrite secondstage)" + by (unfold AArch64_AlignmentFault_def, non_cap_expI) + +lemma non_cap_exp_AArch64_CapabilityPagePermissionFault[non_cap_expI]: + "non_cap_exp (AArch64_CapabilityPagePermissionFault acctype secondstage is_store)" + by (unfold AArch64_CapabilityPagePermissionFault_def, non_cap_expI) + +lemma non_cap_exp_CapabilityFromData[non_cap_expI]: + "non_cap_exp (CapabilityFromData size__arg tag data)" + by (unfold CapabilityFromData_def, non_cap_expI) + +lemma non_cap_exp_AArch64_ReportDeferredSError[non_cap_expI]: + "non_cap_exp (AArch64_ReportDeferredSError syndrome)" + by (unfold AArch64_ReportDeferredSError_def, non_cap_expI) + +lemma non_cap_exp_ExternalDebugInterruptsDisabled[non_cap_expI]: + "non_cap_exp (ExternalDebugInterruptsDisabled target)" + by (unfold ExternalDebugInterruptsDisabled_def, non_cap_expI) + +lemma non_cap_exp_AArch64_ESBOperation[non_cap_expI]: + "non_cap_exp (AArch64_ESBOperation arg0)" + by (unfold AArch64_ESBOperation_def, non_cap_expI) + +lemma non_cap_exp_AArch64_vESBOperation[non_cap_expI]: + "non_cap_exp (AArch64_vESBOperation arg0)" + by (unfold AArch64_vESBOperation_def, non_cap_expI) + +lemma non_cap_exp_DebugTarget[non_cap_expI]: + "non_cap_exp (DebugTarget arg0)" + by (unfold DebugTarget_def, non_cap_expI) + +lemma non_cap_exp_SSAdvance[non_cap_expI]: + "non_cap_exp (SSAdvance arg0)" + by (unfold SSAdvance_def, non_cap_expI) + +lemma non_cap_exp_NextInstrAddr[non_cap_expI]: + "non_cap_exp (NextInstrAddr N)" + by (unfold NextInstrAddr_def, non_cap_expI) + +lemma non_cap_exp_IsTagSettingDisabled[non_cap_expI]: + "non_cap_exp (IsTagSettingDisabled arg0)" + by (unfold IsTagSettingDisabled_def, non_cap_expI) + +lemma non_cap_exp_DecodeRegExtend[non_cap_expI]: + "non_cap_exp (DecodeRegExtend op)" + by (unfold DecodeRegExtend_def, non_cap_expI) + +lemma non_cap_exp_DecodeBitMasks[non_cap_expI]: + "non_cap_exp (DecodeBitMasks M immN imms immr immediate)" + by (unfold DecodeBitMasks_def, non_cap_expI) + +lemma non_cap_exp_DecodeShift[non_cap_expI]: + "non_cap_exp (DecodeShift op)" + by (unfold DecodeShift_def, non_cap_expI) + +lemma non_cap_exp_Prefetch[non_cap_expI]: + "non_cap_exp (Prefetch address prfop)" + by (unfold Prefetch_def, non_cap_expI) + +lemma non_cap_exp_CapSetBounds[non_cap_expI]: + "non_cap_exp (CapSetBounds c__arg req_len exact)" + by (unfold CapSetBounds_def, non_cap_expI) + +lemma non_cap_exp_CapGetRepresentableMask[non_cap_expI]: + "non_cap_exp (CapGetRepresentableMask len)" + by (unfold CapGetRepresentableMask_def, non_cap_expI) + +lemma non_cap_exp_CapIsBaseAboveLimit[non_cap_expI]: + "non_cap_exp (CapIsBaseAboveLimit c__arg)" + by (unfold CapIsBaseAboveLimit_def, non_cap_expI) + +lemma non_cap_exp_CapIsSubSetOf[non_cap_expI]: + "non_cap_exp (CapIsSubSetOf a b)" + by (unfold CapIsSubSetOf_def, non_cap_expI) + +lemma non_cap_exp_CapGetOffset[non_cap_expI]: + "non_cap_exp (CapGetOffset c__arg)" + by (unfold CapGetOffset_def, non_cap_expI) + +lemma non_cap_exp_CapGetLength[non_cap_expI]: + "non_cap_exp (CapGetLength c__arg)" + by (unfold CapGetLength_def, non_cap_expI) + +lemma non_cap_exp_CapIsInBounds[non_cap_expI]: + "non_cap_exp (CapIsInBounds c__arg)" + by (unfold CapIsInBounds_def, non_cap_expI) + +lemma non_cap_exp_CapSetOffset[non_cap_expI]: + "non_cap_exp (CapSetOffset c__arg offset)" + by (unfold CapSetOffset_def, non_cap_expI) + +lemma non_cap_exp_VAAdd[non_cap_expI]: + "non_cap_exp (VAAdd v offset)" + by (unfold VAAdd_def, non_cap_expI) + +lemma non_cap_exp_execute_aarch64_instrs_system_barriers_dmb[non_cap_expI]: + "non_cap_exp (execute_aarch64_instrs_system_barriers_dmb domain types)" + by (unfold execute_aarch64_instrs_system_barriers_dmb_def, non_cap_expI) + +lemma non_cap_exp_decode_dmb_aarch64_instrs_system_barriers_dmb[non_cap_expI]: + "non_cap_exp (decode_dmb_aarch64_instrs_system_barriers_dmb Rt opc CRm CRn op1 op0 L)" + by (unfold decode_dmb_aarch64_instrs_system_barriers_dmb_def, non_cap_expI) + +lemma non_cap_exp_execute_aarch64_instrs_system_barriers_dsb[non_cap_expI]: + "non_cap_exp (execute_aarch64_instrs_system_barriers_dsb domain types)" + by (unfold execute_aarch64_instrs_system_barriers_dsb_def, non_cap_expI) + +lemma non_cap_exp_decode_dsb_aarch64_instrs_system_barriers_dsb[non_cap_expI]: + "non_cap_exp (decode_dsb_aarch64_instrs_system_barriers_dsb Rt opc CRm CRn op1 op0 L)" + by (unfold decode_dsb_aarch64_instrs_system_barriers_dsb_def, non_cap_expI) + +lemma non_cap_exp_execute_aarch64_instrs_system_barriers_sb[non_cap_expI]: + "non_cap_exp (execute_aarch64_instrs_system_barriers_sb arg0)" + by (unfold execute_aarch64_instrs_system_barriers_sb_def, non_cap_expI) + +lemma non_cap_exp_decode_sb_aarch64_instrs_system_barriers_sb[non_cap_expI]: + "non_cap_exp (decode_sb_aarch64_instrs_system_barriers_sb Rt opc CRm CRn op1 op0 L)" + by (unfold decode_sb_aarch64_instrs_system_barriers_sb_def, non_cap_expI) + + +lemma read_cap_regs_derivable[derivable_capsE]: + "\t c s. Run (read_reg CDBGDTR_EL0_ref) t c \ {''CDBGDTR_EL0''} \ accessible_regs s \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg CDLR_EL0_ref) t c \ {''CDLR_EL0''} \ accessible_regs s \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg CID_EL0_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg DDC_EL0_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg DDC_EL1_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg DDC_EL2_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg DDC_EL3_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg ELR_EL1_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg ELR_EL2_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg ELR_EL3_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg PCC_ref) t c \ {''PCC''} \ accessible_regs s \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg RDDC_EL0_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg RSP_EL0_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg RTPIDR_EL0_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg SP_EL0_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg SP_EL1_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg SP_EL2_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg SP_EL3_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg TPIDRRO_EL0_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg TPIDR_EL0_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg TPIDR_EL1_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg TPIDR_EL2_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg TPIDR_EL3_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg VBAR_EL1_ref) t c \ {''VBAR_EL1''} \ accessible_regs s \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg VBAR_EL2_ref) t c \ {''VBAR_EL2''} \ accessible_regs s \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg VBAR_EL3_ref) t c \ {''VBAR_EL3''} \ accessible_regs s \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R00_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R01_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R02_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R03_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R04_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R05_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R06_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R07_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R08_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R09_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R10_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R11_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R12_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R13_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R14_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R15_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R16_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R17_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R18_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R19_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R20_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R21_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R22_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R23_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R24_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R25_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R26_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R27_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R28_ref) t c \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R29_ref) t c \ {''_R29''} \ accessible_regs s \ c \ derivable_caps (run s t)" + "\t c s. Run (read_reg R30_ref) t c \ c \ derivable_caps (run s t)" + by (derivable_capsI elim: read_reg_derivable simp: register_defs)+ + + +lemma R_read_derivable[derivable_capsE]: + "Run (R_read idx) t c \ {''_R29''} \ accessible_regs s \ c \ derivable_caps (run s t)" + by (unfold R_read_def, derivable_capsI) + +lemma CapSetValue_derivable[derivable_capsE]: + "Run (CapSetValue c__arg addr) t c \ c__arg \ derivable_caps s \ CapIsTagSet c__arg \ \CapIsSealed c__arg \ c \ derivable_caps s" + by (non_cap_exp_derivable_insert_run, unfold CapSetValue_def, derivable_capsI elim: update_subrange_addr_CapIsRepresentable_derivable_caps intro: update_subrange_if_derivable update_subrange_addr_CapWithTagClear_derivable) + +lemma BranchAddr_derivable[derivable_capsE]: + "Run (BranchAddr c__arg el) t c \ c__arg \ derivable_caps s \ c \ derivable_caps s" + by (non_cap_exp_derivable_insert_run, unfold BranchAddr_def, derivable_capsI) + +lemma CVBAR_read_derivable[derivable_capsE]: + "Run (CVBAR_read regime) t c \ {''VBAR_EL1'', ''VBAR_EL2'', ''VBAR_EL3''} \ accessible_regs s \ c \ derivable_caps (run s t)" + by (unfold CVBAR_read_def, derivable_capsI) + +lemma CVBAR_read__1_derivable[derivable_capsE]: + "Run (CVBAR_read__1 arg0) t c \ {''VBAR_EL1'', ''VBAR_EL2'', ''VBAR_EL3''} \ accessible_regs s \ c \ derivable_caps (run s t)" + by (unfold CVBAR_read__1_def, derivable_capsI) + +lemma PCC_read_derivable[derivable_capsE]: + "Run (PCC_read arg0) t c \ {''PCC''} \ accessible_regs s \ c \ derivable_caps (run s t)" + by (unfold PCC_read_def, derivable_capsI) + +lemma VAToCapability_derivable[derivable_capsE]: + "Run (VAToCapability va) t c \ VA_derivable va s \ c \ derivable_caps s" + by (auto simp: VA_derivable_def) + +lemma CapAdd_derivable[derivable_capsE]: + "Run (CapAdd c__arg arg1) t c \ c__arg \ derivable_caps s \ CapIsTagSet c__arg \ \CapIsSealed c__arg \ c \ derivable_caps s" + by (non_cap_exp_derivable_insert_run, unfold CapAdd_def, derivable_capsI elim: update_subrange_addr_CapIsRepresentableFast_derivable simp: word_bl.Abs_inject nth_ucast CapGetValue_def update_subrange_vec_dec_test_bit) + +lemma CapAdd__1_derivable[derivable_capsE]: + "Run (CapAdd__1 c__arg incr) t c \ c__arg \ derivable_caps s \ CapIsTagSet c__arg \ \CapIsSealed c__arg \ c \ derivable_caps s" + by (non_cap_exp_derivable_insert_run, unfold CapAdd__1_def, derivable_capsI) + +lemma C_read_derivable[derivable_capsE]: + "Run (C_read n) t c \ {''_R29''} \ accessible_regs s \ c \ derivable_caps (run s t)" + by (unfold C_read_def, derivable_capsI) + +lemma CELR_read_derivable[derivable_capsE]: + "Run (CELR_read el) t c \ c \ derivable_caps (run s t)" + by (unfold CELR_read_def, derivable_capsI) + +lemma CELR_read__1_derivable[derivable_capsE]: + "Run (CELR_read__1 arg0) t c \ c \ derivable_caps (run s t)" + by (unfold CELR_read__1_def, derivable_capsI) + +lemma CapabilityFromData_derivable[derivable_capsE]: + "Run (CapabilityFromData n tag data) t c \ n = 128 \ Capability_of_tag_word (tag !! 0) data \ derivable_caps s \ c \ derivable_caps s" + by (auto simp: CapabilityFromData_def) + +lemma CapSetBounds_derivable[derivable_capsE]: + "Run (CapSetBounds c__arg req_len exact) t c \ c__arg \ derivable_caps s \ CapIsTagSet c__arg \ \CapIsSealed c__arg \ req_len \ 2 ^ 64 \ inv_trace_assms s t \ c \ derivable_caps s" + by (auto dest!: CapSetBounds_derivable_proof inv_trace_assms_accessed_caps_invariant(1) elim!: derivable_cap_invariant simp: accessed_caps_invariant_def derivable_caps_def) + +lemma CapSetOffset_derivable[derivable_capsE]: + "Run (CapSetOffset c__arg incr) t c \ c__arg \ derivable_caps s \ CapIsTagSet c__arg \ \CapIsSealed c__arg \ c \ derivable_caps s" + by (non_cap_exp_derivable_insert_run, unfold CapSetOffset_def, derivable_capsI) + +end + +context Morello_Instr_Axiom_Automaton +begin + +lemma CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34_derivable[derivable_capsE]: + "Run (CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34_def, derivable_capsI) + +lemma CDLR_EL0_CapSysRegRead_619c852c71c0978d_derivable[derivable_capsE]: + "Run (CDLR_EL0_CapSysRegRead_619c852c71c0978d el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CDLR_EL0_CapSysRegRead_619c852c71c0978d_def, derivable_capsI) + +lemma CELR_EL12_CapSysRegRead_4bf271777fe55d1c_derivable[derivable_capsE]: + "Run (CELR_EL12_CapSysRegRead_4bf271777fe55d1c el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CELR_EL12_CapSysRegRead_4bf271777fe55d1c_def, derivable_capsI) + +lemma CELR_EL1_CapSysRegRead_da9869d2314a30d5_derivable[derivable_capsE]: + "Run (CELR_EL1_CapSysRegRead_da9869d2314a30d5 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CELR_EL1_CapSysRegRead_da9869d2314a30d5_def, derivable_capsI) + +lemma CELR_EL2_CapSysRegRead_a9e9661da428a6d4_derivable[derivable_capsE]: + "Run (CELR_EL2_CapSysRegRead_a9e9661da428a6d4 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CELR_EL2_CapSysRegRead_a9e9661da428a6d4_def, derivable_capsI) + +lemma CELR_EL3_CapSysRegRead_d0424a232c45967e_derivable[derivable_capsE]: + "Run (CELR_EL3_CapSysRegRead_d0424a232c45967e el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CELR_EL3_CapSysRegRead_d0424a232c45967e_def, derivable_capsI) + +lemma CID_EL0_CapSysRegRead_d560f6b1104266f1_derivable[derivable_capsE]: + "Run (CID_EL0_CapSysRegRead_d560f6b1104266f1 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CID_EL0_CapSysRegRead_d560f6b1104266f1_def, derivable_capsI) + +lemma CSP_EL0_CapSysRegRead_e5b1ba121f8be4da_derivable[derivable_capsE]: + "Run (CSP_EL0_CapSysRegRead_e5b1ba121f8be4da el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CSP_EL0_CapSysRegRead_e5b1ba121f8be4da_def, derivable_capsI) + +lemma CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb_derivable[derivable_capsE]: + "Run (CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb_def, derivable_capsI) + +lemma CSP_EL2_CapSysRegRead_9b50d2f92d5520da_derivable[derivable_capsE]: + "Run (CSP_EL2_CapSysRegRead_9b50d2f92d5520da el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CSP_EL2_CapSysRegRead_9b50d2f92d5520da_def, derivable_capsI) + +lemma CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc_derivable[derivable_capsE]: + "Run (CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc_def, derivable_capsI) + +lemma CTPIDR_EL0_CapSysRegRead_84b933ea55a77369_derivable[derivable_capsE]: + "Run (CTPIDR_EL0_CapSysRegRead_84b933ea55a77369 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CTPIDR_EL0_CapSysRegRead_84b933ea55a77369_def, derivable_capsI) + +lemma CTPIDR_EL1_CapSysRegRead_016308c12b886084_derivable[derivable_capsE]: + "Run (CTPIDR_EL1_CapSysRegRead_016308c12b886084 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CTPIDR_EL1_CapSysRegRead_016308c12b886084_def, derivable_capsI) + +lemma CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544_derivable[derivable_capsE]: + "Run (CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544_def, derivable_capsI) + +lemma CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449_derivable[derivable_capsE]: + "Run (CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449_def, derivable_capsI) + +lemma CVBAR_EL12_CapSysRegRead_845c94ac498ff593_derivable[derivable_capsE]: + "Run (CVBAR_EL12_CapSysRegRead_845c94ac498ff593 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CVBAR_EL12_CapSysRegRead_845c94ac498ff593_def, derivable_capsI) + +lemma CVBAR_EL1_CapSysRegRead_c42109445741a0d0_derivable[derivable_capsE]: + "Run (CVBAR_EL1_CapSysRegRead_c42109445741a0d0 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CVBAR_EL1_CapSysRegRead_c42109445741a0d0_def, derivable_capsI) + +lemma CVBAR_EL2_CapSysRegRead_537232bbd7d69e00_derivable[derivable_capsE]: + "Run (CVBAR_EL2_CapSysRegRead_537232bbd7d69e00 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CVBAR_EL2_CapSysRegRead_537232bbd7d69e00_def, derivable_capsI) + +lemma CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1_derivable[derivable_capsE]: + "Run (CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1_def, derivable_capsI) + +lemma DDC_CapSysRegRead_eabc4ea34a10a962_derivable[derivable_capsE]: + "Run (DDC_CapSysRegRead_eabc4ea34a10a962 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold DDC_CapSysRegRead_eabc4ea34a10a962_def, derivable_capsI) + +lemma DDC_EL0_CapSysRegRead_e02bc676dce7fb51_derivable[derivable_capsE]: + "Run (DDC_EL0_CapSysRegRead_e02bc676dce7fb51 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold DDC_EL0_CapSysRegRead_e02bc676dce7fb51_def, derivable_capsI) + +lemma DDC_EL1_CapSysRegRead_08f46354e9afc01e_derivable[derivable_capsE]: + "Run (DDC_EL1_CapSysRegRead_08f46354e9afc01e el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold DDC_EL1_CapSysRegRead_08f46354e9afc01e_def, derivable_capsI) + +lemma DDC_EL2_CapSysRegRead_6d2409222a719403_derivable[derivable_capsE]: + "Run (DDC_EL2_CapSysRegRead_6d2409222a719403 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold DDC_EL2_CapSysRegRead_6d2409222a719403_def, derivable_capsI) + +lemma RCSP_EL0_CapSysRegRead_6a9b29b9027548c3_derivable[derivable_capsE]: + "Run (RCSP_EL0_CapSysRegRead_6a9b29b9027548c3 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold RCSP_EL0_CapSysRegRead_6a9b29b9027548c3_def, derivable_capsI) + +lemma RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7_derivable[derivable_capsE]: + "Run (RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7 el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7_def, derivable_capsI) + +lemma RDDC_EL0_CapSysRegRead_c188e736aa7b9beb_derivable[derivable_capsE]: + "Run (RDDC_EL0_CapSysRegRead_c188e736aa7b9beb el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold RDDC_EL0_CapSysRegRead_c188e736aa7b9beb_def, derivable_capsI) + +lemma AArch64_AutoGen_CapSysRegRead_derivable[derivable_capsE]: + "Run (AArch64_AutoGen_CapSysRegRead el op0 op1 CRn op2 CRm) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold AArch64_AutoGen_CapSysRegRead_def, derivable_capsI) + +lemma AArch64_CapSysRegRead_derivable[derivable_capsE]: + "Run (AArch64_CapSysRegRead op0 op1 crn crm op2) t c \ {''PCC''} \ accessible_regs s \ sysreg_trace_assms s t \ c \ derivable_caps (run s t)" + by (unfold AArch64_CapSysRegRead_def, derivable_capsI) + +lemma MemAtomicC_derivable[derivable_capsE]: + assumes "Run (MemAtomicC address op value_name ldacctype stacctype) t c" and "invoked_indirect_caps = {}" and "load_caps_permitted" + shows "c \ derivable_caps (run s t)" + using assms(1) + unfolding MemAtomicC_def + by - (derivable_capsI intro: assms) + + +end + +context Morello_Fetch_Axiom_Automaton +begin + + +end + +end diff --git a/CHERI_Invariant.thy b/CHERI_Invariant.thy new file mode 100644 index 0000000..08bbce9 --- /dev/null +++ b/CHERI_Invariant.thy @@ -0,0 +1,2681 @@ +section \Invariant preservation\ + +theory CHERI_Invariant +imports CHERI_Lemmas +begin + +lemma non_inv_reg_writes_preserve_invariant: + "\v. runs_preserve_invariant (liftS (write_reg ThisInstrAbstract_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg EventRegister_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg saved_exception_level_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SP_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg V_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMSWINC_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg OSLAR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_SGI1R_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_SGI0R_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_EOIR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_EOIR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_EOIR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_EOIR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_DIR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_DIR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_ASGI1R_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DBGDTRTX_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg RDDC_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DDC_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DDC_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DDC_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DDC_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg VTTBR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg VTCR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg VSESR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg TTBR1_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg TTBR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg TTBR0_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg TTBR0_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg TTBR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg TPIDR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg TPIDR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg TPIDR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg TPIDR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg TPIDRRO_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SP_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SP_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SP_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SPSR_und_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SPSR_irq_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SPSR_fiq_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SPSR_abt_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SDER32_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SCXTNUM_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SCXTNUM_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SCXTNUM_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CID_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg S3_op1_Cn_Cm_op2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg RVBAR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg RVBAR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg RVBAR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg RTPIDR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg RSP_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg RMR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg RMR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg RMR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg REVIDR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMXEVTYPER_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMXEVCNTR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMSLATFR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMSIRR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMSIDR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMSICR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMSFCR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMSEVFR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMSELR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMSCR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMSCR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMOVSSET_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMOVSCLR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMINTENSET_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMINTENCLR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMEVTYPER_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMEVCNTR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMCR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMCNTENSET_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMCNTENCLR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMCEID1_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMCEID0_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMCCNTR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMUSERENR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMCCFILTR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMBSR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMBPTR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMBLIMITR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PMBIDR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PAR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg OSECCR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg OSDTRTX_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg OSDTRRX_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MVFR2_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MVFR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MVFR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg VMPIDR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPIDR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAMVPMV_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAMVPM7_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAMVPM6_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAMVPM5_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAMVPM4_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAMVPM3_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAMVPM2_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAMVPM1_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAMVPM0_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAMIDR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAMHCR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAM1_EL1_0_62_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAM2_EL2_0_62_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAM3_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MPAM0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg VPIDR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MIDR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MDRAR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MDCCSR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MDCCINT_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MAIR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MAIR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MAIR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg LORSA_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg LORN_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg LORID_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg LOREA_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg LORC_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ISR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg IFSR32_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_PFR2_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_PFR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_PFR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_MMFR5_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_MMFR4_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_MMFR3_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_MMFR2_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_MMFR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_MMFR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_ISAR6_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_ISAR5_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_ISAR4_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_ISAR3_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_ISAR2_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_ISAR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_ISAR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_DFR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_AFR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_AA64ZFR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_AA64PFR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_AA64PFR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_AA64MMFR2_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_AA64MMFR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_AA64MMFR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_AA64ISAR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_AA64ISAR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_AA64DFR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_AA64DFR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_AA64AFR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ID_AA64AFR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICH_VTR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICH_VMCR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICH_MISR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICH_LR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICH_ELRSR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICH_EISR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICH_AP1R_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICH_AP0R_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_RPR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_RPR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_PMR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_PMR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_IGRPEN1_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_IGRPEN1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_IGRPEN1_EL1_S_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_IGRPEN1_EL1_NS_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_IGRPEN0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_IGRPEN0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_IAR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_IAR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_IAR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_IAR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_HPPIR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_HPPIR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_HPPIR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_HPPIR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_CTLR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_CTLR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_CTLR_EL1_S_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_CTLR_EL1_NS_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_BPR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_BPR1_EL1_S_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_BPR1_EL1_NS_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_BPR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_BPR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_AP1R_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_AP1R_EL1_S_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_AP1R_EL1_NS_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_AP1R_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICV_AP0R_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICH_HCR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_SRE_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_SRE_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_SRE_EL1_S_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_SRE_EL1_NS_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ICC_AP0R_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg HSTR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg HACR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg FPSR_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg FPEXC32_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg FPCR_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ERXSTATUS_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ERXMISC1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ERXMISC0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ERXFR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ERXCTLR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ERXADDR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ERRSELR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ERRIDR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg VDISR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DISR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DBGWVR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DBGWCR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DBGVCR32_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CDBGDTR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MDSCR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DBGDTRRX_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DBGCLAIMSET_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DBGCLAIMCLR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DBGBVR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg OSLSR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg OSDLR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DBGPRCR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SPIDEN_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DSPSR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CDLR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DBGBCR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MDCR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg MDCR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DBGAUTHSTATUS_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg DACR32_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CTR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CSSELR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CSCR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CONTEXTIDR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CONTEXTIDR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTV_TVAL_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTV_CVAL_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTV_CTL_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTVOFF_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTVCT_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTP_TVAL_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTP_CVAL_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTP_CTL_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTPS_TVAL_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTPS_CVAL_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTPS_CTL_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTPCT_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTHV_TVAL_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTHV_CVAL_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTHV_CTL_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTHP_TVAL_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTHP_CVAL_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTHP_CTL_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTKCTL_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTHCTL_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTFRQ_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CLIDR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CHCR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CCSIDR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg AMAIR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg AMAIR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg AMAIR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg AIDR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg AFSR1_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg AFSR1_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg AFSR1_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg AFSR0_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg AFSR0_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg AFSR0_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ACTLR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ACTLR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ACTLR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SPSR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SPSR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SPSR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SCTLR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SCTLR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SCTLR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CPTR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CPTR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CPACR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg VBAR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg VBAR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg VBAR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ELR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ELR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ELR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CCTLR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CCTLR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CCTLR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CCTLR_EL0_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg BranchTaken_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PC_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg TCR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg TCR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg TCR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg HPFAR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg FAR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg FAR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg FAR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ESR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ESR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ESR_EL1_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R30_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R29_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R28_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R27_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R26_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R25_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R24_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R23_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R22_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R21_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R20_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R19_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R18_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R17_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R16_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R15_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R14_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R13_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R12_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R11_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R10_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R09_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R08_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R07_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R06_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R05_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R04_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R03_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R02_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R01_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg R00_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg ThisInstr_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg PSTATE_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg HCR_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg SCR_EL3_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTHVS_TVAL_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTHVS_CVAL_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTHVS_CTL_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTHPS_TVAL_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTHPS_CVAL_EL2_ref v)) cheri_invariant" + "\v. runs_preserve_invariant (liftS (write_reg CNTHPS_CTL_EL2_ref v)) cheri_invariant" + by (non_inv_reg_writes_preserve_cheri_invariant)+ + + +lemmas non_inv_reg_writesS_preserve_invariant[runs_preserve_invariantI] = + non_inv_reg_writes_preserve_invariant[unfolded liftState_simp] + +lemma BranchTo_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (BranchTo target branch_type)) cheri_invariant" + by (unfold BranchTo_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma BranchToCapability_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (BranchToCapability target branch_type)) cheri_invariant" + by (unfold BranchToCapability_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DBGBCR_EL1_SysRegRead_2d021994672d40d3_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DBGBCR_EL1_SysRegRead_2d021994672d40d3 el op0 op1 CRn op2 CRm)) cheri_invariant" + by (unfold DBGBCR_EL1_SysRegRead_2d021994672d40d3_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DBGBVR_EL1_SysRegRead_dc4a8f61b400622f_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DBGBVR_EL1_SysRegRead_dc4a8f61b400622f el op0 op1 CRn op2 CRm)) cheri_invariant" + by (unfold DBGBVR_EL1_SysRegRead_dc4a8f61b400622f_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DBGWCR_EL1_SysRegRead_03139d052b544b2f_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DBGWCR_EL1_SysRegRead_03139d052b544b2f el op0 op1 CRn op2 CRm)) cheri_invariant" + by (unfold DBGWCR_EL1_SysRegRead_03139d052b544b2f_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DBGWVR_EL1_SysRegRead_029de1005ef34888_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DBGWVR_EL1_SysRegRead_029de1005ef34888 el op0 op1 CRn op2 CRm)) cheri_invariant" + by (unfold DBGWVR_EL1_SysRegRead_029de1005ef34888_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_AutoGen_SysRegRead_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_AutoGen_SysRegRead el op0 op1 CRn op2 CRm)) cheri_invariant" + by (unfold AArch64_AutoGen_SysRegRead_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_SysRegRead_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_SysRegRead op0 op1 crn crm op2)) cheri_invariant" + by (unfold AArch64_SysRegRead_def catch_early_return_bind_liftR liftState_bind liftState_read_reg comp_def, preserves_invariantI) + +lemma DBGBCR_EL1_SysRegWrite_6730f3e3839510c5_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DBGBCR_EL1_SysRegWrite_6730f3e3839510c5 el op0 op1 CRn op2 CRm val_name)) cheri_invariant" + by (unfold DBGBCR_EL1_SysRegWrite_6730f3e3839510c5_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b el op0 op1 CRn op2 CRm val_name)) cheri_invariant" + by (unfold DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DBGWCR_EL1_SysRegWrite_6bda3acb5910d354_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DBGWCR_EL1_SysRegWrite_6bda3acb5910d354 el op0 op1 CRn op2 CRm val_name)) cheri_invariant" + by (unfold DBGWCR_EL1_SysRegWrite_6bda3acb5910d354_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DBGWVR_EL1_SysRegWrite_745b296ee53305ea_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DBGWVR_EL1_SysRegWrite_745b296ee53305ea el op0 op1 CRn op2 CRm val_name)) cheri_invariant" + by (unfold DBGWVR_EL1_SysRegWrite_745b296ee53305ea_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_AutoGen_SysRegWrite_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_AutoGen_SysRegWrite el op0 op1 CRn op2 CRm val_name)) cheri_invariant" + by (unfold AArch64_AutoGen_SysRegWrite_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_IMPDEFResets_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_IMPDEFResets arg0)) cheri_invariant" + by (unfold AArch64_IMPDEFResets_def bind_assoc liftState_simp comp_def, preserves_invariantI intro: modify_DCZID_preserves_invariant simp: set_slice_def ucast_update_subrange_vec_dec_simps) + +lemma AArch64_TakeReset_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_TakeReset cold_reset)) cheri_invariant" + by (unfold AArch64_TakeReset_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma TakeReset_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (TakeReset cold)) cheri_invariant" + by (unfold TakeReset_def bind_assoc liftState_simp comp_def, preserves_invariantI intro: modify_EDSCR_preserves_invariant simp: set_slice_def ucast_update_subrange_vec_dec_simps) + +lemma AArch64_SysRegWrite_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_SysRegWrite op0 op1 crn crm op2 val_name)) cheri_invariant" + by (unfold AArch64_SysRegWrite_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_CheckBreakpoint_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_CheckBreakpoint vaddress size__arg)) cheri_invariant" + by (unfold AArch64_CheckBreakpoint_def bind_assoc liftState_simp comp_def, preserves_invariantI elim: Value_and_boolS_elim HaltOnBreakpointOrWatchpoint_False) + +lemma AArch64_CheckWatchpoint_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_CheckWatchpoint vaddress acctype iswrite size__arg)) cheri_invariant" + by (unfold AArch64_CheckWatchpoint_def bind_assoc liftState_simp comp_def, preserves_invariantI elim: Value_and_boolS_elim HaltOnBreakpointOrWatchpoint_False) + +lemma AArch64_CheckDebug_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_CheckDebug vaddress acctype iswrite size__arg)) cheri_invariant" + by (unfold AArch64_CheckDebug_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_TranslateAddressWithTag_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_TranslateAddressWithTag vaddress acctype iswrite wasaligned size__arg iswritevalidcap)) cheri_invariant" + by (unfold AArch64_TranslateAddressWithTag_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_TranslateAddress_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_TranslateAddress vaddress acctype iswrite wasaligned size__arg)) cheri_invariant" + by (unfold AArch64_TranslateAddress_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DC_CIVAC_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DC_CIVAC val_name)) cheri_invariant" + by (unfold DC_CIVAC_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DC_CIVAC0_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DC_CIVAC0 val_name__arg)) cheri_invariant" + by (unfold DC_CIVAC0_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma CIVAC_SysOpsWrite_47ad60ecb930d217_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (CIVAC_SysOpsWrite_47ad60ecb930d217 el op0 op1 CRn op2 CRm val_name)) cheri_invariant" + by (unfold CIVAC_SysOpsWrite_47ad60ecb930d217_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DC_CVAC_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DC_CVAC val_name)) cheri_invariant" + by (unfold DC_CVAC_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DC_CVAC0_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DC_CVAC0 val_name__arg)) cheri_invariant" + by (unfold DC_CVAC0_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma CVAC_SysOpsWrite_c7d2e911c691cc6b_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (CVAC_SysOpsWrite_c7d2e911c691cc6b el op0 op1 CRn op2 CRm val_name)) cheri_invariant" + by (unfold CVAC_SysOpsWrite_c7d2e911c691cc6b_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DC_CVAP_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DC_CVAP val_name)) cheri_invariant" + by (unfold DC_CVAP_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DC_CVADP_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DC_CVADP val_name)) cheri_invariant" + by (unfold DC_CVADP_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma CVADP_SysOpsWrite_9953ef108c01d34a_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (CVADP_SysOpsWrite_9953ef108c01d34a el op0 op1 CRn op2 CRm val_name)) cheri_invariant" + by (unfold CVADP_SysOpsWrite_9953ef108c01d34a_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma CVAP_SysOpsWrite_a43f75867888e74a_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (CVAP_SysOpsWrite_a43f75867888e74a el op0 op1 CRn op2 CRm val_name)) cheri_invariant" + by (unfold CVAP_SysOpsWrite_a43f75867888e74a_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DC_CVAU_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DC_CVAU val_name)) cheri_invariant" + by (unfold DC_CVAU_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DC_CVAU0_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DC_CVAU0 val_name__arg)) cheri_invariant" + by (unfold DC_CVAU0_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma CVAU_SysOpsWrite_4a72bbc98a17973c_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (CVAU_SysOpsWrite_4a72bbc98a17973c el op0 op1 CRn op2 CRm val_name)) cheri_invariant" + by (unfold CVAU_SysOpsWrite_4a72bbc98a17973c_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DC_IVAC_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DC_IVAC val_name)) cheri_invariant" + by (unfold DC_IVAC_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DC_IVAC0_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DC_IVAC0 val_name__arg)) cheri_invariant" + by (unfold DC_IVAC0_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma IVAC_SysOpsWrite_41b93e0e56e4f107_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (IVAC_SysOpsWrite_41b93e0e56e4f107 el op0 op1 CRn op2 CRm val_name)) cheri_invariant" + by (unfold IVAC_SysOpsWrite_41b93e0e56e4f107_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma IC_IVAU_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (IC_IVAU val_name)) cheri_invariant" + by (unfold IC_IVAU_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma IVAU_SysOpsWrite_2dfe97b748dd324e_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (IVAU_SysOpsWrite_2dfe97b748dd324e el op0 op1 CRn op2 CRm val_name)) cheri_invariant" + by (unfold IVAU_SysOpsWrite_2dfe97b748dd324e_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_AutoGen_SysOpsWrite_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_AutoGen_SysOpsWrite el op0 op1 CRn op2 CRm val_name)) cheri_invariant" + by (unfold AArch64_AutoGen_SysOpsWrite_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_SysInstr_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_SysInstr op0 op1 crn crm op2 val_name)) cheri_invariant" + by (unfold AArch64_SysInstr_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma BranchXToCapability_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (BranchXToCapability target__arg branch_type)) cheri_invariant" + by (unfold BranchXToCapability_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma BranchToOffset_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (BranchToOffset offset branch_type)) cheri_invariant" + by (unfold BranchToOffset_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_MemSingle_read_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_MemSingle_read address size__arg acctype wasaligned)) cheri_invariant" + by (unfold AArch64_MemSingle_read_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_MemSingle_set_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_MemSingle_set address size__arg acctype wasaligned value_name)) cheri_invariant" + by (unfold AArch64_MemSingle_set_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_TaggedMemSingle_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_TaggedMemSingle address size__arg acctype wasaligned)) cheri_invariant" + by (unfold AArch64_TaggedMemSingle_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_TaggedMemSingle__1_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_TaggedMemSingle__1 address size__arg acctype wasaligned tags value_name)) cheri_invariant" + by (unfold AArch64_TaggedMemSingle__1_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_CapabilityTag_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_CapabilityTag address acctype)) cheri_invariant" + by (unfold AArch64_CapabilityTag_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_CapabilityTag_set_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_CapabilityTag_set address acctype tag)) cheri_invariant" + by (unfold AArch64_CapabilityTag_set_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma Mem_read0_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (Mem_read0 address size__arg acctype)) cheri_invariant" + by (unfold Mem_read0_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma Mem_set0_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (Mem_set0 address size__arg acctype value_name__arg)) cheri_invariant" + by (unfold Mem_set0_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma MemC_read_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (MemC_read address acctype)) cheri_invariant" + by (unfold MemC_read_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma MemC_set_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (MemC_set address acctype value_name)) cheri_invariant" + by (unfold MemC_set_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma MemCP__1_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (MemCP__1 address acctype value1_name value2_name)) cheri_invariant" + by (unfold MemCP__1_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_TranslateAddressForAtomicAccess_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_TranslateAddressForAtomicAccess address sizeinbits)) cheri_invariant" + by (unfold AArch64_TranslateAddressForAtomicAccess_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma MemAtomicCompareAndSwap_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (MemAtomicCompareAndSwap base expectedvalue newvalue__arg ldacctype stacctype)) cheri_invariant" + by (unfold MemAtomicCompareAndSwap_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma MemAtomic_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (MemAtomic base op value_name ldacctype stacctype)) cheri_invariant" + by (unfold MemAtomic_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma MemAtomicCompareAndSwapC_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (MemAtomicCompareAndSwapC vaddr address expectedcap newcap ldacctype stacctype)) cheri_invariant" + by (unfold MemAtomicCompareAndSwapC_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma MemAtomicC_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (MemAtomicC address op value_name ldacctype stacctype)) cheri_invariant" + by (unfold MemAtomicC_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_SetExclusiveMonitors_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_SetExclusiveMonitors address size__arg)) cheri_invariant" + by (unfold AArch64_SetExclusiveMonitors_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_ExclusiveMonitorsPass_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_ExclusiveMonitorsPass address size__arg)) cheri_invariant" + by (unfold AArch64_ExclusiveMonitorsPass_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_ExceptionReturnToCapability_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_ExceptionReturnToCapability new_pcc__arg spsr)) cheri_invariant" + by (unfold AArch64_ExceptionReturnToCapability_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma CAP_DC_CIVAC_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (CAP_DC_CIVAC cval)) cheri_invariant" + by (unfold CAP_DC_CIVAC_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma CAP_DC_CVAC_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (CAP_DC_CVAC cval)) cheri_invariant" + by (unfold CAP_DC_CVAC_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma CAP_DC_CVADP_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (CAP_DC_CVADP cval)) cheri_invariant" + by (unfold CAP_DC_CVADP_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma CAP_DC_CVAP_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (CAP_DC_CVAP cval)) cheri_invariant" + by (unfold CAP_DC_CVAP_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma CAP_DC_CVAU_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (CAP_DC_CVAU cval)) cheri_invariant" + by (unfold CAP_DC_CVAU_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma CAP_DC_IVAC_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (CAP_DC_IVAC cval)) cheri_invariant" + by (unfold CAP_DC_IVAC_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma CAP_IC_IVAU_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (CAP_IC_IVAU cval)) cheri_invariant" + by (unfold CAP_IC_IVAU_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma AArch64_SysInstrWithCapability_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (AArch64_SysInstrWithCapability op0 op1 crn crm op2 val_name)) cheri_invariant" + by (unfold AArch64_SysInstrWithCapability_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma FetchNextInstr_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (FetchNextInstr arg0)) cheri_invariant" + by (unfold FetchNextInstr_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma Step_PC_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (Step_PC arg0)) cheri_invariant" + by (unfold Step_PC_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDARB_R_R_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDARB_R_R_B acctype datasize n regsize t__arg)) cheri_invariant" + by (unfold execute_ALDARB_R_R_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDARB_R_R_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDARB_R_R_B L Rn Rt)) cheri_invariant" + by (unfold decode_ALDARB_R_R_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDAR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDAR_C_R_C acctype n t__arg)) cheri_invariant" + by (unfold execute_ALDAR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDAR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDAR_C_R_C L Rn Ct)) cheri_invariant" + by (unfold decode_ALDAR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDAR_R_R_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDAR_R_R_32 acctype datasize n regsize t__arg)) cheri_invariant" + by (unfold execute_ALDAR_R_R_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDAR_R_R_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDAR_R_R_32 L Rn Rt)) cheri_invariant" + by (unfold decode_ALDAR_R_R_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDRB_R_RRB_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDRB_R_RRB_B extend_type m n regsize l__550 shift t__arg)) cheri_invariant" + by (unfold execute_ALDRB_R_RRB_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDRB_R_RRB_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDRB_R_RRB_B L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ALDRB_R_RRB_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDRB_R_RUI_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDRB_R_RUI_B datasize n offset regsize t__arg)) cheri_invariant" + by (unfold execute_ALDRB_R_RUI_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDRB_R_RUI_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDRB_R_RUI_B L imm9 op Rn Rt)) cheri_invariant" + by (unfold decode_ALDRB_R_RUI_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDRH_R_RRB_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDRH_R_RRB_32 extend_type m n regsize l__549 shift t__arg)) cheri_invariant" + by (unfold execute_ALDRH_R_RRB_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDRH_R_RRB_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDRH_R_RRB_32 L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ALDRH_R_RRB_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDRSB_R_RRB_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDRSB_R_RRB_32 extend_type m n regsize l__545 shift t__arg)) cheri_invariant" + by (unfold execute_ALDRSB_R_RRB_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDRSB_R_RRB_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDRSB_R_RRB_32 L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ALDRSB_R_RRB_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDRSB_R_RRB_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDRSB_R_RRB_64 extend_type m n regsize l__546 shift t__arg)) cheri_invariant" + by (unfold execute_ALDRSB_R_RRB_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDRSB_R_RRB_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDRSB_R_RRB_64 L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ALDRSB_R_RRB_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDRSH_R_RRB_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDRSH_R_RRB_32 extend_type m n regsize l__543 shift t__arg)) cheri_invariant" + by (unfold execute_ALDRSH_R_RRB_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDRSH_R_RRB_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDRSH_R_RRB_32 L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ALDRSH_R_RRB_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDRSH_R_RRB_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDRSH_R_RRB_64 extend_type m n regsize l__544 shift t__arg)) cheri_invariant" + by (unfold execute_ALDRSH_R_RRB_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDRSH_R_RRB_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDRSH_R_RRB_64 L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ALDRSH_R_RRB_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDR_C_RRB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDR_C_RRB_C extend_type m n shift t__arg)) cheri_invariant" + by (unfold execute_ALDR_C_RRB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDR_C_RRB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDR_C_RRB_C Rm sign sz S L Rn Ct)) cheri_invariant" + by (unfold decode_ALDR_C_RRB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDR_C_RUI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDR_C_RUI_C n offset t__arg)) cheri_invariant" + by (unfold execute_ALDR_C_RUI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDR_C_RUI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDR_C_RUI_C L imm9 op Rn Ct)) cheri_invariant" + by (unfold decode_ALDR_C_RUI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDR_R_RRB_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDR_R_RRB_32 extend_type m n regsize l__548 shift t__arg)) cheri_invariant" + by (unfold execute_ALDR_R_RRB_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDR_R_RRB_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDR_R_RRB_32 L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ALDR_R_RRB_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDR_R_RRB_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDR_R_RRB_64 extend_type m n regsize l__547 shift t__arg)) cheri_invariant" + by (unfold execute_ALDR_R_RRB_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDR_R_RRB_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDR_R_RRB_64 L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ALDR_R_RRB_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDR_R_RUI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDR_R_RUI_32 datasize n offset regsize t__arg)) cheri_invariant" + by (unfold execute_ALDR_R_RUI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDR_R_RUI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDR_R_RUI_32 L imm9 op Rn Rt)) cheri_invariant" + by (unfold decode_ALDR_R_RUI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDR_R_RUI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDR_R_RUI_64 datasize n offset regsize t__arg)) cheri_invariant" + by (unfold execute_ALDR_R_RUI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDR_R_RUI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDR_R_RUI_64 L imm9 op Rn Rt)) cheri_invariant" + by (unfold decode_ALDR_R_RUI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDR_V_RRB_D_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDR_V_RRB_D extend_type m n l__542 shift t__arg)) cheri_invariant" + by (unfold execute_ALDR_V_RRB_D_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDR_V_RRB_D_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDR_V_RRB_D L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ALDR_V_RRB_D_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDR_V_RRB_S_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDR_V_RRB_S extend_type m n l__541 shift t__arg)) cheri_invariant" + by (unfold execute_ALDR_V_RRB_S_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDR_V_RRB_S_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDR_V_RRB_S L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ALDR_V_RRB_S_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDURB_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDURB_R_RI_32 datasize n offset regsize t__arg)) cheri_invariant" + by (unfold execute_ALDURB_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDURB_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDURB_R_RI_32 op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDURB_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDURH_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDURH_R_RI_32 datasize n offset regsize t__arg)) cheri_invariant" + by (unfold execute_ALDURH_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDURH_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDURH_R_RI_32 op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDURH_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDURSB_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDURSB_R_RI_32 datasize n offset regsize t__arg)) cheri_invariant" + by (unfold execute_ALDURSB_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDURSB_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDURSB_R_RI_32 op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDURSB_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDURSB_R_RI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDURSB_R_RI_64 datasize n offset regsize t__arg)) cheri_invariant" + by (unfold execute_ALDURSB_R_RI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDURSB_R_RI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDURSB_R_RI_64 op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDURSB_R_RI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDURSH_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDURSH_R_RI_32 datasize n offset regsize t__arg)) cheri_invariant" + by (unfold execute_ALDURSH_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDURSH_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDURSH_R_RI_32 op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDURSH_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDURSH_R_RI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDURSH_R_RI_64 datasize n offset regsize t__arg)) cheri_invariant" + by (unfold execute_ALDURSH_R_RI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDURSH_R_RI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDURSH_R_RI_64 op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDURSH_R_RI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDURSW_R_RI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDURSW_R_RI_64 datasize n offset regsize t__arg)) cheri_invariant" + by (unfold execute_ALDURSW_R_RI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDURSW_R_RI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDURSW_R_RI_64 op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDURSW_R_RI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDUR_C_RI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDUR_C_RI_C n offset t__arg)) cheri_invariant" + by (unfold execute_ALDUR_C_RI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDUR_C_RI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDUR_C_RI_C op1 V imm9 op2 Rn Ct)) cheri_invariant" + by (unfold decode_ALDUR_C_RI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDUR_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDUR_R_RI_32 datasize n offset regsize t__arg)) cheri_invariant" + by (unfold execute_ALDUR_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDUR_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDUR_R_RI_32 op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDUR_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDUR_R_RI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDUR_R_RI_64 datasize n offset regsize t__arg)) cheri_invariant" + by (unfold execute_ALDUR_R_RI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDUR_R_RI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDUR_R_RI_64 op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDUR_R_RI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDUR_V_RI_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDUR_V_RI_B datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ALDUR_V_RI_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDUR_V_RI_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDUR_V_RI_B op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDUR_V_RI_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDUR_V_RI_D_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDUR_V_RI_D datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ALDUR_V_RI_D_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDUR_V_RI_D_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDUR_V_RI_D op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDUR_V_RI_D_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDUR_V_RI_H_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDUR_V_RI_H datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ALDUR_V_RI_H_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDUR_V_RI_H_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDUR_V_RI_H op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDUR_V_RI_H_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDUR_V_RI_Q_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDUR_V_RI_Q datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ALDUR_V_RI_Q_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDUR_V_RI_Q_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDUR_V_RI_Q op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDUR_V_RI_Q_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ALDUR_V_RI_S_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ALDUR_V_RI_S datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ALDUR_V_RI_S_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ALDUR_V_RI_S_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ALDUR_V_RI_S op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ALDUR_V_RI_S_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTLRB_R_R_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTLRB_R_R_B acctype datasize n t__arg)) cheri_invariant" + by (unfold execute_ASTLRB_R_R_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTLRB_R_R_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTLRB_R_R_B L Rn Rt)) cheri_invariant" + by (unfold decode_ASTLRB_R_R_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTLR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTLR_C_R_C acctype n t__arg)) cheri_invariant" + by (unfold execute_ASTLR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTLR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTLR_C_R_C L Rn Ct)) cheri_invariant" + by (unfold decode_ASTLR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTLR_R_R_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTLR_R_R_32 acctype datasize n t__arg)) cheri_invariant" + by (unfold execute_ASTLR_R_R_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTLR_R_R_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTLR_R_R_32 L Rn Rt)) cheri_invariant" + by (unfold decode_ASTLR_R_R_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTRB_R_RRB_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTRB_R_RRB_B extend_type m n l__556 shift t__arg)) cheri_invariant" + by (unfold execute_ASTRB_R_RRB_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTRB_R_RRB_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTRB_R_RRB_B L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ASTRB_R_RRB_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTRB_R_RUI_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTRB_R_RUI_B datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ASTRB_R_RUI_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTRB_R_RUI_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTRB_R_RUI_B L imm9 op Rn Rt)) cheri_invariant" + by (unfold decode_ASTRB_R_RUI_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTRH_R_RRB_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTRH_R_RRB_32 extend_type m n l__555 shift t__arg)) cheri_invariant" + by (unfold execute_ASTRH_R_RRB_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTRH_R_RRB_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTRH_R_RRB_32 L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ASTRH_R_RRB_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTR_C_RRB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTR_C_RRB_C extend_type m n shift t__arg)) cheri_invariant" + by (unfold execute_ASTR_C_RRB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTR_C_RRB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTR_C_RRB_C Rm sign sz S L Rn Ct)) cheri_invariant" + by (unfold decode_ASTR_C_RRB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTR_C_RUI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTR_C_RUI_C n offset t__arg)) cheri_invariant" + by (unfold execute_ASTR_C_RUI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTR_C_RUI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTR_C_RUI_C L imm9 op Rn Ct)) cheri_invariant" + by (unfold decode_ASTR_C_RUI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTR_R_RRB_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTR_R_RRB_32 extend_type m n l__554 shift t__arg)) cheri_invariant" + by (unfold execute_ASTR_R_RRB_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTR_R_RRB_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTR_R_RRB_32 L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ASTR_R_RRB_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTR_R_RRB_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTR_R_RRB_64 extend_type m n l__553 shift t__arg)) cheri_invariant" + by (unfold execute_ASTR_R_RRB_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTR_R_RRB_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTR_R_RRB_64 L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ASTR_R_RRB_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTR_R_RUI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTR_R_RUI_32 datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ASTR_R_RUI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTR_R_RUI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTR_R_RUI_32 L imm9 op Rn Rt)) cheri_invariant" + by (unfold decode_ASTR_R_RUI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTR_R_RUI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTR_R_RUI_64 datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ASTR_R_RUI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTR_R_RUI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTR_R_RUI_64 L imm9 op Rn Rt)) cheri_invariant" + by (unfold decode_ASTR_R_RUI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTR_V_RRB_D_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTR_V_RRB_D extend_type m n l__552 shift t__arg)) cheri_invariant" + by (unfold execute_ASTR_V_RRB_D_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTR_V_RRB_D_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTR_V_RRB_D L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ASTR_V_RRB_D_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTR_V_RRB_S_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTR_V_RRB_S extend_type m n l__551 shift t__arg)) cheri_invariant" + by (unfold execute_ASTR_V_RRB_S_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTR_V_RRB_S_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTR_V_RRB_S L Rm sign sz S opc Rn Rt)) cheri_invariant" + by (unfold decode_ASTR_V_RRB_S_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTURB_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTURB_R_RI_32 datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ASTURB_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTURB_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTURB_R_RI_32 op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ASTURB_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTURH_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTURH_R_RI_32 datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ASTURH_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTURH_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTURH_R_RI_32 op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ASTURH_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTUR_C_RI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTUR_C_RI_C n offset t__arg)) cheri_invariant" + by (unfold execute_ASTUR_C_RI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTUR_C_RI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTUR_C_RI_C op1 V imm9 op2 Rn Ct)) cheri_invariant" + by (unfold decode_ASTUR_C_RI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTUR_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTUR_R_RI_32 datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ASTUR_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTUR_R_RI_32_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTUR_R_RI_32 op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ASTUR_R_RI_32_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTUR_R_RI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTUR_R_RI_64 datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ASTUR_R_RI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTUR_R_RI_64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTUR_R_RI_64 op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ASTUR_R_RI_64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTUR_V_RI_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTUR_V_RI_B datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ASTUR_V_RI_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTUR_V_RI_B_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTUR_V_RI_B op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ASTUR_V_RI_B_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTUR_V_RI_D_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTUR_V_RI_D datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ASTUR_V_RI_D_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTUR_V_RI_D_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTUR_V_RI_D op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ASTUR_V_RI_D_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTUR_V_RI_H_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTUR_V_RI_H datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ASTUR_V_RI_H_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTUR_V_RI_H_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTUR_V_RI_H op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ASTUR_V_RI_H_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTUR_V_RI_Q_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTUR_V_RI_Q datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ASTUR_V_RI_Q_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTUR_V_RI_Q_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTUR_V_RI_Q op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ASTUR_V_RI_Q_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_ASTUR_V_RI_S_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_ASTUR_V_RI_S datasize n offset t__arg)) cheri_invariant" + by (unfold execute_ASTUR_V_RI_S_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ASTUR_V_RI_S_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ASTUR_V_RI_S op1 V imm9 op2 Rn Rt)) cheri_invariant" + by (unfold decode_ASTUR_V_RI_S_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_BLRR_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_BLRR_C_C branch_type n)) cheri_invariant" + by (unfold execute_BLRR_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_BLRR_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_BLRR_C_C opc Cn)) cheri_invariant" + by (unfold decode_BLRR_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_BLRS_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_BLRS_C_C branch_type n)) cheri_invariant" + by (unfold execute_BLRS_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_BLRS_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_BLRS_C_C opc Cn)) cheri_invariant" + by (unfold decode_BLRS_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_BLRS_C_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_BLRS_C_C_C branch_type m n)) cheri_invariant" + by (unfold execute_BLRS_C_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_BLRS_C_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_BLRS_C_C_C Cm opc Cn)) cheri_invariant" + by (unfold decode_BLRS_C_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_BLR_CI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_BLR_CI_C branch_type n offset)) cheri_invariant" + by (unfold execute_BLR_CI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_BLR_CI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_BLR_CI_C imm7 Cn)) cheri_invariant" + by (unfold decode_BLR_CI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_BLR_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_BLR_C_C branch_type n)) cheri_invariant" + by (unfold execute_BLR_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_BLR_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_BLR_C_C opc Cn)) cheri_invariant" + by (unfold decode_BLR_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_BRR_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_BRR_C_C branch_type n)) cheri_invariant" + by (unfold execute_BRR_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_BRR_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_BRR_C_C opc Cn)) cheri_invariant" + by (unfold decode_BRR_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_BRS_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_BRS_C_C branch_type n)) cheri_invariant" + by (unfold execute_BRS_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_BRS_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_BRS_C_C opc Cn)) cheri_invariant" + by (unfold decode_BRS_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_BRS_C_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_BRS_C_C_C branch_type m n)) cheri_invariant" + by (unfold execute_BRS_C_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_BRS_C_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_BRS_C_C_C Cm opc Cn)) cheri_invariant" + by (unfold decode_BRS_C_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_BR_CI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_BR_CI_C branch_type n offset)) cheri_invariant" + by (unfold execute_BR_CI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_BR_CI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_BR_CI_C imm7 Cn)) cheri_invariant" + by (unfold decode_BR_CI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_BR_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_BR_C_C branch_type n)) cheri_invariant" + by (unfold execute_BR_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_BR_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_BR_C_C opc Cn)) cheri_invariant" + by (unfold decode_BR_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_BX___C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_BX___C branch_type)) cheri_invariant" + by (unfold execute_BX___C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_BX___C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_BX___C opc)) cheri_invariant" + by (unfold decode_BX___C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_CASAL_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_CASAL_C_R_C ldacctype n s__arg stacctype t__arg)) cheri_invariant" + by (unfold execute_CASAL_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_CASAL_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_CASAL_C_R_C L Cs R Rn Ct)) cheri_invariant" + by (unfold decode_CASAL_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_CASA_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_CASA_C_R_C ldacctype n s__arg stacctype t__arg)) cheri_invariant" + by (unfold execute_CASA_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_CASA_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_CASA_C_R_C L Cs R Rn Ct)) cheri_invariant" + by (unfold decode_CASA_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_CASL_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_CASL_C_R_C ldacctype n s__arg stacctype t__arg)) cheri_invariant" + by (unfold execute_CASL_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_CASL_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_CASL_C_R_C L Cs R Rn Ct)) cheri_invariant" + by (unfold decode_CASL_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_CAS_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_CAS_C_R_C ldacctype n s__arg stacctype t__arg)) cheri_invariant" + by (unfold execute_CAS_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_CAS_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_CAS_C_R_C L Cs R Rn Ct)) cheri_invariant" + by (unfold decode_CAS_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDAPR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDAPR_C_R_C acctype n t__arg)) cheri_invariant" + by (unfold execute_LDAPR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDAPR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDAPR_C_R_C Rn Ct)) cheri_invariant" + by (unfold decode_LDAPR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDAR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDAR_C_R_C acctype n t__arg)) cheri_invariant" + by (unfold execute_LDAR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDAR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDAR_C_R_C L Rn Ct)) cheri_invariant" + by (unfold decode_LDAR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDAXP_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDAXP_C_R_C acctype n t__arg t2)) cheri_invariant" + by (unfold execute_LDAXP_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDAXP_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDAXP_C_R_C L Ct2 Rn Ct)) cheri_invariant" + by (unfold decode_LDAXP_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDAXR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDAXR_C_R_C acctype n t__arg)) cheri_invariant" + by (unfold execute_LDAXR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDAXR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDAXR_C_R_C L Rn Ct)) cheri_invariant" + by (unfold decode_LDAXR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDCT_R_R_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDCT_R_R n t__arg)) cheri_invariant" + by (unfold execute_LDCT_R_R_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDCT_R_R_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDCT_R_R opc Rn Rt)) cheri_invariant" + by (unfold decode_LDCT_R_R_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDNP_C_RIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDNP_C_RIB_C acctype n offset t__arg t2)) cheri_invariant" + by (unfold execute_LDNP_C_RIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDNP_C_RIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDNP_C_RIB_C L imm7 Ct2 Rn Ct)) cheri_invariant" + by (unfold decode_LDNP_C_RIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDPBLR_C_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDPBLR_C_C_C branch_type n t__arg)) cheri_invariant" + by (unfold execute_LDPBLR_C_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDPBLR_C_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDPBLR_C_C_C opc Cn Ct)) cheri_invariant" + by (unfold decode_LDPBLR_C_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDPBR_C_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDPBR_C_C_C branch_type n t__arg)) cheri_invariant" + by (unfold execute_LDPBR_C_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDPBR_C_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDPBR_C_C_C opc Cn Ct)) cheri_invariant" + by (unfold decode_LDPBR_C_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDP_CC_RIAW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDP_CC_RIAW_C acctype n offset t__arg t2)) cheri_invariant" + by (unfold execute_LDP_CC_RIAW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDP_CC_RIAW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDP_CC_RIAW_C L imm7 Ct2 Rn Ct)) cheri_invariant" + by (unfold decode_LDP_CC_RIAW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDP_C_RIBW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDP_C_RIBW_C acctype n offset t__arg t2)) cheri_invariant" + by (unfold execute_LDP_C_RIBW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDP_C_RIBW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDP_C_RIBW_C L imm7 Ct2 Rn Ct)) cheri_invariant" + by (unfold decode_LDP_C_RIBW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDP_C_RIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDP_C_RIB_C acctype n offset t__arg t2)) cheri_invariant" + by (unfold execute_LDP_C_RIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDP_C_RIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDP_C_RIB_C L imm7 Ct2 Rn Ct)) cheri_invariant" + by (unfold decode_LDP_C_RIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDR_C_I_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDR_C_I_C offset t__arg)) cheri_invariant" + by (unfold execute_LDR_C_I_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDR_C_I_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDR_C_I_C imm17 Ct)) cheri_invariant" + by (unfold decode_LDR_C_I_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDR_C_RIAW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDR_C_RIAW_C n offset t__arg)) cheri_invariant" + by (unfold execute_LDR_C_RIAW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDR_C_RIAW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDR_C_RIAW_C opc imm9 Rn Ct)) cheri_invariant" + by (unfold decode_LDR_C_RIAW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDR_C_RIBW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDR_C_RIBW_C n offset t__arg)) cheri_invariant" + by (unfold execute_LDR_C_RIBW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDR_C_RIBW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDR_C_RIBW_C opc imm9 Rn Ct)) cheri_invariant" + by (unfold decode_LDR_C_RIBW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDR_C_RRB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDR_C_RRB_C extend_type m n shift t__arg)) cheri_invariant" + by (unfold execute_LDR_C_RRB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDR_C_RRB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDR_C_RRB_C opc Rm sign sz S Rn Ct)) cheri_invariant" + by (unfold decode_LDR_C_RRB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDR_C_RUIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDR_C_RUIB_C n offset t__arg)) cheri_invariant" + by (unfold execute_LDR_C_RUIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDR_C_RUIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDR_C_RUIB_C L imm12 Rn Ct)) cheri_invariant" + by (unfold decode_LDR_C_RUIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDTR_C_RIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDTR_C_RIB_C n offset t__arg)) cheri_invariant" + by (unfold execute_LDTR_C_RIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDTR_C_RIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDTR_C_RIB_C opc imm9 Rn Ct)) cheri_invariant" + by (unfold decode_LDTR_C_RIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDUR_C_RI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDUR_C_RI_C n offset t__arg)) cheri_invariant" + by (unfold execute_LDUR_C_RI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDUR_C_RI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDUR_C_RI_C opc imm9 Rn Ct)) cheri_invariant" + by (unfold decode_LDUR_C_RI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDXP_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDXP_C_R_C acctype n t__arg t2)) cheri_invariant" + by (unfold execute_LDXP_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDXP_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDXP_C_R_C L Ct2 Rn Ct)) cheri_invariant" + by (unfold decode_LDXP_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_LDXR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_LDXR_C_R_C acctype n t__arg)) cheri_invariant" + by (unfold execute_LDXR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_LDXR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_LDXR_C_R_C L Rn Ct)) cheri_invariant" + by (unfold decode_LDXR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_RETR_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_RETR_C_C branch_type n)) cheri_invariant" + by (unfold execute_RETR_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_RETR_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_RETR_C_C opc Cn)) cheri_invariant" + by (unfold decode_RETR_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_RETS_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_RETS_C_C branch_type n)) cheri_invariant" + by (unfold execute_RETS_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_RETS_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_RETS_C_C opc Cn)) cheri_invariant" + by (unfold decode_RETS_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_RETS_C_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_RETS_C_C_C branch_type m n)) cheri_invariant" + by (unfold execute_RETS_C_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_RETS_C_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_RETS_C_C_C Cm opc Cn)) cheri_invariant" + by (unfold decode_RETS_C_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_RET_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_RET_C_C branch_type n)) cheri_invariant" + by (unfold execute_RET_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_RET_C_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_RET_C_C opc Cn)) cheri_invariant" + by (unfold decode_RET_C_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STCT_R_R_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STCT_R_R n t__arg)) cheri_invariant" + by (unfold execute_STCT_R_R_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STCT_R_R_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STCT_R_R opc Rn Rt)) cheri_invariant" + by (unfold decode_STCT_R_R_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STLR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STLR_C_R_C acctype n t__arg)) cheri_invariant" + by (unfold execute_STLR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STLR_C_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STLR_C_R_C L Rn Ct)) cheri_invariant" + by (unfold decode_STLR_C_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STLXP_R_CR_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STLXP_R_CR_C acctype n s__arg t__arg t2)) cheri_invariant" + by (unfold execute_STLXP_R_CR_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STLXP_R_CR_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STLXP_R_CR_C L Rs Ct2 Rn Ct)) cheri_invariant" + by (unfold decode_STLXP_R_CR_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STLXR_R_CR_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STLXR_R_CR_C acctype n s__arg t__arg)) cheri_invariant" + by (unfold execute_STLXR_R_CR_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STLXR_R_CR_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STLXR_R_CR_C L Rs Rn Ct)) cheri_invariant" + by (unfold decode_STLXR_R_CR_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STNP_C_RIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STNP_C_RIB_C acctype n offset t__arg t2)) cheri_invariant" + by (unfold execute_STNP_C_RIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STNP_C_RIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STNP_C_RIB_C L imm7 Ct2 Rn Ct)) cheri_invariant" + by (unfold decode_STNP_C_RIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STP_CC_RIAW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STP_CC_RIAW_C acctype n offset t__arg t2)) cheri_invariant" + by (unfold execute_STP_CC_RIAW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STP_CC_RIAW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STP_CC_RIAW_C L imm7 Ct2 Rn Ct)) cheri_invariant" + by (unfold decode_STP_CC_RIAW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STP_C_RIBW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STP_C_RIBW_C acctype n offset t__arg t2)) cheri_invariant" + by (unfold execute_STP_C_RIBW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STP_C_RIBW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STP_C_RIBW_C L imm7 Ct2 Rn Ct)) cheri_invariant" + by (unfold decode_STP_C_RIBW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STP_C_RIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STP_C_RIB_C acctype n offset t__arg t2)) cheri_invariant" + by (unfold execute_STP_C_RIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STP_C_RIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STP_C_RIB_C L imm7 Ct2 Rn Ct)) cheri_invariant" + by (unfold decode_STP_C_RIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STR_C_RIAW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STR_C_RIAW_C n offset t__arg)) cheri_invariant" + by (unfold execute_STR_C_RIAW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STR_C_RIAW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STR_C_RIAW_C opc imm9 Rn Ct)) cheri_invariant" + by (unfold decode_STR_C_RIAW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STR_C_RIBW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STR_C_RIBW_C n offset t__arg)) cheri_invariant" + by (unfold execute_STR_C_RIBW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STR_C_RIBW_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STR_C_RIBW_C opc imm9 Rn Ct)) cheri_invariant" + by (unfold decode_STR_C_RIBW_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STR_C_RRB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STR_C_RRB_C extend_type m n shift t__arg)) cheri_invariant" + by (unfold execute_STR_C_RRB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STR_C_RRB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STR_C_RRB_C opc Rm sign sz S Rn Ct)) cheri_invariant" + by (unfold decode_STR_C_RRB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STR_C_RUIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STR_C_RUIB_C n offset t__arg)) cheri_invariant" + by (unfold execute_STR_C_RUIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STR_C_RUIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STR_C_RUIB_C L imm12 Rn Ct)) cheri_invariant" + by (unfold decode_STR_C_RUIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STTR_C_RIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STTR_C_RIB_C n offset t__arg)) cheri_invariant" + by (unfold execute_STTR_C_RIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STTR_C_RIB_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STTR_C_RIB_C opc imm9 Rn Ct)) cheri_invariant" + by (unfold decode_STTR_C_RIB_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STUR_C_RI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STUR_C_RI_C n offset t__arg)) cheri_invariant" + by (unfold execute_STUR_C_RI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STUR_C_RI_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STUR_C_RI_C opc imm9 Rn Ct)) cheri_invariant" + by (unfold decode_STUR_C_RI_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STXP_R_CR_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STXP_R_CR_C acctype n s__arg t__arg t2)) cheri_invariant" + by (unfold execute_STXP_R_CR_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STXP_R_CR_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STXP_R_CR_C L Rs Ct2 Rn Ct)) cheri_invariant" + by (unfold decode_STXP_R_CR_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_STXR_R_CR_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_STXR_R_CR_C acctype n s__arg t__arg)) cheri_invariant" + by (unfold execute_STXR_R_CR_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_STXR_R_CR_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_STXR_R_CR_C L Rs Rn Ct)) cheri_invariant" + by (unfold decode_STXR_R_CR_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_SWPAL_CC_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_SWPAL_CC_R_C ldacctype n s__arg stacctype t__arg)) cheri_invariant" + by (unfold execute_SWPAL_CC_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_SWPAL_CC_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_SWPAL_CC_R_C A R Cs Rn Ct)) cheri_invariant" + by (unfold decode_SWPAL_CC_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_SWPA_CC_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_SWPA_CC_R_C ldacctype n s__arg stacctype t__arg)) cheri_invariant" + by (unfold execute_SWPA_CC_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_SWPA_CC_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_SWPA_CC_R_C A R Cs Rn Ct)) cheri_invariant" + by (unfold decode_SWPA_CC_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_SWPL_CC_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_SWPL_CC_R_C ldacctype n s__arg stacctype t__arg)) cheri_invariant" + by (unfold execute_SWPL_CC_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_SWPL_CC_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_SWPL_CC_R_C A R Cs Rn Ct)) cheri_invariant" + by (unfold decode_SWPL_CC_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_SWP_CC_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_SWP_CC_R_C ldacctype n s__arg stacctype t__arg)) cheri_invariant" + by (unfold execute_SWP_CC_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_SWP_CC_R_C_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_SWP_CC_R_C A R Cs Rn Ct)) cheri_invariant" + by (unfold decode_SWP_CC_R_C_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_branch_conditional_cond_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_branch_conditional_cond condition offset)) cheri_invariant" + by (unfold execute_aarch64_instrs_branch_conditional_cond_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_b_cond_aarch64_instrs_branch_conditional_cond_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_b_cond_aarch64_instrs_branch_conditional_cond cond imm19)) cheri_invariant" + by (unfold decode_b_cond_aarch64_instrs_branch_conditional_cond_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_branch_unconditional_immediate_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_branch_unconditional_immediate branch_type offset)) cheri_invariant" + by (unfold execute_aarch64_instrs_branch_unconditional_immediate_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_b_uncond_aarch64_instrs_branch_unconditional_immediate_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_b_uncond_aarch64_instrs_branch_unconditional_immediate imm26 op)) cheri_invariant" + by (unfold decode_b_uncond_aarch64_instrs_branch_unconditional_immediate_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_bl_aarch64_instrs_branch_unconditional_immediate_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_bl_aarch64_instrs_branch_unconditional_immediate imm26 op)) cheri_invariant" + by (unfold decode_bl_aarch64_instrs_branch_unconditional_immediate_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_branch_unconditional_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_branch_unconditional_register branch_type n)) cheri_invariant" + by (unfold execute_aarch64_instrs_branch_unconditional_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_blr_aarch64_instrs_branch_unconditional_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_blr_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)) cheri_invariant" + by (unfold decode_blr_aarch64_instrs_branch_unconditional_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_blra_aarch64_instrs_branch_unconditional_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_blra_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)) cheri_invariant" + by (unfold decode_blra_aarch64_instrs_branch_unconditional_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_br_aarch64_instrs_branch_unconditional_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_br_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)) cheri_invariant" + by (unfold decode_br_aarch64_instrs_branch_unconditional_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_bra_aarch64_instrs_branch_unconditional_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_bra_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)) cheri_invariant" + by (unfold decode_bra_aarch64_instrs_branch_unconditional_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_atomicops_cas_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_atomicops_cas_single (datasize :: 'datasize::len itself) ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_cas_aarch64_instrs_memory_atomicops_cas_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_cas_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs L b__0)) cheri_invariant" + by (unfold decode_cas_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_casb_aarch64_instrs_memory_atomicops_cas_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_casb_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs L b__0)) cheri_invariant" + by (unfold decode_casb_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_cash_aarch64_instrs_memory_atomicops_cas_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_cash_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs L b__0)) cheri_invariant" + by (unfold decode_cash_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_atomicops_cas_pair_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_atomicops_cas_pair l__38 ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_atomicops_cas_pair_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_casp_aarch64_instrs_memory_atomicops_cas_pair_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_casp_aarch64_instrs_memory_atomicops_cas_pair Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_casp_aarch64_instrs_memory_atomicops_cas_pair_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_branch_conditional_compare_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_branch_conditional_compare (datasize :: 'datasize::len itself) iszero__arg offset t__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_branch_conditional_compare_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_cbnz_aarch64_instrs_branch_conditional_compare_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_cbnz_aarch64_instrs_branch_conditional_compare Rt imm19 op b__0)) cheri_invariant" + by (unfold decode_cbnz_aarch64_instrs_branch_conditional_compare_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_cbz_aarch64_instrs_branch_conditional_compare_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_cbz_aarch64_instrs_branch_conditional_compare Rt imm19 op b__0)) cheri_invariant" + by (unfold decode_cbz_aarch64_instrs_branch_conditional_compare_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_dcps1_aarch64_instrs_system_exceptions_debug_exception_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_dcps1_aarch64_instrs_system_exceptions_debug_exception LL imm16)) cheri_invariant" + by (unfold decode_dcps1_aarch64_instrs_system_exceptions_debug_exception_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_dcps2_aarch64_instrs_system_exceptions_debug_exception_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_dcps2_aarch64_instrs_system_exceptions_debug_exception LL imm16)) cheri_invariant" + by (unfold decode_dcps2_aarch64_instrs_system_exceptions_debug_exception_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_dcps3_aarch64_instrs_system_exceptions_debug_exception_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_dcps3_aarch64_instrs_system_exceptions_debug_exception LL imm16)) cheri_invariant" + by (unfold decode_dcps3_aarch64_instrs_system_exceptions_debug_exception_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_drps_aarch64_instrs_branch_unconditional_dret_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_drps_aarch64_instrs_branch_unconditional_dret arg0)) cheri_invariant" + by (unfold decode_drps_aarch64_instrs_branch_unconditional_dret_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_branch_unconditional_eret_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_branch_unconditional_eret arg0)) cheri_invariant" + by (unfold execute_aarch64_instrs_branch_unconditional_eret_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_eret_aarch64_instrs_branch_unconditional_eret_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_eret_aarch64_instrs_branch_unconditional_eret op4 Rn M A)) cheri_invariant" + by (unfold decode_eret_aarch64_instrs_branch_unconditional_eret_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ereta_aarch64_instrs_branch_unconditional_eret_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ereta_aarch64_instrs_branch_unconditional_eret op4 Rn M A)) cheri_invariant" + by (unfold decode_ereta_aarch64_instrs_branch_unconditional_eret_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_hlt_aarch64_instrs_system_exceptions_debug_halt_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_hlt_aarch64_instrs_system_exceptions_debug_halt imm16)) cheri_invariant" + by (unfold decode_hlt_aarch64_instrs_system_exceptions_debug_halt_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_vector_multiple_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_vector_multiple_no_wb (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m memop n rpt selem t__arg wback)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)) cheri_invariant" + by (unfold decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)) cheri_invariant" + by (unfold decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_vector_single_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_vector_single_no_wb (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) index__arg m memop n replicate__arg selem t__arg wback)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)) cheri_invariant" + by (unfold decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)) cheri_invariant" + by (unfold decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)) cheri_invariant" + by (unfold decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)) cheri_invariant" + by (unfold decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)) cheri_invariant" + by (unfold decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)) cheri_invariant" + by (unfold decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)) cheri_invariant" + by (unfold decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)) cheri_invariant" + by (unfold decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)) cheri_invariant" + by (unfold decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)) cheri_invariant" + by (unfold decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)) cheri_invariant" + by (unfold decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)) cheri_invariant" + by (unfold decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)) cheri_invariant" + by (unfold decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)) cheri_invariant" + by (unfold decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)) cheri_invariant" + by (unfold decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)) cheri_invariant" + by (unfold decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)) cheri_invariant" + by (unfold decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)) cheri_invariant" + by (unfold decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)) cheri_invariant" + by (unfold decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)) cheri_invariant" + by (unfold decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)) cheri_invariant" + by (unfold decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)) cheri_invariant" + by (unfold decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_atomicops_ld (datasize :: 'datasize::len itself) ldacctype n op (regsize :: 'regsize::len itself) s__arg stacctype t__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldadd_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldadd_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldadd_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldaddb_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldaddb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldaddb_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldaddh_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldaddh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldaddh_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_ordered_rcpc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_ordered_rcpc acctype (datasize :: 'datasize::len itself) n (regsize :: 'regsize::len itself) t__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_ordered_rcpc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldapr_aarch64_instrs_memory_ordered_rcpc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldapr_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs b__0)) cheri_invariant" + by (unfold decode_ldapr_aarch64_instrs_memory_ordered_rcpc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldaprb_aarch64_instrs_memory_ordered_rcpc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldaprb_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs b__0)) cheri_invariant" + by (unfold decode_ldaprb_aarch64_instrs_memory_ordered_rcpc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldaprh_aarch64_instrs_memory_ordered_rcpc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldaprh_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs b__0)) cheri_invariant" + by (unfold decode_ldaprh_aarch64_instrs_memory_ordered_rcpc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_ordered_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_ordered acctype (datasize :: 'datasize::len itself) memop n (regsize :: 'regsize::len itself) t__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_ordered_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldar_aarch64_instrs_memory_ordered_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldar_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldar_aarch64_instrs_memory_ordered_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldarb_aarch64_instrs_memory_ordered_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldarb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldarb_aarch64_instrs_memory_ordered_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldarh_aarch64_instrs_memory_ordered_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldarh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldarh_aarch64_instrs_memory_ordered_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_exclusive_pair_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_exclusive_pair acctype l__197 elsize memop n pair (regsize :: 'regsize::len itself) s__arg t__arg t2)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_exclusive_pair_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldaxp_aarch64_instrs_memory_exclusive_pair_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldaxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldaxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_exclusive_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_exclusive_single acctype l__532 elsize memop n pair (regsize :: 'regsize::len itself) s__arg t__arg t2)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_exclusive_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldaxr_aarch64_instrs_memory_exclusive_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldaxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldaxr_aarch64_instrs_memory_exclusive_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldaxrb_aarch64_instrs_memory_exclusive_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldaxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldaxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldaxrh_aarch64_instrs_memory_exclusive_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldaxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldaxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldclr_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldclr_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldclr_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldclrb_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldclrb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldclrb_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldclrh_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldclrh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldclrh_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldeor_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldeor_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldeor_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldeorb_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldeorb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldeorb_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldeorh_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldeorh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldeorh_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldlar_aarch64_instrs_memory_ordered_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldlar_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldlar_aarch64_instrs_memory_ordered_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldlarb_aarch64_instrs_memory_ordered_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldlarb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldlarb_aarch64_instrs_memory_ordered_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldlarh_aarch64_instrs_memory_ordered_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldlarh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldlarh_aarch64_instrs_memory_ordered_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_pair_simdfp_no_alloc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_pair_simdfp_no_alloc acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_pair_general_no_alloc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_pair_general_no_alloc acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_pair_simdfp_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_pair_simdfp_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_pair_general_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_pair_general_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex is_signed t__arg t2 wback__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldp_gen_aarch64_instrs_memory_pair_general_offset_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldp_gen_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_ldp_gen_aarch64_instrs_memory_pair_general_offset_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldpsw_aarch64_instrs_memory_pair_general_offset_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldpsw_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_ldpsw_aarch64_instrs_memory_pair_general_offset_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg wback)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned Rt Rn imm12 b__0 b__1)) cheri_invariant" + by (unfold decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)) cheri_invariant" + by (unfold decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_literal_simdfp_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_literal_simdfp offset l__44 t__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_literal_simdfp_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp Rt imm19 opc)) cheri_invariant" + by (unfold decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_literal_general_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_literal_general memop offset is_signed l__200 t__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_literal_general_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldr_lit_gen_aarch64_instrs_memory_literal_general_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldr_lit_gen_aarch64_instrs_memory_literal_general Rt imm19 opc)) cheri_invariant" + by (unfold decode_ldr_lit_gen_aarch64_instrs_memory_literal_general_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_single_simdfp_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_single_simdfp_register acctype (datasize :: 'datasize::len itself) extend_type m memop n postindex shift t__arg wback)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_single_simdfp_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register Rt Rn S option_name Rm b__0 b__1)) cheri_invariant" + by (unfold decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_single_general_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_single_general_register acctype (datasize :: 'datasize::len itself) extend_type m memop n postindex (regsize :: 'regsize::len itself) shift is_signed t__arg wback__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_single_general_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)) cheri_invariant" + by (unfold decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrb_reg_aarch64_instrs_memory_single_general_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)) cheri_invariant" + by (unfold decode_ldrb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrh_reg_aarch64_instrs_memory_single_general_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)) cheri_invariant" + by (unfold decode_ldrh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrsb_reg_aarch64_instrs_memory_single_general_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrsb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)) cheri_invariant" + by (unfold decode_ldrsb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrsh_reg_aarch64_instrs_memory_single_general_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrsh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)) cheri_invariant" + by (unfold decode_ldrsh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)) cheri_invariant" + by (unfold decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrsw_lit_aarch64_instrs_memory_literal_general_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrsw_lit_aarch64_instrs_memory_literal_general Rt imm19 opc)) cheri_invariant" + by (unfold decode_ldrsw_lit_aarch64_instrs_memory_literal_general_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldrsw_reg_aarch64_instrs_memory_single_general_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldrsw_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)) cheri_invariant" + by (unfold decode_ldrsw_reg_aarch64_instrs_memory_single_general_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldset_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldset_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldset_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldsetb_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldsetb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldsetb_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldseth_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldseth_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldseth_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldsmax_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldsmax_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldsmax_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldsmin_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldsmin_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldsmin_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldsminb_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldsminb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldsminb_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldsminh_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldsminh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldsminh_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldumax_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldumax_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldumax_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldumaxb_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldumaxb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldumaxb_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldumaxh_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldumaxh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldumaxh_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldumin_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldumin_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_ldumin_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_lduminb_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_lduminb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_lduminb_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_lduminh_aarch64_instrs_memory_atomicops_ld_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_lduminh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0)) cheri_invariant" + by (unfold decode_lduminh_aarch64_instrs_memory_atomicops_ld_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg wback)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldxp_aarch64_instrs_memory_exclusive_pair_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldxr_aarch64_instrs_memory_exclusive_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldxr_aarch64_instrs_memory_exclusive_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldxrb_aarch64_instrs_memory_exclusive_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ldxrh_aarch64_instrs_memory_exclusive_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ldxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_ldxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_system_register_system_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_system_register_system read sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_system_register_system_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_mrs_aarch64_instrs_system_register_system_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_mrs_aarch64_instrs_system_register_system Rt op2 CRm CRn op1 o0 L)) cheri_invariant" + by (unfold decode_mrs_aarch64_instrs_system_register_system_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_msr_reg_aarch64_instrs_system_register_system_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_msr_reg_aarch64_instrs_system_register_system Rt op2 CRm CRn op1 o0 L)) cheri_invariant" + by (unfold decode_msr_reg_aarch64_instrs_system_register_system_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_single_general_immediate_unsigned_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_single_general_immediate_unsigned acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)) cheri_invariant" + by (unfold decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_prfm_lit_aarch64_instrs_memory_literal_general_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_prfm_lit_aarch64_instrs_memory_literal_general Rt imm19 opc)) cheri_invariant" + by (unfold decode_prfm_lit_aarch64_instrs_memory_literal_general_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_prfm_reg_aarch64_instrs_memory_single_general_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_prfm_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)) cheri_invariant" + by (unfold decode_prfm_reg_aarch64_instrs_memory_single_general_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_ret_aarch64_instrs_branch_unconditional_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_ret_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)) cheri_invariant" + by (unfold decode_ret_aarch64_instrs_branch_unconditional_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_reta_aarch64_instrs_branch_unconditional_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_reta_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)) cheri_invariant" + by (unfold decode_reta_aarch64_instrs_branch_unconditional_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)) cheri_invariant" + by (unfold decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)) cheri_invariant" + by (unfold decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)) cheri_invariant" + by (unfold decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)) cheri_invariant" + by (unfold decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)) cheri_invariant" + by (unfold decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)) cheri_invariant" + by (unfold decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)) cheri_invariant" + by (unfold decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)) cheri_invariant" + by (unfold decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)) cheri_invariant" + by (unfold decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)) cheri_invariant" + by (unfold decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)) cheri_invariant" + by (unfold decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)) cheri_invariant" + by (unfold decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1)) cheri_invariant" + by (unfold decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1)) cheri_invariant" + by (unfold decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2)) cheri_invariant" + by (unfold decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2)) cheri_invariant" + by (unfold decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_atomicops_st (datasize :: 'datasize::len itself) ldacctype n op s__arg stacctype)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stadd_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stadd_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stadd_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_staddb_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_staddb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_staddb_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_staddh_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_staddh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_staddh_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stclr_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stclr_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stclr_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stclrb_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stclrb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stclrb_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stclrh_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stclrh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stclrh_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_steor_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_steor_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_steor_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_steorb_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_steorb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_steorb_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_steorh_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_steorh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_steorh_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stllr_aarch64_instrs_memory_ordered_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stllr_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stllr_aarch64_instrs_memory_ordered_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stllrb_aarch64_instrs_memory_ordered_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stllrb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stllrb_aarch64_instrs_memory_ordered_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stllrh_aarch64_instrs_memory_ordered_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stllrh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stllrh_aarch64_instrs_memory_ordered_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stlr_aarch64_instrs_memory_ordered_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stlr_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stlr_aarch64_instrs_memory_ordered_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stlrb_aarch64_instrs_memory_ordered_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stlrb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stlrb_aarch64_instrs_memory_ordered_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stlrh_aarch64_instrs_memory_ordered_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stlrh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stlrh_aarch64_instrs_memory_ordered_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stlxp_aarch64_instrs_memory_exclusive_pair_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stlxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stlxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stlxr_aarch64_instrs_memory_exclusive_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stlxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stlxr_aarch64_instrs_memory_exclusive_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stlxrb_aarch64_instrs_memory_exclusive_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stlxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stlxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stlxrh_aarch64_instrs_memory_exclusive_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stlxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stlxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stp_gen_aarch64_instrs_memory_pair_general_offset_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stp_gen_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_stp_gen_aarch64_instrs_memory_pair_general_offset_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0)) cheri_invariant" + by (unfold decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned Rt Rn imm12 b__0 b__1)) cheri_invariant" + by (unfold decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)) cheri_invariant" + by (unfold decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register Rt Rn S option_name Rm b__0 b__1)) cheri_invariant" + by (unfold decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_str_reg_gen_aarch64_instrs_memory_single_general_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_str_reg_gen_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)) cheri_invariant" + by (unfold decode_str_reg_gen_aarch64_instrs_memory_single_general_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)) cheri_invariant" + by (unfold decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_strb_reg_aarch64_instrs_memory_single_general_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_strb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)) cheri_invariant" + by (unfold decode_strb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1)) cheri_invariant" + by (unfold decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_strh_reg_aarch64_instrs_memory_single_general_register_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_strh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1)) cheri_invariant" + by (unfold decode_strh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stset_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stset_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stset_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stsetb_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stsetb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stsetb_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stseth_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stseth_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stseth_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stsmax_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stsmax_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stsmax_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stsmaxb_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stsmaxb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stsmaxb_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stsmaxh_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stsmaxh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stsmaxh_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stsmin_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stsmin_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stsmin_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stsminb_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stsminb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stsminb_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stsminh_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stsminh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stsminh_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stumax_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stumax_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stumax_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stumaxb_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stumaxb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stumaxb_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stumaxh_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stumaxh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stumaxh_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stumin_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stumin_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stumin_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stuminb_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stuminb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stuminb_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stuminh_aarch64_instrs_memory_atomicops_st_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stuminh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0)) cheri_invariant" + by (unfold decode_stuminh_aarch64_instrs_memory_atomicops_st_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1)) cheri_invariant" + by (unfold decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stxp_aarch64_instrs_memory_exclusive_pair_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stxr_aarch64_instrs_memory_exclusive_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stxr_aarch64_instrs_memory_exclusive_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stxrb_aarch64_instrs_memory_exclusive_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_stxrh_aarch64_instrs_memory_exclusive_single_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_stxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0)) cheri_invariant" + by (unfold decode_stxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_memory_atomicops_swp_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_memory_atomicops_swp (datasize :: 'datasize::len itself) ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_memory_atomicops_swp_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_swp_aarch64_instrs_memory_atomicops_swp_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_swp_aarch64_instrs_memory_atomicops_swp Rt Rn Rs R A b__0)) cheri_invariant" + by (unfold decode_swp_aarch64_instrs_memory_atomicops_swp_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_swpb_aarch64_instrs_memory_atomicops_swp_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_swpb_aarch64_instrs_memory_atomicops_swp Rt Rn Rs R A b__0)) cheri_invariant" + by (unfold decode_swpb_aarch64_instrs_memory_atomicops_swp_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_swph_aarch64_instrs_memory_atomicops_swp_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_swph_aarch64_instrs_memory_atomicops_swp Rt Rn Rs R A b__0)) cheri_invariant" + by (unfold decode_swph_aarch64_instrs_memory_atomicops_swp_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_system_sysops_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_system_sysops has_result sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_system_sysops_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_sys_aarch64_instrs_system_sysops_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_sys_aarch64_instrs_system_sysops Rt op2 CRm CRn op1 L)) cheri_invariant" + by (unfold decode_sys_aarch64_instrs_system_sysops_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_sysl_aarch64_instrs_system_sysops_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_sysl_aarch64_instrs_system_sysops Rt op2 CRm CRn op1 L)) cheri_invariant" + by (unfold decode_sysl_aarch64_instrs_system_sysops_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma execute_aarch64_instrs_branch_conditional_test_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (execute_aarch64_instrs_branch_conditional_test bit_pos bit_val (datasize :: 'datasize::len itself) offset t__arg)) cheri_invariant" + by (unfold execute_aarch64_instrs_branch_conditional_test_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_tbnz_aarch64_instrs_branch_conditional_test_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_tbnz_aarch64_instrs_branch_conditional_test Rt imm14 b40 op b__0)) cheri_invariant" + by (unfold decode_tbnz_aarch64_instrs_branch_conditional_test_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma decode_tbz_aarch64_instrs_branch_conditional_test_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (decode_tbz_aarch64_instrs_branch_conditional_test Rt imm14 b40 op b__0)) cheri_invariant" + by (unfold decode_tbz_aarch64_instrs_branch_conditional_test_def bind_assoc liftState_simp comp_def, preserves_invariantI) + +lemma DecodeA64_preserves_invariant[runs_preserve_invariantI]: + "runs_preserve_invariant (liftS (DecodeA64 pc opcode)) cheri_invariant" + by (unfold DecodeA64_def bind_assoc liftState_simp comp_def, preserves_invariantI) + + +end diff --git a/CHERI_Mem_Properties.thy b/CHERI_Mem_Properties.thy new file mode 100644 index 0000000..2b37c19 --- /dev/null +++ b/CHERI_Mem_Properties.thy @@ -0,0 +1,10184 @@ +section \Generated instruction memory check proofs\ + +theory CHERI_Mem_Properties +imports CHERI_Lemmas +begin + +context Morello_Axiom_Automaton +begin + +lemma non_mem_exp_R_read[non_mem_expI]: + "non_mem_exp (R_read idx)" + by (unfold R_read_def, non_mem_expI) + +lemma non_mem_exp_R_set[non_mem_expI]: + "non_mem_exp (R_set idx c__arg)" + by (unfold R_set_def, non_mem_expI) + +lemma non_mem_exp_BranchTo[non_mem_expI]: + "non_mem_exp (BranchTo target branch_type)" + by (unfold BranchTo_def, non_mem_expI) + +lemma non_mem_exp_BranchToCapability[non_mem_expI]: + "non_mem_exp (BranchToCapability target branch_type)" + by (unfold BranchToCapability_def, non_mem_expI) + +lemma non_mem_exp_CELR_set[non_mem_expI]: + "non_mem_exp (CELR_set el value_name)" + by (unfold CELR_set_def, non_mem_expI) + +lemma non_mem_exp_CELR_set__1[non_mem_expI]: + "non_mem_exp (CELR_set__1 value_name)" + by (unfold CELR_set__1_def, non_mem_expI) + +lemma non_mem_exp_CVBAR_read[non_mem_expI]: + "non_mem_exp (CVBAR_read regime)" + by (unfold CVBAR_read_def, non_mem_expI) + +lemma non_mem_exp_CVBAR_read__1[non_mem_expI]: + "non_mem_exp (CVBAR_read__1 arg0)" + by (unfold CVBAR_read__1_def, non_mem_expI) + +lemma non_mem_exp_ELR_set[non_mem_expI]: + "non_mem_exp (ELR_set el value_name)" + by (unfold ELR_set_def, non_mem_expI) + +lemma non_mem_exp_ELR_set__1[non_mem_expI]: + "non_mem_exp (ELR_set__1 value_name)" + by (unfold ELR_set__1_def, non_mem_expI) + +lemma non_mem_exp_PCC_read[non_mem_expI]: + "non_mem_exp (PCC_read arg0)" + by (unfold PCC_read_def, non_mem_expI) + +lemma non_mem_exp_IsInRestricted[non_mem_expI]: + "non_mem_exp (IsInRestricted arg0)" + by (unfold IsInRestricted_def, non_mem_expI) + +lemma non_mem_exp_VBAR_read[non_mem_expI]: + "non_mem_exp (VBAR_read regime)" + by (unfold VBAR_read_def, non_mem_expI) + +lemma non_mem_exp_VBAR_read__1[non_mem_expI]: + "non_mem_exp (VBAR_read__1 arg0)" + by (unfold VBAR_read__1_def, non_mem_expI) + +lemma non_mem_exp_AArch64_TakeException[non_mem_expI]: + "non_mem_exp (AArch64_TakeException target_el exception preferred_exception_return vect_offset__arg)" + by (unfold AArch64_TakeException_def, non_mem_expI) + +lemma non_mem_exp_AArch64_SystemAccessTrap[non_mem_expI]: + "non_mem_exp (AArch64_SystemAccessTrap target_el ec)" + by (unfold AArch64_SystemAccessTrap_def, non_mem_expI) + +lemma non_mem_exp_CapIsSystemAccessEnabled[non_mem_expI]: + "non_mem_exp (CapIsSystemAccessEnabled arg0)" + by (unfold CapIsSystemAccessEnabled_def, non_mem_expI) + +lemma non_mem_exp_ACTLR_EL1_SysRegRead_56bd4d0367c16236[non_mem_expI]: + "non_mem_exp (ACTLR_EL1_SysRegRead_56bd4d0367c16236 el op0 op1 CRn op2 CRm)" + by (unfold ACTLR_EL1_SysRegRead_56bd4d0367c16236_def, non_mem_expI) + +lemma non_mem_exp_ACTLR_EL2_SysRegRead_ff23cef1b670b9c7[non_mem_expI]: + "non_mem_exp (ACTLR_EL2_SysRegRead_ff23cef1b670b9c7 el op0 op1 CRn op2 CRm)" + by (unfold ACTLR_EL2_SysRegRead_ff23cef1b670b9c7_def, non_mem_expI) + +lemma non_mem_exp_ACTLR_EL3_SysRegRead_397e6c0342e2936b[non_mem_expI]: + "non_mem_exp (ACTLR_EL3_SysRegRead_397e6c0342e2936b el op0 op1 CRn op2 CRm)" + by (unfold ACTLR_EL3_SysRegRead_397e6c0342e2936b_def, non_mem_expI) + +lemma non_mem_exp_AFSR0_EL12_SysRegRead_2488de32a3f38621[non_mem_expI]: + "non_mem_exp (AFSR0_EL12_SysRegRead_2488de32a3f38621 el op0 op1 CRn op2 CRm)" + by (unfold AFSR0_EL12_SysRegRead_2488de32a3f38621_def, non_mem_expI) + +lemma non_mem_exp_AFSR0_EL1_SysRegRead_80a4a0472e0b9142[non_mem_expI]: + "non_mem_exp (AFSR0_EL1_SysRegRead_80a4a0472e0b9142 el op0 op1 CRn op2 CRm)" + by (unfold AFSR0_EL1_SysRegRead_80a4a0472e0b9142_def, non_mem_expI) + +lemma non_mem_exp_AFSR0_EL2_SysRegRead_07613e9c4b98061a[non_mem_expI]: + "non_mem_exp (AFSR0_EL2_SysRegRead_07613e9c4b98061a el op0 op1 CRn op2 CRm)" + by (unfold AFSR0_EL2_SysRegRead_07613e9c4b98061a_def, non_mem_expI) + +lemma non_mem_exp_AFSR0_EL3_SysRegRead_d2e69d7912ca200c[non_mem_expI]: + "non_mem_exp (AFSR0_EL3_SysRegRead_d2e69d7912ca200c el op0 op1 CRn op2 CRm)" + by (unfold AFSR0_EL3_SysRegRead_d2e69d7912ca200c_def, non_mem_expI) + +lemma non_mem_exp_AFSR1_EL12_SysRegRead_39bb62021df07ecc[non_mem_expI]: + "non_mem_exp (AFSR1_EL12_SysRegRead_39bb62021df07ecc el op0 op1 CRn op2 CRm)" + by (unfold AFSR1_EL12_SysRegRead_39bb62021df07ecc_def, non_mem_expI) + +lemma non_mem_exp_AFSR1_EL1_SysRegRead_495927b72173c55f[non_mem_expI]: + "non_mem_exp (AFSR1_EL1_SysRegRead_495927b72173c55f el op0 op1 CRn op2 CRm)" + by (unfold AFSR1_EL1_SysRegRead_495927b72173c55f_def, non_mem_expI) + +lemma non_mem_exp_AFSR1_EL2_SysRegRead_f7cb9a59387f268f[non_mem_expI]: + "non_mem_exp (AFSR1_EL2_SysRegRead_f7cb9a59387f268f el op0 op1 CRn op2 CRm)" + by (unfold AFSR1_EL2_SysRegRead_f7cb9a59387f268f_def, non_mem_expI) + +lemma non_mem_exp_AFSR1_EL3_SysRegRead_a2ad736ad599f2b2[non_mem_expI]: + "non_mem_exp (AFSR1_EL3_SysRegRead_a2ad736ad599f2b2 el op0 op1 CRn op2 CRm)" + by (unfold AFSR1_EL3_SysRegRead_a2ad736ad599f2b2_def, non_mem_expI) + +lemma non_mem_exp_AIDR_EL1_SysRegRead_74ea31b1dc6f5c6f[non_mem_expI]: + "non_mem_exp (AIDR_EL1_SysRegRead_74ea31b1dc6f5c6f el op0 op1 CRn op2 CRm)" + by (unfold AIDR_EL1_SysRegRead_74ea31b1dc6f5c6f_def, non_mem_expI) + +lemma non_mem_exp_AMAIR_EL12_SysRegRead_87964a33cc1ad0ef[non_mem_expI]: + "non_mem_exp (AMAIR_EL12_SysRegRead_87964a33cc1ad0ef el op0 op1 CRn op2 CRm)" + by (unfold AMAIR_EL12_SysRegRead_87964a33cc1ad0ef_def, non_mem_expI) + +lemma non_mem_exp_AMAIR_EL1_SysRegRead_82d01d3808e04ca3[non_mem_expI]: + "non_mem_exp (AMAIR_EL1_SysRegRead_82d01d3808e04ca3 el op0 op1 CRn op2 CRm)" + by (unfold AMAIR_EL1_SysRegRead_82d01d3808e04ca3_def, non_mem_expI) + +lemma non_mem_exp_AMAIR_EL2_SysRegRead_3c316bb11b239640[non_mem_expI]: + "non_mem_exp (AMAIR_EL2_SysRegRead_3c316bb11b239640 el op0 op1 CRn op2 CRm)" + by (unfold AMAIR_EL2_SysRegRead_3c316bb11b239640_def, non_mem_expI) + +lemma non_mem_exp_AMAIR_EL3_SysRegRead_b1547f511477c529[non_mem_expI]: + "non_mem_exp (AMAIR_EL3_SysRegRead_b1547f511477c529 el op0 op1 CRn op2 CRm)" + by (unfold AMAIR_EL3_SysRegRead_b1547f511477c529_def, non_mem_expI) + +lemma non_mem_exp_CCSIDR_EL1_SysRegRead_210f94b423761d0b[non_mem_expI]: + "non_mem_exp (CCSIDR_EL1_SysRegRead_210f94b423761d0b el op0 op1 CRn op2 CRm)" + by (unfold CCSIDR_EL1_SysRegRead_210f94b423761d0b_def, non_mem_expI) + +lemma non_mem_exp_CCTLR_EL0_SysRegRead_3baa7e22d96a4ce4[non_mem_expI]: + "non_mem_exp (CCTLR_EL0_SysRegRead_3baa7e22d96a4ce4 el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL0_SysRegRead_3baa7e22d96a4ce4_def, non_mem_expI) + +lemma non_mem_exp_CCTLR_EL12_SysRegRead_e8b17aabd47dc7a1[non_mem_expI]: + "non_mem_exp (CCTLR_EL12_SysRegRead_e8b17aabd47dc7a1 el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL12_SysRegRead_e8b17aabd47dc7a1_def, non_mem_expI) + +lemma non_mem_exp_CCTLR_EL1_SysRegRead_de402a061eecb9b9[non_mem_expI]: + "non_mem_exp (CCTLR_EL1_SysRegRead_de402a061eecb9b9 el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL1_SysRegRead_de402a061eecb9b9_def, non_mem_expI) + +lemma non_mem_exp_CCTLR_EL2_SysRegRead_fca4364f27bb9f9b[non_mem_expI]: + "non_mem_exp (CCTLR_EL2_SysRegRead_fca4364f27bb9f9b el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL2_SysRegRead_fca4364f27bb9f9b_def, non_mem_expI) + +lemma non_mem_exp_CCTLR_EL3_SysRegRead_9121a22ebc361586[non_mem_expI]: + "non_mem_exp (CCTLR_EL3_SysRegRead_9121a22ebc361586 el op0 op1 CRn op2 CRm)" + by (unfold CCTLR_EL3_SysRegRead_9121a22ebc361586_def, non_mem_expI) + +lemma non_mem_exp_CHCR_EL2_SysRegRead_7d3c39a46321f1a2[non_mem_expI]: + "non_mem_exp (CHCR_EL2_SysRegRead_7d3c39a46321f1a2 el op0 op1 CRn op2 CRm)" + by (unfold CHCR_EL2_SysRegRead_7d3c39a46321f1a2_def, non_mem_expI) + +lemma non_mem_exp_CLIDR_EL1_SysRegRead_b403ddc99e97c3a8[non_mem_expI]: + "non_mem_exp (CLIDR_EL1_SysRegRead_b403ddc99e97c3a8 el op0 op1 CRn op2 CRm)" + by (unfold CLIDR_EL1_SysRegRead_b403ddc99e97c3a8_def, non_mem_expI) + +lemma non_mem_exp_CNTFRQ_EL0_SysRegRead_891ca00adf0c3783[non_mem_expI]: + "non_mem_exp (CNTFRQ_EL0_SysRegRead_891ca00adf0c3783 el op0 op1 CRn op2 CRm)" + by (unfold CNTFRQ_EL0_SysRegRead_891ca00adf0c3783_def, non_mem_expI) + +lemma non_mem_exp_CNTHCTL_EL2_SysRegRead_5f510d633361c720[non_mem_expI]: + "non_mem_exp (CNTHCTL_EL2_SysRegRead_5f510d633361c720 el op0 op1 CRn op2 CRm)" + by (unfold CNTHCTL_EL2_SysRegRead_5f510d633361c720_def, non_mem_expI) + +lemma non_mem_exp_CNTHP_CTL_EL2_SysRegRead_7103e47839f2c66b[non_mem_expI]: + "non_mem_exp (CNTHP_CTL_EL2_SysRegRead_7103e47839f2c66b el op0 op1 CRn op2 CRm)" + by (unfold CNTHP_CTL_EL2_SysRegRead_7103e47839f2c66b_def, non_mem_expI) + +lemma non_mem_exp_CNTHP_CVAL_EL2_SysRegRead_e25a0257128c640b[non_mem_expI]: + "non_mem_exp (CNTHP_CVAL_EL2_SysRegRead_e25a0257128c640b el op0 op1 CRn op2 CRm)" + by (unfold CNTHP_CVAL_EL2_SysRegRead_e25a0257128c640b_def, non_mem_expI) + +lemma non_mem_exp_CNTHP_TVAL_EL2_SysRegRead_d110a1f1616c9f8f[non_mem_expI]: + "non_mem_exp (CNTHP_TVAL_EL2_SysRegRead_d110a1f1616c9f8f el op0 op1 CRn op2 CRm)" + by (unfold CNTHP_TVAL_EL2_SysRegRead_d110a1f1616c9f8f_def, non_mem_expI) + +lemma non_mem_exp_CNTHV_CTL_EL2_SysRegRead_bc429f3d6b52b800[non_mem_expI]: + "non_mem_exp (CNTHV_CTL_EL2_SysRegRead_bc429f3d6b52b800 el op0 op1 CRn op2 CRm)" + by (unfold CNTHV_CTL_EL2_SysRegRead_bc429f3d6b52b800_def, non_mem_expI) + +lemma non_mem_exp_CNTHV_CVAL_EL2_SysRegRead_2c78392b89702ca9[non_mem_expI]: + "non_mem_exp (CNTHV_CVAL_EL2_SysRegRead_2c78392b89702ca9 el op0 op1 CRn op2 CRm)" + by (unfold CNTHV_CVAL_EL2_SysRegRead_2c78392b89702ca9_def, non_mem_expI) + +lemma non_mem_exp_CNTHV_TVAL_EL2_SysRegRead_2464c0e91db55a22[non_mem_expI]: + "non_mem_exp (CNTHV_TVAL_EL2_SysRegRead_2464c0e91db55a22 el op0 op1 CRn op2 CRm)" + by (unfold CNTHV_TVAL_EL2_SysRegRead_2464c0e91db55a22_def, non_mem_expI) + +lemma non_mem_exp_CNTKCTL_EL12_SysRegRead_c23def3111264258[non_mem_expI]: + "non_mem_exp (CNTKCTL_EL12_SysRegRead_c23def3111264258 el op0 op1 CRn op2 CRm)" + by (unfold CNTKCTL_EL12_SysRegRead_c23def3111264258_def, non_mem_expI) + +lemma non_mem_exp_CNTKCTL_EL1_SysRegRead_6a6cc900bc3c37df[non_mem_expI]: + "non_mem_exp (CNTKCTL_EL1_SysRegRead_6a6cc900bc3c37df el op0 op1 CRn op2 CRm)" + by (unfold CNTKCTL_EL1_SysRegRead_6a6cc900bc3c37df_def, non_mem_expI) + +lemma non_mem_exp_CNTPCT_EL0_SysRegRead_579be4c9ef4e6824[non_mem_expI]: + "non_mem_exp (CNTPCT_EL0_SysRegRead_579be4c9ef4e6824 el op0 op1 CRn op2 CRm)" + by (unfold CNTPCT_EL0_SysRegRead_579be4c9ef4e6824_def, non_mem_expI) + +lemma non_mem_exp_CNTPS_CTL_EL1_SysRegRead_e3bc6e5891147388[non_mem_expI]: + "non_mem_exp (CNTPS_CTL_EL1_SysRegRead_e3bc6e5891147388 el op0 op1 CRn op2 CRm)" + by (unfold CNTPS_CTL_EL1_SysRegRead_e3bc6e5891147388_def, non_mem_expI) + +lemma non_mem_exp_CNTPS_CVAL_EL1_SysRegRead_3e364bd573c45cae[non_mem_expI]: + "non_mem_exp (CNTPS_CVAL_EL1_SysRegRead_3e364bd573c45cae el op0 op1 CRn op2 CRm)" + by (unfold CNTPS_CVAL_EL1_SysRegRead_3e364bd573c45cae_def, non_mem_expI) + +lemma non_mem_exp_CNTPS_TVAL_EL1_SysRegRead_0784a7de0899eff0[non_mem_expI]: + "non_mem_exp (CNTPS_TVAL_EL1_SysRegRead_0784a7de0899eff0 el op0 op1 CRn op2 CRm)" + by (unfold CNTPS_TVAL_EL1_SysRegRead_0784a7de0899eff0_def, non_mem_expI) + +lemma non_mem_exp_CNTP_CTL_EL02_SysRegRead_9d9930274ff7fc36[non_mem_expI]: + "non_mem_exp (CNTP_CTL_EL02_SysRegRead_9d9930274ff7fc36 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_CTL_EL02_SysRegRead_9d9930274ff7fc36_def, non_mem_expI) + +lemma non_mem_exp_CNTP_CTL_EL0_SysRegRead_47237e002d686ac6[non_mem_expI]: + "non_mem_exp (CNTP_CTL_EL0_SysRegRead_47237e002d686ac6 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_CTL_EL0_SysRegRead_47237e002d686ac6_def, non_mem_expI) + +lemma non_mem_exp_CNTP_CVAL_EL02_SysRegRead_8377305437cbebb4[non_mem_expI]: + "non_mem_exp (CNTP_CVAL_EL02_SysRegRead_8377305437cbebb4 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_CVAL_EL02_SysRegRead_8377305437cbebb4_def, non_mem_expI) + +lemma non_mem_exp_CNTP_CVAL_EL0_SysRegRead_4db28ae745612584[non_mem_expI]: + "non_mem_exp (CNTP_CVAL_EL0_SysRegRead_4db28ae745612584 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_CVAL_EL0_SysRegRead_4db28ae745612584_def, non_mem_expI) + +lemma non_mem_exp_CNTP_TVAL_EL02_SysRegRead_6539005e4eb68283[non_mem_expI]: + "non_mem_exp (CNTP_TVAL_EL02_SysRegRead_6539005e4eb68283 el op0 op1 CRn op2 CRm)" + by (unfold CNTP_TVAL_EL02_SysRegRead_6539005e4eb68283_def, non_mem_expI) + +lemma non_mem_exp_CNTP_TVAL_EL0_SysRegRead_54cebb7fbc71b9db[non_mem_expI]: + "non_mem_exp (CNTP_TVAL_EL0_SysRegRead_54cebb7fbc71b9db el op0 op1 CRn op2 CRm)" + by (unfold CNTP_TVAL_EL0_SysRegRead_54cebb7fbc71b9db_def, non_mem_expI) + +lemma non_mem_exp_CNTVCT_EL0_SysRegRead_cd7c8aebed2715e6[non_mem_expI]: + "non_mem_exp (CNTVCT_EL0_SysRegRead_cd7c8aebed2715e6 el op0 op1 CRn op2 CRm)" + by (unfold CNTVCT_EL0_SysRegRead_cd7c8aebed2715e6_def, non_mem_expI) + +lemma non_mem_exp_CNTVOFF_EL2_SysRegRead_5ca7336b54f14c06[non_mem_expI]: + "non_mem_exp (CNTVOFF_EL2_SysRegRead_5ca7336b54f14c06 el op0 op1 CRn op2 CRm)" + by (unfold CNTVOFF_EL2_SysRegRead_5ca7336b54f14c06_def, non_mem_expI) + +lemma non_mem_exp_CNTV_CTL_EL02_SysRegRead_4188a8e2bc5c07aa[non_mem_expI]: + "non_mem_exp (CNTV_CTL_EL02_SysRegRead_4188a8e2bc5c07aa el op0 op1 CRn op2 CRm)" + by (unfold CNTV_CTL_EL02_SysRegRead_4188a8e2bc5c07aa_def, non_mem_expI) + +lemma non_mem_exp_CNTV_CTL_EL0_SysRegRead_bcb2d1b80bdb9c23[non_mem_expI]: + "non_mem_exp (CNTV_CTL_EL0_SysRegRead_bcb2d1b80bdb9c23 el op0 op1 CRn op2 CRm)" + by (unfold CNTV_CTL_EL0_SysRegRead_bcb2d1b80bdb9c23_def, non_mem_expI) + +lemma non_mem_exp_CNTV_CVAL_EL02_SysRegRead_abd2b9f314cb85b2[non_mem_expI]: + "non_mem_exp (CNTV_CVAL_EL02_SysRegRead_abd2b9f314cb85b2 el op0 op1 CRn op2 CRm)" + by (unfold CNTV_CVAL_EL02_SysRegRead_abd2b9f314cb85b2_def, non_mem_expI) + +lemma non_mem_exp_CNTV_CVAL_EL0_SysRegRead_54d5eb0bec99456f[non_mem_expI]: + "non_mem_exp (CNTV_CVAL_EL0_SysRegRead_54d5eb0bec99456f el op0 op1 CRn op2 CRm)" + by (unfold CNTV_CVAL_EL0_SysRegRead_54d5eb0bec99456f_def, non_mem_expI) + +lemma non_mem_exp_CNTV_TVAL_EL02_SysRegRead_f904ccdf39aea128[non_mem_expI]: + "non_mem_exp (CNTV_TVAL_EL02_SysRegRead_f904ccdf39aea128 el op0 op1 CRn op2 CRm)" + by (unfold CNTV_TVAL_EL02_SysRegRead_f904ccdf39aea128_def, non_mem_expI) + +lemma non_mem_exp_CNTV_TVAL_EL0_SysRegRead_919e73a694090e48[non_mem_expI]: + "non_mem_exp (CNTV_TVAL_EL0_SysRegRead_919e73a694090e48 el op0 op1 CRn op2 CRm)" + by (unfold CNTV_TVAL_EL0_SysRegRead_919e73a694090e48_def, non_mem_expI) + +lemma non_mem_exp_CONTEXTIDR_EL12_SysRegRead_2aa676fc0cfd631b[non_mem_expI]: + "non_mem_exp (CONTEXTIDR_EL12_SysRegRead_2aa676fc0cfd631b el op0 op1 CRn op2 CRm)" + by (unfold CONTEXTIDR_EL12_SysRegRead_2aa676fc0cfd631b_def, non_mem_expI) + +lemma non_mem_exp_CONTEXTIDR_EL1_SysRegRead_fa54232c55ea14e3[non_mem_expI]: + "non_mem_exp (CONTEXTIDR_EL1_SysRegRead_fa54232c55ea14e3 el op0 op1 CRn op2 CRm)" + by (unfold CONTEXTIDR_EL1_SysRegRead_fa54232c55ea14e3_def, non_mem_expI) + +lemma non_mem_exp_CONTEXTIDR_EL2_SysRegRead_f7bf9114ce3113a6[non_mem_expI]: + "non_mem_exp (CONTEXTIDR_EL2_SysRegRead_f7bf9114ce3113a6 el op0 op1 CRn op2 CRm)" + by (unfold CONTEXTIDR_EL2_SysRegRead_f7bf9114ce3113a6_def, non_mem_expI) + +lemma non_mem_exp_CPACR_EL12_SysRegRead_0f7867518c4e8e99[non_mem_expI]: + "non_mem_exp (CPACR_EL12_SysRegRead_0f7867518c4e8e99 el op0 op1 CRn op2 CRm)" + by (unfold CPACR_EL12_SysRegRead_0f7867518c4e8e99_def, non_mem_expI) + +lemma non_mem_exp_CPACR_EL1_SysRegRead_63b8f196f3ebba22[non_mem_expI]: + "non_mem_exp (CPACR_EL1_SysRegRead_63b8f196f3ebba22 el op0 op1 CRn op2 CRm)" + by (unfold CPACR_EL1_SysRegRead_63b8f196f3ebba22_def, non_mem_expI) + +lemma non_mem_exp_CPTR_EL2_SysRegRead_d80843789adc6a43[non_mem_expI]: + "non_mem_exp (CPTR_EL2_SysRegRead_d80843789adc6a43 el op0 op1 CRn op2 CRm)" + by (unfold CPTR_EL2_SysRegRead_d80843789adc6a43_def, non_mem_expI) + +lemma non_mem_exp_CPTR_EL3_SysRegRead_33cb1e5ec3c99661[non_mem_expI]: + "non_mem_exp (CPTR_EL3_SysRegRead_33cb1e5ec3c99661 el op0 op1 CRn op2 CRm)" + by (unfold CPTR_EL3_SysRegRead_33cb1e5ec3c99661_def, non_mem_expI) + +lemma non_mem_exp_CSCR_EL3_SysRegRead_3c6b19768f9cd209[non_mem_expI]: + "non_mem_exp (CSCR_EL3_SysRegRead_3c6b19768f9cd209 el op0 op1 CRn op2 CRm)" + by (unfold CSCR_EL3_SysRegRead_3c6b19768f9cd209_def, non_mem_expI) + +lemma non_mem_exp_CSSELR_EL1_SysRegRead_102b4cddc07c9121[non_mem_expI]: + "non_mem_exp (CSSELR_EL1_SysRegRead_102b4cddc07c9121 el op0 op1 CRn op2 CRm)" + by (unfold CSSELR_EL1_SysRegRead_102b4cddc07c9121_def, non_mem_expI) + +lemma non_mem_exp_CTR_EL0_SysRegRead_54ef8c769c3c6bba[non_mem_expI]: + "non_mem_exp (CTR_EL0_SysRegRead_54ef8c769c3c6bba el op0 op1 CRn op2 CRm)" + by (unfold CTR_EL0_SysRegRead_54ef8c769c3c6bba_def, non_mem_expI) + +lemma non_mem_exp_DACR32_EL2_SysRegRead_9571e2946627a596[non_mem_expI]: + "non_mem_exp (DACR32_EL2_SysRegRead_9571e2946627a596 el op0 op1 CRn op2 CRm)" + by (unfold DACR32_EL2_SysRegRead_9571e2946627a596_def, non_mem_expI) + +lemma non_mem_exp_DAIF_SysRegRead_198f3b46fcf6c8f0[non_mem_expI]: + "non_mem_exp (DAIF_SysRegRead_198f3b46fcf6c8f0 el op0 op1 CRn op2 CRm)" + by (unfold DAIF_SysRegRead_198f3b46fcf6c8f0_def, non_mem_expI) + +lemma non_mem_exp_DBGAUTHSTATUS_EL1_SysRegRead_6ade6e7a5265bcb7[non_mem_expI]: + "non_mem_exp (DBGAUTHSTATUS_EL1_SysRegRead_6ade6e7a5265bcb7 el op0 op1 CRn op2 CRm)" + by (unfold DBGAUTHSTATUS_EL1_SysRegRead_6ade6e7a5265bcb7_def, non_mem_expI) + +lemma non_mem_exp_Halt[non_mem_expI]: + "non_mem_exp (Halt reason)" + by (unfold Halt_def, non_mem_expI) + +lemma non_mem_exp_DBGBCR_EL1_SysRegRead_2d021994672d40d3[non_mem_expI]: + "non_mem_exp (DBGBCR_EL1_SysRegRead_2d021994672d40d3 el op0 op1 CRn op2 CRm)" + by (unfold DBGBCR_EL1_SysRegRead_2d021994672d40d3_def, non_mem_expI) + +lemma non_mem_exp_DBGBVR_EL1_SysRegRead_dc4a8f61b400622f[non_mem_expI]: + "non_mem_exp (DBGBVR_EL1_SysRegRead_dc4a8f61b400622f el op0 op1 CRn op2 CRm)" + by (unfold DBGBVR_EL1_SysRegRead_dc4a8f61b400622f_def, non_mem_expI) + +lemma non_mem_exp_DBGCLAIMCLR_EL1_SysRegRead_72ae03c1d5f667da[non_mem_expI]: + "non_mem_exp (DBGCLAIMCLR_EL1_SysRegRead_72ae03c1d5f667da el op0 op1 CRn op2 CRm)" + by (unfold DBGCLAIMCLR_EL1_SysRegRead_72ae03c1d5f667da_def, non_mem_expI) + +lemma non_mem_exp_DBGCLAIMSET_EL1_SysRegRead_8557cf3b6272a9e8[non_mem_expI]: + "non_mem_exp (DBGCLAIMSET_EL1_SysRegRead_8557cf3b6272a9e8 el op0 op1 CRn op2 CRm)" + by (unfold DBGCLAIMSET_EL1_SysRegRead_8557cf3b6272a9e8_def, non_mem_expI) + +lemma non_mem_exp_DBGDTRRX_EL0_SysRegRead_e7b48d8296f3b86b[non_mem_expI]: + "non_mem_exp (DBGDTRRX_EL0_SysRegRead_e7b48d8296f3b86b el op0 op1 CRn op2 CRm)" + by (unfold DBGDTRRX_EL0_SysRegRead_e7b48d8296f3b86b_def, non_mem_expI) + +lemma non_mem_exp_DBGDTR_EL0_read__1[non_mem_expI]: + "non_mem_exp (DBGDTR_EL0_read__1 arg0)" + by (unfold DBGDTR_EL0_read__1_def, non_mem_expI) + +lemma non_mem_exp_DBGDTR_EL0_SysRegRead_537a006eb82c59aa[non_mem_expI]: + "non_mem_exp (DBGDTR_EL0_SysRegRead_537a006eb82c59aa el op0 op1 CRn op2 CRm)" + by (unfold DBGDTR_EL0_SysRegRead_537a006eb82c59aa_def, non_mem_expI) + +lemma non_mem_exp_DBGPRCR_EL1_SysRegRead_6b19d62af9619a21[non_mem_expI]: + "non_mem_exp (DBGPRCR_EL1_SysRegRead_6b19d62af9619a21 el op0 op1 CRn op2 CRm)" + by (unfold DBGPRCR_EL1_SysRegRead_6b19d62af9619a21_def, non_mem_expI) + +lemma non_mem_exp_DBGVCR32_EL2_SysRegRead_7986b2bdf8df010d[non_mem_expI]: + "non_mem_exp (DBGVCR32_EL2_SysRegRead_7986b2bdf8df010d el op0 op1 CRn op2 CRm)" + by (unfold DBGVCR32_EL2_SysRegRead_7986b2bdf8df010d_def, non_mem_expI) + +lemma non_mem_exp_DBGWCR_EL1_SysRegRead_03139d052b544b2f[non_mem_expI]: + "non_mem_exp (DBGWCR_EL1_SysRegRead_03139d052b544b2f el op0 op1 CRn op2 CRm)" + by (unfold DBGWCR_EL1_SysRegRead_03139d052b544b2f_def, non_mem_expI) + +lemma non_mem_exp_DBGWVR_EL1_SysRegRead_029de1005ef34888[non_mem_expI]: + "non_mem_exp (DBGWVR_EL1_SysRegRead_029de1005ef34888 el op0 op1 CRn op2 CRm)" + by (unfold DBGWVR_EL1_SysRegRead_029de1005ef34888_def, non_mem_expI) + +lemma non_mem_exp_DISR_EL1_SysRegRead_d06ce25101dac895[non_mem_expI]: + "non_mem_exp (DISR_EL1_SysRegRead_d06ce25101dac895 el op0 op1 CRn op2 CRm)" + by (unfold DISR_EL1_SysRegRead_d06ce25101dac895_def, non_mem_expI) + +lemma non_mem_exp_DLR_EL0_read[non_mem_expI]: + "non_mem_exp (DLR_EL0_read arg0)" + by (unfold DLR_EL0_read_def, non_mem_expI) + +lemma non_mem_exp_DLR_EL0_SysRegRead_75b9821e3e84ec13[non_mem_expI]: + "non_mem_exp (DLR_EL0_SysRegRead_75b9821e3e84ec13 el op0 op1 CRn op2 CRm)" + by (unfold DLR_EL0_SysRegRead_75b9821e3e84ec13_def, non_mem_expI) + +lemma non_mem_exp_ELR_EL12_SysRegRead_e8215c0ae79859bb[non_mem_expI]: + "non_mem_exp (ELR_EL12_SysRegRead_e8215c0ae79859bb el op0 op1 CRn op2 CRm)" + by (unfold ELR_EL12_SysRegRead_e8215c0ae79859bb_def, non_mem_expI) + +lemma non_mem_exp_ELR_EL1_SysRegRead_0d3f1ad1483e96c2[non_mem_expI]: + "non_mem_exp (ELR_EL1_SysRegRead_0d3f1ad1483e96c2 el op0 op1 CRn op2 CRm)" + by (unfold ELR_EL1_SysRegRead_0d3f1ad1483e96c2_def, non_mem_expI) + +lemma non_mem_exp_ELR_EL2_SysRegRead_00b4dd4251404d91[non_mem_expI]: + "non_mem_exp (ELR_EL2_SysRegRead_00b4dd4251404d91 el op0 op1 CRn op2 CRm)" + by (unfold ELR_EL2_SysRegRead_00b4dd4251404d91_def, non_mem_expI) + +lemma non_mem_exp_ELR_EL3_SysRegRead_a7a7cd4e7e805396[non_mem_expI]: + "non_mem_exp (ELR_EL3_SysRegRead_a7a7cd4e7e805396 el op0 op1 CRn op2 CRm)" + by (unfold ELR_EL3_SysRegRead_a7a7cd4e7e805396_def, non_mem_expI) + +lemma non_mem_exp_ERRIDR_EL1_SysRegRead_41b56b8d34e51109[non_mem_expI]: + "non_mem_exp (ERRIDR_EL1_SysRegRead_41b56b8d34e51109 el op0 op1 CRn op2 CRm)" + by (unfold ERRIDR_EL1_SysRegRead_41b56b8d34e51109_def, non_mem_expI) + +lemma non_mem_exp_ERRSELR_EL1_SysRegRead_1bcf942400e8d57f[non_mem_expI]: + "non_mem_exp (ERRSELR_EL1_SysRegRead_1bcf942400e8d57f el op0 op1 CRn op2 CRm)" + by (unfold ERRSELR_EL1_SysRegRead_1bcf942400e8d57f_def, non_mem_expI) + +lemma non_mem_exp_ERXADDR_EL1_SysRegRead_7dea05bca757fc1d[non_mem_expI]: + "non_mem_exp (ERXADDR_EL1_SysRegRead_7dea05bca757fc1d el op0 op1 CRn op2 CRm)" + by (unfold ERXADDR_EL1_SysRegRead_7dea05bca757fc1d_def, non_mem_expI) + +lemma non_mem_exp_ERXCTLR_EL1_SysRegRead_e46ed88d092db048[non_mem_expI]: + "non_mem_exp (ERXCTLR_EL1_SysRegRead_e46ed88d092db048 el op0 op1 CRn op2 CRm)" + by (unfold ERXCTLR_EL1_SysRegRead_e46ed88d092db048_def, non_mem_expI) + +lemma non_mem_exp_ERXFR_EL1_SysRegRead_ed2a3c237ae67a43[non_mem_expI]: + "non_mem_exp (ERXFR_EL1_SysRegRead_ed2a3c237ae67a43 el op0 op1 CRn op2 CRm)" + by (unfold ERXFR_EL1_SysRegRead_ed2a3c237ae67a43_def, non_mem_expI) + +lemma non_mem_exp_ERXMISC0_EL1_SysRegRead_a71a4de5f2444f19[non_mem_expI]: + "non_mem_exp (ERXMISC0_EL1_SysRegRead_a71a4de5f2444f19 el op0 op1 CRn op2 CRm)" + by (unfold ERXMISC0_EL1_SysRegRead_a71a4de5f2444f19_def, non_mem_expI) + +lemma non_mem_exp_ERXMISC1_EL1_SysRegRead_bda613f8058b1fd8[non_mem_expI]: + "non_mem_exp (ERXMISC1_EL1_SysRegRead_bda613f8058b1fd8 el op0 op1 CRn op2 CRm)" + by (unfold ERXMISC1_EL1_SysRegRead_bda613f8058b1fd8_def, non_mem_expI) + +lemma non_mem_exp_ERXSTATUS_EL1_SysRegRead_0ab2cfe6937b8b64[non_mem_expI]: + "non_mem_exp (ERXSTATUS_EL1_SysRegRead_0ab2cfe6937b8b64 el op0 op1 CRn op2 CRm)" + by (unfold ERXSTATUS_EL1_SysRegRead_0ab2cfe6937b8b64_def, non_mem_expI) + +lemma non_mem_exp_ESR_EL12_SysRegRead_207d3805d256851a[non_mem_expI]: + "non_mem_exp (ESR_EL12_SysRegRead_207d3805d256851a el op0 op1 CRn op2 CRm)" + by (unfold ESR_EL12_SysRegRead_207d3805d256851a_def, non_mem_expI) + +lemma non_mem_exp_ESR_EL1_SysRegRead_4894753806397624[non_mem_expI]: + "non_mem_exp (ESR_EL1_SysRegRead_4894753806397624 el op0 op1 CRn op2 CRm)" + by (unfold ESR_EL1_SysRegRead_4894753806397624_def, non_mem_expI) + +lemma non_mem_exp_ESR_EL2_SysRegRead_e0558cb255261414[non_mem_expI]: + "non_mem_exp (ESR_EL2_SysRegRead_e0558cb255261414 el op0 op1 CRn op2 CRm)" + by (unfold ESR_EL2_SysRegRead_e0558cb255261414_def, non_mem_expI) + +lemma non_mem_exp_ESR_EL3_SysRegRead_e0eabec0b099e366[non_mem_expI]: + "non_mem_exp (ESR_EL3_SysRegRead_e0eabec0b099e366 el op0 op1 CRn op2 CRm)" + by (unfold ESR_EL3_SysRegRead_e0eabec0b099e366_def, non_mem_expI) + +lemma non_mem_exp_FAR_EL12_SysRegRead_061fecffb03f9fc5[non_mem_expI]: + "non_mem_exp (FAR_EL12_SysRegRead_061fecffb03f9fc5 el op0 op1 CRn op2 CRm)" + by (unfold FAR_EL12_SysRegRead_061fecffb03f9fc5_def, non_mem_expI) + +lemma non_mem_exp_FAR_EL1_SysRegRead_136ac0cc65bd5f9d[non_mem_expI]: + "non_mem_exp (FAR_EL1_SysRegRead_136ac0cc65bd5f9d el op0 op1 CRn op2 CRm)" + by (unfold FAR_EL1_SysRegRead_136ac0cc65bd5f9d_def, non_mem_expI) + +lemma non_mem_exp_FAR_EL2_SysRegRead_d686d0a5577f0aae[non_mem_expI]: + "non_mem_exp (FAR_EL2_SysRegRead_d686d0a5577f0aae el op0 op1 CRn op2 CRm)" + by (unfold FAR_EL2_SysRegRead_d686d0a5577f0aae_def, non_mem_expI) + +lemma non_mem_exp_FAR_EL3_SysRegRead_d63ec2764f8ffe40[non_mem_expI]: + "non_mem_exp (FAR_EL3_SysRegRead_d63ec2764f8ffe40 el op0 op1 CRn op2 CRm)" + by (unfold FAR_EL3_SysRegRead_d63ec2764f8ffe40_def, non_mem_expI) + +lemma non_mem_exp_FPCR_SysRegRead_4176e216195c5686[non_mem_expI]: + "non_mem_exp (FPCR_SysRegRead_4176e216195c5686 el op0 op1 CRn op2 CRm)" + by (unfold FPCR_SysRegRead_4176e216195c5686_def, non_mem_expI) + +lemma non_mem_exp_FPEXC32_EL2_SysRegRead_7ee503337da57806[non_mem_expI]: + "non_mem_exp (FPEXC32_EL2_SysRegRead_7ee503337da57806 el op0 op1 CRn op2 CRm)" + by (unfold FPEXC32_EL2_SysRegRead_7ee503337da57806_def, non_mem_expI) + +lemma non_mem_exp_FPSR_SysRegRead_c1fde5c387acaca1[non_mem_expI]: + "non_mem_exp (FPSR_SysRegRead_c1fde5c387acaca1 el op0 op1 CRn op2 CRm)" + by (unfold FPSR_SysRegRead_c1fde5c387acaca1_def, non_mem_expI) + +lemma non_mem_exp_HACR_EL2_SysRegRead_07bc3864e8ed8264[non_mem_expI]: + "non_mem_exp (HACR_EL2_SysRegRead_07bc3864e8ed8264 el op0 op1 CRn op2 CRm)" + by (unfold HACR_EL2_SysRegRead_07bc3864e8ed8264_def, non_mem_expI) + +lemma non_mem_exp_HCR_EL2_SysRegRead_f76ecfdc85c5ff7c[non_mem_expI]: + "non_mem_exp (HCR_EL2_SysRegRead_f76ecfdc85c5ff7c el op0 op1 CRn op2 CRm)" + by (unfold HCR_EL2_SysRegRead_f76ecfdc85c5ff7c_def, non_mem_expI) + +lemma non_mem_exp_HPFAR_EL2_SysRegRead_4c322cee424dff18[non_mem_expI]: + "non_mem_exp (HPFAR_EL2_SysRegRead_4c322cee424dff18 el op0 op1 CRn op2 CRm)" + by (unfold HPFAR_EL2_SysRegRead_4c322cee424dff18_def, non_mem_expI) + +lemma non_mem_exp_HSTR_EL2_SysRegRead_680380b9028cf399[non_mem_expI]: + "non_mem_exp (HSTR_EL2_SysRegRead_680380b9028cf399 el op0 op1 CRn op2 CRm)" + by (unfold HSTR_EL2_SysRegRead_680380b9028cf399_def, non_mem_expI) + +lemma non_mem_exp_ICC_AP0R_EL1_SysRegRead_cac9b22dc3786a15[non_mem_expI]: + "non_mem_exp (ICC_AP0R_EL1_SysRegRead_cac9b22dc3786a15 el op0 op1 CRn op2 CRm)" + by (unfold ICC_AP0R_EL1_SysRegRead_cac9b22dc3786a15_def, non_mem_expI) + +lemma non_mem_exp_ICC_AP1R_EL1_SysRegRead_4127418c67790ba3[non_mem_expI]: + "non_mem_exp (ICC_AP1R_EL1_SysRegRead_4127418c67790ba3 el op0 op1 CRn op2 CRm)" + by (unfold ICC_AP1R_EL1_SysRegRead_4127418c67790ba3_def, non_mem_expI) + +lemma non_mem_exp_ICC_BPR0_EL1_SysRegRead_6ada10a9051248c2[non_mem_expI]: + "non_mem_exp (ICC_BPR0_EL1_SysRegRead_6ada10a9051248c2 el op0 op1 CRn op2 CRm)" + by (unfold ICC_BPR0_EL1_SysRegRead_6ada10a9051248c2_def, non_mem_expI) + +lemma non_mem_exp_ICC_BPR1_EL1_SysRegRead_c56bf88f1b4aee37[non_mem_expI]: + "non_mem_exp (ICC_BPR1_EL1_SysRegRead_c56bf88f1b4aee37 el op0 op1 CRn op2 CRm)" + by (unfold ICC_BPR1_EL1_SysRegRead_c56bf88f1b4aee37_def, non_mem_expI) + +lemma non_mem_exp_ICC_CTLR_EL1_SysRegRead_5754830bf787a1e2[non_mem_expI]: + "non_mem_exp (ICC_CTLR_EL1_SysRegRead_5754830bf787a1e2 el op0 op1 CRn op2 CRm)" + by (unfold ICC_CTLR_EL1_SysRegRead_5754830bf787a1e2_def, non_mem_expI) + +lemma non_mem_exp_ICC_CTLR_EL3_SysRegRead_aba1771445e9d51b[non_mem_expI]: + "non_mem_exp (ICC_CTLR_EL3_SysRegRead_aba1771445e9d51b el op0 op1 CRn op2 CRm)" + by (unfold ICC_CTLR_EL3_SysRegRead_aba1771445e9d51b_def, non_mem_expI) + +lemma non_mem_exp_ICC_HPPIR0_EL1_SysRegRead_221f9a6f32464de4[non_mem_expI]: + "non_mem_exp (ICC_HPPIR0_EL1_SysRegRead_221f9a6f32464de4 el op0 op1 CRn op2 CRm)" + by (unfold ICC_HPPIR0_EL1_SysRegRead_221f9a6f32464de4_def, non_mem_expI) + +lemma non_mem_exp_ICC_HPPIR1_EL1_SysRegRead_88ed0889f7d5a37a[non_mem_expI]: + "non_mem_exp (ICC_HPPIR1_EL1_SysRegRead_88ed0889f7d5a37a el op0 op1 CRn op2 CRm)" + by (unfold ICC_HPPIR1_EL1_SysRegRead_88ed0889f7d5a37a_def, non_mem_expI) + +lemma non_mem_exp_ICC_IAR0_EL1_SysRegRead_dcfaf70befc09037[non_mem_expI]: + "non_mem_exp (ICC_IAR0_EL1_SysRegRead_dcfaf70befc09037 el op0 op1 CRn op2 CRm)" + by (unfold ICC_IAR0_EL1_SysRegRead_dcfaf70befc09037_def, non_mem_expI) + +lemma non_mem_exp_ICC_IAR1_EL1_SysRegRead_9f370ba68fd3e44f[non_mem_expI]: + "non_mem_exp (ICC_IAR1_EL1_SysRegRead_9f370ba68fd3e44f el op0 op1 CRn op2 CRm)" + by (unfold ICC_IAR1_EL1_SysRegRead_9f370ba68fd3e44f_def, non_mem_expI) + +lemma non_mem_exp_ICC_IGRPEN0_EL1_SysRegRead_e575448f3c7e7a94[non_mem_expI]: + "non_mem_exp (ICC_IGRPEN0_EL1_SysRegRead_e575448f3c7e7a94 el op0 op1 CRn op2 CRm)" + by (unfold ICC_IGRPEN0_EL1_SysRegRead_e575448f3c7e7a94_def, non_mem_expI) + +lemma non_mem_exp_ICC_IGRPEN1_EL1_SysRegRead_3cfd0733ef9b6efa[non_mem_expI]: + "non_mem_exp (ICC_IGRPEN1_EL1_SysRegRead_3cfd0733ef9b6efa el op0 op1 CRn op2 CRm)" + by (unfold ICC_IGRPEN1_EL1_SysRegRead_3cfd0733ef9b6efa_def, non_mem_expI) + +lemma non_mem_exp_ICC_IGRPEN1_EL3_SysRegRead_d192d252016b4c8d[non_mem_expI]: + "non_mem_exp (ICC_IGRPEN1_EL3_SysRegRead_d192d252016b4c8d el op0 op1 CRn op2 CRm)" + by (unfold ICC_IGRPEN1_EL3_SysRegRead_d192d252016b4c8d_def, non_mem_expI) + +lemma non_mem_exp_ICC_PMR_EL1_SysRegRead_4ab2c9427488fbf4[non_mem_expI]: + "non_mem_exp (ICC_PMR_EL1_SysRegRead_4ab2c9427488fbf4 el op0 op1 CRn op2 CRm)" + by (unfold ICC_PMR_EL1_SysRegRead_4ab2c9427488fbf4_def, non_mem_expI) + +lemma non_mem_exp_ICC_RPR_EL1_SysRegRead_bea9edc41b26aab0[non_mem_expI]: + "non_mem_exp (ICC_RPR_EL1_SysRegRead_bea9edc41b26aab0 el op0 op1 CRn op2 CRm)" + by (unfold ICC_RPR_EL1_SysRegRead_bea9edc41b26aab0_def, non_mem_expI) + +lemma non_mem_exp_ICC_SRE_EL1_SysRegRead_7cf0aa9fc619dea4[non_mem_expI]: + "non_mem_exp (ICC_SRE_EL1_SysRegRead_7cf0aa9fc619dea4 el op0 op1 CRn op2 CRm)" + by (unfold ICC_SRE_EL1_SysRegRead_7cf0aa9fc619dea4_def, non_mem_expI) + +lemma non_mem_exp_ICC_SRE_EL2_SysRegRead_35c9349812c986fe[non_mem_expI]: + "non_mem_exp (ICC_SRE_EL2_SysRegRead_35c9349812c986fe el op0 op1 CRn op2 CRm)" + by (unfold ICC_SRE_EL2_SysRegRead_35c9349812c986fe_def, non_mem_expI) + +lemma non_mem_exp_ICC_SRE_EL3_SysRegRead_c7d421022a5f589d[non_mem_expI]: + "non_mem_exp (ICC_SRE_EL3_SysRegRead_c7d421022a5f589d el op0 op1 CRn op2 CRm)" + by (unfold ICC_SRE_EL3_SysRegRead_c7d421022a5f589d_def, non_mem_expI) + +lemma non_mem_exp_ICH_AP0R_EL2_SysRegRead_a38114229330a389[non_mem_expI]: + "non_mem_exp (ICH_AP0R_EL2_SysRegRead_a38114229330a389 el op0 op1 CRn op2 CRm)" + by (unfold ICH_AP0R_EL2_SysRegRead_a38114229330a389_def, non_mem_expI) + +lemma non_mem_exp_ICH_AP1R_EL2_SysRegRead_3ef1256520a6f18e[non_mem_expI]: + "non_mem_exp (ICH_AP1R_EL2_SysRegRead_3ef1256520a6f18e el op0 op1 CRn op2 CRm)" + by (unfold ICH_AP1R_EL2_SysRegRead_3ef1256520a6f18e_def, non_mem_expI) + +lemma non_mem_exp_ICH_EISR_EL2_SysRegRead_a45d99ec0ef64804[non_mem_expI]: + "non_mem_exp (ICH_EISR_EL2_SysRegRead_a45d99ec0ef64804 el op0 op1 CRn op2 CRm)" + by (unfold ICH_EISR_EL2_SysRegRead_a45d99ec0ef64804_def, non_mem_expI) + +lemma non_mem_exp_ICH_ELRSR_EL2_SysRegRead_93859a236e9efe6d[non_mem_expI]: + "non_mem_exp (ICH_ELRSR_EL2_SysRegRead_93859a236e9efe6d el op0 op1 CRn op2 CRm)" + by (unfold ICH_ELRSR_EL2_SysRegRead_93859a236e9efe6d_def, non_mem_expI) + +lemma non_mem_exp_ICH_HCR_EL2_SysRegRead_bd436f3e91661e3b[non_mem_expI]: + "non_mem_exp (ICH_HCR_EL2_SysRegRead_bd436f3e91661e3b el op0 op1 CRn op2 CRm)" + by (unfold ICH_HCR_EL2_SysRegRead_bd436f3e91661e3b_def, non_mem_expI) + +lemma non_mem_exp_ICH_LR_EL2_SysRegRead_f9d8d38c7064e389[non_mem_expI]: + "non_mem_exp (ICH_LR_EL2_SysRegRead_f9d8d38c7064e389 el op0 op1 CRn op2 CRm)" + by (unfold ICH_LR_EL2_SysRegRead_f9d8d38c7064e389_def, non_mem_expI) + +lemma non_mem_exp_ICH_MISR_EL2_SysRegRead_4e46f86d49bd21cd[non_mem_expI]: + "non_mem_exp (ICH_MISR_EL2_SysRegRead_4e46f86d49bd21cd el op0 op1 CRn op2 CRm)" + by (unfold ICH_MISR_EL2_SysRegRead_4e46f86d49bd21cd_def, non_mem_expI) + +lemma non_mem_exp_ICH_VMCR_EL2_SysRegRead_3c019711ec735507[non_mem_expI]: + "non_mem_exp (ICH_VMCR_EL2_SysRegRead_3c019711ec735507 el op0 op1 CRn op2 CRm)" + by (unfold ICH_VMCR_EL2_SysRegRead_3c019711ec735507_def, non_mem_expI) + +lemma non_mem_exp_ICH_VTR_EL2_SysRegRead_2ed82d00af03b344[non_mem_expI]: + "non_mem_exp (ICH_VTR_EL2_SysRegRead_2ed82d00af03b344 el op0 op1 CRn op2 CRm)" + by (unfold ICH_VTR_EL2_SysRegRead_2ed82d00af03b344_def, non_mem_expI) + +lemma non_mem_exp_ID_AA64AFR0_EL1_SysRegRead_325547f3ac10431a[non_mem_expI]: + "non_mem_exp (ID_AA64AFR0_EL1_SysRegRead_325547f3ac10431a el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64AFR0_EL1_SysRegRead_325547f3ac10431a_def, non_mem_expI) + +lemma non_mem_exp_ID_AA64AFR1_EL1_SysRegRead_99b67b76121ee706[non_mem_expI]: + "non_mem_exp (ID_AA64AFR1_EL1_SysRegRead_99b67b76121ee706 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64AFR1_EL1_SysRegRead_99b67b76121ee706_def, non_mem_expI) + +lemma non_mem_exp_ID_AA64DFR0_EL1_SysRegRead_c3e6b049dd70bbab[non_mem_expI]: + "non_mem_exp (ID_AA64DFR0_EL1_SysRegRead_c3e6b049dd70bbab el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64DFR0_EL1_SysRegRead_c3e6b049dd70bbab_def, non_mem_expI) + +lemma non_mem_exp_ID_AA64DFR1_EL1_SysRegRead_2f066031859d7035[non_mem_expI]: + "non_mem_exp (ID_AA64DFR1_EL1_SysRegRead_2f066031859d7035 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64DFR1_EL1_SysRegRead_2f066031859d7035_def, non_mem_expI) + +lemma non_mem_exp_ID_AA64ISAR0_EL1_SysRegRead_d35f255c04eaab0f[non_mem_expI]: + "non_mem_exp (ID_AA64ISAR0_EL1_SysRegRead_d35f255c04eaab0f el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64ISAR0_EL1_SysRegRead_d35f255c04eaab0f_def, non_mem_expI) + +lemma non_mem_exp_ID_AA64ISAR1_EL1_SysRegRead_1132f371c4707f61[non_mem_expI]: + "non_mem_exp (ID_AA64ISAR1_EL1_SysRegRead_1132f371c4707f61 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64ISAR1_EL1_SysRegRead_1132f371c4707f61_def, non_mem_expI) + +lemma non_mem_exp_ID_AA64MMFR0_EL1_SysRegRead_836c46ff67ac3f3d[non_mem_expI]: + "non_mem_exp (ID_AA64MMFR0_EL1_SysRegRead_836c46ff67ac3f3d el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64MMFR0_EL1_SysRegRead_836c46ff67ac3f3d_def, non_mem_expI) + +lemma non_mem_exp_ID_AA64MMFR1_EL1_SysRegRead_3abbf4d2af8dd3be[non_mem_expI]: + "non_mem_exp (ID_AA64MMFR1_EL1_SysRegRead_3abbf4d2af8dd3be el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64MMFR1_EL1_SysRegRead_3abbf4d2af8dd3be_def, non_mem_expI) + +lemma non_mem_exp_ID_AA64MMFR2_EL1_SysRegRead_1443648da3ca79dd[non_mem_expI]: + "non_mem_exp (ID_AA64MMFR2_EL1_SysRegRead_1443648da3ca79dd el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64MMFR2_EL1_SysRegRead_1443648da3ca79dd_def, non_mem_expI) + +lemma non_mem_exp_ID_AA64PFR0_EL1_SysRegRead_fe78f914579c8717[non_mem_expI]: + "non_mem_exp (ID_AA64PFR0_EL1_SysRegRead_fe78f914579c8717 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64PFR0_EL1_SysRegRead_fe78f914579c8717_def, non_mem_expI) + +lemma non_mem_exp_ID_AA64PFR1_EL1_SysRegRead_3be470f3d1bff138[non_mem_expI]: + "non_mem_exp (ID_AA64PFR1_EL1_SysRegRead_3be470f3d1bff138 el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64PFR1_EL1_SysRegRead_3be470f3d1bff138_def, non_mem_expI) + +lemma non_mem_exp_ID_AA64ZFR0_EL1_SysRegRead_70425f5143f66c9f[non_mem_expI]: + "non_mem_exp (ID_AA64ZFR0_EL1_SysRegRead_70425f5143f66c9f el op0 op1 CRn op2 CRm)" + by (unfold ID_AA64ZFR0_EL1_SysRegRead_70425f5143f66c9f_def, non_mem_expI) + +lemma non_mem_exp_ID_AFR0_EL1_SysRegRead_019e5ec822653217[non_mem_expI]: + "non_mem_exp (ID_AFR0_EL1_SysRegRead_019e5ec822653217 el op0 op1 CRn op2 CRm)" + by (unfold ID_AFR0_EL1_SysRegRead_019e5ec822653217_def, non_mem_expI) + +lemma non_mem_exp_ID_DFR0_EL1_SysRegRead_12146217191b4fee[non_mem_expI]: + "non_mem_exp (ID_DFR0_EL1_SysRegRead_12146217191b4fee el op0 op1 CRn op2 CRm)" + by (unfold ID_DFR0_EL1_SysRegRead_12146217191b4fee_def, non_mem_expI) + +lemma non_mem_exp_ID_ISAR0_EL1_SysRegRead_4e2f04c3a26dddb3[non_mem_expI]: + "non_mem_exp (ID_ISAR0_EL1_SysRegRead_4e2f04c3a26dddb3 el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR0_EL1_SysRegRead_4e2f04c3a26dddb3_def, non_mem_expI) + +lemma non_mem_exp_ID_ISAR1_EL1_SysRegRead_2f4500748023e22b[non_mem_expI]: + "non_mem_exp (ID_ISAR1_EL1_SysRegRead_2f4500748023e22b el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR1_EL1_SysRegRead_2f4500748023e22b_def, non_mem_expI) + +lemma non_mem_exp_ID_ISAR2_EL1_SysRegRead_1e8edaee6a0e9ef9[non_mem_expI]: + "non_mem_exp (ID_ISAR2_EL1_SysRegRead_1e8edaee6a0e9ef9 el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR2_EL1_SysRegRead_1e8edaee6a0e9ef9_def, non_mem_expI) + +lemma non_mem_exp_ID_ISAR3_EL1_SysRegRead_cf9a1aae39d73bdd[non_mem_expI]: + "non_mem_exp (ID_ISAR3_EL1_SysRegRead_cf9a1aae39d73bdd el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR3_EL1_SysRegRead_cf9a1aae39d73bdd_def, non_mem_expI) + +lemma non_mem_exp_ID_ISAR4_EL1_SysRegRead_9bffd9dcf4dd4ef4[non_mem_expI]: + "non_mem_exp (ID_ISAR4_EL1_SysRegRead_9bffd9dcf4dd4ef4 el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR4_EL1_SysRegRead_9bffd9dcf4dd4ef4_def, non_mem_expI) + +lemma non_mem_exp_ID_ISAR5_EL1_SysRegRead_f70928ed2f55c1f0[non_mem_expI]: + "non_mem_exp (ID_ISAR5_EL1_SysRegRead_f70928ed2f55c1f0 el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR5_EL1_SysRegRead_f70928ed2f55c1f0_def, non_mem_expI) + +lemma non_mem_exp_ID_ISAR6_EL1_SysRegRead_6ce3605912a2db6d[non_mem_expI]: + "non_mem_exp (ID_ISAR6_EL1_SysRegRead_6ce3605912a2db6d el op0 op1 CRn op2 CRm)" + by (unfold ID_ISAR6_EL1_SysRegRead_6ce3605912a2db6d_def, non_mem_expI) + +lemma non_mem_exp_ID_MMFR0_EL1_SysRegRead_b31c5faa39841084[non_mem_expI]: + "non_mem_exp (ID_MMFR0_EL1_SysRegRead_b31c5faa39841084 el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR0_EL1_SysRegRead_b31c5faa39841084_def, non_mem_expI) + +lemma non_mem_exp_ID_MMFR1_EL1_SysRegRead_b0f4bc0d71c9af14[non_mem_expI]: + "non_mem_exp (ID_MMFR1_EL1_SysRegRead_b0f4bc0d71c9af14 el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR1_EL1_SysRegRead_b0f4bc0d71c9af14_def, non_mem_expI) + +lemma non_mem_exp_ID_MMFR2_EL1_SysRegRead_b60501193094f759[non_mem_expI]: + "non_mem_exp (ID_MMFR2_EL1_SysRegRead_b60501193094f759 el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR2_EL1_SysRegRead_b60501193094f759_def, non_mem_expI) + +lemma non_mem_exp_ID_MMFR3_EL1_SysRegRead_dc45af19c356c392[non_mem_expI]: + "non_mem_exp (ID_MMFR3_EL1_SysRegRead_dc45af19c356c392 el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR3_EL1_SysRegRead_dc45af19c356c392_def, non_mem_expI) + +lemma non_mem_exp_ID_MMFR4_EL1_SysRegRead_237ae4b6fb487f3e[non_mem_expI]: + "non_mem_exp (ID_MMFR4_EL1_SysRegRead_237ae4b6fb487f3e el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR4_EL1_SysRegRead_237ae4b6fb487f3e_def, non_mem_expI) + +lemma non_mem_exp_ID_MMFR5_EL1_SysRegRead_00dc6140c3593f6a[non_mem_expI]: + "non_mem_exp (ID_MMFR5_EL1_SysRegRead_00dc6140c3593f6a el op0 op1 CRn op2 CRm)" + by (unfold ID_MMFR5_EL1_SysRegRead_00dc6140c3593f6a_def, non_mem_expI) + +lemma non_mem_exp_ID_PFR0_EL1_SysRegRead_ab73eb91d66cfece[non_mem_expI]: + "non_mem_exp (ID_PFR0_EL1_SysRegRead_ab73eb91d66cfece el op0 op1 CRn op2 CRm)" + by (unfold ID_PFR0_EL1_SysRegRead_ab73eb91d66cfece_def, non_mem_expI) + +lemma non_mem_exp_ID_PFR1_EL1_SysRegRead_264075958e26856b[non_mem_expI]: + "non_mem_exp (ID_PFR1_EL1_SysRegRead_264075958e26856b el op0 op1 CRn op2 CRm)" + by (unfold ID_PFR1_EL1_SysRegRead_264075958e26856b_def, non_mem_expI) + +lemma non_mem_exp_ID_PFR2_EL1_SysRegRead_8561b575e8dfcee0[non_mem_expI]: + "non_mem_exp (ID_PFR2_EL1_SysRegRead_8561b575e8dfcee0 el op0 op1 CRn op2 CRm)" + by (unfold ID_PFR2_EL1_SysRegRead_8561b575e8dfcee0_def, non_mem_expI) + +lemma non_mem_exp_IFSR32_EL2_SysRegRead_3b41290786c143ba[non_mem_expI]: + "non_mem_exp (IFSR32_EL2_SysRegRead_3b41290786c143ba el op0 op1 CRn op2 CRm)" + by (unfold IFSR32_EL2_SysRegRead_3b41290786c143ba_def, non_mem_expI) + +lemma non_mem_exp_ISR_EL1_SysRegRead_41b7dbf26b89e726[non_mem_expI]: + "non_mem_exp (ISR_EL1_SysRegRead_41b7dbf26b89e726 el op0 op1 CRn op2 CRm)" + by (unfold ISR_EL1_SysRegRead_41b7dbf26b89e726_def, non_mem_expI) + +lemma non_mem_exp_LORC_EL1_SysRegRead_0067e90ee116c26f[non_mem_expI]: + "non_mem_exp (LORC_EL1_SysRegRead_0067e90ee116c26f el op0 op1 CRn op2 CRm)" + by (unfold LORC_EL1_SysRegRead_0067e90ee116c26f_def, non_mem_expI) + +lemma non_mem_exp_LOREA_EL1_SysRegRead_ec495c3c15ed4dbe[non_mem_expI]: + "non_mem_exp (LOREA_EL1_SysRegRead_ec495c3c15ed4dbe el op0 op1 CRn op2 CRm)" + by (unfold LOREA_EL1_SysRegRead_ec495c3c15ed4dbe_def, non_mem_expI) + +lemma non_mem_exp_LORID_EL1_SysRegRead_a063108cc96d4baa[non_mem_expI]: + "non_mem_exp (LORID_EL1_SysRegRead_a063108cc96d4baa el op0 op1 CRn op2 CRm)" + by (unfold LORID_EL1_SysRegRead_a063108cc96d4baa_def, non_mem_expI) + +lemma non_mem_exp_LORN_EL1_SysRegRead_da981b495b21c400[non_mem_expI]: + "non_mem_exp (LORN_EL1_SysRegRead_da981b495b21c400 el op0 op1 CRn op2 CRm)" + by (unfold LORN_EL1_SysRegRead_da981b495b21c400_def, non_mem_expI) + +lemma non_mem_exp_LORSA_EL1_SysRegRead_cdc08dda4115abc7[non_mem_expI]: + "non_mem_exp (LORSA_EL1_SysRegRead_cdc08dda4115abc7 el op0 op1 CRn op2 CRm)" + by (unfold LORSA_EL1_SysRegRead_cdc08dda4115abc7_def, non_mem_expI) + +lemma non_mem_exp_MAIR_EL12_SysRegRead_ac3327848e47dda6[non_mem_expI]: + "non_mem_exp (MAIR_EL12_SysRegRead_ac3327848e47dda6 el op0 op1 CRn op2 CRm)" + by (unfold MAIR_EL12_SysRegRead_ac3327848e47dda6_def, non_mem_expI) + +lemma non_mem_exp_MAIR_EL1_SysRegRead_ee00b1441fc4a50d[non_mem_expI]: + "non_mem_exp (MAIR_EL1_SysRegRead_ee00b1441fc4a50d el op0 op1 CRn op2 CRm)" + by (unfold MAIR_EL1_SysRegRead_ee00b1441fc4a50d_def, non_mem_expI) + +lemma non_mem_exp_MAIR_EL2_SysRegRead_66c03f7cb594c1bd[non_mem_expI]: + "non_mem_exp (MAIR_EL2_SysRegRead_66c03f7cb594c1bd el op0 op1 CRn op2 CRm)" + by (unfold MAIR_EL2_SysRegRead_66c03f7cb594c1bd_def, non_mem_expI) + +lemma non_mem_exp_MAIR_EL3_SysRegRead_0eb4af28a4f9b45a[non_mem_expI]: + "non_mem_exp (MAIR_EL3_SysRegRead_0eb4af28a4f9b45a el op0 op1 CRn op2 CRm)" + by (unfold MAIR_EL3_SysRegRead_0eb4af28a4f9b45a_def, non_mem_expI) + +lemma non_mem_exp_MDCCINT_EL1_SysRegRead_12f1a0397d5a3729[non_mem_expI]: + "non_mem_exp (MDCCINT_EL1_SysRegRead_12f1a0397d5a3729 el op0 op1 CRn op2 CRm)" + by (unfold MDCCINT_EL1_SysRegRead_12f1a0397d5a3729_def, non_mem_expI) + +lemma non_mem_exp_MDCCSR_EL0_SysRegRead_1ca0d9105cd616c5[non_mem_expI]: + "non_mem_exp (MDCCSR_EL0_SysRegRead_1ca0d9105cd616c5 el op0 op1 CRn op2 CRm)" + by (unfold MDCCSR_EL0_SysRegRead_1ca0d9105cd616c5_def, non_mem_expI) + +lemma non_mem_exp_MDCR_EL2_SysRegRead_f2181c815a998208[non_mem_expI]: + "non_mem_exp (MDCR_EL2_SysRegRead_f2181c815a998208 el op0 op1 CRn op2 CRm)" + by (unfold MDCR_EL2_SysRegRead_f2181c815a998208_def, non_mem_expI) + +lemma non_mem_exp_MDCR_EL3_SysRegRead_229d5ee95c6e9850[non_mem_expI]: + "non_mem_exp (MDCR_EL3_SysRegRead_229d5ee95c6e9850 el op0 op1 CRn op2 CRm)" + by (unfold MDCR_EL3_SysRegRead_229d5ee95c6e9850_def, non_mem_expI) + +lemma non_mem_exp_MDRAR_EL1_SysRegRead_4c6f0d270d3fe56e[non_mem_expI]: + "non_mem_exp (MDRAR_EL1_SysRegRead_4c6f0d270d3fe56e el op0 op1 CRn op2 CRm)" + by (unfold MDRAR_EL1_SysRegRead_4c6f0d270d3fe56e_def, non_mem_expI) + +lemma non_mem_exp_MDSCR_EL1_SysRegRead_5184636ced539526[non_mem_expI]: + "non_mem_exp (MDSCR_EL1_SysRegRead_5184636ced539526 el op0 op1 CRn op2 CRm)" + by (unfold MDSCR_EL1_SysRegRead_5184636ced539526_def, non_mem_expI) + +lemma non_mem_exp_MIDR_EL1_SysRegRead_d49cc5f604ad167e[non_mem_expI]: + "non_mem_exp (MIDR_EL1_SysRegRead_d49cc5f604ad167e el op0 op1 CRn op2 CRm)" + by (unfold MIDR_EL1_SysRegRead_d49cc5f604ad167e_def, non_mem_expI) + +lemma non_mem_exp_MPAM0_EL1_SysRegRead_87af318fd5c9f9f7[non_mem_expI]: + "non_mem_exp (MPAM0_EL1_SysRegRead_87af318fd5c9f9f7 el op0 op1 CRn op2 CRm)" + by (unfold MPAM0_EL1_SysRegRead_87af318fd5c9f9f7_def, non_mem_expI) + +lemma non_mem_exp_MPAM1_EL12_SysRegRead_229a253b730e26d9[non_mem_expI]: + "non_mem_exp (MPAM1_EL12_SysRegRead_229a253b730e26d9 el op0 op1 CRn op2 CRm)" + by (unfold MPAM1_EL12_SysRegRead_229a253b730e26d9_def, non_mem_expI) + +lemma non_mem_exp_MPAM1_EL1_SysRegRead_770ea23b87b18d99[non_mem_expI]: + "non_mem_exp (MPAM1_EL1_SysRegRead_770ea23b87b18d99 el op0 op1 CRn op2 CRm)" + by (unfold MPAM1_EL1_SysRegRead_770ea23b87b18d99_def, non_mem_expI) + +lemma non_mem_exp_MPAM2_EL2_SysRegRead_10b60646fb381bea[non_mem_expI]: + "non_mem_exp (MPAM2_EL2_SysRegRead_10b60646fb381bea el op0 op1 CRn op2 CRm)" + by (unfold MPAM2_EL2_SysRegRead_10b60646fb381bea_def, non_mem_expI) + +lemma non_mem_exp_MPAM3_EL3_SysRegRead_989f38b07d8b4265[non_mem_expI]: + "non_mem_exp (MPAM3_EL3_SysRegRead_989f38b07d8b4265 el op0 op1 CRn op2 CRm)" + by (unfold MPAM3_EL3_SysRegRead_989f38b07d8b4265_def, non_mem_expI) + +lemma non_mem_exp_MPAMHCR_EL2_SysRegRead_6ee5f61be808e32e[non_mem_expI]: + "non_mem_exp (MPAMHCR_EL2_SysRegRead_6ee5f61be808e32e el op0 op1 CRn op2 CRm)" + by (unfold MPAMHCR_EL2_SysRegRead_6ee5f61be808e32e_def, non_mem_expI) + +lemma non_mem_exp_MPAMIDR_EL1_SysRegRead_df4c57d831354b3c[non_mem_expI]: + "non_mem_exp (MPAMIDR_EL1_SysRegRead_df4c57d831354b3c el op0 op1 CRn op2 CRm)" + by (unfold MPAMIDR_EL1_SysRegRead_df4c57d831354b3c_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM0_EL2_SysRegRead_d878a15f2ea1751d[non_mem_expI]: + "non_mem_exp (MPAMVPM0_EL2_SysRegRead_d878a15f2ea1751d el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM0_EL2_SysRegRead_d878a15f2ea1751d_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM1_EL2_SysRegRead_78ba55a3ef5fc5ba[non_mem_expI]: + "non_mem_exp (MPAMVPM1_EL2_SysRegRead_78ba55a3ef5fc5ba el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM1_EL2_SysRegRead_78ba55a3ef5fc5ba_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM2_EL2_SysRegRead_590d1577b5eb780d[non_mem_expI]: + "non_mem_exp (MPAMVPM2_EL2_SysRegRead_590d1577b5eb780d el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM2_EL2_SysRegRead_590d1577b5eb780d_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM3_EL2_SysRegRead_3d93a30deb34ea81[non_mem_expI]: + "non_mem_exp (MPAMVPM3_EL2_SysRegRead_3d93a30deb34ea81 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM3_EL2_SysRegRead_3d93a30deb34ea81_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM4_EL2_SysRegRead_c4fa65dba541d8f3[non_mem_expI]: + "non_mem_exp (MPAMVPM4_EL2_SysRegRead_c4fa65dba541d8f3 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM4_EL2_SysRegRead_c4fa65dba541d8f3_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM5_EL2_SysRegRead_0f596cf6a35cf124[non_mem_expI]: + "non_mem_exp (MPAMVPM5_EL2_SysRegRead_0f596cf6a35cf124 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM5_EL2_SysRegRead_0f596cf6a35cf124_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM6_EL2_SysRegRead_c93ffeb6ea409c71[non_mem_expI]: + "non_mem_exp (MPAMVPM6_EL2_SysRegRead_c93ffeb6ea409c71 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM6_EL2_SysRegRead_c93ffeb6ea409c71_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM7_EL2_SysRegRead_ef19c89f1fa31f3e[non_mem_expI]: + "non_mem_exp (MPAMVPM7_EL2_SysRegRead_ef19c89f1fa31f3e el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPM7_EL2_SysRegRead_ef19c89f1fa31f3e_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPMV_EL2_SysRegRead_6de5731367257b91[non_mem_expI]: + "non_mem_exp (MPAMVPMV_EL2_SysRegRead_6de5731367257b91 el op0 op1 CRn op2 CRm)" + by (unfold MPAMVPMV_EL2_SysRegRead_6de5731367257b91_def, non_mem_expI) + +lemma non_mem_exp_MPIDR_EL1_SysRegRead_1a44c237fc7e90a0[non_mem_expI]: + "non_mem_exp (MPIDR_EL1_SysRegRead_1a44c237fc7e90a0 el op0 op1 CRn op2 CRm)" + by (unfold MPIDR_EL1_SysRegRead_1a44c237fc7e90a0_def, non_mem_expI) + +lemma non_mem_exp_MVFR0_EL1_SysRegRead_982614cb681cfbbf[non_mem_expI]: + "non_mem_exp (MVFR0_EL1_SysRegRead_982614cb681cfbbf el op0 op1 CRn op2 CRm)" + by (unfold MVFR0_EL1_SysRegRead_982614cb681cfbbf_def, non_mem_expI) + +lemma non_mem_exp_MVFR1_EL1_SysRegRead_1964a95566ab0fcd[non_mem_expI]: + "non_mem_exp (MVFR1_EL1_SysRegRead_1964a95566ab0fcd el op0 op1 CRn op2 CRm)" + by (unfold MVFR1_EL1_SysRegRead_1964a95566ab0fcd_def, non_mem_expI) + +lemma non_mem_exp_MVFR2_EL1_SysRegRead_f6245ffc535897f2[non_mem_expI]: + "non_mem_exp (MVFR2_EL1_SysRegRead_f6245ffc535897f2 el op0 op1 CRn op2 CRm)" + by (unfold MVFR2_EL1_SysRegRead_f6245ffc535897f2_def, non_mem_expI) + +lemma non_mem_exp_OSDLR_EL1_SysRegRead_4cb80c508c4cced4[non_mem_expI]: + "non_mem_exp (OSDLR_EL1_SysRegRead_4cb80c508c4cced4 el op0 op1 CRn op2 CRm)" + by (unfold OSDLR_EL1_SysRegRead_4cb80c508c4cced4_def, non_mem_expI) + +lemma non_mem_exp_OSDTRRX_EL1_SysRegRead_d4eb07360bc69d28[non_mem_expI]: + "non_mem_exp (OSDTRRX_EL1_SysRegRead_d4eb07360bc69d28 el op0 op1 CRn op2 CRm)" + by (unfold OSDTRRX_EL1_SysRegRead_d4eb07360bc69d28_def, non_mem_expI) + +lemma non_mem_exp_OSDTRTX_EL1_SysRegRead_008c22058272684f[non_mem_expI]: + "non_mem_exp (OSDTRTX_EL1_SysRegRead_008c22058272684f el op0 op1 CRn op2 CRm)" + by (unfold OSDTRTX_EL1_SysRegRead_008c22058272684f_def, non_mem_expI) + +lemma non_mem_exp_OSECCR_EL1_SysRegRead_264ab12a32fecc30[non_mem_expI]: + "non_mem_exp (OSECCR_EL1_SysRegRead_264ab12a32fecc30 el op0 op1 CRn op2 CRm)" + by (unfold OSECCR_EL1_SysRegRead_264ab12a32fecc30_def, non_mem_expI) + +lemma non_mem_exp_OSLSR_EL1_SysRegRead_d99062033a35ccbf[non_mem_expI]: + "non_mem_exp (OSLSR_EL1_SysRegRead_d99062033a35ccbf el op0 op1 CRn op2 CRm)" + by (unfold OSLSR_EL1_SysRegRead_d99062033a35ccbf_def, non_mem_expI) + +lemma non_mem_exp_PAR_EL1_SysRegRead_888e7c84935ebac7[non_mem_expI]: + "non_mem_exp (PAR_EL1_SysRegRead_888e7c84935ebac7 el op0 op1 CRn op2 CRm)" + by (unfold PAR_EL1_SysRegRead_888e7c84935ebac7_def, non_mem_expI) + +lemma non_mem_exp_PMBIDR_EL1_SysRegRead_306c3f68e41521a3[non_mem_expI]: + "non_mem_exp (PMBIDR_EL1_SysRegRead_306c3f68e41521a3 el op0 op1 CRn op2 CRm)" + by (unfold PMBIDR_EL1_SysRegRead_306c3f68e41521a3_def, non_mem_expI) + +lemma non_mem_exp_PMBLIMITR_EL1_SysRegRead_b7c18938ab0566dc[non_mem_expI]: + "non_mem_exp (PMBLIMITR_EL1_SysRegRead_b7c18938ab0566dc el op0 op1 CRn op2 CRm)" + by (unfold PMBLIMITR_EL1_SysRegRead_b7c18938ab0566dc_def, non_mem_expI) + +lemma non_mem_exp_PMBPTR_EL1_SysRegRead_fb82e1b6e480bd0a[non_mem_expI]: + "non_mem_exp (PMBPTR_EL1_SysRegRead_fb82e1b6e480bd0a el op0 op1 CRn op2 CRm)" + by (unfold PMBPTR_EL1_SysRegRead_fb82e1b6e480bd0a_def, non_mem_expI) + +lemma non_mem_exp_PMBSR_EL1_SysRegRead_87628bec330b9f53[non_mem_expI]: + "non_mem_exp (PMBSR_EL1_SysRegRead_87628bec330b9f53 el op0 op1 CRn op2 CRm)" + by (unfold PMBSR_EL1_SysRegRead_87628bec330b9f53_def, non_mem_expI) + +lemma non_mem_exp_PMCCFILTR_EL0_SysRegRead_349918c2333bfc1e[non_mem_expI]: + "non_mem_exp (PMCCFILTR_EL0_SysRegRead_349918c2333bfc1e el op0 op1 CRn op2 CRm)" + by (unfold PMCCFILTR_EL0_SysRegRead_349918c2333bfc1e_def, non_mem_expI) + +lemma non_mem_exp_PMCCNTR_EL0_SysRegRead_45fc425eff298404[non_mem_expI]: + "non_mem_exp (PMCCNTR_EL0_SysRegRead_45fc425eff298404 el op0 op1 CRn op2 CRm)" + by (unfold PMCCNTR_EL0_SysRegRead_45fc425eff298404_def, non_mem_expI) + +lemma non_mem_exp_PMCEID0_EL0_SysRegRead_1364a10a0c913d82[non_mem_expI]: + "non_mem_exp (PMCEID0_EL0_SysRegRead_1364a10a0c913d82 el op0 op1 CRn op2 CRm)" + by (unfold PMCEID0_EL0_SysRegRead_1364a10a0c913d82_def, non_mem_expI) + +lemma non_mem_exp_PMCEID1_EL0_SysRegRead_2db7a3b96735d30a[non_mem_expI]: + "non_mem_exp (PMCEID1_EL0_SysRegRead_2db7a3b96735d30a el op0 op1 CRn op2 CRm)" + by (unfold PMCEID1_EL0_SysRegRead_2db7a3b96735d30a_def, non_mem_expI) + +lemma non_mem_exp_PMCNTENCLR_EL0_SysRegRead_5ac431b885c9c5e4[non_mem_expI]: + "non_mem_exp (PMCNTENCLR_EL0_SysRegRead_5ac431b885c9c5e4 el op0 op1 CRn op2 CRm)" + by (unfold PMCNTENCLR_EL0_SysRegRead_5ac431b885c9c5e4_def, non_mem_expI) + +lemma non_mem_exp_PMCNTENSET_EL0_SysRegRead_848c3aa603193fb7[non_mem_expI]: + "non_mem_exp (PMCNTENSET_EL0_SysRegRead_848c3aa603193fb7 el op0 op1 CRn op2 CRm)" + by (unfold PMCNTENSET_EL0_SysRegRead_848c3aa603193fb7_def, non_mem_expI) + +lemma non_mem_exp_PMCR_EL0_SysRegRead_9a03e454327a1718[non_mem_expI]: + "non_mem_exp (PMCR_EL0_SysRegRead_9a03e454327a1718 el op0 op1 CRn op2 CRm)" + by (unfold PMCR_EL0_SysRegRead_9a03e454327a1718_def, non_mem_expI) + +lemma non_mem_exp_PMEVCNTR_EL0_SysRegRead_e0380ad70bc25a0c[non_mem_expI]: + "non_mem_exp (PMEVCNTR_EL0_SysRegRead_e0380ad70bc25a0c el op0 op1 CRn op2 CRm)" + by (unfold PMEVCNTR_EL0_SysRegRead_e0380ad70bc25a0c_def, non_mem_expI) + +lemma non_mem_exp_PMEVTYPER_EL0_SysRegRead_b05172ff9d10dad4[non_mem_expI]: + "non_mem_exp (PMEVTYPER_EL0_SysRegRead_b05172ff9d10dad4 el op0 op1 CRn op2 CRm)" + by (unfold PMEVTYPER_EL0_SysRegRead_b05172ff9d10dad4_def, non_mem_expI) + +lemma non_mem_exp_PMINTENCLR_EL1_SysRegRead_43b8f4d9b40b2620[non_mem_expI]: + "non_mem_exp (PMINTENCLR_EL1_SysRegRead_43b8f4d9b40b2620 el op0 op1 CRn op2 CRm)" + by (unfold PMINTENCLR_EL1_SysRegRead_43b8f4d9b40b2620_def, non_mem_expI) + +lemma non_mem_exp_PMINTENSET_EL1_SysRegRead_a3d4464c2051ff23[non_mem_expI]: + "non_mem_exp (PMINTENSET_EL1_SysRegRead_a3d4464c2051ff23 el op0 op1 CRn op2 CRm)" + by (unfold PMINTENSET_EL1_SysRegRead_a3d4464c2051ff23_def, non_mem_expI) + +lemma non_mem_exp_PMOVSCLR_EL0_SysRegRead_300e5dfb491e58fa[non_mem_expI]: + "non_mem_exp (PMOVSCLR_EL0_SysRegRead_300e5dfb491e58fa el op0 op1 CRn op2 CRm)" + by (unfold PMOVSCLR_EL0_SysRegRead_300e5dfb491e58fa_def, non_mem_expI) + +lemma non_mem_exp_PMOVSSET_EL0_SysRegRead_e3c0657a6c8b11c8[non_mem_expI]: + "non_mem_exp (PMOVSSET_EL0_SysRegRead_e3c0657a6c8b11c8 el op0 op1 CRn op2 CRm)" + by (unfold PMOVSSET_EL0_SysRegRead_e3c0657a6c8b11c8_def, non_mem_expI) + +lemma non_mem_exp_PMSCR_EL12_SysRegRead_624c386ea3cce853[non_mem_expI]: + "non_mem_exp (PMSCR_EL12_SysRegRead_624c386ea3cce853 el op0 op1 CRn op2 CRm)" + by (unfold PMSCR_EL12_SysRegRead_624c386ea3cce853_def, non_mem_expI) + +lemma non_mem_exp_PMSCR_EL1_SysRegRead_39ffc554ca37b155[non_mem_expI]: + "non_mem_exp (PMSCR_EL1_SysRegRead_39ffc554ca37b155 el op0 op1 CRn op2 CRm)" + by (unfold PMSCR_EL1_SysRegRead_39ffc554ca37b155_def, non_mem_expI) + +lemma non_mem_exp_PMSCR_EL2_SysRegRead_11330bd80566814a[non_mem_expI]: + "non_mem_exp (PMSCR_EL2_SysRegRead_11330bd80566814a el op0 op1 CRn op2 CRm)" + by (unfold PMSCR_EL2_SysRegRead_11330bd80566814a_def, non_mem_expI) + +lemma non_mem_exp_PMSELR_EL0_SysRegRead_540b592cb875b32f[non_mem_expI]: + "non_mem_exp (PMSELR_EL0_SysRegRead_540b592cb875b32f el op0 op1 CRn op2 CRm)" + by (unfold PMSELR_EL0_SysRegRead_540b592cb875b32f_def, non_mem_expI) + +lemma non_mem_exp_PMSEVFR_EL1_SysRegRead_9e9a58f73d629d59[non_mem_expI]: + "non_mem_exp (PMSEVFR_EL1_SysRegRead_9e9a58f73d629d59 el op0 op1 CRn op2 CRm)" + by (unfold PMSEVFR_EL1_SysRegRead_9e9a58f73d629d59_def, non_mem_expI) + +lemma non_mem_exp_PMSFCR_EL1_SysRegRead_30b07ff27088a488[non_mem_expI]: + "non_mem_exp (PMSFCR_EL1_SysRegRead_30b07ff27088a488 el op0 op1 CRn op2 CRm)" + by (unfold PMSFCR_EL1_SysRegRead_30b07ff27088a488_def, non_mem_expI) + +lemma non_mem_exp_PMSICR_EL1_SysRegRead_1b4bf4bb07470e4c[non_mem_expI]: + "non_mem_exp (PMSICR_EL1_SysRegRead_1b4bf4bb07470e4c el op0 op1 CRn op2 CRm)" + by (unfold PMSICR_EL1_SysRegRead_1b4bf4bb07470e4c_def, non_mem_expI) + +lemma non_mem_exp_PMSIDR_EL1_SysRegRead_062cecff79d24b4d[non_mem_expI]: + "non_mem_exp (PMSIDR_EL1_SysRegRead_062cecff79d24b4d el op0 op1 CRn op2 CRm)" + by (unfold PMSIDR_EL1_SysRegRead_062cecff79d24b4d_def, non_mem_expI) + +lemma non_mem_exp_PMSIRR_EL1_SysRegRead_b565329ce30ac491[non_mem_expI]: + "non_mem_exp (PMSIRR_EL1_SysRegRead_b565329ce30ac491 el op0 op1 CRn op2 CRm)" + by (unfold PMSIRR_EL1_SysRegRead_b565329ce30ac491_def, non_mem_expI) + +lemma non_mem_exp_PMSLATFR_EL1_SysRegRead_f82542fec2521a41[non_mem_expI]: + "non_mem_exp (PMSLATFR_EL1_SysRegRead_f82542fec2521a41 el op0 op1 CRn op2 CRm)" + by (unfold PMSLATFR_EL1_SysRegRead_f82542fec2521a41_def, non_mem_expI) + +lemma non_mem_exp_PMUSERENR_EL0_SysRegRead_7efca1a4be376eb7[non_mem_expI]: + "non_mem_exp (PMUSERENR_EL0_SysRegRead_7efca1a4be376eb7 el op0 op1 CRn op2 CRm)" + by (unfold PMUSERENR_EL0_SysRegRead_7efca1a4be376eb7_def, non_mem_expI) + +lemma non_mem_exp_PMXEVCNTR_EL0_SysRegRead_193921f886161922[non_mem_expI]: + "non_mem_exp (PMXEVCNTR_EL0_SysRegRead_193921f886161922 el op0 op1 CRn op2 CRm)" + by (unfold PMXEVCNTR_EL0_SysRegRead_193921f886161922_def, non_mem_expI) + +lemma non_mem_exp_PMXEVTYPER_EL0_SysRegRead_a34d7cb6f32074c5[non_mem_expI]: + "non_mem_exp (PMXEVTYPER_EL0_SysRegRead_a34d7cb6f32074c5 el op0 op1 CRn op2 CRm)" + by (unfold PMXEVTYPER_EL0_SysRegRead_a34d7cb6f32074c5_def, non_mem_expI) + +lemma non_mem_exp_REVIDR_EL1_SysRegRead_06ac796f098a1e84[non_mem_expI]: + "non_mem_exp (REVIDR_EL1_SysRegRead_06ac796f098a1e84 el op0 op1 CRn op2 CRm)" + by (unfold REVIDR_EL1_SysRegRead_06ac796f098a1e84_def, non_mem_expI) + +lemma non_mem_exp_RMR_EL1_SysRegRead_69f4933c1a574580[non_mem_expI]: + "non_mem_exp (RMR_EL1_SysRegRead_69f4933c1a574580 el op0 op1 CRn op2 CRm)" + by (unfold RMR_EL1_SysRegRead_69f4933c1a574580_def, non_mem_expI) + +lemma non_mem_exp_RMR_EL2_SysRegRead_75749340e0828f00[non_mem_expI]: + "non_mem_exp (RMR_EL2_SysRegRead_75749340e0828f00 el op0 op1 CRn op2 CRm)" + by (unfold RMR_EL2_SysRegRead_75749340e0828f00_def, non_mem_expI) + +lemma non_mem_exp_RMR_EL3_SysRegRead_fa5f18c3b20f8894[non_mem_expI]: + "non_mem_exp (RMR_EL3_SysRegRead_fa5f18c3b20f8894 el op0 op1 CRn op2 CRm)" + by (unfold RMR_EL3_SysRegRead_fa5f18c3b20f8894_def, non_mem_expI) + +lemma non_mem_exp_RSP_EL0_SysRegRead_b64c62bd96d973e3[non_mem_expI]: + "non_mem_exp (RSP_EL0_SysRegRead_b64c62bd96d973e3 el op0 op1 CRn op2 CRm)" + by (unfold RSP_EL0_SysRegRead_b64c62bd96d973e3_def, non_mem_expI) + +lemma non_mem_exp_RTPIDR_EL0_SysRegRead_0ce5a74dba936523[non_mem_expI]: + "non_mem_exp (RTPIDR_EL0_SysRegRead_0ce5a74dba936523 el op0 op1 CRn op2 CRm)" + by (unfold RTPIDR_EL0_SysRegRead_0ce5a74dba936523_def, non_mem_expI) + +lemma non_mem_exp_RVBAR_EL1_SysRegRead_48a958c9250293d1[non_mem_expI]: + "non_mem_exp (RVBAR_EL1_SysRegRead_48a958c9250293d1 el op0 op1 CRn op2 CRm)" + by (unfold RVBAR_EL1_SysRegRead_48a958c9250293d1_def, non_mem_expI) + +lemma non_mem_exp_RVBAR_EL2_SysRegRead_2fb802203150f4cc[non_mem_expI]: + "non_mem_exp (RVBAR_EL2_SysRegRead_2fb802203150f4cc el op0 op1 CRn op2 CRm)" + by (unfold RVBAR_EL2_SysRegRead_2fb802203150f4cc_def, non_mem_expI) + +lemma non_mem_exp_RVBAR_EL3_SysRegRead_000d1ea4b77ffa21[non_mem_expI]: + "non_mem_exp (RVBAR_EL3_SysRegRead_000d1ea4b77ffa21 el op0 op1 CRn op2 CRm)" + by (unfold RVBAR_EL3_SysRegRead_000d1ea4b77ffa21_def, non_mem_expI) + +lemma non_mem_exp_S3_op1_CCn_CCm_op2_SysRegRead_d72a7245384bbc0e[non_mem_expI]: + "non_mem_exp (S3_op1_CCn_CCm_op2_SysRegRead_d72a7245384bbc0e el op0 op1 CRn op2 CRm)" + by (unfold S3_op1_CCn_CCm_op2_SysRegRead_d72a7245384bbc0e_def, non_mem_expI) + +lemma non_mem_exp_SCR_EL3_SysRegRead_082a69b26890132d[non_mem_expI]: + "non_mem_exp (SCR_EL3_SysRegRead_082a69b26890132d el op0 op1 CRn op2 CRm)" + by (unfold SCR_EL3_SysRegRead_082a69b26890132d_def, non_mem_expI) + +lemma non_mem_exp_SCTLR_EL12_SysRegRead_81ba00bca4ce39dc[non_mem_expI]: + "non_mem_exp (SCTLR_EL12_SysRegRead_81ba00bca4ce39dc el op0 op1 CRn op2 CRm)" + by (unfold SCTLR_EL12_SysRegRead_81ba00bca4ce39dc_def, non_mem_expI) + +lemma non_mem_exp_SCTLR_EL1_SysRegRead_cc5fb072b0cb85eb[non_mem_expI]: + "non_mem_exp (SCTLR_EL1_SysRegRead_cc5fb072b0cb85eb el op0 op1 CRn op2 CRm)" + by (unfold SCTLR_EL1_SysRegRead_cc5fb072b0cb85eb_def, non_mem_expI) + +lemma non_mem_exp_SCTLR_EL2_SysRegRead_3cc208f3abf97e34[non_mem_expI]: + "non_mem_exp (SCTLR_EL2_SysRegRead_3cc208f3abf97e34 el op0 op1 CRn op2 CRm)" + by (unfold SCTLR_EL2_SysRegRead_3cc208f3abf97e34_def, non_mem_expI) + +lemma non_mem_exp_SCTLR_EL3_SysRegRead_9c537c9c01007c3e[non_mem_expI]: + "non_mem_exp (SCTLR_EL3_SysRegRead_9c537c9c01007c3e el op0 op1 CRn op2 CRm)" + by (unfold SCTLR_EL3_SysRegRead_9c537c9c01007c3e_def, non_mem_expI) + +lemma non_mem_exp_SCXTNUM_EL0_read[non_mem_expI]: + "non_mem_exp (SCXTNUM_EL0_read arg0)" + by (unfold SCXTNUM_EL0_read_def, non_mem_expI) + +lemma non_mem_exp_SCXTNUM_EL0_SysRegRead_ee5b769fc7f044cc[non_mem_expI]: + "non_mem_exp (SCXTNUM_EL0_SysRegRead_ee5b769fc7f044cc el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL0_SysRegRead_ee5b769fc7f044cc_def, non_mem_expI) + +lemma non_mem_exp_SCXTNUM_EL12_SysRegRead_d31f345333a78d48[non_mem_expI]: + "non_mem_exp (SCXTNUM_EL12_SysRegRead_d31f345333a78d48 el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL12_SysRegRead_d31f345333a78d48_def, non_mem_expI) + +lemma non_mem_exp_SCXTNUM_EL1_SysRegRead_dd27b7ad05ded1ab[non_mem_expI]: + "non_mem_exp (SCXTNUM_EL1_SysRegRead_dd27b7ad05ded1ab el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL1_SysRegRead_dd27b7ad05ded1ab_def, non_mem_expI) + +lemma non_mem_exp_SCXTNUM_EL2_SysRegRead_421b17f19f5fdd2a[non_mem_expI]: + "non_mem_exp (SCXTNUM_EL2_SysRegRead_421b17f19f5fdd2a el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL2_SysRegRead_421b17f19f5fdd2a_def, non_mem_expI) + +lemma non_mem_exp_SCXTNUM_EL3_SysRegRead_5f15a3b4da1bd4bb[non_mem_expI]: + "non_mem_exp (SCXTNUM_EL3_SysRegRead_5f15a3b4da1bd4bb el op0 op1 CRn op2 CRm)" + by (unfold SCXTNUM_EL3_SysRegRead_5f15a3b4da1bd4bb_def, non_mem_expI) + +lemma non_mem_exp_SDER32_EL3_SysRegRead_e21f871563c7e34e[non_mem_expI]: + "non_mem_exp (SDER32_EL3_SysRegRead_e21f871563c7e34e el op0 op1 CRn op2 CRm)" + by (unfold SDER32_EL3_SysRegRead_e21f871563c7e34e_def, non_mem_expI) + +lemma non_mem_exp_SPSel_SysRegRead_ac7632fd1580b15b[non_mem_expI]: + "non_mem_exp (SPSel_SysRegRead_ac7632fd1580b15b el op0 op1 CRn op2 CRm)" + by (unfold SPSel_SysRegRead_ac7632fd1580b15b_def, non_mem_expI) + +lemma non_mem_exp_SP_EL0_SysRegRead_4b07157e43cd0456[non_mem_expI]: + "non_mem_exp (SP_EL0_SysRegRead_4b07157e43cd0456 el op0 op1 CRn op2 CRm)" + by (unfold SP_EL0_SysRegRead_4b07157e43cd0456_def, non_mem_expI) + +lemma non_mem_exp_SP_EL1_SysRegRead_44ac23d2a7608550[non_mem_expI]: + "non_mem_exp (SP_EL1_SysRegRead_44ac23d2a7608550 el op0 op1 CRn op2 CRm)" + by (unfold SP_EL1_SysRegRead_44ac23d2a7608550_def, non_mem_expI) + +lemma non_mem_exp_SP_EL2_SysRegRead_9c4b7d596526b300[non_mem_expI]: + "non_mem_exp (SP_EL2_SysRegRead_9c4b7d596526b300 el op0 op1 CRn op2 CRm)" + by (unfold SP_EL2_SysRegRead_9c4b7d596526b300_def, non_mem_expI) + +lemma non_mem_exp_TCR_EL12_SysRegRead_cefcc3f131a70a7f[non_mem_expI]: + "non_mem_exp (TCR_EL12_SysRegRead_cefcc3f131a70a7f el op0 op1 CRn op2 CRm)" + by (unfold TCR_EL12_SysRegRead_cefcc3f131a70a7f_def, non_mem_expI) + +lemma non_mem_exp_TCR_EL1_SysRegRead_fbe255888fba9865[non_mem_expI]: + "non_mem_exp (TCR_EL1_SysRegRead_fbe255888fba9865 el op0 op1 CRn op2 CRm)" + by (unfold TCR_EL1_SysRegRead_fbe255888fba9865_def, non_mem_expI) + +lemma non_mem_exp_TCR_EL2_SysRegRead_3467687df9c2aec1[non_mem_expI]: + "non_mem_exp (TCR_EL2_SysRegRead_3467687df9c2aec1 el op0 op1 CRn op2 CRm)" + by (unfold TCR_EL2_SysRegRead_3467687df9c2aec1_def, non_mem_expI) + +lemma non_mem_exp_TCR_EL3_SysRegRead_7da88d4a232f9451[non_mem_expI]: + "non_mem_exp (TCR_EL3_SysRegRead_7da88d4a232f9451 el op0 op1 CRn op2 CRm)" + by (unfold TCR_EL3_SysRegRead_7da88d4a232f9451_def, non_mem_expI) + +lemma non_mem_exp_TPIDRRO_EL0_SysRegRead_3dc5dc323922fcfa[non_mem_expI]: + "non_mem_exp (TPIDRRO_EL0_SysRegRead_3dc5dc323922fcfa el op0 op1 CRn op2 CRm)" + by (unfold TPIDRRO_EL0_SysRegRead_3dc5dc323922fcfa_def, non_mem_expI) + +lemma non_mem_exp_TPIDR_EL0_SysRegRead_7b944c4fc3d3f60f[non_mem_expI]: + "non_mem_exp (TPIDR_EL0_SysRegRead_7b944c4fc3d3f60f el op0 op1 CRn op2 CRm)" + by (unfold TPIDR_EL0_SysRegRead_7b944c4fc3d3f60f_def, non_mem_expI) + +lemma non_mem_exp_TPIDR_EL1_SysRegRead_8db91ea8b9abc411[non_mem_expI]: + "non_mem_exp (TPIDR_EL1_SysRegRead_8db91ea8b9abc411 el op0 op1 CRn op2 CRm)" + by (unfold TPIDR_EL1_SysRegRead_8db91ea8b9abc411_def, non_mem_expI) + +lemma non_mem_exp_TPIDR_EL2_SysRegRead_fc4633f7449b5b4a[non_mem_expI]: + "non_mem_exp (TPIDR_EL2_SysRegRead_fc4633f7449b5b4a el op0 op1 CRn op2 CRm)" + by (unfold TPIDR_EL2_SysRegRead_fc4633f7449b5b4a_def, non_mem_expI) + +lemma non_mem_exp_TPIDR_EL3_SysRegRead_c6069d62b310a137[non_mem_expI]: + "non_mem_exp (TPIDR_EL3_SysRegRead_c6069d62b310a137 el op0 op1 CRn op2 CRm)" + by (unfold TPIDR_EL3_SysRegRead_c6069d62b310a137_def, non_mem_expI) + +lemma non_mem_exp_TTBR0_EL12_SysRegRead_73f9bd4d027badee[non_mem_expI]: + "non_mem_exp (TTBR0_EL12_SysRegRead_73f9bd4d027badee el op0 op1 CRn op2 CRm)" + by (unfold TTBR0_EL12_SysRegRead_73f9bd4d027badee_def, non_mem_expI) + +lemma non_mem_exp_TTBR0_EL1_SysRegRead_2e8a6c25b2e4759a[non_mem_expI]: + "non_mem_exp (TTBR0_EL1_SysRegRead_2e8a6c25b2e4759a el op0 op1 CRn op2 CRm)" + by (unfold TTBR0_EL1_SysRegRead_2e8a6c25b2e4759a_def, non_mem_expI) + +lemma non_mem_exp_TTBR0_EL2_SysRegRead_8d4de9e080477354[non_mem_expI]: + "non_mem_exp (TTBR0_EL2_SysRegRead_8d4de9e080477354 el op0 op1 CRn op2 CRm)" + by (unfold TTBR0_EL2_SysRegRead_8d4de9e080477354_def, non_mem_expI) + +lemma non_mem_exp_TTBR0_EL3_SysRegRead_a46e35edfe45a273[non_mem_expI]: + "non_mem_exp (TTBR0_EL3_SysRegRead_a46e35edfe45a273 el op0 op1 CRn op2 CRm)" + by (unfold TTBR0_EL3_SysRegRead_a46e35edfe45a273_def, non_mem_expI) + +lemma non_mem_exp_TTBR1_EL12_SysRegRead_bfbc2899eb278d2b[non_mem_expI]: + "non_mem_exp (TTBR1_EL12_SysRegRead_bfbc2899eb278d2b el op0 op1 CRn op2 CRm)" + by (unfold TTBR1_EL12_SysRegRead_bfbc2899eb278d2b_def, non_mem_expI) + +lemma non_mem_exp_TTBR1_EL1_SysRegRead_2cb2fb59089165c5[non_mem_expI]: + "non_mem_exp (TTBR1_EL1_SysRegRead_2cb2fb59089165c5 el op0 op1 CRn op2 CRm)" + by (unfold TTBR1_EL1_SysRegRead_2cb2fb59089165c5_def, non_mem_expI) + +lemma non_mem_exp_TTBR1_EL2_SysRegRead_08cd28a9b17bc317[non_mem_expI]: + "non_mem_exp (TTBR1_EL2_SysRegRead_08cd28a9b17bc317 el op0 op1 CRn op2 CRm)" + by (unfold TTBR1_EL2_SysRegRead_08cd28a9b17bc317_def, non_mem_expI) + +lemma non_mem_exp_VBAR_EL12_SysRegRead_2ad4e02fbe99cf3d[non_mem_expI]: + "non_mem_exp (VBAR_EL12_SysRegRead_2ad4e02fbe99cf3d el op0 op1 CRn op2 CRm)" + by (unfold VBAR_EL12_SysRegRead_2ad4e02fbe99cf3d_def, non_mem_expI) + +lemma non_mem_exp_VBAR_EL1_SysRegRead_4d14cb3b6fe16ab6[non_mem_expI]: + "non_mem_exp (VBAR_EL1_SysRegRead_4d14cb3b6fe16ab6 el op0 op1 CRn op2 CRm)" + by (unfold VBAR_EL1_SysRegRead_4d14cb3b6fe16ab6_def, non_mem_expI) + +lemma non_mem_exp_VBAR_EL2_SysRegRead_1f6b3c94ccfecacf[non_mem_expI]: + "non_mem_exp (VBAR_EL2_SysRegRead_1f6b3c94ccfecacf el op0 op1 CRn op2 CRm)" + by (unfold VBAR_EL2_SysRegRead_1f6b3c94ccfecacf_def, non_mem_expI) + +lemma non_mem_exp_VBAR_EL3_SysRegRead_32f42cb574998654[non_mem_expI]: + "non_mem_exp (VBAR_EL3_SysRegRead_32f42cb574998654 el op0 op1 CRn op2 CRm)" + by (unfold VBAR_EL3_SysRegRead_32f42cb574998654_def, non_mem_expI) + +lemma non_mem_exp_VDISR_EL2_SysRegRead_14dff4ad4ae8c3a2[non_mem_expI]: + "non_mem_exp (VDISR_EL2_SysRegRead_14dff4ad4ae8c3a2 el op0 op1 CRn op2 CRm)" + by (unfold VDISR_EL2_SysRegRead_14dff4ad4ae8c3a2_def, non_mem_expI) + +lemma non_mem_exp_VMPIDR_EL2_SysRegRead_49b7c13dd1b0804c[non_mem_expI]: + "non_mem_exp (VMPIDR_EL2_SysRegRead_49b7c13dd1b0804c el op0 op1 CRn op2 CRm)" + by (unfold VMPIDR_EL2_SysRegRead_49b7c13dd1b0804c_def, non_mem_expI) + +lemma non_mem_exp_VPIDR_EL2_SysRegRead_f6520cd6a1f62bd8[non_mem_expI]: + "non_mem_exp (VPIDR_EL2_SysRegRead_f6520cd6a1f62bd8 el op0 op1 CRn op2 CRm)" + by (unfold VPIDR_EL2_SysRegRead_f6520cd6a1f62bd8_def, non_mem_expI) + +lemma non_mem_exp_VSESR_EL2_SysRegRead_401c063e57574698[non_mem_expI]: + "non_mem_exp (VSESR_EL2_SysRegRead_401c063e57574698 el op0 op1 CRn op2 CRm)" + by (unfold VSESR_EL2_SysRegRead_401c063e57574698_def, non_mem_expI) + +lemma non_mem_exp_VTCR_EL2_SysRegRead_5c8ea980dc5cc1d1[non_mem_expI]: + "non_mem_exp (VTCR_EL2_SysRegRead_5c8ea980dc5cc1d1 el op0 op1 CRn op2 CRm)" + by (unfold VTCR_EL2_SysRegRead_5c8ea980dc5cc1d1_def, non_mem_expI) + +lemma non_mem_exp_VTTBR_EL2_SysRegRead_2fbbdccc9485564d[non_mem_expI]: + "non_mem_exp (VTTBR_EL2_SysRegRead_2fbbdccc9485564d el op0 op1 CRn op2 CRm)" + by (unfold VTTBR_EL2_SysRegRead_2fbbdccc9485564d_def, non_mem_expI) + +lemma non_mem_exp_AArch64_AutoGen_SysRegRead[non_mem_expI]: + "non_mem_exp (AArch64_AutoGen_SysRegRead el op0 op1 CRn op2 CRm)" + by (unfold AArch64_AutoGen_SysRegRead_def, non_mem_expI) + +lemma non_mem_exp_AArch64_SysRegRead[non_mem_expI]: + "non_mem_exp (AArch64_SysRegRead op0 op1 crn crm op2)" + by (unfold AArch64_SysRegRead_def, non_mem_expI) + +lemma non_mem_exp_CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34[non_mem_expI]: + "non_mem_exp (CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34 el op0 op1 CRn op2 CRm)" + by (unfold CDBGDTR_EL0_CapSysRegRead_8e23daae0e60af34_def, non_mem_expI) + +lemma non_mem_exp_CDLR_EL0_CapSysRegRead_619c852c71c0978d[non_mem_expI]: + "non_mem_exp (CDLR_EL0_CapSysRegRead_619c852c71c0978d el op0 op1 CRn op2 CRm)" + by (unfold CDLR_EL0_CapSysRegRead_619c852c71c0978d_def, non_mem_expI) + +lemma non_mem_exp_CELR_EL12_CapSysRegRead_4bf271777fe55d1c[non_mem_expI]: + "non_mem_exp (CELR_EL12_CapSysRegRead_4bf271777fe55d1c el op0 op1 CRn op2 CRm)" + by (unfold CELR_EL12_CapSysRegRead_4bf271777fe55d1c_def, non_mem_expI) + +lemma non_mem_exp_CELR_EL1_CapSysRegRead_da9869d2314a30d5[non_mem_expI]: + "non_mem_exp (CELR_EL1_CapSysRegRead_da9869d2314a30d5 el op0 op1 CRn op2 CRm)" + by (unfold CELR_EL1_CapSysRegRead_da9869d2314a30d5_def, non_mem_expI) + +lemma non_mem_exp_CELR_EL2_CapSysRegRead_a9e9661da428a6d4[non_mem_expI]: + "non_mem_exp (CELR_EL2_CapSysRegRead_a9e9661da428a6d4 el op0 op1 CRn op2 CRm)" + by (unfold CELR_EL2_CapSysRegRead_a9e9661da428a6d4_def, non_mem_expI) + +lemma non_mem_exp_CELR_EL3_CapSysRegRead_d0424a232c45967e[non_mem_expI]: + "non_mem_exp (CELR_EL3_CapSysRegRead_d0424a232c45967e el op0 op1 CRn op2 CRm)" + by (unfold CELR_EL3_CapSysRegRead_d0424a232c45967e_def, non_mem_expI) + +lemma non_mem_exp_CID_EL0_CapSysRegRead_d560f6b1104266f1[non_mem_expI]: + "non_mem_exp (CID_EL0_CapSysRegRead_d560f6b1104266f1 el op0 op1 CRn op2 CRm)" + by (unfold CID_EL0_CapSysRegRead_d560f6b1104266f1_def, non_mem_expI) + +lemma non_mem_exp_CSP_EL0_CapSysRegRead_e5b1ba121f8be4da[non_mem_expI]: + "non_mem_exp (CSP_EL0_CapSysRegRead_e5b1ba121f8be4da el op0 op1 CRn op2 CRm)" + by (unfold CSP_EL0_CapSysRegRead_e5b1ba121f8be4da_def, non_mem_expI) + +lemma non_mem_exp_CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb[non_mem_expI]: + "non_mem_exp (CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb el op0 op1 CRn op2 CRm)" + by (unfold CSP_EL1_CapSysRegRead_bb8b6c0ba689eafb_def, non_mem_expI) + +lemma non_mem_exp_CSP_EL2_CapSysRegRead_9b50d2f92d5520da[non_mem_expI]: + "non_mem_exp (CSP_EL2_CapSysRegRead_9b50d2f92d5520da el op0 op1 CRn op2 CRm)" + by (unfold CSP_EL2_CapSysRegRead_9b50d2f92d5520da_def, non_mem_expI) + +lemma non_mem_exp_CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc[non_mem_expI]: + "non_mem_exp (CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc el op0 op1 CRn op2 CRm)" + by (unfold CTPIDRRO_EL0_CapSysRegRead_2def4a85803ae7cc_def, non_mem_expI) + +lemma non_mem_exp_CTPIDR_EL0_CapSysRegRead_84b933ea55a77369[non_mem_expI]: + "non_mem_exp (CTPIDR_EL0_CapSysRegRead_84b933ea55a77369 el op0 op1 CRn op2 CRm)" + by (unfold CTPIDR_EL0_CapSysRegRead_84b933ea55a77369_def, non_mem_expI) + +lemma non_mem_exp_CTPIDR_EL1_CapSysRegRead_016308c12b886084[non_mem_expI]: + "non_mem_exp (CTPIDR_EL1_CapSysRegRead_016308c12b886084 el op0 op1 CRn op2 CRm)" + by (unfold CTPIDR_EL1_CapSysRegRead_016308c12b886084_def, non_mem_expI) + +lemma non_mem_exp_CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544[non_mem_expI]: + "non_mem_exp (CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544 el op0 op1 CRn op2 CRm)" + by (unfold CTPIDR_EL2_CapSysRegRead_b7d4714a1ce62544_def, non_mem_expI) + +lemma non_mem_exp_CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449[non_mem_expI]: + "non_mem_exp (CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449 el op0 op1 CRn op2 CRm)" + by (unfold CTPIDR_EL3_CapSysRegRead_c1307a9bc7bc1449_def, non_mem_expI) + +lemma non_mem_exp_CVBAR_EL12_CapSysRegRead_845c94ac498ff593[non_mem_expI]: + "non_mem_exp (CVBAR_EL12_CapSysRegRead_845c94ac498ff593 el op0 op1 CRn op2 CRm)" + by (unfold CVBAR_EL12_CapSysRegRead_845c94ac498ff593_def, non_mem_expI) + +lemma non_mem_exp_CVBAR_EL1_CapSysRegRead_c42109445741a0d0[non_mem_expI]: + "non_mem_exp (CVBAR_EL1_CapSysRegRead_c42109445741a0d0 el op0 op1 CRn op2 CRm)" + by (unfold CVBAR_EL1_CapSysRegRead_c42109445741a0d0_def, non_mem_expI) + +lemma non_mem_exp_CVBAR_EL2_CapSysRegRead_537232bbd7d69e00[non_mem_expI]: + "non_mem_exp (CVBAR_EL2_CapSysRegRead_537232bbd7d69e00 el op0 op1 CRn op2 CRm)" + by (unfold CVBAR_EL2_CapSysRegRead_537232bbd7d69e00_def, non_mem_expI) + +lemma non_mem_exp_CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1[non_mem_expI]: + "non_mem_exp (CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1 el op0 op1 CRn op2 CRm)" + by (unfold CVBAR_EL3_CapSysRegRead_587d4a028f8f0ef1_def, non_mem_expI) + +lemma non_mem_exp_DDC_CapSysRegRead_eabc4ea34a10a962[non_mem_expI]: + "non_mem_exp (DDC_CapSysRegRead_eabc4ea34a10a962 el op0 op1 CRn op2 CRm)" + by (unfold DDC_CapSysRegRead_eabc4ea34a10a962_def, non_mem_expI) + +lemma non_mem_exp_DDC_EL0_CapSysRegRead_e02bc676dce7fb51[non_mem_expI]: + "non_mem_exp (DDC_EL0_CapSysRegRead_e02bc676dce7fb51 el op0 op1 CRn op2 CRm)" + by (unfold DDC_EL0_CapSysRegRead_e02bc676dce7fb51_def, non_mem_expI) + +lemma non_mem_exp_DDC_EL1_CapSysRegRead_08f46354e9afc01e[non_mem_expI]: + "non_mem_exp (DDC_EL1_CapSysRegRead_08f46354e9afc01e el op0 op1 CRn op2 CRm)" + by (unfold DDC_EL1_CapSysRegRead_08f46354e9afc01e_def, non_mem_expI) + +lemma non_mem_exp_DDC_EL2_CapSysRegRead_6d2409222a719403[non_mem_expI]: + "non_mem_exp (DDC_EL2_CapSysRegRead_6d2409222a719403 el op0 op1 CRn op2 CRm)" + by (unfold DDC_EL2_CapSysRegRead_6d2409222a719403_def, non_mem_expI) + +lemma non_mem_exp_RCSP_EL0_CapSysRegRead_6a9b29b9027548c3[non_mem_expI]: + "non_mem_exp (RCSP_EL0_CapSysRegRead_6a9b29b9027548c3 el op0 op1 CRn op2 CRm)" + by (unfold RCSP_EL0_CapSysRegRead_6a9b29b9027548c3_def, non_mem_expI) + +lemma non_mem_exp_RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7[non_mem_expI]: + "non_mem_exp (RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7 el op0 op1 CRn op2 CRm)" + by (unfold RCTPIDR_EL0_CapSysRegRead_0a3ce9d2144ddba7_def, non_mem_expI) + +lemma non_mem_exp_RDDC_EL0_CapSysRegRead_c188e736aa7b9beb[non_mem_expI]: + "non_mem_exp (RDDC_EL0_CapSysRegRead_c188e736aa7b9beb el op0 op1 CRn op2 CRm)" + by (unfold RDDC_EL0_CapSysRegRead_c188e736aa7b9beb_def, non_mem_expI) + +lemma non_mem_exp_AArch64_AutoGen_CapSysRegRead[non_mem_expI]: + "non_mem_exp (AArch64_AutoGen_CapSysRegRead el op0 op1 CRn op2 CRm)" + by (unfold AArch64_AutoGen_CapSysRegRead_def, non_mem_expI) + +lemma non_mem_exp_DDC_read[non_mem_expI]: + "non_mem_exp (DDC_read arg0)" + by (unfold DDC_read_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CapSysRegRead[non_mem_expI]: + "non_mem_exp (AArch64_CapSysRegRead op0 op1 crn crm op2)" + by (unfold AArch64_CapSysRegRead_def, non_mem_expI) + +lemma non_mem_exp_ACTLR_EL1_SysRegWrite_338051dbe9bdf650[non_mem_expI]: + "non_mem_exp (ACTLR_EL1_SysRegWrite_338051dbe9bdf650 el op0 op1 CRn op2 CRm val_name)" + by (unfold ACTLR_EL1_SysRegWrite_338051dbe9bdf650_def, non_mem_expI) + +lemma non_mem_exp_ACTLR_EL2_SysRegWrite_416ec7c6fadd122d[non_mem_expI]: + "non_mem_exp (ACTLR_EL2_SysRegWrite_416ec7c6fadd122d el op0 op1 CRn op2 CRm val_name)" + by (unfold ACTLR_EL2_SysRegWrite_416ec7c6fadd122d_def, non_mem_expI) + +lemma non_mem_exp_ACTLR_EL3_SysRegWrite_c797d5a80525afa4[non_mem_expI]: + "non_mem_exp (ACTLR_EL3_SysRegWrite_c797d5a80525afa4 el op0 op1 CRn op2 CRm val_name)" + by (unfold ACTLR_EL3_SysRegWrite_c797d5a80525afa4_def, non_mem_expI) + +lemma non_mem_exp_AFSR0_EL12_SysRegWrite_9fafb4f6dbddd904[non_mem_expI]: + "non_mem_exp (AFSR0_EL12_SysRegWrite_9fafb4f6dbddd904 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR0_EL12_SysRegWrite_9fafb4f6dbddd904_def, non_mem_expI) + +lemma non_mem_exp_AFSR0_EL1_SysRegWrite_04474930979e1c86[non_mem_expI]: + "non_mem_exp (AFSR0_EL1_SysRegWrite_04474930979e1c86 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR0_EL1_SysRegWrite_04474930979e1c86_def, non_mem_expI) + +lemma non_mem_exp_AFSR0_EL2_SysRegWrite_2f9da4789f5b4073[non_mem_expI]: + "non_mem_exp (AFSR0_EL2_SysRegWrite_2f9da4789f5b4073 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR0_EL2_SysRegWrite_2f9da4789f5b4073_def, non_mem_expI) + +lemma non_mem_exp_AFSR0_EL3_SysRegWrite_e615501306210a25[non_mem_expI]: + "non_mem_exp (AFSR0_EL3_SysRegWrite_e615501306210a25 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR0_EL3_SysRegWrite_e615501306210a25_def, non_mem_expI) + +lemma non_mem_exp_AFSR1_EL12_SysRegWrite_9dbf207cccd92d9d[non_mem_expI]: + "non_mem_exp (AFSR1_EL12_SysRegWrite_9dbf207cccd92d9d el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR1_EL12_SysRegWrite_9dbf207cccd92d9d_def, non_mem_expI) + +lemma non_mem_exp_AFSR1_EL1_SysRegWrite_6690138c9fdd136c[non_mem_expI]: + "non_mem_exp (AFSR1_EL1_SysRegWrite_6690138c9fdd136c el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR1_EL1_SysRegWrite_6690138c9fdd136c_def, non_mem_expI) + +lemma non_mem_exp_AFSR1_EL2_SysRegWrite_c0ebc4cc65472544[non_mem_expI]: + "non_mem_exp (AFSR1_EL2_SysRegWrite_c0ebc4cc65472544 el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR1_EL2_SysRegWrite_c0ebc4cc65472544_def, non_mem_expI) + +lemma non_mem_exp_AFSR1_EL3_SysRegWrite_d776cc264803f49e[non_mem_expI]: + "non_mem_exp (AFSR1_EL3_SysRegWrite_d776cc264803f49e el op0 op1 CRn op2 CRm val_name)" + by (unfold AFSR1_EL3_SysRegWrite_d776cc264803f49e_def, non_mem_expI) + +lemma non_mem_exp_AMAIR_EL12_SysRegWrite_9c44aba2de7c2ff8[non_mem_expI]: + "non_mem_exp (AMAIR_EL12_SysRegWrite_9c44aba2de7c2ff8 el op0 op1 CRn op2 CRm val_name)" + by (unfold AMAIR_EL12_SysRegWrite_9c44aba2de7c2ff8_def, non_mem_expI) + +lemma non_mem_exp_AMAIR_EL1_SysRegWrite_0d9c3d92d9a71703[non_mem_expI]: + "non_mem_exp (AMAIR_EL1_SysRegWrite_0d9c3d92d9a71703 el op0 op1 CRn op2 CRm val_name)" + by (unfold AMAIR_EL1_SysRegWrite_0d9c3d92d9a71703_def, non_mem_expI) + +lemma non_mem_exp_AMAIR_EL2_SysRegWrite_9345da970d78b298[non_mem_expI]: + "non_mem_exp (AMAIR_EL2_SysRegWrite_9345da970d78b298 el op0 op1 CRn op2 CRm val_name)" + by (unfold AMAIR_EL2_SysRegWrite_9345da970d78b298_def, non_mem_expI) + +lemma non_mem_exp_AMAIR_EL3_SysRegWrite_622c473bfedac80a[non_mem_expI]: + "non_mem_exp (AMAIR_EL3_SysRegWrite_622c473bfedac80a el op0 op1 CRn op2 CRm val_name)" + by (unfold AMAIR_EL3_SysRegWrite_622c473bfedac80a_def, non_mem_expI) + +lemma non_mem_exp_CCTLR_EL0_SysRegWrite_a4d8c57cb436292b[non_mem_expI]: + "non_mem_exp (CCTLR_EL0_SysRegWrite_a4d8c57cb436292b el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL0_SysRegWrite_a4d8c57cb436292b_def, non_mem_expI) + +lemma non_mem_exp_CCTLR_EL12_SysRegWrite_c7d9d6463096d910[non_mem_expI]: + "non_mem_exp (CCTLR_EL12_SysRegWrite_c7d9d6463096d910 el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL12_SysRegWrite_c7d9d6463096d910_def, non_mem_expI) + +lemma non_mem_exp_CCTLR_EL1_SysRegWrite_dc20ad2a867ac9bf[non_mem_expI]: + "non_mem_exp (CCTLR_EL1_SysRegWrite_dc20ad2a867ac9bf el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL1_SysRegWrite_dc20ad2a867ac9bf_def, non_mem_expI) + +lemma non_mem_exp_CCTLR_EL2_SysRegWrite_65620c8ccb1113a5[non_mem_expI]: + "non_mem_exp (CCTLR_EL2_SysRegWrite_65620c8ccb1113a5 el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL2_SysRegWrite_65620c8ccb1113a5_def, non_mem_expI) + +lemma non_mem_exp_CCTLR_EL3_SysRegWrite_f5e936c8846e6fc7[non_mem_expI]: + "non_mem_exp (CCTLR_EL3_SysRegWrite_f5e936c8846e6fc7 el op0 op1 CRn op2 CRm val_name)" + by (unfold CCTLR_EL3_SysRegWrite_f5e936c8846e6fc7_def, non_mem_expI) + +lemma non_mem_exp_CHCR_EL2_SysRegWrite_dadda8ecf053e448[non_mem_expI]: + "non_mem_exp (CHCR_EL2_SysRegWrite_dadda8ecf053e448 el op0 op1 CRn op2 CRm val_name)" + by (unfold CHCR_EL2_SysRegWrite_dadda8ecf053e448_def, non_mem_expI) + +lemma non_mem_exp_CNTFRQ_EL0_SysRegWrite_0fac77f077759456[non_mem_expI]: + "non_mem_exp (CNTFRQ_EL0_SysRegWrite_0fac77f077759456 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTFRQ_EL0_SysRegWrite_0fac77f077759456_def, non_mem_expI) + +lemma non_mem_exp_CNTHCTL_EL2_SysRegWrite_eb0cbec9f9398e0e[non_mem_expI]: + "non_mem_exp (CNTHCTL_EL2_SysRegWrite_eb0cbec9f9398e0e el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHCTL_EL2_SysRegWrite_eb0cbec9f9398e0e_def, non_mem_expI) + +lemma non_mem_exp_CNTHP_CTL_EL2_SysRegWrite_92034fc54290a7b8[non_mem_expI]: + "non_mem_exp (CNTHP_CTL_EL2_SysRegWrite_92034fc54290a7b8 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHP_CTL_EL2_SysRegWrite_92034fc54290a7b8_def, non_mem_expI) + +lemma non_mem_exp_CNTHP_CVAL_EL2_SysRegWrite_36de219faded7cbc[non_mem_expI]: + "non_mem_exp (CNTHP_CVAL_EL2_SysRegWrite_36de219faded7cbc el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHP_CVAL_EL2_SysRegWrite_36de219faded7cbc_def, non_mem_expI) + +lemma non_mem_exp_CNTHP_TVAL_EL2_SysRegWrite_877bbf4f78f810b9[non_mem_expI]: + "non_mem_exp (CNTHP_TVAL_EL2_SysRegWrite_877bbf4f78f810b9 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHP_TVAL_EL2_SysRegWrite_877bbf4f78f810b9_def, non_mem_expI) + +lemma non_mem_exp_CNTHV_CTL_EL2_SysRegWrite_ecc786a588fc8ab9[non_mem_expI]: + "non_mem_exp (CNTHV_CTL_EL2_SysRegWrite_ecc786a588fc8ab9 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHV_CTL_EL2_SysRegWrite_ecc786a588fc8ab9_def, non_mem_expI) + +lemma non_mem_exp_CNTHV_CVAL_EL2_SysRegWrite_b3d7c631e2b3eaab[non_mem_expI]: + "non_mem_exp (CNTHV_CVAL_EL2_SysRegWrite_b3d7c631e2b3eaab el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHV_CVAL_EL2_SysRegWrite_b3d7c631e2b3eaab_def, non_mem_expI) + +lemma non_mem_exp_CNTHV_TVAL_EL2_SysRegWrite_e215d12d330397f1[non_mem_expI]: + "non_mem_exp (CNTHV_TVAL_EL2_SysRegWrite_e215d12d330397f1 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTHV_TVAL_EL2_SysRegWrite_e215d12d330397f1_def, non_mem_expI) + +lemma non_mem_exp_CNTKCTL_EL12_SysRegWrite_518123f17a6402e4[non_mem_expI]: + "non_mem_exp (CNTKCTL_EL12_SysRegWrite_518123f17a6402e4 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTKCTL_EL12_SysRegWrite_518123f17a6402e4_def, non_mem_expI) + +lemma non_mem_exp_CNTKCTL_EL1_SysRegWrite_9a7be69aa33bb9c2[non_mem_expI]: + "non_mem_exp (CNTKCTL_EL1_SysRegWrite_9a7be69aa33bb9c2 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTKCTL_EL1_SysRegWrite_9a7be69aa33bb9c2_def, non_mem_expI) + +lemma non_mem_exp_CNTPS_CTL_EL1_SysRegWrite_a0625fd9f7b035a8[non_mem_expI]: + "non_mem_exp (CNTPS_CTL_EL1_SysRegWrite_a0625fd9f7b035a8 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTPS_CTL_EL1_SysRegWrite_a0625fd9f7b035a8_def, non_mem_expI) + +lemma non_mem_exp_CNTPS_CVAL_EL1_SysRegWrite_f09243080b7c260d[non_mem_expI]: + "non_mem_exp (CNTPS_CVAL_EL1_SysRegWrite_f09243080b7c260d el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTPS_CVAL_EL1_SysRegWrite_f09243080b7c260d_def, non_mem_expI) + +lemma non_mem_exp_CNTPS_TVAL_EL1_SysRegWrite_a9b16e60037fa746[non_mem_expI]: + "non_mem_exp (CNTPS_TVAL_EL1_SysRegWrite_a9b16e60037fa746 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTPS_TVAL_EL1_SysRegWrite_a9b16e60037fa746_def, non_mem_expI) + +lemma non_mem_exp_CNTP_CTL_EL02_SysRegWrite_99a9da3e2454714e[non_mem_expI]: + "non_mem_exp (CNTP_CTL_EL02_SysRegWrite_99a9da3e2454714e el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_CTL_EL02_SysRegWrite_99a9da3e2454714e_def, non_mem_expI) + +lemma non_mem_exp_CNTP_CTL_EL0_SysRegWrite_137f81090c1357e6[non_mem_expI]: + "non_mem_exp (CNTP_CTL_EL0_SysRegWrite_137f81090c1357e6 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_CTL_EL0_SysRegWrite_137f81090c1357e6_def, non_mem_expI) + +lemma non_mem_exp_CNTP_CVAL_EL02_SysRegWrite_2b3e9ccfce186a4f[non_mem_expI]: + "non_mem_exp (CNTP_CVAL_EL02_SysRegWrite_2b3e9ccfce186a4f el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_CVAL_EL02_SysRegWrite_2b3e9ccfce186a4f_def, non_mem_expI) + +lemma non_mem_exp_CNTP_CVAL_EL0_SysRegWrite_d54c08ee0cf9aaf7[non_mem_expI]: + "non_mem_exp (CNTP_CVAL_EL0_SysRegWrite_d54c08ee0cf9aaf7 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_CVAL_EL0_SysRegWrite_d54c08ee0cf9aaf7_def, non_mem_expI) + +lemma non_mem_exp_CNTP_TVAL_EL02_SysRegWrite_caa9f2aa73cb6b96[non_mem_expI]: + "non_mem_exp (CNTP_TVAL_EL02_SysRegWrite_caa9f2aa73cb6b96 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_TVAL_EL02_SysRegWrite_caa9f2aa73cb6b96_def, non_mem_expI) + +lemma non_mem_exp_CNTP_TVAL_EL0_SysRegWrite_d7441eec23c3d524[non_mem_expI]: + "non_mem_exp (CNTP_TVAL_EL0_SysRegWrite_d7441eec23c3d524 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTP_TVAL_EL0_SysRegWrite_d7441eec23c3d524_def, non_mem_expI) + +lemma non_mem_exp_CNTVOFF_EL2_SysRegWrite_621ada4cfda60bcb[non_mem_expI]: + "non_mem_exp (CNTVOFF_EL2_SysRegWrite_621ada4cfda60bcb el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTVOFF_EL2_SysRegWrite_621ada4cfda60bcb_def, non_mem_expI) + +lemma non_mem_exp_CNTV_CTL_EL02_SysRegWrite_d6cac9cc52dd8fec[non_mem_expI]: + "non_mem_exp (CNTV_CTL_EL02_SysRegWrite_d6cac9cc52dd8fec el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_CTL_EL02_SysRegWrite_d6cac9cc52dd8fec_def, non_mem_expI) + +lemma non_mem_exp_CNTV_CTL_EL0_SysRegWrite_e9fd22bae4b06064[non_mem_expI]: + "non_mem_exp (CNTV_CTL_EL0_SysRegWrite_e9fd22bae4b06064 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_CTL_EL0_SysRegWrite_e9fd22bae4b06064_def, non_mem_expI) + +lemma non_mem_exp_CNTV_CVAL_EL02_SysRegWrite_7548964ed28b5abb[non_mem_expI]: + "non_mem_exp (CNTV_CVAL_EL02_SysRegWrite_7548964ed28b5abb el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_CVAL_EL02_SysRegWrite_7548964ed28b5abb_def, non_mem_expI) + +lemma non_mem_exp_CNTV_CVAL_EL0_SysRegWrite_f237c5c94ec92951[non_mem_expI]: + "non_mem_exp (CNTV_CVAL_EL0_SysRegWrite_f237c5c94ec92951 el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_CVAL_EL0_SysRegWrite_f237c5c94ec92951_def, non_mem_expI) + +lemma non_mem_exp_CNTV_TVAL_EL02_SysRegWrite_dc97f79a5f74078f[non_mem_expI]: + "non_mem_exp (CNTV_TVAL_EL02_SysRegWrite_dc97f79a5f74078f el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_TVAL_EL02_SysRegWrite_dc97f79a5f74078f_def, non_mem_expI) + +lemma non_mem_exp_CNTV_TVAL_EL0_SysRegWrite_903191acca729cda[non_mem_expI]: + "non_mem_exp (CNTV_TVAL_EL0_SysRegWrite_903191acca729cda el op0 op1 CRn op2 CRm val_name)" + by (unfold CNTV_TVAL_EL0_SysRegWrite_903191acca729cda_def, non_mem_expI) + +lemma non_mem_exp_CONTEXTIDR_EL12_SysRegWrite_33154953ae1b01d5[non_mem_expI]: + "non_mem_exp (CONTEXTIDR_EL12_SysRegWrite_33154953ae1b01d5 el op0 op1 CRn op2 CRm val_name)" + by (unfold CONTEXTIDR_EL12_SysRegWrite_33154953ae1b01d5_def, non_mem_expI) + +lemma non_mem_exp_CONTEXTIDR_EL1_SysRegWrite_5408e4e72af4e23d[non_mem_expI]: + "non_mem_exp (CONTEXTIDR_EL1_SysRegWrite_5408e4e72af4e23d el op0 op1 CRn op2 CRm val_name)" + by (unfold CONTEXTIDR_EL1_SysRegWrite_5408e4e72af4e23d_def, non_mem_expI) + +lemma non_mem_exp_CONTEXTIDR_EL2_SysRegWrite_27187b6dc7c5a748[non_mem_expI]: + "non_mem_exp (CONTEXTIDR_EL2_SysRegWrite_27187b6dc7c5a748 el op0 op1 CRn op2 CRm val_name)" + by (unfold CONTEXTIDR_EL2_SysRegWrite_27187b6dc7c5a748_def, non_mem_expI) + +lemma non_mem_exp_CPACR_EL12_SysRegWrite_637092a999939f8b[non_mem_expI]: + "non_mem_exp (CPACR_EL12_SysRegWrite_637092a999939f8b el op0 op1 CRn op2 CRm val_name)" + by (unfold CPACR_EL12_SysRegWrite_637092a999939f8b_def, non_mem_expI) + +lemma non_mem_exp_CPACR_EL1_SysRegWrite_00878a1f3e87823c[non_mem_expI]: + "non_mem_exp (CPACR_EL1_SysRegWrite_00878a1f3e87823c el op0 op1 CRn op2 CRm val_name)" + by (unfold CPACR_EL1_SysRegWrite_00878a1f3e87823c_def, non_mem_expI) + +lemma non_mem_exp_CPTR_EL2_SysRegWrite_5a082f460b1b2308[non_mem_expI]: + "non_mem_exp (CPTR_EL2_SysRegWrite_5a082f460b1b2308 el op0 op1 CRn op2 CRm val_name)" + by (unfold CPTR_EL2_SysRegWrite_5a082f460b1b2308_def, non_mem_expI) + +lemma non_mem_exp_CPTR_EL3_SysRegWrite_879d4b1bad53408b[non_mem_expI]: + "non_mem_exp (CPTR_EL3_SysRegWrite_879d4b1bad53408b el op0 op1 CRn op2 CRm val_name)" + by (unfold CPTR_EL3_SysRegWrite_879d4b1bad53408b_def, non_mem_expI) + +lemma non_mem_exp_CSCR_EL3_SysRegWrite_22b95c83b04d6c91[non_mem_expI]: + "non_mem_exp (CSCR_EL3_SysRegWrite_22b95c83b04d6c91 el op0 op1 CRn op2 CRm val_name)" + by (unfold CSCR_EL3_SysRegWrite_22b95c83b04d6c91_def, non_mem_expI) + +lemma non_mem_exp_CSSELR_EL1_SysRegWrite_1f9e1e0300c8783c[non_mem_expI]: + "non_mem_exp (CSSELR_EL1_SysRegWrite_1f9e1e0300c8783c el op0 op1 CRn op2 CRm val_name)" + by (unfold CSSELR_EL1_SysRegWrite_1f9e1e0300c8783c_def, non_mem_expI) + +lemma non_mem_exp_DACR32_EL2_SysRegWrite_a8bad0131817f121[non_mem_expI]: + "non_mem_exp (DACR32_EL2_SysRegWrite_a8bad0131817f121 el op0 op1 CRn op2 CRm val_name)" + by (unfold DACR32_EL2_SysRegWrite_a8bad0131817f121_def, non_mem_expI) + +lemma non_mem_exp_DAIF_SysRegWrite_3d31f214debf624b[non_mem_expI]: + "non_mem_exp (DAIF_SysRegWrite_3d31f214debf624b el op0 op1 CRn op2 CRm val_name)" + by (unfold DAIF_SysRegWrite_3d31f214debf624b_def, non_mem_expI) + +lemma non_mem_exp_DBGBCR_EL1_SysRegWrite_6730f3e3839510c5[non_mem_expI]: + "non_mem_exp (DBGBCR_EL1_SysRegWrite_6730f3e3839510c5 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGBCR_EL1_SysRegWrite_6730f3e3839510c5_def, non_mem_expI) + +lemma non_mem_exp_DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b[non_mem_expI]: + "non_mem_exp (DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGBVR_EL1_SysRegWrite_915752bfd6a41a2b_def, non_mem_expI) + +lemma non_mem_exp_DBGCLAIMCLR_EL1_SysRegWrite_2a099a67767e57cf[non_mem_expI]: + "non_mem_exp (DBGCLAIMCLR_EL1_SysRegWrite_2a099a67767e57cf el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGCLAIMCLR_EL1_SysRegWrite_2a099a67767e57cf_def, non_mem_expI) + +lemma non_mem_exp_DBGCLAIMSET_EL1_SysRegWrite_90e355b6a5730770[non_mem_expI]: + "non_mem_exp (DBGCLAIMSET_EL1_SysRegWrite_90e355b6a5730770 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGCLAIMSET_EL1_SysRegWrite_90e355b6a5730770_def, non_mem_expI) + +lemma non_mem_exp_DBGDTRTX_EL0_SysRegWrite_057e8c91e001a69f[non_mem_expI]: + "non_mem_exp (DBGDTRTX_EL0_SysRegWrite_057e8c91e001a69f el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGDTRTX_EL0_SysRegWrite_057e8c91e001a69f_def, non_mem_expI) + +lemma non_mem_exp_DBGDTR_EL0_write[non_mem_expI]: + "non_mem_exp (DBGDTR_EL0_write val_name)" + by (unfold DBGDTR_EL0_write_def, non_mem_expI) + +lemma non_mem_exp_DBGDTR_EL0_SysRegWrite_c7246a22e06c7729[non_mem_expI]: + "non_mem_exp (DBGDTR_EL0_SysRegWrite_c7246a22e06c7729 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGDTR_EL0_SysRegWrite_c7246a22e06c7729_def, non_mem_expI) + +lemma non_mem_exp_DBGPRCR_EL1_SysRegWrite_710b60256172548e[non_mem_expI]: + "non_mem_exp (DBGPRCR_EL1_SysRegWrite_710b60256172548e el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGPRCR_EL1_SysRegWrite_710b60256172548e_def, non_mem_expI) + +lemma non_mem_exp_DBGVCR32_EL2_SysRegWrite_769fbfe4fa51a4e5[non_mem_expI]: + "non_mem_exp (DBGVCR32_EL2_SysRegWrite_769fbfe4fa51a4e5 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGVCR32_EL2_SysRegWrite_769fbfe4fa51a4e5_def, non_mem_expI) + +lemma non_mem_exp_DBGWCR_EL1_SysRegWrite_6bda3acb5910d354[non_mem_expI]: + "non_mem_exp (DBGWCR_EL1_SysRegWrite_6bda3acb5910d354 el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGWCR_EL1_SysRegWrite_6bda3acb5910d354_def, non_mem_expI) + +lemma non_mem_exp_DBGWVR_EL1_SysRegWrite_745b296ee53305ea[non_mem_expI]: + "non_mem_exp (DBGWVR_EL1_SysRegWrite_745b296ee53305ea el op0 op1 CRn op2 CRm val_name)" + by (unfold DBGWVR_EL1_SysRegWrite_745b296ee53305ea_def, non_mem_expI) + +lemma non_mem_exp_DISR_EL1_SysRegWrite_64517664b9260065[non_mem_expI]: + "non_mem_exp (DISR_EL1_SysRegWrite_64517664b9260065 el op0 op1 CRn op2 CRm val_name)" + by (unfold DISR_EL1_SysRegWrite_64517664b9260065_def, non_mem_expI) + +lemma non_mem_exp_DLR_EL0_write[non_mem_expI]: + "non_mem_exp (DLR_EL0_write val_name)" + by (unfold DLR_EL0_write_def, non_mem_expI) + +lemma non_mem_exp_DLR_EL0_SysRegWrite_a2d10a509fed3a63[non_mem_expI]: + "non_mem_exp (DLR_EL0_SysRegWrite_a2d10a509fed3a63 el op0 op1 CRn op2 CRm val_name)" + by (unfold DLR_EL0_SysRegWrite_a2d10a509fed3a63_def, non_mem_expI) + +lemma non_mem_exp_ELR_EL12_SysRegWrite_6720e93c266dadea[non_mem_expI]: + "non_mem_exp (ELR_EL12_SysRegWrite_6720e93c266dadea el op0 op1 CRn op2 CRm val_name)" + by (unfold ELR_EL12_SysRegWrite_6720e93c266dadea_def, non_mem_expI) + +lemma non_mem_exp_ELR_EL1_SysRegWrite_b6bd589b2dd79575[non_mem_expI]: + "non_mem_exp (ELR_EL1_SysRegWrite_b6bd589b2dd79575 el op0 op1 CRn op2 CRm val_name)" + by (unfold ELR_EL1_SysRegWrite_b6bd589b2dd79575_def, non_mem_expI) + +lemma non_mem_exp_ELR_EL2_SysRegWrite_9f4ca59c1a88f1a9[non_mem_expI]: + "non_mem_exp (ELR_EL2_SysRegWrite_9f4ca59c1a88f1a9 el op0 op1 CRn op2 CRm val_name)" + by (unfold ELR_EL2_SysRegWrite_9f4ca59c1a88f1a9_def, non_mem_expI) + +lemma non_mem_exp_ELR_EL3_SysRegWrite_8cd0b0c7f61ee7aa[non_mem_expI]: + "non_mem_exp (ELR_EL3_SysRegWrite_8cd0b0c7f61ee7aa el op0 op1 CRn op2 CRm val_name)" + by (unfold ELR_EL3_SysRegWrite_8cd0b0c7f61ee7aa_def, non_mem_expI) + +lemma non_mem_exp_ERRSELR_EL1_SysRegWrite_551535eed30e26f9[non_mem_expI]: + "non_mem_exp (ERRSELR_EL1_SysRegWrite_551535eed30e26f9 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERRSELR_EL1_SysRegWrite_551535eed30e26f9_def, non_mem_expI) + +lemma non_mem_exp_ERXADDR_EL1_SysRegWrite_8a1eabc2959662e8[non_mem_expI]: + "non_mem_exp (ERXADDR_EL1_SysRegWrite_8a1eabc2959662e8 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXADDR_EL1_SysRegWrite_8a1eabc2959662e8_def, non_mem_expI) + +lemma non_mem_exp_ERXCTLR_EL1_SysRegWrite_acca1e102ba86b42[non_mem_expI]: + "non_mem_exp (ERXCTLR_EL1_SysRegWrite_acca1e102ba86b42 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXCTLR_EL1_SysRegWrite_acca1e102ba86b42_def, non_mem_expI) + +lemma non_mem_exp_ERXMISC0_EL1_SysRegWrite_822ceca9b10b2621[non_mem_expI]: + "non_mem_exp (ERXMISC0_EL1_SysRegWrite_822ceca9b10b2621 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXMISC0_EL1_SysRegWrite_822ceca9b10b2621_def, non_mem_expI) + +lemma non_mem_exp_ERXMISC1_EL1_SysRegWrite_9a9ef77b5fd82587[non_mem_expI]: + "non_mem_exp (ERXMISC1_EL1_SysRegWrite_9a9ef77b5fd82587 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXMISC1_EL1_SysRegWrite_9a9ef77b5fd82587_def, non_mem_expI) + +lemma non_mem_exp_ERXSTATUS_EL1_SysRegWrite_f0798b4207ec0193[non_mem_expI]: + "non_mem_exp (ERXSTATUS_EL1_SysRegWrite_f0798b4207ec0193 el op0 op1 CRn op2 CRm val_name)" + by (unfold ERXSTATUS_EL1_SysRegWrite_f0798b4207ec0193_def, non_mem_expI) + +lemma non_mem_exp_ESR_EL12_SysRegWrite_2b2d6012ba438548[non_mem_expI]: + "non_mem_exp (ESR_EL12_SysRegWrite_2b2d6012ba438548 el op0 op1 CRn op2 CRm val_name)" + by (unfold ESR_EL12_SysRegWrite_2b2d6012ba438548_def, non_mem_expI) + +lemma non_mem_exp_ESR_EL1_SysRegWrite_a8ce40896bd70a6b[non_mem_expI]: + "non_mem_exp (ESR_EL1_SysRegWrite_a8ce40896bd70a6b el op0 op1 CRn op2 CRm val_name)" + by (unfold ESR_EL1_SysRegWrite_a8ce40896bd70a6b_def, non_mem_expI) + +lemma non_mem_exp_ESR_EL2_SysRegWrite_a10e84e3bd1020c8[non_mem_expI]: + "non_mem_exp (ESR_EL2_SysRegWrite_a10e84e3bd1020c8 el op0 op1 CRn op2 CRm val_name)" + by (unfold ESR_EL2_SysRegWrite_a10e84e3bd1020c8_def, non_mem_expI) + +lemma non_mem_exp_ESR_EL3_SysRegWrite_195a2e1a5b40464e[non_mem_expI]: + "non_mem_exp (ESR_EL3_SysRegWrite_195a2e1a5b40464e el op0 op1 CRn op2 CRm val_name)" + by (unfold ESR_EL3_SysRegWrite_195a2e1a5b40464e_def, non_mem_expI) + +lemma non_mem_exp_FAR_EL12_SysRegWrite_78f825940e556299[non_mem_expI]: + "non_mem_exp (FAR_EL12_SysRegWrite_78f825940e556299 el op0 op1 CRn op2 CRm val_name)" + by (unfold FAR_EL12_SysRegWrite_78f825940e556299_def, non_mem_expI) + +lemma non_mem_exp_FAR_EL1_SysRegWrite_fc0bd224b62cc089[non_mem_expI]: + "non_mem_exp (FAR_EL1_SysRegWrite_fc0bd224b62cc089 el op0 op1 CRn op2 CRm val_name)" + by (unfold FAR_EL1_SysRegWrite_fc0bd224b62cc089_def, non_mem_expI) + +lemma non_mem_exp_FAR_EL2_SysRegWrite_6370aabce83a1613[non_mem_expI]: + "non_mem_exp (FAR_EL2_SysRegWrite_6370aabce83a1613 el op0 op1 CRn op2 CRm val_name)" + by (unfold FAR_EL2_SysRegWrite_6370aabce83a1613_def, non_mem_expI) + +lemma non_mem_exp_FAR_EL3_SysRegWrite_397cfda85a093e9d[non_mem_expI]: + "non_mem_exp (FAR_EL3_SysRegWrite_397cfda85a093e9d el op0 op1 CRn op2 CRm val_name)" + by (unfold FAR_EL3_SysRegWrite_397cfda85a093e9d_def, non_mem_expI) + +lemma non_mem_exp_FPCR_SysRegWrite_4f255cf55390cebb[non_mem_expI]: + "non_mem_exp (FPCR_SysRegWrite_4f255cf55390cebb el op0 op1 CRn op2 CRm val_name)" + by (unfold FPCR_SysRegWrite_4f255cf55390cebb_def, non_mem_expI) + +lemma non_mem_exp_FPEXC32_EL2_SysRegWrite_9f180ead5c4d6735[non_mem_expI]: + "non_mem_exp (FPEXC32_EL2_SysRegWrite_9f180ead5c4d6735 el op0 op1 CRn op2 CRm val_name)" + by (unfold FPEXC32_EL2_SysRegWrite_9f180ead5c4d6735_def, non_mem_expI) + +lemma non_mem_exp_FPSR_SysRegWrite_413aed98a94900de[non_mem_expI]: + "non_mem_exp (FPSR_SysRegWrite_413aed98a94900de el op0 op1 CRn op2 CRm val_name)" + by (unfold FPSR_SysRegWrite_413aed98a94900de_def, non_mem_expI) + +lemma non_mem_exp_HACR_EL2_SysRegWrite_5b2ca32fcb39ecab[non_mem_expI]: + "non_mem_exp (HACR_EL2_SysRegWrite_5b2ca32fcb39ecab el op0 op1 CRn op2 CRm val_name)" + by (unfold HACR_EL2_SysRegWrite_5b2ca32fcb39ecab_def, non_mem_expI) + +lemma non_mem_exp_HCR_EL2_SysRegWrite_6fc18e07a17fd5a2[non_mem_expI]: + "non_mem_exp (HCR_EL2_SysRegWrite_6fc18e07a17fd5a2 el op0 op1 CRn op2 CRm val_name)" + by (unfold HCR_EL2_SysRegWrite_6fc18e07a17fd5a2_def, non_mem_expI) + +lemma non_mem_exp_HPFAR_EL2_SysRegWrite_20417eccdd6b4768[non_mem_expI]: + "non_mem_exp (HPFAR_EL2_SysRegWrite_20417eccdd6b4768 el op0 op1 CRn op2 CRm val_name)" + by (unfold HPFAR_EL2_SysRegWrite_20417eccdd6b4768_def, non_mem_expI) + +lemma non_mem_exp_HSTR_EL2_SysRegWrite_391a605c0bfb9d1e[non_mem_expI]: + "non_mem_exp (HSTR_EL2_SysRegWrite_391a605c0bfb9d1e el op0 op1 CRn op2 CRm val_name)" + by (unfold HSTR_EL2_SysRegWrite_391a605c0bfb9d1e_def, non_mem_expI) + +lemma non_mem_exp_ICC_AP0R_EL1_SysRegWrite_949897f971748acc[non_mem_expI]: + "non_mem_exp (ICC_AP0R_EL1_SysRegWrite_949897f971748acc el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_AP0R_EL1_SysRegWrite_949897f971748acc_def, non_mem_expI) + +lemma non_mem_exp_ICC_AP1R_EL1_SysRegWrite_55167410f7650dea[non_mem_expI]: + "non_mem_exp (ICC_AP1R_EL1_SysRegWrite_55167410f7650dea el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_AP1R_EL1_SysRegWrite_55167410f7650dea_def, non_mem_expI) + +lemma non_mem_exp_ICC_ASGI1R_EL1_SysRegWrite_c163c25adc1b1354[non_mem_expI]: + "non_mem_exp (ICC_ASGI1R_EL1_SysRegWrite_c163c25adc1b1354 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_ASGI1R_EL1_SysRegWrite_c163c25adc1b1354_def, non_mem_expI) + +lemma non_mem_exp_ICC_BPR0_EL1_SysRegWrite_10028206553f3655[non_mem_expI]: + "non_mem_exp (ICC_BPR0_EL1_SysRegWrite_10028206553f3655 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_BPR0_EL1_SysRegWrite_10028206553f3655_def, non_mem_expI) + +lemma non_mem_exp_ICC_BPR1_EL1_SysRegWrite_a633b2e9f3626d9b[non_mem_expI]: + "non_mem_exp (ICC_BPR1_EL1_SysRegWrite_a633b2e9f3626d9b el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_BPR1_EL1_SysRegWrite_a633b2e9f3626d9b_def, non_mem_expI) + +lemma non_mem_exp_ICC_CTLR_EL1_SysRegWrite_8ec3f4b67393eba8[non_mem_expI]: + "non_mem_exp (ICC_CTLR_EL1_SysRegWrite_8ec3f4b67393eba8 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_CTLR_EL1_SysRegWrite_8ec3f4b67393eba8_def, non_mem_expI) + +lemma non_mem_exp_ICC_CTLR_EL3_SysRegWrite_ecc8b41b177c53e8[non_mem_expI]: + "non_mem_exp (ICC_CTLR_EL3_SysRegWrite_ecc8b41b177c53e8 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_CTLR_EL3_SysRegWrite_ecc8b41b177c53e8_def, non_mem_expI) + +lemma non_mem_exp_ICC_DIR_EL1_SysRegWrite_77fadeda7efde9c5[non_mem_expI]: + "non_mem_exp (ICC_DIR_EL1_SysRegWrite_77fadeda7efde9c5 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_DIR_EL1_SysRegWrite_77fadeda7efde9c5_def, non_mem_expI) + +lemma non_mem_exp_ICC_EOIR0_EL1_SysRegWrite_9c0fae08cd7a2444[non_mem_expI]: + "non_mem_exp (ICC_EOIR0_EL1_SysRegWrite_9c0fae08cd7a2444 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_EOIR0_EL1_SysRegWrite_9c0fae08cd7a2444_def, non_mem_expI) + +lemma non_mem_exp_ICC_EOIR1_EL1_SysRegWrite_f065db56e179bf6e[non_mem_expI]: + "non_mem_exp (ICC_EOIR1_EL1_SysRegWrite_f065db56e179bf6e el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_EOIR1_EL1_SysRegWrite_f065db56e179bf6e_def, non_mem_expI) + +lemma non_mem_exp_ICC_IGRPEN0_EL1_SysRegWrite_b94e4d10f7a33382[non_mem_expI]: + "non_mem_exp (ICC_IGRPEN0_EL1_SysRegWrite_b94e4d10f7a33382 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_IGRPEN0_EL1_SysRegWrite_b94e4d10f7a33382_def, non_mem_expI) + +lemma non_mem_exp_ICC_IGRPEN1_EL1_SysRegWrite_c36dfa556252f6b4[non_mem_expI]: + "non_mem_exp (ICC_IGRPEN1_EL1_SysRegWrite_c36dfa556252f6b4 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_IGRPEN1_EL1_SysRegWrite_c36dfa556252f6b4_def, non_mem_expI) + +lemma non_mem_exp_ICC_IGRPEN1_EL3_SysRegWrite_6f1db000a53b40ca[non_mem_expI]: + "non_mem_exp (ICC_IGRPEN1_EL3_SysRegWrite_6f1db000a53b40ca el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_IGRPEN1_EL3_SysRegWrite_6f1db000a53b40ca_def, non_mem_expI) + +lemma non_mem_exp_ICC_PMR_EL1_SysRegWrite_8bb2caa31e7d5e1b[non_mem_expI]: + "non_mem_exp (ICC_PMR_EL1_SysRegWrite_8bb2caa31e7d5e1b el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_PMR_EL1_SysRegWrite_8bb2caa31e7d5e1b_def, non_mem_expI) + +lemma non_mem_exp_ICC_SGI0R_EL1_SysRegWrite_ba6d1066ea6fbbb7[non_mem_expI]: + "non_mem_exp (ICC_SGI0R_EL1_SysRegWrite_ba6d1066ea6fbbb7 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SGI0R_EL1_SysRegWrite_ba6d1066ea6fbbb7_def, non_mem_expI) + +lemma non_mem_exp_ICC_SGI1R_EL1_SysRegWrite_0da31fe6c2e1b098[non_mem_expI]: + "non_mem_exp (ICC_SGI1R_EL1_SysRegWrite_0da31fe6c2e1b098 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SGI1R_EL1_SysRegWrite_0da31fe6c2e1b098_def, non_mem_expI) + +lemma non_mem_exp_ICC_SRE_EL1_SysRegWrite_d2efb75caa67d019[non_mem_expI]: + "non_mem_exp (ICC_SRE_EL1_SysRegWrite_d2efb75caa67d019 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SRE_EL1_SysRegWrite_d2efb75caa67d019_def, non_mem_expI) + +lemma non_mem_exp_ICC_SRE_EL2_SysRegWrite_39c314f677b8ec2e[non_mem_expI]: + "non_mem_exp (ICC_SRE_EL2_SysRegWrite_39c314f677b8ec2e el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SRE_EL2_SysRegWrite_39c314f677b8ec2e_def, non_mem_expI) + +lemma non_mem_exp_ICC_SRE_EL3_SysRegWrite_c0af2dd58a7e1d22[non_mem_expI]: + "non_mem_exp (ICC_SRE_EL3_SysRegWrite_c0af2dd58a7e1d22 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICC_SRE_EL3_SysRegWrite_c0af2dd58a7e1d22_def, non_mem_expI) + +lemma non_mem_exp_ICH_AP0R_EL2_SysRegWrite_9517857bb550d699[non_mem_expI]: + "non_mem_exp (ICH_AP0R_EL2_SysRegWrite_9517857bb550d699 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_AP0R_EL2_SysRegWrite_9517857bb550d699_def, non_mem_expI) + +lemma non_mem_exp_ICH_AP1R_EL2_SysRegWrite_20f46016b54a3395[non_mem_expI]: + "non_mem_exp (ICH_AP1R_EL2_SysRegWrite_20f46016b54a3395 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_AP1R_EL2_SysRegWrite_20f46016b54a3395_def, non_mem_expI) + +lemma non_mem_exp_ICH_HCR_EL2_SysRegWrite_2fea52a15cd7dbe5[non_mem_expI]: + "non_mem_exp (ICH_HCR_EL2_SysRegWrite_2fea52a15cd7dbe5 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_HCR_EL2_SysRegWrite_2fea52a15cd7dbe5_def, non_mem_expI) + +lemma non_mem_exp_ICH_LR_EL2_SysRegWrite_8b291f94259261d2[non_mem_expI]: + "non_mem_exp (ICH_LR_EL2_SysRegWrite_8b291f94259261d2 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_LR_EL2_SysRegWrite_8b291f94259261d2_def, non_mem_expI) + +lemma non_mem_exp_ICH_VMCR_EL2_SysRegWrite_86a315374f6b5205[non_mem_expI]: + "non_mem_exp (ICH_VMCR_EL2_SysRegWrite_86a315374f6b5205 el op0 op1 CRn op2 CRm val_name)" + by (unfold ICH_VMCR_EL2_SysRegWrite_86a315374f6b5205_def, non_mem_expI) + +lemma non_mem_exp_IFSR32_EL2_SysRegWrite_6ce25b2b11e30403[non_mem_expI]: + "non_mem_exp (IFSR32_EL2_SysRegWrite_6ce25b2b11e30403 el op0 op1 CRn op2 CRm val_name)" + by (unfold IFSR32_EL2_SysRegWrite_6ce25b2b11e30403_def, non_mem_expI) + +lemma non_mem_exp_LORC_EL1_SysRegWrite_7100b979c23fc52e[non_mem_expI]: + "non_mem_exp (LORC_EL1_SysRegWrite_7100b979c23fc52e el op0 op1 CRn op2 CRm val_name)" + by (unfold LORC_EL1_SysRegWrite_7100b979c23fc52e_def, non_mem_expI) + +lemma non_mem_exp_LOREA_EL1_SysRegWrite_2d068511b7f5ce7b[non_mem_expI]: + "non_mem_exp (LOREA_EL1_SysRegWrite_2d068511b7f5ce7b el op0 op1 CRn op2 CRm val_name)" + by (unfold LOREA_EL1_SysRegWrite_2d068511b7f5ce7b_def, non_mem_expI) + +lemma non_mem_exp_LORN_EL1_SysRegWrite_bde03c74e878b099[non_mem_expI]: + "non_mem_exp (LORN_EL1_SysRegWrite_bde03c74e878b099 el op0 op1 CRn op2 CRm val_name)" + by (unfold LORN_EL1_SysRegWrite_bde03c74e878b099_def, non_mem_expI) + +lemma non_mem_exp_LORSA_EL1_SysRegWrite_9ba633e967136731[non_mem_expI]: + "non_mem_exp (LORSA_EL1_SysRegWrite_9ba633e967136731 el op0 op1 CRn op2 CRm val_name)" + by (unfold LORSA_EL1_SysRegWrite_9ba633e967136731_def, non_mem_expI) + +lemma non_mem_exp_MAIR_EL12_SysRegWrite_da2526ed2008ed50[non_mem_expI]: + "non_mem_exp (MAIR_EL12_SysRegWrite_da2526ed2008ed50 el op0 op1 CRn op2 CRm val_name)" + by (unfold MAIR_EL12_SysRegWrite_da2526ed2008ed50_def, non_mem_expI) + +lemma non_mem_exp_MAIR_EL1_SysRegWrite_45d8150aaf31e3b9[non_mem_expI]: + "non_mem_exp (MAIR_EL1_SysRegWrite_45d8150aaf31e3b9 el op0 op1 CRn op2 CRm val_name)" + by (unfold MAIR_EL1_SysRegWrite_45d8150aaf31e3b9_def, non_mem_expI) + +lemma non_mem_exp_MAIR_EL2_SysRegWrite_4e3422c1776528f5[non_mem_expI]: + "non_mem_exp (MAIR_EL2_SysRegWrite_4e3422c1776528f5 el op0 op1 CRn op2 CRm val_name)" + by (unfold MAIR_EL2_SysRegWrite_4e3422c1776528f5_def, non_mem_expI) + +lemma non_mem_exp_MAIR_EL3_SysRegWrite_d15af780e0b4e771[non_mem_expI]: + "non_mem_exp (MAIR_EL3_SysRegWrite_d15af780e0b4e771 el op0 op1 CRn op2 CRm val_name)" + by (unfold MAIR_EL3_SysRegWrite_d15af780e0b4e771_def, non_mem_expI) + +lemma non_mem_exp_MDCCINT_EL1_SysRegWrite_1e6a37984aec7145[non_mem_expI]: + "non_mem_exp (MDCCINT_EL1_SysRegWrite_1e6a37984aec7145 el op0 op1 CRn op2 CRm val_name)" + by (unfold MDCCINT_EL1_SysRegWrite_1e6a37984aec7145_def, non_mem_expI) + +lemma non_mem_exp_MDCR_EL2_SysRegWrite_3f12005c8c459bf3[non_mem_expI]: + "non_mem_exp (MDCR_EL2_SysRegWrite_3f12005c8c459bf3 el op0 op1 CRn op2 CRm val_name)" + by (unfold MDCR_EL2_SysRegWrite_3f12005c8c459bf3_def, non_mem_expI) + +lemma non_mem_exp_MDCR_EL3_SysRegWrite_37dff5fa83ad16ed[non_mem_expI]: + "non_mem_exp (MDCR_EL3_SysRegWrite_37dff5fa83ad16ed el op0 op1 CRn op2 CRm val_name)" + by (unfold MDCR_EL3_SysRegWrite_37dff5fa83ad16ed_def, non_mem_expI) + +lemma non_mem_exp_MDSCR_EL1_SysRegWrite_94ddb1e46aff4dfa[non_mem_expI]: + "non_mem_exp (MDSCR_EL1_SysRegWrite_94ddb1e46aff4dfa el op0 op1 CRn op2 CRm val_name)" + by (unfold MDSCR_EL1_SysRegWrite_94ddb1e46aff4dfa_def, non_mem_expI) + +lemma non_mem_exp_MPAM0_EL1_SysRegWrite_88f6c0c61a59ac23[non_mem_expI]: + "non_mem_exp (MPAM0_EL1_SysRegWrite_88f6c0c61a59ac23 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM0_EL1_SysRegWrite_88f6c0c61a59ac23_def, non_mem_expI) + +lemma non_mem_exp_MPAM2_EL2_write[non_mem_expI]: + "non_mem_exp (MPAM2_EL2_write val_name)" + by (unfold MPAM2_EL2_write_def, non_mem_expI) + +lemma non_mem_exp_MPAM1_EL1_write[non_mem_expI]: + "non_mem_exp (MPAM1_EL1_write val_name)" + by (unfold MPAM1_EL1_write_def, non_mem_expI) + +lemma non_mem_exp_MPAM1_EL12_SysRegWrite_2cbbb0edf5787671[non_mem_expI]: + "non_mem_exp (MPAM1_EL12_SysRegWrite_2cbbb0edf5787671 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM1_EL12_SysRegWrite_2cbbb0edf5787671_def, non_mem_expI) + +lemma non_mem_exp_MPAM1_EL1_SysRegWrite_cd02720a3298b1c6[non_mem_expI]: + "non_mem_exp (MPAM1_EL1_SysRegWrite_cd02720a3298b1c6 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM1_EL1_SysRegWrite_cd02720a3298b1c6_def, non_mem_expI) + +lemma non_mem_exp_MPAM2_EL2_SysRegWrite_d6bae8d18aebb554[non_mem_expI]: + "non_mem_exp (MPAM2_EL2_SysRegWrite_d6bae8d18aebb554 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM2_EL2_SysRegWrite_d6bae8d18aebb554_def, non_mem_expI) + +lemma non_mem_exp_MPAM3_EL3_SysRegWrite_bb55d8a9d90e05e3[non_mem_expI]: + "non_mem_exp (MPAM3_EL3_SysRegWrite_bb55d8a9d90e05e3 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAM3_EL3_SysRegWrite_bb55d8a9d90e05e3_def, non_mem_expI) + +lemma non_mem_exp_MPAMHCR_EL2_SysRegWrite_e38755d6111336b8[non_mem_expI]: + "non_mem_exp (MPAMHCR_EL2_SysRegWrite_e38755d6111336b8 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMHCR_EL2_SysRegWrite_e38755d6111336b8_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM0_EL2_SysRegWrite_c00108111630aa84[non_mem_expI]: + "non_mem_exp (MPAMVPM0_EL2_SysRegWrite_c00108111630aa84 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM0_EL2_SysRegWrite_c00108111630aa84_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM1_EL2_SysRegWrite_81a739cc4bd1cd46[non_mem_expI]: + "non_mem_exp (MPAMVPM1_EL2_SysRegWrite_81a739cc4bd1cd46 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM1_EL2_SysRegWrite_81a739cc4bd1cd46_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM2_EL2_SysRegWrite_20a1b54bc18980b1[non_mem_expI]: + "non_mem_exp (MPAMVPM2_EL2_SysRegWrite_20a1b54bc18980b1 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM2_EL2_SysRegWrite_20a1b54bc18980b1_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM3_EL2_SysRegWrite_d2a71d8e23cc67af[non_mem_expI]: + "non_mem_exp (MPAMVPM3_EL2_SysRegWrite_d2a71d8e23cc67af el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM3_EL2_SysRegWrite_d2a71d8e23cc67af_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM4_EL2_SysRegWrite_2d0a10731399829d[non_mem_expI]: + "non_mem_exp (MPAMVPM4_EL2_SysRegWrite_2d0a10731399829d el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM4_EL2_SysRegWrite_2d0a10731399829d_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM5_EL2_SysRegWrite_ec98ca57d40ac9ec[non_mem_expI]: + "non_mem_exp (MPAMVPM5_EL2_SysRegWrite_ec98ca57d40ac9ec el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM5_EL2_SysRegWrite_ec98ca57d40ac9ec_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM6_EL2_SysRegWrite_0934853fee68e9bd[non_mem_expI]: + "non_mem_exp (MPAMVPM6_EL2_SysRegWrite_0934853fee68e9bd el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM6_EL2_SysRegWrite_0934853fee68e9bd_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPM7_EL2_SysRegWrite_dfb7f68750df7012[non_mem_expI]: + "non_mem_exp (MPAMVPM7_EL2_SysRegWrite_dfb7f68750df7012 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPM7_EL2_SysRegWrite_dfb7f68750df7012_def, non_mem_expI) + +lemma non_mem_exp_MPAMVPMV_EL2_SysRegWrite_abd8d27e91fadf85[non_mem_expI]: + "non_mem_exp (MPAMVPMV_EL2_SysRegWrite_abd8d27e91fadf85 el op0 op1 CRn op2 CRm val_name)" + by (unfold MPAMVPMV_EL2_SysRegWrite_abd8d27e91fadf85_def, non_mem_expI) + +lemma non_mem_exp_OSDLR_EL1_SysRegWrite_591fd96d91652c64[non_mem_expI]: + "non_mem_exp (OSDLR_EL1_SysRegWrite_591fd96d91652c64 el op0 op1 CRn op2 CRm val_name)" + by (unfold OSDLR_EL1_SysRegWrite_591fd96d91652c64_def, non_mem_expI) + +lemma non_mem_exp_OSDTRRX_EL1_SysRegWrite_6dc5d8521b60df8a[non_mem_expI]: + "non_mem_exp (OSDTRRX_EL1_SysRegWrite_6dc5d8521b60df8a el op0 op1 CRn op2 CRm val_name)" + by (unfold OSDTRRX_EL1_SysRegWrite_6dc5d8521b60df8a_def, non_mem_expI) + +lemma non_mem_exp_OSDTRTX_EL1_SysRegWrite_9ba0c4a85d0c1de5[non_mem_expI]: + "non_mem_exp (OSDTRTX_EL1_SysRegWrite_9ba0c4a85d0c1de5 el op0 op1 CRn op2 CRm val_name)" + by (unfold OSDTRTX_EL1_SysRegWrite_9ba0c4a85d0c1de5_def, non_mem_expI) + +lemma non_mem_exp_OSECCR_EL1_SysRegWrite_cabf381bfb822732[non_mem_expI]: + "non_mem_exp (OSECCR_EL1_SysRegWrite_cabf381bfb822732 el op0 op1 CRn op2 CRm val_name)" + by (unfold OSECCR_EL1_SysRegWrite_cabf381bfb822732_def, non_mem_expI) + +lemma non_mem_exp_OSLAR_EL1_SysRegWrite_582d77c57653b2c4[non_mem_expI]: + "non_mem_exp (OSLAR_EL1_SysRegWrite_582d77c57653b2c4 el op0 op1 CRn op2 CRm val_name)" + by (unfold OSLAR_EL1_SysRegWrite_582d77c57653b2c4_def, non_mem_expI) + +lemma non_mem_exp_PAR_EL1_SysRegWrite_aa92c70a4b5d5873[non_mem_expI]: + "non_mem_exp (PAR_EL1_SysRegWrite_aa92c70a4b5d5873 el op0 op1 CRn op2 CRm val_name)" + by (unfold PAR_EL1_SysRegWrite_aa92c70a4b5d5873_def, non_mem_expI) + +lemma non_mem_exp_PMBLIMITR_EL1_SysRegWrite_ddfe2ba603df6628[non_mem_expI]: + "non_mem_exp (PMBLIMITR_EL1_SysRegWrite_ddfe2ba603df6628 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMBLIMITR_EL1_SysRegWrite_ddfe2ba603df6628_def, non_mem_expI) + +lemma non_mem_exp_PMBPTR_EL1_SysRegWrite_32441d8a7a2b9601[non_mem_expI]: + "non_mem_exp (PMBPTR_EL1_SysRegWrite_32441d8a7a2b9601 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMBPTR_EL1_SysRegWrite_32441d8a7a2b9601_def, non_mem_expI) + +lemma non_mem_exp_PMBSR_EL1_SysRegWrite_ff19dc948509312f[non_mem_expI]: + "non_mem_exp (PMBSR_EL1_SysRegWrite_ff19dc948509312f el op0 op1 CRn op2 CRm val_name)" + by (unfold PMBSR_EL1_SysRegWrite_ff19dc948509312f_def, non_mem_expI) + +lemma non_mem_exp_PMCCFILTR_EL0_SysRegWrite_42277f001664525c[non_mem_expI]: + "non_mem_exp (PMCCFILTR_EL0_SysRegWrite_42277f001664525c el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCCFILTR_EL0_SysRegWrite_42277f001664525c_def, non_mem_expI) + +lemma non_mem_exp_PMCCNTR_EL0_SysRegWrite_1d21e0789830cbf9[non_mem_expI]: + "non_mem_exp (PMCCNTR_EL0_SysRegWrite_1d21e0789830cbf9 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCCNTR_EL0_SysRegWrite_1d21e0789830cbf9_def, non_mem_expI) + +lemma non_mem_exp_PMCNTENCLR_EL0_SysRegWrite_bf2c4fae1a891e1b[non_mem_expI]: + "non_mem_exp (PMCNTENCLR_EL0_SysRegWrite_bf2c4fae1a891e1b el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCNTENCLR_EL0_SysRegWrite_bf2c4fae1a891e1b_def, non_mem_expI) + +lemma non_mem_exp_PMCNTENSET_EL0_SysRegWrite_227af2773d320cb1[non_mem_expI]: + "non_mem_exp (PMCNTENSET_EL0_SysRegWrite_227af2773d320cb1 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCNTENSET_EL0_SysRegWrite_227af2773d320cb1_def, non_mem_expI) + +lemma non_mem_exp_PMCR_EL0_SysRegWrite_87ae64466e09f89a[non_mem_expI]: + "non_mem_exp (PMCR_EL0_SysRegWrite_87ae64466e09f89a el op0 op1 CRn op2 CRm val_name)" + by (unfold PMCR_EL0_SysRegWrite_87ae64466e09f89a_def, non_mem_expI) + +lemma non_mem_exp_PMEVCNTR_EL0_SysRegWrite_c197579331ed9cbb[non_mem_expI]: + "non_mem_exp (PMEVCNTR_EL0_SysRegWrite_c197579331ed9cbb el op0 op1 CRn op2 CRm val_name)" + by (unfold PMEVCNTR_EL0_SysRegWrite_c197579331ed9cbb_def, non_mem_expI) + +lemma non_mem_exp_PMEVTYPER_EL0_SysRegWrite_3e6ae16cd645ec0d[non_mem_expI]: + "non_mem_exp (PMEVTYPER_EL0_SysRegWrite_3e6ae16cd645ec0d el op0 op1 CRn op2 CRm val_name)" + by (unfold PMEVTYPER_EL0_SysRegWrite_3e6ae16cd645ec0d_def, non_mem_expI) + +lemma non_mem_exp_PMINTENCLR_EL1_SysRegWrite_1ebd7bf3738fe872[non_mem_expI]: + "non_mem_exp (PMINTENCLR_EL1_SysRegWrite_1ebd7bf3738fe872 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMINTENCLR_EL1_SysRegWrite_1ebd7bf3738fe872_def, non_mem_expI) + +lemma non_mem_exp_PMINTENSET_EL1_SysRegWrite_dd2481ad892e3441[non_mem_expI]: + "non_mem_exp (PMINTENSET_EL1_SysRegWrite_dd2481ad892e3441 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMINTENSET_EL1_SysRegWrite_dd2481ad892e3441_def, non_mem_expI) + +lemma non_mem_exp_PMOVSCLR_EL0_SysRegWrite_9dfa73cda394af99[non_mem_expI]: + "non_mem_exp (PMOVSCLR_EL0_SysRegWrite_9dfa73cda394af99 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMOVSCLR_EL0_SysRegWrite_9dfa73cda394af99_def, non_mem_expI) + +lemma non_mem_exp_PMOVSSET_EL0_SysRegWrite_cfbbfe3b81fe4290[non_mem_expI]: + "non_mem_exp (PMOVSSET_EL0_SysRegWrite_cfbbfe3b81fe4290 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMOVSSET_EL0_SysRegWrite_cfbbfe3b81fe4290_def, non_mem_expI) + +lemma non_mem_exp_PMSCR_EL12_SysRegWrite_fef9a94f50c2763b[non_mem_expI]: + "non_mem_exp (PMSCR_EL12_SysRegWrite_fef9a94f50c2763b el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSCR_EL12_SysRegWrite_fef9a94f50c2763b_def, non_mem_expI) + +lemma non_mem_exp_PMSCR_EL1_SysRegWrite_9798a89ab6804fe0[non_mem_expI]: + "non_mem_exp (PMSCR_EL1_SysRegWrite_9798a89ab6804fe0 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSCR_EL1_SysRegWrite_9798a89ab6804fe0_def, non_mem_expI) + +lemma non_mem_exp_PMSCR_EL2_SysRegWrite_02cd14dd325ed94b[non_mem_expI]: + "non_mem_exp (PMSCR_EL2_SysRegWrite_02cd14dd325ed94b el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSCR_EL2_SysRegWrite_02cd14dd325ed94b_def, non_mem_expI) + +lemma non_mem_exp_PMSELR_EL0_SysRegWrite_18613307de8564a3[non_mem_expI]: + "non_mem_exp (PMSELR_EL0_SysRegWrite_18613307de8564a3 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSELR_EL0_SysRegWrite_18613307de8564a3_def, non_mem_expI) + +lemma non_mem_exp_PMSEVFR_EL1_SysRegWrite_6524c56cd8a10057[non_mem_expI]: + "non_mem_exp (PMSEVFR_EL1_SysRegWrite_6524c56cd8a10057 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSEVFR_EL1_SysRegWrite_6524c56cd8a10057_def, non_mem_expI) + +lemma non_mem_exp_PMSFCR_EL1_SysRegWrite_44d58271848f0db1[non_mem_expI]: + "non_mem_exp (PMSFCR_EL1_SysRegWrite_44d58271848f0db1 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSFCR_EL1_SysRegWrite_44d58271848f0db1_def, non_mem_expI) + +lemma non_mem_exp_PMSICR_EL1_SysRegWrite_1e74423ea1c96ae7[non_mem_expI]: + "non_mem_exp (PMSICR_EL1_SysRegWrite_1e74423ea1c96ae7 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSICR_EL1_SysRegWrite_1e74423ea1c96ae7_def, non_mem_expI) + +lemma non_mem_exp_PMSIRR_EL1_SysRegWrite_bb25878486c35a36[non_mem_expI]: + "non_mem_exp (PMSIRR_EL1_SysRegWrite_bb25878486c35a36 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSIRR_EL1_SysRegWrite_bb25878486c35a36_def, non_mem_expI) + +lemma non_mem_exp_PMSLATFR_EL1_SysRegWrite_5c8b43a6a65c8272[non_mem_expI]: + "non_mem_exp (PMSLATFR_EL1_SysRegWrite_5c8b43a6a65c8272 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSLATFR_EL1_SysRegWrite_5c8b43a6a65c8272_def, non_mem_expI) + +lemma non_mem_exp_PMSWINC_EL0_SysRegWrite_cce1d915b163d5e3[non_mem_expI]: + "non_mem_exp (PMSWINC_EL0_SysRegWrite_cce1d915b163d5e3 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMSWINC_EL0_SysRegWrite_cce1d915b163d5e3_def, non_mem_expI) + +lemma non_mem_exp_PMUSERENR_EL0_SysRegWrite_e7535626e3360c36[non_mem_expI]: + "non_mem_exp (PMUSERENR_EL0_SysRegWrite_e7535626e3360c36 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMUSERENR_EL0_SysRegWrite_e7535626e3360c36_def, non_mem_expI) + +lemma non_mem_exp_PMXEVCNTR_EL0_SysRegWrite_20b0a6df43a7d4ef[non_mem_expI]: + "non_mem_exp (PMXEVCNTR_EL0_SysRegWrite_20b0a6df43a7d4ef el op0 op1 CRn op2 CRm val_name)" + by (unfold PMXEVCNTR_EL0_SysRegWrite_20b0a6df43a7d4ef_def, non_mem_expI) + +lemma non_mem_exp_PMXEVTYPER_EL0_SysRegWrite_82fb55a6e723e983[non_mem_expI]: + "non_mem_exp (PMXEVTYPER_EL0_SysRegWrite_82fb55a6e723e983 el op0 op1 CRn op2 CRm val_name)" + by (unfold PMXEVTYPER_EL0_SysRegWrite_82fb55a6e723e983_def, non_mem_expI) + +lemma non_mem_exp_RMR_EL1_SysRegWrite_0ae19f794f511c7a[non_mem_expI]: + "non_mem_exp (RMR_EL1_SysRegWrite_0ae19f794f511c7a el op0 op1 CRn op2 CRm val_name)" + by (unfold RMR_EL1_SysRegWrite_0ae19f794f511c7a_def, non_mem_expI) + +lemma non_mem_exp_RMR_EL2_SysRegWrite_df7b9a989e2495d2[non_mem_expI]: + "non_mem_exp (RMR_EL2_SysRegWrite_df7b9a989e2495d2 el op0 op1 CRn op2 CRm val_name)" + by (unfold RMR_EL2_SysRegWrite_df7b9a989e2495d2_def, non_mem_expI) + +lemma non_mem_exp_RMR_EL3_SysRegWrite_2849130fc457929e[non_mem_expI]: + "non_mem_exp (RMR_EL3_SysRegWrite_2849130fc457929e el op0 op1 CRn op2 CRm val_name)" + by (unfold RMR_EL3_SysRegWrite_2849130fc457929e_def, non_mem_expI) + +lemma non_mem_exp_RSP_EL0_SysRegWrite_5b2edb6edd27507d[non_mem_expI]: + "non_mem_exp (RSP_EL0_SysRegWrite_5b2edb6edd27507d el op0 op1 CRn op2 CRm val_name)" + by (unfold RSP_EL0_SysRegWrite_5b2edb6edd27507d_def, non_mem_expI) + +lemma non_mem_exp_RTPIDR_EL0_SysRegWrite_74d55919bd0ab5f3[non_mem_expI]: + "non_mem_exp (RTPIDR_EL0_SysRegWrite_74d55919bd0ab5f3 el op0 op1 CRn op2 CRm val_name)" + by (unfold RTPIDR_EL0_SysRegWrite_74d55919bd0ab5f3_def, non_mem_expI) + +lemma non_mem_exp_S3_op1_CCn_CCm_op2_SysRegWrite_22dd63287f599042[non_mem_expI]: + "non_mem_exp (S3_op1_CCn_CCm_op2_SysRegWrite_22dd63287f599042 el op0 op1 CRn op2 CRm val_name)" + by (unfold S3_op1_CCn_CCm_op2_SysRegWrite_22dd63287f599042_def, non_mem_expI) + +lemma non_mem_exp_SCR_EL3_SysRegWrite_020d082781fa9b72[non_mem_expI]: + "non_mem_exp (SCR_EL3_SysRegWrite_020d082781fa9b72 el op0 op1 CRn op2 CRm val_name)" + by (unfold SCR_EL3_SysRegWrite_020d082781fa9b72_def, non_mem_expI) + +lemma non_mem_exp_SCTLR_EL12_SysRegWrite_302de25977d2a0ca[non_mem_expI]: + "non_mem_exp (SCTLR_EL12_SysRegWrite_302de25977d2a0ca el op0 op1 CRn op2 CRm val_name)" + by (unfold SCTLR_EL12_SysRegWrite_302de25977d2a0ca_def, non_mem_expI) + +lemma non_mem_exp_SCTLR_EL1_SysRegWrite_711b0546c662c54d[non_mem_expI]: + "non_mem_exp (SCTLR_EL1_SysRegWrite_711b0546c662c54d el op0 op1 CRn op2 CRm val_name)" + by (unfold SCTLR_EL1_SysRegWrite_711b0546c662c54d_def, non_mem_expI) + +lemma non_mem_exp_SCTLR_EL2_SysRegWrite_ff61a6f00288b28a[non_mem_expI]: + "non_mem_exp (SCTLR_EL2_SysRegWrite_ff61a6f00288b28a el op0 op1 CRn op2 CRm val_name)" + by (unfold SCTLR_EL2_SysRegWrite_ff61a6f00288b28a_def, non_mem_expI) + +lemma non_mem_exp_SCTLR_EL3_SysRegWrite_5b7cc79e5ea93a8f[non_mem_expI]: + "non_mem_exp (SCTLR_EL3_SysRegWrite_5b7cc79e5ea93a8f el op0 op1 CRn op2 CRm val_name)" + by (unfold SCTLR_EL3_SysRegWrite_5b7cc79e5ea93a8f_def, non_mem_expI) + +lemma non_mem_exp_SCXTNUM_EL0_write[non_mem_expI]: + "non_mem_exp (SCXTNUM_EL0_write val_name)" + by (unfold SCXTNUM_EL0_write_def, non_mem_expI) + +lemma non_mem_exp_SCXTNUM_EL0_SysRegWrite_9dbee2793d69c02e[non_mem_expI]: + "non_mem_exp (SCXTNUM_EL0_SysRegWrite_9dbee2793d69c02e el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL0_SysRegWrite_9dbee2793d69c02e_def, non_mem_expI) + +lemma non_mem_exp_SCXTNUM_EL12_SysRegWrite_ba74367909393c9b[non_mem_expI]: + "non_mem_exp (SCXTNUM_EL12_SysRegWrite_ba74367909393c9b el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL12_SysRegWrite_ba74367909393c9b_def, non_mem_expI) + +lemma non_mem_exp_SCXTNUM_EL1_SysRegWrite_6467f6f26a31cece[non_mem_expI]: + "non_mem_exp (SCXTNUM_EL1_SysRegWrite_6467f6f26a31cece el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL1_SysRegWrite_6467f6f26a31cece_def, non_mem_expI) + +lemma non_mem_exp_SCXTNUM_EL2_SysRegWrite_2fcbb6503badb23c[non_mem_expI]: + "non_mem_exp (SCXTNUM_EL2_SysRegWrite_2fcbb6503badb23c el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL2_SysRegWrite_2fcbb6503badb23c_def, non_mem_expI) + +lemma non_mem_exp_SCXTNUM_EL3_SysRegWrite_b39fe9ab09a67ecd[non_mem_expI]: + "non_mem_exp (SCXTNUM_EL3_SysRegWrite_b39fe9ab09a67ecd el op0 op1 CRn op2 CRm val_name)" + by (unfold SCXTNUM_EL3_SysRegWrite_b39fe9ab09a67ecd_def, non_mem_expI) + +lemma non_mem_exp_SDER32_EL3_SysRegWrite_69011ff5e95ac923[non_mem_expI]: + "non_mem_exp (SDER32_EL3_SysRegWrite_69011ff5e95ac923 el op0 op1 CRn op2 CRm val_name)" + by (unfold SDER32_EL3_SysRegWrite_69011ff5e95ac923_def, non_mem_expI) + +lemma non_mem_exp_SPSel_SysRegWrite_c849e120e8533c8c[non_mem_expI]: + "non_mem_exp (SPSel_SysRegWrite_c849e120e8533c8c el op0 op1 CRn op2 CRm val_name)" + by (unfold SPSel_SysRegWrite_c849e120e8533c8c_def, non_mem_expI) + +lemma non_mem_exp_SP_EL0_SysRegWrite_78f870c69d82f9e2[non_mem_expI]: + "non_mem_exp (SP_EL0_SysRegWrite_78f870c69d82f9e2 el op0 op1 CRn op2 CRm val_name)" + by (unfold SP_EL0_SysRegWrite_78f870c69d82f9e2_def, non_mem_expI) + +lemma non_mem_exp_SP_EL1_SysRegWrite_84ae51cf4bf77caa[non_mem_expI]: + "non_mem_exp (SP_EL1_SysRegWrite_84ae51cf4bf77caa el op0 op1 CRn op2 CRm val_name)" + by (unfold SP_EL1_SysRegWrite_84ae51cf4bf77caa_def, non_mem_expI) + +lemma non_mem_exp_SP_EL2_SysRegWrite_a29ffeac6d3856e5[non_mem_expI]: + "non_mem_exp (SP_EL2_SysRegWrite_a29ffeac6d3856e5 el op0 op1 CRn op2 CRm val_name)" + by (unfold SP_EL2_SysRegWrite_a29ffeac6d3856e5_def, non_mem_expI) + +lemma non_mem_exp_TCR_EL12_SysRegWrite_64a7f44c6ddaa0f8[non_mem_expI]: + "non_mem_exp (TCR_EL12_SysRegWrite_64a7f44c6ddaa0f8 el op0 op1 CRn op2 CRm val_name)" + by (unfold TCR_EL12_SysRegWrite_64a7f44c6ddaa0f8_def, non_mem_expI) + +lemma non_mem_exp_TCR_EL1_SysRegWrite_c27e6fc190bb0f0b[non_mem_expI]: + "non_mem_exp (TCR_EL1_SysRegWrite_c27e6fc190bb0f0b el op0 op1 CRn op2 CRm val_name)" + by (unfold TCR_EL1_SysRegWrite_c27e6fc190bb0f0b_def, non_mem_expI) + +lemma non_mem_exp_TCR_EL2_SysRegWrite_5e38279a245750c4[non_mem_expI]: + "non_mem_exp (TCR_EL2_SysRegWrite_5e38279a245750c4 el op0 op1 CRn op2 CRm val_name)" + by (unfold TCR_EL2_SysRegWrite_5e38279a245750c4_def, non_mem_expI) + +lemma non_mem_exp_TCR_EL3_SysRegWrite_3b3587015a3d20f4[non_mem_expI]: + "non_mem_exp (TCR_EL3_SysRegWrite_3b3587015a3d20f4 el op0 op1 CRn op2 CRm val_name)" + by (unfold TCR_EL3_SysRegWrite_3b3587015a3d20f4_def, non_mem_expI) + +lemma non_mem_exp_TPIDRRO_EL0_SysRegWrite_20bedffb2581e57d[non_mem_expI]: + "non_mem_exp (TPIDRRO_EL0_SysRegWrite_20bedffb2581e57d el op0 op1 CRn op2 CRm val_name)" + by (unfold TPIDRRO_EL0_SysRegWrite_20bedffb2581e57d_def, non_mem_expI) + +lemma non_mem_exp_TPIDR_EL0_SysRegWrite_6b1ef76c828f0bf5[non_mem_expI]: + "non_mem_exp (TPIDR_EL0_SysRegWrite_6b1ef76c828f0bf5 el op0 op1 CRn op2 CRm val_name)" + by (unfold TPIDR_EL0_SysRegWrite_6b1ef76c828f0bf5_def, non_mem_expI) + +lemma non_mem_exp_TPIDR_EL1_SysRegWrite_566127c19bf948d1[non_mem_expI]: + "non_mem_exp (TPIDR_EL1_SysRegWrite_566127c19bf948d1 el op0 op1 CRn op2 CRm val_name)" + by (unfold TPIDR_EL1_SysRegWrite_566127c19bf948d1_def, non_mem_expI) + +lemma non_mem_exp_TPIDR_EL2_SysRegWrite_adfab02a898d4b19[non_mem_expI]: + "non_mem_exp (TPIDR_EL2_SysRegWrite_adfab02a898d4b19 el op0 op1 CRn op2 CRm val_name)" + by (unfold TPIDR_EL2_SysRegWrite_adfab02a898d4b19_def, non_mem_expI) + +lemma non_mem_exp_TPIDR_EL3_SysRegWrite_08e0e9cc5d3f6f5c[non_mem_expI]: + "non_mem_exp (TPIDR_EL3_SysRegWrite_08e0e9cc5d3f6f5c el op0 op1 CRn op2 CRm val_name)" + by (unfold TPIDR_EL3_SysRegWrite_08e0e9cc5d3f6f5c_def, non_mem_expI) + +lemma non_mem_exp_TTBR0_EL12_SysRegWrite_fd9df8519bfad5c0[non_mem_expI]: + "non_mem_exp (TTBR0_EL12_SysRegWrite_fd9df8519bfad5c0 el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR0_EL12_SysRegWrite_fd9df8519bfad5c0_def, non_mem_expI) + +lemma non_mem_exp_TTBR0_EL1_SysRegWrite_8a149790a79e2eab[non_mem_expI]: + "non_mem_exp (TTBR0_EL1_SysRegWrite_8a149790a79e2eab el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR0_EL1_SysRegWrite_8a149790a79e2eab_def, non_mem_expI) + +lemma non_mem_exp_TTBR0_EL2_SysRegWrite_7cd39d4a24a70e7f[non_mem_expI]: + "non_mem_exp (TTBR0_EL2_SysRegWrite_7cd39d4a24a70e7f el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR0_EL2_SysRegWrite_7cd39d4a24a70e7f_def, non_mem_expI) + +lemma non_mem_exp_TTBR0_EL3_SysRegWrite_7e091a8effc9ee7f[non_mem_expI]: + "non_mem_exp (TTBR0_EL3_SysRegWrite_7e091a8effc9ee7f el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR0_EL3_SysRegWrite_7e091a8effc9ee7f_def, non_mem_expI) + +lemma non_mem_exp_TTBR1_EL12_SysRegWrite_4fbeb1f28c2e8107[non_mem_expI]: + "non_mem_exp (TTBR1_EL12_SysRegWrite_4fbeb1f28c2e8107 el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR1_EL12_SysRegWrite_4fbeb1f28c2e8107_def, non_mem_expI) + +lemma non_mem_exp_TTBR1_EL1_SysRegWrite_89690e4d3c87217b[non_mem_expI]: + "non_mem_exp (TTBR1_EL1_SysRegWrite_89690e4d3c87217b el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR1_EL1_SysRegWrite_89690e4d3c87217b_def, non_mem_expI) + +lemma non_mem_exp_TTBR1_EL2_SysRegWrite_59fad32bc548b47a[non_mem_expI]: + "non_mem_exp (TTBR1_EL2_SysRegWrite_59fad32bc548b47a el op0 op1 CRn op2 CRm val_name)" + by (unfold TTBR1_EL2_SysRegWrite_59fad32bc548b47a_def, non_mem_expI) + +lemma non_mem_exp_VBAR_EL12_SysRegWrite_a20f8f7f07b5cf7a[non_mem_expI]: + "non_mem_exp (VBAR_EL12_SysRegWrite_a20f8f7f07b5cf7a el op0 op1 CRn op2 CRm val_name)" + by (unfold VBAR_EL12_SysRegWrite_a20f8f7f07b5cf7a_def, non_mem_expI) + +lemma non_mem_exp_VBAR_EL1_SysRegWrite_29ba7540e032fce6[non_mem_expI]: + "non_mem_exp (VBAR_EL1_SysRegWrite_29ba7540e032fce6 el op0 op1 CRn op2 CRm val_name)" + by (unfold VBAR_EL1_SysRegWrite_29ba7540e032fce6_def, non_mem_expI) + +lemma non_mem_exp_VBAR_EL2_SysRegWrite_d5657e8591e8e22a[non_mem_expI]: + "non_mem_exp (VBAR_EL2_SysRegWrite_d5657e8591e8e22a el op0 op1 CRn op2 CRm val_name)" + by (unfold VBAR_EL2_SysRegWrite_d5657e8591e8e22a_def, non_mem_expI) + +lemma non_mem_exp_VBAR_EL3_SysRegWrite_1da603c27eb5f668[non_mem_expI]: + "non_mem_exp (VBAR_EL3_SysRegWrite_1da603c27eb5f668 el op0 op1 CRn op2 CRm val_name)" + by (unfold VBAR_EL3_SysRegWrite_1da603c27eb5f668_def, non_mem_expI) + +lemma non_mem_exp_VDISR_EL2_SysRegWrite_8b2c23874e253f64[non_mem_expI]: + "non_mem_exp (VDISR_EL2_SysRegWrite_8b2c23874e253f64 el op0 op1 CRn op2 CRm val_name)" + by (unfold VDISR_EL2_SysRegWrite_8b2c23874e253f64_def, non_mem_expI) + +lemma non_mem_exp_VMPIDR_EL2_SysRegWrite_c153d7c8b5628bd5[non_mem_expI]: + "non_mem_exp (VMPIDR_EL2_SysRegWrite_c153d7c8b5628bd5 el op0 op1 CRn op2 CRm val_name)" + by (unfold VMPIDR_EL2_SysRegWrite_c153d7c8b5628bd5_def, non_mem_expI) + +lemma non_mem_exp_VPIDR_EL2_SysRegWrite_0dbf139af5a73d1f[non_mem_expI]: + "non_mem_exp (VPIDR_EL2_SysRegWrite_0dbf139af5a73d1f el op0 op1 CRn op2 CRm val_name)" + by (unfold VPIDR_EL2_SysRegWrite_0dbf139af5a73d1f_def, non_mem_expI) + +lemma non_mem_exp_VSESR_EL2_SysRegWrite_e989f4bcf0ae8aa6[non_mem_expI]: + "non_mem_exp (VSESR_EL2_SysRegWrite_e989f4bcf0ae8aa6 el op0 op1 CRn op2 CRm val_name)" + by (unfold VSESR_EL2_SysRegWrite_e989f4bcf0ae8aa6_def, non_mem_expI) + +lemma non_mem_exp_VTCR_EL2_SysRegWrite_d49abb8b3aa0eff3[non_mem_expI]: + "non_mem_exp (VTCR_EL2_SysRegWrite_d49abb8b3aa0eff3 el op0 op1 CRn op2 CRm val_name)" + by (unfold VTCR_EL2_SysRegWrite_d49abb8b3aa0eff3_def, non_mem_expI) + +lemma non_mem_exp_VTTBR_EL2_SysRegWrite_5198ee0e793550a5[non_mem_expI]: + "non_mem_exp (VTTBR_EL2_SysRegWrite_5198ee0e793550a5 el op0 op1 CRn op2 CRm val_name)" + by (unfold VTTBR_EL2_SysRegWrite_5198ee0e793550a5_def, non_mem_expI) + +lemma non_mem_exp_AArch64_AutoGen_SysRegWrite[non_mem_expI]: + "non_mem_exp (AArch64_AutoGen_SysRegWrite el op0 op1 CRn op2 CRm val_name)" + by (unfold AArch64_AutoGen_SysRegWrite_def, non_mem_expI) + +lemma non_mem_exp_AArch64_IMPDEFResets[non_mem_expI]: + "non_mem_exp (AArch64_IMPDEFResets arg0)" + by (unfold AArch64_IMPDEFResets_def, non_mem_expI) + +lemma non_mem_exp_AArch64_AutoGen_ArchitectureReset[non_mem_expI]: + "non_mem_exp (AArch64_AutoGen_ArchitectureReset cold)" + by (unfold AArch64_AutoGen_ArchitectureReset_def, non_mem_expI) + +lemma non_mem_exp_AArch64_ResetControlRegisters[non_mem_expI]: + "non_mem_exp (AArch64_ResetControlRegisters cold)" + by (unfold AArch64_ResetControlRegisters_def, non_mem_expI) + +lemma non_mem_exp_C_set[non_mem_expI]: + "non_mem_exp (C_set n value_name)" + by (unfold C_set_def, non_mem_expI) + +lemma non_mem_exp_AArch64_ResetGeneralRegisters[non_mem_expI]: + "non_mem_exp (AArch64_ResetGeneralRegisters arg0)" + by (unfold AArch64_ResetGeneralRegisters_def, non_mem_expI) + +lemma non_mem_exp_AArch64_ResetSpecialRegisters[non_mem_expI]: + "non_mem_exp (AArch64_ResetSpecialRegisters arg0)" + by (unfold AArch64_ResetSpecialRegisters_def, non_mem_expI) + +lemma non_mem_exp_AArch64_TakeReset[non_mem_expI]: + "non_mem_exp (AArch64_TakeReset cold_reset)" + by (unfold AArch64_TakeReset_def, non_mem_expI) + +lemma non_mem_exp_TakeReset[non_mem_expI]: + "non_mem_exp (TakeReset cold)" + by (unfold TakeReset_def, non_mem_expI) + +lemma non_mem_exp_AArch64_SysRegWrite[non_mem_expI]: + "non_mem_exp (AArch64_SysRegWrite op0 op1 crn crm op2 val_name)" + by (unfold AArch64_SysRegWrite_def TakeReset_def AArch64_TakeReset_def AArch64_ResetControlRegisters_def AArch64_ResetSpecialRegisters_def AArch64_IMPDEFResets_def AArch64_AutoGen_ArchitectureReset_def MPAM2_EL2_read_def MPAM1_EL1_read_def MPAM2_EL2_write_def MPAM1_EL1_write_def ICC_CTLR_EL1_write_def ICC_CTLR_EL1_read_def Let_def bind_assoc, non_mem_expI intro: non_mem_exp_bind_no_asm non_mem_exp_if_no_asm) + +lemma non_mem_exp_CDBGDTR_EL0_CapSysRegWrite_336052f10e4a36b7[non_mem_expI]: + "non_mem_exp (CDBGDTR_EL0_CapSysRegWrite_336052f10e4a36b7 el op0 op1 CRn op2 CRm val_name)" + by (unfold CDBGDTR_EL0_CapSysRegWrite_336052f10e4a36b7_def, non_mem_expI) + +lemma non_mem_exp_CDLR_EL0_CapSysRegWrite_2763be7daadf3c03[non_mem_expI]: + "non_mem_exp (CDLR_EL0_CapSysRegWrite_2763be7daadf3c03 el op0 op1 CRn op2 CRm val_name)" + by (unfold CDLR_EL0_CapSysRegWrite_2763be7daadf3c03_def, non_mem_expI) + +lemma non_mem_exp_CELR_EL12_CapSysRegWrite_a1507df00ba9d725[non_mem_expI]: + "non_mem_exp (CELR_EL12_CapSysRegWrite_a1507df00ba9d725 el op0 op1 CRn op2 CRm val_name)" + by (unfold CELR_EL12_CapSysRegWrite_a1507df00ba9d725_def, non_mem_expI) + +lemma non_mem_exp_CELR_EL1_CapSysRegWrite_33a9b4f0fad89fe8[non_mem_expI]: + "non_mem_exp (CELR_EL1_CapSysRegWrite_33a9b4f0fad89fe8 el op0 op1 CRn op2 CRm val_name)" + by (unfold CELR_EL1_CapSysRegWrite_33a9b4f0fad89fe8_def, non_mem_expI) + +lemma non_mem_exp_CELR_EL2_CapSysRegWrite_8d32fe1dd5ad0417[non_mem_expI]: + "non_mem_exp (CELR_EL2_CapSysRegWrite_8d32fe1dd5ad0417 el op0 op1 CRn op2 CRm val_name)" + by (unfold CELR_EL2_CapSysRegWrite_8d32fe1dd5ad0417_def, non_mem_expI) + +lemma non_mem_exp_CELR_EL3_CapSysRegWrite_55e82fec5d907003[non_mem_expI]: + "non_mem_exp (CELR_EL3_CapSysRegWrite_55e82fec5d907003 el op0 op1 CRn op2 CRm val_name)" + by (unfold CELR_EL3_CapSysRegWrite_55e82fec5d907003_def, non_mem_expI) + +lemma non_mem_exp_CID_EL0_CapSysRegWrite_8c1c5cf69181759f[non_mem_expI]: + "non_mem_exp (CID_EL0_CapSysRegWrite_8c1c5cf69181759f el op0 op1 CRn op2 CRm val_name)" + by (unfold CID_EL0_CapSysRegWrite_8c1c5cf69181759f_def, non_mem_expI) + +lemma non_mem_exp_CSP_EL0_CapSysRegWrite_ee1d127810ef0f04[non_mem_expI]: + "non_mem_exp (CSP_EL0_CapSysRegWrite_ee1d127810ef0f04 el op0 op1 CRn op2 CRm val_name)" + by (unfold CSP_EL0_CapSysRegWrite_ee1d127810ef0f04_def, non_mem_expI) + +lemma non_mem_exp_CSP_EL1_CapSysRegWrite_f4579d836810c21a[non_mem_expI]: + "non_mem_exp (CSP_EL1_CapSysRegWrite_f4579d836810c21a el op0 op1 CRn op2 CRm val_name)" + by (unfold CSP_EL1_CapSysRegWrite_f4579d836810c21a_def, non_mem_expI) + +lemma non_mem_exp_CSP_EL2_CapSysRegWrite_59c69d74679ef283[non_mem_expI]: + "non_mem_exp (CSP_EL2_CapSysRegWrite_59c69d74679ef283 el op0 op1 CRn op2 CRm val_name)" + by (unfold CSP_EL2_CapSysRegWrite_59c69d74679ef283_def, non_mem_expI) + +lemma non_mem_exp_CTPIDRRO_EL0_CapSysRegWrite_e64109ff95ad4800[non_mem_expI]: + "non_mem_exp (CTPIDRRO_EL0_CapSysRegWrite_e64109ff95ad4800 el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDRRO_EL0_CapSysRegWrite_e64109ff95ad4800_def, non_mem_expI) + +lemma non_mem_exp_CTPIDR_EL0_CapSysRegWrite_8f94c4d256adadf0[non_mem_expI]: + "non_mem_exp (CTPIDR_EL0_CapSysRegWrite_8f94c4d256adadf0 el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDR_EL0_CapSysRegWrite_8f94c4d256adadf0_def, non_mem_expI) + +lemma non_mem_exp_CTPIDR_EL1_CapSysRegWrite_3190df090d2d128f[non_mem_expI]: + "non_mem_exp (CTPIDR_EL1_CapSysRegWrite_3190df090d2d128f el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDR_EL1_CapSysRegWrite_3190df090d2d128f_def, non_mem_expI) + +lemma non_mem_exp_CTPIDR_EL2_CapSysRegWrite_a740113e578c9b32[non_mem_expI]: + "non_mem_exp (CTPIDR_EL2_CapSysRegWrite_a740113e578c9b32 el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDR_EL2_CapSysRegWrite_a740113e578c9b32_def, non_mem_expI) + +lemma non_mem_exp_CTPIDR_EL3_CapSysRegWrite_376b7d525b15b21b[non_mem_expI]: + "non_mem_exp (CTPIDR_EL3_CapSysRegWrite_376b7d525b15b21b el op0 op1 CRn op2 CRm val_name)" + by (unfold CTPIDR_EL3_CapSysRegWrite_376b7d525b15b21b_def, non_mem_expI) + +lemma non_mem_exp_CVBAR_EL12_CapSysRegWrite_3fd157cf974c31e5[non_mem_expI]: + "non_mem_exp (CVBAR_EL12_CapSysRegWrite_3fd157cf974c31e5 el op0 op1 CRn op2 CRm val_name)" + by (unfold CVBAR_EL12_CapSysRegWrite_3fd157cf974c31e5_def, non_mem_expI) + +lemma non_mem_exp_CVBAR_EL1_CapSysRegWrite_bbad0575f41fce2f[non_mem_expI]: + "non_mem_exp (CVBAR_EL1_CapSysRegWrite_bbad0575f41fce2f el op0 op1 CRn op2 CRm val_name)" + by (unfold CVBAR_EL1_CapSysRegWrite_bbad0575f41fce2f_def, non_mem_expI) + +lemma non_mem_exp_CVBAR_EL2_CapSysRegWrite_2a412e2b2c0a0a2b[non_mem_expI]: + "non_mem_exp (CVBAR_EL2_CapSysRegWrite_2a412e2b2c0a0a2b el op0 op1 CRn op2 CRm val_name)" + by (unfold CVBAR_EL2_CapSysRegWrite_2a412e2b2c0a0a2b_def, non_mem_expI) + +lemma non_mem_exp_CVBAR_EL3_CapSysRegWrite_f3c8bbee84b292db[non_mem_expI]: + "non_mem_exp (CVBAR_EL3_CapSysRegWrite_f3c8bbee84b292db el op0 op1 CRn op2 CRm val_name)" + by (unfold CVBAR_EL3_CapSysRegWrite_f3c8bbee84b292db_def, non_mem_expI) + +lemma non_mem_exp_DDC_CapSysRegWrite_9bc98e4e82148914[non_mem_expI]: + "non_mem_exp (DDC_CapSysRegWrite_9bc98e4e82148914 el op0 op1 CRn op2 CRm val_name)" + by (unfold DDC_CapSysRegWrite_9bc98e4e82148914_def, non_mem_expI) + +lemma non_mem_exp_DDC_EL0_CapSysRegWrite_1a928678ff9b43a6[non_mem_expI]: + "non_mem_exp (DDC_EL0_CapSysRegWrite_1a928678ff9b43a6 el op0 op1 CRn op2 CRm val_name)" + by (unfold DDC_EL0_CapSysRegWrite_1a928678ff9b43a6_def, non_mem_expI) + +lemma non_mem_exp_DDC_EL1_CapSysRegWrite_e7ecb5b1f0c49d28[non_mem_expI]: + "non_mem_exp (DDC_EL1_CapSysRegWrite_e7ecb5b1f0c49d28 el op0 op1 CRn op2 CRm val_name)" + by (unfold DDC_EL1_CapSysRegWrite_e7ecb5b1f0c49d28_def, non_mem_expI) + +lemma non_mem_exp_DDC_EL2_CapSysRegWrite_b4142a2dcadf2a34[non_mem_expI]: + "non_mem_exp (DDC_EL2_CapSysRegWrite_b4142a2dcadf2a34 el op0 op1 CRn op2 CRm val_name)" + by (unfold DDC_EL2_CapSysRegWrite_b4142a2dcadf2a34_def, non_mem_expI) + +lemma non_mem_exp_RCSP_EL0_CapSysRegWrite_d8f83400674fbeeb[non_mem_expI]: + "non_mem_exp (RCSP_EL0_CapSysRegWrite_d8f83400674fbeeb el op0 op1 CRn op2 CRm val_name)" + by (unfold RCSP_EL0_CapSysRegWrite_d8f83400674fbeeb_def, non_mem_expI) + +lemma non_mem_exp_RCTPIDR_EL0_CapSysRegWrite_27f7c47e137c72f8[non_mem_expI]: + "non_mem_exp (RCTPIDR_EL0_CapSysRegWrite_27f7c47e137c72f8 el op0 op1 CRn op2 CRm val_name)" + by (unfold RCTPIDR_EL0_CapSysRegWrite_27f7c47e137c72f8_def, non_mem_expI) + +lemma non_mem_exp_RDDC_EL0_CapSysRegWrite_c528d1b2eb785ad7[non_mem_expI]: + "non_mem_exp (RDDC_EL0_CapSysRegWrite_c528d1b2eb785ad7 el op0 op1 CRn op2 CRm val_name)" + by (unfold RDDC_EL0_CapSysRegWrite_c528d1b2eb785ad7_def, non_mem_expI) + +lemma non_mem_exp_AArch64_AutoGen_CapSysRegWrite[non_mem_expI]: + "non_mem_exp (AArch64_AutoGen_CapSysRegWrite el op0 op1 CRn op2 CRm val_name)" + by (unfold AArch64_AutoGen_CapSysRegWrite_def, non_mem_expI) + +lemma non_mem_exp_DDC_set[non_mem_expI]: + "non_mem_exp (DDC_set value_name)" + by (unfold DDC_set_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CapSysRegWrite[non_mem_expI]: + "non_mem_exp (AArch64_CapSysRegWrite op0 op1 crn crm op2 val_name)" + by (unfold AArch64_CapSysRegWrite_def, non_mem_expI) + +lemma non_mem_exp_ALLE1IS_SysOpsWrite_8b81b55e2116aad3[non_mem_expI]: + "non_mem_exp (ALLE1IS_SysOpsWrite_8b81b55e2116aad3 el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE1IS_SysOpsWrite_8b81b55e2116aad3_def, non_mem_expI) + +lemma non_mem_exp_ALLE1_SysOpsWrite_69364bedc72cbe96[non_mem_expI]: + "non_mem_exp (ALLE1_SysOpsWrite_69364bedc72cbe96 el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE1_SysOpsWrite_69364bedc72cbe96_def, non_mem_expI) + +lemma non_mem_exp_AArch64_UndefinedFault[non_mem_expI]: + "non_mem_exp (AArch64_UndefinedFault arg0)" + by (unfold AArch64_UndefinedFault_def, non_mem_expI) + +lemma non_mem_exp_UndefinedFault[non_mem_expI]: + "non_mem_exp (UndefinedFault arg0)" + by (unfold UndefinedFault_def, non_mem_expI) + +lemma non_mem_exp_TLBI_ALLE2IS[non_mem_expI]: + "non_mem_exp (TLBI_ALLE2IS arg0)" + by (unfold TLBI_ALLE2IS_def, non_mem_expI) + +lemma non_mem_exp_ALLE2IS_SysOpsWrite_3a173239947b2c25[non_mem_expI]: + "non_mem_exp (ALLE2IS_SysOpsWrite_3a173239947b2c25 el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE2IS_SysOpsWrite_3a173239947b2c25_def, non_mem_expI) + +lemma non_mem_exp_TLBI_ALLE2[non_mem_expI]: + "non_mem_exp (TLBI_ALLE2 arg0)" + by (unfold TLBI_ALLE2_def, non_mem_expI) + +lemma non_mem_exp_ALLE2_SysOpsWrite_19c7b5110a5efe1d[non_mem_expI]: + "non_mem_exp (ALLE2_SysOpsWrite_19c7b5110a5efe1d el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE2_SysOpsWrite_19c7b5110a5efe1d_def, non_mem_expI) + +lemma non_mem_exp_ALLE3IS_SysOpsWrite_e64b79b4c41910fb[non_mem_expI]: + "non_mem_exp (ALLE3IS_SysOpsWrite_e64b79b4c41910fb el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE3IS_SysOpsWrite_e64b79b4c41910fb_def, non_mem_expI) + +lemma non_mem_exp_ALLE3_SysOpsWrite_5835ce2f987f3d36[non_mem_expI]: + "non_mem_exp (ALLE3_SysOpsWrite_5835ce2f987f3d36 el op0 op1 CRn op2 CRm val_name)" + by (unfold ALLE3_SysOpsWrite_5835ce2f987f3d36_def, non_mem_expI) + +lemma non_mem_exp_ASIDE1IS_SysOpsWrite_5a5dff91f113e41e[non_mem_expI]: + "non_mem_exp (ASIDE1IS_SysOpsWrite_5a5dff91f113e41e el op0 op1 CRn op2 CRm val_name)" + by (unfold ASIDE1IS_SysOpsWrite_5a5dff91f113e41e_def, non_mem_expI) + +lemma non_mem_exp_ASIDE1_SysOpsWrite_7ba7a3df395925e0[non_mem_expI]: + "non_mem_exp (ASIDE1_SysOpsWrite_7ba7a3df395925e0 el op0 op1 CRn op2 CRm val_name)" + by (unfold ASIDE1_SysOpsWrite_7ba7a3df395925e0_def, non_mem_expI) + +lemma non_mem_exp_DC_CISW[non_mem_expI]: + "non_mem_exp (DC_CISW val_name)" + by (unfold DC_CISW_def, non_mem_expI) + +lemma non_mem_exp_CISW_SysOpsWrite_5321b1c3157dccce[non_mem_expI]: + "non_mem_exp (CISW_SysOpsWrite_5321b1c3157dccce el op0 op1 CRn op2 CRm val_name)" + by (unfold CISW_SysOpsWrite_5321b1c3157dccce_def, non_mem_expI) + +lemma non_mem_exp_AArch64_BreakpointException[non_mem_expI]: + "non_mem_exp (AArch64_BreakpointException fault)" + by (unfold AArch64_BreakpointException_def, non_mem_expI) + +lemma non_mem_exp_AArch64_DataAbort[non_mem_expI]: + "non_mem_exp (AArch64_DataAbort vaddress fault)" + by (unfold AArch64_DataAbort_def, non_mem_expI) + +lemma non_mem_exp_AArch64_InstructionAbort[non_mem_expI]: + "non_mem_exp (AArch64_InstructionAbort vaddress fault)" + by (unfold AArch64_InstructionAbort_def, non_mem_expI) + +lemma non_mem_exp_AArch64_WatchpointException[non_mem_expI]: + "non_mem_exp (AArch64_WatchpointException vaddress fault)" + by (unfold AArch64_WatchpointException_def, non_mem_expI) + +lemma non_mem_exp_AArch64_Abort[non_mem_expI]: + "non_mem_exp (AArch64_Abort vaddress fault)" + by (unfold AArch64_Abort_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CheckBreakpoint[non_mem_expI]: + "non_mem_exp (AArch64_CheckBreakpoint vaddress size__arg)" + by (unfold AArch64_CheckBreakpoint_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CheckWatchpoint[non_mem_expI]: + "non_mem_exp (AArch64_CheckWatchpoint vaddress acctype iswrite size__arg)" + by (unfold AArch64_CheckWatchpoint_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CheckDebug[non_mem_expI]: + "non_mem_exp (AArch64_CheckDebug vaddress acctype iswrite size__arg)" + by (unfold AArch64_CheckDebug_def, non_mem_expI) + +lemma non_mem_exp_AArch64_TranslateAddressWithTag[non_mem_expI]: + "non_mem_exp (AArch64_TranslateAddressWithTag vaddress acctype iswrite wasaligned size__arg iswritevalidcap)" + by (unfold AArch64_TranslateAddressWithTag_def, non_mem_expI) + +lemma non_mem_exp_AArch64_TranslateAddress[non_mem_expI]: + "non_mem_exp (AArch64_TranslateAddress vaddress acctype iswrite wasaligned size__arg)" + by (unfold AArch64_TranslateAddress_def, non_mem_expI) + +lemma non_mem_exp_DC_CIVAC[non_mem_expI]: + "non_mem_exp (DC_CIVAC val_name)" + by (unfold DC_CIVAC_def, non_mem_expI) + +lemma non_mem_exp_VAddress[non_mem_expI]: + "non_mem_exp (VAddress addr)" + by (unfold VAddress_def, non_mem_expI) + +lemma non_mem_exp_MorelloCheckForCMO[non_mem_expI]: + "non_mem_exp (MorelloCheckForCMO cval requested_perms acctype)" + by (unfold MorelloCheckForCMO_def, non_mem_expI) + +lemma non_mem_exp_DC_CIVAC0[non_mem_expI]: + "non_mem_exp (DC_CIVAC0 val_name__arg)" + by (unfold DC_CIVAC0_def, non_mem_expI) + +lemma non_mem_exp_CIVAC_SysOpsWrite_47ad60ecb930d217[non_mem_expI]: + "non_mem_exp (CIVAC_SysOpsWrite_47ad60ecb930d217 el op0 op1 CRn op2 CRm val_name)" + by (unfold CIVAC_SysOpsWrite_47ad60ecb930d217_def, non_mem_expI) + +lemma non_mem_exp_DC_CSW[non_mem_expI]: + "non_mem_exp (DC_CSW val_name)" + by (unfold DC_CSW_def, non_mem_expI) + +lemma non_mem_exp_CSW_SysOpsWrite_9544819da3ebaa1b[non_mem_expI]: + "non_mem_exp (CSW_SysOpsWrite_9544819da3ebaa1b el op0 op1 CRn op2 CRm val_name)" + by (unfold CSW_SysOpsWrite_9544819da3ebaa1b_def, non_mem_expI) + +lemma non_mem_exp_DC_CVAC[non_mem_expI]: + "non_mem_exp (DC_CVAC val_name)" + by (unfold DC_CVAC_def, non_mem_expI) + +lemma non_mem_exp_DC_CVAC0[non_mem_expI]: + "non_mem_exp (DC_CVAC0 val_name__arg)" + by (unfold DC_CVAC0_def, non_mem_expI) + +lemma non_mem_exp_CVAC_SysOpsWrite_c7d2e911c691cc6b[non_mem_expI]: + "non_mem_exp (CVAC_SysOpsWrite_c7d2e911c691cc6b el op0 op1 CRn op2 CRm val_name)" + by (unfold CVAC_SysOpsWrite_c7d2e911c691cc6b_def, non_mem_expI) + +lemma non_mem_exp_DC_CVAP[non_mem_expI]: + "non_mem_exp (DC_CVAP val_name)" + by (unfold DC_CVAP_def, non_mem_expI) + +lemma non_mem_exp_DC_CVADP[non_mem_expI]: + "non_mem_exp (DC_CVADP val_name)" + by (unfold DC_CVADP_def, non_mem_expI) + +lemma non_mem_exp_CVADP_SysOpsWrite_9953ef108c01d34a[non_mem_expI]: + "non_mem_exp (CVADP_SysOpsWrite_9953ef108c01d34a el op0 op1 CRn op2 CRm val_name)" + by (unfold CVADP_SysOpsWrite_9953ef108c01d34a_def, non_mem_expI) + +lemma non_mem_exp_CVAP_SysOpsWrite_a43f75867888e74a[non_mem_expI]: + "non_mem_exp (CVAP_SysOpsWrite_a43f75867888e74a el op0 op1 CRn op2 CRm val_name)" + by (unfold CVAP_SysOpsWrite_a43f75867888e74a_def, non_mem_expI) + +lemma non_mem_exp_DC_CVAU[non_mem_expI]: + "non_mem_exp (DC_CVAU val_name)" + by (unfold DC_CVAU_def, non_mem_expI) + +lemma non_mem_exp_DC_CVAU0[non_mem_expI]: + "non_mem_exp (DC_CVAU0 val_name__arg)" + by (unfold DC_CVAU0_def, non_mem_expI) + +lemma non_mem_exp_CVAU_SysOpsWrite_4a72bbc98a17973c[non_mem_expI]: + "non_mem_exp (CVAU_SysOpsWrite_4a72bbc98a17973c el op0 op1 CRn op2 CRm val_name)" + by (unfold CVAU_SysOpsWrite_4a72bbc98a17973c_def, non_mem_expI) + +lemma non_mem_exp_IC_IALLUIS[non_mem_expI]: + "non_mem_exp (IC_IALLUIS arg0)" + by (unfold IC_IALLUIS_def, non_mem_expI) + +lemma non_mem_exp_IALLUIS_SysOpsWrite_9a906c8365100aff[non_mem_expI]: + "non_mem_exp (IALLUIS_SysOpsWrite_9a906c8365100aff el op0 op1 CRn op2 CRm val_name)" + by (unfold IALLUIS_SysOpsWrite_9a906c8365100aff_def, non_mem_expI) + +lemma non_mem_exp_IC_IALLU[non_mem_expI]: + "non_mem_exp (IC_IALLU arg0)" + by (unfold IC_IALLU_def, non_mem_expI) + +lemma non_mem_exp_IALLU_SysOpsWrite_81563797a4921929[non_mem_expI]: + "non_mem_exp (IALLU_SysOpsWrite_81563797a4921929 el op0 op1 CRn op2 CRm val_name)" + by (unfold IALLU_SysOpsWrite_81563797a4921929_def, non_mem_expI) + +lemma non_mem_exp_IPAS2E1IS_SysOpsWrite_ed4be1feae90b987[non_mem_expI]: + "non_mem_exp (IPAS2E1IS_SysOpsWrite_ed4be1feae90b987 el op0 op1 CRn op2 CRm val_name)" + by (unfold IPAS2E1IS_SysOpsWrite_ed4be1feae90b987_def, non_mem_expI) + +lemma non_mem_exp_IPAS2E1_SysOpsWrite_a65fef0d99f9428f[non_mem_expI]: + "non_mem_exp (IPAS2E1_SysOpsWrite_a65fef0d99f9428f el op0 op1 CRn op2 CRm val_name)" + by (unfold IPAS2E1_SysOpsWrite_a65fef0d99f9428f_def, non_mem_expI) + +lemma non_mem_exp_IPAS2LE1IS_SysOpsWrite_5a72848dfefa19f3[non_mem_expI]: + "non_mem_exp (IPAS2LE1IS_SysOpsWrite_5a72848dfefa19f3 el op0 op1 CRn op2 CRm val_name)" + by (unfold IPAS2LE1IS_SysOpsWrite_5a72848dfefa19f3_def, non_mem_expI) + +lemma non_mem_exp_IPAS2LE1_SysOpsWrite_10ca7ac6abdfed50[non_mem_expI]: + "non_mem_exp (IPAS2LE1_SysOpsWrite_10ca7ac6abdfed50 el op0 op1 CRn op2 CRm val_name)" + by (unfold IPAS2LE1_SysOpsWrite_10ca7ac6abdfed50_def, non_mem_expI) + +lemma non_mem_exp_DC_ISW[non_mem_expI]: + "non_mem_exp (DC_ISW val_name)" + by (unfold DC_ISW_def, non_mem_expI) + +lemma non_mem_exp_ISW_SysOpsWrite_d5fceb001aa0aa7a[non_mem_expI]: + "non_mem_exp (ISW_SysOpsWrite_d5fceb001aa0aa7a el op0 op1 CRn op2 CRm val_name)" + by (unfold ISW_SysOpsWrite_d5fceb001aa0aa7a_def, non_mem_expI) + +lemma non_mem_exp_DC_IVAC[non_mem_expI]: + "non_mem_exp (DC_IVAC val_name)" + by (unfold DC_IVAC_def, non_mem_expI) + +lemma non_mem_exp_DC_IVAC0[non_mem_expI]: + "non_mem_exp (DC_IVAC0 val_name__arg)" + by (unfold DC_IVAC0_def, non_mem_expI) + +lemma non_mem_exp_IVAC_SysOpsWrite_41b93e0e56e4f107[non_mem_expI]: + "non_mem_exp (IVAC_SysOpsWrite_41b93e0e56e4f107 el op0 op1 CRn op2 CRm val_name)" + by (unfold IVAC_SysOpsWrite_41b93e0e56e4f107_def, non_mem_expI) + +lemma non_mem_exp_IC_IVAU[non_mem_expI]: + "non_mem_exp (IC_IVAU val_name)" + by (unfold IC_IVAU_def, non_mem_expI) + +lemma non_mem_exp_IVAU_SysOpsWrite_2dfe97b748dd324e[non_mem_expI]: + "non_mem_exp (IVAU_SysOpsWrite_2dfe97b748dd324e el op0 op1 CRn op2 CRm val_name)" + by (unfold IVAU_SysOpsWrite_2dfe97b748dd324e_def, non_mem_expI) + +lemma non_mem_exp_RCTX_SysOpsWrite_bcc8cd10f2e68999[non_mem_expI]: + "non_mem_exp (RCTX_SysOpsWrite_bcc8cd10f2e68999 el op0 op1 CRn op2 CRm val_name)" + by (unfold RCTX_SysOpsWrite_bcc8cd10f2e68999_def, non_mem_expI) + +lemma non_mem_exp_RCTX_SysOpsWrite_c287513d0d3e8e92[non_mem_expI]: + "non_mem_exp (RCTX_SysOpsWrite_c287513d0d3e8e92 el op0 op1 CRn op2 CRm val_name)" + by (unfold RCTX_SysOpsWrite_c287513d0d3e8e92_def, non_mem_expI) + +lemma non_mem_exp_RCTX_SysOpsWrite_d614ec87236c038f[non_mem_expI]: + "non_mem_exp (RCTX_SysOpsWrite_d614ec87236c038f el op0 op1 CRn op2 CRm val_name)" + by (unfold RCTX_SysOpsWrite_d614ec87236c038f_def, non_mem_expI) + +lemma non_mem_exp_AArch64_AT_S1Ex[non_mem_expI]: + "non_mem_exp (AArch64_AT_S1Ex val_name el iswrite)" + by (unfold AArch64_AT_S1Ex_def, non_mem_expI) + +lemma non_mem_exp_AArch64_AT_S12Ex[non_mem_expI]: + "non_mem_exp (AArch64_AT_S12Ex val_name el iswrite)" + by (unfold AArch64_AT_S12Ex_def, non_mem_expI) + +lemma non_mem_exp_AT_S12E0R[non_mem_expI]: + "non_mem_exp (AT_S12E0R val_name)" + by (unfold AT_S12E0R_def, non_mem_expI) + +lemma non_mem_exp_AT_S1E0R[non_mem_expI]: + "non_mem_exp (AT_S1E0R val_name)" + by (unfold AT_S1E0R_def, non_mem_expI) + +lemma non_mem_exp_S12E0R_SysOpsWrite_4df3d544cba811b7[non_mem_expI]: + "non_mem_exp (S12E0R_SysOpsWrite_4df3d544cba811b7 el op0 op1 CRn op2 CRm val_name)" + by (unfold S12E0R_SysOpsWrite_4df3d544cba811b7_def, non_mem_expI) + +lemma non_mem_exp_AT_S12E0W[non_mem_expI]: + "non_mem_exp (AT_S12E0W val_name)" + by (unfold AT_S12E0W_def, non_mem_expI) + +lemma non_mem_exp_AT_S1E0W[non_mem_expI]: + "non_mem_exp (AT_S1E0W val_name)" + by (unfold AT_S1E0W_def, non_mem_expI) + +lemma non_mem_exp_S12E0W_SysOpsWrite_1dbb37d4af097406[non_mem_expI]: + "non_mem_exp (S12E0W_SysOpsWrite_1dbb37d4af097406 el op0 op1 CRn op2 CRm val_name)" + by (unfold S12E0W_SysOpsWrite_1dbb37d4af097406_def, non_mem_expI) + +lemma non_mem_exp_AT_S12E1R[non_mem_expI]: + "non_mem_exp (AT_S12E1R val_name)" + by (unfold AT_S12E1R_def, non_mem_expI) + +lemma non_mem_exp_AT_S1E1R[non_mem_expI]: + "non_mem_exp (AT_S1E1R val_name)" + by (unfold AT_S1E1R_def, non_mem_expI) + +lemma non_mem_exp_S12E1R_SysOpsWrite_e44276c8f24d398f[non_mem_expI]: + "non_mem_exp (S12E1R_SysOpsWrite_e44276c8f24d398f el op0 op1 CRn op2 CRm val_name)" + by (unfold S12E1R_SysOpsWrite_e44276c8f24d398f_def, non_mem_expI) + +lemma non_mem_exp_AT_S12E1W[non_mem_expI]: + "non_mem_exp (AT_S12E1W val_name)" + by (unfold AT_S12E1W_def, non_mem_expI) + +lemma non_mem_exp_AT_S1E1W[non_mem_expI]: + "non_mem_exp (AT_S1E1W val_name)" + by (unfold AT_S1E1W_def, non_mem_expI) + +lemma non_mem_exp_S12E1W_SysOpsWrite_c8b72d75cad90601[non_mem_expI]: + "non_mem_exp (S12E1W_SysOpsWrite_c8b72d75cad90601 el op0 op1 CRn op2 CRm val_name)" + by (unfold S12E1W_SysOpsWrite_c8b72d75cad90601_def, non_mem_expI) + +lemma non_mem_exp_S1E0R_SysOpsWrite_0a1e21ea5b4c8722[non_mem_expI]: + "non_mem_exp (S1E0R_SysOpsWrite_0a1e21ea5b4c8722 el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E0R_SysOpsWrite_0a1e21ea5b4c8722_def, non_mem_expI) + +lemma non_mem_exp_S1E0W_SysOpsWrite_d102d49fd92af65a[non_mem_expI]: + "non_mem_exp (S1E0W_SysOpsWrite_d102d49fd92af65a el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E0W_SysOpsWrite_d102d49fd92af65a_def, non_mem_expI) + +lemma non_mem_exp_AT_S1E1RP[non_mem_expI]: + "non_mem_exp (AT_S1E1RP val_name)" + by (unfold AT_S1E1RP_def, non_mem_expI) + +lemma non_mem_exp_S1E1RP_SysOpsWrite_4a6b1f71ee0182ab[non_mem_expI]: + "non_mem_exp (S1E1RP_SysOpsWrite_4a6b1f71ee0182ab el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E1RP_SysOpsWrite_4a6b1f71ee0182ab_def, non_mem_expI) + +lemma non_mem_exp_S1E1R_SysOpsWrite_018a577644c5d23c[non_mem_expI]: + "non_mem_exp (S1E1R_SysOpsWrite_018a577644c5d23c el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E1R_SysOpsWrite_018a577644c5d23c_def, non_mem_expI) + +lemma non_mem_exp_AT_S1E1WP[non_mem_expI]: + "non_mem_exp (AT_S1E1WP val_name)" + by (unfold AT_S1E1WP_def, non_mem_expI) + +lemma non_mem_exp_S1E1WP_SysOpsWrite_bb1ddb9112effe2a[non_mem_expI]: + "non_mem_exp (S1E1WP_SysOpsWrite_bb1ddb9112effe2a el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E1WP_SysOpsWrite_bb1ddb9112effe2a_def, non_mem_expI) + +lemma non_mem_exp_S1E1W_SysOpsWrite_df64f2f63c0911fd[non_mem_expI]: + "non_mem_exp (S1E1W_SysOpsWrite_df64f2f63c0911fd el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E1W_SysOpsWrite_df64f2f63c0911fd_def, non_mem_expI) + +lemma non_mem_exp_AT_S1E2R[non_mem_expI]: + "non_mem_exp (AT_S1E2R val_name)" + by (unfold AT_S1E2R_def, non_mem_expI) + +lemma non_mem_exp_S1E2R_SysOpsWrite_5e865a96c06417c8[non_mem_expI]: + "non_mem_exp (S1E2R_SysOpsWrite_5e865a96c06417c8 el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E2R_SysOpsWrite_5e865a96c06417c8_def, non_mem_expI) + +lemma non_mem_exp_AT_S1E2W[non_mem_expI]: + "non_mem_exp (AT_S1E2W val_name)" + by (unfold AT_S1E2W_def, non_mem_expI) + +lemma non_mem_exp_S1E2W_SysOpsWrite_1649806418453f02[non_mem_expI]: + "non_mem_exp (S1E2W_SysOpsWrite_1649806418453f02 el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E2W_SysOpsWrite_1649806418453f02_def, non_mem_expI) + +lemma non_mem_exp_AT_S1E3R[non_mem_expI]: + "non_mem_exp (AT_S1E3R val_name)" + by (unfold AT_S1E3R_def, non_mem_expI) + +lemma non_mem_exp_S1E3R_SysOpsWrite_6476f20e79e358be[non_mem_expI]: + "non_mem_exp (S1E3R_SysOpsWrite_6476f20e79e358be el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E3R_SysOpsWrite_6476f20e79e358be_def, non_mem_expI) + +lemma non_mem_exp_AT_S1E3W[non_mem_expI]: + "non_mem_exp (AT_S1E3W val_name)" + by (unfold AT_S1E3W_def, non_mem_expI) + +lemma non_mem_exp_S1E3W_SysOpsWrite_e92e083e28fa4dd0[non_mem_expI]: + "non_mem_exp (S1E3W_SysOpsWrite_e92e083e28fa4dd0 el op0 op1 CRn op2 CRm val_name)" + by (unfold S1E3W_SysOpsWrite_e92e083e28fa4dd0_def, non_mem_expI) + +lemma non_mem_exp_S1_op1_Cn_Cm_op2_SysOpsWrite_d6b17d94c0df44bc[non_mem_expI]: + "non_mem_exp (S1_op1_Cn_Cm_op2_SysOpsWrite_d6b17d94c0df44bc el op0 op1 CRn op2 CRm val_name)" + by (unfold S1_op1_Cn_Cm_op2_SysOpsWrite_d6b17d94c0df44bc_def, non_mem_expI) + +lemma non_mem_exp_VAAE1IS_SysOpsWrite_c22cd5a1dc8e7320[non_mem_expI]: + "non_mem_exp (VAAE1IS_SysOpsWrite_c22cd5a1dc8e7320 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAAE1IS_SysOpsWrite_c22cd5a1dc8e7320_def, non_mem_expI) + +lemma non_mem_exp_VAAE1_SysOpsWrite_8498b4db5afbed38[non_mem_expI]: + "non_mem_exp (VAAE1_SysOpsWrite_8498b4db5afbed38 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAAE1_SysOpsWrite_8498b4db5afbed38_def, non_mem_expI) + +lemma non_mem_exp_VAALE1IS_SysOpsWrite_5c8056a5b649fe2e[non_mem_expI]: + "non_mem_exp (VAALE1IS_SysOpsWrite_5c8056a5b649fe2e el op0 op1 CRn op2 CRm val_name)" + by (unfold VAALE1IS_SysOpsWrite_5c8056a5b649fe2e_def, non_mem_expI) + +lemma non_mem_exp_VAALE1_SysOpsWrite_d3bec3a19881fb1c[non_mem_expI]: + "non_mem_exp (VAALE1_SysOpsWrite_d3bec3a19881fb1c el op0 op1 CRn op2 CRm val_name)" + by (unfold VAALE1_SysOpsWrite_d3bec3a19881fb1c_def, non_mem_expI) + +lemma non_mem_exp_VAE1IS_SysOpsWrite_5eac1ac5cb4e76ff[non_mem_expI]: + "non_mem_exp (VAE1IS_SysOpsWrite_5eac1ac5cb4e76ff el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE1IS_SysOpsWrite_5eac1ac5cb4e76ff_def, non_mem_expI) + +lemma non_mem_exp_VAE1_SysOpsWrite_09dbfc0bf1b19b11[non_mem_expI]: + "non_mem_exp (VAE1_SysOpsWrite_09dbfc0bf1b19b11 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE1_SysOpsWrite_09dbfc0bf1b19b11_def, non_mem_expI) + +lemma non_mem_exp_TLBI_VAE2IS[non_mem_expI]: + "non_mem_exp (TLBI_VAE2IS val_name)" + by (unfold TLBI_VAE2IS_def, non_mem_expI) + +lemma non_mem_exp_VAE2IS_SysOpsWrite_f81411101129df7b[non_mem_expI]: + "non_mem_exp (VAE2IS_SysOpsWrite_f81411101129df7b el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE2IS_SysOpsWrite_f81411101129df7b_def, non_mem_expI) + +lemma non_mem_exp_TLBI_VAE2[non_mem_expI]: + "non_mem_exp (TLBI_VAE2 val_name)" + by (unfold TLBI_VAE2_def, non_mem_expI) + +lemma non_mem_exp_VAE2_SysOpsWrite_78002df18993a4b5[non_mem_expI]: + "non_mem_exp (VAE2_SysOpsWrite_78002df18993a4b5 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE2_SysOpsWrite_78002df18993a4b5_def, non_mem_expI) + +lemma non_mem_exp_VAE3IS_SysOpsWrite_7dc759c51bb69ced[non_mem_expI]: + "non_mem_exp (VAE3IS_SysOpsWrite_7dc759c51bb69ced el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE3IS_SysOpsWrite_7dc759c51bb69ced_def, non_mem_expI) + +lemma non_mem_exp_VAE3_SysOpsWrite_90b5c3b60d3bd152[non_mem_expI]: + "non_mem_exp (VAE3_SysOpsWrite_90b5c3b60d3bd152 el op0 op1 CRn op2 CRm val_name)" + by (unfold VAE3_SysOpsWrite_90b5c3b60d3bd152_def, non_mem_expI) + +lemma non_mem_exp_VALE1IS_SysOpsWrite_7bb7ad05a900b833[non_mem_expI]: + "non_mem_exp (VALE1IS_SysOpsWrite_7bb7ad05a900b833 el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE1IS_SysOpsWrite_7bb7ad05a900b833_def, non_mem_expI) + +lemma non_mem_exp_VALE1_SysOpsWrite_c1766c627b3960ca[non_mem_expI]: + "non_mem_exp (VALE1_SysOpsWrite_c1766c627b3960ca el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE1_SysOpsWrite_c1766c627b3960ca_def, non_mem_expI) + +lemma non_mem_exp_TLBI_VALE2IS[non_mem_expI]: + "non_mem_exp (TLBI_VALE2IS val_name)" + by (unfold TLBI_VALE2IS_def, non_mem_expI) + +lemma non_mem_exp_VALE2IS_SysOpsWrite_a1084cefbce599af[non_mem_expI]: + "non_mem_exp (VALE2IS_SysOpsWrite_a1084cefbce599af el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE2IS_SysOpsWrite_a1084cefbce599af_def, non_mem_expI) + +lemma non_mem_exp_TLBI_VALE2[non_mem_expI]: + "non_mem_exp (TLBI_VALE2 val_name)" + by (unfold TLBI_VALE2_def, non_mem_expI) + +lemma non_mem_exp_VALE2_SysOpsWrite_dce4b2b057d036da[non_mem_expI]: + "non_mem_exp (VALE2_SysOpsWrite_dce4b2b057d036da el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE2_SysOpsWrite_dce4b2b057d036da_def, non_mem_expI) + +lemma non_mem_exp_VALE3IS_SysOpsWrite_8b70cb86db2abfcd[non_mem_expI]: + "non_mem_exp (VALE3IS_SysOpsWrite_8b70cb86db2abfcd el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE3IS_SysOpsWrite_8b70cb86db2abfcd_def, non_mem_expI) + +lemma non_mem_exp_VALE3_SysOpsWrite_df1f91b1bea42ec8[non_mem_expI]: + "non_mem_exp (VALE3_SysOpsWrite_df1f91b1bea42ec8 el op0 op1 CRn op2 CRm val_name)" + by (unfold VALE3_SysOpsWrite_df1f91b1bea42ec8_def, non_mem_expI) + +lemma non_mem_exp_VMALLE1IS_SysOpsWrite_08cfba716c4ca8db[non_mem_expI]: + "non_mem_exp (VMALLE1IS_SysOpsWrite_08cfba716c4ca8db el op0 op1 CRn op2 CRm val_name)" + by (unfold VMALLE1IS_SysOpsWrite_08cfba716c4ca8db_def, non_mem_expI) + +lemma non_mem_exp_VMALLE1_SysOpsWrite_c64f2572b311d9b9[non_mem_expI]: + "non_mem_exp (VMALLE1_SysOpsWrite_c64f2572b311d9b9 el op0 op1 CRn op2 CRm val_name)" + by (unfold VMALLE1_SysOpsWrite_c64f2572b311d9b9_def, non_mem_expI) + +lemma non_mem_exp_VMALLS12E1IS_SysOpsWrite_92a1ba1461a19d4c[non_mem_expI]: + "non_mem_exp (VMALLS12E1IS_SysOpsWrite_92a1ba1461a19d4c el op0 op1 CRn op2 CRm val_name)" + by (unfold VMALLS12E1IS_SysOpsWrite_92a1ba1461a19d4c_def, non_mem_expI) + +lemma non_mem_exp_VMALLS12E1_SysOpsWrite_8f5c303094061f20[non_mem_expI]: + "non_mem_exp (VMALLS12E1_SysOpsWrite_8f5c303094061f20 el op0 op1 CRn op2 CRm val_name)" + by (unfold VMALLS12E1_SysOpsWrite_8f5c303094061f20_def, non_mem_expI) + +lemma non_mem_exp_AArch64_SysInstrWithResult[non_mem_expI]: + "non_mem_exp (AArch64_SysInstrWithResult op0 op1 crn crm op2)" + by (unfold AArch64_SysInstrWithResult_def, non_mem_expI) + +lemma non_mem_exp_AArch64_FPTrappedException[non_mem_expI]: + "non_mem_exp (AArch64_FPTrappedException is_ase element accumulated_exceptions)" + by (unfold AArch64_FPTrappedException_def, non_mem_expI) + +lemma non_mem_exp_FPProcessException[non_mem_expI]: + "non_mem_exp (FPProcessException exception fpcr)" + by (unfold FPProcessException_def, non_mem_expI) + +lemma non_mem_exp_FPRoundBase[non_mem_expI]: + "non_mem_exp (FPRoundBase arg0 arg1 arg2 arg3 arg4)" + by (unfold FPRoundBase_def, non_mem_expI) + +lemma non_mem_exp_FPRound[non_mem_expI]: + "non_mem_exp (FPRound N op fpcr__arg rounding)" + by (unfold FPRound_def, non_mem_expI) + +lemma non_mem_exp_FPRound__1[non_mem_expI]: + "non_mem_exp (FPRound__1 N op fpcr)" + by (unfold FPRound__1_def, non_mem_expI) + +lemma non_mem_exp_FixedToFP[non_mem_expI]: + "non_mem_exp (FixedToFP N op fbits is_unsigned fpcr rounding)" + by (unfold FixedToFP_def, non_mem_expI) + +lemma non_mem_exp_FPProcessNaN[non_mem_expI]: + "non_mem_exp (FPProcessNaN fptype op fpcr)" + by (unfold FPProcessNaN_def, non_mem_expI) + +lemma non_mem_exp_FPProcessNaNs[non_mem_expI]: + "non_mem_exp (FPProcessNaNs type1 type2 op1 op2 fpcr)" + by (unfold FPProcessNaNs_def, non_mem_expI) + +lemma non_mem_exp_FPUnpackBase[non_mem_expI]: + "non_mem_exp (FPUnpackBase fpval fpcr)" + by (unfold FPUnpackBase_def, non_mem_expI) + +lemma non_mem_exp_FPUnpack[non_mem_expI]: + "non_mem_exp (FPUnpack fpval fpcr__arg)" + by (unfold FPUnpack_def, non_mem_expI) + +lemma non_mem_exp_FPAdd[non_mem_expI]: + "non_mem_exp (FPAdd op1 op2 fpcr)" + by (unfold FPAdd_def, non_mem_expI) + +lemma non_mem_exp_FPCompare[non_mem_expI]: + "non_mem_exp (FPCompare op1 op2 signal_nans fpcr)" + by (unfold FPCompare_def, non_mem_expI) + +lemma non_mem_exp_FPCompareEQ[non_mem_expI]: + "non_mem_exp (FPCompareEQ op1 op2 fpcr)" + by (unfold FPCompareEQ_def, non_mem_expI) + +lemma non_mem_exp_FPCompareGE[non_mem_expI]: + "non_mem_exp (FPCompareGE op1 op2 fpcr)" + by (unfold FPCompareGE_def, non_mem_expI) + +lemma non_mem_exp_FPCompareGT[non_mem_expI]: + "non_mem_exp (FPCompareGT op1 op2 fpcr)" + by (unfold FPCompareGT_def, non_mem_expI) + +lemma non_mem_exp_FPRoundCV[non_mem_expI]: + "non_mem_exp (FPRoundCV N op fpcr__arg rounding)" + by (unfold FPRoundCV_def, non_mem_expI) + +lemma non_mem_exp_FPUnpackCV[non_mem_expI]: + "non_mem_exp (FPUnpackCV fpval fpcr__arg)" + by (unfold FPUnpackCV_def, non_mem_expI) + +lemma non_mem_exp_FPConvert[non_mem_expI]: + "non_mem_exp (FPConvert l__604 op fpcr rounding)" + by (unfold FPConvert_def, non_mem_expI) + +lemma non_mem_exp_FPConvert__1[non_mem_expI]: + "non_mem_exp (FPConvert__1 M op fpcr)" + by (unfold FPConvert__1_def, non_mem_expI) + +lemma non_mem_exp_FPDiv[non_mem_expI]: + "non_mem_exp (FPDiv op1 op2 fpcr)" + by (unfold FPDiv_def, non_mem_expI) + +lemma non_mem_exp_FPMax[non_mem_expI]: + "non_mem_exp (FPMax op1 op2 fpcr)" + by (unfold FPMax_def, non_mem_expI) + +lemma non_mem_exp_FPMaxNum[non_mem_expI]: + "non_mem_exp (FPMaxNum op1__arg op2__arg fpcr)" + by (unfold FPMaxNum_def, non_mem_expI) + +lemma non_mem_exp_FPMin[non_mem_expI]: + "non_mem_exp (FPMin op1 op2 fpcr)" + by (unfold FPMin_def, non_mem_expI) + +lemma non_mem_exp_FPMinNum[non_mem_expI]: + "non_mem_exp (FPMinNum op1__arg op2__arg fpcr)" + by (unfold FPMinNum_def, non_mem_expI) + +lemma non_mem_exp_FPMul[non_mem_expI]: + "non_mem_exp (FPMul op1 op2 fpcr)" + by (unfold FPMul_def, non_mem_expI) + +lemma non_mem_exp_FPProcessNaNs3[non_mem_expI]: + "non_mem_exp (FPProcessNaNs3 type1 type2 type3 op1 op2 op3 fpcr)" + by (unfold FPProcessNaNs3_def, non_mem_expI) + +lemma non_mem_exp_FPMulAdd[non_mem_expI]: + "non_mem_exp (FPMulAdd addend op1 op2 fpcr)" + by (unfold FPMulAdd_def, non_mem_expI) + +lemma non_mem_exp_FPMulX[non_mem_expI]: + "non_mem_exp (FPMulX op1 op2 fpcr)" + by (unfold FPMulX_def, non_mem_expI) + +lemma non_mem_exp_FPRecipEstimate[non_mem_expI]: + "non_mem_exp (FPRecipEstimate operand fpcr)" + by (unfold FPRecipEstimate_def, non_mem_expI) + +lemma non_mem_exp_FPRecpX[non_mem_expI]: + "non_mem_exp (FPRecpX l__583 op fpcr)" + by (unfold FPRecpX_def, non_mem_expI) + +lemma non_mem_exp_FPRoundInt[non_mem_expI]: + "non_mem_exp (FPRoundInt op fpcr rounding exact)" + by (unfold FPRoundInt_def, non_mem_expI) + +lemma non_mem_exp_FPRSqrtEstimate[non_mem_expI]: + "non_mem_exp (FPRSqrtEstimate operand fpcr)" + by (unfold FPRSqrtEstimate_def, non_mem_expI) + +lemma non_mem_exp_FPSqrt[non_mem_expI]: + "non_mem_exp (FPSqrt op fpcr)" + by (unfold FPSqrt_def, non_mem_expI) + +lemma non_mem_exp_FPSub[non_mem_expI]: + "non_mem_exp (FPSub op1 op2 fpcr)" + by (unfold FPSub_def, non_mem_expI) + +lemma non_mem_exp_FPToFixed[non_mem_expI]: + "non_mem_exp (FPToFixed M op fbits is_unsigned fpcr rounding)" + by (unfold FPToFixed_def, non_mem_expI) + +lemma non_mem_exp_BranchXToCapability[non_mem_expI]: + "non_mem_exp (BranchXToCapability target__arg branch_type)" + by (unfold BranchXToCapability_def, non_mem_expI) + +lemma non_mem_exp_BranchToOffset[non_mem_expI]: + "non_mem_exp (BranchToOffset offset branch_type)" + by (unfold BranchToOffset_def, non_mem_expI) + +lemma non_mem_exp_X_set[non_mem_expI]: + "non_mem_exp (X_set width n value_name)" + by (unfold X_set_def, non_mem_expI) + +lemma non_mem_exp_X_read[non_mem_expI]: + "non_mem_exp (X_read width n)" + by (unfold X_read_def, non_mem_expI) + +lemma non_mem_exp_C_read[non_mem_expI]: + "non_mem_exp (C_read n)" + by (unfold C_read_def, non_mem_expI) + +lemma non_mem_exp_SP_set[non_mem_expI]: + "non_mem_exp (SP_set width value_name)" + by (unfold SP_set_def, non_mem_expI) + +lemma non_mem_exp_SP_read[non_mem_expI]: + "non_mem_exp (SP_read width)" + by (unfold SP_read_def, non_mem_expI) + +lemma non_mem_exp_CSP_set[non_mem_expI]: + "non_mem_exp (CSP_set value_name)" + by (unfold CSP_set_def, non_mem_expI) + +lemma non_mem_exp_CSP_read[non_mem_expI]: + "non_mem_exp (CSP_read arg0)" + by (unfold CSP_read_def, non_mem_expI) + +lemma non_mem_exp_PC_read[non_mem_expI]: + "non_mem_exp (PC_read arg0)" + by (unfold PC_read_def, non_mem_expI) + +lemma non_mem_exp_AArch64_SPAlignmentFault[non_mem_expI]: + "non_mem_exp (AArch64_SPAlignmentFault arg0)" + by (unfold AArch64_SPAlignmentFault_def, non_mem_expI) + +lemma non_mem_exp_CheckSPAlignment[non_mem_expI]: + "non_mem_exp (CheckSPAlignment arg0)" + by (unfold CheckSPAlignment_def, non_mem_expI) + +lemma non_mem_exp_BaseReg_read[non_mem_expI]: + "non_mem_exp (BaseReg_read n is_prefetch)" + by (unfold BaseReg_read_def, non_mem_expI) + +lemma non_mem_exp_BaseReg_read__1[non_mem_expI]: + "non_mem_exp (BaseReg_read__1 n)" + by (unfold BaseReg_read__1_def, non_mem_expI) + +lemma non_mem_exp_AltBaseReg_read[non_mem_expI]: + "non_mem_exp (AltBaseReg_read n is_prefetch)" + by (unfold AltBaseReg_read_def, non_mem_expI) + +lemma non_mem_exp_AltBaseReg_read__1[non_mem_expI]: + "non_mem_exp (AltBaseReg_read__1 n)" + by (unfold AltBaseReg_read__1_def, non_mem_expI) + +lemma non_mem_exp_BaseReg_set[non_mem_expI]: + "non_mem_exp (BaseReg_set n address)" + by (unfold BaseReg_set_def, non_mem_expI) + +lemma non_mem_exp_ELR_read[non_mem_expI]: + "non_mem_exp (ELR_read el)" + by (unfold ELR_read_def, non_mem_expI) + +lemma non_mem_exp_ELR_read__1[non_mem_expI]: + "non_mem_exp (ELR_read__1 arg0)" + by (unfold ELR_read__1_def, non_mem_expI) + +lemma non_mem_exp_CELR_read[non_mem_expI]: + "non_mem_exp (CELR_read el)" + by (unfold CELR_read_def, non_mem_expI) + +lemma non_mem_exp_CELR_read__1[non_mem_expI]: + "non_mem_exp (CELR_read__1 arg0)" + by (unfold CELR_read__1_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CheckSystemAccess[non_mem_expI]: + "non_mem_exp (AArch64_CheckSystemAccess op0 op1 crn crm op2 rt read)" + by (unfold AArch64_CheckSystemAccess_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CheckAlignment[non_mem_expI]: + "non_mem_exp (AArch64_CheckAlignment address alignment acctype iswrite)" + by (unfold AArch64_CheckAlignment_def, non_mem_expI) + +lemma non_mem_exp_CheckLoadTagsPermission[non_mem_expI]: + "non_mem_exp (CheckLoadTagsPermission desc acctype)" + by (unfold CheckLoadTagsPermission_def, non_mem_expI) + +lemma non_mem_exp_CheckStoreTagsPermission[non_mem_expI]: + "non_mem_exp (CheckStoreTagsPermission desc acctype)" + by (unfold CheckStoreTagsPermission_def, non_mem_expI) + +lemma non_mem_exp_CheckCapabilityAlignment[non_mem_expI]: + "non_mem_exp (CheckCapabilityAlignment address acctype iswrite)" + by (unfold CheckCapabilityAlignment_def, non_mem_expI) + +lemma non_mem_exp_CheckCapabilityStorePairAlignment[non_mem_expI]: + "non_mem_exp (CheckCapabilityStorePairAlignment address acctype iswrite)" + by (unfold CheckCapabilityStorePairAlignment_def, non_mem_expI) + +lemma non_mem_exp_AArch64_TranslateAddressForAtomicAccess[non_mem_expI]: + "non_mem_exp (AArch64_TranslateAddressForAtomicAccess address sizeinbits)" + by (unfold AArch64_TranslateAddressForAtomicAccess_def, non_mem_expI) + +lemma non_mem_exp_CheckCapability[non_mem_expI]: + "non_mem_exp (CheckCapability c__arg address size__arg requested_perms acctype)" + by (unfold CheckCapability_def, non_mem_expI) + +lemma non_mem_exp_VACheckAddress[non_mem_expI]: + "non_mem_exp (VACheckAddress base addr64 size__arg requested_perms acctype)" + by (unfold VACheckAddress_def, non_mem_expI) + +lemma non_mem_exp_CapSquashPostLoadCap[non_mem_expI]: + "non_mem_exp (CapSquashPostLoadCap data__arg addr)" + by (unfold CapSquashPostLoadCap_def, non_mem_expI) + +lemma non_mem_exp_AArch64_SetExclusiveMonitors[non_mem_expI]: + "non_mem_exp (AArch64_SetExclusiveMonitors address size__arg)" + by (unfold AArch64_SetExclusiveMonitors_def, non_mem_expI) + +lemma non_mem_exp_AArch64_ExclusiveMonitorsPass[non_mem_expI]: + "non_mem_exp (AArch64_ExclusiveMonitorsPass address size__arg)" + by (unfold AArch64_ExclusiveMonitorsPass_def, non_mem_expI) + +lemma non_mem_exp_FPRecipStepFused[non_mem_expI]: + "non_mem_exp (FPRecipStepFused op1__arg op2)" + by (unfold FPRecipStepFused_def, non_mem_expI) + +lemma non_mem_exp_FPRSqrtStepFused[non_mem_expI]: + "non_mem_exp (FPRSqrtStepFused op1__arg op2)" + by (unfold FPRSqrtStepFused_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CallSecureMonitor[non_mem_expI]: + "non_mem_exp (AArch64_CallSecureMonitor immediate)" + by (unfold AArch64_CallSecureMonitor_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CallHypervisor[non_mem_expI]: + "non_mem_exp (AArch64_CallHypervisor immediate)" + by (unfold AArch64_CallHypervisor_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CallSupervisor[non_mem_expI]: + "non_mem_exp (AArch64_CallSupervisor immediate)" + by (unfold AArch64_CallSupervisor_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CheckIllegalState[non_mem_expI]: + "non_mem_exp (AArch64_CheckIllegalState arg0)" + by (unfold AArch64_CheckIllegalState_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CheckForSMCUndefOrTrap[non_mem_expI]: + "non_mem_exp (AArch64_CheckForSMCUndefOrTrap imm)" + by (unfold AArch64_CheckForSMCUndefOrTrap_def, non_mem_expI) + +lemma non_mem_exp_AArch64_WFxTrap[non_mem_expI]: + "non_mem_exp (AArch64_WFxTrap target_el is_wfe)" + by (unfold AArch64_WFxTrap_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CheckForWFxTrap[non_mem_expI]: + "non_mem_exp (AArch64_CheckForWFxTrap target_el is_wfe)" + by (unfold AArch64_CheckForWFxTrap_def, non_mem_expI) + +lemma non_mem_exp_AArch64_AdvSIMDFPAccessTrap[non_mem_expI]: + "non_mem_exp (AArch64_AdvSIMDFPAccessTrap target_el)" + by (unfold AArch64_AdvSIMDFPAccessTrap_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CheckFPAdvSIMDTrap[non_mem_expI]: + "non_mem_exp (AArch64_CheckFPAdvSIMDTrap arg0)" + by (unfold AArch64_CheckFPAdvSIMDTrap_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CheckFPAdvSIMDEnabled[non_mem_expI]: + "non_mem_exp (AArch64_CheckFPAdvSIMDEnabled arg0)" + by (unfold AArch64_CheckFPAdvSIMDEnabled_def, non_mem_expI) + +lemma non_mem_exp_CheckFPAdvSIMDEnabled64[non_mem_expI]: + "non_mem_exp (CheckFPAdvSIMDEnabled64 arg0)" + by (unfold CheckFPAdvSIMDEnabled64_def, non_mem_expI) + +lemma non_mem_exp_CapabilityAccessTrap[non_mem_expI]: + "non_mem_exp (CapabilityAccessTrap target_el)" + by (unfold CapabilityAccessTrap_def, non_mem_expI) + +lemma non_mem_exp_CheckCapabilitiesEnabled[non_mem_expI]: + "non_mem_exp (CheckCapabilitiesEnabled arg0)" + by (unfold CheckCapabilitiesEnabled_def, non_mem_expI) + +lemma non_mem_exp_AArch64_TakePhysicalIRQException[non_mem_expI]: + "non_mem_exp (AArch64_TakePhysicalIRQException arg0)" + by (unfold AArch64_TakePhysicalIRQException_def, non_mem_expI) + +lemma non_mem_exp_AArch64_SoftwareBreakpoint[non_mem_expI]: + "non_mem_exp (AArch64_SoftwareBreakpoint immediate)" + by (unfold AArch64_SoftwareBreakpoint_def, non_mem_expI) + +lemma non_mem_exp_AArch64_PCAlignmentFault[non_mem_expI]: + "non_mem_exp (AArch64_PCAlignmentFault arg0)" + by (unfold AArch64_PCAlignmentFault_def, non_mem_expI) + +lemma non_mem_exp_AArch64_CheckPCAlignment[non_mem_expI]: + "non_mem_exp (AArch64_CheckPCAlignment arg0)" + by (unfold AArch64_CheckPCAlignment_def, non_mem_expI) + +lemma non_mem_exp_CheckPCCCapability[non_mem_expI]: + "non_mem_exp (CheckPCCCapability arg0)" + by (unfold CheckPCCCapability_def, non_mem_expI) + +lemma non_mem_exp_AArch64_ExceptionReturnToCapability[non_mem_expI]: + "non_mem_exp (AArch64_ExceptionReturnToCapability new_pcc__arg spsr)" + by (unfold AArch64_ExceptionReturnToCapability_def, non_mem_expI) + +lemma non_mem_exp_ExtendReg[non_mem_expI]: + "non_mem_exp (ExtendReg N reg exttype shift)" + by (unfold ExtendReg_def, non_mem_expI) + +lemma non_mem_exp_ShiftReg[non_mem_expI]: + "non_mem_exp (ShiftReg N reg shiftype amount)" + by (unfold ShiftReg_def, non_mem_expI) + +lemma non_mem_exp_ReduceCombine[non_mem_expI]: + "non_mem_exp (ReduceCombine op lo hi)" + by (unfold ReduceCombine_def, non_mem_expI) + +lemma non_mem_exp_Reduce16[non_mem_expI]: + "non_mem_exp (Reduce16 op input esize)" + by (unfold Reduce16_def, non_mem_expI) + +lemma non_mem_exp_Reduce32[non_mem_expI]: + "non_mem_exp (Reduce32 op input esize)" + by (unfold Reduce32_def, non_mem_expI) + +lemma non_mem_exp_Reduce64[non_mem_expI]: + "non_mem_exp (Reduce64 op input esize)" + by (unfold Reduce64_def, non_mem_expI) + +lemma non_mem_exp_Reduce128[non_mem_expI]: + "non_mem_exp (Reduce128 op input esize)" + by (unfold Reduce128_def, non_mem_expI) + +lemma non_mem_exp_Reduce256[non_mem_expI]: + "non_mem_exp (Reduce256 op input esize)" + by (unfold Reduce256_def, non_mem_expI) + +lemma non_mem_exp_Reduce512[non_mem_expI]: + "non_mem_exp (Reduce512 op input esize)" + by (unfold Reduce512_def, non_mem_expI) + +lemma non_mem_exp_Reduce1024[non_mem_expI]: + "non_mem_exp (Reduce1024 op input esize)" + by (unfold Reduce1024_def, non_mem_expI) + +lemma non_mem_exp_Reduce2048[non_mem_expI]: + "non_mem_exp (Reduce2048 op input esize)" + by (unfold Reduce2048_def, non_mem_expI) + +lemma non_mem_exp_Reduce[non_mem_expI]: + "non_mem_exp (Reduce op input esize)" + by (unfold Reduce_def, non_mem_expI) + +lemma non_mem_exp_DCPSInstruction[non_mem_expI]: + "non_mem_exp (DCPSInstruction target_el)" + by (unfold DCPSInstruction_def, non_mem_expI) + +lemma non_mem_exp_DRPSInstruction[non_mem_expI]: + "non_mem_exp (DRPSInstruction arg0)" + by (unfold DRPSInstruction_def, non_mem_expI) + +lemma non_mem_exp_VACheckPerm[non_mem_expI]: + "non_mem_exp (VACheckPerm base requested_perms)" + by (unfold VACheckPerm_def, non_mem_expI) + +lemma non_mem_exp_CAP_DC_CIVAC[non_mem_expI]: + "non_mem_exp (CAP_DC_CIVAC cval)" + by (unfold CAP_DC_CIVAC_def, non_mem_expI) + +lemma non_mem_exp_CAP_DC_CVAC[non_mem_expI]: + "non_mem_exp (CAP_DC_CVAC cval)" + by (unfold CAP_DC_CVAC_def, non_mem_expI) + +lemma non_mem_exp_CAP_DC_CVADP[non_mem_expI]: + "non_mem_exp (CAP_DC_CVADP cval)" + by (unfold CAP_DC_CVADP_def, non_mem_expI) + +lemma non_mem_exp_CAP_DC_CVAP[non_mem_expI]: + "non_mem_exp (CAP_DC_CVAP cval)" + by (unfold CAP_DC_CVAP_def, non_mem_expI) + +lemma non_mem_exp_CAP_DC_CVAU[non_mem_expI]: + "non_mem_exp (CAP_DC_CVAU cval)" + by (unfold CAP_DC_CVAU_def, non_mem_expI) + +lemma non_mem_exp_CAP_DC_IVAC[non_mem_expI]: + "non_mem_exp (CAP_DC_IVAC cval)" + by (unfold CAP_DC_IVAC_def, non_mem_expI) + +lemma non_mem_exp_CAP_IC_IVAU[non_mem_expI]: + "non_mem_exp (CAP_IC_IVAU cval)" + by (unfold CAP_IC_IVAU_def, non_mem_expI) + +lemma non_mem_exp_Step_PC[non_mem_expI]: + "non_mem_exp (Step_PC arg0)" + by (unfold Step_PC_def, non_mem_expI) + +lemma non_mem_exp_execute_ADD_C_CIS_C[non_mem_expI]: + "non_mem_exp (execute_ADD_C_CIS_C d imm n)" + by (unfold execute_ADD_C_CIS_C_def, non_mem_expI) + +lemma non_mem_exp_decode_ADD_C_CIS_C[non_mem_expI]: + "non_mem_exp (decode_ADD_C_CIS_C A sh imm12 Cn Cd)" + by (unfold decode_ADD_C_CIS_C_def, non_mem_expI) + +lemma non_mem_exp_execute_ADD_C_CRI_C[non_mem_expI]: + "non_mem_exp (execute_ADD_C_CRI_C d extend_type m n shift)" + by (unfold execute_ADD_C_CRI_C_def, non_mem_expI) + +lemma non_mem_exp_decode_ADD_C_CRI_C[non_mem_expI]: + "non_mem_exp (decode_ADD_C_CRI_C Rm option_name imm3 Cn Cd)" + by (unfold decode_ADD_C_CRI_C_def, non_mem_expI) + +lemma non_mem_exp_execute_ADRDP_C_ID_C[non_mem_expI]: + "non_mem_exp (execute_ADRDP_C_ID_C P d imm)" + by (unfold execute_ADRDP_C_ID_C_def, non_mem_expI) + +lemma non_mem_exp_decode_ADRDP_C_ID_C[non_mem_expI]: + "non_mem_exp (decode_ADRDP_C_ID_C op immlo P immhi Rd)" + by (unfold decode_ADRDP_C_ID_C_def, non_mem_expI) + +lemma non_mem_exp_execute_ADRP_C_IP_C[non_mem_expI]: + "non_mem_exp (execute_ADRP_C_IP_C P d imm)" + by (unfold execute_ADRP_C_IP_C_def, non_mem_expI) + +lemma non_mem_exp_decode_ADRP_C_IP_C[non_mem_expI]: + "non_mem_exp (decode_ADRP_C_IP_C op immlo P immhi Rd)" + by (unfold decode_ADRP_C_IP_C_def, non_mem_expI) + +lemma non_mem_exp_execute_ADRP_C_I_C[non_mem_expI]: + "non_mem_exp (execute_ADRP_C_I_C P d imm)" + by (unfold execute_ADRP_C_I_C_def, non_mem_expI) + +lemma non_mem_exp_decode_ADRP_C_I_C[non_mem_expI]: + "non_mem_exp (decode_ADRP_C_I_C op immlo P immhi Rd)" + by (unfold decode_ADRP_C_I_C_def, non_mem_expI) + +lemma non_mem_exp_execute_ADR_C_I_C[non_mem_expI]: + "non_mem_exp (execute_ADR_C_I_C d imm)" + by (unfold execute_ADR_C_I_C_def, non_mem_expI) + +lemma non_mem_exp_decode_ADR_C_I_C[non_mem_expI]: + "non_mem_exp (decode_ADR_C_I_C op immlo P immhi Rd)" + by (unfold decode_ADR_C_I_C_def, non_mem_expI) + +lemma non_mem_exp_execute_ALIGND_C_CI_C[non_mem_expI]: + "non_mem_exp (execute_ALIGND_C_CI_C align d n)" + by (unfold execute_ALIGND_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_decode_ALIGND_C_CI_C[non_mem_expI]: + "non_mem_exp (decode_ALIGND_C_CI_C imm6 U Cn Cd)" + by (unfold decode_ALIGND_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_execute_ALIGNU_C_CI_C[non_mem_expI]: + "non_mem_exp (execute_ALIGNU_C_CI_C align d n)" + by (unfold execute_ALIGNU_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_decode_ALIGNU_C_CI_C[non_mem_expI]: + "non_mem_exp (decode_ALIGNU_C_CI_C imm6 U Cn Cd)" + by (unfold decode_ALIGNU_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_execute_BICFLGS_C_CI_C[non_mem_expI]: + "non_mem_exp (execute_BICFLGS_C_CI_C d mask__arg n)" + by (unfold execute_BICFLGS_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_decode_BICFLGS_C_CI_C[non_mem_expI]: + "non_mem_exp (decode_BICFLGS_C_CI_C imm8 Cn Cd)" + by (unfold decode_BICFLGS_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_execute_BICFLGS_C_CR_C[non_mem_expI]: + "non_mem_exp (execute_BICFLGS_C_CR_C d m n)" + by (unfold execute_BICFLGS_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_decode_BICFLGS_C_CR_C[non_mem_expI]: + "non_mem_exp (decode_BICFLGS_C_CR_C Rm opc Cn Cd)" + by (unfold decode_BICFLGS_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_execute_BLRR_C_C[non_mem_expI]: + "non_mem_exp (execute_BLRR_C_C branch_type n)" + by (unfold execute_BLRR_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_BLRR_C_C[non_mem_expI]: + "non_mem_exp (decode_BLRR_C_C opc Cn)" + by (unfold decode_BLRR_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_BLRS_C_C[non_mem_expI]: + "non_mem_exp (execute_BLRS_C_C branch_type n)" + by (unfold execute_BLRS_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_BLRS_C_C[non_mem_expI]: + "non_mem_exp (decode_BLRS_C_C opc Cn)" + by (unfold decode_BLRS_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_BLRS_C_C_C[non_mem_expI]: + "non_mem_exp (execute_BLRS_C_C_C branch_type m n)" + by (unfold execute_BLRS_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_BLRS_C_C_C[non_mem_expI]: + "non_mem_exp (decode_BLRS_C_C_C Cm opc Cn)" + by (unfold decode_BLRS_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_BLR_C_C[non_mem_expI]: + "non_mem_exp (execute_BLR_C_C branch_type n)" + by (unfold execute_BLR_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_BLR_C_C[non_mem_expI]: + "non_mem_exp (decode_BLR_C_C opc Cn)" + by (unfold decode_BLR_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_BRR_C_C[non_mem_expI]: + "non_mem_exp (execute_BRR_C_C branch_type n)" + by (unfold execute_BRR_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_BRR_C_C[non_mem_expI]: + "non_mem_exp (decode_BRR_C_C opc Cn)" + by (unfold decode_BRR_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_BRS_C_C[non_mem_expI]: + "non_mem_exp (execute_BRS_C_C branch_type n)" + by (unfold execute_BRS_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_BRS_C_C[non_mem_expI]: + "non_mem_exp (decode_BRS_C_C opc Cn)" + by (unfold decode_BRS_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_BRS_C_C_C[non_mem_expI]: + "non_mem_exp (execute_BRS_C_C_C branch_type m n)" + by (unfold execute_BRS_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_BRS_C_C_C[non_mem_expI]: + "non_mem_exp (decode_BRS_C_C_C Cm opc Cn)" + by (unfold decode_BRS_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_BR_C_C[non_mem_expI]: + "non_mem_exp (execute_BR_C_C branch_type n)" + by (unfold execute_BR_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_BR_C_C[non_mem_expI]: + "non_mem_exp (decode_BR_C_C opc Cn)" + by (unfold decode_BR_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_BUILD_C_C_C[non_mem_expI]: + "non_mem_exp (execute_BUILD_C_C_C d m n)" + by (unfold execute_BUILD_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_BUILD_C_C_C[non_mem_expI]: + "non_mem_exp (decode_BUILD_C_C_C Cm opc Cn Cd)" + by (unfold decode_BUILD_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_BX___C[non_mem_expI]: + "non_mem_exp (execute_BX___C branch_type)" + by (unfold execute_BX___C_def, non_mem_expI) + +lemma non_mem_exp_decode_BX___C[non_mem_expI]: + "non_mem_exp (decode_BX___C opc)" + by (unfold decode_BX___C_def, non_mem_expI) + +lemma non_mem_exp_execute_CFHI_R_C_C[non_mem_expI]: + "non_mem_exp (execute_CFHI_R_C_C d n)" + by (unfold execute_CFHI_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CFHI_R_C_C[non_mem_expI]: + "non_mem_exp (decode_CFHI_R_C_C opc Cn Rd)" + by (unfold decode_CFHI_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CHKEQ___CC_C[non_mem_expI]: + "non_mem_exp (execute_CHKEQ___CC_C m n)" + by (unfold execute_CHKEQ___CC_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CHKEQ___CC_C[non_mem_expI]: + "non_mem_exp (decode_CHKEQ___CC_C Cm opc Cn)" + by (unfold decode_CHKEQ___CC_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CHKSLD_C_C[non_mem_expI]: + "non_mem_exp (execute_CHKSLD_C_C n)" + by (unfold execute_CHKSLD_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CHKSLD_C_C[non_mem_expI]: + "non_mem_exp (decode_CHKSLD_C_C opc Cn)" + by (unfold decode_CHKSLD_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CHKSSU_C_CC_C[non_mem_expI]: + "non_mem_exp (execute_CHKSSU_C_CC_C d m n)" + by (unfold execute_CHKSSU_C_CC_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CHKSSU_C_CC_C[non_mem_expI]: + "non_mem_exp (decode_CHKSSU_C_CC_C Cm opc Cn Cd)" + by (unfold decode_CHKSSU_C_CC_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CHKSS___CC_C[non_mem_expI]: + "non_mem_exp (execute_CHKSS___CC_C m n)" + by (unfold execute_CHKSS___CC_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CHKSS___CC_C[non_mem_expI]: + "non_mem_exp (decode_CHKSS___CC_C Cm opc Cn)" + by (unfold decode_CHKSS___CC_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CHKTGD_C_C[non_mem_expI]: + "non_mem_exp (execute_CHKTGD_C_C n)" + by (unfold execute_CHKTGD_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CHKTGD_C_C[non_mem_expI]: + "non_mem_exp (decode_CHKTGD_C_C opc Cn)" + by (unfold decode_CHKTGD_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CLRPERM_C_CI_C[non_mem_expI]: + "non_mem_exp (execute_CLRPERM_C_CI_C d imm n)" + by (unfold execute_CLRPERM_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CLRPERM_C_CI_C[non_mem_expI]: + "non_mem_exp (decode_CLRPERM_C_CI_C perm__arg Cn Cd)" + by (unfold decode_CLRPERM_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CLRPERM_C_CR_C[non_mem_expI]: + "non_mem_exp (execute_CLRPERM_C_CR_C d m n)" + by (unfold execute_CLRPERM_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CLRPERM_C_CR_C[non_mem_expI]: + "non_mem_exp (decode_CLRPERM_C_CR_C Rm Cn Cd)" + by (unfold decode_CLRPERM_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CLRTAG_C_C_C[non_mem_expI]: + "non_mem_exp (execute_CLRTAG_C_C_C d n)" + by (unfold execute_CLRTAG_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CLRTAG_C_C_C[non_mem_expI]: + "non_mem_exp (decode_CLRTAG_C_C_C opc Cn Cd)" + by (unfold decode_CLRTAG_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CPYTYPE_C_C_C[non_mem_expI]: + "non_mem_exp (execute_CPYTYPE_C_C_C d m n)" + by (unfold execute_CPYTYPE_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CPYTYPE_C_C_C[non_mem_expI]: + "non_mem_exp (decode_CPYTYPE_C_C_C Cm opc Cn Cd)" + by (unfold decode_CPYTYPE_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CPYVALUE_C_C_C[non_mem_expI]: + "non_mem_exp (execute_CPYVALUE_C_C_C d m n)" + by (unfold execute_CPYVALUE_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CPYVALUE_C_C_C[non_mem_expI]: + "non_mem_exp (decode_CPYVALUE_C_C_C Cm opc Cn Cd)" + by (unfold decode_CPYVALUE_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CPY_C_C_C[non_mem_expI]: + "non_mem_exp (execute_CPY_C_C_C d n)" + by (unfold execute_CPY_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CPY_C_C_C[non_mem_expI]: + "non_mem_exp (decode_CPY_C_C_C opc Cn Cd)" + by (unfold decode_CPY_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CSEAL_C_C_C[non_mem_expI]: + "non_mem_exp (execute_CSEAL_C_C_C d m n)" + by (unfold execute_CSEAL_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CSEAL_C_C_C[non_mem_expI]: + "non_mem_exp (decode_CSEAL_C_C_C Cm opc Cn Cd)" + by (unfold decode_CSEAL_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CSEL_C_CI_C[non_mem_expI]: + "non_mem_exp (execute_CSEL_C_CI_C cond d m n)" + by (unfold execute_CSEL_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CSEL_C_CI_C[non_mem_expI]: + "non_mem_exp (decode_CSEL_C_CI_C Cm cond Cn Cd)" + by (unfold decode_CSEL_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CTHI_C_CR_C[non_mem_expI]: + "non_mem_exp (execute_CTHI_C_CR_C d m n)" + by (unfold execute_CTHI_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CTHI_C_CR_C[non_mem_expI]: + "non_mem_exp (decode_CTHI_C_CR_C Rm opc Cn Cd)" + by (unfold decode_CTHI_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CVTDZ_C_R_C[non_mem_expI]: + "non_mem_exp (execute_CVTDZ_C_R_C d n)" + by (unfold execute_CVTDZ_C_R_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CVTDZ_C_R_C[non_mem_expI]: + "non_mem_exp (decode_CVTDZ_C_R_C opc Rn Cd)" + by (unfold decode_CVTDZ_C_R_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CVTD_C_R_C[non_mem_expI]: + "non_mem_exp (execute_CVTD_C_R_C d n)" + by (unfold execute_CVTD_C_R_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CVTD_C_R_C[non_mem_expI]: + "non_mem_exp (decode_CVTD_C_R_C opc Rn Cd)" + by (unfold decode_CVTD_C_R_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CVTD_R_C_C[non_mem_expI]: + "non_mem_exp (execute_CVTD_R_C_C d n)" + by (unfold execute_CVTD_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CVTD_R_C_C[non_mem_expI]: + "non_mem_exp (decode_CVTD_R_C_C opc Cn Rd)" + by (unfold decode_CVTD_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CVTPZ_C_R_C[non_mem_expI]: + "non_mem_exp (execute_CVTPZ_C_R_C d n)" + by (unfold execute_CVTPZ_C_R_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CVTPZ_C_R_C[non_mem_expI]: + "non_mem_exp (decode_CVTPZ_C_R_C opc Rn Cd)" + by (unfold decode_CVTPZ_C_R_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CVTP_C_R_C[non_mem_expI]: + "non_mem_exp (execute_CVTP_C_R_C d n)" + by (unfold execute_CVTP_C_R_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CVTP_C_R_C[non_mem_expI]: + "non_mem_exp (decode_CVTP_C_R_C opc Rn Cd)" + by (unfold decode_CVTP_C_R_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CVTP_R_C_C[non_mem_expI]: + "non_mem_exp (execute_CVTP_R_C_C d n)" + by (unfold execute_CVTP_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CVTP_R_C_C[non_mem_expI]: + "non_mem_exp (decode_CVTP_R_C_C opc Cn Rd)" + by (unfold decode_CVTP_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CVTZ_C_CR_C[non_mem_expI]: + "non_mem_exp (execute_CVTZ_C_CR_C d m n)" + by (unfold execute_CVTZ_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CVTZ_C_CR_C[non_mem_expI]: + "non_mem_exp (decode_CVTZ_C_CR_C Rm Cn Cd)" + by (unfold decode_CVTZ_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CVT_C_CR_C[non_mem_expI]: + "non_mem_exp (execute_CVT_C_CR_C d m n)" + by (unfold execute_CVT_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CVT_C_CR_C[non_mem_expI]: + "non_mem_exp (decode_CVT_C_CR_C Rm Cn Cd)" + by (unfold decode_CVT_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_execute_CVT_R_CC_C[non_mem_expI]: + "non_mem_exp (execute_CVT_R_CC_C d m n)" + by (unfold execute_CVT_R_CC_C_def, non_mem_expI) + +lemma non_mem_exp_decode_CVT_R_CC_C[non_mem_expI]: + "non_mem_exp (decode_CVT_R_CC_C Cm Cn Rd)" + by (unfold decode_CVT_R_CC_C_def, non_mem_expI) + +lemma non_mem_exp_execute_EORFLGS_C_CI_C[non_mem_expI]: + "non_mem_exp (execute_EORFLGS_C_CI_C d mask__arg n)" + by (unfold execute_EORFLGS_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_decode_EORFLGS_C_CI_C[non_mem_expI]: + "non_mem_exp (decode_EORFLGS_C_CI_C imm8 Cn Cd)" + by (unfold decode_EORFLGS_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_execute_EORFLGS_C_CR_C[non_mem_expI]: + "non_mem_exp (execute_EORFLGS_C_CR_C d m n)" + by (unfold execute_EORFLGS_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_decode_EORFLGS_C_CR_C[non_mem_expI]: + "non_mem_exp (decode_EORFLGS_C_CR_C Rm opc Cn Cd)" + by (unfold decode_EORFLGS_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_execute_GCBASE_R_C_C[non_mem_expI]: + "non_mem_exp (execute_GCBASE_R_C_C d n)" + by (unfold execute_GCBASE_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_GCBASE_R_C_C[non_mem_expI]: + "non_mem_exp (decode_GCBASE_R_C_C opc Cn Rd)" + by (unfold decode_GCBASE_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_GCFLGS_R_C_C[non_mem_expI]: + "non_mem_exp (execute_GCFLGS_R_C_C d n)" + by (unfold execute_GCFLGS_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_GCFLGS_R_C_C[non_mem_expI]: + "non_mem_exp (decode_GCFLGS_R_C_C opc Cn Rd)" + by (unfold decode_GCFLGS_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_GCLEN_R_C_C[non_mem_expI]: + "non_mem_exp (execute_GCLEN_R_C_C d n)" + by (unfold execute_GCLEN_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_GCLEN_R_C_C[non_mem_expI]: + "non_mem_exp (decode_GCLEN_R_C_C opc Cn Rd)" + by (unfold decode_GCLEN_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_GCLIM_R_C_C[non_mem_expI]: + "non_mem_exp (execute_GCLIM_R_C_C d n)" + by (unfold execute_GCLIM_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_GCLIM_R_C_C[non_mem_expI]: + "non_mem_exp (decode_GCLIM_R_C_C opc Cn Rd)" + by (unfold decode_GCLIM_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_GCOFF_R_C_C[non_mem_expI]: + "non_mem_exp (execute_GCOFF_R_C_C d n)" + by (unfold execute_GCOFF_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_GCOFF_R_C_C[non_mem_expI]: + "non_mem_exp (decode_GCOFF_R_C_C opc Cn Rd)" + by (unfold decode_GCOFF_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_GCPERM_R_C_C[non_mem_expI]: + "non_mem_exp (execute_GCPERM_R_C_C d n)" + by (unfold execute_GCPERM_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_GCPERM_R_C_C[non_mem_expI]: + "non_mem_exp (decode_GCPERM_R_C_C opc Cn Rd)" + by (unfold decode_GCPERM_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_GCSEAL_R_C_C[non_mem_expI]: + "non_mem_exp (execute_GCSEAL_R_C_C d n)" + by (unfold execute_GCSEAL_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_GCSEAL_R_C_C[non_mem_expI]: + "non_mem_exp (decode_GCSEAL_R_C_C opc Cn Rd)" + by (unfold decode_GCSEAL_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_GCTAG_R_C_C[non_mem_expI]: + "non_mem_exp (execute_GCTAG_R_C_C d n)" + by (unfold execute_GCTAG_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_GCTAG_R_C_C[non_mem_expI]: + "non_mem_exp (decode_GCTAG_R_C_C opc Cn Rd)" + by (unfold decode_GCTAG_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_GCTYPE_R_C_C[non_mem_expI]: + "non_mem_exp (execute_GCTYPE_R_C_C d n)" + by (unfold execute_GCTYPE_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_GCTYPE_R_C_C[non_mem_expI]: + "non_mem_exp (decode_GCTYPE_R_C_C opc Cn Rd)" + by (unfold decode_GCTYPE_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_GCVALUE_R_C_C[non_mem_expI]: + "non_mem_exp (execute_GCVALUE_R_C_C d n)" + by (unfold execute_GCVALUE_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_GCVALUE_R_C_C[non_mem_expI]: + "non_mem_exp (decode_GCVALUE_R_C_C opc Cn Rd)" + by (unfold decode_GCVALUE_R_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_MRS_C_I_C[non_mem_expI]: + "non_mem_exp (execute_MRS_C_I_C sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg)" + by (unfold execute_MRS_C_I_C_def, non_mem_expI) + +lemma non_mem_exp_decode_MRS_C_I_C[non_mem_expI]: + "non_mem_exp (decode_MRS_C_I_C L o0 op1 CRn CRm op2 Ct)" + by (unfold decode_MRS_C_I_C_def, non_mem_expI) + +lemma non_mem_exp_execute_MSR_C_I_C[non_mem_expI]: + "non_mem_exp (execute_MSR_C_I_C sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg)" + by (unfold execute_MSR_C_I_C_def, non_mem_expI) + +lemma non_mem_exp_decode_MSR_C_I_C[non_mem_expI]: + "non_mem_exp (decode_MSR_C_I_C L o0 op1 CRn CRm op2 Ct)" + by (unfold decode_MSR_C_I_C_def, non_mem_expI) + +lemma non_mem_exp_execute_ORRFLGS_C_CI_C[non_mem_expI]: + "non_mem_exp (execute_ORRFLGS_C_CI_C d mask__arg n)" + by (unfold execute_ORRFLGS_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_decode_ORRFLGS_C_CI_C[non_mem_expI]: + "non_mem_exp (decode_ORRFLGS_C_CI_C imm8 Cn Cd)" + by (unfold decode_ORRFLGS_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_execute_ORRFLGS_C_CR_C[non_mem_expI]: + "non_mem_exp (execute_ORRFLGS_C_CR_C d m n)" + by (unfold execute_ORRFLGS_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_decode_ORRFLGS_C_CR_C[non_mem_expI]: + "non_mem_exp (decode_ORRFLGS_C_CR_C Rm opc Cn Cd)" + by (unfold decode_ORRFLGS_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_execute_RETR_C_C[non_mem_expI]: + "non_mem_exp (execute_RETR_C_C branch_type n)" + by (unfold execute_RETR_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_RETR_C_C[non_mem_expI]: + "non_mem_exp (decode_RETR_C_C opc Cn)" + by (unfold decode_RETR_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_RETS_C_C[non_mem_expI]: + "non_mem_exp (execute_RETS_C_C branch_type n)" + by (unfold execute_RETS_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_RETS_C_C[non_mem_expI]: + "non_mem_exp (decode_RETS_C_C opc Cn)" + by (unfold decode_RETS_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_RETS_C_C_C[non_mem_expI]: + "non_mem_exp (execute_RETS_C_C_C branch_type m n)" + by (unfold execute_RETS_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_RETS_C_C_C[non_mem_expI]: + "non_mem_exp (decode_RETS_C_C_C Cm opc Cn)" + by (unfold decode_RETS_C_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_RET_C_C[non_mem_expI]: + "non_mem_exp (execute_RET_C_C branch_type n)" + by (unfold execute_RET_C_C_def, non_mem_expI) + +lemma non_mem_exp_decode_RET_C_C[non_mem_expI]: + "non_mem_exp (decode_RET_C_C opc Cn)" + by (unfold decode_RET_C_C_def, non_mem_expI) + +lemma non_mem_exp_execute_RRLEN_R_R_C[non_mem_expI]: + "non_mem_exp (execute_RRLEN_R_R_C d n)" + by (unfold execute_RRLEN_R_R_C_def, non_mem_expI) + +lemma non_mem_exp_decode_RRLEN_R_R_C[non_mem_expI]: + "non_mem_exp (decode_RRLEN_R_R_C opc Rn Rd)" + by (unfold decode_RRLEN_R_R_C_def, non_mem_expI) + +lemma non_mem_exp_execute_RRMASK_R_R_C[non_mem_expI]: + "non_mem_exp (execute_RRMASK_R_R_C d n)" + by (unfold execute_RRMASK_R_R_C_def, non_mem_expI) + +lemma non_mem_exp_decode_RRMASK_R_R_C[non_mem_expI]: + "non_mem_exp (decode_RRMASK_R_R_C opc Rn Rd)" + by (unfold decode_RRMASK_R_R_C_def, non_mem_expI) + +lemma non_mem_exp_execute_SCBNDSE_C_CR_C[non_mem_expI]: + "non_mem_exp (execute_SCBNDSE_C_CR_C d m n)" + by (unfold execute_SCBNDSE_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_decode_SCBNDSE_C_CR_C[non_mem_expI]: + "non_mem_exp (decode_SCBNDSE_C_CR_C Rm opc Cn Cd)" + by (unfold decode_SCBNDSE_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_execute_SCBNDS_C_CI_C[non_mem_expI]: + "non_mem_exp (execute_SCBNDS_C_CI_C d length__arg n)" + by (unfold execute_SCBNDS_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_decode_SCBNDS_C_CI_C[non_mem_expI]: + "non_mem_exp (decode_SCBNDS_C_CI_C imm6 S Cn Cd)" + by (unfold decode_SCBNDS_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_execute_SCBNDS_C_CI_S[non_mem_expI]: + "non_mem_exp (execute_SCBNDS_C_CI_S d length__arg n)" + by (unfold execute_SCBNDS_C_CI_S_def, non_mem_expI) + +lemma non_mem_exp_decode_SCBNDS_C_CI_S[non_mem_expI]: + "non_mem_exp (decode_SCBNDS_C_CI_S imm6 S Cn Cd)" + by (unfold decode_SCBNDS_C_CI_S_def, non_mem_expI) + +lemma non_mem_exp_execute_SCBNDS_C_CR_C[non_mem_expI]: + "non_mem_exp (execute_SCBNDS_C_CR_C d m n)" + by (unfold execute_SCBNDS_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_decode_SCBNDS_C_CR_C[non_mem_expI]: + "non_mem_exp (decode_SCBNDS_C_CR_C Rm opc Cn Cd)" + by (unfold decode_SCBNDS_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_execute_SCFLGS_C_CR_C[non_mem_expI]: + "non_mem_exp (execute_SCFLGS_C_CR_C d m n)" + by (unfold execute_SCFLGS_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_decode_SCFLGS_C_CR_C[non_mem_expI]: + "non_mem_exp (decode_SCFLGS_C_CR_C Rm Cn Cd)" + by (unfold decode_SCFLGS_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_execute_SCOFF_C_CR_C[non_mem_expI]: + "non_mem_exp (execute_SCOFF_C_CR_C d m n)" + by (unfold execute_SCOFF_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_decode_SCOFF_C_CR_C[non_mem_expI]: + "non_mem_exp (decode_SCOFF_C_CR_C Rm opc Cn Cd)" + by (unfold decode_SCOFF_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_execute_SCTAG_C_CR_C[non_mem_expI]: + "non_mem_exp (execute_SCTAG_C_CR_C d m n)" + by (unfold execute_SCTAG_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_decode_SCTAG_C_CR_C[non_mem_expI]: + "non_mem_exp (decode_SCTAG_C_CR_C Rm Cn Cd)" + by (unfold decode_SCTAG_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_execute_SCVALUE_C_CR_C[non_mem_expI]: + "non_mem_exp (execute_SCVALUE_C_CR_C d m n)" + by (unfold execute_SCVALUE_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_decode_SCVALUE_C_CR_C[non_mem_expI]: + "non_mem_exp (decode_SCVALUE_C_CR_C Rm opc Cn Cd)" + by (unfold decode_SCVALUE_C_CR_C_def, non_mem_expI) + +lemma non_mem_exp_execute_SEAL_C_CC_C[non_mem_expI]: + "non_mem_exp (execute_SEAL_C_CC_C d m n)" + by (unfold execute_SEAL_C_CC_C_def, non_mem_expI) + +lemma non_mem_exp_decode_SEAL_C_CC_C[non_mem_expI]: + "non_mem_exp (decode_SEAL_C_CC_C Cm opc Cn Cd)" + by (unfold decode_SEAL_C_CC_C_def, non_mem_expI) + +lemma non_mem_exp_execute_SEAL_C_CI_C[non_mem_expI]: + "non_mem_exp (execute_SEAL_C_CI_C d f n)" + by (unfold execute_SEAL_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_decode_SEAL_C_CI_C[non_mem_expI]: + "non_mem_exp (decode_SEAL_C_CI_C form Cn Cd)" + by (unfold decode_SEAL_C_CI_C_def, non_mem_expI) + +lemma non_mem_exp_execute_SUBS_R_CC_C[non_mem_expI]: + "non_mem_exp (execute_SUBS_R_CC_C d m n)" + by (unfold execute_SUBS_R_CC_C_def, non_mem_expI) + +lemma non_mem_exp_decode_SUBS_R_CC_C[non_mem_expI]: + "non_mem_exp (decode_SUBS_R_CC_C Cm Cn Rd)" + by (unfold decode_SUBS_R_CC_C_def, non_mem_expI) + +lemma non_mem_exp_execute_SUB_C_CIS_C[non_mem_expI]: + "non_mem_exp (execute_SUB_C_CIS_C d imm n)" + by (unfold execute_SUB_C_CIS_C_def, non_mem_expI) + +lemma non_mem_exp_decode_SUB_C_CIS_C[non_mem_expI]: + "non_mem_exp (decode_SUB_C_CIS_C A sh imm12 Cn Cd)" + by (unfold decode_SUB_C_CIS_C_def, non_mem_expI) + +lemma non_mem_exp_execute_UNSEAL_C_CC_C[non_mem_expI]: + "non_mem_exp (execute_UNSEAL_C_CC_C d m n)" + by (unfold execute_UNSEAL_C_CC_C_def, non_mem_expI) + +lemma non_mem_exp_decode_UNSEAL_C_CC_C[non_mem_expI]: + "non_mem_exp (decode_UNSEAL_C_CC_C Cm opc Cn Cd)" + by (unfold decode_UNSEAL_C_CC_C_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n neg)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd[non_mem_expI]: + "non_mem_exp (decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd Rd Rn b__0 U b__1)" + by (unfold decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd[non_mem_expI]: + "non_mem_exp (decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd Rd Rn b__0 U)" + by (unfold decode_abs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_arithmetic_add_sub_carry[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_arithmetic_add_sub_carry d (datasize :: 'datasize::len itself) m n setflags sub_op)" + by (unfold execute_aarch64_instrs_integer_arithmetic_add_sub_carry_def, non_mem_expI) + +lemma non_mem_exp_decode_adc_aarch64_instrs_integer_arithmetic_add_sub_carry[non_mem_expI]: + "non_mem_exp (decode_adc_aarch64_instrs_integer_arithmetic_add_sub_carry Rd Rn Rm S op b__0)" + by (unfold decode_adc_aarch64_instrs_integer_arithmetic_add_sub_carry_def, non_mem_expI) + +lemma non_mem_exp_decode_adcs_aarch64_instrs_integer_arithmetic_add_sub_carry[non_mem_expI]: + "non_mem_exp (decode_adcs_aarch64_instrs_integer_arithmetic_add_sub_carry Rd Rn Rm S op b__0)" + by (unfold decode_adcs_aarch64_instrs_integer_arithmetic_add_sub_carry_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_arithmetic_add_sub_extendedreg d (datasize :: 'datasize::len itself) extend_type m n setflags shift sub_op)" + by (unfold execute_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def, non_mem_expI) + +lemma non_mem_exp_decode_add_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[non_mem_expI]: + "non_mem_exp (decode_add_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg Rd Rn imm3 option_name Rm S op b__0)" + by (unfold decode_add_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_arithmetic_add_sub_immediate[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_arithmetic_add_sub_immediate d datasize imm n setflags sub_op)" + by (unfold execute_aarch64_instrs_integer_arithmetic_add_sub_immediate_def, non_mem_expI) + +lemma non_mem_exp_decode_add_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate[non_mem_expI]: + "non_mem_exp (decode_add_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate Rd Rn imm12 sh S op b__0)" + by (unfold decode_add_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg d (datasize :: 'datasize::len itself) m n setflags shift_amount shift_type sub_op)" + by (unfold execute_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_decode_add_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[non_mem_expI]: + "non_mem_exp (decode_add_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg Rd Rn imm6 Rm shift S op b__0)" + by (unfold decode_add_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd[non_mem_expI]: + "non_mem_exp (decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd[non_mem_expI]: + "non_mem_exp (decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd Rd Rn Rm b__0 U)" + by (unfold decode_add_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow d datasize elements l__40 m n part round__arg sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def, non_mem_expI) + +lemma non_mem_exp_decode_addhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[non_mem_expI]: + "non_mem_exp (decode_addhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_addhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_reduce_add_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_reduce_add_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_add_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_addp_advsimd_pair_aarch64_instrs_vector_reduce_add_sisd[non_mem_expI]: + "non_mem_exp (decode_addp_advsimd_pair_aarch64_instrs_vector_reduce_add_sisd Rd Rn b__0)" + by (unfold decode_addp_advsimd_pair_aarch64_instrs_vector_reduce_add_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair d l__179 elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair_def, non_mem_expI) + +lemma non_mem_exp_decode_addp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair[non_mem_expI]: + "non_mem_exp (decode_addp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair Rd Rn Rm b__0 b__1)" + by (unfold decode_addp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_pair_def, non_mem_expI) + +lemma non_mem_exp_decode_adds_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[non_mem_expI]: + "non_mem_exp (decode_adds_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg Rd Rn imm3 option_name Rm S op b__0)" + by (unfold decode_adds_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def, non_mem_expI) + +lemma non_mem_exp_decode_adds_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate[non_mem_expI]: + "non_mem_exp (decode_adds_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate Rd Rn imm12 sh S op b__0)" + by (unfold decode_adds_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate_def, non_mem_expI) + +lemma non_mem_exp_decode_adds_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[non_mem_expI]: + "non_mem_exp (decode_adds_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg Rd Rn imm6 Rm shift S op b__0)" + by (unfold decode_adds_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_reduce_add_simd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_reduce_add_simd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_add_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_addv_advsimd_aarch64_instrs_vector_reduce_add_simd[non_mem_expI]: + "non_mem_exp (decode_addv_advsimd_aarch64_instrs_vector_reduce_add_simd Rd Rn b__0 b__1)" + by (unfold decode_addv_advsimd_aarch64_instrs_vector_reduce_add_simd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_aes_round[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_aes_round d decrypt n)" + by (unfold execute_aarch64_instrs_vector_crypto_aes_round_def, non_mem_expI) + +lemma non_mem_exp_decode_aesd_advsimd_aarch64_instrs_vector_crypto_aes_round[non_mem_expI]: + "non_mem_exp (decode_aesd_advsimd_aarch64_instrs_vector_crypto_aes_round Rd Rn D)" + by (unfold decode_aesd_advsimd_aarch64_instrs_vector_crypto_aes_round_def, non_mem_expI) + +lemma non_mem_exp_decode_aese_advsimd_aarch64_instrs_vector_crypto_aes_round[non_mem_expI]: + "non_mem_exp (decode_aese_advsimd_aarch64_instrs_vector_crypto_aes_round Rd Rn D)" + by (unfold decode_aese_advsimd_aarch64_instrs_vector_crypto_aes_round_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_aes_mix[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_aes_mix d decrypt n)" + by (unfold execute_aarch64_instrs_vector_crypto_aes_mix_def, non_mem_expI) + +lemma non_mem_exp_decode_aesimc_advsimd_aarch64_instrs_vector_crypto_aes_mix[non_mem_expI]: + "non_mem_exp (decode_aesimc_advsimd_aarch64_instrs_vector_crypto_aes_mix Rd Rn D)" + by (unfold decode_aesimc_advsimd_aarch64_instrs_vector_crypto_aes_mix_def, non_mem_expI) + +lemma non_mem_exp_decode_aesmc_advsimd_aarch64_instrs_vector_crypto_aes_mix[non_mem_expI]: + "non_mem_exp (decode_aesmc_advsimd_aarch64_instrs_vector_crypto_aes_mix Rd Rn D)" + by (unfold decode_aesmc_advsimd_aarch64_instrs_vector_crypto_aes_mix_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr d (datasize :: 'datasize::len itself) invert m n op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def, non_mem_expI) + +lemma non_mem_exp_decode_and_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[non_mem_expI]: + "non_mem_exp (decode_and_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0)" + by (unfold decode_and_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_logical_immediate[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_logical_immediate d datasize imm n op setflags)" + by (unfold execute_aarch64_instrs_integer_logical_immediate_def, non_mem_expI) + +lemma non_mem_exp_decode_and_log_imm_aarch64_instrs_integer_logical_immediate[non_mem_expI]: + "non_mem_exp (decode_and_log_imm_aarch64_instrs_integer_logical_immediate Rd Rn imms immr N opc b__0)" + by (unfold decode_and_log_imm_aarch64_instrs_integer_logical_immediate_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_logical_shiftedreg[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_logical_shiftedreg d (datasize :: 'datasize::len itself) invert m n op setflags shift_amount shift_type)" + by (unfold execute_aarch64_instrs_integer_logical_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_decode_and_log_shift_aarch64_instrs_integer_logical_shiftedreg[non_mem_expI]: + "non_mem_exp (decode_and_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_and_log_shift_aarch64_instrs_integer_logical_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_decode_ands_log_imm_aarch64_instrs_integer_logical_immediate[non_mem_expI]: + "non_mem_exp (decode_ands_log_imm_aarch64_instrs_integer_logical_immediate Rd Rn imms immr N opc b__0)" + by (unfold decode_ands_log_imm_aarch64_instrs_integer_logical_immediate_def, non_mem_expI) + +lemma non_mem_exp_decode_ands_log_shift_aarch64_instrs_integer_logical_shiftedreg[non_mem_expI]: + "non_mem_exp (decode_ands_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_ands_log_shift_aarch64_instrs_integer_logical_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_shift_variable[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_shift_variable d (datasize :: 'datasize::len itself) m n shift_type)" + by (unfold execute_aarch64_instrs_integer_shift_variable_def, non_mem_expI) + +lemma non_mem_exp_decode_asrv_aarch64_instrs_integer_shift_variable[non_mem_expI]: + "non_mem_exp (decode_asrv_aarch64_instrs_integer_shift_variable Rd Rn op2 Rm b__0)" + by (unfold decode_asrv_aarch64_instrs_integer_shift_variable_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_branch_conditional_cond[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_branch_conditional_cond condition offset)" + by (unfold execute_aarch64_instrs_branch_conditional_cond_def, non_mem_expI) + +lemma non_mem_exp_decode_b_cond_aarch64_instrs_branch_conditional_cond[non_mem_expI]: + "non_mem_exp (decode_b_cond_aarch64_instrs_branch_conditional_cond cond imm19)" + by (unfold decode_b_cond_aarch64_instrs_branch_conditional_cond_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_branch_unconditional_immediate[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_branch_unconditional_immediate branch_type offset)" + by (unfold execute_aarch64_instrs_branch_unconditional_immediate_def, non_mem_expI) + +lemma non_mem_exp_decode_b_uncond_aarch64_instrs_branch_unconditional_immediate[non_mem_expI]: + "non_mem_exp (decode_b_uncond_aarch64_instrs_branch_unconditional_immediate imm26 op)" + by (unfold decode_b_uncond_aarch64_instrs_branch_unconditional_immediate_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha3_bcax[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha3_bcax a d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3_bcax_def, non_mem_expI) + +lemma non_mem_exp_decode_bcax_advsimd_aarch64_instrs_vector_crypto_sha3_bcax[non_mem_expI]: + "non_mem_exp (decode_bcax_advsimd_aarch64_instrs_vector_crypto_sha3_bcax Rd Rn Ra Rm)" + by (unfold decode_bcax_advsimd_aarch64_instrs_vector_crypto_sha3_bcax_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_bitfield[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_bitfield R S d datasize extend__arg inzero n tmask wmask)" + by (unfold execute_aarch64_instrs_integer_bitfield_def, non_mem_expI) + +lemma non_mem_exp_decode_bfm_aarch64_instrs_integer_bitfield[non_mem_expI]: + "non_mem_exp (decode_bfm_aarch64_instrs_integer_bitfield Rd Rn imms immr N opc b__0)" + by (unfold decode_bfm_aarch64_instrs_integer_bitfield_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_logical[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_logical datasize imm operation rd)" + by (unfold execute_aarch64_instrs_vector_logical_def, non_mem_expI) + +lemma non_mem_exp_decode_bic_advsimd_imm_aarch64_instrs_vector_logical[non_mem_expI]: + "non_mem_exp (decode_bic_advsimd_imm_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_bic_advsimd_imm_aarch64_instrs_vector_logical_def, non_mem_expI) + +lemma non_mem_exp_decode_bic_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[non_mem_expI]: + "non_mem_exp (decode_bic_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0)" + by (unfold decode_bic_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def, non_mem_expI) + +lemma non_mem_exp_decode_bic_log_shift_aarch64_instrs_integer_logical_shiftedreg[non_mem_expI]: + "non_mem_exp (decode_bic_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_bic_log_shift_aarch64_instrs_integer_logical_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_decode_bics_aarch64_instrs_integer_logical_shiftedreg[non_mem_expI]: + "non_mem_exp (decode_bics_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_bics_aarch64_instrs_integer_logical_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor d (datasize :: 'datasize::len itself) m n op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def, non_mem_expI) + +lemma non_mem_exp_decode_bif_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[non_mem_expI]: + "non_mem_exp (decode_bif_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0)" + by (unfold decode_bif_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def, non_mem_expI) + +lemma non_mem_exp_decode_bit_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[non_mem_expI]: + "non_mem_exp (decode_bit_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0)" + by (unfold decode_bit_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def, non_mem_expI) + +lemma non_mem_exp_decode_bl_aarch64_instrs_branch_unconditional_immediate[non_mem_expI]: + "non_mem_exp (decode_bl_aarch64_instrs_branch_unconditional_immediate imm26 op)" + by (unfold decode_bl_aarch64_instrs_branch_unconditional_immediate_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_branch_unconditional_register[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_branch_unconditional_register branch_type n)" + by (unfold execute_aarch64_instrs_branch_unconditional_register_def, non_mem_expI) + +lemma non_mem_exp_decode_blr_aarch64_instrs_branch_unconditional_register[non_mem_expI]: + "non_mem_exp (decode_blr_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)" + by (unfold decode_blr_aarch64_instrs_branch_unconditional_register_def, non_mem_expI) + +lemma non_mem_exp_decode_blra_aarch64_instrs_branch_unconditional_register[non_mem_expI]: + "non_mem_exp (decode_blra_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)" + by (unfold decode_blra_aarch64_instrs_branch_unconditional_register_def, non_mem_expI) + +lemma non_mem_exp_decode_br_aarch64_instrs_branch_unconditional_register[non_mem_expI]: + "non_mem_exp (decode_br_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)" + by (unfold decode_br_aarch64_instrs_branch_unconditional_register_def, non_mem_expI) + +lemma non_mem_exp_decode_bra_aarch64_instrs_branch_unconditional_register[non_mem_expI]: + "non_mem_exp (decode_bra_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)" + by (unfold decode_bra_aarch64_instrs_branch_unconditional_register_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_system_exceptions_debug_breakpoint[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_system_exceptions_debug_breakpoint comment)" + by (unfold execute_aarch64_instrs_system_exceptions_debug_breakpoint_def, non_mem_expI) + +lemma non_mem_exp_decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint[non_mem_expI]: + "non_mem_exp (decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint imm16)" + by (unfold decode_brk_aarch64_instrs_system_exceptions_debug_breakpoint_def, non_mem_expI) + +lemma non_mem_exp_decode_bsl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[non_mem_expI]: + "non_mem_exp (decode_bsl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0)" + by (unfold decode_bsl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_branch_conditional_compare[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_branch_conditional_compare (datasize :: 'datasize::len itself) iszero__arg offset t__arg)" + by (unfold execute_aarch64_instrs_branch_conditional_compare_def, non_mem_expI) + +lemma non_mem_exp_decode_cbnz_aarch64_instrs_branch_conditional_compare[non_mem_expI]: + "non_mem_exp (decode_cbnz_aarch64_instrs_branch_conditional_compare Rt imm19 op b__0)" + by (unfold decode_cbnz_aarch64_instrs_branch_conditional_compare_def, non_mem_expI) + +lemma non_mem_exp_decode_cbz_aarch64_instrs_branch_conditional_compare[non_mem_expI]: + "non_mem_exp (decode_cbz_aarch64_instrs_branch_conditional_compare Rt imm19 op b__0)" + by (unfold decode_cbz_aarch64_instrs_branch_conditional_compare_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_conditional_compare_immediate[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_conditional_compare_immediate condition datasize flags__arg imm n sub_op)" + by (unfold execute_aarch64_instrs_integer_conditional_compare_immediate_def, non_mem_expI) + +lemma non_mem_exp_decode_ccmn_imm_aarch64_instrs_integer_conditional_compare_immediate[non_mem_expI]: + "non_mem_exp (decode_ccmn_imm_aarch64_instrs_integer_conditional_compare_immediate nzcv Rn cond imm5 op b__0)" + by (unfold decode_ccmn_imm_aarch64_instrs_integer_conditional_compare_immediate_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_conditional_compare_register[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_conditional_compare_register condition (datasize :: 'datasize::len itself) flags__arg m n sub_op)" + by (unfold execute_aarch64_instrs_integer_conditional_compare_register_def, non_mem_expI) + +lemma non_mem_exp_decode_ccmn_reg_aarch64_instrs_integer_conditional_compare_register[non_mem_expI]: + "non_mem_exp (decode_ccmn_reg_aarch64_instrs_integer_conditional_compare_register nzcv Rn cond Rm op b__0)" + by (unfold decode_ccmn_reg_aarch64_instrs_integer_conditional_compare_register_def, non_mem_expI) + +lemma non_mem_exp_decode_ccmp_imm_aarch64_instrs_integer_conditional_compare_immediate[non_mem_expI]: + "non_mem_exp (decode_ccmp_imm_aarch64_instrs_integer_conditional_compare_immediate nzcv Rn cond imm5 op b__0)" + by (unfold decode_ccmp_imm_aarch64_instrs_integer_conditional_compare_immediate_def, non_mem_expI) + +lemma non_mem_exp_decode_ccmp_reg_aarch64_instrs_integer_conditional_compare_register[non_mem_expI]: + "non_mem_exp (decode_ccmp_reg_aarch64_instrs_integer_conditional_compare_register nzcv Rn cond Rm op b__0)" + by (unfold decode_ccmp_reg_aarch64_instrs_integer_conditional_compare_register_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_clsz[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_clsz countop d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_clsz_def, non_mem_expI) + +lemma non_mem_exp_decode_cls_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz[non_mem_expI]: + "non_mem_exp (decode_cls_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz Rd Rn b__0 U b__1)" + by (unfold decode_cls_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_arithmetic_cnt[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_arithmetic_cnt d (datasize :: 'datasize::len itself) n opcode)" + by (unfold execute_aarch64_instrs_integer_arithmetic_cnt_def, non_mem_expI) + +lemma non_mem_exp_decode_cls_int_aarch64_instrs_integer_arithmetic_cnt[non_mem_expI]: + "non_mem_exp (decode_cls_int_aarch64_instrs_integer_arithmetic_cnt Rd Rn op b__0)" + by (unfold decode_cls_int_aarch64_instrs_integer_arithmetic_cnt_def, non_mem_expI) + +lemma non_mem_exp_decode_clz_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz[non_mem_expI]: + "non_mem_exp (decode_clz_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz Rd Rn b__0 U b__1)" + by (unfold decode_clz_advsimd_aarch64_instrs_vector_arithmetic_unary_clsz_def, non_mem_expI) + +lemma non_mem_exp_decode_clz_int_aarch64_instrs_integer_arithmetic_cnt[non_mem_expI]: + "non_mem_exp (decode_clz_int_aarch64_instrs_integer_arithmetic_cnt Rd Rn op b__0)" + by (unfold decode_clz_int_aarch64_instrs_integer_arithmetic_cnt_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd and_test d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd[non_mem_expI]: + "non_mem_exp (decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd[non_mem_expI]: + "non_mem_exp (decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd Rd Rn Rm b__0 U)" + by (unfold decode_cmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_cmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd cmp_eq d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[non_mem_expI]: + "non_mem_exp (decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1)" + by (unfold decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[non_mem_expI]: + "non_mem_exp (decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U)" + by (unfold decode_cmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_cmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[non_mem_expI]: + "non_mem_exp (decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1)" + by (unfold decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[non_mem_expI]: + "non_mem_exp (decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U)" + by (unfold decode_cmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_cmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[non_mem_expI]: + "non_mem_exp (decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1)" + by (unfold decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[non_mem_expI]: + "non_mem_exp (decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U)" + by (unfold decode_cmhi_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd[non_mem_expI]: + "non_mem_exp (decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd Rd Rn eq Rm b__0 U b__1)" + by (unfold decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd[non_mem_expI]: + "non_mem_exp (decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd Rd Rn eq Rm b__0 U)" + by (unfold decode_cmhs_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_cmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_simd[non_mem_expI]: + "non_mem_exp (decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_simd Rd Rn b__0 b__1)" + by (unfold decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd[non_mem_expI]: + "non_mem_exp (decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd Rd Rn b__0)" + by (unfold decode_cmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_int_lessthan_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd[non_mem_expI]: + "non_mem_exp (decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd[non_mem_expI]: + "non_mem_exp (decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd Rd Rn Rm b__0 U)" + by (unfold decode_cmtst_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_bitwise_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_cnt[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_cnt d (datasize :: 'datasize::len itself) elements esize n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cnt_def, non_mem_expI) + +lemma non_mem_exp_decode_cnt_advsimd_aarch64_instrs_vector_arithmetic_unary_cnt[non_mem_expI]: + "non_mem_exp (decode_cnt_advsimd_aarch64_instrs_vector_arithmetic_unary_cnt Rd Rn size__arg b__0)" + by (unfold decode_cnt_advsimd_aarch64_instrs_vector_arithmetic_unary_cnt_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_crc[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_crc crc32c d m n l__155)" + by (unfold execute_aarch64_instrs_integer_crc_def, non_mem_expI) + +lemma non_mem_exp_decode_crc32_aarch64_instrs_integer_crc[non_mem_expI]: + "non_mem_exp (decode_crc32_aarch64_instrs_integer_crc Rd Rn b__0 C Rm sf)" + by (unfold decode_crc32_aarch64_instrs_integer_crc_def, non_mem_expI) + +lemma non_mem_exp_decode_crc32c_aarch64_instrs_integer_crc[non_mem_expI]: + "non_mem_exp (decode_crc32c_aarch64_instrs_integer_crc Rd Rn b__0 C Rm sf)" + by (unfold decode_crc32c_aarch64_instrs_integer_crc_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_conditional_select[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_conditional_select condition d (datasize :: 'datasize::len itself) else_inc else_inv m n)" + by (unfold execute_aarch64_instrs_integer_conditional_select_def, non_mem_expI) + +lemma non_mem_exp_decode_csel_aarch64_instrs_integer_conditional_select[non_mem_expI]: + "non_mem_exp (decode_csel_aarch64_instrs_integer_conditional_select Rd Rn o2 cond Rm op b__0)" + by (unfold decode_csel_aarch64_instrs_integer_conditional_select_def, non_mem_expI) + +lemma non_mem_exp_decode_csinc_aarch64_instrs_integer_conditional_select[non_mem_expI]: + "non_mem_exp (decode_csinc_aarch64_instrs_integer_conditional_select Rd Rn o2 cond Rm op b__0)" + by (unfold decode_csinc_aarch64_instrs_integer_conditional_select_def, non_mem_expI) + +lemma non_mem_exp_decode_csinv_aarch64_instrs_integer_conditional_select[non_mem_expI]: + "non_mem_exp (decode_csinv_aarch64_instrs_integer_conditional_select Rd Rn o2 cond Rm op b__0)" + by (unfold decode_csinv_aarch64_instrs_integer_conditional_select_def, non_mem_expI) + +lemma non_mem_exp_decode_csneg_aarch64_instrs_integer_conditional_select[non_mem_expI]: + "non_mem_exp (decode_csneg_aarch64_instrs_integer_conditional_select Rd Rn o2 cond Rm op b__0)" + by (unfold decode_csneg_aarch64_instrs_integer_conditional_select_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_system_exceptions_debug_exception[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_system_exceptions_debug_exception target_level)" + by (unfold execute_aarch64_instrs_system_exceptions_debug_exception_def, non_mem_expI) + +lemma non_mem_exp_decode_dcps1_aarch64_instrs_system_exceptions_debug_exception[non_mem_expI]: + "non_mem_exp (decode_dcps1_aarch64_instrs_system_exceptions_debug_exception LL imm16)" + by (unfold decode_dcps1_aarch64_instrs_system_exceptions_debug_exception_def, non_mem_expI) + +lemma non_mem_exp_decode_dcps2_aarch64_instrs_system_exceptions_debug_exception[non_mem_expI]: + "non_mem_exp (decode_dcps2_aarch64_instrs_system_exceptions_debug_exception LL imm16)" + by (unfold decode_dcps2_aarch64_instrs_system_exceptions_debug_exception_def, non_mem_expI) + +lemma non_mem_exp_decode_dcps3_aarch64_instrs_system_exceptions_debug_exception[non_mem_expI]: + "non_mem_exp (decode_dcps3_aarch64_instrs_system_exceptions_debug_exception LL imm16)" + by (unfold decode_dcps3_aarch64_instrs_system_exceptions_debug_exception_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_branch_unconditional_dret[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_branch_unconditional_dret arg0)" + by (unfold execute_aarch64_instrs_branch_unconditional_dret_def, non_mem_expI) + +lemma non_mem_exp_decode_drps_aarch64_instrs_branch_unconditional_dret[non_mem_expI]: + "non_mem_exp (decode_drps_aarch64_instrs_branch_unconditional_dret arg0)" + by (unfold decode_drps_aarch64_instrs_branch_unconditional_dret_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg n)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_simd[non_mem_expI]: + "non_mem_exp (decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_simd Rd Rn b__0 b__1)" + by (unfold decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd[non_mem_expI]: + "non_mem_exp (decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd Rd Rn b__0)" + by (unfold decode_dup_advsimd_elt_aarch64_instrs_vector_transfer_vector_cpy_dup_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_transfer_integer_dup[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_transfer_integer_dup d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_transfer_integer_dup_def, non_mem_expI) + +lemma non_mem_exp_decode_dup_advsimd_gen_aarch64_instrs_vector_transfer_integer_dup[non_mem_expI]: + "non_mem_exp (decode_dup_advsimd_gen_aarch64_instrs_vector_transfer_integer_dup Rd Rn b__0 b__1)" + by (unfold decode_dup_advsimd_gen_aarch64_instrs_vector_transfer_integer_dup_def, non_mem_expI) + +lemma non_mem_exp_decode_eon_aarch64_instrs_integer_logical_shiftedreg[non_mem_expI]: + "non_mem_exp (decode_eon_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_eon_aarch64_instrs_integer_logical_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha3_eor3[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha3_eor3 a d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3_eor3_def, non_mem_expI) + +lemma non_mem_exp_decode_eor3_advsimd_aarch64_instrs_vector_crypto_sha3_eor3[non_mem_expI]: + "non_mem_exp (decode_eor3_advsimd_aarch64_instrs_vector_crypto_sha3_eor3 Rd Rn Ra Rm)" + by (unfold decode_eor3_advsimd_aarch64_instrs_vector_crypto_sha3_eor3_def, non_mem_expI) + +lemma non_mem_exp_decode_eor_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor[non_mem_expI]: + "non_mem_exp (decode_eor_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor Rd Rn Rm opc2 b__0)" + by (unfold decode_eor_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_bsl_eor_def, non_mem_expI) + +lemma non_mem_exp_decode_eor_log_imm_aarch64_instrs_integer_logical_immediate[non_mem_expI]: + "non_mem_exp (decode_eor_log_imm_aarch64_instrs_integer_logical_immediate Rd Rn imms immr N opc b__0)" + by (unfold decode_eor_log_imm_aarch64_instrs_integer_logical_immediate_def, non_mem_expI) + +lemma non_mem_exp_decode_eor_log_shift_aarch64_instrs_integer_logical_shiftedreg[non_mem_expI]: + "non_mem_exp (decode_eor_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_eor_log_shift_aarch64_instrs_integer_logical_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_branch_unconditional_eret[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_branch_unconditional_eret arg0)" + by (unfold execute_aarch64_instrs_branch_unconditional_eret_def, non_mem_expI) + +lemma non_mem_exp_decode_eret_aarch64_instrs_branch_unconditional_eret[non_mem_expI]: + "non_mem_exp (decode_eret_aarch64_instrs_branch_unconditional_eret op4 Rn M A)" + by (unfold decode_eret_aarch64_instrs_branch_unconditional_eret_def, non_mem_expI) + +lemma non_mem_exp_decode_ereta_aarch64_instrs_branch_unconditional_eret[non_mem_expI]: + "non_mem_exp (decode_ereta_aarch64_instrs_branch_unconditional_eret op4 Rn M A)" + by (unfold decode_ereta_aarch64_instrs_branch_unconditional_eret_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_system_hints[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_system_hints op)" + by (cases op; simp; non_mem_expI) + +lemma non_mem_exp_decode_esb_aarch64_instrs_system_hints[non_mem_expI]: + "non_mem_exp (decode_esb_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_esb_aarch64_instrs_system_hints_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_transfer_vector_extract[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_transfer_vector_extract d l__47 m n position)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_extract_def, non_mem_expI) + +lemma non_mem_exp_decode_ext_advsimd_aarch64_instrs_vector_transfer_vector_extract[non_mem_expI]: + "non_mem_exp (decode_ext_advsimd_aarch64_instrs_vector_transfer_vector_extract Rd Rn imm4 Rm b__0)" + by (unfold decode_ext_advsimd_aarch64_instrs_vector_transfer_vector_extract_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_ins_ext_extract_immediate[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_ins_ext_extract_immediate d l__36 lsb__arg m n)" + by (unfold execute_aarch64_instrs_integer_ins_ext_extract_immediate_def, non_mem_expI) + +lemma non_mem_exp_decode_extr_aarch64_instrs_integer_ins_ext_extract_immediate[non_mem_expI]: + "non_mem_exp (decode_extr_aarch64_instrs_integer_ins_ext_extract_immediate Rd Rn imms Rm N b__0)" + by (unfold decode_extr_aarch64_instrs_integer_ins_ext_extract_immediate_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd abs__arg d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd Rd Rn Rm U b__0)" + by (unfold decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd Rd Rn Rm)" + by (unfold decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd[non_mem_expI]: + "non_mem_exp (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_sisd[non_mem_expI]: + "non_mem_exp (decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_sisd Rd Rn Rm b__0)" + by (unfold decode_fabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n neg)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16_def, non_mem_expI) + +lemma non_mem_exp_decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float[non_mem_expI]: + "non_mem_exp (decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float Rd Rn b__0 U b__1)" + by (unfold decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float_def, non_mem_expI) + +lemma non_mem_exp_decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16[non_mem_expI]: + "non_mem_exp (decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16 Rd Rn U b__0)" + by (unfold decode_fabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_arithmetic_unary[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_arithmetic_unary d (datasize :: 'datasize::len itself) fpop n)" + by (unfold execute_aarch64_instrs_float_arithmetic_unary_def, non_mem_expI) + +lemma non_mem_exp_decode_fabs_float_aarch64_instrs_float_arithmetic_unary[non_mem_expI]: + "non_mem_exp (decode_fabs_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0)" + by (unfold decode_fabs_float_aarch64_instrs_float_arithmetic_unary_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd abs__arg cmp d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[non_mem_expI]: + "non_mem_exp (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[non_mem_expI]: + "non_mem_exp (decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_facge_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[non_mem_expI]: + "non_mem_exp (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[non_mem_expI]: + "non_mem_exp (decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_facgt_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16 d l__163 elements (esize :: 'esize::len itself) m n pair)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16_def, non_mem_expI) + +lemma non_mem_exp_decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp[non_mem_expI]: + "non_mem_exp (decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp Rd Rn Rm b__0 U b__1)" + by (unfold decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp_def, non_mem_expI) + +lemma non_mem_exp_decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16[non_mem_expI]: + "non_mem_exp (decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16 Rd Rn Rm U b__0)" + by (unfold decode_fadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_arithmetic_add_sub[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_arithmetic_add_sub d (datasize :: 'datasize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_float_arithmetic_add_sub_def, non_mem_expI) + +lemma non_mem_exp_decode_fadd_float_aarch64_instrs_float_arithmetic_add_sub[non_mem_expI]: + "non_mem_exp (decode_fadd_float_aarch64_instrs_float_arithmetic_add_sub Rd Rn op Rm b__0)" + by (unfold decode_fadd_float_aarch64_instrs_float_arithmetic_add_sub_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_reduce_fp16_add_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_reduce_fp16_add_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_add_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_add_sisd[non_mem_expI]: + "non_mem_exp (decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_add_sisd Rd Rn sz)" + by (unfold decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_add_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp_add_sisd[non_mem_expI]: + "non_mem_exp (decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp_add_sisd Rd Rn b__0)" + by (unfold decode_faddp_advsimd_pair_aarch64_instrs_vector_reduce_fp_add_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp[non_mem_expI]: + "non_mem_exp (decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp Rd Rn Rm b__0 U b__1)" + by (unfold decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp_def, non_mem_expI) + +lemma non_mem_exp_decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16[non_mem_expI]: + "non_mem_exp (decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16 Rd Rn Rm U b__0)" + by (unfold decode_faddp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_add_fp16_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_compare_cond[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_compare_cond condition (datasize :: 'datasize::len itself) flags__arg m n signal_all_nans)" + by (unfold execute_aarch64_instrs_float_compare_cond_def, non_mem_expI) + +lemma non_mem_exp_decode_fccmp_float_aarch64_instrs_float_compare_cond[non_mem_expI]: + "non_mem_exp (decode_fccmp_float_aarch64_instrs_float_compare_cond nzcv op Rn cond Rm b__0)" + by (unfold decode_fccmp_float_aarch64_instrs_float_compare_cond_def, non_mem_expI) + +lemma non_mem_exp_decode_fccmpe_float_aarch64_instrs_float_compare_cond[non_mem_expI]: + "non_mem_exp (decode_fccmpe_float_aarch64_instrs_float_compare_cond nzcv op Rn cond Rm b__0)" + by (unfold decode_fccmpe_float_aarch64_instrs_float_compare_cond_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[non_mem_expI]: + "non_mem_exp (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_fcmeq_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0)" + by (unfold decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U)" + by (unfold decode_fcmeq_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[non_mem_expI]: + "non_mem_exp (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_fcmge_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0)" + by (unfold decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U)" + by (unfold decode_fcmge_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd Rd Rn ac Rm E U b__0)" + by (unfold decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd Rd Rn ac Rm E U)" + by (unfold decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd[non_mem_expI]: + "non_mem_exp (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd Rd Rn ac Rm b__0 E U b__1)" + by (unfold decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd Rd Rn ac Rm b__0 E U)" + by (unfold decode_fcmgt_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_cmp_fp_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0)" + by (unfold decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U)" + by (unfold decode_fcmgt_advsimd_zero_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd Rd Rn op b__0 U b__1)" + by (unfold decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd Rd Rn op b__0 U)" + by (unfold decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd Rd Rn op U b__0)" + by (unfold decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd Rd Rn op U)" + by (unfold decode_fcmle_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd comparison d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_simd[non_mem_expI]: + "non_mem_exp (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_simd Rd Rn b__0 b__1)" + by (unfold decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_sisd Rd Rn b__0)" + by (unfold decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_float_lessthan_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_simd[non_mem_expI]: + "non_mem_exp (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_simd Rd Rn b__0)" + by (unfold decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd[non_mem_expI]: + "non_mem_exp (decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd Rd Rn)" + by (unfold decode_fcmlt_advsimd_aarch64_instrs_vector_arithmetic_unary_cmp_fp16_lessthan_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_compare_uncond[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_compare_uncond cmp_with_zero (datasize :: 'datasize::len itself) m n signal_all_nans)" + by (unfold execute_aarch64_instrs_float_compare_uncond_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmp_float_aarch64_instrs_float_compare_uncond[non_mem_expI]: + "non_mem_exp (decode_fcmp_float_aarch64_instrs_float_compare_uncond opc Rn Rm b__0)" + by (unfold decode_fcmp_float_aarch64_instrs_float_compare_uncond_def, non_mem_expI) + +lemma non_mem_exp_decode_fcmpe_float_aarch64_instrs_float_compare_uncond[non_mem_expI]: + "non_mem_exp (decode_fcmpe_float_aarch64_instrs_float_compare_uncond opc Rn Rm b__0)" + by (unfold decode_fcmpe_float_aarch64_instrs_float_compare_uncond_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_move_fp_select[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_move_fp_select condition d (datasize :: 'datasize::len itself) m n)" + by (unfold execute_aarch64_instrs_float_move_fp_select_def, non_mem_expI) + +lemma non_mem_exp_decode_fcsel_float_aarch64_instrs_float_move_fp_select[non_mem_expI]: + "non_mem_exp (decode_fcsel_float_aarch64_instrs_float_move_fp_select Rd Rn cond Rm b__0)" + by (unfold decode_fcsel_float_aarch64_instrs_float_move_fp_select_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_convert_fp[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_convert_fp d (dstsize :: 'dstsize::len itself) n (srcsize :: 'srcsize::len itself))" + by (unfold execute_aarch64_instrs_float_convert_fp_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvt_float_aarch64_instrs_float_convert_fp[non_mem_expI]: + "non_mem_exp (decode_fcvt_float_aarch64_instrs_float_convert_fp Rd Rn b__0 b__1)" + by (unfold decode_fcvt_float_aarch64_instrs_float_convert_fp_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n rounding is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd Rd Rn b__0 U b__1)" + by (unfold decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd Rd Rn b__0 U)" + by (unfold decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd Rd Rn U b__0)" + by (unfold decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd Rd Rn U)" + by (unfold decode_fcvtas_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_convert_int d (fltsize :: 'fltsize::len itself) (intsize :: 'intsize::len itself) n op part rounding is_unsigned)" + by (unfold execute_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtas_float_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_fcvtas_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtas_float_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd Rd Rn b__0 U b__1)" + by (unfold decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd Rd Rn b__0 U)" + by (unfold decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_tieaway_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd Rd Rn U b__0)" + by (unfold decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd Rd Rn U)" + by (unfold decode_fcvtau_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_tieaway_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtau_float_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_fcvtau_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtau_float_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_float_widen[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_float_widen d datasize elements l__177 n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_float_widen_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtl_advsimd_aarch64_instrs_vector_arithmetic_unary_float_widen[non_mem_expI]: + "non_mem_exp (decode_fcvtl_advsimd_aarch64_instrs_vector_arithmetic_unary_float_widen Rd Rn b__0 Q)" + by (unfold decode_fcvtl_advsimd_aarch64_instrs_vector_arithmetic_unary_float_widen_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n rounding is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtms_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtms_float_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_fcvtms_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtms_float_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtmu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtmu_float_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_fcvtmu_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtmu_float_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_float_narrow[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_float_narrow d datasize elements l__202 n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_float_narrow_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_narrow[non_mem_expI]: + "non_mem_exp (decode_fcvtn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_narrow Rd Rn b__0 Q)" + by (unfold decode_fcvtn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_narrow_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtns_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtns_float_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_fcvtns_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtns_float_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtnu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtnu_float_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_fcvtnu_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtnu_float_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtps_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtps_float_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_fcvtps_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtps_float_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtpu_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtpu_float_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_fcvtpu_float_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtpu_float_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd d l__53 elements esize n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_simd Rd Rn sz Q)" + by (unfold decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd Rd Rn sz)" + by (unfold decode_fcvtxn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_xtn_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_shift_conv_float_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_shift_conv_float_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) fracbits n rounding is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_conv_float_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd Rd Rn immb b__0 U b__1)" + by (unfold decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd Rd Rn immb b__0 U)" + by (unfold decode_fcvtzs_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtzs_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_convert_fix[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_convert_fix d (fltsize :: 'fltsize::len itself) fracbits (intsize :: 'intsize::len itself) n op rounding is_unsigned)" + by (unfold execute_aarch64_instrs_float_convert_fix_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzs_float_fix_aarch64_instrs_float_convert_fix[non_mem_expI]: + "non_mem_exp (decode_fcvtzs_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1)" + by (unfold decode_fcvtzs_float_fix_aarch64_instrs_float_convert_fix_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzs_float_int_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_fcvtzs_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtzs_float_int_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd Rd Rn immb b__0 U b__1)" + by (unfold decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd Rd Rn immb b__0 U)" + by (unfold decode_fcvtzu_advsimd_fix_aarch64_instrs_vector_shift_conv_float_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd Rd Rn o1 b__0 o2 U)" + by (unfold decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd[non_mem_expI]: + "non_mem_exp (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd Rd Rn o1 o2 U b__0)" + by (unfold decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd[non_mem_expI]: + "non_mem_exp (decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd Rd Rn o1 o2 U)" + by (unfold decode_fcvtzu_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_float_bulk_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzu_float_fix_aarch64_instrs_float_convert_fix[non_mem_expI]: + "non_mem_exp (decode_fcvtzu_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1)" + by (unfold decode_fcvtzu_float_fix_aarch64_instrs_float_convert_fix_def, non_mem_expI) + +lemma non_mem_exp_decode_fcvtzu_float_int_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_fcvtzu_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fcvtzu_float_int_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16_def, non_mem_expI) + +lemma non_mem_exp_decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div[non_mem_expI]: + "non_mem_exp (decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div Rd Rn Rm b__0 b__1)" + by (unfold decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_def, non_mem_expI) + +lemma non_mem_exp_decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16[non_mem_expI]: + "non_mem_exp (decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16 Rd Rn Rm b__0)" + by (unfold decode_fdiv_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_div_fp16_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_arithmetic_div[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_arithmetic_div d (datasize :: 'datasize::len itself) m n)" + by (unfold execute_aarch64_instrs_float_arithmetic_div_def, non_mem_expI) + +lemma non_mem_exp_decode_fdiv_float_aarch64_instrs_float_arithmetic_div[non_mem_expI]: + "non_mem_exp (decode_fdiv_float_aarch64_instrs_float_arithmetic_div Rd Rn Rm b__0)" + by (unfold decode_fdiv_float_aarch64_instrs_float_arithmetic_div_def, non_mem_expI) + +lemma non_mem_exp_decode_fjcvtzs_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_fjcvtzs_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fjcvtzs_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_arithmetic_mul_add_sub[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_arithmetic_mul_add_sub a d (datasize :: 'datasize::len itself) m n op1_neg opa_neg)" + by (unfold execute_aarch64_instrs_float_arithmetic_mul_add_sub_def, non_mem_expI) + +lemma non_mem_exp_decode_fmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub[non_mem_expI]: + "non_mem_exp (decode_fmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0)" + by (unfold decode_fmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 d l__401 elements (esize :: 'esize::len itself) m minimum n pair)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def, non_mem_expI) + +lemma non_mem_exp_decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[non_mem_expI]: + "non_mem_exp (decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0)" + by (unfold decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def, non_mem_expI) + +lemma non_mem_exp_decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[non_mem_expI]: + "non_mem_exp (decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_arithmetic_max_min[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_arithmetic_max_min d (datasize :: 'datasize::len itself) m n operation)" + by (unfold execute_aarch64_instrs_float_arithmetic_max_min_def, non_mem_expI) + +lemma non_mem_exp_decode_fmax_float_aarch64_instrs_float_arithmetic_max_min[non_mem_expI]: + "non_mem_exp (decode_fmax_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0)" + by (unfold decode_fmax_float_aarch64_instrs_float_arithmetic_max_min_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 d l__435 elements (esize :: 'esize::len itself) m minimum n pair)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[non_mem_expI]: + "non_mem_exp (decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0)" + by (unfold decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[non_mem_expI]: + "non_mem_exp (decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmaxnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxnm_float_aarch64_instrs_float_arithmetic_max_min[non_mem_expI]: + "non_mem_exp (decode_fmaxnm_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0)" + by (unfold decode_fmaxnm_float_aarch64_instrs_float_arithmetic_max_min_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_reduce_fp16_maxnm_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_reduce_fp16_maxnm_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_maxnm_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd[non_mem_expI]: + "non_mem_exp (decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd Rd Rn sz o1)" + by (unfold decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd[non_mem_expI]: + "non_mem_exp (decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd Rd Rn b__0 o1)" + by (unfold decode_fmaxnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[non_mem_expI]: + "non_mem_exp (decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0)" + by (unfold decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[non_mem_expI]: + "non_mem_exp (decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmaxnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_reduce_fp16_maxnm_simd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_reduce_fp16_maxnm_simd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_maxnm_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd[non_mem_expI]: + "non_mem_exp (decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd Rd Rn o1 b__0)" + by (unfold decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd[non_mem_expI]: + "non_mem_exp (decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd Rd Rn b__0 o1 b__1)" + by (unfold decode_fmaxnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_reduce_fp16_max_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_reduce_fp16_max_sisd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_max_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd[non_mem_expI]: + "non_mem_exp (decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd Rd Rn sz o1)" + by (unfold decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd[non_mem_expI]: + "non_mem_exp (decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd Rd Rn b__0 o1)" + by (unfold decode_fmaxp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[non_mem_expI]: + "non_mem_exp (decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0)" + by (unfold decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[non_mem_expI]: + "non_mem_exp (decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmaxp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_reduce_fp16_max_simd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_reduce_fp16_max_simd d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) n op)" + by (unfold execute_aarch64_instrs_vector_reduce_fp16_max_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd[non_mem_expI]: + "non_mem_exp (decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd Rd Rn o1 b__0)" + by (unfold decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd[non_mem_expI]: + "non_mem_exp (decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd Rd Rn b__0 o1 b__1)" + by (unfold decode_fmaxv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[non_mem_expI]: + "non_mem_exp (decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0)" + by (unfold decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def, non_mem_expI) + +lemma non_mem_exp_decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[non_mem_expI]: + "non_mem_exp (decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fmin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def, non_mem_expI) + +lemma non_mem_exp_decode_fmin_float_aarch64_instrs_float_arithmetic_max_min[non_mem_expI]: + "non_mem_exp (decode_fmin_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0)" + by (unfold decode_fmin_float_aarch64_instrs_float_arithmetic_max_min_def, non_mem_expI) + +lemma non_mem_exp_decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[non_mem_expI]: + "non_mem_exp (decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0)" + by (unfold decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def, non_mem_expI) + +lemma non_mem_exp_decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[non_mem_expI]: + "non_mem_exp (decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fminnm_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def, non_mem_expI) + +lemma non_mem_exp_decode_fminnm_float_aarch64_instrs_float_arithmetic_max_min[non_mem_expI]: + "non_mem_exp (decode_fminnm_float_aarch64_instrs_float_arithmetic_max_min Rd Rn op Rm b__0)" + by (unfold decode_fminnm_float_aarch64_instrs_float_arithmetic_max_min_def, non_mem_expI) + +lemma non_mem_exp_decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd[non_mem_expI]: + "non_mem_exp (decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd Rd Rn sz o1)" + by (unfold decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_maxnm_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd[non_mem_expI]: + "non_mem_exp (decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd Rd Rn b__0 o1)" + by (unfold decode_fminnmp_advsimd_pair_aarch64_instrs_vector_reduce_fp_maxnm_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008[non_mem_expI]: + "non_mem_exp (decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008 Rd Rn Rm a U b__0)" + by (unfold decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_2008_def, non_mem_expI) + +lemma non_mem_exp_decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008[non_mem_expI]: + "non_mem_exp (decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fminnmp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_2008_def, non_mem_expI) + +lemma non_mem_exp_decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd[non_mem_expI]: + "non_mem_exp (decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd Rd Rn o1 b__0)" + by (unfold decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp16_maxnm_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd[non_mem_expI]: + "non_mem_exp (decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd Rd Rn b__0 o1 b__1)" + by (unfold decode_fminnmv_advsimd_aarch64_instrs_vector_reduce_fp_maxnm_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd[non_mem_expI]: + "non_mem_exp (decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd Rd Rn sz o1)" + by (unfold decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp16_max_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd[non_mem_expI]: + "non_mem_exp (decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd Rd Rn b__0 o1)" + by (unfold decode_fminp_advsimd_pair_aarch64_instrs_vector_reduce_fp_max_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985[non_mem_expI]: + "non_mem_exp (decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985 Rd Rn Rm o1 U b__0)" + by (unfold decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp16_1985_def, non_mem_expI) + +lemma non_mem_exp_decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985[non_mem_expI]: + "non_mem_exp (decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985 Rd Rn Rm b__0 o1 U b__1)" + by (unfold decode_fminp_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_fp_1985_def, non_mem_expI) + +lemma non_mem_exp_decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd[non_mem_expI]: + "non_mem_exp (decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd Rd Rn o1 b__0)" + by (unfold decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp16_max_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd[non_mem_expI]: + "non_mem_exp (decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd Rd Rn b__0 o1 b__1)" + by (unfold decode_fminv_advsimd_aarch64_instrs_vector_reduce_fp_max_simd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd Rd Rn b__0 o2 Rm M L)" + by (unfold decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd[non_mem_expI]: + "non_mem_exp (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd Rd Rn b__0 o2 Rm M L b__1 b__2)" + by (unfold decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd[non_mem_expI]: + "non_mem_exp (decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_fmla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused_def, non_mem_expI) + +lemma non_mem_exp_decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused[non_mem_expI]: + "non_mem_exp (decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused Rd Rn Rm a b__0)" + by (unfold decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused_def, non_mem_expI) + +lemma non_mem_exp_decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused[non_mem_expI]: + "non_mem_exp (decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused Rd Rn Rm b__0 op b__1)" + by (unfold decode_fmla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused_def, non_mem_expI) + +lemma non_mem_exp_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd Rd Rn b__0 o2 Rm M L)" + by (unfold decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd[non_mem_expI]: + "non_mem_exp (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd Rd Rn b__0 o2 Rm M L b__1 b__2)" + by (unfold decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd[non_mem_expI]: + "non_mem_exp (decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_fmls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_fp_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused[non_mem_expI]: + "non_mem_exp (decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused Rd Rn Rm a b__0)" + by (unfold decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_fused_def, non_mem_expI) + +lemma non_mem_exp_decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused[non_mem_expI]: + "non_mem_exp (decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused Rd Rn Rm b__0 op b__1)" + by (unfold decode_fmls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_fused_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_fp16_movi[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_fp16_movi datasize imm rd)" + by (unfold execute_aarch64_instrs_vector_fp16_movi_def, non_mem_expI) + +lemma non_mem_exp_decode_fmov_advsimd_aarch64_instrs_vector_fp16_movi[non_mem_expI]: + "non_mem_exp (decode_fmov_advsimd_aarch64_instrs_vector_fp16_movi Rd h g f e d c__arg b a b__0)" + by (unfold decode_fmov_advsimd_aarch64_instrs_vector_fp16_movi_def, non_mem_expI) + +lemma non_mem_exp_decode_fmov_advsimd_aarch64_instrs_vector_logical[non_mem_expI]: + "non_mem_exp (decode_fmov_advsimd_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_fmov_advsimd_aarch64_instrs_vector_logical_def, non_mem_expI) + +lemma non_mem_exp_decode_fmov_float_aarch64_instrs_float_arithmetic_unary[non_mem_expI]: + "non_mem_exp (decode_fmov_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0)" + by (unfold decode_fmov_float_aarch64_instrs_float_arithmetic_unary_def, non_mem_expI) + +lemma non_mem_exp_decode_fmov_float_gen_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_fmov_float_gen_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_fmov_float_gen_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_move_fp_imm[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_move_fp_imm d datasize imm)" + by (unfold execute_aarch64_instrs_float_move_fp_imm_def, non_mem_expI) + +lemma non_mem_exp_decode_fmov_float_imm_aarch64_instrs_float_move_fp_imm[non_mem_expI]: + "non_mem_exp (decode_fmov_float_imm_aarch64_instrs_float_move_fp_imm Rd imm8 b__0)" + by (unfold decode_fmov_float_imm_aarch64_instrs_float_move_fp_imm_def, non_mem_expI) + +lemma non_mem_exp_decode_fmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub[non_mem_expI]: + "non_mem_exp (decode_fmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0)" + by (unfold decode_fmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m mulx_op n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd Rd Rn b__0 Rm M L U b__1)" + by (unfold decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd Rd Rn b__0 Rm M L U)" + by (unfold decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd[non_mem_expI]: + "non_mem_exp (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd Rd Rn b__0 Rm M L b__1 U b__2)" + by (unfold decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd[non_mem_expI]: + "non_mem_exp (decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd Rd Rn b__0 Rm M L b__1 U)" + by (unfold decode_fmul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product_def, non_mem_expI) + +lemma non_mem_exp_decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product[non_mem_expI]: + "non_mem_exp (decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product Rd Rn Rm b__0)" + by (unfold decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_product_def, non_mem_expI) + +lemma non_mem_exp_decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_product[non_mem_expI]: + "non_mem_exp (decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_product Rd Rn Rm b__0 b__1)" + by (unfold decode_fmul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_product_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_arithmetic_mul_product[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_arithmetic_mul_product d (datasize :: 'datasize::len itself) m n negated)" + by (unfold execute_aarch64_instrs_float_arithmetic_mul_product_def, non_mem_expI) + +lemma non_mem_exp_decode_fmul_float_aarch64_instrs_float_arithmetic_mul_product[non_mem_expI]: + "non_mem_exp (decode_fmul_float_aarch64_instrs_float_arithmetic_mul_product Rd Rn op Rm b__0)" + by (unfold decode_fmul_float_aarch64_instrs_float_arithmetic_mul_product_def, non_mem_expI) + +lemma non_mem_exp_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd Rd Rn b__0 Rm M L U b__1)" + by (unfold decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd Rd Rn b__0 Rm M L U)" + by (unfold decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd[non_mem_expI]: + "non_mem_exp (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd Rd Rn b__0 Rm M L b__1 U b__2)" + by (unfold decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd[non_mem_expI]: + "non_mem_exp (decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd Rd Rn b__0 Rm M L b__1 U)" + by (unfold decode_fmulx_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_fp_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_simd[non_mem_expI]: + "non_mem_exp (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_simd Rd Rn Rm b__0)" + by (unfold decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd[non_mem_expI]: + "non_mem_exp (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd Rd Rn Rm)" + by (unfold decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp16_extended_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_simd[non_mem_expI]: + "non_mem_exp (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_simd Rd Rn Rm b__0 b__1)" + by (unfold decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_sisd[non_mem_expI]: + "non_mem_exp (decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_sisd Rd Rn Rm b__0)" + by (unfold decode_fmulx_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_fp_extended_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float[non_mem_expI]: + "non_mem_exp (decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float Rd Rn b__0 U b__1)" + by (unfold decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_float_def, non_mem_expI) + +lemma non_mem_exp_decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16[non_mem_expI]: + "non_mem_exp (decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16 Rd Rn U b__0)" + by (unfold decode_fneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_fp16_def, non_mem_expI) + +lemma non_mem_exp_decode_fneg_float_aarch64_instrs_float_arithmetic_unary[non_mem_expI]: + "non_mem_exp (decode_fneg_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0)" + by (unfold decode_fneg_float_aarch64_instrs_float_arithmetic_unary_def, non_mem_expI) + +lemma non_mem_exp_decode_fnmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub[non_mem_expI]: + "non_mem_exp (decode_fnmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0)" + by (unfold decode_fnmadd_float_aarch64_instrs_float_arithmetic_mul_add_sub_def, non_mem_expI) + +lemma non_mem_exp_decode_fnmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub[non_mem_expI]: + "non_mem_exp (decode_fnmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub Rd Rn Ra o0 Rm o1 b__0)" + by (unfold decode_fnmsub_float_aarch64_instrs_float_arithmetic_mul_add_sub_def, non_mem_expI) + +lemma non_mem_exp_decode_fnmul_float_aarch64_instrs_float_arithmetic_mul_product[non_mem_expI]: + "non_mem_exp (decode_fnmul_float_aarch64_instrs_float_arithmetic_mul_product Rd Rn op Rm b__0)" + by (unfold decode_fnmul_float_aarch64_instrs_float_arithmetic_mul_product_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_simd[non_mem_expI]: + "non_mem_exp (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_simd Rd Rn b__0 b__1)" + by (unfold decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_sisd[non_mem_expI]: + "non_mem_exp (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_sisd Rd Rn b__0)" + by (unfold decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_float_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_simd Rd Rn b__0)" + by (unfold decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd Rd Rn)" + by (unfold decode_frecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_simd Rd Rn Rm b__0)" + by (unfold decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd Rd Rn Rm)" + by (unfold decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_simd[non_mem_expI]: + "non_mem_exp (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_simd Rd Rn Rm b__0 b__1)" + by (unfold decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_sisd[non_mem_expI]: + "non_mem_exp (decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_sisd Rd Rn Rm b__0)" + by (unfold decode_frecps_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_recps_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16_def, non_mem_expI) + +lemma non_mem_exp_decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx[non_mem_expI]: + "non_mem_exp (decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx Rd Rn b__0)" + by (unfold decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_def, non_mem_expI) + +lemma non_mem_exp_decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16[non_mem_expI]: + "non_mem_exp (decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16 Rd Rn)" + by (unfold decode_frecpx_advsimd_aarch64_instrs_vector_arithmetic_unary_special_frecpx_fp16_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_fp16_round[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_fp16_round d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) exact n rounding)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_fp16_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[non_mem_expI]: + "non_mem_exp (decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[non_mem_expI]: + "non_mem_exp (decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frinta_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_float_arithmetic_round_frint[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_float_arithmetic_round_frint d (datasize :: 'datasize::len itself) exact n rounding)" + by (unfold execute_aarch64_instrs_float_arithmetic_round_frint_def, non_mem_expI) + +lemma non_mem_exp_decode_frinta_float_aarch64_instrs_float_arithmetic_round_frint[non_mem_expI]: + "non_mem_exp (decode_frinta_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frinta_float_aarch64_instrs_float_arithmetic_round_frint_def, non_mem_expI) + +lemma non_mem_exp_decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[non_mem_expI]: + "non_mem_exp (decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[non_mem_expI]: + "non_mem_exp (decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frinti_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frinti_float_aarch64_instrs_float_arithmetic_round_frint[non_mem_expI]: + "non_mem_exp (decode_frinti_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frinti_float_aarch64_instrs_float_arithmetic_round_frint_def, non_mem_expI) + +lemma non_mem_exp_decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[non_mem_expI]: + "non_mem_exp (decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[non_mem_expI]: + "non_mem_exp (decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintm_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frintm_float_aarch64_instrs_float_arithmetic_round_frint[non_mem_expI]: + "non_mem_exp (decode_frintm_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintm_float_aarch64_instrs_float_arithmetic_round_frint_def, non_mem_expI) + +lemma non_mem_exp_decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[non_mem_expI]: + "non_mem_exp (decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[non_mem_expI]: + "non_mem_exp (decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintn_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frintn_float_aarch64_instrs_float_arithmetic_round_frint[non_mem_expI]: + "non_mem_exp (decode_frintn_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintn_float_aarch64_instrs_float_arithmetic_round_frint_def, non_mem_expI) + +lemma non_mem_exp_decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[non_mem_expI]: + "non_mem_exp (decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[non_mem_expI]: + "non_mem_exp (decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintp_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frintp_float_aarch64_instrs_float_arithmetic_round_frint[non_mem_expI]: + "non_mem_exp (decode_frintp_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintp_float_aarch64_instrs_float_arithmetic_round_frint_def, non_mem_expI) + +lemma non_mem_exp_decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[non_mem_expI]: + "non_mem_exp (decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[non_mem_expI]: + "non_mem_exp (decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintx_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frintx_float_aarch64_instrs_float_arithmetic_round_frint[non_mem_expI]: + "non_mem_exp (decode_frintx_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintx_float_aarch64_instrs_float_arithmetic_round_frint_def, non_mem_expI) + +lemma non_mem_exp_decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round[non_mem_expI]: + "non_mem_exp (decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round Rd Rn o1 b__0 o2 U b__1)" + by (unfold decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_float_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round[non_mem_expI]: + "non_mem_exp (decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round Rd Rn o1 o2 U b__0)" + by (unfold decode_frintz_advsimd_aarch64_instrs_vector_arithmetic_unary_fp16_round_def, non_mem_expI) + +lemma non_mem_exp_decode_frintz_float_aarch64_instrs_float_arithmetic_round_frint[non_mem_expI]: + "non_mem_exp (decode_frintz_float_aarch64_instrs_float_arithmetic_round_frint Rd Rn rmode b__0 S M)" + by (unfold decode_frintz_float_aarch64_instrs_float_arithmetic_round_frint_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_simd[non_mem_expI]: + "non_mem_exp (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_simd Rd Rn b__0 b__1)" + by (unfold decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_sisd[non_mem_expI]: + "non_mem_exp (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_sisd Rd Rn b__0)" + by (unfold decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_float_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_simd Rd Rn b__0)" + by (unfold decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd Rd Rn)" + by (unfold decode_frsqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_simd Rd Rn Rm b__0)" + by (unfold decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd[non_mem_expI]: + "non_mem_exp (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd Rd Rn Rm)" + by (unfold decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_fp16_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_simd[non_mem_expI]: + "non_mem_exp (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_simd Rd Rn Rm b__0 b__1)" + by (unfold decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_sisd[non_mem_expI]: + "non_mem_exp (decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_sisd Rd Rn Rm b__0)" + by (unfold decode_frsqrts_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_rsqrts_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16 d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16_def, non_mem_expI) + +lemma non_mem_exp_decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt[non_mem_expI]: + "non_mem_exp (decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt Rd Rn b__0 b__1)" + by (unfold decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_def, non_mem_expI) + +lemma non_mem_exp_decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16[non_mem_expI]: + "non_mem_exp (decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16 Rd Rn b__0)" + by (unfold decode_fsqrt_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_fp16_def, non_mem_expI) + +lemma non_mem_exp_decode_fsqrt_float_aarch64_instrs_float_arithmetic_unary[non_mem_expI]: + "non_mem_exp (decode_fsqrt_float_aarch64_instrs_float_arithmetic_unary Rd Rn opc b__0)" + by (unfold decode_fsqrt_float_aarch64_instrs_float_arithmetic_unary_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd abs__arg d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd[non_mem_expI]: + "non_mem_exp (decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd Rd Rn Rm U b__0)" + by (unfold decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp16_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd[non_mem_expI]: + "non_mem_exp (decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_fsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_fp_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_fsub_float_aarch64_instrs_float_arithmetic_add_sub[non_mem_expI]: + "non_mem_exp (decode_fsub_float_aarch64_instrs_float_arithmetic_add_sub Rd Rn op Rm b__0)" + by (unfold decode_fsub_float_aarch64_instrs_float_arithmetic_add_sub_def, non_mem_expI) + +lemma non_mem_exp_decode_hint_aarch64_instrs_system_hints[non_mem_expI]: + "non_mem_exp (decode_hint_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_hint_aarch64_instrs_system_hints_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_system_exceptions_debug_halt[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_system_exceptions_debug_halt arg0)" + by (unfold execute_aarch64_instrs_system_exceptions_debug_halt_def, non_mem_expI) + +lemma non_mem_exp_decode_hlt_aarch64_instrs_system_exceptions_debug_halt[non_mem_expI]: + "non_mem_exp (decode_hlt_aarch64_instrs_system_exceptions_debug_halt imm16)" + by (unfold decode_hlt_aarch64_instrs_system_exceptions_debug_halt_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_system_exceptions_runtime_hvc[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_system_exceptions_runtime_hvc imm)" + by (unfold execute_aarch64_instrs_system_exceptions_runtime_hvc_def, non_mem_expI) + +lemma non_mem_exp_decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc[non_mem_expI]: + "non_mem_exp (decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc imm16)" + by (unfold decode_hvc_aarch64_instrs_system_exceptions_runtime_hvc_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_transfer_vector_insert[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_transfer_vector_insert d dst_index (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) n src_index)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_insert_def, non_mem_expI) + +lemma non_mem_exp_decode_ins_advsimd_elt_aarch64_instrs_vector_transfer_vector_insert[non_mem_expI]: + "non_mem_exp (decode_ins_advsimd_elt_aarch64_instrs_vector_transfer_vector_insert Rd Rn imm4 imm5)" + by (unfold decode_ins_advsimd_elt_aarch64_instrs_vector_transfer_vector_insert_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_transfer_integer_insert[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_transfer_integer_insert d datasize (esize :: 'esize::len itself) index__arg n)" + by (unfold execute_aarch64_instrs_vector_transfer_integer_insert_def, non_mem_expI) + +lemma non_mem_exp_decode_ins_advsimd_gen_aarch64_instrs_vector_transfer_integer_insert[non_mem_expI]: + "non_mem_exp (decode_ins_advsimd_gen_aarch64_instrs_vector_transfer_integer_insert Rd Rn b__0)" + by (unfold decode_ins_advsimd_gen_aarch64_instrs_vector_transfer_integer_insert_def, non_mem_expI) + +lemma non_mem_exp_decode_lslv_aarch64_instrs_integer_shift_variable[non_mem_expI]: + "non_mem_exp (decode_lslv_aarch64_instrs_integer_shift_variable Rd Rn op2 Rm b__0)" + by (unfold decode_lslv_aarch64_instrs_integer_shift_variable_def, non_mem_expI) + +lemma non_mem_exp_decode_lsrv_aarch64_instrs_integer_shift_variable[non_mem_expI]: + "non_mem_exp (decode_lsrv_aarch64_instrs_integer_shift_variable Rd Rn op2 Rm b__0)" + by (unfold decode_lsrv_aarch64_instrs_integer_shift_variable_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub a d (datasize :: 'datasize::len itself) (destsize :: 'destsize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub_def, non_mem_expI) + +lemma non_mem_exp_decode_madd_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub[non_mem_expI]: + "non_mem_exp (decode_madd_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub Rd Rn Ra o0 Rm b__0)" + by (unfold decode_madd_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int_def, non_mem_expI) + +lemma non_mem_exp_decode_mla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int[non_mem_expI]: + "non_mem_exp (decode_mla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int Rd Rn b__0 o2 Rm M L b__1 b__2)" + by (unfold decode_mla_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum_def, non_mem_expI) + +lemma non_mem_exp_decode_mla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum[non_mem_expI]: + "non_mem_exp (decode_mla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum Rd Rn Rm b__0 U b__1)" + by (unfold decode_mla_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum_def, non_mem_expI) + +lemma non_mem_exp_decode_mls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int[non_mem_expI]: + "non_mem_exp (decode_mls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int Rd Rn b__0 o2 Rm M L b__1 b__2)" + by (unfold decode_mls_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_int_def, non_mem_expI) + +lemma non_mem_exp_decode_mls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum[non_mem_expI]: + "non_mem_exp (decode_mls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum Rd Rn Rm b__0 U b__1)" + by (unfold decode_mls_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_accum_def, non_mem_expI) + +lemma non_mem_exp_decode_movi_advsimd_aarch64_instrs_vector_logical[non_mem_expI]: + "non_mem_exp (decode_movi_advsimd_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_movi_advsimd_aarch64_instrs_vector_logical_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_ins_ext_insert_movewide[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_ins_ext_insert_movewide d (datasize :: 'datasize::len itself) imm opcode pos)" + by (unfold execute_aarch64_instrs_integer_ins_ext_insert_movewide_def, non_mem_expI) + +lemma non_mem_exp_decode_movk_aarch64_instrs_integer_ins_ext_insert_movewide[non_mem_expI]: + "non_mem_exp (decode_movk_aarch64_instrs_integer_ins_ext_insert_movewide Rd imm16 hw opc b__0)" + by (unfold decode_movk_aarch64_instrs_integer_ins_ext_insert_movewide_def, non_mem_expI) + +lemma non_mem_exp_decode_movn_aarch64_instrs_integer_ins_ext_insert_movewide[non_mem_expI]: + "non_mem_exp (decode_movn_aarch64_instrs_integer_ins_ext_insert_movewide Rd imm16 hw opc b__0)" + by (unfold decode_movn_aarch64_instrs_integer_ins_ext_insert_movewide_def, non_mem_expI) + +lemma non_mem_exp_decode_movz_aarch64_instrs_integer_ins_ext_insert_movewide[non_mem_expI]: + "non_mem_exp (decode_movz_aarch64_instrs_integer_ins_ext_insert_movewide Rd imm16 hw opc b__0)" + by (unfold decode_movz_aarch64_instrs_integer_ins_ext_insert_movewide_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_system_register_system[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_system_register_system read sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg)" + by (unfold execute_aarch64_instrs_system_register_system_def, non_mem_expI) + +lemma non_mem_exp_decode_mrs_aarch64_instrs_system_register_system[non_mem_expI]: + "non_mem_exp (decode_mrs_aarch64_instrs_system_register_system Rt op2 CRm CRn op1 o0 L)" + by (unfold decode_mrs_aarch64_instrs_system_register_system_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_system_register_cpsr[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_system_register_cpsr field operand)" + by (cases field; simp; non_mem_expI) + +lemma non_mem_exp_decode_msr_imm_aarch64_instrs_system_register_cpsr[non_mem_expI]: + "non_mem_exp (decode_msr_imm_aarch64_instrs_system_register_cpsr op2 CRm op1)" + by (unfold decode_msr_imm_aarch64_instrs_system_register_cpsr_def, non_mem_expI) + +lemma non_mem_exp_decode_msr_reg_aarch64_instrs_system_register_system[non_mem_expI]: + "non_mem_exp (decode_msr_reg_aarch64_instrs_system_register_system Rt op2 CRm CRn op1 o0 L)" + by (unfold decode_msr_reg_aarch64_instrs_system_register_system_def, non_mem_expI) + +lemma non_mem_exp_decode_msub_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub[non_mem_expI]: + "non_mem_exp (decode_msub_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub Rd Rn Ra o0 Rm b__0)" + by (unfold decode_msub_aarch64_instrs_integer_arithmetic_mul_uniform_add_sub_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_int[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_int d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_int_def, non_mem_expI) + +lemma non_mem_exp_decode_mul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_int[non_mem_expI]: + "non_mem_exp (decode_mul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_int Rd Rn b__0 Rm M L b__1 b__2)" + by (unfold decode_mul_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_int_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product d (datasize :: 'datasize::len itself) elements l__55 m n poly)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product_def, non_mem_expI) + +lemma non_mem_exp_decode_mul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product[non_mem_expI]: + "non_mem_exp (decode_mul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product Rd Rn Rm b__0 U b__1)" + by (unfold decode_mul_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product_def, non_mem_expI) + +lemma non_mem_exp_decode_mvni_advsimd_aarch64_instrs_vector_logical[non_mem_expI]: + "non_mem_exp (decode_mvni_advsimd_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_mvni_advsimd_aarch64_instrs_vector_logical_def, non_mem_expI) + +lemma non_mem_exp_decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd[non_mem_expI]: + "non_mem_exp (decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd Rd Rn b__0 U b__1)" + by (unfold decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd[non_mem_expI]: + "non_mem_exp (decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd Rd Rn b__0 U)" + by (unfold decode_neg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_nop_aarch64_instrs_system_hints[non_mem_expI]: + "non_mem_exp (decode_nop_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_nop_aarch64_instrs_system_hints_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_not[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_not d (datasize :: 'datasize::len itself) elements esize n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_not_def, non_mem_expI) + +lemma non_mem_exp_decode_not_advsimd_aarch64_instrs_vector_arithmetic_unary_not[non_mem_expI]: + "non_mem_exp (decode_not_advsimd_aarch64_instrs_vector_arithmetic_unary_not Rd Rn b__0)" + by (unfold decode_not_advsimd_aarch64_instrs_vector_arithmetic_unary_not_def, non_mem_expI) + +lemma non_mem_exp_decode_orn_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[non_mem_expI]: + "non_mem_exp (decode_orn_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0)" + by (unfold decode_orn_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def, non_mem_expI) + +lemma non_mem_exp_decode_orn_log_shift_aarch64_instrs_integer_logical_shiftedreg[non_mem_expI]: + "non_mem_exp (decode_orn_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_orn_log_shift_aarch64_instrs_integer_logical_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_decode_orr_advsimd_imm_aarch64_instrs_vector_logical[non_mem_expI]: + "non_mem_exp (decode_orr_advsimd_imm_aarch64_instrs_vector_logical Rd h g f e d cmode c__arg b a op b__0)" + by (unfold decode_orr_advsimd_imm_aarch64_instrs_vector_logical_def, non_mem_expI) + +lemma non_mem_exp_decode_orr_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr[non_mem_expI]: + "non_mem_exp (decode_orr_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr Rd Rn Rm size__arg b__0)" + by (unfold decode_orr_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_logical_and_orr_def, non_mem_expI) + +lemma non_mem_exp_decode_orr_log_imm_aarch64_instrs_integer_logical_immediate[non_mem_expI]: + "non_mem_exp (decode_orr_log_imm_aarch64_instrs_integer_logical_immediate Rd Rn imms immr N opc b__0)" + by (unfold decode_orr_log_imm_aarch64_instrs_integer_logical_immediate_def, non_mem_expI) + +lemma non_mem_exp_decode_orr_log_shift_aarch64_instrs_integer_logical_shiftedreg[non_mem_expI]: + "non_mem_exp (decode_orr_log_shift_aarch64_instrs_integer_logical_shiftedreg Rd Rn imm6 Rm N shift opc b__0)" + by (unfold decode_orr_log_shift_aarch64_instrs_integer_logical_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_decode_pmul_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product[non_mem_expI]: + "non_mem_exp (decode_pmul_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product Rd Rn Rm b__0 U b__1)" + by (unfold decode_pmul_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_product_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly d datasize elements l__379 m n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly_def, non_mem_expI) + +lemma non_mem_exp_decode_pmull_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly[non_mem_expI]: + "non_mem_exp (decode_pmull_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly Rd Rn Rm b__0 Q)" + by (unfold decode_pmull_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_mul_poly_def, non_mem_expI) + +lemma non_mem_exp_decode_psb_aarch64_instrs_system_hints[non_mem_expI]: + "non_mem_exp (decode_psb_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_psb_aarch64_instrs_system_hints_def, non_mem_expI) + +lemma non_mem_exp_decode_raddhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[non_mem_expI]: + "non_mem_exp (decode_raddhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_raddhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha3_rax1[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha3_rax1 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3_rax1_def, non_mem_expI) + +lemma non_mem_exp_decode_rax1_advsimd_aarch64_instrs_vector_crypto_sha3_rax1[non_mem_expI]: + "non_mem_exp (decode_rax1_advsimd_aarch64_instrs_vector_crypto_sha3_rax1 Rd Rn Rm)" + by (unfold decode_rax1_advsimd_aarch64_instrs_vector_crypto_sha3_rax1_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_arithmetic_rbit[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_arithmetic_rbit d (datasize :: 'datasize::len itself) n)" + by (unfold execute_aarch64_instrs_integer_arithmetic_rbit_def, non_mem_expI) + +lemma non_mem_exp_decode_rbit_int_aarch64_instrs_integer_arithmetic_rbit[non_mem_expI]: + "non_mem_exp (decode_rbit_int_aarch64_instrs_integer_arithmetic_rbit Rd Rn b__0)" + by (unfold decode_rbit_int_aarch64_instrs_integer_arithmetic_rbit_def, non_mem_expI) + +lemma non_mem_exp_decode_ret_aarch64_instrs_branch_unconditional_register[non_mem_expI]: + "non_mem_exp (decode_ret_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)" + by (unfold decode_ret_aarch64_instrs_branch_unconditional_register_def, non_mem_expI) + +lemma non_mem_exp_decode_reta_aarch64_instrs_branch_unconditional_register[non_mem_expI]: + "non_mem_exp (decode_reta_aarch64_instrs_branch_unconditional_register Rm Rn M A op Z)" + by (unfold decode_reta_aarch64_instrs_branch_unconditional_register_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_rev[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_rev containers d (datasize :: 'datasize::len itself) elements_per_container (esize :: 'esize::len itself) n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_rev_def, non_mem_expI) + +lemma non_mem_exp_decode_rev16_advsimd_aarch64_instrs_vector_arithmetic_unary_rev[non_mem_expI]: + "non_mem_exp (decode_rev16_advsimd_aarch64_instrs_vector_arithmetic_unary_rev Rd Rn o0 b__0 U b__1)" + by (unfold decode_rev16_advsimd_aarch64_instrs_vector_arithmetic_unary_rev_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_arithmetic_rev[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_arithmetic_rev container_size d (datasize :: 'datasize::len itself) n)" + by (unfold execute_aarch64_instrs_integer_arithmetic_rev_def, non_mem_expI) + +lemma non_mem_exp_decode_rev16_int_aarch64_instrs_integer_arithmetic_rev[non_mem_expI]: + "non_mem_exp (decode_rev16_int_aarch64_instrs_integer_arithmetic_rev Rd Rn opc b__0)" + by (unfold decode_rev16_int_aarch64_instrs_integer_arithmetic_rev_def, non_mem_expI) + +lemma non_mem_exp_decode_rev32_advsimd_aarch64_instrs_vector_arithmetic_unary_rev[non_mem_expI]: + "non_mem_exp (decode_rev32_advsimd_aarch64_instrs_vector_arithmetic_unary_rev Rd Rn o0 b__0 U b__1)" + by (unfold decode_rev32_advsimd_aarch64_instrs_vector_arithmetic_unary_rev_def, non_mem_expI) + +lemma non_mem_exp_decode_rev32_int_aarch64_instrs_integer_arithmetic_rev[non_mem_expI]: + "non_mem_exp (decode_rev32_int_aarch64_instrs_integer_arithmetic_rev Rd Rn opc b__0)" + by (unfold decode_rev32_int_aarch64_instrs_integer_arithmetic_rev_def, non_mem_expI) + +lemma non_mem_exp_decode_rev64_advsimd_aarch64_instrs_vector_arithmetic_unary_rev[non_mem_expI]: + "non_mem_exp (decode_rev64_advsimd_aarch64_instrs_vector_arithmetic_unary_rev Rd Rn o0 b__0 U b__1)" + by (unfold decode_rev64_advsimd_aarch64_instrs_vector_arithmetic_unary_rev_def, non_mem_expI) + +lemma non_mem_exp_decode_rev_aarch64_instrs_integer_arithmetic_rev[non_mem_expI]: + "non_mem_exp (decode_rev_aarch64_instrs_integer_arithmetic_rev Rd Rn opc b__0)" + by (unfold decode_rev_aarch64_instrs_integer_arithmetic_rev_def, non_mem_expI) + +lemma non_mem_exp_decode_rorv_aarch64_instrs_integer_shift_variable[non_mem_expI]: + "non_mem_exp (decode_rorv_aarch64_instrs_integer_shift_variable Rd Rn op2 Rm b__0)" + by (unfold decode_rorv_aarch64_instrs_integer_shift_variable_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_shift_right_narrow_logical[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_shift_right_narrow_logical d datasize elements l__473 n part round__arg shift)" + by (unfold execute_aarch64_instrs_vector_shift_right_narrow_logical_def, non_mem_expI) + +lemma non_mem_exp_decode_rshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical[non_mem_expI]: + "non_mem_exp (decode_rshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical Rd Rn op immb b__0 Q)" + by (unfold decode_rshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical_def, non_mem_expI) + +lemma non_mem_exp_decode_rsubhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[non_mem_expI]: + "non_mem_exp (decode_rsubhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_rsubhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_diff[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_diff accumulate d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def, non_mem_expI) + +lemma non_mem_exp_decode_saba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[non_mem_expI]: + "non_mem_exp (decode_saba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1)" + by (unfold decode_saba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_disparate_diff[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_disparate_diff accumulate d datasize elements l__469 m n part is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def, non_mem_expI) + +lemma non_mem_exp_decode_sabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[non_mem_expI]: + "non_mem_exp (decode_sabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q)" + by (unfold decode_sabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def, non_mem_expI) + +lemma non_mem_exp_decode_sabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[non_mem_expI]: + "non_mem_exp (decode_sabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1)" + by (unfold decode_sabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def, non_mem_expI) + +lemma non_mem_exp_decode_sabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[non_mem_expI]: + "non_mem_exp (decode_sabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q)" + by (unfold decode_sabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_add_pairwise[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_add_pairwise acc d (datasize :: 'datasize::len itself) elements l__169 n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def, non_mem_expI) + +lemma non_mem_exp_decode_sadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[non_mem_expI]: + "non_mem_exp (decode_sadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1)" + by (unfold decode_sadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long d datasize elements l__316 m n part sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def, non_mem_expI) + +lemma non_mem_exp_decode_saddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[non_mem_expI]: + "non_mem_exp (decode_saddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_saddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def, non_mem_expI) + +lemma non_mem_exp_decode_saddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[non_mem_expI]: + "non_mem_exp (decode_saddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1)" + by (unfold decode_saddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_reduce_add_long[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_reduce_add_long d (datasize :: 'datasize::len itself) elements l__159 n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_reduce_add_long_def, non_mem_expI) + +lemma non_mem_exp_decode_saddlv_advsimd_aarch64_instrs_vector_reduce_add_long[non_mem_expI]: + "non_mem_exp (decode_saddlv_advsimd_aarch64_instrs_vector_reduce_add_long Rd Rn b__0 U b__1)" + by (unfold decode_saddlv_advsimd_aarch64_instrs_vector_reduce_add_long_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide d datasize elements l__478 m n part sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def, non_mem_expI) + +lemma non_mem_exp_decode_saddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[non_mem_expI]: + "non_mem_exp (decode_saddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_saddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def, non_mem_expI) + +lemma non_mem_exp_decode_sbc_aarch64_instrs_integer_arithmetic_add_sub_carry[non_mem_expI]: + "non_mem_exp (decode_sbc_aarch64_instrs_integer_arithmetic_add_sub_carry Rd Rn Rm S op b__0)" + by (unfold decode_sbc_aarch64_instrs_integer_arithmetic_add_sub_carry_def, non_mem_expI) + +lemma non_mem_exp_decode_sbcs_aarch64_instrs_integer_arithmetic_add_sub_carry[non_mem_expI]: + "non_mem_exp (decode_sbcs_aarch64_instrs_integer_arithmetic_add_sub_carry Rd Rn Rm S op b__0)" + by (unfold decode_sbcs_aarch64_instrs_integer_arithmetic_add_sub_carry_def, non_mem_expI) + +lemma non_mem_exp_decode_sbfm_aarch64_instrs_integer_bitfield[non_mem_expI]: + "non_mem_exp (decode_sbfm_aarch64_instrs_integer_bitfield Rd Rn imms immr N opc b__0)" + by (unfold decode_sbfm_aarch64_instrs_integer_bitfield_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_shift_conv_int_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_shift_conv_int_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) fracbits n rounding is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_conv_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd[non_mem_expI]: + "non_mem_exp (decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd Rd Rn immb b__0 U b__1)" + by (unfold decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd[non_mem_expI]: + "non_mem_exp (decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd Rd Rn immb b__0 U)" + by (unfold decode_scvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd[non_mem_expI]: + "non_mem_exp (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd Rd Rn b__0 U b__1)" + by (unfold decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd[non_mem_expI]: + "non_mem_exp (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd Rd Rn b__0 U)" + by (unfold decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd[non_mem_expI]: + "non_mem_exp (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd Rd Rn U b__0)" + by (unfold decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd[non_mem_expI]: + "non_mem_exp (decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd Rd Rn U)" + by (unfold decode_scvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_scvtf_float_fix_aarch64_instrs_float_convert_fix[non_mem_expI]: + "non_mem_exp (decode_scvtf_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1)" + by (unfold decode_scvtf_float_fix_aarch64_instrs_float_convert_fix_def, non_mem_expI) + +lemma non_mem_exp_decode_scvtf_float_int_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_scvtf_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_scvtf_float_int_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_arithmetic_div[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_arithmetic_div d (datasize :: 'datasize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_integer_arithmetic_div_def, non_mem_expI) + +lemma non_mem_exp_decode_sdiv_aarch64_instrs_integer_arithmetic_div[non_mem_expI]: + "non_mem_exp (decode_sdiv_aarch64_instrs_integer_arithmetic_div Rd Rn o1 Rm b__0)" + by (unfold decode_sdiv_aarch64_instrs_integer_arithmetic_div_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_element_dotp[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_element_dotp d (datasize :: 'datasize::len itself) elements l__375 index__arg m n is_signed)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_dotp_def, non_mem_expI) + +lemma non_mem_exp_decode_sdot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp[non_mem_expI]: + "non_mem_exp (decode_sdot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp Rd Rn H Rm M L b__0 U b__1)" + by (unfold decode_sdot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp d (datasize :: 'datasize::len itself) elements l__165 m n is_signed)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp_def, non_mem_expI) + +lemma non_mem_exp_decode_sdot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp[non_mem_expI]: + "non_mem_exp (decode_sdot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp Rd Rn Rm b__0 U b__1)" + by (unfold decode_sdot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp_def, non_mem_expI) + +lemma non_mem_exp_decode_sev_aarch64_instrs_system_hints[non_mem_expI]: + "non_mem_exp (decode_sev_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_sev_aarch64_instrs_system_hints_def, non_mem_expI) + +lemma non_mem_exp_decode_sevl_aarch64_instrs_system_hints[non_mem_expI]: + "non_mem_exp (decode_sevl_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_sevl_aarch64_instrs_system_hints_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose_def, non_mem_expI) + +lemma non_mem_exp_decode_sha1c_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose[non_mem_expI]: + "non_mem_exp (decode_sha1c_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose Rd Rn Rm)" + by (unfold decode_sha1c_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_choose_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha2op_sha1_hash[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha2op_sha1_hash d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha2op_sha1_hash_def, non_mem_expI) + +lemma non_mem_exp_decode_sha1h_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_hash[non_mem_expI]: + "non_mem_exp (decode_sha1h_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_hash Rd Rn)" + by (unfold decode_sha1h_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_hash_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority_def, non_mem_expI) + +lemma non_mem_exp_decode_sha1m_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority[non_mem_expI]: + "non_mem_exp (decode_sha1m_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority Rd Rn Rm)" + by (unfold decode_sha1m_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_majority_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity_def, non_mem_expI) + +lemma non_mem_exp_decode_sha1p_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity[non_mem_expI]: + "non_mem_exp (decode_sha1p_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity Rd Rn Rm)" + by (unfold decode_sha1p_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_hash_parity_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha3op_sha1_sched0[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha3op_sha1_sched0 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha1_sched0_def, non_mem_expI) + +lemma non_mem_exp_decode_sha1su0_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_sched0[non_mem_expI]: + "non_mem_exp (decode_sha1su0_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_sched0 Rd Rn Rm)" + by (unfold decode_sha1su0_advsimd_aarch64_instrs_vector_crypto_sha3op_sha1_sched0_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha2op_sha1_sched1[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha2op_sha1_sched1 d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha2op_sha1_sched1_def, non_mem_expI) + +lemma non_mem_exp_decode_sha1su1_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_sched1[non_mem_expI]: + "non_mem_exp (decode_sha1su1_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_sched1 Rd Rn)" + by (unfold decode_sha1su1_advsimd_aarch64_instrs_vector_crypto_sha2op_sha1_sched1_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha3op_sha256_hash[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha3op_sha256_hash d m n part1)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha256_hash_def, non_mem_expI) + +lemma non_mem_exp_decode_sha256h2_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash[non_mem_expI]: + "non_mem_exp (decode_sha256h2_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash Rd Rn P Rm)" + by (unfold decode_sha256h2_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash_def, non_mem_expI) + +lemma non_mem_exp_decode_sha256h_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash[non_mem_expI]: + "non_mem_exp (decode_sha256h_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash Rd Rn P Rm)" + by (unfold decode_sha256h_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_hash_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha2op_sha256_sched0[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha2op_sha256_sched0 d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha2op_sha256_sched0_def, non_mem_expI) + +lemma non_mem_exp_decode_sha256su0_advsimd_aarch64_instrs_vector_crypto_sha2op_sha256_sched0[non_mem_expI]: + "non_mem_exp (decode_sha256su0_advsimd_aarch64_instrs_vector_crypto_sha2op_sha256_sched0 Rd Rn)" + by (unfold decode_sha256su0_advsimd_aarch64_instrs_vector_crypto_sha2op_sha256_sched0_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha3op_sha256_sched1[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha3op_sha256_sched1 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3op_sha256_sched1_def, non_mem_expI) + +lemma non_mem_exp_decode_sha256su1_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_sched1[non_mem_expI]: + "non_mem_exp (decode_sha256su1_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_sched1 Rd Rn Rm)" + by (unfold decode_sha256su1_advsimd_aarch64_instrs_vector_crypto_sha3op_sha256_sched1_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha512_sha512h2[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha512_sha512h2 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha512_sha512h2_def, non_mem_expI) + +lemma non_mem_exp_decode_sha512h2_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h2[non_mem_expI]: + "non_mem_exp (decode_sha512h2_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h2 Rd Rn Rm)" + by (unfold decode_sha512h2_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h2_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha512_sha512h[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha512_sha512h d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha512_sha512h_def, non_mem_expI) + +lemma non_mem_exp_decode_sha512h_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h[non_mem_expI]: + "non_mem_exp (decode_sha512h_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h Rd Rn Rm)" + by (unfold decode_sha512h_advsimd_aarch64_instrs_vector_crypto_sha512_sha512h_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha512_sha512su0[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha512_sha512su0 d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha512_sha512su0_def, non_mem_expI) + +lemma non_mem_exp_decode_sha512su0_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su0[non_mem_expI]: + "non_mem_exp (decode_sha512su0_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su0 Rd Rn)" + by (unfold decode_sha512su0_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su0_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha512_sha512su1[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha512_sha512su1 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha512_sha512su1_def, non_mem_expI) + +lemma non_mem_exp_decode_sha512su1_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su1[non_mem_expI]: + "non_mem_exp (decode_sha512su1_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su1 Rd Rn Rm)" + by (unfold decode_sha512su1_advsimd_aarch64_instrs_vector_crypto_sha512_sha512su1_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating_def, non_mem_expI) + +lemma non_mem_exp_decode_shadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating[non_mem_expI]: + "non_mem_exp (decode_shadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating Rd Rn Rm b__0 U b__1)" + by (unfold decode_shadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_shift_left_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_shift_left_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n shift)" + by (unfold execute_aarch64_instrs_vector_shift_left_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_shl_advsimd_aarch64_instrs_vector_shift_left_simd[non_mem_expI]: + "non_mem_exp (decode_shl_advsimd_aarch64_instrs_vector_shift_left_simd Rd Rn immb b__0 b__1)" + by (unfold decode_shl_advsimd_aarch64_instrs_vector_shift_left_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_shl_advsimd_aarch64_instrs_vector_shift_left_sisd[non_mem_expI]: + "non_mem_exp (decode_shl_advsimd_aarch64_instrs_vector_shift_left_sisd Rd Rn immb immh)" + by (unfold decode_shl_advsimd_aarch64_instrs_vector_shift_left_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_shift[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_shift d datasize elements l__49 n part shift is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_shift_def, non_mem_expI) + +lemma non_mem_exp_decode_shll_advsimd_aarch64_instrs_vector_arithmetic_unary_shift[non_mem_expI]: + "non_mem_exp (decode_shll_advsimd_aarch64_instrs_vector_arithmetic_unary_shift Rd Rn b__0 Q)" + by (unfold decode_shll_advsimd_aarch64_instrs_vector_arithmetic_unary_shift_def, non_mem_expI) + +lemma non_mem_exp_decode_shrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical[non_mem_expI]: + "non_mem_exp (decode_shrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical Rd Rn op immb b__0 Q)" + by (unfold decode_shrn_advsimd_aarch64_instrs_vector_shift_right_narrow_logical_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int_def, non_mem_expI) + +lemma non_mem_exp_decode_shsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int[non_mem_expI]: + "non_mem_exp (decode_shsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int Rd Rn Rm b__0 U b__1)" + by (unfold decode_shsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_shift_left_insert_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_shift_left_insert_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n shift)" + by (unfold execute_aarch64_instrs_vector_shift_left_insert_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_simd[non_mem_expI]: + "non_mem_exp (decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_simd Rd Rn immb b__0 b__1)" + by (unfold decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_sisd[non_mem_expI]: + "non_mem_exp (decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_sisd Rd Rn immb immh)" + by (unfold decode_sli_advsimd_aarch64_instrs_vector_shift_left_insert_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sm3_sm3partw1[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sm3_sm3partw1 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3partw1_def, non_mem_expI) + +lemma non_mem_exp_decode_sm3partw1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw1[non_mem_expI]: + "non_mem_exp (decode_sm3partw1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw1 Rd Rn Rm)" + by (unfold decode_sm3partw1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw1_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sm3_sm3partw2[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sm3_sm3partw2 d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3partw2_def, non_mem_expI) + +lemma non_mem_exp_decode_sm3partw2_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw2[non_mem_expI]: + "non_mem_exp (decode_sm3partw2_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw2 Rd Rn Rm)" + by (unfold decode_sm3partw2_advsimd_aarch64_instrs_vector_crypto_sm3_sm3partw2_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sm3_sm3ss1[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sm3_sm3ss1 a d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3ss1_def, non_mem_expI) + +lemma non_mem_exp_decode_sm3ss1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3ss1[non_mem_expI]: + "non_mem_exp (decode_sm3ss1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3ss1 Rd Rn Ra Rm)" + by (unfold decode_sm3ss1_advsimd_aarch64_instrs_vector_crypto_sm3_sm3ss1_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sm3_sm3tt1a[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sm3_sm3tt1a d i m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3tt1a_def, non_mem_expI) + +lemma non_mem_exp_decode_sm3tt1a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1a[non_mem_expI]: + "non_mem_exp (decode_sm3tt1a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1a Rd Rn imm2 Rm)" + by (unfold decode_sm3tt1a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1a_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sm3_sm3tt1b[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sm3_sm3tt1b d i m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3tt1b_def, non_mem_expI) + +lemma non_mem_exp_decode_sm3tt1b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1b[non_mem_expI]: + "non_mem_exp (decode_sm3tt1b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1b Rd Rn imm2 Rm)" + by (unfold decode_sm3tt1b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt1b_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sm3_sm3tt2a[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sm3_sm3tt2a d i m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3tt2a_def, non_mem_expI) + +lemma non_mem_exp_decode_sm3tt2a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2a[non_mem_expI]: + "non_mem_exp (decode_sm3tt2a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2a Rd Rn imm2 Rm)" + by (unfold decode_sm3tt2a_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2a_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sm3_sm3tt2b[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sm3_sm3tt2b d i m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm3_sm3tt2b_def, non_mem_expI) + +lemma non_mem_exp_decode_sm3tt2b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2b[non_mem_expI]: + "non_mem_exp (decode_sm3tt2b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2b Rd Rn imm2 Rm)" + by (unfold decode_sm3tt2b_advsimd_aarch64_instrs_vector_crypto_sm3_sm3tt2b_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sm4_sm4enc[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sm4_sm4enc d n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm4_sm4enc_def, non_mem_expI) + +lemma non_mem_exp_decode_sm4e_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enc[non_mem_expI]: + "non_mem_exp (decode_sm4e_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enc Rd Rn)" + by (unfold decode_sm4e_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enc_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sm4_sm4enckey[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sm4_sm4enckey d m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sm4_sm4enckey_def, non_mem_expI) + +lemma non_mem_exp_decode_sm4ekey_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enckey[non_mem_expI]: + "non_mem_exp (decode_sm4ekey_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enckey Rd Rn Rm)" + by (unfold decode_sm4ekey_advsimd_aarch64_instrs_vector_crypto_sm4_sm4enckey_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_arithmetic_mul_widening_32_64[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_arithmetic_mul_widening_32_64 a d datasize destsize m n sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def, non_mem_expI) + +lemma non_mem_exp_decode_smaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64[non_mem_expI]: + "non_mem_exp (decode_smaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64 Rd Rn Ra o0 Rm U)" + by (unfold decode_smaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m minimum n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def, non_mem_expI) + +lemma non_mem_exp_decode_smax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[non_mem_expI]: + "non_mem_exp (decode_smax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_smax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair d l__193 elements (esize :: 'esize::len itself) m minimum n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def, non_mem_expI) + +lemma non_mem_exp_decode_smaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[non_mem_expI]: + "non_mem_exp (decode_smaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_smaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_reduce_int_max[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_reduce_int_max d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) min__arg n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_reduce_int_max_def, non_mem_expI) + +lemma non_mem_exp_decode_smaxv_advsimd_aarch64_instrs_vector_reduce_int_max[non_mem_expI]: + "non_mem_exp (decode_smaxv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1)" + by (unfold decode_smaxv_advsimd_aarch64_instrs_vector_reduce_int_max_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_system_exceptions_runtime_smc[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_system_exceptions_runtime_smc imm)" + by (unfold execute_aarch64_instrs_system_exceptions_runtime_smc_def, non_mem_expI) + +lemma non_mem_exp_decode_smc_aarch64_instrs_system_exceptions_runtime_smc[non_mem_expI]: + "non_mem_exp (decode_smc_aarch64_instrs_system_exceptions_runtime_smc imm16)" + by (unfold decode_smc_aarch64_instrs_system_exceptions_runtime_smc_def, non_mem_expI) + +lemma non_mem_exp_decode_smin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[non_mem_expI]: + "non_mem_exp (decode_smin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_smin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def, non_mem_expI) + +lemma non_mem_exp_decode_sminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[non_mem_expI]: + "non_mem_exp (decode_sminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_sminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def, non_mem_expI) + +lemma non_mem_exp_decode_sminv_advsimd_aarch64_instrs_vector_reduce_int_max[non_mem_expI]: + "non_mem_exp (decode_sminv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1)" + by (unfold decode_sminv_advsimd_aarch64_instrs_vector_reduce_int_max_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long d datasize elements l__185 (idxdsize :: 'idxdsize::len itself) index__arg m n part sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def, non_mem_expI) + +lemma non_mem_exp_decode_smlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[non_mem_expI]: + "non_mem_exp (decode_smlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q)" + by (unfold decode_smlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum d datasize elements l__537 m n part sub_op is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def, non_mem_expI) + +lemma non_mem_exp_decode_smlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[non_mem_expI]: + "non_mem_exp (decode_smlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_smlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def, non_mem_expI) + +lemma non_mem_exp_decode_smlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[non_mem_expI]: + "non_mem_exp (decode_smlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q)" + by (unfold decode_smlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def, non_mem_expI) + +lemma non_mem_exp_decode_smlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[non_mem_expI]: + "non_mem_exp (decode_smlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_smlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_transfer_integer_move_signed[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_transfer_integer_move_signed d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg n)" + by (unfold execute_aarch64_instrs_vector_transfer_integer_move_signed_def, non_mem_expI) + +lemma non_mem_exp_decode_smov_advsimd_aarch64_instrs_vector_transfer_integer_move_signed[non_mem_expI]: + "non_mem_exp (decode_smov_advsimd_aarch64_instrs_vector_transfer_integer_move_signed Rd Rn b__0 b__1)" + by (unfold decode_smov_advsimd_aarch64_instrs_vector_transfer_integer_move_signed_def, non_mem_expI) + +lemma non_mem_exp_decode_smsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64[non_mem_expI]: + "non_mem_exp (decode_smsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64 Rd Rn Ra o0 Rm U)" + by (unfold decode_smsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi d datasize m n is_unsigned)" + by (unfold execute_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi_def, non_mem_expI) + +lemma non_mem_exp_decode_smulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi[non_mem_expI]: + "non_mem_exp (decode_smulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi Rd Rn Ra Rm U)" + by (unfold decode_smulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_long[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_long d datasize elements l__173 (idxdsize :: 'idxdsize::len itself) index__arg m n part is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_long_def, non_mem_expI) + +lemma non_mem_exp_decode_smull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long[non_mem_expI]: + "non_mem_exp (decode_smull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long Rd Rn b__0 Rm M L b__1 U Q)" + by (unfold decode_smull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product d datasize elements l__189 m n part is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product_def, non_mem_expI) + +lemma non_mem_exp_decode_smull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product[non_mem_expI]: + "non_mem_exp (decode_smull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product Rd Rn Rm b__0 U Q)" + by (unfold decode_smull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n neg)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd[non_mem_expI]: + "non_mem_exp (decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd Rd Rn b__0 U b__1)" + by (unfold decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd[non_mem_expI]: + "non_mem_exp (decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd Rd Rn b__0 U)" + by (unfold decode_sqabs_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd[non_mem_expI]: + "non_mem_exp (decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd[non_mem_expI]: + "non_mem_exp (decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd d l__403 elements l__404 (idxdsize :: 'idxdsize::len itself) index__arg m n part sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd[non_mem_expI]: + "non_mem_exp (decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd Rd Rn b__0 o2 Rm M L b__1 Q)" + by (unfold decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd[non_mem_expI]: + "non_mem_exp (decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_sqdmlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd d l__437 elements l__438 m n part sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd[non_mem_expI]: + "non_mem_exp (decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd Rd Rn o1 Rm b__0 Q)" + by (unfold decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd[non_mem_expI]: + "non_mem_exp (decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd Rd Rn o1 Rm b__0)" + by (unfold decode_sqdmlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd[non_mem_expI]: + "non_mem_exp (decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd Rd Rn b__0 o2 Rm M L b__1 Q)" + by (unfold decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd[non_mem_expI]: + "non_mem_exp (decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd Rd Rn b__0 o2 Rm M L b__1)" + by (unfold decode_sqdmlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_double_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd[non_mem_expI]: + "non_mem_exp (decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd Rd Rn o1 Rm b__0 Q)" + by (unfold decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd[non_mem_expI]: + "non_mem_exp (decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd Rd Rn o1 Rm b__0)" + by (unfold decode_sqdmlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_dmacc_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n round__arg)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd[non_mem_expI]: + "non_mem_exp (decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd Rd Rn b__0 op Rm M L b__1 b__2)" + by (unfold decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd[non_mem_expI]: + "non_mem_exp (decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd Rd Rn b__0 op Rm M L b__1)" + by (unfold decode_sqdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n rounding)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd[non_mem_expI]: + "non_mem_exp (decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd[non_mem_expI]: + "non_mem_exp (decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sqdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd d l__123 elements l__124 (idxdsize :: 'idxdsize::len itself) index__arg m n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_simd[non_mem_expI]: + "non_mem_exp (decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_simd Rd Rn b__0 Rm M L b__1 Q)" + by (unfold decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd[non_mem_expI]: + "non_mem_exp (decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd Rd Rn b__0 Rm M L b__1)" + by (unfold decode_sqdmull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_double_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd d l__59 elements l__60 m n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_simd[non_mem_expI]: + "non_mem_exp (decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_simd Rd Rn Rm b__0 Q)" + by (unfold decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd[non_mem_expI]: + "non_mem_exp (decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd Rd Rn Rm b__0)" + by (unfold decode_sqdmull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_double_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd[non_mem_expI]: + "non_mem_exp (decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd Rd Rn b__0 U b__1)" + by (unfold decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd[non_mem_expI]: + "non_mem_exp (decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd Rd Rn b__0 U)" + by (unfold decode_sqneg_advsimd_aarch64_instrs_vector_arithmetic_unary_diff_neg_sat_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg m n rounding sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd[non_mem_expI]: + "non_mem_exp (decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd Rd Rn b__0 S Rm M L b__1 b__2)" + by (unfold decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd[non_mem_expI]: + "non_mem_exp (decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd Rd Rn b__0 S Rm M L b__1)" + by (unfold decode_sqrdmlah_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n rounding sub_op)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd[non_mem_expI]: + "non_mem_exp (decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd Rd Rn S Rm b__0 b__1)" + by (unfold decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd[non_mem_expI]: + "non_mem_exp (decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd Rd Rn S Rm b__0)" + by (unfold decode_sqrdmlah_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd[non_mem_expI]: + "non_mem_exp (decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd Rd Rn b__0 S Rm M L b__1 b__2)" + by (unfold decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd[non_mem_expI]: + "non_mem_exp (decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd Rd Rn b__0 S Rm M L b__1)" + by (unfold decode_sqrdmlsh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_high_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd[non_mem_expI]: + "non_mem_exp (decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd Rd Rn S Rm b__0 b__1)" + by (unfold decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd[non_mem_expI]: + "non_mem_exp (decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd Rd Rn S Rm b__0)" + by (unfold decode_sqrdmlsh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_accum_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd[non_mem_expI]: + "non_mem_exp (decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd Rd Rn b__0 op Rm M L b__1 b__2)" + by (unfold decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd[non_mem_expI]: + "non_mem_exp (decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd Rd Rn b__0 op Rm M L b__1)" + by (unfold decode_sqrdmulh_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_high_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd[non_mem_expI]: + "non_mem_exp (decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd[non_mem_expI]: + "non_mem_exp (decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sqrdmulh_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_doubling_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n rounding saturating is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[non_mem_expI]: + "non_mem_exp (decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[non_mem_expI]: + "non_mem_exp (decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_sqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_shift_right_narrow_uniform_sisd d l__325 elements l__326 n part round__arg shift is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[non_mem_expI]: + "non_mem_exp (decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q)" + by (unfold decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[non_mem_expI]: + "non_mem_exp (decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U)" + by (unfold decode_sqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd d l__482 elements l__483 n part round__arg shift)" + by (unfold execute_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd[non_mem_expI]: + "non_mem_exp (decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd Rd Rn op immb b__0 Q)" + by (unfold decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd[non_mem_expI]: + "non_mem_exp (decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd Rd Rn op immb b__0)" + by (unfold decode_sqrshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_shift_left_sat_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_shift_left_sat_sisd d (datasize :: 'datasize::len itself) dst_unsigned elements (esize :: 'esize::len itself) n shift src_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_left_sat_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd[non_mem_expI]: + "non_mem_exp (decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd Rd Rn op immb b__0 U b__1)" + by (unfold decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd[non_mem_expI]: + "non_mem_exp (decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd Rd Rn op immb b__0 U)" + by (unfold decode_sqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[non_mem_expI]: + "non_mem_exp (decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[non_mem_expI]: + "non_mem_exp (decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_sqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_simd[non_mem_expI]: + "non_mem_exp (decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_simd Rd Rn op immb b__0 U b__1)" + by (unfold decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_sisd[non_mem_expI]: + "non_mem_exp (decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_sisd Rd Rn op immb b__0 U)" + by (unfold decode_sqshlu_advsimd_aarch64_instrs_vector_shift_left_sat_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[non_mem_expI]: + "non_mem_exp (decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q)" + by (unfold decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[non_mem_expI]: + "non_mem_exp (decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U)" + by (unfold decode_sqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd[non_mem_expI]: + "non_mem_exp (decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd Rd Rn op immb b__0 Q)" + by (unfold decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd[non_mem_expI]: + "non_mem_exp (decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd Rd Rn op immb b__0)" + by (unfold decode_sqshrun_advsimd_aarch64_instrs_vector_shift_right_narrow_nonuniform_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd[non_mem_expI]: + "non_mem_exp (decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd[non_mem_expI]: + "non_mem_exp (decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd d l__91 elements l__92 n part is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd[non_mem_expI]: + "non_mem_exp (decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd Rd Rn b__0 U Q)" + by (unfold decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd[non_mem_expI]: + "non_mem_exp (decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd Rd Rn b__0 U)" + by (unfold decode_sqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd d l__4 elements l__5 n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_simd[non_mem_expI]: + "non_mem_exp (decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_simd Rd Rn b__0 Q)" + by (unfold decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd[non_mem_expI]: + "non_mem_exp (decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd Rd Rn b__0)" + by (unfold decode_sqxtun_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sqxtun_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding_def, non_mem_expI) + +lemma non_mem_exp_decode_srhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding[non_mem_expI]: + "non_mem_exp (decode_srhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding Rd Rn Rm b__0 U b__1)" + by (unfold decode_srhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_shift_right_insert_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_shift_right_insert_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n shift)" + by (unfold execute_aarch64_instrs_vector_shift_right_insert_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_simd[non_mem_expI]: + "non_mem_exp (decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_simd Rd Rn immb b__0 b__1)" + by (unfold decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_sisd[non_mem_expI]: + "non_mem_exp (decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_sisd Rd Rn immb immh)" + by (unfold decode_sri_advsimd_aarch64_instrs_vector_shift_right_insert_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[non_mem_expI]: + "non_mem_exp (decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[non_mem_expI]: + "non_mem_exp (decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_srshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_shift_right_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_shift_right_sisd accumulate d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n round__arg shift is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_right_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_srshr_advsimd_aarch64_instrs_vector_shift_right_simd[non_mem_expI]: + "non_mem_exp (decode_srshr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_srshr_advsimd_aarch64_instrs_vector_shift_right_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_srshr_advsimd_aarch64_instrs_vector_shift_right_sisd[non_mem_expI]: + "non_mem_exp (decode_srshr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_srshr_advsimd_aarch64_instrs_vector_shift_right_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_srsra_advsimd_aarch64_instrs_vector_shift_right_simd[non_mem_expI]: + "non_mem_exp (decode_srsra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_srsra_advsimd_aarch64_instrs_vector_shift_right_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_srsra_advsimd_aarch64_instrs_vector_shift_right_sisd[non_mem_expI]: + "non_mem_exp (decode_srsra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_srsra_advsimd_aarch64_instrs_vector_shift_right_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[non_mem_expI]: + "non_mem_exp (decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[non_mem_expI]: + "non_mem_exp (decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_sshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_shift_left_long[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_shift_left_long d datasize elements l__320 n part shift is_unsigned)" + by (unfold execute_aarch64_instrs_vector_shift_left_long_def, non_mem_expI) + +lemma non_mem_exp_decode_sshll_advsimd_aarch64_instrs_vector_shift_left_long[non_mem_expI]: + "non_mem_exp (decode_sshll_advsimd_aarch64_instrs_vector_shift_left_long Rd Rn immb b__0 U Q)" + by (unfold decode_sshll_advsimd_aarch64_instrs_vector_shift_left_long_def, non_mem_expI) + +lemma non_mem_exp_decode_sshr_advsimd_aarch64_instrs_vector_shift_right_simd[non_mem_expI]: + "non_mem_exp (decode_sshr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_sshr_advsimd_aarch64_instrs_vector_shift_right_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sshr_advsimd_aarch64_instrs_vector_shift_right_sisd[non_mem_expI]: + "non_mem_exp (decode_sshr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_sshr_advsimd_aarch64_instrs_vector_shift_right_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_ssra_advsimd_aarch64_instrs_vector_shift_right_simd[non_mem_expI]: + "non_mem_exp (decode_ssra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_ssra_advsimd_aarch64_instrs_vector_shift_right_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_ssra_advsimd_aarch64_instrs_vector_shift_right_sisd[non_mem_expI]: + "non_mem_exp (decode_ssra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_ssra_advsimd_aarch64_instrs_vector_shift_right_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_ssubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[non_mem_expI]: + "non_mem_exp (decode_ssubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_ssubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def, non_mem_expI) + +lemma non_mem_exp_decode_ssubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[non_mem_expI]: + "non_mem_exp (decode_ssubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_ssubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def, non_mem_expI) + +lemma non_mem_exp_decode_sub_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[non_mem_expI]: + "non_mem_exp (decode_sub_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg Rd Rn imm3 option_name Rm S op b__0)" + by (unfold decode_sub_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def, non_mem_expI) + +lemma non_mem_exp_decode_sub_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate[non_mem_expI]: + "non_mem_exp (decode_sub_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate Rd Rn imm12 sh S op b__0)" + by (unfold decode_sub_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate_def, non_mem_expI) + +lemma non_mem_exp_decode_sub_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[non_mem_expI]: + "non_mem_exp (decode_sub_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg Rd Rn imm6 Rm shift S op b__0)" + by (unfold decode_sub_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd[non_mem_expI]: + "non_mem_exp (decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd[non_mem_expI]: + "non_mem_exp (decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd Rd Rn Rm b__0 U)" + by (unfold decode_sub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_wrapping_single_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_subhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow[non_mem_expI]: + "non_mem_exp (decode_subhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_subhn_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_narrow_def, non_mem_expI) + +lemma non_mem_exp_decode_subs_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg[non_mem_expI]: + "non_mem_exp (decode_subs_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg Rd Rn imm3 option_name Rm S op b__0)" + by (unfold decode_subs_addsub_ext_aarch64_instrs_integer_arithmetic_add_sub_extendedreg_def, non_mem_expI) + +lemma non_mem_exp_decode_subs_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate[non_mem_expI]: + "non_mem_exp (decode_subs_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate Rd Rn imm12 sh S op b__0)" + by (unfold decode_subs_addsub_imm_aarch64_instrs_integer_arithmetic_add_sub_immediate_def, non_mem_expI) + +lemma non_mem_exp_decode_subs_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg[non_mem_expI]: + "non_mem_exp (decode_subs_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg Rd Rn imm6 Rm shift S op b__0)" + by (unfold decode_subs_addsub_shift_aarch64_instrs_integer_arithmetic_add_sub_shiftedreg_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd d (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) n is_unsigned)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd[non_mem_expI]: + "non_mem_exp (decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd Rd Rn b__0 U b__1)" + by (unfold decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd[non_mem_expI]: + "non_mem_exp (decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd Rd Rn b__0 U)" + by (unfold decode_suqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_system_exceptions_runtime_svc[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_system_exceptions_runtime_svc imm)" + by (unfold execute_aarch64_instrs_system_exceptions_runtime_svc_def, non_mem_expI) + +lemma non_mem_exp_decode_svc_aarch64_instrs_system_exceptions_runtime_svc[non_mem_expI]: + "non_mem_exp (decode_svc_aarch64_instrs_system_exceptions_runtime_svc imm16)" + by (unfold decode_svc_aarch64_instrs_system_exceptions_runtime_svc_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_transfer_vector_table[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_transfer_vector_table d (datasize :: 'datasize::len itself) elements is_tbl m n__arg l__181)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_table_def, non_mem_expI) + +lemma non_mem_exp_decode_tbl_advsimd_aarch64_instrs_vector_transfer_vector_table[non_mem_expI]: + "non_mem_exp (decode_tbl_advsimd_aarch64_instrs_vector_transfer_vector_table Rd Rn op len Rm b__0)" + by (unfold decode_tbl_advsimd_aarch64_instrs_vector_transfer_vector_table_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_branch_conditional_test[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_branch_conditional_test bit_pos bit_val (datasize :: 'datasize::len itself) offset t__arg)" + by (unfold execute_aarch64_instrs_branch_conditional_test_def, non_mem_expI) + +lemma non_mem_exp_decode_tbnz_aarch64_instrs_branch_conditional_test[non_mem_expI]: + "non_mem_exp (decode_tbnz_aarch64_instrs_branch_conditional_test Rt imm14 b40 op b__0)" + by (unfold decode_tbnz_aarch64_instrs_branch_conditional_test_def, non_mem_expI) + +lemma non_mem_exp_decode_tbx_advsimd_aarch64_instrs_vector_transfer_vector_table[non_mem_expI]: + "non_mem_exp (decode_tbx_advsimd_aarch64_instrs_vector_transfer_vector_table Rd Rn op len Rm b__0)" + by (unfold decode_tbx_advsimd_aarch64_instrs_vector_transfer_vector_table_def, non_mem_expI) + +lemma non_mem_exp_decode_tbz_aarch64_instrs_branch_conditional_test[non_mem_expI]: + "non_mem_exp (decode_tbz_aarch64_instrs_branch_conditional_test Rt imm14 b40 op b__0)" + by (unfold decode_tbz_aarch64_instrs_branch_conditional_test_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_transfer_vector_permute_transpose[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_transfer_vector_permute_transpose d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) m n pairs part)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_permute_transpose_def, non_mem_expI) + +lemma non_mem_exp_decode_trn1_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose[non_mem_expI]: + "non_mem_exp (decode_trn1_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose Rd Rn op Rm b__0 b__1)" + by (unfold decode_trn1_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose_def, non_mem_expI) + +lemma non_mem_exp_decode_trn2_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose[non_mem_expI]: + "non_mem_exp (decode_trn2_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose Rd Rn op Rm b__0 b__1)" + by (unfold decode_trn2_advsimd_aarch64_instrs_vector_transfer_vector_permute_transpose_def, non_mem_expI) + +lemma non_mem_exp_decode_uaba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[non_mem_expI]: + "non_mem_exp (decode_uaba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1)" + by (unfold decode_uaba_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def, non_mem_expI) + +lemma non_mem_exp_decode_uabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[non_mem_expI]: + "non_mem_exp (decode_uabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q)" + by (unfold decode_uabal_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def, non_mem_expI) + +lemma non_mem_exp_decode_uabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff[non_mem_expI]: + "non_mem_exp (decode_uabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff Rd Rn ac Rm b__0 U b__1)" + by (unfold decode_uabd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_diff_def, non_mem_expI) + +lemma non_mem_exp_decode_uabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff[non_mem_expI]: + "non_mem_exp (decode_uabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff Rd Rn op Rm b__0 U Q)" + by (unfold decode_uabdl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_diff_def, non_mem_expI) + +lemma non_mem_exp_decode_uadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[non_mem_expI]: + "non_mem_exp (decode_uadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1)" + by (unfold decode_uadalp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def, non_mem_expI) + +lemma non_mem_exp_decode_uaddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[non_mem_expI]: + "non_mem_exp (decode_uaddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_uaddl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def, non_mem_expI) + +lemma non_mem_exp_decode_uaddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise[non_mem_expI]: + "non_mem_exp (decode_uaddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise Rd Rn op b__0 U b__1)" + by (unfold decode_uaddlp_advsimd_aarch64_instrs_vector_arithmetic_unary_add_pairwise_def, non_mem_expI) + +lemma non_mem_exp_decode_uaddlv_advsimd_aarch64_instrs_vector_reduce_add_long[non_mem_expI]: + "non_mem_exp (decode_uaddlv_advsimd_aarch64_instrs_vector_reduce_add_long Rd Rn b__0 U b__1)" + by (unfold decode_uaddlv_advsimd_aarch64_instrs_vector_reduce_add_long_def, non_mem_expI) + +lemma non_mem_exp_decode_uaddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[non_mem_expI]: + "non_mem_exp (decode_uaddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_uaddw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def, non_mem_expI) + +lemma non_mem_exp_decode_ubfm_aarch64_instrs_integer_bitfield[non_mem_expI]: + "non_mem_exp (decode_ubfm_aarch64_instrs_integer_bitfield Rd Rn imms immr N opc b__0)" + by (unfold decode_ubfm_aarch64_instrs_integer_bitfield_def, non_mem_expI) + +lemma non_mem_exp_decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd[non_mem_expI]: + "non_mem_exp (decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd Rd Rn immb b__0 U b__1)" + by (unfold decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd[non_mem_expI]: + "non_mem_exp (decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd Rd Rn immb b__0 U)" + by (unfold decode_ucvtf_advsimd_fix_aarch64_instrs_vector_shift_conv_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd[non_mem_expI]: + "non_mem_exp (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd Rd Rn b__0 U b__1)" + by (unfold decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd[non_mem_expI]: + "non_mem_exp (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd Rd Rn b__0 U)" + by (unfold decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_float_conv_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd[non_mem_expI]: + "non_mem_exp (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd Rd Rn U b__0)" + by (unfold decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd[non_mem_expI]: + "non_mem_exp (decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd Rd Rn U)" + by (unfold decode_ucvtf_advsimd_int_aarch64_instrs_vector_arithmetic_unary_fp16_conv_int_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_ucvtf_float_fix_aarch64_instrs_float_convert_fix[non_mem_expI]: + "non_mem_exp (decode_ucvtf_float_fix_aarch64_instrs_float_convert_fix Rd Rn scale opcode rmode b__0 b__1)" + by (unfold decode_ucvtf_float_fix_aarch64_instrs_float_convert_fix_def, non_mem_expI) + +lemma non_mem_exp_decode_ucvtf_float_int_aarch64_instrs_float_convert_int[non_mem_expI]: + "non_mem_exp (decode_ucvtf_float_int_aarch64_instrs_float_convert_int Rd Rn opcode rmode ftype b__0)" + by (unfold decode_ucvtf_float_int_aarch64_instrs_float_convert_int_def, non_mem_expI) + +lemma non_mem_exp_decode_udiv_aarch64_instrs_integer_arithmetic_div[non_mem_expI]: + "non_mem_exp (decode_udiv_aarch64_instrs_integer_arithmetic_div Rd Rn o1 Rm b__0)" + by (unfold decode_udiv_aarch64_instrs_integer_arithmetic_div_def, non_mem_expI) + +lemma non_mem_exp_decode_udot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp[non_mem_expI]: + "non_mem_exp (decode_udot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp Rd Rn H Rm M L b__0 U b__1)" + by (unfold decode_udot_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_dotp_def, non_mem_expI) + +lemma non_mem_exp_decode_udot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp[non_mem_expI]: + "non_mem_exp (decode_udot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp Rd Rn Rm b__0 U b__1)" + by (unfold decode_udot_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_uniform_mul_int_dotp_def, non_mem_expI) + +lemma non_mem_exp_decode_uhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating[non_mem_expI]: + "non_mem_exp (decode_uhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating Rd Rn Rm b__0 U b__1)" + by (unfold decode_uhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_truncating_def, non_mem_expI) + +lemma non_mem_exp_decode_uhsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int[non_mem_expI]: + "non_mem_exp (decode_uhsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int Rd Rn Rm b__0 U b__1)" + by (unfold decode_uhsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_int_def, non_mem_expI) + +lemma non_mem_exp_decode_umaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64[non_mem_expI]: + "non_mem_exp (decode_umaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64 Rd Rn Ra o0 Rm U)" + by (unfold decode_umaddl_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def, non_mem_expI) + +lemma non_mem_exp_decode_umax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[non_mem_expI]: + "non_mem_exp (decode_umax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_umax_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def, non_mem_expI) + +lemma non_mem_exp_decode_umaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[non_mem_expI]: + "non_mem_exp (decode_umaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_umaxp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def, non_mem_expI) + +lemma non_mem_exp_decode_umaxv_advsimd_aarch64_instrs_vector_reduce_int_max[non_mem_expI]: + "non_mem_exp (decode_umaxv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1)" + by (unfold decode_umaxv_advsimd_aarch64_instrs_vector_reduce_int_max_def, non_mem_expI) + +lemma non_mem_exp_decode_umin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single[non_mem_expI]: + "non_mem_exp (decode_umin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_umin_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_single_def, non_mem_expI) + +lemma non_mem_exp_decode_uminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair[non_mem_expI]: + "non_mem_exp (decode_uminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair Rd Rn o1 Rm b__0 U b__1)" + by (unfold decode_uminp_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_max_min_pair_def, non_mem_expI) + +lemma non_mem_exp_decode_uminv_advsimd_aarch64_instrs_vector_reduce_int_max[non_mem_expI]: + "non_mem_exp (decode_uminv_advsimd_aarch64_instrs_vector_reduce_int_max Rd Rn op b__0 U b__1)" + by (unfold decode_uminv_advsimd_aarch64_instrs_vector_reduce_int_max_def, non_mem_expI) + +lemma non_mem_exp_decode_umlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[non_mem_expI]: + "non_mem_exp (decode_umlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q)" + by (unfold decode_umlal_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def, non_mem_expI) + +lemma non_mem_exp_decode_umlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[non_mem_expI]: + "non_mem_exp (decode_umlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_umlal_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def, non_mem_expI) + +lemma non_mem_exp_decode_umlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long[non_mem_expI]: + "non_mem_exp (decode_umlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long Rd Rn b__0 o2 Rm M L b__1 U Q)" + by (unfold decode_umlsl_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_acc_long_def, non_mem_expI) + +lemma non_mem_exp_decode_umlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum[non_mem_expI]: + "non_mem_exp (decode_umlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_umlsl_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_accum_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_transfer_integer_move_unsigned[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_transfer_integer_move_unsigned d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) (idxdsize :: 'idxdsize::len itself) index__arg n)" + by (unfold execute_aarch64_instrs_vector_transfer_integer_move_unsigned_def, non_mem_expI) + +lemma non_mem_exp_decode_umov_advsimd_aarch64_instrs_vector_transfer_integer_move_unsigned[non_mem_expI]: + "non_mem_exp (decode_umov_advsimd_aarch64_instrs_vector_transfer_integer_move_unsigned Rd Rn b__0 b__1)" + by (unfold decode_umov_advsimd_aarch64_instrs_vector_transfer_integer_move_unsigned_def, non_mem_expI) + +lemma non_mem_exp_decode_umsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64[non_mem_expI]: + "non_mem_exp (decode_umsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64 Rd Rn Ra o0 Rm U)" + by (unfold decode_umsubl_aarch64_instrs_integer_arithmetic_mul_widening_32_64_def, non_mem_expI) + +lemma non_mem_exp_decode_umulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi[non_mem_expI]: + "non_mem_exp (decode_umulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi Rd Rn Ra Rm U)" + by (unfold decode_umulh_aarch64_instrs_integer_arithmetic_mul_widening_64_128hi_def, non_mem_expI) + +lemma non_mem_exp_decode_umull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long[non_mem_expI]: + "non_mem_exp (decode_umull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long Rd Rn b__0 Rm M L b__1 U Q)" + by (unfold decode_umull_advsimd_elt_aarch64_instrs_vector_arithmetic_binary_element_mul_long_def, non_mem_expI) + +lemma non_mem_exp_decode_umull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product[non_mem_expI]: + "non_mem_exp (decode_umull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product Rd Rn Rm b__0 U Q)" + by (unfold decode_umull_advsimd_vec_aarch64_instrs_vector_arithmetic_binary_disparate_mul_product_def, non_mem_expI) + +lemma non_mem_exp_decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd[non_mem_expI]: + "non_mem_exp (decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd[non_mem_expI]: + "non_mem_exp (decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd Rd Rn Rm b__0 U)" + by (unfold decode_uqadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_saturating_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[non_mem_expI]: + "non_mem_exp (decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[non_mem_expI]: + "non_mem_exp (decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_uqrshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[non_mem_expI]: + "non_mem_exp (decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q)" + by (unfold decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[non_mem_expI]: + "non_mem_exp (decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U)" + by (unfold decode_uqrshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd[non_mem_expI]: + "non_mem_exp (decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd Rd Rn op immb b__0 U b__1)" + by (unfold decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd[non_mem_expI]: + "non_mem_exp (decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd Rd Rn op immb b__0 U)" + by (unfold decode_uqshl_advsimd_imm_aarch64_instrs_vector_shift_left_sat_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[non_mem_expI]: + "non_mem_exp (decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[non_mem_expI]: + "non_mem_exp (decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_uqshl_advsimd_reg_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd[non_mem_expI]: + "non_mem_exp (decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd Rd Rn op immb b__0 U Q)" + by (unfold decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd[non_mem_expI]: + "non_mem_exp (decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd Rd Rn op immb b__0 U)" + by (unfold decode_uqshrn_advsimd_aarch64_instrs_vector_shift_right_narrow_uniform_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd[non_mem_expI]: + "non_mem_exp (decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd Rd Rn Rm b__0 U b__1)" + by (unfold decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd[non_mem_expI]: + "non_mem_exp (decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd Rd Rn Rm b__0 U)" + by (unfold decode_uqsub_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_sub_saturating_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd[non_mem_expI]: + "non_mem_exp (decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd Rd Rn b__0 U Q)" + by (unfold decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd[non_mem_expI]: + "non_mem_exp (decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd Rd Rn b__0 U)" + by (unfold decode_uqxtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_sat_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_special_recip_int[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_special_recip_int d (datasize :: 'datasize::len itself) elements n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_recip_int_def, non_mem_expI) + +lemma non_mem_exp_decode_urecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_int[non_mem_expI]: + "non_mem_exp (decode_urecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_int Rd Rn sz b__0)" + by (unfold decode_urecpe_advsimd_aarch64_instrs_vector_arithmetic_unary_special_recip_int_def, non_mem_expI) + +lemma non_mem_exp_decode_urhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding[non_mem_expI]: + "non_mem_exp (decode_urhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding Rd Rn Rm b__0 U b__1)" + by (unfold decode_urhadd_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_add_halving_rounding_def, non_mem_expI) + +lemma non_mem_exp_decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[non_mem_expI]: + "non_mem_exp (decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[non_mem_expI]: + "non_mem_exp (decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_urshl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_urshr_advsimd_aarch64_instrs_vector_shift_right_simd[non_mem_expI]: + "non_mem_exp (decode_urshr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_urshr_advsimd_aarch64_instrs_vector_shift_right_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_urshr_advsimd_aarch64_instrs_vector_shift_right_sisd[non_mem_expI]: + "non_mem_exp (decode_urshr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_urshr_advsimd_aarch64_instrs_vector_shift_right_sisd_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int d (datasize :: 'datasize::len itself) elements n)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int_def, non_mem_expI) + +lemma non_mem_exp_decode_ursqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int[non_mem_expI]: + "non_mem_exp (decode_ursqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int Rd Rn sz b__0)" + by (unfold decode_ursqrte_advsimd_aarch64_instrs_vector_arithmetic_unary_special_sqrt_est_int_def, non_mem_expI) + +lemma non_mem_exp_decode_ursra_advsimd_aarch64_instrs_vector_shift_right_simd[non_mem_expI]: + "non_mem_exp (decode_ursra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_ursra_advsimd_aarch64_instrs_vector_shift_right_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_ursra_advsimd_aarch64_instrs_vector_shift_right_sisd[non_mem_expI]: + "non_mem_exp (decode_ursra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_ursra_advsimd_aarch64_instrs_vector_shift_right_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd[non_mem_expI]: + "non_mem_exp (decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd Rd Rn S R Rm b__0 U b__1)" + by (unfold decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd[non_mem_expI]: + "non_mem_exp (decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd Rd Rn S R Rm b__0 U)" + by (unfold decode_ushl_advsimd_aarch64_instrs_vector_arithmetic_binary_uniform_shift_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_ushll_advsimd_aarch64_instrs_vector_shift_left_long[non_mem_expI]: + "non_mem_exp (decode_ushll_advsimd_aarch64_instrs_vector_shift_left_long Rd Rn immb b__0 U Q)" + by (unfold decode_ushll_advsimd_aarch64_instrs_vector_shift_left_long_def, non_mem_expI) + +lemma non_mem_exp_decode_ushr_advsimd_aarch64_instrs_vector_shift_right_simd[non_mem_expI]: + "non_mem_exp (decode_ushr_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_ushr_advsimd_aarch64_instrs_vector_shift_right_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_ushr_advsimd_aarch64_instrs_vector_shift_right_sisd[non_mem_expI]: + "non_mem_exp (decode_ushr_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_ushr_advsimd_aarch64_instrs_vector_shift_right_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd[non_mem_expI]: + "non_mem_exp (decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd Rd Rn b__0 U b__1)" + by (unfold decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd[non_mem_expI]: + "non_mem_exp (decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd Rd Rn b__0 U)" + by (unfold decode_usqadd_advsimd_aarch64_instrs_vector_arithmetic_unary_add_saturating_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_usra_advsimd_aarch64_instrs_vector_shift_right_simd[non_mem_expI]: + "non_mem_exp (decode_usra_advsimd_aarch64_instrs_vector_shift_right_simd Rd Rn o0 o1 immb b__0 U b__1)" + by (unfold decode_usra_advsimd_aarch64_instrs_vector_shift_right_simd_def, non_mem_expI) + +lemma non_mem_exp_decode_usra_advsimd_aarch64_instrs_vector_shift_right_sisd[non_mem_expI]: + "non_mem_exp (decode_usra_advsimd_aarch64_instrs_vector_shift_right_sisd Rd Rn o0 o1 immb immh U)" + by (unfold decode_usra_advsimd_aarch64_instrs_vector_shift_right_sisd_def, non_mem_expI) + +lemma non_mem_exp_decode_usubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long[non_mem_expI]: + "non_mem_exp (decode_usubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_usubl_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_long_def, non_mem_expI) + +lemma non_mem_exp_decode_usubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide[non_mem_expI]: + "non_mem_exp (decode_usubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide Rd Rn o1 Rm b__0 U Q)" + by (unfold decode_usubw_advsimd_aarch64_instrs_vector_arithmetic_binary_disparate_add_sub_wide_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_transfer_vector_permute_unzip[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_transfer_vector_permute_unzip d l__195 elements (esize :: 'esize::len itself) m n part)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_permute_unzip_def, non_mem_expI) + +lemma non_mem_exp_decode_uzp1_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip[non_mem_expI]: + "non_mem_exp (decode_uzp1_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip Rd Rn op Rm b__0 b__1)" + by (unfold decode_uzp1_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip_def, non_mem_expI) + +lemma non_mem_exp_decode_uzp2_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip[non_mem_expI]: + "non_mem_exp (decode_uzp2_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip Rd Rn op Rm b__0 b__1)" + by (unfold decode_uzp2_advsimd_aarch64_instrs_vector_transfer_vector_permute_unzip_def, non_mem_expI) + +lemma non_mem_exp_decode_wfe_aarch64_instrs_system_hints[non_mem_expI]: + "non_mem_exp (decode_wfe_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_wfe_aarch64_instrs_system_hints_def, non_mem_expI) + +lemma non_mem_exp_decode_wfi_aarch64_instrs_system_hints[non_mem_expI]: + "non_mem_exp (decode_wfi_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_wfi_aarch64_instrs_system_hints_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_crypto_sha3_xar[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_crypto_sha3_xar d imm6 m n)" + by (unfold execute_aarch64_instrs_vector_crypto_sha3_xar_def, non_mem_expI) + +lemma non_mem_exp_decode_xar_advsimd_aarch64_instrs_vector_crypto_sha3_xar[non_mem_expI]: + "non_mem_exp (decode_xar_advsimd_aarch64_instrs_vector_crypto_sha3_xar Rd Rn imm6 Rm)" + by (unfold decode_xar_advsimd_aarch64_instrs_vector_crypto_sha3_xar_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_arithmetic_unary_extract_nosat[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_arithmetic_unary_extract_nosat d datasize elements l__0 n part)" + by (unfold execute_aarch64_instrs_vector_arithmetic_unary_extract_nosat_def, non_mem_expI) + +lemma non_mem_exp_decode_xtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_nosat[non_mem_expI]: + "non_mem_exp (decode_xtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_nosat Rd Rn b__0 Q)" + by (unfold decode_xtn_advsimd_aarch64_instrs_vector_arithmetic_unary_extract_nosat_def, non_mem_expI) + +lemma non_mem_exp_decode_yield_aarch64_instrs_system_hints[non_mem_expI]: + "non_mem_exp (decode_yield_aarch64_instrs_system_hints op2 CRm)" + by (unfold decode_yield_aarch64_instrs_system_hints_def, non_mem_expI) + +lemma non_mem_exp_execute_aarch64_instrs_vector_transfer_vector_permute_zip[non_mem_expI]: + "non_mem_exp (execute_aarch64_instrs_vector_transfer_vector_permute_zip d (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) m n pairs part)" + by (unfold execute_aarch64_instrs_vector_transfer_vector_permute_zip_def, non_mem_expI) + +lemma non_mem_exp_decode_zip1_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip[non_mem_expI]: + "non_mem_exp (decode_zip1_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip Rd Rn op Rm b__0 b__1)" + by (unfold decode_zip1_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip_def, non_mem_expI) + +lemma non_mem_exp_decode_zip2_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip[non_mem_expI]: + "non_mem_exp (decode_zip2_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip Rd Rn op Rm b__0 b__1)" + by (unfold decode_zip2_advsimd_aarch64_instrs_vector_transfer_vector_permute_zip_def, non_mem_expI) + +end + +context Morello_Instr_Mem_Automaton +begin + +lemmas non_cap_exp_traces_enabled[traces_enabledI] = non_cap_expI[THEN non_cap_exp_traces_enabledI] + +lemmas non_mem_exp_traces_enabled[traces_enabledI] = non_mem_expI[THEN non_mem_exp_traces_enabledI] + + +lemma traces_enabled_DC_ZVA[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "store_enabled s AccType_DCZVA (unat (Align val_name 64)) 64 (0 :: 512 word) False" + shows "traces_enabled (DC_ZVA val_name) s" + unfolding DC_ZVA_def bind_assoc + by (traces_enabledI assms: assms intro: traces_enabled_foreachM_index_list_inv2[where Inv = "\idx _ memaddrdesc s. {''PCC''} \ accessible_regs s \ FullAddress_address (AddressDescriptor_paddress memaddrdesc) = FullAddress_address (AddressDescriptor_paddress memaddrdesc0) + word_of_int idx" and var_b = memaddrdesc0 for memaddrdesc0] store_enabled_data_paccess_enabled_subset[OF assms(2)] simp: DCZID_EL0_assm exp_fails_if_then_else aligned_unat_plus_distrib[where sz = 64] AArch64_FullTranslate_translate_address[THEN translate_address_aligned_iff] wi_hom_syms elim: Run_bindE) + +lemma traces_enabled_DC_ZVA0[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (DC_ZVA0 val_name__arg) s" + unfolding DC_ZVA0_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_ZVA_SysOpsWrite_b40574bff0ba4354[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (ZVA_SysOpsWrite_b40574bff0ba4354 el op0 op1 CRn op2 CRm val_name) s" + unfolding ZVA_SysOpsWrite_b40574bff0ba4354_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_AutoGen_SysOpsWrite[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_AutoGen_SysOpsWrite el op0 op1 CRn op2 CRm val_name) s" + unfolding AArch64_AutoGen_SysOpsWrite_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_SysInstr[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (AArch64_SysInstr op0 op1 crn crm op2 val_name) s" + unfolding AArch64_SysInstr_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_MemSingle_read[traces_enabledI]: + assumes "translate_address (unat address) \ None \ load_enabled s acctype (unat address) size__arg False" + shows "traces_enabled (AArch64_MemSingle_read address size__arg acctype wasaligned :: 'size_times_p8::len word M) s" + unfolding AArch64_MemSingle_read_def bind_assoc + by (traces_enabledI assms: assms simp: exp_fails_if_then_else) + +lemma traces_enabled_AArch64_MemSingle_set[traces_enabledI]: + assumes "translate_address (unat address) \ None \ store_enabled s acctype (unat address) size__arg value_name False" and "LENGTH('a) = 8 * nat size__arg" + shows "traces_enabled (AArch64_MemSingle_set address size__arg acctype wasaligned (value_name :: 'a::len word)) s" + unfolding AArch64_MemSingle_set_def bind_assoc + by (traces_enabledI assms: assms simp: exp_fails_if_then_else translate_address_aligned32_plus16) + +lemma traces_enabled_AArch64_TaggedMemSingle[traces_enabledI]: + assumes "aligned (unat address) (nat size__arg)" and "load_enabled s acctype (unat address) 16 True" and "size__arg = 32 \ load_enabled s acctype (unat address + 16) 16 True" and "size__arg = 32 \ load_enabled s acctype (unat address) 32 False" + shows "traces_enabled (AArch64_TaggedMemSingle address size__arg acctype wasaligned) s" + unfolding AArch64_TaggedMemSingle_def bind_assoc + by (traces_enabledI assms: assms simp: exp_fails_if_then_else translate_address_aligned32_plus16) + +lemma traces_enabled_AArch64_TaggedMemSingle__1[traces_enabledI]: + assumes "aligned (unat addr) (nat sz)" and "store_enabled s acctype (unat addr) 16 (ucast data :: 128 word) (tags !! 0)" and "sz = 32 \ store_enabled s acctype (unat addr + 16) 16 (Word.slice 128 data :: 128 word) (tags !! 1)" and "LENGTH('t) = nat sz div 16" and "LENGTH('d) = 8 * nat sz" + shows "traces_enabled (AArch64_TaggedMemSingle__1 addr sz acctype wasaligned (tags :: 't::len word) (data :: 'd::len word)) s" + unfolding AArch64_TaggedMemSingle__1_def bind_assoc + by (traces_enabledI assms: assms intro: access_enabled_runI simp: exp_fails_if_then_else translate_address_aligned32_plus16) + +lemma traces_enabled_AArch64_CapabilityTag[traces_enabledI]: + assumes "aligned (unat address) 16 \ load_enabled s acctype (unat address) 16 True" + shows "traces_enabled (AArch64_CapabilityTag address acctype) s" + unfolding AArch64_CapabilityTag_def bind_assoc + by (traces_enabledI assms: assms simp: exp_fails_if_then_else) + +lemma traces_enabled_AArch64_CapabilityTag_set[traces_enabledI]: + assumes "\data :: 128 word. aligned (unat vaddr) 16 \ store_enabled s acctype (unat vaddr) 16 data False" and "tag = 0" + shows "traces_enabled (AArch64_CapabilityTag_set vaddr acctype tag) s" + unfolding AArch64_CapabilityTag_set_def AArch64_TranslateAddress_def bind_assoc + by (traces_enabledI assms: assms simp: exp_fails_if_then_else intro: paccess_enabled_runI store_enabled_access_enabled[OF assms(1)]) + +lemma traces_enabled_Mem_read0[traces_enabledI]: + assumes "load_enabled s acctype (unat vaddr) sz False" + shows "traces_enabled (Mem_read0 vaddr sz acctype) s" + unfolding Mem_read0_def bind_assoc + by (traces_enabledI assms: assms simp: AArch64_MemSingle_read_translate_address_Some) + +lemma traces_enabled_Mem_set0[traces_enabledI]: + assumes "store_enabled s acctype (unat vaddr) sz data False" and "LENGTH('a) = 8 * nat sz" and "sz \ 16" + shows "traces_enabled (Mem_set0 vaddr sz acctype (data :: 'a::len word)) s" + unfolding Mem_set0_def bind_assoc + by (traces_enabledI assms: assms simp: AArch64_MemSingle_set_translate_address_Some) + +lemma traces_enabled_MemC_read[traces_enabledI]: + assumes "aligned (unat address) 16 \ load_enabled s acctype (unat address) 16 True" + shows "traces_enabled (MemC_read address acctype) s" + unfolding MemC_read_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_MemC_set[traces_enabledI]: + assumes "aligned (unat address) 16 \ store_enabled s acctype (unat address) 16 (ucast value_name :: 128 word) (CapIsTagSet value_name)" + shows "traces_enabled (MemC_set address acctype value_name) s" + unfolding MemC_set_def bind_assoc + by (traces_enabledI assms: assms simp: update_subrange_vec_dec_test_bit) + +lemma traces_enabled_MemCP__1[traces_enabledI]: + assumes "aligned (unat address) 32" and "store_enabled s acctype (unat address) 16 (ucast value1_name :: 128 word) (CapIsTagSet value1_name)" and "store_enabled s acctype (unat address + 16) 16 (ucast value2_name :: 128 word) (CapIsTagSet value2_name)" + shows "traces_enabled (MemCP__1 address acctype value1_name value2_name) s" + unfolding MemCP__1_def bind_assoc + by (traces_enabledI assms: assms simp: DataFromCapability_def update_subrange_vec_dec_test_bit update_subrange_vec_dec_word_cat_cap_pair slice_128_cat_cap_pair) + +lemma traces_enabled_MemAtomicCompareAndSwap[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "VA_derivable base s" and "8 dvd LENGTH('a)" + shows "traces_enabled (MemAtomicCompareAndSwap base expval (newval :: 'a::len word) ldacctype stacctype) s" + unfolding MemAtomicCompareAndSwap_def AArch64_TranslateAddressForAtomicAccess_def Let_def bind_assoc + by (traces_enabledI assms: assms simp: exp_fails_if_then_else) + +lemma traces_enabled_MemAtomic[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "VA_derivable base s" and "8 dvd LENGTH('a)" + shows "traces_enabled (MemAtomic base op (data :: 'a::len word) ldacctype stacctype) s" + unfolding MemAtomic_def AArch64_TranslateAddressForAtomicAccess_def Let_def bind_assoc + by (traces_enabledI assms: assms simp: exp_fails_if_then_else) + +lemma traces_enabled_MemAtomicCompareAndSwapC[traces_enabledI]: + assumes "aligned (unat addr) 16 \ load_enabled s ldacctype (unat addr) 16 True" and "aligned (unat addr) 16 \ store_enabled s stacctype (unat addr) 16 (ucast newcap :: 128 word) (CapIsTagSet newcap)" and "newcap \ derivable_caps s" + shows "traces_enabled (MemAtomicCompareAndSwapC va addr expcap newcap ldacctype stacctype) s" + unfolding MemAtomicCompareAndSwapC_def AArch64_TranslateAddressForAtomicAccess_def Let_def bind_assoc + by (traces_enabledI assms: assms simp: exp_fails_if_then_else update_subrange_vec_dec_test_bit) + +lemma traces_enabled_MemAtomicC[traces_enabledI]: + assumes "aligned (unat address) 16 \ load_enabled s ldacctype (unat address) 16 True" and "aligned (unat address) 16 \ store_enabled s stacctype (unat address) 16 (ucast value_name :: 128 word) (CapIsTagSet value_name)" and "value_name \ derivable_caps s" + shows "traces_enabled (MemAtomicC address op value_name ldacctype stacctype) s" + unfolding MemAtomicC_def AArch64_TranslateAddressForAtomicAccess_def Let_def bind_assoc + by (traces_enabledI assms: assms simp: DataFromCapability_def update_subrange_vec_dec_test_bit test_bit_of_bl exp_fails_if_then_else) + +lemma traces_enabled_CAP_DC_ZVA[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "cval \ derivable_caps s" + shows "traces_enabled (CAP_DC_ZVA cval) s" + unfolding CAP_DC_ZVA_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_AArch64_SysInstrWithCapability[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "val_name \ derivable_caps s" + shows "traces_enabled (AArch64_SysInstrWithCapability op0 op1 crn crm op2 val_name) s" + unfolding AArch64_SysInstrWithCapability_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDARB_R_R_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ALDARB_R_R_B acctype datasize n regsize t__arg) s" + unfolding execute_ALDARB_R_R_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDARB_R_R_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDARB_R_R_B L Rn Rt) s" + unfolding decode_ALDARB_R_R_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDAR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "AltBaseRegAuth n \ load_auths" + shows "traces_enabled (execute_ALDAR_C_R_C acctype n t__arg) s" + unfolding execute_ALDAR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDAR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "AltBaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_ALDAR_C_R_C L Rn Ct) s" + unfolding decode_ALDAR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDAR_R_R_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ALDAR_R_R_32 acctype datasize n regsize t__arg) s" + unfolding execute_ALDAR_R_R_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDAR_R_R_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDAR_R_R_32 L Rn Rt) s" + unfolding decode_ALDAR_R_R_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRB_R_RRB_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift = 0" and "l__550 = 0" and "regsize = 32" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDRB_R_RRB_B extend_type m n regsize l__550 shift t__arg) s" + unfolding execute_ALDRB_R_RRB_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRB_R_RRB_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRB_R_RRB_B L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDRB_R_RRB_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRB_R_RUI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ALDRB_R_RUI_B datasize n offset regsize t__arg) s" + unfolding execute_ALDRB_R_RUI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRB_R_RUI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRB_R_RUI_B L imm9 op Rn Rt) s" + unfolding decode_ALDRB_R_RUI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRH_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 1}" and "l__549 = 1" and "regsize = 32" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDRH_R_RRB_32 extend_type m n regsize l__549 shift t__arg) s" + unfolding execute_ALDRH_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRH_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRH_R_RRB_32 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDRH_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRSB_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift = 0" and "l__545 = 0" and "regsize = 32" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDRSB_R_RRB_32 extend_type m n regsize l__545 shift t__arg) s" + unfolding execute_ALDRSB_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRSB_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRSB_R_RRB_32 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDRSB_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRSB_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift = 0" and "l__546 = 0" and "regsize = 64" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDRSB_R_RRB_64 extend_type m n regsize l__546 shift t__arg) s" + unfolding execute_ALDRSB_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRSB_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRSB_R_RRB_64 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDRSB_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRSH_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 1}" and "l__543 = 1" and "regsize = 32" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDRSH_R_RRB_32 extend_type m n regsize l__543 shift t__arg) s" + unfolding execute_ALDRSH_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRSH_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRSH_R_RRB_32 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDRSH_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDRSH_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 1}" and "l__544 = 1" and "regsize = 64" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDRSH_R_RRB_64 extend_type m n regsize l__544 shift t__arg) s" + unfolding execute_ALDRSH_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDRSH_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDRSH_R_RRB_64 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDRSH_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "\invokes_indirect_caps" and "AltBaseRegAuth n \ load_auths" + shows "traces_enabled (execute_ALDR_C_RRB_C extend_type m n shift t__arg) s" + unfolding execute_ALDR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "AltBaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_ALDR_C_RRB_C Rm sign sz S L Rn Ct) s" + unfolding decode_ALDR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_C_RUI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "AltBaseRegAuth n \ load_auths" + shows "traces_enabled (execute_ALDR_C_RUI_C n offset t__arg) s" + unfolding execute_ALDR_C_RUI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_C_RUI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "AltBaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_ALDR_C_RUI_C L imm9 op Rn Ct) s" + unfolding decode_ALDR_C_RUI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 2}" and "l__548 = 2" and "regsize = 32" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDR_R_RRB_32 extend_type m n regsize l__548 shift t__arg) s" + unfolding execute_ALDR_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDR_R_RRB_32 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDR_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 3}" and "l__547 = 3" and "regsize = 64" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDR_R_RRB_64 extend_type m n regsize l__547 shift t__arg) s" + unfolding execute_ALDR_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDR_R_RRB_64 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDR_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_R_RUI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ALDR_R_RUI_32 datasize n offset regsize t__arg) s" + unfolding execute_ALDR_R_RUI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_R_RUI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDR_R_RUI_32 L imm9 op Rn Rt) s" + unfolding decode_ALDR_R_RUI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_R_RUI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 64" and "0 \ n" and "n \ 31" and "datasize = 64" + shows "traces_enabled (execute_ALDR_R_RUI_64 datasize n offset regsize t__arg) s" + unfolding execute_ALDR_R_RUI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_R_RUI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDR_R_RUI_64 L imm9 op Rn Rt) s" + unfolding decode_ALDR_R_RUI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_V_RRB_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 3}" and "l__542 = 3" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDR_V_RRB_D extend_type m n l__542 shift t__arg) s" + unfolding execute_ALDR_V_RRB_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_V_RRB_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDR_V_RRB_D L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDR_V_RRB_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDR_V_RRB_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 2}" and "l__541 = 2" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ALDR_V_RRB_S extend_type m n l__541 shift t__arg) s" + unfolding execute_ALDR_V_RRB_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDR_V_RRB_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDR_V_RRB_S L Rm sign sz S opc Rn Rt) s" + unfolding decode_ALDR_V_RRB_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURB_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ALDURB_R_RI_32 datasize n offset regsize t__arg) s" + unfolding execute_ALDURB_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURB_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURB_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURB_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURH_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 16" + shows "traces_enabled (execute_ALDURH_R_RI_32 datasize n offset regsize t__arg) s" + unfolding execute_ALDURH_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURH_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURH_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURH_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURSB_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ALDURSB_R_RI_32 datasize n offset regsize t__arg) s" + unfolding execute_ALDURSB_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURSB_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURSB_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURSB_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURSB_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 64" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ALDURSB_R_RI_64 datasize n offset regsize t__arg) s" + unfolding execute_ALDURSB_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURSB_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURSB_R_RI_64 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURSB_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURSH_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 16" + shows "traces_enabled (execute_ALDURSH_R_RI_32 datasize n offset regsize t__arg) s" + unfolding execute_ALDURSH_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURSH_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURSH_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURSH_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURSH_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 64" and "0 \ n" and "n \ 31" and "datasize = 16" + shows "traces_enabled (execute_ALDURSH_R_RI_64 datasize n offset regsize t__arg) s" + unfolding execute_ALDURSH_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURSH_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURSH_R_RI_64 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURSH_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDURSW_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 64" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ALDURSW_R_RI_64 datasize n offset regsize t__arg) s" + unfolding execute_ALDURSW_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDURSW_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDURSW_R_RI_64 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDURSW_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "AltBaseRegAuth n \ load_auths" + shows "traces_enabled (execute_ALDUR_C_RI_C n offset t__arg) s" + unfolding execute_ALDUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "AltBaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_ALDUR_C_RI_C op1 V imm9 op2 Rn Ct) s" + unfolding decode_ALDUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 32" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ALDUR_R_RI_32 datasize n offset regsize t__arg) s" + unfolding execute_ALDUR_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "regsize = 64" and "0 \ n" and "n \ 31" and "datasize = 64" + shows "traces_enabled (execute_ALDUR_R_RI_64 datasize n offset regsize t__arg) s" + unfolding execute_ALDUR_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_R_RI_64 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_V_RI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ALDUR_V_RI_B datasize n offset t__arg) s" + unfolding execute_ALDUR_V_RI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_V_RI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_V_RI_B op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_V_RI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_V_RI_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 64" + shows "traces_enabled (execute_ALDUR_V_RI_D datasize n offset t__arg) s" + unfolding execute_ALDUR_V_RI_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_V_RI_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_V_RI_D op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_V_RI_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_V_RI_H[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 16" + shows "traces_enabled (execute_ALDUR_V_RI_H datasize n offset t__arg) s" + unfolding execute_ALDUR_V_RI_H_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_V_RI_H[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_V_RI_H op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_V_RI_H_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_V_RI_Q[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 128" + shows "traces_enabled (execute_ALDUR_V_RI_Q datasize n offset t__arg) s" + unfolding execute_ALDUR_V_RI_Q_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_V_RI_Q[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_V_RI_Q op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_V_RI_Q_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ALDUR_V_RI_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ALDUR_V_RI_S datasize n offset t__arg) s" + unfolding execute_ALDUR_V_RI_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ALDUR_V_RI_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ALDUR_V_RI_S op1 V imm9 op2 Rn Rt) s" + unfolding decode_ALDUR_V_RI_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTLRB_R_R_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ASTLRB_R_R_B acctype datasize n t__arg) s" + unfolding execute_ASTLRB_R_R_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTLRB_R_R_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTLRB_R_R_B L Rn Rt) s" + unfolding decode_ASTLRB_R_R_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTLR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_ASTLR_C_R_C acctype n t__arg) s" + unfolding execute_ASTLR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTLR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTLR_C_R_C L Rn Ct) s" + unfolding decode_ASTLR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTLR_R_R_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ASTLR_R_R_32 acctype datasize n t__arg) s" + unfolding execute_ASTLR_R_R_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTLR_R_R_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTLR_R_R_32 L Rn Rt) s" + unfolding decode_ASTLR_R_R_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTRB_R_RRB_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift = 0" and "l__556 = 0" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTRB_R_RRB_B extend_type m n l__556 shift t__arg) s" + unfolding execute_ASTRB_R_RRB_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTRB_R_RRB_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTRB_R_RRB_B L Rm sign sz S opc Rn Rt) s" + unfolding decode_ASTRB_R_RRB_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTRB_R_RUI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ASTRB_R_RUI_B datasize n offset t__arg) s" + unfolding execute_ASTRB_R_RUI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTRB_R_RUI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTRB_R_RUI_B L imm9 op Rn Rt) s" + unfolding decode_ASTRB_R_RUI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTRH_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 1}" and "l__555 = 1" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTRH_R_RRB_32 extend_type m n l__555 shift t__arg) s" + unfolding execute_ASTRH_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTRH_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTRH_R_RRB_32 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ASTRH_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTR_C_RRB_C extend_type m n shift t__arg) s" + unfolding execute_ASTR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_C_RRB_C Rm sign sz S L Rn Ct) s" + unfolding decode_ASTR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_C_RUI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_ASTR_C_RUI_C n offset t__arg) s" + unfolding execute_ASTR_C_RUI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_C_RUI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_C_RUI_C L imm9 op Rn Ct) s" + unfolding decode_ASTR_C_RUI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 2}" and "l__554 = 2" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTR_R_RRB_32 extend_type m n l__554 shift t__arg) s" + unfolding execute_ASTR_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_R_RRB_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_R_RRB_32 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ASTR_R_RRB_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 3}" and "l__553 = 3" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTR_R_RRB_64 extend_type m n l__553 shift t__arg) s" + unfolding execute_ASTR_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_R_RRB_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_R_RRB_64 L Rm sign sz S opc Rn Rt) s" + unfolding decode_ASTR_R_RRB_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_R_RUI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ASTR_R_RUI_32 datasize n offset t__arg) s" + unfolding execute_ASTR_R_RUI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_R_RUI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_R_RUI_32 L imm9 op Rn Rt) s" + unfolding decode_ASTR_R_RUI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_R_RUI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 64" + shows "traces_enabled (execute_ASTR_R_RUI_64 datasize n offset t__arg) s" + unfolding execute_ASTR_R_RUI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_R_RUI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_R_RUI_64 L imm9 op Rn Rt) s" + unfolding decode_ASTR_R_RUI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_V_RRB_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 3}" and "l__552 = 3" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTR_V_RRB_D extend_type m n l__552 shift t__arg) s" + unfolding execute_ASTR_V_RRB_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_V_RRB_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_V_RRB_D L Rm sign sz S opc Rn Rt) s" + unfolding decode_ASTR_V_RRB_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTR_V_RRB_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 2}" and "l__551 = 2" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_ASTR_V_RRB_S extend_type m n l__551 shift t__arg) s" + unfolding execute_ASTR_V_RRB_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTR_V_RRB_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTR_V_RRB_S L Rm sign sz S opc Rn Rt) s" + unfolding decode_ASTR_V_RRB_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTURB_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ASTURB_R_RI_32 datasize n offset t__arg) s" + unfolding execute_ASTURB_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTURB_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTURB_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTURB_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTURH_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 16" + shows "traces_enabled (execute_ASTURH_R_RI_32 datasize n offset t__arg) s" + unfolding execute_ASTURH_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTURH_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTURH_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTURH_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_ASTUR_C_RI_C n offset t__arg) s" + unfolding execute_ASTUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_C_RI_C op1 V imm9 op2 Rn Ct) s" + unfolding decode_ASTUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ASTUR_R_RI_32 datasize n offset t__arg) s" + unfolding execute_ASTUR_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_R_RI_32[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_R_RI_32 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_R_RI_32_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 64" + shows "traces_enabled (execute_ASTUR_R_RI_64 datasize n offset t__arg) s" + unfolding execute_ASTUR_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_R_RI_64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_R_RI_64 op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_R_RI_64_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_V_RI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 8" + shows "traces_enabled (execute_ASTUR_V_RI_B datasize n offset t__arg) s" + unfolding execute_ASTUR_V_RI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_V_RI_B[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_V_RI_B op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_V_RI_B_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_V_RI_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 64" + shows "traces_enabled (execute_ASTUR_V_RI_D datasize n offset t__arg) s" + unfolding execute_ASTUR_V_RI_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_V_RI_D[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_V_RI_D op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_V_RI_D_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_V_RI_H[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 16" + shows "traces_enabled (execute_ASTUR_V_RI_H datasize n offset t__arg) s" + unfolding execute_ASTUR_V_RI_H_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_V_RI_H[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_V_RI_H op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_V_RI_H_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_V_RI_Q[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 128" + shows "traces_enabled (execute_ASTUR_V_RI_Q datasize n offset t__arg) s" + unfolding execute_ASTUR_V_RI_Q_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_V_RI_Q[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_V_RI_Q op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_V_RI_Q_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_ASTUR_V_RI_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "datasize = 32" + shows "traces_enabled (execute_ASTUR_V_RI_S datasize n offset t__arg) s" + unfolding execute_ASTUR_V_RI_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ASTUR_V_RI_S[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ASTUR_V_RI_S op1 V imm9 op2 Rn Rt) s" + unfolding decode_ASTUR_V_RI_S_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BLR_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "n = 29 \ 29 \ invoked_indirect_regs" and "RegAuth n \ load_auths" and "is_indirect_branch" + shows "traces_enabled (execute_BLR_CI_C branch_type n offset) s" + unfolding execute_BLR_CI_C_def bind_assoc + by (traces_enabledI assms: assms elim: VADeref_load_enabled) + +lemma traces_enabled_decode_BLR_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cn = 29 \ 29 \ invoked_indirect_regs" and "RegAuth (uint Cn) \ load_auths" and "is_indirect_branch" + shows "traces_enabled (decode_BLR_CI_C imm7 Cn) s" + unfolding decode_BLR_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_BR_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ n" and "n \ 31" and "n = 29 \ 29 \ invoked_indirect_regs" and "RegAuth n \ load_auths" and "is_indirect_branch" + shows "traces_enabled (execute_BR_CI_C branch_type n offset) s" + unfolding execute_BR_CI_C_def bind_assoc + by (traces_enabledI assms: assms elim: VADeref_load_enabled) + +lemma traces_enabled_decode_BR_CI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Cn = 29 \ 29 \ invoked_indirect_regs" and "RegAuth (uint Cn) \ load_auths" and "is_indirect_branch" + shows "traces_enabled (decode_BR_CI_C imm7 Cn) s" + unfolding decode_BR_CI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CASAL_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_CASAL_C_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_CASAL_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CASAL_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_CASAL_C_R_C L Cs R Rn Ct) s" + unfolding decode_CASAL_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CASA_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_CASA_C_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_CASA_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CASA_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_CASA_C_R_C L Cs R Rn Ct) s" + unfolding decode_CASA_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CASL_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_CASL_C_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_CASL_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CASL_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_CASL_C_R_C L Cs R Rn Ct) s" + unfolding decode_CASL_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_CAS_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_CAS_C_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_CAS_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_CAS_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_CAS_C_R_C L Cs R Rn Ct) s" + unfolding decode_CAS_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDAPR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDAPR_C_R_C acctype n t__arg) s" + unfolding execute_LDAPR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDAPR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDAPR_C_R_C Rn Ct) s" + unfolding decode_LDAPR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDAR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDAR_C_R_C acctype n t__arg) s" + unfolding execute_LDAR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDAR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDAR_C_R_C L Rn Ct) s" + unfolding decode_LDAR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDAXP_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDAXP_C_R_C acctype n t__arg t2) s" + unfolding execute_LDAXP_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDAXP_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDAXP_C_R_C L Ct2 Rn Ct) s" + unfolding decode_LDAXP_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDAXR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDAXR_C_R_C acctype n t__arg) s" + unfolding execute_LDAXR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDAXR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDAXR_C_R_C L Rn Ct) s" + unfolding decode_LDAXR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDCT_R_R[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDCT_R_R n t__arg) s" + unfolding execute_LDCT_R_R_def bind_assoc + by (traces_enabledI assms: assms intro: traces_enabled_foreachM_index_list_inv2[where Inv = "\idx addr _ s. addr = addr0 + word_of_int (idx * 16) \ {''PCC'', ''_R29''} \ accessible_regs s \ (idx = 0 \ valid_address AccType_NORMAL (unat addr0))" and var_a = addr0 for addr0] elim: VADeref_load_enabled AArch64_CapabilityTag_valid_address simp: wi_hom_syms) + +lemma traces_enabled_decode_LDCT_R_R[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDCT_R_R opc Rn Rt) s" + unfolding decode_LDCT_R_R_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDNP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDNP_C_RIB_C acctype n offset t__arg t2) s" + unfolding execute_LDNP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDNP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDNP_C_RIB_C L imm7 Ct2 Rn Ct) s" + unfolding decode_LDNP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDPBLR_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "t__arg = 29 \ n \ invoked_indirect_regs" and "RegAuth n \ load_auths" and "t__arg \ 29 \ \invokes_indirect_caps" and "is_indirect_branch" + shows "traces_enabled (execute_LDPBLR_C_C_C branch_type n t__arg) s" + unfolding execute_LDPBLR_C_C_C_def bind_assoc + by (traces_enabledI assms: assms elim: VADeref_load_enabled) + +lemma traces_enabled_decode_LDPBLR_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Ct = 29 \ uint Cn \ invoked_indirect_regs" and "RegAuth (uint Cn) \ load_auths" and "uint Ct \ 29 \ \invokes_indirect_caps" and "is_indirect_branch" + shows "traces_enabled (decode_LDPBLR_C_C_C opc Cn Ct) s" + unfolding decode_LDPBLR_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDPBR_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "t__arg = 29 \ n \ invoked_indirect_regs" and "RegAuth n \ load_auths" and "t__arg \ 29 \ \invokes_indirect_caps" and "is_indirect_branch" + shows "traces_enabled (execute_LDPBR_C_C_C branch_type n t__arg) s" + unfolding execute_LDPBR_C_C_C_def bind_assoc + by (traces_enabledI assms: assms elim: VADeref_load_enabled) + +lemma traces_enabled_decode_LDPBR_C_C_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "uint Ct = 29 \ uint Cn \ invoked_indirect_regs" and "RegAuth (uint Cn) \ load_auths" and "uint Ct \ 29 \ \invokes_indirect_caps" and "is_indirect_branch" + shows "traces_enabled (decode_LDPBR_C_C_C opc Cn Ct) s" + unfolding decode_LDPBR_C_C_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDP_CC_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDP_CC_RIAW_C acctype n offset t__arg t2) s" + unfolding execute_LDP_CC_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDP_CC_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDP_CC_RIAW_C L imm7 Ct2 Rn Ct) s" + unfolding decode_LDP_CC_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDP_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDP_C_RIBW_C acctype n offset t__arg t2) s" + unfolding execute_LDP_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDP_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDP_C_RIBW_C L imm7 Ct2 Rn Ct) s" + unfolding decode_LDP_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDP_C_RIB_C acctype n offset t__arg t2) s" + unfolding execute_LDP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDP_C_RIB_C L imm7 Ct2 Rn Ct) s" + unfolding decode_LDP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDR_C_I_C[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "\invokes_indirect_caps" and "PCCAuth \ load_auths" + shows "traces_enabled (execute_LDR_C_I_C offset t__arg) s" + unfolding execute_LDR_C_I_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDR_C_I_C[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "\invokes_indirect_caps" and "PCCAuth \ load_auths" + shows "traces_enabled (decode_LDR_C_I_C imm17 Ct) s" + unfolding decode_LDR_C_I_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDR_C_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDR_C_RIAW_C n offset t__arg) s" + unfolding execute_LDR_C_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDR_C_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDR_C_RIAW_C opc imm9 Rn Ct) s" + unfolding decode_LDR_C_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDR_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDR_C_RIBW_C n offset t__arg) s" + unfolding execute_LDR_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDR_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDR_C_RIBW_C opc imm9 Rn Ct) s" + unfolding decode_LDR_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDR_C_RRB_C extend_type m n shift t__arg) s" + unfolding execute_LDR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDR_C_RRB_C opc Rm sign sz S Rn Ct) s" + unfolding decode_LDR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDR_C_RUIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDR_C_RUIB_C n offset t__arg) s" + unfolding execute_LDR_C_RUIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDR_C_RUIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDR_C_RUIB_C L imm12 Rn Ct) s" + unfolding decode_LDR_C_RUIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDTR_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDTR_C_RIB_C n offset t__arg) s" + unfolding execute_LDTR_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDTR_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDTR_C_RIB_C opc imm9 Rn Ct) s" + unfolding decode_LDTR_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDUR_C_RI_C n offset t__arg) s" + unfolding execute_LDUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDUR_C_RI_C opc imm9 Rn Ct) s" + unfolding decode_LDUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDXP_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDXP_C_R_C acctype n t__arg t2) s" + unfolding execute_LDXP_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDXP_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDXP_C_R_C L Ct2 Rn Ct) s" + unfolding decode_LDXP_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_LDXR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_LDXR_C_R_C acctype n t__arg) s" + unfolding execute_LDXR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_LDXR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_LDXR_C_R_C L Rn Ct) s" + unfolding decode_LDXR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STCT_R_R[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STCT_R_R n t__arg) s" + unfolding execute_STCT_R_R_def bind_assoc + by (traces_enabledI assms: assms elim: VADeref_store_enabled and_SystemAccessEnabled_TagSettingEnabledE[where thesis = "(if a then x else y) = z" and a = a for a x y z]) + +lemma traces_enabled_decode_STCT_R_R[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STCT_R_R opc Rn Rt) s" + unfolding decode_STCT_R_R_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STLR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STLR_C_R_C acctype n t__arg) s" + unfolding execute_STLR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STLR_C_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STLR_C_R_C L Rn Ct) s" + unfolding decode_STLR_C_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STLXP_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STLXP_R_CR_C acctype n s__arg t__arg t2) s" + unfolding execute_STLXP_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STLXP_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STLXP_R_CR_C L Rs Ct2 Rn Ct) s" + unfolding decode_STLXP_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STLXR_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STLXR_R_CR_C acctype n s__arg t__arg) s" + unfolding execute_STLXR_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STLXR_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STLXR_R_CR_C L Rs Rn Ct) s" + unfolding decode_STLXR_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STNP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STNP_C_RIB_C acctype n offset t__arg t2) s" + unfolding execute_STNP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STNP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STNP_C_RIB_C L imm7 Ct2 Rn Ct) s" + unfolding decode_STNP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STP_CC_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STP_CC_RIAW_C acctype n offset t__arg t2) s" + unfolding execute_STP_CC_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STP_CC_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STP_CC_RIAW_C L imm7 Ct2 Rn Ct) s" + unfolding decode_STP_CC_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STP_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STP_C_RIBW_C acctype n offset t__arg t2) s" + unfolding execute_STP_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STP_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STP_C_RIBW_C L imm7 Ct2 Rn Ct) s" + unfolding decode_STP_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STP_C_RIB_C acctype n offset t__arg t2) s" + unfolding execute_STP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STP_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STP_C_RIB_C L imm7 Ct2 Rn Ct) s" + unfolding decode_STP_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STR_C_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STR_C_RIAW_C n offset t__arg) s" + unfolding execute_STR_C_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STR_C_RIAW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STR_C_RIAW_C opc imm9 Rn Ct) s" + unfolding decode_STR_C_RIAW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STR_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STR_C_RIBW_C n offset t__arg) s" + unfolding execute_STR_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STR_C_RIBW_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STR_C_RIBW_C opc imm9 Rn Ct) s" + unfolding decode_STR_C_RIBW_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" + shows "traces_enabled (execute_STR_C_RRB_C extend_type m n shift t__arg) s" + unfolding execute_STR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STR_C_RRB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STR_C_RRB_C opc Rm sign sz S Rn Ct) s" + unfolding decode_STR_C_RRB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STR_C_RUIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STR_C_RUIB_C n offset t__arg) s" + unfolding execute_STR_C_RUIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STR_C_RUIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STR_C_RUIB_C L imm12 Rn Ct) s" + unfolding decode_STR_C_RUIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STTR_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STTR_C_RIB_C n offset t__arg) s" + unfolding execute_STTR_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STTR_C_RIB_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STTR_C_RIB_C opc imm9 Rn Ct) s" + unfolding decode_STTR_C_RIB_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STUR_C_RI_C n offset t__arg) s" + unfolding execute_STUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STUR_C_RI_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STUR_C_RI_C opc imm9 Rn Ct) s" + unfolding decode_STUR_C_RI_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STXP_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STXP_R_CR_C acctype n s__arg t__arg t2) s" + unfolding execute_STXP_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STXP_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STXP_R_CR_C L Rs Ct2 Rn Ct) s" + unfolding decode_STXP_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_STXR_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" + shows "traces_enabled (execute_STXR_R_CR_C acctype n s__arg t__arg) s" + unfolding execute_STXR_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_STXR_R_CR_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_STXR_R_CR_C L Rs Rn Ct) s" + unfolding decode_STXR_R_CR_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SWPAL_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_SWPAL_CC_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_SWPAL_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SWPAL_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_SWPAL_CC_R_C A R Cs Rn Ct) s" + unfolding decode_SWPAL_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SWPA_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_SWPA_CC_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_SWPA_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SWPA_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_SWPA_CC_R_C A R Cs Rn Ct) s" + unfolding decode_SWPA_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SWPL_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_SWPL_CC_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_SWPL_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SWPL_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_SWPL_CC_R_C A R Cs Rn Ct) s" + unfolding decode_SWPL_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_SWP_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "\invokes_indirect_caps" and "BaseRegAuth n \ load_auths" + shows "traces_enabled (execute_SWP_CC_R_C ldacctype n s__arg stacctype t__arg) s" + unfolding execute_SWP_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_SWP_CC_R_C[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "\invokes_indirect_caps" and "BaseRegAuth (uint Rn) \ load_auths" + shows "traces_enabled (decode_SWP_CC_R_C A R Cs Rn Ct) s" + unfolding decode_SWP_CC_R_C_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_atomicops_cas_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_atomicops_cas_single (datasize :: 'datasize::len itself) ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg) s" + unfolding execute_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cas_aarch64_instrs_memory_atomicops_cas_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_cas_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs L b__0) s" + unfolding decode_cas_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_casb_aarch64_instrs_memory_atomicops_cas_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_casb_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs L b__0) s" + unfolding decode_casb_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_cash_aarch64_instrs_memory_atomicops_cas_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_cash_aarch64_instrs_memory_atomicops_cas_single Rt Rn o0 Rs L b__0) s" + unfolding decode_cash_aarch64_instrs_memory_atomicops_cas_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_atomicops_cas_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "l__38 \ {32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_atomicops_cas_pair l__38 ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg) s" + unfolding execute_aarch64_instrs_memory_atomicops_cas_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_casp_aarch64_instrs_memory_atomicops_cas_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_casp_aarch64_instrs_memory_atomicops_cas_pair Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_casp_aarch64_instrs_memory_atomicops_cas_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "LENGTH('esize) \ {8, 16, 32, 64}" and "LENGTH('datasize) \ {64, 128}" and "elements = int LENGTH('datasize) div int LENGTH('esize)" and "rpt \ {1, 2, 3, 4}" and "selem \ {1, 2, 3, 4}" + shows "traces_enabled (execute_aarch64_instrs_memory_vector_multiple_no_wb (datasize :: 'datasize::len itself) elements (esize :: 'esize::len itself) m memop n rpt selem t__arg wback) s" + unfolding execute_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc Let_def case_prod_beta + by (traces_enabledI assms: assms intro: traces_enabled_triple_foreachM_index_list_inv[where Inv = "Inv_vector_multiple_no_wb (LENGTH('esize) div 8) elements selem base" and body = "\idx_a idx_b idx_c (vars :: (64 word * 'datasize word * int)). (V_read _ (snd (snd vars)) :: 'datasize word M) \ (\w. (if memop = MemOp_LOAD then Mem_read0 (add_vec base (fst vars)) _ _ \ (_ w idx_b vars :: 'esize word \ 'datasize word M) else _ w base idx_b vars) \ (_ vars :: 'datasize word \ (64 word * 'datasize word * int) M))" for base :: "64 word"] elim: Run_bindE[where thesis = "Inv_vector_multiple_no_wb _ _ _ _ _ _ (_ + 1) _ _"] Run_ifE[where thesis = "Inv_vector_multiple_no_wb _ _ _ _ _ _ (_ + 1) _ _"] Inv_vector_multiple_no_wb_step Mem_read0_valid_address Mem_set0_valid_address simp: unat_0_iff) + +lemma traces_enabled_decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_ld1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "selem \ {1, 2, 3, 4}" and "0 \ n" and "n \ 31" and "int LENGTH('esize) \ {8, 16, 32, 64}" and "int LENGTH('datasize) \ {64, 128}" + shows "traces_enabled (execute_aarch64_instrs_memory_vector_single_no_wb (datasize :: 'datasize::len itself) (esize :: 'esize::len itself) index__arg m memop n replicate__arg selem t__arg wback) s" + unfolding execute_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc Let_def case_prod_beta + by (traces_enabledI assms: assms intro: traces_enabled_foreachM_index_list_inv[where Inv = "\idx vars s. Inv_vector_single_no_wb ebytes idx address (fst (snd vars))" and body = "\s (vars :: ('esize word * 64 word * int)). (Mem_read0 (add_vec address (fst (snd vars))) ebytes _ :: 'esize word M) \ (\w. _ w vars :: ('esize word * 64 word * int) M)" for address :: "64 word" and ebytes] traces_enabled_foreachM_index_list_inv[where Inv = "\idx vars s. Inv_vector_single_no_wb ebytes idx address (fst vars)" and body = "\s (vars :: 64 word * 128 word * int). (V_read 128 (snd (snd vars)) :: 128 word M) \ (\w. (if memop = MemOp_LOAD then Mem_read0 (add_vec address (fst vars)) ebytes _ \ (\w'. _ w' w vars :: 128 word M) else (_ w vars :: 128 word M)) \ (\w'. _ w' w vars :: (64 word * 128 word * int) M))" for address :: "64 word" and ebytes] elim: Run_bindE[where thesis = "Inv_vector_single_no_wb _ (_ + 1) _ _"] Run_ifE[where thesis = "Inv_vector_single_no_wb _ (_ + 1) _ _"] Mem_read0_valid_address Mem_set0_valid_address simp: unat_0_iff) + +lemma traces_enabled_decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld1r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_ld2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld2r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_ld3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld3r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_ld4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_ld4r_advsimd_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_atomicops_ld (datasize :: 'datasize::len itself) ldacctype n op (regsize :: 'regsize::len itself) s__arg stacctype t__arg) s" + unfolding execute_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldadd_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldadd_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldadd_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaddb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaddb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldaddb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaddh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaddh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldaddh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_ordered_rcpc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_ordered_rcpc acctype (datasize :: 'datasize::len itself) n (regsize :: 'regsize::len itself) t__arg) s" + unfolding execute_aarch64_instrs_memory_ordered_rcpc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldapr_aarch64_instrs_memory_ordered_rcpc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldapr_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs b__0) s" + unfolding decode_ldapr_aarch64_instrs_memory_ordered_rcpc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaprb_aarch64_instrs_memory_ordered_rcpc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaprb_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs b__0) s" + unfolding decode_ldaprb_aarch64_instrs_memory_ordered_rcpc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaprh_aarch64_instrs_memory_ordered_rcpc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaprh_aarch64_instrs_memory_ordered_rcpc Rt Rn Rs b__0) s" + unfolding decode_ldaprh_aarch64_instrs_memory_ordered_rcpc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_ordered acctype (datasize :: 'datasize::len itself) memop n (regsize :: 'regsize::len itself) t__arg) s" + unfolding execute_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldar_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldar_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldar_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldarb_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldarb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldarb_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldarh_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldarh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldarh_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_exclusive_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "LENGTH('regsize) \ {32, 64} \ elsize \ {32, 64} \ datasize = 2 * elsize" + shows "traces_enabled (execute_aarch64_instrs_memory_exclusive_pair acctype datasize elsize memop n True (regsize :: 'regsize::len itself) s__arg t__arg t2) s" + unfolding execute_aarch64_instrs_memory_exclusive_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaxp_aarch64_instrs_memory_exclusive_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldaxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "LENGTH('regsize) \ {32, 64} \ elsize \ {8, 16, 32, 64} \ datasize = elsize" + shows "traces_enabled (execute_aarch64_instrs_memory_exclusive_single acctype datasize elsize memop n False (regsize :: 'regsize::len itself) s__arg t__arg t2) s" + unfolding execute_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaxr_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldaxr_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaxrb_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldaxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldaxrh_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldaxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldaxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldclr_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldclr_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldclr_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldclrb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldclrb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldclrb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldclrh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldclrh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldclrh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldeor_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldeor_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldeor_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldeorb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldeorb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldeorb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldeorh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldeorh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldeorh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldlar_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldlar_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldlar_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldlarb_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldlarb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldlarb_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldlarh_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldlarh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldlarh_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_pair_simdfp_no_alloc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {32, 64, 128, 256}" + shows "traces_enabled (execute_aarch64_instrs_memory_pair_simdfp_no_alloc acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback) s" + unfolding execute_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_pair_general_no_alloc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_pair_general_no_alloc acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback) s" + unfolding execute_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldnp_gen_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_pair_simdfp_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {32, 64, 128, 256}" + shows "traces_enabled (execute_aarch64_instrs_memory_pair_simdfp_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg t2 wback) s" + unfolding execute_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_pair_general_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t2" and "t2 \ 31" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_pair_general_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex is_signed t__arg t2 wback__arg) s" + unfolding execute_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldp_gen_aarch64_instrs_memory_pair_general_offset[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldp_gen_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldp_gen_aarch64_instrs_memory_pair_general_offset_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldp_gen_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldp_gen_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldpsw_aarch64_instrs_memory_pair_general_offset[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldpsw_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldpsw_aarch64_instrs_memory_pair_general_offset_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldpsw_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_ldpsw_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128, 256, 512, 1024}" + shows "traces_enabled (execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg wback) s" + unfolding execute_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldr_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg) s" + unfolding execute_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldr_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_literal_simdfp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "l__44 \ {4, 8, 16}" + shows "traces_enabled (execute_aarch64_instrs_memory_literal_simdfp offset l__44 t__arg) s" + unfolding execute_aarch64_instrs_memory_literal_simdfp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp Rt imm19 opc) s" + unfolding decode_ldr_lit_fpsimd_aarch64_instrs_memory_literal_simdfp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_literal_general[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "l__200 \ {4, 8}" + shows "traces_enabled (execute_aarch64_instrs_memory_literal_general memop offset is_signed l__200 t__arg) s" + unfolding execute_aarch64_instrs_memory_literal_general_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_lit_gen_aarch64_instrs_memory_literal_general[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_lit_gen_aarch64_instrs_memory_literal_general Rt imm19 opc) s" + unfolding decode_ldr_lit_gen_aarch64_instrs_memory_literal_general_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_simdfp_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (execute_aarch64_instrs_memory_single_simdfp_register acctype (datasize :: 'datasize::len itself) extend_type m memop n postindex shift t__arg wback) s" + unfolding execute_aarch64_instrs_memory_single_simdfp_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldr_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "shift \ {0, 1, 2, 3}" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "0 \ m" and "m \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_single_general_register acctype (datasize :: 'datasize::len itself) extend_type m memop n postindex (regsize :: 'regsize::len itself) shift is_signed t__arg wback__arg) s" + unfolding execute_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldr_reg_gen_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldrb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrb_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldrb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldrh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrh_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldrh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldrsb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsb_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldrsb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldrsh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsh_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldrsh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_ldrsw_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsw_lit_aarch64_instrs_memory_literal_general[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsw_lit_aarch64_instrs_memory_literal_general Rt imm19 opc) s" + unfolding decode_ldrsw_lit_aarch64_instrs_memory_literal_general_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldrsw_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldrsw_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_ldrsw_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldset_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldset_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldset_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsetb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsetb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsetb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldseth_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldseth_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldseth_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsmax_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsmax_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsmax_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsmaxb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsmaxh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsmin_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsmin_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsmin_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsminb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsminb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsminb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldsminh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldsminh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldsminh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg) s" + unfolding execute_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldtr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldtrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldtrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldtrsb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldtrsh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldtrsw_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldumax_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldumax_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldumax_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldumaxb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldumaxb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldumaxb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldumaxh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldumaxh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldumaxh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldumin_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldumin_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_ldumin_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_lduminb_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_lduminb_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_lduminb_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_lduminh_aarch64_instrs_memory_atomicops_ld[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_lduminh_aarch64_instrs_memory_atomicops_ld Rt Rn opc Rs R A b__0) s" + unfolding decode_lduminh_aarch64_instrs_memory_atomicops_ld_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64, 128, 256, 512, 1024}" + shows "traces_enabled (execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal acctype (datasize :: 'datasize::len itself) memop n offset postindex t__arg wback) s" + unfolding execute_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg) s" + unfolding execute_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldurb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldurh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldursb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldursh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_ldursw_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldxp_aarch64_instrs_memory_exclusive_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldxr_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldxr_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldxrb_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_ldxrh_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_ldxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_ldxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_single_general_immediate_unsigned acctype (datasize :: 'datasize::len itself) memop n offset postindex (regsize :: 'regsize::len itself) is_signed t__arg wback__arg) s" + unfolding execute_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_prfm_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_prfm_lit_aarch64_instrs_memory_literal_general[traces_enabledI]: + assumes "{''PCC''} \ accessible_regs s" + shows "traces_enabled (decode_prfm_lit_aarch64_instrs_memory_literal_general Rt imm19 opc) s" + unfolding decode_prfm_lit_aarch64_instrs_memory_literal_general_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_prfm_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_prfm_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_prfm_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_prfum_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_st1_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_st1_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_st2_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_st2_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_st3_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_st3_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb Rt Rn b__0 opcode L b__1) s" + unfolding decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc Rt Rn b__0 opcode Rm L b__1) s" + unfolding decode_st4_advsimd_mult_aarch64_instrs_memory_vector_multiple_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb Rt Rn b__0 S b__1 R L b__2) s" + unfolding decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_no_wb_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc Rt Rn b__0 S b__1 Rm R L b__2) s" + unfolding decode_st4_advsimd_sngl_aarch64_instrs_memory_vector_single_post_inc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ s__arg" and "s__arg \ 31" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_atomicops_st (datasize :: 'datasize::len itself) ldacctype n op s__arg stacctype) s" + unfolding execute_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stadd_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stadd_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stadd_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_staddb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_staddb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_staddb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_staddh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_staddh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_staddh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stclr_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stclr_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stclr_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stclrb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stclrb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stclrb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stclrh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stclrh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stclrh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_steor_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_steor_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_steor_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_steorb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_steorb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_steorb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_steorh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_steorh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_steorh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stllr_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stllr_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stllr_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stllrb_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stllrb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stllrb_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stllrh_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stllrh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stllrh_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlr_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlr_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlr_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlrb_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlrb_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlrb_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlrh_aarch64_instrs_memory_ordered[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlrh_aarch64_instrs_memory_ordered Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlrh_aarch64_instrs_memory_ordered_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlxp_aarch64_instrs_memory_exclusive_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlxr_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlxr_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlxrb_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stlxrh_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stlxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stlxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stnp_fpsimd_aarch64_instrs_memory_pair_simdfp_no_alloc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stnp_gen_aarch64_instrs_memory_pair_general_no_alloc_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_offset_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stp_fpsimd_aarch64_instrs_memory_pair_simdfp_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stp_gen_aarch64_instrs_memory_pair_general_offset[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stp_gen_aarch64_instrs_memory_pair_general_offset Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stp_gen_aarch64_instrs_memory_pair_general_offset_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stp_gen_aarch64_instrs_memory_pair_general_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx Rt Rn Rt2 imm7 L b__0) s" + unfolding decode_stp_gen_aarch64_instrs_memory_pair_general_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_str_imm_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_str_imm_gen_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_str_reg_fpsimd_aarch64_instrs_memory_single_simdfp_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_str_reg_gen_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_str_reg_gen_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_str_reg_gen_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_strb_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_strb_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strb_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strb_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_strb_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_post_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx Rt Rn imm9 b__0 b__1) s" + unfolding decode_strh_imm_aarch64_instrs_memory_single_general_immediate_signed_pre_idx_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned Rt Rn imm12 b__0 b__1) s" + unfolding decode_strh_imm_aarch64_instrs_memory_single_general_immediate_unsigned_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_strh_reg_aarch64_instrs_memory_single_general_register[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_strh_reg_aarch64_instrs_memory_single_general_register Rt Rn S option_name Rm b__0 b__1) s" + unfolding decode_strh_reg_aarch64_instrs_memory_single_general_register_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stset_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stset_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stset_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsetb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsetb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsetb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stseth_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stseth_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stseth_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsmax_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsmax_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsmax_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsmaxb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsmaxb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsmaxb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsmaxh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsmaxh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsmaxh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsmin_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsmin_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsmin_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsminb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsminb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsminb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stsminh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stsminh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stsminh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_sttr_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_sttrb_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv Rt Rn imm9 b__0 b__1) s" + unfolding decode_sttrh_aarch64_instrs_memory_single_general_immediate_signed_offset_unpriv_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stumax_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stumax_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stumax_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stumaxb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stumaxb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stumaxb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stumaxh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stumaxh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stumaxh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stumin_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stumin_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stumin_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stuminb_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stuminb_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stuminb_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stuminh_aarch64_instrs_memory_atomicops_st[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stuminh_aarch64_instrs_memory_atomicops_st Rn opc o3 Rs R A V b__0) s" + unfolding decode_stuminh_aarch64_instrs_memory_atomicops_st_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_stur_fpsimd_aarch64_instrs_memory_single_simdfp_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_stur_gen_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_sturb_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal Rt Rn imm9 b__0 b__1) s" + unfolding decode_sturh_aarch64_instrs_memory_single_general_immediate_signed_offset_normal_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stxp_aarch64_instrs_memory_exclusive_pair[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stxp_aarch64_instrs_memory_exclusive_pair Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stxp_aarch64_instrs_memory_exclusive_pair_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stxr_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stxr_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stxr_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stxrb_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stxrb_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stxrb_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_stxrh_aarch64_instrs_memory_exclusive_single[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_stxrh_aarch64_instrs_memory_exclusive_single Rt Rn Rt2 o0 Rs L b__0) s" + unfolding decode_stxrh_aarch64_instrs_memory_exclusive_single_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_memory_atomicops_swp[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "0 \ s__arg" and "s__arg \ 31" and "int LENGTH('regsize) \ {32, 64}" and "0 \ n" and "n \ 31" and "int LENGTH('datasize) \ {8, 16, 32, 64}" + shows "traces_enabled (execute_aarch64_instrs_memory_atomicops_swp (datasize :: 'datasize::len itself) ldacctype n (regsize :: 'regsize::len itself) s__arg stacctype t__arg) s" + unfolding execute_aarch64_instrs_memory_atomicops_swp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_swp_aarch64_instrs_memory_atomicops_swp[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_swp_aarch64_instrs_memory_atomicops_swp Rt Rn Rs R A b__0) s" + unfolding decode_swp_aarch64_instrs_memory_atomicops_swp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_swpb_aarch64_instrs_memory_atomicops_swp[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_swpb_aarch64_instrs_memory_atomicops_swp Rt Rn Rs R A b__0) s" + unfolding decode_swpb_aarch64_instrs_memory_atomicops_swp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_swph_aarch64_instrs_memory_atomicops_swp[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_swph_aarch64_instrs_memory_atomicops_swp Rt Rn Rs R A b__0) s" + unfolding decode_swph_aarch64_instrs_memory_atomicops_swp_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_execute_aarch64_instrs_system_sysops[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "0 \ t__arg" and "t__arg \ 31" and "sys_op2 \ {0, 1, 2, 3, 4, 5, 6, 7}" and "sys_op1 \ {0, 1, 2, 3, 4, 5, 6, 7}" and "sys_op0 = 1" and "0 \ sys_crn" and "sys_crn \ 15" and "0 \ sys_crm" and "sys_crm \ 15" + shows "traces_enabled (execute_aarch64_instrs_system_sysops has_result sys_crm sys_crn sys_op0 sys_op1 sys_op2 t__arg) s" + unfolding execute_aarch64_instrs_system_sysops_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sys_aarch64_instrs_system_sysops[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sys_aarch64_instrs_system_sysops Rt op2 CRm CRn op1 L) s" + unfolding decode_sys_aarch64_instrs_system_sysops_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_decode_sysl_aarch64_instrs_system_sysops[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" + shows "traces_enabled (decode_sysl_aarch64_instrs_system_sysops Rt op2 CRm CRn op1 L) s" + unfolding decode_sysl_aarch64_instrs_system_sysops_def bind_assoc + by (traces_enabledI assms: assms) + +lemma traces_enabled_DecodeA64[traces_enabledI]: + assumes "{''PCC'', ''_R29''} \ accessible_regs s" and "instr_exp_assms (DecodeA64 pc opcode)" and "no_system_reg_access" + shows "traces_enabled (DecodeA64 pc opcode) s" + using assms(2) + by (unfold DecodeA64_def, elim instr_exp_assms_traces_enabled_ifE instr_exp_assms_traces_enabled_letE) (solves \traces_enabledI assms: assms(1) intro: assms(3) simp: instr_exp_assms_def invocation_instr_exp_assms_write_ThisInstrAbstract_iff load_instr_exp_assms_write_ThisInstrAbstract_iff\)+ + +end + +end diff --git a/Makefile b/Makefile index 31586f5..5d085a0 100644 --- a/Makefile +++ b/Makefile @@ -22,12 +22,21 @@ else LEM_DIR:=$(shell opam config var lem:share) endif +# Check if the sail-morello directory has snapshots of the Lem and Sail Isabelle libraries +ifneq ($(wildcard $(MORELLO_DIR)/lib/isabelle),) + SAIL_LEM_LIB = $(MORELLO_DIR)/lib/isabelle/lem + SAIL_ISA_LIB = $(MORELLO_DIR)/lib/isabelle/sail +else + SAIL_LEM_LIB = $(LEM_DIR)/isabelle-lib + SAIL_ISA_LIB = $(SAIL_DIR)/lib/isabelle +endif + GEN_LEMMAS = $(T_CHERI_DIR)/tools/gen_lemmas MORELLO_SAIL_DIR = $(MORELLO_DIR)/src MORELLO_ISA_DIR = $(MORELLO_DIR)/isabelle MORELLO_PATCHES_DIR = $(MORELLO_SAIL_DIR)/patches -ISA_DEPS = $(LEM_DIR)/isabelle-lib $(SAIL_DIR)/lib/isabelle $(AFP_DIR)/thys/Word_Lib $(T_CHERI_DIR)/model/isabelle $(MORELLO_ISA_DIR) +ISA_DEPS = $(SAIL_LEM_LIB) $(SAIL_ISA_LIB) $(AFP_DIR)/thys/Word_Lib $(T_CHERI_DIR)/model/isabelle $(MORELLO_ISA_DIR) ISA_DEP_FLAGS = $(foreach dir,$(ISA_DEPS),-d $(dir)) ISA_BUILD_FLAGS = -v $(ISA_DEP_FLAGS)