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Reverting to faac06f version of config.json
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Peter-Herrmann committed Oct 30, 2023
1 parent c96009a commit 26d189d
Showing 1 changed file with 8 additions and 8 deletions.
16 changes: 8 additions & 8 deletions openlane/user_project_wrapper/config.json
Original file line number Diff line number Diff line change
Expand Up @@ -64,24 +64,24 @@
"dir::../../verilog/rtl/rtl/soc/soc.sv",
"dir::../../verilog/rtl/carp-lib/obi_qspi_controller/spimemio.v"
],
"VERILOG_INCLUDE_DIRS": "pdk_dir::libs.ref/sky130_sram_macros/verilog",
"VERILOG_FILES_BLACKBOX": "dir::../macros/sky130_sram_2kbyte_1rw1r_32x512_8.v",
"EXTRA_LEFS": "pdk_dir::libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef",
"EXTRA_LIBS": "pdk_dir::libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib",
"EXTRA_GDS_FILES": "pdk_dir::libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds",
"VERILOG_INCLUDE_DIRS": ["dir::../../../../pdk/sky130A/libs.ref/sky130_sram_macros/"],
"VERILOG_FILES_BLACKBOX": ["dir::../macros/sky130_sram_2kbyte_1rw1r_32x512_8.v"],
"EXTRA_LEFS": ["dir::../../../../pdk/sky130A/libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef"],
"EXTRA_LIBS": ["dir::../../../../pdk/sky130A/libs.ref/sky130_sram_macros/lib/sky130_sram_2kbyte_1rw1r_32x512_8_TT_1p8V_25C.lib"],
"EXTRA_GDS_FILES": ["dir::../../../../pdk/sky130A/libs.ref/sky130_sram_macros/gds/sky130_sram_2kbyte_1rw1r_32x512_8.gds"],
"ROUTING_CORES": 20,
"KLAYOUT_XOR_THREADS": 20,
"FP_IO_UNMATCHED_ERROR": 0,
"FP_PDN_MACRO_HOOKS": "soc_i.sram.sram0 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram1 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram2 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram3 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram4 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram5 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram6 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram7 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram8 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram9 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram10 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram11 vccd1 vssd1 vccd1 vssd1",
"QUIT_ON_LVS_ERROR": 0,
"CLOCK_PERIOD": 100,
"CLOCK_PERIOD": 50,
"CLOCK_PORT": "user_clock2",
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 2920 3520",
"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
"MAX_TRANSITION_CONSTRAINT": 1.0,
"MAX_FANOUT_CONSTRAINT": 16,
"PL_TARGET_DENSITY": 0.41,
"PL_TARGET_DENSITY": 0.30,
"LEC_ENABLE": 0,
"GRT_OVERFLOW_ITERS": 100000,
"PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
Expand Down Expand Up @@ -168,4 +168,4 @@
"SYNTH_MAX_FANOUT": 4,
"PL_TARGET_DENSITY": 0.45
}
}
}

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