diff --git a/openlane/user_project_wrapper/config.json b/openlane/user_project_wrapper/config.json
index 65eceaf..c1445c8 100644
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -78,7 +78,7 @@
     "ROUTING_CORES": 20,
 	"KLAYOUT_XOR_THREADS": 20,
 	"FP_IO_UNMATCHED_ERROR": 0,
-    "FP_PDN_MACRO_HOOKS": "soc_i.sram.sram0 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram1 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram2 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram3 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram4 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram5 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram6 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram7 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram8 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram9 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram10 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram11 vccd1 vssd1 vccd1 vssd1",
+    "FP_PDN_MACRO_HOOKS": "soc_i.sram.sram0 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram1 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram2 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram3 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram4 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram5 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram6 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram7 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram8 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram9 vccd1 vssd1 vccd1 vssd1",
 	"CLOCK_PORT": "user_clock2",
     "FP_SIZING": "absolute",
     "DIE_AREA": "0 0 2920 3520",
diff --git a/openlane/user_project_wrapper/macro.cfg b/openlane/user_project_wrapper/macro.cfg
index ab2da13..b4da2cf 100644
--- a/openlane/user_project_wrapper/macro.cfg
+++ b/openlane/user_project_wrapper/macro.cfg
@@ -1,13 +1,11 @@
-soc_i.sram.sram0 566.9 300 R180
-soc_i.sram.sram1 566.9 786.692 MY
-soc_i.sram.sram2 566.9 1253.384 R180
-soc_i.sram.sram3 566.9 1710.076 MY
-soc_i.sram.sram4 566.9 2196.768 R180
-soc_i.sram.sram5 566.9 2683.46 MY
+soc_i.sram.sram0 376.9 400 R180
+soc_i.sram.sram1 376.9 975.865 MY
+soc_i.sram.sram2 376.9 1551.73 R180
+soc_i.sram.sram3 376.9 2127.595 MY
+soc_i.sram.sram4 376.9 2703.46 R180
 
-soc_i.sram.sram6 1670 300 MX
-soc_i.sram.sram7 1670 786.692 R0
-soc_i.sram.sram8 1670 1253.384 MX
-soc_i.sram.sram9 1670 1710.076 R0
-soc_i.sram.sram10 1670 2196.768 MX
-soc_i.sram.sram11 1670 2683.46 R0
\ No newline at end of file
+soc_i.sram.sram5 1860 400 MX
+soc_i.sram.sram6 1860 975.865 R0
+soc_i.sram.sram7 1860 1551.73 MX
+soc_i.sram.sram8 1860 2127.595 R0
+soc_i.sram.sram9 1860 2703.46 MX
\ No newline at end of file
diff --git a/verilog/rtl/rtl/soc/modules/sram_wrap.sv b/verilog/rtl/rtl/soc/modules/sram_wrap.sv
index dad0be5..e675417 100644
--- a/verilog/rtl/rtl/soc/modules/sram_wrap.sv
+++ b/verilog/rtl/rtl/soc/modules/sram_wrap.sv
@@ -12,7 +12,7 @@
 
 module sram_wrap #(
     parameter SRAM_BASE_ADDR      = 32'h8000_0000,
-    parameter SRAM_NUM_BLOCKS     = 12,
+    parameter SRAM_NUM_BLOCKS     = 10,
     parameter SRAM_BLOCK_SIZE     = 512,
     parameter SRAM_LOG_BLOCK_SIZE = $clog2(SRAM_BLOCK_SIZE),
     parameter SRAM_END_ADDR       = (SRAM_BASE_ADDR + (SRAM_NUM_BLOCKS * SRAM_BLOCK_SIZE)),
@@ -280,42 +280,6 @@ module sram_wrap #(
         .dout1     (sram_i_read_vec[9]) 
     );
 
-    sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram10 (
-    `ifdef USE_POWER_PINS
-        .vccd1(vccd1), // 1.8V
-        .vssd1(vssd1), // Digital ground
-    `endif
-        .clk0      (clk_i),
-        .csb0      (~cs_data[10]),   // Active Low
-        .web0      (~sram_d_we_i),  // Active Low
-        .wmask0    (sram_d_be_i),
-        .addr0     (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
-        .din0      (sram_d_wdata_i), 
-        .dout0     (sram_d_read_vec[10]), 
-        .clk1      (clk_i),
-        .csb1      (~cs_inst[10]),    // Active Low
-        .addr1     (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]), 
-        .dout1     (sram_i_read_vec[10]) 
-    );
-
-    sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram11 (
-    `ifdef USE_POWER_PINS
-        .vccd1(vccd1), // 1.8V
-        .vssd1(vssd1), // Digital ground
-    `endif
-        .clk0      (clk_i),
-        .csb0      (~cs_data[11]),   // Active Low
-        .web0      (~sram_d_we_i),  // Active Low
-        .wmask0    (sram_d_be_i),
-        .addr0     (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
-        .din0      (sram_d_wdata_i), 
-        .dout0     (sram_d_read_vec[11]), 
-        .clk1      (clk_i),
-        .csb1      (~cs_inst[11]),    // Active Low
-        .addr1     (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]), 
-        .dout1     (sram_i_read_vec[11]) 
-    );
-
 
 `ifdef VERILATOR
     logic [31:0] _unused;