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Adding More RAM #32

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Adding More RAM #32

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0c88d82
decreasing GRT_ADJUSTMENT to 0.1
Peter-Herrmann Nov 6, 2023
1822d9c
allow congestion
Peter-Herrmann Nov 6, 2023
0901de3
10 SRAMS (Revert b720c3b)
Peter-Herrmann Nov 6, 2023
dc47f8e
10, no congestion
Peter-Herrmann Nov 6, 2023
317a508
8 SRAMs, allow gongestion
Peter-Herrmann Nov 6, 2023
0c3599f
¿Por qué no los doce?
Peter-Herrmann Nov 6, 2023
e558139
12, allow congestion
Peter-Herrmann Nov 6, 2023
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4 changes: 3 additions & 1 deletion openlane/user_project_wrapper/config.json
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,9 @@
"RUN_LVS": 1,
"RUN_MAGIC_DRC": 1,
"YOSYS_REWRITE_VERILOG": 1,
"GRT_ALLOW_CONGESTION": 1,
"QUIT_ON_LINTER_ERRORS": 0,
"GRT_ADJUSTMENT": 0.1,
"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
"VERILOG_FILES": [
"dir::../../verilog/rtl/defines.v",
Expand Down Expand Up @@ -76,7 +78,7 @@
"ROUTING_CORES": 20,
"KLAYOUT_XOR_THREADS": 20,
"FP_IO_UNMATCHED_ERROR": 0,
"FP_PDN_MACRO_HOOKS": "soc_i.sram.sram0 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram1 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram2 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram3 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram4 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram5 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram6 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram7 vccd1 vssd1 vccd1 vssd1",
"FP_PDN_MACRO_HOOKS": "soc_i.sram.sram0 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram1 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram2 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram3 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram4 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram5 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram6 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram7 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram8 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram9 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram10 vccd1 vssd1 vccd1 vssd1, soc_i.sram.sram11 vccd1 vssd1 vccd1 vssd1",
"CLOCK_PORT": "user_clock2",
"FP_SIZING": "absolute",
"DIE_AREA": "0 0 2920 3520",
Expand Down
20 changes: 12 additions & 8 deletions openlane/user_project_wrapper/macro.cfg
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Original file line number Diff line number Diff line change
@@ -1,9 +1,13 @@
soc_i.sram.sram0 376.9 300 R180
soc_i.sram.sram1 376.9 1134.5 MY
soc_i.sram.sram2 376.9 1968.97 R180
soc_i.sram.sram3 376.9 2803.46 MY
soc_i.sram.sram0 566.9 300 R180
soc_i.sram.sram1 566.9 786.692 MY
soc_i.sram.sram2 566.9 1253.384 R180
soc_i.sram.sram3 566.9 1710.076 MY
soc_i.sram.sram4 566.9 2196.768 R180
soc_i.sram.sram5 566.9 2683.46 MY

soc_i.sram.sram4 1860 300 MX
soc_i.sram.sram5 1860 1134.5 R0
soc_i.sram.sram6 1860 1968.97 MX
soc_i.sram.sram7 1860 2803.46 R0
soc_i.sram.sram6 1670 300 MX
soc_i.sram.sram7 1670 786.692 R0
soc_i.sram.sram8 1670 1253.384 MX
soc_i.sram.sram9 1670 1710.076 R0
soc_i.sram.sram10 1670 2196.768 MX
soc_i.sram.sram11 1670 2683.46 R0
78 changes: 74 additions & 4 deletions verilog/rtl/rtl/soc/modules/sram_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@

module sram_wrap #(
parameter SRAM_BASE_ADDR = 32'h8000_0000,
parameter SRAM_NUM_BLOCKS = 8,
parameter SRAM_NUM_BLOCKS = 12,
parameter SRAM_BLOCK_SIZE = 512,
parameter SRAM_LOG_BLOCK_SIZE = $clog2(SRAM_BLOCK_SIZE),
parameter SRAM_END_ADDR = (SRAM_BASE_ADDR + (SRAM_NUM_BLOCKS * SRAM_BLOCK_SIZE)),
Expand Down Expand Up @@ -87,8 +87,8 @@ module sram_wrap #(
for (int i = 0; i < SRAM_NUM_BLOCKS; i++ )
begin
// CS selection
if ( sram_d_req_i && i == {29'b0, sram_d_cs_addr}) cs_data[i] = 1;
if ( sram_i_req_i && i == {29'b0, sram_i_cs_addr}) cs_inst[i] = 1;
if ( sram_d_req_i && i == {28'b0, sram_d_cs_addr}) cs_data[i] = 1;
if ( sram_i_req_i && i == {28'b0, sram_i_cs_addr}) cs_inst[i] = 1;

if (cs_data_prev[i] == 1'b1) sram_d_rdata_o = sram_d_read_vec[i];
if (cs_inst_prev[i] == 1'b1) sram_i_rdata_o = sram_i_read_vec[i];
Expand Down Expand Up @@ -244,6 +244,77 @@ module sram_wrap #(
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[7])
);
sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram8 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[8]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[8]),
.clk1 (clk_i),
.csb1 (~cs_inst[8]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[8])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram9 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[9]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[9]),
.clk1 (clk_i),
.csb1 (~cs_inst[9]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[9])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram10 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[10]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[10]),
.clk1 (clk_i),
.csb1 (~cs_inst[10]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[10])
);

sky130_sram_2kbyte_1rw1r_32x512_8 #(.DELAY(0)) sram11 (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // 1.8V
.vssd1(vssd1), // Digital ground
`endif
.clk0 (clk_i),
.csb0 (~cs_data[11]), // Active Low
.web0 (~sram_d_we_i), // Active Low
.wmask0 (sram_d_be_i),
.addr0 (sram_d_addr_i[SRAM_LOG_BLOCK_SIZE+2 -1 : 2]),
.din0 (sram_d_wdata_i),
.dout0 (sram_d_read_vec[11]),
.clk1 (clk_i),
.csb1 (~cs_inst[11]), // Active Low
.addr1 (sram_i_addr_i[SRAM_LOG_BLOCK_SIZE+2-1 : 2]),
.dout1 (sram_i_read_vec[11])
);


`ifdef VERILATOR
Expand All @@ -263,4 +334,3 @@ module sram_wrap #(
`endif

endmodule

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