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cache.cc
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#include "cache.h"
//uint64_t l2pf_access = 0;
void CACHE::handle_fill()
{
// handle fill
uint32_t fill_cpu = (MSHR.next_fill_index == MSHR_SIZE) ? NUM_CPUS : MSHR.entry[MSHR.next_fill_index].cpu;
if (fill_cpu == NUM_CPUS)
return;
if (MSHR.next_fill_cycle <= current_core_cycle[fill_cpu]) {
#ifdef SANITY_CHECK
if (MSHR.next_fill_index >= MSHR.SIZE)
assert(0);
#endif
uint32_t mshr_index = MSHR.next_fill_index;
// find victim
uint32_t set = get_set(MSHR.entry[mshr_index].address), way;
if (cache_type == IS_LLC) {
way = llc_find_victim(fill_cpu, MSHR.entry[mshr_index].instr_id, set, block[set], MSHR.entry[mshr_index].ip, MSHR.entry[mshr_index].full_addr, MSHR.entry[mshr_index].type);
}
else
way = find_victim(fill_cpu, MSHR.entry[mshr_index].instr_id, set, block[set], MSHR.entry[mshr_index].ip, MSHR.entry[mshr_index].full_addr, MSHR.entry[mshr_index].type);
#ifdef LLC_BYPASS
if ((cache_type == IS_LLC) && (way == LLC_WAY)) { // this is a bypass that does not fill the LLC
// update replacement policy
if (cache_type == IS_LLC) {
llc_update_replacement_state(fill_cpu, set, way, MSHR.entry[mshr_index].full_addr, MSHR.entry[mshr_index].ip, 0, MSHR.entry[mshr_index].type, 0);
}
else
update_replacement_state(fill_cpu, set, way, MSHR.entry[mshr_index].full_addr, MSHR.entry[mshr_index].ip, 0, MSHR.entry[mshr_index].type, 0);
// COLLECT STATS
sim_miss[fill_cpu][MSHR.entry[mshr_index].type]++;
sim_access[fill_cpu][MSHR.entry[mshr_index].type]++;
// check fill level
if (MSHR.entry[mshr_index].fill_level < fill_level) {
if (MSHR.entry[mshr_index].instruction)
upper_level_icache[fill_cpu]->return_data(&MSHR.entry[mshr_index]);
else // data
upper_level_dcache[fill_cpu]->return_data(&MSHR.entry[mshr_index]);
}
MSHR.remove_queue(&MSHR.entry[mshr_index]);
MSHR.num_returned--;
update_fill_cycle();
return; // return here, no need to process further in this function
}
#endif
uint8_t do_fill = 1;
// is this dirty?
if (block[set][way].dirty) {
// check if the lower level WQ has enough room to keep this writeback request
if (lower_level) {
if (lower_level->get_occupancy(2, block[set][way].address) == lower_level->get_size(2, block[set][way].address)) {
// lower level WQ is full, cannot replace this victim
do_fill = 0;
lower_level->increment_WQ_FULL(block[set][way].address);
STALL[MSHR.entry[mshr_index].type]++;
DP ( if (warmup_complete[fill_cpu]) {
cout << "[" << NAME << "] " << __func__ << "do_fill: " << +do_fill;
cout << " lower level wq is full!" << " fill_addr: " << hex << MSHR.entry[mshr_index].address;
cout << " victim_addr: " << block[set][way].tag << dec << "\tfill_cpu = " << fill_cpu << endl; });
}
else {
PACKET writeback_packet;
writeback_packet.fill_level = fill_level << 1;
writeback_packet.cpu = fill_cpu;
writeback_packet.address = block[set][way].address;
writeback_packet.full_addr = block[set][way].full_addr;
writeback_packet.data = block[set][way].data;
writeback_packet.instr_id = MSHR.entry[mshr_index].instr_id;
writeback_packet.ip = 0; // writeback does not have ip
writeback_packet.type = WRITEBACK;
writeback_packet.event_cycle = current_core_cycle[fill_cpu];
lower_level->add_wq(&writeback_packet);
}
}
#ifdef SANITY_CHECK
else {
// sanity check
if (cache_type != IS_STLB)
assert(0);
}
#endif
}
if (do_fill) {
// update prefetcher
if (cache_type == IS_L1D)
l1d_prefetcher_cache_fill(MSHR.entry[mshr_index].full_addr, set, way, (MSHR.entry[mshr_index].type == PREFETCH) ? 1 : 0, block[set][way].full_addr);
else if (cache_type == IS_LLC)//Bingo
llc_prefetcher_cache_fill(fill_cpu, MSHR.entry[mshr_index].full_addr, set, way, (MSHR.entry[mshr_index].type == PREFETCH) ? 1 : 0, block[set][way].full_addr);//Bingo
// update replacement policy
if (cache_type == IS_LLC) {
llc_update_replacement_state(fill_cpu, set, way, MSHR.entry[mshr_index].full_addr, MSHR.entry[mshr_index].ip, block[set][way].full_addr, MSHR.entry[mshr_index].type, 0);
}
else
update_replacement_state(fill_cpu, set, way, MSHR.entry[mshr_index].full_addr, MSHR.entry[mshr_index].ip, block[set][way].full_addr, MSHR.entry[mshr_index].type, 0);
// COLLECT STATS
sim_miss[fill_cpu][MSHR.entry[mshr_index].type]++;
sim_access[fill_cpu][MSHR.entry[mshr_index].type]++;
fill_cache(set, way, &MSHR.entry[mshr_index]);
// RFO marks cache line dirty
if (cache_type == IS_L1D) {
if (MSHR.entry[mshr_index].type == RFO)
block[set][way].dirty = 1;
}
// check fill level
if (MSHR.entry[mshr_index].fill_level < fill_level) {
if (MSHR.entry[mshr_index].instruction)
upper_level_icache[fill_cpu]->return_data(&MSHR.entry[mshr_index]);
else // data
upper_level_dcache[fill_cpu]->return_data(&MSHR.entry[mshr_index]);
}
// update processed packets
if (cache_type == IS_ITLB) {
MSHR.entry[mshr_index].instruction_pa = block[set][way].data;
if (PROCESSED.occupancy < PROCESSED.SIZE)
PROCESSED.add_queue(&MSHR.entry[mshr_index]);
}
else if (cache_type == IS_DTLB) {
MSHR.entry[mshr_index].data_pa = block[set][way].data;
if (PROCESSED.occupancy < PROCESSED.SIZE)
PROCESSED.add_queue(&MSHR.entry[mshr_index]);
}
else if (cache_type == IS_L1I) {
if (PROCESSED.occupancy < PROCESSED.SIZE)
PROCESSED.add_queue(&MSHR.entry[mshr_index]);
}
//else if (cache_type == IS_L1D) {
else if ((cache_type == IS_L1D) && (MSHR.entry[mshr_index].type != PREFETCH)) {
if (PROCESSED.occupancy < PROCESSED.SIZE)
PROCESSED.add_queue(&MSHR.entry[mshr_index]);
}
MSHR.remove_queue(&MSHR.entry[mshr_index]);
MSHR.num_returned--;
update_fill_cycle();
}
}
}
void CACHE::handle_writeback()
{
// handle write
uint32_t writeback_cpu = WQ.entry[WQ.head].cpu;
if (writeback_cpu == NUM_CPUS)
return;
// handle the oldest entry
if ((WQ.entry[WQ.head].event_cycle <= current_core_cycle[writeback_cpu]) && (WQ.occupancy > 0)) {
int index = WQ.head;
// access cache
uint32_t set = get_set(WQ.entry[index].address);
int way = check_hit(&WQ.entry[index]);
if (way >= 0) { // writeback hit (or RFO hit for L1D)
if (cache_type == IS_LLC) {
llc_update_replacement_state(writeback_cpu, set, way, block[set][way].full_addr, WQ.entry[index].ip, 0, WQ.entry[index].type, 1);
}
else
update_replacement_state(writeback_cpu, set, way, block[set][way].full_addr, WQ.entry[index].ip, 0, WQ.entry[index].type, 1);
// COLLECT STATS
sim_hit[writeback_cpu][WQ.entry[index].type]++;
sim_access[writeback_cpu][WQ.entry[index].type]++;
// mark dirty
block[set][way].dirty = 1;
if (cache_type == IS_ITLB)
WQ.entry[index].instruction_pa = block[set][way].data;
else if (cache_type == IS_DTLB)
WQ.entry[index].data_pa = block[set][way].data;
else if (cache_type == IS_STLB)
WQ.entry[index].data = block[set][way].data;
// check fill level
if (WQ.entry[index].fill_level < fill_level) {
if (WQ.entry[index].instruction)
upper_level_icache[writeback_cpu]->return_data(&WQ.entry[index]);
else // data
upper_level_dcache[writeback_cpu]->return_data(&WQ.entry[index]);
}
HIT[WQ.entry[index].type]++;
ACCESS[WQ.entry[index].type]++;
// remove this entry from WQ
WQ.remove_queue(&WQ.entry[index]);
}
else { // writeback miss (or RFO miss for L1D)
DP ( if (warmup_complete[writeback_cpu]) {
cout << "[" << NAME << "] " << __func__ << " type: " << +WQ.entry[index].type << " miss";
cout << " instr_id: " << WQ.entry[index].instr_id << " address: " << hex << WQ.entry[index].address;
cout << " full_addr: " << WQ.entry[index].full_addr << dec;
cout << " cycle: " << WQ.entry[index].event_cycle << "\twriteback_cpu = " << writeback_cpu << endl; });
if (cache_type == IS_L1D) { // RFO miss
// check mshr
uint8_t miss_handled = 1;
int mshr_index = check_mshr(&WQ.entry[index]);
if ((mshr_index == -1) && (MSHR.occupancy < MSHR_SIZE)) { // this is a new miss
// add it to mshr (RFO miss)
add_mshr(&WQ.entry[index]);
// add it to the next level's read queue
//if (lower_level) // L1D always has a lower level cache
lower_level->add_rq(&WQ.entry[index]);
}
else {
if ((mshr_index == -1) && (MSHR.occupancy == MSHR_SIZE)) { // not enough MSHR resource
// cannot handle miss request until one of MSHRs is available
miss_handled = 0;
STALL[WQ.entry[index].type]++;
}
else if (mshr_index != -1) { // already in-flight miss
// update fill_level
if (WQ.entry[index].fill_level < MSHR.entry[mshr_index].fill_level)
MSHR.entry[mshr_index].fill_level = WQ.entry[index].fill_level;
// update request
if (MSHR.entry[mshr_index].type == PREFETCH) {
uint8_t prior_returned = MSHR.entry[mshr_index].returned;
uint64_t prior_event_cycle = MSHR.entry[mshr_index].event_cycle;
memcpy(&MSHR.entry[mshr_index], &WQ.entry[index], sizeof(PACKET));
// in case request is already returned, we should keep event_cycle and retunred variables
MSHR.entry[mshr_index].returned = prior_returned;
MSHR.entry[mshr_index].event_cycle = prior_event_cycle;
}
MSHR_MERGED[WQ.entry[index].type]++;
DP ( if (warmup_complete[writeback_cpu]) {
cout << "[" << NAME << "] " << __func__ << " mshr merged";
cout << " instr_id: " << WQ.entry[index].instr_id << " prior_id: " << MSHR.entry[mshr_index].instr_id;
cout << " address: " << hex << WQ.entry[index].address;
cout << " full_addr: " << WQ.entry[index].full_addr << dec;
cout << " cycle: " << WQ.entry[index].event_cycle << "\twriteback_cpu = " << writeback_cpu << endl; });
}
else { // WE SHOULD NOT REACH HERE
cerr << "[" << NAME << "] MSHR errors" << endl;
assert(0);
}
}
if (miss_handled) {
MISS[WQ.entry[index].type]++;
ACCESS[WQ.entry[index].type]++;
// remove this entry from WQ
WQ.remove_queue(&WQ.entry[index]);
}
}
else {
// find victim
uint32_t set = get_set(WQ.entry[index].address), way;
if (cache_type == IS_LLC) {
way = llc_find_victim(writeback_cpu, WQ.entry[index].instr_id, set, block[set], WQ.entry[index].ip, WQ.entry[index].full_addr, WQ.entry[index].type);
}
else
way = find_victim(writeback_cpu, WQ.entry[index].instr_id, set, block[set], WQ.entry[index].ip, WQ.entry[index].full_addr, WQ.entry[index].type);
#ifdef LLC_BYPASS
if ((cache_type == IS_LLC) && (way == LLC_WAY)) {
cerr << "LLC bypassing for writebacks is not allowed!" << endl;
assert(0);
}
#endif
uint8_t do_fill = 1;
// is this dirty?
if (block[set][way].dirty) {
// check if the lower level WQ has enough room to keep this writeback request
if (lower_level) {
if (lower_level->get_occupancy(2, block[set][way].address) == lower_level->get_size(2, block[set][way].address)) {
// lower level WQ is full, cannot replace this victim
do_fill = 0;
lower_level->increment_WQ_FULL(block[set][way].address);
STALL[WQ.entry[index].type]++;
DP ( if (warmup_complete[writeback_cpu]) {
cout << "[" << NAME << "] " << __func__ << "do_fill: " << +do_fill;
cout << " lower level wq is full!" << " fill_addr: " << hex << WQ.entry[index].address;
cout << " victim_addr: " << block[set][way].tag << dec << "\twriteback_cpu = " << writeback_cpu << endl; });
}
else {
PACKET writeback_packet;
writeback_packet.fill_level = fill_level << 1;
writeback_packet.cpu = writeback_cpu;
writeback_packet.address = block[set][way].address;
writeback_packet.full_addr = block[set][way].full_addr;
writeback_packet.data = block[set][way].data;
writeback_packet.instr_id = WQ.entry[index].instr_id;
writeback_packet.ip = 0;
writeback_packet.type = WRITEBACK;
writeback_packet.event_cycle = current_core_cycle[writeback_cpu];
lower_level->add_wq(&writeback_packet);
}
}
#ifdef SANITY_CHECK
else {
// sanity check
if (cache_type != IS_STLB)
assert(0);
}
#endif
}
if (do_fill) {
// update prefetcher
if (cache_type == IS_L1D)
l1d_prefetcher_cache_fill(WQ.entry[index].full_addr, set, way, 0, block[set][way].full_addr);
else if (cache_type == IS_LLC)//Bingo
llc_prefetcher_cache_fill(writeback_cpu, WQ.entry[index].full_addr, set, way, 0, block[set][way].full_addr);//Bingo
// update replacement policy
if (cache_type == IS_LLC) {
llc_update_replacement_state(writeback_cpu, set, way, WQ.entry[index].full_addr, WQ.entry[index].ip, block[set][way].full_addr, WQ.entry[index].type, 0);
}
else
update_replacement_state(writeback_cpu, set, way, WQ.entry[index].full_addr, WQ.entry[index].ip, block[set][way].full_addr, WQ.entry[index].type, 0);
// COLLECT STATS
sim_miss[writeback_cpu][WQ.entry[index].type]++;
sim_access[writeback_cpu][WQ.entry[index].type]++;
fill_cache(set, way, &WQ.entry[index]);
// mark dirty
block[set][way].dirty = 1;
// check fill level
if (WQ.entry[index].fill_level < fill_level) {
if (WQ.entry[index].instruction)
upper_level_icache[writeback_cpu]->return_data(&WQ.entry[index]);
else // data
upper_level_dcache[writeback_cpu]->return_data(&WQ.entry[index]);
}
MISS[WQ.entry[index].type]++;
ACCESS[WQ.entry[index].type]++;
// remove this entry from WQ
WQ.remove_queue(&WQ.entry[index]);
}
}
}
}
}
void CACHE::handle_read()
{
// handle read
uint32_t read_cpu = RQ.entry[RQ.head].cpu;
if (read_cpu == NUM_CPUS)
return;
for (uint32_t i=0; i<MAX_READ; i++) {
// handle the oldest entry
if ((RQ.entry[RQ.head].event_cycle <= current_core_cycle[read_cpu]) && (RQ.occupancy > 0)) {
int index = RQ.head;
// access cache
uint32_t set = get_set(RQ.entry[index].address);
int way = check_hit(&RQ.entry[index]);
if (way >= 0) { // read hit
if (cache_type == IS_ITLB) {
RQ.entry[index].instruction_pa = block[set][way].data;
if (PROCESSED.occupancy < PROCESSED.SIZE)
PROCESSED.add_queue(&RQ.entry[index]);
}
else if (cache_type == IS_DTLB) {
RQ.entry[index].data_pa = block[set][way].data;
if (PROCESSED.occupancy < PROCESSED.SIZE)
PROCESSED.add_queue(&RQ.entry[index]);
}
else if (cache_type == IS_STLB)
RQ.entry[index].data = block[set][way].data;
else if (cache_type == IS_L1I) {
if (PROCESSED.occupancy < PROCESSED.SIZE)
PROCESSED.add_queue(&RQ.entry[index]);
}
//else if (cache_type == IS_L1D) {
else if ((cache_type == IS_L1D) && (RQ.entry[index].type != PREFETCH)) {
if (PROCESSED.occupancy < PROCESSED.SIZE)
PROCESSED.add_queue(&RQ.entry[index]);
}
// update prefetcher on load instruction
if (RQ.entry[index].type == LOAD) {
if (cache_type == IS_L1D)
l1d_prefetcher_operate(block[set][way].full_addr, RQ.entry[index].ip, 1, RQ.entry[index].type);
else if (cache_type == IS_LLC)//Bingo
llc_prefetcher_operate(read_cpu, block[set][way].full_addr, RQ.entry[index].ip, 1, RQ.entry[index].type);//Bingo
}
// update replacement policy
if (cache_type == IS_LLC) {
llc_update_replacement_state(read_cpu, set, way, block[set][way].full_addr, RQ.entry[index].ip, 0, RQ.entry[index].type, 1);
}
else
update_replacement_state(read_cpu, set, way, block[set][way].full_addr, RQ.entry[index].ip, 0, RQ.entry[index].type, 1);
// COLLECT STATS
sim_hit[read_cpu][RQ.entry[index].type]++;
sim_access[read_cpu][RQ.entry[index].type]++;
// check fill level
if (RQ.entry[index].fill_level < fill_level) {
if (RQ.entry[index].instruction)
upper_level_icache[read_cpu]->return_data(&RQ.entry[index]);
else // data
upper_level_dcache[read_cpu]->return_data(&RQ.entry[index]);
}
// update prefetch stats and reset prefetch bit
if (block[set][way].prefetch) {
pf_useful++;
block[set][way].prefetch = 0;
}
block[set][way].used = 1;
//icp
if (block[set][way].prefState == PREFETCHED_UNUSED) {
block[set][way].prefState = PREFETCHED_USED;
used_prefetches ++;
} else if (block[set][way].prefState == PREFETCHED_USED) {
block[set][way].prefState = PREFETCHED_REUSED;
reused_prefetches ++;
} else if (block[set][way].prefState == PREFETCHED_REUSED) {
reused_prefetches ++;
}
HIT[RQ.entry[index].type]++;
ACCESS[RQ.entry[index].type]++;
// remove this entry from RQ
RQ.remove_queue(&RQ.entry[index]);
}
else { // read miss
DP ( if (warmup_complete[read_cpu]) {
cout << "[" << NAME << "] " << __func__ << " read miss";
cout << " instr_id: " << RQ.entry[index].instr_id << " address: " << hex << RQ.entry[index].address;
cout << " full_addr: " << RQ.entry[index].full_addr << dec;
cout << " cycle: " << RQ.entry[index].event_cycle << "\tread_cpu = " << read_cpu << endl; });
// check mshr
uint8_t miss_handled = 1;
int mshr_index = check_mshr(&RQ.entry[index]);
if ((mshr_index == -1) && (MSHR.occupancy < MSHR_SIZE)) { // this is a new miss
// add it to mshr (read miss)
add_mshr(&RQ.entry[index]);
// add it to the next level's read queue
if (lower_level)
lower_level->add_rq(&RQ.entry[index]);
else { // this is the last level
if (cache_type == IS_STLB) {
// TODO: need to differentiate page table walk and actual swap
// emulate page table walk
uint64_t pa = va_to_pa(read_cpu, RQ.entry[index].instr_id, RQ.entry[index].full_addr, RQ.entry[index].address);
RQ.entry[index].data = pa >> LOG2_PAGE_SIZE;
RQ.entry[index].event_cycle = current_core_cycle[read_cpu];
return_data(&RQ.entry[index]);
}
}
}
else {
if ((mshr_index == -1) && (MSHR.occupancy == MSHR_SIZE)) { // not enough MSHR resource
// cannot handle miss request until one of MSHRs is available
miss_handled = 0;
STALL[RQ.entry[index].type]++;
}
else if (mshr_index != -1) { // already in-flight miss
// mark merged consumer
if (RQ.entry[index].type == RFO) {
if (RQ.entry[index].tlb_access) {
uint32_t sq_index = RQ.entry[index].sq_index;
MSHR.entry[mshr_index].store_merged = 1;
MSHR.entry[mshr_index].sq_index_depend_on_me[sq_index] = 1;
for (uint32_t i=0; i<SQ_SIZE; i++) {
if (RQ.entry[index].sq_index_depend_on_me[i])
MSHR.entry[mshr_index].sq_index_depend_on_me[i] = 1;
else
continue;
}
}
if (RQ.entry[index].load_merged) {
//uint32_t lq_index = RQ.entry[index].lq_index;
MSHR.entry[mshr_index].load_merged = 1;
//MSHR.entry[mshr_index].lq_index_depend_on_me[lq_index] = 1;
for (uint32_t i=0; i<LQ_SIZE; i++) {
if (RQ.entry[index].lq_index_depend_on_me[i])
MSHR.entry[mshr_index].lq_index_depend_on_me[i] = 1;
}
}
}
else {
if (RQ.entry[index].instruction) {
uint32_t rob_index = RQ.entry[index].rob_index;
MSHR.entry[mshr_index].instr_merged = 1;
MSHR.entry[mshr_index].rob_index_depend_on_me[rob_index] = 1;
DP (if (warmup_complete[MSHR.entry[mshr_index].cpu]) {
cout << "[INSTR_MERGED] " << __func__ << " cpu: " << MSHR.entry[mshr_index].cpu << " instr_id: " << MSHR.entry[mshr_index].instr_id;
cout << " merged rob_index: " << rob_index << " instr_id: " << RQ.entry[index].instr_id << "\tMSHR.entry[mshr_index].cpu = " << MSHR.entry[mshr_index].cpu << endl; });
if (RQ.entry[index].instr_merged) {
for (uint32_t i=0; i<ROB_SIZE; i++) {
if (RQ.entry[index].rob_index_depend_on_me[i]) {
MSHR.entry[mshr_index].rob_index_depend_on_me[i] = 1;
DP (if (warmup_complete[MSHR.entry[mshr_index].cpu]) {
cout << "[INSTR_MERGED] " << __func__ << " cpu: " << MSHR.entry[mshr_index].cpu << " instr_id: " << MSHR.entry[mshr_index].instr_id;
cout << " merged rob_index: " << i << " instr_id: N/A" << "\tMSHR.entry[mshr_index].cpu = " << MSHR.entry[mshr_index].cpu << endl; });
}
}
}
}
else
{
uint32_t lq_index = RQ.entry[index].lq_index;
MSHR.entry[mshr_index].load_merged = 1;
MSHR.entry[mshr_index].lq_index_depend_on_me[lq_index] = 1;
DP (if (warmup_complete[read_cpu]) {
cout << "[DATA_MERGED] " << __func__ << " cpu: " << read_cpu << " instr_id: " << RQ.entry[index].instr_id;
cout << " merged rob_index: " << RQ.entry[index].rob_index << " instr_id: " << RQ.entry[index].instr_id << " lq_index: " << RQ.entry[index].lq_index << "\tread_cpu = " << read_cpu << endl; });
for (uint32_t i=0; i<LQ_SIZE; i++) {
if (RQ.entry[index].lq_index_depend_on_me[i])
MSHR.entry[mshr_index].lq_index_depend_on_me[i] = 1;
}
if (RQ.entry[index].store_merged) {
//uint32_t sq_index = RQ.entry[index].sq_index;
MSHR.entry[mshr_index].store_merged = 1;
//MSHR.entry[mshr_index].sq_index_depend_on_me[sq_index] = 1;
for (uint32_t i=0; i<SQ_SIZE; i++) {
if (RQ.entry[index].sq_index_depend_on_me[i])
MSHR.entry[mshr_index].sq_index_depend_on_me[i] = 1;
else
continue;
}
}
}
}
// update fill_level
if (RQ.entry[index].fill_level < MSHR.entry[mshr_index].fill_level)
MSHR.entry[mshr_index].fill_level = RQ.entry[index].fill_level;
// update request
if (MSHR.entry[mshr_index].type == PREFETCH) {
uint8_t prior_returned = MSHR.entry[mshr_index].returned;
uint64_t prior_event_cycle = MSHR.entry[mshr_index].event_cycle;
memcpy(&MSHR.entry[mshr_index], &RQ.entry[index], sizeof(PACKET));
// in case request is already returned, we should keep event_cycle and retunred variables
MSHR.entry[mshr_index].returned = prior_returned;
MSHR.entry[mshr_index].event_cycle = prior_event_cycle;
}
MSHR_MERGED[RQ.entry[index].type]++;
DP ( if (warmup_complete[read_cpu]) {
cout << "[" << NAME << "] " << __func__ << " mshr merged";
cout << " instr_id: " << RQ.entry[index].instr_id << " prior_id: " << MSHR.entry[mshr_index].instr_id;
cout << " address: " << hex << RQ.entry[index].address;
cout << " full_addr: " << RQ.entry[index].full_addr << dec;
cout << " cycle: " << RQ.entry[index].event_cycle << "\tread_cpu = " << read_cpu << endl; });
}
else { // WE SHOULD NOT REACH HERE
cerr << "[" << NAME << "] MSHR errors" << endl;
assert(0);
}
}
if (miss_handled) {
// update prefetcher on load instruction
if (RQ.entry[index].type == LOAD) {
if (cache_type == IS_L1D)
l1d_prefetcher_operate(RQ.entry[index].full_addr, RQ.entry[index].ip, 0, RQ.entry[index].type);
else if (cache_type == IS_LLC)//Bingo
llc_prefetcher_operate(read_cpu, RQ.entry[index].full_addr, RQ.entry[index].ip, 0, RQ.entry[index].type);//Bingo
}
MISS[RQ.entry[index].type]++;
ACCESS[RQ.entry[index].type]++;
// remove this entry from RQ
RQ.remove_queue(&RQ.entry[index]);
}
}
}
}
}
void CACHE::handle_prefetch()
{
// handle prefetch
uint32_t prefetch_cpu = PQ.entry[PQ.head].cpu;
if (prefetch_cpu == NUM_CPUS)
return;
for (uint32_t i=0; i<MAX_READ; i++) {
// handle the oldest entry
if ((PQ.entry[PQ.head].event_cycle <= current_core_cycle[prefetch_cpu]) && (PQ.occupancy > 0)) {
int index = PQ.head;
// access cache
uint32_t set = get_set(PQ.entry[index].address);
int way = check_hit(&PQ.entry[index]);
if (way >= 0) { // prefetch hit
// update replacement policy
if (cache_type == IS_LLC) {
llc_update_replacement_state(prefetch_cpu, set, way, block[set][way].full_addr, PQ.entry[index].ip, 0, PQ.entry[index].type, 1);
}
else
update_replacement_state(prefetch_cpu, set, way, block[set][way].full_addr, PQ.entry[index].ip, 0, PQ.entry[index].type, 1);
// COLLECT STATS
sim_hit[prefetch_cpu][PQ.entry[index].type]++;
sim_access[prefetch_cpu][PQ.entry[index].type]++;
// check fill level
if (PQ.entry[index].fill_level < fill_level) {
if (PQ.entry[index].instruction)
upper_level_icache[prefetch_cpu]->return_data(&PQ.entry[index]);
else // data
upper_level_dcache[prefetch_cpu]->return_data(&PQ.entry[index]);
}
HIT[PQ.entry[index].type]++;
ACCESS[PQ.entry[index].type]++;
// remove this entry from PQ
PQ.remove_queue(&PQ.entry[index]);
}
else { // prefetch miss
DP ( if (warmup_complete[prefetch_cpu]) {
cout << "[" << NAME << "] " << __func__ << " prefetch miss";
cout << " instr_id: " << PQ.entry[index].instr_id << " address: " << hex << PQ.entry[index].address;
cout << " full_addr: " << PQ.entry[index].full_addr << dec << " fill_level: " << PQ.entry[index].fill_level;
cout << " cycle: " << PQ.entry[index].event_cycle << "\tprefetch_cpu = " << prefetch_cpu << endl; });
// check mshr
uint8_t miss_handled = 1;
int mshr_index = check_mshr(&PQ.entry[index]);
if ((mshr_index == -1) && (MSHR.occupancy < MSHR_SIZE)) { // this is a new miss
DP ( if (warmup_complete[PQ.entry[index].cpu]) {
cout << "[" << NAME << "_PQ] " << __func__ << " want to add instr_id: " << PQ.entry[index].instr_id << " address: " << hex << PQ.entry[index].address;
cout << " full_addr: " << PQ.entry[index].full_addr << dec;
cout << " occupancy: " << lower_level->get_occupancy(3, PQ.entry[index].address) << " SIZE: " << lower_level->get_size(3, PQ.entry[index].address) << "\tPQ.entry[index].cpu = " << PQ.entry[index].cpu << endl; });
// first check if the lower level PQ is full or not
// this is possible since multiple prefetchers can exist at each level of caches
if (lower_level) {
if (cache_type == IS_LLC) {
if (lower_level->get_occupancy(1, PQ.entry[index].address) == lower_level->get_size(1, PQ.entry[index].address))
miss_handled = 0;
else {
// add it to MSHRs if this prefetch miss will be filled to this cache level
if (PQ.entry[index].fill_level <= fill_level)
add_mshr(&PQ.entry[index]);
lower_level->add_rq(&PQ.entry[index]); // add it to the DRAM RQ
}
}
else {
if (lower_level->get_occupancy(3, PQ.entry[index].address) == lower_level->get_size(3, PQ.entry[index].address))
miss_handled = 0;
else {
// add it to MSHRs if this prefetch miss will be filled to this cache level
if (PQ.entry[index].fill_level <= fill_level)
add_mshr(&PQ.entry[index]);
lower_level->add_pq(&PQ.entry[index]); // add it to the DRAM RQ. [Bingo: The comment is wrong!!!]
}
}
}
}
else {
if ((mshr_index == -1) && (MSHR.occupancy == MSHR_SIZE)) { // not enough MSHR resource
// TODO: should we allow prefetching with lower fill level at this case?
// cannot handle miss request until one of MSHRs is available
miss_handled = 0;
STALL[PQ.entry[index].type]++;
}
else if (mshr_index != -1) { // already in-flight miss
// no need to update request except fill_level
// update fill_level
if (PQ.entry[index].fill_level < MSHR.entry[mshr_index].fill_level)
MSHR.entry[mshr_index].fill_level = PQ.entry[index].fill_level;
MSHR_MERGED[PQ.entry[index].type]++;
DP ( if (warmup_complete[prefetch_cpu]) {
cout << "[" << NAME << "] " << __func__ << " mshr merged";
cout << " instr_id: " << PQ.entry[index].instr_id << " prior_id: " << MSHR.entry[mshr_index].instr_id;
cout << " address: " << hex << PQ.entry[index].address;
cout << " full_addr: " << PQ.entry[index].full_addr << dec << " fill_level: " << MSHR.entry[mshr_index].fill_level;
cout << " cycle: " << MSHR.entry[mshr_index].event_cycle << "\tprefetch_cpu = " << prefetch_cpu << endl; });
}
else { // WE SHOULD NOT REACH HERE
cerr << "[" << NAME << "] MSHR errors" << endl;
assert(0);
}
}
if (miss_handled) {
DP ( if (warmup_complete[prefetch_cpu]) {
cout << "[" << NAME << "] " << __func__ << " prefetch miss handled";
cout << " instr_id: " << PQ.entry[index].instr_id << " address: " << hex << PQ.entry[index].address;
cout << " full_addr: " << PQ.entry[index].full_addr << dec << " fill_level: " << PQ.entry[index].fill_level;
cout << " cycle: " << PQ.entry[index].event_cycle << "\tprefetch_cpu = " << prefetch_cpu << endl; });
MISS[PQ.entry[index].type]++;
ACCESS[PQ.entry[index].type]++;
// remove this entry from PQ
PQ.remove_queue(&PQ.entry[index]);
}
}
}
}
}
void CACHE::operate()
{
handle_fill();
handle_writeback();
handle_read();
if (PQ.occupancy && (RQ.occupancy == 0))
handle_prefetch();
}
uint32_t CACHE::get_set(uint64_t address)
{
return (uint32_t) (address & ((1 << lg2(NUM_SET)) - 1));
}
uint32_t CACHE::get_way(uint64_t address, uint32_t set)
{
for (uint32_t way=0; way<NUM_WAY; way++) {
if (block[set][way].valid && (block[set][way].tag == address))
return way;
}
return NUM_WAY;
}
void CACHE::fill_cache(uint32_t set, uint32_t way, PACKET *packet)
{
#ifdef SANITY_CHECK
if (cache_type == IS_ITLB) {
if (packet->data == 0)
assert(0);
}
if (cache_type == IS_DTLB) {
if (packet->data == 0)
assert(0);
}
if (cache_type == IS_STLB) {
if (packet->data == 0)
assert(0);
}
#endif
if (block[set][way].prefetch && (block[set][way].used == 0))
pf_useless++;
//icp
if (block[set][way].prefState == PREFETCHED_UNUSED)
unused_prefetches ++;
if (block[set][way].prefState == PREFETCHED_USED)
unreused_prefetches ++;
if (block[set][way].valid == 0)
block[set][way].valid = 1;
block[set][way].dirty = 0;
block[set][way].prefetch = (packet->type == PREFETCH) ? 1 : 0;
block[set][way].used = 0;
//icp
if (block[set][way].prefetch) {
block[set][way].prefState = PREFETCHED_UNUSED;
}else {
block[set][way].prefState = NOT_PREFETCHED;
}
if (block[set][way].prefetch)
pf_fill++;
block[set][way].delta = packet->delta;
block[set][way].depth = packet->depth;
block[set][way].signature = packet->signature;
block[set][way].confidence = packet->confidence;
block[set][way].tag = packet->address;
block[set][way].address = packet->address;
block[set][way].full_addr = packet->full_addr;
block[set][way].data = packet->data;
block[set][way].cpu = packet->cpu;
block[set][way].instr_id = packet->instr_id;
DP ( if (warmup_complete[packet->cpu]) {
cout << "[" << NAME << "] " << __func__ << " set: " << set << " way: " << way;
cout << " lru: " << block[set][way].lru << " tag: " << hex << block[set][way].tag << " full_addr: " << block[set][way].full_addr;
cout << " data: " << block[set][way].data << dec << "\tpacket->cpu = " << packet->cpu << endl; });
}
int CACHE::check_hit(PACKET *packet)
{
uint32_t set = get_set(packet->address);
int match_way = -1;
if (NUM_SET < set) {
cerr << "[" << NAME << "_ERROR] " << __func__ << " invalid set index: " << set << " NUM_SET: " << NUM_SET;
cerr << " address: " << hex << packet->address << " full_addr: " << packet->full_addr << dec;
cerr << " event: " << packet->event_cycle << endl;
assert(0);
}
// hit
for (uint32_t way=0; way<NUM_WAY; way++) {
if (block[set][way].valid && (block[set][way].tag == packet->address)) {
match_way = way;
DP ( if (warmup_complete[packet->cpu]) {
cout << "[" << NAME << "] " << __func__ << " instr_id: " << packet->instr_id << " type: " << +packet->type << hex << " addr: " << packet->address;
cout << " full_addr: " << packet->full_addr << " tag: " << block[set][way].tag << " data: " << block[set][way].data << dec;
cout << " set: " << set << " way: " << way << " lru: " << block[set][way].lru;
cout << " event: " << packet->event_cycle << " cycle: " << current_core_cycle[cpu] << "\tpacket->cpu = " << packet->cpu << endl; });
break;
}
}
return match_way;
}
int CACHE::invalidate_entry(uint64_t inval_addr)
{
uint32_t set = get_set(inval_addr);
int match_way = -1;
if (NUM_SET < set) {
cerr << "[" << NAME << "_ERROR] " << __func__ << " invalid set index: " << set << " NUM_SET: " << NUM_SET;
cerr << " inval_addr: " << hex << inval_addr << dec << endl;
assert(0);
}
// invalidate
for (uint32_t way=0; way<NUM_WAY; way++) {
if (block[set][way].valid && (block[set][way].tag == inval_addr)) {
block[set][way].valid = 0;
match_way = way;
DP ( if (warmup_complete[cpu]) {
cout << "[" << NAME << "] " << __func__ << " inval_addr: " << hex << inval_addr;
cout << " tag: " << block[set][way].tag << " data: " << block[set][way].data << dec;
cout << " set: " << set << " way: " << way << " lru: " << block[set][way].lru << " cycle: " << current_core_cycle[cpu] << "\tcpu = " << cpu << endl; });
break;
}
}
return match_way;
}
int CACHE::add_rq(PACKET *packet)
{
// check for the latest wirtebacks in the write queue
int wq_index = WQ.check_queue(packet);
if (wq_index != -1) {
// check fill level
if (packet->fill_level < fill_level) {
packet->data = WQ.entry[wq_index].data;
if (packet->instruction)
upper_level_icache[packet->cpu]->return_data(packet);
else // data
upper_level_dcache[packet->cpu]->return_data(packet);
}
#ifdef SANITY_CHECK
if (cache_type == IS_ITLB)
assert(0);
else if (cache_type == IS_DTLB)
assert(0);
else if (cache_type == IS_L1I)
assert(0);
#endif
// update processed packets
if ((cache_type == IS_L1D) && (packet->type != PREFETCH)) {
if (PROCESSED.occupancy < PROCESSED.SIZE)
PROCESSED.add_queue(packet);
DP ( if (warmup_complete[packet->cpu]) {
cout << "[" << NAME << "_RQ] " << __func__ << " instr_id: " << packet->instr_id << " found recent writebacks";
cout << hex << " read: " << packet->address << " writeback: " << WQ.entry[wq_index].address << dec;
cout << " index: " << MAX_READ << " rob_signal: " << packet->rob_signal << "\tpacket->cpu = " << packet->cpu << endl; });
}
HIT[packet->type]++;
ACCESS[packet->type]++;
WQ.FORWARD++;
RQ.ACCESS++;
return -1;
}
// check for duplicates in the read queue
int index = RQ.check_queue(packet);
if (index != -1) {
if (packet->instruction) {
uint32_t rob_index = packet->rob_index;
RQ.entry[index].rob_index_depend_on_me[rob_index] = 1;
RQ.entry[index].instr_merged = 1;