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ooo_cpu.cc
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#include "ooo_cpu.h"
// out-of-order core
O3_CPU ooo_cpu[NUM_CPUS];
uint64_t current_core_cycle[NUM_CPUS], stall_cycle[NUM_CPUS];
uint32_t SCHEDULING_LATENCY = 0, EXEC_LATENCY = 0;
void O3_CPU::initialize_core()
{
}
void O3_CPU::handle_branch()
{
// actual processors do not work like this but for easier implementation,
// we read instruction traces and virtually add them in the ROB
// note that these traces are not yet translated and fetched
uint8_t continue_reading = 1;
uint32_t num_reads = 0;
instrs_to_read_this_cycle = FETCH_WIDTH;
// first, read PIN trace
while (continue_reading) {
size_t instr_size = knob_cloudsuite ? sizeof(cloudsuite_instr) : sizeof(input_instr);
if (knob_cloudsuite) {
if (!fread(¤t_cloudsuite_instr, instr_size, 1, trace_file)) {
// reached end of file for this trace
cout << "*** Reached end of trace for Core: " << cpu << " Repeating trace: " << trace_string << endl;
// close the trace file and re-open it
pclose(trace_file);
trace_file = popen(gunzip_command, "r");
if (trace_file == NULL) {
cerr << endl << "*** CANNOT REOPEN TRACE FILE: " << trace_string << " ***" << endl;
assert(0);
}
} else { // successfully read the trace
// copy the instruction into the performance model's instruction format
ooo_model_instr arch_instr;
int num_reg_ops = 0, num_mem_ops = 0;
arch_instr.instr_id = instr_unique_id;
arch_instr.ip = current_cloudsuite_instr.ip;
arch_instr.is_branch = current_cloudsuite_instr.is_branch;
arch_instr.branch_taken = current_cloudsuite_instr.branch_taken;
arch_instr.asid[0] = current_cloudsuite_instr.asid[0];
arch_instr.asid[1] = current_cloudsuite_instr.asid[1];
for (uint32_t i=0; i<MAX_INSTR_DESTINATIONS; i++) {
arch_instr.destination_registers[i] = current_cloudsuite_instr.destination_registers[i];
arch_instr.destination_memory[i] = current_cloudsuite_instr.destination_memory[i];
arch_instr.destination_virtual_address[i] = current_cloudsuite_instr.destination_memory[i];
if (arch_instr.destination_registers[i])
num_reg_ops++;
if (arch_instr.destination_memory[i]) {
num_mem_ops++;
// update STA, this structure is required to execute store instructios properly without deadlock
if (num_mem_ops > 0) {
#ifdef SANITY_CHECK
if (STA[STA_tail] < UINT64_MAX) {
if (STA_head != STA_tail)
assert(0);
}
#endif
STA[STA_tail] = instr_unique_id;
STA_tail++;
if (STA_tail == STA_SIZE)
STA_tail = 0;
}
}
}
for (int i=0; i<NUM_INSTR_SOURCES; i++) {
arch_instr.source_registers[i] = current_cloudsuite_instr.source_registers[i];
arch_instr.source_memory[i] = current_cloudsuite_instr.source_memory[i];
arch_instr.source_virtual_address[i] = current_cloudsuite_instr.source_memory[i];
if (arch_instr.source_registers[i])
num_reg_ops++;
if (arch_instr.source_memory[i])
num_mem_ops++;
}
arch_instr.num_reg_ops = num_reg_ops;
arch_instr.num_mem_ops = num_mem_ops;
if (num_mem_ops > 0)
arch_instr.is_memory = 1;
// virtually add this instruction to the ROB
if (ROB.occupancy < ROB.SIZE) {
uint32_t rob_index = add_to_rob(&arch_instr);
num_reads++;
// branch prediction
if (arch_instr.is_branch) {
DP( if (warmup_complete[cpu]) {
cout << "[BRANCH] instr_id: " << instr_unique_id << " ip: " << hex << arch_instr.ip << dec << " taken: " << +arch_instr.branch_taken << "\tcpu = " << cpu << endl; });
num_branch++;
/*
uint8_t branch_prediction;
// for faster simulation, force perfect prediction during the warmup
// note that branch predictor is still learning with real branch results
if (all_warmup_complete == 0)
branch_prediction = arch_instr.branch_taken;
else
branch_prediction = predict_branch(arch_instr.ip);
*/
uint8_t branch_prediction = predict_branch(arch_instr.ip);
if (arch_instr.branch_taken != branch_prediction) {
branch_mispredictions++;
DP( if (warmup_complete[cpu]) {
cout << "[BRANCH] MISPREDICTED instr_id: " << instr_unique_id << " ip: " << hex << arch_instr.ip << dec;
cout << " taken: " << +arch_instr.branch_taken << " predicted: " << +branch_prediction << "\tcpu = " << cpu << endl; });
// halt any further fetch this cycle
instrs_to_read_this_cycle = 0;
// and stall any additional fetches until the branch is executed
fetch_stall = 1;
ROB.entry[rob_index].branch_mispredicted = 1;
}
else {
if (branch_prediction == 1) {
// if we are accurately predicting a branch to be taken, then we can't possibly fetch down that path this cycle,
// so we have to wait until the next cycle to fetch those
instrs_to_read_this_cycle = 0;
}
DP( if (warmup_complete[cpu]) {
cout << "[BRANCH] PREDICTED instr_id: " << instr_unique_id << " ip: " << hex << arch_instr.ip << dec;
cout << " taken: " << +arch_instr.branch_taken << " predicted: " << +branch_prediction << "\tcpu = " << cpu << endl; });
}
last_branch_result(arch_instr.ip, arch_instr.branch_taken);
}
//if ((num_reads == FETCH_WIDTH) || (ROB.occupancy == ROB.SIZE))
if ((num_reads >= instrs_to_read_this_cycle) || (ROB.occupancy == ROB.SIZE))
continue_reading = 0;
}
instr_unique_id++;
}
} else {
if (!fread(¤t_instr, instr_size, 1, trace_file)) {
// reached end of file for this trace
cout << "*** Reached end of trace for Core: " << cpu << " Repeating trace: " << trace_string << endl;
// close the trace file and re-open it
pclose(trace_file);
trace_file = popen(gunzip_command, "r");
if (trace_file == NULL) {
cerr << endl << "*** CANNOT REOPEN TRACE FILE: " << trace_string << " ***" << endl;
assert(0);
}
} else { // successfully read the trace
// copy the instruction into the performance model's instruction format
ooo_model_instr arch_instr;
int num_reg_ops = 0, num_mem_ops = 0;
arch_instr.instr_id = instr_unique_id;
arch_instr.ip = current_instr.ip;
arch_instr.is_branch = current_instr.is_branch;
arch_instr.branch_taken = current_instr.branch_taken;
arch_instr.asid[0] = cpu;
arch_instr.asid[1] = cpu;
for (uint32_t i=0; i<MAX_INSTR_DESTINATIONS; i++) {
arch_instr.destination_registers[i] = current_instr.destination_registers[i];
arch_instr.destination_memory[i] = current_instr.destination_memory[i];
arch_instr.destination_virtual_address[i] = current_instr.destination_memory[i];
if (arch_instr.destination_registers[i])
num_reg_ops++;
if (arch_instr.destination_memory[i]) {
num_mem_ops++;
// update STA, this structure is required to execute store instructios properly without deadlock
if (num_mem_ops > 0) {
#ifdef SANITY_CHECK
if (STA[STA_tail] < UINT64_MAX) {
if (STA_head != STA_tail)
assert(0);
}
#endif
STA[STA_tail] = instr_unique_id;
STA_tail++;
if (STA_tail == STA_SIZE)
STA_tail = 0;
}
}
}
for (int i=0; i<NUM_INSTR_SOURCES; i++) {
arch_instr.source_registers[i] = current_instr.source_registers[i];
arch_instr.source_memory[i] = current_instr.source_memory[i];
arch_instr.source_virtual_address[i] = current_instr.source_memory[i];
if (arch_instr.source_registers[i])
num_reg_ops++;
if (arch_instr.source_memory[i])
num_mem_ops++;
}
arch_instr.num_reg_ops = num_reg_ops;
arch_instr.num_mem_ops = num_mem_ops;
if (num_mem_ops > 0)
arch_instr.is_memory = 1;
// virtually add this instruction to the ROB
if (ROB.occupancy < ROB.SIZE) {
uint32_t rob_index = add_to_rob(&arch_instr);
num_reads++;
// branch prediction
if (arch_instr.is_branch) {
DP( if (warmup_complete[cpu]) {
cout << "[BRANCH] instr_id: " << instr_unique_id << " ip: " << hex << arch_instr.ip << dec << " taken: " << +arch_instr.branch_taken << "\tcpu = " << cpu << endl; });
num_branch++;
/*
uint8_t branch_prediction;
// for faster simulation, force perfect prediction during the warmup
// note that branch predictor is still learning with real branch results
if (all_warmup_complete == 0)
branch_prediction = arch_instr.branch_taken;
else
branch_prediction = predict_branch(arch_instr.ip);
*/
uint8_t branch_prediction = predict_branch(arch_instr.ip);
if (arch_instr.branch_taken != branch_prediction) {
branch_mispredictions++;
DP( if (warmup_complete[cpu]) {
cout << "[BRANCH] MISPREDICTED instr_id: " << instr_unique_id << " ip: " << hex << arch_instr.ip << dec;
cout << " taken: " << +arch_instr.branch_taken << " predicted: " << +branch_prediction << "\tcpu = " << cpu << endl; });
// halt any further fetch this cycle
instrs_to_read_this_cycle = 0;
// and stall any additional fetches until the branch is executed
fetch_stall = 1;
ROB.entry[rob_index].branch_mispredicted = 1;
}
else {
if (branch_prediction == 1) {
// if we are accurately predicting a branch to be taken, then we can't possibly fetch down that path this cycle,
// so we have to wait until the next cycle to fetch those
instrs_to_read_this_cycle = 0;
}
DP( if (warmup_complete[cpu]) {
cout << "[BRANCH] PREDICTED instr_id: " << instr_unique_id << " ip: " << hex << arch_instr.ip << dec;
cout << " taken: " << +arch_instr.branch_taken << " predicted: " << +branch_prediction << "\tcpu = " << cpu << endl; });
}
last_branch_result(arch_instr.ip, arch_instr.branch_taken);
}
//if ((num_reads == FETCH_WIDTH) || (ROB.occupancy == ROB.SIZE))
if ((num_reads >= instrs_to_read_this_cycle) || (ROB.occupancy == ROB.SIZE))
continue_reading = 0;
}
instr_unique_id++;
}
}
}
//instrs_to_fetch_this_cycle = num_reads;
}
uint32_t O3_CPU::add_to_rob(ooo_model_instr *arch_instr)
{
uint32_t index = ROB.tail;
// sanity check
if (ROB.entry[index].instr_id != 0) {
cerr << "[ROB_ERROR] " << __func__ << " is not empty index: " << index;
cerr << " instr_id: " << ROB.entry[index].instr_id << endl;
assert(0);
}
memcpy (&ROB.entry[index], arch_instr, sizeof(ooo_model_instr));
ROB.entry[index].event_cycle = current_core_cycle[cpu];
ROB.occupancy++;
ROB.tail++;
if (ROB.tail >= ROB.SIZE)
ROB.tail = 0;
DP ( if (warmup_complete[cpu]) {
cout << "[ROB] " << __func__ << " instr_id: " << ROB.entry[index].instr_id;
cout << " ip: " << hex << ROB.entry[index].ip << dec;
cout << " head: " << ROB.head << " tail: " << ROB.tail << " occupancy: " << ROB.occupancy;
cout << " event: " << ROB.entry[index].event_cycle << " current: " << current_core_cycle[cpu] << "\tcpu = " << cpu << endl; });
#ifdef SANITY_CHECK
if (ROB.entry[index].ip == 0) {
cerr << "[ROB_ERROR] " << __func__ << " ip is zero index: " << index;
cerr << " instr_id: " << ROB.entry[index].instr_id << " ip: " << ROB.entry[index].ip << endl;
assert(0);
}
#endif
return index;
}
uint32_t O3_CPU::check_rob(uint64_t instr_id)
{
if ((ROB.head == ROB.tail) && ROB.occupancy == 0)
return ROB.SIZE;
if (ROB.head < ROB.tail) {
for (uint32_t i=ROB.head; i<ROB.tail; i++) {
if (ROB.entry[i].instr_id == instr_id) {
DP ( if (warmup_complete[ROB.cpu]) {
cout << "[ROB] " << __func__ << " same instr_id: " << ROB.entry[i].instr_id;
cout << " rob_index: " << i << "\tcpu = " << cpu << endl; });
return i;
}
}
}
else {
for (uint32_t i=ROB.head; i<ROB.SIZE; i++) {
if (ROB.entry[i].instr_id == instr_id) {
DP ( if (warmup_complete[cpu]) {
cout << "[ROB] " << __func__ << " same instr_id: " << ROB.entry[i].instr_id;
cout << " rob_index: " << i << "\tcpu = " << cpu << endl; });
return i;
}
}
for (uint32_t i=0; i<ROB.tail; i++) {
if (ROB.entry[i].instr_id == instr_id) {
DP ( if (warmup_complete[cpu]) {
cout << "[ROB] " << __func__ << " same instr_id: " << ROB.entry[i].instr_id;
cout << " rob_index: " << i << "\tcpu = " << cpu << endl; });
return i;
}
}
}
cerr << "[ROB_ERROR] " << __func__ << " does not have any matching index! ";
cerr << " instr_id: " << instr_id << endl;
assert(0);
return ROB.SIZE;
}
void O3_CPU::fetch_instruction()
{
// TODO: can we model wrong path execusion?
// add this request to ITLB
uint32_t read_index = (ROB.last_read == (ROB.SIZE-1)) ? 0 : (ROB.last_read + 1);
for (uint32_t i=0; i<FETCH_WIDTH; i++) {
if (ROB.entry[read_index].ip == 0)
break;
#ifdef SANITY_CHECK
// sanity check
if (ROB.entry[read_index].translated) {
if (read_index == ROB.head)
break;
else {
cout << "read_index: " << read_index << " ROB.head: " << ROB.head << " ROB.tail: " << ROB.tail << endl;
assert(0);
}
}
#endif
PACKET trace_packet;
trace_packet.instruction = 1;
trace_packet.tlb_access = 1;
trace_packet.fill_level = FILL_L1;
trace_packet.cpu = cpu;
trace_packet.address = ROB.entry[read_index].ip >> LOG2_PAGE_SIZE;
if (knob_cloudsuite)
trace_packet.address = ((ROB.entry[read_index].ip >> LOG2_PAGE_SIZE) << 9) | ( 256 + ROB.entry[read_index].asid[0]);
else
trace_packet.address = ROB.entry[read_index].ip >> LOG2_PAGE_SIZE;
trace_packet.full_addr = ROB.entry[read_index].ip;
trace_packet.instr_id = ROB.entry[read_index].instr_id;
trace_packet.rob_index = read_index;
trace_packet.producer = 0; // TODO: check if this guy gets used or not
trace_packet.ip = ROB.entry[read_index].ip;
trace_packet.type = LOAD;
trace_packet.asid[0] = ROB.entry[read_index].asid[0];
trace_packet.asid[1] = ROB.entry[read_index].asid[1];
trace_packet.event_cycle = current_core_cycle[cpu];
int rq_index = ITLB.add_rq(&trace_packet);
if (rq_index == -2)
break;
else {
/*
if (rq_index >= 0) {
uint32_t producer = ITLB.RQ.entry[rq_index].rob_index;
ROB.entry[read_index].fetch_producer = producer;
ROB.entry[read_index].is_consumer = 1;
ROB.entry[producer].memory_instrs_depend_on_me[read_index] = 1;
ROB.entry[producer].is_producer = 1; // producer for fetch
}
*/
ROB.last_read = read_index;
read_index++;
if (read_index == ROB.SIZE)
read_index = 0;
}
}
uint32_t fetch_index = (ROB.last_fetch == (ROB.SIZE-1)) ? 0 : (ROB.last_fetch + 1);
for (uint32_t i=0; i<FETCH_WIDTH; i++) {
// fetch is in-order so it should be break
if ((ROB.entry[fetch_index].translated != COMPLETED) || (ROB.entry[fetch_index].event_cycle > current_core_cycle[cpu]))
break;
// sanity check
if (ROB.entry[fetch_index].fetched) {
if (fetch_index == ROB.head)
break;
else {
cout << "fetch_index: " << fetch_index << " ROB.head: " << ROB.head << " ROB.tail: " << ROB.tail << endl;
assert(0);
}
}
// add it to L1I
PACKET fetch_packet;
fetch_packet.instruction = 1;
fetch_packet.fill_level = FILL_L1;
fetch_packet.cpu = cpu;
fetch_packet.address = ROB.entry[fetch_index].instruction_pa >> 6;
fetch_packet.instruction_pa = ROB.entry[fetch_index].instruction_pa;
fetch_packet.full_addr = ROB.entry[fetch_index].instruction_pa;
fetch_packet.instr_id = ROB.entry[fetch_index].instr_id;
fetch_packet.rob_index = fetch_index;
fetch_packet.producer = 0;
fetch_packet.ip = ROB.entry[fetch_index].ip;
fetch_packet.type = LOAD;
fetch_packet.asid[0] = ROB.entry[fetch_index].asid[0];
fetch_packet.asid[1] = ROB.entry[fetch_index].asid[1];
fetch_packet.event_cycle = current_core_cycle[cpu];
int rq_index = L1I.add_rq(&fetch_packet);
if (rq_index == -2)
break;
else {
/*
if (rq_index >= 0) {
uint32_t producer = L1I.RQ.entry[rq_index].rob_index;
ROB.entry[fetch_index].fetch_producer = producer;
ROB.entry[fetch_index].is_consumer = 1;
ROB.entry[producer].memory_instrs_depend_on_me[fetch_index] = 1;
ROB.entry[producer].is_producer = 1;
}
*/
ROB.entry[fetch_index].fetched = INFLIGHT;
ROB.last_fetch = fetch_index;
fetch_index++;
if (fetch_index == ROB.SIZE)
fetch_index = 0;
}
}
}
// TODO: When should we update ROB.schedule_event_cycle?
// I. Instruction is fetched
// II. Instruction is completed
// III. Instruction is retired
void O3_CPU::schedule_instruction()
{
if ((ROB.head == ROB.tail) && ROB.occupancy == 0)
return;
// execution is out-of-order but we have an in-order scheduling algorithm to detect all RAW dependencies
uint32_t limit = ROB.next_fetch[1];
num_searched = 0;
if (ROB.head < limit) {
for (uint32_t i=ROB.head; i<limit; i++) {
if ((ROB.entry[i].fetched != COMPLETED) || (ROB.entry[i].event_cycle > current_core_cycle[cpu]) || (num_searched >= SCHEDULER_SIZE))
return;
if (ROB.entry[i].scheduled == 0)
do_scheduling(i);
num_searched++;
}
}
else {
for (uint32_t i=ROB.head; i<ROB.SIZE; i++) {
if ((ROB.entry[i].fetched != COMPLETED) || (ROB.entry[i].event_cycle > current_core_cycle[cpu]) || (num_searched >= SCHEDULER_SIZE))
return;
if (ROB.entry[i].scheduled == 0)
do_scheduling(i);
num_searched++;
}
for (uint32_t i=0; i<limit; i++) {
if ((ROB.entry[i].fetched != COMPLETED) || (ROB.entry[i].event_cycle > current_core_cycle[cpu]) || (num_searched >= SCHEDULER_SIZE))
return;
if (ROB.entry[i].scheduled == 0)
do_scheduling(i);
num_searched++;
}
}
}
void O3_CPU::do_scheduling(uint32_t rob_index)
{
ROB.entry[rob_index].reg_ready = 1; // reg_ready will be reset to 0 if there is RAW dependency
reg_dependency(rob_index);
ROB.next_schedule = (rob_index == (ROB.SIZE - 1)) ? 0 : (rob_index + 1);
if (ROB.entry[rob_index].is_memory)
ROB.entry[rob_index].scheduled = INFLIGHT;
else {
ROB.entry[rob_index].scheduled = COMPLETED;
// ADD LATENCY
if (ROB.entry[rob_index].event_cycle < current_core_cycle[cpu])
ROB.entry[rob_index].event_cycle = current_core_cycle[cpu] + SCHEDULING_LATENCY;
else
ROB.entry[rob_index].event_cycle += SCHEDULING_LATENCY;
if (ROB.entry[rob_index].reg_ready) {
#ifdef SANITY_CHECK
if (RTE1[RTE1_tail] < ROB_SIZE)
assert(0);
#endif
// remember this rob_index in the Ready-To-Execute array 1
RTE1[RTE1_tail] = rob_index;
DP (if (warmup_complete[cpu]) {
cout << "[RTE1] " << __func__ << " instr_id: " << ROB.entry[rob_index].instr_id << " rob_index: " << rob_index << " is added to RTE1";
cout << " head: " << RTE1_head << " tail: " << RTE1_tail << "\tcpu = " << cpu << endl; });
RTE1_tail++;
if (RTE1_tail == ROB_SIZE)
RTE1_tail = 0;
}
}
}
void O3_CPU::reg_dependency(uint32_t rob_index)
{
// print out source/destination registers
DP (if (warmup_complete[cpu]) {
for (uint32_t i=0; i<NUM_INSTR_SOURCES; i++) {
if (ROB.entry[rob_index].source_registers[i]) {
cout << "[ROB] " << __func__ << " instr_id: " << ROB.entry[rob_index].instr_id << " is_memory: " << +ROB.entry[rob_index].is_memory;
cout << " load reg_index: " << +ROB.entry[rob_index].source_registers[i] << "\tcpu = " << cpu << endl;
}
}
for (uint32_t i=0; i<MAX_INSTR_DESTINATIONS; i++) {
if (ROB.entry[rob_index].destination_registers[i]) {
cout << "[ROB] " << __func__ << " instr_id: " << ROB.entry[rob_index].instr_id << " is_memory: " << +ROB.entry[rob_index].is_memory;
cout << " store reg_index: " << +ROB.entry[rob_index].destination_registers[i] << "\tcpu = " << cpu << endl;
}
} });
// check RAW dependency
int prior = rob_index - 1;
if (prior < 0)
prior = ROB.SIZE - 1;
if (rob_index != ROB.head) {
if ((int)ROB.head <= prior) {
for (int i=prior; i>=(int)ROB.head; i--) {
//if (ROB.entry[i].destination_registers[0] && (ROB.entry[i].executed != COMPLETED)) {
if (ROB.entry[i].executed != COMPLETED) {
for (uint32_t j=0; j<NUM_INSTR_SOURCES; j++) {
if (ROB.entry[rob_index].source_registers[j] && (ROB.entry[rob_index].reg_RAW_checked[j] == 0))
reg_RAW_dependency(i, rob_index, j);
}
}
}
}
else {
for (int i=prior; i>=0; i--) {
//if (ROB.entry[i].destination_registers[0] && (ROB.entry[i].executed != COMPLETED)) {
if (ROB.entry[i].executed != COMPLETED) {
for (uint32_t j=0; j<NUM_INSTR_SOURCES; j++) {
if (ROB.entry[rob_index].source_registers[j] && (ROB.entry[rob_index].reg_RAW_checked[j] == 0))
reg_RAW_dependency(i, rob_index, j);
}
}
}
for (int i=ROB.SIZE-1; i>=(int)ROB.head; i--) {
//if (ROB.entry[i].destination_registers[0] && (ROB.entry[i].executed != COMPLETED)) {
if (ROB.entry[i].executed != COMPLETED) {
for (uint32_t j=0; j<NUM_INSTR_SOURCES; j++) {
if (ROB.entry[rob_index].source_registers[j] && (ROB.entry[rob_index].reg_RAW_checked[j] == 0))
reg_RAW_dependency(i, rob_index, j);
}
}
}
}
}
}
void O3_CPU::reg_RAW_dependency(uint32_t prior, uint32_t current, uint32_t source_index)
{
for (uint32_t i=0; i<MAX_INSTR_DESTINATIONS; i++) {
if (ROB.entry[prior].destination_registers[i] == 0)
continue;
if (ROB.entry[prior].destination_registers[i] == ROB.entry[current].source_registers[source_index]) {
// we need to mark this dependency in the ROB since the producer might not be added in the store queue yet
ROB.entry[prior].registers_instrs_depend_on_me[current] = 1; // this load cannot be executed until the prior store gets executed
ROB.entry[prior].registers_index_depend_on_me[current][source_index] = 1; // this load cannot be executed until the prior store gets executed
ROB.entry[prior].reg_RAW_producer = 1;
ROB.entry[current].reg_ready = 0;
ROB.entry[current].producer_id = ROB.entry[prior].instr_id;
ROB.entry[current].num_reg_dependent++;
ROB.entry[current].reg_RAW_checked[source_index] = 1;
DP (if(warmup_complete[cpu]) {
cout << "[ROB] " << __func__ << " instr_id: " << ROB.entry[current].instr_id << " is_memory: " << +ROB.entry[current].is_memory;
cout << " RAW reg_index: " << +ROB.entry[current].source_registers[source_index];
cout << " producer_id: " << ROB.entry[prior].instr_id << "\tcpu = " << cpu << endl; });
return;
}
}
}
void O3_CPU::execute_instruction()
{
if ((ROB.head == ROB.tail) && ROB.occupancy == 0)
return;
// out-of-order execution for non-memory instructions
// memory instructions are handled by memory_instruction()
uint32_t exec_issued = 0, num_iteration = 0;
while (exec_issued < EXEC_WIDTH) {
if (RTE0[RTE0_head] < ROB_SIZE) {
uint32_t exec_index = RTE0[RTE0_head];
if (ROB.entry[exec_index].event_cycle <= current_core_cycle[cpu]) {
do_execution(exec_index);
RTE0[RTE0_head] = ROB_SIZE;
RTE0_head++;
if (RTE0_head == ROB_SIZE)
RTE0_head = 0;
exec_issued++;
}
}
else {
//DP (if (warmup_complete[cpu]) {
//cout << "[RTE0] is empty head: " << RTE0_head << " tail: " << RTE0_tail << endl; });
break;
}
num_iteration++;
if (num_iteration == (ROB_SIZE-1))
break;
}
num_iteration = 0;
while (exec_issued < EXEC_WIDTH) {
if (RTE1[RTE1_head] < ROB_SIZE) {
uint32_t exec_index = RTE1[RTE1_head];
if (ROB.entry[exec_index].event_cycle <= current_core_cycle[cpu]) {
do_execution(exec_index);
RTE1[RTE1_head] = ROB_SIZE;
RTE1_head++;
if (RTE1_head == ROB_SIZE)
RTE1_head = 0;
exec_issued++;
}
}
else {
//DP (if (warmup_complete[cpu]) {
//cout << "[RTE1] is empty head: " << RTE1_head << " tail: " << RTE1_tail << endl; });
break;
}
num_iteration++;
if (num_iteration == (ROB_SIZE-1))
break;
}
}
void O3_CPU::do_execution(uint32_t rob_index)
{
//if (ROB.entry[rob_index].reg_ready && (ROB.entry[rob_index].scheduled == COMPLETED) && (ROB.entry[rob_index].event_cycle <= current_core_cycle[cpu])) {
ROB.entry[rob_index].executed = INFLIGHT;
// ADD LATENCY
if (ROB.entry[rob_index].event_cycle < current_core_cycle[cpu])
ROB.entry[rob_index].event_cycle = current_core_cycle[cpu] + EXEC_LATENCY;
else
ROB.entry[rob_index].event_cycle += EXEC_LATENCY;
inflight_reg_executions++;
DP (if (warmup_complete[cpu]) {
cout << "[ROB] " << __func__ << " non-memory instr_id: " << ROB.entry[rob_index].instr_id;
cout << " event_cycle: " << ROB.entry[rob_index].event_cycle << "\tcpu = " << cpu << endl;});
//}
}
void O3_CPU::schedule_memory_instruction()
{
if ((ROB.head == ROB.tail) && ROB.occupancy == 0)
return;
// execution is out-of-order but we have an in-order scheduling algorithm to detect all RAW dependencies
uint32_t limit = ROB.next_schedule;
num_searched = 0;
if (ROB.head < limit) {
for (uint32_t i=ROB.head; i<limit; i++) {
if (ROB.entry[i].is_memory == 0)
continue;
if ((ROB.entry[i].fetched != COMPLETED) || (ROB.entry[i].event_cycle > current_core_cycle[cpu]) || (num_searched >= SCHEDULER_SIZE))
break;
if (ROB.entry[i].is_memory && ROB.entry[i].reg_ready && (ROB.entry[i].scheduled == INFLIGHT))
do_memory_scheduling(i);
}
}
else {
for (uint32_t i=ROB.head; i<ROB.SIZE; i++) {
if (ROB.entry[i].is_memory == 0)
continue;
if ((ROB.entry[i].fetched != COMPLETED) || (ROB.entry[i].event_cycle > current_core_cycle[cpu]) || (num_searched >= SCHEDULER_SIZE))
break;
if (ROB.entry[i].is_memory && ROB.entry[i].reg_ready && (ROB.entry[i].scheduled == INFLIGHT))
do_memory_scheduling(i);
}
for (uint32_t i=0; i<limit; i++) {
if (ROB.entry[i].is_memory == 0)
continue;
if ((ROB.entry[i].fetched != COMPLETED) || (ROB.entry[i].event_cycle > current_core_cycle[cpu]) || (num_searched >= SCHEDULER_SIZE))
break;
if (ROB.entry[i].is_memory && ROB.entry[i].reg_ready && (ROB.entry[i].scheduled == INFLIGHT))
do_memory_scheduling(i);
}
}
}
void O3_CPU::execute_memory_instruction()
{
operate_lsq();
operate_cache();
}
void O3_CPU::do_memory_scheduling(uint32_t rob_index)
{
uint32_t not_available = check_and_add_lsq(rob_index);
if (not_available == 0) {
ROB.entry[rob_index].scheduled = COMPLETED;
if (ROB.entry[rob_index].executed == 0) // it could be already set to COMPLETED due to store-to-load forwarding
ROB.entry[rob_index].executed = INFLIGHT;
DP (if (warmup_complete[cpu]) {
cout << "[ROB] " << __func__ << " instr_id: " << ROB.entry[rob_index].instr_id << " rob_index: " << rob_index;
cout << " scheduled all num_mem_ops: " << ROB.entry[rob_index].num_mem_ops << "\tcpu = " << cpu << endl; });
}
num_searched++;
}
uint32_t O3_CPU::check_and_add_lsq(uint32_t rob_index)
{
uint32_t num_mem_ops = 0, num_added = 0;
// load
for (uint32_t i=0; i<NUM_INSTR_SOURCES; i++) {
if (ROB.entry[rob_index].source_memory[i]) {
num_mem_ops++;
if (ROB.entry[rob_index].source_added[i])
num_added++;
else if (LQ.occupancy < LQ.SIZE) {
add_load_queue(rob_index, i);
num_added++;
}
else {
DP(if(warmup_complete[cpu]) {
cout << "[LQ] " << __func__ << " instr_id: " << ROB.entry[rob_index].instr_id;
cout << " cannot be added in the load queue occupancy: " << LQ.occupancy << " cycle: " << current_core_cycle[cpu] << "\tcpu = " << cpu << endl; });
}
}
}
// store
for (uint32_t i=0; i<MAX_INSTR_DESTINATIONS; i++) {
if (ROB.entry[rob_index].destination_memory[i]) {
num_mem_ops++;
if (ROB.entry[rob_index].destination_added[i])
num_added++;
else if (SQ.occupancy < SQ.SIZE) {
if (STA[STA_head] == ROB.entry[rob_index].instr_id) {
add_store_queue(rob_index, i);
num_added++;
}
//add_store_queue(rob_index, i);
//num_added++;
}
else {
DP(if(warmup_complete[cpu]) {
cout << "[SQ] " << __func__ << " instr_id: " << ROB.entry[rob_index].instr_id;
cout << " cannot be added in the store queue occupancy: " << SQ.occupancy << " cycle: " << current_core_cycle[cpu] << "\tcpu = " << cpu << endl; });
}
}
}
if (num_added == num_mem_ops)
return 0;
uint32_t not_available = num_mem_ops - num_added;
if (not_available > num_mem_ops) {
cerr << "instr_id: " << ROB.entry[rob_index].instr_id << endl;
assert(0);
}
return not_available;
}
void O3_CPU::add_load_queue(uint32_t rob_index, uint32_t data_index)
{
// search for an empty slot
uint32_t lq_index = LQ.SIZE;
for (uint32_t i=0; i<LQ.SIZE; i++) {
if (LQ.entry[i].virtual_address == 0) {
lq_index = i;
break;
}
}
// sanity check
if (lq_index == LQ.SIZE) {
cerr << "instr_id: " << ROB.entry[rob_index].instr_id << " no empty slot in the load queue!!!" << endl;
assert(0);
}
// add it to the load queue
ROB.entry[rob_index].lq_index[data_index] = lq_index;
LQ.entry[lq_index].instr_id = ROB.entry[rob_index].instr_id;
LQ.entry[lq_index].virtual_address = ROB.entry[rob_index].source_memory[data_index];
LQ.entry[lq_index].ip = ROB.entry[rob_index].ip;
LQ.entry[lq_index].data_index = data_index;
LQ.entry[lq_index].rob_index = rob_index;
LQ.entry[lq_index].asid[0] = ROB.entry[rob_index].asid[0];
LQ.entry[lq_index].asid[1] = ROB.entry[rob_index].asid[1];
LQ.entry[lq_index].event_cycle = current_core_cycle[cpu] + SCHEDULING_LATENCY;
LQ.occupancy++;
// check RAW dependency
int prior = rob_index - 1;
if (prior < 0)
prior = ROB.SIZE - 1;
if (rob_index != ROB.head) {
if ((int)ROB.head <= prior) {
for (int i=prior; i>=(int)ROB.head; i--) {
if (LQ.entry[lq_index].producer_id != UINT64_MAX)
break;
mem_RAW_dependency(i, rob_index, data_index, lq_index);
}
}
else {
for (int i=prior; i>=0; i--) {
if (LQ.entry[lq_index].producer_id != UINT64_MAX)
break;
mem_RAW_dependency(i, rob_index, data_index, lq_index);
}
for (int i=ROB.SIZE-1; i>=(int)ROB.head; i--) {
if (LQ.entry[lq_index].producer_id != UINT64_MAX)
break;
mem_RAW_dependency(i, rob_index, data_index, lq_index);
}
}
}
// check
// 1) if store-to-load forwarding is possible
// 2) if there is WAR that are not correctly executed
uint32_t forwarding_index = SQ.SIZE;
for (uint32_t i=0; i<SQ.SIZE; i++) {
// skip empty slot
if (SQ.entry[i].virtual_address == 0)
continue;
// forwarding should be done by the SQ entry that holds the same producer_id from RAW dependency check
if (SQ.entry[i].virtual_address == LQ.entry[lq_index].virtual_address) { // store-to-load forwarding check
// forwarding store is in the SQ
if ((rob_index != ROB.head) && (LQ.entry[lq_index].producer_id == SQ.entry[i].instr_id)) { // RAW
forwarding_index = i;
break; // should be break
}
if ((LQ.entry[lq_index].producer_id == UINT64_MAX) && (LQ.entry[lq_index].instr_id <= SQ.entry[i].instr_id)) { // WAR
// a load is about to be added in the load queue and we found a store that is
// "logically later in the program order but already executed" => this is not correctly executed WAR
// due to out-of-order execution, this case is possible, for example
// 1) application is load intensive and load queue is full
// 2) we have loads that can't be added in the load queue
// 3) subsequent stores logically behind in the program order are added in the store queue first
// thanks to the store buffer, data is not written back to the memory system until retirement
// also due to in-order retirement, this "already executed store" cannot be retired until we finish the prior load instruction
// if we detect WAR when a load is added in the load queue, just let the load instruction to access the memory system
// no need to mark any dependency because this is actually WAR not RAW
// do not forward data from the store queue since this is WAR
// just read correct data from data cache
LQ.entry[lq_index].physical_address = 0;
LQ.entry[lq_index].translated = 0;
LQ.entry[lq_index].fetched = 0;
DP(if(warmup_complete[cpu]) {
cout << "[LQ] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id << " reset fetched: " << +LQ.entry[lq_index].fetched;
cout << " to obey WAR store instr_id: " << SQ.entry[i].instr_id << " cycle: " << current_core_cycle[cpu] << "\tcpu = " << cpu << endl; });
}
}
}
if (forwarding_index != SQ.SIZE) { // we have a store-to-load forwarding
if ((SQ.entry[forwarding_index].fetched == COMPLETED) && (SQ.entry[forwarding_index].event_cycle <= current_core_cycle[cpu])) {
LQ.entry[lq_index].physical_address = (SQ.entry[forwarding_index].physical_address & ~(uint64_t) ((1 << LOG2_BLOCK_SIZE) - 1)) | (LQ.entry[lq_index].virtual_address & ((1 << LOG2_BLOCK_SIZE) - 1));
LQ.entry[lq_index].translated = COMPLETED;
LQ.entry[lq_index].fetched = COMPLETED;
uint32_t fwr_rob_index = LQ.entry[lq_index].rob_index;
ROB.entry[fwr_rob_index].num_mem_ops--;
ROB.entry[fwr_rob_index].event_cycle = current_core_cycle[cpu];
if (ROB.entry[fwr_rob_index].num_mem_ops < 0) {
cerr << "instr_id: " << ROB.entry[fwr_rob_index].instr_id << endl;
assert(0);
}
if (ROB.entry[fwr_rob_index].num_mem_ops == 0)
inflight_mem_executions++;
DP(if(warmup_complete[cpu]) {
cout << "[LQ] " << __func__ << " instr_id: " << LQ.entry[lq_index].instr_id << hex;
cout << " full_addr: " << LQ.entry[lq_index].physical_address << dec << " is forwarded by store instr_id: ";
cout << SQ.entry[forwarding_index].instr_id << " remain_num_ops: " << ROB.entry[fwr_rob_index].num_mem_ops << " cycle: " << current_core_cycle[cpu] << "\tcpu = " << cpu << endl; });
release_load_queue(lq_index);
}
else
; // store is not executed yet, forwarding will be handled by execute_store()
}
// succesfully added to the load queue