refactor: patch fesvr includes in Verilator build steps and streamline include paths

Author: shirohasuki

api/steps/verilator/02_verilog_event_step.py

@@ -65,10 +65,33 @@ async def handler(data, context):
         stderr_prefix="verilator verilog",
     )
 
-    # Remove unwanted file
-    topname_file = f"{arch_dir}/BBSimHarness.sv"
-    if os.path.exists(topname_file):
-        os.remove(topname_file)
+    # Remove testchipip C++ sources that depend on fesvr (which we don't have).
+    # SimTSI.v is kept so verilator can resolve the SimTSI module reference in BBSimHarness.sv;
+    # tsi_tick DPI symbol is satisfied by arch/src/csrc/src/monitor/ioe/tsi_stub.cc instead.
+    for unwanted in [
+        f"{build_dir}/testchip_htif.cc",
+        f"{build_dir}/testchip_htif.h",
+        f"{build_dir}/testchip_tsi.cc",
+        f"{build_dir}/testchip_tsi.h",
+        f"{build_dir}/SimTSI.cc",
+    ]:
+        if os.path.exists(unwanted):
+            os.remove(unwanted)
+
+    # Patch fesvr includes out of mm.h and mm.cc (copied from testchipip resources).
+    # They reference fesvr/memif.h which we don't have — our SimDRAM_bb.cc doesn't use it.
+    for patch_file in [f"{build_dir}/mm.h", f"{build_dir}/mm.cc"]:
+        if os.path.exists(patch_file):
+            with open(patch_file, "r") as f:
+                content = f.read()
+            patched = "\n".join(
+                line for line in content.splitlines()
+                if "fesvr/memif.h" not in line and "fesvr/elfloader.h" not in line
+            )
+            if patched != content:
+                with open(patch_file, "w") as f:
+                    f.write(patched)
+                context.logger.info(f"Patched fesvr includes from {patch_file}")
 
     # ==================================================================================
     # Return result to API

api/steps/verilator/03_build_event_step.py

@@ -46,68 +46,42 @@ async def handler(data, context):
     # Exclude testchipip's SimDRAM.cc — our SimDRAM_bb.cc overrides memory_init
     csrcs = [f for f in csrcs if not f.endswith("SimDRAM.cc") or "src/csrc" in f]
 
-    # Patch fesvr includes out of build/mm.h and build/mm.cc.
-    # These files are auto-copied from testchipip by Verilator as SimDRAM.v
-    # companion sources. They reference fesvr/memif.h which we don't have
-    # (fesvr is removed). The memif_t dependency was only used by SimDRAM.cc's
-    # load_elf — our SimDRAM_bb.cc doesn't use it.
-    for patch_file in [f"{build_dir}/mm.h", f"{build_dir}/mm.cc"]:
-        if os.path.exists(patch_file):
-            with open(patch_file, "r") as f:
-                content = f.read()
-            patched = "\n".join(
-                line for line in content.splitlines()
-                if "fesvr/memif.h" not in line and "fesvr/elfloader.h" not in line
-            )
-            if patched != content:
-                with open(patch_file, "w") as f:
-                    f.write(patched)
-                context.logger.info(f"Patched fesvr includes from {patch_file}")
+    # Exclude testchipip's TSI/HTIF C++ sources (deleted in verilog step, but guard anyway).
+    # tsi_tick DPI symbol is provided by tsi_stub.cc in src/csrc instead.
+    _tsi_htif = {"testchip_tsi.cc", "testchip_htif.cc", "SimTSI.cc"}
+    csrcs = [f for f in csrcs if os.path.basename(f) not in _tsi_htif]
 
     topname = "BBSimHarness"
 
     # ==================================================================================
     # Build flags
     # ==================================================================================
-    dramsim2_dir = f"{arch_dir}/thirdparty/chipyard/tools/DRAMSim2"
-
-    # Find readline headers/libs in nix store (not in standard paths under nix)
-    rl_headers = glob.glob("/nix/store/*readline*-dev/include/readline/readline.h")
-    readline_inc = os.path.dirname(os.path.dirname(rl_headers[0])) if rl_headers else ""
-    rl_libs = glob.glob("/nix/store/*readline*/lib/libreadline.so")
-    readline_lib = os.path.dirname(rl_libs[0]) if rl_libs else ""
-
-    # Find zlib headers/libs in nix store
-    zlib_headers = glob.glob("/nix/store/*zlib*-dev/include/zlib.h")
-    if not zlib_headers:
-        zlib_headers = glob.glob("/nix/store/*zlib*/include/zlib.h")
-    zlib_inc = os.path.dirname(zlib_headers[0]) if zlib_headers else ""
-    zlib_libs = glob.glob("/nix/store/*zlib*/lib/libz.so")
-    zlib_lib = os.path.dirname(zlib_libs[0]) if zlib_libs else ""
-
-    inc_paths = [
-        dramsim2_dir,
-        build_dir,
-        f"{arch_dir}/src/csrc/include",
-    ]
-    if readline_inc:
-        inc_paths.append(readline_inc)
-    if zlib_inc:
-        inc_paths.append(zlib_inc)
-    inc_flags = " ".join([f"-I{p}" for p in inc_paths if p])
+    result_dir   = f"{bbdir}/result"
+
+    def pkg_config(flag, pkg):
+        r = subprocess.run(["pkg-config", flag, pkg], capture_output=True, text=True)
+        return r.stdout.strip() if r.returncode == 0 else ""
+
+    readline_inc = pkg_config("--variable=includedir", "readline")
+    readline_lib = pkg_config("--variable=libdir", "readline")
+    zlib_lib     = pkg_config("--variable=libdir", "zlib")
+
+    inc_flags = " ".join([
+        f"-I{result_dir}/include",
+        f"-I{build_dir}",
+        f"-I{arch_dir}/src/csrc/include",
+        f"-I{readline_inc}",
+    ])
 
     # -DBBSIM: selects VBBSimHarness in bdb.h / main.cc
     cflags = f"{inc_flags} -DBBSIM -DTOP_NAME='\"V{topname}\"' -std=c++17"
 
     ldflags = (
         f"-lreadline -ldramsim -lstdc++ -lz "
-        f"-L{bbdir}/result/lib "
-        f"-L{dramsim2_dir} "
+        f"-L{result_dir}/lib "
+        f"-L{readline_lib} -Wl,-rpath,{readline_lib} "
+        f"-L{zlib_lib} -Wl,-rpath,{zlib_lib} "
     )
-    if readline_lib:
-        ldflags += f"-L{readline_lib} -Wl,-rpath,{readline_lib} "
-    if zlib_lib:
-        ldflags += f"-L{zlib_lib} -Wl,-rpath,{zlib_lib} "
 
     obj_dir = f"{build_dir}/obj_dir"
     subprocess.run(f"rm -rf {obj_dir}", shell=True)