feat: integrate RiscvBebopInOCPU into gem5

Author: shirohasuki

host/gem5/BebopInOCPU/BaseBebopInOCPU.py

@@ -4,11 +4,170 @@
 from m5.objects.DummyChecker import DummyChecker
 from m5.objects.FuncUnit import OpClass
 from m5.objects.TimingExpr import TimingExpr
+from m5.objects.BebopInOFU import (
+  BebopInOOpClass,
+  BebopInOOpClassSet,
+  BebopInOFUTiming,
+  BebopInOFU,
+  BebopInOFUPool,
+)
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
 
+def bebopMakeOpClassSet(op_classes):
+  def boxOpClass(op_class):
+    return BebopInOOpClass(opClass=op_class)
+
+  return BebopInOOpClassSet(opClasses=[boxOpClass(o) for o in op_classes])
+
+
+class BebopInODefaultIntFU(BebopInOFU):
+  opClasses = bebopMakeOpClassSet(["IntAlu"])
+  timings = [BebopInOFUTiming(description="Int", srcRegsRelativeLats=[2])]
+  opLat = 3
+
+
+class BebopInODefaultIntMulFU(BebopInOFU):
+  opClasses = bebopMakeOpClassSet(["IntMult"])
+  timings = [BebopInOFUTiming(description="Mul", srcRegsRelativeLats=[0])]
+  opLat = 3
+
+
+class BebopInODefaultIntDivFU(BebopInOFU):
+  opClasses = bebopMakeOpClassSet(["IntDiv"])
+  issueLat = 9
+  opLat = 9
+
+
+class BebopInODefaultFloatSimdFU(BebopInOFU):
+  opClasses = bebopMakeOpClassSet(
+    [
+      "FloatAdd",
+      "FloatCmp",
+      "FloatCvt",
+      "FloatMisc",
+      "FloatMult",
+      "FloatMultAcc",
+      "FloatDiv",
+      "FloatSqrt",
+      "Bf16Cvt",
+      "SimdAdd",
+      "SimdAddAcc",
+      "SimdAlu",
+      "SimdCmp",
+      "SimdCvt",
+      "SimdMisc",
+      "SimdMult",
+      "SimdMultAcc",
+      "SimdMatMultAcc",
+      "SimdShift",
+      "SimdShiftAcc",
+      "SimdDiv",
+      "SimdSqrt",
+      "SimdFloatAdd",
+      "SimdFloatAlu",
+      "SimdFloatCmp",
+      "SimdFloatCvt",
+      "SimdFloatDiv",
+      "SimdFloatMisc",
+      "SimdFloatMult",
+      "SimdFloatMultAcc",
+      "SimdFloatMatMultAcc",
+      "SimdFloatSqrt",
+      "SimdReduceAdd",
+      "SimdReduceAlu",
+      "SimdReduceCmp",
+      "SimdFloatReduceAdd",
+      "SimdFloatReduceCmp",
+      "SimdAes",
+      "SimdAesMix",
+      "SimdSha1Hash",
+      "SimdSha1Hash2",
+      "SimdSha256Hash",
+      "SimdSha256Hash2",
+      "SimdShaSigma2",
+      "SimdShaSigma3",
+      "SimdSha3",
+      "SimdSm4e",
+      "SimdCrc",
+      "Matrix",
+      "MatrixMov",
+      "MatrixOP",
+      "SimdExt",
+      "SimdFloatExt",
+      "SimdFloatCvt",
+      "SimdConfig",
+      "SimdDotProd",
+      "SimdBf16Add",
+      "SimdBf16Cmp",
+      "SimdBf16Cvt",
+      "SimdBf16DotProd",
+      "SimdBf16MatMultAcc",
+      "SimdBf16Mult",
+      "SimdBf16MultAcc",
+    ]
+  )
+
+  timings = [
+    BebopInOFUTiming(description="FloatSimd", srcRegsRelativeLats=[2])
+  ]
+  opLat = 6
+
+
+class BebopInODefaultPredFU(BebopInOFU):
+  opClasses = bebopMakeOpClassSet(["SimdPredAlu"])
+  timings = [BebopInOFUTiming(description="Pred", srcRegsRelativeLats=[2])]
+  opLat = 3
+
+
+class BebopInODefaultMemFU(BebopInOFU):
+  opClasses = bebopMakeOpClassSet(
+    [
+      "MemRead",
+      "MemWrite",
+      "FloatMemRead",
+      "FloatMemWrite",
+      "SimdUnitStrideLoad",
+      "SimdUnitStrideStore",
+      "SimdUnitStrideMaskLoad",
+      "SimdUnitStrideMaskStore",
+      "SimdStridedLoad",
+      "SimdStridedStore",
+      "SimdIndexedLoad",
+      "SimdIndexedStore",
+      "SimdUnitStrideFaultOnlyFirstLoad",
+      "SimdWholeRegisterLoad",
+      "SimdWholeRegisterStore",
+    ]
+  )
+  timings = [
+    BebopInOFUTiming(
+      description="Mem", srcRegsRelativeLats=[1], extraAssumedLat=2
+    )
+  ]
+  opLat = 1
+
+
+class BebopInODefaultMiscFU(BebopInOFU):
+  opClasses = bebopMakeOpClassSet(["InstPrefetch", "System"])
+  opLat = 1
+
+
+class BebopInODefaultFUPool(BebopInOFUPool):
+  funcUnits = [
+    BebopInODefaultIntFU(),
+    BebopInODefaultIntFU(),
+    BebopInODefaultIntMulFU(),
+    BebopInODefaultIntDivFU(),
+    BebopInODefaultFloatSimdFU(),
+    BebopInODefaultPredFU(),
+    BebopInODefaultMemFU(),
+    BebopInODefaultMiscFU(),
+  ]
+
+
 class BaseBebopInOCPU(BaseCPU):
   type = "BaseBebopInOCPU"
   cxx_header = "BebopInOCPU/cpu.hh"
@@ -157,6 +316,6 @@ def addCheckerCpu(self):
 
   # Functional unit pool
   executeFuncUnits = Param.BebopInOFUPool(
-    "FU pool for this processor"
+    BebopInODefaultFUPool(), "FU pool for this processor"
   )
 

host/gem5/BebopInOCPU/BebopInOCPUArch.py

@@ -8,16 +8,10 @@
   from m5.objects.ArmCPU import ArmCPU, ArmMMU
 
   class ArmBebopInOCPU(BaseBebopInOCPU, ArmCPU):
-    type = "ArmBebopInOCPU"
-    cxx_header = "BebopInOCPU/cpu.hh"
-    cxx_class = "gem5::BebopInOCPU"
     mmu = ArmMMU()
 
 
 if buildEnv.get("USE_RISCV_ISA"):
   class RiscvBebopInOCPU(BaseBebopInOCPU, RiscvCPU):
-    type = "RiscvBebopInOCPU"
-    cxx_header = "BebopInOCPU/cpu.hh"
-    cxx_class = "gem5::BebopInOCPU"
     mmu = RiscvMMU()
 

host/gem5/BebopInOCPU/BebopInOFU.py

@@ -35,7 +35,7 @@ class BebopInOFUTiming(SimObject):
     [], "per-src-reg relative latencies"
   )
   opClasses = Param.BebopInOOpClassSet(
-    NULL, "op classes to apply timing to"
+    BebopInOOpClassSet(), "op classes to apply timing to"
   )
   description = Param.String("", "description string")
 

host/gem5/riscv-se.py

@@ -11,6 +11,7 @@
 import m5
 import m5.stats
 from m5.objects import *
+from m5.objects import RiscvBebopInOCPU 
 
 # Parse command line arguments
 parser = argparse.ArgumentParser(description='Run a binary on RISCV using gem5')
@@ -33,12 +34,13 @@
 system.clk_domain.voltage_domain = VoltageDomain()
 
 # Set memory mode and range
-system.mem_mode = "atomic"
-# system.mem_mode = "timing"
+# system.mem_mode = "atomic"
+system.mem_mode = "timing"
 system.mem_ranges = [AddrRange("32GiB")]
 
 # Create CPU
-system.cpu = AtomicSimpleCPU()
+# system.cpu = AtomicSimpleCPU()
+system.cpu = RiscvBebopInOCPU()
 # system.cpu = RiscvTimingSimpleCPU()
 # system.cpu = RiscvMinorCPU()
 # system.cpu = RiscvO3CPU()