From 42e9386840fdc188c93196775a8a52443c4ff0c1 Mon Sep 17 00:00:00 2001
From: Akhil Velagapudi <4@4khil.com>
Date: Wed, 4 Dec 2024 16:08:19 -0800
Subject: [PATCH] Make error clearing more robust on non-F4 families

G4, H7, etc. require explicitly clearing the error flags from the ICR
register.

Signed-off-by: Akhil Velagapudi <4@4khil.com>
---
 src/usart.rs | 34 +++++++++++++++++++---------------
 1 file changed, 19 insertions(+), 15 deletions(-)

diff --git a/src/usart.rs b/src/usart.rs
index 747e97b..ca4100e 100644
--- a/src/usart.rs
+++ b/src/usart.rs
@@ -933,21 +933,7 @@ where
                 let status = self.regs.isr.read();
             }
         }
-        if status.pe().bit_is_set()
-            || status.fe().bit_is_set()
-            || status.nf().bit_is_set()
-            || status.ore().bit_is_set()
-        {
-            // Clear error flags by reading DR/RDR
-            cfg_if! {
-                if #[cfg(feature = "f4")] {
-                    let _ = self.regs.dr.read();
-                } else {
-                    let _ = self.regs.rdr.read();
-                }
-            }
-        }
-        if status.pe().bit_is_set() {
+        let result = if status.pe().bit_is_set() {
             Err(UartError::Parity)
         } else if status.fe().bit_is_set() {
             Err(UartError::Framing)
@@ -957,7 +943,25 @@ where
             Err(UartError::Overrun)
         } else {
             Ok(())
+        };
+        if result.is_err() {
+            // For F4, clear error flags by reading SR and DR
+            // For others, clear error flags by reading ISR, clearing ICR, then reading RDR
+            cfg_if! {
+                if #[cfg(feature = "f4")] {
+                    let _ = self.regs.dr.read();
+                } else {
+                    self.regs.icr.write(|w| {
+                        w.pecf().set_bit();
+                        w.fecf().set_bit();
+                        w.ncf().set_bit();
+                        w.orecf().set_bit()
+                    });
+                    let _ = self.regs.rdr.read();
+                }
+            }
         }
+        result
     }
 }