[SCEV] Add additional test with guards for 3-op AddRec.

Add additional tests for using information from loop guards in SCEV.

Author: fhahn

llvm/test/Analysis/ScalarEvolution/backedge-taken-count-guard-info-apply-to-adds.ll

@@ -56,3 +56,37 @@ loop:
 exit:
   ret void
 }
+
+declare void @use(ptr)
+
+define i32 @test_3_op_add(i32 %x, i32 %y, ptr %A) {
+; CHECK-LABEL: 'test_3_op_add'
+; CHECK-NEXT:  Determining loop execution counts for: @test_3_op_add
+; CHECK-NEXT:  Loop %loop: backedge-taken count is (-1 + (zext i32 (1 + (-1 * %x) + %y) to i64))<nsw>
+; CHECK-NEXT:  Loop %loop: constant max backedge-taken count is i64 2147483647
+; CHECK-NEXT:  Loop %loop: symbolic max backedge-taken count is (-1 + (zext i32 (1 + (-1 * %x) + %y) to i64))<nsw>
+; CHECK-NEXT:  Loop %loop: Trip multiple is 1
+;
+entry:
+  %pre.0 = icmp ugt i32 %x, 0
+  br i1 %pre.0, label %then, label %exit
+
+then:
+  %y.sub.x = sub i32 %y, %x
+  %pre.1 = icmp slt i32 %y.sub.x, 0
+  %add.1 = add i32 %y.sub.x, 1
+  %add.ext = zext i32 %add.1 to i64
+  br i1 %pre.1, label %exit, label %loop
+
+loop:
+  %iv = phi i64 [ %iv.next, %loop ], [ 0, %then ]
+  %and = and i64 %iv, 1
+  %gep = getelementptr i8, ptr %A, i64 %and
+  call void @use(ptr %gep)
+  %iv.next = add i64 %iv, 1
+  %ec = icmp eq i64 %iv.next, %add.ext
+  br i1 %ec, label %exit, label %loop
+
+exit:
+  ret i32 0
+}

llvm/test/Transforms/LoopIdiom/add-nsw-zext-fold.ll

@@ -1,4 +1,4 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
 ; RUN: opt -p loop-idiom -S %s | FileCheck %s
 
 define void @fold_add_zext_to_sext(ptr %dst, i1 %start) {
@@ -40,3 +40,56 @@ loop:
 exit:
   ret void
 }
+
+declare i16 @get()
+
+define void @test_memset_size_can_use_info_from_guards(i32 %x, ptr %dst) {
+; CHECK-LABEL: define void @test_memset_size_can_use_info_from_guards(
+; CHECK-SAME: i32 [[X:%.*]], ptr [[DST:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*]]:
+; CHECK-NEXT:    br label %[[LOOP1:.*]]
+; CHECK:       [[LOOP1_LOOPEXIT:.*]]:
+; CHECK-NEXT:    br label %[[LOOP1_BACKEDGE:.*]]
+; CHECK:       [[LOOP1]]:
+; CHECK-NEXT:    [[P:%.*]] = phi i32 [ 0, %[[ENTRY]] ], [ [[X]], %[[LOOP1_BACKEDGE]] ]
+; CHECK-NEXT:    [[L:%.*]] = call i16 @get()
+; CHECK-NEXT:    [[L_EXT:%.*]] = zext i16 [[L]] to i32
+; CHECK-NEXT:    [[SUB:%.*]] = sub i32 [[L_EXT]], [[P]]
+; CHECK-NEXT:    [[SHR:%.*]] = lshr i32 [[SUB]], 1
+; CHECK-NEXT:    [[EC:%.*]] = icmp ult i32 [[SUB]], 2
+; CHECK-NEXT:    br i1 [[EC]], label %[[LOOP1_BACKEDGE]], label %[[LOOP2_PREHEADER:.*]]
+; CHECK:       [[LOOP1_BACKEDGE]]:
+; CHECK-NEXT:    br label %[[LOOP1]]
+; CHECK:       [[LOOP2_PREHEADER]]:
+; CHECK-NEXT:    [[TMP0:%.*]] = zext i32 [[SUB]] to i64
+; CHECK-NEXT:    [[TMP1:%.*]] = lshr i64 [[TMP0]], 1
+; CHECK-NEXT:    [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[TMP1]], i64 1)
+; CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 1 [[DST]], i8 0, i64 [[UMAX]], i1 false)
+; CHECK-NEXT:    br label %[[LOOP2:.*]]
+; CHECK:       [[LOOP2]]:
+; CHECK-NEXT:    [[IV_2:%.*]] = phi i32 [ [[IV_2_NEXT:%.*]], %[[LOOP2]] ], [ 0, %[[LOOP2_PREHEADER]] ]
+; CHECK-NEXT:    [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i32 [[IV_2]]
+; CHECK-NEXT:    [[IV_2_NEXT]] = add i32 [[IV_2]], 1
+; CHECK-NEXT:    [[EC_2:%.*]] = icmp ult i32 [[IV_2_NEXT]], [[SHR]]
+; CHECK-NEXT:    br i1 [[EC_2]], label %[[LOOP2]], label %[[LOOP1_LOOPEXIT]]
+;
+entry:
+  br label %loop1
+
+loop1:
+  %p = phi i32 [ 0, %entry ], [ %x, %loop1 ], [ %x, %loop2 ]
+  %l = call i16 @get()
+  %l.ext = zext i16 %l to i32
+  %sub = sub i32 %l.ext, %p
+  %shr = lshr i32 %sub, 1
+  %ec = icmp ult i32 %sub, 2
+  br i1 %ec, label %loop1, label %loop2
+
+loop2:
+  %iv.2 = phi i32 [ 0, %loop1 ], [ %iv.2.next, %loop2 ]
+  %gep.dst = getelementptr i8, ptr %dst, i32 %iv.2
+  store i8 0, ptr %gep.dst, align 1
+  %iv.2.next = add i32 %iv.2, 1
+  %ec.2 = icmp ult i32 %iv.2.next, %shr
+  br i1 %ec.2, label %loop2, label %loop1
+}