AXISoCQuadCoreModule_TopLevel_cpu0IOGateway_readAddress.v

`timescale 1ns/1ps
`default_nettype none
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// * Place custom code between [BEGIN USER ***] and [END USER ***].
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// System configuration name is AXISoCQuadCoreModule_TopLevel_cpu0IOGateway_readAddress, clock frequency is 1Hz, Embedded
// FSM summary
// -- Packages
module AXISoCQuadCoreModule_TopLevel_cpu0IOGateway_readAddress
(
	// [BEGIN USER PORTS]
	// [END USER PORTS]
	input wire [31:0] iMapAddress,
	input wire [31:0] iOriginalAddress,
	output wire [31:0] oAddress
);
	// [BEGIN USER SIGNALS]
	// [END USER SIGNALS]
	localparam HiSignal = 1'b1;
	localparam LoSignal = 1'b0;
	wire Zero = 1'b0;
	wire One = 1'b1;
	wire true = 1'b1;
	wire false = 1'b0;
	wire signed [6: 0] axiSize = 7'b0100000;
	wire signed [1: 0] originalLowerBits = 2'b00;
	wire AXI4GatewayAddressModule_L31F13T35_Expr = 1'b1;
	wire [31: 0] Inputs_iMapAddress;
	wire [31: 0] Inputs_iOriginalAddress;
	assign Inputs_iMapAddress = iMapAddress;
	assign Inputs_iOriginalAddress = iOriginalAddress;
	assign oAddress = Inputs_iOriginalAddress;
	// [BEGIN USER ARCHITECTURE]
	// [END USER ARCHITECTURE]
endmodule